commit 0b982e5d4dc33cb02419a27c311bda0f69e49453 Author: Vyacheslav Aksenov Date: Mon Mar 30 13:45:38 2026 +0300 init commit diff --git a/Core/Inc/dma.h b/Core/Inc/dma.h new file mode 100644 index 0000000..d3aa0a3 --- /dev/null +++ b/Core/Inc/dma.h @@ -0,0 +1,52 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file dma.h + * @brief This file contains all the function prototypes for + * the dma.c file + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __DMA_H__ +#define __DMA_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* DMA memory to memory transfer handles -------------------------------------*/ + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +void MX_DMA_Init(void); + +/* USER CODE BEGIN Prototypes */ + +/* USER CODE END Prototypes */ + +#ifdef __cplusplus +} +#endif + +#endif /* __DMA_H__ */ + diff --git a/Core/Inc/gpio.h b/Core/Inc/gpio.h new file mode 100644 index 0000000..f4d298c --- /dev/null +++ b/Core/Inc/gpio.h @@ -0,0 +1,49 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file gpio.h + * @brief This file contains all the function prototypes for + * the gpio.c file + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __GPIO_H__ +#define __GPIO_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +void MX_GPIO_Init(void); + +/* USER CODE BEGIN Prototypes */ + +/* USER CODE END Prototypes */ + +#ifdef __cplusplus +} +#endif +#endif /*__ GPIO_H__ */ + diff --git a/Core/Inc/main.h b/Core/Inc/main.h new file mode 100644 index 0000000..8ce4f11 --- /dev/null +++ b/Core/Inc/main.h @@ -0,0 +1,95 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wlxx_hal.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +void Error_Handler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +/* Private defines -----------------------------------------------------------*/ +#define RTC_N_PREDIV_S 10 +#define RTC_PREDIV_S ((1< +#include "stm32wlxx.h" +#include "main.h" +#include "stm32wlxx_ll_gpio.h" +#if defined(USE_BSP_DRIVER) +/* code generated by STM32CubeMX does not support BSP. */ +/* In order to use BSP, users can add the BSP files in the IDE project space */ +/* and define USE_BSP_DRIVER in the preprocessor definitions */ +#include "stm32wlxx_nucleo_radio.h" +#include "stm32wlxx_nucleo.h" /* not used by this project*/ +#endif /* defined(USE_BSP_DRIVER) */ + +/* USER CODE BEGIN include */ + +/* USER CODE END include */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +#ifdef __cplusplus +} +#endif + +#endif /* __PLATFORM_H__ */ diff --git a/Core/Inc/rtc.h b/Core/Inc/rtc.h new file mode 100644 index 0000000..486491a --- /dev/null +++ b/Core/Inc/rtc.h @@ -0,0 +1,52 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file rtc.h + * @brief This file contains all the function prototypes for + * the rtc.c file + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __RTC_H__ +#define __RTC_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +extern RTC_HandleTypeDef hrtc; + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +void MX_RTC_Init(void); + +/* USER CODE BEGIN Prototypes */ + +/* USER CODE END Prototypes */ + +#ifdef __cplusplus +} +#endif + +#endif /* __RTC_H__ */ + diff --git a/Core/Inc/stm32_lpm_if.h b/Core/Inc/stm32_lpm_if.h new file mode 100644 index 0000000..8c63420 --- /dev/null +++ b/Core/Inc/stm32_lpm_if.h @@ -0,0 +1,99 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32_lpm_if.h + * @author MCD Application Team + * @brief Header for Low Power Manager interface configuration + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32_LPM_IF_H__ +#define __STM32_LPM_IF_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32_lpm.h" + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +/** + * @brief Enters Low Power Off Mode + */ +void PWR_EnterOffMode(void); + +/** + * @brief Exits Low Power Off Mode + */ +void PWR_ExitOffMode(void); + +/** + * @brief Enters Low Power Stop Mode + * @note ARM exists the function when waking up + */ +void PWR_EnterStopMode(void); + +/** + * @brief Exits Low Power Stop Mode + * @note Enable the pll at 32MHz + */ +void PWR_ExitStopMode(void); + +/** + * @brief Enters Low Power Sleep Mode + * @note ARM exits the function when waking up + */ +void PWR_EnterSleepMode(void); + +/** + * @brief Exits Low Power Sleep Mode + * @note ARM exits the function when waking up + */ +void PWR_ExitSleepMode(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32_LPM_IF_H__ */ diff --git a/Core/Inc/stm32wlxx_hal_conf.h b/Core/Inc/stm32wlxx_hal_conf.h new file mode 100644 index 0000000..9d4b764 --- /dev/null +++ b/Core/Inc/stm32wlxx_hal_conf.h @@ -0,0 +1,337 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32wlxx_hal_conf.h + * @author MCD Application Team + * @brief HAL configuration file. + ****************************************************************************** + * @attention + * + * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32WLxx_HAL_CONF_H +#define STM32WLxx_HAL_CONF_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* ########################## Module Selection ############################## */ +/** + * @brief This is the list of modules to be used in the HAL driver + */ +#define HAL_MODULE_ENABLED +/*#define HAL_ADC_MODULE_ENABLED */ +/*#define HAL_COMP_MODULE_ENABLED */ +/*#define HAL_CRC_MODULE_ENABLED */ +/*#define HAL_CRYP_MODULE_ENABLED */ +/*#define HAL_DAC_MODULE_ENABLED */ +/*#define HAL_GTZC_MODULE_ENABLED */ +/*#define HAL_HSEM_MODULE_ENABLED */ +/*#define HAL_I2C_MODULE_ENABLED */ +/*#define HAL_I2S_MODULE_ENABLED */ +/*#define HAL_IPCC_MODULE_ENABLED */ +/*#define HAL_IRDA_MODULE_ENABLED */ +/*#define HAL_IWDG_MODULE_ENABLED */ +/*#define HAL_LPTIM_MODULE_ENABLED */ +/*#define HAL_PKA_MODULE_ENABLED */ +/*#define HAL_RNG_MODULE_ENABLED */ +#define HAL_RTC_MODULE_ENABLED +/*#define HAL_SMARTCARD_MODULE_ENABLED */ +/*#define HAL_SMBUS_MODULE_ENABLED */ +/*#define HAL_SPI_MODULE_ENABLED */ +#define HAL_SUBGHZ_MODULE_ENABLED +/*#define HAL_TIM_MODULE_ENABLED */ +#define HAL_UART_MODULE_ENABLED +/*#define HAL_USART_MODULE_ENABLED */ +/*#define HAL_WWDG_MODULE_ENABLED */ +#define HAL_EXTI_MODULE_ENABLED +#define HAL_CORTEX_MODULE_ENABLED +#define HAL_DMA_MODULE_ENABLED +#define HAL_FLASH_MODULE_ENABLED +#define HAL_GPIO_MODULE_ENABLED +#define HAL_PWR_MODULE_ENABLED +#define HAL_RCC_MODULE_ENABLED + +/* ########################## Register Callbacks selection ############################## */ +/** + * @brief This is the list of modules where register callback can be used + */ +#define USE_HAL_ADC_REGISTER_CALLBACKS 0u +#define USE_HAL_COMP_REGISTER_CALLBACKS 0u +#define USE_HAL_CRYP_REGISTER_CALLBACKS 0u +#define USE_HAL_DAC_REGISTER_CALLBACKS 0u +#define USE_HAL_I2C_REGISTER_CALLBACKS 0u +#define USE_HAL_I2S_REGISTER_CALLBACKS 0u +#define USE_HAL_IRDA_REGISTER_CALLBACKS 0u +#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0u +#define USE_HAL_PKA_REGISTER_CALLBACKS 0u +#define USE_HAL_RNG_REGISTER_CALLBACKS 0u +#define USE_HAL_RTC_REGISTER_CALLBACKS 0u +#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0u +#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0u +#define USE_HAL_SPI_REGISTER_CALLBACKS 0u +#define USE_HAL_SUBGHZ_REGISTER_CALLBACKS 0u +#define USE_HAL_TIM_REGISTER_CALLBACKS 0u +#define USE_HAL_UART_REGISTER_CALLBACKS 0u +#define USE_HAL_USART_REGISTER_CALLBACKS 0u +#define USE_HAL_WWDG_REGISTER_CALLBACKS 0u + +/* ########################## Oscillator Values adaptation ####################*/ +/** + * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSE is used as system clock source, directly or through the PLL). + */ + +#if !defined (HSE_VALUE) +#define HSE_VALUE 32000000UL /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSE_STARTUP_TIMEOUT) +#define HSE_STARTUP_TIMEOUT 100UL /*!< Time out for HSE start up, in ms */ +#endif /* HSE_STARTUP_TIMEOUT */ + +/** + * @brief Internal Multiple Speed oscillator (MSI) default value. + * This value is the default MSI range value after Reset. + */ +#if !defined (MSI_VALUE) +#define MSI_VALUE 4000000UL /*!< Value of the Internal oscillator in Hz*/ +#endif /* MSI_VALUE */ + +/** + * @brief Internal High Speed oscillator (HSI) value. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSI is used as system clock source, directly or through the PLL). + */ +#if !defined (HSI_VALUE) +#define HSI_VALUE 16000000UL /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @brief Internal Low Speed oscillator (LSI) value. + */ +#if !defined (LSI_VALUE) +#define LSI_VALUE 32000UL /*!< LSI Typical Value in Hz*/ +#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz + The real value may vary depending on the variations + in voltage and temperature. */ + +/** + * @brief External Low Speed oscillator (LSE) value. + * This value is used by the UART, RTC HAL module to compute the system frequency + */ +#if !defined (LSE_VALUE) +#define LSE_VALUE 32768UL /*!< Value of the External oscillator in Hz*/ +#endif /* LSE_VALUE */ + +/** + * @brief Internal Multiple Speed oscillator (HSI48) default value. + * This value is the default HSI48 range value after Reset. + */ +#if !defined (HSI48_VALUE) +#define HSI48_VALUE 48000000UL /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI48_VALUE */ + +#if !defined (LSE_STARTUP_TIMEOUT) +#define LSE_STARTUP_TIMEOUT 5000UL /*!< Time out for LSE start up, in ms */ +#endif /* LSE_STARTUP_TIMEOUT */ + +/* Tip: To avoid modifying this file each time you need to use different HSE, + === you can define the HSE value in your toolchain compiler preprocessor. */ + +/* ########################### System Configuration ######################### */ +/** + * @brief This is the HAL system configuration section + */ +#define VDD_VALUE 3300U /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY ((1uL <<__NVIC_PRIO_BITS) - 1uL) /*!< tick interrupt priority (lowest by default) */ +#define USE_RTOS 0U +#define PREFETCH_ENABLE 0U +#define INSTRUCTION_CACHE_ENABLE 1U +#define DATA_CACHE_ENABLE 1U + +/* ########################## Assert Selection ############################## */ +/** + * @brief Uncomment the line below to expanse the "assert_param" macro in the + * HAL drivers code + */ +/* #define USE_FULL_ASSERT 1 */ + +/* ################## SPI peripheral configuration ########################## */ + +/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver + * Activated: CRC code is present inside driver + * Deactivated: CRC code cleaned from driver + */ + +#define USE_SPI_CRC 1U + +/* ################## CRYP peripheral configuration ########################## */ + +#define USE_HAL_CRYP_SUSPEND_RESUME 1U + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ +#ifdef HAL_DMA_MODULE_ENABLED + #include "stm32wlxx_hal_dma.h" +#endif /* HAL_DMA_MODULE_ENABLED */ + +#ifdef HAL_ADC_MODULE_ENABLED + #include "stm32wlxx_hal_adc.h" +#endif /* HAL_ADC_MODULE_ENABLED */ + +#ifdef HAL_COMP_MODULE_ENABLED + #include "stm32wlxx_hal_comp.h" +#endif /* HAL_COMP_MODULE_ENABLED */ + +#ifdef HAL_CORTEX_MODULE_ENABLED + #include "stm32wlxx_hal_cortex.h" +#endif /* HAL_CORTEX_MODULE_ENABLED */ + +#ifdef HAL_CRC_MODULE_ENABLED + #include "stm32wlxx_hal_crc.h" +#endif /* HAL_CRC_MODULE_ENABLED */ + +#ifdef HAL_CRYP_MODULE_ENABLED + #include "stm32wlxx_hal_cryp.h" +#endif /* HAL_CRYP_MODULE_ENABLED */ + +#ifdef HAL_DAC_MODULE_ENABLED + #include "stm32wlxx_hal_dac.h" +#endif /* HAL_DAC_MODULE_ENABLED */ + +#ifdef HAL_EXTI_MODULE_ENABLED + #include "stm32wlxx_hal_exti.h" +#endif /* HAL_EXTI_MODULE_ENABLED */ + +#ifdef HAL_FLASH_MODULE_ENABLED + #include "stm32wlxx_hal_flash.h" +#endif /* HAL_FLASH_MODULE_ENABLED */ + +#ifdef HAL_GPIO_MODULE_ENABLED + #include "stm32wlxx_hal_gpio.h" +#endif /* HAL_GPIO_MODULE_ENABLED */ + +#ifdef HAL_GTZC_MODULE_ENABLED + #include "stm32wlxx_hal_gtzc.h" +#endif /* HAL_GTZC_MODULE_ENABLED */ + +#ifdef HAL_HSEM_MODULE_ENABLED + #include "stm32wlxx_hal_hsem.h" +#endif /* HAL_HSEM_MODULE_ENABLED */ + +#ifdef HAL_I2C_MODULE_ENABLED + #include "stm32wlxx_hal_i2c.h" +#endif /* HAL_I2C_MODULE_ENABLED */ + +#ifdef HAL_I2S_MODULE_ENABLED + #include "stm32wlxx_hal_i2s.h" +#endif /* HAL_I2S_MODULE_ENABLED */ + +#ifdef HAL_IPCC_MODULE_ENABLED + #include "stm32wlxx_hal_ipcc.h" +#endif /* HAL_IPCC_MODULE_ENABLED */ + +#ifdef HAL_IRDA_MODULE_ENABLED + #include "stm32wlxx_hal_irda.h" +#endif /* HAL_IRDA_MODULE_ENABLED */ + +#ifdef HAL_IWDG_MODULE_ENABLED + #include "stm32wlxx_hal_iwdg.h" +#endif /* HAL_IWDG_MODULE_ENABLED */ + +#ifdef HAL_LPTIM_MODULE_ENABLED + #include "stm32wlxx_hal_lptim.h" +#endif /* HAL_LPTIM_MODULE_ENABLED */ + +#ifdef HAL_PKA_MODULE_ENABLED + #include "stm32wlxx_hal_pka.h" +#endif /* HAL_PKA_MODULE_ENABLED */ + +#ifdef HAL_PWR_MODULE_ENABLED + #include "stm32wlxx_hal_pwr.h" +#endif /* HAL_PWR_MODULE_ENABLED */ + +#ifdef HAL_RCC_MODULE_ENABLED + #include "stm32wlxx_hal_rcc.h" +#endif /* HAL_RCC_MODULE_ENABLED */ + +#ifdef HAL_RNG_MODULE_ENABLED + #include "stm32wlxx_hal_rng.h" +#endif /* HAL_RNG_MODULE_ENABLED */ + +#ifdef HAL_RTC_MODULE_ENABLED + #include "stm32wlxx_hal_rtc.h" +#endif /* HAL_RTC_MODULE_ENABLED */ + +#ifdef HAL_SMARTCARD_MODULE_ENABLED + #include "stm32wlxx_hal_smartcard.h" +#endif /* HAL_SMARTCARD_MODULE_ENABLED */ + +#ifdef HAL_SMBUS_MODULE_ENABLED + #include "stm32wlxx_hal_smbus.h" +#endif /* HAL_SMBUS_MODULE_ENABLED */ + +#ifdef HAL_SPI_MODULE_ENABLED + #include "stm32wlxx_hal_spi.h" +#endif /* HAL_SPI_MODULE_ENABLED */ + +#ifdef HAL_SUBGHZ_MODULE_ENABLED + #include "stm32wlxx_hal_subghz.h" +#endif /* HAL_SUBGHZ_MODULE_ENABLED */ + +#ifdef HAL_TIM_MODULE_ENABLED + #include "stm32wlxx_hal_tim.h" +#endif /* HAL_TIM_MODULE_ENABLED */ + +#ifdef HAL_UART_MODULE_ENABLED + #include "stm32wlxx_hal_uart.h" +#endif /* HAL_UART_MODULE_ENABLED */ + +#ifdef HAL_USART_MODULE_ENABLED + #include "stm32wlxx_hal_usart.h" +#endif /* HAL_USART_MODULE_ENABLED */ + +#ifdef HAL_WWDG_MODULE_ENABLED + #include "stm32wlxx_hal_wwdg.h" +#endif /* HAL_WWDG_MODULE_ENABLED */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32WLxx_HAL_CONF_H */ diff --git a/Core/Inc/stm32wlxx_it.h b/Core/Inc/stm32wlxx_it.h new file mode 100644 index 0000000..4137bcc --- /dev/null +++ b/Core/Inc/stm32wlxx_it.h @@ -0,0 +1,74 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32wlxx_it.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32WLxx_IT_H +#define __STM32WLxx_IT_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +void TAMP_STAMP_LSECSS_SSRU_IRQHandler(void); +void EXTI0_IRQHandler(void); +void EXTI1_IRQHandler(void); +void DMA1_Channel5_IRQHandler(void); +void EXTI9_5_IRQHandler(void); +void USART2_IRQHandler(void); +void RTC_Alarm_IRQHandler(void); +void SUBGHZ_Radio_IRQHandler(void); +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32WLxx_IT_H */ diff --git a/Core/Inc/stm32wlxx_nucleo_conf.h b/Core/Inc/stm32wlxx_nucleo_conf.h new file mode 100644 index 0000000..61a27b8 --- /dev/null +++ b/Core/Inc/stm32wlxx_nucleo_conf.h @@ -0,0 +1,105 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32wlxx_nucleo_conf.h + * @author MCD Application Team + * @brief STM32WLxx_Nucleo board configuration file. + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32WLXX_NUCLEO_CONF_H +#define STM32WLXX_NUCLEO_CONF_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wlxx_hal.h" + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/** @addtogroup BSP + * @{ + */ + +/** @addtogroup STM32WLXX_NUCLEO + * @{ + */ + +/** @defgroup STM32WLXX_NUCLEO_CONFIG CONFIG + * @{ + */ + +/** @defgroup STM32WLXX_NUCLEO_CONFIG_Exported_Constants Exported Constants + * @{ + */ +/* COM usage define */ +#define USE_BSP_COM_FEATURE 0U + +/* COM log define */ +#define USE_COM_LOG 0U + +/* IRQ priorities */ +#define BSP_BUTTON_USER_IT_PRIORITY 14U + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32WLXX_NUCLEO_CONF_H */ diff --git a/Core/Inc/subghz.h b/Core/Inc/subghz.h new file mode 100644 index 0000000..a220c5b --- /dev/null +++ b/Core/Inc/subghz.h @@ -0,0 +1,52 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file subghz.h + * @brief This file contains all the function prototypes for + * the subghz.c file + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __SUBGHZ_H__ +#define __SUBGHZ_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +extern SUBGHZ_HandleTypeDef hsubghz; + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +void MX_SUBGHZ_Init(void); + +/* USER CODE BEGIN Prototypes */ + +/* USER CODE END Prototypes */ + +#ifdef __cplusplus +} +#endif + +#endif /* __SUBGHZ_H__ */ + diff --git a/Core/Inc/sys_app.h b/Core/Inc/sys_app.h new file mode 100644 index 0000000..3b34a8e --- /dev/null +++ b/Core/Inc/sys_app.h @@ -0,0 +1,89 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file sys_app.h + * @author MCD Application Team + * @brief Function prototypes for sys_app.c file + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __SYS_APP_H__ +#define __SYS_APP_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stdint.h" +#include "sys_conf.h" +#include "stm32_adv_trace.h" +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported defines ----------------------------------------------------------*/ +/* USER CODE BEGIN ED */ + +/* USER CODE END ED */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + +/* Exported macros -----------------------------------------------------------*/ +#define APP_PPRINTF(...) do{ } while( UTIL_ADV_TRACE_OK \ + != UTIL_ADV_TRACE_COND_FSend(VLEVEL_ALWAYS, T_REG_OFF, TS_OFF, __VA_ARGS__) ) /* Polling Mode */ +#define APP_TPRINTF(...) do{ {UTIL_ADV_TRACE_COND_FSend(VLEVEL_ALWAYS, T_REG_OFF, TS_ON, __VA_ARGS__);} }while(0); /* with timestamp */ +#define APP_PRINTF(...) do{ {UTIL_ADV_TRACE_COND_FSend(VLEVEL_ALWAYS, T_REG_OFF, TS_OFF, __VA_ARGS__);} }while(0); + +#if defined (APP_LOG_ENABLED) && (APP_LOG_ENABLED == 1) +#define APP_LOG(TS,VL,...) do{ {UTIL_ADV_TRACE_COND_FSend(VL, T_REG_OFF, TS, __VA_ARGS__);} }while(0); +#elif defined (APP_LOG_ENABLED) && (APP_LOG_ENABLED == 0) /* APP_LOG disabled */ +#define APP_LOG(TS,VL,...) +#else +#error "APP_LOG_ENABLED not defined or out of range <0,1>" +#endif /* APP_LOG_ENABLED */ + +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +/** + * @brief initialize the system (dbg pins, trace, mbmux, sys timer, LPM, ...) + */ +void SystemApp_Init(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +#ifdef __cplusplus +} +#endif + +#endif /* __SYS_APP_H__ */ diff --git a/Core/Inc/sys_conf.h b/Core/Inc/sys_conf.h new file mode 100644 index 0000000..8a99691 --- /dev/null +++ b/Core/Inc/sys_conf.h @@ -0,0 +1,103 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file sys_conf.h + * @author MCD Application Team + * @brief Applicative configuration, e.g. : debug, trace, low power, sensors + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __SYS_CONF_H__ +#define __SYS_CONF_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ + +/** + * @brief Verbose level for all trace logs + */ +#define VERBOSE_LEVEL VLEVEL_M + +/** + * @brief Enable trace logs + */ +#define APP_LOG_ENABLED 1 + +/** + * @brief Activate monitoring (probes) of some internal RF signals for debug purpose + */ +#define DEBUG_SUBGHZSPI_MONITORING_ENABLED 0 + +#define DEBUG_RF_NRESET_ENABLED 0 + +#define DEBUG_RF_HSE32RDY_ENABLED 0 + +#define DEBUG_RF_SMPSRDY_ENABLED 0 + +#define DEBUG_RF_LDORDY_ENABLED 0 + +#define DEBUG_RF_DTB1_ENABLED 0 + +#define DEBUG_RF_BUSY_ENABLED 0 + +/** + * @brief Enable/Disable MCU Debugger pins (dbg serial wires) + * @note by HW serial wires are ON by default, need to put them OFF to save power + */ +#define DEBUGGER_ENABLED 1 + +/** + * @brief Disable Low Power mode + * @note 0: LowPowerMode enabled. MCU enters stop2 mode, 1: LowPowerMode disabled. MCU enters sleep mode only + */ +#define LOW_POWER_DISABLE 1 + +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +#ifdef __cplusplus +} +#endif + +#endif /* __SYS_CONF_H__ */ diff --git a/Core/Inc/sys_debug.h b/Core/Inc/sys_debug.h new file mode 100644 index 0000000..cdee22e --- /dev/null +++ b/Core/Inc/sys_debug.h @@ -0,0 +1,151 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file sys_debug.h + * @author MCD Application Team + * @brief Configuration of the debug.c instances + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __SYS_DEBUG_H__ +#define __SYS_DEBUG_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "sys_conf.h" +#include "platform.h" + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* Pin defines */ + +/** Definition for Probe Line 1 **/ +/** + * @brief Pin of Probe Line 1 + */ +#define PROBE_LINE1_PIN GPIO_PIN_12 + +/** + * @brief Port of Probe Line 1 + */ +#define PROBE_LINE1_PORT GPIOB + +/** + * @brief Enable GPIOs clock of Probe Line 1 + */ +#define PROBE_LINE1_CLK_ENABLE() __HAL_RCC_GPIOB_CLK_ENABLE() + +/** + * @brief Disable GPIOs clock of Probe Line 1 + */ +#define PROBE_LINE1_CLK_DISABLE() __HAL_RCC_GPIOB_CLK_DISABLE() + +/** Definition for Probe Line 2 **/ +/** + * @brief Pin of Probe Line 2 + */ +#define PROBE_LINE2_PIN GPIO_PIN_13 + +/** + * @brief Port of Probe Line 2 + */ +#define PROBE_LINE2_PORT GPIOB + +/** + * @brief Enable GPIOs clock of Probe Line 2 + */ +#define PROBE_LINE2_CLK_ENABLE() __HAL_RCC_GPIOB_CLK_ENABLE() + +/** + * @brief Disable GPIOs clock of Probe Line 2 + */ +#define PROBE_LINE2_CLK_DISABLE() __HAL_RCC_GPIOB_CLK_DISABLE() + +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + +/* Exported macro ------------------------------------------------------------*/ +#if !defined (DISABLE_PROBE_GPIO) + +/** + * @brief Set pin to x value + */ +#define PROBE_GPIO_WRITE( gpio, n, x ) HAL_GPIO_WritePin( gpio, n, (GPIO_PinState)(x) ) + +/** + * @brief Set pin to high level + */ +#define PROBE_GPIO_SET_LINE( gpio, n ) LL_GPIO_SetOutputPin( gpio, n ) + +/** + * @brief Set pin to low level + */ +#define PROBE_GPIO_RST_LINE( gpio, n ) LL_GPIO_ResetOutputPin( gpio, n ) + +#else /* DISABLE_PROBE_GPIO */ + +/** + * @brief not usable + */ +#define PROBE_GPIO_WRITE( gpio, n, x ) + +/** + * @brief not usable + */ +#define PROBE_GPIO_SET_LINE( gpio, n ) + +/** + * @brief not usable + */ +#define PROBE_GPIO_RST_LINE( gpio, n ) + +#endif /* DISABLE_PROBE_GPIO */ + +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +/** + * @brief Initializes the SW probes pins and the monitor RF pins via Alternate Function + */ +void DBG_Init(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +#ifdef __cplusplus +} +#endif + +#endif /* __SYS_DEBUG_H__ */ diff --git a/Core/Inc/timer_if.h b/Core/Inc/timer_if.h new file mode 100644 index 0000000..f3d4122 --- /dev/null +++ b/Core/Inc/timer_if.h @@ -0,0 +1,171 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file timer_if.h + * @author MCD Application Team + * @brief configuration of the timer_if.c instances + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __TIMER_IF_H__ +#define __TIMER_IF_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32_timer.h" +#include "stm32_systime.h" + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +/** + * @brief Init RTC hardware + * @return Status based on @ref UTIL_TIMER_Status_t + */ +UTIL_TIMER_Status_t TIMER_IF_Init(void); + +/** + * @brief Set the alarm + * @note The alarm is set at timeout from timer Reference (TimerContext) + * @param timeout Duration of the Timer in ticks + * @return Status based on @ref UTIL_TIMER_Status_t + */ +UTIL_TIMER_Status_t TIMER_IF_StartTimer(uint32_t timeout); + +/** + * @brief Stop the Alarm + * @return Status based on @ref UTIL_TIMER_Status_t + */ +UTIL_TIMER_Status_t TIMER_IF_StopTimer(void); + +/** + * @brief set timer Reference (TimerContext) + * @return Timer Reference Value in Ticks + */ +uint32_t TIMER_IF_SetTimerContext(void); + +/** + * @brief Get the RTC timer Reference + * @return Timer Value in Ticks + */ +uint32_t TIMER_IF_GetTimerContext(void); + +/** + * @brief Get the timer elapsed time since timer Reference (TimerContext) was set + * @return RTC Elapsed time in ticks + */ +uint32_t TIMER_IF_GetTimerElapsedTime(void); + +/** + * @brief Get the timer value + * @return RTC Timer value in ticks + */ +uint32_t TIMER_IF_GetTimerValue(void); + +/** + * @brief Return the minimum timeout in ticks the RTC is able to handle + * @return minimum value for a timeout in ticks + */ +uint32_t TIMER_IF_GetMinimumTimeout(void); + +/** + * @brief a delay of delay ms by polling RTC + * @param delay in ms + */ +void TIMER_IF_DelayMs(uint32_t delay); + +/** + * @brief converts time in ms to time in ticks + * @param[in] timeMilliSec time in milliseconds + * @return time in timer ticks + */ +uint32_t TIMER_IF_Convert_ms2Tick(uint32_t timeMilliSec); + +/** + * @brief converts time in ticks to time in ms + * @param[in] tick time in timer ticks + * @return time in timer milliseconds + */ +uint32_t TIMER_IF_Convert_Tick2ms(uint32_t tick); + +/** + * @brief Get rtc time + * @param[out] subSeconds in ticks + * @return time seconds + */ +uint32_t TIMER_IF_GetTime(uint16_t *subSeconds); + +/** + * @brief write seconds in backUp register + * @note Used to store seconds difference between RTC time and Unix time + * @param[in] Seconds time in seconds + */ +void TIMER_IF_BkUp_Write_Seconds(uint32_t Seconds); + +/** + * @brief reads seconds from backUp register + * @note Used to store seconds difference between RTC time and Unix time + * @return Time in seconds + */ +uint32_t TIMER_IF_BkUp_Read_Seconds(void); + +/** + * @brief writes SubSeconds in backUp register + * @note Used to store SubSeconds difference between RTC time and Unix time + * @param[in] SubSeconds time in SubSeconds + */ +void TIMER_IF_BkUp_Write_SubSeconds(uint32_t SubSeconds); + +/** + * @brief reads SubSeconds from backUp register + * @note Used to store SubSeconds difference between RTC time and Unix time + * @return Time in SubSeconds + */ +uint32_t TIMER_IF_BkUp_Read_SubSeconds(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +#ifdef __cplusplus +} +#endif + +#endif /* __TIMER_IF_H__ */ diff --git a/Core/Inc/usart.h b/Core/Inc/usart.h new file mode 100644 index 0000000..df11a99 --- /dev/null +++ b/Core/Inc/usart.h @@ -0,0 +1,52 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file usart.h + * @brief This file contains all the function prototypes for + * the usart.c file + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __USART_H__ +#define __USART_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +extern UART_HandleTypeDef huart2; + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +void MX_USART2_UART_Init(void); + +/* USER CODE BEGIN Prototypes */ + +/* USER CODE END Prototypes */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USART_H__ */ + diff --git a/Core/Inc/usart_if.h b/Core/Inc/usart_if.h new file mode 100644 index 0000000..b598e16 --- /dev/null +++ b/Core/Inc/usart_if.h @@ -0,0 +1,117 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file usart_if.h + * @author MCD Application Team + * @brief Header for USART interface configuration + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +#include "stm32_adv_trace.h" +#include "usart.h" +#include "dma.h" + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __USART_IF_H__ +#define __USART_IF_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +/** + * @brief Init the UART and associated DMA. + * @param cb TxCpltCallback + * @return @ref UTIL_ADV_TRACE_Status_t + */ +UTIL_ADV_TRACE_Status_t vcom_Init(void (*cb)(void *)); + +/** + * @brief init receiver of vcom + * @param RxCb callback when Rx char is received + * @return @ref UTIL_ADV_TRACE_Status_t + */ +UTIL_ADV_TRACE_Status_t vcom_ReceiveInit(void (*RxCb)(uint8_t *rxChar, uint16_t size, uint8_t error)); + +/** + * @brief DeInit the UART and associated DMA. + * @return @ref UTIL_ADV_TRACE_Status_t + */ +UTIL_ADV_TRACE_Status_t vcom_DeInit(void); + +/** + * @brief send buffer \p p_data of size \p size to vcom in polling mode + * @param p_data data to be sent + * @param size of buffer p_data to be sent + */ +void vcom_Trace(uint8_t *p_data, uint16_t size); + +/** + * @brief send buffer \p p_data of size \p size to vcom using DMA + * @param p_data data to be sent + * @param size of buffer p_data to be sent + * @return @ref UTIL_ADV_TRACE_Status_t + */ +UTIL_ADV_TRACE_Status_t vcom_Trace_DMA(uint8_t *p_data, uint16_t size); + +/** + * @brief last byte has been sent on the uart line + */ +void vcom_IRQHandler(void); + +/** + * @brief last byte has been sent from memory to uart data register + */ +void vcom_DMA_TX_IRQHandler(void); + +/** + * @brief Resume the UART and associated DMA (used by LPM) + */ +void vcom_Resume(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USART_IF_H__ */ diff --git a/Core/Inc/utilities_conf.h b/Core/Inc/utilities_conf.h new file mode 100644 index 0000000..573a572 --- /dev/null +++ b/Core/Inc/utilities_conf.h @@ -0,0 +1,177 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file utilities_conf.h + * @author MCD Application Team + * @brief Header for configuration file to utilities + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __UTILITIES_CONF_H__ +#define __UTILITIES_CONF_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "cmsis_compiler.h" + +/* definitions to be provided to "sequencer" utility */ +#include "stm32_mem.h" +/* definition and callback for tiny_vsnprintf */ +#include "stm32_tiny_vsnprintf.h" + +/* enum number of task and priority*/ +#include "utilities_def.h" +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +#define VLEVEL_OFF 0 /*!< used to set UTIL_ADV_TRACE_SetVerboseLevel() (not as message param) */ +#define VLEVEL_ALWAYS 0 /*!< used as message params, if this level is given + trace will be printed even when UTIL_ADV_TRACE_SetVerboseLevel(OFF) */ +#define VLEVEL_L 1 /*!< just essential traces */ +#define VLEVEL_M 2 /*!< functional traces */ +#define VLEVEL_H 3 /*!< all traces */ + +#define TS_OFF 0 /*!< Log without TimeStamp */ +#define TS_ON 1 /*!< Log with TimeStamp */ + +#define T_REG_OFF 0 /*!< Log without bitmask */ + +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + +/* Exported macros -----------------------------------------------------------*/ +/****************************************************************************** + * common + ******************************************************************************/ +/** + * @brief Memory placement macro + */ +#if defined(__CC_ARM) +#define UTIL_PLACE_IN_SECTION( __x__ ) __attribute__((section (__x__), zero_init)) +#elif defined(__ICCARM__) +#define UTIL_PLACE_IN_SECTION( __x__ ) __attribute__((section (__x__))) +#else /* __GNUC__ */ +#define UTIL_PLACE_IN_SECTION( __x__ ) __attribute__((section (__x__))) +#endif /* __CC_ARM | __ICCARM__ | __GNUC__ */ + +/** + * @brief Memory alignment macro + */ +#undef ALIGN +#ifdef WIN32 +#define ALIGN(n) +#else +#define ALIGN(n) __attribute__((aligned(n))) +#endif /* WIN32 */ + +/** + * @brief macro used to initialize the critical section + */ +#define UTILS_INIT_CRITICAL_SECTION() + +/** + * @brief macro used to enter the critical section + */ +#define UTILS_ENTER_CRITICAL_SECTION() uint32_t primask_bit= __get_PRIMASK();\ + __disable_irq() + +/** + * @brief macro used to exit the critical section + */ +#define UTILS_EXIT_CRITICAL_SECTION() __set_PRIMASK(primask_bit) +/****************************************************************************** + * sequencer + ******************************************************************************/ + +/** + * @brief default number of tasks configured in sequencer + */ +#define UTIL_SEQ_CONF_TASK_NBR CFG_SEQ_Task_NBR + +/** + * @brief default value of priority task + */ + +#define UTIL_SEQ_CONF_PRIO_NBR CFG_SEQ_Prio_NBR + +/** + * @brief macro used to initialize the critical section + */ +#define UTIL_SEQ_INIT_CRITICAL_SECTION( ) UTILS_INIT_CRITICAL_SECTION() + +/** + * @brief macro used to enter the critical section + */ +#define UTIL_SEQ_ENTER_CRITICAL_SECTION( ) UTILS_ENTER_CRITICAL_SECTION() + +/** + * @brief macro used to exit the critical section + */ +#define UTIL_SEQ_EXIT_CRITICAL_SECTION( ) UTILS_EXIT_CRITICAL_SECTION() + +/** + * @brief Memset utilities interface to application + */ +#define UTIL_SEQ_MEMSET8( dest, value, size ) UTIL_MEM_set_8( dest, value, size ) + +/****************************************************************************** + * trace\advanced + * the define option + * UTIL_ADV_TRACE_CONDITIONNAL shall be defined if you want use conditional function + * UTIL_ADV_TRACE_UNCHUNK_MODE shall be defined if you want use the unchunk mode + * + ******************************************************************************/ + +#define UTIL_ADV_TRACE_CONDITIONNAL /*!< not used */ +#define UTIL_ADV_TRACE_UNCHUNK_MODE /*!< not used */ +#define UTIL_ADV_TRACE_DEBUG(...) /*!< not used */ +#define UTIL_ADV_TRACE_INIT_CRITICAL_SECTION( ) UTILS_INIT_CRITICAL_SECTION() /*!< init the critical section in trace feature */ +#define UTIL_ADV_TRACE_ENTER_CRITICAL_SECTION( ) UTILS_ENTER_CRITICAL_SECTION() /*!< enter the critical section in trace feature */ +#define UTIL_ADV_TRACE_EXIT_CRITICAL_SECTION( ) UTILS_EXIT_CRITICAL_SECTION() /*!< exit the critical section in trace feature */ +#define UTIL_ADV_TRACE_TMP_BUF_SIZE (256U) /*!< default trace buffer size */ +#define UTIL_ADV_TRACE_TMP_MAX_TIMESTMAP_SIZE (15U) /*!< default trace timestamp size */ +#define UTIL_ADV_TRACE_FIFO_SIZE (512U) /*!< default trace fifo size */ +#define UTIL_ADV_TRACE_MEMSET8( dest, value, size) UTIL_MEM_set_8((dest),(value),(size)) /*!< memset utilities interface to trace feature */ +#define UTIL_ADV_TRACE_VSNPRINTF(...) tiny_vsnprintf_like(__VA_ARGS__) /*!< vsnprintf utilities interface to trace feature */ + +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +#ifdef __cplusplus +} +#endif + +#endif /*__UTILITIES_CONF_H__ */ diff --git a/Core/Inc/utilities_def.h b/Core/Inc/utilities_def.h new file mode 100644 index 0000000..e77118f --- /dev/null +++ b/Core/Inc/utilities_def.h @@ -0,0 +1,113 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file utilities_def.h + * @author MCD Application Team + * @brief Definitions for modules requiring utilities + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __UTILITIES_DEF_H__ +#define __UTILITIES_DEF_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/****************************************************************************** + * LOW POWER MANAGER + ******************************************************************************/ +/** + * Supported requester to the MCU Low Power Manager - can be increased up to 32 + * It lists a bit mapping of all user of the Low Power Manager + */ +typedef enum +{ + /* USER CODE BEGIN CFG_LPM_Id_t_0 */ + + /* USER CODE END CFG_LPM_Id_t_0 */ + CFG_LPM_APPLI_Id, + CFG_LPM_UART_TX_Id, + /* USER CODE BEGIN CFG_LPM_Id_t */ + + /* USER CODE END CFG_LPM_Id_t */ +} CFG_LPM_Id_t; + +/*---------------------------------------------------------------------------*/ +/* sequencer definitions */ +/*---------------------------------------------------------------------------*/ + +/** + * This is the list of priority required by the application + * Each Id shall be in the range 0..31 + */ +typedef enum +{ + CFG_SEQ_Prio_0, + /* USER CODE BEGIN CFG_SEQ_Prio_Id_t */ + + /* USER CODE END CFG_SEQ_Prio_Id_t */ + CFG_SEQ_Prio_NBR, +} CFG_SEQ_Prio_Id_t; + +/** + * This is the list of task id required by the application + * Each Id shall be in the range 0..31 + */ +typedef enum +{ + CFG_SEQ_Task_SubGHz_Phy_App_Process, + /* USER CODE BEGIN CFG_SEQ_Task_Id_t */ + + /* USER CODE END CFG_SEQ_Task_Id_t */ + CFG_SEQ_Task_NBR +} CFG_SEQ_Task_Id_t; + +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +#ifdef __cplusplus +} +#endif + +#endif /* __UTILITIES_DEF_H__ */ diff --git a/Core/Src/dma.c b/Core/Src/dma.c new file mode 100644 index 0000000..dc7afb9 --- /dev/null +++ b/Core/Src/dma.c @@ -0,0 +1,56 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file dma.c + * @brief This file provides code for the configuration + * of all the requested memory to memory DMA transfers. + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "dma.h" + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/*----------------------------------------------------------------------------*/ +/* Configure DMA */ +/*----------------------------------------------------------------------------*/ + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/** + * Enable DMA controller clock + */ +void MX_DMA_Init(void) +{ + + /* DMA controller clock enable */ + __HAL_RCC_DMAMUX1_CLK_ENABLE(); + __HAL_RCC_DMA1_CLK_ENABLE(); + + /* DMA interrupt init */ + /* DMA1_Channel5_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(DMA1_Channel5_IRQn, 2, 0); + HAL_NVIC_EnableIRQ(DMA1_Channel5_IRQn); + +} + +/* USER CODE BEGIN 2 */ + +/* USER CODE END 2 */ + diff --git a/Core/Src/gpio.c b/Core/Src/gpio.c new file mode 100644 index 0000000..6c9de36 --- /dev/null +++ b/Core/Src/gpio.c @@ -0,0 +1,96 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file gpio.c + * @brief This file provides code for the configuration + * of all used GPIO pins. + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "gpio.h" + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/*----------------------------------------------------------------------------*/ +/* Configure GPIO */ +/*----------------------------------------------------------------------------*/ +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/** Configure pins as + * Analog + * Input + * Output + * EVENT_OUT + * EXTI +*/ +void MX_GPIO_Init(void) +{ + + GPIO_InitTypeDef GPIO_InitStruct = {0}; + + /* GPIO Ports Clock Enable */ + __HAL_RCC_GPIOB_CLK_ENABLE(); + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOA_CLK_ENABLE(); + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(GPIOB, LED1_Pin|LED2_Pin|PROB2_Pin|PROB1_Pin + |LED3_Pin, GPIO_PIN_RESET); + + /*Configure GPIO pins : LED1_Pin LED2_Pin LED3_Pin */ + GPIO_InitStruct.Pin = LED1_Pin|LED2_Pin|LED3_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /*Configure GPIO pins : BUT1_Pin BUT2_Pin */ + GPIO_InitStruct.Pin = BUT1_Pin|BUT2_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING; + GPIO_InitStruct.Pull = GPIO_PULLUP; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /*Configure GPIO pins : PROB2_Pin PROB1_Pin */ + GPIO_InitStruct.Pin = PROB2_Pin|PROB1_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /*Configure GPIO pin : BUT3_Pin */ + GPIO_InitStruct.Pin = BUT3_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING; + GPIO_InitStruct.Pull = GPIO_PULLUP; + HAL_GPIO_Init(BUT3_GPIO_Port, &GPIO_InitStruct); + + /* EXTI interrupt init*/ + HAL_NVIC_SetPriority(EXTI0_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(EXTI0_IRQn); + + HAL_NVIC_SetPriority(EXTI1_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(EXTI1_IRQn); + + HAL_NVIC_SetPriority(EXTI9_5_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(EXTI9_5_IRQn); + +} + +/* USER CODE BEGIN 2 */ + +/* USER CODE END 2 */ diff --git a/Core/Src/main.c b/Core/Src/main.c new file mode 100644 index 0000000..0d900a5 --- /dev/null +++ b/Core/Src/main.c @@ -0,0 +1,190 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.c + * @brief : Main program body + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "app_subghz_phy.h" +#include "gpio.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN PTD */ + +/* USER CODE END PTD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ + +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +void SystemClock_Config(void); +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/** + * @brief The application entry point. + * @retval int + */ +int main(void) +{ + + /* USER CODE BEGIN 1 */ + + /* USER CODE END 1 */ + + /* MCU Configuration--------------------------------------------------------*/ + + /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ + HAL_Init(); + + /* USER CODE BEGIN Init */ + + /* USER CODE END Init */ + + /* Configure the system clock */ + SystemClock_Config(); + + /* USER CODE BEGIN SysInit */ + + /* USER CODE END SysInit */ + + /* Initialize all configured peripherals */ + MX_GPIO_Init(); + MX_SubGHz_Phy_Init(); + /* USER CODE BEGIN 2 */ + + /* USER CODE END 2 */ + + /* Infinite loop */ + /* USER CODE BEGIN WHILE */ + while (1) + { + /* USER CODE END WHILE */ + MX_SubGHz_Phy_Process(); + + /* USER CODE BEGIN 3 */ + } + /* USER CODE END 3 */ +} + +/** + * @brief System Clock Configuration + * @retval None + */ +void SystemClock_Config(void) +{ + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + + /** Configure LSE Drive Capability + */ + HAL_PWR_EnableBkUpAccess(); + __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW); + + /** Configure the main internal regulator output voltage + */ + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + + /** Initializes the CPU, AHB and APB buses clocks + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE|RCC_OSCILLATORTYPE_MSI; + RCC_OscInitStruct.LSEState = RCC_LSE_ON; + RCC_OscInitStruct.MSIState = RCC_MSI_ON; + RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT; + RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_11; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + Error_Handler(); + } + + /** Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK3|RCC_CLOCKTYPE_HCLK + |RCC_CLOCKTYPE_SYSCLK|RCC_CLOCKTYPE_PCLK1 + |RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + RCC_ClkInitStruct.AHBCLK3Divider = RCC_SYSCLK_DIV1; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) + { + Error_Handler(); + } +} + +/* USER CODE BEGIN 4 */ + +/* USER CODE END 4 */ + +/** + * @brief This function is executed in case of error occurrence. + * @retval None + */ +void Error_Handler(void) +{ + /* USER CODE BEGIN Error_Handler_Debug */ + /* User can add his own implementation to report the HAL error return state */ + __disable_irq(); + while (1) + { + } + /* USER CODE END Error_Handler_Debug */ +} +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + while (1) + { + } + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ diff --git a/Core/Src/rtc.c b/Core/Src/rtc.c new file mode 100644 index 0000000..cff5296 --- /dev/null +++ b/Core/Src/rtc.c @@ -0,0 +1,144 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file rtc.c + * @brief This file provides code for the configuration + * of the RTC instances. + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Includes ------------------------------------------------------------------*/ +#include "rtc.h" + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +RTC_HandleTypeDef hrtc; + +/* RTC init function */ +void MX_RTC_Init(void) +{ + + /* USER CODE BEGIN RTC_Init 0 */ + + /* USER CODE END RTC_Init 0 */ + + RTC_AlarmTypeDef sAlarm = {0}; + + /* USER CODE BEGIN RTC_Init 1 */ + + /* USER CODE END RTC_Init 1 */ + + /** Initialize RTC Only + */ + hrtc.Instance = RTC; + hrtc.Init.AsynchPrediv = RTC_PREDIV_A; + hrtc.Init.OutPut = RTC_OUTPUT_DISABLE; + hrtc.Init.OutPutRemap = RTC_OUTPUT_REMAP_NONE; + hrtc.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH; + hrtc.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN; + hrtc.Init.OutPutPullUp = RTC_OUTPUT_PULLUP_NONE; + hrtc.Init.BinMode = RTC_BINARY_ONLY; + if (HAL_RTC_Init(&hrtc) != HAL_OK) + { + Error_Handler(); + } + + /* USER CODE BEGIN Check_RTC_BKUP */ + + /* USER CODE END Check_RTC_BKUP */ + + /** Initialize RTC and set the Time and Date + */ + if (HAL_RTCEx_SetSSRU_IT(&hrtc) != HAL_OK) + { + Error_Handler(); + } + + /** Enable the Alarm A + */ + sAlarm.BinaryAutoClr = RTC_ALARMSUBSECONDBIN_AUTOCLR_NO; + sAlarm.AlarmTime.SubSeconds = 0x0; + sAlarm.AlarmMask = RTC_ALARMMASK_NONE; + sAlarm.AlarmSubSecondMask = RTC_ALARMSUBSECONDBINMASK_NONE; + sAlarm.Alarm = RTC_ALARM_A; + if (HAL_RTC_SetAlarm_IT(&hrtc, &sAlarm, 0) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN RTC_Init 2 */ + + /* USER CODE END RTC_Init 2 */ + +} + +void HAL_RTC_MspInit(RTC_HandleTypeDef* rtcHandle) +{ + + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; + if(rtcHandle->Instance==RTC) + { + /* USER CODE BEGIN RTC_MspInit 0 */ + + /* USER CODE END RTC_MspInit 0 */ + + /** Initializes the peripherals clocks + */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC; + PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE; + + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) + { + Error_Handler(); + } + + /* RTC clock enable */ + __HAL_RCC_RTC_ENABLE(); + __HAL_RCC_RTCAPB_CLK_ENABLE(); + + /* RTC interrupt Init */ + HAL_NVIC_SetPriority(TAMP_STAMP_LSECSS_SSRU_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(TAMP_STAMP_LSECSS_SSRU_IRQn); + HAL_NVIC_SetPriority(RTC_Alarm_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(RTC_Alarm_IRQn); + /* USER CODE BEGIN RTC_MspInit 1 */ + + /* USER CODE END RTC_MspInit 1 */ + } +} + +void HAL_RTC_MspDeInit(RTC_HandleTypeDef* rtcHandle) +{ + + if(rtcHandle->Instance==RTC) + { + /* USER CODE BEGIN RTC_MspDeInit 0 */ + + /* USER CODE END RTC_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_RTC_DISABLE(); + __HAL_RCC_RTCAPB_CLK_DISABLE(); + + /* RTC interrupt Deinit */ + HAL_NVIC_DisableIRQ(TAMP_STAMP_LSECSS_SSRU_IRQn); + HAL_NVIC_DisableIRQ(RTC_Alarm_IRQn); + /* USER CODE BEGIN RTC_MspDeInit 1 */ + + /* USER CODE END RTC_MspDeInit 1 */ + } +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ diff --git a/Core/Src/stm32_lpm_if.c b/Core/Src/stm32_lpm_if.c new file mode 100644 index 0000000..a57680c --- /dev/null +++ b/Core/Src/stm32_lpm_if.c @@ -0,0 +1,165 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32_lpm_if.c + * @author MCD Application Team + * @brief Low layer function to enter/exit low power modes (stop, sleep) + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "platform.h" +#include "stm32_lpm.h" +#include "stm32_lpm_if.h" +#include "usart_if.h" + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* External variables ---------------------------------------------------------*/ +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + +/* Private typedef -----------------------------------------------------------*/ +/** + * @brief Power driver callbacks handler + */ +const struct UTIL_LPM_Driver_s UTIL_PowerDriver = +{ + PWR_EnterSleepMode, + PWR_ExitSleepMode, + + PWR_EnterStopMode, + PWR_ExitStopMode, + + PWR_EnterOffMode, + PWR_ExitOffMode, +}; + +/* USER CODE BEGIN PTD */ + +/* USER CODE END PTD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ + +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* Exported functions --------------------------------------------------------*/ + +void PWR_EnterOffMode(void) +{ + /* USER CODE BEGIN EnterOffMode_1 */ + + /* USER CODE END EnterOffMode_1 */ +} + +void PWR_ExitOffMode(void) +{ + /* USER CODE BEGIN ExitOffMode_1 */ + + /* USER CODE END ExitOffMode_1 */ +} + +void PWR_EnterStopMode(void) +{ + /* USER CODE BEGIN EnterStopMode_1 */ + + /* USER CODE END EnterStopMode_1 */ + HAL_SuspendTick(); + /* Clear Status Flag before entering STOP/STANDBY Mode */ + LL_PWR_ClearFlag_C1STOP_C1STB(); + + /* USER CODE BEGIN EnterStopMode_2 */ + + /* USER CODE END EnterStopMode_2 */ + HAL_PWREx_EnterSTOP2Mode(PWR_STOPENTRY_WFI); + /* USER CODE BEGIN EnterStopMode_3 */ + + /* USER CODE END EnterStopMode_3 */ +} + +void PWR_ExitStopMode(void) +{ + /* USER CODE BEGIN ExitStopMode_1 */ + + /* USER CODE END ExitStopMode_1 */ + /* Resume sysTick : work around for debugger problem in dual core */ + HAL_ResumeTick(); + /*Not retained periph: + ADC interface + DAC interface USARTx, TIMx, i2Cx, SPIx + SRAM ctrls, DMAx, DMAMux, AES, RNG, HSEM */ + + /* Resume not retained USARTx and DMA */ + vcom_Resume(); + /* USER CODE BEGIN ExitStopMode_2 */ + + /* USER CODE END ExitStopMode_2 */ +} + +void PWR_EnterSleepMode(void) +{ + /* USER CODE BEGIN EnterSleepMode_1 */ + + /* USER CODE END EnterSleepMode_1 */ + /* Suspend sysTick */ + HAL_SuspendTick(); + /* USER CODE BEGIN EnterSleepMode_2 */ + + /* USER CODE END EnterSleepMode_2 */ + HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI); + /* USER CODE BEGIN EnterSleepMode_3 */ + + /* USER CODE END EnterSleepMode_3 */ +} + +void PWR_ExitSleepMode(void) +{ + /* USER CODE BEGIN ExitSleepMode_1 */ + + /* USER CODE END ExitSleepMode_1 */ + /* Resume sysTick */ + HAL_ResumeTick(); + + /* USER CODE BEGIN ExitSleepMode_2 */ + + /* USER CODE END ExitSleepMode_2 */ +} + +/* USER CODE BEGIN EF */ + +/* USER CODE END EF */ + +/* Private Functions Definition -----------------------------------------------*/ +/* USER CODE BEGIN PrFD */ + +/* USER CODE END PrFD */ diff --git a/Core/Src/stm32wlxx_hal_msp.c b/Core/Src/stm32wlxx_hal_msp.c new file mode 100644 index 0000000..7e95565 --- /dev/null +++ b/Core/Src/stm32wlxx_hal_msp.c @@ -0,0 +1,79 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32wlxx_hal_msp.c + * @brief This file provides code for the MSP Initialization + * and de-Initialization codes. + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ + +/* USER CODE END TD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN Define */ + +/* USER CODE END Define */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN Macro */ + +/* USER CODE END Macro */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* External functions --------------------------------------------------------*/ +/* USER CODE BEGIN ExternalFunctions */ + +/* USER CODE END ExternalFunctions */ + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ +/** + * Initializes the Global MSP. + */ +void HAL_MspInit(void) +{ + + /* USER CODE BEGIN MspInit 0 */ + + /* USER CODE END MspInit 0 */ + + /* System interrupt init*/ + + /* USER CODE BEGIN MspInit 1 */ + + /* USER CODE END MspInit 1 */ +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ diff --git a/Core/Src/stm32wlxx_it.c b/Core/Src/stm32wlxx_it.c new file mode 100644 index 0000000..5563bb8 --- /dev/null +++ b/Core/Src/stm32wlxx_it.c @@ -0,0 +1,317 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32wlxx_it.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "stm32wlxx_it.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ + +/* USER CODE END TD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ + +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +extern RTC_HandleTypeDef hrtc; +extern SUBGHZ_HandleTypeDef hsubghz; +extern DMA_HandleTypeDef hdma_usart2_tx; +extern UART_HandleTypeDef huart2; +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + +/******************************************************************************/ +/* Cortex Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ + + /* USER CODE END NonMaskableInt_IRQn 0 */ + /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ + while (1) + { + } + /* USER CODE END NonMaskableInt_IRQn 1 */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn 0 */ + + /* USER CODE END HardFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn 0 */ + /* USER CODE END W1_HardFault_IRQn 0 */ + } +} + +/** + * @brief This function handles Memory management fault. + */ +void MemManage_Handler(void) +{ + /* USER CODE BEGIN MemoryManagement_IRQn 0 */ + + /* USER CODE END MemoryManagement_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */ + /* USER CODE END W1_MemoryManagement_IRQn 0 */ + } +} + +/** + * @brief This function handles Prefetch fault, memory access fault. + */ +void BusFault_Handler(void) +{ + /* USER CODE BEGIN BusFault_IRQn 0 */ + + /* USER CODE END BusFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_BusFault_IRQn 0 */ + /* USER CODE END W1_BusFault_IRQn 0 */ + } +} + +/** + * @brief This function handles Undefined instruction or illegal state. + */ +void UsageFault_Handler(void) +{ + /* USER CODE BEGIN UsageFault_IRQn 0 */ + + /* USER CODE END UsageFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_UsageFault_IRQn 0 */ + /* USER CODE END W1_UsageFault_IRQn 0 */ + } +} + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn 0 */ + + /* USER CODE END SVCall_IRQn 0 */ + /* USER CODE BEGIN SVCall_IRQn 1 */ + + /* USER CODE END SVCall_IRQn 1 */ +} + +/** + * @brief This function handles Debug monitor. + */ +void DebugMon_Handler(void) +{ + /* USER CODE BEGIN DebugMonitor_IRQn 0 */ + + /* USER CODE END DebugMonitor_IRQn 0 */ + /* USER CODE BEGIN DebugMonitor_IRQn 1 */ + + /* USER CODE END DebugMonitor_IRQn 1 */ +} + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn 0 */ + + /* USER CODE END PendSV_IRQn 0 */ + /* USER CODE BEGIN PendSV_IRQn 1 */ + + /* USER CODE END PendSV_IRQn 1 */ +} + +/** + * @brief This function handles System tick timer. + */ +void SysTick_Handler(void) +{ + /* USER CODE BEGIN SysTick_IRQn 0 */ + + /* USER CODE END SysTick_IRQn 0 */ + /* USER CODE BEGIN SysTick_IRQn 1 */ + + /* USER CODE END SysTick_IRQn 1 */ +} + +/******************************************************************************/ +/* STM32WLxx Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_stm32wlxx.s). */ +/******************************************************************************/ + +/** + * @brief This function handles RTC Tamper, RTC TimeStamp, LSECSS and RTC SSRU Interrupts. + */ +void TAMP_STAMP_LSECSS_SSRU_IRQHandler(void) +{ + /* USER CODE BEGIN TAMP_STAMP_LSECSS_SSRU_IRQn 0 */ + + /* USER CODE END TAMP_STAMP_LSECSS_SSRU_IRQn 0 */ + HAL_RTCEx_SSRUIRQHandler(&hrtc); + /* USER CODE BEGIN TAMP_STAMP_LSECSS_SSRU_IRQn 1 */ + + /* USER CODE END TAMP_STAMP_LSECSS_SSRU_IRQn 1 */ +} + +/** + * @brief This function handles EXTI Line 0 Interrupt. + */ +void EXTI0_IRQHandler(void) +{ + /* USER CODE BEGIN EXTI0_IRQn 0 */ + + /* USER CODE END EXTI0_IRQn 0 */ + HAL_GPIO_EXTI_IRQHandler(BUT1_Pin); + /* USER CODE BEGIN EXTI0_IRQn 1 */ + + /* USER CODE END EXTI0_IRQn 1 */ +} + +/** + * @brief This function handles EXTI Line 1 Interrupt. + */ +void EXTI1_IRQHandler(void) +{ + /* USER CODE BEGIN EXTI1_IRQn 0 */ + + /* USER CODE END EXTI1_IRQn 0 */ + HAL_GPIO_EXTI_IRQHandler(BUT2_Pin); + /* USER CODE BEGIN EXTI1_IRQn 1 */ + + /* USER CODE END EXTI1_IRQn 1 */ +} + +/** + * @brief This function handles DMA1 Channel 5 Interrupt. + */ +void DMA1_Channel5_IRQHandler(void) +{ + /* USER CODE BEGIN DMA1_Channel5_IRQn 0 */ + + /* USER CODE END DMA1_Channel5_IRQn 0 */ + HAL_DMA_IRQHandler(&hdma_usart2_tx); + /* USER CODE BEGIN DMA1_Channel5_IRQn 1 */ + + /* USER CODE END DMA1_Channel5_IRQn 1 */ +} + +/** + * @brief This function handles EXTI Lines [9:5] Interrupt. + */ +void EXTI9_5_IRQHandler(void) +{ + /* USER CODE BEGIN EXTI9_5_IRQn 0 */ + + /* USER CODE END EXTI9_5_IRQn 0 */ + HAL_GPIO_EXTI_IRQHandler(BUT3_Pin); + /* USER CODE BEGIN EXTI9_5_IRQn 1 */ + + /* USER CODE END EXTI9_5_IRQn 1 */ +} + +/** + * @brief This function handles USART2 Interrupt. + */ +void USART2_IRQHandler(void) +{ + /* USER CODE BEGIN USART2_IRQn 0 */ + + /* USER CODE END USART2_IRQn 0 */ + HAL_UART_IRQHandler(&huart2); + /* USER CODE BEGIN USART2_IRQn 1 */ + + /* USER CODE END USART2_IRQn 1 */ +} + +/** + * @brief This function handles RTC Alarms (A and B) Interrupt. + */ +void RTC_Alarm_IRQHandler(void) +{ + /* USER CODE BEGIN RTC_Alarm_IRQn 0 */ + + /* USER CODE END RTC_Alarm_IRQn 0 */ + HAL_RTC_AlarmIRQHandler(&hrtc); + /* USER CODE BEGIN RTC_Alarm_IRQn 1 */ + + /* USER CODE END RTC_Alarm_IRQn 1 */ +} + +/** + * @brief This function handles SUBGHZ Radio Interrupt. + */ +void SUBGHZ_Radio_IRQHandler(void) +{ + /* USER CODE BEGIN SUBGHZ_Radio_IRQn 0 */ + + /* USER CODE END SUBGHZ_Radio_IRQn 0 */ + HAL_SUBGHZ_IRQHandler(&hsubghz); + /* USER CODE BEGIN SUBGHZ_Radio_IRQn 1 */ + + /* USER CODE END SUBGHZ_Radio_IRQn 1 */ +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ diff --git a/Core/Src/subghz.c b/Core/Src/subghz.c new file mode 100644 index 0000000..e67aa1a --- /dev/null +++ b/Core/Src/subghz.c @@ -0,0 +1,86 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file subghz.c + * @brief This file provides code for the configuration + * of the SUBGHZ instances. + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Includes ------------------------------------------------------------------*/ +#include "subghz.h" + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +SUBGHZ_HandleTypeDef hsubghz; + +/* SUBGHZ init function */ +void MX_SUBGHZ_Init(void) +{ + + /* USER CODE BEGIN SUBGHZ_Init 0 */ + + /* USER CODE END SUBGHZ_Init 0 */ + + /* USER CODE BEGIN SUBGHZ_Init 1 */ + + /* USER CODE END SUBGHZ_Init 1 */ + hsubghz.Init.BaudratePrescaler = SUBGHZSPI_BAUDRATEPRESCALER_4; + if (HAL_SUBGHZ_Init(&hsubghz) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN SUBGHZ_Init 2 */ + + /* USER CODE END SUBGHZ_Init 2 */ + +} + +void HAL_SUBGHZ_MspInit(SUBGHZ_HandleTypeDef* subghzHandle) +{ + + /* USER CODE BEGIN SUBGHZ_MspInit 0 */ + + /* USER CODE END SUBGHZ_MspInit 0 */ + /* SUBGHZ clock enable */ + __HAL_RCC_SUBGHZSPI_CLK_ENABLE(); + + /* SUBGHZ interrupt Init */ + HAL_NVIC_SetPriority(SUBGHZ_Radio_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(SUBGHZ_Radio_IRQn); + /* USER CODE BEGIN SUBGHZ_MspInit 1 */ + + /* USER CODE END SUBGHZ_MspInit 1 */ +} + +void HAL_SUBGHZ_MspDeInit(SUBGHZ_HandleTypeDef* subghzHandle) +{ + + /* USER CODE BEGIN SUBGHZ_MspDeInit 0 */ + + /* USER CODE END SUBGHZ_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_SUBGHZSPI_CLK_DISABLE(); + + /* SUBGHZ interrupt Deinit */ + HAL_NVIC_DisableIRQ(SUBGHZ_Radio_IRQn); + /* USER CODE BEGIN SUBGHZ_MspDeInit 1 */ + + /* USER CODE END SUBGHZ_MspDeInit 1 */ +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ diff --git a/Core/Src/sys_app.c b/Core/Src/sys_app.c new file mode 100644 index 0000000..7194906 --- /dev/null +++ b/Core/Src/sys_app.c @@ -0,0 +1,262 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file sys_app.c + * @author MCD Application Team + * @brief Initializes HW and SW system entities (not related to the radio) + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include +#include "platform.h" +#include "sys_app.h" +#include "stm32_seq.h" +#include "stm32_systime.h" +#include "stm32_lpm.h" +#include "timer_if.h" +#include "utilities_def.h" +#include "sys_debug.h" + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* External variables ---------------------------------------------------------*/ +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN PTD */ + +/* USER CODE END PTD */ + +/* Private define ------------------------------------------------------------*/ +#define MAX_TS_SIZE (int) 16 + +/* USER CODE BEGIN PD */ + +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ +static uint8_t SYS_TimerInitialisedFlag = 0; + +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/** + * @brief Returns sec and msec based on the systime in use + * @param buff to update with timestamp + * @param size of updated buffer + */ +static void TimestampNow(uint8_t *buff, uint16_t *size); + +/** + * @brief it calls UTIL_ADV_TRACE_VSNPRINTF + */ +static void tiny_snprintf_like(char *buf, uint32_t maxsize, const char *strFormat, ...); + +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* Exported functions ---------------------------------------------------------*/ +void SystemApp_Init(void) +{ + /* USER CODE BEGIN SystemApp_Init_1 */ + + /* USER CODE END SystemApp_Init_1 */ + + /* Ensure that MSI is wake-up system clock */ + __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(RCC_STOP_WAKEUPCLOCK_MSI); + + /*Initialize timer and RTC*/ + UTIL_TIMER_Init(); + SYS_TimerInitialisedFlag = 1; + /* Initializes the SW probes pins and the monitor RF pins via Alternate Function */ + DBG_Init(); + + /*Initialize the terminal */ + UTIL_ADV_TRACE_Init(); + UTIL_ADV_TRACE_RegisterTimeStampFunction(TimestampNow); + + /*Set verbose LEVEL*/ + UTIL_ADV_TRACE_SetVerboseLevel(VERBOSE_LEVEL); + + /*Init low power manager*/ + UTIL_LPM_Init(); + /* Disable Stand-by mode */ + UTIL_LPM_SetOffMode((1 << CFG_LPM_APPLI_Id), UTIL_LPM_DISABLE); + +#if defined (LOW_POWER_DISABLE) && (LOW_POWER_DISABLE == 1) + /* Disable Stop Mode */ + UTIL_LPM_SetStopMode((1 << CFG_LPM_APPLI_Id), UTIL_LPM_DISABLE); +#elif !defined (LOW_POWER_DISABLE) +#error LOW_POWER_DISABLE not defined +#endif /* LOW_POWER_DISABLE */ + + /* USER CODE BEGIN SystemApp_Init_2 */ + + /* USER CODE END SystemApp_Init_2 */ +} + +/** + * @brief redefines __weak function in stm32_seq.c such to enter low power + */ +void UTIL_SEQ_Idle(void) +{ + /* USER CODE BEGIN UTIL_SEQ_Idle_1 */ + + /* USER CODE END UTIL_SEQ_Idle_1 */ + UTIL_LPM_EnterLowPower(); + /* USER CODE BEGIN UTIL_SEQ_Idle_2 */ + + /* USER CODE END UTIL_SEQ_Idle_2 */ +} + +/* USER CODE BEGIN EF */ + +/* USER CODE END EF */ + +/* Private functions ---------------------------------------------------------*/ + +static void TimestampNow(uint8_t *buff, uint16_t *size) +{ + /* USER CODE BEGIN TimestampNow_1 */ + + /* USER CODE END TimestampNow_1 */ + SysTime_t curtime = SysTimeGet(); + tiny_snprintf_like((char *)buff, MAX_TS_SIZE, "%ds%03d:", curtime.Seconds, curtime.SubSeconds); + *size = strlen((char *)buff); + /* USER CODE BEGIN TimestampNow_2 */ + + /* USER CODE END TimestampNow_2 */ +} + +/* Disable StopMode when traces need to be printed */ +void UTIL_ADV_TRACE_PreSendHook(void) +{ + /* USER CODE BEGIN UTIL_ADV_TRACE_PreSendHook_1 */ + + /* USER CODE END UTIL_ADV_TRACE_PreSendHook_1 */ + UTIL_LPM_SetStopMode((1 << CFG_LPM_UART_TX_Id), UTIL_LPM_DISABLE); + /* USER CODE BEGIN UTIL_ADV_TRACE_PreSendHook_2 */ + + /* USER CODE END UTIL_ADV_TRACE_PreSendHook_2 */ +} +/* Re-enable StopMode when traces have been printed */ +void UTIL_ADV_TRACE_PostSendHook(void) +{ + /* USER CODE BEGIN UTIL_LPM_SetStopMode_1 */ + + /* USER CODE END UTIL_LPM_SetStopMode_1 */ + UTIL_LPM_SetStopMode((1 << CFG_LPM_UART_TX_Id), UTIL_LPM_ENABLE); + /* USER CODE BEGIN UTIL_LPM_SetStopMode_2 */ + + /* USER CODE END UTIL_LPM_SetStopMode_2 */ +} + +static void tiny_snprintf_like(char *buf, uint32_t maxsize, const char *strFormat, ...) +{ + /* USER CODE BEGIN tiny_snprintf_like_1 */ + + /* USER CODE END tiny_snprintf_like_1 */ + va_list vaArgs; + va_start(vaArgs, strFormat); + UTIL_ADV_TRACE_VSNPRINTF(buf, maxsize, strFormat, vaArgs); + va_end(vaArgs); + /* USER CODE BEGIN tiny_snprintf_like_2 */ + + /* USER CODE END tiny_snprintf_like_2 */ +} + +/* USER CODE BEGIN PrFD */ + +/* USER CODE END PrFD */ + +/* HAL overload functions ---------------------------------------------------------*/ + +/** + * @note This function overwrites the __weak one from HAL + */ +HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) +{ + /*Don't enable SysTick if TIMER_IF is based on other counters (e.g. RTC) */ + /* USER CODE BEGIN HAL_InitTick_1 */ + + /* USER CODE END HAL_InitTick_1 */ + return HAL_OK; + /* USER CODE BEGIN HAL_InitTick_2 */ + + /* USER CODE END HAL_InitTick_2 */ +} + +/** + * @note This function overwrites the __weak one from HAL + */ +uint32_t HAL_GetTick(void) +{ + uint32_t ret = 0; + /* TIMER_IF can be based on other counter the SysTick e.g. RTC */ + /* USER CODE BEGIN HAL_GetTick_1 */ + + /* USER CODE END HAL_GetTick_1 */ + if (SYS_TimerInitialisedFlag == 0) + { + /* TIMER_IF_GetTimerValue should be used only once UTIL_TIMER_Init() is initialized */ + /* If HAL_Delay or a TIMEOUT countdown is necessary during initialization phase */ + /* please use temporarily another timebase source (SysTick or TIMx), which implies also */ + /* to rework the above function HAL_InitTick() and to call HAL_IncTick() on the timebase IRQ */ + /* Note: when TIMER_IF is based on RTC, stm32wlxx_hal_rtc.c calls this function before TimeServer is functional */ + /* RTC TIMEOUT will not expire, i.e. if RTC has an hw problem it will keep looping in the RTC_Init function */ + /* USER CODE BEGIN HAL_GetTick_EarlyCall */ + + /* USER CODE END HAL_GetTick_EarlyCall */ + } + else + { + ret = TIMER_IF_GetTimerValue(); + } + /* USER CODE BEGIN HAL_GetTick_2 */ + + /* USER CODE END HAL_GetTick_2 */ + return ret; +} + +/** + * @note This function overwrites the __weak one from HAL + */ +void HAL_Delay(__IO uint32_t Delay) +{ + /* TIMER_IF can be based on other counter the SysTick e.g. RTC */ + /* USER CODE BEGIN HAL_Delay_1 */ + + /* USER CODE END HAL_Delay_1 */ + TIMER_IF_DelayMs(Delay); + /* USER CODE BEGIN HAL_Delay_2 */ + + /* USER CODE END HAL_Delay_2 */ +} + +/* USER CODE BEGIN Overload_HAL_weaks */ + +/* USER CODE END Overload_HAL_weaks */ diff --git a/Core/Src/sys_debug.c b/Core/Src/sys_debug.c new file mode 100644 index 0000000..dc42069 --- /dev/null +++ b/Core/Src/sys_debug.c @@ -0,0 +1,196 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file sys_debug.c + * @author MCD Application Team + * @brief Configure probes pins RealTime debugging and JTAG/SerialWires for LowPower + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "platform.h" +#include "sys_debug.h" + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* External variables ---------------------------------------------------------*/ +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN PTD */ + +/* USER CODE END PTD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ + +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* Exported functions --------------------------------------------------------*/ + +/** + * @brief Initializes the SW probes pins and the monitor RF pins via Alternate Function + */ +void DBG_Init(void) +{ + /* USER CODE BEGIN DBG_Init_1 */ + + /* USER CODE END DBG_Init_1 */ + + /* SW probes */ +#if defined (DEBUGGER_ENABLED) && ( DEBUGGER_ENABLED == 0 ) + HAL_DBGMCU_DisableDBGSleepMode(); + HAL_DBGMCU_DisableDBGStopMode(); + HAL_DBGMCU_DisableDBGStandbyMode(); +#elif defined (DEBUGGER_ENABLED) && ( DEBUGGER_ENABLED == 1 ) + /*Debug power up request wakeup CBDGPWRUPREQ*/ + LL_EXTI_EnableIT_32_63(LL_EXTI_LINE_46); + /* Disabled HAL_DBGMCU_ */ + HAL_DBGMCU_EnableDBGSleepMode(); + HAL_DBGMCU_EnableDBGStopMode(); + HAL_DBGMCU_EnableDBGStandbyMode(); +#elif !defined (DEBUGGER_ENABLED) +#error "DEBUGGER_ENABLED not defined or out of range <0,1>" +#endif /* DEBUGGER_OFF */ + + GPIO_InitTypeDef GPIO_InitStruct = {0}; + + /* Configure the GPIO pin */ + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + + /* Enable the GPIO Clock */ + PROBE_LINE1_CLK_ENABLE(); + PROBE_LINE2_CLK_ENABLE(); + + GPIO_InitStruct.Pin = PROBE_LINE1_PIN; + HAL_GPIO_Init(PROBE_LINE1_PORT, &GPIO_InitStruct); + GPIO_InitStruct.Pin = PROBE_LINE2_PIN; + HAL_GPIO_Init(PROBE_LINE2_PORT, &GPIO_InitStruct); + + /* Reset probe Pins */ + HAL_GPIO_WritePin(PROBE_LINE1_PORT, PROBE_LINE1_PIN, GPIO_PIN_RESET); + HAL_GPIO_WritePin(PROBE_LINE2_PORT, PROBE_LINE2_PIN, GPIO_PIN_RESET); + /* USER CODE BEGIN DBG_Init_2 */ + + /* USER CODE END DBG_Init_2 */ + + /* HW alternate functions for monitoring RF */ + +#if (DEBUG_SUBGHZSPI_MONITORING_ENABLED == 1) + /*spi dbg*/ + GPIO_InitStruct.Pin = (GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7); + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF13_DEBUG_SUBGHZSPI; + __HAL_RCC_GPIOA_CLK_ENABLE(); + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); +#endif /* DEBUG_SUBGHZSPI_MONITORING_ENABLED */ + +#if (DEBUG_RF_NRESET_ENABLED == 1) + GPIO_InitStruct.Pin = GPIO_PIN_11; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF13_DEBUG_RF; + __HAL_RCC_GPIOA_CLK_ENABLE(); + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); +#endif /* DEBUG_RF_NRESET_ENABLED */ + +#if (DEBUG_RF_HSE32RDY_ENABLED == 1) + GPIO_InitStruct.Pin = GPIO_PIN_10; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF13_DEBUG_RF; + __HAL_RCC_GPIOA_CLK_ENABLE(); + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); +#endif /* DEBUG_RF_HSE32RDY_ENABLED */ + +#if (DEBUG_RF_SMPSRDY_ENABLED == 1) + GPIO_InitStruct.Pin = (GPIO_PIN_2); + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF13_DEBUG_RF; + __HAL_RCC_GPIOB_CLK_ENABLE(); + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); +#endif /* DEBUG_RF_SMPSRDY_ENABLED */ + +#if (DEBUG_RF_LDORDY_ENABLED == 1) + GPIO_InitStruct.Pin = (GPIO_PIN_4); + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF13_DEBUG_RF; + __HAL_RCC_GPIOB_CLK_ENABLE(); + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); +#endif /* DEBUG_RF_LDORDY_ENABLED */ + +#if (DEBUG_RF_DTB1_ENABLED == 1) + GPIO_InitStruct.Pin = GPIO_PIN_3; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF13_DEBUG_RF; + __HAL_RCC_GPIOB_CLK_ENABLE(); + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); +#endif /* DEBUG_RF_DTB1_ENABLED */ + +#if (DEBUG_RF_BUSY_ENABLED == 1) + /* Busy */ + GPIO_InitStruct.Pin = (GPIO_PIN_12); + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF6_RF_BUSY; + __HAL_RCC_GPIOA_CLK_ENABLE() ; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); +#endif /* DEBUG_RF_BUSY_ENABLED */ + + /* USER CODE BEGIN DBG_Init_3 */ + + /* USER CODE END DBG_Init_3 */ +} + +/* USER CODE BEGIN EF */ + +/* USER CODE END EF */ + +/* Private Functions Definition -----------------------------------------------*/ + +/* USER CODE BEGIN PrFD */ + +/* USER CODE END PrFD */ diff --git a/Core/Src/syscalls.c b/Core/Src/syscalls.c new file mode 100644 index 0000000..8884b5a --- /dev/null +++ b/Core/Src/syscalls.c @@ -0,0 +1,176 @@ +/** + ****************************************************************************** + * @file syscalls.c + * @author Auto-generated by STM32CubeIDE + * @brief STM32CubeIDE Minimal System calls file + * + * For more information about which c-functions + * need which of these lowlevel functions + * please consult the Newlib libc-manual + ****************************************************************************** + * @attention + * + * Copyright (c) 2020-2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes */ +#include +#include +#include +#include +#include +#include +#include +#include + + +/* Variables */ +extern int __io_putchar(int ch) __attribute__((weak)); +extern int __io_getchar(void) __attribute__((weak)); + + +char *__env[1] = { 0 }; +char **environ = __env; + + +/* Functions */ +void initialise_monitor_handles() +{ +} + +int _getpid(void) +{ + return 1; +} + +int _kill(int pid, int sig) +{ + (void)pid; + (void)sig; + errno = EINVAL; + return -1; +} + +void _exit (int status) +{ + _kill(status, -1); + while (1) {} /* Make sure we hang here */ +} + +__attribute__((weak)) int _read(int file, char *ptr, int len) +{ + (void)file; + int DataIdx; + + for (DataIdx = 0; DataIdx < len; DataIdx++) + { + *ptr++ = __io_getchar(); + } + + return len; +} + +__attribute__((weak)) int _write(int file, char *ptr, int len) +{ + (void)file; + int DataIdx; + + for (DataIdx = 0; DataIdx < len; DataIdx++) + { + __io_putchar(*ptr++); + } + return len; +} + +int _close(int file) +{ + (void)file; + return -1; +} + + +int _fstat(int file, struct stat *st) +{ + (void)file; + st->st_mode = S_IFCHR; + return 0; +} + +int _isatty(int file) +{ + (void)file; + return 1; +} + +int _lseek(int file, int ptr, int dir) +{ + (void)file; + (void)ptr; + (void)dir; + return 0; +} + +int _open(char *path, int flags, ...) +{ + (void)path; + (void)flags; + /* Pretend like we always fail */ + return -1; +} + +int _wait(int *status) +{ + (void)status; + errno = ECHILD; + return -1; +} + +int _unlink(char *name) +{ + (void)name; + errno = ENOENT; + return -1; +} + +int _times(struct tms *buf) +{ + (void)buf; + return -1; +} + +int _stat(char *file, struct stat *st) +{ + (void)file; + st->st_mode = S_IFCHR; + return 0; +} + +int _link(char *old, char *new) +{ + (void)old; + (void)new; + errno = EMLINK; + return -1; +} + +int _fork(void) +{ + errno = EAGAIN; + return -1; +} + +int _execve(char *name, char **argv, char **env) +{ + (void)name; + (void)argv; + (void)env; + errno = ENOMEM; + return -1; +} diff --git a/Core/Src/sysmem.c b/Core/Src/sysmem.c new file mode 100644 index 0000000..5d9f7e6 --- /dev/null +++ b/Core/Src/sysmem.c @@ -0,0 +1,79 @@ +/** + ****************************************************************************** + * @file sysmem.c + * @author Generated by STM32CubeIDE + * @brief STM32CubeIDE System Memory calls file + * + * For more information about which C functions + * need which of these lowlevel functions + * please consult the newlib libc manual + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes */ +#include +#include + +/** + * Pointer to the current high watermark of the heap usage + */ +static uint8_t *__sbrk_heap_end = NULL; + +/** + * @brief _sbrk() allocates memory to the newlib heap and is used by malloc + * and others from the C library + * + * @verbatim + * ############################################################################ + * # .data # .bss # newlib heap # MSP stack # + * # # # # Reserved by _Min_Stack_Size # + * ############################################################################ + * ^-- RAM start ^-- _end _estack, RAM end --^ + * @endverbatim + * + * This implementation starts allocating at the '_end' linker symbol + * The '_Min_Stack_Size' linker symbol reserves a memory for the MSP stack + * The implementation considers '_estack' linker symbol to be RAM end + * NOTE: If the MSP stack, at any point during execution, grows larger than the + * reserved size, please increase the '_Min_Stack_Size'. + * + * @param incr Memory size + * @return Pointer to allocated memory + */ +void *_sbrk(ptrdiff_t incr) +{ + extern uint8_t _end; /* Symbol defined in the linker script */ + extern uint8_t _estack; /* Symbol defined in the linker script */ + extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */ + const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size; + const uint8_t *max_heap = (uint8_t *)stack_limit; + uint8_t *prev_heap_end; + + /* Initialize heap end at first call */ + if (NULL == __sbrk_heap_end) + { + __sbrk_heap_end = &_end; + } + + /* Protect heap from growing into the reserved MSP stack */ + if (__sbrk_heap_end + incr > max_heap) + { + errno = ENOMEM; + return (void *)-1; + } + + prev_heap_end = __sbrk_heap_end; + __sbrk_heap_end += incr; + + return (void *)prev_heap_end; +} diff --git a/Core/Src/system_stm32wlxx.c b/Core/Src/system_stm32wlxx.c new file mode 100644 index 0000000..13522cd --- /dev/null +++ b/Core/Src/system_stm32wlxx.c @@ -0,0 +1,357 @@ +/** + ****************************************************************************** + * @file system_stm32wlxx.c + * @author MCD Application Team + * @brief CMSIS Cortex Device Peripheral Access Layer System Source File + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2020-2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + * This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32wlxx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * After each device reset the MSI (4 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32wlxx.s" file, to + * configure the system clock before to branch to main program. + * + * This file configures the system clock as follows: + *============================================================================= + *----------------------------------------------------------------------------- + * System Clock source | MSI + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 4000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 4000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 1 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 1 + *----------------------------------------------------------------------------- + * PLL_M | 1 + *----------------------------------------------------------------------------- + * PLL_N | 8 + *----------------------------------------------------------------------------- + * PLL_P | 7 + *----------------------------------------------------------------------------- + * PLL_Q | 2 + *----------------------------------------------------------------------------- + * PLL_R | 2 + *----------------------------------------------------------------------------- + * PLLSAI1_P | NA + *----------------------------------------------------------------------------- + * PLLSAI1_Q | NA + *----------------------------------------------------------------------------- + * PLLSAI1_R | NA + *----------------------------------------------------------------------------- + * Require 48MHz for USB OTG FS, | Disabled + * SDIO and RNG clock | + *----------------------------------------------------------------------------- + *============================================================================= + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32WLxx_system + * @{ + */ + +/** @addtogroup stm32WLxx_System_Private_Includes + * @{ + */ + +#include "stm32wlxx.h" + +#if !defined (HSE_VALUE) + #define HSE_VALUE (32000000UL) /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (MSI_VALUE) + #define MSI_VALUE (4000000UL) /*!< Value of the Internal oscillator in Hz*/ +#endif /* MSI_VALUE */ + +#if !defined (HSI_VALUE) + #define HSI_VALUE (16000000UL) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +#if !defined (LSI_VALUE) + #define LSI_VALUE (32000UL) /*!< Value of LSI in Hz*/ +#endif /* LSI_VALUE */ + +#if !defined (LSE_VALUE) + #define LSE_VALUE (32768UL) /*!< Value of LSE in Hz*/ +#endif /* LSE_VALUE */ + +/** + * @} + */ + +/** @addtogroup STM32WLxx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32WLxx_System_Private_Defines + * @{ + */ + +/* Note: Following vector table addresses must be defined in line with linker + configuration. */ +/*!< Uncomment the following line if you need to relocate CPU1 CM4 and/or CPU2 + CM0+ vector table anywhere in Sram or Flash. Else vector table will be kept + at address 0x00 which correspond to automatic remap of boot address selected */ +/* #define USER_VECT_TAB_ADDRESS */ +#if defined(USER_VECT_TAB_ADDRESS) +#ifdef CORE_CM0PLUS + /*!< Uncomment this line for user vector table remap in Sram else user remap + will be done in Flash. */ +/* #define VECT_TAB_SRAM */ +#if defined(VECT_TAB_SRAM) +#define VECT_TAB_BASE_ADDRESS SRAM2_BASE /*!< Vector Table base address field. + This value must be a multiple of 0x100. */ +#define VECT_TAB_OFFSET 0x00008000U /*!< Vector Table base offset field. + This value must be a multiple of 0x100. */ +#else +#define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field. + This value must be a multiple of 0x100. */ +#define VECT_TAB_OFFSET 0x00020000U /*!< Vector Table base offset field. + This value must be a multiple of 0x100. */ +#endif +#else /* CORE_CM4 */ + /*!< Uncomment this line for user vector table remap in Sram else user remap + will be done in Flash. */ +/* #define VECT_TAB_SRAM */ +#if defined(VECT_TAB_SRAM) +#define VECT_TAB_BASE_ADDRESS SRAM1_BASE /*!< Vector Table base address field. + This value must be a multiple of 0x200. */ +#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +#else +#define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field. + This value must be a multiple of 0x200. */ +#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +#endif +#endif +#endif + +/** + * @} + */ + +/** @addtogroup STM32WLxx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32WLxx_System_Private_Variables + * @{ + */ + /* The SystemCoreClock variable is updated in three ways: + 1) from within HAL_Init() + 2) by calling CMSIS function SystemCoreClockUpdate() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + */ + uint32_t SystemCoreClock = 4000000UL; /*CPU1: M4 on MSI clock after startup (4MHz)*/ + + const uint32_t AHBPrescTable[16UL] = {1UL, 3UL, 5UL, 1UL, 1UL, 6UL, 10UL, 32UL, 2UL, 4UL, 8UL, 16UL, 64UL, 128UL, 256UL, 512UL}; + + const uint32_t APBPrescTable[8UL] = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL}; + + const uint32_t MSIRangeTable[16UL] = {100000UL, 200000UL, 400000UL, 800000UL, 1000000UL, 2000000UL, \ + 4000000UL, 8000000UL, 16000000UL, 24000000UL, 32000000UL, 48000000UL, 0UL, 0UL, 0UL, 0UL}; /* 0UL values are incorrect cases */ +/** + * @} + */ + +/** @addtogroup STM32WLxx_System_Private_FunctionPrototypes + * @{ + */ +/** + * @} + */ + +/** @addtogroup STM32WLxx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system. + * @param None + * @retval None + */ +void SystemInit(void) +{ +#if defined(USER_VECT_TAB_ADDRESS) + /* Configure the Vector Table location add offset address ------------------*/ + SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; +#endif + + /* FPU settings ------------------------------------------------------------*/ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << (10UL*2UL))|(3UL << (11UL*2UL))); /* set CP10 and CP11 Full Access */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*) + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***) + * or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) MSI_VALUE is a constant defined in stm32wlxx_hal.h file (default value + * 4 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSI_VALUE is a constant defined in stm32wlxx_hal_conf.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (***) HSE_VALUE is a constant defined in stm32wlxx_hal_conf.h file (default value + * 32 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp, msirange, pllvco, pllr, pllsource , pllm; + + /* Get MSI Range frequency--------------------------------------------------*/ + + /* Get MSI Range frequency--------------------------------------------------*/ + if((RCC->CR & RCC_CR_MSIRGSEL) == 0U) + { /* MSISRANGE from RCC_CSR applies */ + msirange = (RCC->CSR & RCC_CSR_MSISRANGE) >> 8U; + } + else + { /* MSIRANGE from RCC_CR applies */ + msirange = (RCC->CR & RCC_CR_MSIRANGE) >> 4U; + } + /*MSI frequency range in HZ*/ + msirange = MSIRangeTable[msirange]; + + + /*SystemCoreClock=HAL_RCC_GetSysClockFreq();*/ + /* Get SYSCLK source -------------------------------------------------------*/ + switch (RCC->CFGR & RCC_CFGR_SWS) + { + case 0x00: /* MSI used as system clock source */ + SystemCoreClock = msirange; + break; + + case 0x04: /* HSI used as system clock source */ + /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + + case 0x08: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + + case 0x0C: /* PLL used as system clock source */ + /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN + SYSCLK = PLL_VCO / PLLR + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC); + pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL ; + + switch (pllsource) + { + case 0x02: /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm); + break; + + case 0x03: /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm); + break; + + default: /* MSI used as PLL clock source */ + pllvco = (msirange / pllm); + break; + } + + pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); + pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL); + + SystemCoreClock = pllvco/pllr; + break; + + default: + SystemCoreClock = msirange; + break; + } + + /* Compute HCLK clock frequency --------------------------------------------*/ +#if defined(DUAL_CORE) && defined(CORE_CM0PLUS) + /* Get HCLK2 prescaler */ + tmp = AHBPrescTable[((RCC->EXTCFGR & RCC_EXTCFGR_C2HPRE) >> RCC_EXTCFGR_C2HPRE_Pos)]; +#else + /* Get HCLK1 prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)]; +#endif + + /* Core clock frequency */ + SystemCoreClock = SystemCoreClock / tmp; +} +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/Core/Src/timer_if.c b/Core/Src/timer_if.c new file mode 100644 index 0000000..bdace1b --- /dev/null +++ b/Core/Src/timer_if.c @@ -0,0 +1,521 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file timer_if.c + * @author MCD Application Team + * @brief Configure RTC Alarm, Tick and Calendar manager + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include +#include "timer_if.h" +#include "main.h" /*for STM32CubeMX generated RTC_N_PREDIV_S and RTC_N_PREDIV_A*/ +#include "rtc.h" +#include "utilities_def.h" +#include "stm32wlxx_ll_rtc.h" + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* External variables ---------------------------------------------------------*/ +/** + * @brief RTC handle + */ +extern RTC_HandleTypeDef hrtc; + +/** + * @brief Timer driver callbacks handler + */ +const UTIL_TIMER_Driver_s UTIL_TimerDriver = +{ + TIMER_IF_Init, + NULL, + + TIMER_IF_StartTimer, + TIMER_IF_StopTimer, + + TIMER_IF_SetTimerContext, + TIMER_IF_GetTimerContext, + + TIMER_IF_GetTimerElapsedTime, + TIMER_IF_GetTimerValue, + TIMER_IF_GetMinimumTimeout, + + TIMER_IF_Convert_ms2Tick, + TIMER_IF_Convert_Tick2ms, +}; + +/** + * @brief SysTime driver callbacks handler + */ +const UTIL_SYSTIM_Driver_s UTIL_SYSTIMDriver = +{ + TIMER_IF_BkUp_Write_Seconds, + TIMER_IF_BkUp_Read_Seconds, + TIMER_IF_BkUp_Write_SubSeconds, + TIMER_IF_BkUp_Read_SubSeconds, + TIMER_IF_GetTime, +}; + +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN PTD */ + +/* USER CODE END PTD */ + +/* Private define ------------------------------------------------------------*/ +/** + * @brief Minimum timeout delay of Alarm in ticks + */ +#define MIN_ALARM_DELAY 3 + +/** + * @brief Backup seconds register + */ +#define RTC_BKP_SECONDS RTC_BKP_DR0 + +/** + * @brief Backup subseconds register + */ +#define RTC_BKP_SUBSECONDS RTC_BKP_DR1 + +/** + * @brief Backup msbticks register + */ +#define RTC_BKP_MSBTICKS RTC_BKP_DR2 + +/* #define RTIF_DEBUG */ + +/** + * @brief Map UTIL_TIMER_IRQ can be overridden in utilities_conf.h to Map on Task rather then Isr + */ +#ifndef UTIL_TIMER_IRQ_MAP_INIT +#define UTIL_TIMER_IRQ_MAP_INIT() +#endif /* UTIL_TIMER_IRQ_MAP_INIT */ + +#ifndef UTIL_TIMER_IRQ_MAP_PROCESS +#define UTIL_TIMER_IRQ_MAP_PROCESS() UTIL_TIMER_IRQ_Handler() +#endif /* UTIL_TIMER_IRQ_MAP_PROCESS */ + +/* USER CODE BEGIN PD */ + +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +#ifdef RTIF_DEBUG +#include "sys_app.h" /*for app_log*/ +/** + * @brief Post the RTC log string format to the circular queue for printing in using the polling mode + */ +#define TIMER_IF_DBG_PRINTF(...) do{ {UTIL_ADV_TRACE_COND_FSend(VLEVEL_ALWAYS, T_REG_OFF, TS_OFF, __VA_ARGS__);} }while(0); +#else +/** + * @brief not used + */ +#define TIMER_IF_DBG_PRINTF(...) +#endif /* RTIF_DEBUG */ + +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ +/** + * @brief Indicates if the RTC is already Initialized or not + */ +static bool RTC_Initialized = false; + +/** + * @brief RtcTimerContext + */ +static uint32_t RtcTimerContext = 0; + +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/** + * @brief Get rtc timer Value in rtc tick + * @return val the rtc timer value (upcounting) + */ +static inline uint32_t GetTimerTicks(void); + +/** + * @brief Writes MSBticks to backup register + * Absolute RTC time in tick is (MSBticks)<<32 + (32bits binary counter) + * @note MSBticks incremented every time the 32bits RTC timer wraps around (~44days) + * @param[in] MSBticks + */ +static void TIMER_IF_BkUp_Write_MSBticks(uint32_t MSBticks); + +/** + * @brief Reads MSBticks from backup register + * Absolute RTC time in tick is (MSBticks)<<32 + (32bits binary counter) + * @note MSBticks incremented every time the 32bits RTC timer wraps around (~44days) + * @retval MSBticks + */ +static uint32_t TIMER_IF_BkUp_Read_MSBticks(void); + +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* Exported functions ---------------------------------------------------------*/ +UTIL_TIMER_Status_t TIMER_IF_Init(void) +{ + UTIL_TIMER_Status_t ret = UTIL_TIMER_OK; + /* USER CODE BEGIN TIMER_IF_Init */ + + /* USER CODE END TIMER_IF_Init */ + if (RTC_Initialized == false) + { + hrtc.IsEnabled.RtcFeatures = UINT32_MAX; + /*Init RTC*/ + MX_RTC_Init(); + /*Stop Timer */ + TIMER_IF_StopTimer(); + /** DeActivate the Alarm A enabled by STM32CubeMX during MX_RTC_Init() */ + HAL_RTC_DeactivateAlarm(&hrtc, RTC_ALARM_A); + /*overload RTC feature enable*/ + hrtc.IsEnabled.RtcFeatures = UINT32_MAX; + + /*Enable Direct Read of the calendar registers (not through Shadow) */ + HAL_RTCEx_EnableBypassShadow(&hrtc); + /*Initialize MSB ticks*/ + TIMER_IF_BkUp_Write_MSBticks(0); + + TIMER_IF_SetTimerContext(); + + /* Register a task to associate to UTIL_TIMER_Irq() interrupt */ + UTIL_TIMER_IRQ_MAP_INIT(); + + RTC_Initialized = true; + } + + /* USER CODE BEGIN TIMER_IF_Init_Last */ + + /* USER CODE END TIMER_IF_Init_Last */ + return ret; +} + +UTIL_TIMER_Status_t TIMER_IF_StartTimer(uint32_t timeout) +{ + UTIL_TIMER_Status_t ret = UTIL_TIMER_OK; + /* USER CODE BEGIN TIMER_IF_StartTimer */ + + /* USER CODE END TIMER_IF_StartTimer */ + RTC_AlarmTypeDef sAlarm = {0}; + /*Stop timer if one is already started*/ + TIMER_IF_StopTimer(); + timeout += RtcTimerContext; + + TIMER_IF_DBG_PRINTF("Start timer: time=%d, alarm=%d\n\r", GetTimerTicks(), timeout); + /* starts timer*/ + sAlarm.BinaryAutoClr = RTC_ALARMSUBSECONDBIN_AUTOCLR_NO; + sAlarm.AlarmTime.SubSeconds = UINT32_MAX - timeout; + sAlarm.AlarmMask = RTC_ALARMMASK_NONE; + sAlarm.AlarmSubSecondMask = RTC_ALARMSUBSECONDBINMASK_NONE; + sAlarm.Alarm = RTC_ALARM_A; + if (HAL_RTC_SetAlarm_IT(&hrtc, &sAlarm, RTC_FORMAT_BCD) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN TIMER_IF_StartTimer_Last */ + + /* USER CODE END TIMER_IF_StartTimer_Last */ + return ret; +} + +UTIL_TIMER_Status_t TIMER_IF_StopTimer(void) +{ + UTIL_TIMER_Status_t ret = UTIL_TIMER_OK; + /* USER CODE BEGIN TIMER_IF_StopTimer */ + + /* USER CODE END TIMER_IF_StopTimer */ + /* Clear RTC Alarm Flag */ + __HAL_RTC_ALARM_CLEAR_FLAG(&hrtc, RTC_FLAG_ALRAF); + /* Disable the Alarm A interrupt */ + HAL_RTC_DeactivateAlarm(&hrtc, RTC_ALARM_A); + /*overload RTC feature enable*/ + hrtc.IsEnabled.RtcFeatures = UINT32_MAX; + /* USER CODE BEGIN TIMER_IF_StopTimer_Last */ + + /* USER CODE END TIMER_IF_StopTimer_Last */ + return ret; +} + +uint32_t TIMER_IF_SetTimerContext(void) +{ + /*store time context*/ + RtcTimerContext = GetTimerTicks(); + + /* USER CODE BEGIN TIMER_IF_SetTimerContext */ + + /* USER CODE END TIMER_IF_SetTimerContext */ + + TIMER_IF_DBG_PRINTF("TIMER_IF_SetTimerContext=%d\n\r", RtcTimerContext); + /*return time context*/ + return RtcTimerContext; +} + +uint32_t TIMER_IF_GetTimerContext(void) +{ + /* USER CODE BEGIN TIMER_IF_GetTimerContext */ + + /* USER CODE END TIMER_IF_GetTimerContext */ + + TIMER_IF_DBG_PRINTF("TIMER_IF_GetTimerContext=%d\n\r", RtcTimerContext); + /*return time context*/ + return RtcTimerContext; +} + +uint32_t TIMER_IF_GetTimerElapsedTime(void) +{ + uint32_t ret = 0; + /* USER CODE BEGIN TIMER_IF_GetTimerElapsedTime */ + + /* USER CODE END TIMER_IF_GetTimerElapsedTime */ + ret = ((uint32_t)(GetTimerTicks() - RtcTimerContext)); + /* USER CODE BEGIN TIMER_IF_GetTimerElapsedTime_Last */ + + /* USER CODE END TIMER_IF_GetTimerElapsedTime_Last */ + return ret; +} + +uint32_t TIMER_IF_GetTimerValue(void) +{ + uint32_t ret = 0; + /* USER CODE BEGIN TIMER_IF_GetTimerValue */ + + /* USER CODE END TIMER_IF_GetTimerValue */ + if (RTC_Initialized == true) + { + ret = GetTimerTicks(); + } + /* USER CODE BEGIN TIMER_IF_GetTimerValue_Last */ + + /* USER CODE END TIMER_IF_GetTimerValue_Last */ + return ret; +} + +uint32_t TIMER_IF_GetMinimumTimeout(void) +{ + uint32_t ret = 0; + /* USER CODE BEGIN TIMER_IF_GetMinimumTimeout */ + + /* USER CODE END TIMER_IF_GetMinimumTimeout */ + ret = (MIN_ALARM_DELAY); + /* USER CODE BEGIN TIMER_IF_GetMinimumTimeout_Last */ + + /* USER CODE END TIMER_IF_GetMinimumTimeout_Last */ + return ret; +} + +uint32_t TIMER_IF_Convert_ms2Tick(uint32_t timeMilliSec) +{ + uint32_t ret = 0; + /* USER CODE BEGIN TIMER_IF_Convert_ms2Tick */ + + /* USER CODE END TIMER_IF_Convert_ms2Tick */ + ret = ((uint32_t)((((uint64_t) timeMilliSec) << RTC_N_PREDIV_S) / 1000)); + /* USER CODE BEGIN TIMER_IF_Convert_ms2Tick_Last */ + + /* USER CODE END TIMER_IF_Convert_ms2Tick_Last */ + return ret; +} + +uint32_t TIMER_IF_Convert_Tick2ms(uint32_t tick) +{ + uint32_t ret = 0; + /* USER CODE BEGIN TIMER_IF_Convert_Tick2ms */ + + /* USER CODE END TIMER_IF_Convert_Tick2ms */ + ret = ((uint32_t)((((uint64_t)(tick)) * 1000) >> RTC_N_PREDIV_S)); + /* USER CODE BEGIN TIMER_IF_Convert_Tick2ms_Last */ + + /* USER CODE END TIMER_IF_Convert_Tick2ms_Last */ + return ret; +} + +void TIMER_IF_DelayMs(uint32_t delay) +{ + /* USER CODE BEGIN TIMER_IF_DelayMs */ + + /* USER CODE END TIMER_IF_DelayMs */ + uint32_t delayTicks = TIMER_IF_Convert_ms2Tick(delay); + uint32_t timeout = GetTimerTicks(); + + /* Wait delay ms */ + while (((GetTimerTicks() - timeout)) < delayTicks) + { + __NOP(); + } + /* USER CODE BEGIN TIMER_IF_DelayMs_Last */ + + /* USER CODE END TIMER_IF_DelayMs_Last */ +} + +void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc) +{ + /* USER CODE BEGIN HAL_RTC_AlarmAEventCallback */ + + /* USER CODE END HAL_RTC_AlarmAEventCallback */ + UTIL_TIMER_IRQ_MAP_PROCESS(); + /* USER CODE BEGIN HAL_RTC_AlarmAEventCallback_Last */ + + /* USER CODE END HAL_RTC_AlarmAEventCallback_Last */ +} + +void HAL_RTCEx_SSRUEventCallback(RTC_HandleTypeDef *hrtc) +{ + /* USER CODE BEGIN HAL_RTCEx_SSRUEventCallback */ + + /* USER CODE END HAL_RTCEx_SSRUEventCallback */ + /*called every 48 days with 1024 ticks per seconds*/ + TIMER_IF_DBG_PRINTF(">>Handler SSRUnderflow at %d\n\r", GetTimerTicks()); + /*Increment MSBticks*/ + uint32_t MSB_ticks = TIMER_IF_BkUp_Read_MSBticks(); + TIMER_IF_BkUp_Write_MSBticks(MSB_ticks + 1); + /* USER CODE BEGIN HAL_RTCEx_SSRUEventCallback_Last */ + + /* USER CODE END HAL_RTCEx_SSRUEventCallback_Last */ +} + +uint32_t TIMER_IF_GetTime(uint16_t *mSeconds) +{ + uint32_t seconds = 0; + /* USER CODE BEGIN TIMER_IF_GetTime */ + + /* USER CODE END TIMER_IF_GetTime */ + uint64_t ticks; + uint32_t timerValueLsb = GetTimerTicks(); + uint32_t timerValueMSB = TIMER_IF_BkUp_Read_MSBticks(); + + ticks = (((uint64_t) timerValueMSB) << 32) + timerValueLsb; + + seconds = (uint32_t)(ticks >> RTC_N_PREDIV_S); + + ticks = (uint32_t) ticks & RTC_PREDIV_S; + + *mSeconds = TIMER_IF_Convert_Tick2ms(ticks); + + /* USER CODE BEGIN TIMER_IF_GetTime_Last */ + + /* USER CODE END TIMER_IF_GetTime_Last */ + return seconds; +} + +void TIMER_IF_BkUp_Write_Seconds(uint32_t Seconds) +{ + /* USER CODE BEGIN TIMER_IF_BkUp_Write_Seconds */ + + /* USER CODE END TIMER_IF_BkUp_Write_Seconds */ + HAL_RTCEx_BKUPWrite(&hrtc, RTC_BKP_SECONDS, Seconds); + /* USER CODE BEGIN TIMER_IF_BkUp_Write_Seconds_Last */ + + /* USER CODE END TIMER_IF_BkUp_Write_Seconds_Last */ +} + +void TIMER_IF_BkUp_Write_SubSeconds(uint32_t SubSeconds) +{ + /* USER CODE BEGIN TIMER_IF_BkUp_Write_SubSeconds */ + + /* USER CODE END TIMER_IF_BkUp_Write_SubSeconds */ + HAL_RTCEx_BKUPWrite(&hrtc, RTC_BKP_SUBSECONDS, SubSeconds); + /* USER CODE BEGIN TIMER_IF_BkUp_Write_SubSeconds_Last */ + + /* USER CODE END TIMER_IF_BkUp_Write_SubSeconds_Last */ +} + +uint32_t TIMER_IF_BkUp_Read_Seconds(void) +{ + uint32_t ret = 0; + /* USER CODE BEGIN TIMER_IF_BkUp_Read_Seconds */ + + /* USER CODE END TIMER_IF_BkUp_Read_Seconds */ + ret = HAL_RTCEx_BKUPRead(&hrtc, RTC_BKP_SECONDS); + /* USER CODE BEGIN TIMER_IF_BkUp_Read_Seconds_Last */ + + /* USER CODE END TIMER_IF_BkUp_Read_Seconds_Last */ + return ret; +} + +uint32_t TIMER_IF_BkUp_Read_SubSeconds(void) +{ + uint32_t ret = 0; + /* USER CODE BEGIN TIMER_IF_BkUp_Read_SubSeconds */ + + /* USER CODE END TIMER_IF_BkUp_Read_SubSeconds */ + ret = HAL_RTCEx_BKUPRead(&hrtc, RTC_BKP_SUBSECONDS); + /* USER CODE BEGIN TIMER_IF_BkUp_Read_SubSeconds_Last */ + + /* USER CODE END TIMER_IF_BkUp_Read_SubSeconds_Last */ + return ret; +} + +/* USER CODE BEGIN EF */ + +/* USER CODE END EF */ + +/* Private functions ---------------------------------------------------------*/ +static void TIMER_IF_BkUp_Write_MSBticks(uint32_t MSBticks) +{ + /* USER CODE BEGIN TIMER_IF_BkUp_Write_MSBticks */ + + /* USER CODE END TIMER_IF_BkUp_Write_MSBticks */ + HAL_RTCEx_BKUPWrite(&hrtc, RTC_BKP_MSBTICKS, MSBticks); + /* USER CODE BEGIN TIMER_IF_BkUp_Write_MSBticks_Last */ + + /* USER CODE END TIMER_IF_BkUp_Write_MSBticks_Last */ +} + +static uint32_t TIMER_IF_BkUp_Read_MSBticks(void) +{ + /* USER CODE BEGIN TIMER_IF_BkUp_Read_MSBticks */ + + /* USER CODE END TIMER_IF_BkUp_Read_MSBticks */ + uint32_t MSBticks; + MSBticks = HAL_RTCEx_BKUPRead(&hrtc, RTC_BKP_MSBTICKS); + return MSBticks; + /* USER CODE BEGIN TIMER_IF_BkUp_Read_MSBticks_Last */ + + /* USER CODE END TIMER_IF_BkUp_Read_MSBticks_Last */ +} + +static inline uint32_t GetTimerTicks(void) +{ + /* USER CODE BEGIN GetTimerTicks */ + + /* USER CODE END GetTimerTicks */ + uint32_t ssr = LL_RTC_TIME_GetSubSecond(RTC); + /* read twice to make sure value it valid*/ + while (ssr != LL_RTC_TIME_GetSubSecond(RTC)) + { + ssr = LL_RTC_TIME_GetSubSecond(RTC); + } + return UINT32_MAX - ssr; + /* USER CODE BEGIN GetTimerTicks_Last */ + + /* USER CODE END GetTimerTicks_Last */ +} + +/* USER CODE BEGIN PrFD */ + +/* USER CODE END PrFD */ diff --git a/Core/Src/usart.c b/Core/Src/usart.c new file mode 100644 index 0000000..8210f4a --- /dev/null +++ b/Core/Src/usart.c @@ -0,0 +1,172 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file usart.c + * @brief This file provides code for the configuration + * of the USART instances. + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Includes ------------------------------------------------------------------*/ +#include "usart.h" + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +UART_HandleTypeDef huart2; +DMA_HandleTypeDef hdma_usart2_tx; + +/* USART2 init function */ + +void MX_USART2_UART_Init(void) +{ + + /* USER CODE BEGIN USART2_Init 0 */ + + /* USER CODE END USART2_Init 0 */ + + /* USER CODE BEGIN USART2_Init 1 */ + + /* USER CODE END USART2_Init 1 */ + huart2.Instance = USART2; + huart2.Init.BaudRate = 115200; + huart2.Init.WordLength = UART_WORDLENGTH_8B; + huart2.Init.StopBits = UART_STOPBITS_1; + huart2.Init.Parity = UART_PARITY_NONE; + huart2.Init.Mode = UART_MODE_TX_RX; + huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE; + huart2.Init.OverSampling = UART_OVERSAMPLING_16; + huart2.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; + huart2.Init.ClockPrescaler = UART_PRESCALER_DIV1; + huart2.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; + if (HAL_UART_Init(&huart2) != HAL_OK) + { + Error_Handler(); + } + if (HAL_UARTEx_SetTxFifoThreshold(&huart2, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK) + { + Error_Handler(); + } + if (HAL_UARTEx_SetRxFifoThreshold(&huart2, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK) + { + Error_Handler(); + } + if (HAL_UARTEx_EnableFifoMode(&huart2) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN USART2_Init 2 */ + + /* USER CODE END USART2_Init 2 */ + +} + +void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle) +{ + + GPIO_InitTypeDef GPIO_InitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; + if(uartHandle->Instance==USART2) + { + /* USER CODE BEGIN USART2_MspInit 0 */ + + /* USER CODE END USART2_MspInit 0 */ + + /** Initializes the peripherals clocks + */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USART2; + PeriphClkInitStruct.Usart2ClockSelection = RCC_USART2CLKSOURCE_SYSCLK; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) + { + Error_Handler(); + } + + /* USART2 clock enable */ + __HAL_RCC_USART2_CLK_ENABLE(); + + __HAL_RCC_GPIOA_CLK_ENABLE(); + /**USART2 GPIO Configuration + PA3 ------> USART2_RX + PA2 ------> USART2_TX + */ + GPIO_InitStruct.Pin = USARTx_RX_Pin|USARTx_TX_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF7_USART2; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /* USART2 DMA Init */ + /* USART2_TX Init */ + hdma_usart2_tx.Instance = DMA1_Channel5; + hdma_usart2_tx.Init.Request = DMA_REQUEST_USART2_TX; + hdma_usart2_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; + hdma_usart2_tx.Init.PeriphInc = DMA_PINC_DISABLE; + hdma_usart2_tx.Init.MemInc = DMA_MINC_ENABLE; + hdma_usart2_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; + hdma_usart2_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; + hdma_usart2_tx.Init.Mode = DMA_NORMAL; + hdma_usart2_tx.Init.Priority = DMA_PRIORITY_LOW; + if (HAL_DMA_Init(&hdma_usart2_tx) != HAL_OK) + { + Error_Handler(); + } + + if (HAL_DMA_ConfigChannelAttributes(&hdma_usart2_tx, DMA_CHANNEL_NPRIV) != HAL_OK) + { + Error_Handler(); + } + + __HAL_LINKDMA(uartHandle,hdmatx,hdma_usart2_tx); + + /* USART2 interrupt Init */ + HAL_NVIC_SetPriority(USART2_IRQn, 2, 0); + HAL_NVIC_EnableIRQ(USART2_IRQn); + /* USER CODE BEGIN USART2_MspInit 1 */ + + /* USER CODE END USART2_MspInit 1 */ + } +} + +void HAL_UART_MspDeInit(UART_HandleTypeDef* uartHandle) +{ + + if(uartHandle->Instance==USART2) + { + /* USER CODE BEGIN USART2_MspDeInit 0 */ + + /* USER CODE END USART2_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_USART2_CLK_DISABLE(); + + /**USART2 GPIO Configuration + PA3 ------> USART2_RX + PA2 ------> USART2_TX + */ + HAL_GPIO_DeInit(GPIOA, USARTx_RX_Pin|USARTx_TX_Pin); + + /* USART2 DMA DeInit */ + HAL_DMA_DeInit(uartHandle->hdmatx); + + /* USART2 interrupt Deinit */ + HAL_NVIC_DisableIRQ(USART2_IRQn); + /* USER CODE BEGIN USART2_MspDeInit 1 */ + + /* USER CODE END USART2_MspDeInit 1 */ + } +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ diff --git a/Core/Src/usart_if.c b/Core/Src/usart_if.c new file mode 100644 index 0000000..9f0331e --- /dev/null +++ b/Core/Src/usart_if.c @@ -0,0 +1,260 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file usart_if.c + * @author MCD Application Team + * @brief Configuration of UART driver interface for hyperterminal communication + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "usart_if.h" + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* External variables ---------------------------------------------------------*/ +/** + * @brief DMA handle + */ +extern DMA_HandleTypeDef hdma_usart2_tx; + +/** + * @brief UART handle + */ +extern UART_HandleTypeDef huart2; + +/** + * @brief buffer to receive 1 character + */ +uint8_t charRx; + +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + +/* Private typedef -----------------------------------------------------------*/ +/** + * @brief Trace driver callbacks handler + */ +const UTIL_ADV_TRACE_Driver_s UTIL_TraceDriver = +{ + vcom_Init, + vcom_DeInit, + vcom_ReceiveInit, + vcom_Trace_DMA, +}; + +/* USER CODE BEGIN PTD */ + +/* USER CODE END PTD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ + +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ +/** + * @brief TX complete callback + * @return none + */ +static void (*TxCpltCallback)(void *); +/** + * @brief RX complete callback + * @param rxChar ptr of chars buffer sent by user + * @param size buffer size + * @param error errorcode + * @return none + */ +static void (*RxCpltCallback)(uint8_t *rxChar, uint16_t size, uint8_t error); + +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ + +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* Exported functions --------------------------------------------------------*/ + +UTIL_ADV_TRACE_Status_t vcom_Init(void (*cb)(void *)) +{ + /* USER CODE BEGIN vcom_Init_1 */ + + /* USER CODE END vcom_Init_1 */ + TxCpltCallback = cb; + MX_DMA_Init(); + MX_USART2_UART_Init(); + LL_EXTI_EnableIT_0_31(LL_EXTI_LINE_27); + return UTIL_ADV_TRACE_OK; + /* USER CODE BEGIN vcom_Init_2 */ + + /* USER CODE END vcom_Init_2 */ +} + +UTIL_ADV_TRACE_Status_t vcom_DeInit(void) +{ + /* USER CODE BEGIN vcom_DeInit_1 */ + + /* USER CODE END vcom_DeInit_1 */ + /* ##-1- Reset peripherals ################################################## */ + __HAL_RCC_USART2_FORCE_RESET(); + __HAL_RCC_USART2_RELEASE_RESET(); + + /* ##-2- MspDeInit ################################################## */ + HAL_UART_MspDeInit(&huart2); + + /* ##-3- Disable the NVIC for DMA ########################################### */ + /* USER CODE BEGIN 1 */ + HAL_NVIC_DisableIRQ(DMA1_Channel5_IRQn); + + return UTIL_ADV_TRACE_OK; + /* USER CODE END 1 */ + /* USER CODE BEGIN vcom_DeInit_2 */ + + /* USER CODE END vcom_DeInit_2 */ +} + +void vcom_Trace(uint8_t *p_data, uint16_t size) +{ + /* USER CODE BEGIN vcom_Trace_1 */ + + /* USER CODE END vcom_Trace_1 */ + HAL_UART_Transmit(&huart2, p_data, size, 1000); + /* USER CODE BEGIN vcom_Trace_2 */ + + /* USER CODE END vcom_Trace_2 */ +} + +UTIL_ADV_TRACE_Status_t vcom_Trace_DMA(uint8_t *p_data, uint16_t size) +{ + /* USER CODE BEGIN vcom_Trace_DMA_1 */ + + /* USER CODE END vcom_Trace_DMA_1 */ + HAL_UART_Transmit_DMA(&huart2, p_data, size); + return UTIL_ADV_TRACE_OK; + /* USER CODE BEGIN vcom_Trace_DMA_2 */ + + /* USER CODE END vcom_Trace_DMA_2 */ +} + +UTIL_ADV_TRACE_Status_t vcom_ReceiveInit(void (*RxCb)(uint8_t *rxChar, uint16_t size, uint8_t error)) +{ + /* USER CODE BEGIN vcom_ReceiveInit_1 */ + + /* USER CODE END vcom_ReceiveInit_1 */ + UART_WakeUpTypeDef WakeUpSelection; + + /*record call back*/ + RxCpltCallback = RxCb; + + /*Set wakeUp event on start bit*/ + WakeUpSelection.WakeUpEvent = UART_WAKEUP_ON_STARTBIT; + + HAL_UARTEx_StopModeWakeUpSourceConfig(&huart2, WakeUpSelection); + + /* Make sure that no UART transfer is on-going */ + while (__HAL_UART_GET_FLAG(&huart2, USART_ISR_BUSY) == SET); + + /* Make sure that UART is ready to receive) */ + while (__HAL_UART_GET_FLAG(&huart2, USART_ISR_REACK) == RESET); + + /* Enable USART interrupt */ + __HAL_UART_ENABLE_IT(&huart2, UART_IT_WUF); + + /*Enable wakeup from stop mode*/ + HAL_UARTEx_EnableStopMode(&huart2); + + /*Start LPUART receive on IT*/ + HAL_UART_Receive_IT(&huart2, &charRx, 1); + + return UTIL_ADV_TRACE_OK; + /* USER CODE BEGIN vcom_ReceiveInit_2 */ + + /* USER CODE END vcom_ReceiveInit_2 */ +} + +void vcom_Resume(void) +{ + /* USER CODE BEGIN vcom_Resume_1 */ + + /* USER CODE END vcom_Resume_1 */ + /*to re-enable lost UART settings*/ + if (HAL_UART_Init(&huart2) != HAL_OK) + { + Error_Handler(); + } + + /*to re-enable lost DMA settings*/ + if (HAL_DMA_Init(&hdma_usart2_tx) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN vcom_Resume_2 */ + + /* USER CODE END vcom_Resume_2 */ +} + +void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) +{ + /* USER CODE BEGIN HAL_UART_TxCpltCallback_1 */ + + /* USER CODE END HAL_UART_TxCpltCallback_1 */ + /* buffer transmission complete*/ + if (huart->Instance == USART2) + { + TxCpltCallback(NULL); + } + /* USER CODE BEGIN HAL_UART_TxCpltCallback_2 */ + + /* USER CODE END HAL_UART_TxCpltCallback_2 */ +} + +void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) +{ + /* USER CODE BEGIN HAL_UART_RxCpltCallback_1 */ + + /* USER CODE END HAL_UART_RxCpltCallback_1 */ + if (huart->Instance == USART2) + { + if ((NULL != RxCpltCallback) && (HAL_UART_ERROR_NONE == huart->ErrorCode)) + { + RxCpltCallback(&charRx, 1, 0); + } + HAL_UART_Receive_IT(huart, &charRx, 1); + } + /* USER CODE BEGIN HAL_UART_RxCpltCallback_2 */ + + /* USER CODE END HAL_UART_RxCpltCallback_2 */ +} + +/* USER CODE BEGIN EF */ + +/* USER CODE END EF */ + +/* Private Functions Definition -----------------------------------------------*/ + +/* USER CODE BEGIN PrFD */ + +/* USER CODE END PrFD */ diff --git a/Core/Startup/startup_stm32wl55jcix.s b/Core/Startup/startup_stm32wl55jcix.s new file mode 100644 index 0000000..478c7e4 --- /dev/null +++ b/Core/Startup/startup_stm32wl55jcix.s @@ -0,0 +1,434 @@ +/** + ****************************************************************************** + * @file startup_stm32wl55xx_cm4.s + * @author MCD Application Team + * @brief STM32WL55xx devices Cortex-M4 vector table for GCC toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address, + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M4 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + * Copyright (c) 2020-2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +.syntax unified +.cpu cortex-m4 +.fpu softvfp +.thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr r0, =_estack + mov sp, r0 /* set stack pointer */ + +/* Call the clock system initialization function.*/ + bl SystemInit + +/* Copy the data segment initializers from flash to SRAM */ + ldr r0, =_sdata + ldr r1, =_edata + ldr r2, =_sidata + movs r3, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r4, [r2, r3] + str r4, [r0, r3] + adds r3, r3, #4 + +LoopCopyDataInit: + adds r4, r0, r3 + cmp r4, r1 + bcc CopyDataInit + +/* Zero fill the bss segment. */ + ldr r2, =_sbss + ldr r4, =_ebss + movs r3, #0 + b LoopFillZerobss + +FillZerobss: + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + cmp r2, r4 + bcc FillZerobss + +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + + .size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler + +/****************************************************************************** +* +* The STM32WL55xx Cortex-M4 vector table. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler /* Window Watchdog interrupt */ + .word PVD_PVM_IRQHandler /* PVD and PVM interrupt through EXTI */ + .word TAMP_STAMP_LSECSS_SSRU_IRQHandler /* RTC Tamper, RTC TimeStamp, LSECSS and RTC SSRU int.*/ + .word RTC_WKUP_IRQHandler /* RTC wakeup interrupt through EXTI[19] */ + .word FLASH_IRQHandler /* Flash memory global interrupt and Flash memory ECC */ + .word RCC_IRQHandler /* RCC global interrupt */ + .word EXTI0_IRQHandler /* EXTI line 0 interrupt */ + .word EXTI1_IRQHandler /* EXTI line 1 interrupt */ + .word EXTI2_IRQHandler /* EXTI line 2 interrupt */ + .word EXTI3_IRQHandler /* EXTI line 3 interrupt */ + .word EXTI4_IRQHandler /* EXTI line 4 interrupt */ + .word DMA1_Channel1_IRQHandler /* DMA1 channel 1 interrupt */ + .word DMA1_Channel2_IRQHandler /* DMA1 channel 2 interrupt */ + .word DMA1_Channel3_IRQHandler /* DMA1 channel 3 interrupt */ + .word DMA1_Channel4_IRQHandler /* DMA1 channel 4 interrupt */ + .word DMA1_Channel5_IRQHandler /* DMA1 channel 5 interrupt */ + .word DMA1_Channel6_IRQHandler /* DMA1 channel 6 interrupt */ + .word DMA1_Channel7_IRQHandler /* DMA1 channel 7 interrupt */ + .word ADC_IRQHandler /* ADC interrupt */ + .word DAC_IRQHandler /* DAC interrupt */ + .word C2SEV_PWR_C2H_IRQHandler /* CPU M0+ SEV Interrupt */ + .word COMP_IRQHandler /* COMP1 and COMP2 interrupt through EXTI */ + .word EXTI9_5_IRQHandler /* EXTI line 9_5 interrupt */ + .word TIM1_BRK_IRQHandler /* Timer 1 break interrupt */ + .word TIM1_UP_IRQHandler /* Timer 1 Update */ + .word TIM1_TRG_COM_IRQHandler /* Timer 1 trigger and communication */ + .word TIM1_CC_IRQHandler /* Timer 1 capture compare interrupt */ + .word TIM2_IRQHandler /* TIM2 global interrupt */ + .word TIM16_IRQHandler /* Timer 16 global interrupt */ + .word TIM17_IRQHandler /* Timer 17 global interrupt */ + .word I2C1_EV_IRQHandler /* I2C1 event interrupt */ + .word I2C1_ER_IRQHandler /* I2C1 event interrupt */ + .word I2C2_EV_IRQHandler /* I2C2 error interrupt */ + .word I2C2_ER_IRQHandler /* I2C2 error interrupt */ + .word SPI1_IRQHandler /* SPI1 global interrupt */ + .word SPI2_IRQHandler /* SPI2 global interrupt */ + .word USART1_IRQHandler /* USART1 global interrupt */ + .word USART2_IRQHandler /* USART2 global interrupt */ + .word LPUART1_IRQHandler /* LPUART1 global interrupt */ + .word LPTIM1_IRQHandler /* LPtimer 1 global interrupt */ + .word LPTIM2_IRQHandler /* LPtimer 2 global interrupt */ + .word EXTI15_10_IRQHandler /* EXTI line 15_10] interrupt through EXTI */ + .word RTC_Alarm_IRQHandler /* RTC Alarms A & B interrupt */ + .word LPTIM3_IRQHandler /* LPtimer 3 global interrupt */ + .word SUBGHZSPI_IRQHandler /* SUBGHZSPI global interrupt */ + .word IPCC_C1_RX_IRQHandler /* IPCC CPU1 RX occupied interrupt */ + .word IPCC_C1_TX_IRQHandler /* IPCC CPU1 RX free interrupt */ + .word HSEM_IRQHandler /* Semaphore interrupt 0 to CPU1 */ + .word I2C3_EV_IRQHandler /* I2C3 event interrupt */ + .word I2C3_ER_IRQHandler /* I2C3 error interrupt */ + .word SUBGHZ_Radio_IRQHandler /* Radio IRQs RFBUSY interrupt through EXTI */ + .word AES_IRQHandler /* AES global interrupt */ + .word RNG_IRQHandler /* RNG interrupt */ + .word PKA_IRQHandler /* PKA interrupt */ + .word DMA2_Channel1_IRQHandler /* DMA2 channel 1 interrupt */ + .word DMA2_Channel2_IRQHandler /* DMA2 channel 2 interrupt */ + .word DMA2_Channel3_IRQHandler /* DMA2 channel 3 interrupt */ + .word DMA2_Channel4_IRQHandler /* DMA2 channel 4 interrupt */ + .word DMA2_Channel5_IRQHandler /* DMA2 channel 5 interrupt */ + .word DMA2_Channel6_IRQHandler /* DMA2 channel 6 interrupt */ + .word DMA2_Channel7_IRQHandler /* DMA2 channel 7 interrupt */ + .word DMAMUX1_OVR_IRQHandler /* DMAMUX overrun interrupt */ + + .size g_pfnVectors, .-g_pfnVectors + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_PVM_IRQHandler + .thumb_set PVD_PVM_IRQHandler,Default_Handler + + .weak TAMP_STAMP_LSECSS_SSRU_IRQHandler + .thumb_set TAMP_STAMP_LSECSS_SSRU_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC_IRQHandler + .thumb_set ADC_IRQHandler,Default_Handler + + .weak DAC_IRQHandler + .thumb_set DAC_IRQHandler,Default_Handler + + .weak C2SEV_PWR_C2H_IRQHandler + .thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler + + .weak COMP_IRQHandler + .thumb_set COMP_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_IRQHandler + .thumb_set TIM1_BRK_IRQHandler,Default_Handler + + .weak TIM1_UP_IRQHandler + .thumb_set TIM1_UP_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_IRQHandler + .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM16_IRQHandler + .thumb_set TIM16_IRQHandler,Default_Handler + + .weak TIM17_IRQHandler + .thumb_set TIM17_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak LPUART1_IRQHandler + .thumb_set LPUART1_IRQHandler,Default_Handler + + .weak LPTIM1_IRQHandler + .thumb_set LPTIM1_IRQHandler,Default_Handler + + .weak LPTIM2_IRQHandler + .thumb_set LPTIM2_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak LPTIM3_IRQHandler + .thumb_set LPTIM3_IRQHandler,Default_Handler + + .weak SUBGHZSPI_IRQHandler + .thumb_set SUBGHZSPI_IRQHandler,Default_Handler + + .weak IPCC_C1_RX_IRQHandler + .thumb_set IPCC_C1_RX_IRQHandler,Default_Handler + + .weak IPCC_C1_TX_IRQHandler + .thumb_set IPCC_C1_TX_IRQHandler,Default_Handler + + .weak HSEM_IRQHandler + .thumb_set HSEM_IRQHandler,Default_Handler + + .weak I2C3_EV_IRQHandler + .thumb_set I2C3_EV_IRQHandler,Default_Handler + + .weak I2C3_ER_IRQHandler + .thumb_set I2C3_ER_IRQHandler,Default_Handler + + .weak SUBGHZ_Radio_IRQHandler + .thumb_set SUBGHZ_Radio_IRQHandler,Default_Handler + + .weak AES_IRQHandler + .thumb_set AES_IRQHandler,Default_Handler + + .weak RNG_IRQHandler + .thumb_set RNG_IRQHandler,Default_Handler + + .weak PKA_IRQHandler + .thumb_set PKA_IRQHandler,Default_Handler + + .weak DMA2_Channel1_IRQHandler + .thumb_set DMA2_Channel1_IRQHandler,Default_Handler + + .weak DMA2_Channel2_IRQHandler + .thumb_set DMA2_Channel2_IRQHandler,Default_Handler + + .weak DMA2_Channel3_IRQHandler + .thumb_set DMA2_Channel3_IRQHandler,Default_Handler + + .weak DMA2_Channel4_IRQHandler + .thumb_set DMA2_Channel4_IRQHandler,Default_Handler + + .weak DMA2_Channel5_IRQHandler + .thumb_set DMA2_Channel5_IRQHandler,Default_Handler + + .weak DMA2_Channel6_IRQHandler + .thumb_set DMA2_Channel6_IRQHandler,Default_Handler + + .weak DMA2_Channel7_IRQHandler + .thumb_set DMA2_Channel7_IRQHandler,Default_Handler + + .weak DMAMUX1_OVR_IRQHandler + .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler + + .weak SystemInit diff --git a/Debug/Core/Src/dma.cyclo b/Debug/Core/Src/dma.cyclo new file mode 100644 index 0000000..72d8471 --- /dev/null +++ b/Debug/Core/Src/dma.cyclo @@ -0,0 +1,2 @@ +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h:287:22:LL_AHB1_GRP1_EnableClock 1 +../Core/Src/dma.c:39:6:MX_DMA_Init 1 diff --git a/Debug/Core/Src/dma.d b/Debug/Core/Src/dma.d new file mode 100644 index 0000000..19aff10 --- /dev/null +++ b/Debug/Core/Src/dma.d @@ -0,0 +1,77 @@ +Core/Src/dma.o: ../Core/Src/dma.c ../Core/Inc/dma.h ../Core/Inc/main.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h \ + ../Core/Inc/stm32wlxx_hal_conf.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wl55xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h +../Core/Inc/dma.h: +../Core/Inc/main.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h: +../Core/Inc/stm32wlxx_hal_conf.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wl55xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h: diff --git a/Debug/Core/Src/dma.o b/Debug/Core/Src/dma.o new file mode 100644 index 0000000..a20e3d6 Binary files /dev/null and b/Debug/Core/Src/dma.o differ diff --git a/Debug/Core/Src/dma.su b/Debug/Core/Src/dma.su new file mode 100644 index 0000000..6fe4ee8 --- /dev/null +++ b/Debug/Core/Src/dma.su @@ -0,0 +1,2 @@ +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h:287:22:LL_AHB1_GRP1_EnableClock 24 static +../Core/Src/dma.c:39:6:MX_DMA_Init 8 static diff --git a/Debug/Core/Src/gpio.cyclo b/Debug/Core/Src/gpio.cyclo new file mode 100644 index 0000000..dc16afa --- /dev/null +++ b/Debug/Core/Src/gpio.cyclo @@ -0,0 +1,2 @@ +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h:449:22:LL_AHB2_GRP1_EnableClock 1 +../Core/Src/gpio.c:42:6:MX_GPIO_Init 1 diff --git a/Debug/Core/Src/gpio.d b/Debug/Core/Src/gpio.d new file mode 100644 index 0000000..bb8b04c --- /dev/null +++ b/Debug/Core/Src/gpio.d @@ -0,0 +1,77 @@ +Core/Src/gpio.o: ../Core/Src/gpio.c ../Core/Inc/gpio.h ../Core/Inc/main.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h \ + ../Core/Inc/stm32wlxx_hal_conf.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wl55xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h +../Core/Inc/gpio.h: +../Core/Inc/main.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h: +../Core/Inc/stm32wlxx_hal_conf.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wl55xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h: diff --git a/Debug/Core/Src/gpio.o b/Debug/Core/Src/gpio.o new file mode 100644 index 0000000..3f05ca1 Binary files /dev/null and b/Debug/Core/Src/gpio.o differ diff --git a/Debug/Core/Src/gpio.su b/Debug/Core/Src/gpio.su new file mode 100644 index 0000000..5c03272 --- /dev/null +++ b/Debug/Core/Src/gpio.su @@ -0,0 +1,2 @@ +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h:449:22:LL_AHB2_GRP1_EnableClock 24 static +../Core/Src/gpio.c:42:6:MX_GPIO_Init 32 static diff --git a/Debug/Core/Src/main.cyclo b/Debug/Core/Src/main.cyclo new file mode 100644 index 0000000..6a8eab9 --- /dev/null +++ b/Debug/Core/Src/main.cyclo @@ -0,0 +1,4 @@ +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1257:22:LL_RCC_LSE_SetDriveCapability 1 +../Core/Src/main.c:64:5:main 1 +../Core/Src/main.c:110:6:SystemClock_Config 3 +../Core/Src/main.c:162:6:Error_Handler 1 diff --git a/Debug/Core/Src/main.d b/Debug/Core/Src/main.d new file mode 100644 index 0000000..bdae6b7 --- /dev/null +++ b/Debug/Core/Src/main.d @@ -0,0 +1,80 @@ +Core/Src/main.o: ../Core/Src/main.c ../Core/Inc/main.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h \ + ../Core/Inc/stm32wlxx_hal_conf.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wl55xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h \ + ../SubGHz_Phy/App/app_subghz_phy.h ../Core/Inc/gpio.h ../Core/Inc/main.h +../Core/Inc/main.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h: +../Core/Inc/stm32wlxx_hal_conf.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wl55xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h: +../SubGHz_Phy/App/app_subghz_phy.h: +../Core/Inc/gpio.h: +../Core/Inc/main.h: diff --git a/Debug/Core/Src/main.o b/Debug/Core/Src/main.o new file mode 100644 index 0000000..4cef3e0 Binary files /dev/null and b/Debug/Core/Src/main.o differ diff --git a/Debug/Core/Src/main.su b/Debug/Core/Src/main.su new file mode 100644 index 0000000..e55db8a --- /dev/null +++ b/Debug/Core/Src/main.su @@ -0,0 +1,4 @@ +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1257:22:LL_RCC_LSE_SetDriveCapability 16 static +../Core/Src/main.c:64:5:main 8 static +../Core/Src/main.c:110:6:SystemClock_Config 112 static +../Core/Src/main.c:162:6:Error_Handler 4 static,ignoring_inline_asm diff --git a/Debug/Core/Src/rtc.cyclo b/Debug/Core/Src/rtc.cyclo new file mode 100644 index 0000000..6c61529 --- /dev/null +++ b/Debug/Core/Src/rtc.cyclo @@ -0,0 +1,7 @@ +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2331:22:LL_RCC_EnableRTC 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2341:22:LL_RCC_DisableRTC 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h:914:22:LL_APB1_GRP1_EnableClock 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h:1018:22:LL_APB1_GRP1_DisableClock 1 +../Core/Src/rtc.c:30:6:MX_RTC_Init 4 +../Core/Src/rtc.c:86:6:HAL_RTC_MspInit 3 +../Core/Src/rtc.c:121:6:HAL_RTC_MspDeInit 2 diff --git a/Debug/Core/Src/rtc.d b/Debug/Core/Src/rtc.d new file mode 100644 index 0000000..7a50566 --- /dev/null +++ b/Debug/Core/Src/rtc.d @@ -0,0 +1,77 @@ +Core/Src/rtc.o: ../Core/Src/rtc.c ../Core/Inc/rtc.h ../Core/Inc/main.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h \ + ../Core/Inc/stm32wlxx_hal_conf.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wl55xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h +../Core/Inc/rtc.h: +../Core/Inc/main.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h: +../Core/Inc/stm32wlxx_hal_conf.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wl55xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h: diff --git a/Debug/Core/Src/rtc.o b/Debug/Core/Src/rtc.o new file mode 100644 index 0000000..03abf3e Binary files /dev/null and b/Debug/Core/Src/rtc.o differ diff --git a/Debug/Core/Src/rtc.su b/Debug/Core/Src/rtc.su new file mode 100644 index 0000000..c66adda --- /dev/null +++ b/Debug/Core/Src/rtc.su @@ -0,0 +1,7 @@ +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2331:22:LL_RCC_EnableRTC 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2341:22:LL_RCC_DisableRTC 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h:914:22:LL_APB1_GRP1_EnableClock 24 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h:1018:22:LL_APB1_GRP1_DisableClock 16 static +../Core/Src/rtc.c:30:6:MX_RTC_Init 56 static +../Core/Src/rtc.c:86:6:HAL_RTC_MspInit 72 static +../Core/Src/rtc.c:121:6:HAL_RTC_MspDeInit 16 static diff --git a/Debug/Core/Src/stm32_lpm_if.cyclo b/Debug/Core/Src/stm32_lpm_if.cyclo new file mode 100644 index 0000000..d946d53 --- /dev/null +++ b/Debug/Core/Src/stm32_lpm_if.cyclo @@ -0,0 +1,7 @@ +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h:2196:22:LL_PWR_ClearFlag_C1STOP_C1STB 1 +../Core/Src/stm32_lpm_if.c:78:6:PWR_EnterOffMode 1 +../Core/Src/stm32_lpm_if.c:85:6:PWR_ExitOffMode 1 +../Core/Src/stm32_lpm_if.c:92:6:PWR_EnterStopMode 1 +../Core/Src/stm32_lpm_if.c:110:6:PWR_ExitStopMode 1 +../Core/Src/stm32_lpm_if.c:129:6:PWR_EnterSleepMode 1 +../Core/Src/stm32_lpm_if.c:145:6:PWR_ExitSleepMode 1 diff --git a/Debug/Core/Src/stm32_lpm_if.d b/Debug/Core/Src/stm32_lpm_if.d new file mode 100644 index 0000000..0750dae --- /dev/null +++ b/Debug/Core/Src/stm32_lpm_if.d @@ -0,0 +1,105 @@ +Core/Src/stm32_lpm_if.o: ../Core/Src/stm32_lpm_if.c \ + ../Core/Inc/platform.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wl55xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h \ + ../Core/Inc/stm32wlxx_hal_conf.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h \ + ../Core/Inc/main.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_gpio.h \ + ../Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo_radio.h \ + ../Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo_errno.h \ + ../Core/Inc/stm32wlxx_nucleo_conf.h \ + ../Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo.h \ + ../Utilities/lpm/tiny_lpm/stm32_lpm.h ../Core/Inc/stm32_lpm_if.h \ + ../Core/Inc/usart_if.h ../Utilities/trace/adv_trace/stm32_adv_trace.h \ + ../Core/Inc/utilities_conf.h ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Utilities/misc/stm32_mem.h ../Utilities/misc/stm32_tiny_vsnprintf.h \ + ../Core/Inc/utilities_def.h ../Core/Inc/usart.h ../Core/Inc/dma.h +../Core/Inc/platform.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wl55xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h: +../Core/Inc/stm32wlxx_hal_conf.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h: +../Core/Inc/main.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_gpio.h: +../Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo_radio.h: +../Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo_errno.h: +../Core/Inc/stm32wlxx_nucleo_conf.h: +../Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo.h: +../Utilities/lpm/tiny_lpm/stm32_lpm.h: +../Core/Inc/stm32_lpm_if.h: +../Core/Inc/usart_if.h: +../Utilities/trace/adv_trace/stm32_adv_trace.h: +../Core/Inc/utilities_conf.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Utilities/misc/stm32_mem.h: +../Utilities/misc/stm32_tiny_vsnprintf.h: +../Core/Inc/utilities_def.h: +../Core/Inc/usart.h: +../Core/Inc/dma.h: diff --git a/Debug/Core/Src/stm32_lpm_if.o b/Debug/Core/Src/stm32_lpm_if.o new file mode 100644 index 0000000..d63e8c0 Binary files /dev/null and b/Debug/Core/Src/stm32_lpm_if.o differ diff --git a/Debug/Core/Src/stm32_lpm_if.su b/Debug/Core/Src/stm32_lpm_if.su new file mode 100644 index 0000000..0150788 --- /dev/null +++ b/Debug/Core/Src/stm32_lpm_if.su @@ -0,0 +1,7 @@ +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h:2196:22:LL_PWR_ClearFlag_C1STOP_C1STB 4 static +../Core/Src/stm32_lpm_if.c:78:6:PWR_EnterOffMode 4 static +../Core/Src/stm32_lpm_if.c:85:6:PWR_ExitOffMode 4 static +../Core/Src/stm32_lpm_if.c:92:6:PWR_EnterStopMode 8 static +../Core/Src/stm32_lpm_if.c:110:6:PWR_ExitStopMode 8 static +../Core/Src/stm32_lpm_if.c:129:6:PWR_EnterSleepMode 8 static +../Core/Src/stm32_lpm_if.c:145:6:PWR_ExitSleepMode 8 static diff --git a/Debug/Core/Src/stm32wlxx_hal_msp.cyclo b/Debug/Core/Src/stm32wlxx_hal_msp.cyclo new file mode 100644 index 0000000..5c76cfc --- /dev/null +++ b/Debug/Core/Src/stm32wlxx_hal_msp.cyclo @@ -0,0 +1 @@ +../Core/Src/stm32wlxx_hal_msp.c:63:6:HAL_MspInit 1 diff --git a/Debug/Core/Src/stm32wlxx_hal_msp.d b/Debug/Core/Src/stm32wlxx_hal_msp.d new file mode 100644 index 0000000..cc2b865 --- /dev/null +++ b/Debug/Core/Src/stm32wlxx_hal_msp.d @@ -0,0 +1,76 @@ +Core/Src/stm32wlxx_hal_msp.o: ../Core/Src/stm32wlxx_hal_msp.c \ + ../Core/Inc/main.h ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h \ + ../Core/Inc/stm32wlxx_hal_conf.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wl55xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h +../Core/Inc/main.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h: +../Core/Inc/stm32wlxx_hal_conf.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wl55xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h: diff --git a/Debug/Core/Src/stm32wlxx_hal_msp.o b/Debug/Core/Src/stm32wlxx_hal_msp.o new file mode 100644 index 0000000..921bd3b Binary files /dev/null and b/Debug/Core/Src/stm32wlxx_hal_msp.o differ diff --git a/Debug/Core/Src/stm32wlxx_hal_msp.su b/Debug/Core/Src/stm32wlxx_hal_msp.su new file mode 100644 index 0000000..f059ec5 --- /dev/null +++ b/Debug/Core/Src/stm32wlxx_hal_msp.su @@ -0,0 +1 @@ +../Core/Src/stm32wlxx_hal_msp.c:63:6:HAL_MspInit 4 static diff --git a/Debug/Core/Src/stm32wlxx_it.cyclo b/Debug/Core/Src/stm32wlxx_it.cyclo new file mode 100644 index 0000000..bdee8c7 --- /dev/null +++ b/Debug/Core/Src/stm32wlxx_it.cyclo @@ -0,0 +1,17 @@ +../Core/Src/stm32wlxx_it.c:72:6:NMI_Handler 1 +../Core/Src/stm32wlxx_it.c:87:6:HardFault_Handler 1 +../Core/Src/stm32wlxx_it.c:102:6:MemManage_Handler 1 +../Core/Src/stm32wlxx_it.c:117:6:BusFault_Handler 1 +../Core/Src/stm32wlxx_it.c:132:6:UsageFault_Handler 1 +../Core/Src/stm32wlxx_it.c:147:6:SVC_Handler 1 +../Core/Src/stm32wlxx_it.c:160:6:DebugMon_Handler 1 +../Core/Src/stm32wlxx_it.c:173:6:PendSV_Handler 1 +../Core/Src/stm32wlxx_it.c:186:6:SysTick_Handler 1 +../Core/Src/stm32wlxx_it.c:206:6:TAMP_STAMP_LSECSS_SSRU_IRQHandler 1 +../Core/Src/stm32wlxx_it.c:220:6:EXTI0_IRQHandler 1 +../Core/Src/stm32wlxx_it.c:234:6:EXTI1_IRQHandler 1 +../Core/Src/stm32wlxx_it.c:248:6:DMA1_Channel5_IRQHandler 1 +../Core/Src/stm32wlxx_it.c:262:6:EXTI9_5_IRQHandler 1 +../Core/Src/stm32wlxx_it.c:276:6:USART2_IRQHandler 1 +../Core/Src/stm32wlxx_it.c:290:6:RTC_Alarm_IRQHandler 1 +../Core/Src/stm32wlxx_it.c:304:6:SUBGHZ_Radio_IRQHandler 1 diff --git a/Debug/Core/Src/stm32wlxx_it.d b/Debug/Core/Src/stm32wlxx_it.d new file mode 100644 index 0000000..2ec0bb4 --- /dev/null +++ b/Debug/Core/Src/stm32wlxx_it.d @@ -0,0 +1,78 @@ +Core/Src/stm32wlxx_it.o: ../Core/Src/stm32wlxx_it.c ../Core/Inc/main.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h \ + ../Core/Inc/stm32wlxx_hal_conf.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wl55xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h \ + ../Core/Inc/stm32wlxx_it.h +../Core/Inc/main.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h: +../Core/Inc/stm32wlxx_hal_conf.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wl55xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h: +../Core/Inc/stm32wlxx_it.h: diff --git a/Debug/Core/Src/stm32wlxx_it.o b/Debug/Core/Src/stm32wlxx_it.o new file mode 100644 index 0000000..3c8a00f Binary files /dev/null and b/Debug/Core/Src/stm32wlxx_it.o differ diff --git a/Debug/Core/Src/stm32wlxx_it.su b/Debug/Core/Src/stm32wlxx_it.su new file mode 100644 index 0000000..5394604 --- /dev/null +++ b/Debug/Core/Src/stm32wlxx_it.su @@ -0,0 +1,17 @@ +../Core/Src/stm32wlxx_it.c:72:6:NMI_Handler 4 static +../Core/Src/stm32wlxx_it.c:87:6:HardFault_Handler 4 static +../Core/Src/stm32wlxx_it.c:102:6:MemManage_Handler 4 static +../Core/Src/stm32wlxx_it.c:117:6:BusFault_Handler 4 static +../Core/Src/stm32wlxx_it.c:132:6:UsageFault_Handler 4 static +../Core/Src/stm32wlxx_it.c:147:6:SVC_Handler 4 static +../Core/Src/stm32wlxx_it.c:160:6:DebugMon_Handler 4 static +../Core/Src/stm32wlxx_it.c:173:6:PendSV_Handler 4 static +../Core/Src/stm32wlxx_it.c:186:6:SysTick_Handler 4 static +../Core/Src/stm32wlxx_it.c:206:6:TAMP_STAMP_LSECSS_SSRU_IRQHandler 8 static +../Core/Src/stm32wlxx_it.c:220:6:EXTI0_IRQHandler 8 static +../Core/Src/stm32wlxx_it.c:234:6:EXTI1_IRQHandler 8 static +../Core/Src/stm32wlxx_it.c:248:6:DMA1_Channel5_IRQHandler 8 static +../Core/Src/stm32wlxx_it.c:262:6:EXTI9_5_IRQHandler 8 static +../Core/Src/stm32wlxx_it.c:276:6:USART2_IRQHandler 8 static +../Core/Src/stm32wlxx_it.c:290:6:RTC_Alarm_IRQHandler 8 static +../Core/Src/stm32wlxx_it.c:304:6:SUBGHZ_Radio_IRQHandler 8 static diff --git a/Debug/Core/Src/subdir.mk b/Debug/Core/Src/subdir.mk new file mode 100644 index 0000000..ccadf88 --- /dev/null +++ b/Debug/Core/Src/subdir.mk @@ -0,0 +1,72 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (13.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Core/Src/dma.c \ +../Core/Src/gpio.c \ +../Core/Src/main.c \ +../Core/Src/rtc.c \ +../Core/Src/stm32_lpm_if.c \ +../Core/Src/stm32wlxx_hal_msp.c \ +../Core/Src/stm32wlxx_it.c \ +../Core/Src/subghz.c \ +../Core/Src/sys_app.c \ +../Core/Src/sys_debug.c \ +../Core/Src/syscalls.c \ +../Core/Src/sysmem.c \ +../Core/Src/system_stm32wlxx.c \ +../Core/Src/timer_if.c \ +../Core/Src/usart.c \ +../Core/Src/usart_if.c + +OBJS += \ +./Core/Src/dma.o \ +./Core/Src/gpio.o \ +./Core/Src/main.o \ +./Core/Src/rtc.o \ +./Core/Src/stm32_lpm_if.o \ +./Core/Src/stm32wlxx_hal_msp.o \ +./Core/Src/stm32wlxx_it.o \ +./Core/Src/subghz.o \ +./Core/Src/sys_app.o \ +./Core/Src/sys_debug.o \ +./Core/Src/syscalls.o \ +./Core/Src/sysmem.o \ +./Core/Src/system_stm32wlxx.o \ +./Core/Src/timer_if.o \ +./Core/Src/usart.o \ +./Core/Src/usart_if.o + +C_DEPS += \ +./Core/Src/dma.d \ +./Core/Src/gpio.d \ +./Core/Src/main.d \ +./Core/Src/rtc.d \ +./Core/Src/stm32_lpm_if.d \ +./Core/Src/stm32wlxx_hal_msp.d \ +./Core/Src/stm32wlxx_it.d \ +./Core/Src/subghz.d \ +./Core/Src/sys_app.d \ +./Core/Src/sys_debug.d \ +./Core/Src/syscalls.d \ +./Core/Src/sysmem.d \ +./Core/Src/system_stm32wlxx.d \ +./Core/Src/timer_if.d \ +./Core/Src/usart.d \ +./Core/Src/usart_if.d + + +# Each subdirectory must supply rules for building sources it contributes +Core/Src/%.o Core/Src/%.su Core/Src/%.cyclo: ../Core/Src/%.c Core/Src/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WL55xx -c -I../Core/Inc -I../SubGHz_Phy/App -I../SubGHz_Phy/Target -I../Utilities/trace/adv_trace -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Utilities/misc -I../Utilities/sequencer -I../Utilities/timer -I../Utilities/lpm/tiny_lpm -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Middlewares/Third_Party/SubGHz_Phy -I../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver -I../Drivers/CMSIS/Include -I../Drivers/BSP/STM32WLxx_Nucleo -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Core-2f-Src + +clean-Core-2f-Src: + -$(RM) ./Core/Src/dma.cyclo ./Core/Src/dma.d ./Core/Src/dma.o ./Core/Src/dma.su ./Core/Src/gpio.cyclo ./Core/Src/gpio.d ./Core/Src/gpio.o ./Core/Src/gpio.su ./Core/Src/main.cyclo ./Core/Src/main.d ./Core/Src/main.o ./Core/Src/main.su ./Core/Src/rtc.cyclo ./Core/Src/rtc.d ./Core/Src/rtc.o ./Core/Src/rtc.su ./Core/Src/stm32_lpm_if.cyclo ./Core/Src/stm32_lpm_if.d ./Core/Src/stm32_lpm_if.o ./Core/Src/stm32_lpm_if.su ./Core/Src/stm32wlxx_hal_msp.cyclo ./Core/Src/stm32wlxx_hal_msp.d ./Core/Src/stm32wlxx_hal_msp.o ./Core/Src/stm32wlxx_hal_msp.su ./Core/Src/stm32wlxx_it.cyclo ./Core/Src/stm32wlxx_it.d ./Core/Src/stm32wlxx_it.o ./Core/Src/stm32wlxx_it.su ./Core/Src/subghz.cyclo ./Core/Src/subghz.d ./Core/Src/subghz.o ./Core/Src/subghz.su ./Core/Src/sys_app.cyclo ./Core/Src/sys_app.d ./Core/Src/sys_app.o ./Core/Src/sys_app.su ./Core/Src/sys_debug.cyclo ./Core/Src/sys_debug.d ./Core/Src/sys_debug.o ./Core/Src/sys_debug.su ./Core/Src/syscalls.cyclo ./Core/Src/syscalls.d ./Core/Src/syscalls.o ./Core/Src/syscalls.su ./Core/Src/sysmem.cyclo ./Core/Src/sysmem.d ./Core/Src/sysmem.o ./Core/Src/sysmem.su ./Core/Src/system_stm32wlxx.cyclo ./Core/Src/system_stm32wlxx.d ./Core/Src/system_stm32wlxx.o ./Core/Src/system_stm32wlxx.su ./Core/Src/timer_if.cyclo ./Core/Src/timer_if.d ./Core/Src/timer_if.o ./Core/Src/timer_if.su ./Core/Src/usart.cyclo ./Core/Src/usart.d ./Core/Src/usart.o ./Core/Src/usart.su ./Core/Src/usart_if.cyclo ./Core/Src/usart_if.d ./Core/Src/usart_if.o ./Core/Src/usart_if.su + +.PHONY: clean-Core-2f-Src + diff --git a/Debug/Core/Src/subghz.cyclo b/Debug/Core/Src/subghz.cyclo new file mode 100644 index 0000000..17cb04f --- /dev/null +++ b/Debug/Core/Src/subghz.cyclo @@ -0,0 +1,5 @@ +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h:1488:22:LL_APB3_GRP1_EnableClock 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h:1516:22:LL_APB3_GRP1_DisableClock 1 +../Core/Src/subghz.c:30:6:MX_SUBGHZ_Init 2 +../Core/Src/subghz.c:51:6:HAL_SUBGHZ_MspInit 1 +../Core/Src/subghz.c:68:6:HAL_SUBGHZ_MspDeInit 1 diff --git a/Debug/Core/Src/subghz.d b/Debug/Core/Src/subghz.d new file mode 100644 index 0000000..ae1445c --- /dev/null +++ b/Debug/Core/Src/subghz.d @@ -0,0 +1,77 @@ +Core/Src/subghz.o: ../Core/Src/subghz.c ../Core/Inc/subghz.h \ + ../Core/Inc/main.h ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h \ + ../Core/Inc/stm32wlxx_hal_conf.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wl55xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h +../Core/Inc/subghz.h: +../Core/Inc/main.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h: +../Core/Inc/stm32wlxx_hal_conf.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wl55xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h: diff --git a/Debug/Core/Src/subghz.o b/Debug/Core/Src/subghz.o new file mode 100644 index 0000000..abd910f Binary files /dev/null and b/Debug/Core/Src/subghz.o differ diff --git a/Debug/Core/Src/subghz.su b/Debug/Core/Src/subghz.su new file mode 100644 index 0000000..d2f1f5f --- /dev/null +++ b/Debug/Core/Src/subghz.su @@ -0,0 +1,5 @@ +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h:1488:22:LL_APB3_GRP1_EnableClock 24 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h:1516:22:LL_APB3_GRP1_DisableClock 16 static +../Core/Src/subghz.c:30:6:MX_SUBGHZ_Init 8 static +../Core/Src/subghz.c:51:6:HAL_SUBGHZ_MspInit 16 static +../Core/Src/subghz.c:68:6:HAL_SUBGHZ_MspDeInit 16 static diff --git a/Debug/Core/Src/sys_app.cyclo b/Debug/Core/Src/sys_app.cyclo new file mode 100644 index 0000000..b5cb7c9 --- /dev/null +++ b/Debug/Core/Src/sys_app.cyclo @@ -0,0 +1,10 @@ +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1971:22:LL_RCC_SetClkAfterWakeFromStop 1 +../Core/Src/sys_app.c:83:6:SystemApp_Init 1 +../Core/Src/sys_app.c:125:6:UTIL_SEQ_Idle 1 +../Core/Src/sys_app.c:142:13:TimestampNow 1 +../Core/Src/sys_app.c:156:6:UTIL_ADV_TRACE_PreSendHook 1 +../Core/Src/sys_app.c:167:6:UTIL_ADV_TRACE_PostSendHook 1 +../Core/Src/sys_app.c:178:13:tiny_snprintf_like 1 +../Core/Src/sys_app.c:201:19:HAL_InitTick 1 +../Core/Src/sys_app.c:216:10:HAL_GetTick 2 +../Core/Src/sys_app.c:248:6:HAL_Delay 1 diff --git a/Debug/Core/Src/sys_app.d b/Debug/Core/Src/sys_app.d new file mode 100644 index 0000000..1597f21 --- /dev/null +++ b/Debug/Core/Src/sys_app.d @@ -0,0 +1,112 @@ +Core/Src/sys_app.o: ../Core/Src/sys_app.c ../Core/Inc/platform.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wl55xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h \ + ../Core/Inc/stm32wlxx_hal_conf.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h \ + ../Core/Inc/main.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_gpio.h \ + ../Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo_radio.h \ + ../Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo_errno.h \ + ../Core/Inc/stm32wlxx_nucleo_conf.h \ + ../Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo.h ../Core/Inc/sys_app.h \ + ../Core/Inc/sys_conf.h ../Utilities/trace/adv_trace/stm32_adv_trace.h \ + ../Core/Inc/utilities_conf.h ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Utilities/misc/stm32_mem.h ../Utilities/misc/stm32_tiny_vsnprintf.h \ + ../Core/Inc/utilities_def.h ../Utilities/sequencer/stm32_seq.h \ + ../Utilities/misc/stm32_systime.h ../Utilities/lpm/tiny_lpm/stm32_lpm.h \ + ../Core/Inc/timer_if.h ../Utilities/timer/stm32_timer.h \ + ../Core/Inc/utilities_def.h ../Core/Inc/sys_debug.h \ + ../Core/Inc/platform.h +../Core/Inc/platform.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wl55xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h: +../Core/Inc/stm32wlxx_hal_conf.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h: +../Core/Inc/main.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_gpio.h: +../Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo_radio.h: +../Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo_errno.h: +../Core/Inc/stm32wlxx_nucleo_conf.h: +../Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo.h: +../Core/Inc/sys_app.h: +../Core/Inc/sys_conf.h: +../Utilities/trace/adv_trace/stm32_adv_trace.h: +../Core/Inc/utilities_conf.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Utilities/misc/stm32_mem.h: +../Utilities/misc/stm32_tiny_vsnprintf.h: +../Core/Inc/utilities_def.h: +../Utilities/sequencer/stm32_seq.h: +../Utilities/misc/stm32_systime.h: +../Utilities/lpm/tiny_lpm/stm32_lpm.h: +../Core/Inc/timer_if.h: +../Utilities/timer/stm32_timer.h: +../Core/Inc/utilities_def.h: +../Core/Inc/sys_debug.h: +../Core/Inc/platform.h: diff --git a/Debug/Core/Src/sys_app.o b/Debug/Core/Src/sys_app.o new file mode 100644 index 0000000..7e97573 Binary files /dev/null and b/Debug/Core/Src/sys_app.o differ diff --git a/Debug/Core/Src/sys_app.su b/Debug/Core/Src/sys_app.su new file mode 100644 index 0000000..b46bd04 --- /dev/null +++ b/Debug/Core/Src/sys_app.su @@ -0,0 +1,10 @@ +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1971:22:LL_RCC_SetClkAfterWakeFromStop 16 static +../Core/Src/sys_app.c:83:6:SystemApp_Init 8 static +../Core/Src/sys_app.c:125:6:UTIL_SEQ_Idle 8 static +../Core/Src/sys_app.c:142:13:TimestampNow 32 static +../Core/Src/sys_app.c:156:6:UTIL_ADV_TRACE_PreSendHook 8 static +../Core/Src/sys_app.c:167:6:UTIL_ADV_TRACE_PostSendHook 8 static +../Core/Src/sys_app.c:178:13:tiny_snprintf_like 24 static +../Core/Src/sys_app.c:201:19:HAL_InitTick 16 static +../Core/Src/sys_app.c:216:10:HAL_GetTick 16 static +../Core/Src/sys_app.c:248:6:HAL_Delay 16 static diff --git a/Debug/Core/Src/sys_debug.cyclo b/Debug/Core/Src/sys_debug.cyclo new file mode 100644 index 0000000..eed2153 --- /dev/null +++ b/Debug/Core/Src/sys_debug.cyclo @@ -0,0 +1,3 @@ +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h:449:22:LL_AHB2_GRP1_EnableClock 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h:336:22:LL_EXTI_EnableIT_32_63 1 +../Core/Src/sys_debug.c:64:6:DBG_Init 1 diff --git a/Debug/Core/Src/sys_debug.d b/Debug/Core/Src/sys_debug.d new file mode 100644 index 0000000..f367ba6 --- /dev/null +++ b/Debug/Core/Src/sys_debug.d @@ -0,0 +1,92 @@ +Core/Src/sys_debug.o: ../Core/Src/sys_debug.c ../Core/Inc/platform.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wl55xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h \ + ../Core/Inc/stm32wlxx_hal_conf.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h \ + ../Core/Inc/main.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_gpio.h \ + ../Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo_radio.h \ + ../Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo_errno.h \ + ../Core/Inc/stm32wlxx_nucleo_conf.h \ + ../Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo.h \ + ../Core/Inc/sys_debug.h ../Core/Inc/sys_conf.h ../Core/Inc/platform.h +../Core/Inc/platform.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wl55xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h: +../Core/Inc/stm32wlxx_hal_conf.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h: +../Core/Inc/main.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_gpio.h: +../Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo_radio.h: +../Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo_errno.h: +../Core/Inc/stm32wlxx_nucleo_conf.h: +../Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo.h: +../Core/Inc/sys_debug.h: +../Core/Inc/sys_conf.h: +../Core/Inc/platform.h: diff --git a/Debug/Core/Src/sys_debug.o b/Debug/Core/Src/sys_debug.o new file mode 100644 index 0000000..a6bd727 Binary files /dev/null and b/Debug/Core/Src/sys_debug.o differ diff --git a/Debug/Core/Src/sys_debug.su b/Debug/Core/Src/sys_debug.su new file mode 100644 index 0000000..c7afbf9 --- /dev/null +++ b/Debug/Core/Src/sys_debug.su @@ -0,0 +1,3 @@ +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h:449:22:LL_AHB2_GRP1_EnableClock 24 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h:336:22:LL_EXTI_EnableIT_32_63 16 static +../Core/Src/sys_debug.c:64:6:DBG_Init 32 static diff --git a/Debug/Core/Src/syscalls.cyclo b/Debug/Core/Src/syscalls.cyclo new file mode 100644 index 0000000..6cbfdd0 --- /dev/null +++ b/Debug/Core/Src/syscalls.cyclo @@ -0,0 +1,18 @@ +../Core/Src/syscalls.c:44:6:initialise_monitor_handles 1 +../Core/Src/syscalls.c:48:5:_getpid 1 +../Core/Src/syscalls.c:53:5:_kill 1 +../Core/Src/syscalls.c:61:6:_exit 1 +../Core/Src/syscalls.c:67:27:_read 2 +../Core/Src/syscalls.c:80:27:_write 2 +../Core/Src/syscalls.c:92:5:_close 1 +../Core/Src/syscalls.c:99:5:_fstat 1 +../Core/Src/syscalls.c:106:5:_isatty 1 +../Core/Src/syscalls.c:112:5:_lseek 1 +../Core/Src/syscalls.c:120:5:_open 1 +../Core/Src/syscalls.c:128:5:_wait 1 +../Core/Src/syscalls.c:135:5:_unlink 1 +../Core/Src/syscalls.c:142:5:_times 1 +../Core/Src/syscalls.c:148:5:_stat 1 +../Core/Src/syscalls.c:155:5:_link 1 +../Core/Src/syscalls.c:163:5:_fork 1 +../Core/Src/syscalls.c:169:5:_execve 1 diff --git a/Debug/Core/Src/syscalls.d b/Debug/Core/Src/syscalls.d new file mode 100644 index 0000000..8667c70 --- /dev/null +++ b/Debug/Core/Src/syscalls.d @@ -0,0 +1 @@ +Core/Src/syscalls.o: ../Core/Src/syscalls.c diff --git a/Debug/Core/Src/syscalls.o b/Debug/Core/Src/syscalls.o new file mode 100644 index 0000000..8446af3 Binary files /dev/null and b/Debug/Core/Src/syscalls.o differ diff --git a/Debug/Core/Src/syscalls.su b/Debug/Core/Src/syscalls.su new file mode 100644 index 0000000..50b547a --- /dev/null +++ b/Debug/Core/Src/syscalls.su @@ -0,0 +1,18 @@ +../Core/Src/syscalls.c:44:6:initialise_monitor_handles 4 static +../Core/Src/syscalls.c:48:5:_getpid 4 static +../Core/Src/syscalls.c:53:5:_kill 16 static +../Core/Src/syscalls.c:61:6:_exit 16 static +../Core/Src/syscalls.c:67:27:_read 32 static +../Core/Src/syscalls.c:80:27:_write 32 static +../Core/Src/syscalls.c:92:5:_close 16 static +../Core/Src/syscalls.c:99:5:_fstat 16 static +../Core/Src/syscalls.c:106:5:_isatty 16 static +../Core/Src/syscalls.c:112:5:_lseek 24 static +../Core/Src/syscalls.c:120:5:_open 12 static +../Core/Src/syscalls.c:128:5:_wait 16 static +../Core/Src/syscalls.c:135:5:_unlink 16 static +../Core/Src/syscalls.c:142:5:_times 16 static +../Core/Src/syscalls.c:148:5:_stat 16 static +../Core/Src/syscalls.c:155:5:_link 16 static +../Core/Src/syscalls.c:163:5:_fork 8 static +../Core/Src/syscalls.c:169:5:_execve 24 static diff --git a/Debug/Core/Src/sysmem.cyclo b/Debug/Core/Src/sysmem.cyclo new file mode 100644 index 0000000..0090c10 --- /dev/null +++ b/Debug/Core/Src/sysmem.cyclo @@ -0,0 +1 @@ +../Core/Src/sysmem.c:53:7:_sbrk 3 diff --git a/Debug/Core/Src/sysmem.d b/Debug/Core/Src/sysmem.d new file mode 100644 index 0000000..74fecf9 --- /dev/null +++ b/Debug/Core/Src/sysmem.d @@ -0,0 +1 @@ +Core/Src/sysmem.o: ../Core/Src/sysmem.c diff --git a/Debug/Core/Src/sysmem.o b/Debug/Core/Src/sysmem.o new file mode 100644 index 0000000..9d498f4 Binary files /dev/null and b/Debug/Core/Src/sysmem.o differ diff --git a/Debug/Core/Src/sysmem.su b/Debug/Core/Src/sysmem.su new file mode 100644 index 0000000..12d5f17 --- /dev/null +++ b/Debug/Core/Src/sysmem.su @@ -0,0 +1 @@ +../Core/Src/sysmem.c:53:7:_sbrk 32 static diff --git a/Debug/Core/Src/system_stm32wlxx.cyclo b/Debug/Core/Src/system_stm32wlxx.cyclo new file mode 100644 index 0000000..ca65f98 --- /dev/null +++ b/Debug/Core/Src/system_stm32wlxx.cyclo @@ -0,0 +1,2 @@ +../Core/Src/system_stm32wlxx.c:211:6:SystemInit 1 +../Core/Src/system_stm32wlxx.c:266:6:SystemCoreClockUpdate 8 diff --git a/Debug/Core/Src/system_stm32wlxx.d b/Debug/Core/Src/system_stm32wlxx.d new file mode 100644 index 0000000..a16f011 --- /dev/null +++ b/Debug/Core/Src/system_stm32wlxx.d @@ -0,0 +1,75 @@ +Core/Src/system_stm32wlxx.o: ../Core/Src/system_stm32wlxx.c \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wl55xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h \ + ../Core/Inc/stm32wlxx_hal_conf.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wl55xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h: +../Core/Inc/stm32wlxx_hal_conf.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h: diff --git a/Debug/Core/Src/system_stm32wlxx.o b/Debug/Core/Src/system_stm32wlxx.o new file mode 100644 index 0000000..8211369 Binary files /dev/null and b/Debug/Core/Src/system_stm32wlxx.o differ diff --git a/Debug/Core/Src/system_stm32wlxx.su b/Debug/Core/Src/system_stm32wlxx.su new file mode 100644 index 0000000..bd11e85 --- /dev/null +++ b/Debug/Core/Src/system_stm32wlxx.su @@ -0,0 +1,2 @@ +../Core/Src/system_stm32wlxx.c:211:6:SystemInit 4 static +../Core/Src/system_stm32wlxx.c:266:6:SystemCoreClockUpdate 32 static diff --git a/Debug/Core/Src/timer_if.cyclo b/Debug/Core/Src/timer_if.cyclo new file mode 100644 index 0000000..db33676 --- /dev/null +++ b/Debug/Core/Src/timer_if.cyclo @@ -0,0 +1,22 @@ +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rtc.h:1528:26:LL_RTC_TIME_GetSubSecond 1 +../Core/Src/timer_if.c:181:21:TIMER_IF_Init 2 +../Core/Src/timer_if.c:218:21:TIMER_IF_StartTimer 2 +../Core/Src/timer_if.c:246:21:TIMER_IF_StopTimer 1 +../Core/Src/timer_if.c:264:10:TIMER_IF_SetTimerContext 1 +../Core/Src/timer_if.c:278:10:TIMER_IF_GetTimerContext 1 +../Core/Src/timer_if.c:289:10:TIMER_IF_GetTimerElapsedTime 1 +../Core/Src/timer_if.c:302:10:TIMER_IF_GetTimerValue 2 +../Core/Src/timer_if.c:318:10:TIMER_IF_GetMinimumTimeout 1 +../Core/Src/timer_if.c:331:10:TIMER_IF_Convert_ms2Tick 1 +../Core/Src/timer_if.c:344:10:TIMER_IF_Convert_Tick2ms 1 +../Core/Src/timer_if.c:357:6:TIMER_IF_DelayMs 2 +../Core/Src/timer_if.c:375:6:HAL_RTC_AlarmAEventCallback 1 +../Core/Src/timer_if.c:386:6:HAL_RTCEx_SSRUEventCallback 1 +../Core/Src/timer_if.c:401:10:TIMER_IF_GetTime 1 +../Core/Src/timer_if.c:425:6:TIMER_IF_BkUp_Write_Seconds 1 +../Core/Src/timer_if.c:436:6:TIMER_IF_BkUp_Write_SubSeconds 1 +../Core/Src/timer_if.c:447:10:TIMER_IF_BkUp_Read_Seconds 1 +../Core/Src/timer_if.c:460:10:TIMER_IF_BkUp_Read_SubSeconds 1 +../Core/Src/timer_if.c:478:13:TIMER_IF_BkUp_Write_MSBticks 1 +../Core/Src/timer_if.c:489:17:TIMER_IF_BkUp_Read_MSBticks 1 +../Core/Src/timer_if.c:502:24:GetTimerTicks 2 diff --git a/Debug/Core/Src/timer_if.d b/Debug/Core/Src/timer_if.d new file mode 100644 index 0000000..0271ac8 --- /dev/null +++ b/Debug/Core/Src/timer_if.d @@ -0,0 +1,94 @@ +Core/Src/timer_if.o: ../Core/Src/timer_if.c ../Core/Inc/timer_if.h \ + ../Utilities/timer/stm32_timer.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h ../Core/Inc/utilities_conf.h \ + ../Utilities/misc/stm32_mem.h ../Utilities/misc/stm32_tiny_vsnprintf.h \ + ../Core/Inc/utilities_def.h ../Utilities/misc/stm32_systime.h \ + ../Core/Inc/main.h ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h \ + ../Core/Inc/stm32wlxx_hal_conf.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wl55xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h \ + ../Core/Inc/rtc.h ../Core/Inc/main.h ../Core/Inc/utilities_def.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rtc.h +../Core/Inc/timer_if.h: +../Utilities/timer/stm32_timer.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Core/Inc/utilities_conf.h: +../Utilities/misc/stm32_mem.h: +../Utilities/misc/stm32_tiny_vsnprintf.h: +../Core/Inc/utilities_def.h: +../Utilities/misc/stm32_systime.h: +../Core/Inc/main.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h: +../Core/Inc/stm32wlxx_hal_conf.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wl55xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h: +../Core/Inc/rtc.h: +../Core/Inc/main.h: +../Core/Inc/utilities_def.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rtc.h: diff --git a/Debug/Core/Src/timer_if.o b/Debug/Core/Src/timer_if.o new file mode 100644 index 0000000..9ffa57c Binary files /dev/null and b/Debug/Core/Src/timer_if.o differ diff --git a/Debug/Core/Src/timer_if.su b/Debug/Core/Src/timer_if.su new file mode 100644 index 0000000..3ce7f32 --- /dev/null +++ b/Debug/Core/Src/timer_if.su @@ -0,0 +1,22 @@ +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rtc.h:1528:26:LL_RTC_TIME_GetSubSecond 16 static +../Core/Src/timer_if.c:181:21:TIMER_IF_Init 16 static +../Core/Src/timer_if.c:218:21:TIMER_IF_StartTimer 64 static +../Core/Src/timer_if.c:246:21:TIMER_IF_StopTimer 16 static +../Core/Src/timer_if.c:264:10:TIMER_IF_SetTimerContext 8 static +../Core/Src/timer_if.c:278:10:TIMER_IF_GetTimerContext 4 static +../Core/Src/timer_if.c:289:10:TIMER_IF_GetTimerElapsedTime 16 static +../Core/Src/timer_if.c:302:10:TIMER_IF_GetTimerValue 16 static +../Core/Src/timer_if.c:318:10:TIMER_IF_GetMinimumTimeout 16 static +../Core/Src/timer_if.c:331:10:TIMER_IF_Convert_ms2Tick 32 static +../Core/Src/timer_if.c:344:10:TIMER_IF_Convert_Tick2ms 48 static +../Core/Src/timer_if.c:357:6:TIMER_IF_DelayMs 24 static,ignoring_inline_asm +../Core/Src/timer_if.c:375:6:HAL_RTC_AlarmAEventCallback 16 static +../Core/Src/timer_if.c:386:6:HAL_RTCEx_SSRUEventCallback 24 static +../Core/Src/timer_if.c:401:10:TIMER_IF_GetTime 80 static +../Core/Src/timer_if.c:425:6:TIMER_IF_BkUp_Write_Seconds 16 static +../Core/Src/timer_if.c:436:6:TIMER_IF_BkUp_Write_SubSeconds 16 static +../Core/Src/timer_if.c:447:10:TIMER_IF_BkUp_Read_Seconds 16 static +../Core/Src/timer_if.c:460:10:TIMER_IF_BkUp_Read_SubSeconds 16 static +../Core/Src/timer_if.c:478:13:TIMER_IF_BkUp_Write_MSBticks 16 static +../Core/Src/timer_if.c:489:17:TIMER_IF_BkUp_Read_MSBticks 16 static +../Core/Src/timer_if.c:502:24:GetTimerTicks 16 static diff --git a/Debug/Core/Src/usart.cyclo b/Debug/Core/Src/usart.cyclo new file mode 100644 index 0000000..8c10c84 --- /dev/null +++ b/Debug/Core/Src/usart.cyclo @@ -0,0 +1,6 @@ +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h:449:22:LL_AHB2_GRP1_EnableClock 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h:914:22:LL_APB1_GRP1_EnableClock 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h:1018:22:LL_APB1_GRP1_DisableClock 1 +../Core/Src/usart.c:32:6:MX_USART2_UART_Init 5 +../Core/Src/usart.c:75:6:HAL_UART_MspInit 5 +../Core/Src/usart.c:142:6:HAL_UART_MspDeInit 2 diff --git a/Debug/Core/Src/usart.d b/Debug/Core/Src/usart.d new file mode 100644 index 0000000..3a9f480 --- /dev/null +++ b/Debug/Core/Src/usart.d @@ -0,0 +1,77 @@ +Core/Src/usart.o: ../Core/Src/usart.c ../Core/Inc/usart.h \ + ../Core/Inc/main.h ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h \ + ../Core/Inc/stm32wlxx_hal_conf.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wl55xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h +../Core/Inc/usart.h: +../Core/Inc/main.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h: +../Core/Inc/stm32wlxx_hal_conf.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wl55xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h: diff --git a/Debug/Core/Src/usart.o b/Debug/Core/Src/usart.o new file mode 100644 index 0000000..9f765bd Binary files /dev/null and b/Debug/Core/Src/usart.o differ diff --git a/Debug/Core/Src/usart.su b/Debug/Core/Src/usart.su new file mode 100644 index 0000000..3876035 --- /dev/null +++ b/Debug/Core/Src/usart.su @@ -0,0 +1,6 @@ +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h:449:22:LL_AHB2_GRP1_EnableClock 24 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h:914:22:LL_APB1_GRP1_EnableClock 24 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h:1018:22:LL_APB1_GRP1_DisableClock 16 static +../Core/Src/usart.c:32:6:MX_USART2_UART_Init 8 static +../Core/Src/usart.c:75:6:HAL_UART_MspInit 96 static +../Core/Src/usart.c:142:6:HAL_UART_MspDeInit 16 static diff --git a/Debug/Core/Src/usart_if.cyclo b/Debug/Core/Src/usart_if.cyclo new file mode 100644 index 0000000..c129200 --- /dev/null +++ b/Debug/Core/Src/usart_if.cyclo @@ -0,0 +1,11 @@ +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h:1062:22:LL_APB1_GRP1_ForceReset 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h:1107:22:LL_APB1_GRP1_ReleaseReset 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h:265:22:LL_EXTI_EnableIT_0_31 1 +../Core/Src/usart_if.c:101:25:vcom_Init 1 +../Core/Src/usart_if.c:116:25:vcom_DeInit 1 +../Core/Src/usart_if.c:139:6:vcom_Trace 1 +../Core/Src/usart_if.c:150:25:vcom_Trace_DMA 1 +../Core/Src/usart_if.c:162:25:vcom_ReceiveInit 3 +../Core/Src/usart_if.c:198:6:vcom_Resume 3 +../Core/Src/usart_if.c:219:6:HAL_UART_TxCpltCallback 2 +../Core/Src/usart_if.c:234:6:HAL_UART_RxCpltCallback 4 diff --git a/Debug/Core/Src/usart_if.d b/Debug/Core/Src/usart_if.d new file mode 100644 index 0000000..e3f5fca --- /dev/null +++ b/Debug/Core/Src/usart_if.d @@ -0,0 +1,90 @@ +Core/Src/usart_if.o: ../Core/Src/usart_if.c ../Core/Inc/usart_if.h \ + ../Utilities/trace/adv_trace/stm32_adv_trace.h \ + ../Core/Inc/utilities_conf.h ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h ../Utilities/misc/stm32_mem.h \ + ../Utilities/misc/stm32_tiny_vsnprintf.h ../Core/Inc/utilities_def.h \ + ../Core/Inc/usart.h ../Core/Inc/main.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h \ + ../Core/Inc/stm32wlxx_hal_conf.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wl55xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h \ + ../Core/Inc/dma.h +../Core/Inc/usart_if.h: +../Utilities/trace/adv_trace/stm32_adv_trace.h: +../Core/Inc/utilities_conf.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Utilities/misc/stm32_mem.h: +../Utilities/misc/stm32_tiny_vsnprintf.h: +../Core/Inc/utilities_def.h: +../Core/Inc/usart.h: +../Core/Inc/main.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h: +../Core/Inc/stm32wlxx_hal_conf.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wl55xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h: +../Core/Inc/dma.h: diff --git a/Debug/Core/Src/usart_if.o b/Debug/Core/Src/usart_if.o new file mode 100644 index 0000000..6d8406e Binary files /dev/null and b/Debug/Core/Src/usart_if.o differ diff --git a/Debug/Core/Src/usart_if.su b/Debug/Core/Src/usart_if.su new file mode 100644 index 0000000..268c307 --- /dev/null +++ b/Debug/Core/Src/usart_if.su @@ -0,0 +1,11 @@ +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h:1062:22:LL_APB1_GRP1_ForceReset 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h:1107:22:LL_APB1_GRP1_ReleaseReset 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h:265:22:LL_EXTI_EnableIT_0_31 16 static +../Core/Src/usart_if.c:101:25:vcom_Init 16 static +../Core/Src/usart_if.c:116:25:vcom_DeInit 8 static +../Core/Src/usart_if.c:139:6:vcom_Trace 16 static +../Core/Src/usart_if.c:150:25:vcom_Trace_DMA 16 static +../Core/Src/usart_if.c:162:25:vcom_ReceiveInit 24 static +../Core/Src/usart_if.c:198:6:vcom_Resume 8 static +../Core/Src/usart_if.c:219:6:HAL_UART_TxCpltCallback 16 static +../Core/Src/usart_if.c:234:6:HAL_UART_RxCpltCallback 16 static diff --git a/Debug/Core/Startup/startup_stm32wl55jcix.d b/Debug/Core/Startup/startup_stm32wl55jcix.d new file mode 100644 index 0000000..10d65ab --- /dev/null +++ b/Debug/Core/Startup/startup_stm32wl55jcix.d @@ -0,0 +1,2 @@ +Core/Startup/startup_stm32wl55jcix.o: \ + ../Core/Startup/startup_stm32wl55jcix.s diff --git a/Debug/Core/Startup/startup_stm32wl55jcix.o b/Debug/Core/Startup/startup_stm32wl55jcix.o new file mode 100644 index 0000000..ef878ea Binary files /dev/null and b/Debug/Core/Startup/startup_stm32wl55jcix.o differ diff --git a/Debug/Core/Startup/subdir.mk b/Debug/Core/Startup/subdir.mk new file mode 100644 index 0000000..96c4aae --- /dev/null +++ b/Debug/Core/Startup/subdir.mk @@ -0,0 +1,27 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (13.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +S_SRCS += \ +../Core/Startup/startup_stm32wl55jcix.s + +OBJS += \ +./Core/Startup/startup_stm32wl55jcix.o + +S_DEPS += \ +./Core/Startup/startup_stm32wl55jcix.d + + +# Each subdirectory must supply rules for building sources it contributes +Core/Startup/%.o: ../Core/Startup/%.s Core/Startup/subdir.mk + arm-none-eabi-gcc -mcpu=cortex-m4 -g3 -DDEBUG -c -x assembler-with-cpp -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" "$<" + +clean: clean-Core-2f-Startup + +clean-Core-2f-Startup: + -$(RM) ./Core/Startup/startup_stm32wl55jcix.d ./Core/Startup/startup_stm32wl55jcix.o + +.PHONY: clean-Core-2f-Startup + diff --git a/Debug/Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo.cyclo b/Debug/Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo.cyclo new file mode 100644 index 0000000..99e9147 --- /dev/null +++ b/Debug/Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo.cyclo @@ -0,0 +1,16 @@ +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h:449:22:LL_AHB2_GRP1_EnableClock 1 +../Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo.c:137:10:BSP_GetVersion 1 +../Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo.c:155:9:BSP_LED_Init 1 +../Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo.c:184:9:BSP_LED_DeInit 1 +../Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo.c:204:9:BSP_LED_On 1 +../Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo.c:220:9:BSP_LED_Off 1 +../Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo.c:236:9:BSP_LED_Toggle 1 +../Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo.c:252:9:BSP_LED_GetState 1 +../Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo.c:279:9:BSP_PB_Init 5 +../Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo.c:327:9:BSP_PB_DeInit 1 +../Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo.c:344:9:BSP_PB_GetState 1 +../Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo.c:354:6:BSP_PB_IRQHandler 1 +../Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo.c:368:13:BSP_PB_Callback 1 +../Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo.c:619:13:BUTTON_SW1_EXTI_Callback 1 +../Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo.c:628:13:BUTTON_SW2_EXTI_Callback 1 +../Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo.c:637:13:BUTTON_SW3_EXTI_Callback 1 diff --git a/Debug/Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo.d b/Debug/Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo.d new file mode 100644 index 0000000..f31fe0c --- /dev/null +++ b/Debug/Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo.d @@ -0,0 +1,82 @@ +Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo.o: \ + ../Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo.c \ + ../Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo.h \ + ../Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo_errno.h \ + ../Core/Inc/stm32wlxx_nucleo_conf.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h \ + ../Core/Inc/stm32wlxx_hal_conf.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wl55xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h +../Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo.h: +../Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo_errno.h: +../Core/Inc/stm32wlxx_nucleo_conf.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h: +../Core/Inc/stm32wlxx_hal_conf.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wl55xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h: diff --git a/Debug/Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo.o b/Debug/Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo.o new file mode 100644 index 0000000..f01f598 Binary files /dev/null and b/Debug/Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo.o differ diff --git a/Debug/Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo.su b/Debug/Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo.su new file mode 100644 index 0000000..060fec9 --- /dev/null +++ b/Debug/Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo.su @@ -0,0 +1,16 @@ +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h:449:22:LL_AHB2_GRP1_EnableClock 24 static +../Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo.c:137:10:BSP_GetVersion 4 static +../Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo.c:155:9:BSP_LED_Init 40 static +../Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo.c:184:9:BSP_LED_DeInit 16 static +../Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo.c:204:9:BSP_LED_On 16 static +../Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo.c:220:9:BSP_LED_Off 16 static +../Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo.c:236:9:BSP_LED_Toggle 16 static +../Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo.c:252:9:BSP_LED_GetState 16 static +../Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo.c:279:9:BSP_PB_Init 40 static +../Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo.c:327:9:BSP_PB_DeInit 16 static +../Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo.c:344:9:BSP_PB_GetState 16 static +../Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo.c:354:6:BSP_PB_IRQHandler 16 static +../Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo.c:368:13:BSP_PB_Callback 16 static +../Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo.c:619:13:BUTTON_SW1_EXTI_Callback 8 static +../Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo.c:628:13:BUTTON_SW2_EXTI_Callback 8 static +../Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo.c:637:13:BUTTON_SW3_EXTI_Callback 8 static diff --git a/Debug/Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo_radio.cyclo b/Debug/Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo_radio.cyclo new file mode 100644 index 0000000..939e800 --- /dev/null +++ b/Debug/Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo_radio.cyclo @@ -0,0 +1,8 @@ +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h:449:22:LL_AHB2_GRP1_EnableClock 1 +../Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo_radio.c:46:9:BSP_RADIO_Init 1 +../Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo_radio.c:78:9:BSP_RADIO_DeInit 1 +../Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo_radio.c:105:9:BSP_RADIO_ConfigRFSwitch 5 +../Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo_radio.c:155:9:BSP_RADIO_GetTxConfig 1 +../Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo_radio.c:167:9:BSP_RADIO_IsTCXO 1 +../Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo_radio.c:179:9:BSP_RADIO_IsDCDC 1 +../Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo_radio.c:190:9:BSP_RADIO_GetRFOMaxPowerConfig 2 diff --git a/Debug/Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo_radio.d b/Debug/Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo_radio.d new file mode 100644 index 0000000..0257f1c --- /dev/null +++ b/Debug/Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo_radio.d @@ -0,0 +1,82 @@ +Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo_radio.o: \ + ../Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo_radio.c \ + ../Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo_radio.h \ + ../Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo_errno.h \ + ../Core/Inc/stm32wlxx_nucleo_conf.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h \ + ../Core/Inc/stm32wlxx_hal_conf.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wl55xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h +../Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo_radio.h: +../Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo_errno.h: +../Core/Inc/stm32wlxx_nucleo_conf.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h: +../Core/Inc/stm32wlxx_hal_conf.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wl55xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h: diff --git a/Debug/Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo_radio.o b/Debug/Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo_radio.o new file mode 100644 index 0000000..f1c2322 Binary files /dev/null and b/Debug/Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo_radio.o differ diff --git a/Debug/Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo_radio.su b/Debug/Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo_radio.su new file mode 100644 index 0000000..0de8577 --- /dev/null +++ b/Debug/Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo_radio.su @@ -0,0 +1,8 @@ +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h:449:22:LL_AHB2_GRP1_EnableClock 24 static +../Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo_radio.c:46:9:BSP_RADIO_Init 32 static +../Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo_radio.c:78:9:BSP_RADIO_DeInit 8 static +../Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo_radio.c:105:9:BSP_RADIO_ConfigRFSwitch 16 static +../Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo_radio.c:155:9:BSP_RADIO_GetTxConfig 4 static +../Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo_radio.c:167:9:BSP_RADIO_IsTCXO 4 static +../Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo_radio.c:179:9:BSP_RADIO_IsDCDC 4 static +../Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo_radio.c:190:9:BSP_RADIO_GetRFOMaxPowerConfig 24 static diff --git a/Debug/Drivers/BSP/STM32WLxx_Nucleo/subdir.mk b/Debug/Drivers/BSP/STM32WLxx_Nucleo/subdir.mk new file mode 100644 index 0000000..92ad9c6 --- /dev/null +++ b/Debug/Drivers/BSP/STM32WLxx_Nucleo/subdir.mk @@ -0,0 +1,30 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (13.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo.c \ +../Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo_radio.c + +OBJS += \ +./Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo.o \ +./Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo_radio.o + +C_DEPS += \ +./Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo.d \ +./Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo_radio.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/BSP/STM32WLxx_Nucleo/%.o Drivers/BSP/STM32WLxx_Nucleo/%.su Drivers/BSP/STM32WLxx_Nucleo/%.cyclo: ../Drivers/BSP/STM32WLxx_Nucleo/%.c Drivers/BSP/STM32WLxx_Nucleo/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WL55xx -c -I../Core/Inc -I../SubGHz_Phy/App -I../SubGHz_Phy/Target -I../Utilities/trace/adv_trace -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Utilities/misc -I../Utilities/sequencer -I../Utilities/timer -I../Utilities/lpm/tiny_lpm -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Middlewares/Third_Party/SubGHz_Phy -I../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver -I../Drivers/CMSIS/Include -I../Drivers/BSP/STM32WLxx_Nucleo -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Drivers-2f-BSP-2f-STM32WLxx_Nucleo + +clean-Drivers-2f-BSP-2f-STM32WLxx_Nucleo: + -$(RM) ./Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo.cyclo ./Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo.d ./Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo.o ./Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo.su ./Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo_radio.cyclo ./Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo_radio.d ./Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo_radio.o ./Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo_radio.su + +.PHONY: clean-Drivers-2f-BSP-2f-STM32WLxx_Nucleo + diff --git a/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.cyclo b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.cyclo new file mode 100644 index 0000000..24a0aea --- /dev/null +++ b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.cyclo @@ -0,0 +1,69 @@ +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h:346:22:LL_AHB1_GRP1_ForceReset 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h:365:22:LL_AHB1_GRP1_ReleaseReset 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h:508:22:LL_AHB2_GRP1_ForceReset 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h:527:22:LL_AHB2_GRP1_ReleaseReset 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h:763:22:LL_AHB3_GRP1_ForceReset 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h:806:22:LL_AHB3_GRP1_ReleaseReset 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h:1062:22:LL_APB1_GRP1_ForceReset 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h:1079:22:LL_APB1_GRP2_ForceReset 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h:1107:22:LL_APB1_GRP1_ReleaseReset 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h:1124:22:LL_APB1_GRP2_ReleaseReset 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h:1374:22:LL_APB2_GRP1_ForceReset 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h:1397:22:LL_APB2_GRP1_ReleaseReset 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h:1529:22:LL_APB3_GRP1_ForceReset 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h:1541:22:LL_APB3_GRP1_ReleaseReset 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h:460:22:LL_SYSCFG_EnableAnalogBooster 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h:479:22:LL_SYSCFG_DisableAnalogBooster 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h:605:22:LL_SYSCFG_EnableSRAM2Erase 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h:748:22:LL_SYSCFG_UnlockSRAM2WRP 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h:777:22:LL_SYSCFG_GRP1_EnableIT 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h:791:22:LL_SYSCFG_GRP2_EnableIT 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h:817:22:LL_SYSCFG_GRP1_DisableIT 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h:831:22:LL_SYSCFG_GRP2_DisableIT 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h:1162:26:LL_DBGMCU_GetDeviceID 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h:1173:26:LL_DBGMCU_GetRevisionID 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h:1183:22:LL_DBGMCU_EnableDBGSleepMode 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h:1193:22:LL_DBGMCU_DisableDBGSleepMode 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h:1205:22:LL_DBGMCU_EnableDBGStopMode 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h:1215:22:LL_DBGMCU_DisableDBGStopMode 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h:1227:22:LL_DBGMCU_EnableDBGStandbyMode 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h:1237:22:LL_DBGMCU_DisableDBGStandbyMode 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h:1451:22:LL_VREFBUF_Enable 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h:1461:22:LL_VREFBUF_Disable 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h:1494:22:LL_VREFBUF_SetVoltageScaling 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h:1560:22:LL_VREFBUF_SetTrimming 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:152:19:HAL_Init 2 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:208:19:HAL_DeInit 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:240:13:HAL_MspInit 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:251:13:HAL_MspDeInit 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:274:26:HAL_InitTick 4 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:347:13:HAL_IncTick 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:358:17:HAL_GetTick 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:367:10:HAL_GetTickPrio 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:376:19:HAL_SetTickFreq 3 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:408:21:HAL_GetTickFreq 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:424:13:HAL_Delay 3 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:451:13:HAL_SuspendTick 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:467:13:HAL_ResumeTick 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:477:10:HAL_GetHalVersion 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:488:10:HAL_GetREVID 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:497:10:HAL_GetDEVID 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:507:10:HAL_GetUIDw0 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:516:10:HAL_GetUIDw1 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:525:10:HAL_GetUIDw2 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:556:6:HAL_DBGMCU_EnableDBGSleepMode 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:565:6:HAL_DBGMCU_DisableDBGSleepMode 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:576:6:HAL_DBGMCU_EnableDBGStopMode 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:585:6:HAL_DBGMCU_DisableDBGStopMode 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:596:6:HAL_DBGMCU_EnableDBGStandbyMode 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:605:6:HAL_DBGMCU_DisableDBGStandbyMode 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:638:6:HAL_SYSCFG_SRAM2Erase 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:658:6:HAL_SYSCFG_VREFBUF_VoltageScalingConfig 2 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:689:6:HAL_SYSCFG_VREFBUF_HighImpedanceConfig 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:710:6:HAL_SYSCFG_VREFBUF_TrimmingConfig 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:723:19:HAL_SYSCFG_EnableVREFBUF 3 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:749:6:HAL_SYSCFG_DisableVREFBUF 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:759:6:HAL_SYSCFG_EnableIOAnalogSwitchBooster 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:769:6:HAL_SYSCFG_DisableIOAnalogSwitchBooster 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:783:6:HAL_SYSCFG_EnableIT 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:809:6:HAL_SYSCFG_DisableIT 1 diff --git a/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.d b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.d new file mode 100644 index 0000000..ed24a38 --- /dev/null +++ b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.d @@ -0,0 +1,76 @@ +Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.o: \ + ../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h \ + ../Core/Inc/stm32wlxx_hal_conf.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wl55xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h: +../Core/Inc/stm32wlxx_hal_conf.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wl55xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h: diff --git a/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.o b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.o new file mode 100644 index 0000000..17fb9f3 Binary files /dev/null and b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.o differ diff --git a/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.su b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.su new file mode 100644 index 0000000..3f505f8 --- /dev/null +++ b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.su @@ -0,0 +1,69 @@ +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h:346:22:LL_AHB1_GRP1_ForceReset 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h:365:22:LL_AHB1_GRP1_ReleaseReset 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h:508:22:LL_AHB2_GRP1_ForceReset 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h:527:22:LL_AHB2_GRP1_ReleaseReset 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h:763:22:LL_AHB3_GRP1_ForceReset 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h:806:22:LL_AHB3_GRP1_ReleaseReset 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h:1062:22:LL_APB1_GRP1_ForceReset 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h:1079:22:LL_APB1_GRP2_ForceReset 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h:1107:22:LL_APB1_GRP1_ReleaseReset 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h:1124:22:LL_APB1_GRP2_ReleaseReset 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h:1374:22:LL_APB2_GRP1_ForceReset 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h:1397:22:LL_APB2_GRP1_ReleaseReset 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h:1529:22:LL_APB3_GRP1_ForceReset 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h:1541:22:LL_APB3_GRP1_ReleaseReset 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h:460:22:LL_SYSCFG_EnableAnalogBooster 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h:479:22:LL_SYSCFG_DisableAnalogBooster 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h:605:22:LL_SYSCFG_EnableSRAM2Erase 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h:748:22:LL_SYSCFG_UnlockSRAM2WRP 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h:777:22:LL_SYSCFG_GRP1_EnableIT 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h:791:22:LL_SYSCFG_GRP2_EnableIT 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h:817:22:LL_SYSCFG_GRP1_DisableIT 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h:831:22:LL_SYSCFG_GRP2_DisableIT 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h:1162:26:LL_DBGMCU_GetDeviceID 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h:1173:26:LL_DBGMCU_GetRevisionID 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h:1183:22:LL_DBGMCU_EnableDBGSleepMode 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h:1193:22:LL_DBGMCU_DisableDBGSleepMode 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h:1205:22:LL_DBGMCU_EnableDBGStopMode 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h:1215:22:LL_DBGMCU_DisableDBGStopMode 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h:1227:22:LL_DBGMCU_EnableDBGStandbyMode 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h:1237:22:LL_DBGMCU_DisableDBGStandbyMode 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h:1451:22:LL_VREFBUF_Enable 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h:1461:22:LL_VREFBUF_Disable 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h:1494:22:LL_VREFBUF_SetVoltageScaling 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h:1560:22:LL_VREFBUF_SetTrimming 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:152:19:HAL_Init 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:208:19:HAL_DeInit 8 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:240:13:HAL_MspInit 4 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:251:13:HAL_MspDeInit 4 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:274:26:HAL_InitTick 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:347:13:HAL_IncTick 4 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:358:17:HAL_GetTick 4 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:367:10:HAL_GetTickPrio 4 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:376:19:HAL_SetTickFreq 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:408:21:HAL_GetTickFreq 4 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:424:13:HAL_Delay 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:451:13:HAL_SuspendTick 4 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:467:13:HAL_ResumeTick 4 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:477:10:HAL_GetHalVersion 4 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:488:10:HAL_GetREVID 8 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:497:10:HAL_GetDEVID 8 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:507:10:HAL_GetUIDw0 4 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:516:10:HAL_GetUIDw1 4 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:525:10:HAL_GetUIDw2 4 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:556:6:HAL_DBGMCU_EnableDBGSleepMode 8 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:565:6:HAL_DBGMCU_DisableDBGSleepMode 8 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:576:6:HAL_DBGMCU_EnableDBGStopMode 8 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:585:6:HAL_DBGMCU_DisableDBGStopMode 8 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:596:6:HAL_DBGMCU_EnableDBGStandbyMode 8 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:605:6:HAL_DBGMCU_DisableDBGStandbyMode 8 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:638:6:HAL_SYSCFG_SRAM2Erase 8 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:658:6:HAL_SYSCFG_VREFBUF_VoltageScalingConfig 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:689:6:HAL_SYSCFG_VREFBUF_HighImpedanceConfig 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:710:6:HAL_SYSCFG_VREFBUF_TrimmingConfig 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:723:19:HAL_SYSCFG_EnableVREFBUF 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:749:6:HAL_SYSCFG_DisableVREFBUF 8 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:759:6:HAL_SYSCFG_EnableIOAnalogSwitchBooster 8 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:769:6:HAL_SYSCFG_DisableIOAnalogSwitchBooster 8 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:783:6:HAL_SYSCFG_EnableIT 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:809:6:HAL_SYSCFG_DisableIT 24 static diff --git a/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.cyclo b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.cyclo new file mode 100644 index 0000000..4cdb773 --- /dev/null +++ b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.cyclo @@ -0,0 +1,34 @@ +../Drivers/CMSIS/Include/core_cm4.h:1648:22:__NVIC_SetPriorityGrouping 1 +../Drivers/CMSIS/Include/core_cm4.h:1667:26:__NVIC_GetPriorityGrouping 1 +../Drivers/CMSIS/Include/core_cm4.h:1679:22:__NVIC_EnableIRQ 2 +../Drivers/CMSIS/Include/core_cm4.h:1717:22:__NVIC_DisableIRQ 2 +../Drivers/CMSIS/Include/core_cm4.h:1736:26:__NVIC_GetPendingIRQ 2 +../Drivers/CMSIS/Include/core_cm4.h:1755:22:__NVIC_SetPendingIRQ 2 +../Drivers/CMSIS/Include/core_cm4.h:1770:22:__NVIC_ClearPendingIRQ 2 +../Drivers/CMSIS/Include/core_cm4.h:1787:26:__NVIC_GetActive 2 +../Drivers/CMSIS/Include/core_cm4.h:1809:22:__NVIC_SetPriority 2 +../Drivers/CMSIS/Include/core_cm4.h:1831:26:__NVIC_GetPriority 2 +../Drivers/CMSIS/Include/core_cm4.h:1856:26:NVIC_EncodePriority 2 +../Drivers/CMSIS/Include/core_cm4.h:1883:22:NVIC_DecodePriority 2 +../Drivers/CMSIS/Include/core_cm4.h:1933:34:__NVIC_SystemReset 1 +../Drivers/CMSIS/Include/core_cm4.h:2017:26:SysTick_Config 2 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.c:184:6:HAL_NVIC_SetPriorityGrouping 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.c:207:6:HAL_NVIC_SetPriority 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.c:231:6:HAL_NVIC_EnableIRQ 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.c:248:6:HAL_NVIC_DisableIRQ 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.c:261:6:HAL_NVIC_SystemReset 0 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.c:274:10:HAL_SYSTICK_Config 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.c:318:10:HAL_NVIC_GetPriorityGrouping 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.c:346:6:HAL_NVIC_GetPriority 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.c:363:10:HAL_NVIC_GetActive 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.c:379:6:HAL_NVIC_SetPendingIRQ 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.c:398:10:HAL_NVIC_GetPendingIRQ 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.c:415:6:HAL_NVIC_ClearPendingIRQ 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.c:432:6:HAL_SYSTICK_CLKSourceConfig 2 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.c:450:6:HAL_SYSTICK_IRQHandler 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.c:459:13:HAL_SYSTICK_Callback 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.c:479:6:HAL_MPU_Enable 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.c:494:6:HAL_MPU_Disable 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.c:507:6:HAL_MPU_EnableRegion 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.c:523:6:HAL_MPU_DisableRegion 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.c:541:6:HAL_MPU_ConfigRegion 1 diff --git a/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.d b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.d new file mode 100644 index 0000000..08e4bc5 --- /dev/null +++ b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.d @@ -0,0 +1,76 @@ +Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.o: \ + ../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.c \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h \ + ../Core/Inc/stm32wlxx_hal_conf.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wl55xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h: +../Core/Inc/stm32wlxx_hal_conf.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wl55xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h: diff --git a/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.o b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.o new file mode 100644 index 0000000..7a605cc Binary files /dev/null and b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.o differ diff --git a/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.su b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.su new file mode 100644 index 0000000..3743400 --- /dev/null +++ b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.su @@ -0,0 +1,34 @@ +../Drivers/CMSIS/Include/core_cm4.h:1648:22:__NVIC_SetPriorityGrouping 24 static +../Drivers/CMSIS/Include/core_cm4.h:1667:26:__NVIC_GetPriorityGrouping 4 static +../Drivers/CMSIS/Include/core_cm4.h:1679:22:__NVIC_EnableIRQ 16 static,ignoring_inline_asm +../Drivers/CMSIS/Include/core_cm4.h:1717:22:__NVIC_DisableIRQ 16 static,ignoring_inline_asm +../Drivers/CMSIS/Include/core_cm4.h:1736:26:__NVIC_GetPendingIRQ 16 static +../Drivers/CMSIS/Include/core_cm4.h:1755:22:__NVIC_SetPendingIRQ 16 static +../Drivers/CMSIS/Include/core_cm4.h:1770:22:__NVIC_ClearPendingIRQ 16 static +../Drivers/CMSIS/Include/core_cm4.h:1787:26:__NVIC_GetActive 16 static +../Drivers/CMSIS/Include/core_cm4.h:1809:22:__NVIC_SetPriority 16 static +../Drivers/CMSIS/Include/core_cm4.h:1831:26:__NVIC_GetPriority 16 static +../Drivers/CMSIS/Include/core_cm4.h:1856:26:NVIC_EncodePriority 40 static +../Drivers/CMSIS/Include/core_cm4.h:1883:22:NVIC_DecodePriority 40 static +../Drivers/CMSIS/Include/core_cm4.h:1933:34:__NVIC_SystemReset 4 static,ignoring_inline_asm +../Drivers/CMSIS/Include/core_cm4.h:2017:26:SysTick_Config 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.c:184:6:HAL_NVIC_SetPriorityGrouping 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.c:207:6:HAL_NVIC_SetPriority 32 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.c:231:6:HAL_NVIC_EnableIRQ 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.c:248:6:HAL_NVIC_DisableIRQ 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.c:261:6:HAL_NVIC_SystemReset 8 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.c:274:10:HAL_SYSTICK_Config 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.c:318:10:HAL_NVIC_GetPriorityGrouping 8 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.c:346:6:HAL_NVIC_GetPriority 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.c:363:10:HAL_NVIC_GetActive 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.c:379:6:HAL_NVIC_SetPendingIRQ 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.c:398:10:HAL_NVIC_GetPendingIRQ 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.c:415:6:HAL_NVIC_ClearPendingIRQ 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.c:432:6:HAL_SYSTICK_CLKSourceConfig 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.c:450:6:HAL_SYSTICK_IRQHandler 8 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.c:459:13:HAL_SYSTICK_Callback 4 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.c:479:6:HAL_MPU_Enable 16 static,ignoring_inline_asm +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.c:494:6:HAL_MPU_Disable 4 static,ignoring_inline_asm +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.c:507:6:HAL_MPU_EnableRegion 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.c:523:6:HAL_MPU_DisableRegion 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.c:541:6:HAL_MPU_ConfigRegion 16 static diff --git a/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.cyclo b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.cyclo new file mode 100644 index 0000000..ed51626 --- /dev/null +++ b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.cyclo @@ -0,0 +1,17 @@ +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.c:153:19:HAL_DMA_Init 6 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.c:256:19:HAL_DMA_DeInit 5 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.c:371:19:HAL_DMA_Start 3 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.c:422:19:HAL_DMA_Start_IT 6 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.c:496:19:HAL_DMA_Abort 4 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.c:557:19:HAL_DMA_Abort_IT 4 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.c:618:19:HAL_DMA_PollForTransfer 13 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.c:747:6:HAL_DMA_IRQHandler 13 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.c:841:19:HAL_DMA_RegisterCallback 7 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.c:892:19:HAL_DMA_UnRegisterCallback 8 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.c:969:22:HAL_DMA_GetState 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.c:981:10:HAL_DMA_GetError 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.c:1025:19:HAL_DMA_ConfigChannelAttributes 4 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.c:1153:19:HAL_DMA_GetConfigChannelAttributes 5 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.c:1211:13:DMA_SetConfig 3 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.c:1254:13:DMA_CalcDMAMUXChannelBaseAndMask 2 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.c:1292:13:DMA_CalcDMAMUXRequestGenBaseAndMask 1 diff --git a/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.d b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.d new file mode 100644 index 0000000..158bd4b --- /dev/null +++ b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.d @@ -0,0 +1,76 @@ +Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.o: \ + ../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.c \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h \ + ../Core/Inc/stm32wlxx_hal_conf.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wl55xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h: +../Core/Inc/stm32wlxx_hal_conf.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wl55xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h: diff --git a/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.o b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.o new file mode 100644 index 0000000..6ef4d17 Binary files /dev/null and b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.o differ diff --git a/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.su b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.su new file mode 100644 index 0000000..18bc111 --- /dev/null +++ b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.su @@ -0,0 +1,17 @@ +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.c:153:19:HAL_DMA_Init 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.c:256:19:HAL_DMA_DeInit 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.c:371:19:HAL_DMA_Start 32 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.c:422:19:HAL_DMA_Start_IT 32 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.c:496:19:HAL_DMA_Abort 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.c:557:19:HAL_DMA_Abort_IT 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.c:618:19:HAL_DMA_PollForTransfer 32 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.c:747:6:HAL_DMA_IRQHandler 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.c:841:19:HAL_DMA_RegisterCallback 32 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.c:892:19:HAL_DMA_UnRegisterCallback 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.c:969:22:HAL_DMA_GetState 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.c:981:10:HAL_DMA_GetError 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.c:1025:19:HAL_DMA_ConfigChannelAttributes 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.c:1153:19:HAL_DMA_GetConfigChannelAttributes 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.c:1211:13:DMA_SetConfig 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.c:1254:13:DMA_CalcDMAMUXChannelBaseAndMask 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.c:1292:13:DMA_CalcDMAMUXRequestGenBaseAndMask 24 static diff --git a/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma_ex.cyclo b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma_ex.cyclo new file mode 100644 index 0000000..f7afa3e --- /dev/null +++ b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma_ex.cyclo @@ -0,0 +1,5 @@ +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma_ex.c:95:19:HAL_DMAEx_ConfigMuxSync 3 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma_ex.c:144:19:HAL_DMAEx_ConfigMuxRequestGenerator 5 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma_ex.c:203:19:HAL_DMAEx_EnableMuxRequestGenerator 3 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma_ex.c:231:19:HAL_DMAEx_DisableMuxRequestGenerator 3 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma_ex.c:259:6:HAL_DMAEx_MUX_IRQHandler 6 diff --git a/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma_ex.d b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma_ex.d new file mode 100644 index 0000000..57e4538 --- /dev/null +++ b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma_ex.d @@ -0,0 +1,76 @@ +Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma_ex.o: \ + ../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma_ex.c \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h \ + ../Core/Inc/stm32wlxx_hal_conf.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wl55xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h: +../Core/Inc/stm32wlxx_hal_conf.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wl55xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h: diff --git a/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma_ex.o b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma_ex.o new file mode 100644 index 0000000..d3bf22a Binary files /dev/null and b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma_ex.o differ diff --git a/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma_ex.su b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma_ex.su new file mode 100644 index 0000000..0517c80 --- /dev/null +++ b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma_ex.su @@ -0,0 +1,5 @@ +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma_ex.c:95:19:HAL_DMAEx_ConfigMuxSync 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma_ex.c:144:19:HAL_DMAEx_ConfigMuxRequestGenerator 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma_ex.c:203:19:HAL_DMAEx_EnableMuxRequestGenerator 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma_ex.c:231:19:HAL_DMAEx_DisableMuxRequestGenerator 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma_ex.c:259:6:HAL_DMAEx_MUX_IRQHandler 16 static diff --git a/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_exti.cyclo b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_exti.cyclo new file mode 100644 index 0000000..b1bab83 --- /dev/null +++ b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_exti.cyclo @@ -0,0 +1,9 @@ +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_exti.c:143:19:HAL_EXTI_SetConfigLine 9 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_exti.c:275:19:HAL_EXTI_GetConfigLine 9 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_exti.c:375:19:HAL_EXTI_ClearConfigLine 4 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_exti.c:447:19:HAL_EXTI_RegisterCallback 2 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_exti.c:473:19:HAL_EXTI_GetHandle 2 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_exti.c:514:6:HAL_EXTI_IRQHandler 3 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_exti.c:552:10:HAL_EXTI_GetPending 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_exti.c:588:6:HAL_EXTI_ClearPending 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_exti.c:615:6:HAL_EXTI_GenerateSWI 1 diff --git a/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_exti.d b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_exti.d new file mode 100644 index 0000000..266a0dd --- /dev/null +++ b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_exti.d @@ -0,0 +1,76 @@ +Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_exti.o: \ + ../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_exti.c \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h \ + ../Core/Inc/stm32wlxx_hal_conf.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wl55xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h: +../Core/Inc/stm32wlxx_hal_conf.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wl55xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h: diff --git a/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_exti.o b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_exti.o new file mode 100644 index 0000000..a2fa272 Binary files /dev/null and b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_exti.o differ diff --git a/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_exti.su b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_exti.su new file mode 100644 index 0000000..7a316b3 --- /dev/null +++ b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_exti.su @@ -0,0 +1,9 @@ +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_exti.c:143:19:HAL_EXTI_SetConfigLine 40 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_exti.c:275:19:HAL_EXTI_GetConfigLine 40 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_exti.c:375:19:HAL_EXTI_ClearConfigLine 40 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_exti.c:447:19:HAL_EXTI_RegisterCallback 32 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_exti.c:473:19:HAL_EXTI_GetHandle 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_exti.c:514:6:HAL_EXTI_IRQHandler 32 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_exti.c:552:10:HAL_EXTI_GetPending 40 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_exti.c:588:6:HAL_EXTI_ClearPending 32 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_exti.c:615:6:HAL_EXTI_GenerateSWI 32 static diff --git a/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash.cyclo b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash.cyclo new file mode 100644 index 0000000..60a115e --- /dev/null +++ b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash.cyclo @@ -0,0 +1,14 @@ +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash.c:178:19:HAL_FLASH_Program 4 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash.c:246:19:HAL_FLASH_Program_IT 4 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash.c:304:6:HAL_FLASH_IRQHandler 10 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash.c:409:13:HAL_FLASH_EndOfOperationCallback 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash.c:427:13:HAL_FLASH_OperationErrorCallback 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash.c:460:19:HAL_FLASH_Unlock 3 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash.c:484:19:HAL_FLASH_Lock 2 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash.c:505:19:HAL_FLASH_OB_Unlock 3 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash.c:530:19:HAL_FLASH_OB_Lock 2 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash.c:551:19:HAL_FLASH_OB_Launch 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash.c:595:10:HAL_FLASH_GetError 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash.c:619:19:FLASH_WaitForLastOperation 9 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash.c:682:13:FLASH_Program_DoubleWord 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash.c:712:13:FLASH_Program_Fast 3 diff --git a/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash.d b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash.d new file mode 100644 index 0000000..2f2330c --- /dev/null +++ b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash.d @@ -0,0 +1,76 @@ +Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash.o: \ + ../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash.c \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h \ + ../Core/Inc/stm32wlxx_hal_conf.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wl55xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h: +../Core/Inc/stm32wlxx_hal_conf.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wl55xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h: diff --git a/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash.o b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash.o new file mode 100644 index 0000000..000c469 Binary files /dev/null and b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash.o differ diff --git a/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash.su b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash.su new file mode 100644 index 0000000..561b88a --- /dev/null +++ b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash.su @@ -0,0 +1,14 @@ +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash.c:178:19:HAL_FLASH_Program 32 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash.c:246:19:HAL_FLASH_Program_IT 32 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash.c:304:6:HAL_FLASH_IRQHandler 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash.c:409:13:HAL_FLASH_EndOfOperationCallback 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash.c:427:13:HAL_FLASH_OperationErrorCallback 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash.c:460:19:HAL_FLASH_Unlock 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash.c:484:19:HAL_FLASH_Lock 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash.c:505:19:HAL_FLASH_OB_Unlock 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash.c:530:19:HAL_FLASH_OB_Lock 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash.c:551:19:HAL_FLASH_OB_Launch 4 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash.c:595:10:HAL_FLASH_GetError 4 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash.c:619:19:FLASH_WaitForLastOperation 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash.c:682:13:FLASH_Program_DoubleWord 24 static,ignoring_inline_asm +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash.c:712:13:FLASH_Program_Fast 40 static,ignoring_inline_asm diff --git a/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.cyclo b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.cyclo new file mode 100644 index 0000000..d2deb8e --- /dev/null +++ b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.cyclo @@ -0,0 +1,36 @@ +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c:180:19:HAL_FLASHEx_Erase 6 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c:252:19:HAL_FLASHEx_Erase_IT 4 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c:316:19:HAL_FLASHEx_OBProgram 11 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c:420:6:HAL_FLASHEx_OBGetConfig 3 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c:469:10:HAL_FLASHEx_FlashEmptyCheck 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c:486:6:HAL_FLASHEx_ForceFlashEmpty 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c:502:6:HAL_FLASHEx_SuspendOperation 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c:520:6:HAL_FLASHEx_AllowOperation 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c:540:10:HAL_FLASHEx_IsOperationSuspended 2 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c:564:6:HAL_FLASHEx_DisableC2Debug 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c:576:6:HAL_FLASHEx_EnableC2Debug 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c:587:6:HAL_FLASHEx_EnableSecHideProtection 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c:601:6:HAL_FLASHEx_ConfigPrivMode 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c:617:10:HAL_FLASHEx_GetPrivMode 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c:640:13:FLASH_MassErase 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c:656:6:FLASH_PageErase 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c:673:6:FLASH_FlushCaches 3 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c:705:13:FLASH_AcknowledgePageErase 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c:737:13:FLASH_OB_WRPConfig 2 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c:829:13:FLASH_OB_OptrConfig 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c:859:13:FLASH_OB_PCROP1AConfig 3 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c:910:13:FLASH_OB_PCROP1BConfig 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c:941:13:FLASH_OB_IPCCBufferAddrConfig 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c:958:13:FLASH_OB_SecureConfig 8 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c:1067:13:FLASH_OB_GetWRP 2 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c:1093:17:FLASH_OB_GetRDP 3 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c:1147:17:FLASH_OB_GetUser 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c:1168:13:FLASH_OB_GetPCROP 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c:1196:17:FLASH_OB_GetIPCCBufferAddr 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c:1222:13:FLASH_OB_GetSecureMemoryConfig 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c:1263:13:FLASH_OB_GetC2BootResetConfig 2 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c:1283:17:FLASH_OB_GetSUBGHZSPISecureAccess 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c:1294:17:FLASH_OB_GetC2DebugAccessMode 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c:1304:26:FLASH_OB_ProceedWriteOperation 2 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c:1332:13:FLASH_OB_ConfigSecureMode 2 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c:1357:17:FLASH_OB_GetSecureMode 2 diff --git a/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.d b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.d new file mode 100644 index 0000000..01cca29 --- /dev/null +++ b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.d @@ -0,0 +1,76 @@ +Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.o: \ + ../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h \ + ../Core/Inc/stm32wlxx_hal_conf.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wl55xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h: +../Core/Inc/stm32wlxx_hal_conf.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wl55xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h: diff --git a/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.o b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.o new file mode 100644 index 0000000..1346927 Binary files /dev/null and b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.o differ diff --git a/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.su b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.su new file mode 100644 index 0000000..599d559 --- /dev/null +++ b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.su @@ -0,0 +1,36 @@ +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c:180:19:HAL_FLASHEx_Erase 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c:252:19:HAL_FLASHEx_Erase_IT 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c:316:19:HAL_FLASHEx_OBProgram 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c:420:6:HAL_FLASHEx_OBGetConfig 32 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c:469:10:HAL_FLASHEx_FlashEmptyCheck 4 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c:486:6:HAL_FLASHEx_ForceFlashEmpty 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c:502:6:HAL_FLASHEx_SuspendOperation 4 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c:520:6:HAL_FLASHEx_AllowOperation 4 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c:540:10:HAL_FLASHEx_IsOperationSuspended 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c:564:6:HAL_FLASHEx_DisableC2Debug 4 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c:576:6:HAL_FLASHEx_EnableC2Debug 4 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c:587:6:HAL_FLASHEx_EnableSecHideProtection 4 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c:601:6:HAL_FLASHEx_ConfigPrivMode 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c:617:10:HAL_FLASHEx_GetPrivMode 4 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c:640:13:FLASH_MassErase 4 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c:656:6:FLASH_PageErase 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c:673:6:FLASH_FlushCaches 4 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c:705:13:FLASH_AcknowledgePageErase 4 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c:737:13:FLASH_OB_WRPConfig 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c:829:13:FLASH_OB_OptrConfig 32 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c:859:13:FLASH_OB_PCROP1AConfig 40 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c:910:13:FLASH_OB_PCROP1BConfig 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c:941:13:FLASH_OB_IPCCBufferAddrConfig 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c:958:13:FLASH_OB_SecureConfig 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c:1067:13:FLASH_OB_GetWRP 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c:1093:17:FLASH_OB_GetRDP 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c:1147:17:FLASH_OB_GetUser 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c:1168:13:FLASH_OB_GetPCROP 32 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c:1196:17:FLASH_OB_GetIPCCBufferAddr 4 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c:1222:13:FLASH_OB_GetSecureMemoryConfig 48 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c:1263:13:FLASH_OB_GetC2BootResetConfig 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c:1283:17:FLASH_OB_GetSUBGHZSPISecureAccess 4 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c:1294:17:FLASH_OB_GetC2DebugAccessMode 4 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c:1304:26:FLASH_OB_ProceedWriteOperation 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c:1332:13:FLASH_OB_ConfigSecureMode 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c:1357:17:FLASH_OB_GetSecureMode 24 static diff --git a/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_gpio.cyclo b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_gpio.cyclo new file mode 100644 index 0000000..96d8ee0 --- /dev/null +++ b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_gpio.cyclo @@ -0,0 +1,9 @@ +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_gpio.c:159:6:HAL_GPIO_Init 15 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_gpio.c:299:6:HAL_GPIO_DeInit 7 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_gpio.c:386:15:HAL_GPIO_ReadPin 2 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_gpio.c:418:6:HAL_GPIO_WritePin 2 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_gpio.c:448:6:HAL_GPIO_WriteMultipleStatePin 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_gpio.c:468:6:HAL_GPIO_TogglePin 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_gpio.c:493:19:HAL_GPIO_LockPin 2 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_gpio.c:528:6:HAL_GPIO_EXTI_IRQHandler 2 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_gpio.c:543:13:HAL_GPIO_EXTI_Callback 1 diff --git a/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_gpio.d b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_gpio.d new file mode 100644 index 0000000..fb555ca --- /dev/null +++ b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_gpio.d @@ -0,0 +1,76 @@ +Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_gpio.o: \ + ../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_gpio.c \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h \ + ../Core/Inc/stm32wlxx_hal_conf.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wl55xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h: +../Core/Inc/stm32wlxx_hal_conf.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wl55xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h: diff --git a/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_gpio.o b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_gpio.o new file mode 100644 index 0000000..8987a8d Binary files /dev/null and b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_gpio.o differ diff --git a/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_gpio.su b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_gpio.su new file mode 100644 index 0000000..a93fc07 --- /dev/null +++ b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_gpio.su @@ -0,0 +1,9 @@ +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_gpio.c:159:6:HAL_GPIO_Init 32 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_gpio.c:299:6:HAL_GPIO_DeInit 32 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_gpio.c:386:15:HAL_GPIO_ReadPin 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_gpio.c:418:6:HAL_GPIO_WritePin 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_gpio.c:448:6:HAL_GPIO_WriteMultipleStatePin 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_gpio.c:468:6:HAL_GPIO_TogglePin 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_gpio.c:493:19:HAL_GPIO_LockPin 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_gpio.c:528:6:HAL_GPIO_EXTI_IRQHandler 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_gpio.c:543:13:HAL_GPIO_EXTI_Callback 16 static diff --git a/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.cyclo b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.cyclo new file mode 100644 index 0000000..f462808 --- /dev/null +++ b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.cyclo @@ -0,0 +1,22 @@ +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h:265:22:LL_EXTI_EnableIT_0_31 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h:407:22:LL_EXTI_DisableIT_0_31 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h:989:22:LL_EXTI_EnableRisingTrig_0_31 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h:1049:22:LL_EXTI_DisableRisingTrig_0_31 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h:1164:22:LL_EXTI_EnableFallingTrig_0_31 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h:1223:22:LL_EXTI_DisableFallingTrig_0_31 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.c:90:6:HAL_PWR_DeInit 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.c:149:6:HAL_PWR_EnableBkUpAccess 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.c:159:6:HAL_PWR_DisableBkUpAccess 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.c:348:19:HAL_PWR_ConfigPVD 4 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.c:389:6:HAL_PWR_EnablePVD 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.c:399:6:HAL_PWR_DisablePVD 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.c:421:6:HAL_PWR_EnableWakeUpPin 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.c:447:6:HAL_PWR_DisableWakeUpPin 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.c:480:6:HAL_PWR_EnterSLEEPMode 6 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.c:563:6:HAL_PWR_EnterSTOPMode 2 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.c:598:6:HAL_PWR_EnterSTANDBYMode 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.c:636:6:HAL_PWR_EnableSleepOnExit 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.c:648:6:HAL_PWR_DisableSleepOnExit 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.c:660:6:HAL_PWR_EnableSEVOnPend 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.c:672:6:HAL_PWR_DisableSEVOnPend 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.c:682:13:HAL_PWR_PVDCallback 1 diff --git a/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.d b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.d new file mode 100644 index 0000000..7d6795e --- /dev/null +++ b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.d @@ -0,0 +1,76 @@ +Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.o: \ + ../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.c \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h \ + ../Core/Inc/stm32wlxx_hal_conf.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wl55xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h: +../Core/Inc/stm32wlxx_hal_conf.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wl55xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h: diff --git a/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.o b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.o new file mode 100644 index 0000000..4fca181 Binary files /dev/null and b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.o differ diff --git a/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.su b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.su new file mode 100644 index 0000000..f721169 --- /dev/null +++ b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.su @@ -0,0 +1,22 @@ +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h:265:22:LL_EXTI_EnableIT_0_31 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h:407:22:LL_EXTI_DisableIT_0_31 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h:989:22:LL_EXTI_EnableRisingTrig_0_31 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h:1049:22:LL_EXTI_DisableRisingTrig_0_31 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h:1164:22:LL_EXTI_EnableFallingTrig_0_31 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h:1223:22:LL_EXTI_DisableFallingTrig_0_31 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.c:90:6:HAL_PWR_DeInit 4 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.c:149:6:HAL_PWR_EnableBkUpAccess 4 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.c:159:6:HAL_PWR_DisableBkUpAccess 4 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.c:348:19:HAL_PWR_ConfigPVD 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.c:389:6:HAL_PWR_EnablePVD 4 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.c:399:6:HAL_PWR_DisablePVD 4 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.c:421:6:HAL_PWR_EnableWakeUpPin 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.c:447:6:HAL_PWR_DisableWakeUpPin 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.c:480:6:HAL_PWR_EnterSLEEPMode 16 static,ignoring_inline_asm +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.c:563:6:HAL_PWR_EnterSTOPMode 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.c:598:6:HAL_PWR_EnterSTANDBYMode 4 static,ignoring_inline_asm +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.c:636:6:HAL_PWR_EnableSleepOnExit 4 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.c:648:6:HAL_PWR_DisableSleepOnExit 4 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.c:660:6:HAL_PWR_EnableSEVOnPend 4 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.c:672:6:HAL_PWR_DisableSEVOnPend 4 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.c:682:13:HAL_PWR_PVDCallback 4 static diff --git a/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.cyclo b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.cyclo new file mode 100644 index 0000000..e12c06c --- /dev/null +++ b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.cyclo @@ -0,0 +1,61 @@ +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h:705:22:LL_PWR_EnableSRAM2Retention 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h:715:22:LL_PWR_DisableSRAM2Retention 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h:737:22:LL_PWR_EnableWPVD 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h:747:22:LL_PWR_DisableWPVD 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h:1272:22:LL_PWR_SetRadioBusyPolarity 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h:1300:22:LL_PWR_SetRadioBusyTrigger 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h:1327:22:LL_PWR_SetRadioIRQTrigger 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h:1482:22:LL_PWR_EnableBootC2 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h:1493:22:LL_PWR_DisableBootC2 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h:336:22:LL_EXTI_EnableIT_32_63 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h:478:22:LL_EXTI_DisableIT_32_63 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h:831:22:LL_EXTI_DisableEvent_32_63 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h:1011:22:LL_EXTI_EnableRisingTrig_32_63 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h:1072:22:LL_EXTI_DisableRisingTrig_32_63 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h:1186:22:LL_EXTI_EnableFallingTrig_32_63 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h:1244:22:LL_EXTI_DisableFallingTrig_32_63 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h:1446:26:LL_EXTI_ReadFlag_0_31 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h:1463:26:LL_EXTI_ReadFlag_32_63 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h:1496:22:LL_EXTI_ClearFlag_0_31 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h:1513:22:LL_EXTI_ClearFlag_32_63 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:86:10:HAL_PWREx_GetVoltageRange 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:111:19:HAL_PWREx_ControlVoltageScaling 7 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:161:6:HAL_PWREx_EnableBatteryCharging 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:176:6:HAL_PWREx_DisableBatteryCharging 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:187:6:HAL_PWREx_EnableInternalWakeUpLine 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:200:6:HAL_PWREx_DisableInternalWakeUpLine 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:216:6:HAL_PWREx_SetRadioBusyPolarity 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:234:6:HAL_PWREx_SetRadioBusyTrigger 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:254:6:HAL_PWREx_SetRadioIRQTrigger 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:271:6:HAL_PWREx_EnableHOLDC2IT 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:280:6:HAL_PWREx_DisableHOLDC2IT 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:309:19:HAL_PWREx_EnableGPIOPullUp 5 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:357:19:HAL_PWREx_DisableGPIOPullUp 5 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:407:19:HAL_PWREx_EnableGPIOPullDown 5 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:455:19:HAL_PWREx_DisableGPIOPullDown 5 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:494:6:HAL_PWREx_EnablePullUpPullDownConfig 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:509:6:HAL_PWREx_DisablePullUpPullDownConfig 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:529:6:HAL_PWREx_HoldCore 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:544:6:HAL_PWREx_ReleaseCore 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:594:6:HAL_PWREx_EnableSRAMRetention 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:605:6:HAL_PWREx_DisableSRAMRetention 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:621:6:HAL_PWREx_EnableFlashPowerDown 2 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:656:6:HAL_PWREx_DisableFlashPowerDown 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:676:6:HAL_PWREx_EnableWPVD 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:689:6:HAL_PWREx_DisableWPVD 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:706:6:HAL_PWREx_EnableBORPVD_ULP 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:718:6:HAL_PWREx_DisableBORPVD_ULP 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:729:6:HAL_PWREx_EnablePVM3 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:738:6:HAL_PWREx_DisablePVM3 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:755:19:HAL_PWREx_ConfigPVM 5 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:811:6:HAL_PWREx_SetRadioEOL 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:826:6:HAL_PWREx_SMPS_SetMode 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:842:10:HAL_PWREx_SMPS_GetEffectiveMode 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:857:6:HAL_PWREx_EnableLowPowerRunMode 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:871:19:HAL_PWREx_DisableLowPowerRunMode 4 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:918:6:HAL_PWREx_EnterSTOP0Mode 2 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:977:6:HAL_PWREx_EnterSTOP1Mode 2 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:1036:6:HAL_PWREx_EnterSTOP2Mode 2 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:1081:6:HAL_PWREx_EnterSHUTDOWNMode 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:1116:6:HAL_PWREx_PVD_PVM_IRQHandler 3 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:1142:13:HAL_PWREx_PVM3Callback 1 diff --git a/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.d b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.d new file mode 100644 index 0000000..10db246 --- /dev/null +++ b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.d @@ -0,0 +1,76 @@ +Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.o: \ + ../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h \ + ../Core/Inc/stm32wlxx_hal_conf.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wl55xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h: +../Core/Inc/stm32wlxx_hal_conf.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wl55xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h: diff --git a/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.o b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.o new file mode 100644 index 0000000..d37d5d2 Binary files /dev/null and b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.o differ diff --git a/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.su b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.su new file mode 100644 index 0000000..13b42f2 --- /dev/null +++ b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.su @@ -0,0 +1,61 @@ +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h:705:22:LL_PWR_EnableSRAM2Retention 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h:715:22:LL_PWR_DisableSRAM2Retention 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h:737:22:LL_PWR_EnableWPVD 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h:747:22:LL_PWR_DisableWPVD 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h:1272:22:LL_PWR_SetRadioBusyPolarity 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h:1300:22:LL_PWR_SetRadioBusyTrigger 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h:1327:22:LL_PWR_SetRadioIRQTrigger 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h:1482:22:LL_PWR_EnableBootC2 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h:1493:22:LL_PWR_DisableBootC2 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h:336:22:LL_EXTI_EnableIT_32_63 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h:478:22:LL_EXTI_DisableIT_32_63 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h:831:22:LL_EXTI_DisableEvent_32_63 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h:1011:22:LL_EXTI_EnableRisingTrig_32_63 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h:1072:22:LL_EXTI_DisableRisingTrig_32_63 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h:1186:22:LL_EXTI_EnableFallingTrig_32_63 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h:1244:22:LL_EXTI_DisableFallingTrig_32_63 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h:1446:26:LL_EXTI_ReadFlag_0_31 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h:1463:26:LL_EXTI_ReadFlag_32_63 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h:1496:22:LL_EXTI_ClearFlag_0_31 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h:1513:22:LL_EXTI_ClearFlag_32_63 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:86:10:HAL_PWREx_GetVoltageRange 4 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:111:19:HAL_PWREx_ControlVoltageScaling 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:161:6:HAL_PWREx_EnableBatteryCharging 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:176:6:HAL_PWREx_DisableBatteryCharging 4 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:187:6:HAL_PWREx_EnableInternalWakeUpLine 4 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:200:6:HAL_PWREx_DisableInternalWakeUpLine 4 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:216:6:HAL_PWREx_SetRadioBusyPolarity 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:234:6:HAL_PWREx_SetRadioBusyTrigger 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:254:6:HAL_PWREx_SetRadioIRQTrigger 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:271:6:HAL_PWREx_EnableHOLDC2IT 4 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:280:6:HAL_PWREx_DisableHOLDC2IT 4 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:309:19:HAL_PWREx_EnableGPIOPullUp 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:357:19:HAL_PWREx_DisableGPIOPullUp 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:407:19:HAL_PWREx_EnableGPIOPullDown 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:455:19:HAL_PWREx_DisableGPIOPullDown 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:494:6:HAL_PWREx_EnablePullUpPullDownConfig 4 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:509:6:HAL_PWREx_DisablePullUpPullDownConfig 4 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:529:6:HAL_PWREx_HoldCore 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:544:6:HAL_PWREx_ReleaseCore 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:594:6:HAL_PWREx_EnableSRAMRetention 8 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:605:6:HAL_PWREx_DisableSRAMRetention 8 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:621:6:HAL_PWREx_EnableFlashPowerDown 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:656:6:HAL_PWREx_DisableFlashPowerDown 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:676:6:HAL_PWREx_EnableWPVD 8 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:689:6:HAL_PWREx_DisableWPVD 8 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:706:6:HAL_PWREx_EnableBORPVD_ULP 4 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:718:6:HAL_PWREx_DisableBORPVD_ULP 4 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:729:6:HAL_PWREx_EnablePVM3 4 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:738:6:HAL_PWREx_DisablePVM3 4 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:755:19:HAL_PWREx_ConfigPVM 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:811:6:HAL_PWREx_SetRadioEOL 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:826:6:HAL_PWREx_SMPS_SetMode 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:842:10:HAL_PWREx_SMPS_GetEffectiveMode 4 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:857:6:HAL_PWREx_EnableLowPowerRunMode 4 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:871:19:HAL_PWREx_DisableLowPowerRunMode 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:918:6:HAL_PWREx_EnterSTOP0Mode 16 static,ignoring_inline_asm +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:977:6:HAL_PWREx_EnterSTOP1Mode 16 static,ignoring_inline_asm +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:1036:6:HAL_PWREx_EnterSTOP2Mode 16 static,ignoring_inline_asm +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:1081:6:HAL_PWREx_EnterSHUTDOWNMode 4 static,ignoring_inline_asm +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:1116:6:HAL_PWREx_PVD_PVM_IRQHandler 8 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:1142:13:HAL_PWREx_PVM3Callback 4 static diff --git a/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.cyclo b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.cyclo new file mode 100644 index 0000000..d1fce87 --- /dev/null +++ b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.cyclo @@ -0,0 +1,67 @@ +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h:421:26:LL_PWR_IsEnabledBkUpAccess 2 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:968:22:LL_RCC_HSE_EnableTcxo 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:978:22:LL_RCC_HSE_DisableTcxo 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1019:26:LL_RCC_HSE_IsEnabledDiv2 2 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1029:22:LL_RCC_HSE_EnableCSS 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1039:22:LL_RCC_HSE_Enable 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1049:22:LL_RCC_HSE_Disable 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1059:26:LL_RCC_HSE_IsReady 2 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1108:22:LL_RCC_HSI_Enable 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1118:22:LL_RCC_HSI_Disable 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1128:26:LL_RCC_HSI_IsReady 2 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1173:22:LL_RCC_HSI_SetCalibTrimming 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1334:26:LL_RCC_LSE_IsReady 2 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1389:22:LL_RCC_LSI_Enable 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1399:22:LL_RCC_LSI_Disable 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1409:26:LL_RCC_LSI_IsReady 2 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1427:22:LL_RCC_MSI_Enable 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1437:22:LL_RCC_MSI_Disable 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1447:26:LL_RCC_MSI_IsReady 2 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1496:26:LL_RCC_MSI_IsEnabledRangeSelect 2 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1519:22:LL_RCC_MSI_SetRange 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1541:26:LL_RCC_MSI_GetRange 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1570:26:LL_RCC_MSI_GetRangeAfterStandby 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1594:22:LL_RCC_MSI_SetCalibTrimming 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1730:22:LL_RCC_SetSysClkSource 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1744:26:LL_RCC_GetSysClkSource 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1770:22:LL_RCC_SetAHBPrescaler 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1796:22:LL_C2_RCC_SetAHBPrescaler 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1822:22:LL_RCC_SetAHB3Prescaler 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1838:22:LL_RCC_SetAPB1Prescaler 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1854:22:LL_RCC_SetAPB2Prescaler 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1878:26:LL_RCC_GetAHBPrescaler 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1903:26:LL_C2_RCC_GetAHBPrescaler 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1928:26:LL_RCC_GetAHB3Prescaler 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1943:26:LL_RCC_GetAPB1Prescaler 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1958:26:LL_RCC_GetAPB2Prescaler 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2020:22:LL_RCC_ConfigMCO 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2390:22:LL_RCC_PLL_Enable 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2401:22:LL_RCC_PLL_Disable 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2411:26:LL_RCC_PLL_IsReady 2 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2601:26:LL_RCC_PLL_GetN 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2678:26:LL_RCC_PLL_GetR 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2696:26:LL_RCC_PLL_GetDivider 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2853:26:LL_RCC_PLL_GetMainSource 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:3035:26:LL_RCC_IsActiveFlag_HPRE 2 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:3046:26:LL_RCC_IsActiveFlag_C2HPRE 2 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:3057:26:LL_RCC_IsActiveFlag_SHDHPRE 2 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:3068:26:LL_RCC_IsActiveFlag_PPRE1 2 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:3078:26:LL_RCC_IsActiveFlag_PPRE2 2 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.c:228:19:HAL_RCC_DeInit 10 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.c:335:19:HAL_RCC_OscConfig 84 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.c:925:19:HAL_RCC_ClockConfig 33 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.c:1188:6:HAL_RCC_MCOConfig 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.c:1251:10:HAL_RCC_GetSysClockFreq 15 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.c:1337:10:HAL_RCC_GetHCLKFreq 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.c:1348:10:HAL_RCC_GetHCLK2Freq 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.c:1359:10:HAL_RCC_GetHCLK3Freq 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.c:1369:10:HAL_RCC_GetPCLK1Freq 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.c:1379:10:HAL_RCC_GetPCLK2Freq 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.c:1392:6:HAL_RCC_GetOscConfig 2 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.c:1455:6:HAL_RCC_GetClockConfig 3 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.c:1510:6:HAL_RCC_EnableCSS 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.c:1520:6:HAL_RCC_NMI_IRQHandler 2 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.c:1537:13:HAL_RCC_CSSCallback 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.c:1550:10:HAL_RCC_GetResetSource 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.c:1583:26:RCC_SetFlashLatencyFromMSIRange 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.c:1605:26:RCC_SetFlashLatency 8 diff --git a/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.d b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.d new file mode 100644 index 0000000..1cf1027 --- /dev/null +++ b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.d @@ -0,0 +1,76 @@ +Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.o: \ + ../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.c \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h \ + ../Core/Inc/stm32wlxx_hal_conf.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wl55xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h: +../Core/Inc/stm32wlxx_hal_conf.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wl55xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h: diff --git a/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.o b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.o new file mode 100644 index 0000000..32c234e Binary files /dev/null and b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.o differ diff --git a/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.su b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.su new file mode 100644 index 0000000..c6865b0 --- /dev/null +++ b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.su @@ -0,0 +1,67 @@ +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h:421:26:LL_PWR_IsEnabledBkUpAccess 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:968:22:LL_RCC_HSE_EnableTcxo 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:978:22:LL_RCC_HSE_DisableTcxo 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1019:26:LL_RCC_HSE_IsEnabledDiv2 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1029:22:LL_RCC_HSE_EnableCSS 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1039:22:LL_RCC_HSE_Enable 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1049:22:LL_RCC_HSE_Disable 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1059:26:LL_RCC_HSE_IsReady 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1108:22:LL_RCC_HSI_Enable 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1118:22:LL_RCC_HSI_Disable 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1128:26:LL_RCC_HSI_IsReady 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1173:22:LL_RCC_HSI_SetCalibTrimming 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1334:26:LL_RCC_LSE_IsReady 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1389:22:LL_RCC_LSI_Enable 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1399:22:LL_RCC_LSI_Disable 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1409:26:LL_RCC_LSI_IsReady 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1427:22:LL_RCC_MSI_Enable 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1437:22:LL_RCC_MSI_Disable 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1447:26:LL_RCC_MSI_IsReady 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1496:26:LL_RCC_MSI_IsEnabledRangeSelect 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1519:22:LL_RCC_MSI_SetRange 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1541:26:LL_RCC_MSI_GetRange 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1570:26:LL_RCC_MSI_GetRangeAfterStandby 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1594:22:LL_RCC_MSI_SetCalibTrimming 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1730:22:LL_RCC_SetSysClkSource 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1744:26:LL_RCC_GetSysClkSource 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1770:22:LL_RCC_SetAHBPrescaler 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1796:22:LL_C2_RCC_SetAHBPrescaler 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1822:22:LL_RCC_SetAHB3Prescaler 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1838:22:LL_RCC_SetAPB1Prescaler 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1854:22:LL_RCC_SetAPB2Prescaler 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1878:26:LL_RCC_GetAHBPrescaler 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1903:26:LL_C2_RCC_GetAHBPrescaler 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1928:26:LL_RCC_GetAHB3Prescaler 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1943:26:LL_RCC_GetAPB1Prescaler 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1958:26:LL_RCC_GetAPB2Prescaler 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2020:22:LL_RCC_ConfigMCO 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2390:22:LL_RCC_PLL_Enable 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2401:22:LL_RCC_PLL_Disable 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2411:26:LL_RCC_PLL_IsReady 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2601:26:LL_RCC_PLL_GetN 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2678:26:LL_RCC_PLL_GetR 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2696:26:LL_RCC_PLL_GetDivider 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2853:26:LL_RCC_PLL_GetMainSource 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:3035:26:LL_RCC_IsActiveFlag_HPRE 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:3046:26:LL_RCC_IsActiveFlag_C2HPRE 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:3057:26:LL_RCC_IsActiveFlag_SHDHPRE 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:3068:26:LL_RCC_IsActiveFlag_PPRE1 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:3078:26:LL_RCC_IsActiveFlag_PPRE2 4 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.c:228:19:HAL_RCC_DeInit 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.c:335:19:HAL_RCC_OscConfig 40 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.c:925:19:HAL_RCC_ClockConfig 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.c:1188:6:HAL_RCC_MCOConfig 56 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.c:1251:10:HAL_RCC_GetSysClockFreq 40 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.c:1337:10:HAL_RCC_GetHCLKFreq 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.c:1348:10:HAL_RCC_GetHCLK2Freq 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.c:1359:10:HAL_RCC_GetHCLK3Freq 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.c:1369:10:HAL_RCC_GetPCLK1Freq 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.c:1379:10:HAL_RCC_GetPCLK2Freq 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.c:1392:6:HAL_RCC_GetOscConfig 32 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.c:1455:6:HAL_RCC_GetClockConfig 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.c:1510:6:HAL_RCC_EnableCSS 8 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.c:1520:6:HAL_RCC_NMI_IRQHandler 8 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.c:1537:13:HAL_RCC_CSSCallback 4 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.c:1550:10:HAL_RCC_GetResetSource 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.c:1583:26:RCC_SetFlashLatencyFromMSIRange 32 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.c:1605:26:RCC_SetFlashLatency 64 static diff --git a/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.cyclo b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.cyclo new file mode 100644 index 0000000..e888961 --- /dev/null +++ b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.cyclo @@ -0,0 +1,58 @@ +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1019:26:LL_RCC_HSE_IsEnabledDiv2 2 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1128:26:LL_RCC_HSI_IsReady 2 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1281:22:LL_RCC_LSE_EnableCSS 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1293:22:LL_RCC_LSE_DisableCSS 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1334:26:LL_RCC_LSE_IsReady 2 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1378:26:LL_RCC_LSI_GetPrediv 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1409:26:LL_RCC_LSI_IsReady 2 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1447:26:LL_RCC_MSI_IsReady 2 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1461:22:LL_RCC_MSI_EnablePLLMode 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1473:22:LL_RCC_MSI_DisablePLLMode 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1496:26:LL_RCC_MSI_IsEnabledRangeSelect 2 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1541:26:LL_RCC_MSI_GetRange 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1570:26:LL_RCC_MSI_GetRangeAfterStandby 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1632:22:LL_RCC_LSCO_Disable 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1878:26:LL_RCC_GetAHBPrescaler 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1943:26:LL_RCC_GetAPB1Prescaler 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1958:26:LL_RCC_GetAPB2Prescaler 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1971:22:LL_RCC_SetClkAfterWakeFromStop 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2047:22:LL_RCC_SetUSARTClockSource 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2061:22:LL_RCC_SetI2SClockSource 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2076:22:LL_RCC_SetLPUARTClockSource 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2096:22:LL_RCC_SetI2CClockSource 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2119:22:LL_RCC_SetLPTIMClockSource 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2134:22:LL_RCC_SetRNGClockSource 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2149:22:LL_RCC_SetADCClockSource 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2169:26:LL_RCC_GetUSARTClockSource 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2184:26:LL_RCC_GetI2SClockSource 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2200:26:LL_RCC_GetLPUARTClockSource 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2222:26:LL_RCC_GetI2CClockSource 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2249:26:LL_RCC_GetLPTIMClockSource 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2265:26:LL_RCC_GetRNGClockSource 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2281:26:LL_RCC_GetADCClockSource 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2307:22:LL_RCC_SetRTCClockSource 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2321:26:LL_RCC_GetRTCClockSource 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2361:22:LL_RCC_ForceBackupDomainReset 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2371:22:LL_RCC_ReleaseBackupDomainReset 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2411:26:LL_RCC_PLL_IsReady 2 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2601:26:LL_RCC_PLL_GetN 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2642:26:LL_RCC_PLL_GetP 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2660:26:LL_RCC_PLL_GetQ 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2696:26:LL_RCC_PLL_GetDivider 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2853:26:LL_RCC_PLL_GetMainSource 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h:265:22:LL_EXTI_EnableIT_0_31 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.c:113:19:HAL_RCCEx_PeriphCLKConfig 25 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.c:345:6:HAL_RCCEx_GetPeriphCLKConfig 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.c:416:10:HAL_RCCEx_GetPeriphCLKFreq 103 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.c:928:6:HAL_RCCEx_WakeUpStopCLKConfig 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.c:942:6:HAL_RCCEx_EnableLSECSS 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.c:952:6:HAL_RCCEx_DisableLSECSS 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.c:968:6:HAL_RCCEx_EnableLSECSS_IT 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.c:988:6:HAL_RCCEx_LSECSS_IRQHandler 2 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.c:1003:13:HAL_RCCEx_LSECSS_Callback 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.c:1018:6:HAL_RCCEx_EnableLSCO 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.c:1031:6:HAL_RCCEx_DisableLSCO 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.c:1043:6:HAL_RCCEx_EnableMSIPLLMode 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.c:1053:6:HAL_RCCEx_DisableMSIPLLMode 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.c:1075:17:RCC_PLL_GetFreqDomain_P 12 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.c:1125:17:RCC_PLL_GetFreqDomain_Q 12 diff --git a/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.d b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.d new file mode 100644 index 0000000..1c75ca5 --- /dev/null +++ b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.d @@ -0,0 +1,76 @@ +Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.o: \ + ../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.c \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h \ + ../Core/Inc/stm32wlxx_hal_conf.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wl55xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h: +../Core/Inc/stm32wlxx_hal_conf.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wl55xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h: diff --git a/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.o b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.o new file mode 100644 index 0000000..1a1f512 Binary files /dev/null and b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.o differ diff --git a/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.su b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.su new file mode 100644 index 0000000..eb53986 --- /dev/null +++ b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.su @@ -0,0 +1,58 @@ +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1019:26:LL_RCC_HSE_IsEnabledDiv2 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1128:26:LL_RCC_HSI_IsReady 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1281:22:LL_RCC_LSE_EnableCSS 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1293:22:LL_RCC_LSE_DisableCSS 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1334:26:LL_RCC_LSE_IsReady 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1378:26:LL_RCC_LSI_GetPrediv 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1409:26:LL_RCC_LSI_IsReady 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1447:26:LL_RCC_MSI_IsReady 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1461:22:LL_RCC_MSI_EnablePLLMode 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1473:22:LL_RCC_MSI_DisablePLLMode 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1496:26:LL_RCC_MSI_IsEnabledRangeSelect 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1541:26:LL_RCC_MSI_GetRange 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1570:26:LL_RCC_MSI_GetRangeAfterStandby 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1632:22:LL_RCC_LSCO_Disable 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1878:26:LL_RCC_GetAHBPrescaler 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1943:26:LL_RCC_GetAPB1Prescaler 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1958:26:LL_RCC_GetAPB2Prescaler 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1971:22:LL_RCC_SetClkAfterWakeFromStop 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2047:22:LL_RCC_SetUSARTClockSource 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2061:22:LL_RCC_SetI2SClockSource 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2076:22:LL_RCC_SetLPUARTClockSource 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2096:22:LL_RCC_SetI2CClockSource 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2119:22:LL_RCC_SetLPTIMClockSource 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2134:22:LL_RCC_SetRNGClockSource 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2149:22:LL_RCC_SetADCClockSource 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2169:26:LL_RCC_GetUSARTClockSource 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2184:26:LL_RCC_GetI2SClockSource 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2200:26:LL_RCC_GetLPUARTClockSource 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2222:26:LL_RCC_GetI2CClockSource 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2249:26:LL_RCC_GetLPTIMClockSource 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2265:26:LL_RCC_GetRNGClockSource 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2281:26:LL_RCC_GetADCClockSource 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2307:22:LL_RCC_SetRTCClockSource 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2321:26:LL_RCC_GetRTCClockSource 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2361:22:LL_RCC_ForceBackupDomainReset 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2371:22:LL_RCC_ReleaseBackupDomainReset 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2411:26:LL_RCC_PLL_IsReady 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2601:26:LL_RCC_PLL_GetN 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2642:26:LL_RCC_PLL_GetP 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2660:26:LL_RCC_PLL_GetQ 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2696:26:LL_RCC_PLL_GetDivider 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2853:26:LL_RCC_PLL_GetMainSource 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h:265:22:LL_EXTI_EnableIT_0_31 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.c:113:19:HAL_RCCEx_PeriphCLKConfig 32 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.c:345:6:HAL_RCCEx_GetPeriphCLKConfig 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.c:416:10:HAL_RCCEx_GetPeriphCLKFreq 32 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.c:928:6:HAL_RCCEx_WakeUpStopCLKConfig 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.c:942:6:HAL_RCCEx_EnableLSECSS 8 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.c:952:6:HAL_RCCEx_DisableLSECSS 8 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.c:968:6:HAL_RCCEx_EnableLSECSS_IT 8 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.c:988:6:HAL_RCCEx_LSECSS_IRQHandler 8 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.c:1003:13:HAL_RCCEx_LSECSS_Callback 4 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.c:1018:6:HAL_RCCEx_EnableLSCO 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.c:1031:6:HAL_RCCEx_DisableLSCO 8 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.c:1043:6:HAL_RCCEx_EnableMSIPLLMode 8 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.c:1053:6:HAL_RCCEx_DisableMSIPLLMode 8 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.c:1075:17:RCC_PLL_GetFreqDomain_P 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.c:1125:17:RCC_PLL_GetFreqDomain_Q 24 static diff --git a/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.cyclo b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.cyclo new file mode 100644 index 0000000..082a104 --- /dev/null +++ b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.cyclo @@ -0,0 +1,26 @@ +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.c:242:19:HAL_RTC_Init 8 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.c:372:19:HAL_RTC_DeInit 4 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.c:704:13:HAL_RTC_MspInit 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.c:719:13:HAL_RTC_MspDeInit 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.c:760:19:HAL_RTC_SetTime 8 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.c:884:19:HAL_RTC_GetTime 3 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.c:932:19:HAL_RTC_SetDate 7 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.c:1016:19:HAL_RTC_GetDate 2 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.c:1050:6:HAL_RTC_DST_Add1Hour 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.c:1064:6:HAL_RTC_DST_Sub1Hour 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.c:1078:6:HAL_RTC_DST_SetStoreOperation 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.c:1091:6:HAL_RTC_DST_ClearStoreOperation 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.c:1104:10:HAL_RTC_DST_ReadStoreOperation 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.c:1143:19:HAL_RTC_SetAlarm 11 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.c:1349:19:HAL_RTC_SetAlarm_IT 11 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.c:1550:19:HAL_RTC_DeactivateAlarm 3 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.c:1617:19:HAL_RTC_GetAlarm 5 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.c:1701:6:HAL_RTC_AlarmIRQHandler 3 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.c:1740:13:HAL_RTC_AlarmAEventCallback 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.c:1756:19:HAL_RTC_PollForAlarmAEvent 5 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.c:1814:19:HAL_RTC_WaitForSynchro 3 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.c:1859:21:HAL_RTC_GetState 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.c:1882:19:RTC_EnterInitMode 5 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.c:1914:19:RTC_ExitInitMode 4 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.c:1951:9:RTC_ByteToBcd2 2 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.c:1970:9:RTC_Bcd2ToByte 1 diff --git a/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.d b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.d new file mode 100644 index 0000000..0dc7f03 --- /dev/null +++ b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.d @@ -0,0 +1,76 @@ +Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.o: \ + ../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.c \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h \ + ../Core/Inc/stm32wlxx_hal_conf.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wl55xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h: +../Core/Inc/stm32wlxx_hal_conf.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wl55xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h: diff --git a/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.o b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.o new file mode 100644 index 0000000..bc23ee2 Binary files /dev/null and b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.o differ diff --git a/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.su b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.su new file mode 100644 index 0000000..a9ced69 --- /dev/null +++ b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.su @@ -0,0 +1,26 @@ +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.c:242:19:HAL_RTC_Init 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.c:372:19:HAL_RTC_DeInit 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.c:704:13:HAL_RTC_MspInit 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.c:719:13:HAL_RTC_MspDeInit 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.c:760:19:HAL_RTC_SetTime 40 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.c:884:19:HAL_RTC_GetTime 32 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.c:932:19:HAL_RTC_SetDate 40 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.c:1016:19:HAL_RTC_GetDate 32 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.c:1050:6:HAL_RTC_DST_Add1Hour 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.c:1064:6:HAL_RTC_DST_Sub1Hour 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.c:1078:6:HAL_RTC_DST_SetStoreOperation 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.c:1091:6:HAL_RTC_DST_ClearStoreOperation 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.c:1104:10:HAL_RTC_DST_ReadStoreOperation 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.c:1143:19:HAL_RTC_SetAlarm 40 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.c:1349:19:HAL_RTC_SetAlarm_IT 40 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.c:1550:19:HAL_RTC_DeactivateAlarm 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.c:1617:19:HAL_RTC_GetAlarm 40 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.c:1701:6:HAL_RTC_AlarmIRQHandler 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.c:1740:13:HAL_RTC_AlarmAEventCallback 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.c:1756:19:HAL_RTC_PollForAlarmAEvent 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.c:1814:19:HAL_RTC_WaitForSynchro 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.c:1859:21:HAL_RTC_GetState 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.c:1882:19:RTC_EnterInitMode 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.c:1914:19:RTC_ExitInitMode 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.c:1951:9:RTC_ByteToBcd2 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.c:1970:9:RTC_Bcd2ToByte 24 static diff --git a/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.cyclo b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.cyclo new file mode 100644 index 0000000..b5eb055 --- /dev/null +++ b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.cyclo @@ -0,0 +1,51 @@ +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:178:19:HAL_RTCEx_SetTimeStamp 2 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:229:19:HAL_RTCEx_SetTimeStamp_IT 2 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:272:19:HAL_RTCEx_DeactivateTimeStamp 3 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:308:19:HAL_RTCEx_SetInternalTimeStamp 2 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:338:19:HAL_RTCEx_DeactivateInternalTimeStamp 4 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:386:19:HAL_RTCEx_GetTimeStamp 3 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:442:6:HAL_RTCEx_TimeStampIRQHandler 2 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:465:13:HAL_RTCEx_TimeStampEventCallback 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:481:19:HAL_RTCEx_PollForTimeStampEvent 6 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:539:19:HAL_RTCEx_SetWakeUpTimer 5 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:612:19:HAL_RTCEx_SetWakeUpTimer_IT 6 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:697:19:HAL_RTCEx_DeactivateWakeUpTimer 4 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:750:10:HAL_RTCEx_GetWakeUpTimer 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:762:6:HAL_RTCEx_WakeUpTimerIRQHandler 2 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:787:13:HAL_RTCEx_WakeUpTimerEventCallback 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:804:19:HAL_RTCEx_PollForWakeUpTimerEvent 5 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:882:19:HAL_RTCEx_SetSmoothCalib 5 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:949:19:HAL_RTCEx_SetLowPowerCalib 2 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:989:19:HAL_RTCEx_SetSynchroShift 7 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:1082:19:HAL_RTCEx_SetCalibrationOutPut 2 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:1118:19:HAL_RTCEx_DeactivateCalibrationOutPut 2 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:1148:19:HAL_RTCEx_SetRefClock 4 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:1190:19:HAL_RTCEx_DeactivateRefClock 4 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:1234:19:HAL_RTCEx_EnableBypassShadow 2 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:1266:19:HAL_RTCEx_DisableBypassShadow 2 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:1299:19:HAL_RTCEx_MonotonicCounterIncrement 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:1319:19:HAL_RTCEx_MonotonicCounterGet 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:1336:19:HAL_RTCEx_SetSSRU_IT 2 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:1368:19:HAL_RTCEx_DeactivateSSRU 2 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:1400:6:HAL_RTCEx_SSRUIRQHandler 2 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:1425:13:HAL_RTCEx_SSRUEventCallback 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:1459:13:HAL_RTCEx_AlarmBEventCallback 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:1475:19:HAL_RTCEx_PollForAlarmBEvent 5 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:1538:19:HAL_RTCEx_SetTamper 6 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:1603:19:HAL_RTCEx_SetTamper_IT 6 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:1677:19:HAL_RTCEx_DeactivateTamper 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:1713:19:HAL_RTCEx_PollForTamperEvent 5 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:1745:19:HAL_RTCEx_SetInternalTamper 3 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:1785:19:HAL_RTCEx_SetInternalTamper_IT 3 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:1831:19:HAL_RTCEx_DeactivateInternalTamper 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:1860:19:HAL_RTCEx_PollForInternalTamperEvent 5 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:1891:6:HAL_RTCEx_TamperIRQHandler 8 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:1988:13:HAL_RTCEx_Tamper1EventCallback 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:2004:13:HAL_RTCEx_Tamper2EventCallback 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:2019:13:HAL_RTCEx_Tamper3EventCallback 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:2034:13:HAL_RTCEx_InternalTamper3EventCallback 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:2050:13:HAL_RTCEx_InternalTamper5EventCallback 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:2065:13:HAL_RTCEx_InternalTamper6EventCallback 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:2080:13:HAL_RTCEx_InternalTamper8EventCallback 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:2122:6:HAL_RTCEx_BKUPWrite 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:2145:10:HAL_RTCEx_BKUPRead 1 diff --git a/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.d b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.d new file mode 100644 index 0000000..ea71c38 --- /dev/null +++ b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.d @@ -0,0 +1,76 @@ +Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.o: \ + ../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h \ + ../Core/Inc/stm32wlxx_hal_conf.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wl55xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h: +../Core/Inc/stm32wlxx_hal_conf.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wl55xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h: diff --git a/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.o b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.o new file mode 100644 index 0000000..b76a092 Binary files /dev/null and b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.o differ diff --git a/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.su b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.su new file mode 100644 index 0000000..da9103b --- /dev/null +++ b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.su @@ -0,0 +1,51 @@ +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:178:19:HAL_RTCEx_SetTimeStamp 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:229:19:HAL_RTCEx_SetTimeStamp_IT 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:272:19:HAL_RTCEx_DeactivateTimeStamp 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:308:19:HAL_RTCEx_SetInternalTimeStamp 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:338:19:HAL_RTCEx_DeactivateInternalTimeStamp 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:386:19:HAL_RTCEx_GetTimeStamp 32 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:442:6:HAL_RTCEx_TimeStampIRQHandler 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:465:13:HAL_RTCEx_TimeStampEventCallback 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:481:19:HAL_RTCEx_PollForTimeStampEvent 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:539:19:HAL_RTCEx_SetWakeUpTimer 32 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:612:19:HAL_RTCEx_SetWakeUpTimer_IT 32 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:697:19:HAL_RTCEx_DeactivateWakeUpTimer 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:750:10:HAL_RTCEx_GetWakeUpTimer 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:762:6:HAL_RTCEx_WakeUpTimerIRQHandler 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:787:13:HAL_RTCEx_WakeUpTimerEventCallback 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:804:19:HAL_RTCEx_PollForWakeUpTimerEvent 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:882:19:HAL_RTCEx_SetSmoothCalib 32 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:949:19:HAL_RTCEx_SetLowPowerCalib 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:989:19:HAL_RTCEx_SetSynchroShift 32 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:1082:19:HAL_RTCEx_SetCalibrationOutPut 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:1118:19:HAL_RTCEx_DeactivateCalibrationOutPut 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:1148:19:HAL_RTCEx_SetRefClock 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:1190:19:HAL_RTCEx_DeactivateRefClock 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:1234:19:HAL_RTCEx_EnableBypassShadow 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:1266:19:HAL_RTCEx_DisableBypassShadow 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:1299:19:HAL_RTCEx_MonotonicCounterIncrement 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:1319:19:HAL_RTCEx_MonotonicCounterGet 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:1336:19:HAL_RTCEx_SetSSRU_IT 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:1368:19:HAL_RTCEx_DeactivateSSRU 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:1400:6:HAL_RTCEx_SSRUIRQHandler 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:1425:13:HAL_RTCEx_SSRUEventCallback 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:1459:13:HAL_RTCEx_AlarmBEventCallback 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:1475:19:HAL_RTCEx_PollForAlarmBEvent 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:1538:19:HAL_RTCEx_SetTamper 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:1603:19:HAL_RTCEx_SetTamper_IT 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:1677:19:HAL_RTCEx_DeactivateTamper 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:1713:19:HAL_RTCEx_PollForTamperEvent 32 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:1745:19:HAL_RTCEx_SetInternalTamper 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:1785:19:HAL_RTCEx_SetInternalTamper_IT 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:1831:19:HAL_RTCEx_DeactivateInternalTamper 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:1860:19:HAL_RTCEx_PollForInternalTamperEvent 32 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:1891:6:HAL_RTCEx_TamperIRQHandler 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:1988:13:HAL_RTCEx_Tamper1EventCallback 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:2004:13:HAL_RTCEx_Tamper2EventCallback 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:2019:13:HAL_RTCEx_Tamper3EventCallback 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:2034:13:HAL_RTCEx_InternalTamper3EventCallback 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:2050:13:HAL_RTCEx_InternalTamper5EventCallback 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:2065:13:HAL_RTCEx_InternalTamper6EventCallback 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:2080:13:HAL_RTCEx_InternalTamper8EventCallback 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:2122:6:HAL_RTCEx_BKUPWrite 32 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:2145:10:HAL_RTCEx_BKUPRead 24 static diff --git a/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.cyclo b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.cyclo new file mode 100644 index 0000000..0e9ba66 --- /dev/null +++ b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.cyclo @@ -0,0 +1,42 @@ +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h:1300:22:LL_PWR_SetRadioBusyTrigger 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h:1375:22:LL_PWR_UnselectSUBGHZSPI_NSS 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h:1385:22:LL_PWR_SelectSUBGHZSPI_NSS 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h:2035:22:LL_PWR_ClearFlag_RFBUSY 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h:2048:26:LL_PWR_IsActiveFlag_RFBUSYS 2 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h:2061:26:LL_PWR_IsActiveFlag_RFBUSYMS 2 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1675:22:LL_RCC_RF_EnableReset 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1685:22:LL_RCC_RF_DisableReset 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1705:26:LL_RCC_IsRFUnderReset 2 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h:336:22:LL_EXTI_EnableIT_32_63 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h:478:22:LL_EXTI_DisableIT_32_63 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c:220:19:HAL_SUBGHZ_Init 8 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c:337:19:HAL_SUBGHZ_DeInit 4 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c:420:13:HAL_SUBGHZ_MspInit 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c:436:13:HAL_SUBGHZ_MspDeInit 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c:801:19:HAL_SUBGHZ_WriteRegisters 5 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c:865:19:HAL_SUBGHZ_ReadRegisters 5 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c:929:19:HAL_SUBGHZ_WriteRegister 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c:944:19:HAL_SUBGHZ_ReadRegister 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c:960:19:HAL_SUBGHZ_ExecSetCmd 8 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c:1036:19:HAL_SUBGHZ_ExecGetCmd 5 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c:1101:19:HAL_SUBGHZ_WriteBuffer 5 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c:1161:19:HAL_SUBGHZ_ReadBuffer 5 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c:1222:6:HAL_SUBGHZ_IRQHandler 13 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c:1362:13:HAL_SUBGHZ_TxCpltCallback 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c:1378:13:HAL_SUBGHZ_RxCpltCallback 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c:1394:13:HAL_SUBGHZ_PreambleDetectedCallback 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c:1410:13:HAL_SUBGHZ_SyncWordValidCallback 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c:1426:13:HAL_SUBGHZ_HeaderValidCallback 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c:1442:13:HAL_SUBGHZ_HeaderErrorCallback 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c:1458:13:HAL_SUBGHZ_CRCErrorCallback 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c:1476:13:HAL_SUBGHZ_CADStatusCallback 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c:1494:13:HAL_SUBGHZ_RxTxTimeoutCallback 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c:1510:13:HAL_SUBGHZ_LrFhssHopCallback 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c:1544:25:HAL_SUBGHZ_GetState 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c:1556:10:HAL_SUBGHZ_GetError 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c:1580:6:SUBGHZSPI_Init 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c:1616:7:SUBGHZSPI_DeInit 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c:1632:19:SUBGHZSPI_Transmit 5 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c:1691:19:SUBGHZSPI_Receive 5 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c:1749:19:SUBGHZ_CheckDeviceReady 3 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c:1780:19:SUBGHZ_WaitOnBusy 3 diff --git a/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.d b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.d new file mode 100644 index 0000000..1233e2f --- /dev/null +++ b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.d @@ -0,0 +1,76 @@ +Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.o: \ + ../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h \ + ../Core/Inc/stm32wlxx_hal_conf.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wl55xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h: +../Core/Inc/stm32wlxx_hal_conf.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wl55xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h: diff --git a/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.o b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.o new file mode 100644 index 0000000..cb3be18 Binary files /dev/null and b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.o differ diff --git a/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.su b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.su new file mode 100644 index 0000000..488354e --- /dev/null +++ b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.su @@ -0,0 +1,42 @@ +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h:1300:22:LL_PWR_SetRadioBusyTrigger 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h:1375:22:LL_PWR_UnselectSUBGHZSPI_NSS 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h:1385:22:LL_PWR_SelectSUBGHZSPI_NSS 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h:2035:22:LL_PWR_ClearFlag_RFBUSY 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h:2048:26:LL_PWR_IsActiveFlag_RFBUSYS 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h:2061:26:LL_PWR_IsActiveFlag_RFBUSYMS 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1675:22:LL_RCC_RF_EnableReset 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1685:22:LL_RCC_RF_DisableReset 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1705:26:LL_RCC_IsRFUnderReset 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h:336:22:LL_EXTI_EnableIT_32_63 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h:478:22:LL_EXTI_DisableIT_32_63 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c:220:19:HAL_SUBGHZ_Init 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c:337:19:HAL_SUBGHZ_DeInit 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c:420:13:HAL_SUBGHZ_MspInit 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c:436:13:HAL_SUBGHZ_MspDeInit 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c:801:19:HAL_SUBGHZ_WriteRegisters 32 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c:865:19:HAL_SUBGHZ_ReadRegisters 40 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c:929:19:HAL_SUBGHZ_WriteRegister 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c:944:19:HAL_SUBGHZ_ReadRegister 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c:960:19:HAL_SUBGHZ_ExecSetCmd 32 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c:1036:19:HAL_SUBGHZ_ExecGetCmd 40 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c:1101:19:HAL_SUBGHZ_WriteBuffer 32 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c:1161:19:HAL_SUBGHZ_ReadBuffer 40 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c:1222:6:HAL_SUBGHZ_IRQHandler 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c:1362:13:HAL_SUBGHZ_TxCpltCallback 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c:1378:13:HAL_SUBGHZ_RxCpltCallback 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c:1394:13:HAL_SUBGHZ_PreambleDetectedCallback 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c:1410:13:HAL_SUBGHZ_SyncWordValidCallback 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c:1426:13:HAL_SUBGHZ_HeaderValidCallback 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c:1442:13:HAL_SUBGHZ_HeaderErrorCallback 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c:1458:13:HAL_SUBGHZ_CRCErrorCallback 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c:1476:13:HAL_SUBGHZ_CADStatusCallback 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c:1494:13:HAL_SUBGHZ_RxTxTimeoutCallback 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c:1510:13:HAL_SUBGHZ_LrFhssHopCallback 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c:1544:25:HAL_SUBGHZ_GetState 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c:1556:10:HAL_SUBGHZ_GetError 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c:1580:6:SUBGHZSPI_Init 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c:1616:7:SUBGHZSPI_DeInit 4 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c:1632:19:SUBGHZSPI_Transmit 32 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c:1691:19:SUBGHZSPI_Receive 32 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c:1749:19:SUBGHZ_CheckDeviceReady 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c:1780:19:SUBGHZ_WaitOnBusy 32 static diff --git a/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.cyclo b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.cyclo new file mode 100644 index 0000000..0e4ce7e --- /dev/null +++ b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.cyclo @@ -0,0 +1,72 @@ +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2169:26:LL_RCC_GetUSARTClockSource 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2200:26:LL_RCC_GetLPUARTClockSource 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:307:19:HAL_UART_Init 5 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:382:19:HAL_HalfDuplex_Init 5 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:457:19:HAL_LIN_Init 7 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:556:19:HAL_MultiProcessor_Init 6 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:632:19:HAL_UART_DeInit 2 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:679:13:HAL_UART_MspInit 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:694:13:HAL_UART_MspDeInit 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:1129:19:HAL_UART_Transmit 11 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:1248:19:HAL_UART_Receive 16 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:1361:19:HAL_UART_Transmit_IT 11 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:1450:19:HAL_UART_Receive_IT 7 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:1512:19:HAL_UART_Transmit_DMA 7 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:1603:19:HAL_UART_Receive_DMA 7 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:1652:19:HAL_UART_DMAPause 9 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:1682:19:HAL_UART_DMAResume 8 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:1713:19:HAL_UART_DMAStop 13 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:1788:19:HAL_UART_Abort 16 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:1887:19:HAL_UART_AbortTransmit 9 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:1943:19:HAL_UART_AbortReceive 10 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:2008:19:HAL_UART_Abort_IT 19 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:2157:19:HAL_UART_AbortTransmit_IT 8 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:2243:19:HAL_UART_AbortReceive_IT 9 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:2330:6:HAL_UART_IRQHandler 61 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:2682:13:HAL_UART_TxCpltCallback 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:2697:13:HAL_UART_TxHalfCpltCallback 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:2712:13:HAL_UART_RxCpltCallback 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:2727:13:HAL_UART_RxHalfCpltCallback 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:2742:13:HAL_UART_ErrorCallback 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:2757:13:HAL_UART_AbortCpltCallback 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:2772:13:HAL_UART_AbortTransmitCpltCallback 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:2787:13:HAL_UART_AbortReceiveCpltCallback 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:2804:13:HAL_UARTEx_RxEventCallback 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:2852:6:HAL_UART_ReceiverTimeout_Config 2 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:2867:19:HAL_UART_EnableReceiverTimeout 4 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:2905:19:HAL_UART_DisableReceiverTimeout 4 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:2943:19:HAL_MultiProcessor_EnableMuteMode 3 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:2963:19:HAL_MultiProcessor_DisableMuteMode 3 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:2983:6:HAL_MultiProcessor_EnterMuteMode 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:2993:19:HAL_HalfDuplex_EnableTransmitter 4 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:3016:19:HAL_HalfDuplex_EnableReceiver 4 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:3040:19:HAL_LIN_SendBreak 2 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:3085:23:HAL_UART_GetState 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:3101:10:HAL_UART_GetError 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:3147:19:UART_SetConfig 46 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:3364:6:UART_AdvFeatureConfig 10 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:3438:19:UART_CheckIdleState 8 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:3507:19:UART_WaitOnFlagUntilTimeout 10 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:3575:19:UART_Start_Receive_IT 20 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:3647:19:UART_Start_Receive_DMA 7 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:3704:13:UART_EndTxTransfer 3 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:3720:13:UART_EndRxTransfer 5 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:3746:13:UART_DMATransmitCplt 4 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:3778:13:UART_DMATxHalfCplt 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:3796:13:UART_DMAReceiveCplt 9 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:3865:13:UART_DMARxHalfCplt 3 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:3913:13:UART_DMAError 5 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:3951:13:UART_DMAAbortOnError 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:3972:13:UART_DMATxAbortCallback 4 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:4023:13:UART_DMARxAbortCallback 3 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:4071:13:UART_DMATxOnlyAbortCallback 2 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:4102:13:UART_DMARxOnlyAbortCallback 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:4133:13:UART_TxISR_8BIT 5 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:4162:13:UART_TxISR_16BIT 5 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:4194:13:UART_TxISR_8BIT_FIFOEN 7 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:4234:13:UART_TxISR_16BIT_FIFOEN 7 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:4275:13:UART_EndTransmit_IT 2 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:4300:13:UART_RxISR_8BIT 11 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:4391:13:UART_RxISR_16BIT 11 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:4484:13:UART_RxISR_8BIT_FIFOEN 25 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:4647:13:UART_RxISR_16BIT_FIFOEN 25 diff --git a/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.d b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.d new file mode 100644 index 0000000..9e2d740 --- /dev/null +++ b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.d @@ -0,0 +1,76 @@ +Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.o: \ + ../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h \ + ../Core/Inc/stm32wlxx_hal_conf.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wl55xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h: +../Core/Inc/stm32wlxx_hal_conf.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wl55xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h: diff --git a/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.o b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.o new file mode 100644 index 0000000..51330c4 Binary files /dev/null and b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.o differ diff --git a/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.su b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.su new file mode 100644 index 0000000..92628c1 --- /dev/null +++ b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.su @@ -0,0 +1,72 @@ +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2169:26:LL_RCC_GetUSARTClockSource 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2200:26:LL_RCC_GetLPUARTClockSource 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:307:19:HAL_UART_Init 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:382:19:HAL_HalfDuplex_Init 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:457:19:HAL_LIN_Init 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:556:19:HAL_MultiProcessor_Init 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:632:19:HAL_UART_DeInit 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:679:13:HAL_UART_MspInit 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:694:13:HAL_UART_MspDeInit 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:1129:19:HAL_UART_Transmit 48 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:1248:19:HAL_UART_Receive 48 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:1361:19:HAL_UART_Transmit_IT 72 static,ignoring_inline_asm +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:1450:19:HAL_UART_Receive_IT 48 static,ignoring_inline_asm +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:1512:19:HAL_UART_Transmit_DMA 48 static,ignoring_inline_asm +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:1603:19:HAL_UART_Receive_DMA 48 static,ignoring_inline_asm +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:1652:19:HAL_UART_DMAPause 120 static,ignoring_inline_asm +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:1682:19:HAL_UART_DMAResume 112 static,ignoring_inline_asm +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:1713:19:HAL_UART_DMAStop 72 static,ignoring_inline_asm +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:1788:19:HAL_UART_Abort 136 static,ignoring_inline_asm +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:1887:19:HAL_UART_AbortTransmit 88 static,ignoring_inline_asm +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:1943:19:HAL_UART_AbortReceive 112 static,ignoring_inline_asm +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:2008:19:HAL_UART_Abort_IT 144 static,ignoring_inline_asm +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:2157:19:HAL_UART_AbortTransmit_IT 88 static,ignoring_inline_asm +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:2243:19:HAL_UART_AbortReceive_IT 112 static,ignoring_inline_asm +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:2330:6:HAL_UART_IRQHandler 240 static,ignoring_inline_asm +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:2682:13:HAL_UART_TxCpltCallback 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:2697:13:HAL_UART_TxHalfCpltCallback 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:2712:13:HAL_UART_RxCpltCallback 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:2727:13:HAL_UART_RxHalfCpltCallback 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:2742:13:HAL_UART_ErrorCallback 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:2757:13:HAL_UART_AbortCpltCallback 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:2772:13:HAL_UART_AbortTransmitCpltCallback 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:2787:13:HAL_UART_AbortReceiveCpltCallback 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:2804:13:HAL_UARTEx_RxEventCallback 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:2852:6:HAL_UART_ReceiverTimeout_Config 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:2867:19:HAL_UART_EnableReceiverTimeout 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:2905:19:HAL_UART_DisableReceiverTimeout 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:2943:19:HAL_MultiProcessor_EnableMuteMode 40 static,ignoring_inline_asm +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:2963:19:HAL_MultiProcessor_DisableMuteMode 40 static,ignoring_inline_asm +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:2983:6:HAL_MultiProcessor_EnterMuteMode 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:2993:19:HAL_HalfDuplex_EnableTransmitter 64 static,ignoring_inline_asm +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:3016:19:HAL_HalfDuplex_EnableReceiver 64 static,ignoring_inline_asm +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:3040:19:HAL_LIN_SendBreak 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:3085:23:HAL_UART_GetState 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:3101:10:HAL_UART_GetError 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:3147:19:UART_SetConfig 80 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:3364:6:UART_AdvFeatureConfig 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:3438:19:UART_CheckIdleState 104 static,ignoring_inline_asm +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:3507:19:UART_WaitOnFlagUntilTimeout 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:3575:19:UART_Start_Receive_IT 144 static,ignoring_inline_asm +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:3647:19:UART_Start_Receive_DMA 96 static,ignoring_inline_asm +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:3704:13:UART_EndTxTransfer 64 static,ignoring_inline_asm +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:3720:13:UART_EndRxTransfer 88 static,ignoring_inline_asm +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:3746:13:UART_DMATransmitCplt 72 static,ignoring_inline_asm +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:3778:13:UART_DMATxHalfCplt 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:3796:13:UART_DMAReceiveCplt 120 static,ignoring_inline_asm +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:3865:13:UART_DMARxHalfCplt 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:3913:13:UART_DMAError 32 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:3951:13:UART_DMAAbortOnError 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:3972:13:UART_DMATxAbortCallback 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:4023:13:UART_DMARxAbortCallback 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:4071:13:UART_DMATxOnlyAbortCallback 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:4102:13:UART_DMARxOnlyAbortCallback 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:4133:13:UART_TxISR_8BIT 64 static,ignoring_inline_asm +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:4162:13:UART_TxISR_16BIT 72 static,ignoring_inline_asm +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:4194:13:UART_TxISR_8BIT_FIFOEN 72 static,ignoring_inline_asm +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:4234:13:UART_TxISR_16BIT_FIFOEN 72 static,ignoring_inline_asm +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:4275:13:UART_EndTransmit_IT 40 static,ignoring_inline_asm +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:4300:13:UART_RxISR_8BIT 120 static,ignoring_inline_asm +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:4391:13:UART_RxISR_16BIT 120 static,ignoring_inline_asm +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:4484:13:UART_RxISR_8BIT_FIFOEN 184 static,ignoring_inline_asm +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:4647:13:UART_RxISR_16BIT_FIFOEN 192 static,ignoring_inline_asm diff --git a/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.cyclo b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.cyclo new file mode 100644 index 0000000..bdfaabf --- /dev/null +++ b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.cyclo @@ -0,0 +1,18 @@ +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.c:166:19:HAL_RS485Ex_Init 5 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.c:272:13:HAL_UARTEx_WakeupCallback 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.c:287:13:HAL_UARTEx_RxFifoFullCallback 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.c:302:13:HAL_UARTEx_TxFifoEmptyCallback 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.c:387:19:HAL_MultiProcessorEx_AddressLength_Set 2 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.c:425:19:HAL_UARTEx_StopModeWakeUpSourceConfig 4 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.c:480:19:HAL_UARTEx_EnableStopMode 3 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.c:499:19:HAL_UARTEx_DisableStopMode 3 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.c:518:19:HAL_UARTEx_EnableFifoMode 2 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.c:559:19:HAL_UARTEx_DisableFifoMode 2 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.c:605:19:HAL_UARTEx_SetTxFifoThreshold 2 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.c:654:19:HAL_UARTEx_SetRxFifoThreshold 2 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.c:719:19:HAL_UARTEx_ReceiveToIdle 20 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.c:863:19:HAL_UARTEx_ReceiveToIdle_IT 6 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.c:941:19:HAL_UARTEx_ReceiveToIdle_DMA 7 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.c:1020:29:HAL_UARTEx_GetRxEventType 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.c:1044:13:UARTEx_Wakeup_AddressConfig 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.c:1062:13:UARTEx_SetNbDataToProcess 2 diff --git a/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.d b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.d new file mode 100644 index 0000000..785733a --- /dev/null +++ b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.d @@ -0,0 +1,76 @@ +Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.o: \ + ../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.c \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h \ + ../Core/Inc/stm32wlxx_hal_conf.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wl55xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h: +../Core/Inc/stm32wlxx_hal_conf.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wl55xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h: diff --git a/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.o b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.o new file mode 100644 index 0000000..cb7d871 Binary files /dev/null and b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.o differ diff --git a/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.su b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.su new file mode 100644 index 0000000..d76006e --- /dev/null +++ b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.su @@ -0,0 +1,18 @@ +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.c:166:19:HAL_RS485Ex_Init 32 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.c:272:13:HAL_UARTEx_WakeupCallback 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.c:287:13:HAL_UARTEx_RxFifoFullCallback 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.c:302:13:HAL_UARTEx_TxFifoEmptyCallback 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.c:387:19:HAL_MultiProcessorEx_AddressLength_Set 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.c:425:19:HAL_UARTEx_StopModeWakeUpSourceConfig 40 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.c:480:19:HAL_UARTEx_EnableStopMode 40 static,ignoring_inline_asm +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.c:499:19:HAL_UARTEx_DisableStopMode 40 static,ignoring_inline_asm +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.c:518:19:HAL_UARTEx_EnableFifoMode 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.c:559:19:HAL_UARTEx_DisableFifoMode 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.c:605:19:HAL_UARTEx_SetTxFifoThreshold 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.c:654:19:HAL_UARTEx_SetRxFifoThreshold 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.c:719:19:HAL_UARTEx_ReceiveToIdle 40 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.c:863:19:HAL_UARTEx_ReceiveToIdle_IT 56 static,ignoring_inline_asm +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.c:941:19:HAL_UARTEx_ReceiveToIdle_DMA 56 static,ignoring_inline_asm +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.c:1020:29:HAL_UARTEx_GetRxEventType 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.c:1044:13:UARTEx_Wakeup_AddressConfig 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.c:1062:13:UARTEx_SetNbDataToProcess 24 static diff --git a/Debug/Drivers/STM32WLxx_HAL_Driver/Src/subdir.mk b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/subdir.mk new file mode 100644 index 0000000..63eb4f2 --- /dev/null +++ b/Debug/Drivers/STM32WLxx_HAL_Driver/Src/subdir.mk @@ -0,0 +1,75 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (13.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c \ +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.c \ +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.c \ +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma_ex.c \ +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_exti.c \ +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash.c \ +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c \ +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_gpio.c \ +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.c \ +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c \ +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.c \ +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.c \ +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.c \ +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c \ +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c \ +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c \ +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.c + +OBJS += \ +./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.o \ +./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.o \ +./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.o \ +./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma_ex.o \ +./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_exti.o \ +./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash.o \ +./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.o \ +./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_gpio.o \ +./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.o \ +./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.o \ +./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.o \ +./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.o \ +./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.o \ +./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.o \ +./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.o \ +./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.o \ +./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.o + +C_DEPS += \ +./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.d \ +./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.d \ +./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.d \ +./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma_ex.d \ +./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_exti.d \ +./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash.d \ +./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.d \ +./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_gpio.d \ +./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.d \ +./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.d \ +./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.d \ +./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.d \ +./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.d \ +./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.d \ +./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.d \ +./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.d \ +./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/STM32WLxx_HAL_Driver/Src/%.o Drivers/STM32WLxx_HAL_Driver/Src/%.su Drivers/STM32WLxx_HAL_Driver/Src/%.cyclo: ../Drivers/STM32WLxx_HAL_Driver/Src/%.c Drivers/STM32WLxx_HAL_Driver/Src/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WL55xx -c -I../Core/Inc -I../SubGHz_Phy/App -I../SubGHz_Phy/Target -I../Utilities/trace/adv_trace -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Utilities/misc -I../Utilities/sequencer -I../Utilities/timer -I../Utilities/lpm/tiny_lpm -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Middlewares/Third_Party/SubGHz_Phy -I../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver -I../Drivers/CMSIS/Include -I../Drivers/BSP/STM32WLxx_Nucleo -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Drivers-2f-STM32WLxx_HAL_Driver-2f-Src + +clean-Drivers-2f-STM32WLxx_HAL_Driver-2f-Src: + -$(RM) ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.cyclo ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.d ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.o ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.su ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.cyclo ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.d ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.o ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.su ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.cyclo ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.d ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.o ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.su ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma_ex.cyclo ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma_ex.d ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma_ex.o ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma_ex.su ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_exti.cyclo ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_exti.d ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_exti.o ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_exti.su ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash.cyclo ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash.d ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash.o ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash.su ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.cyclo ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.d ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.o ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.su ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_gpio.cyclo ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_gpio.d ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_gpio.o ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_gpio.su ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.cyclo ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.d ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.o ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.su ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.cyclo ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.d ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.o ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.su ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.cyclo ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.d ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.o ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.su ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.cyclo ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.d ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.o ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.su ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.cyclo ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.d ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.o ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.su ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.cyclo ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.d ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.o ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.su ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.cyclo ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.d ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.o ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.su ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.cyclo ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.d ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.o ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.su ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.cyclo ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.d ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.o ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.su + +.PHONY: clean-Drivers-2f-STM32WLxx_HAL_Driver-2f-Src + diff --git a/Debug/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.cyclo b/Debug/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.cyclo new file mode 100644 index 0000000..50a1e06 --- /dev/null +++ b/Debug/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.cyclo @@ -0,0 +1,22 @@ +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.h:174:24:lr_fhss_get_time_on_air_numerator 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.c:324:14:lr_fhss_get_hop_sequence_count 4 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.c:334:6:lr_fhss_process_parameters 3 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.c:349:16:lr_fhss_get_hop_params 23 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.c:426:10:lr_fhss_get_next_state 4 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.c:448:9:lr_fhss_get_next_freq_in_grid 3 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.c:480:10:lr_fhss_build_frame 15 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.c:589:10:lr_fhss_get_time_on_air_in_ms 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.c:600:17:lr_fhss_payload_crc16 2 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.c:612:16:lr_fhss_header_crc8 2 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.c:624:13:lr_fhss_payload_whitening 2 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.c:638:16:lr_fhss_extract_bit_in_byte_vector 2 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.c:650:13:lr_fhss_set_bit_in_byte_vector 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.c:658:17:lr_fhss_convolution_encode_viterbi_1_2_base 4 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.c:691:17:lr_fhss_convolution_encode_viterbi_1_3_base 4 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.c:726:17:lr_fhss_convolution_encode_viterbi_1_2 2 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.c:742:17:lr_fhss_convolution_encode_viterbi_1_3 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.c:749:17:sqrt_uint16 2 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.c:761:17:lr_fhss_payload_interleaving 6 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.c:809:13:lr_fhss_raw_header 2 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.c:819:13:lr_fhss_store_header_sync_word_index 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.c:824:17:lr_fhss_get_bit_and_hop_count 6 diff --git a/Debug/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.d b/Debug/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.d new file mode 100644 index 0000000..74d4db7 --- /dev/null +++ b/Debug/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.d @@ -0,0 +1,8 @@ +Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.o: \ + ../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.c \ + ../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.h \ + ../Middlewares/Third_Party/SubGHz_Phy/radio_def.h \ + ../Middlewares/Third_Party/SubGHz_Phy/lr_fhss_v1_base_types.h +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.h: +../Middlewares/Third_Party/SubGHz_Phy/radio_def.h: +../Middlewares/Third_Party/SubGHz_Phy/lr_fhss_v1_base_types.h: diff --git a/Debug/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.o b/Debug/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.o new file mode 100644 index 0000000..6e8e5a2 Binary files /dev/null and b/Debug/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.o differ diff --git a/Debug/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.su b/Debug/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.su new file mode 100644 index 0000000..f5d979e --- /dev/null +++ b/Debug/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.su @@ -0,0 +1,22 @@ +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.h:174:24:lr_fhss_get_time_on_air_numerator 24 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.c:324:14:lr_fhss_get_hop_sequence_count 16 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.c:334:6:lr_fhss_process_parameters 24 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.c:349:16:lr_fhss_get_hop_params 32 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.c:426:10:lr_fhss_get_next_state 24 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.c:448:9:lr_fhss_get_next_freq_in_grid 32 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.c:480:10:lr_fhss_build_frame 720 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.c:589:10:lr_fhss_get_time_on_air_in_ms 16 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.c:600:17:lr_fhss_payload_crc16 24 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.c:612:16:lr_fhss_header_crc8 24 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.c:624:13:lr_fhss_payload_whitening 32 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.c:638:16:lr_fhss_extract_bit_in_byte_vector 24 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.c:650:13:lr_fhss_set_bit_in_byte_vector 32 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.c:658:17:lr_fhss_convolution_encode_viterbi_1_2_base 32 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.c:691:17:lr_fhss_convolution_encode_viterbi_1_3_base 40 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.c:726:17:lr_fhss_convolution_encode_viterbi_1_2 32 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.c:742:17:lr_fhss_convolution_encode_viterbi_1_3 32 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.c:749:17:sqrt_uint16 24 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.c:761:17:lr_fhss_payload_interleaving 56 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.c:809:13:lr_fhss_raw_header 24 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.c:819:13:lr_fhss_store_header_sync_word_index 16 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.c:824:17:lr_fhss_get_bit_and_hop_count 32 static diff --git a/Debug/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.cyclo b/Debug/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.cyclo new file mode 100644 index 0000000..4a3dba2 --- /dev/null +++ b/Debug/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.cyclo @@ -0,0 +1,44 @@ +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_gpio.h:936:22:LL_GPIO_SetOutputPin 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_gpio.h:965:22:LL_GPIO_ResetOutputPin 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:704:13:RadioInit 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:737:21:RadioGetStatus 5 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:752:13:RadioSetModem 7 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:803:13:RadioSetChannel 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:808:13:RadioIsChannelFree 3 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:845:17:RadioRandom 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:860:13:RadioSetRxConfig 17 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1049:13:RadioSetTxConfig 14 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1159:13:RadioCheckRfFrequency 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1164:17:RadioGetLoRaBandwidthInHz 11 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1205:17:RadioGetGfskTimeOnAirNumerator 3 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1214:17:RadioGetLoRaTimeOnAirNumerator 15 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1278:17:RadioTimeOnAir 3 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1311:23:RadioSend 10 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1444:13:RadioSleep 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1454:13:RadioStandby 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1459:13:RadioRx 4 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1501:13:RadioRxBoosted 4 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1542:13:RadioSetRxDutyCycle 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1554:13:RadioStartCad 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1566:13:RadioSetTxContinuousWave 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1593:16:RadioRssi 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1598:13:RadioWrite 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1603:16:RadioRead 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1608:13:RadioWriteRegisters 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1613:13:RadioReadRegisters 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1618:13:RadioSetMaxPayloadLength 3 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1635:13:RadioSetPublicNetwork 2 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1654:17:RadioGetWakeupTime 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1659:13:RadioOnTxTimeoutIrq 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1664:13:RadioOnRxTimeoutIrq 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1669:13:RadioOnTxTimeoutProcess 3 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1679:13:RadioOnRxTimeoutProcess 3 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1689:13:RadioOnDioIrq 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1696:13:RadioIrqProcess 41 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1876:13:RadioTxPrbs 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1884:13:RadioTxCw 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1894:13:payload_integration 6 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1932:16:RadioSetRxGenericConfig 24 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:2110:16:RadioSetTxGenericConfig 31 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:2348:23:RadioLrFhssSetCfg 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:2379:23:RadioLrFhssGetTimeOnAirInMs 1 diff --git a/Debug/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.d b/Debug/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.d new file mode 100644 index 0000000..21ca32d --- /dev/null +++ b/Debug/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.d @@ -0,0 +1,138 @@ +Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o: \ + ../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c \ + ../Middlewares/Third_Party/SubGHz_Phy/radio.h \ + ../Middlewares/Third_Party/SubGHz_Phy/radio_def.h \ + ../Middlewares/Third_Party/SubGHz_Phy/radio_ex.h \ + ../Middlewares/Third_Party/SubGHz_Phy/lr_fhss_v1_base_types.h \ + ../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/wl_lr_fhss.h \ + ../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.h \ + ../SubGHz_Phy/Target/radio_conf.h ../Core/Inc/platform.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wl55xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h \ + ../Core/Inc/stm32wlxx_hal_conf.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h \ + ../Core/Inc/main.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_gpio.h \ + ../Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo_radio.h \ + ../Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo_errno.h \ + ../Core/Inc/stm32wlxx_nucleo_conf.h \ + ../Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo.h ../Core/Inc/subghz.h \ + ../Utilities/misc/stm32_mem.h ../Core/Inc/utilities_conf.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Utilities/misc/stm32_tiny_vsnprintf.h ../Core/Inc/utilities_def.h \ + ../SubGHz_Phy/Target/mw_log_conf.h \ + ../Utilities/trace/adv_trace/stm32_adv_trace.h \ + ../SubGHz_Phy/Target/radio_board_if.h ../Core/Inc/utilities_def.h \ + ../Core/Inc/sys_debug.h ../Core/Inc/sys_conf.h ../Core/Inc/platform.h \ + ../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.h \ + ../Middlewares/Third_Party/SubGHz_Phy/radio_def.h \ + ../Middlewares/Third_Party/SubGHz_Phy/lr_fhss_v1_base_types.h \ + ../SubGHz_Phy/Target/timer.h ../Utilities/timer/stm32_timer.h \ + ../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.h \ + ../Middlewares/Third_Party/SubGHz_Phy/radio_ex.h \ + ../SubGHz_Phy/Target/mw_log_conf.h +../Middlewares/Third_Party/SubGHz_Phy/radio.h: +../Middlewares/Third_Party/SubGHz_Phy/radio_def.h: +../Middlewares/Third_Party/SubGHz_Phy/radio_ex.h: +../Middlewares/Third_Party/SubGHz_Phy/lr_fhss_v1_base_types.h: +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/wl_lr_fhss.h: +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.h: +../SubGHz_Phy/Target/radio_conf.h: +../Core/Inc/platform.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wl55xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h: +../Core/Inc/stm32wlxx_hal_conf.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h: +../Core/Inc/main.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_gpio.h: +../Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo_radio.h: +../Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo_errno.h: +../Core/Inc/stm32wlxx_nucleo_conf.h: +../Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo.h: +../Core/Inc/subghz.h: +../Utilities/misc/stm32_mem.h: +../Core/Inc/utilities_conf.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Utilities/misc/stm32_tiny_vsnprintf.h: +../Core/Inc/utilities_def.h: +../SubGHz_Phy/Target/mw_log_conf.h: +../Utilities/trace/adv_trace/stm32_adv_trace.h: +../SubGHz_Phy/Target/radio_board_if.h: +../Core/Inc/utilities_def.h: +../Core/Inc/sys_debug.h: +../Core/Inc/sys_conf.h: +../Core/Inc/platform.h: +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.h: +../Middlewares/Third_Party/SubGHz_Phy/radio_def.h: +../Middlewares/Third_Party/SubGHz_Phy/lr_fhss_v1_base_types.h: +../SubGHz_Phy/Target/timer.h: +../Utilities/timer/stm32_timer.h: +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.h: +../Middlewares/Third_Party/SubGHz_Phy/radio_ex.h: +../SubGHz_Phy/Target/mw_log_conf.h: diff --git a/Debug/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o b/Debug/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o new file mode 100644 index 0000000..0c45c2b Binary files /dev/null and b/Debug/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o differ diff --git a/Debug/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.su b/Debug/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.su new file mode 100644 index 0000000..7314ce1 --- /dev/null +++ b/Debug/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.su @@ -0,0 +1,44 @@ +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_gpio.h:936:22:LL_GPIO_SetOutputPin 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_gpio.h:965:22:LL_GPIO_ResetOutputPin 16 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:704:13:RadioInit 24 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:737:21:RadioGetStatus 8 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:752:13:RadioSetModem 16 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:803:13:RadioSetChannel 16 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:808:13:RadioIsChannelFree 72 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:845:17:RadioRandom 16 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:860:13:RadioSetRxConfig 48 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1049:13:RadioSetTxConfig 32 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1159:13:RadioCheckRfFrequency 16 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1164:17:RadioGetLoRaBandwidthInHz 24 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1205:17:RadioGetGfskTimeOnAirNumerator 16 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1214:17:RadioGetLoRaTimeOnAirNumerator 48 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1278:17:RadioTimeOnAir 48 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1311:23:RadioSend 24 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1444:13:RadioSleep 16 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1454:13:RadioStandby 8 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1459:13:RadioRx 16 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1501:13:RadioRxBoosted 16 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1542:13:RadioSetRxDutyCycle 16 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1554:13:RadioStartCad 8 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1566:13:RadioSetTxContinuousWave 24 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1593:16:RadioRssi 16 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1598:13:RadioWrite 16 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1603:16:RadioRead 16 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1608:13:RadioWriteRegisters 16 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1613:13:RadioReadRegisters 16 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1618:13:RadioSetMaxPayloadLength 16 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1635:13:RadioSetPublicNetwork 16 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1654:17:RadioGetWakeupTime 8 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1659:13:RadioOnTxTimeoutIrq 16 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1664:13:RadioOnRxTimeoutIrq 16 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1669:13:RadioOnTxTimeoutProcess 8 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1679:13:RadioOnRxTimeoutProcess 8 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1689:13:RadioOnDioIrq 16 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1696:13:RadioIrqProcess 24 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1876:13:RadioTxPrbs 8 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1884:13:RadioTxCw 24 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1894:13:payload_integration 40 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1932:16:RadioSetRxGenericConfig 56 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:2110:16:RadioSetTxGenericConfig 64 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:2348:23:RadioLrFhssSetCfg 24 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:2379:23:RadioLrFhssGetTimeOnAirInMs 16 static diff --git a/Debug/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.cyclo b/Debug/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.cyclo new file mode 100644 index 0000000..2fbdf3e --- /dev/null +++ b/Debug/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.cyclo @@ -0,0 +1,69 @@ +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:184:6:SUBGRF_Init 3 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:226:23:SUBGRF_GetOperatingMode 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:231:6:SUBGRF_SetPayload 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:236:9:SUBGRF_GetPayload 2 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:250:6:SUBGRF_SendPayload 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:256:9:SUBGRF_SetSyncWord 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:262:6:SUBGRF_SetCrcSeed 2 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:280:6:SUBGRF_SetCrcPolynomial 2 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:298:6:SUBGRF_SetWhiteningSeed 2 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:316:10:SUBGRF_GetRandom 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:341:6:SUBGRF_SetSleep 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:355:6:SUBGRF_SetStandby 2 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:368:6:SUBGRF_SetFs 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:374:6:SUBGRF_SetTx 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:386:6:SUBGRF_SetRx 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:398:6:SUBGRF_SetRxBoosted 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:412:6:SUBGRF_SetRxDutyCycle 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:426:6:SUBGRF_SetCad 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:432:6:SUBGRF_SetTxContinuousWave 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:437:6:SUBGRF_SetTxInfinitePreamble 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:442:6:SUBGRF_SetStopRxTimerOnPreambleDetect 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:447:6:SUBGRF_SetLoRaSymbNumTimeout 3 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:468:6:SUBGRF_SetRegulatorMode 2 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:483:6:SUBGRF_Calibrate 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:496:6:SUBGRF_CalibrateImage 6 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:534:6:SUBGRF_SetPaConfig 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:545:6:SUBGRF_SetRxTxFallbackMode 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:550:6:SUBGRF_SetDioIrqParams 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:565:10:SUBGRF_GetIrqStatus 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:573:6:SUBGRF_SetTcxoMode 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:585:6:SUBGRF_SetRfFrequency 2 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:603:6:SUBGRF_SetPacketType 2 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:615:20:SUBGRF_GetPacketType 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:620:6:SUBGRF_SetTxParams 11 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:694:6:SUBGRF_SetModulationParams 6 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:758:6:SUBGRF_SetPacketParams 7 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:822:6:SUBGRF_SetCadParams 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:837:6:SUBGRF_SetBufferBaseAddress 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:846:18:SUBGRF_GetStatus 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:857:8:SUBGRF_GetRssiInst 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:867:6:SUBGRF_GetRxBufferStatus 3 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:886:6:SUBGRF_GetPacketStatus 3 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:920:14:SUBGRF_GetDeviceErrors 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:937:6:SUBGRF_ClearDeviceErrors 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:943:6:SUBGRF_ClearIrqStatus 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:952:6:SUBGRF_WriteRegister 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:959:9:SUBGRF_ReadRegister 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:968:6:SUBGRF_WriteRegisters 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:975:6:SUBGRF_ReadRegisters 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:982:6:SUBGRF_WriteBuffer 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:989:6:SUBGRF_ReadBuffer 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:996:6:SUBGRF_WriteCommand 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:1004:6:SUBGRF_ReadCommand 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:1012:6:SUBGRF_SetSwitch 5 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:1038:9:SUBGRF_SetRfTxPower 6 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:1077:10:SUBGRF_GetRadioWakeUpTime 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:1083:6:HAL_SUBGHZ_TxCpltCallback 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:1088:6:HAL_SUBGHZ_RxCpltCallback 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:1093:6:HAL_SUBGHZ_CRCErrorCallback 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:1098:6:HAL_SUBGHZ_CADStatusCallback 3 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:1113:6:HAL_SUBGHZ_RxTxTimeoutCallback 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:1118:6:HAL_SUBGHZ_HeaderErrorCallback 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:1123:6:HAL_SUBGHZ_PreambleDetectedCallback 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:1128:6:HAL_SUBGHZ_SyncWordValidCallback 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:1133:6:HAL_SUBGHZ_HeaderValidCallback 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:1138:6:HAL_SUBGHZ_LrFhssHopCallback 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:1143:13:Radio_SMPS_Set 2 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:1154:9:SUBGRF_GetFskBandwidthRegValue 4 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:1173:6:SUBGRF_GetCFO 4 diff --git a/Debug/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.d b/Debug/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.d new file mode 100644 index 0000000..3832730 --- /dev/null +++ b/Debug/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.d @@ -0,0 +1,115 @@ +Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o: \ + ../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c \ + ../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.h \ + ../SubGHz_Phy/Target/radio_conf.h ../Core/Inc/platform.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wl55xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h \ + ../Core/Inc/stm32wlxx_hal_conf.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h \ + ../Core/Inc/main.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_gpio.h \ + ../Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo_radio.h \ + ../Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo_errno.h \ + ../Core/Inc/stm32wlxx_nucleo_conf.h \ + ../Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo.h ../Core/Inc/subghz.h \ + ../Utilities/misc/stm32_mem.h ../Core/Inc/utilities_conf.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Utilities/misc/stm32_tiny_vsnprintf.h ../Core/Inc/utilities_def.h \ + ../SubGHz_Phy/Target/mw_log_conf.h \ + ../Utilities/trace/adv_trace/stm32_adv_trace.h \ + ../SubGHz_Phy/Target/radio_board_if.h ../Core/Inc/utilities_def.h \ + ../Core/Inc/sys_debug.h ../Core/Inc/sys_conf.h ../Core/Inc/platform.h \ + ../SubGHz_Phy/Target/mw_log_conf.h +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.h: +../SubGHz_Phy/Target/radio_conf.h: +../Core/Inc/platform.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wl55xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h: +../Core/Inc/stm32wlxx_hal_conf.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h: +../Core/Inc/main.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_gpio.h: +../Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo_radio.h: +../Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo_errno.h: +../Core/Inc/stm32wlxx_nucleo_conf.h: +../Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo.h: +../Core/Inc/subghz.h: +../Utilities/misc/stm32_mem.h: +../Core/Inc/utilities_conf.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Utilities/misc/stm32_tiny_vsnprintf.h: +../Core/Inc/utilities_def.h: +../SubGHz_Phy/Target/mw_log_conf.h: +../Utilities/trace/adv_trace/stm32_adv_trace.h: +../SubGHz_Phy/Target/radio_board_if.h: +../Core/Inc/utilities_def.h: +../Core/Inc/sys_debug.h: +../Core/Inc/sys_conf.h: +../Core/Inc/platform.h: +../SubGHz_Phy/Target/mw_log_conf.h: diff --git a/Debug/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o b/Debug/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o new file mode 100644 index 0000000..ddb61d7 Binary files /dev/null and b/Debug/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o differ diff --git a/Debug/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.su b/Debug/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.su new file mode 100644 index 0000000..acd67fd --- /dev/null +++ b/Debug/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.su @@ -0,0 +1,69 @@ +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:184:6:SUBGRF_Init 24 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:226:23:SUBGRF_GetOperatingMode 4 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:231:6:SUBGRF_SetPayload 16 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:236:9:SUBGRF_GetPayload 32 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:250:6:SUBGRF_SendPayload 24 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:256:9:SUBGRF_SetSyncWord 16 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:262:6:SUBGRF_SetCrcSeed 24 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:280:6:SUBGRF_SetCrcPolynomial 24 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:298:6:SUBGRF_SetWhiteningSeed 24 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:316:10:SUBGRF_GetRandom 16 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:341:6:SUBGRF_SetSleep 24 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:355:6:SUBGRF_SetStandby 16 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:368:6:SUBGRF_SetFs 8 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:374:6:SUBGRF_SetTx 24 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:386:6:SUBGRF_SetRx 24 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:398:6:SUBGRF_SetRxBoosted 24 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:412:6:SUBGRF_SetRxDutyCycle 24 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:426:6:SUBGRF_SetCad 8 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:432:6:SUBGRF_SetTxContinuousWave 8 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:437:6:SUBGRF_SetTxInfinitePreamble 8 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:442:6:SUBGRF_SetStopRxTimerOnPreambleDetect 16 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:447:6:SUBGRF_SetLoRaSymbNumTimeout 24 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:468:6:SUBGRF_SetRegulatorMode 16 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:483:6:SUBGRF_Calibrate 24 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:496:6:SUBGRF_CalibrateImage 24 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:534:6:SUBGRF_SetPaConfig 32 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:545:6:SUBGRF_SetRxTxFallbackMode 16 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:550:6:SUBGRF_SetDioIrqParams 32 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:565:10:SUBGRF_GetIrqStatus 16 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:573:6:SUBGRF_SetTcxoMode 24 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:585:6:SUBGRF_SetRfFrequency 40 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:603:6:SUBGRF_SetPacketType 16 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:615:20:SUBGRF_GetPacketType 4 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:620:6:SUBGRF_SetTxParams 24 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:694:6:SUBGRF_SetModulationParams 48 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:758:6:SUBGRF_SetPacketParams 32 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:822:6:SUBGRF_SetCadParams 32 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:837:6:SUBGRF_SetBufferBaseAddress 24 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:846:18:SUBGRF_GetStatus 16 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:857:8:SUBGRF_GetRssiInst 16 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:867:6:SUBGRF_GetRxBufferStatus 24 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:886:6:SUBGRF_GetPacketStatus 24 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:920:14:SUBGRF_GetDeviceErrors 16 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:937:6:SUBGRF_ClearDeviceErrors 16 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:943:6:SUBGRF_ClearIrqStatus 24 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:952:6:SUBGRF_WriteRegister 32 static,ignoring_inline_asm +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:959:9:SUBGRF_ReadRegister 32 static,ignoring_inline_asm +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:968:6:SUBGRF_WriteRegisters 32 static,ignoring_inline_asm +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:975:6:SUBGRF_ReadRegisters 32 static,ignoring_inline_asm +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:982:6:SUBGRF_WriteBuffer 32 static,ignoring_inline_asm +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:989:6:SUBGRF_ReadBuffer 32 static,ignoring_inline_asm +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:996:6:SUBGRF_WriteCommand 32 static,ignoring_inline_asm +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:1004:6:SUBGRF_ReadCommand 32 static,ignoring_inline_asm +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:1012:6:SUBGRF_SetSwitch 24 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:1038:9:SUBGRF_SetRfTxPower 24 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:1077:10:SUBGRF_GetRadioWakeUpTime 4 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:1083:6:HAL_SUBGHZ_TxCpltCallback 16 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:1088:6:HAL_SUBGHZ_RxCpltCallback 16 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:1093:6:HAL_SUBGHZ_CRCErrorCallback 16 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:1098:6:HAL_SUBGHZ_CADStatusCallback 16 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:1113:6:HAL_SUBGHZ_RxTxTimeoutCallback 16 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:1118:6:HAL_SUBGHZ_HeaderErrorCallback 16 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:1123:6:HAL_SUBGHZ_PreambleDetectedCallback 16 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:1128:6:HAL_SUBGHZ_SyncWordValidCallback 16 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:1133:6:HAL_SUBGHZ_HeaderValidCallback 16 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:1138:6:HAL_SUBGHZ_LrFhssHopCallback 16 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:1143:13:Radio_SMPS_Set 24 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:1154:9:SUBGRF_GetFskBandwidthRegValue 24 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:1173:6:SUBGRF_GetCFO 48 static diff --git a/Debug/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.cyclo b/Debug/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.cyclo new file mode 100644 index 0000000..f4e3976 --- /dev/null +++ b/Debug/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.cyclo @@ -0,0 +1,29 @@ +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h:1173:26:LL_DBGMCU_GetRevisionID 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_gpio.h:936:22:LL_GPIO_SetOutputPin 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_gpio.h:965:22:LL_GPIO_ResetOutputPin 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.c:257:9:RFW_TransmitLongPacket 15 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.c:422:9:RFW_ReceiveLongPacket 5 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.c:474:9:RFW_Init 6 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.c:552:6:RFW_DeInit 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.c:559:9:RFW_Is_Init 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.c:568:9:RFW_Is_LongPacketModeEnabled 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.c:577:6:RFW_SetAntSwitch 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.c:584:9:RFW_TransmitInit 4 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.c:636:9:RFW_ReceiveInit 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.c:659:6:RFW_DeInit_TxLongPacket 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.c:669:6:RFW_ReceivePayload 5 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.c:724:6:RFW_SetRadioModem 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.c:733:13:RFW_TransmitLongPacket_NewTxChunkTimerEvent 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.c:738:13:RFW_TransmitLongPacket_TxChunkProcess 5 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.c:822:13:RFW_WhiteInitState 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.c:827:13:RFW_WhiteSetState 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.c:832:13:RFW_CrcInitState 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.c:840:13:RFW_CrcSetState 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.c:845:13:RFW_WhiteRun 3 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.c:861:16:RFW_CrcRun 3 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.c:890:10:RFW_CrcRun1Byte 3 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.c:909:16:RFW_PollRxBytes 3 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.c:929:16:RFW_GetPacketLength 4 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.c:959:13:RFW_GetPayloadTimerEvent 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.c:964:13:RFW_GetPayloadProcess 8 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.c:1053:13:RFW_GetPayload 7 diff --git a/Debug/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.d b/Debug/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.d new file mode 100644 index 0000000..4c91012 --- /dev/null +++ b/Debug/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.d @@ -0,0 +1,124 @@ +Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.o: \ + ../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.c \ + ../SubGHz_Phy/Target/timer.h ../Utilities/timer/stm32_timer.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h ../Core/Inc/utilities_conf.h \ + ../Utilities/misc/stm32_mem.h ../Utilities/misc/stm32_tiny_vsnprintf.h \ + ../Core/Inc/utilities_def.h \ + ../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.h \ + ../Middlewares/Third_Party/SubGHz_Phy/radio_def.h \ + ../Middlewares/Third_Party/SubGHz_Phy/radio_ex.h \ + ../SubGHz_Phy/Target/radio_conf.h ../Core/Inc/platform.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wl55xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h \ + ../Core/Inc/stm32wlxx_hal_conf.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h \ + ../Core/Inc/main.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_gpio.h \ + ../Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo_radio.h \ + ../Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo_errno.h \ + ../Core/Inc/stm32wlxx_nucleo_conf.h \ + ../Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo.h ../Core/Inc/subghz.h \ + ../SubGHz_Phy/Target/mw_log_conf.h \ + ../Utilities/trace/adv_trace/stm32_adv_trace.h \ + ../SubGHz_Phy/Target/radio_board_if.h ../Core/Inc/utilities_def.h \ + ../Core/Inc/sys_debug.h ../Core/Inc/sys_conf.h ../Core/Inc/platform.h \ + ../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.h \ + ../SubGHz_Phy/Target/mw_log_conf.h +../SubGHz_Phy/Target/timer.h: +../Utilities/timer/stm32_timer.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Core/Inc/utilities_conf.h: +../Utilities/misc/stm32_mem.h: +../Utilities/misc/stm32_tiny_vsnprintf.h: +../Core/Inc/utilities_def.h: +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.h: +../Middlewares/Third_Party/SubGHz_Phy/radio_def.h: +../Middlewares/Third_Party/SubGHz_Phy/radio_ex.h: +../SubGHz_Phy/Target/radio_conf.h: +../Core/Inc/platform.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wl55xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h: +../Core/Inc/stm32wlxx_hal_conf.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h: +../Core/Inc/main.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_gpio.h: +../Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo_radio.h: +../Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo_errno.h: +../Core/Inc/stm32wlxx_nucleo_conf.h: +../Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo.h: +../Core/Inc/subghz.h: +../SubGHz_Phy/Target/mw_log_conf.h: +../Utilities/trace/adv_trace/stm32_adv_trace.h: +../SubGHz_Phy/Target/radio_board_if.h: +../Core/Inc/utilities_def.h: +../Core/Inc/sys_debug.h: +../Core/Inc/sys_conf.h: +../Core/Inc/platform.h: +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.h: +../SubGHz_Phy/Target/mw_log_conf.h: diff --git a/Debug/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.o b/Debug/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.o new file mode 100644 index 0000000..540925a Binary files /dev/null and b/Debug/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.o differ diff --git a/Debug/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.su b/Debug/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.su new file mode 100644 index 0000000..47aa6fa --- /dev/null +++ b/Debug/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.su @@ -0,0 +1,29 @@ +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h:1173:26:LL_DBGMCU_GetRevisionID 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_gpio.h:936:22:LL_GPIO_SetOutputPin 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_gpio.h:965:22:LL_GPIO_ResetOutputPin 16 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.c:257:9:RFW_TransmitLongPacket 64 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.c:422:9:RFW_ReceiveLongPacket 32 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.c:474:9:RFW_Init 48 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.c:552:6:RFW_DeInit 4 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.c:559:9:RFW_Is_Init 4 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.c:568:9:RFW_Is_LongPacketModeEnabled 4 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.c:577:6:RFW_SetAntSwitch 16 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.c:584:9:RFW_TransmitInit 32 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.c:636:9:RFW_ReceiveInit 8 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.c:659:6:RFW_DeInit_TxLongPacket 16 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.c:669:6:RFW_ReceivePayload 32 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.c:724:6:RFW_SetRadioModem 16 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.c:733:13:RFW_TransmitLongPacket_NewTxChunkTimerEvent 16 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.c:738:13:RFW_TransmitLongPacket_TxChunkProcess 64 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.c:822:13:RFW_WhiteInitState 16 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.c:827:13:RFW_WhiteSetState 16 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.c:832:13:RFW_CrcInitState 24 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.c:840:13:RFW_CrcSetState 16 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.c:845:13:RFW_WhiteRun 40 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.c:861:16:RFW_CrcRun 40 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.c:890:10:RFW_CrcRun1Byte 24 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.c:909:16:RFW_PollRxBytes 32 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.c:929:16:RFW_GetPacketLength 32 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.c:959:13:RFW_GetPayloadTimerEvent 16 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.c:964:13:RFW_GetPayloadProcess 32 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.c:1053:13:RFW_GetPayload 48 static diff --git a/Debug/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/subdir.mk b/Debug/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/subdir.mk new file mode 100644 index 0000000..d7e2ba1 --- /dev/null +++ b/Debug/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/subdir.mk @@ -0,0 +1,39 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (13.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.c \ +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c \ +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c \ +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.c \ +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/wl_lr_fhss.c + +OBJS += \ +./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.o \ +./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o \ +./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o \ +./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.o \ +./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/wl_lr_fhss.o + +C_DEPS += \ +./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.d \ +./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.d \ +./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.d \ +./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.d \ +./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/wl_lr_fhss.d + + +# Each subdirectory must supply rules for building sources it contributes +Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/%.o Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/%.su Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/%.cyclo: ../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/%.c Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WL55xx -c -I../Core/Inc -I../SubGHz_Phy/App -I../SubGHz_Phy/Target -I../Utilities/trace/adv_trace -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Utilities/misc -I../Utilities/sequencer -I../Utilities/timer -I../Utilities/lpm/tiny_lpm -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Middlewares/Third_Party/SubGHz_Phy -I../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver -I../Drivers/CMSIS/Include -I../Drivers/BSP/STM32WLxx_Nucleo -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Middlewares-2f-Third_Party-2f-SubGHz_Phy-2f-stm32_radio_driver + +clean-Middlewares-2f-Third_Party-2f-SubGHz_Phy-2f-stm32_radio_driver: + -$(RM) ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.cyclo ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.d ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.o ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.su ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.cyclo ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.d ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.su ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.cyclo ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.d ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.su ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.cyclo ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.d ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.o ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.su ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/wl_lr_fhss.cyclo ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/wl_lr_fhss.d ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/wl_lr_fhss.o ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/wl_lr_fhss.su + +.PHONY: clean-Middlewares-2f-Third_Party-2f-SubGHz_Phy-2f-stm32_radio_driver + diff --git a/Debug/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/wl_lr_fhss.cyclo b/Debug/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/wl_lr_fhss.cyclo new file mode 100644 index 0000000..0df5957 --- /dev/null +++ b/Debug/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/wl_lr_fhss.cyclo @@ -0,0 +1,11 @@ +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/wl_lr_fhss.c:134:16:wl_lr_fhss_init 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/wl_lr_fhss.c:150:16:wl_lr_fhss_process_parameters 12 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/wl_lr_fhss.c:200:16:wl_lr_fhss_write_hop_sequence_head 10 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/wl_lr_fhss.c:276:16:wl_lr_fhss_write_payload 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/wl_lr_fhss.c:284:16:wl_lr_fhss_build_frame 4 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/wl_lr_fhss.c:314:16:wl_lr_fhss_handle_hop 4 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/wl_lr_fhss.c:342:16:wl_lr_fhss_handle_tx_done 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/wl_lr_fhss.c:357:16:wl_lr_fhss_write_hop_config 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/wl_lr_fhss.c:366:16:wl_lr_fhss_write_hop 2 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/wl_lr_fhss.c:388:10:wl_lr_fhss_get_next_freq_in_pll_steps 5 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/wl_lr_fhss.c:420:28:wl_lr_fhss_get_grid_in_pll_steps 2 diff --git a/Debug/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/wl_lr_fhss.d b/Debug/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/wl_lr_fhss.d new file mode 100644 index 0000000..c399038 --- /dev/null +++ b/Debug/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/wl_lr_fhss.d @@ -0,0 +1,121 @@ +Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/wl_lr_fhss.o: \ + ../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/wl_lr_fhss.c \ + ../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/wl_lr_fhss.h \ + ../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.h \ + ../SubGHz_Phy/Target/radio_conf.h ../Core/Inc/platform.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wl55xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h \ + ../Core/Inc/stm32wlxx_hal_conf.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h \ + ../Core/Inc/main.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_gpio.h \ + ../Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo_radio.h \ + ../Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo_errno.h \ + ../Core/Inc/stm32wlxx_nucleo_conf.h \ + ../Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo.h ../Core/Inc/subghz.h \ + ../Utilities/misc/stm32_mem.h ../Core/Inc/utilities_conf.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Utilities/misc/stm32_tiny_vsnprintf.h ../Core/Inc/utilities_def.h \ + ../SubGHz_Phy/Target/mw_log_conf.h \ + ../Utilities/trace/adv_trace/stm32_adv_trace.h \ + ../SubGHz_Phy/Target/radio_board_if.h ../Core/Inc/utilities_def.h \ + ../Core/Inc/sys_debug.h ../Core/Inc/sys_conf.h ../Core/Inc/platform.h \ + ../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.h \ + ../Middlewares/Third_Party/SubGHz_Phy/radio_def.h \ + ../Middlewares/Third_Party/SubGHz_Phy/lr_fhss_v1_base_types.h +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/wl_lr_fhss.h: +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.h: +../SubGHz_Phy/Target/radio_conf.h: +../Core/Inc/platform.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wl55xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h: +../Core/Inc/stm32wlxx_hal_conf.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h: +../Core/Inc/main.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_gpio.h: +../Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo_radio.h: +../Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo_errno.h: +../Core/Inc/stm32wlxx_nucleo_conf.h: +../Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo.h: +../Core/Inc/subghz.h: +../Utilities/misc/stm32_mem.h: +../Core/Inc/utilities_conf.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Utilities/misc/stm32_tiny_vsnprintf.h: +../Core/Inc/utilities_def.h: +../SubGHz_Phy/Target/mw_log_conf.h: +../Utilities/trace/adv_trace/stm32_adv_trace.h: +../SubGHz_Phy/Target/radio_board_if.h: +../Core/Inc/utilities_def.h: +../Core/Inc/sys_debug.h: +../Core/Inc/sys_conf.h: +../Core/Inc/platform.h: +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.h: +../Middlewares/Third_Party/SubGHz_Phy/radio_def.h: +../Middlewares/Third_Party/SubGHz_Phy/lr_fhss_v1_base_types.h: diff --git a/Debug/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/wl_lr_fhss.o b/Debug/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/wl_lr_fhss.o new file mode 100644 index 0000000..ea6c0cd Binary files /dev/null and b/Debug/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/wl_lr_fhss.o differ diff --git a/Debug/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/wl_lr_fhss.su b/Debug/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/wl_lr_fhss.su new file mode 100644 index 0000000..eab3158 --- /dev/null +++ b/Debug/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/wl_lr_fhss.su @@ -0,0 +1,11 @@ +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/wl_lr_fhss.c:134:16:wl_lr_fhss_init 40 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/wl_lr_fhss.c:150:16:wl_lr_fhss_process_parameters 32 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/wl_lr_fhss.c:200:16:wl_lr_fhss_write_hop_sequence_head 24 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/wl_lr_fhss.c:276:16:wl_lr_fhss_write_payload 16 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/wl_lr_fhss.c:284:16:wl_lr_fhss_build_frame 296 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/wl_lr_fhss.c:314:16:wl_lr_fhss_handle_hop 24 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/wl_lr_fhss.c:342:16:wl_lr_fhss_handle_tx_done 16 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/wl_lr_fhss.c:357:16:wl_lr_fhss_write_hop_config 24 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/wl_lr_fhss.c:366:16:wl_lr_fhss_write_hop 24 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/wl_lr_fhss.c:388:10:wl_lr_fhss_get_next_freq_in_pll_steps 40 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/wl_lr_fhss.c:420:28:wl_lr_fhss_get_grid_in_pll_steps 16 static diff --git a/Debug/SubGHz_Phy/App/app_subghz_phy.cyclo b/Debug/SubGHz_Phy/App/app_subghz_phy.cyclo new file mode 100644 index 0000000..908bb09 --- /dev/null +++ b/Debug/SubGHz_Phy/App/app_subghz_phy.cyclo @@ -0,0 +1,2 @@ +../SubGHz_Phy/App/app_subghz_phy.c:6:6:MX_SubGHz_Phy_Init 1 +../SubGHz_Phy/App/app_subghz_phy.c:12:6:MX_SubGHz_Phy_Process 1 diff --git a/Debug/SubGHz_Phy/App/app_subghz_phy.d b/Debug/SubGHz_Phy/App/app_subghz_phy.d new file mode 100644 index 0000000..4a168f6 --- /dev/null +++ b/Debug/SubGHz_Phy/App/app_subghz_phy.d @@ -0,0 +1,20 @@ +SubGHz_Phy/App/app_subghz_phy.o: ../SubGHz_Phy/App/app_subghz_phy.c \ + ../SubGHz_Phy/App/app_subghz_phy.h ../SubGHz_Phy/App/subghz_phy_app.h \ + ../Core/Inc/sys_app.h ../Core/Inc/sys_conf.h \ + ../Utilities/trace/adv_trace/stm32_adv_trace.h \ + ../Core/Inc/utilities_conf.h ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h ../Utilities/misc/stm32_mem.h \ + ../Utilities/misc/stm32_tiny_vsnprintf.h ../Core/Inc/utilities_def.h \ + ../Utilities/sequencer/stm32_seq.h +../SubGHz_Phy/App/app_subghz_phy.h: +../SubGHz_Phy/App/subghz_phy_app.h: +../Core/Inc/sys_app.h: +../Core/Inc/sys_conf.h: +../Utilities/trace/adv_trace/stm32_adv_trace.h: +../Core/Inc/utilities_conf.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Utilities/misc/stm32_mem.h: +../Utilities/misc/stm32_tiny_vsnprintf.h: +../Core/Inc/utilities_def.h: +../Utilities/sequencer/stm32_seq.h: diff --git a/Debug/SubGHz_Phy/App/app_subghz_phy.o b/Debug/SubGHz_Phy/App/app_subghz_phy.o new file mode 100644 index 0000000..f156931 Binary files /dev/null and b/Debug/SubGHz_Phy/App/app_subghz_phy.o differ diff --git a/Debug/SubGHz_Phy/App/app_subghz_phy.su b/Debug/SubGHz_Phy/App/app_subghz_phy.su new file mode 100644 index 0000000..73d62d6 --- /dev/null +++ b/Debug/SubGHz_Phy/App/app_subghz_phy.su @@ -0,0 +1,2 @@ +../SubGHz_Phy/App/app_subghz_phy.c:6:6:MX_SubGHz_Phy_Init 8 static +../SubGHz_Phy/App/app_subghz_phy.c:12:6:MX_SubGHz_Phy_Process 8 static diff --git a/Debug/SubGHz_Phy/App/subdir.mk b/Debug/SubGHz_Phy/App/subdir.mk new file mode 100644 index 0000000..4b9e0c0 --- /dev/null +++ b/Debug/SubGHz_Phy/App/subdir.mk @@ -0,0 +1,30 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (13.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../SubGHz_Phy/App/app_subghz_phy.c \ +../SubGHz_Phy/App/subghz_phy_app.c + +OBJS += \ +./SubGHz_Phy/App/app_subghz_phy.o \ +./SubGHz_Phy/App/subghz_phy_app.o + +C_DEPS += \ +./SubGHz_Phy/App/app_subghz_phy.d \ +./SubGHz_Phy/App/subghz_phy_app.d + + +# Each subdirectory must supply rules for building sources it contributes +SubGHz_Phy/App/%.o SubGHz_Phy/App/%.su SubGHz_Phy/App/%.cyclo: ../SubGHz_Phy/App/%.c SubGHz_Phy/App/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WL55xx -c -I../Core/Inc -I../SubGHz_Phy/App -I../SubGHz_Phy/Target -I../Utilities/trace/adv_trace -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Utilities/misc -I../Utilities/sequencer -I../Utilities/timer -I../Utilities/lpm/tiny_lpm -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Middlewares/Third_Party/SubGHz_Phy -I../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver -I../Drivers/CMSIS/Include -I../Drivers/BSP/STM32WLxx_Nucleo -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-SubGHz_Phy-2f-App + +clean-SubGHz_Phy-2f-App: + -$(RM) ./SubGHz_Phy/App/app_subghz_phy.cyclo ./SubGHz_Phy/App/app_subghz_phy.d ./SubGHz_Phy/App/app_subghz_phy.o ./SubGHz_Phy/App/app_subghz_phy.su ./SubGHz_Phy/App/subghz_phy_app.cyclo ./SubGHz_Phy/App/subghz_phy_app.d ./SubGHz_Phy/App/subghz_phy_app.o ./SubGHz_Phy/App/subghz_phy_app.su + +.PHONY: clean-SubGHz_Phy-2f-App + diff --git a/Debug/SubGHz_Phy/App/subghz_phy_app.cyclo b/Debug/SubGHz_Phy/App/subghz_phy_app.cyclo new file mode 100644 index 0000000..26d3421 --- /dev/null +++ b/Debug/SubGHz_Phy/App/subghz_phy_app.cyclo @@ -0,0 +1,33 @@ +../SubGHz_Phy/App/subghz_phy_app.c:146:6:SubghzApp_Init 1 +../SubGHz_Phy/App/subghz_phy_app.c:165:6:SubghzApp_Process 1 +../SubGHz_Phy/App/subghz_phy_app.c:173:13:App_ProcessRadioEvents 10 +../SubGHz_Phy/App/subghz_phy_app.c:221:13:App_ProcessUartPacketizer 5 +../SubGHz_Phy/App/subghz_phy_app.c:238:13:App_ProcessEscape 8 +../SubGHz_Phy/App/subghz_phy_app.c:267:13:App_StartNextTxIfPossible 4 +../SubGHz_Phy/App/subghz_phy_app.c:279:13:App_RadioApplyConfig 1 +../SubGHz_Phy/App/subghz_phy_app.c:285:13:App_RadioConfigureRx 2 +../SubGHz_Phy/App/subghz_phy_app.c:315:13:App_RadioConfigureTx 2 +../SubGHz_Phy/App/subghz_phy_app.c:341:13:App_RadioEnterRx 1 +../SubGHz_Phy/App/subghz_phy_app.c:347:13:App_EnterConfigMode 1 +../SubGHz_Phy/App/subghz_phy_app.c:356:13:App_ExitConfigMode 1 +../SubGHz_Phy/App/subghz_phy_app.c:365:13:App_ResetDataPath 1 +../SubGHz_Phy/App/subghz_phy_app.c:375:13:App_DataModeFeedByte 3 +../SubGHz_Phy/App/subghz_phy_app.c:395:13:App_DataModeFlushBuilder 3 +../SubGHz_Phy/App/subghz_phy_app.c:409:16:App_QueuePush 4 +../SubGHz_Phy/App/subghz_phy_app.c:423:13:App_QueuePop 2 +../SubGHz_Phy/App/subghz_phy_app.c:434:13:UartRxByteCallback 13 +../SubGHz_Phy/App/subghz_phy_app.c:497:13:App_ConfigFeedByte 9 +../SubGHz_Phy/App/subghz_phy_app.c:529:13:App_ConfigExecuteLine 33 +../SubGHz_Phy/App/subghz_phy_app.c:704:13:App_PrintConfigPrompt 2 +../SubGHz_Phy/App/subghz_phy_app.c:712:13:App_PrintHelp 1 +../SubGHz_Phy/App/subghz_phy_app.c:730:13:App_PrintStatus 2 +../SubGHz_Phy/App/subghz_phy_app.c:752:13:App_Printf 3 +../SubGHz_Phy/App/subghz_phy_app.c:775:13:App_Write 3 +../SubGHz_Phy/App/subghz_phy_app.c:785:13:App_ReconfigureUart 5 +../SubGHz_Phy/App/subghz_phy_app.c:811:16:App_ParseHexSyncWord 11 +../SubGHz_Phy/App/subghz_phy_app.c:859:14:App_SkipSpaces 4 +../SubGHz_Phy/App/subghz_phy_app.c:868:13:OnTxDone 1 +../SubGHz_Phy/App/subghz_phy_app.c:873:13:OnRxDone 2 +../SubGHz_Phy/App/subghz_phy_app.c:888:13:OnTxTimeout 1 +../SubGHz_Phy/App/subghz_phy_app.c:893:13:OnRxTimeout 1 +../SubGHz_Phy/App/subghz_phy_app.c:898:13:OnRxError 1 diff --git a/Debug/SubGHz_Phy/App/subghz_phy_app.d b/Debug/SubGHz_Phy/App/subghz_phy_app.d new file mode 100644 index 0000000..85b1701 --- /dev/null +++ b/Debug/SubGHz_Phy/App/subghz_phy_app.d @@ -0,0 +1,115 @@ +SubGHz_Phy/App/subghz_phy_app.o: ../SubGHz_Phy/App/subghz_phy_app.c \ + ../Core/Inc/platform.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wl55xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h \ + ../Core/Inc/stm32wlxx_hal_conf.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h \ + ../Core/Inc/main.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_gpio.h \ + ../Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo_radio.h \ + ../Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo_errno.h \ + ../Core/Inc/stm32wlxx_nucleo_conf.h \ + ../Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo.h \ + ../SubGHz_Phy/App/subghz_phy_app.h \ + ../Middlewares/Third_Party/SubGHz_Phy/radio.h \ + ../Middlewares/Third_Party/SubGHz_Phy/radio_def.h \ + ../Middlewares/Third_Party/SubGHz_Phy/radio_ex.h \ + ../Middlewares/Third_Party/SubGHz_Phy/lr_fhss_v1_base_types.h \ + ../Core/Inc/usart_if.h ../Utilities/trace/adv_trace/stm32_adv_trace.h \ + ../Core/Inc/utilities_conf.h ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Utilities/misc/stm32_mem.h ../Utilities/misc/stm32_tiny_vsnprintf.h \ + ../Core/Inc/utilities_def.h ../Core/Inc/usart.h ../Core/Inc/dma.h \ + ../Core/Inc/usart.h ../Core/Inc/main.h +../Core/Inc/platform.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wl55xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h: +../Core/Inc/stm32wlxx_hal_conf.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h: +../Core/Inc/main.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_gpio.h: +../Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo_radio.h: +../Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo_errno.h: +../Core/Inc/stm32wlxx_nucleo_conf.h: +../Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo.h: +../SubGHz_Phy/App/subghz_phy_app.h: +../Middlewares/Third_Party/SubGHz_Phy/radio.h: +../Middlewares/Third_Party/SubGHz_Phy/radio_def.h: +../Middlewares/Third_Party/SubGHz_Phy/radio_ex.h: +../Middlewares/Third_Party/SubGHz_Phy/lr_fhss_v1_base_types.h: +../Core/Inc/usart_if.h: +../Utilities/trace/adv_trace/stm32_adv_trace.h: +../Core/Inc/utilities_conf.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Utilities/misc/stm32_mem.h: +../Utilities/misc/stm32_tiny_vsnprintf.h: +../Core/Inc/utilities_def.h: +../Core/Inc/usart.h: +../Core/Inc/dma.h: +../Core/Inc/usart.h: +../Core/Inc/main.h: diff --git a/Debug/SubGHz_Phy/App/subghz_phy_app.o b/Debug/SubGHz_Phy/App/subghz_phy_app.o new file mode 100644 index 0000000..8d514ac Binary files /dev/null and b/Debug/SubGHz_Phy/App/subghz_phy_app.o differ diff --git a/Debug/SubGHz_Phy/App/subghz_phy_app.su b/Debug/SubGHz_Phy/App/subghz_phy_app.su new file mode 100644 index 0000000..c32902d --- /dev/null +++ b/Debug/SubGHz_Phy/App/subghz_phy_app.su @@ -0,0 +1,33 @@ +../SubGHz_Phy/App/subghz_phy_app.c:146:6:SubghzApp_Init 8 static +../SubGHz_Phy/App/subghz_phy_app.c:165:6:SubghzApp_Process 8 static +../SubGHz_Phy/App/subghz_phy_app.c:173:13:App_ProcessRadioEvents 8 static +../SubGHz_Phy/App/subghz_phy_app.c:221:13:App_ProcessUartPacketizer 16 static +../SubGHz_Phy/App/subghz_phy_app.c:238:13:App_ProcessEscape 16 static +../SubGHz_Phy/App/subghz_phy_app.c:267:13:App_StartNextTxIfPossible 16 static +../SubGHz_Phy/App/subghz_phy_app.c:279:13:App_RadioApplyConfig 8 static +../SubGHz_Phy/App/subghz_phy_app.c:285:13:App_RadioConfigureRx 72 static +../SubGHz_Phy/App/subghz_phy_app.c:315:13:App_RadioConfigureTx 48 static +../SubGHz_Phy/App/subghz_phy_app.c:341:13:App_RadioEnterRx 8 static +../SubGHz_Phy/App/subghz_phy_app.c:347:13:App_EnterConfigMode 8 static +../SubGHz_Phy/App/subghz_phy_app.c:356:13:App_ExitConfigMode 8 static +../SubGHz_Phy/App/subghz_phy_app.c:365:13:App_ResetDataPath 4 static +../SubGHz_Phy/App/subghz_phy_app.c:375:13:App_DataModeFeedByte 16 static +../SubGHz_Phy/App/subghz_phy_app.c:395:13:App_DataModeFlushBuilder 8 static +../SubGHz_Phy/App/subghz_phy_app.c:409:16:App_QueuePush 16 static +../SubGHz_Phy/App/subghz_phy_app.c:423:13:App_QueuePop 4 static +../SubGHz_Phy/App/subghz_phy_app.c:434:13:UartRxByteCallback 24 static +../SubGHz_Phy/App/subghz_phy_app.c:497:13:App_ConfigFeedByte 16 static +../SubGHz_Phy/App/subghz_phy_app.c:529:13:App_ConfigExecuteLine 32 static +../SubGHz_Phy/App/subghz_phy_app.c:704:13:App_PrintConfigPrompt 8 static +../SubGHz_Phy/App/subghz_phy_app.c:712:13:App_PrintHelp 8 static +../SubGHz_Phy/App/subghz_phy_app.c:730:13:App_PrintStatus 8 static +../SubGHz_Phy/App/subghz_phy_app.c:752:13:App_Printf 208 static +../SubGHz_Phy/App/subghz_phy_app.c:775:13:App_Write 16 static +../SubGHz_Phy/App/subghz_phy_app.c:785:13:App_ReconfigureUart 16 static +../SubGHz_Phy/App/subghz_phy_app.c:811:16:App_ParseHexSyncWord 40 static +../SubGHz_Phy/App/subghz_phy_app.c:859:14:App_SkipSpaces 16 static +../SubGHz_Phy/App/subghz_phy_app.c:868:13:OnTxDone 4 static +../SubGHz_Phy/App/subghz_phy_app.c:873:13:OnRxDone 24 static +../SubGHz_Phy/App/subghz_phy_app.c:888:13:OnTxTimeout 4 static +../SubGHz_Phy/App/subghz_phy_app.c:893:13:OnRxTimeout 4 static +../SubGHz_Phy/App/subghz_phy_app.c:898:13:OnRxError 4 static diff --git a/Debug/SubGHz_Phy/Target/radio_board_if.cyclo b/Debug/SubGHz_Phy/Target/radio_board_if.cyclo new file mode 100644 index 0000000..e13c7eb --- /dev/null +++ b/Debug/SubGHz_Phy/Target/radio_board_if.cyclo @@ -0,0 +1,7 @@ +../SubGHz_Phy/Target/radio_board_if.c:59:9:RBI_Init 1 +../SubGHz_Phy/Target/radio_board_if.c:85:9:RBI_DeInit 1 +../SubGHz_Phy/Target/radio_board_if.c:111:9:RBI_ConfigRFSwitch 1 +../SubGHz_Phy/Target/radio_board_if.c:138:9:RBI_GetTxConfig 1 +../SubGHz_Phy/Target/radio_board_if.c:164:9:RBI_IsTCXO 1 +../SubGHz_Phy/Target/radio_board_if.c:190:9:RBI_IsDCDC 1 +../SubGHz_Phy/Target/radio_board_if.c:216:9:RBI_GetRFOMaxPowerConfig 1 diff --git a/Debug/SubGHz_Phy/Target/radio_board_if.d b/Debug/SubGHz_Phy/Target/radio_board_if.d new file mode 100644 index 0000000..a28d9d1 --- /dev/null +++ b/Debug/SubGHz_Phy/Target/radio_board_if.d @@ -0,0 +1,90 @@ +SubGHz_Phy/Target/radio_board_if.o: ../SubGHz_Phy/Target/radio_board_if.c \ + ../SubGHz_Phy/Target/radio_board_if.h ../Core/Inc/platform.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wl55xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h \ + ../Core/Inc/stm32wlxx_hal_conf.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h \ + ../Core/Inc/main.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_gpio.h \ + ../Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo_radio.h \ + ../Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo_errno.h \ + ../Core/Inc/stm32wlxx_nucleo_conf.h \ + ../Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo.h +../SubGHz_Phy/Target/radio_board_if.h: +../Core/Inc/platform.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wl55xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h: +../Core/Inc/stm32wlxx_hal_conf.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h: +../Core/Inc/main.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_gpio.h: +../Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo_radio.h: +../Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo_errno.h: +../Core/Inc/stm32wlxx_nucleo_conf.h: +../Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo.h: diff --git a/Debug/SubGHz_Phy/Target/radio_board_if.o b/Debug/SubGHz_Phy/Target/radio_board_if.o new file mode 100644 index 0000000..c9eb426 Binary files /dev/null and b/Debug/SubGHz_Phy/Target/radio_board_if.o differ diff --git a/Debug/SubGHz_Phy/Target/radio_board_if.su b/Debug/SubGHz_Phy/Target/radio_board_if.su new file mode 100644 index 0000000..835eebc --- /dev/null +++ b/Debug/SubGHz_Phy/Target/radio_board_if.su @@ -0,0 +1,7 @@ +../SubGHz_Phy/Target/radio_board_if.c:59:9:RBI_Init 8 static +../SubGHz_Phy/Target/radio_board_if.c:85:9:RBI_DeInit 8 static +../SubGHz_Phy/Target/radio_board_if.c:111:9:RBI_ConfigRFSwitch 16 static +../SubGHz_Phy/Target/radio_board_if.c:138:9:RBI_GetTxConfig 8 static +../SubGHz_Phy/Target/radio_board_if.c:164:9:RBI_IsTCXO 8 static +../SubGHz_Phy/Target/radio_board_if.c:190:9:RBI_IsDCDC 8 static +../SubGHz_Phy/Target/radio_board_if.c:216:9:RBI_GetRFOMaxPowerConfig 16 static diff --git a/Debug/SubGHz_Phy/Target/subdir.mk b/Debug/SubGHz_Phy/Target/subdir.mk new file mode 100644 index 0000000..43929a8 --- /dev/null +++ b/Debug/SubGHz_Phy/Target/subdir.mk @@ -0,0 +1,27 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (13.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../SubGHz_Phy/Target/radio_board_if.c + +OBJS += \ +./SubGHz_Phy/Target/radio_board_if.o + +C_DEPS += \ +./SubGHz_Phy/Target/radio_board_if.d + + +# Each subdirectory must supply rules for building sources it contributes +SubGHz_Phy/Target/%.o SubGHz_Phy/Target/%.su SubGHz_Phy/Target/%.cyclo: ../SubGHz_Phy/Target/%.c SubGHz_Phy/Target/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WL55xx -c -I../Core/Inc -I../SubGHz_Phy/App -I../SubGHz_Phy/Target -I../Utilities/trace/adv_trace -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Utilities/misc -I../Utilities/sequencer -I../Utilities/timer -I../Utilities/lpm/tiny_lpm -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Middlewares/Third_Party/SubGHz_Phy -I../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver -I../Drivers/CMSIS/Include -I../Drivers/BSP/STM32WLxx_Nucleo -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-SubGHz_Phy-2f-Target + +clean-SubGHz_Phy-2f-Target: + -$(RM) ./SubGHz_Phy/Target/radio_board_if.cyclo ./SubGHz_Phy/Target/radio_board_if.d ./SubGHz_Phy/Target/radio_board_if.o ./SubGHz_Phy/Target/radio_board_if.su + +.PHONY: clean-SubGHz_Phy-2f-Target + diff --git a/Debug/SubGHz_Phy_Per.elf b/Debug/SubGHz_Phy_Per.elf new file mode 100755 index 0000000..e6f9cce Binary files /dev/null and b/Debug/SubGHz_Phy_Per.elf differ diff --git a/Debug/SubGHz_Phy_Per.list b/Debug/SubGHz_Phy_Per.list new file mode 100644 index 0000000..9e596c6 --- /dev/null +++ b/Debug/SubGHz_Phy_Per.list @@ -0,0 +1,36581 @@ + +SubGHz_Phy_Per.elf: file format elf32-littlearm + +Sections: +Idx Name Size VMA LMA File off Algn + 0 .isr_vector 00000138 08000000 08000000 00001000 2**0 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 1 .text 0000d3c8 08000138 08000138 00001138 2**2 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 2 .rodata 00000630 0800d500 0800d500 0000e500 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 3 .ARM.extab 00000000 0800db30 0800db30 0000f024 2**0 + CONTENTS, READONLY + 4 .ARM 00000008 0800db30 0800db30 0000eb30 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 5 .preinit_array 00000000 0800db38 0800db38 0000f024 2**0 + CONTENTS, ALLOC, LOAD, DATA + 6 .init_array 00000004 0800db38 0800db38 0000eb38 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 7 .fini_array 00000004 0800db3c 0800db3c 0000eb3c 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 8 .data 00000024 20000000 0800db40 0000f000 2**2 + CONTENTS, ALLOC, LOAD, DATA + 9 .bss 00000cc4 20000024 0800db64 0000f024 2**2 + ALLOC + 10 ._user_heap_stack 00000a00 20000ce8 0800db64 0000fce8 2**0 + ALLOC + 11 .ARM.attributes 0000002a 00000000 00000000 0000f024 2**0 + CONTENTS, READONLY + 12 .debug_info 000233f6 00000000 00000000 0000f04e 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 13 .debug_abbrev 00005f69 00000000 00000000 00032444 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 14 .debug_aranges 00002028 00000000 00000000 000383b0 2**3 + CONTENTS, READONLY, DEBUGGING, OCTETS + 15 .debug_rnglists 0000182b 00000000 00000000 0003a3d8 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 16 .debug_macro 000235c5 00000000 00000000 0003bc03 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 17 .debug_line 00022287 00000000 00000000 0005f1c8 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 18 .debug_str 000c58b3 00000000 00000000 0008144f 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 19 .comment 00000043 00000000 00000000 00146d02 2**0 + CONTENTS, READONLY + 20 .debug_frame 00008274 00000000 00000000 00146d48 2**2 + CONTENTS, READONLY, DEBUGGING, OCTETS + 21 .debug_line_str 0000005f 00000000 00000000 0014efbc 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + +Disassembly of section .text: + +08000138 <__do_global_dtors_aux>: + 8000138: b510 push {r4, lr} + 800013a: 4c05 ldr r4, [pc, #20] @ (8000150 <__do_global_dtors_aux+0x18>) + 800013c: 7823 ldrb r3, [r4, #0] + 800013e: b933 cbnz r3, 800014e <__do_global_dtors_aux+0x16> + 8000140: 4b04 ldr r3, [pc, #16] @ (8000154 <__do_global_dtors_aux+0x1c>) + 8000142: b113 cbz r3, 800014a <__do_global_dtors_aux+0x12> + 8000144: 4804 ldr r0, [pc, #16] @ (8000158 <__do_global_dtors_aux+0x20>) + 8000146: f3af 8000 nop.w + 800014a: 2301 movs r3, #1 + 800014c: 7023 strb r3, [r4, #0] + 800014e: bd10 pop {r4, pc} + 8000150: 20000024 .word 0x20000024 + 8000154: 00000000 .word 0x00000000 + 8000158: 0800d4e8 .word 0x0800d4e8 + +0800015c : + 800015c: b508 push {r3, lr} + 800015e: 4b03 ldr r3, [pc, #12] @ (800016c ) + 8000160: b11b cbz r3, 800016a + 8000162: 4903 ldr r1, [pc, #12] @ (8000170 ) + 8000164: 4803 ldr r0, [pc, #12] @ (8000174 ) + 8000166: f3af 8000 nop.w + 800016a: bd08 pop {r3, pc} + 800016c: 00000000 .word 0x00000000 + 8000170: 20000028 .word 0x20000028 + 8000174: 0800d4e8 .word 0x0800d4e8 + +08000178 : + 8000178: 4603 mov r3, r0 + 800017a: f813 2b01 ldrb.w r2, [r3], #1 + 800017e: 2a00 cmp r2, #0 + 8000180: d1fb bne.n 800017a + 8000182: 1a18 subs r0, r3, r0 + 8000184: 3801 subs r0, #1 + 8000186: 4770 bx lr + +08000188 <__aeabi_uldivmod>: + 8000188: b953 cbnz r3, 80001a0 <__aeabi_uldivmod+0x18> + 800018a: b94a cbnz r2, 80001a0 <__aeabi_uldivmod+0x18> + 800018c: 2900 cmp r1, #0 + 800018e: bf08 it eq + 8000190: 2800 cmpeq r0, #0 + 8000192: bf1c itt ne + 8000194: f04f 31ff movne.w r1, #4294967295 @ 0xffffffff + 8000198: f04f 30ff movne.w r0, #4294967295 @ 0xffffffff + 800019c: f000 b988 b.w 80004b0 <__aeabi_idiv0> + 80001a0: f1ad 0c08 sub.w ip, sp, #8 + 80001a4: e96d ce04 strd ip, lr, [sp, #-16]! + 80001a8: f000 f806 bl 80001b8 <__udivmoddi4> + 80001ac: f8dd e004 ldr.w lr, [sp, #4] + 80001b0: e9dd 2302 ldrd r2, r3, [sp, #8] + 80001b4: b004 add sp, #16 + 80001b6: 4770 bx lr + +080001b8 <__udivmoddi4>: + 80001b8: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} + 80001bc: 9d08 ldr r5, [sp, #32] + 80001be: 468e mov lr, r1 + 80001c0: 4604 mov r4, r0 + 80001c2: 4688 mov r8, r1 + 80001c4: 2b00 cmp r3, #0 + 80001c6: d14a bne.n 800025e <__udivmoddi4+0xa6> + 80001c8: 428a cmp r2, r1 + 80001ca: 4617 mov r7, r2 + 80001cc: d962 bls.n 8000294 <__udivmoddi4+0xdc> + 80001ce: fab2 f682 clz r6, r2 + 80001d2: b14e cbz r6, 80001e8 <__udivmoddi4+0x30> + 80001d4: f1c6 0320 rsb r3, r6, #32 + 80001d8: fa01 f806 lsl.w r8, r1, r6 + 80001dc: fa20 f303 lsr.w r3, r0, r3 + 80001e0: 40b7 lsls r7, r6 + 80001e2: ea43 0808 orr.w r8, r3, r8 + 80001e6: 40b4 lsls r4, r6 + 80001e8: ea4f 4e17 mov.w lr, r7, lsr #16 + 80001ec: fa1f fc87 uxth.w ip, r7 + 80001f0: fbb8 f1fe udiv r1, r8, lr + 80001f4: 0c23 lsrs r3, r4, #16 + 80001f6: fb0e 8811 mls r8, lr, r1, r8 + 80001fa: ea43 4308 orr.w r3, r3, r8, lsl #16 + 80001fe: fb01 f20c mul.w r2, r1, ip + 8000202: 429a cmp r2, r3 + 8000204: d909 bls.n 800021a <__udivmoddi4+0x62> + 8000206: 18fb adds r3, r7, r3 + 8000208: f101 30ff add.w r0, r1, #4294967295 @ 0xffffffff + 800020c: f080 80ea bcs.w 80003e4 <__udivmoddi4+0x22c> + 8000210: 429a cmp r2, r3 + 8000212: f240 80e7 bls.w 80003e4 <__udivmoddi4+0x22c> + 8000216: 3902 subs r1, #2 + 8000218: 443b add r3, r7 + 800021a: 1a9a subs r2, r3, r2 + 800021c: b2a3 uxth r3, r4 + 800021e: fbb2 f0fe udiv r0, r2, lr + 8000222: fb0e 2210 mls r2, lr, r0, r2 + 8000226: ea43 4302 orr.w r3, r3, r2, lsl #16 + 800022a: fb00 fc0c mul.w ip, r0, ip + 800022e: 459c cmp ip, r3 + 8000230: d909 bls.n 8000246 <__udivmoddi4+0x8e> + 8000232: 18fb adds r3, r7, r3 + 8000234: f100 32ff add.w r2, r0, #4294967295 @ 0xffffffff + 8000238: f080 80d6 bcs.w 80003e8 <__udivmoddi4+0x230> + 800023c: 459c cmp ip, r3 + 800023e: f240 80d3 bls.w 80003e8 <__udivmoddi4+0x230> + 8000242: 443b add r3, r7 + 8000244: 3802 subs r0, #2 + 8000246: ea40 4001 orr.w r0, r0, r1, lsl #16 + 800024a: eba3 030c sub.w r3, r3, ip + 800024e: 2100 movs r1, #0 + 8000250: b11d cbz r5, 800025a <__udivmoddi4+0xa2> + 8000252: 40f3 lsrs r3, r6 + 8000254: 2200 movs r2, #0 + 8000256: e9c5 3200 strd r3, r2, [r5] + 800025a: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} + 800025e: 428b cmp r3, r1 + 8000260: d905 bls.n 800026e <__udivmoddi4+0xb6> + 8000262: b10d cbz r5, 8000268 <__udivmoddi4+0xb0> + 8000264: e9c5 0100 strd r0, r1, [r5] + 8000268: 2100 movs r1, #0 + 800026a: 4608 mov r0, r1 + 800026c: e7f5 b.n 800025a <__udivmoddi4+0xa2> + 800026e: fab3 f183 clz r1, r3 + 8000272: 2900 cmp r1, #0 + 8000274: d146 bne.n 8000304 <__udivmoddi4+0x14c> + 8000276: 4573 cmp r3, lr + 8000278: d302 bcc.n 8000280 <__udivmoddi4+0xc8> + 800027a: 4282 cmp r2, r0 + 800027c: f200 8105 bhi.w 800048a <__udivmoddi4+0x2d2> + 8000280: 1a84 subs r4, r0, r2 + 8000282: eb6e 0203 sbc.w r2, lr, r3 + 8000286: 2001 movs r0, #1 + 8000288: 4690 mov r8, r2 + 800028a: 2d00 cmp r5, #0 + 800028c: d0e5 beq.n 800025a <__udivmoddi4+0xa2> + 800028e: e9c5 4800 strd r4, r8, [r5] + 8000292: e7e2 b.n 800025a <__udivmoddi4+0xa2> + 8000294: 2a00 cmp r2, #0 + 8000296: f000 8090 beq.w 80003ba <__udivmoddi4+0x202> + 800029a: fab2 f682 clz r6, r2 + 800029e: 2e00 cmp r6, #0 + 80002a0: f040 80a4 bne.w 80003ec <__udivmoddi4+0x234> + 80002a4: 1a8a subs r2, r1, r2 + 80002a6: 0c03 lsrs r3, r0, #16 + 80002a8: ea4f 4e17 mov.w lr, r7, lsr #16 + 80002ac: b280 uxth r0, r0 + 80002ae: b2bc uxth r4, r7 + 80002b0: 2101 movs r1, #1 + 80002b2: fbb2 fcfe udiv ip, r2, lr + 80002b6: fb0e 221c mls r2, lr, ip, r2 + 80002ba: ea43 4302 orr.w r3, r3, r2, lsl #16 + 80002be: fb04 f20c mul.w r2, r4, ip + 80002c2: 429a cmp r2, r3 + 80002c4: d907 bls.n 80002d6 <__udivmoddi4+0x11e> + 80002c6: 18fb adds r3, r7, r3 + 80002c8: f10c 38ff add.w r8, ip, #4294967295 @ 0xffffffff + 80002cc: d202 bcs.n 80002d4 <__udivmoddi4+0x11c> + 80002ce: 429a cmp r2, r3 + 80002d0: f200 80e0 bhi.w 8000494 <__udivmoddi4+0x2dc> + 80002d4: 46c4 mov ip, r8 + 80002d6: 1a9b subs r3, r3, r2 + 80002d8: fbb3 f2fe udiv r2, r3, lr + 80002dc: fb0e 3312 mls r3, lr, r2, r3 + 80002e0: ea40 4303 orr.w r3, r0, r3, lsl #16 + 80002e4: fb02 f404 mul.w r4, r2, r4 + 80002e8: 429c cmp r4, r3 + 80002ea: d907 bls.n 80002fc <__udivmoddi4+0x144> + 80002ec: 18fb adds r3, r7, r3 + 80002ee: f102 30ff add.w r0, r2, #4294967295 @ 0xffffffff + 80002f2: d202 bcs.n 80002fa <__udivmoddi4+0x142> + 80002f4: 429c cmp r4, r3 + 80002f6: f200 80ca bhi.w 800048e <__udivmoddi4+0x2d6> + 80002fa: 4602 mov r2, r0 + 80002fc: 1b1b subs r3, r3, r4 + 80002fe: ea42 400c orr.w r0, r2, ip, lsl #16 + 8000302: e7a5 b.n 8000250 <__udivmoddi4+0x98> + 8000304: f1c1 0620 rsb r6, r1, #32 + 8000308: 408b lsls r3, r1 + 800030a: fa22 f706 lsr.w r7, r2, r6 + 800030e: 431f orrs r7, r3 + 8000310: fa0e f401 lsl.w r4, lr, r1 + 8000314: fa20 f306 lsr.w r3, r0, r6 + 8000318: fa2e fe06 lsr.w lr, lr, r6 + 800031c: ea4f 4917 mov.w r9, r7, lsr #16 + 8000320: 4323 orrs r3, r4 + 8000322: fa00 f801 lsl.w r8, r0, r1 + 8000326: fa1f fc87 uxth.w ip, r7 + 800032a: fbbe f0f9 udiv r0, lr, r9 + 800032e: 0c1c lsrs r4, r3, #16 + 8000330: fb09 ee10 mls lr, r9, r0, lr + 8000334: ea44 440e orr.w r4, r4, lr, lsl #16 + 8000338: fb00 fe0c mul.w lr, r0, ip + 800033c: 45a6 cmp lr, r4 + 800033e: fa02 f201 lsl.w r2, r2, r1 + 8000342: d909 bls.n 8000358 <__udivmoddi4+0x1a0> + 8000344: 193c adds r4, r7, r4 + 8000346: f100 3aff add.w sl, r0, #4294967295 @ 0xffffffff + 800034a: f080 809c bcs.w 8000486 <__udivmoddi4+0x2ce> + 800034e: 45a6 cmp lr, r4 + 8000350: f240 8099 bls.w 8000486 <__udivmoddi4+0x2ce> + 8000354: 3802 subs r0, #2 + 8000356: 443c add r4, r7 + 8000358: eba4 040e sub.w r4, r4, lr + 800035c: fa1f fe83 uxth.w lr, r3 + 8000360: fbb4 f3f9 udiv r3, r4, r9 + 8000364: fb09 4413 mls r4, r9, r3, r4 + 8000368: ea4e 4404 orr.w r4, lr, r4, lsl #16 + 800036c: fb03 fc0c mul.w ip, r3, ip + 8000370: 45a4 cmp ip, r4 + 8000372: d908 bls.n 8000386 <__udivmoddi4+0x1ce> + 8000374: 193c adds r4, r7, r4 + 8000376: f103 3eff add.w lr, r3, #4294967295 @ 0xffffffff + 800037a: f080 8082 bcs.w 8000482 <__udivmoddi4+0x2ca> + 800037e: 45a4 cmp ip, r4 + 8000380: d97f bls.n 8000482 <__udivmoddi4+0x2ca> + 8000382: 3b02 subs r3, #2 + 8000384: 443c add r4, r7 + 8000386: ea43 4000 orr.w r0, r3, r0, lsl #16 + 800038a: eba4 040c sub.w r4, r4, ip + 800038e: fba0 ec02 umull lr, ip, r0, r2 + 8000392: 4564 cmp r4, ip + 8000394: 4673 mov r3, lr + 8000396: 46e1 mov r9, ip + 8000398: d362 bcc.n 8000460 <__udivmoddi4+0x2a8> + 800039a: d05f beq.n 800045c <__udivmoddi4+0x2a4> + 800039c: b15d cbz r5, 80003b6 <__udivmoddi4+0x1fe> + 800039e: ebb8 0203 subs.w r2, r8, r3 + 80003a2: eb64 0409 sbc.w r4, r4, r9 + 80003a6: fa04 f606 lsl.w r6, r4, r6 + 80003aa: fa22 f301 lsr.w r3, r2, r1 + 80003ae: 431e orrs r6, r3 + 80003b0: 40cc lsrs r4, r1 + 80003b2: e9c5 6400 strd r6, r4, [r5] + 80003b6: 2100 movs r1, #0 + 80003b8: e74f b.n 800025a <__udivmoddi4+0xa2> + 80003ba: fbb1 fcf2 udiv ip, r1, r2 + 80003be: 0c01 lsrs r1, r0, #16 + 80003c0: ea41 410e orr.w r1, r1, lr, lsl #16 + 80003c4: b280 uxth r0, r0 + 80003c6: ea40 4201 orr.w r2, r0, r1, lsl #16 + 80003ca: 463b mov r3, r7 + 80003cc: 4638 mov r0, r7 + 80003ce: 463c mov r4, r7 + 80003d0: 46b8 mov r8, r7 + 80003d2: 46be mov lr, r7 + 80003d4: 2620 movs r6, #32 + 80003d6: fbb1 f1f7 udiv r1, r1, r7 + 80003da: eba2 0208 sub.w r2, r2, r8 + 80003de: ea41 410c orr.w r1, r1, ip, lsl #16 + 80003e2: e766 b.n 80002b2 <__udivmoddi4+0xfa> + 80003e4: 4601 mov r1, r0 + 80003e6: e718 b.n 800021a <__udivmoddi4+0x62> + 80003e8: 4610 mov r0, r2 + 80003ea: e72c b.n 8000246 <__udivmoddi4+0x8e> + 80003ec: f1c6 0220 rsb r2, r6, #32 + 80003f0: fa2e f302 lsr.w r3, lr, r2 + 80003f4: 40b7 lsls r7, r6 + 80003f6: 40b1 lsls r1, r6 + 80003f8: fa20 f202 lsr.w r2, r0, r2 + 80003fc: ea4f 4e17 mov.w lr, r7, lsr #16 + 8000400: 430a orrs r2, r1 + 8000402: fbb3 f8fe udiv r8, r3, lr + 8000406: b2bc uxth r4, r7 + 8000408: fb0e 3318 mls r3, lr, r8, r3 + 800040c: 0c11 lsrs r1, r2, #16 + 800040e: ea41 4103 orr.w r1, r1, r3, lsl #16 + 8000412: fb08 f904 mul.w r9, r8, r4 + 8000416: 40b0 lsls r0, r6 + 8000418: 4589 cmp r9, r1 + 800041a: ea4f 4310 mov.w r3, r0, lsr #16 + 800041e: b280 uxth r0, r0 + 8000420: d93e bls.n 80004a0 <__udivmoddi4+0x2e8> + 8000422: 1879 adds r1, r7, r1 + 8000424: f108 3cff add.w ip, r8, #4294967295 @ 0xffffffff + 8000428: d201 bcs.n 800042e <__udivmoddi4+0x276> + 800042a: 4589 cmp r9, r1 + 800042c: d81f bhi.n 800046e <__udivmoddi4+0x2b6> + 800042e: eba1 0109 sub.w r1, r1, r9 + 8000432: fbb1 f9fe udiv r9, r1, lr + 8000436: fb09 f804 mul.w r8, r9, r4 + 800043a: fb0e 1119 mls r1, lr, r9, r1 + 800043e: b292 uxth r2, r2 + 8000440: ea42 4201 orr.w r2, r2, r1, lsl #16 + 8000444: 4542 cmp r2, r8 + 8000446: d229 bcs.n 800049c <__udivmoddi4+0x2e4> + 8000448: 18ba adds r2, r7, r2 + 800044a: f109 31ff add.w r1, r9, #4294967295 @ 0xffffffff + 800044e: d2c4 bcs.n 80003da <__udivmoddi4+0x222> + 8000450: 4542 cmp r2, r8 + 8000452: d2c2 bcs.n 80003da <__udivmoddi4+0x222> + 8000454: f1a9 0102 sub.w r1, r9, #2 + 8000458: 443a add r2, r7 + 800045a: e7be b.n 80003da <__udivmoddi4+0x222> + 800045c: 45f0 cmp r8, lr + 800045e: d29d bcs.n 800039c <__udivmoddi4+0x1e4> + 8000460: ebbe 0302 subs.w r3, lr, r2 + 8000464: eb6c 0c07 sbc.w ip, ip, r7 + 8000468: 3801 subs r0, #1 + 800046a: 46e1 mov r9, ip + 800046c: e796 b.n 800039c <__udivmoddi4+0x1e4> + 800046e: eba7 0909 sub.w r9, r7, r9 + 8000472: 4449 add r1, r9 + 8000474: f1a8 0c02 sub.w ip, r8, #2 + 8000478: fbb1 f9fe udiv r9, r1, lr + 800047c: fb09 f804 mul.w r8, r9, r4 + 8000480: e7db b.n 800043a <__udivmoddi4+0x282> + 8000482: 4673 mov r3, lr + 8000484: e77f b.n 8000386 <__udivmoddi4+0x1ce> + 8000486: 4650 mov r0, sl + 8000488: e766 b.n 8000358 <__udivmoddi4+0x1a0> + 800048a: 4608 mov r0, r1 + 800048c: e6fd b.n 800028a <__udivmoddi4+0xd2> + 800048e: 443b add r3, r7 + 8000490: 3a02 subs r2, #2 + 8000492: e733 b.n 80002fc <__udivmoddi4+0x144> + 8000494: f1ac 0c02 sub.w ip, ip, #2 + 8000498: 443b add r3, r7 + 800049a: e71c b.n 80002d6 <__udivmoddi4+0x11e> + 800049c: 4649 mov r1, r9 + 800049e: e79c b.n 80003da <__udivmoddi4+0x222> + 80004a0: eba1 0109 sub.w r1, r1, r9 + 80004a4: 46c4 mov ip, r8 + 80004a6: fbb1 f9fe udiv r9, r1, lr + 80004aa: fb09 f804 mul.w r8, r9, r4 + 80004ae: e7c4 b.n 800043a <__udivmoddi4+0x282> + +080004b0 <__aeabi_idiv0>: + 80004b0: 4770 bx lr + 80004b2: bf00 nop + +080004b4 : + * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1 + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @retval None + */ +__STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) +{ + 80004b4: b480 push {r7} + 80004b6: b085 sub sp, #20 + 80004b8: af00 add r7, sp, #0 + 80004ba: 6078 str r0, [r7, #4] + __IO uint32_t tmpreg; + SET_BIT(RCC->AHB1ENR, Periphs); + 80004bc: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 80004c0: 6c9a ldr r2, [r3, #72] @ 0x48 + 80004c2: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 80004c6: 687b ldr r3, [r7, #4] + 80004c8: 4313 orrs r3, r2 + 80004ca: 648b str r3, [r1, #72] @ 0x48 + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHB1ENR, Periphs); + 80004cc: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 80004d0: 6c9a ldr r2, [r3, #72] @ 0x48 + 80004d2: 687b ldr r3, [r7, #4] + 80004d4: 4013 ands r3, r2 + 80004d6: 60fb str r3, [r7, #12] + (void)tmpreg; + 80004d8: 68fb ldr r3, [r7, #12] +} + 80004da: bf00 nop + 80004dc: 3714 adds r7, #20 + 80004de: 46bd mov sp, r7 + 80004e0: bc80 pop {r7} + 80004e2: 4770 bx lr + +080004e4 : + +/** + * Enable DMA controller clock + */ +void MX_DMA_Init(void) +{ + 80004e4: b580 push {r7, lr} + 80004e6: af00 add r7, sp, #0 + + /* DMA controller clock enable */ + __HAL_RCC_DMAMUX1_CLK_ENABLE(); + 80004e8: 2004 movs r0, #4 + 80004ea: f7ff ffe3 bl 80004b4 + __HAL_RCC_DMA1_CLK_ENABLE(); + 80004ee: 2001 movs r0, #1 + 80004f0: f7ff ffe0 bl 80004b4 + + /* DMA interrupt init */ + /* DMA1_Channel5_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(DMA1_Channel5_IRQn, 2, 0); + 80004f4: 2200 movs r2, #0 + 80004f6: 2102 movs r1, #2 + 80004f8: 200f movs r0, #15 + 80004fa: f001 faa6 bl 8001a4a + HAL_NVIC_EnableIRQ(DMA1_Channel5_IRQn); + 80004fe: 200f movs r0, #15 + 8000500: f001 fabd bl 8001a7e + +} + 8000504: bf00 nop + 8000506: bd80 pop {r7, pc} + +08000508 : + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH + * @retval None + */ +__STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs) +{ + 8000508: b480 push {r7} + 800050a: b085 sub sp, #20 + 800050c: af00 add r7, sp, #0 + 800050e: 6078 str r0, [r7, #4] + __IO uint32_t tmpreg; + SET_BIT(RCC->AHB2ENR, Periphs); + 8000510: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8000514: 6cda ldr r2, [r3, #76] @ 0x4c + 8000516: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 800051a: 687b ldr r3, [r7, #4] + 800051c: 4313 orrs r3, r2 + 800051e: 64cb str r3, [r1, #76] @ 0x4c + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHB2ENR, Periphs); + 8000520: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8000524: 6cda ldr r2, [r3, #76] @ 0x4c + 8000526: 687b ldr r3, [r7, #4] + 8000528: 4013 ands r3, r2 + 800052a: 60fb str r3, [r7, #12] + (void)tmpreg; + 800052c: 68fb ldr r3, [r7, #12] +} + 800052e: bf00 nop + 8000530: 3714 adds r7, #20 + 8000532: 46bd mov sp, r7 + 8000534: bc80 pop {r7} + 8000536: 4770 bx lr + +08000538 : + * Output + * EVENT_OUT + * EXTI +*/ +void MX_GPIO_Init(void) +{ + 8000538: b580 push {r7, lr} + 800053a: b086 sub sp, #24 + 800053c: af00 add r7, sp, #0 + + GPIO_InitTypeDef GPIO_InitStruct = {0}; + 800053e: 1d3b adds r3, r7, #4 + 8000540: 2200 movs r2, #0 + 8000542: 601a str r2, [r3, #0] + 8000544: 605a str r2, [r3, #4] + 8000546: 609a str r2, [r3, #8] + 8000548: 60da str r2, [r3, #12] + 800054a: 611a str r2, [r3, #16] + + /* GPIO Ports Clock Enable */ + __HAL_RCC_GPIOB_CLK_ENABLE(); + 800054c: 2002 movs r0, #2 + 800054e: f7ff ffdb bl 8000508 + __HAL_RCC_GPIOC_CLK_ENABLE(); + 8000552: 2004 movs r0, #4 + 8000554: f7ff ffd8 bl 8000508 + __HAL_RCC_GPIOA_CLK_ENABLE(); + 8000558: 2001 movs r0, #1 + 800055a: f7ff ffd5 bl 8000508 + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(GPIOB, LED1_Pin|LED2_Pin|PROB2_Pin|PROB1_Pin + 800055e: 2200 movs r2, #0 + 8000560: f44f 413a mov.w r1, #47616 @ 0xba00 + 8000564: 4829 ldr r0, [pc, #164] @ (800060c ) + 8000566: f002 f8ed bl 8002744 + |LED3_Pin, GPIO_PIN_RESET); + + /*Configure GPIO pins : LED1_Pin LED2_Pin LED3_Pin */ + GPIO_InitStruct.Pin = LED1_Pin|LED2_Pin|LED3_Pin; + 800056a: f44f 430a mov.w r3, #35328 @ 0x8a00 + 800056e: 607b str r3, [r7, #4] + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + 8000570: 2301 movs r3, #1 + 8000572: 60bb str r3, [r7, #8] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8000574: 2300 movs r3, #0 + 8000576: 60fb str r3, [r7, #12] + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; + 8000578: 2302 movs r3, #2 + 800057a: 613b str r3, [r7, #16] + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + 800057c: 1d3b adds r3, r7, #4 + 800057e: 4619 mov r1, r3 + 8000580: 4822 ldr r0, [pc, #136] @ (800060c ) + 8000582: f001 feb1 bl 80022e8 + + /*Configure GPIO pins : BUT1_Pin BUT2_Pin */ + GPIO_InitStruct.Pin = BUT1_Pin|BUT2_Pin; + 8000586: 2303 movs r3, #3 + 8000588: 607b str r3, [r7, #4] + GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING; + 800058a: f44f 1304 mov.w r3, #2162688 @ 0x210000 + 800058e: 60bb str r3, [r7, #8] + GPIO_InitStruct.Pull = GPIO_PULLUP; + 8000590: 2301 movs r3, #1 + 8000592: 60fb str r3, [r7, #12] + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 8000594: 1d3b adds r3, r7, #4 + 8000596: 4619 mov r1, r3 + 8000598: f04f 4090 mov.w r0, #1207959552 @ 0x48000000 + 800059c: f001 fea4 bl 80022e8 + + /*Configure GPIO pins : PROB2_Pin PROB1_Pin */ + GPIO_InitStruct.Pin = PROB2_Pin|PROB1_Pin; + 80005a0: f44f 5340 mov.w r3, #12288 @ 0x3000 + 80005a4: 607b str r3, [r7, #4] + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + 80005a6: 2301 movs r3, #1 + 80005a8: 60bb str r3, [r7, #8] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 80005aa: 2300 movs r3, #0 + 80005ac: 60fb str r3, [r7, #12] + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + 80005ae: 2303 movs r3, #3 + 80005b0: 613b str r3, [r7, #16] + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + 80005b2: 1d3b adds r3, r7, #4 + 80005b4: 4619 mov r1, r3 + 80005b6: 4815 ldr r0, [pc, #84] @ (800060c ) + 80005b8: f001 fe96 bl 80022e8 + + /*Configure GPIO pin : BUT3_Pin */ + GPIO_InitStruct.Pin = BUT3_Pin; + 80005bc: 2340 movs r3, #64 @ 0x40 + 80005be: 607b str r3, [r7, #4] + GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING; + 80005c0: f44f 1304 mov.w r3, #2162688 @ 0x210000 + 80005c4: 60bb str r3, [r7, #8] + GPIO_InitStruct.Pull = GPIO_PULLUP; + 80005c6: 2301 movs r3, #1 + 80005c8: 60fb str r3, [r7, #12] + HAL_GPIO_Init(BUT3_GPIO_Port, &GPIO_InitStruct); + 80005ca: 1d3b adds r3, r7, #4 + 80005cc: 4619 mov r1, r3 + 80005ce: 4810 ldr r0, [pc, #64] @ (8000610 ) + 80005d0: f001 fe8a bl 80022e8 + + /* EXTI interrupt init*/ + HAL_NVIC_SetPriority(EXTI0_IRQn, 0, 0); + 80005d4: 2200 movs r2, #0 + 80005d6: 2100 movs r1, #0 + 80005d8: 2006 movs r0, #6 + 80005da: f001 fa36 bl 8001a4a + HAL_NVIC_EnableIRQ(EXTI0_IRQn); + 80005de: 2006 movs r0, #6 + 80005e0: f001 fa4d bl 8001a7e + + HAL_NVIC_SetPriority(EXTI1_IRQn, 0, 0); + 80005e4: 2200 movs r2, #0 + 80005e6: 2100 movs r1, #0 + 80005e8: 2007 movs r0, #7 + 80005ea: f001 fa2e bl 8001a4a + HAL_NVIC_EnableIRQ(EXTI1_IRQn); + 80005ee: 2007 movs r0, #7 + 80005f0: f001 fa45 bl 8001a7e + + HAL_NVIC_SetPriority(EXTI9_5_IRQn, 0, 0); + 80005f4: 2200 movs r2, #0 + 80005f6: 2100 movs r1, #0 + 80005f8: 2016 movs r0, #22 + 80005fa: f001 fa26 bl 8001a4a + HAL_NVIC_EnableIRQ(EXTI9_5_IRQn); + 80005fe: 2016 movs r0, #22 + 8000600: f001 fa3d bl 8001a7e + +} + 8000604: bf00 nop + 8000606: 3718 adds r7, #24 + 8000608: 46bd mov sp, r7 + 800060a: bd80 pop {r7, pc} + 800060c: 48000400 .word 0x48000400 + 8000610: 48000800 .word 0x48000800 + +08000614 : + * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH + * @arg @ref LL_RCC_LSEDRIVE_HIGH + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive) +{ + 8000614: b480 push {r7} + 8000616: b083 sub sp, #12 + 8000618: af00 add r7, sp, #0 + 800061a: 6078 str r0, [r7, #4] + MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, LSEDrive); + 800061c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8000620: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 8000624: f023 0218 bic.w r2, r3, #24 + 8000628: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 800062c: 687b ldr r3, [r7, #4] + 800062e: 4313 orrs r3, r2 + 8000630: f8c1 3090 str.w r3, [r1, #144] @ 0x90 +} + 8000634: bf00 nop + 8000636: 370c adds r7, #12 + 8000638: 46bd mov sp, r7 + 800063a: bc80 pop {r7} + 800063c: 4770 bx lr + +0800063e
: +/** + * @brief The application entry point. + * @retval int + */ +int main(void) +{ + 800063e: b580 push {r7, lr} + 8000640: af00 add r7, sp, #0 + /* USER CODE END 1 */ + + /* MCU Configuration--------------------------------------------------------*/ + + /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ + HAL_Init(); + 8000642: f001 f8db bl 80017fc + /* USER CODE BEGIN Init */ + + /* USER CODE END Init */ + + /* Configure the system clock */ + SystemClock_Config(); + 8000646: f000 f807 bl 8000658 + /* USER CODE BEGIN SysInit */ + + /* USER CODE END SysInit */ + + /* Initialize all configured peripherals */ + MX_GPIO_Init(); + 800064a: f7ff ff75 bl 8000538 + MX_SubGHz_Phy_Init(); + 800064e: f00b f9cf bl 800b9f0 + /* Infinite loop */ + /* USER CODE BEGIN WHILE */ + while (1) + { + /* USER CODE END WHILE */ + MX_SubGHz_Phy_Process(); + 8000652: f00b f9d5 bl 800ba00 + 8000656: e7fc b.n 8000652 + +08000658 : +/** + * @brief System Clock Configuration + * @retval None + */ +void SystemClock_Config(void) +{ + 8000658: b580 push {r7, lr} + 800065a: b09a sub sp, #104 @ 0x68 + 800065c: af00 add r7, sp, #0 + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + 800065e: f107 0320 add.w r3, r7, #32 + 8000662: 2248 movs r2, #72 @ 0x48 + 8000664: 2100 movs r1, #0 + 8000666: 4618 mov r0, r3 + 8000668: f00c ff04 bl 800d474 + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + 800066c: 1d3b adds r3, r7, #4 + 800066e: 2200 movs r2, #0 + 8000670: 601a str r2, [r3, #0] + 8000672: 605a str r2, [r3, #4] + 8000674: 609a str r2, [r3, #8] + 8000676: 60da str r2, [r3, #12] + 8000678: 611a str r2, [r3, #16] + 800067a: 615a str r2, [r3, #20] + 800067c: 619a str r2, [r3, #24] + + /** Configure LSE Drive Capability + */ + HAL_PWR_EnableBkUpAccess(); + 800067e: f002 f891 bl 80027a4 + __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW); + 8000682: 2000 movs r0, #0 + 8000684: f7ff ffc6 bl 8000614 + + /** Configure the main internal regulator output voltage + */ + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + 8000688: 4b1e ldr r3, [pc, #120] @ (8000704 ) + 800068a: 681b ldr r3, [r3, #0] + 800068c: f423 63c0 bic.w r3, r3, #1536 @ 0x600 + 8000690: 4a1c ldr r2, [pc, #112] @ (8000704 ) + 8000692: f443 7300 orr.w r3, r3, #512 @ 0x200 + 8000696: 6013 str r3, [r2, #0] + 8000698: 4b1a ldr r3, [pc, #104] @ (8000704 ) + 800069a: 681b ldr r3, [r3, #0] + 800069c: f403 63c0 and.w r3, r3, #1536 @ 0x600 + 80006a0: 603b str r3, [r7, #0] + 80006a2: 683b ldr r3, [r7, #0] + + /** Initializes the CPU, AHB and APB buses clocks + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE|RCC_OSCILLATORTYPE_MSI; + 80006a4: 2324 movs r3, #36 @ 0x24 + 80006a6: 623b str r3, [r7, #32] + RCC_OscInitStruct.LSEState = RCC_LSE_ON; + 80006a8: 2381 movs r3, #129 @ 0x81 + 80006aa: 62fb str r3, [r7, #44] @ 0x2c + RCC_OscInitStruct.MSIState = RCC_MSI_ON; + 80006ac: 2301 movs r3, #1 + 80006ae: 643b str r3, [r7, #64] @ 0x40 + RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT; + 80006b0: 2300 movs r3, #0 + 80006b2: 647b str r3, [r7, #68] @ 0x44 + RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_11; + 80006b4: 23b0 movs r3, #176 @ 0xb0 + 80006b6: 64bb str r3, [r7, #72] @ 0x48 + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; + 80006b8: 2300 movs r3, #0 + 80006ba: 64fb str r3, [r7, #76] @ 0x4c + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + 80006bc: f107 0320 add.w r3, r7, #32 + 80006c0: 4618 mov r0, r3 + 80006c2: f002 fbe3 bl 8002e8c + 80006c6: 4603 mov r3, r0 + 80006c8: 2b00 cmp r3, #0 + 80006ca: d001 beq.n 80006d0 + { + Error_Handler(); + 80006cc: f000 f81c bl 8000708 + } + + /** Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK3|RCC_CLOCKTYPE_HCLK + 80006d0: 234f movs r3, #79 @ 0x4f + 80006d2: 607b str r3, [r7, #4] + |RCC_CLOCKTYPE_SYSCLK|RCC_CLOCKTYPE_PCLK1 + |RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI; + 80006d4: 2300 movs r3, #0 + 80006d6: 60bb str r3, [r7, #8] + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + 80006d8: 2300 movs r3, #0 + 80006da: 60fb str r3, [r7, #12] + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; + 80006dc: 2300 movs r3, #0 + 80006de: 613b str r3, [r7, #16] + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + 80006e0: 2300 movs r3, #0 + 80006e2: 617b str r3, [r7, #20] + RCC_ClkInitStruct.AHBCLK3Divider = RCC_SYSCLK_DIV1; + 80006e4: 2300 movs r3, #0 + 80006e6: 61fb str r3, [r7, #28] + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) + 80006e8: 1d3b adds r3, r7, #4 + 80006ea: 2102 movs r1, #2 + 80006ec: 4618 mov r0, r3 + 80006ee: f002 ff4f bl 8003590 + 80006f2: 4603 mov r3, r0 + 80006f4: 2b00 cmp r3, #0 + 80006f6: d001 beq.n 80006fc + { + Error_Handler(); + 80006f8: f000 f806 bl 8000708 + } +} + 80006fc: bf00 nop + 80006fe: 3768 adds r7, #104 @ 0x68 + 8000700: 46bd mov sp, r7 + 8000702: bd80 pop {r7, pc} + 8000704: 58000400 .word 0x58000400 + +08000708 : +/** + * @brief This function is executed in case of error occurrence. + * @retval None + */ +void Error_Handler(void) +{ + 8000708: b480 push {r7} + 800070a: af00 add r7, sp, #0 + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); + 800070c: b672 cpsid i +} + 800070e: bf00 nop + /* USER CODE BEGIN Error_Handler_Debug */ + /* User can add his own implementation to report the HAL error return state */ + __disable_irq(); + while (1) + 8000710: bf00 nop + 8000712: e7fd b.n 8000710 + +08000714 : + * @brief Enable RTC + * @rmtoll BDCR RTCEN LL_RCC_EnableRTC + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableRTC(void) +{ + 8000714: b480 push {r7} + 8000716: af00 add r7, sp, #0 + SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN); + 8000718: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 800071c: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 8000720: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 8000724: f443 4300 orr.w r3, r3, #32768 @ 0x8000 + 8000728: f8c2 3090 str.w r3, [r2, #144] @ 0x90 +} + 800072c: bf00 nop + 800072e: 46bd mov sp, r7 + 8000730: bc80 pop {r7} + 8000732: 4770 bx lr + +08000734 : + * @arg @ref LL_APB1_GRP1_PERIPH_DAC + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + * @retval None + */ +__STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs) +{ + 8000734: b480 push {r7} + 8000736: b085 sub sp, #20 + 8000738: af00 add r7, sp, #0 + 800073a: 6078 str r0, [r7, #4] + __IO uint32_t tmpreg; + SET_BIT(RCC->APB1ENR1, Periphs); + 800073c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8000740: 6d9a ldr r2, [r3, #88] @ 0x58 + 8000742: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 8000746: 687b ldr r3, [r7, #4] + 8000748: 4313 orrs r3, r2 + 800074a: 658b str r3, [r1, #88] @ 0x58 + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB1ENR1, Periphs); + 800074c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8000750: 6d9a ldr r2, [r3, #88] @ 0x58 + 8000752: 687b ldr r3, [r7, #4] + 8000754: 4013 ands r3, r2 + 8000756: 60fb str r3, [r7, #12] + (void)tmpreg; + 8000758: 68fb ldr r3, [r7, #12] +} + 800075a: bf00 nop + 800075c: 3714 adds r7, #20 + 800075e: 46bd mov sp, r7 + 8000760: bc80 pop {r7} + 8000762: 4770 bx lr + +08000764 : + +RTC_HandleTypeDef hrtc; + +/* RTC init function */ +void MX_RTC_Init(void) +{ + 8000764: b580 push {r7, lr} + 8000766: b08c sub sp, #48 @ 0x30 + 8000768: af00 add r7, sp, #0 + + /* USER CODE BEGIN RTC_Init 0 */ + + /* USER CODE END RTC_Init 0 */ + + RTC_AlarmTypeDef sAlarm = {0}; + 800076a: 1d3b adds r3, r7, #4 + 800076c: 222c movs r2, #44 @ 0x2c + 800076e: 2100 movs r1, #0 + 8000770: 4618 mov r0, r3 + 8000772: f00c fe7f bl 800d474 + + /* USER CODE END RTC_Init 1 */ + + /** Initialize RTC Only + */ + hrtc.Instance = RTC; + 8000776: 4b22 ldr r3, [pc, #136] @ (8000800 ) + 8000778: 4a22 ldr r2, [pc, #136] @ (8000804 ) + 800077a: 601a str r2, [r3, #0] + hrtc.Init.AsynchPrediv = RTC_PREDIV_A; + 800077c: 4b20 ldr r3, [pc, #128] @ (8000800 ) + 800077e: 221f movs r2, #31 + 8000780: 609a str r2, [r3, #8] + hrtc.Init.OutPut = RTC_OUTPUT_DISABLE; + 8000782: 4b1f ldr r3, [pc, #124] @ (8000800 ) + 8000784: 2200 movs r2, #0 + 8000786: 611a str r2, [r3, #16] + hrtc.Init.OutPutRemap = RTC_OUTPUT_REMAP_NONE; + 8000788: 4b1d ldr r3, [pc, #116] @ (8000800 ) + 800078a: 2200 movs r2, #0 + 800078c: 615a str r2, [r3, #20] + hrtc.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH; + 800078e: 4b1c ldr r3, [pc, #112] @ (8000800 ) + 8000790: 2200 movs r2, #0 + 8000792: 619a str r2, [r3, #24] + hrtc.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN; + 8000794: 4b1a ldr r3, [pc, #104] @ (8000800 ) + 8000796: f04f 4280 mov.w r2, #1073741824 @ 0x40000000 + 800079a: 61da str r2, [r3, #28] + hrtc.Init.OutPutPullUp = RTC_OUTPUT_PULLUP_NONE; + 800079c: 4b18 ldr r3, [pc, #96] @ (8000800 ) + 800079e: 2200 movs r2, #0 + 80007a0: 621a str r2, [r3, #32] + hrtc.Init.BinMode = RTC_BINARY_ONLY; + 80007a2: 4b17 ldr r3, [pc, #92] @ (8000800 ) + 80007a4: f44f 7280 mov.w r2, #256 @ 0x100 + 80007a8: 625a str r2, [r3, #36] @ 0x24 + if (HAL_RTC_Init(&hrtc) != HAL_OK) + 80007aa: 4815 ldr r0, [pc, #84] @ (8000800 ) + 80007ac: f003 fbca bl 8003f44 + 80007b0: 4603 mov r3, r0 + 80007b2: 2b00 cmp r3, #0 + 80007b4: d001 beq.n 80007ba + { + Error_Handler(); + 80007b6: f7ff ffa7 bl 8000708 + + /* USER CODE END Check_RTC_BKUP */ + + /** Initialize RTC and set the Time and Date + */ + if (HAL_RTCEx_SetSSRU_IT(&hrtc) != HAL_OK) + 80007ba: 4811 ldr r0, [pc, #68] @ (8000800 ) + 80007bc: f003 feca bl 8004554 + 80007c0: 4603 mov r3, r0 + 80007c2: 2b00 cmp r3, #0 + 80007c4: d001 beq.n 80007ca + { + Error_Handler(); + 80007c6: f7ff ff9f bl 8000708 + } + + /** Enable the Alarm A + */ + sAlarm.BinaryAutoClr = RTC_ALARMSUBSECONDBIN_AUTOCLR_NO; + 80007ca: 2300 movs r3, #0 + 80007cc: 623b str r3, [r7, #32] + sAlarm.AlarmTime.SubSeconds = 0x0; + 80007ce: 2300 movs r3, #0 + 80007d0: 60bb str r3, [r7, #8] + sAlarm.AlarmMask = RTC_ALARMMASK_NONE; + 80007d2: 2300 movs r3, #0 + 80007d4: 61bb str r3, [r7, #24] + sAlarm.AlarmSubSecondMask = RTC_ALARMSUBSECONDBINMASK_NONE; + 80007d6: f04f 5300 mov.w r3, #536870912 @ 0x20000000 + 80007da: 61fb str r3, [r7, #28] + sAlarm.Alarm = RTC_ALARM_A; + 80007dc: f44f 7380 mov.w r3, #256 @ 0x100 + 80007e0: 62fb str r3, [r7, #44] @ 0x2c + if (HAL_RTC_SetAlarm_IT(&hrtc, &sAlarm, 0) != HAL_OK) + 80007e2: 1d3b adds r3, r7, #4 + 80007e4: 2200 movs r2, #0 + 80007e6: 4619 mov r1, r3 + 80007e8: 4805 ldr r0, [pc, #20] @ (8000800 ) + 80007ea: f003 fc37 bl 800405c + 80007ee: 4603 mov r3, r0 + 80007f0: 2b00 cmp r3, #0 + 80007f2: d001 beq.n 80007f8 + { + Error_Handler(); + 80007f4: f7ff ff88 bl 8000708 + } + /* USER CODE BEGIN RTC_Init 2 */ + + /* USER CODE END RTC_Init 2 */ + +} + 80007f8: bf00 nop + 80007fa: 3730 adds r7, #48 @ 0x30 + 80007fc: 46bd mov sp, r7 + 80007fe: bd80 pop {r7, pc} + 8000800: 20000040 .word 0x20000040 + 8000804: 40002800 .word 0x40002800 + +08000808 : + +void HAL_RTC_MspInit(RTC_HandleTypeDef* rtcHandle) +{ + 8000808: b580 push {r7, lr} + 800080a: b090 sub sp, #64 @ 0x40 + 800080c: af00 add r7, sp, #0 + 800080e: 6078 str r0, [r7, #4] + + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; + 8000810: f107 0308 add.w r3, r7, #8 + 8000814: 2238 movs r2, #56 @ 0x38 + 8000816: 2100 movs r1, #0 + 8000818: 4618 mov r0, r3 + 800081a: f00c fe2b bl 800d474 + if(rtcHandle->Instance==RTC) + 800081e: 687b ldr r3, [r7, #4] + 8000820: 681b ldr r3, [r3, #0] + 8000822: 4a16 ldr r2, [pc, #88] @ (800087c ) + 8000824: 4293 cmp r3, r2 + 8000826: d125 bne.n 8000874 + + /* USER CODE END RTC_MspInit 0 */ + + /** Initializes the peripherals clocks + */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC; + 8000828: f44f 3380 mov.w r3, #65536 @ 0x10000 + 800082c: 60bb str r3, [r7, #8] + PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE; + 800082e: f44f 7380 mov.w r3, #256 @ 0x100 + 8000832: 63fb str r3, [r7, #60] @ 0x3c + + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) + 8000834: f107 0308 add.w r3, r7, #8 + 8000838: 4618 mov r0, r3 + 800083a: f003 fa69 bl 8003d10 + 800083e: 4603 mov r3, r0 + 8000840: 2b00 cmp r3, #0 + 8000842: d001 beq.n 8000848 + { + Error_Handler(); + 8000844: f7ff ff60 bl 8000708 + } + + /* RTC clock enable */ + __HAL_RCC_RTC_ENABLE(); + 8000848: f7ff ff64 bl 8000714 + __HAL_RCC_RTCAPB_CLK_ENABLE(); + 800084c: f44f 6080 mov.w r0, #1024 @ 0x400 + 8000850: f7ff ff70 bl 8000734 + + /* RTC interrupt Init */ + HAL_NVIC_SetPriority(TAMP_STAMP_LSECSS_SSRU_IRQn, 0, 0); + 8000854: 2200 movs r2, #0 + 8000856: 2100 movs r1, #0 + 8000858: 2002 movs r0, #2 + 800085a: f001 f8f6 bl 8001a4a + HAL_NVIC_EnableIRQ(TAMP_STAMP_LSECSS_SSRU_IRQn); + 800085e: 2002 movs r0, #2 + 8000860: f001 f90d bl 8001a7e + HAL_NVIC_SetPriority(RTC_Alarm_IRQn, 0, 0); + 8000864: 2200 movs r2, #0 + 8000866: 2100 movs r1, #0 + 8000868: 202a movs r0, #42 @ 0x2a + 800086a: f001 f8ee bl 8001a4a + HAL_NVIC_EnableIRQ(RTC_Alarm_IRQn); + 800086e: 202a movs r0, #42 @ 0x2a + 8000870: f001 f905 bl 8001a7e + /* USER CODE BEGIN RTC_MspInit 1 */ + + /* USER CODE END RTC_MspInit 1 */ + } +} + 8000874: bf00 nop + 8000876: 3740 adds r7, #64 @ 0x40 + 8000878: 46bd mov sp, r7 + 800087a: bd80 pop {r7, pc} + 800087c: 40002800 .word 0x40002800 + +08000880 : + * @brief Clear standby and stop flags for CPU1 + * @rmtoll EXTSCR C1CSSF LL_PWR_ClearFlag_C1STOP_C1STB + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_C1STOP_C1STB(void) +{ + 8000880: b480 push {r7} + 8000882: af00 add r7, sp, #0 + WRITE_REG(PWR->EXTSCR, PWR_EXTSCR_C1CSSF); + 8000884: 4b03 ldr r3, [pc, #12] @ (8000894 ) + 8000886: 2201 movs r2, #1 + 8000888: f8c3 2088 str.w r2, [r3, #136] @ 0x88 +} + 800088c: bf00 nop + 800088e: 46bd mov sp, r7 + 8000890: bc80 pop {r7} + 8000892: 4770 bx lr + 8000894: 58000400 .word 0x58000400 + +08000898 : +/* USER CODE END PFP */ + +/* Exported functions --------------------------------------------------------*/ + +void PWR_EnterOffMode(void) +{ + 8000898: b480 push {r7} + 800089a: af00 add r7, sp, #0 + /* USER CODE BEGIN EnterOffMode_1 */ + + /* USER CODE END EnterOffMode_1 */ +} + 800089c: bf00 nop + 800089e: 46bd mov sp, r7 + 80008a0: bc80 pop {r7} + 80008a2: 4770 bx lr + +080008a4 : + +void PWR_ExitOffMode(void) +{ + 80008a4: b480 push {r7} + 80008a6: af00 add r7, sp, #0 + /* USER CODE BEGIN ExitOffMode_1 */ + + /* USER CODE END ExitOffMode_1 */ +} + 80008a8: bf00 nop + 80008aa: 46bd mov sp, r7 + 80008ac: bc80 pop {r7} + 80008ae: 4770 bx lr + +080008b0 : + +void PWR_EnterStopMode(void) +{ + 80008b0: b580 push {r7, lr} + 80008b2: af00 add r7, sp, #0 + /* USER CODE BEGIN EnterStopMode_1 */ + + /* USER CODE END EnterStopMode_1 */ + HAL_SuspendTick(); + 80008b4: f000 ffc2 bl 800183c + /* Clear Status Flag before entering STOP/STANDBY Mode */ + LL_PWR_ClearFlag_C1STOP_C1STB(); + 80008b8: f7ff ffe2 bl 8000880 + + /* USER CODE BEGIN EnterStopMode_2 */ + + /* USER CODE END EnterStopMode_2 */ + HAL_PWREx_EnterSTOP2Mode(PWR_STOPENTRY_WFI); + 80008bc: 2001 movs r0, #1 + 80008be: f002 f803 bl 80028c8 + /* USER CODE BEGIN EnterStopMode_3 */ + + /* USER CODE END EnterStopMode_3 */ +} + 80008c2: bf00 nop + 80008c4: bd80 pop {r7, pc} + +080008c6 : + +void PWR_ExitStopMode(void) +{ + 80008c6: b580 push {r7, lr} + 80008c8: af00 add r7, sp, #0 + /* USER CODE BEGIN ExitStopMode_1 */ + + /* USER CODE END ExitStopMode_1 */ + /* Resume sysTick : work around for debugger problem in dual core */ + HAL_ResumeTick(); + 80008ca: f000 ffc5 bl 8001858 + ADC interface + DAC interface USARTx, TIMx, i2Cx, SPIx + SRAM ctrls, DMAx, DMAMux, AES, RNG, HSEM */ + + /* Resume not retained USARTx and DMA */ + vcom_Resume(); + 80008ce: f000 fe11 bl 80014f4 + /* USER CODE BEGIN ExitStopMode_2 */ + + /* USER CODE END ExitStopMode_2 */ +} + 80008d2: bf00 nop + 80008d4: bd80 pop {r7, pc} + +080008d6 : + +void PWR_EnterSleepMode(void) +{ + 80008d6: b580 push {r7, lr} + 80008d8: af00 add r7, sp, #0 + /* USER CODE BEGIN EnterSleepMode_1 */ + + /* USER CODE END EnterSleepMode_1 */ + /* Suspend sysTick */ + HAL_SuspendTick(); + 80008da: f000 ffaf bl 800183c + /* USER CODE BEGIN EnterSleepMode_2 */ + + /* USER CODE END EnterSleepMode_2 */ + HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI); + 80008de: 2101 movs r1, #1 + 80008e0: 2000 movs r0, #0 + 80008e2: f001 ff6d bl 80027c0 + /* USER CODE BEGIN EnterSleepMode_3 */ + + /* USER CODE END EnterSleepMode_3 */ +} + 80008e6: bf00 nop + 80008e8: bd80 pop {r7, pc} + +080008ea : + +void PWR_ExitSleepMode(void) +{ + 80008ea: b580 push {r7, lr} + 80008ec: af00 add r7, sp, #0 + /* USER CODE BEGIN ExitSleepMode_1 */ + + /* USER CODE END ExitSleepMode_1 */ + /* Resume sysTick */ + HAL_ResumeTick(); + 80008ee: f000 ffb3 bl 8001858 + + /* USER CODE BEGIN ExitSleepMode_2 */ + + /* USER CODE END ExitSleepMode_2 */ +} + 80008f2: bf00 nop + 80008f4: bd80 pop {r7, pc} + +080008f6 : +/* USER CODE END 0 */ +/** + * Initializes the Global MSP. + */ +void HAL_MspInit(void) +{ + 80008f6: b480 push {r7} + 80008f8: af00 add r7, sp, #0 + /* System interrupt init*/ + + /* USER CODE BEGIN MspInit 1 */ + + /* USER CODE END MspInit 1 */ +} + 80008fa: bf00 nop + 80008fc: 46bd mov sp, r7 + 80008fe: bc80 pop {r7} + 8000900: 4770 bx lr + +08000902 : +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + 8000902: b480 push {r7} + 8000904: af00 add r7, sp, #0 + /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ + + /* USER CODE END NonMaskableInt_IRQn 0 */ + /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ + while (1) + 8000906: bf00 nop + 8000908: e7fd b.n 8000906 + +0800090a : + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + 800090a: b480 push {r7} + 800090c: af00 add r7, sp, #0 + /* USER CODE BEGIN HardFault_IRQn 0 */ + + /* USER CODE END HardFault_IRQn 0 */ + while (1) + 800090e: bf00 nop + 8000910: e7fd b.n 800090e + +08000912 : + +/** + * @brief This function handles Memory management fault. + */ +void MemManage_Handler(void) +{ + 8000912: b480 push {r7} + 8000914: af00 add r7, sp, #0 + /* USER CODE BEGIN MemoryManagement_IRQn 0 */ + + /* USER CODE END MemoryManagement_IRQn 0 */ + while (1) + 8000916: bf00 nop + 8000918: e7fd b.n 8000916 + +0800091a : + +/** + * @brief This function handles Prefetch fault, memory access fault. + */ +void BusFault_Handler(void) +{ + 800091a: b480 push {r7} + 800091c: af00 add r7, sp, #0 + /* USER CODE BEGIN BusFault_IRQn 0 */ + + /* USER CODE END BusFault_IRQn 0 */ + while (1) + 800091e: bf00 nop + 8000920: e7fd b.n 800091e + +08000922 : + +/** + * @brief This function handles Undefined instruction or illegal state. + */ +void UsageFault_Handler(void) +{ + 8000922: b480 push {r7} + 8000924: af00 add r7, sp, #0 + /* USER CODE BEGIN UsageFault_IRQn 0 */ + + /* USER CODE END UsageFault_IRQn 0 */ + while (1) + 8000926: bf00 nop + 8000928: e7fd b.n 8000926 + +0800092a : + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + 800092a: b480 push {r7} + 800092c: af00 add r7, sp, #0 + + /* USER CODE END SVCall_IRQn 0 */ + /* USER CODE BEGIN SVCall_IRQn 1 */ + + /* USER CODE END SVCall_IRQn 1 */ +} + 800092e: bf00 nop + 8000930: 46bd mov sp, r7 + 8000932: bc80 pop {r7} + 8000934: 4770 bx lr + +08000936 : + +/** + * @brief This function handles Debug monitor. + */ +void DebugMon_Handler(void) +{ + 8000936: b480 push {r7} + 8000938: af00 add r7, sp, #0 + + /* USER CODE END DebugMonitor_IRQn 0 */ + /* USER CODE BEGIN DebugMonitor_IRQn 1 */ + + /* USER CODE END DebugMonitor_IRQn 1 */ +} + 800093a: bf00 nop + 800093c: 46bd mov sp, r7 + 800093e: bc80 pop {r7} + 8000940: 4770 bx lr + +08000942 : + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + 8000942: b480 push {r7} + 8000944: af00 add r7, sp, #0 + + /* USER CODE END PendSV_IRQn 0 */ + /* USER CODE BEGIN PendSV_IRQn 1 */ + + /* USER CODE END PendSV_IRQn 1 */ +} + 8000946: bf00 nop + 8000948: 46bd mov sp, r7 + 800094a: bc80 pop {r7} + 800094c: 4770 bx lr + +0800094e : + +/** + * @brief This function handles System tick timer. + */ +void SysTick_Handler(void) +{ + 800094e: b480 push {r7} + 8000950: af00 add r7, sp, #0 + + /* USER CODE END SysTick_IRQn 0 */ + /* USER CODE BEGIN SysTick_IRQn 1 */ + + /* USER CODE END SysTick_IRQn 1 */ +} + 8000952: bf00 nop + 8000954: 46bd mov sp, r7 + 8000956: bc80 pop {r7} + 8000958: 4770 bx lr + ... + +0800095c : + +/** + * @brief This function handles RTC Tamper, RTC TimeStamp, LSECSS and RTC SSRU Interrupts. + */ +void TAMP_STAMP_LSECSS_SSRU_IRQHandler(void) +{ + 800095c: b580 push {r7, lr} + 800095e: af00 add r7, sp, #0 + /* USER CODE BEGIN TAMP_STAMP_LSECSS_SSRU_IRQn 0 */ + + /* USER CODE END TAMP_STAMP_LSECSS_SSRU_IRQn 0 */ + HAL_RTCEx_SSRUIRQHandler(&hrtc); + 8000960: 4802 ldr r0, [pc, #8] @ (800096c ) + 8000962: f003 fe33 bl 80045cc + /* USER CODE BEGIN TAMP_STAMP_LSECSS_SSRU_IRQn 1 */ + + /* USER CODE END TAMP_STAMP_LSECSS_SSRU_IRQn 1 */ +} + 8000966: bf00 nop + 8000968: bd80 pop {r7, pc} + 800096a: bf00 nop + 800096c: 20000040 .word 0x20000040 + +08000970 : + +/** + * @brief This function handles EXTI Line 0 Interrupt. + */ +void EXTI0_IRQHandler(void) +{ + 8000970: b580 push {r7, lr} + 8000972: af00 add r7, sp, #0 + /* USER CODE BEGIN EXTI0_IRQn 0 */ + + /* USER CODE END EXTI0_IRQn 0 */ + HAL_GPIO_EXTI_IRQHandler(BUT1_Pin); + 8000974: 2001 movs r0, #1 + 8000976: f001 fefd bl 8002774 + /* USER CODE BEGIN EXTI0_IRQn 1 */ + + /* USER CODE END EXTI0_IRQn 1 */ +} + 800097a: bf00 nop + 800097c: bd80 pop {r7, pc} + +0800097e : + +/** + * @brief This function handles EXTI Line 1 Interrupt. + */ +void EXTI1_IRQHandler(void) +{ + 800097e: b580 push {r7, lr} + 8000980: af00 add r7, sp, #0 + /* USER CODE BEGIN EXTI1_IRQn 0 */ + + /* USER CODE END EXTI1_IRQn 0 */ + HAL_GPIO_EXTI_IRQHandler(BUT2_Pin); + 8000982: 2002 movs r0, #2 + 8000984: f001 fef6 bl 8002774 + /* USER CODE BEGIN EXTI1_IRQn 1 */ + + /* USER CODE END EXTI1_IRQn 1 */ +} + 8000988: bf00 nop + 800098a: bd80 pop {r7, pc} + +0800098c : + +/** + * @brief This function handles DMA1 Channel 5 Interrupt. + */ +void DMA1_Channel5_IRQHandler(void) +{ + 800098c: b580 push {r7, lr} + 800098e: af00 add r7, sp, #0 + /* USER CODE BEGIN DMA1_Channel5_IRQn 0 */ + + /* USER CODE END DMA1_Channel5_IRQn 0 */ + HAL_DMA_IRQHandler(&hdma_usart2_tx); + 8000990: 4802 ldr r0, [pc, #8] @ (800099c ) + 8000992: f001 fb0b bl 8001fac + /* USER CODE BEGIN DMA1_Channel5_IRQn 1 */ + + /* USER CODE END DMA1_Channel5_IRQn 1 */ +} + 8000996: bf00 nop + 8000998: bd80 pop {r7, pc} + 800099a: bf00 nop + 800099c: 20000120 .word 0x20000120 + +080009a0 : + +/** + * @brief This function handles EXTI Lines [9:5] Interrupt. + */ +void EXTI9_5_IRQHandler(void) +{ + 80009a0: b580 push {r7, lr} + 80009a2: af00 add r7, sp, #0 + /* USER CODE BEGIN EXTI9_5_IRQn 0 */ + + /* USER CODE END EXTI9_5_IRQn 0 */ + HAL_GPIO_EXTI_IRQHandler(BUT3_Pin); + 80009a4: 2040 movs r0, #64 @ 0x40 + 80009a6: f001 fee5 bl 8002774 + /* USER CODE BEGIN EXTI9_5_IRQn 1 */ + + /* USER CODE END EXTI9_5_IRQn 1 */ +} + 80009aa: bf00 nop + 80009ac: bd80 pop {r7, pc} + ... + +080009b0 : + +/** + * @brief This function handles USART2 Interrupt. + */ +void USART2_IRQHandler(void) +{ + 80009b0: b580 push {r7, lr} + 80009b2: af00 add r7, sp, #0 + /* USER CODE BEGIN USART2_IRQn 0 */ + + /* USER CODE END USART2_IRQn 0 */ + HAL_UART_IRQHandler(&huart2); + 80009b4: 4802 ldr r0, [pc, #8] @ (80009c0 ) + 80009b6: f004 fc65 bl 8005284 + /* USER CODE BEGIN USART2_IRQn 1 */ + + /* USER CODE END USART2_IRQn 1 */ +} + 80009ba: bf00 nop + 80009bc: bd80 pop {r7, pc} + 80009be: bf00 nop + 80009c0: 2000008c .word 0x2000008c + +080009c4 : + +/** + * @brief This function handles RTC Alarms (A and B) Interrupt. + */ +void RTC_Alarm_IRQHandler(void) +{ + 80009c4: b580 push {r7, lr} + 80009c6: af00 add r7, sp, #0 + /* USER CODE BEGIN RTC_Alarm_IRQn 0 */ + + /* USER CODE END RTC_Alarm_IRQn 0 */ + HAL_RTC_AlarmIRQHandler(&hrtc); + 80009c8: 4802 ldr r0, [pc, #8] @ (80009d4 ) + 80009ca: f003 fcaf bl 800432c + /* USER CODE BEGIN RTC_Alarm_IRQn 1 */ + + /* USER CODE END RTC_Alarm_IRQn 1 */ +} + 80009ce: bf00 nop + 80009d0: bd80 pop {r7, pc} + 80009d2: bf00 nop + 80009d4: 20000040 .word 0x20000040 + +080009d8 : + +/** + * @brief This function handles SUBGHZ Radio Interrupt. + */ +void SUBGHZ_Radio_IRQHandler(void) +{ + 80009d8: b580 push {r7, lr} + 80009da: af00 add r7, sp, #0 + /* USER CODE BEGIN SUBGHZ_Radio_IRQn 0 */ + + /* USER CODE END SUBGHZ_Radio_IRQn 0 */ + HAL_SUBGHZ_IRQHandler(&hsubghz); + 80009dc: 4802 ldr r0, [pc, #8] @ (80009e8 ) + 80009de: f004 f963 bl 8004ca8 + /* USER CODE BEGIN SUBGHZ_Radio_IRQn 1 */ + + /* USER CODE END SUBGHZ_Radio_IRQn 1 */ +} + 80009e2: bf00 nop + 80009e4: bd80 pop {r7, pc} + 80009e6: bf00 nop + 80009e8: 20000078 .word 0x20000078 + +080009ec : + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB3_GRP1_PERIPH_SUBGHZSPI + * @retval None + */ +__STATIC_INLINE void LL_APB3_GRP1_EnableClock(uint32_t Periphs) +{ + 80009ec: b480 push {r7} + 80009ee: b085 sub sp, #20 + 80009f0: af00 add r7, sp, #0 + 80009f2: 6078 str r0, [r7, #4] + __IO uint32_t tmpreg; + SET_BIT(RCC->APB3ENR, Periphs); + 80009f4: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 80009f8: 6e5a ldr r2, [r3, #100] @ 0x64 + 80009fa: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 80009fe: 687b ldr r3, [r7, #4] + 8000a00: 4313 orrs r3, r2 + 8000a02: 664b str r3, [r1, #100] @ 0x64 + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB3ENR, Periphs); + 8000a04: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8000a08: 6e5a ldr r2, [r3, #100] @ 0x64 + 8000a0a: 687b ldr r3, [r7, #4] + 8000a0c: 4013 ands r3, r2 + 8000a0e: 60fb str r3, [r7, #12] + (void)tmpreg; + 8000a10: 68fb ldr r3, [r7, #12] +} + 8000a12: bf00 nop + 8000a14: 3714 adds r7, #20 + 8000a16: 46bd mov sp, r7 + 8000a18: bc80 pop {r7} + 8000a1a: 4770 bx lr + +08000a1c : + +SUBGHZ_HandleTypeDef hsubghz; + +/* SUBGHZ init function */ +void MX_SUBGHZ_Init(void) +{ + 8000a1c: b580 push {r7, lr} + 8000a1e: af00 add r7, sp, #0 + /* USER CODE END SUBGHZ_Init 0 */ + + /* USER CODE BEGIN SUBGHZ_Init 1 */ + + /* USER CODE END SUBGHZ_Init 1 */ + hsubghz.Init.BaudratePrescaler = SUBGHZSPI_BAUDRATEPRESCALER_4; + 8000a20: 4b06 ldr r3, [pc, #24] @ (8000a3c ) + 8000a22: 2208 movs r2, #8 + 8000a24: 601a str r2, [r3, #0] + if (HAL_SUBGHZ_Init(&hsubghz) != HAL_OK) + 8000a26: 4805 ldr r0, [pc, #20] @ (8000a3c ) + 8000a28: f003 febc bl 80047a4 + 8000a2c: 4603 mov r3, r0 + 8000a2e: 2b00 cmp r3, #0 + 8000a30: d001 beq.n 8000a36 + { + Error_Handler(); + 8000a32: f7ff fe69 bl 8000708 + } + /* USER CODE BEGIN SUBGHZ_Init 2 */ + + /* USER CODE END SUBGHZ_Init 2 */ + +} + 8000a36: bf00 nop + 8000a38: bd80 pop {r7, pc} + 8000a3a: bf00 nop + 8000a3c: 20000078 .word 0x20000078 + +08000a40 : + +void HAL_SUBGHZ_MspInit(SUBGHZ_HandleTypeDef* subghzHandle) +{ + 8000a40: b580 push {r7, lr} + 8000a42: b082 sub sp, #8 + 8000a44: af00 add r7, sp, #0 + 8000a46: 6078 str r0, [r7, #4] + + /* USER CODE BEGIN SUBGHZ_MspInit 0 */ + + /* USER CODE END SUBGHZ_MspInit 0 */ + /* SUBGHZ clock enable */ + __HAL_RCC_SUBGHZSPI_CLK_ENABLE(); + 8000a48: 2001 movs r0, #1 + 8000a4a: f7ff ffcf bl 80009ec + + /* SUBGHZ interrupt Init */ + HAL_NVIC_SetPriority(SUBGHZ_Radio_IRQn, 0, 0); + 8000a4e: 2200 movs r2, #0 + 8000a50: 2100 movs r1, #0 + 8000a52: 2032 movs r0, #50 @ 0x32 + 8000a54: f000 fff9 bl 8001a4a + HAL_NVIC_EnableIRQ(SUBGHZ_Radio_IRQn); + 8000a58: 2032 movs r0, #50 @ 0x32 + 8000a5a: f001 f810 bl 8001a7e + /* USER CODE BEGIN SUBGHZ_MspInit 1 */ + + /* USER CODE END SUBGHZ_MspInit 1 */ +} + 8000a5e: bf00 nop + 8000a60: 3708 adds r7, #8 + 8000a62: 46bd mov sp, r7 + 8000a64: bd80 pop {r7, pc} + +08000a66 : +{ + 8000a66: b480 push {r7} + 8000a68: b083 sub sp, #12 + 8000a6a: af00 add r7, sp, #0 + 8000a6c: 6078 str r0, [r7, #4] + MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, Clock); + 8000a6e: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8000a72: 689b ldr r3, [r3, #8] + 8000a74: f423 4200 bic.w r2, r3, #32768 @ 0x8000 + 8000a78: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 8000a7c: 687b ldr r3, [r7, #4] + 8000a7e: 4313 orrs r3, r2 + 8000a80: 608b str r3, [r1, #8] +} + 8000a82: bf00 nop + 8000a84: 370c adds r7, #12 + 8000a86: 46bd mov sp, r7 + 8000a88: bc80 pop {r7} + 8000a8a: 4770 bx lr + +08000a8c : + +/* USER CODE END PFP */ + +/* Exported functions ---------------------------------------------------------*/ +void SystemApp_Init(void) +{ + 8000a8c: b580 push {r7, lr} + 8000a8e: af00 add r7, sp, #0 + /* USER CODE BEGIN SystemApp_Init_1 */ + + /* USER CODE END SystemApp_Init_1 */ + + /* Ensure that MSI is wake-up system clock */ + __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(RCC_STOP_WAKEUPCLOCK_MSI); + 8000a90: 2000 movs r0, #0 + 8000a92: f7ff ffe8 bl 8000a66 + + /*Initialize timer and RTC*/ + UTIL_TIMER_Init(); + 8000a96: f00b ffc9 bl 800ca2c + SYS_TimerInitialisedFlag = 1; + 8000a9a: 4b0c ldr r3, [pc, #48] @ (8000acc ) + 8000a9c: 2201 movs r2, #1 + 8000a9e: 701a strb r2, [r3, #0] + /* Initializes the SW probes pins and the monitor RF pins via Alternate Function */ + DBG_Init(); + 8000aa0: f000 f8ba bl 8000c18 + + /*Initialize the terminal */ + UTIL_ADV_TRACE_Init(); + 8000aa4: f00c fa52 bl 800cf4c + UTIL_ADV_TRACE_RegisterTimeStampFunction(TimestampNow); + 8000aa8: 4809 ldr r0, [pc, #36] @ (8000ad0 ) + 8000aaa: f00c faeb bl 800d084 + + /*Set verbose LEVEL*/ + UTIL_ADV_TRACE_SetVerboseLevel(VERBOSE_LEVEL); + 8000aae: 2002 movs r0, #2 + 8000ab0: f00c faf6 bl 800d0a0 + + /*Init low power manager*/ + UTIL_LPM_Init(); + 8000ab4: f00b fa74 bl 800bfa0 + /* Disable Stand-by mode */ + UTIL_LPM_SetOffMode((1 << CFG_LPM_APPLI_Id), UTIL_LPM_DISABLE); + 8000ab8: 2101 movs r1, #1 + 8000aba: 2001 movs r0, #1 + 8000abc: f00b fab0 bl 800c020 + +#if defined (LOW_POWER_DISABLE) && (LOW_POWER_DISABLE == 1) + /* Disable Stop Mode */ + UTIL_LPM_SetStopMode((1 << CFG_LPM_APPLI_Id), UTIL_LPM_DISABLE); + 8000ac0: 2101 movs r1, #1 + 8000ac2: 2001 movs r0, #1 + 8000ac4: f00b fa7c bl 800bfc0 +#endif /* LOW_POWER_DISABLE */ + + /* USER CODE BEGIN SystemApp_Init_2 */ + + /* USER CODE END SystemApp_Init_2 */ +} + 8000ac8: bf00 nop + 8000aca: bd80 pop {r7, pc} + 8000acc: 20000084 .word 0x20000084 + 8000ad0: 08000ae1 .word 0x08000ae1 + +08000ad4 : + +/** + * @brief redefines __weak function in stm32_seq.c such to enter low power + */ +void UTIL_SEQ_Idle(void) +{ + 8000ad4: b580 push {r7, lr} + 8000ad6: af00 add r7, sp, #0 + /* USER CODE BEGIN UTIL_SEQ_Idle_1 */ + + /* USER CODE END UTIL_SEQ_Idle_1 */ + UTIL_LPM_EnterLowPower(); + 8000ad8: f00b fad2 bl 800c080 + /* USER CODE BEGIN UTIL_SEQ_Idle_2 */ + + /* USER CODE END UTIL_SEQ_Idle_2 */ +} + 8000adc: bf00 nop + 8000ade: bd80 pop {r7, pc} + +08000ae0 : +/* USER CODE END EF */ + +/* Private functions ---------------------------------------------------------*/ + +static void TimestampNow(uint8_t *buff, uint16_t *size) +{ + 8000ae0: b580 push {r7, lr} + 8000ae2: b086 sub sp, #24 + 8000ae4: af02 add r7, sp, #8 + 8000ae6: 6078 str r0, [r7, #4] + 8000ae8: 6039 str r1, [r7, #0] + /* USER CODE BEGIN TimestampNow_1 */ + + /* USER CODE END TimestampNow_1 */ + SysTime_t curtime = SysTimeGet(); + 8000aea: f107 0308 add.w r3, r7, #8 + 8000aee: 4618 mov r0, r3 + 8000af0: f00b fb70 bl 800c1d4 + tiny_snprintf_like((char *)buff, MAX_TS_SIZE, "%ds%03d:", curtime.Seconds, curtime.SubSeconds); + 8000af4: 68bb ldr r3, [r7, #8] + 8000af6: f9b7 200c ldrsh.w r2, [r7, #12] + 8000afa: 9200 str r2, [sp, #0] + 8000afc: 4a07 ldr r2, [pc, #28] @ (8000b1c ) + 8000afe: 2110 movs r1, #16 + 8000b00: 6878 ldr r0, [r7, #4] + 8000b02: f000 f81d bl 8000b40 + *size = strlen((char *)buff); + 8000b06: 6878 ldr r0, [r7, #4] + 8000b08: f7ff fb36 bl 8000178 + 8000b0c: 4603 mov r3, r0 + 8000b0e: b29a uxth r2, r3 + 8000b10: 683b ldr r3, [r7, #0] + 8000b12: 801a strh r2, [r3, #0] + /* USER CODE BEGIN TimestampNow_2 */ + + /* USER CODE END TimestampNow_2 */ +} + 8000b14: bf00 nop + 8000b16: 3710 adds r7, #16 + 8000b18: 46bd mov sp, r7 + 8000b1a: bd80 pop {r7, pc} + 8000b1c: 0800d500 .word 0x0800d500 + +08000b20 : + +/* Disable StopMode when traces need to be printed */ +void UTIL_ADV_TRACE_PreSendHook(void) +{ + 8000b20: b580 push {r7, lr} + 8000b22: af00 add r7, sp, #0 + /* USER CODE BEGIN UTIL_ADV_TRACE_PreSendHook_1 */ + + /* USER CODE END UTIL_ADV_TRACE_PreSendHook_1 */ + UTIL_LPM_SetStopMode((1 << CFG_LPM_UART_TX_Id), UTIL_LPM_DISABLE); + 8000b24: 2101 movs r1, #1 + 8000b26: 2002 movs r0, #2 + 8000b28: f00b fa4a bl 800bfc0 + /* USER CODE BEGIN UTIL_ADV_TRACE_PreSendHook_2 */ + + /* USER CODE END UTIL_ADV_TRACE_PreSendHook_2 */ +} + 8000b2c: bf00 nop + 8000b2e: bd80 pop {r7, pc} + +08000b30 : +/* Re-enable StopMode when traces have been printed */ +void UTIL_ADV_TRACE_PostSendHook(void) +{ + 8000b30: b580 push {r7, lr} + 8000b32: af00 add r7, sp, #0 + /* USER CODE BEGIN UTIL_LPM_SetStopMode_1 */ + + /* USER CODE END UTIL_LPM_SetStopMode_1 */ + UTIL_LPM_SetStopMode((1 << CFG_LPM_UART_TX_Id), UTIL_LPM_ENABLE); + 8000b34: 2100 movs r1, #0 + 8000b36: 2002 movs r0, #2 + 8000b38: f00b fa42 bl 800bfc0 + /* USER CODE BEGIN UTIL_LPM_SetStopMode_2 */ + + /* USER CODE END UTIL_LPM_SetStopMode_2 */ +} + 8000b3c: bf00 nop + 8000b3e: bd80 pop {r7, pc} + +08000b40 : + +static void tiny_snprintf_like(char *buf, uint32_t maxsize, const char *strFormat, ...) +{ + 8000b40: b40c push {r2, r3} + 8000b42: b580 push {r7, lr} + 8000b44: b084 sub sp, #16 + 8000b46: af00 add r7, sp, #0 + 8000b48: 6078 str r0, [r7, #4] + 8000b4a: 6039 str r1, [r7, #0] + /* USER CODE BEGIN tiny_snprintf_like_1 */ + + /* USER CODE END tiny_snprintf_like_1 */ + va_list vaArgs; + va_start(vaArgs, strFormat); + 8000b4c: f107 031c add.w r3, r7, #28 + 8000b50: 60fb str r3, [r7, #12] + UTIL_ADV_TRACE_VSNPRINTF(buf, maxsize, strFormat, vaArgs); + 8000b52: 6839 ldr r1, [r7, #0] + 8000b54: 68fb ldr r3, [r7, #12] + 8000b56: 69ba ldr r2, [r7, #24] + 8000b58: 6878 ldr r0, [r7, #4] + 8000b5a: f00b fc87 bl 800c46c + va_end(vaArgs); + /* USER CODE BEGIN tiny_snprintf_like_2 */ + + /* USER CODE END tiny_snprintf_like_2 */ +} + 8000b5e: bf00 nop + 8000b60: 3710 adds r7, #16 + 8000b62: 46bd mov sp, r7 + 8000b64: e8bd 4080 ldmia.w sp!, {r7, lr} + 8000b68: b002 add sp, #8 + 8000b6a: 4770 bx lr + +08000b6c : + +/** + * @note This function overwrites the __weak one from HAL + */ +HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) +{ + 8000b6c: b480 push {r7} + 8000b6e: b083 sub sp, #12 + 8000b70: af00 add r7, sp, #0 + 8000b72: 6078 str r0, [r7, #4] + /*Don't enable SysTick if TIMER_IF is based on other counters (e.g. RTC) */ + /* USER CODE BEGIN HAL_InitTick_1 */ + + /* USER CODE END HAL_InitTick_1 */ + return HAL_OK; + 8000b74: 2300 movs r3, #0 + /* USER CODE BEGIN HAL_InitTick_2 */ + + /* USER CODE END HAL_InitTick_2 */ +} + 8000b76: 4618 mov r0, r3 + 8000b78: 370c adds r7, #12 + 8000b7a: 46bd mov sp, r7 + 8000b7c: bc80 pop {r7} + 8000b7e: 4770 bx lr + +08000b80 : + +/** + * @note This function overwrites the __weak one from HAL + */ +uint32_t HAL_GetTick(void) +{ + 8000b80: b580 push {r7, lr} + 8000b82: b082 sub sp, #8 + 8000b84: af00 add r7, sp, #0 + uint32_t ret = 0; + 8000b86: 2300 movs r3, #0 + 8000b88: 607b str r3, [r7, #4] + /* TIMER_IF can be based on other counter the SysTick e.g. RTC */ + /* USER CODE BEGIN HAL_GetTick_1 */ + + /* USER CODE END HAL_GetTick_1 */ + if (SYS_TimerInitialisedFlag == 0) + 8000b8a: 4b06 ldr r3, [pc, #24] @ (8000ba4 ) + 8000b8c: 781b ldrb r3, [r3, #0] + 8000b8e: 2b00 cmp r3, #0 + 8000b90: d002 beq.n 8000b98 + + /* USER CODE END HAL_GetTick_EarlyCall */ + } + else + { + ret = TIMER_IF_GetTimerValue(); + 8000b92: f000 f945 bl 8000e20 + 8000b96: 6078 str r0, [r7, #4] + } + /* USER CODE BEGIN HAL_GetTick_2 */ + + /* USER CODE END HAL_GetTick_2 */ + return ret; + 8000b98: 687b ldr r3, [r7, #4] +} + 8000b9a: 4618 mov r0, r3 + 8000b9c: 3708 adds r7, #8 + 8000b9e: 46bd mov sp, r7 + 8000ba0: bd80 pop {r7, pc} + 8000ba2: bf00 nop + 8000ba4: 20000084 .word 0x20000084 + +08000ba8 : + +/** + * @note This function overwrites the __weak one from HAL + */ +void HAL_Delay(__IO uint32_t Delay) +{ + 8000ba8: b580 push {r7, lr} + 8000baa: b082 sub sp, #8 + 8000bac: af00 add r7, sp, #0 + 8000bae: 6078 str r0, [r7, #4] + /* TIMER_IF can be based on other counter the SysTick e.g. RTC */ + /* USER CODE BEGIN HAL_Delay_1 */ + + /* USER CODE END HAL_Delay_1 */ + TIMER_IF_DelayMs(Delay); + 8000bb0: 687b ldr r3, [r7, #4] + 8000bb2: 4618 mov r0, r3 + 8000bb4: f000 f9bb bl 8000f2e + /* USER CODE BEGIN HAL_Delay_2 */ + + /* USER CODE END HAL_Delay_2 */ +} + 8000bb8: bf00 nop + 8000bba: 3708 adds r7, #8 + 8000bbc: 46bd mov sp, r7 + 8000bbe: bd80 pop {r7, pc} + +08000bc0 : +{ + 8000bc0: b480 push {r7} + 8000bc2: b085 sub sp, #20 + 8000bc4: af00 add r7, sp, #0 + 8000bc6: 6078 str r0, [r7, #4] + SET_BIT(RCC->AHB2ENR, Periphs); + 8000bc8: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8000bcc: 6cda ldr r2, [r3, #76] @ 0x4c + 8000bce: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 8000bd2: 687b ldr r3, [r7, #4] + 8000bd4: 4313 orrs r3, r2 + 8000bd6: 64cb str r3, [r1, #76] @ 0x4c + tmpreg = READ_BIT(RCC->AHB2ENR, Periphs); + 8000bd8: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8000bdc: 6cda ldr r2, [r3, #76] @ 0x4c + 8000bde: 687b ldr r3, [r7, #4] + 8000be0: 4013 ands r3, r2 + 8000be2: 60fb str r3, [r7, #12] + (void)tmpreg; + 8000be4: 68fb ldr r3, [r7, #12] +} + 8000be6: bf00 nop + 8000be8: 3714 adds r7, #20 + 8000bea: 46bd mov sp, r7 + 8000bec: bc80 pop {r7} + 8000bee: 4770 bx lr + +08000bf0 : + * @arg @ref LL_EXTI_LINE_ALL_32_63 + * (*) value not defined in all devices + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableIT_32_63(uint32_t ExtiLine) +{ + 8000bf0: b480 push {r7} + 8000bf2: b083 sub sp, #12 + 8000bf4: af00 add r7, sp, #0 + 8000bf6: 6078 str r0, [r7, #4] + SET_BIT(EXTI->IMR2, ExtiLine); + 8000bf8: 4b06 ldr r3, [pc, #24] @ (8000c14 ) + 8000bfa: f8d3 2090 ldr.w r2, [r3, #144] @ 0x90 + 8000bfe: 4905 ldr r1, [pc, #20] @ (8000c14 ) + 8000c00: 687b ldr r3, [r7, #4] + 8000c02: 4313 orrs r3, r2 + 8000c04: f8c1 3090 str.w r3, [r1, #144] @ 0x90 +} + 8000c08: bf00 nop + 8000c0a: 370c adds r7, #12 + 8000c0c: 46bd mov sp, r7 + 8000c0e: bc80 pop {r7} + 8000c10: 4770 bx lr + 8000c12: bf00 nop + 8000c14: 58000800 .word 0x58000800 + +08000c18 : + +/** + * @brief Initializes the SW probes pins and the monitor RF pins via Alternate Function + */ +void DBG_Init(void) +{ + 8000c18: b580 push {r7, lr} + 8000c1a: b086 sub sp, #24 + 8000c1c: af00 add r7, sp, #0 + HAL_DBGMCU_DisableDBGSleepMode(); + HAL_DBGMCU_DisableDBGStopMode(); + HAL_DBGMCU_DisableDBGStandbyMode(); +#elif defined (DEBUGGER_ENABLED) && ( DEBUGGER_ENABLED == 1 ) + /*Debug power up request wakeup CBDGPWRUPREQ*/ + LL_EXTI_EnableIT_32_63(LL_EXTI_LINE_46); + 8000c1e: f44f 4080 mov.w r0, #16384 @ 0x4000 + 8000c22: f7ff ffe5 bl 8000bf0 + /* Disabled HAL_DBGMCU_ */ + HAL_DBGMCU_EnableDBGSleepMode(); + 8000c26: f000 fe25 bl 8001874 + HAL_DBGMCU_EnableDBGStopMode(); + 8000c2a: f000 fe29 bl 8001880 + HAL_DBGMCU_EnableDBGStandbyMode(); + 8000c2e: f000 fe2d bl 800188c +#elif !defined (DEBUGGER_ENABLED) +#error "DEBUGGER_ENABLED not defined or out of range <0,1>" +#endif /* DEBUGGER_OFF */ + + GPIO_InitTypeDef GPIO_InitStruct = {0}; + 8000c32: 1d3b adds r3, r7, #4 + 8000c34: 2200 movs r2, #0 + 8000c36: 601a str r2, [r3, #0] + 8000c38: 605a str r2, [r3, #4] + 8000c3a: 609a str r2, [r3, #8] + 8000c3c: 60da str r2, [r3, #12] + 8000c3e: 611a str r2, [r3, #16] + + /* Configure the GPIO pin */ + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + 8000c40: 2301 movs r3, #1 + 8000c42: 60bb str r3, [r7, #8] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8000c44: 2300 movs r3, #0 + 8000c46: 60fb str r3, [r7, #12] + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + 8000c48: 2303 movs r3, #3 + 8000c4a: 613b str r3, [r7, #16] + + /* Enable the GPIO Clock */ + PROBE_LINE1_CLK_ENABLE(); + 8000c4c: 2002 movs r0, #2 + 8000c4e: f7ff ffb7 bl 8000bc0 + PROBE_LINE2_CLK_ENABLE(); + 8000c52: 2002 movs r0, #2 + 8000c54: f7ff ffb4 bl 8000bc0 + + GPIO_InitStruct.Pin = PROBE_LINE1_PIN; + 8000c58: f44f 5380 mov.w r3, #4096 @ 0x1000 + 8000c5c: 607b str r3, [r7, #4] + HAL_GPIO_Init(PROBE_LINE1_PORT, &GPIO_InitStruct); + 8000c5e: 1d3b adds r3, r7, #4 + 8000c60: 4619 mov r1, r3 + 8000c62: 480d ldr r0, [pc, #52] @ (8000c98 ) + 8000c64: f001 fb40 bl 80022e8 + GPIO_InitStruct.Pin = PROBE_LINE2_PIN; + 8000c68: f44f 5300 mov.w r3, #8192 @ 0x2000 + 8000c6c: 607b str r3, [r7, #4] + HAL_GPIO_Init(PROBE_LINE2_PORT, &GPIO_InitStruct); + 8000c6e: 1d3b adds r3, r7, #4 + 8000c70: 4619 mov r1, r3 + 8000c72: 4809 ldr r0, [pc, #36] @ (8000c98 ) + 8000c74: f001 fb38 bl 80022e8 + + /* Reset probe Pins */ + HAL_GPIO_WritePin(PROBE_LINE1_PORT, PROBE_LINE1_PIN, GPIO_PIN_RESET); + 8000c78: 2200 movs r2, #0 + 8000c7a: f44f 5180 mov.w r1, #4096 @ 0x1000 + 8000c7e: 4806 ldr r0, [pc, #24] @ (8000c98 ) + 8000c80: f001 fd60 bl 8002744 + HAL_GPIO_WritePin(PROBE_LINE2_PORT, PROBE_LINE2_PIN, GPIO_PIN_RESET); + 8000c84: 2200 movs r2, #0 + 8000c86: f44f 5100 mov.w r1, #8192 @ 0x2000 + 8000c8a: 4803 ldr r0, [pc, #12] @ (8000c98 ) + 8000c8c: f001 fd5a bl 8002744 +#endif /* DEBUG_RF_BUSY_ENABLED */ + + /* USER CODE BEGIN DBG_Init_3 */ + + /* USER CODE END DBG_Init_3 */ +} + 8000c90: bf00 nop + 8000c92: 3718 adds r7, #24 + 8000c94: 46bd mov sp, r7 + 8000c96: bd80 pop {r7, pc} + 8000c98: 48000400 .word 0x48000400 + +08000c9c : + * @brief Setup the microcontroller system. + * @param None + * @retval None + */ +void SystemInit(void) +{ + 8000c9c: b480 push {r7} + 8000c9e: af00 add r7, sp, #0 + + /* FPU settings ------------------------------------------------------------*/ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << (10UL*2UL))|(3UL << (11UL*2UL))); /* set CP10 and CP11 Full Access */ +#endif +} + 8000ca0: bf00 nop + 8000ca2: 46bd mov sp, r7 + 8000ca4: bc80 pop {r7} + 8000ca6: 4770 bx lr + +08000ca8 : + * @param RTCx RTC Instance + * @retval If binary mode is none, Value between Min_Data=0x0 and Max_Data=0x7FFF + * else Value between Min_Data=0x0 and Max_Data=0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_RTC_TIME_GetSubSecond(const RTC_TypeDef *RTCx) +{ + 8000ca8: b480 push {r7} + 8000caa: b083 sub sp, #12 + 8000cac: af00 add r7, sp, #0 + 8000cae: 6078 str r0, [r7, #4] + return (uint32_t)(READ_BIT(RTCx->SSR, RTC_SSR_SS)); + 8000cb0: 687b ldr r3, [r7, #4] + 8000cb2: 689b ldr r3, [r3, #8] +} + 8000cb4: 4618 mov r0, r3 + 8000cb6: 370c adds r7, #12 + 8000cb8: 46bd mov sp, r7 + 8000cba: bc80 pop {r7} + 8000cbc: 4770 bx lr + ... + +08000cc0 : + +/* USER CODE END PFP */ + +/* Exported functions ---------------------------------------------------------*/ +UTIL_TIMER_Status_t TIMER_IF_Init(void) +{ + 8000cc0: b580 push {r7, lr} + 8000cc2: b082 sub sp, #8 + 8000cc4: af00 add r7, sp, #0 + UTIL_TIMER_Status_t ret = UTIL_TIMER_OK; + 8000cc6: 2300 movs r3, #0 + 8000cc8: 71fb strb r3, [r7, #7] + /* USER CODE BEGIN TIMER_IF_Init */ + + /* USER CODE END TIMER_IF_Init */ + if (RTC_Initialized == false) + 8000cca: 4b14 ldr r3, [pc, #80] @ (8000d1c ) + 8000ccc: 781b ldrb r3, [r3, #0] + 8000cce: f083 0301 eor.w r3, r3, #1 + 8000cd2: b2db uxtb r3, r3 + 8000cd4: 2b00 cmp r3, #0 + 8000cd6: d01b beq.n 8000d10 + { + hrtc.IsEnabled.RtcFeatures = UINT32_MAX; + 8000cd8: 4b11 ldr r3, [pc, #68] @ (8000d20 ) + 8000cda: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff + 8000cde: 631a str r2, [r3, #48] @ 0x30 + /*Init RTC*/ + MX_RTC_Init(); + 8000ce0: f7ff fd40 bl 8000764 + /*Stop Timer */ + TIMER_IF_StopTimer(); + 8000ce4: f000 f856 bl 8000d94 + /** DeActivate the Alarm A enabled by STM32CubeMX during MX_RTC_Init() */ + HAL_RTC_DeactivateAlarm(&hrtc, RTC_ALARM_A); + 8000ce8: f44f 7180 mov.w r1, #256 @ 0x100 + 8000cec: 480c ldr r0, [pc, #48] @ (8000d20 ) + 8000cee: f003 fac1 bl 8004274 + /*overload RTC feature enable*/ + hrtc.IsEnabled.RtcFeatures = UINT32_MAX; + 8000cf2: 4b0b ldr r3, [pc, #44] @ (8000d20 ) + 8000cf4: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff + 8000cf8: 631a str r2, [r3, #48] @ 0x30 + + /*Enable Direct Read of the calendar registers (not through Shadow) */ + HAL_RTCEx_EnableBypassShadow(&hrtc); + 8000cfa: 4809 ldr r0, [pc, #36] @ (8000d20 ) + 8000cfc: f003 fbf8 bl 80044f0 + /*Initialize MSB ticks*/ + TIMER_IF_BkUp_Write_MSBticks(0); + 8000d00: 2000 movs r0, #0 + 8000d02: f000 f9d3 bl 80010ac + + TIMER_IF_SetTimerContext(); + 8000d06: f000 f85f bl 8000dc8 + + /* Register a task to associate to UTIL_TIMER_Irq() interrupt */ + UTIL_TIMER_IRQ_MAP_INIT(); + + RTC_Initialized = true; + 8000d0a: 4b04 ldr r3, [pc, #16] @ (8000d1c ) + 8000d0c: 2201 movs r2, #1 + 8000d0e: 701a strb r2, [r3, #0] + } + + /* USER CODE BEGIN TIMER_IF_Init_Last */ + + /* USER CODE END TIMER_IF_Init_Last */ + return ret; + 8000d10: 79fb ldrb r3, [r7, #7] +} + 8000d12: 4618 mov r0, r3 + 8000d14: 3708 adds r7, #8 + 8000d16: 46bd mov sp, r7 + 8000d18: bd80 pop {r7, pc} + 8000d1a: bf00 nop + 8000d1c: 20000085 .word 0x20000085 + 8000d20: 20000040 .word 0x20000040 + +08000d24 : + +UTIL_TIMER_Status_t TIMER_IF_StartTimer(uint32_t timeout) +{ + 8000d24: b580 push {r7, lr} + 8000d26: b08e sub sp, #56 @ 0x38 + 8000d28: af00 add r7, sp, #0 + 8000d2a: 6078 str r0, [r7, #4] + UTIL_TIMER_Status_t ret = UTIL_TIMER_OK; + 8000d2c: 2300 movs r3, #0 + 8000d2e: f887 3037 strb.w r3, [r7, #55] @ 0x37 + /* USER CODE BEGIN TIMER_IF_StartTimer */ + + /* USER CODE END TIMER_IF_StartTimer */ + RTC_AlarmTypeDef sAlarm = {0}; + 8000d32: f107 0308 add.w r3, r7, #8 + 8000d36: 222c movs r2, #44 @ 0x2c + 8000d38: 2100 movs r1, #0 + 8000d3a: 4618 mov r0, r3 + 8000d3c: f00c fb9a bl 800d474 + /*Stop timer if one is already started*/ + TIMER_IF_StopTimer(); + 8000d40: f000 f828 bl 8000d94 + timeout += RtcTimerContext; + 8000d44: 4b11 ldr r3, [pc, #68] @ (8000d8c ) + 8000d46: 681b ldr r3, [r3, #0] + 8000d48: 687a ldr r2, [r7, #4] + 8000d4a: 4413 add r3, r2 + 8000d4c: 607b str r3, [r7, #4] + + TIMER_IF_DBG_PRINTF("Start timer: time=%d, alarm=%d\n\r", GetTimerTicks(), timeout); + /* starts timer*/ + sAlarm.BinaryAutoClr = RTC_ALARMSUBSECONDBIN_AUTOCLR_NO; + 8000d4e: 2300 movs r3, #0 + 8000d50: 627b str r3, [r7, #36] @ 0x24 + sAlarm.AlarmTime.SubSeconds = UINT32_MAX - timeout; + 8000d52: 687b ldr r3, [r7, #4] + 8000d54: 43db mvns r3, r3 + 8000d56: 60fb str r3, [r7, #12] + sAlarm.AlarmMask = RTC_ALARMMASK_NONE; + 8000d58: 2300 movs r3, #0 + 8000d5a: 61fb str r3, [r7, #28] + sAlarm.AlarmSubSecondMask = RTC_ALARMSUBSECONDBINMASK_NONE; + 8000d5c: f04f 5300 mov.w r3, #536870912 @ 0x20000000 + 8000d60: 623b str r3, [r7, #32] + sAlarm.Alarm = RTC_ALARM_A; + 8000d62: f44f 7380 mov.w r3, #256 @ 0x100 + 8000d66: 633b str r3, [r7, #48] @ 0x30 + if (HAL_RTC_SetAlarm_IT(&hrtc, &sAlarm, RTC_FORMAT_BCD) != HAL_OK) + 8000d68: f107 0308 add.w r3, r7, #8 + 8000d6c: 2201 movs r2, #1 + 8000d6e: 4619 mov r1, r3 + 8000d70: 4807 ldr r0, [pc, #28] @ (8000d90 ) + 8000d72: f003 f973 bl 800405c + 8000d76: 4603 mov r3, r0 + 8000d78: 2b00 cmp r3, #0 + 8000d7a: d001 beq.n 8000d80 + { + Error_Handler(); + 8000d7c: f7ff fcc4 bl 8000708 + } + /* USER CODE BEGIN TIMER_IF_StartTimer_Last */ + + /* USER CODE END TIMER_IF_StartTimer_Last */ + return ret; + 8000d80: f897 3037 ldrb.w r3, [r7, #55] @ 0x37 +} + 8000d84: 4618 mov r0, r3 + 8000d86: 3738 adds r7, #56 @ 0x38 + 8000d88: 46bd mov sp, r7 + 8000d8a: bd80 pop {r7, pc} + 8000d8c: 20000088 .word 0x20000088 + 8000d90: 20000040 .word 0x20000040 + +08000d94 : + +UTIL_TIMER_Status_t TIMER_IF_StopTimer(void) +{ + 8000d94: b580 push {r7, lr} + 8000d96: b082 sub sp, #8 + 8000d98: af00 add r7, sp, #0 + UTIL_TIMER_Status_t ret = UTIL_TIMER_OK; + 8000d9a: 2300 movs r3, #0 + 8000d9c: 71fb strb r3, [r7, #7] + /* USER CODE BEGIN TIMER_IF_StopTimer */ + + /* USER CODE END TIMER_IF_StopTimer */ + /* Clear RTC Alarm Flag */ + __HAL_RTC_ALARM_CLEAR_FLAG(&hrtc, RTC_FLAG_ALRAF); + 8000d9e: 4b08 ldr r3, [pc, #32] @ (8000dc0 ) + 8000da0: 2201 movs r2, #1 + 8000da2: 65da str r2, [r3, #92] @ 0x5c + /* Disable the Alarm A interrupt */ + HAL_RTC_DeactivateAlarm(&hrtc, RTC_ALARM_A); + 8000da4: f44f 7180 mov.w r1, #256 @ 0x100 + 8000da8: 4806 ldr r0, [pc, #24] @ (8000dc4 ) + 8000daa: f003 fa63 bl 8004274 + /*overload RTC feature enable*/ + hrtc.IsEnabled.RtcFeatures = UINT32_MAX; + 8000dae: 4b05 ldr r3, [pc, #20] @ (8000dc4 ) + 8000db0: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff + 8000db4: 631a str r2, [r3, #48] @ 0x30 + /* USER CODE BEGIN TIMER_IF_StopTimer_Last */ + + /* USER CODE END TIMER_IF_StopTimer_Last */ + return ret; + 8000db6: 79fb ldrb r3, [r7, #7] +} + 8000db8: 4618 mov r0, r3 + 8000dba: 3708 adds r7, #8 + 8000dbc: 46bd mov sp, r7 + 8000dbe: bd80 pop {r7, pc} + 8000dc0: 40002800 .word 0x40002800 + 8000dc4: 20000040 .word 0x20000040 + +08000dc8 : + +uint32_t TIMER_IF_SetTimerContext(void) +{ + 8000dc8: b580 push {r7, lr} + 8000dca: af00 add r7, sp, #0 + /*store time context*/ + RtcTimerContext = GetTimerTicks(); + 8000dcc: f000 f98e bl 80010ec + 8000dd0: 4603 mov r3, r0 + 8000dd2: 4a03 ldr r2, [pc, #12] @ (8000de0 ) + 8000dd4: 6013 str r3, [r2, #0] + + /* USER CODE END TIMER_IF_SetTimerContext */ + + TIMER_IF_DBG_PRINTF("TIMER_IF_SetTimerContext=%d\n\r", RtcTimerContext); + /*return time context*/ + return RtcTimerContext; + 8000dd6: 4b02 ldr r3, [pc, #8] @ (8000de0 ) + 8000dd8: 681b ldr r3, [r3, #0] +} + 8000dda: 4618 mov r0, r3 + 8000ddc: bd80 pop {r7, pc} + 8000dde: bf00 nop + 8000de0: 20000088 .word 0x20000088 + +08000de4 : + +uint32_t TIMER_IF_GetTimerContext(void) +{ + 8000de4: b480 push {r7} + 8000de6: af00 add r7, sp, #0 + + /* USER CODE END TIMER_IF_GetTimerContext */ + + TIMER_IF_DBG_PRINTF("TIMER_IF_GetTimerContext=%d\n\r", RtcTimerContext); + /*return time context*/ + return RtcTimerContext; + 8000de8: 4b02 ldr r3, [pc, #8] @ (8000df4 ) + 8000dea: 681b ldr r3, [r3, #0] +} + 8000dec: 4618 mov r0, r3 + 8000dee: 46bd mov sp, r7 + 8000df0: bc80 pop {r7} + 8000df2: 4770 bx lr + 8000df4: 20000088 .word 0x20000088 + +08000df8 : + +uint32_t TIMER_IF_GetTimerElapsedTime(void) +{ + 8000df8: b580 push {r7, lr} + 8000dfa: b082 sub sp, #8 + 8000dfc: af00 add r7, sp, #0 + uint32_t ret = 0; + 8000dfe: 2300 movs r3, #0 + 8000e00: 607b str r3, [r7, #4] + /* USER CODE BEGIN TIMER_IF_GetTimerElapsedTime */ + + /* USER CODE END TIMER_IF_GetTimerElapsedTime */ + ret = ((uint32_t)(GetTimerTicks() - RtcTimerContext)); + 8000e02: f000 f973 bl 80010ec + 8000e06: 4602 mov r2, r0 + 8000e08: 4b04 ldr r3, [pc, #16] @ (8000e1c ) + 8000e0a: 681b ldr r3, [r3, #0] + 8000e0c: 1ad3 subs r3, r2, r3 + 8000e0e: 607b str r3, [r7, #4] + /* USER CODE BEGIN TIMER_IF_GetTimerElapsedTime_Last */ + + /* USER CODE END TIMER_IF_GetTimerElapsedTime_Last */ + return ret; + 8000e10: 687b ldr r3, [r7, #4] +} + 8000e12: 4618 mov r0, r3 + 8000e14: 3708 adds r7, #8 + 8000e16: 46bd mov sp, r7 + 8000e18: bd80 pop {r7, pc} + 8000e1a: bf00 nop + 8000e1c: 20000088 .word 0x20000088 + +08000e20 : + +uint32_t TIMER_IF_GetTimerValue(void) +{ + 8000e20: b580 push {r7, lr} + 8000e22: b082 sub sp, #8 + 8000e24: af00 add r7, sp, #0 + uint32_t ret = 0; + 8000e26: 2300 movs r3, #0 + 8000e28: 607b str r3, [r7, #4] + /* USER CODE BEGIN TIMER_IF_GetTimerValue */ + + /* USER CODE END TIMER_IF_GetTimerValue */ + if (RTC_Initialized == true) + 8000e2a: 4b06 ldr r3, [pc, #24] @ (8000e44 ) + 8000e2c: 781b ldrb r3, [r3, #0] + 8000e2e: 2b00 cmp r3, #0 + 8000e30: d002 beq.n 8000e38 + { + ret = GetTimerTicks(); + 8000e32: f000 f95b bl 80010ec + 8000e36: 6078 str r0, [r7, #4] + } + /* USER CODE BEGIN TIMER_IF_GetTimerValue_Last */ + + /* USER CODE END TIMER_IF_GetTimerValue_Last */ + return ret; + 8000e38: 687b ldr r3, [r7, #4] +} + 8000e3a: 4618 mov r0, r3 + 8000e3c: 3708 adds r7, #8 + 8000e3e: 46bd mov sp, r7 + 8000e40: bd80 pop {r7, pc} + 8000e42: bf00 nop + 8000e44: 20000085 .word 0x20000085 + +08000e48 : + +uint32_t TIMER_IF_GetMinimumTimeout(void) +{ + 8000e48: b480 push {r7} + 8000e4a: b083 sub sp, #12 + 8000e4c: af00 add r7, sp, #0 + uint32_t ret = 0; + 8000e4e: 2300 movs r3, #0 + 8000e50: 607b str r3, [r7, #4] + /* USER CODE BEGIN TIMER_IF_GetMinimumTimeout */ + + /* USER CODE END TIMER_IF_GetMinimumTimeout */ + ret = (MIN_ALARM_DELAY); + 8000e52: 2303 movs r3, #3 + 8000e54: 607b str r3, [r7, #4] + /* USER CODE BEGIN TIMER_IF_GetMinimumTimeout_Last */ + + /* USER CODE END TIMER_IF_GetMinimumTimeout_Last */ + return ret; + 8000e56: 687b ldr r3, [r7, #4] +} + 8000e58: 4618 mov r0, r3 + 8000e5a: 370c adds r7, #12 + 8000e5c: 46bd mov sp, r7 + 8000e5e: bc80 pop {r7} + 8000e60: 4770 bx lr + +08000e62 : + +uint32_t TIMER_IF_Convert_ms2Tick(uint32_t timeMilliSec) +{ + 8000e62: b5b0 push {r4, r5, r7, lr} + 8000e64: b084 sub sp, #16 + 8000e66: af00 add r7, sp, #0 + 8000e68: 6078 str r0, [r7, #4] + uint32_t ret = 0; + 8000e6a: 2100 movs r1, #0 + 8000e6c: 60f9 str r1, [r7, #12] + /* USER CODE BEGIN TIMER_IF_Convert_ms2Tick */ + + /* USER CODE END TIMER_IF_Convert_ms2Tick */ + ret = ((uint32_t)((((uint64_t) timeMilliSec) << RTC_N_PREDIV_S) / 1000)); + 8000e6e: 6879 ldr r1, [r7, #4] + 8000e70: 2000 movs r0, #0 + 8000e72: 460a mov r2, r1 + 8000e74: 4603 mov r3, r0 + 8000e76: 0d95 lsrs r5, r2, #22 + 8000e78: 0294 lsls r4, r2, #10 + 8000e7a: f44f 727a mov.w r2, #1000 @ 0x3e8 + 8000e7e: f04f 0300 mov.w r3, #0 + 8000e82: 4620 mov r0, r4 + 8000e84: 4629 mov r1, r5 + 8000e86: f7ff f97f bl 8000188 <__aeabi_uldivmod> + 8000e8a: 4602 mov r2, r0 + 8000e8c: 460b mov r3, r1 + 8000e8e: 4613 mov r3, r2 + 8000e90: 60fb str r3, [r7, #12] + /* USER CODE BEGIN TIMER_IF_Convert_ms2Tick_Last */ + + /* USER CODE END TIMER_IF_Convert_ms2Tick_Last */ + return ret; + 8000e92: 68fb ldr r3, [r7, #12] +} + 8000e94: 4618 mov r0, r3 + 8000e96: 3710 adds r7, #16 + 8000e98: 46bd mov sp, r7 + 8000e9a: bdb0 pop {r4, r5, r7, pc} + +08000e9c : + +uint32_t TIMER_IF_Convert_Tick2ms(uint32_t tick) +{ + 8000e9c: e92d 0fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp} + 8000ea0: b085 sub sp, #20 + 8000ea2: af00 add r7, sp, #0 + 8000ea4: 6078 str r0, [r7, #4] + uint32_t ret = 0; + 8000ea6: 2100 movs r1, #0 + 8000ea8: 60f9 str r1, [r7, #12] + /* USER CODE BEGIN TIMER_IF_Convert_Tick2ms */ + + /* USER CODE END TIMER_IF_Convert_Tick2ms */ + ret = ((uint32_t)((((uint64_t)(tick)) * 1000) >> RTC_N_PREDIV_S)); + 8000eaa: 6879 ldr r1, [r7, #4] + 8000eac: 2000 movs r0, #0 + 8000eae: 460c mov r4, r1 + 8000eb0: 4605 mov r5, r0 + 8000eb2: 4620 mov r0, r4 + 8000eb4: 4629 mov r1, r5 + 8000eb6: f04f 0a00 mov.w sl, #0 + 8000eba: f04f 0b00 mov.w fp, #0 + 8000ebe: ea4f 1b41 mov.w fp, r1, lsl #5 + 8000ec2: ea4b 6bd0 orr.w fp, fp, r0, lsr #27 + 8000ec6: ea4f 1a40 mov.w sl, r0, lsl #5 + 8000eca: 4650 mov r0, sl + 8000ecc: 4659 mov r1, fp + 8000ece: 1b02 subs r2, r0, r4 + 8000ed0: eb61 0305 sbc.w r3, r1, r5 + 8000ed4: f04f 0000 mov.w r0, #0 + 8000ed8: f04f 0100 mov.w r1, #0 + 8000edc: 0099 lsls r1, r3, #2 + 8000ede: ea41 7192 orr.w r1, r1, r2, lsr #30 + 8000ee2: 0090 lsls r0, r2, #2 + 8000ee4: 4602 mov r2, r0 + 8000ee6: 460b mov r3, r1 + 8000ee8: eb12 0804 adds.w r8, r2, r4 + 8000eec: eb43 0905 adc.w r9, r3, r5 + 8000ef0: f04f 0200 mov.w r2, #0 + 8000ef4: f04f 0300 mov.w r3, #0 + 8000ef8: ea4f 03c9 mov.w r3, r9, lsl #3 + 8000efc: ea43 7358 orr.w r3, r3, r8, lsr #29 + 8000f00: ea4f 02c8 mov.w r2, r8, lsl #3 + 8000f04: 4690 mov r8, r2 + 8000f06: 4699 mov r9, r3 + 8000f08: 4640 mov r0, r8 + 8000f0a: 4649 mov r1, r9 + 8000f0c: f04f 0200 mov.w r2, #0 + 8000f10: f04f 0300 mov.w r3, #0 + 8000f14: 0a82 lsrs r2, r0, #10 + 8000f16: ea42 5281 orr.w r2, r2, r1, lsl #22 + 8000f1a: 0a8b lsrs r3, r1, #10 + 8000f1c: 4613 mov r3, r2 + 8000f1e: 60fb str r3, [r7, #12] + /* USER CODE BEGIN TIMER_IF_Convert_Tick2ms_Last */ + + /* USER CODE END TIMER_IF_Convert_Tick2ms_Last */ + return ret; + 8000f20: 68fb ldr r3, [r7, #12] +} + 8000f22: 4618 mov r0, r3 + 8000f24: 3714 adds r7, #20 + 8000f26: 46bd mov sp, r7 + 8000f28: e8bd 0fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp} + 8000f2c: 4770 bx lr + +08000f2e : + +void TIMER_IF_DelayMs(uint32_t delay) +{ + 8000f2e: b580 push {r7, lr} + 8000f30: b084 sub sp, #16 + 8000f32: af00 add r7, sp, #0 + 8000f34: 6078 str r0, [r7, #4] + /* USER CODE BEGIN TIMER_IF_DelayMs */ + + /* USER CODE END TIMER_IF_DelayMs */ + uint32_t delayTicks = TIMER_IF_Convert_ms2Tick(delay); + 8000f36: 6878 ldr r0, [r7, #4] + 8000f38: f7ff ff93 bl 8000e62 + 8000f3c: 60f8 str r0, [r7, #12] + uint32_t timeout = GetTimerTicks(); + 8000f3e: f000 f8d5 bl 80010ec + 8000f42: 60b8 str r0, [r7, #8] + + /* Wait delay ms */ + while (((GetTimerTicks() - timeout)) < delayTicks) + 8000f44: e000 b.n 8000f48 + { + __NOP(); + 8000f46: bf00 nop + while (((GetTimerTicks() - timeout)) < delayTicks) + 8000f48: f000 f8d0 bl 80010ec + 8000f4c: 4602 mov r2, r0 + 8000f4e: 68bb ldr r3, [r7, #8] + 8000f50: 1ad3 subs r3, r2, r3 + 8000f52: 68fa ldr r2, [r7, #12] + 8000f54: 429a cmp r2, r3 + 8000f56: d8f6 bhi.n 8000f46 + } + /* USER CODE BEGIN TIMER_IF_DelayMs_Last */ + + /* USER CODE END TIMER_IF_DelayMs_Last */ +} + 8000f58: bf00 nop + 8000f5a: bf00 nop + 8000f5c: 3710 adds r7, #16 + 8000f5e: 46bd mov sp, r7 + 8000f60: bd80 pop {r7, pc} + +08000f62 : + +void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc) +{ + 8000f62: b580 push {r7, lr} + 8000f64: b082 sub sp, #8 + 8000f66: af00 add r7, sp, #0 + 8000f68: 6078 str r0, [r7, #4] + /* USER CODE BEGIN HAL_RTC_AlarmAEventCallback */ + + /* USER CODE END HAL_RTC_AlarmAEventCallback */ + UTIL_TIMER_IRQ_MAP_PROCESS(); + 8000f6a: f00b fead bl 800ccc8 + /* USER CODE BEGIN HAL_RTC_AlarmAEventCallback_Last */ + + /* USER CODE END HAL_RTC_AlarmAEventCallback_Last */ +} + 8000f6e: bf00 nop + 8000f70: 3708 adds r7, #8 + 8000f72: 46bd mov sp, r7 + 8000f74: bd80 pop {r7, pc} + +08000f76 : + +void HAL_RTCEx_SSRUEventCallback(RTC_HandleTypeDef *hrtc) +{ + 8000f76: b580 push {r7, lr} + 8000f78: b084 sub sp, #16 + 8000f7a: af00 add r7, sp, #0 + 8000f7c: 6078 str r0, [r7, #4] + + /* USER CODE END HAL_RTCEx_SSRUEventCallback */ + /*called every 48 days with 1024 ticks per seconds*/ + TIMER_IF_DBG_PRINTF(">>Handler SSRUnderflow at %d\n\r", GetTimerTicks()); + /*Increment MSBticks*/ + uint32_t MSB_ticks = TIMER_IF_BkUp_Read_MSBticks(); + 8000f7e: f000 f8a5 bl 80010cc + 8000f82: 60f8 str r0, [r7, #12] + TIMER_IF_BkUp_Write_MSBticks(MSB_ticks + 1); + 8000f84: 68fb ldr r3, [r7, #12] + 8000f86: 3301 adds r3, #1 + 8000f88: 4618 mov r0, r3 + 8000f8a: f000 f88f bl 80010ac + /* USER CODE BEGIN HAL_RTCEx_SSRUEventCallback_Last */ + + /* USER CODE END HAL_RTCEx_SSRUEventCallback_Last */ +} + 8000f8e: bf00 nop + 8000f90: 3710 adds r7, #16 + 8000f92: 46bd mov sp, r7 + 8000f94: bd80 pop {r7, pc} + +08000f96 : + +uint32_t TIMER_IF_GetTime(uint16_t *mSeconds) +{ + 8000f96: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr} + 8000f9a: b08c sub sp, #48 @ 0x30 + 8000f9c: af00 add r7, sp, #0 + 8000f9e: 6178 str r0, [r7, #20] + uint32_t seconds = 0; + 8000fa0: 2300 movs r3, #0 + 8000fa2: 62fb str r3, [r7, #44] @ 0x2c + /* USER CODE BEGIN TIMER_IF_GetTime */ + + /* USER CODE END TIMER_IF_GetTime */ + uint64_t ticks; + uint32_t timerValueLsb = GetTimerTicks(); + 8000fa4: f000 f8a2 bl 80010ec + 8000fa8: 62b8 str r0, [r7, #40] @ 0x28 + uint32_t timerValueMSB = TIMER_IF_BkUp_Read_MSBticks(); + 8000faa: f000 f88f bl 80010cc + 8000fae: 6278 str r0, [r7, #36] @ 0x24 + + ticks = (((uint64_t) timerValueMSB) << 32) + timerValueLsb; + 8000fb0: 6a7b ldr r3, [r7, #36] @ 0x24 + 8000fb2: 2200 movs r2, #0 + 8000fb4: 60bb str r3, [r7, #8] + 8000fb6: 60fa str r2, [r7, #12] + 8000fb8: f04f 0200 mov.w r2, #0 + 8000fbc: f04f 0300 mov.w r3, #0 + 8000fc0: 68b9 ldr r1, [r7, #8] + 8000fc2: 000b movs r3, r1 + 8000fc4: 2200 movs r2, #0 + 8000fc6: 6ab9 ldr r1, [r7, #40] @ 0x28 + 8000fc8: 2000 movs r0, #0 + 8000fca: 460c mov r4, r1 + 8000fcc: 4605 mov r5, r0 + 8000fce: eb12 0804 adds.w r8, r2, r4 + 8000fd2: eb43 0905 adc.w r9, r3, r5 + 8000fd6: e9c7 8906 strd r8, r9, [r7, #24] + + seconds = (uint32_t)(ticks >> RTC_N_PREDIV_S); + 8000fda: e9d7 0106 ldrd r0, r1, [r7, #24] + 8000fde: f04f 0200 mov.w r2, #0 + 8000fe2: f04f 0300 mov.w r3, #0 + 8000fe6: 0a82 lsrs r2, r0, #10 + 8000fe8: ea42 5281 orr.w r2, r2, r1, lsl #22 + 8000fec: 0a8b lsrs r3, r1, #10 + 8000fee: 4613 mov r3, r2 + 8000ff0: 62fb str r3, [r7, #44] @ 0x2c + + ticks = (uint32_t) ticks & RTC_PREDIV_S; + 8000ff2: 69bb ldr r3, [r7, #24] + 8000ff4: 2200 movs r2, #0 + 8000ff6: 603b str r3, [r7, #0] + 8000ff8: 607a str r2, [r7, #4] + 8000ffa: 683b ldr r3, [r7, #0] + 8000ffc: f3c3 0a09 ubfx sl, r3, #0, #10 + 8001000: f04f 0b00 mov.w fp, #0 + 8001004: e9c7 ab06 strd sl, fp, [r7, #24] + + *mSeconds = TIMER_IF_Convert_Tick2ms(ticks); + 8001008: 69bb ldr r3, [r7, #24] + 800100a: 4618 mov r0, r3 + 800100c: f7ff ff46 bl 8000e9c + 8001010: 4603 mov r3, r0 + 8001012: b29a uxth r2, r3 + 8001014: 697b ldr r3, [r7, #20] + 8001016: 801a strh r2, [r3, #0] + + /* USER CODE BEGIN TIMER_IF_GetTime_Last */ + + /* USER CODE END TIMER_IF_GetTime_Last */ + return seconds; + 8001018: 6afb ldr r3, [r7, #44] @ 0x2c +} + 800101a: 4618 mov r0, r3 + 800101c: 3730 adds r7, #48 @ 0x30 + 800101e: 46bd mov sp, r7 + 8001020: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc} + +08001024 : + +void TIMER_IF_BkUp_Write_Seconds(uint32_t Seconds) +{ + 8001024: b580 push {r7, lr} + 8001026: b082 sub sp, #8 + 8001028: af00 add r7, sp, #0 + 800102a: 6078 str r0, [r7, #4] + /* USER CODE BEGIN TIMER_IF_BkUp_Write_Seconds */ + + /* USER CODE END TIMER_IF_BkUp_Write_Seconds */ + HAL_RTCEx_BKUPWrite(&hrtc, RTC_BKP_SECONDS, Seconds); + 800102c: 687a ldr r2, [r7, #4] + 800102e: 2100 movs r1, #0 + 8001030: 4803 ldr r0, [pc, #12] @ (8001040 ) + 8001032: f003 faef bl 8004614 + /* USER CODE BEGIN TIMER_IF_BkUp_Write_Seconds_Last */ + + /* USER CODE END TIMER_IF_BkUp_Write_Seconds_Last */ +} + 8001036: bf00 nop + 8001038: 3708 adds r7, #8 + 800103a: 46bd mov sp, r7 + 800103c: bd80 pop {r7, pc} + 800103e: bf00 nop + 8001040: 20000040 .word 0x20000040 + +08001044 : + +void TIMER_IF_BkUp_Write_SubSeconds(uint32_t SubSeconds) +{ + 8001044: b580 push {r7, lr} + 8001046: b082 sub sp, #8 + 8001048: af00 add r7, sp, #0 + 800104a: 6078 str r0, [r7, #4] + /* USER CODE BEGIN TIMER_IF_BkUp_Write_SubSeconds */ + + /* USER CODE END TIMER_IF_BkUp_Write_SubSeconds */ + HAL_RTCEx_BKUPWrite(&hrtc, RTC_BKP_SUBSECONDS, SubSeconds); + 800104c: 687a ldr r2, [r7, #4] + 800104e: 2101 movs r1, #1 + 8001050: 4803 ldr r0, [pc, #12] @ (8001060 ) + 8001052: f003 fadf bl 8004614 + /* USER CODE BEGIN TIMER_IF_BkUp_Write_SubSeconds_Last */ + + /* USER CODE END TIMER_IF_BkUp_Write_SubSeconds_Last */ +} + 8001056: bf00 nop + 8001058: 3708 adds r7, #8 + 800105a: 46bd mov sp, r7 + 800105c: bd80 pop {r7, pc} + 800105e: bf00 nop + 8001060: 20000040 .word 0x20000040 + +08001064 : + +uint32_t TIMER_IF_BkUp_Read_Seconds(void) +{ + 8001064: b580 push {r7, lr} + 8001066: b082 sub sp, #8 + 8001068: af00 add r7, sp, #0 + uint32_t ret = 0; + 800106a: 2300 movs r3, #0 + 800106c: 607b str r3, [r7, #4] + /* USER CODE BEGIN TIMER_IF_BkUp_Read_Seconds */ + + /* USER CODE END TIMER_IF_BkUp_Read_Seconds */ + ret = HAL_RTCEx_BKUPRead(&hrtc, RTC_BKP_SECONDS); + 800106e: 2100 movs r1, #0 + 8001070: 4804 ldr r0, [pc, #16] @ (8001084 ) + 8001072: f003 fae7 bl 8004644 + 8001076: 6078 str r0, [r7, #4] + /* USER CODE BEGIN TIMER_IF_BkUp_Read_Seconds_Last */ + + /* USER CODE END TIMER_IF_BkUp_Read_Seconds_Last */ + return ret; + 8001078: 687b ldr r3, [r7, #4] +} + 800107a: 4618 mov r0, r3 + 800107c: 3708 adds r7, #8 + 800107e: 46bd mov sp, r7 + 8001080: bd80 pop {r7, pc} + 8001082: bf00 nop + 8001084: 20000040 .word 0x20000040 + +08001088 : + +uint32_t TIMER_IF_BkUp_Read_SubSeconds(void) +{ + 8001088: b580 push {r7, lr} + 800108a: b082 sub sp, #8 + 800108c: af00 add r7, sp, #0 + uint32_t ret = 0; + 800108e: 2300 movs r3, #0 + 8001090: 607b str r3, [r7, #4] + /* USER CODE BEGIN TIMER_IF_BkUp_Read_SubSeconds */ + + /* USER CODE END TIMER_IF_BkUp_Read_SubSeconds */ + ret = HAL_RTCEx_BKUPRead(&hrtc, RTC_BKP_SUBSECONDS); + 8001092: 2101 movs r1, #1 + 8001094: 4804 ldr r0, [pc, #16] @ (80010a8 ) + 8001096: f003 fad5 bl 8004644 + 800109a: 6078 str r0, [r7, #4] + /* USER CODE BEGIN TIMER_IF_BkUp_Read_SubSeconds_Last */ + + /* USER CODE END TIMER_IF_BkUp_Read_SubSeconds_Last */ + return ret; + 800109c: 687b ldr r3, [r7, #4] +} + 800109e: 4618 mov r0, r3 + 80010a0: 3708 adds r7, #8 + 80010a2: 46bd mov sp, r7 + 80010a4: bd80 pop {r7, pc} + 80010a6: bf00 nop + 80010a8: 20000040 .word 0x20000040 + +080010ac : + +/* USER CODE END EF */ + +/* Private functions ---------------------------------------------------------*/ +static void TIMER_IF_BkUp_Write_MSBticks(uint32_t MSBticks) +{ + 80010ac: b580 push {r7, lr} + 80010ae: b082 sub sp, #8 + 80010b0: af00 add r7, sp, #0 + 80010b2: 6078 str r0, [r7, #4] + /* USER CODE BEGIN TIMER_IF_BkUp_Write_MSBticks */ + + /* USER CODE END TIMER_IF_BkUp_Write_MSBticks */ + HAL_RTCEx_BKUPWrite(&hrtc, RTC_BKP_MSBTICKS, MSBticks); + 80010b4: 687a ldr r2, [r7, #4] + 80010b6: 2102 movs r1, #2 + 80010b8: 4803 ldr r0, [pc, #12] @ (80010c8 ) + 80010ba: f003 faab bl 8004614 + /* USER CODE BEGIN TIMER_IF_BkUp_Write_MSBticks_Last */ + + /* USER CODE END TIMER_IF_BkUp_Write_MSBticks_Last */ +} + 80010be: bf00 nop + 80010c0: 3708 adds r7, #8 + 80010c2: 46bd mov sp, r7 + 80010c4: bd80 pop {r7, pc} + 80010c6: bf00 nop + 80010c8: 20000040 .word 0x20000040 + +080010cc : + +static uint32_t TIMER_IF_BkUp_Read_MSBticks(void) +{ + 80010cc: b580 push {r7, lr} + 80010ce: b082 sub sp, #8 + 80010d0: af00 add r7, sp, #0 + /* USER CODE BEGIN TIMER_IF_BkUp_Read_MSBticks */ + + /* USER CODE END TIMER_IF_BkUp_Read_MSBticks */ + uint32_t MSBticks; + MSBticks = HAL_RTCEx_BKUPRead(&hrtc, RTC_BKP_MSBTICKS); + 80010d2: 2102 movs r1, #2 + 80010d4: 4804 ldr r0, [pc, #16] @ (80010e8 ) + 80010d6: f003 fab5 bl 8004644 + 80010da: 6078 str r0, [r7, #4] + return MSBticks; + 80010dc: 687b ldr r3, [r7, #4] + /* USER CODE BEGIN TIMER_IF_BkUp_Read_MSBticks_Last */ + + /* USER CODE END TIMER_IF_BkUp_Read_MSBticks_Last */ +} + 80010de: 4618 mov r0, r3 + 80010e0: 3708 adds r7, #8 + 80010e2: 46bd mov sp, r7 + 80010e4: bd80 pop {r7, pc} + 80010e6: bf00 nop + 80010e8: 20000040 .word 0x20000040 + +080010ec : + +static inline uint32_t GetTimerTicks(void) +{ + 80010ec: b580 push {r7, lr} + 80010ee: b082 sub sp, #8 + 80010f0: af00 add r7, sp, #0 + /* USER CODE BEGIN GetTimerTicks */ + + /* USER CODE END GetTimerTicks */ + uint32_t ssr = LL_RTC_TIME_GetSubSecond(RTC); + 80010f2: 480b ldr r0, [pc, #44] @ (8001120 ) + 80010f4: f7ff fdd8 bl 8000ca8 + 80010f8: 6078 str r0, [r7, #4] + /* read twice to make sure value it valid*/ + while (ssr != LL_RTC_TIME_GetSubSecond(RTC)) + 80010fa: e003 b.n 8001104 + { + ssr = LL_RTC_TIME_GetSubSecond(RTC); + 80010fc: 4808 ldr r0, [pc, #32] @ (8001120 ) + 80010fe: f7ff fdd3 bl 8000ca8 + 8001102: 6078 str r0, [r7, #4] + while (ssr != LL_RTC_TIME_GetSubSecond(RTC)) + 8001104: 4806 ldr r0, [pc, #24] @ (8001120 ) + 8001106: f7ff fdcf bl 8000ca8 + 800110a: 4602 mov r2, r0 + 800110c: 687b ldr r3, [r7, #4] + 800110e: 4293 cmp r3, r2 + 8001110: d1f4 bne.n 80010fc + } + return UINT32_MAX - ssr; + 8001112: 687b ldr r3, [r7, #4] + 8001114: 43db mvns r3, r3 + /* USER CODE BEGIN GetTimerTicks_Last */ + + /* USER CODE END GetTimerTicks_Last */ +} + 8001116: 4618 mov r0, r3 + 8001118: 3708 adds r7, #8 + 800111a: 46bd mov sp, r7 + 800111c: bd80 pop {r7, pc} + 800111e: bf00 nop + 8001120: 40002800 .word 0x40002800 + +08001124 : +{ + 8001124: b480 push {r7} + 8001126: b085 sub sp, #20 + 8001128: af00 add r7, sp, #0 + 800112a: 6078 str r0, [r7, #4] + SET_BIT(RCC->AHB2ENR, Periphs); + 800112c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8001130: 6cda ldr r2, [r3, #76] @ 0x4c + 8001132: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 8001136: 687b ldr r3, [r7, #4] + 8001138: 4313 orrs r3, r2 + 800113a: 64cb str r3, [r1, #76] @ 0x4c + tmpreg = READ_BIT(RCC->AHB2ENR, Periphs); + 800113c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8001140: 6cda ldr r2, [r3, #76] @ 0x4c + 8001142: 687b ldr r3, [r7, #4] + 8001144: 4013 ands r3, r2 + 8001146: 60fb str r3, [r7, #12] + (void)tmpreg; + 8001148: 68fb ldr r3, [r7, #12] +} + 800114a: bf00 nop + 800114c: 3714 adds r7, #20 + 800114e: 46bd mov sp, r7 + 8001150: bc80 pop {r7} + 8001152: 4770 bx lr + +08001154 : +{ + 8001154: b480 push {r7} + 8001156: b085 sub sp, #20 + 8001158: af00 add r7, sp, #0 + 800115a: 6078 str r0, [r7, #4] + SET_BIT(RCC->APB1ENR1, Periphs); + 800115c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8001160: 6d9a ldr r2, [r3, #88] @ 0x58 + 8001162: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 8001166: 687b ldr r3, [r7, #4] + 8001168: 4313 orrs r3, r2 + 800116a: 658b str r3, [r1, #88] @ 0x58 + tmpreg = READ_BIT(RCC->APB1ENR1, Periphs); + 800116c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8001170: 6d9a ldr r2, [r3, #88] @ 0x58 + 8001172: 687b ldr r3, [r7, #4] + 8001174: 4013 ands r3, r2 + 8001176: 60fb str r3, [r7, #12] + (void)tmpreg; + 8001178: 68fb ldr r3, [r7, #12] +} + 800117a: bf00 nop + 800117c: 3714 adds r7, #20 + 800117e: 46bd mov sp, r7 + 8001180: bc80 pop {r7} + 8001182: 4770 bx lr + +08001184 : +{ + 8001184: b480 push {r7} + 8001186: b083 sub sp, #12 + 8001188: af00 add r7, sp, #0 + 800118a: 6078 str r0, [r7, #4] + CLEAR_BIT(RCC->APB1ENR1, Periphs); + 800118c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8001190: 6d9a ldr r2, [r3, #88] @ 0x58 + 8001192: 687b ldr r3, [r7, #4] + 8001194: 43db mvns r3, r3 + 8001196: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 800119a: 4013 ands r3, r2 + 800119c: 658b str r3, [r1, #88] @ 0x58 +} + 800119e: bf00 nop + 80011a0: 370c adds r7, #12 + 80011a2: 46bd mov sp, r7 + 80011a4: bc80 pop {r7} + 80011a6: 4770 bx lr + +080011a8 : +DMA_HandleTypeDef hdma_usart2_tx; + +/* USART2 init function */ + +void MX_USART2_UART_Init(void) +{ + 80011a8: b580 push {r7, lr} + 80011aa: af00 add r7, sp, #0 + /* USER CODE END USART2_Init 0 */ + + /* USER CODE BEGIN USART2_Init 1 */ + + /* USER CODE END USART2_Init 1 */ + huart2.Instance = USART2; + 80011ac: 4b22 ldr r3, [pc, #136] @ (8001238 ) + 80011ae: 4a23 ldr r2, [pc, #140] @ (800123c ) + 80011b0: 601a str r2, [r3, #0] + huart2.Init.BaudRate = 115200; + 80011b2: 4b21 ldr r3, [pc, #132] @ (8001238 ) + 80011b4: f44f 32e1 mov.w r2, #115200 @ 0x1c200 + 80011b8: 605a str r2, [r3, #4] + huart2.Init.WordLength = UART_WORDLENGTH_8B; + 80011ba: 4b1f ldr r3, [pc, #124] @ (8001238 ) + 80011bc: 2200 movs r2, #0 + 80011be: 609a str r2, [r3, #8] + huart2.Init.StopBits = UART_STOPBITS_1; + 80011c0: 4b1d ldr r3, [pc, #116] @ (8001238 ) + 80011c2: 2200 movs r2, #0 + 80011c4: 60da str r2, [r3, #12] + huart2.Init.Parity = UART_PARITY_NONE; + 80011c6: 4b1c ldr r3, [pc, #112] @ (8001238 ) + 80011c8: 2200 movs r2, #0 + 80011ca: 611a str r2, [r3, #16] + huart2.Init.Mode = UART_MODE_TX_RX; + 80011cc: 4b1a ldr r3, [pc, #104] @ (8001238 ) + 80011ce: 220c movs r2, #12 + 80011d0: 615a str r2, [r3, #20] + huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE; + 80011d2: 4b19 ldr r3, [pc, #100] @ (8001238 ) + 80011d4: 2200 movs r2, #0 + 80011d6: 619a str r2, [r3, #24] + huart2.Init.OverSampling = UART_OVERSAMPLING_16; + 80011d8: 4b17 ldr r3, [pc, #92] @ (8001238 ) + 80011da: 2200 movs r2, #0 + 80011dc: 61da str r2, [r3, #28] + huart2.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; + 80011de: 4b16 ldr r3, [pc, #88] @ (8001238 ) + 80011e0: 2200 movs r2, #0 + 80011e2: 621a str r2, [r3, #32] + huart2.Init.ClockPrescaler = UART_PRESCALER_DIV1; + 80011e4: 4b14 ldr r3, [pc, #80] @ (8001238 ) + 80011e6: 2200 movs r2, #0 + 80011e8: 625a str r2, [r3, #36] @ 0x24 + huart2.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; + 80011ea: 4b13 ldr r3, [pc, #76] @ (8001238 ) + 80011ec: 2200 movs r2, #0 + 80011ee: 629a str r2, [r3, #40] @ 0x28 + if (HAL_UART_Init(&huart2) != HAL_OK) + 80011f0: 4811 ldr r0, [pc, #68] @ (8001238 ) + 80011f2: f003 ff2a bl 800504a + 80011f6: 4603 mov r3, r0 + 80011f8: 2b00 cmp r3, #0 + 80011fa: d001 beq.n 8001200 + { + Error_Handler(); + 80011fc: f7ff fa84 bl 8000708 + } + if (HAL_UARTEx_SetTxFifoThreshold(&huart2, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK) + 8001200: 2100 movs r1, #0 + 8001202: 480d ldr r0, [pc, #52] @ (8001238 ) + 8001204: f006 f85b bl 80072be + 8001208: 4603 mov r3, r0 + 800120a: 2b00 cmp r3, #0 + 800120c: d001 beq.n 8001212 + { + Error_Handler(); + 800120e: f7ff fa7b bl 8000708 + } + if (HAL_UARTEx_SetRxFifoThreshold(&huart2, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK) + 8001212: 2100 movs r1, #0 + 8001214: 4808 ldr r0, [pc, #32] @ (8001238 ) + 8001216: f006 f890 bl 800733a + 800121a: 4603 mov r3, r0 + 800121c: 2b00 cmp r3, #0 + 800121e: d001 beq.n 8001224 + { + Error_Handler(); + 8001220: f7ff fa72 bl 8000708 + } + if (HAL_UARTEx_EnableFifoMode(&huart2) != HAL_OK) + 8001224: 4804 ldr r0, [pc, #16] @ (8001238 ) + 8001226: f006 f80f bl 8007248 + 800122a: 4603 mov r3, r0 + 800122c: 2b00 cmp r3, #0 + 800122e: d001 beq.n 8001234 + { + Error_Handler(); + 8001230: f7ff fa6a bl 8000708 + } + /* USER CODE BEGIN USART2_Init 2 */ + + /* USER CODE END USART2_Init 2 */ + +} + 8001234: bf00 nop + 8001236: bd80 pop {r7, pc} + 8001238: 2000008c .word 0x2000008c + 800123c: 40004400 .word 0x40004400 + +08001240 : + +void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle) +{ + 8001240: b580 push {r7, lr} + 8001242: b096 sub sp, #88 @ 0x58 + 8001244: af00 add r7, sp, #0 + 8001246: 6078 str r0, [r7, #4] + + GPIO_InitTypeDef GPIO_InitStruct = {0}; + 8001248: f107 0344 add.w r3, r7, #68 @ 0x44 + 800124c: 2200 movs r2, #0 + 800124e: 601a str r2, [r3, #0] + 8001250: 605a str r2, [r3, #4] + 8001252: 609a str r2, [r3, #8] + 8001254: 60da str r2, [r3, #12] + 8001256: 611a str r2, [r3, #16] + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; + 8001258: f107 030c add.w r3, r7, #12 + 800125c: 2238 movs r2, #56 @ 0x38 + 800125e: 2100 movs r1, #0 + 8001260: 4618 mov r0, r3 + 8001262: f00c f907 bl 800d474 + if(uartHandle->Instance==USART2) + 8001266: 687b ldr r3, [r7, #4] + 8001268: 681b ldr r3, [r3, #0] + 800126a: 4a33 ldr r2, [pc, #204] @ (8001338 ) + 800126c: 4293 cmp r3, r2 + 800126e: d15f bne.n 8001330 + + /* USER CODE END USART2_MspInit 0 */ + + /** Initializes the peripherals clocks + */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USART2; + 8001270: 2302 movs r3, #2 + 8001272: 60fb str r3, [r7, #12] + PeriphClkInitStruct.Usart2ClockSelection = RCC_USART2CLKSOURCE_SYSCLK; + 8001274: 4b31 ldr r3, [pc, #196] @ (800133c ) + 8001276: 617b str r3, [r7, #20] + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) + 8001278: f107 030c add.w r3, r7, #12 + 800127c: 4618 mov r0, r3 + 800127e: f002 fd47 bl 8003d10 + 8001282: 4603 mov r3, r0 + 8001284: 2b00 cmp r3, #0 + 8001286: d001 beq.n 800128c + { + Error_Handler(); + 8001288: f7ff fa3e bl 8000708 + } + + /* USART2 clock enable */ + __HAL_RCC_USART2_CLK_ENABLE(); + 800128c: f44f 3000 mov.w r0, #131072 @ 0x20000 + 8001290: f7ff ff60 bl 8001154 + + __HAL_RCC_GPIOA_CLK_ENABLE(); + 8001294: 2001 movs r0, #1 + 8001296: f7ff ff45 bl 8001124 + /**USART2 GPIO Configuration + PA3 ------> USART2_RX + PA2 ------> USART2_TX + */ + GPIO_InitStruct.Pin = USARTx_RX_Pin|USARTx_TX_Pin; + 800129a: 230c movs r3, #12 + 800129c: 647b str r3, [r7, #68] @ 0x44 + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 800129e: 2302 movs r3, #2 + 80012a0: 64bb str r3, [r7, #72] @ 0x48 + GPIO_InitStruct.Pull = GPIO_NOPULL; + 80012a2: 2300 movs r3, #0 + 80012a4: 64fb str r3, [r7, #76] @ 0x4c + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + 80012a6: 2303 movs r3, #3 + 80012a8: 653b str r3, [r7, #80] @ 0x50 + GPIO_InitStruct.Alternate = GPIO_AF7_USART2; + 80012aa: 2307 movs r3, #7 + 80012ac: 657b str r3, [r7, #84] @ 0x54 + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 80012ae: f107 0344 add.w r3, r7, #68 @ 0x44 + 80012b2: 4619 mov r1, r3 + 80012b4: f04f 4090 mov.w r0, #1207959552 @ 0x48000000 + 80012b8: f001 f816 bl 80022e8 + + /* USART2 DMA Init */ + /* USART2_TX Init */ + hdma_usart2_tx.Instance = DMA1_Channel5; + 80012bc: 4b20 ldr r3, [pc, #128] @ (8001340 ) + 80012be: 4a21 ldr r2, [pc, #132] @ (8001344 ) + 80012c0: 601a str r2, [r3, #0] + hdma_usart2_tx.Init.Request = DMA_REQUEST_USART2_TX; + 80012c2: 4b1f ldr r3, [pc, #124] @ (8001340 ) + 80012c4: 2214 movs r2, #20 + 80012c6: 605a str r2, [r3, #4] + hdma_usart2_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; + 80012c8: 4b1d ldr r3, [pc, #116] @ (8001340 ) + 80012ca: 2210 movs r2, #16 + 80012cc: 609a str r2, [r3, #8] + hdma_usart2_tx.Init.PeriphInc = DMA_PINC_DISABLE; + 80012ce: 4b1c ldr r3, [pc, #112] @ (8001340 ) + 80012d0: 2200 movs r2, #0 + 80012d2: 60da str r2, [r3, #12] + hdma_usart2_tx.Init.MemInc = DMA_MINC_ENABLE; + 80012d4: 4b1a ldr r3, [pc, #104] @ (8001340 ) + 80012d6: 2280 movs r2, #128 @ 0x80 + 80012d8: 611a str r2, [r3, #16] + hdma_usart2_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; + 80012da: 4b19 ldr r3, [pc, #100] @ (8001340 ) + 80012dc: 2200 movs r2, #0 + 80012de: 615a str r2, [r3, #20] + hdma_usart2_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; + 80012e0: 4b17 ldr r3, [pc, #92] @ (8001340 ) + 80012e2: 2200 movs r2, #0 + 80012e4: 619a str r2, [r3, #24] + hdma_usart2_tx.Init.Mode = DMA_NORMAL; + 80012e6: 4b16 ldr r3, [pc, #88] @ (8001340 ) + 80012e8: 2200 movs r2, #0 + 80012ea: 61da str r2, [r3, #28] + hdma_usart2_tx.Init.Priority = DMA_PRIORITY_LOW; + 80012ec: 4b14 ldr r3, [pc, #80] @ (8001340 ) + 80012ee: 2200 movs r2, #0 + 80012f0: 621a str r2, [r3, #32] + if (HAL_DMA_Init(&hdma_usart2_tx) != HAL_OK) + 80012f2: 4813 ldr r0, [pc, #76] @ (8001340 ) + 80012f4: f000 fbe0 bl 8001ab8 + 80012f8: 4603 mov r3, r0 + 80012fa: 2b00 cmp r3, #0 + 80012fc: d001 beq.n 8001302 + { + Error_Handler(); + 80012fe: f7ff fa03 bl 8000708 + } + + if (HAL_DMA_ConfigChannelAttributes(&hdma_usart2_tx, DMA_CHANNEL_NPRIV) != HAL_OK) + 8001302: 2110 movs r1, #16 + 8001304: 480e ldr r0, [pc, #56] @ (8001340 ) + 8001306: f000 ff17 bl 8002138 + 800130a: 4603 mov r3, r0 + 800130c: 2b00 cmp r3, #0 + 800130e: d001 beq.n 8001314 + { + Error_Handler(); + 8001310: f7ff f9fa bl 8000708 + } + + __HAL_LINKDMA(uartHandle,hdmatx,hdma_usart2_tx); + 8001314: 687b ldr r3, [r7, #4] + 8001316: 4a0a ldr r2, [pc, #40] @ (8001340 ) + 8001318: 67da str r2, [r3, #124] @ 0x7c + 800131a: 4a09 ldr r2, [pc, #36] @ (8001340 ) + 800131c: 687b ldr r3, [r7, #4] + 800131e: 6293 str r3, [r2, #40] @ 0x28 + + /* USART2 interrupt Init */ + HAL_NVIC_SetPriority(USART2_IRQn, 2, 0); + 8001320: 2200 movs r2, #0 + 8001322: 2102 movs r1, #2 + 8001324: 2025 movs r0, #37 @ 0x25 + 8001326: f000 fb90 bl 8001a4a + HAL_NVIC_EnableIRQ(USART2_IRQn); + 800132a: 2025 movs r0, #37 @ 0x25 + 800132c: f000 fba7 bl 8001a7e + /* USER CODE BEGIN USART2_MspInit 1 */ + + /* USER CODE END USART2_MspInit 1 */ + } +} + 8001330: bf00 nop + 8001332: 3758 adds r7, #88 @ 0x58 + 8001334: 46bd mov sp, r7 + 8001336: bd80 pop {r7, pc} + 8001338: 40004400 .word 0x40004400 + 800133c: 000c0004 .word 0x000c0004 + 8001340: 20000120 .word 0x20000120 + 8001344: 40020058 .word 0x40020058 + +08001348 : + +void HAL_UART_MspDeInit(UART_HandleTypeDef* uartHandle) +{ + 8001348: b580 push {r7, lr} + 800134a: b082 sub sp, #8 + 800134c: af00 add r7, sp, #0 + 800134e: 6078 str r0, [r7, #4] + + if(uartHandle->Instance==USART2) + 8001350: 687b ldr r3, [r7, #4] + 8001352: 681b ldr r3, [r3, #0] + 8001354: 4a0b ldr r2, [pc, #44] @ (8001384 ) + 8001356: 4293 cmp r3, r2 + 8001358: d110 bne.n 800137c + { + /* USER CODE BEGIN USART2_MspDeInit 0 */ + + /* USER CODE END USART2_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_USART2_CLK_DISABLE(); + 800135a: f44f 3000 mov.w r0, #131072 @ 0x20000 + 800135e: f7ff ff11 bl 8001184 + + /**USART2 GPIO Configuration + PA3 ------> USART2_RX + PA2 ------> USART2_TX + */ + HAL_GPIO_DeInit(GPIOA, USARTx_RX_Pin|USARTx_TX_Pin); + 8001362: 210c movs r1, #12 + 8001364: f04f 4090 mov.w r0, #1207959552 @ 0x48000000 + 8001368: f001 f91e bl 80025a8 + + /* USART2 DMA DeInit */ + HAL_DMA_DeInit(uartHandle->hdmatx); + 800136c: 687b ldr r3, [r7, #4] + 800136e: 6fdb ldr r3, [r3, #124] @ 0x7c + 8001370: 4618 mov r0, r3 + 8001372: f000 fc49 bl 8001c08 + + /* USART2 interrupt Deinit */ + HAL_NVIC_DisableIRQ(USART2_IRQn); + 8001376: 2025 movs r0, #37 @ 0x25 + 8001378: f000 fb8f bl 8001a9a + /* USER CODE BEGIN USART2_MspDeInit 1 */ + + /* USER CODE END USART2_MspDeInit 1 */ + } +} + 800137c: bf00 nop + 800137e: 3708 adds r7, #8 + 8001380: 46bd mov sp, r7 + 8001382: bd80 pop {r7, pc} + 8001384: 40004400 .word 0x40004400 + +08001388 : +{ + 8001388: b480 push {r7} + 800138a: b083 sub sp, #12 + 800138c: af00 add r7, sp, #0 + 800138e: 6078 str r0, [r7, #4] + SET_BIT(RCC->APB1RSTR1, Periphs); + 8001390: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8001394: 6b9a ldr r2, [r3, #56] @ 0x38 + 8001396: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 800139a: 687b ldr r3, [r7, #4] + 800139c: 4313 orrs r3, r2 + 800139e: 638b str r3, [r1, #56] @ 0x38 +} + 80013a0: bf00 nop + 80013a2: 370c adds r7, #12 + 80013a4: 46bd mov sp, r7 + 80013a6: bc80 pop {r7} + 80013a8: 4770 bx lr + +080013aa : +{ + 80013aa: b480 push {r7} + 80013ac: b083 sub sp, #12 + 80013ae: af00 add r7, sp, #0 + 80013b0: 6078 str r0, [r7, #4] + CLEAR_BIT(RCC->APB1RSTR1, Periphs); + 80013b2: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 80013b6: 6b9a ldr r2, [r3, #56] @ 0x38 + 80013b8: 687b ldr r3, [r7, #4] + 80013ba: 43db mvns r3, r3 + 80013bc: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 80013c0: 4013 ands r3, r2 + 80013c2: 638b str r3, [r1, #56] @ 0x38 +} + 80013c4: bf00 nop + 80013c6: 370c adds r7, #12 + 80013c8: 46bd mov sp, r7 + 80013ca: bc80 pop {r7} + 80013cc: 4770 bx lr + ... + +080013d0 : +{ + 80013d0: b480 push {r7} + 80013d2: b083 sub sp, #12 + 80013d4: af00 add r7, sp, #0 + 80013d6: 6078 str r0, [r7, #4] + SET_BIT(EXTI->IMR1, ExtiLine); + 80013d8: 4b06 ldr r3, [pc, #24] @ (80013f4 ) + 80013da: f8d3 2080 ldr.w r2, [r3, #128] @ 0x80 + 80013de: 4905 ldr r1, [pc, #20] @ (80013f4 ) + 80013e0: 687b ldr r3, [r7, #4] + 80013e2: 4313 orrs r3, r2 + 80013e4: f8c1 3080 str.w r3, [r1, #128] @ 0x80 +} + 80013e8: bf00 nop + 80013ea: 370c adds r7, #12 + 80013ec: 46bd mov sp, r7 + 80013ee: bc80 pop {r7} + 80013f0: 4770 bx lr + 80013f2: bf00 nop + 80013f4: 58000800 .word 0x58000800 + +080013f8 : +/* USER CODE END PFP */ + +/* Exported functions --------------------------------------------------------*/ + +UTIL_ADV_TRACE_Status_t vcom_Init(void (*cb)(void *)) +{ + 80013f8: b580 push {r7, lr} + 80013fa: b082 sub sp, #8 + 80013fc: af00 add r7, sp, #0 + 80013fe: 6078 str r0, [r7, #4] + /* USER CODE BEGIN vcom_Init_1 */ + + /* USER CODE END vcom_Init_1 */ + TxCpltCallback = cb; + 8001400: 4a07 ldr r2, [pc, #28] @ (8001420 ) + 8001402: 687b ldr r3, [r7, #4] + 8001404: 6013 str r3, [r2, #0] + MX_DMA_Init(); + 8001406: f7ff f86d bl 80004e4 + MX_USART2_UART_Init(); + 800140a: f7ff fecd bl 80011a8 + LL_EXTI_EnableIT_0_31(LL_EXTI_LINE_27); + 800140e: f04f 6000 mov.w r0, #134217728 @ 0x8000000 + 8001412: f7ff ffdd bl 80013d0 + return UTIL_ADV_TRACE_OK; + 8001416: 2300 movs r3, #0 + /* USER CODE BEGIN vcom_Init_2 */ + + /* USER CODE END vcom_Init_2 */ +} + 8001418: 4618 mov r0, r3 + 800141a: 3708 adds r7, #8 + 800141c: 46bd mov sp, r7 + 800141e: bd80 pop {r7, pc} + 8001420: 20000184 .word 0x20000184 + +08001424 : + +UTIL_ADV_TRACE_Status_t vcom_DeInit(void) +{ + 8001424: b580 push {r7, lr} + 8001426: af00 add r7, sp, #0 + /* USER CODE BEGIN vcom_DeInit_1 */ + + /* USER CODE END vcom_DeInit_1 */ + /* ##-1- Reset peripherals ################################################## */ + __HAL_RCC_USART2_FORCE_RESET(); + 8001428: f44f 3000 mov.w r0, #131072 @ 0x20000 + 800142c: f7ff ffac bl 8001388 + __HAL_RCC_USART2_RELEASE_RESET(); + 8001430: f44f 3000 mov.w r0, #131072 @ 0x20000 + 8001434: f7ff ffb9 bl 80013aa + + /* ##-2- MspDeInit ################################################## */ + HAL_UART_MspDeInit(&huart2); + 8001438: 4804 ldr r0, [pc, #16] @ (800144c ) + 800143a: f7ff ff85 bl 8001348 + + /* ##-3- Disable the NVIC for DMA ########################################### */ + /* USER CODE BEGIN 1 */ + HAL_NVIC_DisableIRQ(DMA1_Channel5_IRQn); + 800143e: 200f movs r0, #15 + 8001440: f000 fb2b bl 8001a9a + + return UTIL_ADV_TRACE_OK; + 8001444: 2300 movs r3, #0 + /* USER CODE END 1 */ + /* USER CODE BEGIN vcom_DeInit_2 */ + + /* USER CODE END vcom_DeInit_2 */ +} + 8001446: 4618 mov r0, r3 + 8001448: bd80 pop {r7, pc} + 800144a: bf00 nop + 800144c: 2000008c .word 0x2000008c + +08001450 : + + /* USER CODE END vcom_Trace_2 */ +} + +UTIL_ADV_TRACE_Status_t vcom_Trace_DMA(uint8_t *p_data, uint16_t size) +{ + 8001450: b580 push {r7, lr} + 8001452: b082 sub sp, #8 + 8001454: af00 add r7, sp, #0 + 8001456: 6078 str r0, [r7, #4] + 8001458: 460b mov r3, r1 + 800145a: 807b strh r3, [r7, #2] + /* USER CODE BEGIN vcom_Trace_DMA_1 */ + + /* USER CODE END vcom_Trace_DMA_1 */ + HAL_UART_Transmit_DMA(&huart2, p_data, size); + 800145c: 887b ldrh r3, [r7, #2] + 800145e: 461a mov r2, r3 + 8001460: 6879 ldr r1, [r7, #4] + 8001462: 4804 ldr r0, [pc, #16] @ (8001474 ) + 8001464: f003 fe8e bl 8005184 + return UTIL_ADV_TRACE_OK; + 8001468: 2300 movs r3, #0 + /* USER CODE BEGIN vcom_Trace_DMA_2 */ + + /* USER CODE END vcom_Trace_DMA_2 */ +} + 800146a: 4618 mov r0, r3 + 800146c: 3708 adds r7, #8 + 800146e: 46bd mov sp, r7 + 8001470: bd80 pop {r7, pc} + 8001472: bf00 nop + 8001474: 2000008c .word 0x2000008c + +08001478 : + +UTIL_ADV_TRACE_Status_t vcom_ReceiveInit(void (*RxCb)(uint8_t *rxChar, uint16_t size, uint8_t error)) +{ + 8001478: b580 push {r7, lr} + 800147a: b084 sub sp, #16 + 800147c: af00 add r7, sp, #0 + 800147e: 6078 str r0, [r7, #4] + + /* USER CODE END vcom_ReceiveInit_1 */ + UART_WakeUpTypeDef WakeUpSelection; + + /*record call back*/ + RxCpltCallback = RxCb; + 8001480: 4a19 ldr r2, [pc, #100] @ (80014e8 ) + 8001482: 687b ldr r3, [r7, #4] + 8001484: 6013 str r3, [r2, #0] + + /*Set wakeUp event on start bit*/ + WakeUpSelection.WakeUpEvent = UART_WAKEUP_ON_STARTBIT; + 8001486: f44f 1300 mov.w r3, #2097152 @ 0x200000 + 800148a: 60bb str r3, [r7, #8] + + HAL_UARTEx_StopModeWakeUpSourceConfig(&huart2, WakeUpSelection); + 800148c: f107 0308 add.w r3, r7, #8 + 8001490: e893 0006 ldmia.w r3, {r1, r2} + 8001494: 4815 ldr r0, [pc, #84] @ (80014ec ) + 8001496: f005 fe4a bl 800712e + + /* Make sure that no UART transfer is on-going */ + while (__HAL_UART_GET_FLAG(&huart2, USART_ISR_BUSY) == SET); + 800149a: bf00 nop + 800149c: 4b13 ldr r3, [pc, #76] @ (80014ec ) + 800149e: 681b ldr r3, [r3, #0] + 80014a0: 69db ldr r3, [r3, #28] + 80014a2: f403 3380 and.w r3, r3, #65536 @ 0x10000 + 80014a6: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 + 80014aa: d0f7 beq.n 800149c + + /* Make sure that UART is ready to receive) */ + while (__HAL_UART_GET_FLAG(&huart2, USART_ISR_REACK) == RESET); + 80014ac: bf00 nop + 80014ae: 4b0f ldr r3, [pc, #60] @ (80014ec ) + 80014b0: 681b ldr r3, [r3, #0] + 80014b2: 69db ldr r3, [r3, #28] + 80014b4: f403 0380 and.w r3, r3, #4194304 @ 0x400000 + 80014b8: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 + 80014bc: d1f7 bne.n 80014ae + + /* Enable USART interrupt */ + __HAL_UART_ENABLE_IT(&huart2, UART_IT_WUF); + 80014be: 4b0b ldr r3, [pc, #44] @ (80014ec ) + 80014c0: 681b ldr r3, [r3, #0] + 80014c2: 689a ldr r2, [r3, #8] + 80014c4: 4b09 ldr r3, [pc, #36] @ (80014ec ) + 80014c6: 681b ldr r3, [r3, #0] + 80014c8: f442 0280 orr.w r2, r2, #4194304 @ 0x400000 + 80014cc: 609a str r2, [r3, #8] + + /*Enable wakeup from stop mode*/ + HAL_UARTEx_EnableStopMode(&huart2); + 80014ce: 4807 ldr r0, [pc, #28] @ (80014ec ) + 80014d0: f005 fe88 bl 80071e4 + + /*Start LPUART receive on IT*/ + HAL_UART_Receive_IT(&huart2, &charRx, 1); + 80014d4: 2201 movs r2, #1 + 80014d6: 4906 ldr r1, [pc, #24] @ (80014f0 ) + 80014d8: 4804 ldr r0, [pc, #16] @ (80014ec ) + 80014da: f003 fe07 bl 80050ec + + return UTIL_ADV_TRACE_OK; + 80014de: 2300 movs r3, #0 + /* USER CODE BEGIN vcom_ReceiveInit_2 */ + + /* USER CODE END vcom_ReceiveInit_2 */ +} + 80014e0: 4618 mov r0, r3 + 80014e2: 3710 adds r7, #16 + 80014e4: 46bd mov sp, r7 + 80014e6: bd80 pop {r7, pc} + 80014e8: 20000188 .word 0x20000188 + 80014ec: 2000008c .word 0x2000008c + 80014f0: 20000180 .word 0x20000180 + +080014f4 : + +void vcom_Resume(void) +{ + 80014f4: b580 push {r7, lr} + 80014f6: af00 add r7, sp, #0 + /* USER CODE BEGIN vcom_Resume_1 */ + + /* USER CODE END vcom_Resume_1 */ + /*to re-enable lost UART settings*/ + if (HAL_UART_Init(&huart2) != HAL_OK) + 80014f8: 4808 ldr r0, [pc, #32] @ (800151c ) + 80014fa: f003 fda6 bl 800504a + 80014fe: 4603 mov r3, r0 + 8001500: 2b00 cmp r3, #0 + 8001502: d001 beq.n 8001508 + { + Error_Handler(); + 8001504: f7ff f900 bl 8000708 + } + + /*to re-enable lost DMA settings*/ + if (HAL_DMA_Init(&hdma_usart2_tx) != HAL_OK) + 8001508: 4805 ldr r0, [pc, #20] @ (8001520 ) + 800150a: f000 fad5 bl 8001ab8 + 800150e: 4603 mov r3, r0 + 8001510: 2b00 cmp r3, #0 + 8001512: d001 beq.n 8001518 + { + Error_Handler(); + 8001514: f7ff f8f8 bl 8000708 + } + /* USER CODE BEGIN vcom_Resume_2 */ + + /* USER CODE END vcom_Resume_2 */ +} + 8001518: bf00 nop + 800151a: bd80 pop {r7, pc} + 800151c: 2000008c .word 0x2000008c + 8001520: 20000120 .word 0x20000120 + +08001524 : + +void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) +{ + 8001524: b580 push {r7, lr} + 8001526: b082 sub sp, #8 + 8001528: af00 add r7, sp, #0 + 800152a: 6078 str r0, [r7, #4] + /* USER CODE BEGIN HAL_UART_TxCpltCallback_1 */ + + /* USER CODE END HAL_UART_TxCpltCallback_1 */ + /* buffer transmission complete*/ + if (huart->Instance == USART2) + 800152c: 687b ldr r3, [r7, #4] + 800152e: 681b ldr r3, [r3, #0] + 8001530: 4a05 ldr r2, [pc, #20] @ (8001548 ) + 8001532: 4293 cmp r3, r2 + 8001534: d103 bne.n 800153e + { + TxCpltCallback(NULL); + 8001536: 4b05 ldr r3, [pc, #20] @ (800154c ) + 8001538: 681b ldr r3, [r3, #0] + 800153a: 2000 movs r0, #0 + 800153c: 4798 blx r3 + } + /* USER CODE BEGIN HAL_UART_TxCpltCallback_2 */ + + /* USER CODE END HAL_UART_TxCpltCallback_2 */ +} + 800153e: bf00 nop + 8001540: 3708 adds r7, #8 + 8001542: 46bd mov sp, r7 + 8001544: bd80 pop {r7, pc} + 8001546: bf00 nop + 8001548: 40004400 .word 0x40004400 + 800154c: 20000184 .word 0x20000184 + +08001550 : + +void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) +{ + 8001550: b580 push {r7, lr} + 8001552: b082 sub sp, #8 + 8001554: af00 add r7, sp, #0 + 8001556: 6078 str r0, [r7, #4] + /* USER CODE BEGIN HAL_UART_RxCpltCallback_1 */ + + /* USER CODE END HAL_UART_RxCpltCallback_1 */ + if (huart->Instance == USART2) + 8001558: 687b ldr r3, [r7, #4] + 800155a: 681b ldr r3, [r3, #0] + 800155c: 4a0d ldr r2, [pc, #52] @ (8001594 ) + 800155e: 4293 cmp r3, r2 + 8001560: d113 bne.n 800158a + { + if ((NULL != RxCpltCallback) && (HAL_UART_ERROR_NONE == huart->ErrorCode)) + 8001562: 4b0d ldr r3, [pc, #52] @ (8001598 ) + 8001564: 681b ldr r3, [r3, #0] + 8001566: 2b00 cmp r3, #0 + 8001568: d00a beq.n 8001580 + 800156a: 687b ldr r3, [r7, #4] + 800156c: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 8001570: 2b00 cmp r3, #0 + 8001572: d105 bne.n 8001580 + { + RxCpltCallback(&charRx, 1, 0); + 8001574: 4b08 ldr r3, [pc, #32] @ (8001598 ) + 8001576: 681b ldr r3, [r3, #0] + 8001578: 2200 movs r2, #0 + 800157a: 2101 movs r1, #1 + 800157c: 4807 ldr r0, [pc, #28] @ (800159c ) + 800157e: 4798 blx r3 + } + HAL_UART_Receive_IT(huart, &charRx, 1); + 8001580: 2201 movs r2, #1 + 8001582: 4906 ldr r1, [pc, #24] @ (800159c ) + 8001584: 6878 ldr r0, [r7, #4] + 8001586: f003 fdb1 bl 80050ec + } + /* USER CODE BEGIN HAL_UART_RxCpltCallback_2 */ + + /* USER CODE END HAL_UART_RxCpltCallback_2 */ +} + 800158a: bf00 nop + 800158c: 3708 adds r7, #8 + 800158e: 46bd mov sp, r7 + 8001590: bd80 pop {r7, pc} + 8001592: bf00 nop + 8001594: 40004400 .word 0x40004400 + 8001598: 20000188 .word 0x20000188 + 800159c: 20000180 .word 0x20000180 + +080015a0 : + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr r0, =_estack + 80015a0: 480d ldr r0, [pc, #52] @ (80015d8 ) + mov sp, r0 /* set stack pointer */ + 80015a2: 4685 mov sp, r0 + +/* Call the clock system initialization function.*/ + bl SystemInit + 80015a4: f7ff fb7a bl 8000c9c + +/* Copy the data segment initializers from flash to SRAM */ + ldr r0, =_sdata + 80015a8: 480c ldr r0, [pc, #48] @ (80015dc ) + ldr r1, =_edata + 80015aa: 490d ldr r1, [pc, #52] @ (80015e0 ) + ldr r2, =_sidata + 80015ac: 4a0d ldr r2, [pc, #52] @ (80015e4 ) + movs r3, #0 + 80015ae: 2300 movs r3, #0 + b LoopCopyDataInit + 80015b0: e002 b.n 80015b8 + +080015b2 : + +CopyDataInit: + ldr r4, [r2, r3] + 80015b2: 58d4 ldr r4, [r2, r3] + str r4, [r0, r3] + 80015b4: 50c4 str r4, [r0, r3] + adds r3, r3, #4 + 80015b6: 3304 adds r3, #4 + +080015b8 : + +LoopCopyDataInit: + adds r4, r0, r3 + 80015b8: 18c4 adds r4, r0, r3 + cmp r4, r1 + 80015ba: 428c cmp r4, r1 + bcc CopyDataInit + 80015bc: d3f9 bcc.n 80015b2 + +/* Zero fill the bss segment. */ + ldr r2, =_sbss + 80015be: 4a0a ldr r2, [pc, #40] @ (80015e8 ) + ldr r4, =_ebss + 80015c0: 4c0a ldr r4, [pc, #40] @ (80015ec ) + movs r3, #0 + 80015c2: 2300 movs r3, #0 + b LoopFillZerobss + 80015c4: e001 b.n 80015ca + +080015c6 : + +FillZerobss: + str r3, [r2] + 80015c6: 6013 str r3, [r2, #0] + adds r2, r2, #4 + 80015c8: 3204 adds r2, #4 + +080015ca : + +LoopFillZerobss: + cmp r2, r4 + 80015ca: 42a2 cmp r2, r4 + bcc FillZerobss + 80015cc: d3fb bcc.n 80015c6 + +/* Call static constructors */ + bl __libc_init_array + 80015ce: f00b ff59 bl 800d484 <__libc_init_array> +/* Call the application's entry point.*/ + bl main + 80015d2: f7ff f834 bl 800063e
+ +080015d6 : + +LoopForever: + b LoopForever + 80015d6: e7fe b.n 80015d6 + ldr r0, =_estack + 80015d8: 20010000 .word 0x20010000 + ldr r0, =_sdata + 80015dc: 20000000 .word 0x20000000 + ldr r1, =_edata + 80015e0: 20000024 .word 0x20000024 + ldr r2, =_sidata + 80015e4: 0800db40 .word 0x0800db40 + ldr r2, =_sbss + 80015e8: 20000024 .word 0x20000024 + ldr r4, =_ebss + 80015ec: 20000ce8 .word 0x20000ce8 + +080015f0 : + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + 80015f0: e7fe b.n 80015f0 + +080015f2 : +{ + 80015f2: b480 push {r7} + 80015f4: b085 sub sp, #20 + 80015f6: af00 add r7, sp, #0 + 80015f8: 6078 str r0, [r7, #4] + SET_BIT(RCC->AHB2ENR, Periphs); + 80015fa: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 80015fe: 6cda ldr r2, [r3, #76] @ 0x4c + 8001600: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 8001604: 687b ldr r3, [r7, #4] + 8001606: 4313 orrs r3, r2 + 8001608: 64cb str r3, [r1, #76] @ 0x4c + tmpreg = READ_BIT(RCC->AHB2ENR, Periphs); + 800160a: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 800160e: 6cda ldr r2, [r3, #76] @ 0x4c + 8001610: 687b ldr r3, [r7, #4] + 8001612: 4013 ands r3, r2 + 8001614: 60fb str r3, [r7, #12] + (void)tmpreg; + 8001616: 68fb ldr r3, [r7, #12] +} + 8001618: bf00 nop + 800161a: 3714 adds r7, #20 + 800161c: 46bd mov sp, r7 + 800161e: bc80 pop {r7} + 8001620: 4770 bx lr + ... + +08001624 : +/** + * @brief Init Radio Switch + * @retval BSP status + */ +int32_t BSP_RADIO_Init(void) +{ + 8001624: b580 push {r7, lr} + 8001626: b086 sub sp, #24 + 8001628: af00 add r7, sp, #0 + GPIO_InitTypeDef gpio_init_structure = {0}; + 800162a: 1d3b adds r3, r7, #4 + 800162c: 2200 movs r2, #0 + 800162e: 601a str r2, [r3, #0] + 8001630: 605a str r2, [r3, #4] + 8001632: 609a str r2, [r3, #8] + 8001634: 60da str r2, [r3, #12] + 8001636: 611a str r2, [r3, #16] + + /* Enable the Radio Switch Clock */ + RF_SW_CTRL3_GPIO_CLK_ENABLE(); + 8001638: 2004 movs r0, #4 + 800163a: f7ff ffda bl 80015f2 + + /* Configure the Radio Switch pin */ + gpio_init_structure.Pin = RF_SW_CTRL1_PIN; + 800163e: 2310 movs r3, #16 + 8001640: 607b str r3, [r7, #4] + gpio_init_structure.Mode = GPIO_MODE_OUTPUT_PP; + 8001642: 2301 movs r3, #1 + 8001644: 60bb str r3, [r7, #8] + gpio_init_structure.Pull = GPIO_NOPULL; + 8001646: 2300 movs r3, #0 + 8001648: 60fb str r3, [r7, #12] + gpio_init_structure.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + 800164a: 2303 movs r3, #3 + 800164c: 613b str r3, [r7, #16] + + HAL_GPIO_Init(RF_SW_CTRL1_GPIO_PORT, &gpio_init_structure); + 800164e: 1d3b adds r3, r7, #4 + 8001650: 4619 mov r1, r3 + 8001652: 4812 ldr r0, [pc, #72] @ (800169c ) + 8001654: f000 fe48 bl 80022e8 + + gpio_init_structure.Pin = RF_SW_CTRL2_PIN; + 8001658: 2320 movs r3, #32 + 800165a: 607b str r3, [r7, #4] + HAL_GPIO_Init(RF_SW_CTRL2_GPIO_PORT, &gpio_init_structure); + 800165c: 1d3b adds r3, r7, #4 + 800165e: 4619 mov r1, r3 + 8001660: 480e ldr r0, [pc, #56] @ (800169c ) + 8001662: f000 fe41 bl 80022e8 + + gpio_init_structure.Pin = RF_SW_CTRL3_PIN; + 8001666: 2308 movs r3, #8 + 8001668: 607b str r3, [r7, #4] + HAL_GPIO_Init(RF_SW_CTRL3_GPIO_PORT, &gpio_init_structure); + 800166a: 1d3b adds r3, r7, #4 + 800166c: 4619 mov r1, r3 + 800166e: 480b ldr r0, [pc, #44] @ (800169c ) + 8001670: f000 fe3a bl 80022e8 + + HAL_GPIO_WritePin(RF_SW_CTRL2_GPIO_PORT, RF_SW_CTRL2_PIN, GPIO_PIN_RESET); + 8001674: 2200 movs r2, #0 + 8001676: 2120 movs r1, #32 + 8001678: 4808 ldr r0, [pc, #32] @ (800169c ) + 800167a: f001 f863 bl 8002744 + HAL_GPIO_WritePin(RF_SW_CTRL1_GPIO_PORT, RF_SW_CTRL1_PIN, GPIO_PIN_RESET); + 800167e: 2200 movs r2, #0 + 8001680: 2110 movs r1, #16 + 8001682: 4806 ldr r0, [pc, #24] @ (800169c ) + 8001684: f001 f85e bl 8002744 + HAL_GPIO_WritePin(RF_SW_CTRL3_GPIO_PORT, RF_SW_CTRL3_PIN, GPIO_PIN_RESET); + 8001688: 2200 movs r2, #0 + 800168a: 2108 movs r1, #8 + 800168c: 4803 ldr r0, [pc, #12] @ (800169c ) + 800168e: f001 f859 bl 8002744 + + return BSP_ERROR_NONE; + 8001692: 2300 movs r3, #0 +} + 8001694: 4618 mov r0, r3 + 8001696: 3718 adds r7, #24 + 8001698: 46bd mov sp, r7 + 800169a: bd80 pop {r7, pc} + 800169c: 48000800 .word 0x48000800 + +080016a0 : + * @arg RADIO_SWITCH_RFO_LP + * @arg RADIO_SWITCH_RFO_HP + * @retval BSP status + */ +int32_t BSP_RADIO_ConfigRFSwitch(BSP_RADIO_Switch_TypeDef Config) +{ + 80016a0: b580 push {r7, lr} + 80016a2: b082 sub sp, #8 + 80016a4: af00 add r7, sp, #0 + 80016a6: 4603 mov r3, r0 + 80016a8: 71fb strb r3, [r7, #7] + switch (Config) + 80016aa: 79fb ldrb r3, [r7, #7] + 80016ac: 2b03 cmp r3, #3 + 80016ae: d84b bhi.n 8001748 + 80016b0: a201 add r2, pc, #4 @ (adr r2, 80016b8 ) + 80016b2: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 80016b6: bf00 nop + 80016b8: 080016c9 .word 0x080016c9 + 80016bc: 080016e9 .word 0x080016e9 + 80016c0: 08001709 .word 0x08001709 + 80016c4: 08001729 .word 0x08001729 + { + case RADIO_SWITCH_OFF: + { + /* Turn off switch */ + HAL_GPIO_WritePin(RF_SW_CTRL3_GPIO_PORT, RF_SW_CTRL3_PIN, GPIO_PIN_RESET); + 80016c8: 2200 movs r2, #0 + 80016ca: 2108 movs r1, #8 + 80016cc: 4821 ldr r0, [pc, #132] @ (8001754 ) + 80016ce: f001 f839 bl 8002744 + HAL_GPIO_WritePin(RF_SW_CTRL1_GPIO_PORT, RF_SW_CTRL1_PIN, GPIO_PIN_RESET); + 80016d2: 2200 movs r2, #0 + 80016d4: 2110 movs r1, #16 + 80016d6: 481f ldr r0, [pc, #124] @ (8001754 ) + 80016d8: f001 f834 bl 8002744 + HAL_GPIO_WritePin(RF_SW_CTRL2_GPIO_PORT, RF_SW_CTRL2_PIN, GPIO_PIN_RESET); + 80016dc: 2200 movs r2, #0 + 80016de: 2120 movs r1, #32 + 80016e0: 481c ldr r0, [pc, #112] @ (8001754 ) + 80016e2: f001 f82f bl 8002744 + break; + 80016e6: e030 b.n 800174a + } + case RADIO_SWITCH_RX: + { + /*Turns On in Rx Mode the RF Switch */ + HAL_GPIO_WritePin(RF_SW_CTRL3_GPIO_PORT, RF_SW_CTRL3_PIN, GPIO_PIN_SET); + 80016e8: 2201 movs r2, #1 + 80016ea: 2108 movs r1, #8 + 80016ec: 4819 ldr r0, [pc, #100] @ (8001754 ) + 80016ee: f001 f829 bl 8002744 + HAL_GPIO_WritePin(RF_SW_CTRL1_GPIO_PORT, RF_SW_CTRL1_PIN, GPIO_PIN_SET); + 80016f2: 2201 movs r2, #1 + 80016f4: 2110 movs r1, #16 + 80016f6: 4817 ldr r0, [pc, #92] @ (8001754 ) + 80016f8: f001 f824 bl 8002744 + HAL_GPIO_WritePin(RF_SW_CTRL2_GPIO_PORT, RF_SW_CTRL2_PIN, GPIO_PIN_RESET); + 80016fc: 2200 movs r2, #0 + 80016fe: 2120 movs r1, #32 + 8001700: 4814 ldr r0, [pc, #80] @ (8001754 ) + 8001702: f001 f81f bl 8002744 + break; + 8001706: e020 b.n 800174a + } + case RADIO_SWITCH_RFO_LP: + { + /*Turns On in Tx Low Power the RF Switch */ + HAL_GPIO_WritePin(RF_SW_CTRL3_GPIO_PORT, RF_SW_CTRL3_PIN, GPIO_PIN_SET); + 8001708: 2201 movs r2, #1 + 800170a: 2108 movs r1, #8 + 800170c: 4811 ldr r0, [pc, #68] @ (8001754 ) + 800170e: f001 f819 bl 8002744 + HAL_GPIO_WritePin(RF_SW_CTRL1_GPIO_PORT, RF_SW_CTRL1_PIN, GPIO_PIN_SET); + 8001712: 2201 movs r2, #1 + 8001714: 2110 movs r1, #16 + 8001716: 480f ldr r0, [pc, #60] @ (8001754 ) + 8001718: f001 f814 bl 8002744 + HAL_GPIO_WritePin(RF_SW_CTRL2_GPIO_PORT, RF_SW_CTRL2_PIN, GPIO_PIN_SET); + 800171c: 2201 movs r2, #1 + 800171e: 2120 movs r1, #32 + 8001720: 480c ldr r0, [pc, #48] @ (8001754 ) + 8001722: f001 f80f bl 8002744 + break; + 8001726: e010 b.n 800174a + } + case RADIO_SWITCH_RFO_HP: + { + /*Turns On in Tx High Power the RF Switch */ + HAL_GPIO_WritePin(RF_SW_CTRL3_GPIO_PORT, RF_SW_CTRL3_PIN, GPIO_PIN_SET); + 8001728: 2201 movs r2, #1 + 800172a: 2108 movs r1, #8 + 800172c: 4809 ldr r0, [pc, #36] @ (8001754 ) + 800172e: f001 f809 bl 8002744 + HAL_GPIO_WritePin(RF_SW_CTRL1_GPIO_PORT, RF_SW_CTRL1_PIN, GPIO_PIN_RESET); + 8001732: 2200 movs r2, #0 + 8001734: 2110 movs r1, #16 + 8001736: 4807 ldr r0, [pc, #28] @ (8001754 ) + 8001738: f001 f804 bl 8002744 + HAL_GPIO_WritePin(RF_SW_CTRL2_GPIO_PORT, RF_SW_CTRL2_PIN, GPIO_PIN_SET); + 800173c: 2201 movs r2, #1 + 800173e: 2120 movs r1, #32 + 8001740: 4804 ldr r0, [pc, #16] @ (8001754 ) + 8001742: f000 ffff bl 8002744 + break; + 8001746: e000 b.n 800174a + } + default: + break; + 8001748: bf00 nop + } + + return BSP_ERROR_NONE; + 800174a: 2300 movs r3, #0 +} + 800174c: 4618 mov r0, r3 + 800174e: 3708 adds r7, #8 + 8001750: 46bd mov sp, r7 + 8001752: bd80 pop {r7, pc} + 8001754: 48000800 .word 0x48000800 + +08001758 : + * RADIO_CONF_RFO_LP_HP + * RADIO_CONF_RFO_LP + * RADIO_CONF_RFO_HP + */ +int32_t BSP_RADIO_GetTxConfig(void) +{ + 8001758: b480 push {r7} + 800175a: af00 add r7, sp, #0 + return RADIO_CONF_RFO_LP_HP; + 800175c: 2300 movs r3, #0 +} + 800175e: 4618 mov r0, r3 + 8001760: 46bd mov sp, r7 + 8001762: bc80 pop {r7} + 8001764: 4770 bx lr + +08001766 : + * @retval + * RADIO_CONF_TCXO_NOT_SUPPORTED + * RADIO_CONF_TCXO_SUPPORTED + */ +int32_t BSP_RADIO_IsTCXO(void) +{ + 8001766: b480 push {r7} + 8001768: af00 add r7, sp, #0 + return RADIO_CONF_TCXO_SUPPORTED; + 800176a: 2301 movs r3, #1 +} + 800176c: 4618 mov r0, r3 + 800176e: 46bd mov sp, r7 + 8001770: bc80 pop {r7} + 8001772: 4770 bx lr + +08001774 : + * @retval + * RADIO_CONF_DCDC_NOT_SUPPORTED + * RADIO_CONF_DCDC_SUPPORTED + */ +int32_t BSP_RADIO_IsDCDC(void) +{ + 8001774: b480 push {r7} + 8001776: af00 add r7, sp, #0 + return RADIO_CONF_DCDC_SUPPORTED; + 8001778: 2301 movs r3, #1 +} + 800177a: 4618 mov r0, r3 + 800177c: 46bd mov sp, r7 + 800177e: bc80 pop {r7} + 8001780: 4770 bx lr + +08001782 : + * @retval + * RADIO_CONF_RFO_LP_MAX_15_dBm for LP mode + * RADIO_CONF_RFO_HP_MAX_22_dBm for HP mode + */ +int32_t BSP_RADIO_GetRFOMaxPowerConfig(BSP_RADIO_RFOMaxPowerConfig_TypeDef Config) +{ + 8001782: b480 push {r7} + 8001784: b085 sub sp, #20 + 8001786: af00 add r7, sp, #0 + 8001788: 4603 mov r3, r0 + 800178a: 71fb strb r3, [r7, #7] + int32_t ret; + + if(Config == RADIO_RFO_LP_MAXPOWER) + 800178c: 79fb ldrb r3, [r7, #7] + 800178e: 2b00 cmp r3, #0 + 8001790: d102 bne.n 8001798 + { + ret = RADIO_CONF_RFO_LP_MAX_15_dBm; + 8001792: 230f movs r3, #15 + 8001794: 60fb str r3, [r7, #12] + 8001796: e001 b.n 800179c + } + else + { + ret = RADIO_CONF_RFO_HP_MAX_22_dBm; + 8001798: 2316 movs r3, #22 + 800179a: 60fb str r3, [r7, #12] + } + + return ret; + 800179c: 68fb ldr r3, [r7, #12] +} + 800179e: 4618 mov r0, r3 + 80017a0: 3714 adds r7, #20 + 80017a2: 46bd mov sp, r7 + 80017a4: bc80 pop {r7} + 80017a6: 4770 bx lr + +080017a8 : + * @brief Enable the CPU1 Debug Module during SLEEP mode + * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_EnableDBGSleepMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_EnableDBGSleepMode(void) +{ + 80017a8: b480 push {r7} + 80017aa: af00 add r7, sp, #0 + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); + 80017ac: 4b04 ldr r3, [pc, #16] @ (80017c0 ) + 80017ae: 685b ldr r3, [r3, #4] + 80017b0: 4a03 ldr r2, [pc, #12] @ (80017c0 ) + 80017b2: f043 0301 orr.w r3, r3, #1 + 80017b6: 6053 str r3, [r2, #4] +} + 80017b8: bf00 nop + 80017ba: 46bd mov sp, r7 + 80017bc: bc80 pop {r7} + 80017be: 4770 bx lr + 80017c0: e0042000 .word 0xe0042000 + +080017c4 : + * in Stop mode even when this bit is enabled + * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void) +{ + 80017c4: b480 push {r7} + 80017c6: af00 add r7, sp, #0 + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); + 80017c8: 4b04 ldr r3, [pc, #16] @ (80017dc ) + 80017ca: 685b ldr r3, [r3, #4] + 80017cc: 4a03 ldr r2, [pc, #12] @ (80017dc ) + 80017ce: f043 0302 orr.w r3, r3, #2 + 80017d2: 6053 str r3, [r2, #4] +} + 80017d4: bf00 nop + 80017d6: 46bd mov sp, r7 + 80017d8: bc80 pop {r7} + 80017da: 4770 bx lr + 80017dc: e0042000 .word 0xe0042000 + +080017e0 : + * in Standby mode even when this bit is enabled + * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void) +{ + 80017e0: b480 push {r7} + 80017e2: af00 add r7, sp, #0 + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); + 80017e4: 4b04 ldr r3, [pc, #16] @ (80017f8 ) + 80017e6: 685b ldr r3, [r3, #4] + 80017e8: 4a03 ldr r2, [pc, #12] @ (80017f8 ) + 80017ea: f043 0304 orr.w r3, r3, #4 + 80017ee: 6053 str r3, [r2, #4] +} + 80017f0: bf00 nop + 80017f2: 46bd mov sp, r7 + 80017f4: bc80 pop {r7} + 80017f6: 4770 bx lr + 80017f8: e0042000 .word 0xe0042000 + +080017fc : + * need to ensure that the SysTick time base is always set to 1 millisecond + * to have correct HAL operation. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_Init(void) +{ + 80017fc: b580 push {r7, lr} + 80017fe: b082 sub sp, #8 + 8001800: af00 add r7, sp, #0 + HAL_StatusTypeDef status = HAL_OK; + 8001802: 2300 movs r3, #0 + 8001804: 71fb strb r3, [r7, #7] +#endif /* PREFETCH_ENABLE */ + +#ifdef CORE_CM0PLUS +#else + /* Set Interrupt Group Priority */ + HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); + 8001806: 2003 movs r0, #3 + 8001808: f000 f914 bl 8001a34 + + /* Update the SystemCoreClock global variable */ +#if defined(DUAL_CORE) && defined(CORE_CM0PLUS) + SystemCoreClock = HAL_RCC_GetHCLK2Freq(); +#else + SystemCoreClock = HAL_RCC_GetHCLKFreq(); + 800180c: f002 f8a2 bl 8003954 + 8001810: 4603 mov r3, r0 + 8001812: 4a09 ldr r2, [pc, #36] @ (8001838 ) + 8001814: 6013 str r3, [r2, #0] +#endif + + /* Use SysTick as time base source and configure 1ms tick (default clock after Reset is MSI) */ + if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) + 8001816: 200f movs r0, #15 + 8001818: f7ff f9a8 bl 8000b6c + 800181c: 4603 mov r3, r0 + 800181e: 2b00 cmp r3, #0 + 8001820: d002 beq.n 8001828 + { + status = HAL_ERROR; + 8001822: 2301 movs r3, #1 + 8001824: 71fb strb r3, [r7, #7] + 8001826: e001 b.n 800182c + } + else + { + /* Init the low level hardware */ + HAL_MspInit(); + 8001828: f7ff f865 bl 80008f6 + } + + /* Return function status */ + return status; + 800182c: 79fb ldrb r3, [r7, #7] +} + 800182e: 4618 mov r0, r3 + 8001830: 3708 adds r7, #8 + 8001832: 46bd mov sp, r7 + 8001834: bd80 pop {r7, pc} + 8001836: bf00 nop + 8001838: 20000000 .word 0x20000000 + +0800183c : + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void HAL_SuspendTick(void) +{ + 800183c: b480 push {r7} + 800183e: af00 add r7, sp, #0 + /* Disable SysTick Interrupt */ + CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); + 8001840: 4b04 ldr r3, [pc, #16] @ (8001854 ) + 8001842: 681b ldr r3, [r3, #0] + 8001844: 4a03 ldr r2, [pc, #12] @ (8001854 ) + 8001846: f023 0302 bic.w r3, r3, #2 + 800184a: 6013 str r3, [r2, #0] +} + 800184c: bf00 nop + 800184e: 46bd mov sp, r7 + 8001850: bc80 pop {r7} + 8001852: 4770 bx lr + 8001854: e000e010 .word 0xe000e010 + +08001858 : + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void HAL_ResumeTick(void) +{ + 8001858: b480 push {r7} + 800185a: af00 add r7, sp, #0 + /* Enable SysTick Interrupt */ + SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); + 800185c: 4b04 ldr r3, [pc, #16] @ (8001870 ) + 800185e: 681b ldr r3, [r3, #0] + 8001860: 4a03 ldr r2, [pc, #12] @ (8001870 ) + 8001862: f043 0302 orr.w r3, r3, #2 + 8001866: 6013 str r3, [r2, #0] +} + 8001868: bf00 nop + 800186a: 46bd mov sp, r7 + 800186c: bc80 pop {r7} + 800186e: 4770 bx lr + 8001870: e000e010 .word 0xe000e010 + +08001874 : +/** + * @brief Enable the CPU1 Debug Module during SLEEP mode + * @retval None + */ +void HAL_DBGMCU_EnableDBGSleepMode(void) +{ + 8001874: b580 push {r7, lr} + 8001876: af00 add r7, sp, #0 + LL_DBGMCU_EnableDBGSleepMode(); + 8001878: f7ff ff96 bl 80017a8 +} + 800187c: bf00 nop + 800187e: bd80 pop {r7, pc} + +08001880 : + * @note This functionality does not influence CPU2 operation, CPU2 cannot be debugged + * in Stop mode even when this bit is enabled + * @retval None + */ +void HAL_DBGMCU_EnableDBGStopMode(void) +{ + 8001880: b580 push {r7, lr} + 8001882: af00 add r7, sp, #0 + LL_DBGMCU_EnableDBGStopMode(); + 8001884: f7ff ff9e bl 80017c4 +} + 8001888: bf00 nop + 800188a: bd80 pop {r7, pc} + +0800188c : + * @note This functionality does not influence CPU2 operation, CPU2 cannot be debugged + * in Standby mode even when this bit is enabled + * @retval None + */ +void HAL_DBGMCU_EnableDBGStandbyMode(void) +{ + 800188c: b580 push {r7, lr} + 800188e: af00 add r7, sp, #0 + LL_DBGMCU_EnableDBGStandbyMode(); + 8001890: f7ff ffa6 bl 80017e0 +} + 8001894: bf00 nop + 8001896: bd80 pop {r7, pc} + +08001898 <__NVIC_SetPriorityGrouping>: + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + 8001898: b480 push {r7} + 800189a: b085 sub sp, #20 + 800189c: af00 add r7, sp, #0 + 800189e: 6078 str r0, [r7, #4] + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + 80018a0: 687b ldr r3, [r7, #4] + 80018a2: f003 0307 and.w r3, r3, #7 + 80018a6: 60fb str r3, [r7, #12] + + reg_value = SCB->AIRCR; /* read old register configuration */ + 80018a8: 4b0c ldr r3, [pc, #48] @ (80018dc <__NVIC_SetPriorityGrouping+0x44>) + 80018aa: 68db ldr r3, [r3, #12] + 80018ac: 60bb str r3, [r7, #8] + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + 80018ae: 68ba ldr r2, [r7, #8] + 80018b0: f64f 03ff movw r3, #63743 @ 0xf8ff + 80018b4: 4013 ands r3, r2 + 80018b6: 60bb str r3, [r7, #8] + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + 80018b8: 68fb ldr r3, [r7, #12] + 80018ba: 021a lsls r2, r3, #8 + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + 80018bc: 68bb ldr r3, [r7, #8] + 80018be: 4313 orrs r3, r2 + reg_value = (reg_value | + 80018c0: f043 63bf orr.w r3, r3, #100139008 @ 0x5f80000 + 80018c4: f443 3300 orr.w r3, r3, #131072 @ 0x20000 + 80018c8: 60bb str r3, [r7, #8] + SCB->AIRCR = reg_value; + 80018ca: 4a04 ldr r2, [pc, #16] @ (80018dc <__NVIC_SetPriorityGrouping+0x44>) + 80018cc: 68bb ldr r3, [r7, #8] + 80018ce: 60d3 str r3, [r2, #12] +} + 80018d0: bf00 nop + 80018d2: 3714 adds r7, #20 + 80018d4: 46bd mov sp, r7 + 80018d6: bc80 pop {r7} + 80018d8: 4770 bx lr + 80018da: bf00 nop + 80018dc: e000ed00 .word 0xe000ed00 + +080018e0 <__NVIC_GetPriorityGrouping>: + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + 80018e0: b480 push {r7} + 80018e2: af00 add r7, sp, #0 + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); + 80018e4: 4b04 ldr r3, [pc, #16] @ (80018f8 <__NVIC_GetPriorityGrouping+0x18>) + 80018e6: 68db ldr r3, [r3, #12] + 80018e8: 0a1b lsrs r3, r3, #8 + 80018ea: f003 0307 and.w r3, r3, #7 +} + 80018ee: 4618 mov r0, r3 + 80018f0: 46bd mov sp, r7 + 80018f2: bc80 pop {r7} + 80018f4: 4770 bx lr + 80018f6: bf00 nop + 80018f8: e000ed00 .word 0xe000ed00 + +080018fc <__NVIC_EnableIRQ>: + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + 80018fc: b480 push {r7} + 80018fe: b083 sub sp, #12 + 8001900: af00 add r7, sp, #0 + 8001902: 4603 mov r3, r0 + 8001904: 71fb strb r3, [r7, #7] + if ((int32_t)(IRQn) >= 0) + 8001906: f997 3007 ldrsb.w r3, [r7, #7] + 800190a: 2b00 cmp r3, #0 + 800190c: db0b blt.n 8001926 <__NVIC_EnableIRQ+0x2a> + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + 800190e: 79fb ldrb r3, [r7, #7] + 8001910: f003 021f and.w r2, r3, #31 + 8001914: 4906 ldr r1, [pc, #24] @ (8001930 <__NVIC_EnableIRQ+0x34>) + 8001916: f997 3007 ldrsb.w r3, [r7, #7] + 800191a: 095b lsrs r3, r3, #5 + 800191c: 2001 movs r0, #1 + 800191e: fa00 f202 lsl.w r2, r0, r2 + 8001922: f841 2023 str.w r2, [r1, r3, lsl #2] + __COMPILER_BARRIER(); + } +} + 8001926: bf00 nop + 8001928: 370c adds r7, #12 + 800192a: 46bd mov sp, r7 + 800192c: bc80 pop {r7} + 800192e: 4770 bx lr + 8001930: e000e100 .word 0xe000e100 + +08001934 <__NVIC_DisableIRQ>: + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + 8001934: b480 push {r7} + 8001936: b083 sub sp, #12 + 8001938: af00 add r7, sp, #0 + 800193a: 4603 mov r3, r0 + 800193c: 71fb strb r3, [r7, #7] + if ((int32_t)(IRQn) >= 0) + 800193e: f997 3007 ldrsb.w r3, [r7, #7] + 8001942: 2b00 cmp r3, #0 + 8001944: db12 blt.n 800196c <__NVIC_DisableIRQ+0x38> + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + 8001946: 79fb ldrb r3, [r7, #7] + 8001948: f003 021f and.w r2, r3, #31 + 800194c: 490a ldr r1, [pc, #40] @ (8001978 <__NVIC_DisableIRQ+0x44>) + 800194e: f997 3007 ldrsb.w r3, [r7, #7] + 8001952: 095b lsrs r3, r3, #5 + 8001954: 2001 movs r0, #1 + 8001956: fa00 f202 lsl.w r2, r0, r2 + 800195a: 3320 adds r3, #32 + 800195c: f841 2023 str.w r2, [r1, r3, lsl #2] + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); + 8001960: f3bf 8f4f dsb sy +} + 8001964: bf00 nop + __ASM volatile ("isb 0xF":::"memory"); + 8001966: f3bf 8f6f isb sy +} + 800196a: bf00 nop + __DSB(); + __ISB(); + } +} + 800196c: bf00 nop + 800196e: 370c adds r7, #12 + 8001970: 46bd mov sp, r7 + 8001972: bc80 pop {r7} + 8001974: 4770 bx lr + 8001976: bf00 nop + 8001978: e000e100 .word 0xe000e100 + +0800197c <__NVIC_SetPriority>: + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + 800197c: b480 push {r7} + 800197e: b083 sub sp, #12 + 8001980: af00 add r7, sp, #0 + 8001982: 4603 mov r3, r0 + 8001984: 6039 str r1, [r7, #0] + 8001986: 71fb strb r3, [r7, #7] + if ((int32_t)(IRQn) >= 0) + 8001988: f997 3007 ldrsb.w r3, [r7, #7] + 800198c: 2b00 cmp r3, #0 + 800198e: db0a blt.n 80019a6 <__NVIC_SetPriority+0x2a> + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + 8001990: 683b ldr r3, [r7, #0] + 8001992: b2da uxtb r2, r3 + 8001994: 490c ldr r1, [pc, #48] @ (80019c8 <__NVIC_SetPriority+0x4c>) + 8001996: f997 3007 ldrsb.w r3, [r7, #7] + 800199a: 0112 lsls r2, r2, #4 + 800199c: b2d2 uxtb r2, r2 + 800199e: 440b add r3, r1 + 80019a0: f883 2300 strb.w r2, [r3, #768] @ 0x300 + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + 80019a4: e00a b.n 80019bc <__NVIC_SetPriority+0x40> + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + 80019a6: 683b ldr r3, [r7, #0] + 80019a8: b2da uxtb r2, r3 + 80019aa: 4908 ldr r1, [pc, #32] @ (80019cc <__NVIC_SetPriority+0x50>) + 80019ac: 79fb ldrb r3, [r7, #7] + 80019ae: f003 030f and.w r3, r3, #15 + 80019b2: 3b04 subs r3, #4 + 80019b4: 0112 lsls r2, r2, #4 + 80019b6: b2d2 uxtb r2, r2 + 80019b8: 440b add r3, r1 + 80019ba: 761a strb r2, [r3, #24] +} + 80019bc: bf00 nop + 80019be: 370c adds r7, #12 + 80019c0: 46bd mov sp, r7 + 80019c2: bc80 pop {r7} + 80019c4: 4770 bx lr + 80019c6: bf00 nop + 80019c8: e000e100 .word 0xe000e100 + 80019cc: e000ed00 .word 0xe000ed00 + +080019d0 : + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + 80019d0: b480 push {r7} + 80019d2: b089 sub sp, #36 @ 0x24 + 80019d4: af00 add r7, sp, #0 + 80019d6: 60f8 str r0, [r7, #12] + 80019d8: 60b9 str r1, [r7, #8] + 80019da: 607a str r2, [r7, #4] + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + 80019dc: 68fb ldr r3, [r7, #12] + 80019de: f003 0307 and.w r3, r3, #7 + 80019e2: 61fb str r3, [r7, #28] + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + 80019e4: 69fb ldr r3, [r7, #28] + 80019e6: f1c3 0307 rsb r3, r3, #7 + 80019ea: 2b04 cmp r3, #4 + 80019ec: bf28 it cs + 80019ee: 2304 movcs r3, #4 + 80019f0: 61bb str r3, [r7, #24] + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + 80019f2: 69fb ldr r3, [r7, #28] + 80019f4: 3304 adds r3, #4 + 80019f6: 2b06 cmp r3, #6 + 80019f8: d902 bls.n 8001a00 + 80019fa: 69fb ldr r3, [r7, #28] + 80019fc: 3b03 subs r3, #3 + 80019fe: e000 b.n 8001a02 + 8001a00: 2300 movs r3, #0 + 8001a02: 617b str r3, [r7, #20] + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + 8001a04: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff + 8001a08: 69bb ldr r3, [r7, #24] + 8001a0a: fa02 f303 lsl.w r3, r2, r3 + 8001a0e: 43da mvns r2, r3 + 8001a10: 68bb ldr r3, [r7, #8] + 8001a12: 401a ands r2, r3 + 8001a14: 697b ldr r3, [r7, #20] + 8001a16: 409a lsls r2, r3 + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + 8001a18: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff + 8001a1c: 697b ldr r3, [r7, #20] + 8001a1e: fa01 f303 lsl.w r3, r1, r3 + 8001a22: 43d9 mvns r1, r3 + 8001a24: 687b ldr r3, [r7, #4] + 8001a26: 400b ands r3, r1 + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + 8001a28: 4313 orrs r3, r2 + ); +} + 8001a2a: 4618 mov r0, r3 + 8001a2c: 3724 adds r7, #36 @ 0x24 + 8001a2e: 46bd mov sp, r7 + 8001a30: bc80 pop {r7} + 8001a32: 4770 bx lr + +08001a34 : + * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. + * The pending IRQ priority will be managed only by the subpriority. + * @retval None + */ +void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + 8001a34: b580 push {r7, lr} + 8001a36: b082 sub sp, #8 + 8001a38: af00 add r7, sp, #0 + 8001a3a: 6078 str r0, [r7, #4] + /* Check the parameters */ + assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); + + /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ + NVIC_SetPriorityGrouping(PriorityGroup); + 8001a3c: 6878 ldr r0, [r7, #4] + 8001a3e: f7ff ff2b bl 8001898 <__NVIC_SetPriorityGrouping> +} + 8001a42: bf00 nop + 8001a44: 3708 adds r7, #8 + 8001a46: 46bd mov sp, r7 + 8001a48: bd80 pop {r7, pc} + +08001a4a : + * This parameter can be a value between 0 and 15 + * A lower priority value indicates a higher priority. + * @retval None + */ +void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) +{ + 8001a4a: b580 push {r7, lr} + 8001a4c: b086 sub sp, #24 + 8001a4e: af00 add r7, sp, #0 + 8001a50: 4603 mov r3, r0 + 8001a52: 60b9 str r1, [r7, #8] + 8001a54: 607a str r2, [r7, #4] + 8001a56: 73fb strb r3, [r7, #15] + + /* Check the parameters */ + assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); + assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); + + prioritygroup = NVIC_GetPriorityGrouping(); + 8001a58: f7ff ff42 bl 80018e0 <__NVIC_GetPriorityGrouping> + 8001a5c: 6178 str r0, [r7, #20] + + NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); + 8001a5e: 687a ldr r2, [r7, #4] + 8001a60: 68b9 ldr r1, [r7, #8] + 8001a62: 6978 ldr r0, [r7, #20] + 8001a64: f7ff ffb4 bl 80019d0 + 8001a68: 4602 mov r2, r0 + 8001a6a: f997 300f ldrsb.w r3, [r7, #15] + 8001a6e: 4611 mov r1, r2 + 8001a70: 4618 mov r0, r3 + 8001a72: f7ff ff83 bl 800197c <__NVIC_SetPriority> +} + 8001a76: bf00 nop + 8001a78: 3718 adds r7, #24 + 8001a7a: 46bd mov sp, r7 + 8001a7c: bd80 pop {r7, pc} + +08001a7e : + * (For the complete STM32 Devices IRQ Channels list, please refer + * to the appropriate CMSIS device file (stm32wlxxxx.h)) + * @retval None + */ +void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) +{ + 8001a7e: b580 push {r7, lr} + 8001a80: b082 sub sp, #8 + 8001a82: af00 add r7, sp, #0 + 8001a84: 4603 mov r3, r0 + 8001a86: 71fb strb r3, [r7, #7] + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Enable interrupt */ + NVIC_EnableIRQ(IRQn); + 8001a88: f997 3007 ldrsb.w r3, [r7, #7] + 8001a8c: 4618 mov r0, r3 + 8001a8e: f7ff ff35 bl 80018fc <__NVIC_EnableIRQ> +} + 8001a92: bf00 nop + 8001a94: 3708 adds r7, #8 + 8001a96: 46bd mov sp, r7 + 8001a98: bd80 pop {r7, pc} + +08001a9a : + * (For the complete STM32 Devices IRQ Channels list, please refer + * to the appropriate CMSIS device file (stm32wlxxxx.h)) + * @retval None + */ +void HAL_NVIC_DisableIRQ(IRQn_Type IRQn) +{ + 8001a9a: b580 push {r7, lr} + 8001a9c: b082 sub sp, #8 + 8001a9e: af00 add r7, sp, #0 + 8001aa0: 4603 mov r3, r0 + 8001aa2: 71fb strb r3, [r7, #7] + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Disable interrupt */ + NVIC_DisableIRQ(IRQn); + 8001aa4: f997 3007 ldrsb.w r3, [r7, #7] + 8001aa8: 4618 mov r0, r3 + 8001aaa: f7ff ff43 bl 8001934 <__NVIC_DisableIRQ> +} + 8001aae: bf00 nop + 8001ab0: 3708 adds r7, #8 + 8001ab2: 46bd mov sp, r7 + 8001ab4: bd80 pop {r7, pc} + ... + +08001ab8 : + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) +{ + 8001ab8: b580 push {r7, lr} + 8001aba: b082 sub sp, #8 + 8001abc: af00 add r7, sp, #0 + 8001abe: 6078 str r0, [r7, #4] + /* Check the DMA handle allocation */ + if (hdma == NULL) + 8001ac0: 687b ldr r3, [r7, #4] + 8001ac2: 2b00 cmp r3, #0 + 8001ac4: d101 bne.n 8001aca + { + return HAL_ERROR; + 8001ac6: 2301 movs r3, #1 + 8001ac8: e08e b.n 8001be8 + assert_param(IS_DMA_PRIORITY(hdma->Init.Priority)); + + assert_param(IS_DMA_ALL_REQUEST(hdma->Init.Request)); + + /* Compute the channel index */ + if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1)) + 8001aca: 687b ldr r3, [r7, #4] + 8001acc: 681b ldr r3, [r3, #0] + 8001ace: 461a mov r2, r3 + 8001ad0: 4b47 ldr r3, [pc, #284] @ (8001bf0 ) + 8001ad2: 429a cmp r2, r3 + 8001ad4: d80f bhi.n 8001af6 + { + /* DMA1 */ + hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U; + 8001ad6: 687b ldr r3, [r7, #4] + 8001ad8: 681b ldr r3, [r3, #0] + 8001ada: 461a mov r2, r3 + 8001adc: 4b45 ldr r3, [pc, #276] @ (8001bf4 ) + 8001ade: 4413 add r3, r2 + 8001ae0: 4a45 ldr r2, [pc, #276] @ (8001bf8 ) + 8001ae2: fba2 2303 umull r2, r3, r2, r3 + 8001ae6: 091b lsrs r3, r3, #4 + 8001ae8: 009a lsls r2, r3, #2 + 8001aea: 687b ldr r3, [r7, #4] + 8001aec: 645a str r2, [r3, #68] @ 0x44 + hdma->DmaBaseAddress = DMA1; + 8001aee: 687b ldr r3, [r7, #4] + 8001af0: 4a42 ldr r2, [pc, #264] @ (8001bfc ) + 8001af2: 641a str r2, [r3, #64] @ 0x40 + 8001af4: e00e b.n 8001b14 + } + else + { + /* DMA2 */ + hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2U; + 8001af6: 687b ldr r3, [r7, #4] + 8001af8: 681b ldr r3, [r3, #0] + 8001afa: 461a mov r2, r3 + 8001afc: 4b40 ldr r3, [pc, #256] @ (8001c00 ) + 8001afe: 4413 add r3, r2 + 8001b00: 4a3d ldr r2, [pc, #244] @ (8001bf8 ) + 8001b02: fba2 2303 umull r2, r3, r2, r3 + 8001b06: 091b lsrs r3, r3, #4 + 8001b08: 009a lsls r2, r3, #2 + 8001b0a: 687b ldr r3, [r7, #4] + 8001b0c: 645a str r2, [r3, #68] @ 0x44 + hdma->DmaBaseAddress = DMA2; + 8001b0e: 687b ldr r3, [r7, #4] + 8001b10: 4a3c ldr r2, [pc, #240] @ (8001c04 ) + 8001b12: 641a str r2, [r3, #64] @ 0x40 + } + + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_BUSY; + 8001b14: 687b ldr r3, [r7, #4] + 8001b16: 2202 movs r2, #2 + 8001b18: f883 2025 strb.w r2, [r3, #37] @ 0x25 + + /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR and MEM2MEM bits */ + CLEAR_BIT(hdma->Instance->CCR, (DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | \ + 8001b1c: 687b ldr r3, [r7, #4] + 8001b1e: 681b ldr r3, [r3, #0] + 8001b20: 681b ldr r3, [r3, #0] + 8001b22: 687a ldr r2, [r7, #4] + 8001b24: 6812 ldr r2, [r2, #0] + 8001b26: f423 43ff bic.w r3, r3, #32640 @ 0x7f80 + 8001b2a: f023 0370 bic.w r3, r3, #112 @ 0x70 + 8001b2e: 6013 str r3, [r2, #0] + DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | \ + DMA_CCR_DIR | DMA_CCR_MEM2MEM)); + + /* Set the DMA Channel configuration */ + SET_BIT(hdma->Instance->CCR, (hdma->Init.Direction | \ + 8001b30: 687b ldr r3, [r7, #4] + 8001b32: 681b ldr r3, [r3, #0] + 8001b34: 6819 ldr r1, [r3, #0] + 8001b36: 687b ldr r3, [r7, #4] + 8001b38: 689a ldr r2, [r3, #8] + 8001b3a: 687b ldr r3, [r7, #4] + 8001b3c: 68db ldr r3, [r3, #12] + 8001b3e: 431a orrs r2, r3 + 8001b40: 687b ldr r3, [r7, #4] + 8001b42: 691b ldr r3, [r3, #16] + 8001b44: 431a orrs r2, r3 + 8001b46: 687b ldr r3, [r7, #4] + 8001b48: 695b ldr r3, [r3, #20] + 8001b4a: 431a orrs r2, r3 + 8001b4c: 687b ldr r3, [r7, #4] + 8001b4e: 699b ldr r3, [r3, #24] + 8001b50: 431a orrs r2, r3 + 8001b52: 687b ldr r3, [r7, #4] + 8001b54: 69db ldr r3, [r3, #28] + 8001b56: 431a orrs r2, r3 + 8001b58: 687b ldr r3, [r7, #4] + 8001b5a: 6a1b ldr r3, [r3, #32] + 8001b5c: 431a orrs r2, r3 + 8001b5e: 687b ldr r3, [r7, #4] + 8001b60: 681b ldr r3, [r3, #0] + 8001b62: 430a orrs r2, r1 + 8001b64: 601a str r2, [r3, #0] + hdma->Init.Mode | hdma->Init.Priority)); + + /* Initialize parameters for DMAMUX channel : + DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask + */ + DMA_CalcDMAMUXChannelBaseAndMask(hdma); + 8001b66: 6878 ldr r0, [r7, #4] + 8001b68: f000 fb52 bl 8002210 + + if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY) + 8001b6c: 687b ldr r3, [r7, #4] + 8001b6e: 689b ldr r3, [r3, #8] + 8001b70: f5b3 4f80 cmp.w r3, #16384 @ 0x4000 + 8001b74: d102 bne.n 8001b7c + { + /* if memory to memory force the request to 0*/ + hdma->Init.Request = DMA_REQUEST_MEM2MEM; + 8001b76: 687b ldr r3, [r7, #4] + 8001b78: 2200 movs r2, #0 + 8001b7a: 605a str r2, [r3, #4] + } + + /* Set peripheral request to DMAMUX channel */ + hdma->DMAmuxChannel->CCR = (hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID); + 8001b7c: 687b ldr r3, [r7, #4] + 8001b7e: 685a ldr r2, [r3, #4] + 8001b80: 687b ldr r3, [r7, #4] + 8001b82: 6c9b ldr r3, [r3, #72] @ 0x48 + 8001b84: f002 027f and.w r2, r2, #127 @ 0x7f + 8001b88: 601a str r2, [r3, #0] + + /* Clear the DMAMUX synchro overrun flag */ + hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; + 8001b8a: 687b ldr r3, [r7, #4] + 8001b8c: 6cdb ldr r3, [r3, #76] @ 0x4c + 8001b8e: 687a ldr r2, [r7, #4] + 8001b90: 6d12 ldr r2, [r2, #80] @ 0x50 + 8001b92: 605a str r2, [r3, #4] + + if (((hdma->Init.Request > 0UL) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR3))) + 8001b94: 687b ldr r3, [r7, #4] + 8001b96: 685b ldr r3, [r3, #4] + 8001b98: 2b00 cmp r3, #0 + 8001b9a: d010 beq.n 8001bbe + 8001b9c: 687b ldr r3, [r7, #4] + 8001b9e: 685b ldr r3, [r3, #4] + 8001ba0: 2b04 cmp r3, #4 + 8001ba2: d80c bhi.n 8001bbe + { + /* Initialize parameters for DMAMUX request generator : + DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask + */ + DMA_CalcDMAMUXRequestGenBaseAndMask(hdma); + 8001ba4: 6878 ldr r0, [r7, #4] + 8001ba6: f000 fb7b bl 80022a0 + + /* Reset the DMAMUX request generator register*/ + hdma->DMAmuxRequestGen->RGCR = 0U; + 8001baa: 687b ldr r3, [r7, #4] + 8001bac: 6d5b ldr r3, [r3, #84] @ 0x54 + 8001bae: 2200 movs r2, #0 + 8001bb0: 601a str r2, [r3, #0] + + /* Clear the DMAMUX request generator overrun flag */ + hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; + 8001bb2: 687b ldr r3, [r7, #4] + 8001bb4: 6d9b ldr r3, [r3, #88] @ 0x58 + 8001bb6: 687a ldr r2, [r7, #4] + 8001bb8: 6dd2 ldr r2, [r2, #92] @ 0x5c + 8001bba: 605a str r2, [r3, #4] + 8001bbc: e008 b.n 8001bd0 + } + else + { + hdma->DMAmuxRequestGen = NULL; + 8001bbe: 687b ldr r3, [r7, #4] + 8001bc0: 2200 movs r2, #0 + 8001bc2: 655a str r2, [r3, #84] @ 0x54 + hdma->DMAmuxRequestGenStatus = NULL; + 8001bc4: 687b ldr r3, [r7, #4] + 8001bc6: 2200 movs r2, #0 + 8001bc8: 659a str r2, [r3, #88] @ 0x58 + hdma->DMAmuxRequestGenStatusMask = 0U; + 8001bca: 687b ldr r3, [r7, #4] + 8001bcc: 2200 movs r2, #0 + 8001bce: 65da str r2, [r3, #92] @ 0x5c + } + + /* Initialize the error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + 8001bd0: 687b ldr r3, [r7, #4] + 8001bd2: 2200 movs r2, #0 + 8001bd4: 63da str r2, [r3, #60] @ 0x3c + + /* Initialize the DMA state*/ + hdma->State = HAL_DMA_STATE_READY; + 8001bd6: 687b ldr r3, [r7, #4] + 8001bd8: 2201 movs r2, #1 + 8001bda: f883 2025 strb.w r2, [r3, #37] @ 0x25 + + /* Release Lock */ + __HAL_UNLOCK(hdma); + 8001bde: 687b ldr r3, [r7, #4] + 8001be0: 2200 movs r2, #0 + 8001be2: f883 2024 strb.w r2, [r3, #36] @ 0x24 + + return HAL_OK; + 8001be6: 2300 movs r3, #0 +} + 8001be8: 4618 mov r0, r3 + 8001bea: 3708 adds r7, #8 + 8001bec: 46bd mov sp, r7 + 8001bee: bd80 pop {r7, pc} + 8001bf0: 40020407 .word 0x40020407 + 8001bf4: bffdfff8 .word 0xbffdfff8 + 8001bf8: cccccccd .word 0xcccccccd + 8001bfc: 40020000 .word 0x40020000 + 8001c00: bffdfbf8 .word 0xbffdfbf8 + 8001c04: 40020400 .word 0x40020400 + +08001c08 : + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) +{ + 8001c08: b580 push {r7, lr} + 8001c0a: b082 sub sp, #8 + 8001c0c: af00 add r7, sp, #0 + 8001c0e: 6078 str r0, [r7, #4] + /* Check the DMA handle allocation */ + if (NULL == hdma) + 8001c10: 687b ldr r3, [r7, #4] + 8001c12: 2b00 cmp r3, #0 + 8001c14: d101 bne.n 8001c1a + { + return HAL_ERROR; + 8001c16: 2301 movs r3, #1 + 8001c18: e07b b.n 8001d12 + + /* Check the parameters */ + assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); + + /* Disable the selected DMA Channelx */ + __HAL_DMA_DISABLE(hdma); + 8001c1a: 687b ldr r3, [r7, #4] + 8001c1c: 681b ldr r3, [r3, #0] + 8001c1e: 681a ldr r2, [r3, #0] + 8001c20: 687b ldr r3, [r7, #4] + 8001c22: 681b ldr r3, [r3, #0] + 8001c24: f022 0201 bic.w r2, r2, #1 + 8001c28: 601a str r2, [r3, #0] + + /* Compute the channel index */ + if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1)) + 8001c2a: 687b ldr r3, [r7, #4] + 8001c2c: 681b ldr r3, [r3, #0] + 8001c2e: 461a mov r2, r3 + 8001c30: 4b3a ldr r3, [pc, #232] @ (8001d1c ) + 8001c32: 429a cmp r2, r3 + 8001c34: d80f bhi.n 8001c56 + { + /* DMA1 */ + hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U; + 8001c36: 687b ldr r3, [r7, #4] + 8001c38: 681b ldr r3, [r3, #0] + 8001c3a: 461a mov r2, r3 + 8001c3c: 4b38 ldr r3, [pc, #224] @ (8001d20 ) + 8001c3e: 4413 add r3, r2 + 8001c40: 4a38 ldr r2, [pc, #224] @ (8001d24 ) + 8001c42: fba2 2303 umull r2, r3, r2, r3 + 8001c46: 091b lsrs r3, r3, #4 + 8001c48: 009a lsls r2, r3, #2 + 8001c4a: 687b ldr r3, [r7, #4] + 8001c4c: 645a str r2, [r3, #68] @ 0x44 + hdma->DmaBaseAddress = DMA1; + 8001c4e: 687b ldr r3, [r7, #4] + 8001c50: 4a35 ldr r2, [pc, #212] @ (8001d28 ) + 8001c52: 641a str r2, [r3, #64] @ 0x40 + 8001c54: e00e b.n 8001c74 + } + else + { + /* DMA2 */ + hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2U; + 8001c56: 687b ldr r3, [r7, #4] + 8001c58: 681b ldr r3, [r3, #0] + 8001c5a: 461a mov r2, r3 + 8001c5c: 4b33 ldr r3, [pc, #204] @ (8001d2c ) + 8001c5e: 4413 add r3, r2 + 8001c60: 4a30 ldr r2, [pc, #192] @ (8001d24 ) + 8001c62: fba2 2303 umull r2, r3, r2, r3 + 8001c66: 091b lsrs r3, r3, #4 + 8001c68: 009a lsls r2, r3, #2 + 8001c6a: 687b ldr r3, [r7, #4] + 8001c6c: 645a str r2, [r3, #68] @ 0x44 + hdma->DmaBaseAddress = DMA2; + 8001c6e: 687b ldr r3, [r7, #4] + 8001c70: 4a2f ldr r2, [pc, #188] @ (8001d30 ) + 8001c72: 641a str r2, [r3, #64] @ 0x40 + } + + /* Reset DMA Channel control register */ + hdma->Instance->CCR = 0U; + 8001c74: 687b ldr r3, [r7, #4] + 8001c76: 681b ldr r3, [r3, #0] + 8001c78: 2200 movs r2, #0 + 8001c7a: 601a str r2, [r3, #0] + + /* Clear all flags */ + hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU)); + 8001c7c: 687b ldr r3, [r7, #4] + 8001c7e: 6c5b ldr r3, [r3, #68] @ 0x44 + 8001c80: f003 021c and.w r2, r3, #28 + 8001c84: 687b ldr r3, [r7, #4] + 8001c86: 6c1b ldr r3, [r3, #64] @ 0x40 + 8001c88: 2101 movs r1, #1 + 8001c8a: fa01 f202 lsl.w r2, r1, r2 + 8001c8e: 605a str r2, [r3, #4] + + /* Initialize parameters for DMAMUX channel : + DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask */ + + DMA_CalcDMAMUXChannelBaseAndMask(hdma); + 8001c90: 6878 ldr r0, [r7, #4] + 8001c92: f000 fabd bl 8002210 + + /* Reset the DMAMUX channel that corresponds to the DMA channel */ + hdma->DMAmuxChannel->CCR = 0U; + 8001c96: 687b ldr r3, [r7, #4] + 8001c98: 6c9b ldr r3, [r3, #72] @ 0x48 + 8001c9a: 2200 movs r2, #0 + 8001c9c: 601a str r2, [r3, #0] + + /* Clear the DMAMUX synchro overrun flag */ + hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; + 8001c9e: 687b ldr r3, [r7, #4] + 8001ca0: 6cdb ldr r3, [r3, #76] @ 0x4c + 8001ca2: 687a ldr r2, [r7, #4] + 8001ca4: 6d12 ldr r2, [r2, #80] @ 0x50 + 8001ca6: 605a str r2, [r3, #4] + + /* Reset Request generator parameters if any */ + if (((hdma->Init.Request > 0UL) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR3))) + 8001ca8: 687b ldr r3, [r7, #4] + 8001caa: 685b ldr r3, [r3, #4] + 8001cac: 2b00 cmp r3, #0 + 8001cae: d00f beq.n 8001cd0 + 8001cb0: 687b ldr r3, [r7, #4] + 8001cb2: 685b ldr r3, [r3, #4] + 8001cb4: 2b04 cmp r3, #4 + 8001cb6: d80b bhi.n 8001cd0 + { + /* Initialize parameters for DMAMUX request generator : + DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask + */ + DMA_CalcDMAMUXRequestGenBaseAndMask(hdma); + 8001cb8: 6878 ldr r0, [r7, #4] + 8001cba: f000 faf1 bl 80022a0 + + /* Reset the DMAMUX request generator register*/ + hdma->DMAmuxRequestGen->RGCR = 0U; + 8001cbe: 687b ldr r3, [r7, #4] + 8001cc0: 6d5b ldr r3, [r3, #84] @ 0x54 + 8001cc2: 2200 movs r2, #0 + 8001cc4: 601a str r2, [r3, #0] + + /* Clear the DMAMUX request generator overrun flag */ + hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; + 8001cc6: 687b ldr r3, [r7, #4] + 8001cc8: 6d9b ldr r3, [r3, #88] @ 0x58 + 8001cca: 687a ldr r2, [r7, #4] + 8001ccc: 6dd2 ldr r2, [r2, #92] @ 0x5c + 8001cce: 605a str r2, [r3, #4] + } + + hdma->DMAmuxRequestGen = NULL; + 8001cd0: 687b ldr r3, [r7, #4] + 8001cd2: 2200 movs r2, #0 + 8001cd4: 655a str r2, [r3, #84] @ 0x54 + hdma->DMAmuxRequestGenStatus = NULL; + 8001cd6: 687b ldr r3, [r7, #4] + 8001cd8: 2200 movs r2, #0 + 8001cda: 659a str r2, [r3, #88] @ 0x58 + hdma->DMAmuxRequestGenStatusMask = 0U; + 8001cdc: 687b ldr r3, [r7, #4] + 8001cde: 2200 movs r2, #0 + 8001ce0: 65da str r2, [r3, #92] @ 0x5c + + /* Clean callbacks */ + hdma->XferCpltCallback = NULL; + 8001ce2: 687b ldr r3, [r7, #4] + 8001ce4: 2200 movs r2, #0 + 8001ce6: 62da str r2, [r3, #44] @ 0x2c + hdma->XferHalfCpltCallback = NULL; + 8001ce8: 687b ldr r3, [r7, #4] + 8001cea: 2200 movs r2, #0 + 8001cec: 631a str r2, [r3, #48] @ 0x30 + hdma->XferErrorCallback = NULL; + 8001cee: 687b ldr r3, [r7, #4] + 8001cf0: 2200 movs r2, #0 + 8001cf2: 635a str r2, [r3, #52] @ 0x34 + hdma->XferAbortCallback = NULL; + 8001cf4: 687b ldr r3, [r7, #4] + 8001cf6: 2200 movs r2, #0 + 8001cf8: 639a str r2, [r3, #56] @ 0x38 + + /* Initialize the error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + 8001cfa: 687b ldr r3, [r7, #4] + 8001cfc: 2200 movs r2, #0 + 8001cfe: 63da str r2, [r3, #60] @ 0x3c + + /* Initialize the DMA state */ + hdma->State = HAL_DMA_STATE_RESET; + 8001d00: 687b ldr r3, [r7, #4] + 8001d02: 2200 movs r2, #0 + 8001d04: f883 2025 strb.w r2, [r3, #37] @ 0x25 + + /* Release Lock */ + __HAL_UNLOCK(hdma); + 8001d08: 687b ldr r3, [r7, #4] + 8001d0a: 2200 movs r2, #0 + 8001d0c: f883 2024 strb.w r2, [r3, #36] @ 0x24 + + return HAL_OK; + 8001d10: 2300 movs r3, #0 +} + 8001d12: 4618 mov r0, r3 + 8001d14: 3708 adds r7, #8 + 8001d16: 46bd mov sp, r7 + 8001d18: bd80 pop {r7, pc} + 8001d1a: bf00 nop + 8001d1c: 40020407 .word 0x40020407 + 8001d20: bffdfff8 .word 0xbffdfff8 + 8001d24: cccccccd .word 0xcccccccd + 8001d28: 40020000 .word 0x40020000 + 8001d2c: bffdfbf8 .word 0xbffdfbf8 + 8001d30: 40020400 .word 0x40020400 + +08001d34 : + * @param DataLength The length of data to be transferred from source to destination + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, + uint32_t DataLength) +{ + 8001d34: b580 push {r7, lr} + 8001d36: b086 sub sp, #24 + 8001d38: af00 add r7, sp, #0 + 8001d3a: 60f8 str r0, [r7, #12] + 8001d3c: 60b9 str r1, [r7, #8] + 8001d3e: 607a str r2, [r7, #4] + 8001d40: 603b str r3, [r7, #0] + HAL_StatusTypeDef status = HAL_OK; + 8001d42: 2300 movs r3, #0 + 8001d44: 75fb strb r3, [r7, #23] + + /* Check the parameters */ + assert_param(IS_DMA_BUFFER_SIZE(DataLength)); + + /* Process locked */ + __HAL_LOCK(hdma); + 8001d46: 68fb ldr r3, [r7, #12] + 8001d48: f893 3024 ldrb.w r3, [r3, #36] @ 0x24 + 8001d4c: 2b01 cmp r3, #1 + 8001d4e: d101 bne.n 8001d54 + 8001d50: 2302 movs r3, #2 + 8001d52: e069 b.n 8001e28 + 8001d54: 68fb ldr r3, [r7, #12] + 8001d56: 2201 movs r2, #1 + 8001d58: f883 2024 strb.w r2, [r3, #36] @ 0x24 + + if (hdma->State == HAL_DMA_STATE_READY) + 8001d5c: 68fb ldr r3, [r7, #12] + 8001d5e: f893 3025 ldrb.w r3, [r3, #37] @ 0x25 + 8001d62: b2db uxtb r3, r3 + 8001d64: 2b01 cmp r3, #1 + 8001d66: d155 bne.n 8001e14 + { + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_BUSY; + 8001d68: 68fb ldr r3, [r7, #12] + 8001d6a: 2202 movs r2, #2 + 8001d6c: f883 2025 strb.w r2, [r3, #37] @ 0x25 + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + 8001d70: 68fb ldr r3, [r7, #12] + 8001d72: 2200 movs r2, #0 + 8001d74: 63da str r2, [r3, #60] @ 0x3c + + /* Disable the peripheral */ + __HAL_DMA_DISABLE(hdma); + 8001d76: 68fb ldr r3, [r7, #12] + 8001d78: 681b ldr r3, [r3, #0] + 8001d7a: 681a ldr r2, [r3, #0] + 8001d7c: 68fb ldr r3, [r7, #12] + 8001d7e: 681b ldr r3, [r3, #0] + 8001d80: f022 0201 bic.w r2, r2, #1 + 8001d84: 601a str r2, [r3, #0] + + /* Configure the source, destination address and the data length & clear flags*/ + DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); + 8001d86: 683b ldr r3, [r7, #0] + 8001d88: 687a ldr r2, [r7, #4] + 8001d8a: 68b9 ldr r1, [r7, #8] + 8001d8c: 68f8 ldr r0, [r7, #12] + 8001d8e: f000 fa02 bl 8002196 + + /* Enable the transfer complete interrupt */ + /* Enable the transfer Error interrupt */ + if (NULL != hdma->XferHalfCpltCallback) + 8001d92: 68fb ldr r3, [r7, #12] + 8001d94: 6b1b ldr r3, [r3, #48] @ 0x30 + 8001d96: 2b00 cmp r3, #0 + 8001d98: d008 beq.n 8001dac + { + /* Enable the Half transfer complete interrupt as well */ + __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); + 8001d9a: 68fb ldr r3, [r7, #12] + 8001d9c: 681b ldr r3, [r3, #0] + 8001d9e: 681a ldr r2, [r3, #0] + 8001da0: 68fb ldr r3, [r7, #12] + 8001da2: 681b ldr r3, [r3, #0] + 8001da4: f042 020e orr.w r2, r2, #14 + 8001da8: 601a str r2, [r3, #0] + 8001daa: e00f b.n 8001dcc + } + else + { + __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); + 8001dac: 68fb ldr r3, [r7, #12] + 8001dae: 681b ldr r3, [r3, #0] + 8001db0: 681a ldr r2, [r3, #0] + 8001db2: 68fb ldr r3, [r7, #12] + 8001db4: 681b ldr r3, [r3, #0] + 8001db6: f022 0204 bic.w r2, r2, #4 + 8001dba: 601a str r2, [r3, #0] + __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE)); + 8001dbc: 68fb ldr r3, [r7, #12] + 8001dbe: 681b ldr r3, [r3, #0] + 8001dc0: 681a ldr r2, [r3, #0] + 8001dc2: 68fb ldr r3, [r7, #12] + 8001dc4: 681b ldr r3, [r3, #0] + 8001dc6: f042 020a orr.w r2, r2, #10 + 8001dca: 601a str r2, [r3, #0] + } + + /* Check if DMAMUX Synchronization is enabled*/ + if ((hdma->DMAmuxChannel->CCR & DMAMUX_CxCR_SE) != 0U) + 8001dcc: 68fb ldr r3, [r7, #12] + 8001dce: 6c9b ldr r3, [r3, #72] @ 0x48 + 8001dd0: 681b ldr r3, [r3, #0] + 8001dd2: f403 3380 and.w r3, r3, #65536 @ 0x10000 + 8001dd6: 2b00 cmp r3, #0 + 8001dd8: d007 beq.n 8001dea + { + /* Enable DMAMUX sync overrun IT*/ + hdma->DMAmuxChannel->CCR |= DMAMUX_CxCR_SOIE; + 8001dda: 68fb ldr r3, [r7, #12] + 8001ddc: 6c9b ldr r3, [r3, #72] @ 0x48 + 8001dde: 681a ldr r2, [r3, #0] + 8001de0: 68fb ldr r3, [r7, #12] + 8001de2: 6c9b ldr r3, [r3, #72] @ 0x48 + 8001de4: f442 7280 orr.w r2, r2, #256 @ 0x100 + 8001de8: 601a str r2, [r3, #0] + } + + if (hdma->DMAmuxRequestGen != NULL) + 8001dea: 68fb ldr r3, [r7, #12] + 8001dec: 6d5b ldr r3, [r3, #84] @ 0x54 + 8001dee: 2b00 cmp r3, #0 + 8001df0: d007 beq.n 8001e02 + { + /* if using DMAMUX request generator, enable the DMAMUX request generator overrun IT*/ + /* enable the request gen overrun IT*/ + hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE; + 8001df2: 68fb ldr r3, [r7, #12] + 8001df4: 6d5b ldr r3, [r3, #84] @ 0x54 + 8001df6: 681a ldr r2, [r3, #0] + 8001df8: 68fb ldr r3, [r7, #12] + 8001dfa: 6d5b ldr r3, [r3, #84] @ 0x54 + 8001dfc: f442 7280 orr.w r2, r2, #256 @ 0x100 + 8001e00: 601a str r2, [r3, #0] + } + + /* Enable the Peripheral */ + __HAL_DMA_ENABLE(hdma); + 8001e02: 68fb ldr r3, [r7, #12] + 8001e04: 681b ldr r3, [r3, #0] + 8001e06: 681a ldr r2, [r3, #0] + 8001e08: 68fb ldr r3, [r7, #12] + 8001e0a: 681b ldr r3, [r3, #0] + 8001e0c: f042 0201 orr.w r2, r2, #1 + 8001e10: 601a str r2, [r3, #0] + 8001e12: e008 b.n 8001e26 + } + else + { + /* Change the error code */ + hdma->ErrorCode = HAL_DMA_ERROR_BUSY; + 8001e14: 68fb ldr r3, [r7, #12] + 8001e16: 2280 movs r2, #128 @ 0x80 + 8001e18: 63da str r2, [r3, #60] @ 0x3c + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + 8001e1a: 68fb ldr r3, [r7, #12] + 8001e1c: 2200 movs r2, #0 + 8001e1e: f883 2024 strb.w r2, [r3, #36] @ 0x24 + + /* Return error status */ + status = HAL_ERROR; + 8001e22: 2301 movs r3, #1 + 8001e24: 75fb strb r3, [r7, #23] + } + + return status; + 8001e26: 7dfb ldrb r3, [r7, #23] +} + 8001e28: 4618 mov r0, r3 + 8001e2a: 3718 adds r7, #24 + 8001e2c: 46bd mov sp, r7 + 8001e2e: bd80 pop {r7, pc} + +08001e30 : + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) +{ + 8001e30: b480 push {r7} + 8001e32: b083 sub sp, #12 + 8001e34: af00 add r7, sp, #0 + 8001e36: 6078 str r0, [r7, #4] + /* Check the DMA peripheral handle */ + if (NULL == hdma) + 8001e38: 687b ldr r3, [r7, #4] + 8001e3a: 2b00 cmp r3, #0 + 8001e3c: d101 bne.n 8001e42 + { + return HAL_ERROR; + 8001e3e: 2301 movs r3, #1 + 8001e40: e04f b.n 8001ee2 + } + + /* Check the DMA peripheral state */ + if (hdma->State != HAL_DMA_STATE_BUSY) + 8001e42: 687b ldr r3, [r7, #4] + 8001e44: f893 3025 ldrb.w r3, [r3, #37] @ 0x25 + 8001e48: b2db uxtb r3, r3 + 8001e4a: 2b02 cmp r3, #2 + 8001e4c: d008 beq.n 8001e60 + { + hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + 8001e4e: 687b ldr r3, [r7, #4] + 8001e50: 2204 movs r2, #4 + 8001e52: 63da str r2, [r3, #60] @ 0x3c + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + 8001e54: 687b ldr r3, [r7, #4] + 8001e56: 2200 movs r2, #0 + 8001e58: f883 2024 strb.w r2, [r3, #36] @ 0x24 + + return HAL_ERROR; + 8001e5c: 2301 movs r3, #1 + 8001e5e: e040 b.n 8001ee2 + } + else + { + /* Disable the channel */ + __HAL_DMA_DISABLE(hdma); + 8001e60: 687b ldr r3, [r7, #4] + 8001e62: 681b ldr r3, [r3, #0] + 8001e64: 681a ldr r2, [r3, #0] + 8001e66: 687b ldr r3, [r7, #4] + 8001e68: 681b ldr r3, [r3, #0] + 8001e6a: f022 0201 bic.w r2, r2, #1 + 8001e6e: 601a str r2, [r3, #0] + + /* Disable DMA IT */ + __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); + 8001e70: 687b ldr r3, [r7, #4] + 8001e72: 681b ldr r3, [r3, #0] + 8001e74: 681a ldr r2, [r3, #0] + 8001e76: 687b ldr r3, [r7, #4] + 8001e78: 681b ldr r3, [r3, #0] + 8001e7a: f022 020e bic.w r2, r2, #14 + 8001e7e: 601a str r2, [r3, #0] + + /* disable the DMAMUX sync overrun IT*/ + hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; + 8001e80: 687b ldr r3, [r7, #4] + 8001e82: 6c9b ldr r3, [r3, #72] @ 0x48 + 8001e84: 681a ldr r2, [r3, #0] + 8001e86: 687b ldr r3, [r7, #4] + 8001e88: 6c9b ldr r3, [r3, #72] @ 0x48 + 8001e8a: f422 7280 bic.w r2, r2, #256 @ 0x100 + 8001e8e: 601a str r2, [r3, #0] + + /* Clear all flags */ + hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU)); + 8001e90: 687b ldr r3, [r7, #4] + 8001e92: 6c5b ldr r3, [r3, #68] @ 0x44 + 8001e94: f003 021c and.w r2, r3, #28 + 8001e98: 687b ldr r3, [r7, #4] + 8001e9a: 6c1b ldr r3, [r3, #64] @ 0x40 + 8001e9c: 2101 movs r1, #1 + 8001e9e: fa01 f202 lsl.w r2, r1, r2 + 8001ea2: 605a str r2, [r3, #4] + + /* Clear the DMAMUX synchro overrun flag */ + hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; + 8001ea4: 687b ldr r3, [r7, #4] + 8001ea6: 6cdb ldr r3, [r3, #76] @ 0x4c + 8001ea8: 687a ldr r2, [r7, #4] + 8001eaa: 6d12 ldr r2, [r2, #80] @ 0x50 + 8001eac: 605a str r2, [r3, #4] + + if (hdma->DMAmuxRequestGen != NULL) + 8001eae: 687b ldr r3, [r7, #4] + 8001eb0: 6d5b ldr r3, [r3, #84] @ 0x54 + 8001eb2: 2b00 cmp r3, #0 + 8001eb4: d00c beq.n 8001ed0 + { + /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/ + /* disable the request gen overrun IT*/ + hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE; + 8001eb6: 687b ldr r3, [r7, #4] + 8001eb8: 6d5b ldr r3, [r3, #84] @ 0x54 + 8001eba: 681a ldr r2, [r3, #0] + 8001ebc: 687b ldr r3, [r7, #4] + 8001ebe: 6d5b ldr r3, [r3, #84] @ 0x54 + 8001ec0: f422 7280 bic.w r2, r2, #256 @ 0x100 + 8001ec4: 601a str r2, [r3, #0] + + /* Clear the DMAMUX request generator overrun flag */ + hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; + 8001ec6: 687b ldr r3, [r7, #4] + 8001ec8: 6d9b ldr r3, [r3, #88] @ 0x58 + 8001eca: 687a ldr r2, [r7, #4] + 8001ecc: 6dd2 ldr r2, [r2, #92] @ 0x5c + 8001ece: 605a str r2, [r3, #4] + } + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + 8001ed0: 687b ldr r3, [r7, #4] + 8001ed2: 2201 movs r2, #1 + 8001ed4: f883 2025 strb.w r2, [r3, #37] @ 0x25 + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + 8001ed8: 687b ldr r3, [r7, #4] + 8001eda: 2200 movs r2, #0 + 8001edc: f883 2024 strb.w r2, [r3, #36] @ 0x24 + } + + return HAL_OK; + 8001ee0: 2300 movs r3, #0 +} + 8001ee2: 4618 mov r0, r3 + 8001ee4: 370c adds r7, #12 + 8001ee6: 46bd mov sp, r7 + 8001ee8: bc80 pop {r7} + 8001eea: 4770 bx lr + +08001eec : + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) +{ + 8001eec: b580 push {r7, lr} + 8001eee: b084 sub sp, #16 + 8001ef0: af00 add r7, sp, #0 + 8001ef2: 6078 str r0, [r7, #4] + HAL_StatusTypeDef status = HAL_OK; + 8001ef4: 2300 movs r3, #0 + 8001ef6: 73fb strb r3, [r7, #15] + + if (hdma->State != HAL_DMA_STATE_BUSY) + 8001ef8: 687b ldr r3, [r7, #4] + 8001efa: f893 3025 ldrb.w r3, [r3, #37] @ 0x25 + 8001efe: b2db uxtb r3, r3 + 8001f00: 2b02 cmp r3, #2 + 8001f02: d005 beq.n 8001f10 + { + /* no transfer ongoing */ + hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + 8001f04: 687b ldr r3, [r7, #4] + 8001f06: 2204 movs r2, #4 + 8001f08: 63da str r2, [r3, #60] @ 0x3c + + status = HAL_ERROR; + 8001f0a: 2301 movs r3, #1 + 8001f0c: 73fb strb r3, [r7, #15] + 8001f0e: e047 b.n 8001fa0 + } + else + { + /* Disable the channel */ + __HAL_DMA_DISABLE(hdma); + 8001f10: 687b ldr r3, [r7, #4] + 8001f12: 681b ldr r3, [r3, #0] + 8001f14: 681a ldr r2, [r3, #0] + 8001f16: 687b ldr r3, [r7, #4] + 8001f18: 681b ldr r3, [r3, #0] + 8001f1a: f022 0201 bic.w r2, r2, #1 + 8001f1e: 601a str r2, [r3, #0] + + /* Disable DMA IT */ + __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); + 8001f20: 687b ldr r3, [r7, #4] + 8001f22: 681b ldr r3, [r3, #0] + 8001f24: 681a ldr r2, [r3, #0] + 8001f26: 687b ldr r3, [r7, #4] + 8001f28: 681b ldr r3, [r3, #0] + 8001f2a: f022 020e bic.w r2, r2, #14 + 8001f2e: 601a str r2, [r3, #0] + + /* disable the DMAMUX sync overrun IT*/ + hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; + 8001f30: 687b ldr r3, [r7, #4] + 8001f32: 6c9b ldr r3, [r3, #72] @ 0x48 + 8001f34: 681a ldr r2, [r3, #0] + 8001f36: 687b ldr r3, [r7, #4] + 8001f38: 6c9b ldr r3, [r3, #72] @ 0x48 + 8001f3a: f422 7280 bic.w r2, r2, #256 @ 0x100 + 8001f3e: 601a str r2, [r3, #0] + + /* Clear all flags */ + hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU)); + 8001f40: 687b ldr r3, [r7, #4] + 8001f42: 6c5b ldr r3, [r3, #68] @ 0x44 + 8001f44: f003 021c and.w r2, r3, #28 + 8001f48: 687b ldr r3, [r7, #4] + 8001f4a: 6c1b ldr r3, [r3, #64] @ 0x40 + 8001f4c: 2101 movs r1, #1 + 8001f4e: fa01 f202 lsl.w r2, r1, r2 + 8001f52: 605a str r2, [r3, #4] + + /* Clear the DMAMUX synchro overrun flag */ + hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; + 8001f54: 687b ldr r3, [r7, #4] + 8001f56: 6cdb ldr r3, [r3, #76] @ 0x4c + 8001f58: 687a ldr r2, [r7, #4] + 8001f5a: 6d12 ldr r2, [r2, #80] @ 0x50 + 8001f5c: 605a str r2, [r3, #4] + + if (hdma->DMAmuxRequestGen != NULL) + 8001f5e: 687b ldr r3, [r7, #4] + 8001f60: 6d5b ldr r3, [r3, #84] @ 0x54 + 8001f62: 2b00 cmp r3, #0 + 8001f64: d00c beq.n 8001f80 + { + /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/ + /* disable the request gen overrun IT*/ + hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE; + 8001f66: 687b ldr r3, [r7, #4] + 8001f68: 6d5b ldr r3, [r3, #84] @ 0x54 + 8001f6a: 681a ldr r2, [r3, #0] + 8001f6c: 687b ldr r3, [r7, #4] + 8001f6e: 6d5b ldr r3, [r3, #84] @ 0x54 + 8001f70: f422 7280 bic.w r2, r2, #256 @ 0x100 + 8001f74: 601a str r2, [r3, #0] + + /* Clear the DMAMUX request generator overrun flag */ + hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; + 8001f76: 687b ldr r3, [r7, #4] + 8001f78: 6d9b ldr r3, [r3, #88] @ 0x58 + 8001f7a: 687a ldr r2, [r7, #4] + 8001f7c: 6dd2 ldr r2, [r2, #92] @ 0x5c + 8001f7e: 605a str r2, [r3, #4] + } + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + 8001f80: 687b ldr r3, [r7, #4] + 8001f82: 2201 movs r2, #1 + 8001f84: f883 2025 strb.w r2, [r3, #37] @ 0x25 + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + 8001f88: 687b ldr r3, [r7, #4] + 8001f8a: 2200 movs r2, #0 + 8001f8c: f883 2024 strb.w r2, [r3, #36] @ 0x24 + + /* Call User Abort callback */ + if (hdma->XferAbortCallback != NULL) + 8001f90: 687b ldr r3, [r7, #4] + 8001f92: 6b9b ldr r3, [r3, #56] @ 0x38 + 8001f94: 2b00 cmp r3, #0 + 8001f96: d003 beq.n 8001fa0 + { + hdma->XferAbortCallback(hdma); + 8001f98: 687b ldr r3, [r7, #4] + 8001f9a: 6b9b ldr r3, [r3, #56] @ 0x38 + 8001f9c: 6878 ldr r0, [r7, #4] + 8001f9e: 4798 blx r3 + } + } + return status; + 8001fa0: 7bfb ldrb r3, [r7, #15] +} + 8001fa2: 4618 mov r0, r3 + 8001fa4: 3710 adds r7, #16 + 8001fa6: 46bd mov sp, r7 + 8001fa8: bd80 pop {r7, pc} + ... + +08001fac : + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @retval None + */ +void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) +{ + 8001fac: b580 push {r7, lr} + 8001fae: b084 sub sp, #16 + 8001fb0: af00 add r7, sp, #0 + 8001fb2: 6078 str r0, [r7, #4] + uint32_t flag_it = hdma->DmaBaseAddress->ISR; + 8001fb4: 687b ldr r3, [r7, #4] + 8001fb6: 6c1b ldr r3, [r3, #64] @ 0x40 + 8001fb8: 681b ldr r3, [r3, #0] + 8001fba: 60fb str r3, [r7, #12] + uint32_t source_it = hdma->Instance->CCR; + 8001fbc: 687b ldr r3, [r7, #4] + 8001fbe: 681b ldr r3, [r3, #0] + 8001fc0: 681b ldr r3, [r3, #0] + 8001fc2: 60bb str r3, [r7, #8] + + /* Half Transfer Complete Interrupt management ******************************/ + if (((flag_it & (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1CU))) != 0U) && ((source_it & DMA_IT_HT) != 0U)) + 8001fc4: 687b ldr r3, [r7, #4] + 8001fc6: 6c5b ldr r3, [r3, #68] @ 0x44 + 8001fc8: f003 031c and.w r3, r3, #28 + 8001fcc: 2204 movs r2, #4 + 8001fce: 409a lsls r2, r3 + 8001fd0: 68fb ldr r3, [r7, #12] + 8001fd2: 4013 ands r3, r2 + 8001fd4: 2b00 cmp r3, #0 + 8001fd6: d027 beq.n 8002028 + 8001fd8: 68bb ldr r3, [r7, #8] + 8001fda: f003 0304 and.w r3, r3, #4 + 8001fde: 2b00 cmp r3, #0 + 8001fe0: d022 beq.n 8002028 + { + /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */ + if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) + 8001fe2: 687b ldr r3, [r7, #4] + 8001fe4: 681b ldr r3, [r3, #0] + 8001fe6: 681b ldr r3, [r3, #0] + 8001fe8: f003 0320 and.w r3, r3, #32 + 8001fec: 2b00 cmp r3, #0 + 8001fee: d107 bne.n 8002000 + { + /* Disable the half transfer interrupt */ + __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); + 8001ff0: 687b ldr r3, [r7, #4] + 8001ff2: 681b ldr r3, [r3, #0] + 8001ff4: 681a ldr r2, [r3, #0] + 8001ff6: 687b ldr r3, [r7, #4] + 8001ff8: 681b ldr r3, [r3, #0] + 8001ffa: f022 0204 bic.w r2, r2, #4 + 8001ffe: 601a str r2, [r3, #0] + } + /* Clear the half transfer complete flag */ + hdma->DmaBaseAddress->IFCR = DMA_ISR_HTIF1 << (hdma->ChannelIndex & 0x1CU); + 8002000: 687b ldr r3, [r7, #4] + 8002002: 6c5b ldr r3, [r3, #68] @ 0x44 + 8002004: f003 021c and.w r2, r3, #28 + 8002008: 687b ldr r3, [r7, #4] + 800200a: 6c1b ldr r3, [r3, #64] @ 0x40 + 800200c: 2104 movs r1, #4 + 800200e: fa01 f202 lsl.w r2, r1, r2 + 8002012: 605a str r2, [r3, #4] + + /* DMA peripheral state is not updated in Half Transfer */ + /* but in Transfer Complete case */ + + if (hdma->XferHalfCpltCallback != NULL) + 8002014: 687b ldr r3, [r7, #4] + 8002016: 6b1b ldr r3, [r3, #48] @ 0x30 + 8002018: 2b00 cmp r3, #0 + 800201a: f000 8081 beq.w 8002120 + { + /* Half transfer callback */ + hdma->XferHalfCpltCallback(hdma); + 800201e: 687b ldr r3, [r7, #4] + 8002020: 6b1b ldr r3, [r3, #48] @ 0x30 + 8002022: 6878 ldr r0, [r7, #4] + 8002024: 4798 blx r3 + if (hdma->XferHalfCpltCallback != NULL) + 8002026: e07b b.n 8002120 + } + } + + /* Transfer Complete Interrupt management ***********************************/ + else if ((0U != (flag_it & (DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1CU)))) && (0U != (source_it & DMA_IT_TC))) + 8002028: 687b ldr r3, [r7, #4] + 800202a: 6c5b ldr r3, [r3, #68] @ 0x44 + 800202c: f003 031c and.w r3, r3, #28 + 8002030: 2202 movs r2, #2 + 8002032: 409a lsls r2, r3 + 8002034: 68fb ldr r3, [r7, #12] + 8002036: 4013 ands r3, r2 + 8002038: 2b00 cmp r3, #0 + 800203a: d03d beq.n 80020b8 + 800203c: 68bb ldr r3, [r7, #8] + 800203e: f003 0302 and.w r3, r3, #2 + 8002042: 2b00 cmp r3, #0 + 8002044: d038 beq.n 80020b8 + { + if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) + 8002046: 687b ldr r3, [r7, #4] + 8002048: 681b ldr r3, [r3, #0] + 800204a: 681b ldr r3, [r3, #0] + 800204c: f003 0320 and.w r3, r3, #32 + 8002050: 2b00 cmp r3, #0 + 8002052: d10b bne.n 800206c + { + /* Disable the transfer complete and error interrupt */ + __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC); + 8002054: 687b ldr r3, [r7, #4] + 8002056: 681b ldr r3, [r3, #0] + 8002058: 681a ldr r2, [r3, #0] + 800205a: 687b ldr r3, [r7, #4] + 800205c: 681b ldr r3, [r3, #0] + 800205e: f022 020a bic.w r2, r2, #10 + 8002062: 601a str r2, [r3, #0] + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + 8002064: 687b ldr r3, [r7, #4] + 8002066: 2201 movs r2, #1 + 8002068: f883 2025 strb.w r2, [r3, #37] @ 0x25 + } + /* Clear the transfer complete flag */ + __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1CU))); + 800206c: 687b ldr r3, [r7, #4] + 800206e: 681b ldr r3, [r3, #0] + 8002070: 461a mov r2, r3 + 8002072: 4b2e ldr r3, [pc, #184] @ (800212c ) + 8002074: 429a cmp r2, r3 + 8002076: d909 bls.n 800208c + 8002078: 687b ldr r3, [r7, #4] + 800207a: 6c5b ldr r3, [r3, #68] @ 0x44 + 800207c: f003 031c and.w r3, r3, #28 + 8002080: 4a2b ldr r2, [pc, #172] @ (8002130 ) + 8002082: 2102 movs r1, #2 + 8002084: fa01 f303 lsl.w r3, r1, r3 + 8002088: 6053 str r3, [r2, #4] + 800208a: e008 b.n 800209e + 800208c: 687b ldr r3, [r7, #4] + 800208e: 6c5b ldr r3, [r3, #68] @ 0x44 + 8002090: f003 031c and.w r3, r3, #28 + 8002094: 4a27 ldr r2, [pc, #156] @ (8002134 ) + 8002096: 2102 movs r1, #2 + 8002098: fa01 f303 lsl.w r3, r1, r3 + 800209c: 6053 str r3, [r2, #4] + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + 800209e: 687b ldr r3, [r7, #4] + 80020a0: 2200 movs r2, #0 + 80020a2: f883 2024 strb.w r2, [r3, #36] @ 0x24 + + if (hdma->XferCpltCallback != NULL) + 80020a6: 687b ldr r3, [r7, #4] + 80020a8: 6adb ldr r3, [r3, #44] @ 0x2c + 80020aa: 2b00 cmp r3, #0 + 80020ac: d038 beq.n 8002120 + { + /* Transfer complete callback */ + hdma->XferCpltCallback(hdma); + 80020ae: 687b ldr r3, [r7, #4] + 80020b0: 6adb ldr r3, [r3, #44] @ 0x2c + 80020b2: 6878 ldr r0, [r7, #4] + 80020b4: 4798 blx r3 + if (hdma->XferCpltCallback != NULL) + 80020b6: e033 b.n 8002120 + } + } + + /* Transfer Error Interrupt management **************************************/ + else if (((flag_it & (DMA_FLAG_TE1 << (hdma->ChannelIndex & 0x1CU))) != 0U) && ((source_it & DMA_IT_TE) != 0U)) + 80020b8: 687b ldr r3, [r7, #4] + 80020ba: 6c5b ldr r3, [r3, #68] @ 0x44 + 80020bc: f003 031c and.w r3, r3, #28 + 80020c0: 2208 movs r2, #8 + 80020c2: 409a lsls r2, r3 + 80020c4: 68fb ldr r3, [r7, #12] + 80020c6: 4013 ands r3, r2 + 80020c8: 2b00 cmp r3, #0 + 80020ca: d02a beq.n 8002122 + 80020cc: 68bb ldr r3, [r7, #8] + 80020ce: f003 0308 and.w r3, r3, #8 + 80020d2: 2b00 cmp r3, #0 + 80020d4: d025 beq.n 8002122 + { + /* When a DMA transfer error occurs */ + /* A hardware clear of its EN bits is performed */ + /* Disable ALL DMA IT */ + __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); + 80020d6: 687b ldr r3, [r7, #4] + 80020d8: 681b ldr r3, [r3, #0] + 80020da: 681a ldr r2, [r3, #0] + 80020dc: 687b ldr r3, [r7, #4] + 80020de: 681b ldr r3, [r3, #0] + 80020e0: f022 020e bic.w r2, r2, #14 + 80020e4: 601a str r2, [r3, #0] + + /* Clear all flags */ + hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU)); + 80020e6: 687b ldr r3, [r7, #4] + 80020e8: 6c5b ldr r3, [r3, #68] @ 0x44 + 80020ea: f003 021c and.w r2, r3, #28 + 80020ee: 687b ldr r3, [r7, #4] + 80020f0: 6c1b ldr r3, [r3, #64] @ 0x40 + 80020f2: 2101 movs r1, #1 + 80020f4: fa01 f202 lsl.w r2, r1, r2 + 80020f8: 605a str r2, [r3, #4] + + /* Update error code */ + hdma->ErrorCode = HAL_DMA_ERROR_TE; + 80020fa: 687b ldr r3, [r7, #4] + 80020fc: 2201 movs r2, #1 + 80020fe: 63da str r2, [r3, #60] @ 0x3c + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + 8002100: 687b ldr r3, [r7, #4] + 8002102: 2201 movs r2, #1 + 8002104: f883 2025 strb.w r2, [r3, #37] @ 0x25 + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + 8002108: 687b ldr r3, [r7, #4] + 800210a: 2200 movs r2, #0 + 800210c: f883 2024 strb.w r2, [r3, #36] @ 0x24 + + if (hdma->XferErrorCallback != NULL) + 8002110: 687b ldr r3, [r7, #4] + 8002112: 6b5b ldr r3, [r3, #52] @ 0x34 + 8002114: 2b00 cmp r3, #0 + 8002116: d004 beq.n 8002122 + { + /* Transfer error callback */ + hdma->XferErrorCallback(hdma); + 8002118: 687b ldr r3, [r7, #4] + 800211a: 6b5b ldr r3, [r3, #52] @ 0x34 + 800211c: 6878 ldr r0, [r7, #4] + 800211e: 4798 blx r3 + } + else + { + /* Nothing To Do */ + } + return; + 8002120: bf00 nop + 8002122: bf00 nop +} + 8002124: 3710 adds r7, #16 + 8002126: 46bd mov sp, r7 + 8002128: bd80 pop {r7, pc} + 800212a: bf00 nop + 800212c: 40020080 .word 0x40020080 + 8002130: 40020400 .word 0x40020400 + 8002134: 40020000 .word 0x40020000 + +08002138 : + * @param ChannelAttributes specifies the DMA channel secure/privilege attributes. + * This parameter can be a one or a combination of @ref DMA_Channel_Attributes + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_DMA_ConfigChannelAttributes(DMA_HandleTypeDef *hdma, uint32_t ChannelAttributes) +{ + 8002138: b480 push {r7} + 800213a: b085 sub sp, #20 + 800213c: af00 add r7, sp, #0 + 800213e: 6078 str r0, [r7, #4] + 8002140: 6039 str r1, [r7, #0] + HAL_StatusTypeDef status = HAL_OK; + 8002142: 2300 movs r3, #0 + 8002144: 72fb strb r3, [r7, #11] +#if defined (CORE_CM0PLUS) + uint32_t ccr_SECM; +#endif /* CORE_CM0PLUS */ + + /* Check the DMA peripheral handle */ + if (hdma == NULL) + 8002146: 687b ldr r3, [r7, #4] + 8002148: 2b00 cmp r3, #0 + 800214a: d103 bne.n 8002154 + { + status = HAL_ERROR; + 800214c: 2301 movs r3, #1 + 800214e: 72fb strb r3, [r7, #11] + return status; + 8002150: 7afb ldrb r3, [r7, #11] + 8002152: e01b b.n 800218c + + /* Check the parameters */ + assert_param(IS_DMA_ATTRIBUTES(ChannelAttributes)); + + /* Read CCR register */ + ccr = READ_REG(hdma->Instance->CCR); + 8002154: 687b ldr r3, [r7, #4] + 8002156: 681b ldr r3, [r3, #0] + 8002158: 681b ldr r3, [r3, #0] + 800215a: 60fb str r3, [r7, #12] + + /* Apply any requested privilege/non-privilege attributes */ + if ((ChannelAttributes & DMA_CHANNEL_ATTR_PRIV_MASK) != 0U) + 800215c: 683b ldr r3, [r7, #0] + 800215e: f003 0310 and.w r3, r3, #16 + 8002162: 2b00 cmp r3, #0 + 8002164: d00d beq.n 8002182 + { + if ((ChannelAttributes & DMA_CCR_PRIV) != 0U) + 8002166: 683b ldr r3, [r7, #0] + 8002168: f403 1380 and.w r3, r3, #1048576 @ 0x100000 + 800216c: 2b00 cmp r3, #0 + 800216e: d004 beq.n 800217a + { + SET_BIT(ccr, DMA_CCR_PRIV); + 8002170: 68fb ldr r3, [r7, #12] + 8002172: f443 1380 orr.w r3, r3, #1048576 @ 0x100000 + 8002176: 60fb str r3, [r7, #12] + 8002178: e003 b.n 8002182 + } + else + { + CLEAR_BIT(ccr, DMA_CCR_PRIV); + 800217a: 68fb ldr r3, [r7, #12] + 800217c: f423 1380 bic.w r3, r3, #1048576 @ 0x100000 + 8002180: 60fb str r3, [r7, #12] + } + +#endif /* CORE_CM0PLUS */ + + /* Update CCR Register: PRIV, SECM, SCEC, DSEC bits */ + WRITE_REG(hdma->Instance->CCR, ccr); + 8002182: 687b ldr r3, [r7, #4] + 8002184: 681b ldr r3, [r3, #0] + 8002186: 68fa ldr r2, [r7, #12] + 8002188: 601a str r2, [r3, #0] + + return status; + 800218a: 7afb ldrb r3, [r7, #11] +} + 800218c: 4618 mov r0, r3 + 800218e: 3714 adds r7, #20 + 8002190: 46bd mov sp, r7 + 8002192: bc80 pop {r7} + 8002194: 4770 bx lr + +08002196 : + * @param DstAddress The destination memory Buffer address + * @param DataLength The length of data to be transferred from source to destination + * @retval HAL status + */ +static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) +{ + 8002196: b480 push {r7} + 8002198: b085 sub sp, #20 + 800219a: af00 add r7, sp, #0 + 800219c: 60f8 str r0, [r7, #12] + 800219e: 60b9 str r1, [r7, #8] + 80021a0: 607a str r2, [r7, #4] + 80021a2: 603b str r3, [r7, #0] + /* Clear the DMAMUX synchro overrun flag */ + hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; + 80021a4: 68fb ldr r3, [r7, #12] + 80021a6: 6cdb ldr r3, [r3, #76] @ 0x4c + 80021a8: 68fa ldr r2, [r7, #12] + 80021aa: 6d12 ldr r2, [r2, #80] @ 0x50 + 80021ac: 605a str r2, [r3, #4] + + if (hdma->DMAmuxRequestGen != NULL) + 80021ae: 68fb ldr r3, [r7, #12] + 80021b0: 6d5b ldr r3, [r3, #84] @ 0x54 + 80021b2: 2b00 cmp r3, #0 + 80021b4: d004 beq.n 80021c0 + { + /* Clear the DMAMUX request generator overrun flag */ + hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; + 80021b6: 68fb ldr r3, [r7, #12] + 80021b8: 6d9b ldr r3, [r3, #88] @ 0x58 + 80021ba: 68fa ldr r2, [r7, #12] + 80021bc: 6dd2 ldr r2, [r2, #92] @ 0x5c + 80021be: 605a str r2, [r3, #4] + } + + /* Clear all flags */ + hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU)); + 80021c0: 68fb ldr r3, [r7, #12] + 80021c2: 6c5b ldr r3, [r3, #68] @ 0x44 + 80021c4: f003 021c and.w r2, r3, #28 + 80021c8: 68fb ldr r3, [r7, #12] + 80021ca: 6c1b ldr r3, [r3, #64] @ 0x40 + 80021cc: 2101 movs r1, #1 + 80021ce: fa01 f202 lsl.w r2, r1, r2 + 80021d2: 605a str r2, [r3, #4] + + /* Configure DMA Channel data length */ + hdma->Instance->CNDTR = DataLength; + 80021d4: 68fb ldr r3, [r7, #12] + 80021d6: 681b ldr r3, [r3, #0] + 80021d8: 683a ldr r2, [r7, #0] + 80021da: 605a str r2, [r3, #4] + + /* Memory to Peripheral */ + if ((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) + 80021dc: 68fb ldr r3, [r7, #12] + 80021de: 689b ldr r3, [r3, #8] + 80021e0: 2b10 cmp r3, #16 + 80021e2: d108 bne.n 80021f6 + { + /* Configure DMA Channel destination address */ + hdma->Instance->CPAR = DstAddress; + 80021e4: 68fb ldr r3, [r7, #12] + 80021e6: 681b ldr r3, [r3, #0] + 80021e8: 687a ldr r2, [r7, #4] + 80021ea: 609a str r2, [r3, #8] + + /* Configure DMA Channel source address */ + hdma->Instance->CMAR = SrcAddress; + 80021ec: 68fb ldr r3, [r7, #12] + 80021ee: 681b ldr r3, [r3, #0] + 80021f0: 68ba ldr r2, [r7, #8] + 80021f2: 60da str r2, [r3, #12] + hdma->Instance->CPAR = SrcAddress; + + /* Configure DMA Channel destination address */ + hdma->Instance->CMAR = DstAddress; + } +} + 80021f4: e007 b.n 8002206 + hdma->Instance->CPAR = SrcAddress; + 80021f6: 68fb ldr r3, [r7, #12] + 80021f8: 681b ldr r3, [r3, #0] + 80021fa: 68ba ldr r2, [r7, #8] + 80021fc: 609a str r2, [r3, #8] + hdma->Instance->CMAR = DstAddress; + 80021fe: 68fb ldr r3, [r7, #12] + 8002200: 681b ldr r3, [r3, #0] + 8002202: 687a ldr r2, [r7, #4] + 8002204: 60da str r2, [r3, #12] +} + 8002206: bf00 nop + 8002208: 3714 adds r7, #20 + 800220a: 46bd mov sp, r7 + 800220c: bc80 pop {r7} + 800220e: 4770 bx lr + +08002210 : + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @retval None + */ +static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma) +{ + 8002210: b480 push {r7} + 8002212: b085 sub sp, #20 + 8002214: af00 add r7, sp, #0 + 8002216: 6078 str r0, [r7, #4] + uint32_t channel_number; + + /* check if instance is not outside the DMA channel range */ + if ((uint32_t)hdma->Instance < (uint32_t)DMA2_Channel1) + 8002218: 687b ldr r3, [r7, #4] + 800221a: 681b ldr r3, [r3, #0] + 800221c: 461a mov r2, r3 + 800221e: 4b1c ldr r3, [pc, #112] @ (8002290 ) + 8002220: 429a cmp r2, r3 + 8002222: d813 bhi.n 800224c + { + /* DMA1 */ + /* Associate a DMA Channel to a DMAMUX channel */ + hdma->DMAmuxChannel = (DMAMUX1_Channel0 + (hdma->ChannelIndex >> 2U)); + 8002224: 687b ldr r3, [r7, #4] + 8002226: 6c5b ldr r3, [r3, #68] @ 0x44 + 8002228: 089b lsrs r3, r3, #2 + 800222a: 009b lsls r3, r3, #2 + 800222c: f103 4380 add.w r3, r3, #1073741824 @ 0x40000000 + 8002230: f503 3302 add.w r3, r3, #133120 @ 0x20800 + 8002234: 687a ldr r2, [r7, #4] + 8002236: 6493 str r3, [r2, #72] @ 0x48 + + /* Prepare channel_number used for DMAmuxChannelStatusMask computation */ + channel_number = (((uint32_t)hdma->Instance & 0xFFU) - 8U) / 20U; + 8002238: 687b ldr r3, [r7, #4] + 800223a: 681b ldr r3, [r3, #0] + 800223c: b2db uxtb r3, r3 + 800223e: 3b08 subs r3, #8 + 8002240: 4a14 ldr r2, [pc, #80] @ (8002294 ) + 8002242: fba2 2303 umull r2, r3, r2, r3 + 8002246: 091b lsrs r3, r3, #4 + 8002248: 60fb str r3, [r7, #12] + 800224a: e011 b.n 8002270 + } + else + { + /* DMA2 */ + /* Associate a DMA Channel to a DMAMUX channel */ + hdma->DMAmuxChannel = (DMAMUX1_Channel7 + (hdma->ChannelIndex >> 2U)); + 800224c: 687b ldr r3, [r7, #4] + 800224e: 6c5b ldr r3, [r3, #68] @ 0x44 + 8002250: 089b lsrs r3, r3, #2 + 8002252: 009a lsls r2, r3, #2 + 8002254: 4b10 ldr r3, [pc, #64] @ (8002298 ) + 8002256: 4413 add r3, r2 + 8002258: 687a ldr r2, [r7, #4] + 800225a: 6493 str r3, [r2, #72] @ 0x48 + + /* Prepare channel_number used for DMAmuxChannelStatusMask computation */ + channel_number = (((((uint32_t)hdma->Instance & 0xFFU) - 8U) / 20U) + 7U); + 800225c: 687b ldr r3, [r7, #4] + 800225e: 681b ldr r3, [r3, #0] + 8002260: b2db uxtb r3, r3 + 8002262: 3b08 subs r3, #8 + 8002264: 4a0b ldr r2, [pc, #44] @ (8002294 ) + 8002266: fba2 2303 umull r2, r3, r2, r3 + 800226a: 091b lsrs r3, r3, #4 + 800226c: 3307 adds r3, #7 + 800226e: 60fb str r3, [r7, #12] + } + + /* Initialize the field DMAmuxChannelStatus to DMAMUX1_ChannelStatus base */ + hdma->DMAmuxChannelStatus = DMAMUX1_ChannelStatus; + 8002270: 687b ldr r3, [r7, #4] + 8002272: 4a0a ldr r2, [pc, #40] @ (800229c ) + 8002274: 64da str r2, [r3, #76] @ 0x4c + + /* Initialize the field DMAmuxChannelStatusMask with the corresponding index of the DMAMUX channel selected for the current ChannelIndex */ + hdma->DMAmuxChannelStatusMask = 1UL << (channel_number & 0x1FU); + 8002276: 68fb ldr r3, [r7, #12] + 8002278: f003 031f and.w r3, r3, #31 + 800227c: 2201 movs r2, #1 + 800227e: 409a lsls r2, r3 + 8002280: 687b ldr r3, [r7, #4] + 8002282: 651a str r2, [r3, #80] @ 0x50 +} + 8002284: bf00 nop + 8002286: 3714 adds r7, #20 + 8002288: 46bd mov sp, r7 + 800228a: bc80 pop {r7} + 800228c: 4770 bx lr + 800228e: bf00 nop + 8002290: 40020407 .word 0x40020407 + 8002294: cccccccd .word 0xcccccccd + 8002298: 4002081c .word 0x4002081c + 800229c: 40020880 .word 0x40020880 + +080022a0 : + * the configuration information for the specified DMA Channel. + * @retval None + */ + +static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma) +{ + 80022a0: b480 push {r7} + 80022a2: b085 sub sp, #20 + 80022a4: af00 add r7, sp, #0 + 80022a6: 6078 str r0, [r7, #4] + uint32_t request = hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID; + 80022a8: 687b ldr r3, [r7, #4] + 80022aa: 685b ldr r3, [r3, #4] + 80022ac: f003 037f and.w r3, r3, #127 @ 0x7f + 80022b0: 60fb str r3, [r7, #12] + + /* DMA Channels are connected to DMAMUX1 request generator blocks*/ + hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_RequestGenerator0) + ((request - 1U) * 4U))); + 80022b2: 68fa ldr r2, [r7, #12] + 80022b4: 4b0a ldr r3, [pc, #40] @ (80022e0 ) + 80022b6: 4413 add r3, r2 + 80022b8: 009b lsls r3, r3, #2 + 80022ba: 461a mov r2, r3 + 80022bc: 687b ldr r3, [r7, #4] + 80022be: 655a str r2, [r3, #84] @ 0x54 + + hdma->DMAmuxRequestGenStatus = DMAMUX1_RequestGenStatus; + 80022c0: 687b ldr r3, [r7, #4] + 80022c2: 4a08 ldr r2, [pc, #32] @ (80022e4 ) + 80022c4: 659a str r2, [r3, #88] @ 0x58 + + /* here "Request" is either DMA_REQUEST_GENERATOR0 to DMA_REQUEST_GENERATOR3, i.e. <= 4*/ + hdma->DMAmuxRequestGenStatusMask = 1UL << ((request - 1U) & 0x3U); + 80022c6: 68fb ldr r3, [r7, #12] + 80022c8: 3b01 subs r3, #1 + 80022ca: f003 0303 and.w r3, r3, #3 + 80022ce: 2201 movs r2, #1 + 80022d0: 409a lsls r2, r3 + 80022d2: 687b ldr r3, [r7, #4] + 80022d4: 65da str r2, [r3, #92] @ 0x5c +} + 80022d6: bf00 nop + 80022d8: 3714 adds r7, #20 + 80022da: 46bd mov sp, r7 + 80022dc: bc80 pop {r7} + 80022de: 4770 bx lr + 80022e0: 1000823f .word 0x1000823f + 80022e4: 40020940 .word 0x40020940 + +080022e8 : + * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains + * the configuration information for the specified GPIO peripheral. + * @retval None + */ +void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, const GPIO_InitTypeDef *GPIO_Init) +{ + 80022e8: b480 push {r7} + 80022ea: b087 sub sp, #28 + 80022ec: af00 add r7, sp, #0 + 80022ee: 6078 str r0, [r7, #4] + 80022f0: 6039 str r1, [r7, #0] + uint32_t position = 0x00u; + 80022f2: 2300 movs r3, #0 + 80022f4: 617b str r3, [r7, #20] + assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); + assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); + assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); + + /* Configure the port pins */ + while (((GPIO_Init->Pin) >> position) != 0x00u) + 80022f6: e140 b.n 800257a + { + /* Get current io position */ + iocurrent = (GPIO_Init->Pin) & (1uL << position); + 80022f8: 683b ldr r3, [r7, #0] + 80022fa: 681a ldr r2, [r3, #0] + 80022fc: 2101 movs r1, #1 + 80022fe: 697b ldr r3, [r7, #20] + 8002300: fa01 f303 lsl.w r3, r1, r3 + 8002304: 4013 ands r3, r2 + 8002306: 60fb str r3, [r7, #12] + + if (iocurrent != 0x00u) + 8002308: 68fb ldr r3, [r7, #12] + 800230a: 2b00 cmp r3, #0 + 800230c: f000 8132 beq.w 8002574 + { + /*--------------------- GPIO Mode Configuration ------------------------*/ + /* In case of Output or Alternate function mode selection */ + if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)) + 8002310: 683b ldr r3, [r7, #0] + 8002312: 685b ldr r3, [r3, #4] + 8002314: f003 0303 and.w r3, r3, #3 + 8002318: 2b01 cmp r3, #1 + 800231a: d005 beq.n 8002328 + 800231c: 683b ldr r3, [r7, #0] + 800231e: 685b ldr r3, [r3, #4] + 8002320: f003 0303 and.w r3, r3, #3 + 8002324: 2b02 cmp r3, #2 + 8002326: d130 bne.n 800238a + { + /* Check the Speed parameter */ + assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); + /* Configure the IO Speed */ + temp = GPIOx->OSPEEDR; + 8002328: 687b ldr r3, [r7, #4] + 800232a: 689b ldr r3, [r3, #8] + 800232c: 613b str r3, [r7, #16] + temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U)); + 800232e: 697b ldr r3, [r7, #20] + 8002330: 005b lsls r3, r3, #1 + 8002332: 2203 movs r2, #3 + 8002334: fa02 f303 lsl.w r3, r2, r3 + 8002338: 43db mvns r3, r3 + 800233a: 693a ldr r2, [r7, #16] + 800233c: 4013 ands r3, r2 + 800233e: 613b str r3, [r7, #16] + temp |= (GPIO_Init->Speed << (position * 2U)); + 8002340: 683b ldr r3, [r7, #0] + 8002342: 68da ldr r2, [r3, #12] + 8002344: 697b ldr r3, [r7, #20] + 8002346: 005b lsls r3, r3, #1 + 8002348: fa02 f303 lsl.w r3, r2, r3 + 800234c: 693a ldr r2, [r7, #16] + 800234e: 4313 orrs r3, r2 + 8002350: 613b str r3, [r7, #16] + GPIOx->OSPEEDR = temp; + 8002352: 687b ldr r3, [r7, #4] + 8002354: 693a ldr r2, [r7, #16] + 8002356: 609a str r2, [r3, #8] + + /* Configure the IO Output Type */ + temp = GPIOx->OTYPER; + 8002358: 687b ldr r3, [r7, #4] + 800235a: 685b ldr r3, [r3, #4] + 800235c: 613b str r3, [r7, #16] + temp &= ~(GPIO_OTYPER_OT0 << position) ; + 800235e: 2201 movs r2, #1 + 8002360: 697b ldr r3, [r7, #20] + 8002362: fa02 f303 lsl.w r3, r2, r3 + 8002366: 43db mvns r3, r3 + 8002368: 693a ldr r2, [r7, #16] + 800236a: 4013 ands r3, r2 + 800236c: 613b str r3, [r7, #16] + temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position); + 800236e: 683b ldr r3, [r7, #0] + 8002370: 685b ldr r3, [r3, #4] + 8002372: 091b lsrs r3, r3, #4 + 8002374: f003 0201 and.w r2, r3, #1 + 8002378: 697b ldr r3, [r7, #20] + 800237a: fa02 f303 lsl.w r3, r2, r3 + 800237e: 693a ldr r2, [r7, #16] + 8002380: 4313 orrs r3, r2 + 8002382: 613b str r3, [r7, #16] + GPIOx->OTYPER = temp; + 8002384: 687b ldr r3, [r7, #4] + 8002386: 693a ldr r2, [r7, #16] + 8002388: 605a str r2, [r3, #4] + } + + /* Activate the Pull-up or Pull down resistor for the current IO */ + if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) + 800238a: 683b ldr r3, [r7, #0] + 800238c: 685b ldr r3, [r3, #4] + 800238e: f003 0303 and.w r3, r3, #3 + 8002392: 2b03 cmp r3, #3 + 8002394: d017 beq.n 80023c6 + { + temp = GPIOx->PUPDR; + 8002396: 687b ldr r3, [r7, #4] + 8002398: 68db ldr r3, [r3, #12] + 800239a: 613b str r3, [r7, #16] + temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U)); + 800239c: 697b ldr r3, [r7, #20] + 800239e: 005b lsls r3, r3, #1 + 80023a0: 2203 movs r2, #3 + 80023a2: fa02 f303 lsl.w r3, r2, r3 + 80023a6: 43db mvns r3, r3 + 80023a8: 693a ldr r2, [r7, #16] + 80023aa: 4013 ands r3, r2 + 80023ac: 613b str r3, [r7, #16] + temp |= ((GPIO_Init->Pull) << (position * 2U)); + 80023ae: 683b ldr r3, [r7, #0] + 80023b0: 689a ldr r2, [r3, #8] + 80023b2: 697b ldr r3, [r7, #20] + 80023b4: 005b lsls r3, r3, #1 + 80023b6: fa02 f303 lsl.w r3, r2, r3 + 80023ba: 693a ldr r2, [r7, #16] + 80023bc: 4313 orrs r3, r2 + 80023be: 613b str r3, [r7, #16] + GPIOx->PUPDR = temp; + 80023c0: 687b ldr r3, [r7, #4] + 80023c2: 693a ldr r2, [r7, #16] + 80023c4: 60da str r2, [r3, #12] + } + + /* In case of Alternate function mode selection */ + if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF) + 80023c6: 683b ldr r3, [r7, #0] + 80023c8: 685b ldr r3, [r3, #4] + 80023ca: f003 0303 and.w r3, r3, #3 + 80023ce: 2b02 cmp r3, #2 + 80023d0: d123 bne.n 800241a + /* Check the Alternate function parameters */ + assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); + assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); + + /* Configure Alternate function mapped with the current IO */ + temp = GPIOx->AFR[position >> 3U]; + 80023d2: 697b ldr r3, [r7, #20] + 80023d4: 08da lsrs r2, r3, #3 + 80023d6: 687b ldr r3, [r7, #4] + 80023d8: 3208 adds r2, #8 + 80023da: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 80023de: 613b str r3, [r7, #16] + temp &= ~(0xFU << ((position & 0x07U) * 4U)); + 80023e0: 697b ldr r3, [r7, #20] + 80023e2: f003 0307 and.w r3, r3, #7 + 80023e6: 009b lsls r3, r3, #2 + 80023e8: 220f movs r2, #15 + 80023ea: fa02 f303 lsl.w r3, r2, r3 + 80023ee: 43db mvns r3, r3 + 80023f0: 693a ldr r2, [r7, #16] + 80023f2: 4013 ands r3, r2 + 80023f4: 613b str r3, [r7, #16] + temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * 4U)); + 80023f6: 683b ldr r3, [r7, #0] + 80023f8: 691a ldr r2, [r3, #16] + 80023fa: 697b ldr r3, [r7, #20] + 80023fc: f003 0307 and.w r3, r3, #7 + 8002400: 009b lsls r3, r3, #2 + 8002402: fa02 f303 lsl.w r3, r2, r3 + 8002406: 693a ldr r2, [r7, #16] + 8002408: 4313 orrs r3, r2 + 800240a: 613b str r3, [r7, #16] + GPIOx->AFR[position >> 3u] = temp; + 800240c: 697b ldr r3, [r7, #20] + 800240e: 08da lsrs r2, r3, #3 + 8002410: 687b ldr r3, [r7, #4] + 8002412: 3208 adds r2, #8 + 8002414: 6939 ldr r1, [r7, #16] + 8002416: f843 1022 str.w r1, [r3, r2, lsl #2] + } + + /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ + temp = GPIOx->MODER; + 800241a: 687b ldr r3, [r7, #4] + 800241c: 681b ldr r3, [r3, #0] + 800241e: 613b str r3, [r7, #16] + temp &= ~(GPIO_MODER_MODE0 << (position * 2U)); + 8002420: 697b ldr r3, [r7, #20] + 8002422: 005b lsls r3, r3, #1 + 8002424: 2203 movs r2, #3 + 8002426: fa02 f303 lsl.w r3, r2, r3 + 800242a: 43db mvns r3, r3 + 800242c: 693a ldr r2, [r7, #16] + 800242e: 4013 ands r3, r2 + 8002430: 613b str r3, [r7, #16] + temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U)); + 8002432: 683b ldr r3, [r7, #0] + 8002434: 685b ldr r3, [r3, #4] + 8002436: f003 0203 and.w r2, r3, #3 + 800243a: 697b ldr r3, [r7, #20] + 800243c: 005b lsls r3, r3, #1 + 800243e: fa02 f303 lsl.w r3, r2, r3 + 8002442: 693a ldr r2, [r7, #16] + 8002444: 4313 orrs r3, r2 + 8002446: 613b str r3, [r7, #16] + GPIOx->MODER = temp; + 8002448: 687b ldr r3, [r7, #4] + 800244a: 693a ldr r2, [r7, #16] + 800244c: 601a str r2, [r3, #0] + + /*--------------------- EXTI Mode Configuration ------------------------*/ + /* Configure the External Interrupt or event for the current IO */ + if ((GPIO_Init->Mode & EXTI_MODE) != 0x00u) + 800244e: 683b ldr r3, [r7, #0] + 8002450: 685b ldr r3, [r3, #4] + 8002452: f403 3340 and.w r3, r3, #196608 @ 0x30000 + 8002456: 2b00 cmp r3, #0 + 8002458: f000 808c beq.w 8002574 + { + temp = SYSCFG->EXTICR[position >> 2u]; + 800245c: 4a4e ldr r2, [pc, #312] @ (8002598 ) + 800245e: 697b ldr r3, [r7, #20] + 8002460: 089b lsrs r3, r3, #2 + 8002462: 3302 adds r3, #2 + 8002464: f852 3023 ldr.w r3, [r2, r3, lsl #2] + 8002468: 613b str r3, [r7, #16] + temp &= ~(0x07uL << (4U * (position & 0x03U))); + 800246a: 697b ldr r3, [r7, #20] + 800246c: f003 0303 and.w r3, r3, #3 + 8002470: 009b lsls r3, r3, #2 + 8002472: 2207 movs r2, #7 + 8002474: fa02 f303 lsl.w r3, r2, r3 + 8002478: 43db mvns r3, r3 + 800247a: 693a ldr r2, [r7, #16] + 800247c: 4013 ands r3, r2 + 800247e: 613b str r3, [r7, #16] + temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U))); + 8002480: 687b ldr r3, [r7, #4] + 8002482: f1b3 4f90 cmp.w r3, #1207959552 @ 0x48000000 + 8002486: d00d beq.n 80024a4 + 8002488: 687b ldr r3, [r7, #4] + 800248a: 4a44 ldr r2, [pc, #272] @ (800259c ) + 800248c: 4293 cmp r3, r2 + 800248e: d007 beq.n 80024a0 + 8002490: 687b ldr r3, [r7, #4] + 8002492: 4a43 ldr r2, [pc, #268] @ (80025a0 ) + 8002494: 4293 cmp r3, r2 + 8002496: d101 bne.n 800249c + 8002498: 2302 movs r3, #2 + 800249a: e004 b.n 80024a6 + 800249c: 2307 movs r3, #7 + 800249e: e002 b.n 80024a6 + 80024a0: 2301 movs r3, #1 + 80024a2: e000 b.n 80024a6 + 80024a4: 2300 movs r3, #0 + 80024a6: 697a ldr r2, [r7, #20] + 80024a8: f002 0203 and.w r2, r2, #3 + 80024ac: 0092 lsls r2, r2, #2 + 80024ae: 4093 lsls r3, r2 + 80024b0: 693a ldr r2, [r7, #16] + 80024b2: 4313 orrs r3, r2 + 80024b4: 613b str r3, [r7, #16] + SYSCFG->EXTICR[position >> 2u] = temp; + 80024b6: 4938 ldr r1, [pc, #224] @ (8002598 ) + 80024b8: 697b ldr r3, [r7, #20] + 80024ba: 089b lsrs r3, r3, #2 + 80024bc: 3302 adds r3, #2 + 80024be: 693a ldr r2, [r7, #16] + 80024c0: f841 2023 str.w r2, [r1, r3, lsl #2] + + /* Clear Rising Falling edge configuration */ + temp = EXTI->RTSR1; + 80024c4: 4b37 ldr r3, [pc, #220] @ (80025a4 ) + 80024c6: 681b ldr r3, [r3, #0] + 80024c8: 613b str r3, [r7, #16] + temp &= ~(iocurrent); + 80024ca: 68fb ldr r3, [r7, #12] + 80024cc: 43db mvns r3, r3 + 80024ce: 693a ldr r2, [r7, #16] + 80024d0: 4013 ands r3, r2 + 80024d2: 613b str r3, [r7, #16] + if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00u) + 80024d4: 683b ldr r3, [r7, #0] + 80024d6: 685b ldr r3, [r3, #4] + 80024d8: f403 1380 and.w r3, r3, #1048576 @ 0x100000 + 80024dc: 2b00 cmp r3, #0 + 80024de: d003 beq.n 80024e8 + { + temp |= iocurrent; + 80024e0: 693a ldr r2, [r7, #16] + 80024e2: 68fb ldr r3, [r7, #12] + 80024e4: 4313 orrs r3, r2 + 80024e6: 613b str r3, [r7, #16] + } + EXTI->RTSR1 = temp; + 80024e8: 4a2e ldr r2, [pc, #184] @ (80025a4 ) + 80024ea: 693b ldr r3, [r7, #16] + 80024ec: 6013 str r3, [r2, #0] + + temp = EXTI->FTSR1; + 80024ee: 4b2d ldr r3, [pc, #180] @ (80025a4 ) + 80024f0: 685b ldr r3, [r3, #4] + 80024f2: 613b str r3, [r7, #16] + temp &= ~(iocurrent); + 80024f4: 68fb ldr r3, [r7, #12] + 80024f6: 43db mvns r3, r3 + 80024f8: 693a ldr r2, [r7, #16] + 80024fa: 4013 ands r3, r2 + 80024fc: 613b str r3, [r7, #16] + if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00u) + 80024fe: 683b ldr r3, [r7, #0] + 8002500: 685b ldr r3, [r3, #4] + 8002502: f403 1300 and.w r3, r3, #2097152 @ 0x200000 + 8002506: 2b00 cmp r3, #0 + 8002508: d003 beq.n 8002512 + { + temp |= iocurrent; + 800250a: 693a ldr r2, [r7, #16] + 800250c: 68fb ldr r3, [r7, #12] + 800250e: 4313 orrs r3, r2 + 8002510: 613b str r3, [r7, #16] + } + EXTI->FTSR1 = temp; + 8002512: 4a24 ldr r2, [pc, #144] @ (80025a4 ) + 8002514: 693b ldr r3, [r7, #16] + 8002516: 6053 str r3, [r2, #4] + + /* Clear EXTI line configuration */ +#ifdef CORE_CM0PLUS + temp = EXTI->C2IMR1; +#else + temp = EXTI->IMR1; + 8002518: 4b22 ldr r3, [pc, #136] @ (80025a4 ) + 800251a: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 + 800251e: 613b str r3, [r7, #16] +#endif /* CORE_CM0PLUS */ + temp &= ~(iocurrent); + 8002520: 68fb ldr r3, [r7, #12] + 8002522: 43db mvns r3, r3 + 8002524: 693a ldr r2, [r7, #16] + 8002526: 4013 ands r3, r2 + 8002528: 613b str r3, [r7, #16] + if ((GPIO_Init->Mode & EXTI_IT) != 0x00u) + 800252a: 683b ldr r3, [r7, #0] + 800252c: 685b ldr r3, [r3, #4] + 800252e: f403 3380 and.w r3, r3, #65536 @ 0x10000 + 8002532: 2b00 cmp r3, #0 + 8002534: d003 beq.n 800253e + { + temp |= iocurrent; + 8002536: 693a ldr r2, [r7, #16] + 8002538: 68fb ldr r3, [r7, #12] + 800253a: 4313 orrs r3, r2 + 800253c: 613b str r3, [r7, #16] + } +#ifdef CORE_CM0PLUS + EXTI->C2IMR1 = temp; +#else + EXTI->IMR1 = temp; + 800253e: 4a19 ldr r2, [pc, #100] @ (80025a4 ) + 8002540: 693b ldr r3, [r7, #16] + 8002542: f8c2 3080 str.w r3, [r2, #128] @ 0x80 +#endif /* CORE_CM0PLUS */ + +#ifdef CORE_CM0PLUS + temp = EXTI->C2EMR1; +#else + temp = EXTI->EMR1; + 8002546: 4b17 ldr r3, [pc, #92] @ (80025a4 ) + 8002548: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 + 800254c: 613b str r3, [r7, #16] +#endif /* CORE_CM0PLUS */ + temp &= ~(iocurrent); + 800254e: 68fb ldr r3, [r7, #12] + 8002550: 43db mvns r3, r3 + 8002552: 693a ldr r2, [r7, #16] + 8002554: 4013 ands r3, r2 + 8002556: 613b str r3, [r7, #16] + if ((GPIO_Init->Mode & EXTI_EVT) != 0x00u) + 8002558: 683b ldr r3, [r7, #0] + 800255a: 685b ldr r3, [r3, #4] + 800255c: f403 3300 and.w r3, r3, #131072 @ 0x20000 + 8002560: 2b00 cmp r3, #0 + 8002562: d003 beq.n 800256c + { + temp |= iocurrent; + 8002564: 693a ldr r2, [r7, #16] + 8002566: 68fb ldr r3, [r7, #12] + 8002568: 4313 orrs r3, r2 + 800256a: 613b str r3, [r7, #16] + } +#ifdef CORE_CM0PLUS + EXTI->C2EMR1 = temp; +#else + EXTI->EMR1 = temp; + 800256c: 4a0d ldr r2, [pc, #52] @ (80025a4 ) + 800256e: 693b ldr r3, [r7, #16] + 8002570: f8c2 3084 str.w r3, [r2, #132] @ 0x84 +#endif /* CORE_CM0PLUS */ + } + } + + position++; + 8002574: 697b ldr r3, [r7, #20] + 8002576: 3301 adds r3, #1 + 8002578: 617b str r3, [r7, #20] + while (((GPIO_Init->Pin) >> position) != 0x00u) + 800257a: 683b ldr r3, [r7, #0] + 800257c: 681a ldr r2, [r3, #0] + 800257e: 697b ldr r3, [r7, #20] + 8002580: fa22 f303 lsr.w r3, r2, r3 + 8002584: 2b00 cmp r3, #0 + 8002586: f47f aeb7 bne.w 80022f8 + } +} + 800258a: bf00 nop + 800258c: bf00 nop + 800258e: 371c adds r7, #28 + 8002590: 46bd mov sp, r7 + 8002592: bc80 pop {r7} + 8002594: 4770 bx lr + 8002596: bf00 nop + 8002598: 40010000 .word 0x40010000 + 800259c: 48000400 .word 0x48000400 + 80025a0: 48000800 .word 0x48000800 + 80025a4: 58000800 .word 0x58000800 + +080025a8 : + * @param GPIO_Pin specifies the port bit to be written. + * This parameter can be any combination of GPIO_PIN_x where x can be (0..15). + * @retval None + */ +void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) +{ + 80025a8: b480 push {r7} + 80025aa: b087 sub sp, #28 + 80025ac: af00 add r7, sp, #0 + 80025ae: 6078 str r0, [r7, #4] + 80025b0: 6039 str r1, [r7, #0] + uint32_t position = 0x00u; + 80025b2: 2300 movs r3, #0 + 80025b4: 617b str r3, [r7, #20] + /* Check the parameters */ + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + /* Configure the port pins */ + while ((GPIO_Pin >> position) != 0x00u) + 80025b6: e0af b.n 8002718 + { + /* Get current io position */ + iocurrent = (GPIO_Pin) & (1uL << position); + 80025b8: 2201 movs r2, #1 + 80025ba: 697b ldr r3, [r7, #20] + 80025bc: fa02 f303 lsl.w r3, r2, r3 + 80025c0: 683a ldr r2, [r7, #0] + 80025c2: 4013 ands r3, r2 + 80025c4: 613b str r3, [r7, #16] + + if (iocurrent != 0x00u) + 80025c6: 693b ldr r3, [r7, #16] + 80025c8: 2b00 cmp r3, #0 + 80025ca: f000 80a2 beq.w 8002712 + { + /*------------------------- EXTI Mode Configuration --------------------*/ + /* Clear the External Interrupt or Event for the current IO */ + + tmp = SYSCFG->EXTICR[position >> 2u]; + 80025ce: 4a59 ldr r2, [pc, #356] @ (8002734 ) + 80025d0: 697b ldr r3, [r7, #20] + 80025d2: 089b lsrs r3, r3, #2 + 80025d4: 3302 adds r3, #2 + 80025d6: f852 3023 ldr.w r3, [r2, r3, lsl #2] + 80025da: 60fb str r3, [r7, #12] + tmp &= (0x07uL << (4U * (position & 0x03U))); + 80025dc: 697b ldr r3, [r7, #20] + 80025de: f003 0303 and.w r3, r3, #3 + 80025e2: 009b lsls r3, r3, #2 + 80025e4: 2207 movs r2, #7 + 80025e6: fa02 f303 lsl.w r3, r2, r3 + 80025ea: 68fa ldr r2, [r7, #12] + 80025ec: 4013 ands r3, r2 + 80025ee: 60fb str r3, [r7, #12] + if (tmp == (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U)))) + 80025f0: 687b ldr r3, [r7, #4] + 80025f2: f1b3 4f90 cmp.w r3, #1207959552 @ 0x48000000 + 80025f6: d00d beq.n 8002614 + 80025f8: 687b ldr r3, [r7, #4] + 80025fa: 4a4f ldr r2, [pc, #316] @ (8002738 ) + 80025fc: 4293 cmp r3, r2 + 80025fe: d007 beq.n 8002610 + 8002600: 687b ldr r3, [r7, #4] + 8002602: 4a4e ldr r2, [pc, #312] @ (800273c ) + 8002604: 4293 cmp r3, r2 + 8002606: d101 bne.n 800260c + 8002608: 2302 movs r3, #2 + 800260a: e004 b.n 8002616 + 800260c: 2307 movs r3, #7 + 800260e: e002 b.n 8002616 + 8002610: 2301 movs r3, #1 + 8002612: e000 b.n 8002616 + 8002614: 2300 movs r3, #0 + 8002616: 697a ldr r2, [r7, #20] + 8002618: f002 0203 and.w r2, r2, #3 + 800261c: 0092 lsls r2, r2, #2 + 800261e: 4093 lsls r3, r2 + 8002620: 68fa ldr r2, [r7, #12] + 8002622: 429a cmp r2, r3 + 8002624: d136 bne.n 8002694 + /* Clear EXTI line configuration */ +#ifdef CORE_CM0PLUS + EXTI->C2IMR1 &= ~(iocurrent); + EXTI->C2EMR1 &= ~(iocurrent); +#else + EXTI->IMR1 &= ~(iocurrent); + 8002626: 4b46 ldr r3, [pc, #280] @ (8002740 ) + 8002628: f8d3 2080 ldr.w r2, [r3, #128] @ 0x80 + 800262c: 693b ldr r3, [r7, #16] + 800262e: 43db mvns r3, r3 + 8002630: 4943 ldr r1, [pc, #268] @ (8002740 ) + 8002632: 4013 ands r3, r2 + 8002634: f8c1 3080 str.w r3, [r1, #128] @ 0x80 + EXTI->EMR1 &= ~(iocurrent); + 8002638: 4b41 ldr r3, [pc, #260] @ (8002740 ) + 800263a: f8d3 2084 ldr.w r2, [r3, #132] @ 0x84 + 800263e: 693b ldr r3, [r7, #16] + 8002640: 43db mvns r3, r3 + 8002642: 493f ldr r1, [pc, #252] @ (8002740 ) + 8002644: 4013 ands r3, r2 + 8002646: f8c1 3084 str.w r3, [r1, #132] @ 0x84 +#endif /* CORE_CM0PLUS */ + + /* Clear Rising Falling edge configuration */ + EXTI->RTSR1 &= ~(iocurrent); + 800264a: 4b3d ldr r3, [pc, #244] @ (8002740 ) + 800264c: 681a ldr r2, [r3, #0] + 800264e: 693b ldr r3, [r7, #16] + 8002650: 43db mvns r3, r3 + 8002652: 493b ldr r1, [pc, #236] @ (8002740 ) + 8002654: 4013 ands r3, r2 + 8002656: 600b str r3, [r1, #0] + EXTI->FTSR1 &= ~(iocurrent); + 8002658: 4b39 ldr r3, [pc, #228] @ (8002740 ) + 800265a: 685a ldr r2, [r3, #4] + 800265c: 693b ldr r3, [r7, #16] + 800265e: 43db mvns r3, r3 + 8002660: 4937 ldr r1, [pc, #220] @ (8002740 ) + 8002662: 4013 ands r3, r2 + 8002664: 604b str r3, [r1, #4] + + /* Clear EXTICR configuration */ + tmp = 0x07uL << (4u * (position & 0x03U)); + 8002666: 697b ldr r3, [r7, #20] + 8002668: f003 0303 and.w r3, r3, #3 + 800266c: 009b lsls r3, r3, #2 + 800266e: 2207 movs r2, #7 + 8002670: fa02 f303 lsl.w r3, r2, r3 + 8002674: 60fb str r3, [r7, #12] + SYSCFG->EXTICR[position >> 2u] &= ~tmp; + 8002676: 4a2f ldr r2, [pc, #188] @ (8002734 ) + 8002678: 697b ldr r3, [r7, #20] + 800267a: 089b lsrs r3, r3, #2 + 800267c: 3302 adds r3, #2 + 800267e: f852 1023 ldr.w r1, [r2, r3, lsl #2] + 8002682: 68fb ldr r3, [r7, #12] + 8002684: 43da mvns r2, r3 + 8002686: 482b ldr r0, [pc, #172] @ (8002734 ) + 8002688: 697b ldr r3, [r7, #20] + 800268a: 089b lsrs r3, r3, #2 + 800268c: 400a ands r2, r1 + 800268e: 3302 adds r3, #2 + 8002690: f840 2023 str.w r2, [r0, r3, lsl #2] + } + + /*------------------------- GPIO Mode Configuration --------------------*/ + /* Configure IO in Analog Mode */ + GPIOx->MODER |= (GPIO_MODER_MODE0 << (position * 2U)); + 8002694: 687b ldr r3, [r7, #4] + 8002696: 681a ldr r2, [r3, #0] + 8002698: 697b ldr r3, [r7, #20] + 800269a: 005b lsls r3, r3, #1 + 800269c: 2103 movs r1, #3 + 800269e: fa01 f303 lsl.w r3, r1, r3 + 80026a2: 431a orrs r2, r3 + 80026a4: 687b ldr r3, [r7, #4] + 80026a6: 601a str r2, [r3, #0] + + /* Configure the default Alternate Function in current IO */ + GPIOx->AFR[position >> 3U] &= ~(0xFU << ((position & 0x07U) * 4U)) ; + 80026a8: 697b ldr r3, [r7, #20] + 80026aa: 08da lsrs r2, r3, #3 + 80026ac: 687b ldr r3, [r7, #4] + 80026ae: 3208 adds r2, #8 + 80026b0: f853 1022 ldr.w r1, [r3, r2, lsl #2] + 80026b4: 697b ldr r3, [r7, #20] + 80026b6: f003 0307 and.w r3, r3, #7 + 80026ba: 009b lsls r3, r3, #2 + 80026bc: 220f movs r2, #15 + 80026be: fa02 f303 lsl.w r3, r2, r3 + 80026c2: 43db mvns r3, r3 + 80026c4: 697a ldr r2, [r7, #20] + 80026c6: 08d2 lsrs r2, r2, #3 + 80026c8: 4019 ands r1, r3 + 80026ca: 687b ldr r3, [r7, #4] + 80026cc: 3208 adds r2, #8 + 80026ce: f843 1022 str.w r1, [r3, r2, lsl #2] + + /* Configure the default value for IO Speed */ + GPIOx->OSPEEDR &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U)); + 80026d2: 687b ldr r3, [r7, #4] + 80026d4: 689a ldr r2, [r3, #8] + 80026d6: 697b ldr r3, [r7, #20] + 80026d8: 005b lsls r3, r3, #1 + 80026da: 2103 movs r1, #3 + 80026dc: fa01 f303 lsl.w r3, r1, r3 + 80026e0: 43db mvns r3, r3 + 80026e2: 401a ands r2, r3 + 80026e4: 687b ldr r3, [r7, #4] + 80026e6: 609a str r2, [r3, #8] + + /* Configure the default value IO Output Type */ + GPIOx->OTYPER &= ~(GPIO_OTYPER_OT0 << position) ; + 80026e8: 687b ldr r3, [r7, #4] + 80026ea: 685a ldr r2, [r3, #4] + 80026ec: 2101 movs r1, #1 + 80026ee: 697b ldr r3, [r7, #20] + 80026f0: fa01 f303 lsl.w r3, r1, r3 + 80026f4: 43db mvns r3, r3 + 80026f6: 401a ands r2, r3 + 80026f8: 687b ldr r3, [r7, #4] + 80026fa: 605a str r2, [r3, #4] + + /* Deactivate the Pull-up and Pull-down resistor for the current IO */ + GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPD0 << (position * 2U)); + 80026fc: 687b ldr r3, [r7, #4] + 80026fe: 68da ldr r2, [r3, #12] + 8002700: 697b ldr r3, [r7, #20] + 8002702: 005b lsls r3, r3, #1 + 8002704: 2103 movs r1, #3 + 8002706: fa01 f303 lsl.w r3, r1, r3 + 800270a: 43db mvns r3, r3 + 800270c: 401a ands r2, r3 + 800270e: 687b ldr r3, [r7, #4] + 8002710: 60da str r2, [r3, #12] + } + + position++; + 8002712: 697b ldr r3, [r7, #20] + 8002714: 3301 adds r3, #1 + 8002716: 617b str r3, [r7, #20] + while ((GPIO_Pin >> position) != 0x00u) + 8002718: 683a ldr r2, [r7, #0] + 800271a: 697b ldr r3, [r7, #20] + 800271c: fa22 f303 lsr.w r3, r2, r3 + 8002720: 2b00 cmp r3, #0 + 8002722: f47f af49 bne.w 80025b8 + } +} + 8002726: bf00 nop + 8002728: bf00 nop + 800272a: 371c adds r7, #28 + 800272c: 46bd mov sp, r7 + 800272e: bc80 pop {r7} + 8002730: 4770 bx lr + 8002732: bf00 nop + 8002734: 40010000 .word 0x40010000 + 8002738: 48000400 .word 0x48000400 + 800273c: 48000800 .word 0x48000800 + 8002740: 58000800 .word 0x58000800 + +08002744 : + * @arg GPIO_PIN_RESET: to clear the port pin + * @arg GPIO_PIN_SET: to set the port pin + * @retval None + */ +void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) +{ + 8002744: b480 push {r7} + 8002746: b083 sub sp, #12 + 8002748: af00 add r7, sp, #0 + 800274a: 6078 str r0, [r7, #4] + 800274c: 460b mov r3, r1 + 800274e: 807b strh r3, [r7, #2] + 8002750: 4613 mov r3, r2 + 8002752: 707b strb r3, [r7, #1] + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + assert_param(IS_GPIO_PIN_ACTION(PinState)); + + if (PinState != GPIO_PIN_RESET) + 8002754: 787b ldrb r3, [r7, #1] + 8002756: 2b00 cmp r3, #0 + 8002758: d003 beq.n 8002762 + { + GPIOx->BSRR = (uint32_t)GPIO_Pin; + 800275a: 887a ldrh r2, [r7, #2] + 800275c: 687b ldr r3, [r7, #4] + 800275e: 619a str r2, [r3, #24] + } + else + { + GPIOx->BRR = (uint32_t)GPIO_Pin; + } +} + 8002760: e002 b.n 8002768 + GPIOx->BRR = (uint32_t)GPIO_Pin; + 8002762: 887a ldrh r2, [r7, #2] + 8002764: 687b ldr r3, [r7, #4] + 8002766: 629a str r2, [r3, #40] @ 0x28 +} + 8002768: bf00 nop + 800276a: 370c adds r7, #12 + 800276c: 46bd mov sp, r7 + 800276e: bc80 pop {r7} + 8002770: 4770 bx lr + ... + +08002774 : + * @brief Handle EXTI interrupt request. + * @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line. + * @retval None + */ +void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) +{ + 8002774: b580 push {r7, lr} + 8002776: b082 sub sp, #8 + 8002778: af00 add r7, sp, #0 + 800277a: 4603 mov r3, r0 + 800277c: 80fb strh r3, [r7, #6] + /* EXTI line interrupt detected */ + if (__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != 0x00u) + 800277e: 4b08 ldr r3, [pc, #32] @ (80027a0 ) + 8002780: 68da ldr r2, [r3, #12] + 8002782: 88fb ldrh r3, [r7, #6] + 8002784: 4013 ands r3, r2 + 8002786: 2b00 cmp r3, #0 + 8002788: d006 beq.n 8002798 + { + __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin); + 800278a: 4a05 ldr r2, [pc, #20] @ (80027a0 ) + 800278c: 88fb ldrh r3, [r7, #6] + 800278e: 60d3 str r3, [r2, #12] + HAL_GPIO_EXTI_Callback(GPIO_Pin); + 8002790: 88fb ldrh r3, [r7, #6] + 8002792: 4618 mov r0, r3 + 8002794: f009 fadc bl 800bd50 + } +} + 8002798: bf00 nop + 800279a: 3708 adds r7, #8 + 800279c: 46bd mov sp, r7 + 800279e: bd80 pop {r7, pc} + 80027a0: 58000800 .word 0x58000800 + +080027a4 : + * @note LSEON bit that switches on and off the LSE crystal belongs as well to the + * backup domain. + * @retval None + */ +void HAL_PWR_EnableBkUpAccess(void) +{ + 80027a4: b480 push {r7} + 80027a6: af00 add r7, sp, #0 + SET_BIT(PWR->CR1, PWR_CR1_DBP); + 80027a8: 4b04 ldr r3, [pc, #16] @ (80027bc ) + 80027aa: 681b ldr r3, [r3, #0] + 80027ac: 4a03 ldr r2, [pc, #12] @ (80027bc ) + 80027ae: f443 7380 orr.w r3, r3, #256 @ 0x100 + 80027b2: 6013 str r3, [r2, #0] +} + 80027b4: bf00 nop + 80027b6: 46bd mov sp, r7 + 80027b8: bc80 pop {r7} + 80027ba: 4770 bx lr + 80027bc: 58000400 .word 0x58000400 + +080027c0 : + * @note When WFI entry is used, tick interrupt have to be disabled if not desired as + * the interrupt wake up source. + * @retval None + */ +void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry) +{ + 80027c0: b580 push {r7, lr} + 80027c2: b082 sub sp, #8 + 80027c4: af00 add r7, sp, #0 + 80027c6: 6078 str r0, [r7, #4] + 80027c8: 460b mov r3, r1 + 80027ca: 70fb strb r3, [r7, #3] + /* Check the parameters */ + assert_param(IS_PWR_REGULATOR(Regulator)); + assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry)); + + /* Set Regulator parameter */ + if (Regulator == PWR_MAINREGULATOR_ON) + 80027cc: 687b ldr r3, [r7, #4] + 80027ce: 2b00 cmp r3, #0 + 80027d0: d10c bne.n 80027ec + { + /* If in low-power run mode at this point, exit it */ + if (HAL_IS_BIT_SET(PWR->SR2, (PWR_SR2_REGLPF))) + 80027d2: 4b13 ldr r3, [pc, #76] @ (8002820 ) + 80027d4: 695b ldr r3, [r3, #20] + 80027d6: f403 7300 and.w r3, r3, #512 @ 0x200 + 80027da: f5b3 7f00 cmp.w r3, #512 @ 0x200 + 80027de: d10d bne.n 80027fc + { + if (HAL_PWREx_DisableLowPowerRunMode() != HAL_OK) + 80027e0: f000 f83c bl 800285c + 80027e4: 4603 mov r3, r0 + 80027e6: 2b00 cmp r3, #0 + 80027e8: d008 beq.n 80027fc + { + return ; + 80027ea: e015 b.n 8002818 + } + else + { + /* If in run mode, first move to low-power run mode. + The system clock frequency must be below 2 MHz at this point. */ + if (HAL_IS_BIT_CLR(PWR->SR2, (PWR_SR2_REGLPF))) + 80027ec: 4b0c ldr r3, [pc, #48] @ (8002820 ) + 80027ee: 695b ldr r3, [r3, #20] + 80027f0: f403 7300 and.w r3, r3, #512 @ 0x200 + 80027f4: 2b00 cmp r3, #0 + 80027f6: d101 bne.n 80027fc + { + HAL_PWREx_EnableLowPowerRunMode(); + 80027f8: f000 f822 bl 8002840 + } + } + + /* Clear SLEEPDEEP bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); + 80027fc: 4b09 ldr r3, [pc, #36] @ (8002824 ) + 80027fe: 691b ldr r3, [r3, #16] + 8002800: 4a08 ldr r2, [pc, #32] @ (8002824 ) + 8002802: f023 0304 bic.w r3, r3, #4 + 8002806: 6113 str r3, [r2, #16] + + /* Select SLEEP mode entry -------------------------------------------------*/ + if (SLEEPEntry == PWR_SLEEPENTRY_WFI) + 8002808: 78fb ldrb r3, [r7, #3] + 800280a: 2b01 cmp r3, #1 + 800280c: d101 bne.n 8002812 + { + /* Request Wait For Interrupt */ + __WFI(); + 800280e: bf30 wfi + 8002810: e002 b.n 8002818 + } + else + { + /* Request Wait For Event */ + __SEV(); + 8002812: bf40 sev + __WFE(); + 8002814: bf20 wfe + __WFE(); + 8002816: bf20 wfe + } +} + 8002818: 3708 adds r7, #8 + 800281a: 46bd mov sp, r7 + 800281c: bd80 pop {r7, pc} + 800281e: bf00 nop + 8002820: 58000400 .word 0x58000400 + 8002824: e000ed00 .word 0xe000ed00 + +08002828 : +/** + * @brief Return Voltage Scaling Range. + * @retval VOS bit field (PWR_REGULATOR_VOLTAGE_SCALE1 or PWPWR_REGULATOR_VOLTAGE_SCALE2) + */ +uint32_t HAL_PWREx_GetVoltageRange(void) +{ + 8002828: b480 push {r7} + 800282a: af00 add r7, sp, #0 + return (PWR->CR1 & PWR_CR1_VOS); + 800282c: 4b03 ldr r3, [pc, #12] @ (800283c ) + 800282e: 681b ldr r3, [r3, #0] + 8002830: f403 63c0 and.w r3, r3, #1536 @ 0x600 +} + 8002834: 4618 mov r0, r3 + 8002836: 46bd mov sp, r7 + 8002838: bc80 pop {r7} + 800283a: 4770 bx lr + 800283c: 58000400 .word 0x58000400 + +08002840 : + * @note In Low-power Run mode, all I/O pins keep the same state as in Run mode. + * @note Clock frequency must be reduced below 2 MHz. + * @retval None + */ +void HAL_PWREx_EnableLowPowerRunMode(void) +{ + 8002840: b480 push {r7} + 8002842: af00 add r7, sp, #0 + /* Set Regulator parameter */ + SET_BIT(PWR->CR1, PWR_CR1_LPR); + 8002844: 4b04 ldr r3, [pc, #16] @ (8002858 ) + 8002846: 681b ldr r3, [r3, #0] + 8002848: 4a03 ldr r2, [pc, #12] @ (8002858 ) + 800284a: f443 4380 orr.w r3, r3, #16384 @ 0x4000 + 800284e: 6013 str r3, [r2, #0] +} + 8002850: bf00 nop + 8002852: 46bd mov sp, r7 + 8002854: bc80 pop {r7} + 8002856: 4770 bx lr + 8002858: 58000400 .word 0x58000400 + +0800285c : + * returns HAL_TIMEOUT status). The system clock frequency can then be + * increased above 2 MHz. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void) +{ + 800285c: b480 push {r7} + 800285e: b083 sub sp, #12 + 8002860: af00 add r7, sp, #0 + uint32_t wait_loop_index; + + /* Clear LPR bit */ + CLEAR_BIT(PWR->CR1, PWR_CR1_LPR); + 8002862: 4b16 ldr r3, [pc, #88] @ (80028bc ) + 8002864: 681b ldr r3, [r3, #0] + 8002866: 4a15 ldr r2, [pc, #84] @ (80028bc ) + 8002868: f423 4380 bic.w r3, r3, #16384 @ 0x4000 + 800286c: 6013 str r3, [r2, #0] + + /* Wait until REGLPF is reset */ + wait_loop_index = ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000UL); + 800286e: 4b14 ldr r3, [pc, #80] @ (80028c0 ) + 8002870: 681b ldr r3, [r3, #0] + 8002872: 2232 movs r2, #50 @ 0x32 + 8002874: fb02 f303 mul.w r3, r2, r3 + 8002878: 4a12 ldr r2, [pc, #72] @ (80028c4 ) + 800287a: fba2 2303 umull r2, r3, r2, r3 + 800287e: 0c9b lsrs r3, r3, #18 + 8002880: 607b str r3, [r7, #4] + while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF)) && (wait_loop_index != 0U)) + 8002882: e002 b.n 800288a + { + wait_loop_index--; + 8002884: 687b ldr r3, [r7, #4] + 8002886: 3b01 subs r3, #1 + 8002888: 607b str r3, [r7, #4] + while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF)) && (wait_loop_index != 0U)) + 800288a: 4b0c ldr r3, [pc, #48] @ (80028bc ) + 800288c: 695b ldr r3, [r3, #20] + 800288e: f403 7300 and.w r3, r3, #512 @ 0x200 + 8002892: f5b3 7f00 cmp.w r3, #512 @ 0x200 + 8002896: d102 bne.n 800289e + 8002898: 687b ldr r3, [r7, #4] + 800289a: 2b00 cmp r3, #0 + 800289c: d1f2 bne.n 8002884 + } + if (HAL_IS_BIT_SET(PWR->SR2, (PWR_SR2_REGLPF))) + 800289e: 4b07 ldr r3, [pc, #28] @ (80028bc ) + 80028a0: 695b ldr r3, [r3, #20] + 80028a2: f403 7300 and.w r3, r3, #512 @ 0x200 + 80028a6: f5b3 7f00 cmp.w r3, #512 @ 0x200 + 80028aa: d101 bne.n 80028b0 + { + return HAL_TIMEOUT; + 80028ac: 2303 movs r3, #3 + 80028ae: e000 b.n 80028b2 + } + + return HAL_OK; + 80028b0: 2300 movs r3, #0 +} + 80028b2: 4618 mov r0, r3 + 80028b4: 370c adds r7, #12 + 80028b6: 46bd mov sp, r7 + 80028b8: bc80 pop {r7} + 80028ba: 4770 bx lr + 80028bc: 58000400 .word 0x58000400 + 80028c0: 20000000 .word 0x20000000 + 80028c4: 431bde83 .word 0x431bde83 + +080028c8 : + * @arg @ref PWR_STOPENTRY_WFI Enter Stop mode with WFI instruction + * @arg @ref PWR_STOPENTRY_WFE Enter Stop mode with WFE instruction + * @retval None + */ +void HAL_PWREx_EnterSTOP2Mode(uint8_t STOPEntry) +{ + 80028c8: b480 push {r7} + 80028ca: b083 sub sp, #12 + 80028cc: af00 add r7, sp, #0 + 80028ce: 4603 mov r3, r0 + 80028d0: 71fb strb r3, [r7, #7] +#ifdef CORE_CM0PLUS + /* Set Stop mode 2 */ + MODIFY_REG(PWR->C2CR1, PWR_C2CR1_LPMS, PWR_LOWPOWERMODE_STOP2); +#else + /* Set Stop mode 2 */ + MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_LOWPOWERMODE_STOP2); + 80028d2: 4b10 ldr r3, [pc, #64] @ (8002914 ) + 80028d4: 681b ldr r3, [r3, #0] + 80028d6: f023 0307 bic.w r3, r3, #7 + 80028da: 4a0e ldr r2, [pc, #56] @ (8002914 ) + 80028dc: f043 0302 orr.w r3, r3, #2 + 80028e0: 6013 str r3, [r2, #0] +#endif /* CORE_CM0PLUS */ + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); + 80028e2: 4b0d ldr r3, [pc, #52] @ (8002918 ) + 80028e4: 691b ldr r3, [r3, #16] + 80028e6: 4a0c ldr r2, [pc, #48] @ (8002918 ) + 80028e8: f043 0304 orr.w r3, r3, #4 + 80028ec: 6113 str r3, [r2, #16] + + /* Select Stop mode entry --------------------------------------------------*/ + if (STOPEntry == PWR_STOPENTRY_WFI) + 80028ee: 79fb ldrb r3, [r7, #7] + 80028f0: 2b01 cmp r3, #1 + 80028f2: d101 bne.n 80028f8 + { + /* Request Wait For Interrupt */ + __WFI(); + 80028f4: bf30 wfi + 80028f6: e002 b.n 80028fe + } + else + { + /* Request Wait For Event */ + __SEV(); + 80028f8: bf40 sev + __WFE(); + 80028fa: bf20 wfe + __WFE(); + 80028fc: bf20 wfe + } + + /* Reset SLEEPDEEP bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); + 80028fe: 4b06 ldr r3, [pc, #24] @ (8002918 ) + 8002900: 691b ldr r3, [r3, #16] + 8002902: 4a05 ldr r2, [pc, #20] @ (8002918 ) + 8002904: f023 0304 bic.w r3, r3, #4 + 8002908: 6113 str r3, [r2, #16] +} + 800290a: bf00 nop + 800290c: 370c adds r7, #12 + 800290e: 46bd mov sp, r7 + 8002910: bc80 pop {r7} + 8002912: 4770 bx lr + 8002914: 58000400 .word 0x58000400 + 8002918: e000ed00 .word 0xe000ed00 + +0800291c : +{ + 800291c: b480 push {r7} + 800291e: af00 add r7, sp, #0 + return ((READ_BIT(PWR->CR1, PWR_CR1_DBP) == (PWR_CR1_DBP)) ? 1UL : 0UL); + 8002920: 4b06 ldr r3, [pc, #24] @ (800293c ) + 8002922: 681b ldr r3, [r3, #0] + 8002924: f403 7380 and.w r3, r3, #256 @ 0x100 + 8002928: f5b3 7f80 cmp.w r3, #256 @ 0x100 + 800292c: d101 bne.n 8002932 + 800292e: 2301 movs r3, #1 + 8002930: e000 b.n 8002934 + 8002932: 2300 movs r3, #0 +} + 8002934: 4618 mov r0, r3 + 8002936: 46bd mov sp, r7 + 8002938: bc80 pop {r7} + 800293a: 4770 bx lr + 800293c: 58000400 .word 0x58000400 + +08002940 : +{ + 8002940: b480 push {r7} + 8002942: af00 add r7, sp, #0 + SET_BIT(RCC->CR, RCC_CR_HSEBYPPWR); + 8002944: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002948: 681b ldr r3, [r3, #0] + 800294a: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 800294e: f443 1300 orr.w r3, r3, #2097152 @ 0x200000 + 8002952: 6013 str r3, [r2, #0] +} + 8002954: bf00 nop + 8002956: 46bd mov sp, r7 + 8002958: bc80 pop {r7} + 800295a: 4770 bx lr + +0800295c : +{ + 800295c: b480 push {r7} + 800295e: af00 add r7, sp, #0 + CLEAR_BIT(RCC->CR, RCC_CR_HSEBYPPWR); + 8002960: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002964: 681b ldr r3, [r3, #0] + 8002966: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 800296a: f423 1300 bic.w r3, r3, #2097152 @ 0x200000 + 800296e: 6013 str r3, [r2, #0] +} + 8002970: bf00 nop + 8002972: 46bd mov sp, r7 + 8002974: bc80 pop {r7} + 8002976: 4770 bx lr + +08002978 : +{ + 8002978: b480 push {r7} + 800297a: af00 add r7, sp, #0 + return ((READ_BIT(RCC->CR, RCC_CR_HSEPRE) == (RCC_CR_HSEPRE)) ? 1UL : 0UL); + 800297c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002980: 681b ldr r3, [r3, #0] + 8002982: f403 1380 and.w r3, r3, #1048576 @ 0x100000 + 8002986: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 + 800298a: d101 bne.n 8002990 + 800298c: 2301 movs r3, #1 + 800298e: e000 b.n 8002992 + 8002990: 2300 movs r3, #0 +} + 8002992: 4618 mov r0, r3 + 8002994: 46bd mov sp, r7 + 8002996: bc80 pop {r7} + 8002998: 4770 bx lr + +0800299a : +{ + 800299a: b480 push {r7} + 800299c: af00 add r7, sp, #0 + SET_BIT(RCC->CR, RCC_CR_HSEON); + 800299e: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 80029a2: 681b ldr r3, [r3, #0] + 80029a4: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 80029a8: f443 3380 orr.w r3, r3, #65536 @ 0x10000 + 80029ac: 6013 str r3, [r2, #0] +} + 80029ae: bf00 nop + 80029b0: 46bd mov sp, r7 + 80029b2: bc80 pop {r7} + 80029b4: 4770 bx lr + +080029b6 : +{ + 80029b6: b480 push {r7} + 80029b8: af00 add r7, sp, #0 + CLEAR_BIT(RCC->CR, RCC_CR_HSEON); + 80029ba: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 80029be: 681b ldr r3, [r3, #0] + 80029c0: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 80029c4: f423 3380 bic.w r3, r3, #65536 @ 0x10000 + 80029c8: 6013 str r3, [r2, #0] +} + 80029ca: bf00 nop + 80029cc: 46bd mov sp, r7 + 80029ce: bc80 pop {r7} + 80029d0: 4770 bx lr + +080029d2 : +{ + 80029d2: b480 push {r7} + 80029d4: af00 add r7, sp, #0 + return ((READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY)) ? 1UL : 0UL); + 80029d6: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 80029da: 681b ldr r3, [r3, #0] + 80029dc: f403 3300 and.w r3, r3, #131072 @ 0x20000 + 80029e0: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 + 80029e4: d101 bne.n 80029ea + 80029e6: 2301 movs r3, #1 + 80029e8: e000 b.n 80029ec + 80029ea: 2300 movs r3, #0 +} + 80029ec: 4618 mov r0, r3 + 80029ee: 46bd mov sp, r7 + 80029f0: bc80 pop {r7} + 80029f2: 4770 bx lr + +080029f4 : +{ + 80029f4: b480 push {r7} + 80029f6: af00 add r7, sp, #0 + SET_BIT(RCC->CR, RCC_CR_HSION); + 80029f8: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 80029fc: 681b ldr r3, [r3, #0] + 80029fe: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 8002a02: f443 7380 orr.w r3, r3, #256 @ 0x100 + 8002a06: 6013 str r3, [r2, #0] +} + 8002a08: bf00 nop + 8002a0a: 46bd mov sp, r7 + 8002a0c: bc80 pop {r7} + 8002a0e: 4770 bx lr + +08002a10 : +{ + 8002a10: b480 push {r7} + 8002a12: af00 add r7, sp, #0 + CLEAR_BIT(RCC->CR, RCC_CR_HSION); + 8002a14: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002a18: 681b ldr r3, [r3, #0] + 8002a1a: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 8002a1e: f423 7380 bic.w r3, r3, #256 @ 0x100 + 8002a22: 6013 str r3, [r2, #0] +} + 8002a24: bf00 nop + 8002a26: 46bd mov sp, r7 + 8002a28: bc80 pop {r7} + 8002a2a: 4770 bx lr + +08002a2c : +{ + 8002a2c: b480 push {r7} + 8002a2e: af00 add r7, sp, #0 + return ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY)) ? 1UL : 0UL); + 8002a30: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002a34: 681b ldr r3, [r3, #0] + 8002a36: f403 6380 and.w r3, r3, #1024 @ 0x400 + 8002a3a: f5b3 6f80 cmp.w r3, #1024 @ 0x400 + 8002a3e: d101 bne.n 8002a44 + 8002a40: 2301 movs r3, #1 + 8002a42: e000 b.n 8002a46 + 8002a44: 2300 movs r3, #0 +} + 8002a46: 4618 mov r0, r3 + 8002a48: 46bd mov sp, r7 + 8002a4a: bc80 pop {r7} + 8002a4c: 4770 bx lr + +08002a4e : +{ + 8002a4e: b480 push {r7} + 8002a50: b083 sub sp, #12 + 8002a52: af00 add r7, sp, #0 + 8002a54: 6078 str r0, [r7, #4] + MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, Value << RCC_ICSCR_HSITRIM_Pos); + 8002a56: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002a5a: 685b ldr r3, [r3, #4] + 8002a5c: f023 42fe bic.w r2, r3, #2130706432 @ 0x7f000000 + 8002a60: 687b ldr r3, [r7, #4] + 8002a62: 061b lsls r3, r3, #24 + 8002a64: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 8002a68: 4313 orrs r3, r2 + 8002a6a: 604b str r3, [r1, #4] +} + 8002a6c: bf00 nop + 8002a6e: 370c adds r7, #12 + 8002a70: 46bd mov sp, r7 + 8002a72: bc80 pop {r7} + 8002a74: 4770 bx lr + +08002a76 : +{ + 8002a76: b480 push {r7} + 8002a78: af00 add r7, sp, #0 + return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY)) ? 1UL : 0UL); + 8002a7a: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002a7e: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 8002a82: f003 0302 and.w r3, r3, #2 + 8002a86: 2b02 cmp r3, #2 + 8002a88: d101 bne.n 8002a8e + 8002a8a: 2301 movs r3, #1 + 8002a8c: e000 b.n 8002a90 + 8002a8e: 2300 movs r3, #0 +} + 8002a90: 4618 mov r0, r3 + 8002a92: 46bd mov sp, r7 + 8002a94: bc80 pop {r7} + 8002a96: 4770 bx lr + +08002a98 : +{ + 8002a98: b480 push {r7} + 8002a9a: af00 add r7, sp, #0 + SET_BIT(RCC->CSR, RCC_CSR_LSION); + 8002a9c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002aa0: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 + 8002aa4: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 8002aa8: f043 0301 orr.w r3, r3, #1 + 8002aac: f8c2 3094 str.w r3, [r2, #148] @ 0x94 +} + 8002ab0: bf00 nop + 8002ab2: 46bd mov sp, r7 + 8002ab4: bc80 pop {r7} + 8002ab6: 4770 bx lr + +08002ab8 : +{ + 8002ab8: b480 push {r7} + 8002aba: af00 add r7, sp, #0 + CLEAR_BIT(RCC->CSR, RCC_CSR_LSION); + 8002abc: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002ac0: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 + 8002ac4: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 8002ac8: f023 0301 bic.w r3, r3, #1 + 8002acc: f8c2 3094 str.w r3, [r2, #148] @ 0x94 +} + 8002ad0: bf00 nop + 8002ad2: 46bd mov sp, r7 + 8002ad4: bc80 pop {r7} + 8002ad6: 4770 bx lr + +08002ad8 : +{ + 8002ad8: b480 push {r7} + 8002ada: af00 add r7, sp, #0 + return ((READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY)) ? 1UL : 0UL); + 8002adc: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002ae0: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 + 8002ae4: f003 0302 and.w r3, r3, #2 + 8002ae8: 2b02 cmp r3, #2 + 8002aea: d101 bne.n 8002af0 + 8002aec: 2301 movs r3, #1 + 8002aee: e000 b.n 8002af2 + 8002af0: 2300 movs r3, #0 +} + 8002af2: 4618 mov r0, r3 + 8002af4: 46bd mov sp, r7 + 8002af6: bc80 pop {r7} + 8002af8: 4770 bx lr + +08002afa : +{ + 8002afa: b480 push {r7} + 8002afc: af00 add r7, sp, #0 + SET_BIT(RCC->CR, RCC_CR_MSION); + 8002afe: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002b02: 681b ldr r3, [r3, #0] + 8002b04: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 8002b08: f043 0301 orr.w r3, r3, #1 + 8002b0c: 6013 str r3, [r2, #0] +} + 8002b0e: bf00 nop + 8002b10: 46bd mov sp, r7 + 8002b12: bc80 pop {r7} + 8002b14: 4770 bx lr + +08002b16 : +{ + 8002b16: b480 push {r7} + 8002b18: af00 add r7, sp, #0 + CLEAR_BIT(RCC->CR, RCC_CR_MSION); + 8002b1a: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002b1e: 681b ldr r3, [r3, #0] + 8002b20: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 8002b24: f023 0301 bic.w r3, r3, #1 + 8002b28: 6013 str r3, [r2, #0] +} + 8002b2a: bf00 nop + 8002b2c: 46bd mov sp, r7 + 8002b2e: bc80 pop {r7} + 8002b30: 4770 bx lr + +08002b32 : +{ + 8002b32: b480 push {r7} + 8002b34: af00 add r7, sp, #0 + return ((READ_BIT(RCC->CR, RCC_CR_MSIRDY) == (RCC_CR_MSIRDY)) ? 1UL : 0UL); + 8002b36: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002b3a: 681b ldr r3, [r3, #0] + 8002b3c: f003 0302 and.w r3, r3, #2 + 8002b40: 2b02 cmp r3, #2 + 8002b42: d101 bne.n 8002b48 + 8002b44: 2301 movs r3, #1 + 8002b46: e000 b.n 8002b4a + 8002b48: 2300 movs r3, #0 +} + 8002b4a: 4618 mov r0, r3 + 8002b4c: 46bd mov sp, r7 + 8002b4e: bc80 pop {r7} + 8002b50: 4770 bx lr + +08002b52 : +{ + 8002b52: b480 push {r7} + 8002b54: af00 add r7, sp, #0 + return ((READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) == (RCC_CR_MSIRGSEL)) ? 1UL : 0UL); + 8002b56: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002b5a: 681b ldr r3, [r3, #0] + 8002b5c: f003 0308 and.w r3, r3, #8 + 8002b60: 2b08 cmp r3, #8 + 8002b62: d101 bne.n 8002b68 + 8002b64: 2301 movs r3, #1 + 8002b66: e000 b.n 8002b6a + 8002b68: 2300 movs r3, #0 +} + 8002b6a: 4618 mov r0, r3 + 8002b6c: 46bd mov sp, r7 + 8002b6e: bc80 pop {r7} + 8002b70: 4770 bx lr + +08002b72 : +{ + 8002b72: b480 push {r7} + 8002b74: af00 add r7, sp, #0 + return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_MSIRANGE)); + 8002b76: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002b7a: 681b ldr r3, [r3, #0] + 8002b7c: f003 03f0 and.w r3, r3, #240 @ 0xf0 +} + 8002b80: 4618 mov r0, r3 + 8002b82: 46bd mov sp, r7 + 8002b84: bc80 pop {r7} + 8002b86: 4770 bx lr + +08002b88 : +{ + 8002b88: b480 push {r7} + 8002b8a: af00 add r7, sp, #0 + return (uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_MSISRANGE)); + 8002b8c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002b90: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 + 8002b94: f403 6370 and.w r3, r3, #3840 @ 0xf00 +} + 8002b98: 4618 mov r0, r3 + 8002b9a: 46bd mov sp, r7 + 8002b9c: bc80 pop {r7} + 8002b9e: 4770 bx lr + +08002ba0 : +{ + 8002ba0: b480 push {r7} + 8002ba2: b083 sub sp, #12 + 8002ba4: af00 add r7, sp, #0 + 8002ba6: 6078 str r0, [r7, #4] + MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, Value << RCC_ICSCR_MSITRIM_Pos); + 8002ba8: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002bac: 685b ldr r3, [r3, #4] + 8002bae: f423 427f bic.w r2, r3, #65280 @ 0xff00 + 8002bb2: 687b ldr r3, [r7, #4] + 8002bb4: 021b lsls r3, r3, #8 + 8002bb6: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 8002bba: 4313 orrs r3, r2 + 8002bbc: 604b str r3, [r1, #4] +} + 8002bbe: bf00 nop + 8002bc0: 370c adds r7, #12 + 8002bc2: 46bd mov sp, r7 + 8002bc4: bc80 pop {r7} + 8002bc6: 4770 bx lr + +08002bc8 : +{ + 8002bc8: b480 push {r7} + 8002bca: b083 sub sp, #12 + 8002bcc: af00 add r7, sp, #0 + 8002bce: 6078 str r0, [r7, #4] + MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source); + 8002bd0: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002bd4: 689b ldr r3, [r3, #8] + 8002bd6: f023 0203 bic.w r2, r3, #3 + 8002bda: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 8002bde: 687b ldr r3, [r7, #4] + 8002be0: 4313 orrs r3, r2 + 8002be2: 608b str r3, [r1, #8] +} + 8002be4: bf00 nop + 8002be6: 370c adds r7, #12 + 8002be8: 46bd mov sp, r7 + 8002bea: bc80 pop {r7} + 8002bec: 4770 bx lr + +08002bee : +{ + 8002bee: b480 push {r7} + 8002bf0: af00 add r7, sp, #0 + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS)); + 8002bf2: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002bf6: 689b ldr r3, [r3, #8] + 8002bf8: f003 030c and.w r3, r3, #12 +} + 8002bfc: 4618 mov r0, r3 + 8002bfe: 46bd mov sp, r7 + 8002c00: bc80 pop {r7} + 8002c02: 4770 bx lr + +08002c04 : +{ + 8002c04: b480 push {r7} + 8002c06: b083 sub sp, #12 + 8002c08: af00 add r7, sp, #0 + 8002c0a: 6078 str r0, [r7, #4] + MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler); + 8002c0c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002c10: 689b ldr r3, [r3, #8] + 8002c12: f023 02f0 bic.w r2, r3, #240 @ 0xf0 + 8002c16: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 8002c1a: 687b ldr r3, [r7, #4] + 8002c1c: 4313 orrs r3, r2 + 8002c1e: 608b str r3, [r1, #8] +} + 8002c20: bf00 nop + 8002c22: 370c adds r7, #12 + 8002c24: 46bd mov sp, r7 + 8002c26: bc80 pop {r7} + 8002c28: 4770 bx lr + +08002c2a : +{ + 8002c2a: b480 push {r7} + 8002c2c: b083 sub sp, #12 + 8002c2e: af00 add r7, sp, #0 + 8002c30: 6078 str r0, [r7, #4] + MODIFY_REG(RCC->EXTCFGR, RCC_EXTCFGR_C2HPRE, Prescaler); + 8002c32: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002c36: f8d3 3108 ldr.w r3, [r3, #264] @ 0x108 + 8002c3a: f023 02f0 bic.w r2, r3, #240 @ 0xf0 + 8002c3e: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 8002c42: 687b ldr r3, [r7, #4] + 8002c44: 4313 orrs r3, r2 + 8002c46: f8c1 3108 str.w r3, [r1, #264] @ 0x108 +} + 8002c4a: bf00 nop + 8002c4c: 370c adds r7, #12 + 8002c4e: 46bd mov sp, r7 + 8002c50: bc80 pop {r7} + 8002c52: 4770 bx lr + +08002c54 : +{ + 8002c54: b480 push {r7} + 8002c56: b083 sub sp, #12 + 8002c58: af00 add r7, sp, #0 + 8002c5a: 6078 str r0, [r7, #4] + MODIFY_REG(RCC->EXTCFGR, RCC_EXTCFGR_SHDHPRE, Prescaler >> 4); + 8002c5c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002c60: f8d3 3108 ldr.w r3, [r3, #264] @ 0x108 + 8002c64: f023 020f bic.w r2, r3, #15 + 8002c68: 687b ldr r3, [r7, #4] + 8002c6a: 091b lsrs r3, r3, #4 + 8002c6c: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 8002c70: 4313 orrs r3, r2 + 8002c72: f8c1 3108 str.w r3, [r1, #264] @ 0x108 +} + 8002c76: bf00 nop + 8002c78: 370c adds r7, #12 + 8002c7a: 46bd mov sp, r7 + 8002c7c: bc80 pop {r7} + 8002c7e: 4770 bx lr + +08002c80 : +{ + 8002c80: b480 push {r7} + 8002c82: b083 sub sp, #12 + 8002c84: af00 add r7, sp, #0 + 8002c86: 6078 str r0, [r7, #4] + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler); + 8002c88: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002c8c: 689b ldr r3, [r3, #8] + 8002c8e: f423 62e0 bic.w r2, r3, #1792 @ 0x700 + 8002c92: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 8002c96: 687b ldr r3, [r7, #4] + 8002c98: 4313 orrs r3, r2 + 8002c9a: 608b str r3, [r1, #8] +} + 8002c9c: bf00 nop + 8002c9e: 370c adds r7, #12 + 8002ca0: 46bd mov sp, r7 + 8002ca2: bc80 pop {r7} + 8002ca4: 4770 bx lr + +08002ca6 : +{ + 8002ca6: b480 push {r7} + 8002ca8: b083 sub sp, #12 + 8002caa: af00 add r7, sp, #0 + 8002cac: 6078 str r0, [r7, #4] + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler); + 8002cae: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002cb2: 689b ldr r3, [r3, #8] + 8002cb4: f423 5260 bic.w r2, r3, #14336 @ 0x3800 + 8002cb8: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 8002cbc: 687b ldr r3, [r7, #4] + 8002cbe: 4313 orrs r3, r2 + 8002cc0: 608b str r3, [r1, #8] +} + 8002cc2: bf00 nop + 8002cc4: 370c adds r7, #12 + 8002cc6: 46bd mov sp, r7 + 8002cc8: bc80 pop {r7} + 8002cca: 4770 bx lr + +08002ccc : +{ + 8002ccc: b480 push {r7} + 8002cce: af00 add r7, sp, #0 + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE)); + 8002cd0: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002cd4: 689b ldr r3, [r3, #8] + 8002cd6: f003 03f0 and.w r3, r3, #240 @ 0xf0 +} + 8002cda: 4618 mov r0, r3 + 8002cdc: 46bd mov sp, r7 + 8002cde: bc80 pop {r7} + 8002ce0: 4770 bx lr + +08002ce2 : +{ + 8002ce2: b480 push {r7} + 8002ce4: af00 add r7, sp, #0 + return (uint32_t)(READ_BIT(RCC->EXTCFGR, RCC_EXTCFGR_SHDHPRE) << 4); + 8002ce6: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002cea: f8d3 3108 ldr.w r3, [r3, #264] @ 0x108 + 8002cee: 011b lsls r3, r3, #4 + 8002cf0: f003 03f0 and.w r3, r3, #240 @ 0xf0 +} + 8002cf4: 4618 mov r0, r3 + 8002cf6: 46bd mov sp, r7 + 8002cf8: bc80 pop {r7} + 8002cfa: 4770 bx lr + +08002cfc : +{ + 8002cfc: b480 push {r7} + 8002cfe: af00 add r7, sp, #0 + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1)); + 8002d00: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002d04: 689b ldr r3, [r3, #8] + 8002d06: f403 63e0 and.w r3, r3, #1792 @ 0x700 +} + 8002d0a: 4618 mov r0, r3 + 8002d0c: 46bd mov sp, r7 + 8002d0e: bc80 pop {r7} + 8002d10: 4770 bx lr + +08002d12 : +{ + 8002d12: b480 push {r7} + 8002d14: af00 add r7, sp, #0 + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2)); + 8002d16: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002d1a: 689b ldr r3, [r3, #8] + 8002d1c: f403 5360 and.w r3, r3, #14336 @ 0x3800 +} + 8002d20: 4618 mov r0, r3 + 8002d22: 46bd mov sp, r7 + 8002d24: bc80 pop {r7} + 8002d26: 4770 bx lr + +08002d28 : + * @brief Enable PLL + * @rmtoll CR PLLON LL_RCC_PLL_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_Enable(void) +{ + 8002d28: b480 push {r7} + 8002d2a: af00 add r7, sp, #0 + SET_BIT(RCC->CR, RCC_CR_PLLON); + 8002d2c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002d30: 681b ldr r3, [r3, #0] + 8002d32: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 8002d36: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000 + 8002d3a: 6013 str r3, [r2, #0] +} + 8002d3c: bf00 nop + 8002d3e: 46bd mov sp, r7 + 8002d40: bc80 pop {r7} + 8002d42: 4770 bx lr + +08002d44 : + * @note Cannot be disabled if the PLL clock is used as the system clock + * @rmtoll CR PLLON LL_RCC_PLL_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_Disable(void) +{ + 8002d44: b480 push {r7} + 8002d46: af00 add r7, sp, #0 + CLEAR_BIT(RCC->CR, RCC_CR_PLLON); + 8002d48: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002d4c: 681b ldr r3, [r3, #0] + 8002d4e: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 8002d52: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000 + 8002d56: 6013 str r3, [r2, #0] +} + 8002d58: bf00 nop + 8002d5a: 46bd mov sp, r7 + 8002d5c: bc80 pop {r7} + 8002d5e: 4770 bx lr + +08002d60 : + * @brief Check if PLL Ready + * @rmtoll CR PLLRDY LL_RCC_PLL_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void) +{ + 8002d60: b480 push {r7} + 8002d62: af00 add r7, sp, #0 + return ((READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY)) ? 1UL : 0UL); + 8002d64: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002d68: 681b ldr r3, [r3, #0] + 8002d6a: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 + 8002d6e: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 + 8002d72: d101 bne.n 8002d78 + 8002d74: 2301 movs r3, #1 + 8002d76: e000 b.n 8002d7a + 8002d78: 2300 movs r3, #0 +} + 8002d7a: 4618 mov r0, r3 + 8002d7c: 46bd mov sp, r7 + 8002d7e: bc80 pop {r7} + 8002d80: 4770 bx lr + +08002d82 : + * @brief Get Main PLL multiplication factor for VCO + * @rmtoll PLLCFGR PLLN LL_RCC_PLL_GetN + * @retval Between 6 and 127 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_GetN(void) +{ + 8002d82: b480 push {r7} + 8002d84: af00 add r7, sp, #0 + return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); + 8002d86: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002d8a: 68db ldr r3, [r3, #12] + 8002d8c: 0a1b lsrs r3, r3, #8 + 8002d8e: f003 037f and.w r3, r3, #127 @ 0x7f +} + 8002d92: 4618 mov r0, r3 + 8002d94: 46bd mov sp, r7 + 8002d96: bc80 pop {r7} + 8002d98: 4770 bx lr + +08002d9a : + * @arg @ref LL_RCC_PLLR_DIV_6 + * @arg @ref LL_RCC_PLLR_DIV_7 + * @arg @ref LL_RCC_PLLR_DIV_8 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_GetR(void) +{ + 8002d9a: b480 push {r7} + 8002d9c: af00 add r7, sp, #0 + return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR)); + 8002d9e: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002da2: 68db ldr r3, [r3, #12] + 8002da4: f003 4360 and.w r3, r3, #3758096384 @ 0xe0000000 +} + 8002da8: 4618 mov r0, r3 + 8002daa: 46bd mov sp, r7 + 8002dac: bc80 pop {r7} + 8002dae: 4770 bx lr + +08002db0 : + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_GetDivider(void) +{ + 8002db0: b480 push {r7} + 8002db2: af00 add r7, sp, #0 + return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM)); + 8002db4: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002db8: 68db ldr r3, [r3, #12] + 8002dba: f003 0370 and.w r3, r3, #112 @ 0x70 +} + 8002dbe: 4618 mov r0, r3 + 8002dc0: 46bd mov sp, r7 + 8002dc2: bc80 pop {r7} + 8002dc4: 4770 bx lr + +08002dc6 : + * @arg @ref LL_RCC_PLLSOURCE_MSI + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void) +{ + 8002dc6: b480 push {r7} + 8002dc8: af00 add r7, sp, #0 + return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC)); + 8002dca: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002dce: 68db ldr r3, [r3, #12] + 8002dd0: f003 0303 and.w r3, r3, #3 +} + 8002dd4: 4618 mov r0, r3 + 8002dd6: 46bd mov sp, r7 + 8002dd8: bc80 pop {r7} + 8002dda: 4770 bx lr + +08002ddc : + * @brief Check if HCLK1 prescaler flag value has been applied or not + * @rmtoll CFGR HPREF LL_RCC_IsActiveFlag_HPRE + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HPRE(void) +{ + 8002ddc: b480 push {r7} + 8002dde: af00 add r7, sp, #0 + return ((READ_BIT(RCC->CFGR, RCC_CFGR_HPREF) == (RCC_CFGR_HPREF)) ? 1UL : 0UL); + 8002de0: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002de4: 689b ldr r3, [r3, #8] + 8002de6: f403 3380 and.w r3, r3, #65536 @ 0x10000 + 8002dea: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 + 8002dee: d101 bne.n 8002df4 + 8002df0: 2301 movs r3, #1 + 8002df2: e000 b.n 8002df6 + 8002df4: 2300 movs r3, #0 +} + 8002df6: 4618 mov r0, r3 + 8002df8: 46bd mov sp, r7 + 8002dfa: bc80 pop {r7} + 8002dfc: 4770 bx lr + +08002dfe : + * @brief Check if HCLK2 prescaler flag value has been applied or not + * @rmtoll EXTCFGR C2HPREF LL_RCC_IsActiveFlag_C2HPRE + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_C2HPRE(void) +{ + 8002dfe: b480 push {r7} + 8002e00: af00 add r7, sp, #0 + return ((READ_BIT(RCC->EXTCFGR, RCC_EXTCFGR_C2HPREF) == (RCC_EXTCFGR_C2HPREF)) ? 1UL : 0UL); + 8002e02: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002e06: f8d3 3108 ldr.w r3, [r3, #264] @ 0x108 + 8002e0a: f403 3300 and.w r3, r3, #131072 @ 0x20000 + 8002e0e: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 + 8002e12: d101 bne.n 8002e18 + 8002e14: 2301 movs r3, #1 + 8002e16: e000 b.n 8002e1a + 8002e18: 2300 movs r3, #0 +} + 8002e1a: 4618 mov r0, r3 + 8002e1c: 46bd mov sp, r7 + 8002e1e: bc80 pop {r7} + 8002e20: 4770 bx lr + +08002e22 : + * @brief Check if HCLK3 prescaler flag value has been applied or not + * @rmtoll EXTCFGR SHDHPREF LL_RCC_IsActiveFlag_SHDHPRE + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SHDHPRE(void) +{ + 8002e22: b480 push {r7} + 8002e24: af00 add r7, sp, #0 + return ((READ_BIT(RCC->EXTCFGR, RCC_EXTCFGR_SHDHPREF) == (RCC_EXTCFGR_SHDHPREF)) ? 1UL : 0UL); + 8002e26: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002e2a: f8d3 3108 ldr.w r3, [r3, #264] @ 0x108 + 8002e2e: f403 3380 and.w r3, r3, #65536 @ 0x10000 + 8002e32: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 + 8002e36: d101 bne.n 8002e3c + 8002e38: 2301 movs r3, #1 + 8002e3a: e000 b.n 8002e3e + 8002e3c: 2300 movs r3, #0 +} + 8002e3e: 4618 mov r0, r3 + 8002e40: 46bd mov sp, r7 + 8002e42: bc80 pop {r7} + 8002e44: 4770 bx lr + +08002e46 : + * @brief Check if PLCK1 prescaler flag value has been applied or not + * @rmtoll CFGR PPRE1F LL_RCC_IsActiveFlag_PPRE1 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PPRE1(void) +{ + 8002e46: b480 push {r7} + 8002e48: af00 add r7, sp, #0 + return ((READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1F) == (RCC_CFGR_PPRE1F)) ? 1UL : 0UL); + 8002e4a: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002e4e: 689b ldr r3, [r3, #8] + 8002e50: f403 3300 and.w r3, r3, #131072 @ 0x20000 + 8002e54: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 + 8002e58: d101 bne.n 8002e5e + 8002e5a: 2301 movs r3, #1 + 8002e5c: e000 b.n 8002e60 + 8002e5e: 2300 movs r3, #0 +} + 8002e60: 4618 mov r0, r3 + 8002e62: 46bd mov sp, r7 + 8002e64: bc80 pop {r7} + 8002e66: 4770 bx lr + +08002e68 : + * @brief Check if PLCK2 prescaler flag value has been applied or not + * @rmtoll CFGR PPRE2F LL_RCC_IsActiveFlag_PPRE2 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PPRE2(void) +{ + 8002e68: b480 push {r7} + 8002e6a: af00 add r7, sp, #0 + return ((READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2F) == (RCC_CFGR_PPRE2F)) ? 1UL : 0UL); + 8002e6c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002e70: 689b ldr r3, [r3, #8] + 8002e72: f403 2380 and.w r3, r3, #262144 @ 0x40000 + 8002e76: f5b3 2f80 cmp.w r3, #262144 @ 0x40000 + 8002e7a: d101 bne.n 8002e80 + 8002e7c: 2301 movs r3, #1 + 8002e7e: e000 b.n 8002e82 + 8002e80: 2300 movs r3, #0 +} + 8002e82: 4618 mov r0, r3 + 8002e84: 46bd mov sp, r7 + 8002e86: bc80 pop {r7} + 8002e88: 4770 bx lr + ... + +08002e8c : + * contains the configuration information for the RCC Oscillators. + * @note The PLL is not disabled when used as system clock. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) +{ + 8002e8c: b580 push {r7, lr} + 8002e8e: b088 sub sp, #32 + 8002e90: af00 add r7, sp, #0 + 8002e92: 6078 str r0, [r7, #4] + uint32_t sysclk_source; + uint32_t pll_config; + HAL_StatusTypeDef status; + + /* Check Null pointer */ + if (RCC_OscInitStruct == NULL) + 8002e94: 687b ldr r3, [r7, #4] + 8002e96: 2b00 cmp r3, #0 + 8002e98: d101 bne.n 8002e9e + { + return HAL_ERROR; + 8002e9a: 2301 movs r3, #1 + 8002e9c: e36f b.n 800357e + } + + /* Check the parameters */ + assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); + + sysclk_source = __HAL_RCC_GET_SYSCLK_SOURCE(); + 8002e9e: f7ff fea6 bl 8002bee + 8002ea2: 61f8 str r0, [r7, #28] + pll_config = __HAL_RCC_GET_PLL_OSCSOURCE(); + 8002ea4: f7ff ff8f bl 8002dc6 + 8002ea8: 61b8 str r0, [r7, #24] + + /*----------------------------- MSI Configuration --------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI) + 8002eaa: 687b ldr r3, [r7, #4] + 8002eac: 681b ldr r3, [r3, #0] + 8002eae: f003 0320 and.w r3, r3, #32 + 8002eb2: 2b00 cmp r3, #0 + 8002eb4: f000 80c4 beq.w 8003040 + assert_param(IS_RCC_MSI(RCC_OscInitStruct->MSIState)); + assert_param(IS_RCC_MSI_CALIBRATION_VALUE(RCC_OscInitStruct->MSICalibrationValue)); + assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange)); + + /* When the MSI is used as system clock it will not be disabled */ + if ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_MSI) || + 8002eb8: 69fb ldr r3, [r7, #28] + 8002eba: 2b00 cmp r3, #0 + 8002ebc: d005 beq.n 8002eca + 8002ebe: 69fb ldr r3, [r7, #28] + 8002ec0: 2b0c cmp r3, #12 + 8002ec2: d176 bne.n 8002fb2 + ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_MSI))) + 8002ec4: 69bb ldr r3, [r7, #24] + 8002ec6: 2b01 cmp r3, #1 + 8002ec8: d173 bne.n 8002fb2 + { + if (RCC_OscInitStruct->MSIState == RCC_MSI_OFF) + 8002eca: 687b ldr r3, [r7, #4] + 8002ecc: 6a1b ldr r3, [r3, #32] + 8002ece: 2b00 cmp r3, #0 + 8002ed0: d101 bne.n 8002ed6 + { + return HAL_ERROR; + 8002ed2: 2301 movs r3, #1 + 8002ed4: e353 b.n 800357e + else + { + /* To correctly read data from FLASH memory, the number of wait states (LATENCY) + must be correctly programmed according to the frequency of the AHB3 clock + and the supply voltage of the device. */ + if (RCC_OscInitStruct->MSIClockRange > __HAL_RCC_GET_MSI_RANGE()) + 8002ed6: 687b ldr r3, [r7, #4] + 8002ed8: 6a9a ldr r2, [r3, #40] @ 0x28 + 8002eda: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002ede: 681b ldr r3, [r3, #0] + 8002ee0: f003 0308 and.w r3, r3, #8 + 8002ee4: 2b00 cmp r3, #0 + 8002ee6: d005 beq.n 8002ef4 + 8002ee8: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002eec: 681b ldr r3, [r3, #0] + 8002eee: f003 03f0 and.w r3, r3, #240 @ 0xf0 + 8002ef2: e006 b.n 8002f02 + 8002ef4: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002ef8: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 + 8002efc: 091b lsrs r3, r3, #4 + 8002efe: f003 03f0 and.w r3, r3, #240 @ 0xf0 + 8002f02: 4293 cmp r3, r2 + 8002f04: d222 bcs.n 8002f4c + { + /* First increase number of wait states update if necessary */ + if (RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK) + 8002f06: 687b ldr r3, [r7, #4] + 8002f08: 6a9b ldr r3, [r3, #40] @ 0x28 + 8002f0a: 4618 mov r0, r3 + 8002f0c: f000 fd5a bl 80039c4 + 8002f10: 4603 mov r3, r0 + 8002f12: 2b00 cmp r3, #0 + 8002f14: d001 beq.n 8002f1a + { + return HAL_ERROR; + 8002f16: 2301 movs r3, #1 + 8002f18: e331 b.n 800357e + } + + /* Selects the Multiple Speed oscillator (MSI) clock range .*/ + __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange); + 8002f1a: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002f1e: 681b ldr r3, [r3, #0] + 8002f20: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 8002f24: f043 0308 orr.w r3, r3, #8 + 8002f28: 6013 str r3, [r2, #0] + 8002f2a: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002f2e: 681b ldr r3, [r3, #0] + 8002f30: f023 02f0 bic.w r2, r3, #240 @ 0xf0 + 8002f34: 687b ldr r3, [r7, #4] + 8002f36: 6a9b ldr r3, [r3, #40] @ 0x28 + 8002f38: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 8002f3c: 4313 orrs r3, r2 + 8002f3e: 600b str r3, [r1, #0] + /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/ + __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue); + 8002f40: 687b ldr r3, [r7, #4] + 8002f42: 6a5b ldr r3, [r3, #36] @ 0x24 + 8002f44: 4618 mov r0, r3 + 8002f46: f7ff fe2b bl 8002ba0 + 8002f4a: e021 b.n 8002f90 + } + else + { + /* Else, keep current flash latency while decreasing applies */ + /* Selects the Multiple Speed oscillator (MSI) clock range. */ + __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange); + 8002f4c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002f50: 681b ldr r3, [r3, #0] + 8002f52: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 8002f56: f043 0308 orr.w r3, r3, #8 + 8002f5a: 6013 str r3, [r2, #0] + 8002f5c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002f60: 681b ldr r3, [r3, #0] + 8002f62: f023 02f0 bic.w r2, r3, #240 @ 0xf0 + 8002f66: 687b ldr r3, [r7, #4] + 8002f68: 6a9b ldr r3, [r3, #40] @ 0x28 + 8002f6a: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 8002f6e: 4313 orrs r3, r2 + 8002f70: 600b str r3, [r1, #0] + /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/ + __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue); + 8002f72: 687b ldr r3, [r7, #4] + 8002f74: 6a5b ldr r3, [r3, #36] @ 0x24 + 8002f76: 4618 mov r0, r3 + 8002f78: f7ff fe12 bl 8002ba0 + + /* Decrease number of wait states update if necessary */ + if (RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK) + 8002f7c: 687b ldr r3, [r7, #4] + 8002f7e: 6a9b ldr r3, [r3, #40] @ 0x28 + 8002f80: 4618 mov r0, r3 + 8002f82: f000 fd1f bl 80039c4 + 8002f86: 4603 mov r3, r0 + 8002f88: 2b00 cmp r3, #0 + 8002f8a: d001 beq.n 8002f90 + { + return HAL_ERROR; + 8002f8c: 2301 movs r3, #1 + 8002f8e: e2f6 b.n 800357e + } + } + + /* Update the SystemCoreClock global variable */ + SystemCoreClock = HAL_RCC_GetHCLKFreq(); + 8002f90: f000 fce0 bl 8003954 + 8002f94: 4603 mov r3, r0 + 8002f96: 4aa7 ldr r2, [pc, #668] @ (8003234 ) + 8002f98: 6013 str r3, [r2, #0] + + /* Configure the source of time base considering new system clocks settings */ + status = HAL_InitTick(uwTickPrio); + 8002f9a: 4ba7 ldr r3, [pc, #668] @ (8003238 ) + 8002f9c: 681b ldr r3, [r3, #0] + 8002f9e: 4618 mov r0, r3 + 8002fa0: f7fd fde4 bl 8000b6c + 8002fa4: 4603 mov r3, r0 + 8002fa6: 74fb strb r3, [r7, #19] + if (status != HAL_OK) + 8002fa8: 7cfb ldrb r3, [r7, #19] + 8002faa: 2b00 cmp r3, #0 + 8002fac: d047 beq.n 800303e + { + return status; + 8002fae: 7cfb ldrb r3, [r7, #19] + 8002fb0: e2e5 b.n 800357e + } + } + else + { + /* Check the MSI State */ + if (RCC_OscInitStruct->MSIState != RCC_MSI_OFF) + 8002fb2: 687b ldr r3, [r7, #4] + 8002fb4: 6a1b ldr r3, [r3, #32] + 8002fb6: 2b00 cmp r3, #0 + 8002fb8: d02c beq.n 8003014 + { + /* Enable the Internal High Speed oscillator (MSI). */ + __HAL_RCC_MSI_ENABLE(); + 8002fba: f7ff fd9e bl 8002afa + + /* Get timeout */ + tickstart = HAL_GetTick(); + 8002fbe: f7fd fddf bl 8000b80 + 8002fc2: 6178 str r0, [r7, #20] + + /* Wait till MSI is ready */ + while (LL_RCC_MSI_IsReady() == 0U) + 8002fc4: e008 b.n 8002fd8 + { + if ((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE) + 8002fc6: f7fd fddb bl 8000b80 + 8002fca: 4602 mov r2, r0 + 8002fcc: 697b ldr r3, [r7, #20] + 8002fce: 1ad3 subs r3, r2, r3 + 8002fd0: 2b02 cmp r3, #2 + 8002fd2: d901 bls.n 8002fd8 + { + return HAL_TIMEOUT; + 8002fd4: 2303 movs r3, #3 + 8002fd6: e2d2 b.n 800357e + while (LL_RCC_MSI_IsReady() == 0U) + 8002fd8: f7ff fdab bl 8002b32 + 8002fdc: 4603 mov r3, r0 + 8002fde: 2b00 cmp r3, #0 + 8002fe0: d0f1 beq.n 8002fc6 + } + } + + /* Selects the Multiple Speed oscillator (MSI) clock range. */ + __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange); + 8002fe2: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002fe6: 681b ldr r3, [r3, #0] + 8002fe8: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 8002fec: f043 0308 orr.w r3, r3, #8 + 8002ff0: 6013 str r3, [r2, #0] + 8002ff2: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002ff6: 681b ldr r3, [r3, #0] + 8002ff8: f023 02f0 bic.w r2, r3, #240 @ 0xf0 + 8002ffc: 687b ldr r3, [r7, #4] + 8002ffe: 6a9b ldr r3, [r3, #40] @ 0x28 + 8003000: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 8003004: 4313 orrs r3, r2 + 8003006: 600b str r3, [r1, #0] + /* Adjusts the Multiple Speed oscillator (MSI) calibration value. */ + __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue); + 8003008: 687b ldr r3, [r7, #4] + 800300a: 6a5b ldr r3, [r3, #36] @ 0x24 + 800300c: 4618 mov r0, r3 + 800300e: f7ff fdc7 bl 8002ba0 + 8003012: e015 b.n 8003040 + + } + else + { + /* Disable the Internal High Speed oscillator (MSI). */ + __HAL_RCC_MSI_DISABLE(); + 8003014: f7ff fd7f bl 8002b16 + + /* Get timeout */ + tickstart = HAL_GetTick(); + 8003018: f7fd fdb2 bl 8000b80 + 800301c: 6178 str r0, [r7, #20] + + /* Wait till MSI is disabled */ + while (LL_RCC_MSI_IsReady() != 0U) + 800301e: e008 b.n 8003032 + { + if ((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE) + 8003020: f7fd fdae bl 8000b80 + 8003024: 4602 mov r2, r0 + 8003026: 697b ldr r3, [r7, #20] + 8003028: 1ad3 subs r3, r2, r3 + 800302a: 2b02 cmp r3, #2 + 800302c: d901 bls.n 8003032 + { + return HAL_TIMEOUT; + 800302e: 2303 movs r3, #3 + 8003030: e2a5 b.n 800357e + while (LL_RCC_MSI_IsReady() != 0U) + 8003032: f7ff fd7e bl 8002b32 + 8003036: 4603 mov r3, r0 + 8003038: 2b00 cmp r3, #0 + 800303a: d1f1 bne.n 8003020 + 800303c: e000 b.n 8003040 + if (RCC_OscInitStruct->MSIState == RCC_MSI_OFF) + 800303e: bf00 nop + } + } + } + + /*------------------------------- HSE Configuration ------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) + 8003040: 687b ldr r3, [r7, #4] + 8003042: 681b ldr r3, [r3, #0] + 8003044: f003 0301 and.w r3, r3, #1 + 8003048: 2b00 cmp r3, #0 + 800304a: d058 beq.n 80030fe + { + /* Check the parameters */ + assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); + + /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ + if ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSE) || + 800304c: 69fb ldr r3, [r7, #28] + 800304e: 2b08 cmp r3, #8 + 8003050: d005 beq.n 800305e + 8003052: 69fb ldr r3, [r7, #28] + 8003054: 2b0c cmp r3, #12 + 8003056: d108 bne.n 800306a + ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_HSE))) + 8003058: 69bb ldr r3, [r7, #24] + 800305a: 2b03 cmp r3, #3 + 800305c: d105 bne.n 800306a + { + if (RCC_OscInitStruct->HSEState == RCC_HSE_OFF) + 800305e: 687b ldr r3, [r7, #4] + 8003060: 685b ldr r3, [r3, #4] + 8003062: 2b00 cmp r3, #0 + 8003064: d14b bne.n 80030fe + { + return HAL_ERROR; + 8003066: 2301 movs r3, #1 + 8003068: e289 b.n 800357e + /* Set the new HSE configuration ---------------------------------------*/ + /* Check HSE division factor */ + assert_param(IS_RCC_HSEDIV(RCC_OscInitStruct->HSEDiv)); + + /* Set HSE division factor */ + MODIFY_REG(RCC->CR, RCC_CR_HSEPRE, RCC_OscInitStruct->HSEDiv); + 800306a: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 800306e: 681b ldr r3, [r3, #0] + 8003070: f423 1280 bic.w r2, r3, #1048576 @ 0x100000 + 8003074: 687b ldr r3, [r7, #4] + 8003076: 689b ldr r3, [r3, #8] + 8003078: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 800307c: 4313 orrs r3, r2 + 800307e: 600b str r3, [r1, #0] + + __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); + 8003080: 687b ldr r3, [r7, #4] + 8003082: 685b ldr r3, [r3, #4] + 8003084: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 + 8003088: d102 bne.n 8003090 + 800308a: f7ff fc86 bl 800299a + 800308e: e00d b.n 80030ac + 8003090: 687b ldr r3, [r7, #4] + 8003092: 685b ldr r3, [r3, #4] + 8003094: f5b3 1f04 cmp.w r3, #2162688 @ 0x210000 + 8003098: d104 bne.n 80030a4 + 800309a: f7ff fc51 bl 8002940 + 800309e: f7ff fc7c bl 800299a + 80030a2: e003 b.n 80030ac + 80030a4: f7ff fc87 bl 80029b6 + 80030a8: f7ff fc58 bl 800295c + + /* Check the HSE State */ + if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF) + 80030ac: 687b ldr r3, [r7, #4] + 80030ae: 685b ldr r3, [r3, #4] + 80030b0: 2b00 cmp r3, #0 + 80030b2: d012 beq.n 80030da + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 80030b4: f7fd fd64 bl 8000b80 + 80030b8: 6178 str r0, [r7, #20] + + /* Wait till HSE is ready */ + while (LL_RCC_HSE_IsReady() == 0U) + 80030ba: e008 b.n 80030ce + { + if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) + 80030bc: f7fd fd60 bl 8000b80 + 80030c0: 4602 mov r2, r0 + 80030c2: 697b ldr r3, [r7, #20] + 80030c4: 1ad3 subs r3, r2, r3 + 80030c6: 2b64 cmp r3, #100 @ 0x64 + 80030c8: d901 bls.n 80030ce + { + return HAL_TIMEOUT; + 80030ca: 2303 movs r3, #3 + 80030cc: e257 b.n 800357e + while (LL_RCC_HSE_IsReady() == 0U) + 80030ce: f7ff fc80 bl 80029d2 + 80030d2: 4603 mov r3, r0 + 80030d4: 2b00 cmp r3, #0 + 80030d6: d0f1 beq.n 80030bc + 80030d8: e011 b.n 80030fe + } + } + else + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 80030da: f7fd fd51 bl 8000b80 + 80030de: 6178 str r0, [r7, #20] + + /* Wait till HSE is disabled */ + while (LL_RCC_HSE_IsReady() != 0U) + 80030e0: e008 b.n 80030f4 + { + if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) + 80030e2: f7fd fd4d bl 8000b80 + 80030e6: 4602 mov r2, r0 + 80030e8: 697b ldr r3, [r7, #20] + 80030ea: 1ad3 subs r3, r2, r3 + 80030ec: 2b64 cmp r3, #100 @ 0x64 + 80030ee: d901 bls.n 80030f4 + { + return HAL_TIMEOUT; + 80030f0: 2303 movs r3, #3 + 80030f2: e244 b.n 800357e + while (LL_RCC_HSE_IsReady() != 0U) + 80030f4: f7ff fc6d bl 80029d2 + 80030f8: 4603 mov r3, r0 + 80030fa: 2b00 cmp r3, #0 + 80030fc: d1f1 bne.n 80030e2 + } + } + } + + /*----------------------------- HSI Configuration --------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) + 80030fe: 687b ldr r3, [r7, #4] + 8003100: 681b ldr r3, [r3, #0] + 8003102: f003 0302 and.w r3, r3, #2 + 8003106: 2b00 cmp r3, #0 + 8003108: d046 beq.n 8003198 + /* Check the parameters */ + assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); + assert_param(IS_RCC_HSI_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); + + /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ + if ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSI) || + 800310a: 69fb ldr r3, [r7, #28] + 800310c: 2b04 cmp r3, #4 + 800310e: d005 beq.n 800311c + 8003110: 69fb ldr r3, [r7, #28] + 8003112: 2b0c cmp r3, #12 + 8003114: d10e bne.n 8003134 + ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_HSI))) + 8003116: 69bb ldr r3, [r7, #24] + 8003118: 2b02 cmp r3, #2 + 800311a: d10b bne.n 8003134 + { + /* When HSI is used as system clock it will not be disabled */ + if (RCC_OscInitStruct->HSIState == RCC_HSI_OFF) + 800311c: 687b ldr r3, [r7, #4] + 800311e: 691b ldr r3, [r3, #16] + 8003120: 2b00 cmp r3, #0 + 8003122: d101 bne.n 8003128 + { + return HAL_ERROR; + 8003124: 2301 movs r3, #1 + 8003126: e22a b.n 800357e + } + /* Otherwise, just the calibration is allowed */ + else + { + /* Adjusts the Internal High Speed oscillator (HSI) calibration value. */ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + 8003128: 687b ldr r3, [r7, #4] + 800312a: 695b ldr r3, [r3, #20] + 800312c: 4618 mov r0, r3 + 800312e: f7ff fc8e bl 8002a4e + if (RCC_OscInitStruct->HSIState == RCC_HSI_OFF) + 8003132: e031 b.n 8003198 + } + } + else + { + /* Check the HSI State */ + if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF) + 8003134: 687b ldr r3, [r7, #4] + 8003136: 691b ldr r3, [r3, #16] + 8003138: 2b00 cmp r3, #0 + 800313a: d019 beq.n 8003170 + { + /* Enable the Internal High Speed oscillator (HSI). */ + __HAL_RCC_HSI_ENABLE(); + 800313c: f7ff fc5a bl 80029f4 + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8003140: f7fd fd1e bl 8000b80 + 8003144: 6178 str r0, [r7, #20] + + /* Wait till HSI is ready */ + while (LL_RCC_HSI_IsReady() == 0U) + 8003146: e008 b.n 800315a + { + if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) + 8003148: f7fd fd1a bl 8000b80 + 800314c: 4602 mov r2, r0 + 800314e: 697b ldr r3, [r7, #20] + 8003150: 1ad3 subs r3, r2, r3 + 8003152: 2b02 cmp r3, #2 + 8003154: d901 bls.n 800315a + { + return HAL_TIMEOUT; + 8003156: 2303 movs r3, #3 + 8003158: e211 b.n 800357e + while (LL_RCC_HSI_IsReady() == 0U) + 800315a: f7ff fc67 bl 8002a2c + 800315e: 4603 mov r3, r0 + 8003160: 2b00 cmp r3, #0 + 8003162: d0f1 beq.n 8003148 + } + } + + /* Adjusts the Internal High Speed oscillator (HSI) calibration value. */ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + 8003164: 687b ldr r3, [r7, #4] + 8003166: 695b ldr r3, [r3, #20] + 8003168: 4618 mov r0, r3 + 800316a: f7ff fc70 bl 8002a4e + 800316e: e013 b.n 8003198 + } + else + { + /* Disable the Internal High Speed oscillator (HSI). */ + __HAL_RCC_HSI_DISABLE(); + 8003170: f7ff fc4e bl 8002a10 + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8003174: f7fd fd04 bl 8000b80 + 8003178: 6178 str r0, [r7, #20] + + /* Wait till HSI is disabled */ + while (LL_RCC_HSI_IsReady() != 0U) + 800317a: e008 b.n 800318e + { + if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) + 800317c: f7fd fd00 bl 8000b80 + 8003180: 4602 mov r2, r0 + 8003182: 697b ldr r3, [r7, #20] + 8003184: 1ad3 subs r3, r2, r3 + 8003186: 2b02 cmp r3, #2 + 8003188: d901 bls.n 800318e + { + return HAL_TIMEOUT; + 800318a: 2303 movs r3, #3 + 800318c: e1f7 b.n 800357e + while (LL_RCC_HSI_IsReady() != 0U) + 800318e: f7ff fc4d bl 8002a2c + 8003192: 4603 mov r3, r0 + 8003194: 2b00 cmp r3, #0 + 8003196: d1f1 bne.n 800317c + } + } + } + + /*------------------------------ LSI Configuration -------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) + 8003198: 687b ldr r3, [r7, #4] + 800319a: 681b ldr r3, [r3, #0] + 800319c: f003 0308 and.w r3, r3, #8 + 80031a0: 2b00 cmp r3, #0 + 80031a2: d06e beq.n 8003282 + { + /* Check the parameters */ + assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); + + /* Check the LSI State */ + if (RCC_OscInitStruct->LSIState != RCC_LSI_OFF) + 80031a4: 687b ldr r3, [r7, #4] + 80031a6: 699b ldr r3, [r3, #24] + 80031a8: 2b00 cmp r3, #0 + 80031aa: d056 beq.n 800325a + { + uint32_t csr_temp = RCC->CSR; + 80031ac: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 80031b0: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 + 80031b4: 60fb str r3, [r7, #12] + + /* Check LSI division factor */ + assert_param(IS_RCC_LSIDIV(RCC_OscInitStruct->LSIDiv)); + + if (RCC_OscInitStruct->LSIDiv != (csr_temp & RCC_CSR_LSIPRE)) + 80031b6: 687b ldr r3, [r7, #4] + 80031b8: 69da ldr r2, [r3, #28] + 80031ba: 68fb ldr r3, [r7, #12] + 80031bc: f003 0310 and.w r3, r3, #16 + 80031c0: 429a cmp r2, r3 + 80031c2: d031 beq.n 8003228 + { + if (((csr_temp & RCC_CSR_LSIRDY) == RCC_CSR_LSIRDY) && \ + 80031c4: 68fb ldr r3, [r7, #12] + 80031c6: f003 0302 and.w r3, r3, #2 + 80031ca: 2b00 cmp r3, #0 + 80031cc: d006 beq.n 80031dc + ((csr_temp & RCC_CSR_LSION) != RCC_CSR_LSION)) + 80031ce: 68fb ldr r3, [r7, #12] + 80031d0: f003 0301 and.w r3, r3, #1 + if (((csr_temp & RCC_CSR_LSIRDY) == RCC_CSR_LSIRDY) && \ + 80031d4: 2b00 cmp r3, #0 + 80031d6: d101 bne.n 80031dc + { + /* If LSIRDY is set while LSION is not enabled, + LSIPRE can't be updated */ + return HAL_ERROR; + 80031d8: 2301 movs r3, #1 + 80031da: e1d0 b.n 800357e + } + + /* Turn off LSI before changing RCC_CSR_LSIPRE */ + if ((csr_temp & RCC_CSR_LSION) == RCC_CSR_LSION) + 80031dc: 68fb ldr r3, [r7, #12] + 80031de: f003 0301 and.w r3, r3, #1 + 80031e2: 2b00 cmp r3, #0 + 80031e4: d013 beq.n 800320e + { + __HAL_RCC_LSI_DISABLE(); + 80031e6: f7ff fc67 bl 8002ab8 + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 80031ea: f7fd fcc9 bl 8000b80 + 80031ee: 6178 str r0, [r7, #20] + + /* Wait till LSI is disabled */ + while (LL_RCC_LSI_IsReady() != 0U) + 80031f0: e008 b.n 8003204 + { + if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) + 80031f2: f7fd fcc5 bl 8000b80 + 80031f6: 4602 mov r2, r0 + 80031f8: 697b ldr r3, [r7, #20] + 80031fa: 1ad3 subs r3, r2, r3 + 80031fc: 2b11 cmp r3, #17 + 80031fe: d901 bls.n 8003204 + { + return HAL_TIMEOUT; + 8003200: 2303 movs r3, #3 + 8003202: e1bc b.n 800357e + while (LL_RCC_LSI_IsReady() != 0U) + 8003204: f7ff fc68 bl 8002ad8 + 8003208: 4603 mov r3, r0 + 800320a: 2b00 cmp r3, #0 + 800320c: d1f1 bne.n 80031f2 + } + } + } + + /* Set LSI division factor */ + MODIFY_REG(RCC->CSR, RCC_CSR_LSIPRE, RCC_OscInitStruct->LSIDiv); + 800320e: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8003212: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 + 8003216: f023 0210 bic.w r2, r3, #16 + 800321a: 687b ldr r3, [r7, #4] + 800321c: 69db ldr r3, [r3, #28] + 800321e: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 8003222: 4313 orrs r3, r2 + 8003224: f8c1 3094 str.w r3, [r1, #148] @ 0x94 + } + + /* Enable the Internal Low Speed oscillator (LSI). */ + __HAL_RCC_LSI_ENABLE(); + 8003228: f7ff fc36 bl 8002a98 + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 800322c: f7fd fca8 bl 8000b80 + 8003230: 6178 str r0, [r7, #20] + + /* Wait till LSI is ready */ + while (LL_RCC_LSI_IsReady() == 0U) + 8003232: e00c b.n 800324e + 8003234: 20000000 .word 0x20000000 + 8003238: 20000004 .word 0x20000004 + { + if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) + 800323c: f7fd fca0 bl 8000b80 + 8003240: 4602 mov r2, r0 + 8003242: 697b ldr r3, [r7, #20] + 8003244: 1ad3 subs r3, r2, r3 + 8003246: 2b11 cmp r3, #17 + 8003248: d901 bls.n 800324e + { + return HAL_TIMEOUT; + 800324a: 2303 movs r3, #3 + 800324c: e197 b.n 800357e + while (LL_RCC_LSI_IsReady() == 0U) + 800324e: f7ff fc43 bl 8002ad8 + 8003252: 4603 mov r3, r0 + 8003254: 2b00 cmp r3, #0 + 8003256: d0f1 beq.n 800323c + 8003258: e013 b.n 8003282 + } + } + else + { + /* Disable the Internal Low Speed oscillator (LSI). */ + __HAL_RCC_LSI_DISABLE(); + 800325a: f7ff fc2d bl 8002ab8 + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 800325e: f7fd fc8f bl 8000b80 + 8003262: 6178 str r0, [r7, #20] + + /* Wait till LSI is disabled */ + while (LL_RCC_LSI_IsReady() != 0U) + 8003264: e008 b.n 8003278 + { + if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) + 8003266: f7fd fc8b bl 8000b80 + 800326a: 4602 mov r2, r0 + 800326c: 697b ldr r3, [r7, #20] + 800326e: 1ad3 subs r3, r2, r3 + 8003270: 2b11 cmp r3, #17 + 8003272: d901 bls.n 8003278 + { + return HAL_TIMEOUT; + 8003274: 2303 movs r3, #3 + 8003276: e182 b.n 800357e + while (LL_RCC_LSI_IsReady() != 0U) + 8003278: f7ff fc2e bl 8002ad8 + 800327c: 4603 mov r3, r0 + 800327e: 2b00 cmp r3, #0 + 8003280: d1f1 bne.n 8003266 + } + } + } + + /*------------------------------ LSE Configuration -------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) + 8003282: 687b ldr r3, [r7, #4] + 8003284: 681b ldr r3, [r3, #0] + 8003286: f003 0304 and.w r3, r3, #4 + 800328a: 2b00 cmp r3, #0 + 800328c: f000 80d8 beq.w 8003440 + assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); + + /* Update LSE configuration in Backup Domain control register */ + /* Requires to enable write access to Backup Domain of necessary */ + + if (LL_PWR_IsEnabledBkUpAccess() == 0U) + 8003290: f7ff fb44 bl 800291c + 8003294: 4603 mov r3, r0 + 8003296: 2b00 cmp r3, #0 + 8003298: d113 bne.n 80032c2 + { + /* Enable write access to Backup domain */ + HAL_PWR_EnableBkUpAccess(); + 800329a: f7ff fa83 bl 80027a4 + + /* Wait for Backup domain Write protection disable */ + tickstart = HAL_GetTick(); + 800329e: f7fd fc6f bl 8000b80 + 80032a2: 6178 str r0, [r7, #20] + + while (LL_PWR_IsEnabledBkUpAccess() == 0U) + 80032a4: e008 b.n 80032b8 + { + if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + 80032a6: f7fd fc6b bl 8000b80 + 80032aa: 4602 mov r2, r0 + 80032ac: 697b ldr r3, [r7, #20] + 80032ae: 1ad3 subs r3, r2, r3 + 80032b0: 2b02 cmp r3, #2 + 80032b2: d901 bls.n 80032b8 + { + return HAL_TIMEOUT; + 80032b4: 2303 movs r3, #3 + 80032b6: e162 b.n 800357e + while (LL_PWR_IsEnabledBkUpAccess() == 0U) + 80032b8: f7ff fb30 bl 800291c + 80032bc: 4603 mov r3, r0 + 80032be: 2b00 cmp r3, #0 + 80032c0: d0f1 beq.n 80032a6 + } + } + } + + /* Set the new LSE configuration -----------------------------------------*/ + if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF) + 80032c2: 687b ldr r3, [r7, #4] + 80032c4: 68db ldr r3, [r3, #12] + 80032c6: 2b00 cmp r3, #0 + 80032c8: d07b beq.n 80033c2 + { + /* Enable LSE bypasss (if requested) */ + if ((RCC_OscInitStruct->LSEState == RCC_LSE_BYPASS) + 80032ca: 687b ldr r3, [r7, #4] + 80032cc: 68db ldr r3, [r3, #12] + 80032ce: 2b85 cmp r3, #133 @ 0x85 + 80032d0: d003 beq.n 80032da + || (RCC_OscInitStruct->LSEState == RCC_LSE_BYPASS_RTC_ONLY)) + 80032d2: 687b ldr r3, [r7, #4] + 80032d4: 68db ldr r3, [r3, #12] + 80032d6: 2b05 cmp r3, #5 + 80032d8: d109 bne.n 80032ee + { + /* LSE oscillator bypass enable */ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); + 80032da: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 80032de: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 80032e2: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 80032e6: f043 0304 orr.w r3, r3, #4 + 80032ea: f8c2 3090 str.w r3, [r2, #144] @ 0x90 + } + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 80032ee: f7fd fc47 bl 8000b80 + 80032f2: 6178 str r0, [r7, #20] + + /* LSE oscillator enable */ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); + 80032f4: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 80032f8: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 80032fc: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 8003300: f043 0301 orr.w r3, r3, #1 + 8003304: f8c2 3090 str.w r3, [r2, #144] @ 0x90 + + /* Wait till LSE is ready */ + while (LL_RCC_LSE_IsReady() == 0U) + 8003308: e00a b.n 8003320 + { + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + 800330a: f7fd fc39 bl 8000b80 + 800330e: 4602 mov r2, r0 + 8003310: 697b ldr r3, [r7, #20] + 8003312: 1ad3 subs r3, r2, r3 + 8003314: f241 3288 movw r2, #5000 @ 0x1388 + 8003318: 4293 cmp r3, r2 + 800331a: d901 bls.n 8003320 + { + return HAL_TIMEOUT; + 800331c: 2303 movs r3, #3 + 800331e: e12e b.n 800357e + while (LL_RCC_LSE_IsReady() == 0U) + 8003320: f7ff fba9 bl 8002a76 + 8003324: 4603 mov r3, r0 + 8003326: 2b00 cmp r3, #0 + 8003328: d0ef beq.n 800330a + } + } + + /* Enable LSE system clock (if requested) */ + if ((RCC_OscInitStruct->LSEState == RCC_LSE_ON) + 800332a: 687b ldr r3, [r7, #4] + 800332c: 68db ldr r3, [r3, #12] + 800332e: 2b81 cmp r3, #129 @ 0x81 + 8003330: d003 beq.n 800333a + || (RCC_OscInitStruct->LSEState == RCC_LSE_BYPASS)) + 8003332: 687b ldr r3, [r7, #4] + 8003334: 68db ldr r3, [r3, #12] + 8003336: 2b85 cmp r3, #133 @ 0x85 + 8003338: d121 bne.n 800337e + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 800333a: f7fd fc21 bl 8000b80 + 800333e: 6178 str r0, [r7, #20] + + SET_BIT(RCC->BDCR, RCC_BDCR_LSESYSEN); + 8003340: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8003344: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 8003348: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 800334c: f043 0380 orr.w r3, r3, #128 @ 0x80 + 8003350: f8c2 3090 str.w r3, [r2, #144] @ 0x90 + + /* Wait till LSESYS is ready */ + while (READ_BIT(RCC->BDCR, RCC_BDCR_LSESYSRDY) == 0U) + 8003354: e00a b.n 800336c + { + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + 8003356: f7fd fc13 bl 8000b80 + 800335a: 4602 mov r2, r0 + 800335c: 697b ldr r3, [r7, #20] + 800335e: 1ad3 subs r3, r2, r3 + 8003360: f241 3288 movw r2, #5000 @ 0x1388 + 8003364: 4293 cmp r3, r2 + 8003366: d901 bls.n 800336c + { + return HAL_TIMEOUT; + 8003368: 2303 movs r3, #3 + 800336a: e108 b.n 800357e + while (READ_BIT(RCC->BDCR, RCC_BDCR_LSESYSRDY) == 0U) + 800336c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8003370: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 8003374: f403 6300 and.w r3, r3, #2048 @ 0x800 + 8003378: 2b00 cmp r3, #0 + 800337a: d0ec beq.n 8003356 + if ((RCC_OscInitStruct->LSEState == RCC_LSE_ON) + 800337c: e060 b.n 8003440 + } + } + else + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 800337e: f7fd fbff bl 8000b80 + 8003382: 6178 str r0, [r7, #20] + + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSESYSEN); + 8003384: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8003388: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 800338c: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 8003390: f023 0380 bic.w r3, r3, #128 @ 0x80 + 8003394: f8c2 3090 str.w r3, [r2, #144] @ 0x90 + + /* Wait till LSESYSRDY is cleared */ + while (READ_BIT(RCC->BDCR, RCC_BDCR_LSESYSRDY) != 0U) + 8003398: e00a b.n 80033b0 + { + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + 800339a: f7fd fbf1 bl 8000b80 + 800339e: 4602 mov r2, r0 + 80033a0: 697b ldr r3, [r7, #20] + 80033a2: 1ad3 subs r3, r2, r3 + 80033a4: f241 3288 movw r2, #5000 @ 0x1388 + 80033a8: 4293 cmp r3, r2 + 80033aa: d901 bls.n 80033b0 + { + return HAL_TIMEOUT; + 80033ac: 2303 movs r3, #3 + 80033ae: e0e6 b.n 800357e + while (READ_BIT(RCC->BDCR, RCC_BDCR_LSESYSRDY) != 0U) + 80033b0: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 80033b4: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 80033b8: f403 6300 and.w r3, r3, #2048 @ 0x800 + 80033bc: 2b00 cmp r3, #0 + 80033be: d1ec bne.n 800339a + 80033c0: e03e b.n 8003440 + } + } + else + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 80033c2: f7fd fbdd bl 8000b80 + 80033c6: 6178 str r0, [r7, #20] + + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSESYSEN); + 80033c8: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 80033cc: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 80033d0: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 80033d4: f023 0380 bic.w r3, r3, #128 @ 0x80 + 80033d8: f8c2 3090 str.w r3, [r2, #144] @ 0x90 + + /* Wait till LSESYSRDY is cleared */ + while (READ_BIT(RCC->BDCR, RCC_BDCR_LSESYSRDY) != 0U) + 80033dc: e00a b.n 80033f4 + { + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + 80033de: f7fd fbcf bl 8000b80 + 80033e2: 4602 mov r2, r0 + 80033e4: 697b ldr r3, [r7, #20] + 80033e6: 1ad3 subs r3, r2, r3 + 80033e8: f241 3288 movw r2, #5000 @ 0x1388 + 80033ec: 4293 cmp r3, r2 + 80033ee: d901 bls.n 80033f4 + { + return HAL_TIMEOUT; + 80033f0: 2303 movs r3, #3 + 80033f2: e0c4 b.n 800357e + while (READ_BIT(RCC->BDCR, RCC_BDCR_LSESYSRDY) != 0U) + 80033f4: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 80033f8: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 80033fc: f403 6300 and.w r3, r3, #2048 @ 0x800 + 8003400: 2b00 cmp r3, #0 + 8003402: d1ec bne.n 80033de + } + } + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8003404: f7fd fbbc bl 8000b80 + 8003408: 6178 str r0, [r7, #20] + + /* LSE oscillator disable */ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); + 800340a: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 800340e: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 8003412: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 8003416: f023 0301 bic.w r3, r3, #1 + 800341a: f8c2 3090 str.w r3, [r2, #144] @ 0x90 + + /* Wait till LSE is disabled */ + while (LL_RCC_LSE_IsReady() != 0U) + 800341e: e00a b.n 8003436 + { + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + 8003420: f7fd fbae bl 8000b80 + 8003424: 4602 mov r2, r0 + 8003426: 697b ldr r3, [r7, #20] + 8003428: 1ad3 subs r3, r2, r3 + 800342a: f241 3288 movw r2, #5000 @ 0x1388 + 800342e: 4293 cmp r3, r2 + 8003430: d901 bls.n 8003436 + { + return HAL_TIMEOUT; + 8003432: 2303 movs r3, #3 + 8003434: e0a3 b.n 800357e + while (LL_RCC_LSE_IsReady() != 0U) + 8003436: f7ff fb1e bl 8002a76 + 800343a: 4603 mov r3, r0 + 800343c: 2b00 cmp r3, #0 + 800343e: d1ef bne.n 8003420 + + /*-------------------------------- PLL Configuration -----------------------*/ + /* Check the parameters */ + assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); + + if (RCC_OscInitStruct->PLL.PLLState != RCC_PLL_NONE) + 8003440: 687b ldr r3, [r7, #4] + 8003442: 6adb ldr r3, [r3, #44] @ 0x2c + 8003444: 2b00 cmp r3, #0 + 8003446: f000 8099 beq.w 800357c + { + /* Check if the PLL is used as system clock or not */ + if (sysclk_source != RCC_SYSCLKSOURCE_STATUS_PLLCLK) + 800344a: 69fb ldr r3, [r7, #28] + 800344c: 2b0c cmp r3, #12 + 800344e: d06c beq.n 800352a + { + if (RCC_OscInitStruct->PLL.PLLState == RCC_PLL_ON) + 8003450: 687b ldr r3, [r7, #4] + 8003452: 6adb ldr r3, [r3, #44] @ 0x2c + 8003454: 2b02 cmp r3, #2 + 8003456: d14b bne.n 80034f0 + assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP)); + assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ)); + assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR)); + + /* Disable the main PLL. */ + __HAL_RCC_PLL_DISABLE(); + 8003458: f7ff fc74 bl 8002d44 + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 800345c: f7fd fb90 bl 8000b80 + 8003460: 6178 str r0, [r7, #20] + + /* Wait till PLL is ready */ + while (LL_RCC_PLL_IsReady() != 0U) + 8003462: e008 b.n 8003476 + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + 8003464: f7fd fb8c bl 8000b80 + 8003468: 4602 mov r2, r0 + 800346a: 697b ldr r3, [r7, #20] + 800346c: 1ad3 subs r3, r2, r3 + 800346e: 2b0a cmp r3, #10 + 8003470: d901 bls.n 8003476 + { + return HAL_TIMEOUT; + 8003472: 2303 movs r3, #3 + 8003474: e083 b.n 800357e + while (LL_RCC_PLL_IsReady() != 0U) + 8003476: f7ff fc73 bl 8002d60 + 800347a: 4603 mov r3, r0 + 800347c: 2b00 cmp r3, #0 + 800347e: d1f1 bne.n 8003464 + } + } + + /* Configure the main PLL clock source, multiplication and division factors. */ + __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, + 8003480: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8003484: 68da ldr r2, [r3, #12] + 8003486: 4b40 ldr r3, [pc, #256] @ (8003588 ) + 8003488: 4013 ands r3, r2 + 800348a: 687a ldr r2, [r7, #4] + 800348c: 6b11 ldr r1, [r2, #48] @ 0x30 + 800348e: 687a ldr r2, [r7, #4] + 8003490: 6b52 ldr r2, [r2, #52] @ 0x34 + 8003492: 4311 orrs r1, r2 + 8003494: 687a ldr r2, [r7, #4] + 8003496: 6b92 ldr r2, [r2, #56] @ 0x38 + 8003498: 0212 lsls r2, r2, #8 + 800349a: 4311 orrs r1, r2 + 800349c: 687a ldr r2, [r7, #4] + 800349e: 6bd2 ldr r2, [r2, #60] @ 0x3c + 80034a0: 4311 orrs r1, r2 + 80034a2: 687a ldr r2, [r7, #4] + 80034a4: 6c12 ldr r2, [r2, #64] @ 0x40 + 80034a6: 4311 orrs r1, r2 + 80034a8: 687a ldr r2, [r7, #4] + 80034aa: 6c52 ldr r2, [r2, #68] @ 0x44 + 80034ac: 430a orrs r2, r1 + 80034ae: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 80034b2: 4313 orrs r3, r2 + 80034b4: 60cb str r3, [r1, #12] + RCC_OscInitStruct->PLL.PLLP, + RCC_OscInitStruct->PLL.PLLQ, + RCC_OscInitStruct->PLL.PLLR); + + /* Enable the main PLL. */ + __HAL_RCC_PLL_ENABLE(); + 80034b6: f7ff fc37 bl 8002d28 + + /* Enable PLL System Clock output. */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SYSCLK); + 80034ba: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 80034be: 68db ldr r3, [r3, #12] + 80034c0: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 80034c4: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 + 80034c8: 60d3 str r3, [r2, #12] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 80034ca: f7fd fb59 bl 8000b80 + 80034ce: 6178 str r0, [r7, #20] + + /* Wait till PLL is ready */ + while (LL_RCC_PLL_IsReady() == 0U) + 80034d0: e008 b.n 80034e4 + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + 80034d2: f7fd fb55 bl 8000b80 + 80034d6: 4602 mov r2, r0 + 80034d8: 697b ldr r3, [r7, #20] + 80034da: 1ad3 subs r3, r2, r3 + 80034dc: 2b0a cmp r3, #10 + 80034de: d901 bls.n 80034e4 + { + return HAL_TIMEOUT; + 80034e0: 2303 movs r3, #3 + 80034e2: e04c b.n 800357e + while (LL_RCC_PLL_IsReady() == 0U) + 80034e4: f7ff fc3c bl 8002d60 + 80034e8: 4603 mov r3, r0 + 80034ea: 2b00 cmp r3, #0 + 80034ec: d0f1 beq.n 80034d2 + 80034ee: e045 b.n 800357c + } + } + else + { + /* Disable the main PLL. */ + __HAL_RCC_PLL_DISABLE(); + 80034f0: f7ff fc28 bl 8002d44 + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 80034f4: f7fd fb44 bl 8000b80 + 80034f8: 6178 str r0, [r7, #20] + + /* Wait till PLL is disabled */ + while (LL_RCC_PLL_IsReady() != 0U) + 80034fa: e008 b.n 800350e + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + 80034fc: f7fd fb40 bl 8000b80 + 8003500: 4602 mov r2, r0 + 8003502: 697b ldr r3, [r7, #20] + 8003504: 1ad3 subs r3, r2, r3 + 8003506: 2b0a cmp r3, #10 + 8003508: d901 bls.n 800350e + { + return HAL_TIMEOUT; + 800350a: 2303 movs r3, #3 + 800350c: e037 b.n 800357e + while (LL_RCC_PLL_IsReady() != 0U) + 800350e: f7ff fc27 bl 8002d60 + 8003512: 4603 mov r3, r0 + 8003514: 2b00 cmp r3, #0 + 8003516: d1f1 bne.n 80034fc + } + } + + /* Disable the PLL source and outputs to save power when PLL is off */ + CLEAR_BIT(RCC->PLLCFGR, (RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLPEN | RCC_PLLCFGR_PLLQEN | RCC_PLLCFGR_PLLREN)); + 8003518: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 800351c: 68da ldr r2, [r3, #12] + 800351e: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 8003522: 4b1a ldr r3, [pc, #104] @ (800358c ) + 8003524: 4013 ands r3, r2 + 8003526: 60cb str r3, [r1, #12] + 8003528: e028 b.n 800357c + } + } + else + { + /* Check if there is a request to disable the PLL used as System clock source */ + if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) + 800352a: 687b ldr r3, [r7, #4] + 800352c: 6adb ldr r3, [r3, #44] @ 0x2c + 800352e: 2b01 cmp r3, #1 + 8003530: d101 bne.n 8003536 + { + return HAL_ERROR; + 8003532: 2301 movs r3, #1 + 8003534: e023 b.n 800357e + } + else + { + /* Do not return HAL_ERROR if request repeats the current configuration */ + pll_config = RCC->PLLCFGR; + 8003536: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 800353a: 68db ldr r3, [r3, #12] + 800353c: 61bb str r3, [r7, #24] + if ((READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) + 800353e: 69bb ldr r3, [r7, #24] + 8003540: f003 0203 and.w r2, r3, #3 + 8003544: 687b ldr r3, [r7, #4] + 8003546: 6b1b ldr r3, [r3, #48] @ 0x30 + 8003548: 429a cmp r2, r3 + 800354a: d115 bne.n 8003578 + || (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) + 800354c: 69bb ldr r3, [r7, #24] + 800354e: f003 0270 and.w r2, r3, #112 @ 0x70 + 8003552: 687b ldr r3, [r7, #4] + 8003554: 6b5b ldr r3, [r3, #52] @ 0x34 + 8003556: 429a cmp r2, r3 + 8003558: d10e bne.n 8003578 + || (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) + 800355a: 69bb ldr r3, [r7, #24] + 800355c: f403 42fe and.w r2, r3, #32512 @ 0x7f00 + 8003560: 687b ldr r3, [r7, #4] + 8003562: 6b9b ldr r3, [r3, #56] @ 0x38 + 8003564: 021b lsls r3, r3, #8 + 8003566: 429a cmp r2, r3 + 8003568: d106 bne.n 8003578 + || (READ_BIT(pll_config, RCC_PLLCFGR_PLLR) != RCC_OscInitStruct->PLL.PLLR)) + 800356a: 69bb ldr r3, [r7, #24] + 800356c: f003 4260 and.w r2, r3, #3758096384 @ 0xe0000000 + 8003570: 687b ldr r3, [r7, #4] + 8003572: 6c5b ldr r3, [r3, #68] @ 0x44 + 8003574: 429a cmp r2, r3 + 8003576: d001 beq.n 800357c + { + return HAL_ERROR; + 8003578: 2301 movs r3, #1 + 800357a: e000 b.n 800357e + } + } + } + } + return HAL_OK; + 800357c: 2300 movs r3, #0 +} + 800357e: 4618 mov r0, r3 + 8003580: 3720 adds r7, #32 + 8003582: 46bd mov sp, r7 + 8003584: bd80 pop {r7, pc} + 8003586: bf00 nop + 8003588: 11c1808c .word 0x11c1808c + 800358c: eefefffc .word 0xeefefffc + +08003590 : + * HPRE[3:0] bits to ensure that HCLK1 not exceed the maximum allowed frequency + * (for more details refer to section above "Initialization/de-initialization functions") + * @retval None + */ +HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) +{ + 8003590: b580 push {r7, lr} + 8003592: b084 sub sp, #16 + 8003594: af00 add r7, sp, #0 + 8003596: 6078 str r0, [r7, #4] + 8003598: 6039 str r1, [r7, #0] + uint32_t tickstart; + + /* Check Null pointer */ + if (RCC_ClkInitStruct == NULL) + 800359a: 687b ldr r3, [r7, #4] + 800359c: 2b00 cmp r3, #0 + 800359e: d101 bne.n 80035a4 + { + return HAL_ERROR; + 80035a0: 2301 movs r3, #1 + 80035a2: e12c b.n 80037fe + /* To correctly read data from FLASH memory, the number of wait states (LATENCY) + must be correctly programmed according to the frequency of the FLASH clock + (HCLK3) and the supply voltage of the device. */ + + /* Increasing the number of wait states because of higher CPU frequency */ + if (FLatency > __HAL_FLASH_GET_LATENCY()) + 80035a4: 4b98 ldr r3, [pc, #608] @ (8003808 ) + 80035a6: 681b ldr r3, [r3, #0] + 80035a8: f003 0307 and.w r3, r3, #7 + 80035ac: 683a ldr r2, [r7, #0] + 80035ae: 429a cmp r2, r3 + 80035b0: d91b bls.n 80035ea + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLatency); + 80035b2: 4b95 ldr r3, [pc, #596] @ (8003808 ) + 80035b4: 681b ldr r3, [r3, #0] + 80035b6: f023 0207 bic.w r2, r3, #7 + 80035ba: 4993 ldr r1, [pc, #588] @ (8003808 ) + 80035bc: 683b ldr r3, [r7, #0] + 80035be: 4313 orrs r3, r2 + 80035c0: 600b str r3, [r1, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 80035c2: f7fd fadd bl 8000b80 + 80035c6: 60f8 str r0, [r7, #12] + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + while (__HAL_FLASH_GET_LATENCY() != FLatency) + 80035c8: e008 b.n 80035dc + { + if ((HAL_GetTick() - tickstart) > LATENCY_TIMEOUT_VALUE) + 80035ca: f7fd fad9 bl 8000b80 + 80035ce: 4602 mov r2, r0 + 80035d0: 68fb ldr r3, [r7, #12] + 80035d2: 1ad3 subs r3, r2, r3 + 80035d4: 2b02 cmp r3, #2 + 80035d6: d901 bls.n 80035dc + { + return HAL_TIMEOUT; + 80035d8: 2303 movs r3, #3 + 80035da: e110 b.n 80037fe + while (__HAL_FLASH_GET_LATENCY() != FLatency) + 80035dc: 4b8a ldr r3, [pc, #552] @ (8003808 ) + 80035de: 681b ldr r3, [r3, #0] + 80035e0: f003 0307 and.w r3, r3, #7 + 80035e4: 683a ldr r2, [r7, #0] + 80035e6: 429a cmp r2, r3 + 80035e8: d1ef bne.n 80035ca + } + } + } + + /*-------------------------- HCLK1 Configuration ---------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) + 80035ea: 687b ldr r3, [r7, #4] + 80035ec: 681b ldr r3, [r3, #0] + 80035ee: f003 0302 and.w r3, r3, #2 + 80035f2: 2b00 cmp r3, #0 + 80035f4: d016 beq.n 8003624 + { + assert_param(IS_RCC_HCLKx(RCC_ClkInitStruct->AHBCLKDivider)); + LL_RCC_SetAHBPrescaler(RCC_ClkInitStruct->AHBCLKDivider); + 80035f6: 687b ldr r3, [r7, #4] + 80035f8: 689b ldr r3, [r3, #8] + 80035fa: 4618 mov r0, r3 + 80035fc: f7ff fb02 bl 8002c04 + + /* HCLK1 prescaler flag when value applied */ + tickstart = HAL_GetTick(); + 8003600: f7fd fabe bl 8000b80 + 8003604: 60f8 str r0, [r7, #12] + while (LL_RCC_IsActiveFlag_HPRE() == 0U) + 8003606: e008 b.n 800361a + { + if ((HAL_GetTick() - tickstart) > PRESCALER_TIMEOUT_VALUE) + 8003608: f7fd faba bl 8000b80 + 800360c: 4602 mov r2, r0 + 800360e: 68fb ldr r3, [r7, #12] + 8003610: 1ad3 subs r3, r2, r3 + 8003612: 2b02 cmp r3, #2 + 8003614: d901 bls.n 800361a + { + return HAL_TIMEOUT; + 8003616: 2303 movs r3, #3 + 8003618: e0f1 b.n 80037fe + while (LL_RCC_IsActiveFlag_HPRE() == 0U) + 800361a: f7ff fbdf bl 8002ddc + 800361e: 4603 mov r3, r0 + 8003620: 2b00 cmp r3, #0 + 8003622: d0f1 beq.n 8003608 + } + } + +#if defined(DUAL_CORE) + /*-------------------------- HCLK2 Configuration ---------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK2) == RCC_CLOCKTYPE_HCLK2) + 8003624: 687b ldr r3, [r7, #4] + 8003626: 681b ldr r3, [r3, #0] + 8003628: f003 0320 and.w r3, r3, #32 + 800362c: 2b00 cmp r3, #0 + 800362e: d016 beq.n 800365e + { + assert_param(IS_RCC_HCLKx(RCC_ClkInitStruct->AHBCLK2Divider)); + LL_C2_RCC_SetAHBPrescaler(RCC_ClkInitStruct->AHBCLK2Divider); + 8003630: 687b ldr r3, [r7, #4] + 8003632: 695b ldr r3, [r3, #20] + 8003634: 4618 mov r0, r3 + 8003636: f7ff faf8 bl 8002c2a + + /* HCLK2 prescaler flag when value applied */ + tickstart = HAL_GetTick(); + 800363a: f7fd faa1 bl 8000b80 + 800363e: 60f8 str r0, [r7, #12] + while (LL_RCC_IsActiveFlag_C2HPRE() == 0U) + 8003640: e008 b.n 8003654 + { + if ((HAL_GetTick() - tickstart) > PRESCALER_TIMEOUT_VALUE) + 8003642: f7fd fa9d bl 8000b80 + 8003646: 4602 mov r2, r0 + 8003648: 68fb ldr r3, [r7, #12] + 800364a: 1ad3 subs r3, r2, r3 + 800364c: 2b02 cmp r3, #2 + 800364e: d901 bls.n 8003654 + { + return HAL_TIMEOUT; + 8003650: 2303 movs r3, #3 + 8003652: e0d4 b.n 80037fe + while (LL_RCC_IsActiveFlag_C2HPRE() == 0U) + 8003654: f7ff fbd3 bl 8002dfe + 8003658: 4603 mov r3, r0 + 800365a: 2b00 cmp r3, #0 + 800365c: d0f1 beq.n 8003642 + } + } +#endif /* DUAL_CORE */ + + /*-------------------------- HCLK3 Configuration ---------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK3) == RCC_CLOCKTYPE_HCLK3) + 800365e: 687b ldr r3, [r7, #4] + 8003660: 681b ldr r3, [r3, #0] + 8003662: f003 0340 and.w r3, r3, #64 @ 0x40 + 8003666: 2b00 cmp r3, #0 + 8003668: d016 beq.n 8003698 + { + assert_param(IS_RCC_HCLKx(RCC_ClkInitStruct->AHBCLK3Divider)); + LL_RCC_SetAHB3Prescaler(RCC_ClkInitStruct->AHBCLK3Divider); + 800366a: 687b ldr r3, [r7, #4] + 800366c: 699b ldr r3, [r3, #24] + 800366e: 4618 mov r0, r3 + 8003670: f7ff faf0 bl 8002c54 + + /* AHB shared prescaler flag when value applied */ + tickstart = HAL_GetTick(); + 8003674: f7fd fa84 bl 8000b80 + 8003678: 60f8 str r0, [r7, #12] + while (LL_RCC_IsActiveFlag_SHDHPRE() == 0U) + 800367a: e008 b.n 800368e + { + if ((HAL_GetTick() - tickstart) > PRESCALER_TIMEOUT_VALUE) + 800367c: f7fd fa80 bl 8000b80 + 8003680: 4602 mov r2, r0 + 8003682: 68fb ldr r3, [r7, #12] + 8003684: 1ad3 subs r3, r2, r3 + 8003686: 2b02 cmp r3, #2 + 8003688: d901 bls.n 800368e + { + return HAL_TIMEOUT; + 800368a: 2303 movs r3, #3 + 800368c: e0b7 b.n 80037fe + while (LL_RCC_IsActiveFlag_SHDHPRE() == 0U) + 800368e: f7ff fbc8 bl 8002e22 + 8003692: 4603 mov r3, r0 + 8003694: 2b00 cmp r3, #0 + 8003696: d0f1 beq.n 800367c + } + } + } + + /*-------------------------- PCLK1 Configuration ---------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) + 8003698: 687b ldr r3, [r7, #4] + 800369a: 681b ldr r3, [r3, #0] + 800369c: f003 0304 and.w r3, r3, #4 + 80036a0: 2b00 cmp r3, #0 + 80036a2: d016 beq.n 80036d2 + { + assert_param(IS_RCC_PCLKx(RCC_ClkInitStruct->APB1CLKDivider)); + LL_RCC_SetAPB1Prescaler(RCC_ClkInitStruct->APB1CLKDivider); + 80036a4: 687b ldr r3, [r7, #4] + 80036a6: 68db ldr r3, [r3, #12] + 80036a8: 4618 mov r0, r3 + 80036aa: f7ff fae9 bl 8002c80 + + /* APB1 prescaler flag when value applied */ + tickstart = HAL_GetTick(); + 80036ae: f7fd fa67 bl 8000b80 + 80036b2: 60f8 str r0, [r7, #12] + while (LL_RCC_IsActiveFlag_PPRE1() == 0U) + 80036b4: e008 b.n 80036c8 + { + if ((HAL_GetTick() - tickstart) > PRESCALER_TIMEOUT_VALUE) + 80036b6: f7fd fa63 bl 8000b80 + 80036ba: 4602 mov r2, r0 + 80036bc: 68fb ldr r3, [r7, #12] + 80036be: 1ad3 subs r3, r2, r3 + 80036c0: 2b02 cmp r3, #2 + 80036c2: d901 bls.n 80036c8 + { + return HAL_TIMEOUT; + 80036c4: 2303 movs r3, #3 + 80036c6: e09a b.n 80037fe + while (LL_RCC_IsActiveFlag_PPRE1() == 0U) + 80036c8: f7ff fbbd bl 8002e46 + 80036cc: 4603 mov r3, r0 + 80036ce: 2b00 cmp r3, #0 + 80036d0: d0f1 beq.n 80036b6 + } + } + } + + /*-------------------------- PCLK2 Configuration ---------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) + 80036d2: 687b ldr r3, [r7, #4] + 80036d4: 681b ldr r3, [r3, #0] + 80036d6: f003 0308 and.w r3, r3, #8 + 80036da: 2b00 cmp r3, #0 + 80036dc: d017 beq.n 800370e + { + assert_param(IS_RCC_PCLKx(RCC_ClkInitStruct->APB2CLKDivider)); + LL_RCC_SetAPB2Prescaler((RCC_ClkInitStruct->APB2CLKDivider) << 3U); + 80036de: 687b ldr r3, [r7, #4] + 80036e0: 691b ldr r3, [r3, #16] + 80036e2: 00db lsls r3, r3, #3 + 80036e4: 4618 mov r0, r3 + 80036e6: f7ff fade bl 8002ca6 + + /* APB2 prescaler flag when value applied */ + tickstart = HAL_GetTick(); + 80036ea: f7fd fa49 bl 8000b80 + 80036ee: 60f8 str r0, [r7, #12] + while (LL_RCC_IsActiveFlag_PPRE2() == 0U) + 80036f0: e008 b.n 8003704 + { + if ((HAL_GetTick() - tickstart) > PRESCALER_TIMEOUT_VALUE) + 80036f2: f7fd fa45 bl 8000b80 + 80036f6: 4602 mov r2, r0 + 80036f8: 68fb ldr r3, [r7, #12] + 80036fa: 1ad3 subs r3, r2, r3 + 80036fc: 2b02 cmp r3, #2 + 80036fe: d901 bls.n 8003704 + { + return HAL_TIMEOUT; + 8003700: 2303 movs r3, #3 + 8003702: e07c b.n 80037fe + while (LL_RCC_IsActiveFlag_PPRE2() == 0U) + 8003704: f7ff fbb0 bl 8002e68 + 8003708: 4603 mov r3, r0 + 800370a: 2b00 cmp r3, #0 + 800370c: d0f1 beq.n 80036f2 + } + } + } + + /*------------------------- SYSCLK Configuration ---------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) + 800370e: 687b ldr r3, [r7, #4] + 8003710: 681b ldr r3, [r3, #0] + 8003712: f003 0301 and.w r3, r3, #1 + 8003716: 2b00 cmp r3, #0 + 8003718: d043 beq.n 80037a2 + { + assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); + + /* HSE is selected as System Clock Source */ + if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) + 800371a: 687b ldr r3, [r7, #4] + 800371c: 685b ldr r3, [r3, #4] + 800371e: 2b02 cmp r3, #2 + 8003720: d106 bne.n 8003730 + { + /* Check the HSE ready flag */ + if (LL_RCC_HSE_IsReady() == 0U) + 8003722: f7ff f956 bl 80029d2 + 8003726: 4603 mov r3, r0 + 8003728: 2b00 cmp r3, #0 + 800372a: d11e bne.n 800376a + { + return HAL_ERROR; + 800372c: 2301 movs r3, #1 + 800372e: e066 b.n 80037fe + } + } + /* PLL is selected as System Clock Source */ + else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) + 8003730: 687b ldr r3, [r7, #4] + 8003732: 685b ldr r3, [r3, #4] + 8003734: 2b03 cmp r3, #3 + 8003736: d106 bne.n 8003746 + { + /* Check the PLL ready flag */ + if (LL_RCC_PLL_IsReady() == 0U) + 8003738: f7ff fb12 bl 8002d60 + 800373c: 4603 mov r3, r0 + 800373e: 2b00 cmp r3, #0 + 8003740: d113 bne.n 800376a + { + return HAL_ERROR; + 8003742: 2301 movs r3, #1 + 8003744: e05b b.n 80037fe + } + } + /* MSI is selected as System Clock Source */ + else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_MSI) + 8003746: 687b ldr r3, [r7, #4] + 8003748: 685b ldr r3, [r3, #4] + 800374a: 2b00 cmp r3, #0 + 800374c: d106 bne.n 800375c + { + /* Check the MSI ready flag */ + if (LL_RCC_MSI_IsReady() == 0U) + 800374e: f7ff f9f0 bl 8002b32 + 8003752: 4603 mov r3, r0 + 8003754: 2b00 cmp r3, #0 + 8003756: d108 bne.n 800376a + { + return HAL_ERROR; + 8003758: 2301 movs r3, #1 + 800375a: e050 b.n 80037fe + } + /* HSI is selected as System Clock Source */ + else + { + /* Check the HSI ready flag */ + if (LL_RCC_HSI_IsReady() == 0U) + 800375c: f7ff f966 bl 8002a2c + 8003760: 4603 mov r3, r0 + 8003762: 2b00 cmp r3, #0 + 8003764: d101 bne.n 800376a + { + return HAL_ERROR; + 8003766: 2301 movs r3, #1 + 8003768: e049 b.n 80037fe + } + + } + + /* apply system clock switch */ + LL_RCC_SetSysClkSource(RCC_ClkInitStruct->SYSCLKSource); + 800376a: 687b ldr r3, [r7, #4] + 800376c: 685b ldr r3, [r3, #4] + 800376e: 4618 mov r0, r3 + 8003770: f7ff fa2a bl 8002bc8 + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8003774: f7fd fa04 bl 8000b80 + 8003778: 60f8 str r0, [r7, #12] + + /* check system clock source switch status */ + while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) + 800377a: e00a b.n 8003792 + { + if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) + 800377c: f7fd fa00 bl 8000b80 + 8003780: 4602 mov r2, r0 + 8003782: 68fb ldr r3, [r7, #12] + 8003784: 1ad3 subs r3, r2, r3 + 8003786: f241 3288 movw r2, #5000 @ 0x1388 + 800378a: 4293 cmp r3, r2 + 800378c: d901 bls.n 8003792 + { + return HAL_TIMEOUT; + 800378e: 2303 movs r3, #3 + 8003790: e035 b.n 80037fe + while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) + 8003792: f7ff fa2c bl 8002bee + 8003796: 4602 mov r2, r0 + 8003798: 687b ldr r3, [r7, #4] + 800379a: 685b ldr r3, [r3, #4] + 800379c: 009b lsls r3, r3, #2 + 800379e: 429a cmp r2, r3 + 80037a0: d1ec bne.n 800377c + } + } + } + + /* Decreasing the number of wait states because of lower CPU frequency */ + if (FLatency < __HAL_FLASH_GET_LATENCY()) + 80037a2: 4b19 ldr r3, [pc, #100] @ (8003808 ) + 80037a4: 681b ldr r3, [r3, #0] + 80037a6: f003 0307 and.w r3, r3, #7 + 80037aa: 683a ldr r2, [r7, #0] + 80037ac: 429a cmp r2, r3 + 80037ae: d21b bcs.n 80037e8 + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLatency); + 80037b0: 4b15 ldr r3, [pc, #84] @ (8003808 ) + 80037b2: 681b ldr r3, [r3, #0] + 80037b4: f023 0207 bic.w r2, r3, #7 + 80037b8: 4913 ldr r1, [pc, #76] @ (8003808 ) + 80037ba: 683b ldr r3, [r7, #0] + 80037bc: 4313 orrs r3, r2 + 80037be: 600b str r3, [r1, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 80037c0: f7fd f9de bl 8000b80 + 80037c4: 60f8 str r0, [r7, #12] + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + while (__HAL_FLASH_GET_LATENCY() != FLatency) + 80037c6: e008 b.n 80037da + { + if ((HAL_GetTick() - tickstart) > LATENCY_TIMEOUT_VALUE) + 80037c8: f7fd f9da bl 8000b80 + 80037cc: 4602 mov r2, r0 + 80037ce: 68fb ldr r3, [r7, #12] + 80037d0: 1ad3 subs r3, r2, r3 + 80037d2: 2b02 cmp r3, #2 + 80037d4: d901 bls.n 80037da + { + return HAL_TIMEOUT; + 80037d6: 2303 movs r3, #3 + 80037d8: e011 b.n 80037fe + while (__HAL_FLASH_GET_LATENCY() != FLatency) + 80037da: 4b0b ldr r3, [pc, #44] @ (8003808 ) + 80037dc: 681b ldr r3, [r3, #0] + 80037de: f003 0307 and.w r3, r3, #7 + 80037e2: 683a ldr r2, [r7, #0] + 80037e4: 429a cmp r2, r3 + 80037e6: d1ef bne.n 80037c8 + } + + /*--------------------------------------------------------------------------*/ + + /* Update the SystemCoreClock global variable */ + SystemCoreClock = HAL_RCC_GetHCLKFreq(); + 80037e8: f000 f8b4 bl 8003954 + 80037ec: 4603 mov r3, r0 + 80037ee: 4a07 ldr r2, [pc, #28] @ (800380c ) + 80037f0: 6013 str r3, [r2, #0] + + /* Configure the source of time base considering new system clocks settings */ + return HAL_InitTick(uwTickPrio); + 80037f2: 4b07 ldr r3, [pc, #28] @ (8003810 ) + 80037f4: 681b ldr r3, [r3, #0] + 80037f6: 4618 mov r0, r3 + 80037f8: f7fd f9b8 bl 8000b6c + 80037fc: 4603 mov r3, r0 +} + 80037fe: 4618 mov r0, r3 + 8003800: 3710 adds r7, #16 + 8003802: 46bd mov sp, r7 + 8003804: bd80 pop {r7, pc} + 8003806: bf00 nop + 8003808: 58004000 .word 0x58004000 + 800380c: 20000000 .word 0x20000000 + 8003810: 20000004 .word 0x20000004 + +08003814 : + * + * + * @retval SYSCLK frequency + */ +uint32_t HAL_RCC_GetSysClockFreq(void) +{ + 8003814: b590 push {r4, r7, lr} + 8003816: b087 sub sp, #28 + 8003818: af00 add r7, sp, #0 + uint32_t sysclk_source; + uint32_t pllsource; + uint32_t sysclockfreq = 0U; + 800381a: 2300 movs r3, #0 + 800381c: 617b str r3, [r7, #20] + uint32_t msifreq = 0U; + 800381e: 2300 movs r3, #0 + 8003820: 613b str r3, [r7, #16] + uint32_t pllinputfreq; + + sysclk_source = __HAL_RCC_GET_SYSCLK_SOURCE(); + 8003822: f7ff f9e4 bl 8002bee + 8003826: 60b8 str r0, [r7, #8] + pllsource = __HAL_RCC_GET_PLL_OSCSOURCE(); + 8003828: f7ff facd bl 8002dc6 + 800382c: 6078 str r0, [r7, #4] + + if ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_MSI) || + 800382e: 68bb ldr r3, [r7, #8] + 8003830: 2b00 cmp r3, #0 + 8003832: d005 beq.n 8003840 + 8003834: 68bb ldr r3, [r7, #8] + 8003836: 2b0c cmp r3, #12 + 8003838: d139 bne.n 80038ae + ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pllsource == RCC_PLLSOURCE_MSI))) + 800383a: 687b ldr r3, [r7, #4] + 800383c: 2b01 cmp r3, #1 + 800383e: d136 bne.n 80038ae + { + /* MSI or PLL with MSI source used as system clock source */ + /* Retrieve MSI frequency range in Hz */ + msifreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), + 8003840: f7ff f987 bl 8002b52 + 8003844: 4603 mov r3, r0 + 8003846: 2b00 cmp r3, #0 + 8003848: d115 bne.n 8003876 + 800384a: f7ff f982 bl 8002b52 + 800384e: 4603 mov r3, r0 + 8003850: 2b01 cmp r3, #1 + 8003852: d106 bne.n 8003862 + 8003854: f7ff f98d bl 8002b72 + 8003858: 4603 mov r3, r0 + 800385a: 0a1b lsrs r3, r3, #8 + 800385c: f003 030f and.w r3, r3, #15 + 8003860: e005 b.n 800386e + 8003862: f7ff f991 bl 8002b88 + 8003866: 4603 mov r3, r0 + 8003868: 0a1b lsrs r3, r3, #8 + 800386a: f003 030f and.w r3, r3, #15 + 800386e: 4a36 ldr r2, [pc, #216] @ (8003948 ) + 8003870: f852 3023 ldr.w r3, [r2, r3, lsl #2] + 8003874: e014 b.n 80038a0 + 8003876: f7ff f96c bl 8002b52 + 800387a: 4603 mov r3, r0 + 800387c: 2b01 cmp r3, #1 + 800387e: d106 bne.n 800388e + 8003880: f7ff f977 bl 8002b72 + 8003884: 4603 mov r3, r0 + 8003886: 091b lsrs r3, r3, #4 + 8003888: f003 030f and.w r3, r3, #15 + 800388c: e005 b.n 800389a + 800388e: f7ff f97b bl 8002b88 + 8003892: 4603 mov r3, r0 + 8003894: 091b lsrs r3, r3, #4 + 8003896: f003 030f and.w r3, r3, #15 + 800389a: 4a2b ldr r2, [pc, #172] @ (8003948 ) + 800389c: f852 3023 ldr.w r3, [r2, r3, lsl #2] + 80038a0: 613b str r3, [r7, #16] + ((LL_RCC_MSI_IsEnabledRangeSelect() == 1U) ? + LL_RCC_MSI_GetRange() : + LL_RCC_MSI_GetRangeAfterStandby())); + + /* Get SYSCLK source */ + if (sysclk_source == RCC_SYSCLKSOURCE_STATUS_MSI) + 80038a2: 68bb ldr r3, [r7, #8] + 80038a4: 2b00 cmp r3, #0 + 80038a6: d115 bne.n 80038d4 + { + /* MSI used as system clock source */ + sysclockfreq = msifreq; + 80038a8: 693b ldr r3, [r7, #16] + 80038aa: 617b str r3, [r7, #20] + if (sysclk_source == RCC_SYSCLKSOURCE_STATUS_MSI) + 80038ac: e012 b.n 80038d4 + } + } + else if (sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSI) + 80038ae: 68bb ldr r3, [r7, #8] + 80038b0: 2b04 cmp r3, #4 + 80038b2: d102 bne.n 80038ba + { + /* HSI used as system clock source */ + sysclockfreq = HSI_VALUE; + 80038b4: 4b25 ldr r3, [pc, #148] @ (800394c ) + 80038b6: 617b str r3, [r7, #20] + 80038b8: e00c b.n 80038d4 + } + else if (sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSE) + 80038ba: 68bb ldr r3, [r7, #8] + 80038bc: 2b08 cmp r3, #8 + 80038be: d109 bne.n 80038d4 + { + /* HSE used as system clock source */ + if (LL_RCC_HSE_IsEnabledDiv2() == 1U) + 80038c0: f7ff f85a bl 8002978 + 80038c4: 4603 mov r3, r0 + 80038c6: 2b01 cmp r3, #1 + 80038c8: d102 bne.n 80038d0 + { + sysclockfreq = HSE_VALUE / 2U; + 80038ca: 4b20 ldr r3, [pc, #128] @ (800394c ) + 80038cc: 617b str r3, [r7, #20] + 80038ce: e001 b.n 80038d4 + } + else + { + sysclockfreq = HSE_VALUE; + 80038d0: 4b1f ldr r3, [pc, #124] @ (8003950 ) + 80038d2: 617b str r3, [r7, #20] + else + { + /* Nothing to do */ + } + + if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) + 80038d4: f7ff f98b bl 8002bee + 80038d8: 4603 mov r3, r0 + 80038da: 2b0c cmp r3, #12 + 80038dc: d12f bne.n 800393e + { + /* PLL used as system clock source */ + pllsource = LL_RCC_PLL_GetMainSource(); + 80038de: f7ff fa72 bl 8002dc6 + 80038e2: 6078 str r0, [r7, #4] + + switch (pllsource) + 80038e4: 687b ldr r3, [r7, #4] + 80038e6: 2b02 cmp r3, #2 + 80038e8: d003 beq.n 80038f2 + 80038ea: 687b ldr r3, [r7, #4] + 80038ec: 2b03 cmp r3, #3 + 80038ee: d003 beq.n 80038f8 + 80038f0: e00d b.n 800390e + { + case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ + pllinputfreq = HSI_VALUE; + 80038f2: 4b16 ldr r3, [pc, #88] @ (800394c ) + 80038f4: 60fb str r3, [r7, #12] + break; + 80038f6: e00d b.n 8003914 + case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ + if (LL_RCC_HSE_IsEnabledDiv2() == 1U) + 80038f8: f7ff f83e bl 8002978 + 80038fc: 4603 mov r3, r0 + 80038fe: 2b01 cmp r3, #1 + 8003900: d102 bne.n 8003908 + { + pllinputfreq = HSE_VALUE / 2U; + 8003902: 4b12 ldr r3, [pc, #72] @ (800394c ) + 8003904: 60fb str r3, [r7, #12] + } + else + { + pllinputfreq = HSE_VALUE; + } + break; + 8003906: e005 b.n 8003914 + pllinputfreq = HSE_VALUE; + 8003908: 4b11 ldr r3, [pc, #68] @ (8003950 ) + 800390a: 60fb str r3, [r7, #12] + break; + 800390c: e002 b.n 8003914 + case RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */ + default: + pllinputfreq = msifreq; + 800390e: 693b ldr r3, [r7, #16] + 8003910: 60fb str r3, [r7, #12] + break; + 8003912: bf00 nop + } + sysclockfreq = __LL_RCC_CALC_PLLCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(), + 8003914: f7ff fa35 bl 8002d82 + 8003918: 4602 mov r2, r0 + 800391a: 68fb ldr r3, [r7, #12] + 800391c: fb03 f402 mul.w r4, r3, r2 + 8003920: f7ff fa46 bl 8002db0 + 8003924: 4603 mov r3, r0 + 8003926: 091b lsrs r3, r3, #4 + 8003928: 3301 adds r3, #1 + 800392a: fbb4 f4f3 udiv r4, r4, r3 + 800392e: f7ff fa34 bl 8002d9a + 8003932: 4603 mov r3, r0 + 8003934: 0f5b lsrs r3, r3, #29 + 8003936: 3301 adds r3, #1 + 8003938: fbb4 f3f3 udiv r3, r4, r3 + 800393c: 617b str r3, [r7, #20] + LL_RCC_PLL_GetN(), LL_RCC_PLL_GetR()); + } + + return sysclockfreq; + 800393e: 697b ldr r3, [r7, #20] +} + 8003940: 4618 mov r0, r3 + 8003942: 371c adds r7, #28 + 8003944: 46bd mov sp, r7 + 8003946: bd90 pop {r4, r7, pc} + 8003948: 0800d928 .word 0x0800d928 + 800394c: 00f42400 .word 0x00f42400 + 8003950: 01e84800 .word 0x01e84800 + +08003954 : +/** + * @brief Return the HCLK frequency. + * @retval HCLK frequency in Hz + */ +uint32_t HAL_RCC_GetHCLKFreq(void) +{ + 8003954: b598 push {r3, r4, r7, lr} + 8003956: af00 add r7, sp, #0 + /* Get SysClock and Compute HCLK1 frequency --------------------------------*/ + return ((uint32_t)(__LL_RCC_CALC_HCLK1_FREQ(HAL_RCC_GetSysClockFreq(), LL_RCC_GetAHBPrescaler()))); + 8003958: f7ff ff5c bl 8003814 + 800395c: 4604 mov r4, r0 + 800395e: f7ff f9b5 bl 8002ccc + 8003962: 4603 mov r3, r0 + 8003964: 091b lsrs r3, r3, #4 + 8003966: f003 030f and.w r3, r3, #15 + 800396a: 4a03 ldr r2, [pc, #12] @ (8003978 ) + 800396c: f852 3023 ldr.w r3, [r2, r3, lsl #2] + 8003970: fbb4 f3f3 udiv r3, r4, r3 +} + 8003974: 4618 mov r0, r3 + 8003976: bd98 pop {r3, r4, r7, pc} + 8003978: 0800d8c8 .word 0x0800d8c8 + +0800397c : +/** + * @brief Return the PCLK1 frequency. + * @retval PCLK1 frequency in Hz + */ +uint32_t HAL_RCC_GetPCLK1Freq(void) +{ + 800397c: b598 push {r3, r4, r7, lr} + 800397e: af00 add r7, sp, #0 + /* Get HCLK source and Compute PCLK1 frequency -----------------------------*/ + return ((uint32_t)(__LL_RCC_CALC_PCLK1_FREQ(HAL_RCC_GetHCLKFreq(), LL_RCC_GetAPB1Prescaler()))); + 8003980: f7ff ffe8 bl 8003954 + 8003984: 4604 mov r4, r0 + 8003986: f7ff f9b9 bl 8002cfc + 800398a: 4603 mov r3, r0 + 800398c: 0a1b lsrs r3, r3, #8 + 800398e: 4a03 ldr r2, [pc, #12] @ (800399c ) + 8003990: f852 3023 ldr.w r3, [r2, r3, lsl #2] + 8003994: fa24 f303 lsr.w r3, r4, r3 +} + 8003998: 4618 mov r0, r3 + 800399a: bd98 pop {r3, r4, r7, pc} + 800399c: 0800d908 .word 0x0800d908 + +080039a0 : +/** + * @brief Return the PCLK2 frequency. + * @retval PCLK2 frequency in Hz + */ +uint32_t HAL_RCC_GetPCLK2Freq(void) +{ + 80039a0: b598 push {r3, r4, r7, lr} + 80039a2: af00 add r7, sp, #0 + /* Get HCLK source and Compute PCLK2 frequency -----------------------------*/ + return ((uint32_t)(__LL_RCC_CALC_PCLK2_FREQ(HAL_RCC_GetHCLKFreq(), LL_RCC_GetAPB2Prescaler()))); + 80039a4: f7ff ffd6 bl 8003954 + 80039a8: 4604 mov r4, r0 + 80039aa: f7ff f9b2 bl 8002d12 + 80039ae: 4603 mov r3, r0 + 80039b0: 0adb lsrs r3, r3, #11 + 80039b2: 4a03 ldr r2, [pc, #12] @ (80039c0 ) + 80039b4: f852 3023 ldr.w r3, [r2, r3, lsl #2] + 80039b8: fa24 f303 lsr.w r3, r4, r3 +} + 80039bc: 4618 mov r0, r3 + 80039be: bd98 pop {r3, r4, r7, pc} + 80039c0: 0800d908 .word 0x0800d908 + +080039c4 : + voltage range. + * @param MSI_Range MSI range value from @ref RCC_MSIRANGE_0 to @ref RCC_MSIRANGE_11 + * @retval HAL status + */ +static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t MSI_Range) +{ + 80039c4: b590 push {r4, r7, lr} + 80039c6: b085 sub sp, #20 + 80039c8: af00 add r7, sp, #0 + 80039ca: 6078 str r0, [r7, #4] + uint32_t flash_clksrcfreq; + uint32_t msifreq; + + /* MSI frequency range in Hz */ + msifreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSIRANGESEL_RUN, MSI_Range); + 80039cc: 687b ldr r3, [r7, #4] + 80039ce: 091b lsrs r3, r3, #4 + 80039d0: f003 030f and.w r3, r3, #15 + 80039d4: 4a10 ldr r2, [pc, #64] @ (8003a18 ) + 80039d6: f852 3023 ldr.w r3, [r2, r3, lsl #2] + 80039da: 60fb str r3, [r7, #12] + flash_clksrcfreq = __LL_RCC_CALC_HCLK3_FREQ(msifreq, LL_RCC_GetAHB3Prescaler()); + 80039dc: f7ff f981 bl 8002ce2 + 80039e0: 4603 mov r3, r0 + 80039e2: 091b lsrs r3, r3, #4 + 80039e4: f003 030f and.w r3, r3, #15 + 80039e8: 4a0c ldr r2, [pc, #48] @ (8003a1c ) + 80039ea: f852 3023 ldr.w r3, [r2, r3, lsl #2] + 80039ee: 68fa ldr r2, [r7, #12] + 80039f0: fbb2 f3f3 udiv r3, r2, r3 + 80039f4: 60bb str r3, [r7, #8] + + return RCC_SetFlashLatency((flash_clksrcfreq / MEGA_HZ), HAL_PWREx_GetVoltageRange()); + 80039f6: 68bb ldr r3, [r7, #8] + 80039f8: 4a09 ldr r2, [pc, #36] @ (8003a20 ) + 80039fa: fba2 2303 umull r2, r3, r2, r3 + 80039fe: 0c9c lsrs r4, r3, #18 + 8003a00: f7fe ff12 bl 8002828 + 8003a04: 4603 mov r3, r0 + 8003a06: 4619 mov r1, r3 + 8003a08: 4620 mov r0, r4 + 8003a0a: f000 f80b bl 8003a24 + 8003a0e: 4603 mov r3, r0 +} + 8003a10: 4618 mov r0, r3 + 8003a12: 3714 adds r7, #20 + 8003a14: 46bd mov sp, r7 + 8003a16: bd90 pop {r4, r7, pc} + 8003a18: 0800d928 .word 0x0800d928 + 8003a1c: 0800d8c8 .word 0x0800d8c8 + 8003a20: 431bde83 .word 0x431bde83 + +08003a24 : + * @arg PWR_REGULATOR_VOLTAGE_SCALE1 Regulator voltage output range 1 mode + * @arg PWR_REGULATOR_VOLTAGE_SCALE2 Regulator voltage output range 2 mode + * @retval HAL status + */ +static HAL_StatusTypeDef RCC_SetFlashLatency(uint32_t Flash_ClkSrcFreq, uint32_t VCORE_Voltage) +{ + 8003a24: b580 push {r7, lr} + 8003a26: b08e sub sp, #56 @ 0x38 + 8003a28: af00 add r7, sp, #0 + 8003a2a: 6078 str r0, [r7, #4] + 8003a2c: 6039 str r1, [r7, #0] + /* Flash Clock source (HCLK3) range in MHz for VCORE range1 */ + const uint16_t FLASH_CLK_SRC_RANGE_VOS1[] = {18, 36, 48}; + 8003a2e: 4a3a ldr r2, [pc, #232] @ (8003b18 ) + 8003a30: f107 0320 add.w r3, r7, #32 + 8003a34: e892 0003 ldmia.w r2, {r0, r1} + 8003a38: 6018 str r0, [r3, #0] + 8003a3a: 3304 adds r3, #4 + 8003a3c: 8019 strh r1, [r3, #0] + + /* Flash Clock source (HCLK3) range in MHz for VCORE range2 */ + const uint16_t FLASH_CLK_SRC_RANGE_VOS2[] = {6, 12, 16}; + 8003a3e: 4a37 ldr r2, [pc, #220] @ (8003b1c ) + 8003a40: f107 0318 add.w r3, r7, #24 + 8003a44: e892 0003 ldmia.w r2, {r0, r1} + 8003a48: 6018 str r0, [r3, #0] + 8003a4a: 3304 adds r3, #4 + 8003a4c: 8019 strh r1, [r3, #0] + + /* Flash Latency range */ + const uint32_t FLASH_LATENCY_RANGE[] = {FLASH_LATENCY_0, FLASH_LATENCY_1, FLASH_LATENCY_2}; + 8003a4e: 4a34 ldr r2, [pc, #208] @ (8003b20 ) + 8003a50: f107 030c add.w r3, r7, #12 + 8003a54: ca07 ldmia r2, {r0, r1, r2} + 8003a56: e883 0007 stmia.w r3, {r0, r1, r2} + + uint32_t latency = FLASH_LATENCY_0; /* default value 0WS */ + 8003a5a: 2300 movs r3, #0 + 8003a5c: 637b str r3, [r7, #52] @ 0x34 + uint32_t tickstart; + + if (VCORE_Voltage == PWR_REGULATOR_VOLTAGE_SCALE1) + 8003a5e: 683b ldr r3, [r7, #0] + 8003a60: f5b3 7f00 cmp.w r3, #512 @ 0x200 + 8003a64: d11b bne.n 8003a9e + { + for (uint32_t index = 0; index < __COUNTOF(FLASH_CLK_SRC_RANGE_VOS1); index++) + 8003a66: 2300 movs r3, #0 + 8003a68: 633b str r3, [r7, #48] @ 0x30 + 8003a6a: e014 b.n 8003a96 + { + if (Flash_ClkSrcFreq <= FLASH_CLK_SRC_RANGE_VOS1[index]) + 8003a6c: 6b3b ldr r3, [r7, #48] @ 0x30 + 8003a6e: 005b lsls r3, r3, #1 + 8003a70: 3338 adds r3, #56 @ 0x38 + 8003a72: 443b add r3, r7 + 8003a74: f833 3c18 ldrh.w r3, [r3, #-24] + 8003a78: 461a mov r2, r3 + 8003a7a: 687b ldr r3, [r7, #4] + 8003a7c: 4293 cmp r3, r2 + 8003a7e: d807 bhi.n 8003a90 + { + latency = FLASH_LATENCY_RANGE[index]; + 8003a80: 6b3b ldr r3, [r7, #48] @ 0x30 + 8003a82: 009b lsls r3, r3, #2 + 8003a84: 3338 adds r3, #56 @ 0x38 + 8003a86: 443b add r3, r7 + 8003a88: f853 3c2c ldr.w r3, [r3, #-44] + 8003a8c: 637b str r3, [r7, #52] @ 0x34 + break; + 8003a8e: e021 b.n 8003ad4 + for (uint32_t index = 0; index < __COUNTOF(FLASH_CLK_SRC_RANGE_VOS1); index++) + 8003a90: 6b3b ldr r3, [r7, #48] @ 0x30 + 8003a92: 3301 adds r3, #1 + 8003a94: 633b str r3, [r7, #48] @ 0x30 + 8003a96: 6b3b ldr r3, [r7, #48] @ 0x30 + 8003a98: 2b02 cmp r3, #2 + 8003a9a: d9e7 bls.n 8003a6c + 8003a9c: e01a b.n 8003ad4 + } + } + } + else /* PWR_REGULATOR_VOLTAGE_SCALE2 */ + { + for (uint32_t index = 0; index < __COUNTOF(FLASH_CLK_SRC_RANGE_VOS2); index++) + 8003a9e: 2300 movs r3, #0 + 8003aa0: 62fb str r3, [r7, #44] @ 0x2c + 8003aa2: e014 b.n 8003ace + { + if (Flash_ClkSrcFreq <= FLASH_CLK_SRC_RANGE_VOS2[index]) + 8003aa4: 6afb ldr r3, [r7, #44] @ 0x2c + 8003aa6: 005b lsls r3, r3, #1 + 8003aa8: 3338 adds r3, #56 @ 0x38 + 8003aaa: 443b add r3, r7 + 8003aac: f833 3c20 ldrh.w r3, [r3, #-32] + 8003ab0: 461a mov r2, r3 + 8003ab2: 687b ldr r3, [r7, #4] + 8003ab4: 4293 cmp r3, r2 + 8003ab6: d807 bhi.n 8003ac8 + { + latency = FLASH_LATENCY_RANGE[index]; + 8003ab8: 6afb ldr r3, [r7, #44] @ 0x2c + 8003aba: 009b lsls r3, r3, #2 + 8003abc: 3338 adds r3, #56 @ 0x38 + 8003abe: 443b add r3, r7 + 8003ac0: f853 3c2c ldr.w r3, [r3, #-44] + 8003ac4: 637b str r3, [r7, #52] @ 0x34 + break; + 8003ac6: e005 b.n 8003ad4 + for (uint32_t index = 0; index < __COUNTOF(FLASH_CLK_SRC_RANGE_VOS2); index++) + 8003ac8: 6afb ldr r3, [r7, #44] @ 0x2c + 8003aca: 3301 adds r3, #1 + 8003acc: 62fb str r3, [r7, #44] @ 0x2c + 8003ace: 6afb ldr r3, [r7, #44] @ 0x2c + 8003ad0: 2b02 cmp r3, #2 + 8003ad2: d9e7 bls.n 8003aa4 + } + } + } + + __HAL_FLASH_SET_LATENCY(latency); + 8003ad4: 4b13 ldr r3, [pc, #76] @ (8003b24 ) + 8003ad6: 681b ldr r3, [r3, #0] + 8003ad8: f023 0207 bic.w r2, r3, #7 + 8003adc: 4911 ldr r1, [pc, #68] @ (8003b24 ) + 8003ade: 6b7b ldr r3, [r7, #52] @ 0x34 + 8003ae0: 4313 orrs r3, r2 + 8003ae2: 600b str r3, [r1, #0] + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8003ae4: f7fd f84c bl 8000b80 + 8003ae8: 62b8 str r0, [r7, #40] @ 0x28 + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + while (__HAL_FLASH_GET_LATENCY() != latency) + 8003aea: e008 b.n 8003afe + { + if ((HAL_GetTick() - tickstart) > LATENCY_TIMEOUT_VALUE) + 8003aec: f7fd f848 bl 8000b80 + 8003af0: 4602 mov r2, r0 + 8003af2: 6abb ldr r3, [r7, #40] @ 0x28 + 8003af4: 1ad3 subs r3, r2, r3 + 8003af6: 2b02 cmp r3, #2 + 8003af8: d901 bls.n 8003afe + { + return HAL_TIMEOUT; + 8003afa: 2303 movs r3, #3 + 8003afc: e007 b.n 8003b0e + while (__HAL_FLASH_GET_LATENCY() != latency) + 8003afe: 4b09 ldr r3, [pc, #36] @ (8003b24 ) + 8003b00: 681b ldr r3, [r3, #0] + 8003b02: f003 0307 and.w r3, r3, #7 + 8003b06: 6b7a ldr r2, [r7, #52] @ 0x34 + 8003b08: 429a cmp r2, r3 + 8003b0a: d1ef bne.n 8003aec + } + } + return HAL_OK; + 8003b0c: 2300 movs r3, #0 +} + 8003b0e: 4618 mov r0, r3 + 8003b10: 3738 adds r7, #56 @ 0x38 + 8003b12: 46bd mov sp, r7 + 8003b14: bd80 pop {r7, pc} + 8003b16: bf00 nop + 8003b18: 0800d50c .word 0x0800d50c + 8003b1c: 0800d514 .word 0x0800d514 + 8003b20: 0800d51c .word 0x0800d51c + 8003b24: 58004000 .word 0x58004000 + +08003b28 : +{ + 8003b28: b480 push {r7} + 8003b2a: af00 add r7, sp, #0 + return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY)) ? 1UL : 0UL); + 8003b2c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8003b30: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 8003b34: f003 0302 and.w r3, r3, #2 + 8003b38: 2b02 cmp r3, #2 + 8003b3a: d101 bne.n 8003b40 + 8003b3c: 2301 movs r3, #1 + 8003b3e: e000 b.n 8003b42 + 8003b40: 2300 movs r3, #0 +} + 8003b42: 4618 mov r0, r3 + 8003b44: 46bd mov sp, r7 + 8003b46: bc80 pop {r7} + 8003b48: 4770 bx lr + +08003b4a : +{ + 8003b4a: b480 push {r7} + 8003b4c: b083 sub sp, #12 + 8003b4e: af00 add r7, sp, #0 + 8003b50: 6078 str r0, [r7, #4] + MODIFY_REG(RCC->CCIPR, (USARTxSource >> 16), (USARTxSource & 0x0000FFFFU)); + 8003b52: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8003b56: f8d3 2088 ldr.w r2, [r3, #136] @ 0x88 + 8003b5a: 687b ldr r3, [r7, #4] + 8003b5c: 0c1b lsrs r3, r3, #16 + 8003b5e: 43db mvns r3, r3 + 8003b60: 401a ands r2, r3 + 8003b62: 687b ldr r3, [r7, #4] + 8003b64: b29b uxth r3, r3 + 8003b66: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 8003b6a: 4313 orrs r3, r2 + 8003b6c: f8c1 3088 str.w r3, [r1, #136] @ 0x88 +} + 8003b70: bf00 nop + 8003b72: 370c adds r7, #12 + 8003b74: 46bd mov sp, r7 + 8003b76: bc80 pop {r7} + 8003b78: 4770 bx lr + +08003b7a : +{ + 8003b7a: b480 push {r7} + 8003b7c: b083 sub sp, #12 + 8003b7e: af00 add r7, sp, #0 + 8003b80: 6078 str r0, [r7, #4] + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2S2SEL, I2SxSource); + 8003b82: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8003b86: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 + 8003b8a: f423 7240 bic.w r2, r3, #768 @ 0x300 + 8003b8e: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 8003b92: 687b ldr r3, [r7, #4] + 8003b94: 4313 orrs r3, r2 + 8003b96: f8c1 3088 str.w r3, [r1, #136] @ 0x88 +} + 8003b9a: bf00 nop + 8003b9c: 370c adds r7, #12 + 8003b9e: 46bd mov sp, r7 + 8003ba0: bc80 pop {r7} + 8003ba2: 4770 bx lr + +08003ba4 : +{ + 8003ba4: b480 push {r7} + 8003ba6: b083 sub sp, #12 + 8003ba8: af00 add r7, sp, #0 + 8003baa: 6078 str r0, [r7, #4] + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, LPUARTxSource); + 8003bac: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8003bb0: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 + 8003bb4: f423 6240 bic.w r2, r3, #3072 @ 0xc00 + 8003bb8: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 8003bbc: 687b ldr r3, [r7, #4] + 8003bbe: 4313 orrs r3, r2 + 8003bc0: f8c1 3088 str.w r3, [r1, #136] @ 0x88 +} + 8003bc4: bf00 nop + 8003bc6: 370c adds r7, #12 + 8003bc8: 46bd mov sp, r7 + 8003bca: bc80 pop {r7} + 8003bcc: 4770 bx lr + +08003bce : +{ + 8003bce: b480 push {r7} + 8003bd0: b083 sub sp, #12 + 8003bd2: af00 add r7, sp, #0 + 8003bd4: 6078 str r0, [r7, #4] + MODIFY_REG(RCC->CCIPR, ((I2CxSource >> 4) & 0x000FF000U), ((I2CxSource << 4) & 0x000FF000U)); + 8003bd6: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8003bda: f8d3 2088 ldr.w r2, [r3, #136] @ 0x88 + 8003bde: 687b ldr r3, [r7, #4] + 8003be0: 091b lsrs r3, r3, #4 + 8003be2: f403 237f and.w r3, r3, #1044480 @ 0xff000 + 8003be6: 43db mvns r3, r3 + 8003be8: 401a ands r2, r3 + 8003bea: 687b ldr r3, [r7, #4] + 8003bec: 011b lsls r3, r3, #4 + 8003bee: f403 237f and.w r3, r3, #1044480 @ 0xff000 + 8003bf2: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 8003bf6: 4313 orrs r3, r2 + 8003bf8: f8c1 3088 str.w r3, [r1, #136] @ 0x88 +} + 8003bfc: bf00 nop + 8003bfe: 370c adds r7, #12 + 8003c00: 46bd mov sp, r7 + 8003c02: bc80 pop {r7} + 8003c04: 4770 bx lr + +08003c06 : +{ + 8003c06: b480 push {r7} + 8003c08: b083 sub sp, #12 + 8003c0a: af00 add r7, sp, #0 + 8003c0c: 6078 str r0, [r7, #4] + MODIFY_REG(RCC->CCIPR, (LPTIMxSource & 0xFFFF0000U), (LPTIMxSource << 16)); + 8003c0e: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8003c12: f8d3 2088 ldr.w r2, [r3, #136] @ 0x88 + 8003c16: 687b ldr r3, [r7, #4] + 8003c18: 0c1b lsrs r3, r3, #16 + 8003c1a: 041b lsls r3, r3, #16 + 8003c1c: 43db mvns r3, r3 + 8003c1e: 401a ands r2, r3 + 8003c20: 687b ldr r3, [r7, #4] + 8003c22: 041b lsls r3, r3, #16 + 8003c24: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 8003c28: 4313 orrs r3, r2 + 8003c2a: f8c1 3088 str.w r3, [r1, #136] @ 0x88 +} + 8003c2e: bf00 nop + 8003c30: 370c adds r7, #12 + 8003c32: 46bd mov sp, r7 + 8003c34: bc80 pop {r7} + 8003c36: 4770 bx lr + +08003c38 : +{ + 8003c38: b480 push {r7} + 8003c3a: b083 sub sp, #12 + 8003c3c: af00 add r7, sp, #0 + 8003c3e: 6078 str r0, [r7, #4] + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_RNGSEL, RNGxSource); + 8003c40: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8003c44: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 + 8003c48: f023 4240 bic.w r2, r3, #3221225472 @ 0xc0000000 + 8003c4c: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 8003c50: 687b ldr r3, [r7, #4] + 8003c52: 4313 orrs r3, r2 + 8003c54: f8c1 3088 str.w r3, [r1, #136] @ 0x88 +} + 8003c58: bf00 nop + 8003c5a: 370c adds r7, #12 + 8003c5c: 46bd mov sp, r7 + 8003c5e: bc80 pop {r7} + 8003c60: 4770 bx lr + +08003c62 : +{ + 8003c62: b480 push {r7} + 8003c64: b083 sub sp, #12 + 8003c66: af00 add r7, sp, #0 + 8003c68: 6078 str r0, [r7, #4] + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADCSEL, ADCxSource); + 8003c6a: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8003c6e: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 + 8003c72: f023 5240 bic.w r2, r3, #805306368 @ 0x30000000 + 8003c76: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 8003c7a: 687b ldr r3, [r7, #4] + 8003c7c: 4313 orrs r3, r2 + 8003c7e: f8c1 3088 str.w r3, [r1, #136] @ 0x88 +} + 8003c82: bf00 nop + 8003c84: 370c adds r7, #12 + 8003c86: 46bd mov sp, r7 + 8003c88: bc80 pop {r7} + 8003c8a: 4770 bx lr + +08003c8c : +{ + 8003c8c: b480 push {r7} + 8003c8e: b083 sub sp, #12 + 8003c90: af00 add r7, sp, #0 + 8003c92: 6078 str r0, [r7, #4] + MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source); + 8003c94: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8003c98: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 8003c9c: f423 7240 bic.w r2, r3, #768 @ 0x300 + 8003ca0: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 8003ca4: 687b ldr r3, [r7, #4] + 8003ca6: 4313 orrs r3, r2 + 8003ca8: f8c1 3090 str.w r3, [r1, #144] @ 0x90 +} + 8003cac: bf00 nop + 8003cae: 370c adds r7, #12 + 8003cb0: 46bd mov sp, r7 + 8003cb2: bc80 pop {r7} + 8003cb4: 4770 bx lr + +08003cb6 : +{ + 8003cb6: b480 push {r7} + 8003cb8: af00 add r7, sp, #0 + return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)); + 8003cba: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8003cbe: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 8003cc2: f403 7340 and.w r3, r3, #768 @ 0x300 +} + 8003cc6: 4618 mov r0, r3 + 8003cc8: 46bd mov sp, r7 + 8003cca: bc80 pop {r7} + 8003ccc: 4770 bx lr + +08003cce : +{ + 8003cce: b480 push {r7} + 8003cd0: af00 add r7, sp, #0 + SET_BIT(RCC->BDCR, RCC_BDCR_BDRST); + 8003cd2: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8003cd6: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 8003cda: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 8003cde: f443 3380 orr.w r3, r3, #65536 @ 0x10000 + 8003ce2: f8c2 3090 str.w r3, [r2, #144] @ 0x90 +} + 8003ce6: bf00 nop + 8003ce8: 46bd mov sp, r7 + 8003cea: bc80 pop {r7} + 8003cec: 4770 bx lr + +08003cee : +{ + 8003cee: b480 push {r7} + 8003cf0: af00 add r7, sp, #0 + CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST); + 8003cf2: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8003cf6: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 8003cfa: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 8003cfe: f423 3380 bic.w r3, r3, #65536 @ 0x10000 + 8003d02: f8c2 3090 str.w r3, [r2, #144] @ 0x90 +} + 8003d06: bf00 nop + 8003d08: 46bd mov sp, r7 + 8003d0a: bc80 pop {r7} + 8003d0c: 4770 bx lr + ... + +08003d10 : + * the RTC clock source: in this case the access to Backup domain is enabled. + * + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) +{ + 8003d10: b580 push {r7, lr} + 8003d12: b086 sub sp, #24 + 8003d14: af00 add r7, sp, #0 + 8003d16: 6078 str r0, [r7, #4] + uint32_t tmpregister = 0; + 8003d18: 2300 movs r3, #0 + 8003d1a: 617b str r3, [r7, #20] + uint32_t tickstart; + HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */ + 8003d1c: 2300 movs r3, #0 + 8003d1e: 74fb strb r3, [r7, #19] + HAL_StatusTypeDef status = HAL_OK; /* Final status */ + 8003d20: 2300 movs r3, #0 + 8003d22: 74bb strb r3, [r7, #18] + + /* Check the parameters */ + assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); + + /*-------------------------- RTC clock source configuration ----------------------*/ + if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) + 8003d24: 687b ldr r3, [r7, #4] + 8003d26: 681b ldr r3, [r3, #0] + 8003d28: f403 3380 and.w r3, r3, #65536 @ 0x10000 + 8003d2c: 2b00 cmp r3, #0 + 8003d2e: d058 beq.n 8003de2 + /* Check for RTC Parameters used to output RTCCLK */ + assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); + + + /* Enable write access to Backup domain */ + HAL_PWR_EnableBkUpAccess(); + 8003d30: f7fe fd38 bl 80027a4 + + /* Wait for Backup domain Write protection disable */ + tickstart = HAL_GetTick(); + 8003d34: f7fc ff24 bl 8000b80 + 8003d38: 60f8 str r0, [r7, #12] + + while (!(READ_BIT(PWR->CR1, PWR_CR1_DBP) == (PWR_CR1_DBP))) + 8003d3a: e009 b.n 8003d50 + { + if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + 8003d3c: f7fc ff20 bl 8000b80 + 8003d40: 4602 mov r2, r0 + 8003d42: 68fb ldr r3, [r7, #12] + 8003d44: 1ad3 subs r3, r2, r3 + 8003d46: 2b02 cmp r3, #2 + 8003d48: d902 bls.n 8003d50 + { + ret = HAL_TIMEOUT; + 8003d4a: 2303 movs r3, #3 + 8003d4c: 74fb strb r3, [r7, #19] + break; + 8003d4e: e006 b.n 8003d5e + while (!(READ_BIT(PWR->CR1, PWR_CR1_DBP) == (PWR_CR1_DBP))) + 8003d50: 4b7b ldr r3, [pc, #492] @ (8003f40 ) + 8003d52: 681b ldr r3, [r3, #0] + 8003d54: f403 7380 and.w r3, r3, #256 @ 0x100 + 8003d58: f5b3 7f80 cmp.w r3, #256 @ 0x100 + 8003d5c: d1ee bne.n 8003d3c + } + } + + if (ret == HAL_OK) + 8003d5e: 7cfb ldrb r3, [r7, #19] + 8003d60: 2b00 cmp r3, #0 + 8003d62: d13c bne.n 8003dde + { + /* Reset the Backup domain only if the RTC Clock source selection is modified */ + if (LL_RCC_GetRTCClockSource() != PeriphClkInit->RTCClockSelection) + 8003d64: f7ff ffa7 bl 8003cb6 + 8003d68: 4602 mov r2, r0 + 8003d6a: 687b ldr r3, [r7, #4] + 8003d6c: 6b5b ldr r3, [r3, #52] @ 0x34 + 8003d6e: 429a cmp r2, r3 + 8003d70: d00f beq.n 8003d92 + { + /* Store the content of BDCR register before the reset of Backup Domain */ + tmpregister = READ_BIT(RCC->BDCR, ~(RCC_BDCR_RTCSEL)); + 8003d72: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8003d76: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 8003d7a: f423 7340 bic.w r3, r3, #768 @ 0x300 + 8003d7e: 617b str r3, [r7, #20] + + /* RTC Clock selection can be changed only if the Backup Domain is reset */ + __HAL_RCC_BACKUPRESET_FORCE(); + 8003d80: f7ff ffa5 bl 8003cce + __HAL_RCC_BACKUPRESET_RELEASE(); + 8003d84: f7ff ffb3 bl 8003cee + + /* Restore the Content of BDCR register */ + RCC->BDCR = tmpregister; + 8003d88: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 8003d8c: 697b ldr r3, [r7, #20] + 8003d8e: f8c2 3090 str.w r3, [r2, #144] @ 0x90 + } + + /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */ + if (HAL_IS_BIT_SET(tmpregister, RCC_BDCR_LSERDY)) + 8003d92: 697b ldr r3, [r7, #20] + 8003d94: f003 0302 and.w r3, r3, #2 + 8003d98: 2b00 cmp r3, #0 + 8003d9a: d014 beq.n 8003dc6 + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8003d9c: f7fc fef0 bl 8000b80 + 8003da0: 60f8 str r0, [r7, #12] + + /* Wait till LSE is ready */ + while (LL_RCC_LSE_IsReady() != 1U) + 8003da2: e00b b.n 8003dbc + { + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + 8003da4: f7fc feec bl 8000b80 + 8003da8: 4602 mov r2, r0 + 8003daa: 68fb ldr r3, [r7, #12] + 8003dac: 1ad3 subs r3, r2, r3 + 8003dae: f241 3288 movw r2, #5000 @ 0x1388 + 8003db2: 4293 cmp r3, r2 + 8003db4: d902 bls.n 8003dbc + { + ret = HAL_TIMEOUT; + 8003db6: 2303 movs r3, #3 + 8003db8: 74fb strb r3, [r7, #19] + break; + 8003dba: e004 b.n 8003dc6 + while (LL_RCC_LSE_IsReady() != 1U) + 8003dbc: f7ff feb4 bl 8003b28 + 8003dc0: 4603 mov r3, r0 + 8003dc2: 2b01 cmp r3, #1 + 8003dc4: d1ee bne.n 8003da4 + } + } + } + + if (ret == HAL_OK) + 8003dc6: 7cfb ldrb r3, [r7, #19] + 8003dc8: 2b00 cmp r3, #0 + 8003dca: d105 bne.n 8003dd8 + { + /* Apply new RTC clock source selection */ + __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); + 8003dcc: 687b ldr r3, [r7, #4] + 8003dce: 6b5b ldr r3, [r3, #52] @ 0x34 + 8003dd0: 4618 mov r0, r3 + 8003dd2: f7ff ff5b bl 8003c8c + 8003dd6: e004 b.n 8003de2 + } + else + { + /* set overall return value */ + status = ret; + 8003dd8: 7cfb ldrb r3, [r7, #19] + 8003dda: 74bb strb r3, [r7, #18] + 8003ddc: e001 b.n 8003de2 + } + } + else + { + /* set overall return value */ + status = ret; + 8003dde: 7cfb ldrb r3, [r7, #19] + 8003de0: 74bb strb r3, [r7, #18] + } + + } + + /*-------------------- USART1 clock source configuration -------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) + 8003de2: 687b ldr r3, [r7, #4] + 8003de4: 681b ldr r3, [r3, #0] + 8003de6: f003 0301 and.w r3, r3, #1 + 8003dea: 2b00 cmp r3, #0 + 8003dec: d004 beq.n 8003df8 + { + /* Check the parameters */ + assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection)); + + /* Configure the USART1 clock source */ + __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection); + 8003dee: 687b ldr r3, [r7, #4] + 8003df0: 685b ldr r3, [r3, #4] + 8003df2: 4618 mov r0, r3 + 8003df4: f7ff fea9 bl 8003b4a + } + + /*-------------------- USART2 clock source configuration -------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) + 8003df8: 687b ldr r3, [r7, #4] + 8003dfa: 681b ldr r3, [r3, #0] + 8003dfc: f003 0302 and.w r3, r3, #2 + 8003e00: 2b00 cmp r3, #0 + 8003e02: d004 beq.n 8003e0e + { + /* Check the parameters */ + assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection)); + + /* Configure the USART2 clock source */ + __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection); + 8003e04: 687b ldr r3, [r7, #4] + 8003e06: 689b ldr r3, [r3, #8] + 8003e08: 4618 mov r0, r3 + 8003e0a: f7ff fe9e bl 8003b4a + } + + /*-------------------- LPUART1 clock source configuration ------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) + 8003e0e: 687b ldr r3, [r7, #4] + 8003e10: 681b ldr r3, [r3, #0] + 8003e12: f003 0320 and.w r3, r3, #32 + 8003e16: 2b00 cmp r3, #0 + 8003e18: d004 beq.n 8003e24 + { + /* Check the parameters */ + assert_param(IS_RCC_LPUART1CLKSOURCE(PeriphClkInit->Lpuart1ClockSelection)); + + /* Configure the LPUAR1 clock source */ + __HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection); + 8003e1a: 687b ldr r3, [r7, #4] + 8003e1c: 691b ldr r3, [r3, #16] + 8003e1e: 4618 mov r0, r3 + 8003e20: f7ff fec0 bl 8003ba4 + } + + /*-------------------- LPTIM1 clock source configuration -------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == (RCC_PERIPHCLK_LPTIM1)) + 8003e24: 687b ldr r3, [r7, #4] + 8003e26: 681b ldr r3, [r3, #0] + 8003e28: f403 7300 and.w r3, r3, #512 @ 0x200 + 8003e2c: 2b00 cmp r3, #0 + 8003e2e: d004 beq.n 8003e3a + { + /* Check the parameters */ + assert_param(IS_RCC_LPTIM1CLKSOURCE(PeriphClkInit->Lptim1ClockSelection)); + + /* Configure the LPTIM1 clock source */ + __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection); + 8003e30: 687b ldr r3, [r7, #4] + 8003e32: 6a1b ldr r3, [r3, #32] + 8003e34: 4618 mov r0, r3 + 8003e36: f7ff fee6 bl 8003c06 + } + + /*-------------------- LPTIM2 clock source configuration -------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM2) == (RCC_PERIPHCLK_LPTIM2)) + 8003e3a: 687b ldr r3, [r7, #4] + 8003e3c: 681b ldr r3, [r3, #0] + 8003e3e: f403 6380 and.w r3, r3, #1024 @ 0x400 + 8003e42: 2b00 cmp r3, #0 + 8003e44: d004 beq.n 8003e50 + { + /* Check the parameters */ + assert_param(IS_RCC_LPTIM2CLKSOURCE(PeriphClkInit->Lptim2ClockSelection)); + + /* Configure the LPTIM2 clock source */ + __HAL_RCC_LPTIM2_CONFIG(PeriphClkInit->Lptim2ClockSelection); + 8003e46: 687b ldr r3, [r7, #4] + 8003e48: 6a5b ldr r3, [r3, #36] @ 0x24 + 8003e4a: 4618 mov r0, r3 + 8003e4c: f7ff fedb bl 8003c06 + } + + /*-------------------- LPTIM3 clock source configuration -------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM3) == (RCC_PERIPHCLK_LPTIM3)) + 8003e50: 687b ldr r3, [r7, #4] + 8003e52: 681b ldr r3, [r3, #0] + 8003e54: f403 6300 and.w r3, r3, #2048 @ 0x800 + 8003e58: 2b00 cmp r3, #0 + 8003e5a: d004 beq.n 8003e66 + { + /* Check the parameters */ + assert_param(IS_RCC_LPTIM3CLKSOURCE(PeriphClkInit->Lptim3ClockSelection)); + + /* Configure the LPTIM3 clock source */ + __HAL_RCC_LPTIM3_CONFIG(PeriphClkInit->Lptim3ClockSelection); + 8003e5c: 687b ldr r3, [r7, #4] + 8003e5e: 6a9b ldr r3, [r3, #40] @ 0x28 + 8003e60: 4618 mov r0, r3 + 8003e62: f7ff fed0 bl 8003c06 + } + + /*-------------------- I2C1 clock source configuration ---------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) + 8003e66: 687b ldr r3, [r7, #4] + 8003e68: 681b ldr r3, [r3, #0] + 8003e6a: f003 0340 and.w r3, r3, #64 @ 0x40 + 8003e6e: 2b00 cmp r3, #0 + 8003e70: d004 beq.n 8003e7c + { + /* Check the parameters */ + assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection)); + + /* Configure the I2C1 clock source */ + __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection); + 8003e72: 687b ldr r3, [r7, #4] + 8003e74: 695b ldr r3, [r3, #20] + 8003e76: 4618 mov r0, r3 + 8003e78: f7ff fea9 bl 8003bce + } + + /*-------------------- I2C2 clock source configuration ---------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) + 8003e7c: 687b ldr r3, [r7, #4] + 8003e7e: 681b ldr r3, [r3, #0] + 8003e80: f003 0380 and.w r3, r3, #128 @ 0x80 + 8003e84: 2b00 cmp r3, #0 + 8003e86: d004 beq.n 8003e92 + { + /* Check the parameters */ + assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection)); + + /* Configure the I2C2 clock source */ + __HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection); + 8003e88: 687b ldr r3, [r7, #4] + 8003e8a: 699b ldr r3, [r3, #24] + 8003e8c: 4618 mov r0, r3 + 8003e8e: f7ff fe9e bl 8003bce + } + + /*-------------------- I2C3 clock source configuration ---------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) + 8003e92: 687b ldr r3, [r7, #4] + 8003e94: 681b ldr r3, [r3, #0] + 8003e96: f403 7380 and.w r3, r3, #256 @ 0x100 + 8003e9a: 2b00 cmp r3, #0 + 8003e9c: d004 beq.n 8003ea8 + { + /* Check the parameters */ + assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection)); + + /* Configure the I2C3 clock source */ + __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection); + 8003e9e: 687b ldr r3, [r7, #4] + 8003ea0: 69db ldr r3, [r3, #28] + 8003ea2: 4618 mov r0, r3 + 8003ea4: f7ff fe93 bl 8003bce + } + + /*-------------------- I2S2 clock source configuration ---------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S2) == (RCC_PERIPHCLK_I2S2)) + 8003ea8: 687b ldr r3, [r7, #4] + 8003eaa: 681b ldr r3, [r3, #0] + 8003eac: f003 0310 and.w r3, r3, #16 + 8003eb0: 2b00 cmp r3, #0 + 8003eb2: d011 beq.n 8003ed8 + { + /* Check the parameters */ + assert_param(IS_RCC_I2S2CLKSOURCE(PeriphClkInit->I2s2ClockSelection)); + + /* Configure the I2S2 clock source */ + __HAL_RCC_I2S2_CONFIG(PeriphClkInit->I2s2ClockSelection); + 8003eb4: 687b ldr r3, [r7, #4] + 8003eb6: 68db ldr r3, [r3, #12] + 8003eb8: 4618 mov r0, r3 + 8003eba: f7ff fe5e bl 8003b7a + + if (PeriphClkInit->I2s2ClockSelection == RCC_I2S2CLKSOURCE_PLL) + 8003ebe: 687b ldr r3, [r7, #4] + 8003ec0: 68db ldr r3, [r3, #12] + 8003ec2: f5b3 7f80 cmp.w r3, #256 @ 0x100 + 8003ec6: d107 bne.n 8003ed8 + { + /* Enable RCC_PLL_I2S2CLK output */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_I2S2CLK); + 8003ec8: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8003ecc: 68db ldr r3, [r3, #12] + 8003ece: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 8003ed2: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000 + 8003ed6: 60d3 str r3, [r2, #12] + } + } + + /*-------------------- RNG clock source configuration ----------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == (RCC_PERIPHCLK_RNG)) + 8003ed8: 687b ldr r3, [r7, #4] + 8003eda: 681b ldr r3, [r3, #0] + 8003edc: f403 4300 and.w r3, r3, #32768 @ 0x8000 + 8003ee0: 2b00 cmp r3, #0 + 8003ee2: d010 beq.n 8003f06 + { + assert_param(IS_RCC_RNGCLKSOURCE(PeriphClkInit->RngClockSelection)); + __HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection); + 8003ee4: 687b ldr r3, [r7, #4] + 8003ee6: 6b1b ldr r3, [r3, #48] @ 0x30 + 8003ee8: 4618 mov r0, r3 + 8003eea: f7ff fea5 bl 8003c38 + + if (PeriphClkInit->RngClockSelection == RCC_RNGCLKSOURCE_PLL) + 8003eee: 687b ldr r3, [r7, #4] + 8003ef0: 6b1b ldr r3, [r3, #48] @ 0x30 + 8003ef2: 2b00 cmp r3, #0 + 8003ef4: d107 bne.n 8003f06 + { + /* Enable RCC_PLL_RNGCLK output */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_RNGCLK); + 8003ef6: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8003efa: 68db ldr r3, [r3, #12] + 8003efc: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 8003f00: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000 + 8003f04: 60d3 str r3, [r2, #12] + } + } + + /*-------------------- ADC clock source configuration ----------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) + 8003f06: 687b ldr r3, [r7, #4] + 8003f08: 681b ldr r3, [r3, #0] + 8003f0a: f403 4380 and.w r3, r3, #16384 @ 0x4000 + 8003f0e: 2b00 cmp r3, #0 + 8003f10: d011 beq.n 8003f36 + { + /* Check the parameters */ + assert_param(IS_RCC_ADCCLKSOURCE(PeriphClkInit->AdcClockSelection)); + + /* Configure the ADC interface clock source */ + __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection); + 8003f12: 687b ldr r3, [r7, #4] + 8003f14: 6adb ldr r3, [r3, #44] @ 0x2c + 8003f16: 4618 mov r0, r3 + 8003f18: f7ff fea3 bl 8003c62 + + if (PeriphClkInit->AdcClockSelection == RCC_ADCCLKSOURCE_PLL) + 8003f1c: 687b ldr r3, [r7, #4] + 8003f1e: 6adb ldr r3, [r3, #44] @ 0x2c + 8003f20: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 + 8003f24: d107 bne.n 8003f36 + { + /* Enable RCC_PLL_RNGCLK output */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_ADCCLK); + 8003f26: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8003f2a: 68db ldr r3, [r3, #12] + 8003f2c: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 8003f30: f443 3380 orr.w r3, r3, #65536 @ 0x10000 + 8003f34: 60d3 str r3, [r2, #12] + } + } + + return status; + 8003f36: 7cbb ldrb r3, [r7, #18] +} + 8003f38: 4618 mov r0, r3 + 8003f3a: 3718 adds r7, #24 + 8003f3c: 46bd mov sp, r7 + 8003f3e: bd80 pop {r7, pc} + 8003f40: 58000400 .word 0x58000400 + +08003f44 : + * @brief Initialize the RTC peripheral + * @param hrtc RTC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc) +{ + 8003f44: b580 push {r7, lr} + 8003f46: b084 sub sp, #16 + 8003f48: af00 add r7, sp, #0 + 8003f4a: 6078 str r0, [r7, #4] + HAL_StatusTypeDef status = HAL_ERROR; + 8003f4c: 2301 movs r3, #1 + 8003f4e: 73fb strb r3, [r7, #15] + + /* Check the RTC peripheral state */ + if (hrtc != NULL) + 8003f50: 687b ldr r3, [r7, #4] + 8003f52: 2b00 cmp r3, #0 + 8003f54: d07b beq.n 800404e + { + hrtc->MspDeInitCallback = HAL_RTC_MspDeInit; + } + } +#else + if (hrtc->State == HAL_RTC_STATE_RESET) + 8003f56: 687b ldr r3, [r7, #4] + 8003f58: f893 302d ldrb.w r3, [r3, #45] @ 0x2d + 8003f5c: b2db uxtb r3, r3 + 8003f5e: 2b00 cmp r3, #0 + 8003f60: d106 bne.n 8003f70 + { + /* Allocate lock resource and initialize it */ + hrtc->Lock = HAL_UNLOCKED; + 8003f62: 687b ldr r3, [r7, #4] + 8003f64: 2200 movs r2, #0 + 8003f66: f883 202c strb.w r2, [r3, #44] @ 0x2c + + /* Initialize RTC MSP */ + HAL_RTC_MspInit(hrtc); + 8003f6a: 6878 ldr r0, [r7, #4] + 8003f6c: f7fc fc4c bl 8000808 + } +#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */ + + /* Set RTC state */ + hrtc->State = HAL_RTC_STATE_BUSY; + 8003f70: 687b ldr r3, [r7, #4] + 8003f72: 2202 movs r2, #2 + 8003f74: f883 202d strb.w r2, [r3, #45] @ 0x2d + + /* Check whether the calendar needs to be initialized */ + if (__HAL_RTC_IS_CALENDAR_INITIALIZED(hrtc) == 0U) + 8003f78: 4b37 ldr r3, [pc, #220] @ (8004058 ) + 8003f7a: 68db ldr r3, [r3, #12] + 8003f7c: f003 0310 and.w r3, r3, #16 + 8003f80: 2b10 cmp r3, #16 + 8003f82: d05b beq.n 800403c + { + /* Check that the RTC mode is not 'binary only' */ + if (__HAL_RTC_GET_BINARY_MODE(hrtc) != RTC_BINARY_ONLY) + 8003f84: 4b34 ldr r3, [pc, #208] @ (8004058 ) + 8003f86: 68db ldr r3, [r3, #12] + 8003f88: f403 7340 and.w r3, r3, #768 @ 0x300 + 8003f8c: f5b3 7f80 cmp.w r3, #256 @ 0x100 + 8003f90: d051 beq.n 8004036 + { + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + 8003f92: 4b31 ldr r3, [pc, #196] @ (8004058 ) + 8003f94: 22ca movs r2, #202 @ 0xca + 8003f96: 625a str r2, [r3, #36] @ 0x24 + 8003f98: 4b2f ldr r3, [pc, #188] @ (8004058 ) + 8003f9a: 2253 movs r2, #83 @ 0x53 + 8003f9c: 625a str r2, [r3, #36] @ 0x24 + + /* Enter Initialization mode */ + status = RTC_EnterInitMode(hrtc); + 8003f9e: 6878 ldr r0, [r7, #4] + 8003fa0: f000 fa14 bl 80043cc + 8003fa4: 4603 mov r3, r0 + 8003fa6: 73fb strb r3, [r7, #15] + + if (status == HAL_OK) + 8003fa8: 7bfb ldrb r3, [r7, #15] + 8003faa: 2b00 cmp r3, #0 + 8003fac: d13f bne.n 800402e + { + /* Clear RTC_CR FMT, OSEL and POL Bits */ + CLEAR_BIT(RTC->CR, (RTC_CR_FMT | RTC_CR_POL | RTC_CR_OSEL | RTC_CR_TAMPOE)); + 8003fae: 4b2a ldr r3, [pc, #168] @ (8004058 ) + 8003fb0: 699b ldr r3, [r3, #24] + 8003fb2: 4a29 ldr r2, [pc, #164] @ (8004058 ) + 8003fb4: f023 638e bic.w r3, r3, #74448896 @ 0x4700000 + 8003fb8: f023 0340 bic.w r3, r3, #64 @ 0x40 + 8003fbc: 6193 str r3, [r2, #24] + /* Set RTC_CR register */ + SET_BIT(RTC->CR, (hrtc->Init.HourFormat | hrtc->Init.OutPut | hrtc->Init.OutPutPolarity)); + 8003fbe: 4b26 ldr r3, [pc, #152] @ (8004058 ) + 8003fc0: 699a ldr r2, [r3, #24] + 8003fc2: 687b ldr r3, [r7, #4] + 8003fc4: 6859 ldr r1, [r3, #4] + 8003fc6: 687b ldr r3, [r7, #4] + 8003fc8: 691b ldr r3, [r3, #16] + 8003fca: 4319 orrs r1, r3 + 8003fcc: 687b ldr r3, [r7, #4] + 8003fce: 699b ldr r3, [r3, #24] + 8003fd0: 430b orrs r3, r1 + 8003fd2: 4921 ldr r1, [pc, #132] @ (8004058 ) + 8003fd4: 4313 orrs r3, r2 + 8003fd6: 618b str r3, [r1, #24] + + /* Configure the RTC PRER */ + WRITE_REG(RTC->PRER, ((hrtc->Init.SynchPrediv) | (hrtc->Init.AsynchPrediv << RTC_PRER_PREDIV_A_Pos))); + 8003fd8: 687b ldr r3, [r7, #4] + 8003fda: 68da ldr r2, [r3, #12] + 8003fdc: 687b ldr r3, [r7, #4] + 8003fde: 689b ldr r3, [r3, #8] + 8003fe0: 041b lsls r3, r3, #16 + 8003fe2: 491d ldr r1, [pc, #116] @ (8004058 ) + 8003fe4: 4313 orrs r3, r2 + 8003fe6: 610b str r3, [r1, #16] + + /* Configure the Binary mode */ + MODIFY_REG(RTC->ICSR, RTC_ICSR_BIN | RTC_ICSR_BCDU, hrtc->Init.BinMode | hrtc->Init.BinMixBcdU); + 8003fe8: 4b1b ldr r3, [pc, #108] @ (8004058 ) + 8003fea: 68db ldr r3, [r3, #12] + 8003fec: f423 52f8 bic.w r2, r3, #7936 @ 0x1f00 + 8003ff0: 687b ldr r3, [r7, #4] + 8003ff2: 6a59 ldr r1, [r3, #36] @ 0x24 + 8003ff4: 687b ldr r3, [r7, #4] + 8003ff6: 6a9b ldr r3, [r3, #40] @ 0x28 + 8003ff8: 430b orrs r3, r1 + 8003ffa: 4917 ldr r1, [pc, #92] @ (8004058 ) + 8003ffc: 4313 orrs r3, r2 + 8003ffe: 60cb str r3, [r1, #12] + + /* Exit Initialization mode */ + status = RTC_ExitInitMode(hrtc); + 8004000: 6878 ldr r0, [r7, #4] + 8004002: f000 fa17 bl 8004434 + 8004006: 4603 mov r3, r0 + 8004008: 73fb strb r3, [r7, #15] + + if (status == HAL_OK) + 800400a: 7bfb ldrb r3, [r7, #15] + 800400c: 2b00 cmp r3, #0 + 800400e: d10e bne.n 800402e + { + MODIFY_REG(RTC->CR, \ + 8004010: 4b11 ldr r3, [pc, #68] @ (8004058 ) + 8004012: 699b ldr r3, [r3, #24] + 8004014: f023 4260 bic.w r2, r3, #3758096384 @ 0xe0000000 + 8004018: 687b ldr r3, [r7, #4] + 800401a: 6a19 ldr r1, [r3, #32] + 800401c: 687b ldr r3, [r7, #4] + 800401e: 69db ldr r3, [r3, #28] + 8004020: 4319 orrs r1, r3 + 8004022: 687b ldr r3, [r7, #4] + 8004024: 695b ldr r3, [r3, #20] + 8004026: 430b orrs r3, r1 + 8004028: 490b ldr r1, [pc, #44] @ (8004058 ) + 800402a: 4313 orrs r3, r2 + 800402c: 618b str r3, [r1, #24] + hrtc->Init.OutPutPullUp | hrtc->Init.OutPutType | hrtc->Init.OutPutRemap); + } + } + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + 800402e: 4b0a ldr r3, [pc, #40] @ (8004058 ) + 8004030: 22ff movs r2, #255 @ 0xff + 8004032: 625a str r2, [r3, #36] @ 0x24 + 8004034: e004 b.n 8004040 + } + else + { + /* The calendar does not need to be initialized as the 'binary only' mode is selected */ + status = HAL_OK; + 8004036: 2300 movs r3, #0 + 8004038: 73fb strb r3, [r7, #15] + 800403a: e001 b.n 8004040 + } + } + else + { + /* The calendar is already initialized */ + status = HAL_OK; + 800403c: 2300 movs r3, #0 + 800403e: 73fb strb r3, [r7, #15] + } + + if (status == HAL_OK) + 8004040: 7bfb ldrb r3, [r7, #15] + 8004042: 2b00 cmp r3, #0 + 8004044: d103 bne.n 800404e + { + hrtc->State = HAL_RTC_STATE_READY; + 8004046: 687b ldr r3, [r7, #4] + 8004048: 2201 movs r2, #1 + 800404a: f883 202d strb.w r2, [r3, #45] @ 0x2d + } + } + + return status; + 800404e: 7bfb ldrb r3, [r7, #15] +} + 8004050: 4618 mov r0, r3 + 8004052: 3710 adds r7, #16 + 8004054: 46bd mov sp, r7 + 8004056: bd80 pop {r7, pc} + 8004058: 40002800 .word 0x40002800 + +0800405c : + * @arg RTC_FORMAT_BIN: Binary format + * @arg RTC_FORMAT_BCD: BCD format + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format) +{ + 800405c: b590 push {r4, r7, lr} + 800405e: b087 sub sp, #28 + 8004060: af00 add r7, sp, #0 + 8004062: 60f8 str r0, [r7, #12] + 8004064: 60b9 str r1, [r7, #8] + 8004066: 607a str r2, [r7, #4] + uint32_t tmpreg = 0; + 8004068: 2300 movs r3, #0 + 800406a: 617b str r3, [r7, #20] + uint32_t binaryMode; + + /* Process Locked */ + __HAL_LOCK(hrtc); + 800406c: 68fb ldr r3, [r7, #12] + 800406e: f893 302c ldrb.w r3, [r3, #44] @ 0x2c + 8004072: 2b01 cmp r3, #1 + 8004074: d101 bne.n 800407a + 8004076: 2302 movs r3, #2 + 8004078: e0f3 b.n 8004262 + 800407a: 68fb ldr r3, [r7, #12] + 800407c: 2201 movs r2, #1 + 800407e: f883 202c strb.w r2, [r3, #44] @ 0x2c + hrtc->State = HAL_RTC_STATE_BUSY; + 8004082: 68fb ldr r3, [r7, #12] + 8004084: 2202 movs r2, #2 + 8004086: f883 202d strb.w r2, [r3, #45] @ 0x2d + RTC_ICSR_BCDU) >> RTC_ICSR_BCDU_Pos))); + } +#endif /* USE_FULL_ASSERT */ + + /* Get Binary mode (32-bit free-running counter configuration) */ + binaryMode = READ_BIT(RTC->ICSR, RTC_ICSR_BIN); + 800408a: 4b78 ldr r3, [pc, #480] @ (800426c ) + 800408c: 68db ldr r3, [r3, #12] + 800408e: f403 7340 and.w r3, r3, #768 @ 0x300 + 8004092: 613b str r3, [r7, #16] + + if (binaryMode != RTC_BINARY_ONLY) + 8004094: 693b ldr r3, [r7, #16] + 8004096: f5b3 7f80 cmp.w r3, #256 @ 0x100 + 800409a: d06a beq.n 8004172 + { + if (Format == RTC_FORMAT_BIN) + 800409c: 687b ldr r3, [r7, #4] + 800409e: 2b00 cmp r3, #0 + 80040a0: d13a bne.n 8004118 + { + if (READ_BIT(RTC->CR, RTC_CR_FMT) != 0U) + 80040a2: 4b72 ldr r3, [pc, #456] @ (800426c ) + 80040a4: 699b ldr r3, [r3, #24] + 80040a6: f003 0340 and.w r3, r3, #64 @ 0x40 + 80040aa: 2b00 cmp r3, #0 + 80040ac: d102 bne.n 80040b4 + assert_param(IS_RTC_HOUR12(sAlarm->AlarmTime.Hours)); + assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat)); + } + else + { + sAlarm->AlarmTime.TimeFormat = 0x00U; + 80040ae: 68bb ldr r3, [r7, #8] + 80040b0: 2200 movs r2, #0 + 80040b2: 70da strb r2, [r3, #3] + assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours)); + } + assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes)); + assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds)); + + if (sAlarm->AlarmMask != RTC_ALARMMASK_DATEWEEKDAY) + 80040b4: 68bb ldr r3, [r7, #8] + 80040b6: 695b ldr r3, [r3, #20] + 80040b8: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 + { + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay)); + } + } + + tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << RTC_ALRMAR_HU_Pos) | \ + 80040bc: 68bb ldr r3, [r7, #8] + 80040be: 781b ldrb r3, [r3, #0] + 80040c0: 4618 mov r0, r3 + 80040c2: f000 f9f5 bl 80044b0 + 80040c6: 4603 mov r3, r0 + 80040c8: 041c lsls r4, r3, #16 + ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << RTC_ALRMAR_MNU_Pos) | \ + 80040ca: 68bb ldr r3, [r7, #8] + 80040cc: 785b ldrb r3, [r3, #1] + 80040ce: 4618 mov r0, r3 + 80040d0: f000 f9ee bl 80044b0 + 80040d4: 4603 mov r3, r0 + 80040d6: 021b lsls r3, r3, #8 + tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << RTC_ALRMAR_HU_Pos) | \ + 80040d8: 431c orrs r4, r3 + ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds) << RTC_ALRMAR_SU_Pos) | \ + 80040da: 68bb ldr r3, [r7, #8] + 80040dc: 789b ldrb r3, [r3, #2] + 80040de: 4618 mov r0, r3 + 80040e0: f000 f9e6 bl 80044b0 + 80040e4: 4603 mov r3, r0 + ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << RTC_ALRMAR_MNU_Pos) | \ + 80040e6: ea44 0203 orr.w r2, r4, r3 + ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_ALRMAR_PM_Pos) | \ + 80040ea: 68bb ldr r3, [r7, #8] + 80040ec: 78db ldrb r3, [r3, #3] + 80040ee: 059b lsls r3, r3, #22 + ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds) << RTC_ALRMAR_SU_Pos) | \ + 80040f0: ea42 0403 orr.w r4, r2, r3 + ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << RTC_ALRMAR_DU_Pos) | \ + 80040f4: 68bb ldr r3, [r7, #8] + 80040f6: f893 3024 ldrb.w r3, [r3, #36] @ 0x24 + 80040fa: 4618 mov r0, r3 + 80040fc: f000 f9d8 bl 80044b0 + 8004100: 4603 mov r3, r0 + 8004102: 061b lsls r3, r3, #24 + ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_ALRMAR_PM_Pos) | \ + 8004104: ea44 0203 orr.w r2, r4, r3 + ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \ + 8004108: 68bb ldr r3, [r7, #8] + 800410a: 6a1b ldr r3, [r3, #32] + ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << RTC_ALRMAR_DU_Pos) | \ + 800410c: 431a orrs r2, r3 + ((uint32_t)sAlarm->AlarmMask)); + 800410e: 68bb ldr r3, [r7, #8] + 8004110: 695b ldr r3, [r3, #20] + tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << RTC_ALRMAR_HU_Pos) | \ + 8004112: 4313 orrs r3, r2 + 8004114: 617b str r3, [r7, #20] + 8004116: e02c b.n 8004172 + } + else /* Format BCD */ + { + if (sAlarm->AlarmMask != RTC_ALARMMASK_ALL) + 8004118: 68bb ldr r3, [r7, #8] + 800411a: 695b ldr r3, [r3, #20] + 800411c: f1b3 3f80 cmp.w r3, #2155905152 @ 0x80808080 + 8004120: d00d beq.n 800413e + { + if (sAlarm->AlarmMask != RTC_ALARMMASK_HOURS) + 8004122: 68bb ldr r3, [r7, #8] + 8004124: 695b ldr r3, [r3, #20] + 8004126: f5b3 0f00 cmp.w r3, #8388608 @ 0x800000 + 800412a: d008 beq.n 800413e + { + if (READ_BIT(RTC->CR, RTC_CR_FMT) != 0U) + 800412c: 4b4f ldr r3, [pc, #316] @ (800426c ) + 800412e: 699b ldr r3, [r3, #24] + 8004130: f003 0340 and.w r3, r3, #64 @ 0x40 + 8004134: 2b00 cmp r3, #0 + 8004136: d102 bne.n 800413e + assert_param(IS_RTC_HOUR12(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours))); + assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat)); + } + else + { + sAlarm->AlarmTime.TimeFormat = 0x00U; + 8004138: 68bb ldr r3, [r7, #8] + 800413a: 2200 movs r2, #0 + 800413c: 70da strb r2, [r3, #3] + { + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay))); + } + } +#endif /* USE_FULL_ASSERT */ + tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << RTC_ALRMAR_HU_Pos) | \ + 800413e: 68bb ldr r3, [r7, #8] + 8004140: 781b ldrb r3, [r3, #0] + 8004142: 041a lsls r2, r3, #16 + ((uint32_t)(sAlarm->AlarmTime.Minutes) << RTC_ALRMAR_MNU_Pos) | \ + 8004144: 68bb ldr r3, [r7, #8] + 8004146: 785b ldrb r3, [r3, #1] + 8004148: 021b lsls r3, r3, #8 + tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << RTC_ALRMAR_HU_Pos) | \ + 800414a: 4313 orrs r3, r2 + ((uint32_t)(sAlarm->AlarmTime.Seconds) << RTC_ALRMAR_SU_Pos) | \ + 800414c: 68ba ldr r2, [r7, #8] + 800414e: 7892 ldrb r2, [r2, #2] + ((uint32_t)(sAlarm->AlarmTime.Minutes) << RTC_ALRMAR_MNU_Pos) | \ + 8004150: 431a orrs r2, r3 + ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_ALRMAR_PM_Pos) | \ + 8004152: 68bb ldr r3, [r7, #8] + 8004154: 78db ldrb r3, [r3, #3] + 8004156: 059b lsls r3, r3, #22 + ((uint32_t)(sAlarm->AlarmTime.Seconds) << RTC_ALRMAR_SU_Pos) | \ + 8004158: 431a orrs r2, r3 + ((uint32_t)(sAlarm->AlarmDateWeekDay) << RTC_ALRMAR_DU_Pos) | \ + 800415a: 68bb ldr r3, [r7, #8] + 800415c: f893 3024 ldrb.w r3, [r3, #36] @ 0x24 + 8004160: 061b lsls r3, r3, #24 + ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_ALRMAR_PM_Pos) | \ + 8004162: 431a orrs r2, r3 + ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \ + 8004164: 68bb ldr r3, [r7, #8] + 8004166: 6a1b ldr r3, [r3, #32] + ((uint32_t)(sAlarm->AlarmDateWeekDay) << RTC_ALRMAR_DU_Pos) | \ + 8004168: 431a orrs r2, r3 + ((uint32_t)sAlarm->AlarmMask)); + 800416a: 68bb ldr r3, [r7, #8] + 800416c: 695b ldr r3, [r3, #20] + tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << RTC_ALRMAR_HU_Pos) | \ + 800416e: 4313 orrs r3, r2 + 8004170: 617b str r3, [r7, #20] + + } + } + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + 8004172: 4b3e ldr r3, [pc, #248] @ (800426c ) + 8004174: 22ca movs r2, #202 @ 0xca + 8004176: 625a str r2, [r3, #36] @ 0x24 + 8004178: 4b3c ldr r3, [pc, #240] @ (800426c ) + 800417a: 2253 movs r2, #83 @ 0x53 + 800417c: 625a str r2, [r3, #36] @ 0x24 + + /* Configure the Alarm register */ + if (sAlarm->Alarm == RTC_ALARM_A) + 800417e: 68bb ldr r3, [r7, #8] + 8004180: 6a9b ldr r3, [r3, #40] @ 0x28 + 8004182: f5b3 7f80 cmp.w r3, #256 @ 0x100 + 8004186: d12c bne.n 80041e2 + { + /* Disable the Alarm A interrupt */ + CLEAR_BIT(RTC->CR, RTC_CR_ALRAE | RTC_CR_ALRAIE); + 8004188: 4b38 ldr r3, [pc, #224] @ (800426c ) + 800418a: 699b ldr r3, [r3, #24] + 800418c: 4a37 ldr r2, [pc, #220] @ (800426c ) + 800418e: f423 5388 bic.w r3, r3, #4352 @ 0x1100 + 8004192: 6193 str r3, [r2, #24] + /* Clear flag alarm A */ + WRITE_REG(RTC->SCR, RTC_SCR_CALRAF); + 8004194: 4b35 ldr r3, [pc, #212] @ (800426c ) + 8004196: 2201 movs r2, #1 + 8004198: 65da str r2, [r3, #92] @ 0x5c + + if (binaryMode == RTC_BINARY_ONLY) + 800419a: 693b ldr r3, [r7, #16] + 800419c: f5b3 7f80 cmp.w r3, #256 @ 0x100 + 80041a0: d107 bne.n 80041b2 + { + RTC->ALRMASSR = sAlarm->AlarmSubSecondMask | sAlarm->BinaryAutoClr; + 80041a2: 68bb ldr r3, [r7, #8] + 80041a4: 699a ldr r2, [r3, #24] + 80041a6: 68bb ldr r3, [r7, #8] + 80041a8: 69db ldr r3, [r3, #28] + 80041aa: 4930 ldr r1, [pc, #192] @ (800426c ) + 80041ac: 4313 orrs r3, r2 + 80041ae: 644b str r3, [r1, #68] @ 0x44 + 80041b0: e006 b.n 80041c0 + } + else + { + WRITE_REG(RTC->ALRMAR, tmpreg); + 80041b2: 4a2e ldr r2, [pc, #184] @ (800426c ) + 80041b4: 697b ldr r3, [r7, #20] + 80041b6: 6413 str r3, [r2, #64] @ 0x40 + WRITE_REG(RTC->ALRMASSR, sAlarm->AlarmSubSecondMask); + 80041b8: 4a2c ldr r2, [pc, #176] @ (800426c ) + 80041ba: 68bb ldr r3, [r7, #8] + 80041bc: 699b ldr r3, [r3, #24] + 80041be: 6453 str r3, [r2, #68] @ 0x44 + } + + WRITE_REG(RTC->ALRABINR, sAlarm->AlarmTime.SubSeconds); + 80041c0: 4a2a ldr r2, [pc, #168] @ (800426c ) + 80041c2: 68bb ldr r3, [r7, #8] + 80041c4: 685b ldr r3, [r3, #4] + 80041c6: 6713 str r3, [r2, #112] @ 0x70 + + /* Store in the handle the Alarm A enabled */ + SET_BIT(hrtc->IsEnabled.RtcFeatures, RTC_MISR_ALRAMF); + 80041c8: 68fb ldr r3, [r7, #12] + 80041ca: 6b1b ldr r3, [r3, #48] @ 0x30 + 80041cc: f043 0201 orr.w r2, r3, #1 + 80041d0: 68fb ldr r3, [r7, #12] + 80041d2: 631a str r2, [r3, #48] @ 0x30 + + /* Configure the Alarm interrupt */ + SET_BIT(RTC->CR, RTC_CR_ALRAE | RTC_CR_ALRAIE); + 80041d4: 4b25 ldr r3, [pc, #148] @ (800426c ) + 80041d6: 699b ldr r3, [r3, #24] + 80041d8: 4a24 ldr r2, [pc, #144] @ (800426c ) + 80041da: f443 5388 orr.w r3, r3, #4352 @ 0x1100 + 80041de: 6193 str r3, [r2, #24] + 80041e0: e02b b.n 800423a + } + else + { + /* Disable the Alarm B interrupt */ + CLEAR_BIT(RTC->CR, RTC_CR_ALRBE | RTC_CR_ALRBIE); + 80041e2: 4b22 ldr r3, [pc, #136] @ (800426c ) + 80041e4: 699b ldr r3, [r3, #24] + 80041e6: 4a21 ldr r2, [pc, #132] @ (800426c ) + 80041e8: f423 5308 bic.w r3, r3, #8704 @ 0x2200 + 80041ec: 6193 str r3, [r2, #24] + /* Clear flag alarm B */ + WRITE_REG(RTC->SCR, RTC_SCR_CALRBF); + 80041ee: 4b1f ldr r3, [pc, #124] @ (800426c ) + 80041f0: 2202 movs r2, #2 + 80041f2: 65da str r2, [r3, #92] @ 0x5c + + if (binaryMode == RTC_BINARY_ONLY) + 80041f4: 693b ldr r3, [r7, #16] + 80041f6: f5b3 7f80 cmp.w r3, #256 @ 0x100 + 80041fa: d107 bne.n 800420c + { + WRITE_REG(RTC->ALRMBSSR, sAlarm->AlarmSubSecondMask | sAlarm->BinaryAutoClr); + 80041fc: 68bb ldr r3, [r7, #8] + 80041fe: 699a ldr r2, [r3, #24] + 8004200: 68bb ldr r3, [r7, #8] + 8004202: 69db ldr r3, [r3, #28] + 8004204: 4919 ldr r1, [pc, #100] @ (800426c ) + 8004206: 4313 orrs r3, r2 + 8004208: 64cb str r3, [r1, #76] @ 0x4c + 800420a: e006 b.n 800421a + } + else + { + WRITE_REG(RTC->ALRMBR, tmpreg); + 800420c: 4a17 ldr r2, [pc, #92] @ (800426c ) + 800420e: 697b ldr r3, [r7, #20] + 8004210: 6493 str r3, [r2, #72] @ 0x48 + WRITE_REG(RTC->ALRMBSSR, sAlarm->AlarmSubSecondMask); + 8004212: 4a16 ldr r2, [pc, #88] @ (800426c ) + 8004214: 68bb ldr r3, [r7, #8] + 8004216: 699b ldr r3, [r3, #24] + 8004218: 64d3 str r3, [r2, #76] @ 0x4c + } + + WRITE_REG(RTC->ALRBBINR, sAlarm->AlarmTime.SubSeconds); + 800421a: 4a14 ldr r2, [pc, #80] @ (800426c ) + 800421c: 68bb ldr r3, [r7, #8] + 800421e: 685b ldr r3, [r3, #4] + 8004220: 6753 str r3, [r2, #116] @ 0x74 + + /* Store in the handle the Alarm B enabled */ + SET_BIT(hrtc->IsEnabled.RtcFeatures, RTC_MISR_ALRBMF); + 8004222: 68fb ldr r3, [r7, #12] + 8004224: 6b1b ldr r3, [r3, #48] @ 0x30 + 8004226: f043 0202 orr.w r2, r3, #2 + 800422a: 68fb ldr r3, [r7, #12] + 800422c: 631a str r2, [r3, #48] @ 0x30 + + /* Configure the Alarm interrupt */ + SET_BIT(RTC->CR, RTC_CR_ALRBE | RTC_CR_ALRBIE); + 800422e: 4b0f ldr r3, [pc, #60] @ (800426c ) + 8004230: 699b ldr r3, [r3, #24] + 8004232: 4a0e ldr r2, [pc, #56] @ (800426c ) + 8004234: f443 5308 orr.w r3, r3, #8704 @ 0x2200 + 8004238: 6193 str r3, [r2, #24] + } + + /* RTC Alarm Interrupt Configuration: EXTI configuration */ + __HAL_RTC_ALARM_EXTI_ENABLE_IT(); + 800423a: 4b0d ldr r3, [pc, #52] @ (8004270 ) + 800423c: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 + 8004240: 4a0b ldr r2, [pc, #44] @ (8004270 ) + 8004242: f443 3300 orr.w r3, r3, #131072 @ 0x20000 + 8004246: f8c2 3080 str.w r3, [r2, #128] @ 0x80 + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + 800424a: 4b08 ldr r3, [pc, #32] @ (800426c ) + 800424c: 22ff movs r2, #255 @ 0xff + 800424e: 625a str r2, [r3, #36] @ 0x24 + + hrtc->State = HAL_RTC_STATE_READY; + 8004250: 68fb ldr r3, [r7, #12] + 8004252: 2201 movs r2, #1 + 8004254: f883 202d strb.w r2, [r3, #45] @ 0x2d + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + 8004258: 68fb ldr r3, [r7, #12] + 800425a: 2200 movs r2, #0 + 800425c: f883 202c strb.w r2, [r3, #44] @ 0x2c + + return HAL_OK; + 8004260: 2300 movs r3, #0 +} + 8004262: 4618 mov r0, r3 + 8004264: 371c adds r7, #28 + 8004266: 46bd mov sp, r7 + 8004268: bd90 pop {r4, r7, pc} + 800426a: bf00 nop + 800426c: 40002800 .word 0x40002800 + 8004270: 58000800 .word 0x58000800 + +08004274 : + * @arg RTC_ALARM_A: AlarmA + * @arg RTC_ALARM_B: AlarmB + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm) +{ + 8004274: b480 push {r7} + 8004276: b083 sub sp, #12 + 8004278: af00 add r7, sp, #0 + 800427a: 6078 str r0, [r7, #4] + 800427c: 6039 str r1, [r7, #0] + /* Check the parameters */ + assert_param(IS_RTC_ALARM(Alarm)); + + /* Process Locked */ + __HAL_LOCK(hrtc); + 800427e: 687b ldr r3, [r7, #4] + 8004280: f893 302c ldrb.w r3, [r3, #44] @ 0x2c + 8004284: 2b01 cmp r3, #1 + 8004286: d101 bne.n 800428c + 8004288: 2302 movs r3, #2 + 800428a: e048 b.n 800431e + 800428c: 687b ldr r3, [r7, #4] + 800428e: 2201 movs r2, #1 + 8004290: f883 202c strb.w r2, [r3, #44] @ 0x2c + + hrtc->State = HAL_RTC_STATE_BUSY; + 8004294: 687b ldr r3, [r7, #4] + 8004296: 2202 movs r2, #2 + 8004298: f883 202d strb.w r2, [r3, #45] @ 0x2d + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + 800429c: 4b22 ldr r3, [pc, #136] @ (8004328 ) + 800429e: 22ca movs r2, #202 @ 0xca + 80042a0: 625a str r2, [r3, #36] @ 0x24 + 80042a2: 4b21 ldr r3, [pc, #132] @ (8004328 ) + 80042a4: 2253 movs r2, #83 @ 0x53 + 80042a6: 625a str r2, [r3, #36] @ 0x24 + + if (Alarm == RTC_ALARM_A) + 80042a8: 683b ldr r3, [r7, #0] + 80042aa: f5b3 7f80 cmp.w r3, #256 @ 0x100 + 80042ae: d115 bne.n 80042dc + { + /* AlarmA, In case of interrupt mode is used, the interrupt source must disabled */ + CLEAR_BIT(RTC->CR, RTC_CR_ALRAE | RTC_CR_ALRAIE); + 80042b0: 4b1d ldr r3, [pc, #116] @ (8004328 ) + 80042b2: 699b ldr r3, [r3, #24] + 80042b4: 4a1c ldr r2, [pc, #112] @ (8004328 ) + 80042b6: f423 5388 bic.w r3, r3, #4352 @ 0x1100 + 80042ba: 6193 str r3, [r2, #24] + + /* AlarmA, Clear SSCLR */ + CLEAR_BIT(RTC->ALRMASSR, RTC_ALRMASSR_SSCLR); + 80042bc: 4b1a ldr r3, [pc, #104] @ (8004328 ) + 80042be: 6c5b ldr r3, [r3, #68] @ 0x44 + 80042c0: 4a19 ldr r2, [pc, #100] @ (8004328 ) + 80042c2: f023 4300 bic.w r3, r3, #2147483648 @ 0x80000000 + 80042c6: 6453 str r3, [r2, #68] @ 0x44 + + /* Store in the handle the Alarm A disabled */ + CLEAR_BIT(hrtc->IsEnabled.RtcFeatures, RTC_MISR_ALRAMF); + 80042c8: 687b ldr r3, [r7, #4] + 80042ca: 6b1b ldr r3, [r3, #48] @ 0x30 + 80042cc: f023 0201 bic.w r2, r3, #1 + 80042d0: 687b ldr r3, [r7, #4] + 80042d2: 631a str r2, [r3, #48] @ 0x30 + + /* Clear AlarmA flag */ + WRITE_REG(RTC->SCR, RTC_SCR_CALRAF); + 80042d4: 4b14 ldr r3, [pc, #80] @ (8004328 ) + 80042d6: 2201 movs r2, #1 + 80042d8: 65da str r2, [r3, #92] @ 0x5c + 80042da: e014 b.n 8004306 + } + else + { + /* AlarmB, In case of interrupt mode is used, the interrupt source must disabled */ + CLEAR_BIT(RTC->CR, RTC_CR_ALRBE | RTC_CR_ALRBIE); + 80042dc: 4b12 ldr r3, [pc, #72] @ (8004328 ) + 80042de: 699b ldr r3, [r3, #24] + 80042e0: 4a11 ldr r2, [pc, #68] @ (8004328 ) + 80042e2: f423 5308 bic.w r3, r3, #8704 @ 0x2200 + 80042e6: 6193 str r3, [r2, #24] + + /* AlarmB, Clear SSCLR */ + CLEAR_BIT(RTC->ALRMBSSR, RTC_ALRMBSSR_SSCLR); + 80042e8: 4b0f ldr r3, [pc, #60] @ (8004328 ) + 80042ea: 6cdb ldr r3, [r3, #76] @ 0x4c + 80042ec: 4a0e ldr r2, [pc, #56] @ (8004328 ) + 80042ee: f023 4300 bic.w r3, r3, #2147483648 @ 0x80000000 + 80042f2: 64d3 str r3, [r2, #76] @ 0x4c + + /* Store in the handle the Alarm B disabled */ + CLEAR_BIT(hrtc->IsEnabled.RtcFeatures, RTC_MISR_ALRBMF); + 80042f4: 687b ldr r3, [r7, #4] + 80042f6: 6b1b ldr r3, [r3, #48] @ 0x30 + 80042f8: f023 0202 bic.w r2, r3, #2 + 80042fc: 687b ldr r3, [r7, #4] + 80042fe: 631a str r2, [r3, #48] @ 0x30 + + /* Clear AlarmB flag */ + WRITE_REG(RTC->SCR, RTC_SCR_CALRBF); + 8004300: 4b09 ldr r3, [pc, #36] @ (8004328 ) + 8004302: 2202 movs r2, #2 + 8004304: 65da str r2, [r3, #92] @ 0x5c + } + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + 8004306: 4b08 ldr r3, [pc, #32] @ (8004328 ) + 8004308: 22ff movs r2, #255 @ 0xff + 800430a: 625a str r2, [r3, #36] @ 0x24 + + hrtc->State = HAL_RTC_STATE_READY; + 800430c: 687b ldr r3, [r7, #4] + 800430e: 2201 movs r2, #1 + 8004310: f883 202d strb.w r2, [r3, #45] @ 0x2d + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + 8004314: 687b ldr r3, [r7, #4] + 8004316: 2200 movs r2, #0 + 8004318: f883 202c strb.w r2, [r3, #44] @ 0x2c + + return HAL_OK; + 800431c: 2300 movs r3, #0 +} + 800431e: 4618 mov r0, r3 + 8004320: 370c adds r7, #12 + 8004322: 46bd mov sp, r7 + 8004324: bc80 pop {r7} + 8004326: 4770 bx lr + 8004328: 40002800 .word 0x40002800 + +0800432c : + * @brief Handle Alarm interrupt request. + * @param hrtc RTC handle + * @retval None + */ +void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc) +{ + 800432c: b580 push {r7, lr} + 800432e: b084 sub sp, #16 + 8004330: af00 add r7, sp, #0 + 8004332: 6078 str r0, [r7, #4] + uint32_t tmp = READ_REG(RTC->MISR) & READ_REG(hrtc->IsEnabled.RtcFeatures); + 8004334: 4b11 ldr r3, [pc, #68] @ (800437c ) + 8004336: 6d5a ldr r2, [r3, #84] @ 0x54 + 8004338: 687b ldr r3, [r7, #4] + 800433a: 6b1b ldr r3, [r3, #48] @ 0x30 + 800433c: 4013 ands r3, r2 + 800433e: 60fb str r3, [r7, #12] + + if ((tmp & RTC_MISR_ALRAMF) != 0U) + 8004340: 68fb ldr r3, [r7, #12] + 8004342: f003 0301 and.w r3, r3, #1 + 8004346: 2b00 cmp r3, #0 + 8004348: d005 beq.n 8004356 + { + /* Clear the AlarmA interrupt pending bit */ + WRITE_REG(RTC->SCR, RTC_SCR_CALRAF); + 800434a: 4b0c ldr r3, [pc, #48] @ (800437c ) + 800434c: 2201 movs r2, #1 + 800434e: 65da str r2, [r3, #92] @ 0x5c + +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + /* Call Compare Match registered Callback */ + hrtc->AlarmAEventCallback(hrtc); +#else + HAL_RTC_AlarmAEventCallback(hrtc); + 8004350: 6878 ldr r0, [r7, #4] + 8004352: f7fc fe06 bl 8000f62 +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ + } + + if ((tmp & RTC_MISR_ALRBMF) != 0U) + 8004356: 68fb ldr r3, [r7, #12] + 8004358: f003 0302 and.w r3, r3, #2 + 800435c: 2b00 cmp r3, #0 + 800435e: d005 beq.n 800436c + { + /* Clear the AlarmB interrupt pending bit */ + WRITE_REG(RTC->SCR, RTC_SCR_CALRBF); + 8004360: 4b06 ldr r3, [pc, #24] @ (800437c ) + 8004362: 2202 movs r2, #2 + 8004364: 65da str r2, [r3, #92] @ 0x5c + +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + /* Call Compare Match registered Callback */ + hrtc->AlarmBEventCallback(hrtc); +#else + HAL_RTCEx_AlarmBEventCallback(hrtc); + 8004366: 6878 ldr r0, [r7, #4] + 8004368: f000 f94a bl 8004600 +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ + } + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + 800436c: 687b ldr r3, [r7, #4] + 800436e: 2201 movs r2, #1 + 8004370: f883 202d strb.w r2, [r3, #45] @ 0x2d +} + 8004374: bf00 nop + 8004376: 3710 adds r7, #16 + 8004378: 46bd mov sp, r7 + 800437a: bd80 pop {r7, pc} + 800437c: 40002800 .word 0x40002800 + +08004380 : + * correctly copied into the RTC_TR and RTC_DR shadow registers. + * @param hrtc RTC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_WaitForSynchro(const RTC_HandleTypeDef *hrtc) +{ + 8004380: b580 push {r7, lr} + 8004382: b084 sub sp, #16 + 8004384: af00 add r7, sp, #0 + 8004386: 6078 str r0, [r7, #4] + uint32_t tickstart; + + UNUSED(hrtc); + /* Clear RSF flag */ + CLEAR_BIT(RTC->ICSR, RTC_ICSR_RSF); + 8004388: 4b0f ldr r3, [pc, #60] @ (80043c8 ) + 800438a: 68db ldr r3, [r3, #12] + 800438c: 4a0e ldr r2, [pc, #56] @ (80043c8 ) + 800438e: f023 0320 bic.w r3, r3, #32 + 8004392: 60d3 str r3, [r2, #12] + + tickstart = HAL_GetTick(); + 8004394: f7fc fbf4 bl 8000b80 + 8004398: 60f8 str r0, [r7, #12] + + /* Wait the registers to be synchronised */ + while (READ_BIT(RTC->ICSR, RTC_ICSR_RSF) == 0U) + 800439a: e009 b.n 80043b0 + { + if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) + 800439c: f7fc fbf0 bl 8000b80 + 80043a0: 4602 mov r2, r0 + 80043a2: 68fb ldr r3, [r7, #12] + 80043a4: 1ad3 subs r3, r2, r3 + 80043a6: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 + 80043aa: d901 bls.n 80043b0 + { + return HAL_TIMEOUT; + 80043ac: 2303 movs r3, #3 + 80043ae: e006 b.n 80043be + while (READ_BIT(RTC->ICSR, RTC_ICSR_RSF) == 0U) + 80043b0: 4b05 ldr r3, [pc, #20] @ (80043c8 ) + 80043b2: 68db ldr r3, [r3, #12] + 80043b4: f003 0320 and.w r3, r3, #32 + 80043b8: 2b00 cmp r3, #0 + 80043ba: d0ef beq.n 800439c + } + } + + return HAL_OK; + 80043bc: 2300 movs r3, #0 +} + 80043be: 4618 mov r0, r3 + 80043c0: 3710 adds r7, #16 + 80043c2: 46bd mov sp, r7 + 80043c4: bd80 pop {r7, pc} + 80043c6: bf00 nop + 80043c8: 40002800 .word 0x40002800 + +080043cc : + * __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function. + * @param hrtc RTC handle + * @retval HAL status + */ +HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef *hrtc) +{ + 80043cc: b580 push {r7, lr} + 80043ce: b084 sub sp, #16 + 80043d0: af00 add r7, sp, #0 + 80043d2: 6078 str r0, [r7, #4] + uint32_t tickstart; + HAL_StatusTypeDef status = HAL_OK; + 80043d4: 2300 movs r3, #0 + 80043d6: 73fb strb r3, [r7, #15] + + UNUSED(hrtc); + /* Check if the Initialization mode is set */ + if (READ_BIT(RTC->ICSR, RTC_ICSR_INITF) == 0U) + 80043d8: 4b15 ldr r3, [pc, #84] @ (8004430 ) + 80043da: 68db ldr r3, [r3, #12] + 80043dc: f003 0340 and.w r3, r3, #64 @ 0x40 + 80043e0: 2b00 cmp r3, #0 + 80043e2: d120 bne.n 8004426 + { + /* Set the Initialization mode */ + SET_BIT(RTC->ICSR, RTC_ICSR_INIT); + 80043e4: 4b12 ldr r3, [pc, #72] @ (8004430 ) + 80043e6: 68db ldr r3, [r3, #12] + 80043e8: 4a11 ldr r2, [pc, #68] @ (8004430 ) + 80043ea: f043 0380 orr.w r3, r3, #128 @ 0x80 + 80043ee: 60d3 str r3, [r2, #12] + + tickstart = HAL_GetTick(); + 80043f0: f7fc fbc6 bl 8000b80 + 80043f4: 60b8 str r0, [r7, #8] + /* Wait till RTC is in INIT state and if Time out is reached exit */ + while ((READ_BIT(RTC->ICSR, RTC_ICSR_INITF) == 0U) && (status != HAL_TIMEOUT)) + 80043f6: e00d b.n 8004414 + { + if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) + 80043f8: f7fc fbc2 bl 8000b80 + 80043fc: 4602 mov r2, r0 + 80043fe: 68bb ldr r3, [r7, #8] + 8004400: 1ad3 subs r3, r2, r3 + 8004402: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 + 8004406: d905 bls.n 8004414 + { + status = HAL_TIMEOUT; + 8004408: 2303 movs r3, #3 + 800440a: 73fb strb r3, [r7, #15] + hrtc->State = HAL_RTC_STATE_TIMEOUT; + 800440c: 687b ldr r3, [r7, #4] + 800440e: 2203 movs r2, #3 + 8004410: f883 202d strb.w r2, [r3, #45] @ 0x2d + while ((READ_BIT(RTC->ICSR, RTC_ICSR_INITF) == 0U) && (status != HAL_TIMEOUT)) + 8004414: 4b06 ldr r3, [pc, #24] @ (8004430 ) + 8004416: 68db ldr r3, [r3, #12] + 8004418: f003 0340 and.w r3, r3, #64 @ 0x40 + 800441c: 2b00 cmp r3, #0 + 800441e: d102 bne.n 8004426 + 8004420: 7bfb ldrb r3, [r7, #15] + 8004422: 2b03 cmp r3, #3 + 8004424: d1e8 bne.n 80043f8 + } + } + } + + return status; + 8004426: 7bfb ldrb r3, [r7, #15] +} + 8004428: 4618 mov r0, r3 + 800442a: 3710 adds r7, #16 + 800442c: 46bd mov sp, r7 + 800442e: bd80 pop {r7, pc} + 8004430: 40002800 .word 0x40002800 + +08004434 : + * @brief Exit the RTC Initialization mode. + * @param hrtc RTC handle + * @retval HAL status + */ +HAL_StatusTypeDef RTC_ExitInitMode(RTC_HandleTypeDef *hrtc) +{ + 8004434: b580 push {r7, lr} + 8004436: b084 sub sp, #16 + 8004438: af00 add r7, sp, #0 + 800443a: 6078 str r0, [r7, #4] + HAL_StatusTypeDef status = HAL_OK; + 800443c: 2300 movs r3, #0 + 800443e: 73fb strb r3, [r7, #15] + + /* Exit Initialization mode */ + CLEAR_BIT(RTC->ICSR, RTC_ICSR_INIT); + 8004440: 4b1a ldr r3, [pc, #104] @ (80044ac ) + 8004442: 68db ldr r3, [r3, #12] + 8004444: 4a19 ldr r2, [pc, #100] @ (80044ac ) + 8004446: f023 0380 bic.w r3, r3, #128 @ 0x80 + 800444a: 60d3 str r3, [r2, #12] + + /* If CR_BYPSHAD bit = 0, wait for synchro */ + if (READ_BIT(RTC->CR, RTC_CR_BYPSHAD) == 0U) + 800444c: 4b17 ldr r3, [pc, #92] @ (80044ac ) + 800444e: 699b ldr r3, [r3, #24] + 8004450: f003 0320 and.w r3, r3, #32 + 8004454: 2b00 cmp r3, #0 + 8004456: d10c bne.n 8004472 + { + if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) + 8004458: 6878 ldr r0, [r7, #4] + 800445a: f7ff ff91 bl 8004380 + 800445e: 4603 mov r3, r0 + 8004460: 2b00 cmp r3, #0 + 8004462: d01e beq.n 80044a2 + { + hrtc->State = HAL_RTC_STATE_TIMEOUT; + 8004464: 687b ldr r3, [r7, #4] + 8004466: 2203 movs r2, #3 + 8004468: f883 202d strb.w r2, [r3, #45] @ 0x2d + status = HAL_TIMEOUT; + 800446c: 2303 movs r3, #3 + 800446e: 73fb strb r3, [r7, #15] + 8004470: e017 b.n 80044a2 + } + } + else /* WA 2.9.6 Calendar initialization may fail in case of consecutive INIT mode entry. */ + { + /* Clear BYPSHAD bit */ + CLEAR_BIT(RTC->CR, RTC_CR_BYPSHAD); + 8004472: 4b0e ldr r3, [pc, #56] @ (80044ac ) + 8004474: 699b ldr r3, [r3, #24] + 8004476: 4a0d ldr r2, [pc, #52] @ (80044ac ) + 8004478: f023 0320 bic.w r3, r3, #32 + 800447c: 6193 str r3, [r2, #24] + if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) + 800447e: 6878 ldr r0, [r7, #4] + 8004480: f7ff ff7e bl 8004380 + 8004484: 4603 mov r3, r0 + 8004486: 2b00 cmp r3, #0 + 8004488: d005 beq.n 8004496 + { + hrtc->State = HAL_RTC_STATE_TIMEOUT; + 800448a: 687b ldr r3, [r7, #4] + 800448c: 2203 movs r2, #3 + 800448e: f883 202d strb.w r2, [r3, #45] @ 0x2d + status = HAL_TIMEOUT; + 8004492: 2303 movs r3, #3 + 8004494: 73fb strb r3, [r7, #15] + } + /* Restore BYPSHAD bit */ + SET_BIT(RTC->CR, RTC_CR_BYPSHAD); + 8004496: 4b05 ldr r3, [pc, #20] @ (80044ac ) + 8004498: 699b ldr r3, [r3, #24] + 800449a: 4a04 ldr r2, [pc, #16] @ (80044ac ) + 800449c: f043 0320 orr.w r3, r3, #32 + 80044a0: 6193 str r3, [r2, #24] + } + + return status; + 80044a2: 7bfb ldrb r3, [r7, #15] +} + 80044a4: 4618 mov r0, r3 + 80044a6: 3710 adds r7, #16 + 80044a8: 46bd mov sp, r7 + 80044aa: bd80 pop {r7, pc} + 80044ac: 40002800 .word 0x40002800 + +080044b0 : + * @brief Convert a 2 digit decimal to BCD format. + * @param Value Byte to be converted + * @retval Converted byte + */ +uint8_t RTC_ByteToBcd2(uint8_t Value) +{ + 80044b0: b480 push {r7} + 80044b2: b085 sub sp, #20 + 80044b4: af00 add r7, sp, #0 + 80044b6: 4603 mov r3, r0 + 80044b8: 71fb strb r3, [r7, #7] + uint32_t bcdhigh = 0U; + 80044ba: 2300 movs r3, #0 + 80044bc: 60fb str r3, [r7, #12] + uint8_t tmp_Value = Value; + 80044be: 79fb ldrb r3, [r7, #7] + 80044c0: 72fb strb r3, [r7, #11] + + while (tmp_Value >= 10U) + 80044c2: e005 b.n 80044d0 + { + bcdhigh++; + 80044c4: 68fb ldr r3, [r7, #12] + 80044c6: 3301 adds r3, #1 + 80044c8: 60fb str r3, [r7, #12] + tmp_Value -= 10U; + 80044ca: 7afb ldrb r3, [r7, #11] + 80044cc: 3b0a subs r3, #10 + 80044ce: 72fb strb r3, [r7, #11] + while (tmp_Value >= 10U) + 80044d0: 7afb ldrb r3, [r7, #11] + 80044d2: 2b09 cmp r3, #9 + 80044d4: d8f6 bhi.n 80044c4 + } + + return ((uint8_t)(bcdhigh << 4U) | tmp_Value); + 80044d6: 68fb ldr r3, [r7, #12] + 80044d8: b2db uxtb r3, r3 + 80044da: 011b lsls r3, r3, #4 + 80044dc: b2da uxtb r2, r3 + 80044de: 7afb ldrb r3, [r7, #11] + 80044e0: 4313 orrs r3, r2 + 80044e2: b2db uxtb r3, r3 +} + 80044e4: 4618 mov r0, r3 + 80044e6: 3714 adds r7, #20 + 80044e8: 46bd mov sp, r7 + 80044ea: bc80 pop {r7} + 80044ec: 4770 bx lr + ... + +080044f0 : + * directly from the Calendar counter. + * @param hrtc RTC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef *hrtc) +{ + 80044f0: b480 push {r7} + 80044f2: b083 sub sp, #12 + 80044f4: af00 add r7, sp, #0 + 80044f6: 6078 str r0, [r7, #4] + /* Process Locked */ + __HAL_LOCK(hrtc); + 80044f8: 687b ldr r3, [r7, #4] + 80044fa: f893 302c ldrb.w r3, [r3, #44] @ 0x2c + 80044fe: 2b01 cmp r3, #1 + 8004500: d101 bne.n 8004506 + 8004502: 2302 movs r3, #2 + 8004504: e01f b.n 8004546 + 8004506: 687b ldr r3, [r7, #4] + 8004508: 2201 movs r2, #1 + 800450a: f883 202c strb.w r2, [r3, #44] @ 0x2c + + hrtc->State = HAL_RTC_STATE_BUSY; + 800450e: 687b ldr r3, [r7, #4] + 8004510: 2202 movs r2, #2 + 8004512: f883 202d strb.w r2, [r3, #45] @ 0x2d + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + 8004516: 4b0e ldr r3, [pc, #56] @ (8004550 ) + 8004518: 22ca movs r2, #202 @ 0xca + 800451a: 625a str r2, [r3, #36] @ 0x24 + 800451c: 4b0c ldr r3, [pc, #48] @ (8004550 ) + 800451e: 2253 movs r2, #83 @ 0x53 + 8004520: 625a str r2, [r3, #36] @ 0x24 + + /* Set the BYPSHAD bit */ + SET_BIT(RTC->CR, RTC_CR_BYPSHAD); + 8004522: 4b0b ldr r3, [pc, #44] @ (8004550 ) + 8004524: 699b ldr r3, [r3, #24] + 8004526: 4a0a ldr r2, [pc, #40] @ (8004550 ) + 8004528: f043 0320 orr.w r3, r3, #32 + 800452c: 6193 str r3, [r2, #24] + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + 800452e: 4b08 ldr r3, [pc, #32] @ (8004550 ) + 8004530: 22ff movs r2, #255 @ 0xff + 8004532: 625a str r2, [r3, #36] @ 0x24 + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + 8004534: 687b ldr r3, [r7, #4] + 8004536: 2201 movs r2, #1 + 8004538: f883 202d strb.w r2, [r3, #45] @ 0x2d + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + 800453c: 687b ldr r3, [r7, #4] + 800453e: 2200 movs r2, #0 + 8004540: f883 202c strb.w r2, [r3, #44] @ 0x2c + + return HAL_OK; + 8004544: 2300 movs r3, #0 +} + 8004546: 4618 mov r0, r3 + 8004548: 370c adds r7, #12 + 800454a: 46bd mov sp, r7 + 800454c: bc80 pop {r7} + 800454e: 4770 bx lr + 8004550: 40002800 .word 0x40002800 + +08004554 : + * @brief Set SSR Underflow detection with Interrupt. + * @param hrtc RTC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_SetSSRU_IT(RTC_HandleTypeDef *hrtc) +{ + 8004554: b480 push {r7} + 8004556: b083 sub sp, #12 + 8004558: af00 add r7, sp, #0 + 800455a: 6078 str r0, [r7, #4] + /* Process Locked */ + __HAL_LOCK(hrtc); + 800455c: 687b ldr r3, [r7, #4] + 800455e: f893 302c ldrb.w r3, [r3, #44] @ 0x2c + 8004562: 2b01 cmp r3, #1 + 8004564: d101 bne.n 800456a + 8004566: 2302 movs r3, #2 + 8004568: e027 b.n 80045ba + 800456a: 687b ldr r3, [r7, #4] + 800456c: 2201 movs r2, #1 + 800456e: f883 202c strb.w r2, [r3, #44] @ 0x2c + + hrtc->State = HAL_RTC_STATE_BUSY; + 8004572: 687b ldr r3, [r7, #4] + 8004574: 2202 movs r2, #2 + 8004576: f883 202d strb.w r2, [r3, #45] @ 0x2d + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + 800457a: 4b12 ldr r3, [pc, #72] @ (80045c4 ) + 800457c: 22ca movs r2, #202 @ 0xca + 800457e: 625a str r2, [r3, #36] @ 0x24 + 8004580: 4b10 ldr r3, [pc, #64] @ (80045c4 ) + 8004582: 2253 movs r2, #83 @ 0x53 + 8004584: 625a str r2, [r3, #36] @ 0x24 + + /* Enable IT SSRU */ + __HAL_RTC_SSRU_ENABLE_IT(hrtc, RTC_IT_SSRU); + 8004586: 4b0f ldr r3, [pc, #60] @ (80045c4 ) + 8004588: 699b ldr r3, [r3, #24] + 800458a: 4a0e ldr r2, [pc, #56] @ (80045c4 ) + 800458c: f043 0380 orr.w r3, r3, #128 @ 0x80 + 8004590: 6193 str r3, [r2, #24] + + /* RTC SSRU Interrupt Configuration: EXTI configuration */ + __HAL_RTC_SSRU_EXTI_ENABLE_IT(); + 8004592: 4b0d ldr r3, [pc, #52] @ (80045c8 ) + 8004594: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 + 8004598: 4a0b ldr r2, [pc, #44] @ (80045c8 ) + 800459a: f443 2380 orr.w r3, r3, #262144 @ 0x40000 + 800459e: f8c2 3080 str.w r3, [r2, #128] @ 0x80 + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + 80045a2: 4b08 ldr r3, [pc, #32] @ (80045c4 ) + 80045a4: 22ff movs r2, #255 @ 0xff + 80045a6: 625a str r2, [r3, #36] @ 0x24 + + hrtc->State = HAL_RTC_STATE_READY; + 80045a8: 687b ldr r3, [r7, #4] + 80045aa: 2201 movs r2, #1 + 80045ac: f883 202d strb.w r2, [r3, #45] @ 0x2d + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + 80045b0: 687b ldr r3, [r7, #4] + 80045b2: 2200 movs r2, #0 + 80045b4: f883 202c strb.w r2, [r3, #44] @ 0x2c + + return HAL_OK; + 80045b8: 2300 movs r3, #0 +} + 80045ba: 4618 mov r0, r3 + 80045bc: 370c adds r7, #12 + 80045be: 46bd mov sp, r7 + 80045c0: bc80 pop {r7} + 80045c2: 4770 bx lr + 80045c4: 40002800 .word 0x40002800 + 80045c8: 58000800 .word 0x58000800 + +080045cc : + * @brief Handle SSR underflow interrupt request. + * @param hrtc RTC handle + * @retval None + */ +void HAL_RTCEx_SSRUIRQHandler(RTC_HandleTypeDef *hrtc) +{ + 80045cc: b580 push {r7, lr} + 80045ce: b082 sub sp, #8 + 80045d0: af00 add r7, sp, #0 + 80045d2: 6078 str r0, [r7, #4] + if ((RTC->MISR & RTC_MISR_SSRUMF) != 0u) + 80045d4: 4b09 ldr r3, [pc, #36] @ (80045fc ) + 80045d6: 6d5b ldr r3, [r3, #84] @ 0x54 + 80045d8: f003 0340 and.w r3, r3, #64 @ 0x40 + 80045dc: 2b00 cmp r3, #0 + 80045de: d005 beq.n 80045ec + { + /* Immediately clear flags */ + RTC->SCR = RTC_SCR_CSSRUF; + 80045e0: 4b06 ldr r3, [pc, #24] @ (80045fc ) + 80045e2: 2240 movs r2, #64 @ 0x40 + 80045e4: 65da str r2, [r3, #92] @ 0x5c + /* SSRU callback */ +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + /* Call SSRUEvent registered Callback */ + hrtc->SSRUEventCallback(hrtc); +#else + HAL_RTCEx_SSRUEventCallback(hrtc); + 80045e6: 6878 ldr r0, [r7, #4] + 80045e8: f7fc fcc5 bl 8000f76 +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ + } + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + 80045ec: 687b ldr r3, [r7, #4] + 80045ee: 2201 movs r2, #1 + 80045f0: f883 202d strb.w r2, [r3, #45] @ 0x2d +} + 80045f4: bf00 nop + 80045f6: 3708 adds r7, #8 + 80045f8: 46bd mov sp, r7 + 80045fa: bd80 pop {r7, pc} + 80045fc: 40002800 .word 0x40002800 + +08004600 : + * @brief Alarm B callback. + * @param hrtc RTC handle + * @retval None + */ +__weak void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc) +{ + 8004600: b480 push {r7} + 8004602: b083 sub sp, #12 + 8004604: af00 add r7, sp, #0 + 8004606: 6078 str r0, [r7, #4] + UNUSED(hrtc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_RTCEx_AlarmBEventCallback could be implemented in the user file + */ +} + 8004608: bf00 nop + 800460a: 370c adds r7, #12 + 800460c: 46bd mov sp, r7 + 800460e: bc80 pop {r7} + 8004610: 4770 bx lr + ... + +08004614 : + * This parameter can be RTC_BKP_DRx where x can be from 0 to RTC_BACKUP_NB + * @param Data Data to be written in the specified Backup data register. + * @retval None + */ +void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data) +{ + 8004614: b480 push {r7} + 8004616: b087 sub sp, #28 + 8004618: af00 add r7, sp, #0 + 800461a: 60f8 str r0, [r7, #12] + 800461c: 60b9 str r1, [r7, #8] + 800461e: 607a str r2, [r7, #4] + + UNUSED(hrtc); + /* Check the parameters */ + assert_param(IS_RTC_BKP(BackupRegister)); + + tmp = (uint32_t) &(TAMP->BKP0R); + 8004620: 4b07 ldr r3, [pc, #28] @ (8004640 ) + 8004622: 617b str r3, [r7, #20] + tmp += (BackupRegister * 4U); + 8004624: 68bb ldr r3, [r7, #8] + 8004626: 009b lsls r3, r3, #2 + 8004628: 697a ldr r2, [r7, #20] + 800462a: 4413 add r3, r2 + 800462c: 617b str r3, [r7, #20] + + /* Write the specified register */ + *(__IO uint32_t *)tmp = (uint32_t)Data; + 800462e: 697b ldr r3, [r7, #20] + 8004630: 687a ldr r2, [r7, #4] + 8004632: 601a str r2, [r3, #0] +} + 8004634: bf00 nop + 8004636: 371c adds r7, #28 + 8004638: 46bd mov sp, r7 + 800463a: bc80 pop {r7} + 800463c: 4770 bx lr + 800463e: bf00 nop + 8004640: 4000b100 .word 0x4000b100 + +08004644 : + * @param BackupRegister RTC Backup data Register number. + * This parameter can be RTC_BKP_DRx where x can be from 0 to RTC_BACKUP_NB + * @retval Read value + */ +uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister) +{ + 8004644: b480 push {r7} + 8004646: b085 sub sp, #20 + 8004648: af00 add r7, sp, #0 + 800464a: 6078 str r0, [r7, #4] + 800464c: 6039 str r1, [r7, #0] + + UNUSED(hrtc); + /* Check the parameters */ + assert_param(IS_RTC_BKP(BackupRegister)); + + tmp = (uint32_t) &(TAMP->BKP0R); + 800464e: 4b07 ldr r3, [pc, #28] @ (800466c ) + 8004650: 60fb str r3, [r7, #12] + tmp += (BackupRegister * 4U); + 8004652: 683b ldr r3, [r7, #0] + 8004654: 009b lsls r3, r3, #2 + 8004656: 68fa ldr r2, [r7, #12] + 8004658: 4413 add r3, r2 + 800465a: 60fb str r3, [r7, #12] + + /* Read the specified register */ + return (*(__IO uint32_t *)tmp); + 800465c: 68fb ldr r3, [r7, #12] + 800465e: 681b ldr r3, [r3, #0] +} + 8004660: 4618 mov r0, r3 + 8004662: 3714 adds r7, #20 + 8004664: 46bd mov sp, r7 + 8004666: bc80 pop {r7} + 8004668: 4770 bx lr + 800466a: bf00 nop + 800466c: 4000b100 .word 0x4000b100 + +08004670 : +{ + 8004670: b480 push {r7} + 8004672: b083 sub sp, #12 + 8004674: af00 add r7, sp, #0 + 8004676: 6078 str r0, [r7, #4] + MODIFY_REG(PWR->CR3, PWR_CR3_EWRFBUSY, RadioBusyTrigger); + 8004678: 4b06 ldr r3, [pc, #24] @ (8004694 ) + 800467a: 689b ldr r3, [r3, #8] + 800467c: f423 6200 bic.w r2, r3, #2048 @ 0x800 + 8004680: 4904 ldr r1, [pc, #16] @ (8004694 ) + 8004682: 687b ldr r3, [r7, #4] + 8004684: 4313 orrs r3, r2 + 8004686: 608b str r3, [r1, #8] +} + 8004688: bf00 nop + 800468a: 370c adds r7, #12 + 800468c: 46bd mov sp, r7 + 800468e: bc80 pop {r7} + 8004690: 4770 bx lr + 8004692: bf00 nop + 8004694: 58000400 .word 0x58000400 + +08004698 : +{ + 8004698: b480 push {r7} + 800469a: af00 add r7, sp, #0 + SET_BIT(PWR->SUBGHZSPICR, PWR_SUBGHZSPICR_NSS); + 800469c: 4b05 ldr r3, [pc, #20] @ (80046b4 ) + 800469e: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 80046a2: 4a04 ldr r2, [pc, #16] @ (80046b4 ) + 80046a4: f443 4300 orr.w r3, r3, #32768 @ 0x8000 + 80046a8: f8c2 3090 str.w r3, [r2, #144] @ 0x90 +} + 80046ac: bf00 nop + 80046ae: 46bd mov sp, r7 + 80046b0: bc80 pop {r7} + 80046b2: 4770 bx lr + 80046b4: 58000400 .word 0x58000400 + +080046b8 : +{ + 80046b8: b480 push {r7} + 80046ba: af00 add r7, sp, #0 + CLEAR_BIT(PWR->SUBGHZSPICR, PWR_SUBGHZSPICR_NSS); + 80046bc: 4b05 ldr r3, [pc, #20] @ (80046d4 ) + 80046be: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 80046c2: 4a04 ldr r2, [pc, #16] @ (80046d4 ) + 80046c4: f423 4300 bic.w r3, r3, #32768 @ 0x8000 + 80046c8: f8c2 3090 str.w r3, [r2, #144] @ 0x90 +} + 80046cc: bf00 nop + 80046ce: 46bd mov sp, r7 + 80046d0: bc80 pop {r7} + 80046d2: 4770 bx lr + 80046d4: 58000400 .word 0x58000400 + +080046d8 : +{ + 80046d8: b480 push {r7} + 80046da: af00 add r7, sp, #0 + WRITE_REG(PWR->SCR, PWR_SCR_CWRFBUSYF); + 80046dc: 4b03 ldr r3, [pc, #12] @ (80046ec ) + 80046de: f44f 6200 mov.w r2, #2048 @ 0x800 + 80046e2: 619a str r2, [r3, #24] +} + 80046e4: bf00 nop + 80046e6: 46bd mov sp, r7 + 80046e8: bc80 pop {r7} + 80046ea: 4770 bx lr + 80046ec: 58000400 .word 0x58000400 + +080046f0 : +{ + 80046f0: b480 push {r7} + 80046f2: af00 add r7, sp, #0 + return ((READ_BIT(PWR->SR2, PWR_SR2_RFBUSYS) == (PWR_SR2_RFBUSYS)) ? 1UL : 0UL); + 80046f4: 4b06 ldr r3, [pc, #24] @ (8004710 ) + 80046f6: 695b ldr r3, [r3, #20] + 80046f8: f003 0302 and.w r3, r3, #2 + 80046fc: 2b02 cmp r3, #2 + 80046fe: d101 bne.n 8004704 + 8004700: 2301 movs r3, #1 + 8004702: e000 b.n 8004706 + 8004704: 2300 movs r3, #0 +} + 8004706: 4618 mov r0, r3 + 8004708: 46bd mov sp, r7 + 800470a: bc80 pop {r7} + 800470c: 4770 bx lr + 800470e: bf00 nop + 8004710: 58000400 .word 0x58000400 + +08004714 : +{ + 8004714: b480 push {r7} + 8004716: af00 add r7, sp, #0 + return ((READ_BIT(PWR->SR2, PWR_SR2_RFBUSYMS) == (PWR_SR2_RFBUSYMS)) ? 1UL : 0UL); + 8004718: 4b06 ldr r3, [pc, #24] @ (8004734 ) + 800471a: 695b ldr r3, [r3, #20] + 800471c: f003 0304 and.w r3, r3, #4 + 8004720: 2b04 cmp r3, #4 + 8004722: d101 bne.n 8004728 + 8004724: 2301 movs r3, #1 + 8004726: e000 b.n 800472a + 8004728: 2300 movs r3, #0 +} + 800472a: 4618 mov r0, r3 + 800472c: 46bd mov sp, r7 + 800472e: bc80 pop {r7} + 8004730: 4770 bx lr + 8004732: bf00 nop + 8004734: 58000400 .word 0x58000400 + +08004738 : +{ + 8004738: b480 push {r7} + 800473a: af00 add r7, sp, #0 + CLEAR_BIT(RCC->CSR, RCC_CSR_RFRST); + 800473c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8004740: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 + 8004744: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 8004748: f423 4300 bic.w r3, r3, #32768 @ 0x8000 + 800474c: f8c2 3094 str.w r3, [r2, #148] @ 0x94 +} + 8004750: bf00 nop + 8004752: 46bd mov sp, r7 + 8004754: bc80 pop {r7} + 8004756: 4770 bx lr + +08004758 : +{ + 8004758: b480 push {r7} + 800475a: af00 add r7, sp, #0 + return ((READ_BIT(RCC->CSR, RCC_CSR_RFRSTF) == (RCC_CSR_RFRSTF)) ? 1UL : 0UL); + 800475c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8004760: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 + 8004764: f403 4380 and.w r3, r3, #16384 @ 0x4000 + 8004768: f5b3 4f80 cmp.w r3, #16384 @ 0x4000 + 800476c: d101 bne.n 8004772 + 800476e: 2301 movs r3, #1 + 8004770: e000 b.n 8004774 + 8004772: 2300 movs r3, #0 +} + 8004774: 4618 mov r0, r3 + 8004776: 46bd mov sp, r7 + 8004778: bc80 pop {r7} + 800477a: 4770 bx lr + +0800477c : +{ + 800477c: b480 push {r7} + 800477e: b083 sub sp, #12 + 8004780: af00 add r7, sp, #0 + 8004782: 6078 str r0, [r7, #4] + SET_BIT(EXTI->IMR2, ExtiLine); + 8004784: 4b06 ldr r3, [pc, #24] @ (80047a0 ) + 8004786: f8d3 2090 ldr.w r2, [r3, #144] @ 0x90 + 800478a: 4905 ldr r1, [pc, #20] @ (80047a0 ) + 800478c: 687b ldr r3, [r7, #4] + 800478e: 4313 orrs r3, r2 + 8004790: f8c1 3090 str.w r3, [r1, #144] @ 0x90 +} + 8004794: bf00 nop + 8004796: 370c adds r7, #12 + 8004798: 46bd mov sp, r7 + 800479a: bc80 pop {r7} + 800479c: 4770 bx lr + 800479e: bf00 nop + 80047a0: 58000800 .word 0x58000800 + +080047a4 : + * set the state to HAL_SUBGHZ_STATE_RESET_RF_READY with __HAL_SUBGHZ_RESET_HANDLE_STATE_RF_READY + * to avoid the reset of Radio peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SUBGHZ_Init(SUBGHZ_HandleTypeDef *hsubghz) +{ + 80047a4: b580 push {r7, lr} + 80047a6: b084 sub sp, #16 + 80047a8: af00 add r7, sp, #0 + 80047aa: 6078 str r0, [r7, #4] + HAL_StatusTypeDef status; + __IO uint32_t count; + HAL_SUBGHZ_StateTypeDef subghz_state; + + /* Check the hsubghz handle allocation */ + if (hsubghz == NULL) + 80047ac: 687b ldr r3, [r7, #4] + 80047ae: 2b00 cmp r3, #0 + 80047b0: d103 bne.n 80047ba + { + status = HAL_ERROR; + 80047b2: 2301 movs r3, #1 + 80047b4: 73fb strb r3, [r7, #15] + return status; + 80047b6: 7bfb ldrb r3, [r7, #15] + 80047b8: e052 b.n 8004860 + } + else + { + status = HAL_OK; + 80047ba: 2300 movs r3, #0 + 80047bc: 73fb strb r3, [r7, #15] + } + + assert_param(IS_SUBGHZSPI_BAUDRATE_PRESCALER(hsubghz->Init.BaudratePrescaler)); + + subghz_state = hsubghz->State; + 80047be: 687b ldr r3, [r7, #4] + 80047c0: 799b ldrb r3, [r3, #6] + 80047c2: 73bb strb r3, [r7, #14] + if ((subghz_state == HAL_SUBGHZ_STATE_RESET) || + 80047c4: 7bbb ldrb r3, [r7, #14] + 80047c6: 2b00 cmp r3, #0 + 80047c8: d002 beq.n 80047d0 + 80047ca: 7bbb ldrb r3, [r7, #14] + 80047cc: 2b03 cmp r3, #3 + 80047ce: d109 bne.n 80047e4 + (subghz_state == HAL_SUBGHZ_STATE_RESET_RF_READY)) + { + /* Allocate lock resource and initialize it */ + hsubghz->Lock = HAL_UNLOCKED; + 80047d0: 687b ldr r3, [r7, #4] + 80047d2: 2200 movs r2, #0 + 80047d4: 715a strb r2, [r3, #5] + + /* Init the low level hardware : GPIO, CLOCK, NVIC... */ + hsubghz->MspInitCallback(hsubghz); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC... */ + HAL_SUBGHZ_MspInit(hsubghz); + 80047d6: 6878 ldr r0, [r7, #4] + 80047d8: f7fc f932 bl 8000a40 +#if defined(CORE_CM0PLUS) + /* Enable EXTI 44 : Radio IRQ ITs for CPU2 */ + LL_C2_EXTI_EnableIT_32_63(LL_EXTI_LINE_44); +#else + /* Enable EXTI 44 : Radio IRQ ITs for CPU1 */ + LL_EXTI_EnableIT_32_63(LL_EXTI_LINE_44); + 80047dc: f44f 5080 mov.w r0, #4096 @ 0x1000 + 80047e0: f7ff ffcc bl 800477c +#endif /* CORE_CM0PLUS */ + } + + if (subghz_state == HAL_SUBGHZ_STATE_RESET) + 80047e4: 7bbb ldrb r3, [r7, #14] + 80047e6: 2b00 cmp r3, #0 + 80047e8: d126 bne.n 8004838 + { + /* Reinitialize Radio peripheral only if SUBGHZ is in full RESET state */ + hsubghz->State = HAL_SUBGHZ_STATE_BUSY; + 80047ea: 687b ldr r3, [r7, #4] + 80047ec: 2202 movs r2, #2 + 80047ee: 719a strb r2, [r3, #6] + + /* De-asserts the reset signal of the Radio peripheral */ + LL_RCC_RF_DisableReset(); + 80047f0: f7ff ffa2 bl 8004738 + + /* Verify that Radio in reset status flag is set */ + count = SUBGHZ_DEFAULT_TIMEOUT * SUBGHZ_DEFAULT_LOOP_TIME; + 80047f4: 4b1c ldr r3, [pc, #112] @ (8004868 ) + 80047f6: 681a ldr r2, [r3, #0] + 80047f8: 4613 mov r3, r2 + 80047fa: 00db lsls r3, r3, #3 + 80047fc: 1a9b subs r3, r3, r2 + 80047fe: 009b lsls r3, r3, #2 + 8004800: 0cdb lsrs r3, r3, #19 + 8004802: 2264 movs r2, #100 @ 0x64 + 8004804: fb02 f303 mul.w r3, r2, r3 + 8004808: 60bb str r3, [r7, #8] + + do + { + if (count == 0U) + 800480a: 68bb ldr r3, [r7, #8] + 800480c: 2b00 cmp r3, #0 + 800480e: d105 bne.n 800481c + { + status = HAL_ERROR; + 8004810: 2301 movs r3, #1 + 8004812: 73fb strb r3, [r7, #15] + hsubghz->ErrorCode = HAL_SUBGHZ_ERROR_TIMEOUT; + 8004814: 687b ldr r3, [r7, #4] + 8004816: 2201 movs r2, #1 + 8004818: 609a str r2, [r3, #8] + break; + 800481a: e007 b.n 800482c + } + count--; + 800481c: 68bb ldr r3, [r7, #8] + 800481e: 3b01 subs r3, #1 + 8004820: 60bb str r3, [r7, #8] + } while (LL_RCC_IsRFUnderReset() != 0UL); + 8004822: f7ff ff99 bl 8004758 + 8004826: 4603 mov r3, r0 + 8004828: 2b00 cmp r3, #0 + 800482a: d1ee bne.n 800480a + + /* Asserts the reset signal of the Radio peripheral */ + LL_PWR_UnselectSUBGHZSPI_NSS(); + 800482c: f7ff ff34 bl 8004698 +#if defined(CORE_CM0PLUS) + /* Enable wakeup signal of the Radio peripheral */ + LL_C2_PWR_SetRadioBusyTrigger(LL_PWR_RADIO_BUSY_TRIGGER_WU_IT); +#else + /* Enable wakeup signal of the Radio peripheral */ + LL_PWR_SetRadioBusyTrigger(LL_PWR_RADIO_BUSY_TRIGGER_WU_IT); + 8004830: f44f 6000 mov.w r0, #2048 @ 0x800 + 8004834: f7ff ff1c bl 8004670 +#endif /* CORE_CM0PLUS */ + } + + /* Clear Pending Flag */ + LL_PWR_ClearFlag_RFBUSY(); + 8004838: f7ff ff4e bl 80046d8 + + if (status == HAL_OK) + 800483c: 7bfb ldrb r3, [r7, #15] + 800483e: 2b00 cmp r3, #0 + 8004840: d10a bne.n 8004858 + { + /* Initialize SUBGHZSPI Peripheral */ + SUBGHZSPI_Init(hsubghz->Init.BaudratePrescaler); + 8004842: 687b ldr r3, [r7, #4] + 8004844: 681b ldr r3, [r3, #0] + 8004846: 4618 mov r0, r3 + 8004848: f000 fac2 bl 8004dd0 + + hsubghz->DeepSleep = SUBGHZ_DEEP_SLEEP_ENABLE; + 800484c: 687b ldr r3, [r7, #4] + 800484e: 2201 movs r2, #1 + 8004850: 711a strb r2, [r3, #4] + hsubghz->ErrorCode = HAL_SUBGHZ_ERROR_NONE; + 8004852: 687b ldr r3, [r7, #4] + 8004854: 2200 movs r2, #0 + 8004856: 609a str r2, [r3, #8] + } + + hsubghz->State = HAL_SUBGHZ_STATE_READY; + 8004858: 687b ldr r3, [r7, #4] + 800485a: 2201 movs r2, #1 + 800485c: 719a strb r2, [r3, #6] + + return status; + 800485e: 7bfb ldrb r3, [r7, #15] +} + 8004860: 4618 mov r0, r3 + 8004862: 3710 adds r7, #16 + 8004864: 46bd mov sp, r7 + 8004866: bd80 pop {r7, pc} + 8004868: 20000000 .word 0x20000000 + +0800486c : + */ +HAL_StatusTypeDef HAL_SUBGHZ_WriteRegisters(SUBGHZ_HandleTypeDef *hsubghz, + uint16_t Address, + uint8_t *pBuffer, + uint16_t Size) +{ + 800486c: b580 push {r7, lr} + 800486e: b086 sub sp, #24 + 8004870: af00 add r7, sp, #0 + 8004872: 60f8 str r0, [r7, #12] + 8004874: 607a str r2, [r7, #4] + 8004876: 461a mov r2, r3 + 8004878: 460b mov r3, r1 + 800487a: 817b strh r3, [r7, #10] + 800487c: 4613 mov r3, r2 + 800487e: 813b strh r3, [r7, #8] + HAL_StatusTypeDef status; + + if (hsubghz->State == HAL_SUBGHZ_STATE_READY) + 8004880: 68fb ldr r3, [r7, #12] + 8004882: 799b ldrb r3, [r3, #6] + 8004884: b2db uxtb r3, r3 + 8004886: 2b01 cmp r3, #1 + 8004888: d14a bne.n 8004920 + { + /* Process Locked */ + __HAL_LOCK(hsubghz); + 800488a: 68fb ldr r3, [r7, #12] + 800488c: 795b ldrb r3, [r3, #5] + 800488e: 2b01 cmp r3, #1 + 8004890: d101 bne.n 8004896 + 8004892: 2302 movs r3, #2 + 8004894: e045 b.n 8004922 + 8004896: 68fb ldr r3, [r7, #12] + 8004898: 2201 movs r2, #1 + 800489a: 715a strb r2, [r3, #5] + + hsubghz->State = HAL_SUBGHZ_STATE_BUSY; + 800489c: 68fb ldr r3, [r7, #12] + 800489e: 2202 movs r2, #2 + 80048a0: 719a strb r2, [r3, #6] + + (void)SUBGHZ_CheckDeviceReady(hsubghz); + 80048a2: 68f8 ldr r0, [r7, #12] + 80048a4: f000 fb62 bl 8004f6c + + /* NSS = 0 */ + LL_PWR_SelectSUBGHZSPI_NSS(); + 80048a8: f7ff ff06 bl 80046b8 + + (void)SUBGHZSPI_Transmit(hsubghz, SUBGHZ_RADIO_WRITE_REGISTER); + 80048ac: 210d movs r1, #13 + 80048ae: 68f8 ldr r0, [r7, #12] + 80048b0: f000 faae bl 8004e10 + (void)SUBGHZSPI_Transmit(hsubghz, (uint8_t)((Address & 0xFF00U) >> 8U)); + 80048b4: 897b ldrh r3, [r7, #10] + 80048b6: 0a1b lsrs r3, r3, #8 + 80048b8: b29b uxth r3, r3 + 80048ba: b2db uxtb r3, r3 + 80048bc: 4619 mov r1, r3 + 80048be: 68f8 ldr r0, [r7, #12] + 80048c0: f000 faa6 bl 8004e10 + (void)SUBGHZSPI_Transmit(hsubghz, (uint8_t)(Address & 0x00FFU)); + 80048c4: 897b ldrh r3, [r7, #10] + 80048c6: b2db uxtb r3, r3 + 80048c8: 4619 mov r1, r3 + 80048ca: 68f8 ldr r0, [r7, #12] + 80048cc: f000 faa0 bl 8004e10 + + for (uint16_t i = 0U; i < Size; i++) + 80048d0: 2300 movs r3, #0 + 80048d2: 82bb strh r3, [r7, #20] + 80048d4: e00a b.n 80048ec + { + (void)SUBGHZSPI_Transmit(hsubghz, pBuffer[i]); + 80048d6: 8abb ldrh r3, [r7, #20] + 80048d8: 687a ldr r2, [r7, #4] + 80048da: 4413 add r3, r2 + 80048dc: 781b ldrb r3, [r3, #0] + 80048de: 4619 mov r1, r3 + 80048e0: 68f8 ldr r0, [r7, #12] + 80048e2: f000 fa95 bl 8004e10 + for (uint16_t i = 0U; i < Size; i++) + 80048e6: 8abb ldrh r3, [r7, #20] + 80048e8: 3301 adds r3, #1 + 80048ea: 82bb strh r3, [r7, #20] + 80048ec: 8aba ldrh r2, [r7, #20] + 80048ee: 893b ldrh r3, [r7, #8] + 80048f0: 429a cmp r2, r3 + 80048f2: d3f0 bcc.n 80048d6 + } + + /* NSS = 1 */ + LL_PWR_UnselectSUBGHZSPI_NSS(); + 80048f4: f7ff fed0 bl 8004698 + + (void)SUBGHZ_WaitOnBusy(hsubghz); + 80048f8: 68f8 ldr r0, [r7, #12] + 80048fa: f000 fb57 bl 8004fac + + if (hsubghz->ErrorCode != HAL_SUBGHZ_ERROR_NONE) + 80048fe: 68fb ldr r3, [r7, #12] + 8004900: 689b ldr r3, [r3, #8] + 8004902: 2b00 cmp r3, #0 + 8004904: d002 beq.n 800490c + { + status = HAL_ERROR; + 8004906: 2301 movs r3, #1 + 8004908: 75fb strb r3, [r7, #23] + 800490a: e001 b.n 8004910 + } + else + { + status = HAL_OK; + 800490c: 2300 movs r3, #0 + 800490e: 75fb strb r3, [r7, #23] + } + + hsubghz->State = HAL_SUBGHZ_STATE_READY; + 8004910: 68fb ldr r3, [r7, #12] + 8004912: 2201 movs r2, #1 + 8004914: 719a strb r2, [r3, #6] + + /* Process Unlocked */ + __HAL_UNLOCK(hsubghz); + 8004916: 68fb ldr r3, [r7, #12] + 8004918: 2200 movs r2, #0 + 800491a: 715a strb r2, [r3, #5] + + return status; + 800491c: 7dfb ldrb r3, [r7, #23] + 800491e: e000 b.n 8004922 + } + else + { + return HAL_BUSY; + 8004920: 2302 movs r3, #2 + } +} + 8004922: 4618 mov r0, r3 + 8004924: 3718 adds r7, #24 + 8004926: 46bd mov sp, r7 + 8004928: bd80 pop {r7, pc} + +0800492a : + */ +HAL_StatusTypeDef HAL_SUBGHZ_ReadRegisters(SUBGHZ_HandleTypeDef *hsubghz, + uint16_t Address, + uint8_t *pBuffer, + uint16_t Size) +{ + 800492a: b580 push {r7, lr} + 800492c: b088 sub sp, #32 + 800492e: af00 add r7, sp, #0 + 8004930: 60f8 str r0, [r7, #12] + 8004932: 607a str r2, [r7, #4] + 8004934: 461a mov r2, r3 + 8004936: 460b mov r3, r1 + 8004938: 817b strh r3, [r7, #10] + 800493a: 4613 mov r3, r2 + 800493c: 813b strh r3, [r7, #8] + HAL_StatusTypeDef status; + uint8_t *pData = pBuffer; + 800493e: 687b ldr r3, [r7, #4] + 8004940: 61bb str r3, [r7, #24] + + if (hsubghz->State == HAL_SUBGHZ_STATE_READY) + 8004942: 68fb ldr r3, [r7, #12] + 8004944: 799b ldrb r3, [r3, #6] + 8004946: b2db uxtb r3, r3 + 8004948: 2b01 cmp r3, #1 + 800494a: d14a bne.n 80049e2 + { + /* Process Locked */ + __HAL_LOCK(hsubghz); + 800494c: 68fb ldr r3, [r7, #12] + 800494e: 795b ldrb r3, [r3, #5] + 8004950: 2b01 cmp r3, #1 + 8004952: d101 bne.n 8004958 + 8004954: 2302 movs r3, #2 + 8004956: e045 b.n 80049e4 + 8004958: 68fb ldr r3, [r7, #12] + 800495a: 2201 movs r2, #1 + 800495c: 715a strb r2, [r3, #5] + + (void)SUBGHZ_CheckDeviceReady(hsubghz); + 800495e: 68f8 ldr r0, [r7, #12] + 8004960: f000 fb04 bl 8004f6c + + /* NSS = 0 */ + LL_PWR_SelectSUBGHZSPI_NSS(); + 8004964: f7ff fea8 bl 80046b8 + + (void)SUBGHZSPI_Transmit(hsubghz, SUBGHZ_RADIO_READ_REGISTER); + 8004968: 211d movs r1, #29 + 800496a: 68f8 ldr r0, [r7, #12] + 800496c: f000 fa50 bl 8004e10 + (void)SUBGHZSPI_Transmit(hsubghz, (uint8_t)((Address & 0xFF00U) >> 8U)); + 8004970: 897b ldrh r3, [r7, #10] + 8004972: 0a1b lsrs r3, r3, #8 + 8004974: b29b uxth r3, r3 + 8004976: b2db uxtb r3, r3 + 8004978: 4619 mov r1, r3 + 800497a: 68f8 ldr r0, [r7, #12] + 800497c: f000 fa48 bl 8004e10 + (void)SUBGHZSPI_Transmit(hsubghz, (uint8_t)(Address & 0x00FFU)); + 8004980: 897b ldrh r3, [r7, #10] + 8004982: b2db uxtb r3, r3 + 8004984: 4619 mov r1, r3 + 8004986: 68f8 ldr r0, [r7, #12] + 8004988: f000 fa42 bl 8004e10 + (void)SUBGHZSPI_Transmit(hsubghz, 0U); + 800498c: 2100 movs r1, #0 + 800498e: 68f8 ldr r0, [r7, #12] + 8004990: f000 fa3e bl 8004e10 + + for (uint16_t i = 0U; i < Size; i++) + 8004994: 2300 movs r3, #0 + 8004996: 82fb strh r3, [r7, #22] + 8004998: e009 b.n 80049ae + { + (void)SUBGHZSPI_Receive(hsubghz, (pData)); + 800499a: 69b9 ldr r1, [r7, #24] + 800499c: 68f8 ldr r0, [r7, #12] + 800499e: f000 fa8d bl 8004ebc + pData++; + 80049a2: 69bb ldr r3, [r7, #24] + 80049a4: 3301 adds r3, #1 + 80049a6: 61bb str r3, [r7, #24] + for (uint16_t i = 0U; i < Size; i++) + 80049a8: 8afb ldrh r3, [r7, #22] + 80049aa: 3301 adds r3, #1 + 80049ac: 82fb strh r3, [r7, #22] + 80049ae: 8afa ldrh r2, [r7, #22] + 80049b0: 893b ldrh r3, [r7, #8] + 80049b2: 429a cmp r2, r3 + 80049b4: d3f1 bcc.n 800499a + } + + /* NSS = 1 */ + LL_PWR_UnselectSUBGHZSPI_NSS(); + 80049b6: f7ff fe6f bl 8004698 + + (void)SUBGHZ_WaitOnBusy(hsubghz); + 80049ba: 68f8 ldr r0, [r7, #12] + 80049bc: f000 faf6 bl 8004fac + + if (hsubghz->ErrorCode != HAL_SUBGHZ_ERROR_NONE) + 80049c0: 68fb ldr r3, [r7, #12] + 80049c2: 689b ldr r3, [r3, #8] + 80049c4: 2b00 cmp r3, #0 + 80049c6: d002 beq.n 80049ce + { + status = HAL_ERROR; + 80049c8: 2301 movs r3, #1 + 80049ca: 77fb strb r3, [r7, #31] + 80049cc: e001 b.n 80049d2 + } + else + { + status = HAL_OK; + 80049ce: 2300 movs r3, #0 + 80049d0: 77fb strb r3, [r7, #31] + } + + hsubghz->State = HAL_SUBGHZ_STATE_READY; + 80049d2: 68fb ldr r3, [r7, #12] + 80049d4: 2201 movs r2, #1 + 80049d6: 719a strb r2, [r3, #6] + + /* Process Unlocked */ + __HAL_UNLOCK(hsubghz); + 80049d8: 68fb ldr r3, [r7, #12] + 80049da: 2200 movs r2, #0 + 80049dc: 715a strb r2, [r3, #5] + + return status; + 80049de: 7ffb ldrb r3, [r7, #31] + 80049e0: e000 b.n 80049e4 + } + else + { + return HAL_BUSY; + 80049e2: 2302 movs r3, #2 + } +} + 80049e4: 4618 mov r0, r3 + 80049e6: 3720 adds r7, #32 + 80049e8: 46bd mov sp, r7 + 80049ea: bd80 pop {r7, pc} + +080049ec : + */ +HAL_StatusTypeDef HAL_SUBGHZ_ExecSetCmd(SUBGHZ_HandleTypeDef *hsubghz, + SUBGHZ_RadioSetCmd_t Command, + uint8_t *pBuffer, + uint16_t Size) +{ + 80049ec: b580 push {r7, lr} + 80049ee: b086 sub sp, #24 + 80049f0: af00 add r7, sp, #0 + 80049f2: 60f8 str r0, [r7, #12] + 80049f4: 607a str r2, [r7, #4] + 80049f6: 461a mov r2, r3 + 80049f8: 460b mov r3, r1 + 80049fa: 72fb strb r3, [r7, #11] + 80049fc: 4613 mov r3, r2 + 80049fe: 813b strh r3, [r7, #8] + HAL_StatusTypeDef status; + + /* LORA Modulation not available on STM32WLx4xx devices */ + assert_param(IS_SUBGHZ_MODULATION_SUPPORTED(Command, pBuffer[0U])); + + if (hsubghz->State == HAL_SUBGHZ_STATE_READY) + 8004a00: 68fb ldr r3, [r7, #12] + 8004a02: 799b ldrb r3, [r3, #6] + 8004a04: b2db uxtb r3, r3 + 8004a06: 2b01 cmp r3, #1 + 8004a08: d14a bne.n 8004aa0 + { + /* Process Locked */ + __HAL_LOCK(hsubghz); + 8004a0a: 68fb ldr r3, [r7, #12] + 8004a0c: 795b ldrb r3, [r3, #5] + 8004a0e: 2b01 cmp r3, #1 + 8004a10: d101 bne.n 8004a16 + 8004a12: 2302 movs r3, #2 + 8004a14: e045 b.n 8004aa2 + 8004a16: 68fb ldr r3, [r7, #12] + 8004a18: 2201 movs r2, #1 + 8004a1a: 715a strb r2, [r3, #5] + + /* Need to wakeup Radio if already in Sleep at startup */ + (void)SUBGHZ_CheckDeviceReady(hsubghz); + 8004a1c: 68f8 ldr r0, [r7, #12] + 8004a1e: f000 faa5 bl 8004f6c + + if ((Command == RADIO_SET_SLEEP) || (Command == RADIO_SET_RXDUTYCYCLE)) + 8004a22: 7afb ldrb r3, [r7, #11] + 8004a24: 2b84 cmp r3, #132 @ 0x84 + 8004a26: d002 beq.n 8004a2e + 8004a28: 7afb ldrb r3, [r7, #11] + 8004a2a: 2b94 cmp r3, #148 @ 0x94 + 8004a2c: d103 bne.n 8004a36 + { + hsubghz->DeepSleep = SUBGHZ_DEEP_SLEEP_ENABLE; + 8004a2e: 68fb ldr r3, [r7, #12] + 8004a30: 2201 movs r2, #1 + 8004a32: 711a strb r2, [r3, #4] + 8004a34: e002 b.n 8004a3c + } + else + { + hsubghz->DeepSleep = SUBGHZ_DEEP_SLEEP_DISABLE; + 8004a36: 68fb ldr r3, [r7, #12] + 8004a38: 2200 movs r2, #0 + 8004a3a: 711a strb r2, [r3, #4] + } + + /* NSS = 0 */ + LL_PWR_SelectSUBGHZSPI_NSS(); + 8004a3c: f7ff fe3c bl 80046b8 + + (void)SUBGHZSPI_Transmit(hsubghz, (uint8_t)Command); + 8004a40: 7afb ldrb r3, [r7, #11] + 8004a42: 4619 mov r1, r3 + 8004a44: 68f8 ldr r0, [r7, #12] + 8004a46: f000 f9e3 bl 8004e10 + + for (uint16_t i = 0U; i < Size; i++) + 8004a4a: 2300 movs r3, #0 + 8004a4c: 82bb strh r3, [r7, #20] + 8004a4e: e00a b.n 8004a66 + { + (void)SUBGHZSPI_Transmit(hsubghz, pBuffer[i]); + 8004a50: 8abb ldrh r3, [r7, #20] + 8004a52: 687a ldr r2, [r7, #4] + 8004a54: 4413 add r3, r2 + 8004a56: 781b ldrb r3, [r3, #0] + 8004a58: 4619 mov r1, r3 + 8004a5a: 68f8 ldr r0, [r7, #12] + 8004a5c: f000 f9d8 bl 8004e10 + for (uint16_t i = 0U; i < Size; i++) + 8004a60: 8abb ldrh r3, [r7, #20] + 8004a62: 3301 adds r3, #1 + 8004a64: 82bb strh r3, [r7, #20] + 8004a66: 8aba ldrh r2, [r7, #20] + 8004a68: 893b ldrh r3, [r7, #8] + 8004a6a: 429a cmp r2, r3 + 8004a6c: d3f0 bcc.n 8004a50 + } + + /* NSS = 1 */ + LL_PWR_UnselectSUBGHZSPI_NSS(); + 8004a6e: f7ff fe13 bl 8004698 + + if (Command != RADIO_SET_SLEEP) + 8004a72: 7afb ldrb r3, [r7, #11] + 8004a74: 2b84 cmp r3, #132 @ 0x84 + 8004a76: d002 beq.n 8004a7e + { + (void)SUBGHZ_WaitOnBusy(hsubghz); + 8004a78: 68f8 ldr r0, [r7, #12] + 8004a7a: f000 fa97 bl 8004fac + } + + if (hsubghz->ErrorCode != HAL_SUBGHZ_ERROR_NONE) + 8004a7e: 68fb ldr r3, [r7, #12] + 8004a80: 689b ldr r3, [r3, #8] + 8004a82: 2b00 cmp r3, #0 + 8004a84: d002 beq.n 8004a8c + { + status = HAL_ERROR; + 8004a86: 2301 movs r3, #1 + 8004a88: 75fb strb r3, [r7, #23] + 8004a8a: e001 b.n 8004a90 + } + else + { + status = HAL_OK; + 8004a8c: 2300 movs r3, #0 + 8004a8e: 75fb strb r3, [r7, #23] + } + + hsubghz->State = HAL_SUBGHZ_STATE_READY; + 8004a90: 68fb ldr r3, [r7, #12] + 8004a92: 2201 movs r2, #1 + 8004a94: 719a strb r2, [r3, #6] + + /* Process Unlocked */ + __HAL_UNLOCK(hsubghz); + 8004a96: 68fb ldr r3, [r7, #12] + 8004a98: 2200 movs r2, #0 + 8004a9a: 715a strb r2, [r3, #5] + + return status; + 8004a9c: 7dfb ldrb r3, [r7, #23] + 8004a9e: e000 b.n 8004aa2 + } + else + { + return HAL_BUSY; + 8004aa0: 2302 movs r3, #2 + } +} + 8004aa2: 4618 mov r0, r3 + 8004aa4: 3718 adds r7, #24 + 8004aa6: 46bd mov sp, r7 + 8004aa8: bd80 pop {r7, pc} + +08004aaa : + */ +HAL_StatusTypeDef HAL_SUBGHZ_ExecGetCmd(SUBGHZ_HandleTypeDef *hsubghz, + SUBGHZ_RadioGetCmd_t Command, + uint8_t *pBuffer, + uint16_t Size) +{ + 8004aaa: b580 push {r7, lr} + 8004aac: b088 sub sp, #32 + 8004aae: af00 add r7, sp, #0 + 8004ab0: 60f8 str r0, [r7, #12] + 8004ab2: 607a str r2, [r7, #4] + 8004ab4: 461a mov r2, r3 + 8004ab6: 460b mov r3, r1 + 8004ab8: 72fb strb r3, [r7, #11] + 8004aba: 4613 mov r3, r2 + 8004abc: 813b strh r3, [r7, #8] + HAL_StatusTypeDef status; + uint8_t *pData = pBuffer; + 8004abe: 687b ldr r3, [r7, #4] + 8004ac0: 61bb str r3, [r7, #24] + + if (hsubghz->State == HAL_SUBGHZ_STATE_READY) + 8004ac2: 68fb ldr r3, [r7, #12] + 8004ac4: 799b ldrb r3, [r3, #6] + 8004ac6: b2db uxtb r3, r3 + 8004ac8: 2b01 cmp r3, #1 + 8004aca: d13d bne.n 8004b48 + { + /* Process Locked */ + __HAL_LOCK(hsubghz); + 8004acc: 68fb ldr r3, [r7, #12] + 8004ace: 795b ldrb r3, [r3, #5] + 8004ad0: 2b01 cmp r3, #1 + 8004ad2: d101 bne.n 8004ad8 + 8004ad4: 2302 movs r3, #2 + 8004ad6: e038 b.n 8004b4a + 8004ad8: 68fb ldr r3, [r7, #12] + 8004ada: 2201 movs r2, #1 + 8004adc: 715a strb r2, [r3, #5] + + (void)SUBGHZ_CheckDeviceReady(hsubghz); + 8004ade: 68f8 ldr r0, [r7, #12] + 8004ae0: f000 fa44 bl 8004f6c + + /* NSS = 0 */ + LL_PWR_SelectSUBGHZSPI_NSS(); + 8004ae4: f7ff fde8 bl 80046b8 + + (void)SUBGHZSPI_Transmit(hsubghz, (uint8_t)Command); + 8004ae8: 7afb ldrb r3, [r7, #11] + 8004aea: 4619 mov r1, r3 + 8004aec: 68f8 ldr r0, [r7, #12] + 8004aee: f000 f98f bl 8004e10 + + /* Use to flush the Status (First byte) receive from SUBGHZ as not use */ + (void)SUBGHZSPI_Transmit(hsubghz, 0x00U); + 8004af2: 2100 movs r1, #0 + 8004af4: 68f8 ldr r0, [r7, #12] + 8004af6: f000 f98b bl 8004e10 + + for (uint16_t i = 0U; i < Size; i++) + 8004afa: 2300 movs r3, #0 + 8004afc: 82fb strh r3, [r7, #22] + 8004afe: e009 b.n 8004b14 + { + (void)SUBGHZSPI_Receive(hsubghz, (pData)); + 8004b00: 69b9 ldr r1, [r7, #24] + 8004b02: 68f8 ldr r0, [r7, #12] + 8004b04: f000 f9da bl 8004ebc + pData++; + 8004b08: 69bb ldr r3, [r7, #24] + 8004b0a: 3301 adds r3, #1 + 8004b0c: 61bb str r3, [r7, #24] + for (uint16_t i = 0U; i < Size; i++) + 8004b0e: 8afb ldrh r3, [r7, #22] + 8004b10: 3301 adds r3, #1 + 8004b12: 82fb strh r3, [r7, #22] + 8004b14: 8afa ldrh r2, [r7, #22] + 8004b16: 893b ldrh r3, [r7, #8] + 8004b18: 429a cmp r2, r3 + 8004b1a: d3f1 bcc.n 8004b00 + } + + /* NSS = 1 */ + LL_PWR_UnselectSUBGHZSPI_NSS(); + 8004b1c: f7ff fdbc bl 8004698 + + (void)SUBGHZ_WaitOnBusy(hsubghz); + 8004b20: 68f8 ldr r0, [r7, #12] + 8004b22: f000 fa43 bl 8004fac + + if (hsubghz->ErrorCode != HAL_SUBGHZ_ERROR_NONE) + 8004b26: 68fb ldr r3, [r7, #12] + 8004b28: 689b ldr r3, [r3, #8] + 8004b2a: 2b00 cmp r3, #0 + 8004b2c: d002 beq.n 8004b34 + { + status = HAL_ERROR; + 8004b2e: 2301 movs r3, #1 + 8004b30: 77fb strb r3, [r7, #31] + 8004b32: e001 b.n 8004b38 + } + else + { + status = HAL_OK; + 8004b34: 2300 movs r3, #0 + 8004b36: 77fb strb r3, [r7, #31] + } + + hsubghz->State = HAL_SUBGHZ_STATE_READY; + 8004b38: 68fb ldr r3, [r7, #12] + 8004b3a: 2201 movs r2, #1 + 8004b3c: 719a strb r2, [r3, #6] + + /* Process Unlocked */ + __HAL_UNLOCK(hsubghz); + 8004b3e: 68fb ldr r3, [r7, #12] + 8004b40: 2200 movs r2, #0 + 8004b42: 715a strb r2, [r3, #5] + + return status; + 8004b44: 7ffb ldrb r3, [r7, #31] + 8004b46: e000 b.n 8004b4a + } + else + { + return HAL_BUSY; + 8004b48: 2302 movs r3, #2 + } +} + 8004b4a: 4618 mov r0, r3 + 8004b4c: 3720 adds r7, #32 + 8004b4e: 46bd mov sp, r7 + 8004b50: bd80 pop {r7, pc} + +08004b52 : + */ +HAL_StatusTypeDef HAL_SUBGHZ_WriteBuffer(SUBGHZ_HandleTypeDef *hsubghz, + uint8_t Offset, + uint8_t *pBuffer, + uint16_t Size) +{ + 8004b52: b580 push {r7, lr} + 8004b54: b086 sub sp, #24 + 8004b56: af00 add r7, sp, #0 + 8004b58: 60f8 str r0, [r7, #12] + 8004b5a: 607a str r2, [r7, #4] + 8004b5c: 461a mov r2, r3 + 8004b5e: 460b mov r3, r1 + 8004b60: 72fb strb r3, [r7, #11] + 8004b62: 4613 mov r3, r2 + 8004b64: 813b strh r3, [r7, #8] + HAL_StatusTypeDef status; + + if (hsubghz->State == HAL_SUBGHZ_STATE_READY) + 8004b66: 68fb ldr r3, [r7, #12] + 8004b68: 799b ldrb r3, [r3, #6] + 8004b6a: b2db uxtb r3, r3 + 8004b6c: 2b01 cmp r3, #1 + 8004b6e: d13e bne.n 8004bee + { + /* Process Locked */ + __HAL_LOCK(hsubghz); + 8004b70: 68fb ldr r3, [r7, #12] + 8004b72: 795b ldrb r3, [r3, #5] + 8004b74: 2b01 cmp r3, #1 + 8004b76: d101 bne.n 8004b7c + 8004b78: 2302 movs r3, #2 + 8004b7a: e039 b.n 8004bf0 + 8004b7c: 68fb ldr r3, [r7, #12] + 8004b7e: 2201 movs r2, #1 + 8004b80: 715a strb r2, [r3, #5] + + (void)SUBGHZ_CheckDeviceReady(hsubghz); + 8004b82: 68f8 ldr r0, [r7, #12] + 8004b84: f000 f9f2 bl 8004f6c + + /* NSS = 0 */ + LL_PWR_SelectSUBGHZSPI_NSS(); + 8004b88: f7ff fd96 bl 80046b8 + + (void)SUBGHZSPI_Transmit(hsubghz, SUBGHZ_RADIO_WRITE_BUFFER); + 8004b8c: 210e movs r1, #14 + 8004b8e: 68f8 ldr r0, [r7, #12] + 8004b90: f000 f93e bl 8004e10 + (void)SUBGHZSPI_Transmit(hsubghz, Offset); + 8004b94: 7afb ldrb r3, [r7, #11] + 8004b96: 4619 mov r1, r3 + 8004b98: 68f8 ldr r0, [r7, #12] + 8004b9a: f000 f939 bl 8004e10 + + for (uint16_t i = 0U; i < Size; i++) + 8004b9e: 2300 movs r3, #0 + 8004ba0: 82bb strh r3, [r7, #20] + 8004ba2: e00a b.n 8004bba + { + (void)SUBGHZSPI_Transmit(hsubghz, pBuffer[i]); + 8004ba4: 8abb ldrh r3, [r7, #20] + 8004ba6: 687a ldr r2, [r7, #4] + 8004ba8: 4413 add r3, r2 + 8004baa: 781b ldrb r3, [r3, #0] + 8004bac: 4619 mov r1, r3 + 8004bae: 68f8 ldr r0, [r7, #12] + 8004bb0: f000 f92e bl 8004e10 + for (uint16_t i = 0U; i < Size; i++) + 8004bb4: 8abb ldrh r3, [r7, #20] + 8004bb6: 3301 adds r3, #1 + 8004bb8: 82bb strh r3, [r7, #20] + 8004bba: 8aba ldrh r2, [r7, #20] + 8004bbc: 893b ldrh r3, [r7, #8] + 8004bbe: 429a cmp r2, r3 + 8004bc0: d3f0 bcc.n 8004ba4 + } + /* NSS = 1 */ + LL_PWR_UnselectSUBGHZSPI_NSS(); + 8004bc2: f7ff fd69 bl 8004698 + + (void)SUBGHZ_WaitOnBusy(hsubghz); + 8004bc6: 68f8 ldr r0, [r7, #12] + 8004bc8: f000 f9f0 bl 8004fac + + if (hsubghz->ErrorCode != HAL_SUBGHZ_ERROR_NONE) + 8004bcc: 68fb ldr r3, [r7, #12] + 8004bce: 689b ldr r3, [r3, #8] + 8004bd0: 2b00 cmp r3, #0 + 8004bd2: d002 beq.n 8004bda + { + status = HAL_ERROR; + 8004bd4: 2301 movs r3, #1 + 8004bd6: 75fb strb r3, [r7, #23] + 8004bd8: e001 b.n 8004bde + } + else + { + status = HAL_OK; + 8004bda: 2300 movs r3, #0 + 8004bdc: 75fb strb r3, [r7, #23] + } + + hsubghz->State = HAL_SUBGHZ_STATE_READY; + 8004bde: 68fb ldr r3, [r7, #12] + 8004be0: 2201 movs r2, #1 + 8004be2: 719a strb r2, [r3, #6] + + /* Process Unlocked */ + __HAL_UNLOCK(hsubghz); + 8004be4: 68fb ldr r3, [r7, #12] + 8004be6: 2200 movs r2, #0 + 8004be8: 715a strb r2, [r3, #5] + + return status; + 8004bea: 7dfb ldrb r3, [r7, #23] + 8004bec: e000 b.n 8004bf0 + } + else + { + return HAL_BUSY; + 8004bee: 2302 movs r3, #2 + } +} + 8004bf0: 4618 mov r0, r3 + 8004bf2: 3718 adds r7, #24 + 8004bf4: 46bd mov sp, r7 + 8004bf6: bd80 pop {r7, pc} + +08004bf8 : + */ +HAL_StatusTypeDef HAL_SUBGHZ_ReadBuffer(SUBGHZ_HandleTypeDef *hsubghz, + uint8_t Offset, + uint8_t *pBuffer, + uint16_t Size) +{ + 8004bf8: b580 push {r7, lr} + 8004bfa: b088 sub sp, #32 + 8004bfc: af00 add r7, sp, #0 + 8004bfe: 60f8 str r0, [r7, #12] + 8004c00: 607a str r2, [r7, #4] + 8004c02: 461a mov r2, r3 + 8004c04: 460b mov r3, r1 + 8004c06: 72fb strb r3, [r7, #11] + 8004c08: 4613 mov r3, r2 + 8004c0a: 813b strh r3, [r7, #8] + HAL_StatusTypeDef status; + uint8_t *pData = pBuffer; + 8004c0c: 687b ldr r3, [r7, #4] + 8004c0e: 61bb str r3, [r7, #24] + + if (hsubghz->State == HAL_SUBGHZ_STATE_READY) + 8004c10: 68fb ldr r3, [r7, #12] + 8004c12: 799b ldrb r3, [r3, #6] + 8004c14: b2db uxtb r3, r3 + 8004c16: 2b01 cmp r3, #1 + 8004c18: d141 bne.n 8004c9e + { + /* Process Locked */ + __HAL_LOCK(hsubghz); + 8004c1a: 68fb ldr r3, [r7, #12] + 8004c1c: 795b ldrb r3, [r3, #5] + 8004c1e: 2b01 cmp r3, #1 + 8004c20: d101 bne.n 8004c26 + 8004c22: 2302 movs r3, #2 + 8004c24: e03c b.n 8004ca0 + 8004c26: 68fb ldr r3, [r7, #12] + 8004c28: 2201 movs r2, #1 + 8004c2a: 715a strb r2, [r3, #5] + + (void)SUBGHZ_CheckDeviceReady(hsubghz); + 8004c2c: 68f8 ldr r0, [r7, #12] + 8004c2e: f000 f99d bl 8004f6c + + /* NSS = 0 */ + LL_PWR_SelectSUBGHZSPI_NSS(); + 8004c32: f7ff fd41 bl 80046b8 + + (void)SUBGHZSPI_Transmit(hsubghz, SUBGHZ_RADIO_READ_BUFFER); + 8004c36: 211e movs r1, #30 + 8004c38: 68f8 ldr r0, [r7, #12] + 8004c3a: f000 f8e9 bl 8004e10 + (void)SUBGHZSPI_Transmit(hsubghz, Offset); + 8004c3e: 7afb ldrb r3, [r7, #11] + 8004c40: 4619 mov r1, r3 + 8004c42: 68f8 ldr r0, [r7, #12] + 8004c44: f000 f8e4 bl 8004e10 + (void)SUBGHZSPI_Transmit(hsubghz, 0x00U); + 8004c48: 2100 movs r1, #0 + 8004c4a: 68f8 ldr r0, [r7, #12] + 8004c4c: f000 f8e0 bl 8004e10 + + for (uint16_t i = 0U; i < Size; i++) + 8004c50: 2300 movs r3, #0 + 8004c52: 82fb strh r3, [r7, #22] + 8004c54: e009 b.n 8004c6a + { + (void)SUBGHZSPI_Receive(hsubghz, (pData)); + 8004c56: 69b9 ldr r1, [r7, #24] + 8004c58: 68f8 ldr r0, [r7, #12] + 8004c5a: f000 f92f bl 8004ebc + pData++; + 8004c5e: 69bb ldr r3, [r7, #24] + 8004c60: 3301 adds r3, #1 + 8004c62: 61bb str r3, [r7, #24] + for (uint16_t i = 0U; i < Size; i++) + 8004c64: 8afb ldrh r3, [r7, #22] + 8004c66: 3301 adds r3, #1 + 8004c68: 82fb strh r3, [r7, #22] + 8004c6a: 8afa ldrh r2, [r7, #22] + 8004c6c: 893b ldrh r3, [r7, #8] + 8004c6e: 429a cmp r2, r3 + 8004c70: d3f1 bcc.n 8004c56 + } + + /* NSS = 1 */ + LL_PWR_UnselectSUBGHZSPI_NSS(); + 8004c72: f7ff fd11 bl 8004698 + + (void)SUBGHZ_WaitOnBusy(hsubghz); + 8004c76: 68f8 ldr r0, [r7, #12] + 8004c78: f000 f998 bl 8004fac + + if (hsubghz->ErrorCode != HAL_SUBGHZ_ERROR_NONE) + 8004c7c: 68fb ldr r3, [r7, #12] + 8004c7e: 689b ldr r3, [r3, #8] + 8004c80: 2b00 cmp r3, #0 + 8004c82: d002 beq.n 8004c8a + { + status = HAL_ERROR; + 8004c84: 2301 movs r3, #1 + 8004c86: 77fb strb r3, [r7, #31] + 8004c88: e001 b.n 8004c8e + } + else + { + status = HAL_OK; + 8004c8a: 2300 movs r3, #0 + 8004c8c: 77fb strb r3, [r7, #31] + } + + hsubghz->State = HAL_SUBGHZ_STATE_READY; + 8004c8e: 68fb ldr r3, [r7, #12] + 8004c90: 2201 movs r2, #1 + 8004c92: 719a strb r2, [r3, #6] + + /* Process Unlocked */ + __HAL_UNLOCK(hsubghz); + 8004c94: 68fb ldr r3, [r7, #12] + 8004c96: 2200 movs r2, #0 + 8004c98: 715a strb r2, [r3, #5] + + return status; + 8004c9a: 7ffb ldrb r3, [r7, #31] + 8004c9c: e000 b.n 8004ca0 + } + else + { + return HAL_BUSY; + 8004c9e: 2302 movs r3, #2 + } +} + 8004ca0: 4618 mov r0, r3 + 8004ca2: 3720 adds r7, #32 + 8004ca4: 46bd mov sp, r7 + 8004ca6: bd80 pop {r7, pc} + +08004ca8 : + * @param hsubghz pointer to a SUBGHZ_HandleTypeDef structure that contains + * the configuration information for the specified SUBGHZ module. + * @retval None + */ +void HAL_SUBGHZ_IRQHandler(SUBGHZ_HandleTypeDef *hsubghz) +{ + 8004ca8: b580 push {r7, lr} + 8004caa: b084 sub sp, #16 + 8004cac: af00 add r7, sp, #0 + 8004cae: 6078 str r0, [r7, #4] + uint8_t tmpisr[2U] = {0U}; + 8004cb0: 2300 movs r3, #0 + 8004cb2: 81bb strh r3, [r7, #12] + uint16_t itsource; + + /* Retrieve Interrupts from SUBGHZ Irq Register */ + (void)HAL_SUBGHZ_ExecGetCmd(hsubghz, RADIO_GET_IRQSTATUS, tmpisr, 2U); + 8004cb4: f107 020c add.w r2, r7, #12 + 8004cb8: 2302 movs r3, #2 + 8004cba: 2112 movs r1, #18 + 8004cbc: 6878 ldr r0, [r7, #4] + 8004cbe: f7ff fef4 bl 8004aaa + itsource = tmpisr[0U]; + 8004cc2: 7b3b ldrb r3, [r7, #12] + 8004cc4: 81fb strh r3, [r7, #14] + itsource = (itsource << 8U) | tmpisr[1U]; + 8004cc6: f9b7 300e ldrsh.w r3, [r7, #14] + 8004cca: 021b lsls r3, r3, #8 + 8004ccc: b21a sxth r2, r3 + 8004cce: 7b7b ldrb r3, [r7, #13] + 8004cd0: b21b sxth r3, r3 + 8004cd2: 4313 orrs r3, r2 + 8004cd4: b21b sxth r3, r3 + 8004cd6: 81fb strh r3, [r7, #14] + + /* Clear SUBGHZ Irq Register */ + (void)HAL_SUBGHZ_ExecSetCmd(hsubghz, RADIO_CLR_IRQSTATUS, tmpisr, 2U); + 8004cd8: f107 020c add.w r2, r7, #12 + 8004cdc: 2302 movs r3, #2 + 8004cde: 2102 movs r1, #2 + 8004ce0: 6878 ldr r0, [r7, #4] + 8004ce2: f7ff fe83 bl 80049ec + + /* Packet transmission completed Interrupt */ + if (SUBGHZ_CHECK_IT_SOURCE(itsource, SUBGHZ_IT_TX_CPLT) != RESET) + 8004ce6: 89fb ldrh r3, [r7, #14] + 8004ce8: f003 0301 and.w r3, r3, #1 + 8004cec: 2b00 cmp r3, #0 + 8004cee: d002 beq.n 8004cf6 + { +#if (USE_HAL_SUBGHZ_REGISTER_CALLBACKS == 1U) + hsubghz->TxCpltCallback(hsubghz); +#else + HAL_SUBGHZ_TxCpltCallback(hsubghz); + 8004cf0: 6878 ldr r0, [r7, #4] + 8004cf2: f005 fc83 bl 800a5fc +#endif /* USE_HAL_SUBGHZ_REGISTER_CALLBACKS */ + } + + /* Packet received Interrupt */ + if ((SUBGHZ_CHECK_IT_SOURCE(itsource, SUBGHZ_IT_RX_CPLT) != RESET)) + 8004cf6: 89fb ldrh r3, [r7, #14] + 8004cf8: 085b lsrs r3, r3, #1 + 8004cfa: f003 0301 and.w r3, r3, #1 + 8004cfe: 2b00 cmp r3, #0 + 8004d00: d00e beq.n 8004d20 + { + if (SUBGHZ_CHECK_IT_SOURCE(itsource, SUBGHZ_IT_CRC_ERROR) != RESET) + 8004d02: 89fb ldrh r3, [r7, #14] + 8004d04: 099b lsrs r3, r3, #6 + 8004d06: f003 0301 and.w r3, r3, #1 + 8004d0a: 2b00 cmp r3, #0 + 8004d0c: d005 beq.n 8004d1a + { + hsubghz->ErrorCode |= HAL_SUBGHZ_ERROR_CRC_MISMATCH; + 8004d0e: 687b ldr r3, [r7, #4] + 8004d10: 689b ldr r3, [r3, #8] + 8004d12: f043 0204 orr.w r2, r3, #4 + 8004d16: 687b ldr r3, [r7, #4] + 8004d18: 609a str r2, [r3, #8] + } +#if (USE_HAL_SUBGHZ_REGISTER_CALLBACKS == 1U) + hsubghz->RxCpltCallback(hsubghz); +#else + HAL_SUBGHZ_RxCpltCallback(hsubghz); + 8004d1a: 6878 ldr r0, [r7, #4] + 8004d1c: f005 fc7c bl 800a618 +#endif /* USE_HAL_SUBGHZ_REGISTER_CALLBACKS */ + } + + /* Preamble Detected Interrupt */ + if (SUBGHZ_CHECK_IT_SOURCE(itsource, SUBGHZ_IT_PREAMBLE_DETECTED) != RESET) + 8004d20: 89fb ldrh r3, [r7, #14] + 8004d22: 089b lsrs r3, r3, #2 + 8004d24: f003 0301 and.w r3, r3, #1 + 8004d28: 2b00 cmp r3, #0 + 8004d2a: d002 beq.n 8004d32 + { +#if (USE_HAL_SUBGHZ_REGISTER_CALLBACKS == 1U) + hsubghz->PreambleDetectedCallback(hsubghz); +#else + HAL_SUBGHZ_PreambleDetectedCallback(hsubghz); + 8004d2c: 6878 ldr r0, [r7, #4] + 8004d2e: f005 fccb bl 800a6c8 +#endif /* USE_HAL_SUBGHZ_REGISTER_CALLBACKS */ + } + + /* Valid sync word detected Interrupt */ + if (SUBGHZ_CHECK_IT_SOURCE(itsource, SUBGHZ_IT_SYNCWORD_VALID) != RESET) + 8004d32: 89fb ldrh r3, [r7, #14] + 8004d34: 08db lsrs r3, r3, #3 + 8004d36: f003 0301 and.w r3, r3, #1 + 8004d3a: 2b00 cmp r3, #0 + 8004d3c: d002 beq.n 8004d44 + { +#if (USE_HAL_SUBGHZ_REGISTER_CALLBACKS == 1U) + hsubghz->SyncWordValidCallback(hsubghz); +#else + HAL_SUBGHZ_SyncWordValidCallback(hsubghz); + 8004d3e: 6878 ldr r0, [r7, #4] + 8004d40: f005 fcd0 bl 800a6e4 +#endif /* USE_HAL_SUBGHZ_REGISTER_CALLBACKS */ + } + + /* Valid LoRa header received Interrupt */ + if (SUBGHZ_CHECK_IT_SOURCE(itsource, SUBGHZ_IT_HEADER_VALID) != RESET) + 8004d44: 89fb ldrh r3, [r7, #14] + 8004d46: 091b lsrs r3, r3, #4 + 8004d48: f003 0301 and.w r3, r3, #1 + 8004d4c: 2b00 cmp r3, #0 + 8004d4e: d002 beq.n 8004d56 + { +#if (USE_HAL_SUBGHZ_REGISTER_CALLBACKS == 1U) + hsubghz->HeaderValidCallback(hsubghz); +#else + HAL_SUBGHZ_HeaderValidCallback(hsubghz); + 8004d50: 6878 ldr r0, [r7, #4] + 8004d52: f005 fcd5 bl 800a700 +#endif /* USE_HAL_SUBGHZ_REGISTER_CALLBACKS */ + } + + /* LoRa header CRC error Interrupt */ + if (SUBGHZ_CHECK_IT_SOURCE(itsource, SUBGHZ_IT_HEADER_ERROR) != RESET) + 8004d56: 89fb ldrh r3, [r7, #14] + 8004d58: 095b lsrs r3, r3, #5 + 8004d5a: f003 0301 and.w r3, r3, #1 + 8004d5e: 2b00 cmp r3, #0 + 8004d60: d002 beq.n 8004d68 + { +#if (USE_HAL_SUBGHZ_REGISTER_CALLBACKS == 1U) + hsubghz->HeaderErrorCallback(hsubghz); +#else + HAL_SUBGHZ_HeaderErrorCallback(hsubghz); + 8004d62: 6878 ldr r0, [r7, #4] + 8004d64: f005 fca2 bl 800a6ac +#endif /* USE_HAL_SUBGHZ_REGISTER_CALLBACKS */ + } + + /* Wrong CRC received Interrupt */ + if (SUBGHZ_CHECK_IT_SOURCE(itsource, SUBGHZ_IT_CRC_ERROR) != RESET) + 8004d68: 89fb ldrh r3, [r7, #14] + 8004d6a: 099b lsrs r3, r3, #6 + 8004d6c: f003 0301 and.w r3, r3, #1 + 8004d70: 2b00 cmp r3, #0 + 8004d72: d002 beq.n 8004d7a + { +#if (USE_HAL_SUBGHZ_REGISTER_CALLBACKS == 1U) + hsubghz->CRCErrorCallback(hsubghz); +#else + HAL_SUBGHZ_CRCErrorCallback(hsubghz); + 8004d74: 6878 ldr r0, [r7, #4] + 8004d76: f005 fc5d bl 800a634 +#endif /* USE_HAL_SUBGHZ_REGISTER_CALLBACKS */ + } + + /* Channel activity detection finished Interrupt */ + if (SUBGHZ_CHECK_IT_SOURCE(itsource, SUBGHZ_IT_CAD_DONE) != RESET) + 8004d7a: 89fb ldrh r3, [r7, #14] + 8004d7c: 09db lsrs r3, r3, #7 + 8004d7e: f003 0301 and.w r3, r3, #1 + 8004d82: 2b00 cmp r3, #0 + 8004d84: d00e beq.n 8004da4 + { + hsubghz->CADStatusCallback(hsubghz, HAL_SUBGHZ_CAD_CLEAR); + } +#else + /* Channel activity Detected Interrupt */ + if (SUBGHZ_CHECK_IT_SOURCE(itsource, SUBGHZ_IT_CAD_ACTIVITY_DETECTED) != RESET) + 8004d86: 89fb ldrh r3, [r7, #14] + 8004d88: 0a1b lsrs r3, r3, #8 + 8004d8a: f003 0301 and.w r3, r3, #1 + 8004d8e: 2b00 cmp r3, #0 + 8004d90: d004 beq.n 8004d9c + { + HAL_SUBGHZ_CADStatusCallback(hsubghz, HAL_SUBGHZ_CAD_DETECTED); + 8004d92: 2101 movs r1, #1 + 8004d94: 6878 ldr r0, [r7, #4] + 8004d96: f005 fc5b bl 800a650 + 8004d9a: e003 b.n 8004da4 + } + else + { + HAL_SUBGHZ_CADStatusCallback(hsubghz, HAL_SUBGHZ_CAD_CLEAR); + 8004d9c: 2100 movs r1, #0 + 8004d9e: 6878 ldr r0, [r7, #4] + 8004da0: f005 fc56 bl 800a650 + } +#endif /* USE_HAL_SUBGHZ_REGISTER_CALLBACKS */ + } + + /* Rx or Tx Timeout Interrupt */ + if (SUBGHZ_CHECK_IT_SOURCE(itsource, SUBGHZ_IT_RX_TX_TIMEOUT) != RESET) + 8004da4: 89fb ldrh r3, [r7, #14] + 8004da6: 0a5b lsrs r3, r3, #9 + 8004da8: f003 0301 and.w r3, r3, #1 + 8004dac: 2b00 cmp r3, #0 + 8004dae: d002 beq.n 8004db6 + { +#if (USE_HAL_SUBGHZ_REGISTER_CALLBACKS == 1U) + hsubghz->RxTxTimeoutCallback(hsubghz); +#else + HAL_SUBGHZ_RxTxTimeoutCallback(hsubghz); + 8004db0: 6878 ldr r0, [r7, #4] + 8004db2: f005 fc6b bl 800a68c +#endif /* USE_HAL_SUBGHZ_REGISTER_CALLBACKS */ + } + + /* LR_FHSS Hop interrupt */ + if (SUBGHZ_CHECK_IT_SOURCE(itsource, SUBGHZ_IT_LR_FHSS_HOP) != RESET) + 8004db6: 89fb ldrh r3, [r7, #14] + 8004db8: 0b9b lsrs r3, r3, #14 + 8004dba: f003 0301 and.w r3, r3, #1 + 8004dbe: 2b00 cmp r3, #0 + 8004dc0: d002 beq.n 8004dc8 + { +#if (USE_HAL_SUBGHZ_REGISTER_CALLBACKS == 1U) + hsubghz->LrFhssHopCallback(hsubghz); +#else + HAL_SUBGHZ_LrFhssHopCallback(hsubghz); + 8004dc2: 6878 ldr r0, [r7, #4] + 8004dc4: f005 fcaa bl 800a71c +#endif /* USE_HAL_SUBGHZ_REGISTER_CALLBACKS */ + } +} + 8004dc8: bf00 nop + 8004dca: 3710 adds r7, #16 + 8004dcc: 46bd mov sp, r7 + 8004dce: bd80 pop {r7, pc} + +08004dd0 : + * @brief Initializes the SUBGHZSPI peripheral + * @param BaudratePrescaler SPI Baudrate prescaler + * @retval None + */ +void SUBGHZSPI_Init(uint32_t BaudratePrescaler) +{ + 8004dd0: b480 push {r7} + 8004dd2: b083 sub sp, #12 + 8004dd4: af00 add r7, sp, #0 + 8004dd6: 6078 str r0, [r7, #4] + /* Check the parameters */ + assert_param(IS_SUBGHZ_ALL_INSTANCE(SUBGHZSPI)); + + /* Disable SUBGHZSPI Peripheral */ + CLEAR_BIT(SUBGHZSPI->CR1, SPI_CR1_SPE); + 8004dd8: 4b0c ldr r3, [pc, #48] @ (8004e0c ) + 8004dda: 681b ldr r3, [r3, #0] + 8004ddc: 4a0b ldr r2, [pc, #44] @ (8004e0c ) + 8004dde: f023 0340 bic.w r3, r3, #64 @ 0x40 + 8004de2: 6013 str r3, [r2, #0] + * NSS management: Internal (Done with External bit inside PWR * + * Communication speed: BaudratePrescaler * + * First bit: MSB * + * CRC calculation: Disable * + *--------------------------------------------------------------------------*/ + WRITE_REG(SUBGHZSPI->CR1, (SPI_CR1_MSTR | SPI_CR1_SSI | BaudratePrescaler | SPI_CR1_SSM)); + 8004de4: 4a09 ldr r2, [pc, #36] @ (8004e0c ) + 8004de6: 687b ldr r3, [r7, #4] + 8004de8: f443 7341 orr.w r3, r3, #772 @ 0x304 + 8004dec: 6013 str r3, [r2, #0] + * Data Size: 8bits * + * TI Mode: Disable * + * NSS Pulse: Disable * + * Rx FIFO Threshold: 8bits * + *--------------------------------------------------------------------------*/ + WRITE_REG(SUBGHZSPI->CR2, (SPI_CR2_FRXTH | SPI_CR2_DS_0 | SPI_CR2_DS_1 | SPI_CR2_DS_2)); + 8004dee: 4b07 ldr r3, [pc, #28] @ (8004e0c ) + 8004df0: f44f 52b8 mov.w r2, #5888 @ 0x1700 + 8004df4: 605a str r2, [r3, #4] + + /* Enable SUBGHZSPI Peripheral */ + SET_BIT(SUBGHZSPI->CR1, SPI_CR1_SPE); + 8004df6: 4b05 ldr r3, [pc, #20] @ (8004e0c ) + 8004df8: 681b ldr r3, [r3, #0] + 8004dfa: 4a04 ldr r2, [pc, #16] @ (8004e0c ) + 8004dfc: f043 0340 orr.w r3, r3, #64 @ 0x40 + 8004e00: 6013 str r3, [r2, #0] +} + 8004e02: bf00 nop + 8004e04: 370c adds r7, #12 + 8004e06: 46bd mov sp, r7 + 8004e08: bc80 pop {r7} + 8004e0a: 4770 bx lr + 8004e0c: 58010000 .word 0x58010000 + +08004e10 : + * @param Data data to transmit + * @retval HAL status + */ +HAL_StatusTypeDef SUBGHZSPI_Transmit(SUBGHZ_HandleTypeDef *hsubghz, + uint8_t Data) +{ + 8004e10: b480 push {r7} + 8004e12: b087 sub sp, #28 + 8004e14: af00 add r7, sp, #0 + 8004e16: 6078 str r0, [r7, #4] + 8004e18: 460b mov r3, r1 + 8004e1a: 70fb strb r3, [r7, #3] + HAL_StatusTypeDef status = HAL_OK; + 8004e1c: 2300 movs r3, #0 + 8004e1e: 75fb strb r3, [r7, #23] + __IO uint32_t count; + + /* Handle Tx transmission from SUBGHZSPI peripheral to Radio ****************/ + /* Initialize Timeout */ + count = SUBGHZ_DEFAULT_TIMEOUT * SUBGHZ_DEFAULT_LOOP_TIME; + 8004e20: 4b23 ldr r3, [pc, #140] @ (8004eb0 ) + 8004e22: 681a ldr r2, [r3, #0] + 8004e24: 4613 mov r3, r2 + 8004e26: 00db lsls r3, r3, #3 + 8004e28: 1a9b subs r3, r3, r2 + 8004e2a: 009b lsls r3, r3, #2 + 8004e2c: 0cdb lsrs r3, r3, #19 + 8004e2e: 2264 movs r2, #100 @ 0x64 + 8004e30: fb02 f303 mul.w r3, r2, r3 + 8004e34: 60fb str r3, [r7, #12] + + /* Wait until TXE flag is set */ + do + { + if (count == 0U) + 8004e36: 68fb ldr r3, [r7, #12] + 8004e38: 2b00 cmp r3, #0 + 8004e3a: d105 bne.n 8004e48 + { + status = HAL_ERROR; + 8004e3c: 2301 movs r3, #1 + 8004e3e: 75fb strb r3, [r7, #23] + hsubghz->ErrorCode = HAL_SUBGHZ_ERROR_TIMEOUT; + 8004e40: 687b ldr r3, [r7, #4] + 8004e42: 2201 movs r2, #1 + 8004e44: 609a str r2, [r3, #8] + break; + 8004e46: e008 b.n 8004e5a + } + count--; + 8004e48: 68fb ldr r3, [r7, #12] + 8004e4a: 3b01 subs r3, #1 + 8004e4c: 60fb str r3, [r7, #12] + } while (READ_BIT(SUBGHZSPI->SR, SPI_SR_TXE) != (SPI_SR_TXE)); + 8004e4e: 4b19 ldr r3, [pc, #100] @ (8004eb4 ) + 8004e50: 689b ldr r3, [r3, #8] + 8004e52: f003 0302 and.w r3, r3, #2 + 8004e56: 2b02 cmp r3, #2 + 8004e58: d1ed bne.n 8004e36 + + /* Transmit Data*/ +#if defined (__GNUC__) + __IO uint8_t *spidr = ((__IO uint8_t *)&SUBGHZSPI->DR); + 8004e5a: 4b17 ldr r3, [pc, #92] @ (8004eb8 ) + 8004e5c: 613b str r3, [r7, #16] + *spidr = Data; + 8004e5e: 693b ldr r3, [r7, #16] + 8004e60: 78fa ldrb r2, [r7, #3] + 8004e62: 701a strb r2, [r3, #0] + *((__IO uint8_t *)&SUBGHZSPI->DR) = Data; +#endif /* __GNUC__ */ + + /* Handle Rx transmission from SUBGHZSPI peripheral to Radio ****************/ + /* Initialize Timeout */ + count = SUBGHZ_DEFAULT_TIMEOUT * SUBGHZ_DEFAULT_LOOP_TIME; + 8004e64: 4b12 ldr r3, [pc, #72] @ (8004eb0 ) + 8004e66: 681a ldr r2, [r3, #0] + 8004e68: 4613 mov r3, r2 + 8004e6a: 00db lsls r3, r3, #3 + 8004e6c: 1a9b subs r3, r3, r2 + 8004e6e: 009b lsls r3, r3, #2 + 8004e70: 0cdb lsrs r3, r3, #19 + 8004e72: 2264 movs r2, #100 @ 0x64 + 8004e74: fb02 f303 mul.w r3, r2, r3 + 8004e78: 60fb str r3, [r7, #12] + + /* Wait until RXNE flag is set */ + do + { + if (count == 0U) + 8004e7a: 68fb ldr r3, [r7, #12] + 8004e7c: 2b00 cmp r3, #0 + 8004e7e: d105 bne.n 8004e8c + { + status = HAL_ERROR; + 8004e80: 2301 movs r3, #1 + 8004e82: 75fb strb r3, [r7, #23] + hsubghz->ErrorCode = HAL_SUBGHZ_ERROR_TIMEOUT; + 8004e84: 687b ldr r3, [r7, #4] + 8004e86: 2201 movs r2, #1 + 8004e88: 609a str r2, [r3, #8] + break; + 8004e8a: e008 b.n 8004e9e + } + count--; + 8004e8c: 68fb ldr r3, [r7, #12] + 8004e8e: 3b01 subs r3, #1 + 8004e90: 60fb str r3, [r7, #12] + } while (READ_BIT(SUBGHZSPI->SR, SPI_SR_RXNE) != (SPI_SR_RXNE)); + 8004e92: 4b08 ldr r3, [pc, #32] @ (8004eb4 ) + 8004e94: 689b ldr r3, [r3, #8] + 8004e96: f003 0301 and.w r3, r3, #1 + 8004e9a: 2b01 cmp r3, #1 + 8004e9c: d1ed bne.n 8004e7a + + /* Flush Rx data */ + READ_REG(SUBGHZSPI->DR); + 8004e9e: 4b05 ldr r3, [pc, #20] @ (8004eb4 ) + 8004ea0: 68db ldr r3, [r3, #12] + + return status; + 8004ea2: 7dfb ldrb r3, [r7, #23] +} + 8004ea4: 4618 mov r0, r3 + 8004ea6: 371c adds r7, #28 + 8004ea8: 46bd mov sp, r7 + 8004eaa: bc80 pop {r7} + 8004eac: 4770 bx lr + 8004eae: bf00 nop + 8004eb0: 20000000 .word 0x20000000 + 8004eb4: 58010000 .word 0x58010000 + 8004eb8: 5801000c .word 0x5801000c + +08004ebc : + * @param pData pointer on data to receive + * @retval HAL status + */ +HAL_StatusTypeDef SUBGHZSPI_Receive(SUBGHZ_HandleTypeDef *hsubghz, + uint8_t *pData) +{ + 8004ebc: b480 push {r7} + 8004ebe: b087 sub sp, #28 + 8004ec0: af00 add r7, sp, #0 + 8004ec2: 6078 str r0, [r7, #4] + 8004ec4: 6039 str r1, [r7, #0] + HAL_StatusTypeDef status = HAL_OK; + 8004ec6: 2300 movs r3, #0 + 8004ec8: 75fb strb r3, [r7, #23] + __IO uint32_t count; + + /* Handle Tx transmission from SUBGHZSPI peripheral to Radio ****************/ + /* Initialize Timeout */ + count = SUBGHZ_DEFAULT_TIMEOUT * SUBGHZ_DEFAULT_LOOP_TIME; + 8004eca: 4b25 ldr r3, [pc, #148] @ (8004f60 ) + 8004ecc: 681a ldr r2, [r3, #0] + 8004ece: 4613 mov r3, r2 + 8004ed0: 00db lsls r3, r3, #3 + 8004ed2: 1a9b subs r3, r3, r2 + 8004ed4: 009b lsls r3, r3, #2 + 8004ed6: 0cdb lsrs r3, r3, #19 + 8004ed8: 2264 movs r2, #100 @ 0x64 + 8004eda: fb02 f303 mul.w r3, r2, r3 + 8004ede: 60fb str r3, [r7, #12] + + /* Wait until TXE flag is set */ + do + { + if (count == 0U) + 8004ee0: 68fb ldr r3, [r7, #12] + 8004ee2: 2b00 cmp r3, #0 + 8004ee4: d105 bne.n 8004ef2 + { + status = HAL_ERROR; + 8004ee6: 2301 movs r3, #1 + 8004ee8: 75fb strb r3, [r7, #23] + hsubghz->ErrorCode = HAL_SUBGHZ_ERROR_TIMEOUT; + 8004eea: 687b ldr r3, [r7, #4] + 8004eec: 2201 movs r2, #1 + 8004eee: 609a str r2, [r3, #8] + break; + 8004ef0: e008 b.n 8004f04 + } + count--; + 8004ef2: 68fb ldr r3, [r7, #12] + 8004ef4: 3b01 subs r3, #1 + 8004ef6: 60fb str r3, [r7, #12] + } while (READ_BIT(SUBGHZSPI->SR, SPI_SR_TXE) != (SPI_SR_TXE)); + 8004ef8: 4b1a ldr r3, [pc, #104] @ (8004f64 ) + 8004efa: 689b ldr r3, [r3, #8] + 8004efc: f003 0302 and.w r3, r3, #2 + 8004f00: 2b02 cmp r3, #2 + 8004f02: d1ed bne.n 8004ee0 + + /* Transmit Data*/ +#if defined (__GNUC__) + __IO uint8_t *spidr = ((__IO uint8_t *)&SUBGHZSPI->DR); + 8004f04: 4b18 ldr r3, [pc, #96] @ (8004f68 ) + 8004f06: 613b str r3, [r7, #16] + *spidr = SUBGHZ_DUMMY_DATA; + 8004f08: 693b ldr r3, [r7, #16] + 8004f0a: 22ff movs r2, #255 @ 0xff + 8004f0c: 701a strb r2, [r3, #0] + *((__IO uint8_t *)&SUBGHZSPI->DR) = SUBGHZ_DUMMY_DATA; +#endif /* __GNUC__ */ + + /* Handle Rx transmission from SUBGHZSPI peripheral to Radio ****************/ + /* Initialize Timeout */ + count = SUBGHZ_DEFAULT_TIMEOUT * SUBGHZ_DEFAULT_LOOP_TIME; + 8004f0e: 4b14 ldr r3, [pc, #80] @ (8004f60 ) + 8004f10: 681a ldr r2, [r3, #0] + 8004f12: 4613 mov r3, r2 + 8004f14: 00db lsls r3, r3, #3 + 8004f16: 1a9b subs r3, r3, r2 + 8004f18: 009b lsls r3, r3, #2 + 8004f1a: 0cdb lsrs r3, r3, #19 + 8004f1c: 2264 movs r2, #100 @ 0x64 + 8004f1e: fb02 f303 mul.w r3, r2, r3 + 8004f22: 60fb str r3, [r7, #12] + + /* Wait until RXNE flag is set */ + do + { + if (count == 0U) + 8004f24: 68fb ldr r3, [r7, #12] + 8004f26: 2b00 cmp r3, #0 + 8004f28: d105 bne.n 8004f36 + { + status = HAL_ERROR; + 8004f2a: 2301 movs r3, #1 + 8004f2c: 75fb strb r3, [r7, #23] + hsubghz->ErrorCode = HAL_SUBGHZ_ERROR_TIMEOUT; + 8004f2e: 687b ldr r3, [r7, #4] + 8004f30: 2201 movs r2, #1 + 8004f32: 609a str r2, [r3, #8] + break; + 8004f34: e008 b.n 8004f48 + } + count--; + 8004f36: 68fb ldr r3, [r7, #12] + 8004f38: 3b01 subs r3, #1 + 8004f3a: 60fb str r3, [r7, #12] + } while (READ_BIT(SUBGHZSPI->SR, SPI_SR_RXNE) != (SPI_SR_RXNE)); + 8004f3c: 4b09 ldr r3, [pc, #36] @ (8004f64 ) + 8004f3e: 689b ldr r3, [r3, #8] + 8004f40: f003 0301 and.w r3, r3, #1 + 8004f44: 2b01 cmp r3, #1 + 8004f46: d1ed bne.n 8004f24 + + /* Retrieve pData */ + *pData = (uint8_t)(READ_REG(SUBGHZSPI->DR)); + 8004f48: 4b06 ldr r3, [pc, #24] @ (8004f64 ) + 8004f4a: 68db ldr r3, [r3, #12] + 8004f4c: b2da uxtb r2, r3 + 8004f4e: 683b ldr r3, [r7, #0] + 8004f50: 701a strb r2, [r3, #0] + + return status; + 8004f52: 7dfb ldrb r3, [r7, #23] +} + 8004f54: 4618 mov r0, r3 + 8004f56: 371c adds r7, #28 + 8004f58: 46bd mov sp, r7 + 8004f5a: bc80 pop {r7} + 8004f5c: 4770 bx lr + 8004f5e: bf00 nop + 8004f60: 20000000 .word 0x20000000 + 8004f64: 58010000 .word 0x58010000 + 8004f68: 5801000c .word 0x5801000c + +08004f6c : + * @param hsubghz pointer to a SUBGHZ_HandleTypeDef structure that contains + * the handle information for SUBGHZ module. + * @retval HAL status + */ +HAL_StatusTypeDef SUBGHZ_CheckDeviceReady(SUBGHZ_HandleTypeDef *hsubghz) +{ + 8004f6c: b580 push {r7, lr} + 8004f6e: b084 sub sp, #16 + 8004f70: af00 add r7, sp, #0 + 8004f72: 6078 str r0, [r7, #4] + __IO uint32_t count; + + /* Wakeup radio in case of sleep mode: Select-Unselect radio */ + if (hsubghz->DeepSleep == SUBGHZ_DEEP_SLEEP_ENABLE) + 8004f74: 687b ldr r3, [r7, #4] + 8004f76: 791b ldrb r3, [r3, #4] + 8004f78: 2b01 cmp r3, #1 + 8004f7a: d10d bne.n 8004f98 + { + /* Initialize NSS switch Delay */ + count = SUBGHZ_NSS_LOOP_TIME; + 8004f7c: 4b0a ldr r3, [pc, #40] @ (8004fa8 ) + 8004f7e: 681b ldr r3, [r3, #0] + 8004f80: 0c1b lsrs r3, r3, #16 + 8004f82: 60fb str r3, [r7, #12] + + /* NSS = 0; */ + LL_PWR_SelectSUBGHZSPI_NSS(); + 8004f84: f7ff fb98 bl 80046b8 + + /* Wait Radio wakeup */ + do + { + count--; + 8004f88: 68fb ldr r3, [r7, #12] + 8004f8a: 3b01 subs r3, #1 + 8004f8c: 60fb str r3, [r7, #12] + } while (count != 0UL); + 8004f8e: 68fb ldr r3, [r7, #12] + 8004f90: 2b00 cmp r3, #0 + 8004f92: d1f9 bne.n 8004f88 + + /* NSS = 1 */ + LL_PWR_UnselectSUBGHZSPI_NSS(); + 8004f94: f7ff fb80 bl 8004698 + } + return (SUBGHZ_WaitOnBusy(hsubghz)); + 8004f98: 6878 ldr r0, [r7, #4] + 8004f9a: f000 f807 bl 8004fac + 8004f9e: 4603 mov r3, r0 +} + 8004fa0: 4618 mov r0, r3 + 8004fa2: 3710 adds r7, #16 + 8004fa4: 46bd mov sp, r7 + 8004fa6: bd80 pop {r7, pc} + 8004fa8: 20000000 .word 0x20000000 + +08004fac : + * @param hsubghz pointer to a SUBGHZ_HandleTypeDef structure that contains + * the handle information for SUBGHZ module. + * @retval HAL status + */ +HAL_StatusTypeDef SUBGHZ_WaitOnBusy(SUBGHZ_HandleTypeDef *hsubghz) +{ + 8004fac: b580 push {r7, lr} + 8004fae: b086 sub sp, #24 + 8004fb0: af00 add r7, sp, #0 + 8004fb2: 6078 str r0, [r7, #4] + HAL_StatusTypeDef status; + __IO uint32_t count; + uint32_t mask; + + status = HAL_OK; + 8004fb4: 2300 movs r3, #0 + 8004fb6: 75fb strb r3, [r7, #23] + count = SUBGHZ_DEFAULT_TIMEOUT * SUBGHZ_RFBUSY_LOOP_TIME; + 8004fb8: 4b12 ldr r3, [pc, #72] @ (8005004 ) + 8004fba: 681a ldr r2, [r3, #0] + 8004fbc: 4613 mov r3, r2 + 8004fbe: 005b lsls r3, r3, #1 + 8004fc0: 4413 add r3, r2 + 8004fc2: 00db lsls r3, r3, #3 + 8004fc4: 0d1b lsrs r3, r3, #20 + 8004fc6: 2264 movs r2, #100 @ 0x64 + 8004fc8: fb02 f303 mul.w r3, r2, r3 + 8004fcc: 60fb str r3, [r7, #12] + + /* Wait until Busy signal is set */ + do + { + mask = LL_PWR_IsActiveFlag_RFBUSYMS(); + 8004fce: f7ff fba1 bl 8004714 + 8004fd2: 6138 str r0, [r7, #16] + + if (count == 0U) + 8004fd4: 68fb ldr r3, [r7, #12] + 8004fd6: 2b00 cmp r3, #0 + 8004fd8: d105 bne.n 8004fe6 + { + status = HAL_ERROR; + 8004fda: 2301 movs r3, #1 + 8004fdc: 75fb strb r3, [r7, #23] + hsubghz->ErrorCode = HAL_SUBGHZ_ERROR_RF_BUSY; + 8004fde: 687b ldr r3, [r7, #4] + 8004fe0: 2202 movs r2, #2 + 8004fe2: 609a str r2, [r3, #8] + break; + 8004fe4: e009 b.n 8004ffa + } + count--; + 8004fe6: 68fb ldr r3, [r7, #12] + 8004fe8: 3b01 subs r3, #1 + 8004fea: 60fb str r3, [r7, #12] + } while ((LL_PWR_IsActiveFlag_RFBUSYS()& mask) == 1UL); + 8004fec: f7ff fb80 bl 80046f0 + 8004ff0: 4602 mov r2, r0 + 8004ff2: 693b ldr r3, [r7, #16] + 8004ff4: 4013 ands r3, r2 + 8004ff6: 2b01 cmp r3, #1 + 8004ff8: d0e9 beq.n 8004fce + + return status; + 8004ffa: 7dfb ldrb r3, [r7, #23] +} + 8004ffc: 4618 mov r0, r3 + 8004ffe: 3718 adds r7, #24 + 8005000: 46bd mov sp, r7 + 8005002: bd80 pop {r7, pc} + 8005004: 20000000 .word 0x20000000 + +08005008 : +{ + 8005008: b480 push {r7} + 800500a: b083 sub sp, #12 + 800500c: af00 add r7, sp, #0 + 800500e: 6078 str r0, [r7, #4] + return (uint32_t)(READ_BIT(RCC->CCIPR, USARTx) | (USARTx << 16)); + 8005010: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8005014: f8d3 2088 ldr.w r2, [r3, #136] @ 0x88 + 8005018: 687b ldr r3, [r7, #4] + 800501a: 401a ands r2, r3 + 800501c: 687b ldr r3, [r7, #4] + 800501e: 041b lsls r3, r3, #16 + 8005020: 4313 orrs r3, r2 +} + 8005022: 4618 mov r0, r3 + 8005024: 370c adds r7, #12 + 8005026: 46bd mov sp, r7 + 8005028: bc80 pop {r7} + 800502a: 4770 bx lr + +0800502c : +{ + 800502c: b480 push {r7} + 800502e: b083 sub sp, #12 + 8005030: af00 add r7, sp, #0 + 8005032: 6078 str r0, [r7, #4] + return (uint32_t)(READ_BIT(RCC->CCIPR, LPUARTx)); + 8005034: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8005038: f8d3 2088 ldr.w r2, [r3, #136] @ 0x88 + 800503c: 687b ldr r3, [r7, #4] + 800503e: 4013 ands r3, r2 +} + 8005040: 4618 mov r0, r3 + 8005042: 370c adds r7, #12 + 8005044: 46bd mov sp, r7 + 8005046: bc80 pop {r7} + 8005048: 4770 bx lr + +0800504a : + * parameters in the UART_InitTypeDef and initialize the associated handle. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) +{ + 800504a: b580 push {r7, lr} + 800504c: b082 sub sp, #8 + 800504e: af00 add r7, sp, #0 + 8005050: 6078 str r0, [r7, #4] + /* Check the UART handle allocation */ + if (huart == NULL) + 8005052: 687b ldr r3, [r7, #4] + 8005054: 2b00 cmp r3, #0 + 8005056: d101 bne.n 800505c + { + return HAL_ERROR; + 8005058: 2301 movs r3, #1 + 800505a: e042 b.n 80050e2 + { + /* Check the parameters */ + assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance))); + } + + if (huart->gState == HAL_UART_STATE_RESET) + 800505c: 687b ldr r3, [r7, #4] + 800505e: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 + 8005062: 2b00 cmp r3, #0 + 8005064: d106 bne.n 8005074 + { + /* Allocate lock resource and initialize it */ + huart->Lock = HAL_UNLOCKED; + 8005066: 687b ldr r3, [r7, #4] + 8005068: 2200 movs r2, #0 + 800506a: f883 2084 strb.w r2, [r3, #132] @ 0x84 + + /* Init the low level hardware */ + huart->MspInitCallback(huart); +#else + /* Init the low level hardware : GPIO, CLOCK */ + HAL_UART_MspInit(huart); + 800506e: 6878 ldr r0, [r7, #4] + 8005070: f7fc f8e6 bl 8001240 +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + + huart->gState = HAL_UART_STATE_BUSY; + 8005074: 687b ldr r3, [r7, #4] + 8005076: 2224 movs r2, #36 @ 0x24 + 8005078: f8c3 2088 str.w r2, [r3, #136] @ 0x88 + + __HAL_UART_DISABLE(huart); + 800507c: 687b ldr r3, [r7, #4] + 800507e: 681b ldr r3, [r3, #0] + 8005080: 681a ldr r2, [r3, #0] + 8005082: 687b ldr r3, [r7, #4] + 8005084: 681b ldr r3, [r3, #0] + 8005086: f022 0201 bic.w r2, r2, #1 + 800508a: 601a str r2, [r3, #0] + + /* Perform advanced settings configuration */ + /* For some items, configuration requires to be done prior TE and RE bits are set */ + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) + 800508c: 687b ldr r3, [r7, #4] + 800508e: 6a9b ldr r3, [r3, #40] @ 0x28 + 8005090: 2b00 cmp r3, #0 + 8005092: d002 beq.n 800509a + { + UART_AdvFeatureConfig(huart); + 8005094: 6878 ldr r0, [r7, #4] + 8005096: f000 fec9 bl 8005e2c + } + + /* Set the UART Communication parameters */ + if (UART_SetConfig(huart) == HAL_ERROR) + 800509a: 6878 ldr r0, [r7, #4] + 800509c: f000 fc52 bl 8005944 + 80050a0: 4603 mov r3, r0 + 80050a2: 2b01 cmp r3, #1 + 80050a4: d101 bne.n 80050aa + { + return HAL_ERROR; + 80050a6: 2301 movs r3, #1 + 80050a8: e01b b.n 80050e2 + } + + /* In asynchronous mode, the following bits must be kept cleared: + - LINEN and CLKEN bits in the USART_CR2 register, + - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ + CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + 80050aa: 687b ldr r3, [r7, #4] + 80050ac: 681b ldr r3, [r3, #0] + 80050ae: 685a ldr r2, [r3, #4] + 80050b0: 687b ldr r3, [r7, #4] + 80050b2: 681b ldr r3, [r3, #0] + 80050b4: f422 4290 bic.w r2, r2, #18432 @ 0x4800 + 80050b8: 605a str r2, [r3, #4] + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); + 80050ba: 687b ldr r3, [r7, #4] + 80050bc: 681b ldr r3, [r3, #0] + 80050be: 689a ldr r2, [r3, #8] + 80050c0: 687b ldr r3, [r7, #4] + 80050c2: 681b ldr r3, [r3, #0] + 80050c4: f022 022a bic.w r2, r2, #42 @ 0x2a + 80050c8: 609a str r2, [r3, #8] + + __HAL_UART_ENABLE(huart); + 80050ca: 687b ldr r3, [r7, #4] + 80050cc: 681b ldr r3, [r3, #0] + 80050ce: 681a ldr r2, [r3, #0] + 80050d0: 687b ldr r3, [r7, #4] + 80050d2: 681b ldr r3, [r3, #0] + 80050d4: f042 0201 orr.w r2, r2, #1 + 80050d8: 601a str r2, [r3, #0] + + /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ + return (UART_CheckIdleState(huart)); + 80050da: 6878 ldr r0, [r7, #4] + 80050dc: f000 ff47 bl 8005f6e + 80050e0: 4603 mov r3, r0 +} + 80050e2: 4618 mov r0, r3 + 80050e4: 3708 adds r7, #8 + 80050e6: 46bd mov sp, r7 + 80050e8: bd80 pop {r7, pc} + ... + +080050ec : + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + 80050ec: b580 push {r7, lr} + 80050ee: b08a sub sp, #40 @ 0x28 + 80050f0: af00 add r7, sp, #0 + 80050f2: 60f8 str r0, [r7, #12] + 80050f4: 60b9 str r1, [r7, #8] + 80050f6: 4613 mov r3, r2 + 80050f8: 80fb strh r3, [r7, #6] + /* Check that a Rx process is not already ongoing */ + if (huart->RxState == HAL_UART_STATE_READY) + 80050fa: 68fb ldr r3, [r7, #12] + 80050fc: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c + 8005100: 2b20 cmp r3, #32 + 8005102: d137 bne.n 8005174 + { + if ((pData == NULL) || (Size == 0U)) + 8005104: 68bb ldr r3, [r7, #8] + 8005106: 2b00 cmp r3, #0 + 8005108: d002 beq.n 8005110 + 800510a: 88fb ldrh r3, [r7, #6] + 800510c: 2b00 cmp r3, #0 + 800510e: d101 bne.n 8005114 + { + return HAL_ERROR; + 8005110: 2301 movs r3, #1 + 8005112: e030 b.n 8005176 + } + } + +#endif /* CORE_CM0PLUS */ + /* Set Reception type to Standard reception */ + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + 8005114: 68fb ldr r3, [r7, #12] + 8005116: 2200 movs r2, #0 + 8005118: 66da str r2, [r3, #108] @ 0x6c + + if (!(IS_LPUART_INSTANCE(huart->Instance))) + 800511a: 68fb ldr r3, [r7, #12] + 800511c: 681b ldr r3, [r3, #0] + 800511e: 4a18 ldr r2, [pc, #96] @ (8005180 ) + 8005120: 4293 cmp r3, r2 + 8005122: d01f beq.n 8005164 + { + /* Check that USART RTOEN bit is set */ + if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) + 8005124: 68fb ldr r3, [r7, #12] + 8005126: 681b ldr r3, [r3, #0] + 8005128: 685b ldr r3, [r3, #4] + 800512a: f403 0300 and.w r3, r3, #8388608 @ 0x800000 + 800512e: 2b00 cmp r3, #0 + 8005130: d018 beq.n 8005164 + { + /* Enable the UART Receiver Timeout Interrupt */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RTOIE); + 8005132: 68fb ldr r3, [r7, #12] + 8005134: 681b ldr r3, [r3, #0] + 8005136: 617b str r3, [r7, #20] + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 8005138: 697b ldr r3, [r7, #20] + 800513a: e853 3f00 ldrex r3, [r3] + 800513e: 613b str r3, [r7, #16] + return(result); + 8005140: 693b ldr r3, [r7, #16] + 8005142: f043 6380 orr.w r3, r3, #67108864 @ 0x4000000 + 8005146: 627b str r3, [r7, #36] @ 0x24 + 8005148: 68fb ldr r3, [r7, #12] + 800514a: 681b ldr r3, [r3, #0] + 800514c: 461a mov r2, r3 + 800514e: 6a7b ldr r3, [r7, #36] @ 0x24 + 8005150: 623b str r3, [r7, #32] + 8005152: 61fa str r2, [r7, #28] + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 8005154: 69f9 ldr r1, [r7, #28] + 8005156: 6a3a ldr r2, [r7, #32] + 8005158: e841 2300 strex r3, r2, [r1] + 800515c: 61bb str r3, [r7, #24] + return(result); + 800515e: 69bb ldr r3, [r7, #24] + 8005160: 2b00 cmp r3, #0 + 8005162: d1e6 bne.n 8005132 + } + } + + return (UART_Start_Receive_IT(huart, pData, Size)); + 8005164: 88fb ldrh r3, [r7, #6] + 8005166: 461a mov r2, r3 + 8005168: 68b9 ldr r1, [r7, #8] + 800516a: 68f8 ldr r0, [r7, #12] + 800516c: f001 f816 bl 800619c + 8005170: 4603 mov r3, r0 + 8005172: e000 b.n 8005176 + } + else + { + return HAL_BUSY; + 8005174: 2302 movs r3, #2 + } +} + 8005176: 4618 mov r0, r3 + 8005178: 3728 adds r7, #40 @ 0x28 + 800517a: 46bd mov sp, r7 + 800517c: bd80 pop {r7, pc} + 800517e: bf00 nop + 8005180: 40008000 .word 0x40008000 + +08005184 : + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be sent. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size) +{ + 8005184: b580 push {r7, lr} + 8005186: b08a sub sp, #40 @ 0x28 + 8005188: af00 add r7, sp, #0 + 800518a: 60f8 str r0, [r7, #12] + 800518c: 60b9 str r1, [r7, #8] + 800518e: 4613 mov r3, r2 + 8005190: 80fb strh r3, [r7, #6] + /* Check that a Tx process is not already ongoing */ + if (huart->gState == HAL_UART_STATE_READY) + 8005192: 68fb ldr r3, [r7, #12] + 8005194: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 + 8005198: 2b20 cmp r3, #32 + 800519a: d167 bne.n 800526c + { + if ((pData == NULL) || (Size == 0U)) + 800519c: 68bb ldr r3, [r7, #8] + 800519e: 2b00 cmp r3, #0 + 80051a0: d002 beq.n 80051a8 + 80051a2: 88fb ldrh r3, [r7, #6] + 80051a4: 2b00 cmp r3, #0 + 80051a6: d101 bne.n 80051ac + { + return HAL_ERROR; + 80051a8: 2301 movs r3, #1 + 80051aa: e060 b.n 800526e + return HAL_ERROR; + } + } + +#endif /* CORE_CM0PLUS */ + huart->pTxBuffPtr = pData; + 80051ac: 68fb ldr r3, [r7, #12] + 80051ae: 68ba ldr r2, [r7, #8] + 80051b0: 651a str r2, [r3, #80] @ 0x50 + huart->TxXferSize = Size; + 80051b2: 68fb ldr r3, [r7, #12] + 80051b4: 88fa ldrh r2, [r7, #6] + 80051b6: f8a3 2054 strh.w r2, [r3, #84] @ 0x54 + huart->TxXferCount = Size; + 80051ba: 68fb ldr r3, [r7, #12] + 80051bc: 88fa ldrh r2, [r7, #6] + 80051be: f8a3 2056 strh.w r2, [r3, #86] @ 0x56 + + huart->ErrorCode = HAL_UART_ERROR_NONE; + 80051c2: 68fb ldr r3, [r7, #12] + 80051c4: 2200 movs r2, #0 + 80051c6: f8c3 2090 str.w r2, [r3, #144] @ 0x90 + huart->gState = HAL_UART_STATE_BUSY_TX; + 80051ca: 68fb ldr r3, [r7, #12] + 80051cc: 2221 movs r2, #33 @ 0x21 + 80051ce: f8c3 2088 str.w r2, [r3, #136] @ 0x88 + + if (huart->hdmatx != NULL) + 80051d2: 68fb ldr r3, [r7, #12] + 80051d4: 6fdb ldr r3, [r3, #124] @ 0x7c + 80051d6: 2b00 cmp r3, #0 + 80051d8: d028 beq.n 800522c + { + /* Set the UART DMA transfer complete callback */ + huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt; + 80051da: 68fb ldr r3, [r7, #12] + 80051dc: 6fdb ldr r3, [r3, #124] @ 0x7c + 80051de: 4a26 ldr r2, [pc, #152] @ (8005278 ) + 80051e0: 62da str r2, [r3, #44] @ 0x2c + + /* Set the UART DMA Half transfer complete callback */ + huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt; + 80051e2: 68fb ldr r3, [r7, #12] + 80051e4: 6fdb ldr r3, [r3, #124] @ 0x7c + 80051e6: 4a25 ldr r2, [pc, #148] @ (800527c ) + 80051e8: 631a str r2, [r3, #48] @ 0x30 + + /* Set the DMA error callback */ + huart->hdmatx->XferErrorCallback = UART_DMAError; + 80051ea: 68fb ldr r3, [r7, #12] + 80051ec: 6fdb ldr r3, [r3, #124] @ 0x7c + 80051ee: 4a24 ldr r2, [pc, #144] @ (8005280 ) + 80051f0: 635a str r2, [r3, #52] @ 0x34 + + /* Set the DMA abort callback */ + huart->hdmatx->XferAbortCallback = NULL; + 80051f2: 68fb ldr r3, [r7, #12] + 80051f4: 6fdb ldr r3, [r3, #124] @ 0x7c + 80051f6: 2200 movs r2, #0 + 80051f8: 639a str r2, [r3, #56] @ 0x38 + + /* Enable the UART transmit DMA channel */ + if (HAL_DMA_Start_IT(huart->hdmatx, (uint32_t)huart->pTxBuffPtr, (uint32_t)&huart->Instance->TDR, Size) != HAL_OK) + 80051fa: 68fb ldr r3, [r7, #12] + 80051fc: 6fd8 ldr r0, [r3, #124] @ 0x7c + 80051fe: 68fb ldr r3, [r7, #12] + 8005200: 6d1b ldr r3, [r3, #80] @ 0x50 + 8005202: 4619 mov r1, r3 + 8005204: 68fb ldr r3, [r7, #12] + 8005206: 681b ldr r3, [r3, #0] + 8005208: 3328 adds r3, #40 @ 0x28 + 800520a: 461a mov r2, r3 + 800520c: 88fb ldrh r3, [r7, #6] + 800520e: f7fc fd91 bl 8001d34 + 8005212: 4603 mov r3, r0 + 8005214: 2b00 cmp r3, #0 + 8005216: d009 beq.n 800522c + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + 8005218: 68fb ldr r3, [r7, #12] + 800521a: 2210 movs r2, #16 + 800521c: f8c3 2090 str.w r2, [r3, #144] @ 0x90 + + /* Restore huart->gState to ready */ + huart->gState = HAL_UART_STATE_READY; + 8005220: 68fb ldr r3, [r7, #12] + 8005222: 2220 movs r2, #32 + 8005224: f8c3 2088 str.w r2, [r3, #136] @ 0x88 + + return HAL_ERROR; + 8005228: 2301 movs r3, #1 + 800522a: e020 b.n 800526e + } + } + /* Clear the TC flag in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF); + 800522c: 68fb ldr r3, [r7, #12] + 800522e: 681b ldr r3, [r3, #0] + 8005230: 2240 movs r2, #64 @ 0x40 + 8005232: 621a str r2, [r3, #32] + + /* Enable the DMA transfer for transmit request by setting the DMAT bit + in the UART CR3 register */ + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); + 8005234: 68fb ldr r3, [r7, #12] + 8005236: 681b ldr r3, [r3, #0] + 8005238: 3308 adds r3, #8 + 800523a: 617b str r3, [r7, #20] + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 800523c: 697b ldr r3, [r7, #20] + 800523e: e853 3f00 ldrex r3, [r3] + 8005242: 613b str r3, [r7, #16] + return(result); + 8005244: 693b ldr r3, [r7, #16] + 8005246: f043 0380 orr.w r3, r3, #128 @ 0x80 + 800524a: 627b str r3, [r7, #36] @ 0x24 + 800524c: 68fb ldr r3, [r7, #12] + 800524e: 681b ldr r3, [r3, #0] + 8005250: 3308 adds r3, #8 + 8005252: 6a7a ldr r2, [r7, #36] @ 0x24 + 8005254: 623a str r2, [r7, #32] + 8005256: 61fb str r3, [r7, #28] + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 8005258: 69f9 ldr r1, [r7, #28] + 800525a: 6a3a ldr r2, [r7, #32] + 800525c: e841 2300 strex r3, r2, [r1] + 8005260: 61bb str r3, [r7, #24] + return(result); + 8005262: 69bb ldr r3, [r7, #24] + 8005264: 2b00 cmp r3, #0 + 8005266: d1e5 bne.n 8005234 + + return HAL_OK; + 8005268: 2300 movs r3, #0 + 800526a: e000 b.n 800526e + } + else + { + return HAL_BUSY; + 800526c: 2302 movs r3, #2 + } +} + 800526e: 4618 mov r0, r3 + 8005270: 3728 adds r7, #40 @ 0x28 + 8005272: 46bd mov sp, r7 + 8005274: bd80 pop {r7, pc} + 8005276: bf00 nop + 8005278: 08006527 .word 0x08006527 + 800527c: 080065b9 .word 0x080065b9 + 8005280: 080065d5 .word 0x080065d5 + +08005284 : + * @brief Handle UART interrupt request. + * @param huart UART handle. + * @retval None + */ +void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) +{ + 8005284: b580 push {r7, lr} + 8005286: b0ba sub sp, #232 @ 0xe8 + 8005288: af00 add r7, sp, #0 + 800528a: 6078 str r0, [r7, #4] + uint32_t isrflags = READ_REG(huart->Instance->ISR); + 800528c: 687b ldr r3, [r7, #4] + 800528e: 681b ldr r3, [r3, #0] + 8005290: 69db ldr r3, [r3, #28] + 8005292: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4 + uint32_t cr1its = READ_REG(huart->Instance->CR1); + 8005296: 687b ldr r3, [r7, #4] + 8005298: 681b ldr r3, [r3, #0] + 800529a: 681b ldr r3, [r3, #0] + 800529c: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0 + uint32_t cr3its = READ_REG(huart->Instance->CR3); + 80052a0: 687b ldr r3, [r7, #4] + 80052a2: 681b ldr r3, [r3, #0] + 80052a4: 689b ldr r3, [r3, #8] + 80052a6: f8c7 30dc str.w r3, [r7, #220] @ 0xdc + + uint32_t errorflags; + uint32_t errorcode; + + /* If no error occurs */ + errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF)); + 80052aa: f8d7 20e4 ldr.w r2, [r7, #228] @ 0xe4 + 80052ae: f640 030f movw r3, #2063 @ 0x80f + 80052b2: 4013 ands r3, r2 + 80052b4: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8 + if (errorflags == 0U) + 80052b8: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8 + 80052bc: 2b00 cmp r3, #0 + 80052be: d11b bne.n 80052f8 + { + /* UART in mode Receiver ---------------------------------------------------*/ + if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U) + 80052c0: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 + 80052c4: f003 0320 and.w r3, r3, #32 + 80052c8: 2b00 cmp r3, #0 + 80052ca: d015 beq.n 80052f8 + && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) + 80052cc: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 + 80052d0: f003 0320 and.w r3, r3, #32 + 80052d4: 2b00 cmp r3, #0 + 80052d6: d105 bne.n 80052e4 + || ((cr3its & USART_CR3_RXFTIE) != 0U))) + 80052d8: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc + 80052dc: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 + 80052e0: 2b00 cmp r3, #0 + 80052e2: d009 beq.n 80052f8 + { + if (huart->RxISR != NULL) + 80052e4: 687b ldr r3, [r7, #4] + 80052e6: 6f5b ldr r3, [r3, #116] @ 0x74 + 80052e8: 2b00 cmp r3, #0 + 80052ea: f000 8300 beq.w 80058ee + { + huart->RxISR(huart); + 80052ee: 687b ldr r3, [r7, #4] + 80052f0: 6f5b ldr r3, [r3, #116] @ 0x74 + 80052f2: 6878 ldr r0, [r7, #4] + 80052f4: 4798 blx r3 + } + return; + 80052f6: e2fa b.n 80058ee + } + } + + /* If some errors occur */ + if ((errorflags != 0U) + 80052f8: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8 + 80052fc: 2b00 cmp r3, #0 + 80052fe: f000 8123 beq.w 8005548 + && ((((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U) + 8005302: f8d7 20dc ldr.w r2, [r7, #220] @ 0xdc + 8005306: 4b8d ldr r3, [pc, #564] @ (800553c ) + 8005308: 4013 ands r3, r2 + 800530a: 2b00 cmp r3, #0 + 800530c: d106 bne.n 800531c + || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE)) != 0U)))) + 800530e: f8d7 20e0 ldr.w r2, [r7, #224] @ 0xe0 + 8005312: 4b8b ldr r3, [pc, #556] @ (8005540 ) + 8005314: 4013 ands r3, r2 + 8005316: 2b00 cmp r3, #0 + 8005318: f000 8116 beq.w 8005548 + { + /* UART parity error interrupt occurred -------------------------------------*/ + if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) + 800531c: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 + 8005320: f003 0301 and.w r3, r3, #1 + 8005324: 2b00 cmp r3, #0 + 8005326: d011 beq.n 800534c + 8005328: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 + 800532c: f403 7380 and.w r3, r3, #256 @ 0x100 + 8005330: 2b00 cmp r3, #0 + 8005332: d00b beq.n 800534c + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF); + 8005334: 687b ldr r3, [r7, #4] + 8005336: 681b ldr r3, [r3, #0] + 8005338: 2201 movs r2, #1 + 800533a: 621a str r2, [r3, #32] + + huart->ErrorCode |= HAL_UART_ERROR_PE; + 800533c: 687b ldr r3, [r7, #4] + 800533e: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 8005342: f043 0201 orr.w r2, r3, #1 + 8005346: 687b ldr r3, [r7, #4] + 8005348: f8c3 2090 str.w r2, [r3, #144] @ 0x90 + } + + /* UART frame error interrupt occurred --------------------------------------*/ + if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) + 800534c: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 + 8005350: f003 0302 and.w r3, r3, #2 + 8005354: 2b00 cmp r3, #0 + 8005356: d011 beq.n 800537c + 8005358: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc + 800535c: f003 0301 and.w r3, r3, #1 + 8005360: 2b00 cmp r3, #0 + 8005362: d00b beq.n 800537c + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF); + 8005364: 687b ldr r3, [r7, #4] + 8005366: 681b ldr r3, [r3, #0] + 8005368: 2202 movs r2, #2 + 800536a: 621a str r2, [r3, #32] + + huart->ErrorCode |= HAL_UART_ERROR_FE; + 800536c: 687b ldr r3, [r7, #4] + 800536e: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 8005372: f043 0204 orr.w r2, r3, #4 + 8005376: 687b ldr r3, [r7, #4] + 8005378: f8c3 2090 str.w r2, [r3, #144] @ 0x90 + } + + /* UART noise error interrupt occurred --------------------------------------*/ + if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) + 800537c: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 + 8005380: f003 0304 and.w r3, r3, #4 + 8005384: 2b00 cmp r3, #0 + 8005386: d011 beq.n 80053ac + 8005388: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc + 800538c: f003 0301 and.w r3, r3, #1 + 8005390: 2b00 cmp r3, #0 + 8005392: d00b beq.n 80053ac + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF); + 8005394: 687b ldr r3, [r7, #4] + 8005396: 681b ldr r3, [r3, #0] + 8005398: 2204 movs r2, #4 + 800539a: 621a str r2, [r3, #32] + + huart->ErrorCode |= HAL_UART_ERROR_NE; + 800539c: 687b ldr r3, [r7, #4] + 800539e: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 80053a2: f043 0202 orr.w r2, r3, #2 + 80053a6: 687b ldr r3, [r7, #4] + 80053a8: f8c3 2090 str.w r2, [r3, #144] @ 0x90 + } + + /* UART Over-Run interrupt occurred -----------------------------------------*/ + if (((isrflags & USART_ISR_ORE) != 0U) + 80053ac: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 + 80053b0: f003 0308 and.w r3, r3, #8 + 80053b4: 2b00 cmp r3, #0 + 80053b6: d017 beq.n 80053e8 + && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) || + 80053b8: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 + 80053bc: f003 0320 and.w r3, r3, #32 + 80053c0: 2b00 cmp r3, #0 + 80053c2: d105 bne.n 80053d0 + ((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U))) + 80053c4: f8d7 20dc ldr.w r2, [r7, #220] @ 0xdc + 80053c8: 4b5c ldr r3, [pc, #368] @ (800553c ) + 80053ca: 4013 ands r3, r2 + && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) || + 80053cc: 2b00 cmp r3, #0 + 80053ce: d00b beq.n 80053e8 + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); + 80053d0: 687b ldr r3, [r7, #4] + 80053d2: 681b ldr r3, [r3, #0] + 80053d4: 2208 movs r2, #8 + 80053d6: 621a str r2, [r3, #32] + + huart->ErrorCode |= HAL_UART_ERROR_ORE; + 80053d8: 687b ldr r3, [r7, #4] + 80053da: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 80053de: f043 0208 orr.w r2, r3, #8 + 80053e2: 687b ldr r3, [r7, #4] + 80053e4: f8c3 2090 str.w r2, [r3, #144] @ 0x90 + } + + /* UART Receiver Timeout interrupt occurred ---------------------------------*/ + if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U)) + 80053e8: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 + 80053ec: f403 6300 and.w r3, r3, #2048 @ 0x800 + 80053f0: 2b00 cmp r3, #0 + 80053f2: d012 beq.n 800541a + 80053f4: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 + 80053f8: f003 6380 and.w r3, r3, #67108864 @ 0x4000000 + 80053fc: 2b00 cmp r3, #0 + 80053fe: d00c beq.n 800541a + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF); + 8005400: 687b ldr r3, [r7, #4] + 8005402: 681b ldr r3, [r3, #0] + 8005404: f44f 6200 mov.w r2, #2048 @ 0x800 + 8005408: 621a str r2, [r3, #32] + + huart->ErrorCode |= HAL_UART_ERROR_RTO; + 800540a: 687b ldr r3, [r7, #4] + 800540c: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 8005410: f043 0220 orr.w r2, r3, #32 + 8005414: 687b ldr r3, [r7, #4] + 8005416: f8c3 2090 str.w r2, [r3, #144] @ 0x90 + } + + /* Call UART Error Call back function if need be ----------------------------*/ + if (huart->ErrorCode != HAL_UART_ERROR_NONE) + 800541a: 687b ldr r3, [r7, #4] + 800541c: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 8005420: 2b00 cmp r3, #0 + 8005422: f000 8266 beq.w 80058f2 + { + /* UART in mode Receiver --------------------------------------------------*/ + if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U) + 8005426: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 + 800542a: f003 0320 and.w r3, r3, #32 + 800542e: 2b00 cmp r3, #0 + 8005430: d013 beq.n 800545a + && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) + 8005432: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 + 8005436: f003 0320 and.w r3, r3, #32 + 800543a: 2b00 cmp r3, #0 + 800543c: d105 bne.n 800544a + || ((cr3its & USART_CR3_RXFTIE) != 0U))) + 800543e: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc + 8005442: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 + 8005446: 2b00 cmp r3, #0 + 8005448: d007 beq.n 800545a + { + if (huart->RxISR != NULL) + 800544a: 687b ldr r3, [r7, #4] + 800544c: 6f5b ldr r3, [r3, #116] @ 0x74 + 800544e: 2b00 cmp r3, #0 + 8005450: d003 beq.n 800545a + { + huart->RxISR(huart); + 8005452: 687b ldr r3, [r7, #4] + 8005454: 6f5b ldr r3, [r3, #116] @ 0x74 + 8005456: 6878 ldr r0, [r7, #4] + 8005458: 4798 blx r3 + /* If Error is to be considered as blocking : + - Receiver Timeout error in Reception + - Overrun error in Reception + - any error occurs in DMA mode reception + */ + errorcode = huart->ErrorCode; + 800545a: 687b ldr r3, [r7, #4] + 800545c: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 8005460: f8c7 30d4 str.w r3, [r7, #212] @ 0xd4 + if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) || + 8005464: 687b ldr r3, [r7, #4] + 8005466: 681b ldr r3, [r3, #0] + 8005468: 689b ldr r3, [r3, #8] + 800546a: f003 0340 and.w r3, r3, #64 @ 0x40 + 800546e: 2b40 cmp r3, #64 @ 0x40 + 8005470: d005 beq.n 800547e + ((errorcode & (HAL_UART_ERROR_RTO | HAL_UART_ERROR_ORE)) != 0U)) + 8005472: f8d7 30d4 ldr.w r3, [r7, #212] @ 0xd4 + 8005476: f003 0328 and.w r3, r3, #40 @ 0x28 + if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) || + 800547a: 2b00 cmp r3, #0 + 800547c: d054 beq.n 8005528 + { + /* Blocking error : transfer is aborted + Set the UART state ready to be able to start again the process, + Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ + UART_EndRxTransfer(huart); + 800547e: 6878 ldr r0, [r7, #4] + 8005480: f000 ffec bl 800645c + + /* Abort the UART DMA Rx channel if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + 8005484: 687b ldr r3, [r7, #4] + 8005486: 681b ldr r3, [r3, #0] + 8005488: 689b ldr r3, [r3, #8] + 800548a: f003 0340 and.w r3, r3, #64 @ 0x40 + 800548e: 2b40 cmp r3, #64 @ 0x40 + 8005490: d146 bne.n 8005520 + { + /* Disable the UART DMA Rx request if enabled */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + 8005492: 687b ldr r3, [r7, #4] + 8005494: 681b ldr r3, [r3, #0] + 8005496: 3308 adds r3, #8 + 8005498: f8c7 309c str.w r3, [r7, #156] @ 0x9c + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 800549c: f8d7 309c ldr.w r3, [r7, #156] @ 0x9c + 80054a0: e853 3f00 ldrex r3, [r3] + 80054a4: f8c7 3098 str.w r3, [r7, #152] @ 0x98 + return(result); + 80054a8: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98 + 80054ac: f023 0340 bic.w r3, r3, #64 @ 0x40 + 80054b0: f8c7 30d0 str.w r3, [r7, #208] @ 0xd0 + 80054b4: 687b ldr r3, [r7, #4] + 80054b6: 681b ldr r3, [r3, #0] + 80054b8: 3308 adds r3, #8 + 80054ba: f8d7 20d0 ldr.w r2, [r7, #208] @ 0xd0 + 80054be: f8c7 20a8 str.w r2, [r7, #168] @ 0xa8 + 80054c2: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4 + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 80054c6: f8d7 10a4 ldr.w r1, [r7, #164] @ 0xa4 + 80054ca: f8d7 20a8 ldr.w r2, [r7, #168] @ 0xa8 + 80054ce: e841 2300 strex r3, r2, [r1] + 80054d2: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0 + return(result); + 80054d6: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0 + 80054da: 2b00 cmp r3, #0 + 80054dc: d1d9 bne.n 8005492 + + /* Abort the UART DMA Rx channel */ + if (huart->hdmarx != NULL) + 80054de: 687b ldr r3, [r7, #4] + 80054e0: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 + 80054e4: 2b00 cmp r3, #0 + 80054e6: d017 beq.n 8005518 + { + /* Set the UART DMA Abort callback : + will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */ + huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError; + 80054e8: 687b ldr r3, [r7, #4] + 80054ea: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 + 80054ee: 4a15 ldr r2, [pc, #84] @ (8005544 ) + 80054f0: 639a str r2, [r3, #56] @ 0x38 + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) + 80054f2: 687b ldr r3, [r7, #4] + 80054f4: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 + 80054f8: 4618 mov r0, r3 + 80054fa: f7fc fcf7 bl 8001eec + 80054fe: 4603 mov r3, r0 + 8005500: 2b00 cmp r3, #0 + 8005502: d019 beq.n 8005538 + { + /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */ + huart->hdmarx->XferAbortCallback(huart->hdmarx); + 8005504: 687b ldr r3, [r7, #4] + 8005506: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 + 800550a: 6b9b ldr r3, [r3, #56] @ 0x38 + 800550c: 687a ldr r2, [r7, #4] + 800550e: f8d2 2080 ldr.w r2, [r2, #128] @ 0x80 + 8005512: 4610 mov r0, r2 + 8005514: 4798 blx r3 + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + 8005516: e00f b.n 8005538 +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); + 8005518: 6878 ldr r0, [r7, #4] + 800551a: f000 f9fe bl 800591a + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + 800551e: e00b b.n 8005538 +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); + 8005520: 6878 ldr r0, [r7, #4] + 8005522: f000 f9fa bl 800591a + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + 8005526: e007 b.n 8005538 +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); + 8005528: 6878 ldr r0, [r7, #4] + 800552a: f000 f9f6 bl 800591a +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + 800552e: 687b ldr r3, [r7, #4] + 8005530: 2200 movs r2, #0 + 8005532: f8c3 2090 str.w r2, [r3, #144] @ 0x90 + } + } + return; + 8005536: e1dc b.n 80058f2 + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + 8005538: bf00 nop + return; + 800553a: e1da b.n 80058f2 + 800553c: 10000001 .word 0x10000001 + 8005540: 04000120 .word 0x04000120 + 8005544: 08006645 .word 0x08006645 + + } /* End if some error occurs */ + + /* Check current reception Mode : + If Reception till IDLE event has been selected : */ + if ((huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + 8005548: 687b ldr r3, [r7, #4] + 800554a: 6edb ldr r3, [r3, #108] @ 0x6c + 800554c: 2b01 cmp r3, #1 + 800554e: f040 8170 bne.w 8005832 + && ((isrflags & USART_ISR_IDLE) != 0U) + 8005552: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 + 8005556: f003 0310 and.w r3, r3, #16 + 800555a: 2b00 cmp r3, #0 + 800555c: f000 8169 beq.w 8005832 + && ((cr1its & USART_ISR_IDLE) != 0U)) + 8005560: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 + 8005564: f003 0310 and.w r3, r3, #16 + 8005568: 2b00 cmp r3, #0 + 800556a: f000 8162 beq.w 8005832 + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + 800556e: 687b ldr r3, [r7, #4] + 8005570: 681b ldr r3, [r3, #0] + 8005572: 2210 movs r2, #16 + 8005574: 621a str r2, [r3, #32] + + /* Check if DMA mode is enabled in UART */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + 8005576: 687b ldr r3, [r7, #4] + 8005578: 681b ldr r3, [r3, #0] + 800557a: 689b ldr r3, [r3, #8] + 800557c: f003 0340 and.w r3, r3, #64 @ 0x40 + 8005580: 2b40 cmp r3, #64 @ 0x40 + 8005582: f040 80d8 bne.w 8005736 + { + /* DMA mode enabled */ + /* Check received length : If all expected data are received, do nothing, + (DMA cplt callback will be called). + Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ + uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx); + 8005586: 687b ldr r3, [r7, #4] + 8005588: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 + 800558c: 681b ldr r3, [r3, #0] + 800558e: 685b ldr r3, [r3, #4] + 8005590: f8a7 30be strh.w r3, [r7, #190] @ 0xbe + if ((nb_remaining_rx_data > 0U) + 8005594: f8b7 30be ldrh.w r3, [r7, #190] @ 0xbe + 8005598: 2b00 cmp r3, #0 + 800559a: f000 80af beq.w 80056fc + && (nb_remaining_rx_data < huart->RxXferSize)) + 800559e: 687b ldr r3, [r7, #4] + 80055a0: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c + 80055a4: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe + 80055a8: 429a cmp r2, r3 + 80055aa: f080 80a7 bcs.w 80056fc + { + /* Reception is not complete */ + huart->RxXferCount = nb_remaining_rx_data; + 80055ae: 687b ldr r3, [r7, #4] + 80055b0: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe + 80055b4: f8a3 205e strh.w r2, [r3, #94] @ 0x5e + + /* In Normal mode, end DMA xfer and HAL UART Rx process*/ + if (HAL_IS_BIT_CLR(huart->hdmarx->Instance->CCR, DMA_CCR_CIRC)) + 80055b8: 687b ldr r3, [r7, #4] + 80055ba: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 + 80055be: 681b ldr r3, [r3, #0] + 80055c0: 681b ldr r3, [r3, #0] + 80055c2: f003 0320 and.w r3, r3, #32 + 80055c6: 2b00 cmp r3, #0 + 80055c8: f040 8087 bne.w 80056da + { + /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); + 80055cc: 687b ldr r3, [r7, #4] + 80055ce: 681b ldr r3, [r3, #0] + 80055d0: f8c7 3088 str.w r3, [r7, #136] @ 0x88 + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 80055d4: f8d7 3088 ldr.w r3, [r7, #136] @ 0x88 + 80055d8: e853 3f00 ldrex r3, [r3] + 80055dc: f8c7 3084 str.w r3, [r7, #132] @ 0x84 + return(result); + 80055e0: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84 + 80055e4: f423 7380 bic.w r3, r3, #256 @ 0x100 + 80055e8: f8c7 30b8 str.w r3, [r7, #184] @ 0xb8 + 80055ec: 687b ldr r3, [r7, #4] + 80055ee: 681b ldr r3, [r3, #0] + 80055f0: 461a mov r2, r3 + 80055f2: f8d7 30b8 ldr.w r3, [r7, #184] @ 0xb8 + 80055f6: f8c7 3094 str.w r3, [r7, #148] @ 0x94 + 80055fa: f8c7 2090 str.w r2, [r7, #144] @ 0x90 + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 80055fe: f8d7 1090 ldr.w r1, [r7, #144] @ 0x90 + 8005602: f8d7 2094 ldr.w r2, [r7, #148] @ 0x94 + 8005606: e841 2300 strex r3, r2, [r1] + 800560a: f8c7 308c str.w r3, [r7, #140] @ 0x8c + return(result); + 800560e: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c + 8005612: 2b00 cmp r3, #0 + 8005614: d1da bne.n 80055cc + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 8005616: 687b ldr r3, [r7, #4] + 8005618: 681b ldr r3, [r3, #0] + 800561a: 3308 adds r3, #8 + 800561c: 677b str r3, [r7, #116] @ 0x74 + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 800561e: 6f7b ldr r3, [r7, #116] @ 0x74 + 8005620: e853 3f00 ldrex r3, [r3] + 8005624: 673b str r3, [r7, #112] @ 0x70 + return(result); + 8005626: 6f3b ldr r3, [r7, #112] @ 0x70 + 8005628: f023 0301 bic.w r3, r3, #1 + 800562c: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 + 8005630: 687b ldr r3, [r7, #4] + 8005632: 681b ldr r3, [r3, #0] + 8005634: 3308 adds r3, #8 + 8005636: f8d7 20b4 ldr.w r2, [r7, #180] @ 0xb4 + 800563a: f8c7 2080 str.w r2, [r7, #128] @ 0x80 + 800563e: 67fb str r3, [r7, #124] @ 0x7c + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 8005640: 6ff9 ldr r1, [r7, #124] @ 0x7c + 8005642: f8d7 2080 ldr.w r2, [r7, #128] @ 0x80 + 8005646: e841 2300 strex r3, r2, [r1] + 800564a: 67bb str r3, [r7, #120] @ 0x78 + return(result); + 800564c: 6fbb ldr r3, [r7, #120] @ 0x78 + 800564e: 2b00 cmp r3, #0 + 8005650: d1e1 bne.n 8005616 + + /* Disable the DMA transfer for the receiver request by resetting the DMAR bit + in the UART CR3 register */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + 8005652: 687b ldr r3, [r7, #4] + 8005654: 681b ldr r3, [r3, #0] + 8005656: 3308 adds r3, #8 + 8005658: 663b str r3, [r7, #96] @ 0x60 + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 800565a: 6e3b ldr r3, [r7, #96] @ 0x60 + 800565c: e853 3f00 ldrex r3, [r3] + 8005660: 65fb str r3, [r7, #92] @ 0x5c + return(result); + 8005662: 6dfb ldr r3, [r7, #92] @ 0x5c + 8005664: f023 0340 bic.w r3, r3, #64 @ 0x40 + 8005668: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 + 800566c: 687b ldr r3, [r7, #4] + 800566e: 681b ldr r3, [r3, #0] + 8005670: 3308 adds r3, #8 + 8005672: f8d7 20b0 ldr.w r2, [r7, #176] @ 0xb0 + 8005676: 66fa str r2, [r7, #108] @ 0x6c + 8005678: 66bb str r3, [r7, #104] @ 0x68 + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 800567a: 6eb9 ldr r1, [r7, #104] @ 0x68 + 800567c: 6efa ldr r2, [r7, #108] @ 0x6c + 800567e: e841 2300 strex r3, r2, [r1] + 8005682: 667b str r3, [r7, #100] @ 0x64 + return(result); + 8005684: 6e7b ldr r3, [r7, #100] @ 0x64 + 8005686: 2b00 cmp r3, #0 + 8005688: d1e3 bne.n 8005652 + + /* At end of Rx process, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + 800568a: 687b ldr r3, [r7, #4] + 800568c: 2220 movs r2, #32 + 800568e: f8c3 208c str.w r2, [r3, #140] @ 0x8c + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + 8005692: 687b ldr r3, [r7, #4] + 8005694: 2200 movs r2, #0 + 8005696: 66da str r2, [r3, #108] @ 0x6c + + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + 8005698: 687b ldr r3, [r7, #4] + 800569a: 681b ldr r3, [r3, #0] + 800569c: 64fb str r3, [r7, #76] @ 0x4c + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 800569e: 6cfb ldr r3, [r7, #76] @ 0x4c + 80056a0: e853 3f00 ldrex r3, [r3] + 80056a4: 64bb str r3, [r7, #72] @ 0x48 + return(result); + 80056a6: 6cbb ldr r3, [r7, #72] @ 0x48 + 80056a8: f023 0310 bic.w r3, r3, #16 + 80056ac: f8c7 30ac str.w r3, [r7, #172] @ 0xac + 80056b0: 687b ldr r3, [r7, #4] + 80056b2: 681b ldr r3, [r3, #0] + 80056b4: 461a mov r2, r3 + 80056b6: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac + 80056ba: 65bb str r3, [r7, #88] @ 0x58 + 80056bc: 657a str r2, [r7, #84] @ 0x54 + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 80056be: 6d79 ldr r1, [r7, #84] @ 0x54 + 80056c0: 6dba ldr r2, [r7, #88] @ 0x58 + 80056c2: e841 2300 strex r3, r2, [r1] + 80056c6: 653b str r3, [r7, #80] @ 0x50 + return(result); + 80056c8: 6d3b ldr r3, [r7, #80] @ 0x50 + 80056ca: 2b00 cmp r3, #0 + 80056cc: d1e4 bne.n 8005698 + + /* Last bytes received, so no need as the abort is immediate */ + (void)HAL_DMA_Abort(huart->hdmarx); + 80056ce: 687b ldr r3, [r7, #4] + 80056d0: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 + 80056d4: 4618 mov r0, r3 + 80056d6: f7fc fbab bl 8001e30 + } + + /* Initialize type of RxEvent that correspond to RxEvent callback execution; + In this case, Rx Event type is Idle Event */ + huart->RxEventType = HAL_UART_RXEVENT_IDLE; + 80056da: 687b ldr r3, [r7, #4] + 80056dc: 2202 movs r2, #2 + 80056de: 671a str r2, [r3, #112] @ 0x70 +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); + 80056e0: 687b ldr r3, [r7, #4] + 80056e2: f8b3 205c ldrh.w r2, [r3, #92] @ 0x5c + 80056e6: 687b ldr r3, [r7, #4] + 80056e8: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e + 80056ec: b29b uxth r3, r3 + 80056ee: 1ad3 subs r3, r2, r3 + 80056f0: b29b uxth r3, r3 + 80056f2: 4619 mov r1, r3 + 80056f4: 6878 ldr r0, [r7, #4] + 80056f6: f000 f919 bl 800592c + HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + } + } + return; + 80056fa: e0fc b.n 80058f6 + if (nb_remaining_rx_data == huart->RxXferSize) + 80056fc: 687b ldr r3, [r7, #4] + 80056fe: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c + 8005702: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe + 8005706: 429a cmp r2, r3 + 8005708: f040 80f5 bne.w 80058f6 + if (HAL_IS_BIT_SET(huart->hdmarx->Instance->CCR, DMA_CCR_CIRC)) + 800570c: 687b ldr r3, [r7, #4] + 800570e: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 + 8005712: 681b ldr r3, [r3, #0] + 8005714: 681b ldr r3, [r3, #0] + 8005716: f003 0320 and.w r3, r3, #32 + 800571a: 2b20 cmp r3, #32 + 800571c: f040 80eb bne.w 80058f6 + huart->RxEventType = HAL_UART_RXEVENT_IDLE; + 8005720: 687b ldr r3, [r7, #4] + 8005722: 2202 movs r2, #2 + 8005724: 671a str r2, [r3, #112] @ 0x70 + HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); + 8005726: 687b ldr r3, [r7, #4] + 8005728: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c + 800572c: 4619 mov r1, r3 + 800572e: 6878 ldr r0, [r7, #4] + 8005730: f000 f8fc bl 800592c + return; + 8005734: e0df b.n 80058f6 + else + { + /* DMA mode not enabled */ + /* Check received length : If all expected data are received, do nothing. + Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ + uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount; + 8005736: 687b ldr r3, [r7, #4] + 8005738: f8b3 205c ldrh.w r2, [r3, #92] @ 0x5c + 800573c: 687b ldr r3, [r7, #4] + 800573e: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e + 8005742: b29b uxth r3, r3 + 8005744: 1ad3 subs r3, r2, r3 + 8005746: f8a7 30ce strh.w r3, [r7, #206] @ 0xce + if ((huart->RxXferCount > 0U) + 800574a: 687b ldr r3, [r7, #4] + 800574c: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e + 8005750: b29b uxth r3, r3 + 8005752: 2b00 cmp r3, #0 + 8005754: f000 80d1 beq.w 80058fa + && (nb_rx_data > 0U)) + 8005758: f8b7 30ce ldrh.w r3, [r7, #206] @ 0xce + 800575c: 2b00 cmp r3, #0 + 800575e: f000 80cc beq.w 80058fa + { + /* Disable the UART Parity Error Interrupt and RXNE interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); + 8005762: 687b ldr r3, [r7, #4] + 8005764: 681b ldr r3, [r3, #0] + 8005766: 63bb str r3, [r7, #56] @ 0x38 + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 8005768: 6bbb ldr r3, [r7, #56] @ 0x38 + 800576a: e853 3f00 ldrex r3, [r3] + 800576e: 637b str r3, [r7, #52] @ 0x34 + return(result); + 8005770: 6b7b ldr r3, [r7, #52] @ 0x34 + 8005772: f423 7390 bic.w r3, r3, #288 @ 0x120 + 8005776: f8c7 30c8 str.w r3, [r7, #200] @ 0xc8 + 800577a: 687b ldr r3, [r7, #4] + 800577c: 681b ldr r3, [r3, #0] + 800577e: 461a mov r2, r3 + 8005780: f8d7 30c8 ldr.w r3, [r7, #200] @ 0xc8 + 8005784: 647b str r3, [r7, #68] @ 0x44 + 8005786: 643a str r2, [r7, #64] @ 0x40 + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 8005788: 6c39 ldr r1, [r7, #64] @ 0x40 + 800578a: 6c7a ldr r2, [r7, #68] @ 0x44 + 800578c: e841 2300 strex r3, r2, [r1] + 8005790: 63fb str r3, [r7, #60] @ 0x3c + return(result); + 8005792: 6bfb ldr r3, [r7, #60] @ 0x3c + 8005794: 2b00 cmp r3, #0 + 8005796: d1e4 bne.n 8005762 + + /* Disable the UART Error Interrupt:(Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); + 8005798: 687b ldr r3, [r7, #4] + 800579a: 681b ldr r3, [r3, #0] + 800579c: 3308 adds r3, #8 + 800579e: 627b str r3, [r7, #36] @ 0x24 + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 80057a0: 6a7b ldr r3, [r7, #36] @ 0x24 + 80057a2: e853 3f00 ldrex r3, [r3] + 80057a6: 623b str r3, [r7, #32] + return(result); + 80057a8: 6a3b ldr r3, [r7, #32] + 80057aa: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 + 80057ae: f023 0301 bic.w r3, r3, #1 + 80057b2: f8c7 30c4 str.w r3, [r7, #196] @ 0xc4 + 80057b6: 687b ldr r3, [r7, #4] + 80057b8: 681b ldr r3, [r3, #0] + 80057ba: 3308 adds r3, #8 + 80057bc: f8d7 20c4 ldr.w r2, [r7, #196] @ 0xc4 + 80057c0: 633a str r2, [r7, #48] @ 0x30 + 80057c2: 62fb str r3, [r7, #44] @ 0x2c + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 80057c4: 6af9 ldr r1, [r7, #44] @ 0x2c + 80057c6: 6b3a ldr r2, [r7, #48] @ 0x30 + 80057c8: e841 2300 strex r3, r2, [r1] + 80057cc: 62bb str r3, [r7, #40] @ 0x28 + return(result); + 80057ce: 6abb ldr r3, [r7, #40] @ 0x28 + 80057d0: 2b00 cmp r3, #0 + 80057d2: d1e1 bne.n 8005798 + + /* Rx process is completed, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + 80057d4: 687b ldr r3, [r7, #4] + 80057d6: 2220 movs r2, #32 + 80057d8: f8c3 208c str.w r2, [r3, #140] @ 0x8c + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + 80057dc: 687b ldr r3, [r7, #4] + 80057de: 2200 movs r2, #0 + 80057e0: 66da str r2, [r3, #108] @ 0x6c + + /* Clear RxISR function pointer */ + huart->RxISR = NULL; + 80057e2: 687b ldr r3, [r7, #4] + 80057e4: 2200 movs r2, #0 + 80057e6: 675a str r2, [r3, #116] @ 0x74 + + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + 80057e8: 687b ldr r3, [r7, #4] + 80057ea: 681b ldr r3, [r3, #0] + 80057ec: 613b str r3, [r7, #16] + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 80057ee: 693b ldr r3, [r7, #16] + 80057f0: e853 3f00 ldrex r3, [r3] + 80057f4: 60fb str r3, [r7, #12] + return(result); + 80057f6: 68fb ldr r3, [r7, #12] + 80057f8: f023 0310 bic.w r3, r3, #16 + 80057fc: f8c7 30c0 str.w r3, [r7, #192] @ 0xc0 + 8005800: 687b ldr r3, [r7, #4] + 8005802: 681b ldr r3, [r3, #0] + 8005804: 461a mov r2, r3 + 8005806: f8d7 30c0 ldr.w r3, [r7, #192] @ 0xc0 + 800580a: 61fb str r3, [r7, #28] + 800580c: 61ba str r2, [r7, #24] + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 800580e: 69b9 ldr r1, [r7, #24] + 8005810: 69fa ldr r2, [r7, #28] + 8005812: e841 2300 strex r3, r2, [r1] + 8005816: 617b str r3, [r7, #20] + return(result); + 8005818: 697b ldr r3, [r7, #20] + 800581a: 2b00 cmp r3, #0 + 800581c: d1e4 bne.n 80057e8 + + /* Initialize type of RxEvent that correspond to RxEvent callback execution; + In this case, Rx Event type is Idle Event */ + huart->RxEventType = HAL_UART_RXEVENT_IDLE; + 800581e: 687b ldr r3, [r7, #4] + 8005820: 2202 movs r2, #2 + 8005822: 671a str r2, [r3, #112] @ 0x70 +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx complete callback*/ + huart->RxEventCallback(huart, nb_rx_data); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, nb_rx_data); + 8005824: f8b7 30ce ldrh.w r3, [r7, #206] @ 0xce + 8005828: 4619 mov r1, r3 + 800582a: 6878 ldr r0, [r7, #4] + 800582c: f000 f87e bl 800592c +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + return; + 8005830: e063 b.n 80058fa + } + } + + /* UART wakeup from Stop mode interrupt occurred ---------------------------*/ + if (((isrflags & USART_ISR_WUF) != 0U) && ((cr3its & USART_CR3_WUFIE) != 0U)) + 8005832: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 + 8005836: f403 1380 and.w r3, r3, #1048576 @ 0x100000 + 800583a: 2b00 cmp r3, #0 + 800583c: d00e beq.n 800585c + 800583e: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc + 8005842: f403 0380 and.w r3, r3, #4194304 @ 0x400000 + 8005846: 2b00 cmp r3, #0 + 8005848: d008 beq.n 800585c + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_WUF); + 800584a: 687b ldr r3, [r7, #4] + 800584c: 681b ldr r3, [r3, #0] + 800584e: f44f 1280 mov.w r2, #1048576 @ 0x100000 + 8005852: 621a str r2, [r3, #32] +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Wakeup Callback */ + huart->WakeupCallback(huart); +#else + /* Call legacy weak Wakeup Callback */ + HAL_UARTEx_WakeupCallback(huart); + 8005854: 6878 ldr r0, [r7, #4] + 8005856: f001 fc4f bl 80070f8 +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + return; + 800585a: e051 b.n 8005900 + } + + /* UART in mode Transmitter ------------------------------------------------*/ + if (((isrflags & USART_ISR_TXE_TXFNF) != 0U) + 800585c: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 + 8005860: f003 0380 and.w r3, r3, #128 @ 0x80 + 8005864: 2b00 cmp r3, #0 + 8005866: d014 beq.n 8005892 + && (((cr1its & USART_CR1_TXEIE_TXFNFIE) != 0U) + 8005868: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 + 800586c: f003 0380 and.w r3, r3, #128 @ 0x80 + 8005870: 2b00 cmp r3, #0 + 8005872: d105 bne.n 8005880 + || ((cr3its & USART_CR3_TXFTIE) != 0U))) + 8005874: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc + 8005878: f403 0300 and.w r3, r3, #8388608 @ 0x800000 + 800587c: 2b00 cmp r3, #0 + 800587e: d008 beq.n 8005892 + { + if (huart->TxISR != NULL) + 8005880: 687b ldr r3, [r7, #4] + 8005882: 6f9b ldr r3, [r3, #120] @ 0x78 + 8005884: 2b00 cmp r3, #0 + 8005886: d03a beq.n 80058fe + { + huart->TxISR(huart); + 8005888: 687b ldr r3, [r7, #4] + 800588a: 6f9b ldr r3, [r3, #120] @ 0x78 + 800588c: 6878 ldr r0, [r7, #4] + 800588e: 4798 blx r3 + } + return; + 8005890: e035 b.n 80058fe + } + + /* UART in mode Transmitter (transmission end) -----------------------------*/ + if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U)) + 8005892: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 + 8005896: f003 0340 and.w r3, r3, #64 @ 0x40 + 800589a: 2b00 cmp r3, #0 + 800589c: d009 beq.n 80058b2 + 800589e: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 + 80058a2: f003 0340 and.w r3, r3, #64 @ 0x40 + 80058a6: 2b00 cmp r3, #0 + 80058a8: d003 beq.n 80058b2 + { + UART_EndTransmit_IT(huart); + 80058aa: 6878 ldr r0, [r7, #4] + 80058ac: f000 fed8 bl 8006660 + return; + 80058b0: e026 b.n 8005900 + } + + /* UART TX Fifo Empty occurred ----------------------------------------------*/ + if (((isrflags & USART_ISR_TXFE) != 0U) && ((cr1its & USART_CR1_TXFEIE) != 0U)) + 80058b2: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 + 80058b6: f403 0300 and.w r3, r3, #8388608 @ 0x800000 + 80058ba: 2b00 cmp r3, #0 + 80058bc: d009 beq.n 80058d2 + 80058be: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 + 80058c2: f003 4380 and.w r3, r3, #1073741824 @ 0x40000000 + 80058c6: 2b00 cmp r3, #0 + 80058c8: d003 beq.n 80058d2 +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Tx Fifo Empty Callback */ + huart->TxFifoEmptyCallback(huart); +#else + /* Call legacy weak Tx Fifo Empty Callback */ + HAL_UARTEx_TxFifoEmptyCallback(huart); + 80058ca: 6878 ldr r0, [r7, #4] + 80058cc: f001 fc26 bl 800711c +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + return; + 80058d0: e016 b.n 8005900 + } + + /* UART RX Fifo Full occurred ----------------------------------------------*/ + if (((isrflags & USART_ISR_RXFF) != 0U) && ((cr1its & USART_CR1_RXFFIE) != 0U)) + 80058d2: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 + 80058d6: f003 7380 and.w r3, r3, #16777216 @ 0x1000000 + 80058da: 2b00 cmp r3, #0 + 80058dc: d010 beq.n 8005900 + 80058de: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 + 80058e2: 2b00 cmp r3, #0 + 80058e4: da0c bge.n 8005900 +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Rx Fifo Full Callback */ + huart->RxFifoFullCallback(huart); +#else + /* Call legacy weak Rx Fifo Full Callback */ + HAL_UARTEx_RxFifoFullCallback(huart); + 80058e6: 6878 ldr r0, [r7, #4] + 80058e8: f001 fc0f bl 800710a +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + return; + 80058ec: e008 b.n 8005900 + return; + 80058ee: bf00 nop + 80058f0: e006 b.n 8005900 + return; + 80058f2: bf00 nop + 80058f4: e004 b.n 8005900 + return; + 80058f6: bf00 nop + 80058f8: e002 b.n 8005900 + return; + 80058fa: bf00 nop + 80058fc: e000 b.n 8005900 + return; + 80058fe: bf00 nop + } +} + 8005900: 37e8 adds r7, #232 @ 0xe8 + 8005902: 46bd mov sp, r7 + 8005904: bd80 pop {r7, pc} + 8005906: bf00 nop + +08005908 : + * @brief Tx Half Transfer completed callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart) +{ + 8005908: b480 push {r7} + 800590a: b083 sub sp, #12 + 800590c: af00 add r7, sp, #0 + 800590e: 6078 str r0, [r7, #4] + UNUSED(huart); + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_UART_TxHalfCpltCallback can be implemented in the user file. + */ +} + 8005910: bf00 nop + 8005912: 370c adds r7, #12 + 8005914: 46bd mov sp, r7 + 8005916: bc80 pop {r7} + 8005918: 4770 bx lr + +0800591a : + * @brief UART error callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) +{ + 800591a: b480 push {r7} + 800591c: b083 sub sp, #12 + 800591e: af00 add r7, sp, #0 + 8005920: 6078 str r0, [r7, #4] + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_ErrorCallback can be implemented in the user file. + */ +} + 8005922: bf00 nop + 8005924: 370c adds r7, #12 + 8005926: 46bd mov sp, r7 + 8005928: bc80 pop {r7} + 800592a: 4770 bx lr + +0800592c : + * @param Size Number of data available in application reception buffer (indicates a position in + * reception buffer until which, data are available) + * @retval None + */ +__weak void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size) +{ + 800592c: b480 push {r7} + 800592e: b083 sub sp, #12 + 8005930: af00 add r7, sp, #0 + 8005932: 6078 str r0, [r7, #4] + 8005934: 460b mov r3, r1 + 8005936: 807b strh r3, [r7, #2] + UNUSED(Size); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UARTEx_RxEventCallback can be implemented in the user file. + */ +} + 8005938: bf00 nop + 800593a: 370c adds r7, #12 + 800593c: 46bd mov sp, r7 + 800593e: bc80 pop {r7} + 8005940: 4770 bx lr + ... + +08005944 : + * @brief Configure the UART peripheral. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) +{ + 8005944: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr} + 8005948: b08c sub sp, #48 @ 0x30 + 800594a: af00 add r7, sp, #0 + 800594c: 6178 str r0, [r7, #20] + uint32_t tmpreg; + uint16_t brrtemp; + UART_ClockSourceTypeDef clocksource; + uint32_t usartdiv; + HAL_StatusTypeDef ret = HAL_OK; + 800594e: 2300 movs r3, #0 + 8005950: f887 302a strb.w r3, [r7, #42] @ 0x2a + * the UART Word Length, Parity, Mode and oversampling: + * set the M bits according to huart->Init.WordLength value + * set PCE and PS bits according to huart->Init.Parity value + * set TE and RE bits according to huart->Init.Mode value + * set OVER8 bit according to huart->Init.OverSampling value */ + tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ; + 8005954: 697b ldr r3, [r7, #20] + 8005956: 689a ldr r2, [r3, #8] + 8005958: 697b ldr r3, [r7, #20] + 800595a: 691b ldr r3, [r3, #16] + 800595c: 431a orrs r2, r3 + 800595e: 697b ldr r3, [r7, #20] + 8005960: 695b ldr r3, [r3, #20] + 8005962: 431a orrs r2, r3 + 8005964: 697b ldr r3, [r7, #20] + 8005966: 69db ldr r3, [r3, #28] + 8005968: 4313 orrs r3, r2 + 800596a: 62fb str r3, [r7, #44] @ 0x2c + MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg); + 800596c: 697b ldr r3, [r7, #20] + 800596e: 681b ldr r3, [r3, #0] + 8005970: 681a ldr r2, [r3, #0] + 8005972: 4b94 ldr r3, [pc, #592] @ (8005bc4 ) + 8005974: 4013 ands r3, r2 + 8005976: 697a ldr r2, [r7, #20] + 8005978: 6812 ldr r2, [r2, #0] + 800597a: 6af9 ldr r1, [r7, #44] @ 0x2c + 800597c: 430b orrs r3, r1 + 800597e: 6013 str r3, [r2, #0] + + /*-------------------------- USART CR2 Configuration -----------------------*/ + /* Configure the UART Stop Bits: Set STOP[13:12] bits according + * to huart->Init.StopBits value */ + MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); + 8005980: 697b ldr r3, [r7, #20] + 8005982: 681b ldr r3, [r3, #0] + 8005984: 685b ldr r3, [r3, #4] + 8005986: f423 5140 bic.w r1, r3, #12288 @ 0x3000 + 800598a: 697b ldr r3, [r7, #20] + 800598c: 68da ldr r2, [r3, #12] + 800598e: 697b ldr r3, [r7, #20] + 8005990: 681b ldr r3, [r3, #0] + 8005992: 430a orrs r2, r1 + 8005994: 605a str r2, [r3, #4] + /* Configure + * - UART HardWare Flow Control: set CTSE and RTSE bits according + * to huart->Init.HwFlowCtl value + * - one-bit sampling method versus three samples' majority rule according + * to huart->Init.OneBitSampling (not applicable to LPUART) */ + tmpreg = (uint32_t)huart->Init.HwFlowCtl; + 8005996: 697b ldr r3, [r7, #20] + 8005998: 699b ldr r3, [r3, #24] + 800599a: 62fb str r3, [r7, #44] @ 0x2c + + if (!(UART_INSTANCE_LOWPOWER(huart))) + 800599c: 697b ldr r3, [r7, #20] + 800599e: 681b ldr r3, [r3, #0] + 80059a0: 4a89 ldr r2, [pc, #548] @ (8005bc8 ) + 80059a2: 4293 cmp r3, r2 + 80059a4: d004 beq.n 80059b0 + { + tmpreg |= huart->Init.OneBitSampling; + 80059a6: 697b ldr r3, [r7, #20] + 80059a8: 6a1b ldr r3, [r3, #32] + 80059aa: 6afa ldr r2, [r7, #44] @ 0x2c + 80059ac: 4313 orrs r3, r2 + 80059ae: 62fb str r3, [r7, #44] @ 0x2c + } + MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg); + 80059b0: 697b ldr r3, [r7, #20] + 80059b2: 681b ldr r3, [r3, #0] + 80059b4: 689b ldr r3, [r3, #8] + 80059b6: f023 436e bic.w r3, r3, #3992977408 @ 0xee000000 + 80059ba: f423 6330 bic.w r3, r3, #2816 @ 0xb00 + 80059be: 697a ldr r2, [r7, #20] + 80059c0: 6812 ldr r2, [r2, #0] + 80059c2: 6af9 ldr r1, [r7, #44] @ 0x2c + 80059c4: 430b orrs r3, r1 + 80059c6: 6093 str r3, [r2, #8] + + /*-------------------------- USART PRESC Configuration -----------------------*/ + /* Configure + * - UART Clock Prescaler : set PRESCALER according to huart->Init.ClockPrescaler value */ + MODIFY_REG(huart->Instance->PRESC, USART_PRESC_PRESCALER, huart->Init.ClockPrescaler); + 80059c8: 697b ldr r3, [r7, #20] + 80059ca: 681b ldr r3, [r3, #0] + 80059cc: 6adb ldr r3, [r3, #44] @ 0x2c + 80059ce: f023 010f bic.w r1, r3, #15 + 80059d2: 697b ldr r3, [r7, #20] + 80059d4: 6a5a ldr r2, [r3, #36] @ 0x24 + 80059d6: 697b ldr r3, [r7, #20] + 80059d8: 681b ldr r3, [r3, #0] + 80059da: 430a orrs r2, r1 + 80059dc: 62da str r2, [r3, #44] @ 0x2c + + /*-------------------------- USART BRR Configuration -----------------------*/ + UART_GETCLOCKSOURCE(huart, clocksource); + 80059de: 697b ldr r3, [r7, #20] + 80059e0: 681b ldr r3, [r3, #0] + 80059e2: 4a7a ldr r2, [pc, #488] @ (8005bcc ) + 80059e4: 4293 cmp r3, r2 + 80059e6: d127 bne.n 8005a38 + 80059e8: 2003 movs r0, #3 + 80059ea: f7ff fb0d bl 8005008 + 80059ee: 4603 mov r3, r0 + 80059f0: f5a3 3340 sub.w r3, r3, #196608 @ 0x30000 + 80059f4: 2b03 cmp r3, #3 + 80059f6: d81b bhi.n 8005a30 + 80059f8: a201 add r2, pc, #4 @ (adr r2, 8005a00 ) + 80059fa: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 80059fe: bf00 nop + 8005a00: 08005a11 .word 0x08005a11 + 8005a04: 08005a21 .word 0x08005a21 + 8005a08: 08005a19 .word 0x08005a19 + 8005a0c: 08005a29 .word 0x08005a29 + 8005a10: 2301 movs r3, #1 + 8005a12: f887 302b strb.w r3, [r7, #43] @ 0x2b + 8005a16: e080 b.n 8005b1a + 8005a18: 2302 movs r3, #2 + 8005a1a: f887 302b strb.w r3, [r7, #43] @ 0x2b + 8005a1e: e07c b.n 8005b1a + 8005a20: 2304 movs r3, #4 + 8005a22: f887 302b strb.w r3, [r7, #43] @ 0x2b + 8005a26: e078 b.n 8005b1a + 8005a28: 2308 movs r3, #8 + 8005a2a: f887 302b strb.w r3, [r7, #43] @ 0x2b + 8005a2e: e074 b.n 8005b1a + 8005a30: 2310 movs r3, #16 + 8005a32: f887 302b strb.w r3, [r7, #43] @ 0x2b + 8005a36: e070 b.n 8005b1a + 8005a38: 697b ldr r3, [r7, #20] + 8005a3a: 681b ldr r3, [r3, #0] + 8005a3c: 4a64 ldr r2, [pc, #400] @ (8005bd0 ) + 8005a3e: 4293 cmp r3, r2 + 8005a40: d138 bne.n 8005ab4 + 8005a42: 200c movs r0, #12 + 8005a44: f7ff fae0 bl 8005008 + 8005a48: 4603 mov r3, r0 + 8005a4a: f5a3 2340 sub.w r3, r3, #786432 @ 0xc0000 + 8005a4e: 2b0c cmp r3, #12 + 8005a50: d82c bhi.n 8005aac + 8005a52: a201 add r2, pc, #4 @ (adr r2, 8005a58 ) + 8005a54: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 8005a58: 08005a8d .word 0x08005a8d + 8005a5c: 08005aad .word 0x08005aad + 8005a60: 08005aad .word 0x08005aad + 8005a64: 08005aad .word 0x08005aad + 8005a68: 08005a9d .word 0x08005a9d + 8005a6c: 08005aad .word 0x08005aad + 8005a70: 08005aad .word 0x08005aad + 8005a74: 08005aad .word 0x08005aad + 8005a78: 08005a95 .word 0x08005a95 + 8005a7c: 08005aad .word 0x08005aad + 8005a80: 08005aad .word 0x08005aad + 8005a84: 08005aad .word 0x08005aad + 8005a88: 08005aa5 .word 0x08005aa5 + 8005a8c: 2300 movs r3, #0 + 8005a8e: f887 302b strb.w r3, [r7, #43] @ 0x2b + 8005a92: e042 b.n 8005b1a + 8005a94: 2302 movs r3, #2 + 8005a96: f887 302b strb.w r3, [r7, #43] @ 0x2b + 8005a9a: e03e b.n 8005b1a + 8005a9c: 2304 movs r3, #4 + 8005a9e: f887 302b strb.w r3, [r7, #43] @ 0x2b + 8005aa2: e03a b.n 8005b1a + 8005aa4: 2308 movs r3, #8 + 8005aa6: f887 302b strb.w r3, [r7, #43] @ 0x2b + 8005aaa: e036 b.n 8005b1a + 8005aac: 2310 movs r3, #16 + 8005aae: f887 302b strb.w r3, [r7, #43] @ 0x2b + 8005ab2: e032 b.n 8005b1a + 8005ab4: 697b ldr r3, [r7, #20] + 8005ab6: 681b ldr r3, [r3, #0] + 8005ab8: 4a43 ldr r2, [pc, #268] @ (8005bc8 ) + 8005aba: 4293 cmp r3, r2 + 8005abc: d12a bne.n 8005b14 + 8005abe: f44f 6040 mov.w r0, #3072 @ 0xc00 + 8005ac2: f7ff fab3 bl 800502c + 8005ac6: 4603 mov r3, r0 + 8005ac8: f5b3 6f40 cmp.w r3, #3072 @ 0xc00 + 8005acc: d01a beq.n 8005b04 + 8005ace: f5b3 6f40 cmp.w r3, #3072 @ 0xc00 + 8005ad2: d81b bhi.n 8005b0c + 8005ad4: f5b3 6f00 cmp.w r3, #2048 @ 0x800 + 8005ad8: d00c beq.n 8005af4 + 8005ada: f5b3 6f00 cmp.w r3, #2048 @ 0x800 + 8005ade: d815 bhi.n 8005b0c + 8005ae0: 2b00 cmp r3, #0 + 8005ae2: d003 beq.n 8005aec + 8005ae4: f5b3 6f80 cmp.w r3, #1024 @ 0x400 + 8005ae8: d008 beq.n 8005afc + 8005aea: e00f b.n 8005b0c + 8005aec: 2300 movs r3, #0 + 8005aee: f887 302b strb.w r3, [r7, #43] @ 0x2b + 8005af2: e012 b.n 8005b1a + 8005af4: 2302 movs r3, #2 + 8005af6: f887 302b strb.w r3, [r7, #43] @ 0x2b + 8005afa: e00e b.n 8005b1a + 8005afc: 2304 movs r3, #4 + 8005afe: f887 302b strb.w r3, [r7, #43] @ 0x2b + 8005b02: e00a b.n 8005b1a + 8005b04: 2308 movs r3, #8 + 8005b06: f887 302b strb.w r3, [r7, #43] @ 0x2b + 8005b0a: e006 b.n 8005b1a + 8005b0c: 2310 movs r3, #16 + 8005b0e: f887 302b strb.w r3, [r7, #43] @ 0x2b + 8005b12: e002 b.n 8005b1a + 8005b14: 2310 movs r3, #16 + 8005b16: f887 302b strb.w r3, [r7, #43] @ 0x2b + + /* Check LPUART instance */ + if (UART_INSTANCE_LOWPOWER(huart)) + 8005b1a: 697b ldr r3, [r7, #20] + 8005b1c: 681b ldr r3, [r3, #0] + 8005b1e: 4a2a ldr r2, [pc, #168] @ (8005bc8 ) + 8005b20: 4293 cmp r3, r2 + 8005b22: f040 80a4 bne.w 8005c6e + { + /* Retrieve frequency clock */ + switch (clocksource) + 8005b26: f897 302b ldrb.w r3, [r7, #43] @ 0x2b + 8005b2a: 2b08 cmp r3, #8 + 8005b2c: d823 bhi.n 8005b76 + 8005b2e: a201 add r2, pc, #4 @ (adr r2, 8005b34 ) + 8005b30: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 8005b34: 08005b59 .word 0x08005b59 + 8005b38: 08005b77 .word 0x08005b77 + 8005b3c: 08005b61 .word 0x08005b61 + 8005b40: 08005b77 .word 0x08005b77 + 8005b44: 08005b67 .word 0x08005b67 + 8005b48: 08005b77 .word 0x08005b77 + 8005b4c: 08005b77 .word 0x08005b77 + 8005b50: 08005b77 .word 0x08005b77 + 8005b54: 08005b6f .word 0x08005b6f + { + case UART_CLOCKSOURCE_PCLK1: + pclk = HAL_RCC_GetPCLK1Freq(); + 8005b58: f7fd ff10 bl 800397c + 8005b5c: 6278 str r0, [r7, #36] @ 0x24 + break; + 8005b5e: e010 b.n 8005b82 + case UART_CLOCKSOURCE_HSI: + pclk = (uint32_t) HSI_VALUE; + 8005b60: 4b1c ldr r3, [pc, #112] @ (8005bd4 ) + 8005b62: 627b str r3, [r7, #36] @ 0x24 + break; + 8005b64: e00d b.n 8005b82 + case UART_CLOCKSOURCE_SYSCLK: + pclk = HAL_RCC_GetSysClockFreq(); + 8005b66: f7fd fe55 bl 8003814 + 8005b6a: 6278 str r0, [r7, #36] @ 0x24 + break; + 8005b6c: e009 b.n 8005b82 + case UART_CLOCKSOURCE_LSE: + pclk = (uint32_t) LSE_VALUE; + 8005b6e: f44f 4300 mov.w r3, #32768 @ 0x8000 + 8005b72: 627b str r3, [r7, #36] @ 0x24 + break; + 8005b74: e005 b.n 8005b82 + default: + pclk = 0U; + 8005b76: 2300 movs r3, #0 + 8005b78: 627b str r3, [r7, #36] @ 0x24 + ret = HAL_ERROR; + 8005b7a: 2301 movs r3, #1 + 8005b7c: f887 302a strb.w r3, [r7, #42] @ 0x2a + break; + 8005b80: bf00 nop + } + + /* If proper clock source reported */ + if (pclk != 0U) + 8005b82: 6a7b ldr r3, [r7, #36] @ 0x24 + 8005b84: 2b00 cmp r3, #0 + 8005b86: f000 8137 beq.w 8005df8 + { + /* Compute clock after Prescaler */ + lpuart_ker_ck_pres = (pclk / UARTPrescTable[huart->Init.ClockPrescaler]); + 8005b8a: 697b ldr r3, [r7, #20] + 8005b8c: 6a5b ldr r3, [r3, #36] @ 0x24 + 8005b8e: 4a12 ldr r2, [pc, #72] @ (8005bd8 ) + 8005b90: f832 3013 ldrh.w r3, [r2, r3, lsl #1] + 8005b94: 461a mov r2, r3 + 8005b96: 6a7b ldr r3, [r7, #36] @ 0x24 + 8005b98: fbb3 f3f2 udiv r3, r3, r2 + 8005b9c: 61bb str r3, [r7, #24] + + /* Ensure that Frequency clock is in the range [3 * baudrate, 4096 * baudrate] */ + if ((lpuart_ker_ck_pres < (3U * huart->Init.BaudRate)) || + 8005b9e: 697b ldr r3, [r7, #20] + 8005ba0: 685a ldr r2, [r3, #4] + 8005ba2: 4613 mov r3, r2 + 8005ba4: 005b lsls r3, r3, #1 + 8005ba6: 4413 add r3, r2 + 8005ba8: 69ba ldr r2, [r7, #24] + 8005baa: 429a cmp r2, r3 + 8005bac: d305 bcc.n 8005bba + (lpuart_ker_ck_pres > (4096U * huart->Init.BaudRate))) + 8005bae: 697b ldr r3, [r7, #20] + 8005bb0: 685b ldr r3, [r3, #4] + 8005bb2: 031b lsls r3, r3, #12 + if ((lpuart_ker_ck_pres < (3U * huart->Init.BaudRate)) || + 8005bb4: 69ba ldr r2, [r7, #24] + 8005bb6: 429a cmp r2, r3 + 8005bb8: d910 bls.n 8005bdc + { + ret = HAL_ERROR; + 8005bba: 2301 movs r3, #1 + 8005bbc: f887 302a strb.w r3, [r7, #42] @ 0x2a + 8005bc0: e11a b.n 8005df8 + 8005bc2: bf00 nop + 8005bc4: cfff69f3 .word 0xcfff69f3 + 8005bc8: 40008000 .word 0x40008000 + 8005bcc: 40013800 .word 0x40013800 + 8005bd0: 40004400 .word 0x40004400 + 8005bd4: 00f42400 .word 0x00f42400 + 8005bd8: 0800d9b8 .word 0x0800d9b8 + } + else + { + /* Check computed UsartDiv value is in allocated range + (it is forbidden to write values lower than 0x300 in the LPUART_BRR register) */ + usartdiv = (uint32_t)(UART_DIV_LPUART(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); + 8005bdc: 6a7b ldr r3, [r7, #36] @ 0x24 + 8005bde: 2200 movs r2, #0 + 8005be0: 60bb str r3, [r7, #8] + 8005be2: 60fa str r2, [r7, #12] + 8005be4: 697b ldr r3, [r7, #20] + 8005be6: 6a5b ldr r3, [r3, #36] @ 0x24 + 8005be8: 4a8e ldr r2, [pc, #568] @ (8005e24 ) + 8005bea: f832 3013 ldrh.w r3, [r2, r3, lsl #1] + 8005bee: b29b uxth r3, r3 + 8005bf0: 2200 movs r2, #0 + 8005bf2: 603b str r3, [r7, #0] + 8005bf4: 607a str r2, [r7, #4] + 8005bf6: e9d7 2300 ldrd r2, r3, [r7] + 8005bfa: e9d7 0102 ldrd r0, r1, [r7, #8] + 8005bfe: f7fa fac3 bl 8000188 <__aeabi_uldivmod> + 8005c02: 4602 mov r2, r0 + 8005c04: 460b mov r3, r1 + 8005c06: 4610 mov r0, r2 + 8005c08: 4619 mov r1, r3 + 8005c0a: f04f 0200 mov.w r2, #0 + 8005c0e: f04f 0300 mov.w r3, #0 + 8005c12: 020b lsls r3, r1, #8 + 8005c14: ea43 6310 orr.w r3, r3, r0, lsr #24 + 8005c18: 0202 lsls r2, r0, #8 + 8005c1a: 6979 ldr r1, [r7, #20] + 8005c1c: 6849 ldr r1, [r1, #4] + 8005c1e: 0849 lsrs r1, r1, #1 + 8005c20: 2000 movs r0, #0 + 8005c22: 460c mov r4, r1 + 8005c24: 4605 mov r5, r0 + 8005c26: eb12 0804 adds.w r8, r2, r4 + 8005c2a: eb43 0905 adc.w r9, r3, r5 + 8005c2e: 697b ldr r3, [r7, #20] + 8005c30: 685b ldr r3, [r3, #4] + 8005c32: 2200 movs r2, #0 + 8005c34: 469a mov sl, r3 + 8005c36: 4693 mov fp, r2 + 8005c38: 4652 mov r2, sl + 8005c3a: 465b mov r3, fp + 8005c3c: 4640 mov r0, r8 + 8005c3e: 4649 mov r1, r9 + 8005c40: f7fa faa2 bl 8000188 <__aeabi_uldivmod> + 8005c44: 4602 mov r2, r0 + 8005c46: 460b mov r3, r1 + 8005c48: 4613 mov r3, r2 + 8005c4a: 623b str r3, [r7, #32] + if ((usartdiv >= LPUART_BRR_MIN) && (usartdiv <= LPUART_BRR_MAX)) + 8005c4c: 6a3b ldr r3, [r7, #32] + 8005c4e: f5b3 7f40 cmp.w r3, #768 @ 0x300 + 8005c52: d308 bcc.n 8005c66 + 8005c54: 6a3b ldr r3, [r7, #32] + 8005c56: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 + 8005c5a: d204 bcs.n 8005c66 + { + huart->Instance->BRR = usartdiv; + 8005c5c: 697b ldr r3, [r7, #20] + 8005c5e: 681b ldr r3, [r3, #0] + 8005c60: 6a3a ldr r2, [r7, #32] + 8005c62: 60da str r2, [r3, #12] + 8005c64: e0c8 b.n 8005df8 + } + else + { + ret = HAL_ERROR; + 8005c66: 2301 movs r3, #1 + 8005c68: f887 302a strb.w r3, [r7, #42] @ 0x2a + 8005c6c: e0c4 b.n 8005df8 + } /* if ( (lpuart_ker_ck_pres < (3 * huart->Init.BaudRate) ) || + (lpuart_ker_ck_pres > (4096 * huart->Init.BaudRate) )) */ + } /* if (pclk != 0) */ + } + /* Check UART Over Sampling to set Baud Rate Register */ + else if (huart->Init.OverSampling == UART_OVERSAMPLING_8) + 8005c6e: 697b ldr r3, [r7, #20] + 8005c70: 69db ldr r3, [r3, #28] + 8005c72: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 + 8005c76: d167 bne.n 8005d48 + { + switch (clocksource) + 8005c78: f897 302b ldrb.w r3, [r7, #43] @ 0x2b + 8005c7c: 2b08 cmp r3, #8 + 8005c7e: d828 bhi.n 8005cd2 + 8005c80: a201 add r2, pc, #4 @ (adr r2, 8005c88 ) + 8005c82: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 8005c86: bf00 nop + 8005c88: 08005cad .word 0x08005cad + 8005c8c: 08005cb5 .word 0x08005cb5 + 8005c90: 08005cbd .word 0x08005cbd + 8005c94: 08005cd3 .word 0x08005cd3 + 8005c98: 08005cc3 .word 0x08005cc3 + 8005c9c: 08005cd3 .word 0x08005cd3 + 8005ca0: 08005cd3 .word 0x08005cd3 + 8005ca4: 08005cd3 .word 0x08005cd3 + 8005ca8: 08005ccb .word 0x08005ccb + { + case UART_CLOCKSOURCE_PCLK1: + pclk = HAL_RCC_GetPCLK1Freq(); + 8005cac: f7fd fe66 bl 800397c + 8005cb0: 6278 str r0, [r7, #36] @ 0x24 + break; + 8005cb2: e014 b.n 8005cde + case UART_CLOCKSOURCE_PCLK2: + pclk = HAL_RCC_GetPCLK2Freq(); + 8005cb4: f7fd fe74 bl 80039a0 + 8005cb8: 6278 str r0, [r7, #36] @ 0x24 + break; + 8005cba: e010 b.n 8005cde + case UART_CLOCKSOURCE_HSI: + pclk = (uint32_t) HSI_VALUE; + 8005cbc: 4b5a ldr r3, [pc, #360] @ (8005e28 ) + 8005cbe: 627b str r3, [r7, #36] @ 0x24 + break; + 8005cc0: e00d b.n 8005cde + case UART_CLOCKSOURCE_SYSCLK: + pclk = HAL_RCC_GetSysClockFreq(); + 8005cc2: f7fd fda7 bl 8003814 + 8005cc6: 6278 str r0, [r7, #36] @ 0x24 + break; + 8005cc8: e009 b.n 8005cde + case UART_CLOCKSOURCE_LSE: + pclk = (uint32_t) LSE_VALUE; + 8005cca: f44f 4300 mov.w r3, #32768 @ 0x8000 + 8005cce: 627b str r3, [r7, #36] @ 0x24 + break; + 8005cd0: e005 b.n 8005cde + default: + pclk = 0U; + 8005cd2: 2300 movs r3, #0 + 8005cd4: 627b str r3, [r7, #36] @ 0x24 + ret = HAL_ERROR; + 8005cd6: 2301 movs r3, #1 + 8005cd8: f887 302a strb.w r3, [r7, #42] @ 0x2a + break; + 8005cdc: bf00 nop + } + + /* USARTDIV must be greater than or equal to 0d16 */ + if (pclk != 0U) + 8005cde: 6a7b ldr r3, [r7, #36] @ 0x24 + 8005ce0: 2b00 cmp r3, #0 + 8005ce2: f000 8089 beq.w 8005df8 + { + usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); + 8005ce6: 697b ldr r3, [r7, #20] + 8005ce8: 6a5b ldr r3, [r3, #36] @ 0x24 + 8005cea: 4a4e ldr r2, [pc, #312] @ (8005e24 ) + 8005cec: f832 3013 ldrh.w r3, [r2, r3, lsl #1] + 8005cf0: 461a mov r2, r3 + 8005cf2: 6a7b ldr r3, [r7, #36] @ 0x24 + 8005cf4: fbb3 f3f2 udiv r3, r3, r2 + 8005cf8: 005a lsls r2, r3, #1 + 8005cfa: 697b ldr r3, [r7, #20] + 8005cfc: 685b ldr r3, [r3, #4] + 8005cfe: 085b lsrs r3, r3, #1 + 8005d00: 441a add r2, r3 + 8005d02: 697b ldr r3, [r7, #20] + 8005d04: 685b ldr r3, [r3, #4] + 8005d06: fbb2 f3f3 udiv r3, r2, r3 + 8005d0a: 623b str r3, [r7, #32] + if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) + 8005d0c: 6a3b ldr r3, [r7, #32] + 8005d0e: 2b0f cmp r3, #15 + 8005d10: d916 bls.n 8005d40 + 8005d12: 6a3b ldr r3, [r7, #32] + 8005d14: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 + 8005d18: d212 bcs.n 8005d40 + { + brrtemp = (uint16_t)(usartdiv & 0xFFF0U); + 8005d1a: 6a3b ldr r3, [r7, #32] + 8005d1c: b29b uxth r3, r3 + 8005d1e: f023 030f bic.w r3, r3, #15 + 8005d22: 83fb strh r3, [r7, #30] + brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); + 8005d24: 6a3b ldr r3, [r7, #32] + 8005d26: 085b lsrs r3, r3, #1 + 8005d28: b29b uxth r3, r3 + 8005d2a: f003 0307 and.w r3, r3, #7 + 8005d2e: b29a uxth r2, r3 + 8005d30: 8bfb ldrh r3, [r7, #30] + 8005d32: 4313 orrs r3, r2 + 8005d34: 83fb strh r3, [r7, #30] + huart->Instance->BRR = brrtemp; + 8005d36: 697b ldr r3, [r7, #20] + 8005d38: 681b ldr r3, [r3, #0] + 8005d3a: 8bfa ldrh r2, [r7, #30] + 8005d3c: 60da str r2, [r3, #12] + 8005d3e: e05b b.n 8005df8 + } + else + { + ret = HAL_ERROR; + 8005d40: 2301 movs r3, #1 + 8005d42: f887 302a strb.w r3, [r7, #42] @ 0x2a + 8005d46: e057 b.n 8005df8 + } + } + } + else + { + switch (clocksource) + 8005d48: f897 302b ldrb.w r3, [r7, #43] @ 0x2b + 8005d4c: 2b08 cmp r3, #8 + 8005d4e: d828 bhi.n 8005da2 + 8005d50: a201 add r2, pc, #4 @ (adr r2, 8005d58 ) + 8005d52: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 8005d56: bf00 nop + 8005d58: 08005d7d .word 0x08005d7d + 8005d5c: 08005d85 .word 0x08005d85 + 8005d60: 08005d8d .word 0x08005d8d + 8005d64: 08005da3 .word 0x08005da3 + 8005d68: 08005d93 .word 0x08005d93 + 8005d6c: 08005da3 .word 0x08005da3 + 8005d70: 08005da3 .word 0x08005da3 + 8005d74: 08005da3 .word 0x08005da3 + 8005d78: 08005d9b .word 0x08005d9b + { + case UART_CLOCKSOURCE_PCLK1: + pclk = HAL_RCC_GetPCLK1Freq(); + 8005d7c: f7fd fdfe bl 800397c + 8005d80: 6278 str r0, [r7, #36] @ 0x24 + break; + 8005d82: e014 b.n 8005dae + case UART_CLOCKSOURCE_PCLK2: + pclk = HAL_RCC_GetPCLK2Freq(); + 8005d84: f7fd fe0c bl 80039a0 + 8005d88: 6278 str r0, [r7, #36] @ 0x24 + break; + 8005d8a: e010 b.n 8005dae + case UART_CLOCKSOURCE_HSI: + pclk = (uint32_t) HSI_VALUE; + 8005d8c: 4b26 ldr r3, [pc, #152] @ (8005e28 ) + 8005d8e: 627b str r3, [r7, #36] @ 0x24 + break; + 8005d90: e00d b.n 8005dae + case UART_CLOCKSOURCE_SYSCLK: + pclk = HAL_RCC_GetSysClockFreq(); + 8005d92: f7fd fd3f bl 8003814 + 8005d96: 6278 str r0, [r7, #36] @ 0x24 + break; + 8005d98: e009 b.n 8005dae + case UART_CLOCKSOURCE_LSE: + pclk = (uint32_t) LSE_VALUE; + 8005d9a: f44f 4300 mov.w r3, #32768 @ 0x8000 + 8005d9e: 627b str r3, [r7, #36] @ 0x24 + break; + 8005da0: e005 b.n 8005dae + default: + pclk = 0U; + 8005da2: 2300 movs r3, #0 + 8005da4: 627b str r3, [r7, #36] @ 0x24 + ret = HAL_ERROR; + 8005da6: 2301 movs r3, #1 + 8005da8: f887 302a strb.w r3, [r7, #42] @ 0x2a + break; + 8005dac: bf00 nop + } + + if (pclk != 0U) + 8005dae: 6a7b ldr r3, [r7, #36] @ 0x24 + 8005db0: 2b00 cmp r3, #0 + 8005db2: d021 beq.n 8005df8 + { + /* USARTDIV must be greater than or equal to 0d16 */ + usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); + 8005db4: 697b ldr r3, [r7, #20] + 8005db6: 6a5b ldr r3, [r3, #36] @ 0x24 + 8005db8: 4a1a ldr r2, [pc, #104] @ (8005e24 ) + 8005dba: f832 3013 ldrh.w r3, [r2, r3, lsl #1] + 8005dbe: 461a mov r2, r3 + 8005dc0: 6a7b ldr r3, [r7, #36] @ 0x24 + 8005dc2: fbb3 f2f2 udiv r2, r3, r2 + 8005dc6: 697b ldr r3, [r7, #20] + 8005dc8: 685b ldr r3, [r3, #4] + 8005dca: 085b lsrs r3, r3, #1 + 8005dcc: 441a add r2, r3 + 8005dce: 697b ldr r3, [r7, #20] + 8005dd0: 685b ldr r3, [r3, #4] + 8005dd2: fbb2 f3f3 udiv r3, r2, r3 + 8005dd6: 623b str r3, [r7, #32] + if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) + 8005dd8: 6a3b ldr r3, [r7, #32] + 8005dda: 2b0f cmp r3, #15 + 8005ddc: d909 bls.n 8005df2 + 8005dde: 6a3b ldr r3, [r7, #32] + 8005de0: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 + 8005de4: d205 bcs.n 8005df2 + { + huart->Instance->BRR = (uint16_t)usartdiv; + 8005de6: 6a3b ldr r3, [r7, #32] + 8005de8: b29a uxth r2, r3 + 8005dea: 697b ldr r3, [r7, #20] + 8005dec: 681b ldr r3, [r3, #0] + 8005dee: 60da str r2, [r3, #12] + 8005df0: e002 b.n 8005df8 + } + else + { + ret = HAL_ERROR; + 8005df2: 2301 movs r3, #1 + 8005df4: f887 302a strb.w r3, [r7, #42] @ 0x2a + } + } + } + + /* Initialize the number of data to process during RX/TX ISR execution */ + huart->NbTxDataToProcess = 1; + 8005df8: 697b ldr r3, [r7, #20] + 8005dfa: 2201 movs r2, #1 + 8005dfc: f8a3 206a strh.w r2, [r3, #106] @ 0x6a + huart->NbRxDataToProcess = 1; + 8005e00: 697b ldr r3, [r7, #20] + 8005e02: 2201 movs r2, #1 + 8005e04: f8a3 2068 strh.w r2, [r3, #104] @ 0x68 + + /* Clear ISR function pointers */ + huart->RxISR = NULL; + 8005e08: 697b ldr r3, [r7, #20] + 8005e0a: 2200 movs r2, #0 + 8005e0c: 675a str r2, [r3, #116] @ 0x74 + huart->TxISR = NULL; + 8005e0e: 697b ldr r3, [r7, #20] + 8005e10: 2200 movs r2, #0 + 8005e12: 679a str r2, [r3, #120] @ 0x78 + + return ret; + 8005e14: f897 302a ldrb.w r3, [r7, #42] @ 0x2a +} + 8005e18: 4618 mov r0, r3 + 8005e1a: 3730 adds r7, #48 @ 0x30 + 8005e1c: 46bd mov sp, r7 + 8005e1e: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc} + 8005e22: bf00 nop + 8005e24: 0800d9b8 .word 0x0800d9b8 + 8005e28: 00f42400 .word 0x00f42400 + +08005e2c : + * @brief Configure the UART peripheral advanced features. + * @param huart UART handle. + * @retval None + */ +void UART_AdvFeatureConfig(UART_HandleTypeDef *huart) +{ + 8005e2c: b480 push {r7} + 8005e2e: b083 sub sp, #12 + 8005e30: af00 add r7, sp, #0 + 8005e32: 6078 str r0, [r7, #4] + /* Check whether the set of advanced features to configure is properly set */ + assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit)); + + /* if required, configure RX/TX pins swap */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT)) + 8005e34: 687b ldr r3, [r7, #4] + 8005e36: 6a9b ldr r3, [r3, #40] @ 0x28 + 8005e38: f003 0308 and.w r3, r3, #8 + 8005e3c: 2b00 cmp r3, #0 + 8005e3e: d00a beq.n 8005e56 + { + assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap); + 8005e40: 687b ldr r3, [r7, #4] + 8005e42: 681b ldr r3, [r3, #0] + 8005e44: 685b ldr r3, [r3, #4] + 8005e46: f423 4100 bic.w r1, r3, #32768 @ 0x8000 + 8005e4a: 687b ldr r3, [r7, #4] + 8005e4c: 6b9a ldr r2, [r3, #56] @ 0x38 + 8005e4e: 687b ldr r3, [r7, #4] + 8005e50: 681b ldr r3, [r3, #0] + 8005e52: 430a orrs r2, r1 + 8005e54: 605a str r2, [r3, #4] + } + + /* if required, configure TX pin active level inversion */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT)) + 8005e56: 687b ldr r3, [r7, #4] + 8005e58: 6a9b ldr r3, [r3, #40] @ 0x28 + 8005e5a: f003 0301 and.w r3, r3, #1 + 8005e5e: 2b00 cmp r3, #0 + 8005e60: d00a beq.n 8005e78 + { + assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert); + 8005e62: 687b ldr r3, [r7, #4] + 8005e64: 681b ldr r3, [r3, #0] + 8005e66: 685b ldr r3, [r3, #4] + 8005e68: f423 3100 bic.w r1, r3, #131072 @ 0x20000 + 8005e6c: 687b ldr r3, [r7, #4] + 8005e6e: 6ada ldr r2, [r3, #44] @ 0x2c + 8005e70: 687b ldr r3, [r7, #4] + 8005e72: 681b ldr r3, [r3, #0] + 8005e74: 430a orrs r2, r1 + 8005e76: 605a str r2, [r3, #4] + } + + /* if required, configure RX pin active level inversion */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT)) + 8005e78: 687b ldr r3, [r7, #4] + 8005e7a: 6a9b ldr r3, [r3, #40] @ 0x28 + 8005e7c: f003 0302 and.w r3, r3, #2 + 8005e80: 2b00 cmp r3, #0 + 8005e82: d00a beq.n 8005e9a + { + assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert); + 8005e84: 687b ldr r3, [r7, #4] + 8005e86: 681b ldr r3, [r3, #0] + 8005e88: 685b ldr r3, [r3, #4] + 8005e8a: f423 3180 bic.w r1, r3, #65536 @ 0x10000 + 8005e8e: 687b ldr r3, [r7, #4] + 8005e90: 6b1a ldr r2, [r3, #48] @ 0x30 + 8005e92: 687b ldr r3, [r7, #4] + 8005e94: 681b ldr r3, [r3, #0] + 8005e96: 430a orrs r2, r1 + 8005e98: 605a str r2, [r3, #4] + } + + /* if required, configure data inversion */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT)) + 8005e9a: 687b ldr r3, [r7, #4] + 8005e9c: 6a9b ldr r3, [r3, #40] @ 0x28 + 8005e9e: f003 0304 and.w r3, r3, #4 + 8005ea2: 2b00 cmp r3, #0 + 8005ea4: d00a beq.n 8005ebc + { + assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert); + 8005ea6: 687b ldr r3, [r7, #4] + 8005ea8: 681b ldr r3, [r3, #0] + 8005eaa: 685b ldr r3, [r3, #4] + 8005eac: f423 2180 bic.w r1, r3, #262144 @ 0x40000 + 8005eb0: 687b ldr r3, [r7, #4] + 8005eb2: 6b5a ldr r2, [r3, #52] @ 0x34 + 8005eb4: 687b ldr r3, [r7, #4] + 8005eb6: 681b ldr r3, [r3, #0] + 8005eb8: 430a orrs r2, r1 + 8005eba: 605a str r2, [r3, #4] + } + + /* if required, configure RX overrun detection disabling */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT)) + 8005ebc: 687b ldr r3, [r7, #4] + 8005ebe: 6a9b ldr r3, [r3, #40] @ 0x28 + 8005ec0: f003 0310 and.w r3, r3, #16 + 8005ec4: 2b00 cmp r3, #0 + 8005ec6: d00a beq.n 8005ede + { + assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable)); + MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable); + 8005ec8: 687b ldr r3, [r7, #4] + 8005eca: 681b ldr r3, [r3, #0] + 8005ecc: 689b ldr r3, [r3, #8] + 8005ece: f423 5180 bic.w r1, r3, #4096 @ 0x1000 + 8005ed2: 687b ldr r3, [r7, #4] + 8005ed4: 6bda ldr r2, [r3, #60] @ 0x3c + 8005ed6: 687b ldr r3, [r7, #4] + 8005ed8: 681b ldr r3, [r3, #0] + 8005eda: 430a orrs r2, r1 + 8005edc: 609a str r2, [r3, #8] + } + + /* if required, configure DMA disabling on reception error */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT)) + 8005ede: 687b ldr r3, [r7, #4] + 8005ee0: 6a9b ldr r3, [r3, #40] @ 0x28 + 8005ee2: f003 0320 and.w r3, r3, #32 + 8005ee6: 2b00 cmp r3, #0 + 8005ee8: d00a beq.n 8005f00 + { + assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError)); + MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError); + 8005eea: 687b ldr r3, [r7, #4] + 8005eec: 681b ldr r3, [r3, #0] + 8005eee: 689b ldr r3, [r3, #8] + 8005ef0: f423 5100 bic.w r1, r3, #8192 @ 0x2000 + 8005ef4: 687b ldr r3, [r7, #4] + 8005ef6: 6c1a ldr r2, [r3, #64] @ 0x40 + 8005ef8: 687b ldr r3, [r7, #4] + 8005efa: 681b ldr r3, [r3, #0] + 8005efc: 430a orrs r2, r1 + 8005efe: 609a str r2, [r3, #8] + } + + /* if required, configure auto Baud rate detection scheme */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT)) + 8005f00: 687b ldr r3, [r7, #4] + 8005f02: 6a9b ldr r3, [r3, #40] @ 0x28 + 8005f04: f003 0340 and.w r3, r3, #64 @ 0x40 + 8005f08: 2b00 cmp r3, #0 + 8005f0a: d01a beq.n 8005f42 + { + assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance)); + assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable); + 8005f0c: 687b ldr r3, [r7, #4] + 8005f0e: 681b ldr r3, [r3, #0] + 8005f10: 685b ldr r3, [r3, #4] + 8005f12: f423 1180 bic.w r1, r3, #1048576 @ 0x100000 + 8005f16: 687b ldr r3, [r7, #4] + 8005f18: 6c5a ldr r2, [r3, #68] @ 0x44 + 8005f1a: 687b ldr r3, [r7, #4] + 8005f1c: 681b ldr r3, [r3, #0] + 8005f1e: 430a orrs r2, r1 + 8005f20: 605a str r2, [r3, #4] + /* set auto Baudrate detection parameters if detection is enabled */ + if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE) + 8005f22: 687b ldr r3, [r7, #4] + 8005f24: 6c5b ldr r3, [r3, #68] @ 0x44 + 8005f26: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 + 8005f2a: d10a bne.n 8005f42 + { + assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode); + 8005f2c: 687b ldr r3, [r7, #4] + 8005f2e: 681b ldr r3, [r3, #0] + 8005f30: 685b ldr r3, [r3, #4] + 8005f32: f423 01c0 bic.w r1, r3, #6291456 @ 0x600000 + 8005f36: 687b ldr r3, [r7, #4] + 8005f38: 6c9a ldr r2, [r3, #72] @ 0x48 + 8005f3a: 687b ldr r3, [r7, #4] + 8005f3c: 681b ldr r3, [r3, #0] + 8005f3e: 430a orrs r2, r1 + 8005f40: 605a str r2, [r3, #4] + } + } + + /* if required, configure MSB first on communication line */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT)) + 8005f42: 687b ldr r3, [r7, #4] + 8005f44: 6a9b ldr r3, [r3, #40] @ 0x28 + 8005f46: f003 0380 and.w r3, r3, #128 @ 0x80 + 8005f4a: 2b00 cmp r3, #0 + 8005f4c: d00a beq.n 8005f64 + { + assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst); + 8005f4e: 687b ldr r3, [r7, #4] + 8005f50: 681b ldr r3, [r3, #0] + 8005f52: 685b ldr r3, [r3, #4] + 8005f54: f423 2100 bic.w r1, r3, #524288 @ 0x80000 + 8005f58: 687b ldr r3, [r7, #4] + 8005f5a: 6cda ldr r2, [r3, #76] @ 0x4c + 8005f5c: 687b ldr r3, [r7, #4] + 8005f5e: 681b ldr r3, [r3, #0] + 8005f60: 430a orrs r2, r1 + 8005f62: 605a str r2, [r3, #4] + } +} + 8005f64: bf00 nop + 8005f66: 370c adds r7, #12 + 8005f68: 46bd mov sp, r7 + 8005f6a: bc80 pop {r7} + 8005f6c: 4770 bx lr + +08005f6e : + * @brief Check the UART Idle State. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) +{ + 8005f6e: b580 push {r7, lr} + 8005f70: b098 sub sp, #96 @ 0x60 + 8005f72: af02 add r7, sp, #8 + 8005f74: 6078 str r0, [r7, #4] + uint32_t tickstart; + + /* Initialize the UART ErrorCode */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + 8005f76: 687b ldr r3, [r7, #4] + 8005f78: 2200 movs r2, #0 + 8005f7a: f8c3 2090 str.w r2, [r3, #144] @ 0x90 + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + 8005f7e: f7fa fdff bl 8000b80 + 8005f82: 6578 str r0, [r7, #84] @ 0x54 + + /* Check if the Transmitter is enabled */ + if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) + 8005f84: 687b ldr r3, [r7, #4] + 8005f86: 681b ldr r3, [r3, #0] + 8005f88: 681b ldr r3, [r3, #0] + 8005f8a: f003 0308 and.w r3, r3, #8 + 8005f8e: 2b08 cmp r3, #8 + 8005f90: d12f bne.n 8005ff2 + { + /* Wait until TEACK flag is set */ + if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) + 8005f92: f06f 437e mvn.w r3, #4261412864 @ 0xfe000000 + 8005f96: 9300 str r3, [sp, #0] + 8005f98: 6d7b ldr r3, [r7, #84] @ 0x54 + 8005f9a: 2200 movs r2, #0 + 8005f9c: f44f 1100 mov.w r1, #2097152 @ 0x200000 + 8005fa0: 6878 ldr r0, [r7, #4] + 8005fa2: f000 f88e bl 80060c2 + 8005fa6: 4603 mov r3, r0 + 8005fa8: 2b00 cmp r3, #0 + 8005faa: d022 beq.n 8005ff2 + { + /* Disable TXE interrupt for the interrupt process */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE)); + 8005fac: 687b ldr r3, [r7, #4] + 8005fae: 681b ldr r3, [r3, #0] + 8005fb0: 63bb str r3, [r7, #56] @ 0x38 + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 8005fb2: 6bbb ldr r3, [r7, #56] @ 0x38 + 8005fb4: e853 3f00 ldrex r3, [r3] + 8005fb8: 637b str r3, [r7, #52] @ 0x34 + return(result); + 8005fba: 6b7b ldr r3, [r7, #52] @ 0x34 + 8005fbc: f023 0380 bic.w r3, r3, #128 @ 0x80 + 8005fc0: 653b str r3, [r7, #80] @ 0x50 + 8005fc2: 687b ldr r3, [r7, #4] + 8005fc4: 681b ldr r3, [r3, #0] + 8005fc6: 461a mov r2, r3 + 8005fc8: 6d3b ldr r3, [r7, #80] @ 0x50 + 8005fca: 647b str r3, [r7, #68] @ 0x44 + 8005fcc: 643a str r2, [r7, #64] @ 0x40 + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 8005fce: 6c39 ldr r1, [r7, #64] @ 0x40 + 8005fd0: 6c7a ldr r2, [r7, #68] @ 0x44 + 8005fd2: e841 2300 strex r3, r2, [r1] + 8005fd6: 63fb str r3, [r7, #60] @ 0x3c + return(result); + 8005fd8: 6bfb ldr r3, [r7, #60] @ 0x3c + 8005fda: 2b00 cmp r3, #0 + 8005fdc: d1e6 bne.n 8005fac + + huart->gState = HAL_UART_STATE_READY; + 8005fde: 687b ldr r3, [r7, #4] + 8005fe0: 2220 movs r2, #32 + 8005fe2: f8c3 2088 str.w r2, [r3, #136] @ 0x88 + + __HAL_UNLOCK(huart); + 8005fe6: 687b ldr r3, [r7, #4] + 8005fe8: 2200 movs r2, #0 + 8005fea: f883 2084 strb.w r2, [r3, #132] @ 0x84 + + /* Timeout occurred */ + return HAL_TIMEOUT; + 8005fee: 2303 movs r3, #3 + 8005ff0: e063 b.n 80060ba + } + } + + /* Check if the Receiver is enabled */ + if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) + 8005ff2: 687b ldr r3, [r7, #4] + 8005ff4: 681b ldr r3, [r3, #0] + 8005ff6: 681b ldr r3, [r3, #0] + 8005ff8: f003 0304 and.w r3, r3, #4 + 8005ffc: 2b04 cmp r3, #4 + 8005ffe: d149 bne.n 8006094 + { + /* Wait until REACK flag is set */ + if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) + 8006000: f06f 437e mvn.w r3, #4261412864 @ 0xfe000000 + 8006004: 9300 str r3, [sp, #0] + 8006006: 6d7b ldr r3, [r7, #84] @ 0x54 + 8006008: 2200 movs r2, #0 + 800600a: f44f 0180 mov.w r1, #4194304 @ 0x400000 + 800600e: 6878 ldr r0, [r7, #4] + 8006010: f000 f857 bl 80060c2 + 8006014: 4603 mov r3, r0 + 8006016: 2b00 cmp r3, #0 + 8006018: d03c beq.n 8006094 + { + /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) + interrupts for the interrupt process */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); + 800601a: 687b ldr r3, [r7, #4] + 800601c: 681b ldr r3, [r3, #0] + 800601e: 627b str r3, [r7, #36] @ 0x24 + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 8006020: 6a7b ldr r3, [r7, #36] @ 0x24 + 8006022: e853 3f00 ldrex r3, [r3] + 8006026: 623b str r3, [r7, #32] + return(result); + 8006028: 6a3b ldr r3, [r7, #32] + 800602a: f423 7390 bic.w r3, r3, #288 @ 0x120 + 800602e: 64fb str r3, [r7, #76] @ 0x4c + 8006030: 687b ldr r3, [r7, #4] + 8006032: 681b ldr r3, [r3, #0] + 8006034: 461a mov r2, r3 + 8006036: 6cfb ldr r3, [r7, #76] @ 0x4c + 8006038: 633b str r3, [r7, #48] @ 0x30 + 800603a: 62fa str r2, [r7, #44] @ 0x2c + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 800603c: 6af9 ldr r1, [r7, #44] @ 0x2c + 800603e: 6b3a ldr r2, [r7, #48] @ 0x30 + 8006040: e841 2300 strex r3, r2, [r1] + 8006044: 62bb str r3, [r7, #40] @ 0x28 + return(result); + 8006046: 6abb ldr r3, [r7, #40] @ 0x28 + 8006048: 2b00 cmp r3, #0 + 800604a: d1e6 bne.n 800601a + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 800604c: 687b ldr r3, [r7, #4] + 800604e: 681b ldr r3, [r3, #0] + 8006050: 3308 adds r3, #8 + 8006052: 613b str r3, [r7, #16] + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 8006054: 693b ldr r3, [r7, #16] + 8006056: e853 3f00 ldrex r3, [r3] + 800605a: 60fb str r3, [r7, #12] + return(result); + 800605c: 68fb ldr r3, [r7, #12] + 800605e: f023 0301 bic.w r3, r3, #1 + 8006062: 64bb str r3, [r7, #72] @ 0x48 + 8006064: 687b ldr r3, [r7, #4] + 8006066: 681b ldr r3, [r3, #0] + 8006068: 3308 adds r3, #8 + 800606a: 6cba ldr r2, [r7, #72] @ 0x48 + 800606c: 61fa str r2, [r7, #28] + 800606e: 61bb str r3, [r7, #24] + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 8006070: 69b9 ldr r1, [r7, #24] + 8006072: 69fa ldr r2, [r7, #28] + 8006074: e841 2300 strex r3, r2, [r1] + 8006078: 617b str r3, [r7, #20] + return(result); + 800607a: 697b ldr r3, [r7, #20] + 800607c: 2b00 cmp r3, #0 + 800607e: d1e5 bne.n 800604c + + huart->RxState = HAL_UART_STATE_READY; + 8006080: 687b ldr r3, [r7, #4] + 8006082: 2220 movs r2, #32 + 8006084: f8c3 208c str.w r2, [r3, #140] @ 0x8c + + __HAL_UNLOCK(huart); + 8006088: 687b ldr r3, [r7, #4] + 800608a: 2200 movs r2, #0 + 800608c: f883 2084 strb.w r2, [r3, #132] @ 0x84 + + /* Timeout occurred */ + return HAL_TIMEOUT; + 8006090: 2303 movs r3, #3 + 8006092: e012 b.n 80060ba + } + } + + /* Initialize the UART State */ + huart->gState = HAL_UART_STATE_READY; + 8006094: 687b ldr r3, [r7, #4] + 8006096: 2220 movs r2, #32 + 8006098: f8c3 2088 str.w r2, [r3, #136] @ 0x88 + huart->RxState = HAL_UART_STATE_READY; + 800609c: 687b ldr r3, [r7, #4] + 800609e: 2220 movs r2, #32 + 80060a0: f8c3 208c str.w r2, [r3, #140] @ 0x8c + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + 80060a4: 687b ldr r3, [r7, #4] + 80060a6: 2200 movs r2, #0 + 80060a8: 66da str r2, [r3, #108] @ 0x6c + huart->RxEventType = HAL_UART_RXEVENT_TC; + 80060aa: 687b ldr r3, [r7, #4] + 80060ac: 2200 movs r2, #0 + 80060ae: 671a str r2, [r3, #112] @ 0x70 + + __HAL_UNLOCK(huart); + 80060b0: 687b ldr r3, [r7, #4] + 80060b2: 2200 movs r2, #0 + 80060b4: f883 2084 strb.w r2, [r3, #132] @ 0x84 + + return HAL_OK; + 80060b8: 2300 movs r3, #0 +} + 80060ba: 4618 mov r0, r3 + 80060bc: 3758 adds r7, #88 @ 0x58 + 80060be: 46bd mov sp, r7 + 80060c0: bd80 pop {r7, pc} + +080060c2 : + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, + uint32_t Tickstart, uint32_t Timeout) +{ + 80060c2: b580 push {r7, lr} + 80060c4: b084 sub sp, #16 + 80060c6: af00 add r7, sp, #0 + 80060c8: 60f8 str r0, [r7, #12] + 80060ca: 60b9 str r1, [r7, #8] + 80060cc: 603b str r3, [r7, #0] + 80060ce: 4613 mov r3, r2 + 80060d0: 71fb strb r3, [r7, #7] + /* Wait until flag is set */ + while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) + 80060d2: e04f b.n 8006174 + { + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + 80060d4: 69bb ldr r3, [r7, #24] + 80060d6: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff + 80060da: d04b beq.n 8006174 + { + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + 80060dc: f7fa fd50 bl 8000b80 + 80060e0: 4602 mov r2, r0 + 80060e2: 683b ldr r3, [r7, #0] + 80060e4: 1ad3 subs r3, r2, r3 + 80060e6: 69ba ldr r2, [r7, #24] + 80060e8: 429a cmp r2, r3 + 80060ea: d302 bcc.n 80060f2 + 80060ec: 69bb ldr r3, [r7, #24] + 80060ee: 2b00 cmp r3, #0 + 80060f0: d101 bne.n 80060f6 + { + + return HAL_TIMEOUT; + 80060f2: 2303 movs r3, #3 + 80060f4: e04e b.n 8006194 + } + + if ((READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) && (Flag != UART_FLAG_TXE) && (Flag != UART_FLAG_TC)) + 80060f6: 68fb ldr r3, [r7, #12] + 80060f8: 681b ldr r3, [r3, #0] + 80060fa: 681b ldr r3, [r3, #0] + 80060fc: f003 0304 and.w r3, r3, #4 + 8006100: 2b00 cmp r3, #0 + 8006102: d037 beq.n 8006174 + 8006104: 68bb ldr r3, [r7, #8] + 8006106: 2b80 cmp r3, #128 @ 0x80 + 8006108: d034 beq.n 8006174 + 800610a: 68bb ldr r3, [r7, #8] + 800610c: 2b40 cmp r3, #64 @ 0x40 + 800610e: d031 beq.n 8006174 + { + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET) + 8006110: 68fb ldr r3, [r7, #12] + 8006112: 681b ldr r3, [r3, #0] + 8006114: 69db ldr r3, [r3, #28] + 8006116: f003 0308 and.w r3, r3, #8 + 800611a: 2b08 cmp r3, #8 + 800611c: d110 bne.n 8006140 + { + /* Clear Overrun Error flag*/ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); + 800611e: 68fb ldr r3, [r7, #12] + 8006120: 681b ldr r3, [r3, #0] + 8006122: 2208 movs r2, #8 + 8006124: 621a str r2, [r3, #32] + + /* Blocking error : transfer is aborted + Set the UART state ready to be able to start again the process, + Disable Rx Interrupts if ongoing */ + UART_EndRxTransfer(huart); + 8006126: 68f8 ldr r0, [r7, #12] + 8006128: f000 f998 bl 800645c + + huart->ErrorCode = HAL_UART_ERROR_ORE; + 800612c: 68fb ldr r3, [r7, #12] + 800612e: 2208 movs r2, #8 + 8006130: f8c3 2090 str.w r2, [r3, #144] @ 0x90 + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + 8006134: 68fb ldr r3, [r7, #12] + 8006136: 2200 movs r2, #0 + 8006138: f883 2084 strb.w r2, [r3, #132] @ 0x84 + + return HAL_ERROR; + 800613c: 2301 movs r3, #1 + 800613e: e029 b.n 8006194 + } + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET) + 8006140: 68fb ldr r3, [r7, #12] + 8006142: 681b ldr r3, [r3, #0] + 8006144: 69db ldr r3, [r3, #28] + 8006146: f403 6300 and.w r3, r3, #2048 @ 0x800 + 800614a: f5b3 6f00 cmp.w r3, #2048 @ 0x800 + 800614e: d111 bne.n 8006174 + { + /* Clear Receiver Timeout flag*/ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF); + 8006150: 68fb ldr r3, [r7, #12] + 8006152: 681b ldr r3, [r3, #0] + 8006154: f44f 6200 mov.w r2, #2048 @ 0x800 + 8006158: 621a str r2, [r3, #32] + + /* Blocking error : transfer is aborted + Set the UART state ready to be able to start again the process, + Disable Rx Interrupts if ongoing */ + UART_EndRxTransfer(huart); + 800615a: 68f8 ldr r0, [r7, #12] + 800615c: f000 f97e bl 800645c + + huart->ErrorCode = HAL_UART_ERROR_RTO; + 8006160: 68fb ldr r3, [r7, #12] + 8006162: 2220 movs r2, #32 + 8006164: f8c3 2090 str.w r2, [r3, #144] @ 0x90 + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + 8006168: 68fb ldr r3, [r7, #12] + 800616a: 2200 movs r2, #0 + 800616c: f883 2084 strb.w r2, [r3, #132] @ 0x84 + + return HAL_TIMEOUT; + 8006170: 2303 movs r3, #3 + 8006172: e00f b.n 8006194 + while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) + 8006174: 68fb ldr r3, [r7, #12] + 8006176: 681b ldr r3, [r3, #0] + 8006178: 69da ldr r2, [r3, #28] + 800617a: 68bb ldr r3, [r7, #8] + 800617c: 4013 ands r3, r2 + 800617e: 68ba ldr r2, [r7, #8] + 8006180: 429a cmp r2, r3 + 8006182: bf0c ite eq + 8006184: 2301 moveq r3, #1 + 8006186: 2300 movne r3, #0 + 8006188: b2db uxtb r3, r3 + 800618a: 461a mov r2, r3 + 800618c: 79fb ldrb r3, [r7, #7] + 800618e: 429a cmp r2, r3 + 8006190: d0a0 beq.n 80060d4 + } + } + } + } + return HAL_OK; + 8006192: 2300 movs r3, #0 +} + 8006194: 4618 mov r0, r3 + 8006196: 3710 adds r7, #16 + 8006198: 46bd mov sp, r7 + 800619a: bd80 pop {r7, pc} + +0800619c : + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. + * @retval HAL status + */ +HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + 800619c: b480 push {r7} + 800619e: b0a3 sub sp, #140 @ 0x8c + 80061a0: af00 add r7, sp, #0 + 80061a2: 60f8 str r0, [r7, #12] + 80061a4: 60b9 str r1, [r7, #8] + 80061a6: 4613 mov r3, r2 + 80061a8: 80fb strh r3, [r7, #6] + huart->pRxBuffPtr = pData; + 80061aa: 68fb ldr r3, [r7, #12] + 80061ac: 68ba ldr r2, [r7, #8] + 80061ae: 659a str r2, [r3, #88] @ 0x58 + huart->RxXferSize = Size; + 80061b0: 68fb ldr r3, [r7, #12] + 80061b2: 88fa ldrh r2, [r7, #6] + 80061b4: f8a3 205c strh.w r2, [r3, #92] @ 0x5c + huart->RxXferCount = Size; + 80061b8: 68fb ldr r3, [r7, #12] + 80061ba: 88fa ldrh r2, [r7, #6] + 80061bc: f8a3 205e strh.w r2, [r3, #94] @ 0x5e + huart->RxISR = NULL; + 80061c0: 68fb ldr r3, [r7, #12] + 80061c2: 2200 movs r2, #0 + 80061c4: 675a str r2, [r3, #116] @ 0x74 + + /* Computation of UART mask to apply to RDR register */ + UART_MASK_COMPUTATION(huart); + 80061c6: 68fb ldr r3, [r7, #12] + 80061c8: 689b ldr r3, [r3, #8] + 80061ca: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 + 80061ce: d10e bne.n 80061ee + 80061d0: 68fb ldr r3, [r7, #12] + 80061d2: 691b ldr r3, [r3, #16] + 80061d4: 2b00 cmp r3, #0 + 80061d6: d105 bne.n 80061e4 + 80061d8: 68fb ldr r3, [r7, #12] + 80061da: f240 12ff movw r2, #511 @ 0x1ff + 80061de: f8a3 2060 strh.w r2, [r3, #96] @ 0x60 + 80061e2: e02d b.n 8006240 + 80061e4: 68fb ldr r3, [r7, #12] + 80061e6: 22ff movs r2, #255 @ 0xff + 80061e8: f8a3 2060 strh.w r2, [r3, #96] @ 0x60 + 80061ec: e028 b.n 8006240 + 80061ee: 68fb ldr r3, [r7, #12] + 80061f0: 689b ldr r3, [r3, #8] + 80061f2: 2b00 cmp r3, #0 + 80061f4: d10d bne.n 8006212 + 80061f6: 68fb ldr r3, [r7, #12] + 80061f8: 691b ldr r3, [r3, #16] + 80061fa: 2b00 cmp r3, #0 + 80061fc: d104 bne.n 8006208 + 80061fe: 68fb ldr r3, [r7, #12] + 8006200: 22ff movs r2, #255 @ 0xff + 8006202: f8a3 2060 strh.w r2, [r3, #96] @ 0x60 + 8006206: e01b b.n 8006240 + 8006208: 68fb ldr r3, [r7, #12] + 800620a: 227f movs r2, #127 @ 0x7f + 800620c: f8a3 2060 strh.w r2, [r3, #96] @ 0x60 + 8006210: e016 b.n 8006240 + 8006212: 68fb ldr r3, [r7, #12] + 8006214: 689b ldr r3, [r3, #8] + 8006216: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 + 800621a: d10d bne.n 8006238 + 800621c: 68fb ldr r3, [r7, #12] + 800621e: 691b ldr r3, [r3, #16] + 8006220: 2b00 cmp r3, #0 + 8006222: d104 bne.n 800622e + 8006224: 68fb ldr r3, [r7, #12] + 8006226: 227f movs r2, #127 @ 0x7f + 8006228: f8a3 2060 strh.w r2, [r3, #96] @ 0x60 + 800622c: e008 b.n 8006240 + 800622e: 68fb ldr r3, [r7, #12] + 8006230: 223f movs r2, #63 @ 0x3f + 8006232: f8a3 2060 strh.w r2, [r3, #96] @ 0x60 + 8006236: e003 b.n 8006240 + 8006238: 68fb ldr r3, [r7, #12] + 800623a: 2200 movs r2, #0 + 800623c: f8a3 2060 strh.w r2, [r3, #96] @ 0x60 + + huart->ErrorCode = HAL_UART_ERROR_NONE; + 8006240: 68fb ldr r3, [r7, #12] + 8006242: 2200 movs r2, #0 + 8006244: f8c3 2090 str.w r2, [r3, #144] @ 0x90 + huart->RxState = HAL_UART_STATE_BUSY_RX; + 8006248: 68fb ldr r3, [r7, #12] + 800624a: 2222 movs r2, #34 @ 0x22 + 800624c: f8c3 208c str.w r2, [r3, #140] @ 0x8c + + /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE); + 8006250: 68fb ldr r3, [r7, #12] + 8006252: 681b ldr r3, [r3, #0] + 8006254: 3308 adds r3, #8 + 8006256: 667b str r3, [r7, #100] @ 0x64 + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 8006258: 6e7b ldr r3, [r7, #100] @ 0x64 + 800625a: e853 3f00 ldrex r3, [r3] + 800625e: 663b str r3, [r7, #96] @ 0x60 + return(result); + 8006260: 6e3b ldr r3, [r7, #96] @ 0x60 + 8006262: f043 0301 orr.w r3, r3, #1 + 8006266: f8c7 3084 str.w r3, [r7, #132] @ 0x84 + 800626a: 68fb ldr r3, [r7, #12] + 800626c: 681b ldr r3, [r3, #0] + 800626e: 3308 adds r3, #8 + 8006270: f8d7 2084 ldr.w r2, [r7, #132] @ 0x84 + 8006274: 673a str r2, [r7, #112] @ 0x70 + 8006276: 66fb str r3, [r7, #108] @ 0x6c + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 8006278: 6ef9 ldr r1, [r7, #108] @ 0x6c + 800627a: 6f3a ldr r2, [r7, #112] @ 0x70 + 800627c: e841 2300 strex r3, r2, [r1] + 8006280: 66bb str r3, [r7, #104] @ 0x68 + return(result); + 8006282: 6ebb ldr r3, [r7, #104] @ 0x68 + 8006284: 2b00 cmp r3, #0 + 8006286: d1e3 bne.n 8006250 + + /* Configure Rx interrupt processing */ + if ((huart->FifoMode == UART_FIFOMODE_ENABLE) && (Size >= huart->NbRxDataToProcess)) + 8006288: 68fb ldr r3, [r7, #12] + 800628a: 6e5b ldr r3, [r3, #100] @ 0x64 + 800628c: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 + 8006290: d14f bne.n 8006332 + 8006292: 68fb ldr r3, [r7, #12] + 8006294: f8b3 3068 ldrh.w r3, [r3, #104] @ 0x68 + 8006298: 88fa ldrh r2, [r7, #6] + 800629a: 429a cmp r2, r3 + 800629c: d349 bcc.n 8006332 + { + /* Set the Rx ISR function pointer according to the data word length */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + 800629e: 68fb ldr r3, [r7, #12] + 80062a0: 689b ldr r3, [r3, #8] + 80062a2: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 + 80062a6: d107 bne.n 80062b8 + 80062a8: 68fb ldr r3, [r7, #12] + 80062aa: 691b ldr r3, [r3, #16] + 80062ac: 2b00 cmp r3, #0 + 80062ae: d103 bne.n 80062b8 + { + huart->RxISR = UART_RxISR_16BIT_FIFOEN; + 80062b0: 68fb ldr r3, [r7, #12] + 80062b2: 4a46 ldr r2, [pc, #280] @ (80063cc ) + 80062b4: 675a str r2, [r3, #116] @ 0x74 + 80062b6: e002 b.n 80062be + } + else + { + huart->RxISR = UART_RxISR_8BIT_FIFOEN; + 80062b8: 68fb ldr r3, [r7, #12] + 80062ba: 4a45 ldr r2, [pc, #276] @ (80063d0 ) + 80062bc: 675a str r2, [r3, #116] @ 0x74 + } + + /* Enable the UART Parity Error interrupt and RX FIFO Threshold interrupt */ + if (huart->Init.Parity != UART_PARITY_NONE) + 80062be: 68fb ldr r3, [r7, #12] + 80062c0: 691b ldr r3, [r3, #16] + 80062c2: 2b00 cmp r3, #0 + 80062c4: d01a beq.n 80062fc + { + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); + 80062c6: 68fb ldr r3, [r7, #12] + 80062c8: 681b ldr r3, [r3, #0] + 80062ca: 653b str r3, [r7, #80] @ 0x50 + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 80062cc: 6d3b ldr r3, [r7, #80] @ 0x50 + 80062ce: e853 3f00 ldrex r3, [r3] + 80062d2: 64fb str r3, [r7, #76] @ 0x4c + return(result); + 80062d4: 6cfb ldr r3, [r7, #76] @ 0x4c + 80062d6: f443 7380 orr.w r3, r3, #256 @ 0x100 + 80062da: f8c7 3080 str.w r3, [r7, #128] @ 0x80 + 80062de: 68fb ldr r3, [r7, #12] + 80062e0: 681b ldr r3, [r3, #0] + 80062e2: 461a mov r2, r3 + 80062e4: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80 + 80062e8: 65fb str r3, [r7, #92] @ 0x5c + 80062ea: 65ba str r2, [r7, #88] @ 0x58 + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 80062ec: 6db9 ldr r1, [r7, #88] @ 0x58 + 80062ee: 6dfa ldr r2, [r7, #92] @ 0x5c + 80062f0: e841 2300 strex r3, r2, [r1] + 80062f4: 657b str r3, [r7, #84] @ 0x54 + return(result); + 80062f6: 6d7b ldr r3, [r7, #84] @ 0x54 + 80062f8: 2b00 cmp r3, #0 + 80062fa: d1e4 bne.n 80062c6 + } + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); + 80062fc: 68fb ldr r3, [r7, #12] + 80062fe: 681b ldr r3, [r3, #0] + 8006300: 3308 adds r3, #8 + 8006302: 63fb str r3, [r7, #60] @ 0x3c + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 8006304: 6bfb ldr r3, [r7, #60] @ 0x3c + 8006306: e853 3f00 ldrex r3, [r3] + 800630a: 63bb str r3, [r7, #56] @ 0x38 + return(result); + 800630c: 6bbb ldr r3, [r7, #56] @ 0x38 + 800630e: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 + 8006312: 67fb str r3, [r7, #124] @ 0x7c + 8006314: 68fb ldr r3, [r7, #12] + 8006316: 681b ldr r3, [r3, #0] + 8006318: 3308 adds r3, #8 + 800631a: 6ffa ldr r2, [r7, #124] @ 0x7c + 800631c: 64ba str r2, [r7, #72] @ 0x48 + 800631e: 647b str r3, [r7, #68] @ 0x44 + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 8006320: 6c79 ldr r1, [r7, #68] @ 0x44 + 8006322: 6cba ldr r2, [r7, #72] @ 0x48 + 8006324: e841 2300 strex r3, r2, [r1] + 8006328: 643b str r3, [r7, #64] @ 0x40 + return(result); + 800632a: 6c3b ldr r3, [r7, #64] @ 0x40 + 800632c: 2b00 cmp r3, #0 + 800632e: d1e5 bne.n 80062fc + 8006330: e046 b.n 80063c0 + } + else + { + /* Set the Rx ISR function pointer according to the data word length */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + 8006332: 68fb ldr r3, [r7, #12] + 8006334: 689b ldr r3, [r3, #8] + 8006336: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 + 800633a: d107 bne.n 800634c + 800633c: 68fb ldr r3, [r7, #12] + 800633e: 691b ldr r3, [r3, #16] + 8006340: 2b00 cmp r3, #0 + 8006342: d103 bne.n 800634c + { + huart->RxISR = UART_RxISR_16BIT; + 8006344: 68fb ldr r3, [r7, #12] + 8006346: 4a23 ldr r2, [pc, #140] @ (80063d4 ) + 8006348: 675a str r2, [r3, #116] @ 0x74 + 800634a: e002 b.n 8006352 + } + else + { + huart->RxISR = UART_RxISR_8BIT; + 800634c: 68fb ldr r3, [r7, #12] + 800634e: 4a22 ldr r2, [pc, #136] @ (80063d8 ) + 8006350: 675a str r2, [r3, #116] @ 0x74 + } + + /* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */ + if (huart->Init.Parity != UART_PARITY_NONE) + 8006352: 68fb ldr r3, [r7, #12] + 8006354: 691b ldr r3, [r3, #16] + 8006356: 2b00 cmp r3, #0 + 8006358: d019 beq.n 800638e + { + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE); + 800635a: 68fb ldr r3, [r7, #12] + 800635c: 681b ldr r3, [r3, #0] + 800635e: 62bb str r3, [r7, #40] @ 0x28 + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 8006360: 6abb ldr r3, [r7, #40] @ 0x28 + 8006362: e853 3f00 ldrex r3, [r3] + 8006366: 627b str r3, [r7, #36] @ 0x24 + return(result); + 8006368: 6a7b ldr r3, [r7, #36] @ 0x24 + 800636a: f443 7390 orr.w r3, r3, #288 @ 0x120 + 800636e: 677b str r3, [r7, #116] @ 0x74 + 8006370: 68fb ldr r3, [r7, #12] + 8006372: 681b ldr r3, [r3, #0] + 8006374: 461a mov r2, r3 + 8006376: 6f7b ldr r3, [r7, #116] @ 0x74 + 8006378: 637b str r3, [r7, #52] @ 0x34 + 800637a: 633a str r2, [r7, #48] @ 0x30 + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 800637c: 6b39 ldr r1, [r7, #48] @ 0x30 + 800637e: 6b7a ldr r2, [r7, #52] @ 0x34 + 8006380: e841 2300 strex r3, r2, [r1] + 8006384: 62fb str r3, [r7, #44] @ 0x2c + return(result); + 8006386: 6afb ldr r3, [r7, #44] @ 0x2c + 8006388: 2b00 cmp r3, #0 + 800638a: d1e6 bne.n 800635a + 800638c: e018 b.n 80063c0 + } + else + { + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); + 800638e: 68fb ldr r3, [r7, #12] + 8006390: 681b ldr r3, [r3, #0] + 8006392: 617b str r3, [r7, #20] + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 8006394: 697b ldr r3, [r7, #20] + 8006396: e853 3f00 ldrex r3, [r3] + 800639a: 613b str r3, [r7, #16] + return(result); + 800639c: 693b ldr r3, [r7, #16] + 800639e: f043 0320 orr.w r3, r3, #32 + 80063a2: 67bb str r3, [r7, #120] @ 0x78 + 80063a4: 68fb ldr r3, [r7, #12] + 80063a6: 681b ldr r3, [r3, #0] + 80063a8: 461a mov r2, r3 + 80063aa: 6fbb ldr r3, [r7, #120] @ 0x78 + 80063ac: 623b str r3, [r7, #32] + 80063ae: 61fa str r2, [r7, #28] + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 80063b0: 69f9 ldr r1, [r7, #28] + 80063b2: 6a3a ldr r2, [r7, #32] + 80063b4: e841 2300 strex r3, r2, [r1] + 80063b8: 61bb str r3, [r7, #24] + return(result); + 80063ba: 69bb ldr r3, [r7, #24] + 80063bc: 2b00 cmp r3, #0 + 80063be: d1e6 bne.n 800638e + } + } + return HAL_OK; + 80063c0: 2300 movs r3, #0 +} + 80063c2: 4618 mov r0, r3 + 80063c4: 378c adds r7, #140 @ 0x8c + 80063c6: 46bd mov sp, r7 + 80063c8: bc80 pop {r7} + 80063ca: 4770 bx lr + 80063cc: 08006d8d .word 0x08006d8d + 80063d0: 08006a29 .word 0x08006a29 + 80063d4: 08006871 .word 0x08006871 + 80063d8: 080066b9 .word 0x080066b9 + +080063dc : + * @brief End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion). + * @param huart UART handle. + * @retval None + */ +static void UART_EndTxTransfer(UART_HandleTypeDef *huart) +{ + 80063dc: b480 push {r7} + 80063de: b08f sub sp, #60 @ 0x3c + 80063e0: af00 add r7, sp, #0 + 80063e2: 6078 str r0, [r7, #4] + /* Disable TXEIE, TCIE, TXFT interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); + 80063e4: 687b ldr r3, [r7, #4] + 80063e6: 681b ldr r3, [r3, #0] + 80063e8: 623b str r3, [r7, #32] + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 80063ea: 6a3b ldr r3, [r7, #32] + 80063ec: e853 3f00 ldrex r3, [r3] + 80063f0: 61fb str r3, [r7, #28] + return(result); + 80063f2: 69fb ldr r3, [r7, #28] + 80063f4: f023 03c0 bic.w r3, r3, #192 @ 0xc0 + 80063f8: 637b str r3, [r7, #52] @ 0x34 + 80063fa: 687b ldr r3, [r7, #4] + 80063fc: 681b ldr r3, [r3, #0] + 80063fe: 461a mov r2, r3 + 8006400: 6b7b ldr r3, [r7, #52] @ 0x34 + 8006402: 62fb str r3, [r7, #44] @ 0x2c + 8006404: 62ba str r2, [r7, #40] @ 0x28 + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 8006406: 6ab9 ldr r1, [r7, #40] @ 0x28 + 8006408: 6afa ldr r2, [r7, #44] @ 0x2c + 800640a: e841 2300 strex r3, r2, [r1] + 800640e: 627b str r3, [r7, #36] @ 0x24 + return(result); + 8006410: 6a7b ldr r3, [r7, #36] @ 0x24 + 8006412: 2b00 cmp r3, #0 + 8006414: d1e6 bne.n 80063e4 + ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_TXFTIE)); + 8006416: 687b ldr r3, [r7, #4] + 8006418: 681b ldr r3, [r3, #0] + 800641a: 3308 adds r3, #8 + 800641c: 60fb str r3, [r7, #12] + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 800641e: 68fb ldr r3, [r7, #12] + 8006420: e853 3f00 ldrex r3, [r3] + 8006424: 60bb str r3, [r7, #8] + return(result); + 8006426: 68bb ldr r3, [r7, #8] + 8006428: f423 0300 bic.w r3, r3, #8388608 @ 0x800000 + 800642c: 633b str r3, [r7, #48] @ 0x30 + 800642e: 687b ldr r3, [r7, #4] + 8006430: 681b ldr r3, [r3, #0] + 8006432: 3308 adds r3, #8 + 8006434: 6b3a ldr r2, [r7, #48] @ 0x30 + 8006436: 61ba str r2, [r7, #24] + 8006438: 617b str r3, [r7, #20] + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 800643a: 6979 ldr r1, [r7, #20] + 800643c: 69ba ldr r2, [r7, #24] + 800643e: e841 2300 strex r3, r2, [r1] + 8006442: 613b str r3, [r7, #16] + return(result); + 8006444: 693b ldr r3, [r7, #16] + 8006446: 2b00 cmp r3, #0 + 8006448: d1e5 bne.n 8006416 + + /* At end of Tx process, restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + 800644a: 687b ldr r3, [r7, #4] + 800644c: 2220 movs r2, #32 + 800644e: f8c3 2088 str.w r2, [r3, #136] @ 0x88 +} + 8006452: bf00 nop + 8006454: 373c adds r7, #60 @ 0x3c + 8006456: 46bd mov sp, r7 + 8006458: bc80 pop {r7} + 800645a: 4770 bx lr + +0800645c : + * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion). + * @param huart UART handle. + * @retval None + */ +static void UART_EndRxTransfer(UART_HandleTypeDef *huart) +{ + 800645c: b480 push {r7} + 800645e: b095 sub sp, #84 @ 0x54 + 8006460: af00 add r7, sp, #0 + 8006462: 6078 str r0, [r7, #4] + /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); + 8006464: 687b ldr r3, [r7, #4] + 8006466: 681b ldr r3, [r3, #0] + 8006468: 637b str r3, [r7, #52] @ 0x34 + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 800646a: 6b7b ldr r3, [r7, #52] @ 0x34 + 800646c: e853 3f00 ldrex r3, [r3] + 8006470: 633b str r3, [r7, #48] @ 0x30 + return(result); + 8006472: 6b3b ldr r3, [r7, #48] @ 0x30 + 8006474: f423 7390 bic.w r3, r3, #288 @ 0x120 + 8006478: 64fb str r3, [r7, #76] @ 0x4c + 800647a: 687b ldr r3, [r7, #4] + 800647c: 681b ldr r3, [r3, #0] + 800647e: 461a mov r2, r3 + 8006480: 6cfb ldr r3, [r7, #76] @ 0x4c + 8006482: 643b str r3, [r7, #64] @ 0x40 + 8006484: 63fa str r2, [r7, #60] @ 0x3c + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 8006486: 6bf9 ldr r1, [r7, #60] @ 0x3c + 8006488: 6c3a ldr r2, [r7, #64] @ 0x40 + 800648a: e841 2300 strex r3, r2, [r1] + 800648e: 63bb str r3, [r7, #56] @ 0x38 + return(result); + 8006490: 6bbb ldr r3, [r7, #56] @ 0x38 + 8006492: 2b00 cmp r3, #0 + 8006494: d1e6 bne.n 8006464 + ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); + 8006496: 687b ldr r3, [r7, #4] + 8006498: 681b ldr r3, [r3, #0] + 800649a: 3308 adds r3, #8 + 800649c: 623b str r3, [r7, #32] + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 800649e: 6a3b ldr r3, [r7, #32] + 80064a0: e853 3f00 ldrex r3, [r3] + 80064a4: 61fb str r3, [r7, #28] + return(result); + 80064a6: 69fb ldr r3, [r7, #28] + 80064a8: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 + 80064ac: f023 0301 bic.w r3, r3, #1 + 80064b0: 64bb str r3, [r7, #72] @ 0x48 + 80064b2: 687b ldr r3, [r7, #4] + 80064b4: 681b ldr r3, [r3, #0] + 80064b6: 3308 adds r3, #8 + 80064b8: 6cba ldr r2, [r7, #72] @ 0x48 + 80064ba: 62fa str r2, [r7, #44] @ 0x2c + 80064bc: 62bb str r3, [r7, #40] @ 0x28 + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 80064be: 6ab9 ldr r1, [r7, #40] @ 0x28 + 80064c0: 6afa ldr r2, [r7, #44] @ 0x2c + 80064c2: e841 2300 strex r3, r2, [r1] + 80064c6: 627b str r3, [r7, #36] @ 0x24 + return(result); + 80064c8: 6a7b ldr r3, [r7, #36] @ 0x24 + 80064ca: 2b00 cmp r3, #0 + 80064cc: d1e3 bne.n 8006496 + + /* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + 80064ce: 687b ldr r3, [r7, #4] + 80064d0: 6edb ldr r3, [r3, #108] @ 0x6c + 80064d2: 2b01 cmp r3, #1 + 80064d4: d118 bne.n 8006508 + { + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + 80064d6: 687b ldr r3, [r7, #4] + 80064d8: 681b ldr r3, [r3, #0] + 80064da: 60fb str r3, [r7, #12] + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 80064dc: 68fb ldr r3, [r7, #12] + 80064de: e853 3f00 ldrex r3, [r3] + 80064e2: 60bb str r3, [r7, #8] + return(result); + 80064e4: 68bb ldr r3, [r7, #8] + 80064e6: f023 0310 bic.w r3, r3, #16 + 80064ea: 647b str r3, [r7, #68] @ 0x44 + 80064ec: 687b ldr r3, [r7, #4] + 80064ee: 681b ldr r3, [r3, #0] + 80064f0: 461a mov r2, r3 + 80064f2: 6c7b ldr r3, [r7, #68] @ 0x44 + 80064f4: 61bb str r3, [r7, #24] + 80064f6: 617a str r2, [r7, #20] + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 80064f8: 6979 ldr r1, [r7, #20] + 80064fa: 69ba ldr r2, [r7, #24] + 80064fc: e841 2300 strex r3, r2, [r1] + 8006500: 613b str r3, [r7, #16] + return(result); + 8006502: 693b ldr r3, [r7, #16] + 8006504: 2b00 cmp r3, #0 + 8006506: d1e6 bne.n 80064d6 + } + + /* At end of Rx process, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + 8006508: 687b ldr r3, [r7, #4] + 800650a: 2220 movs r2, #32 + 800650c: f8c3 208c str.w r2, [r3, #140] @ 0x8c + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + 8006510: 687b ldr r3, [r7, #4] + 8006512: 2200 movs r2, #0 + 8006514: 66da str r2, [r3, #108] @ 0x6c + + /* Reset RxIsr function pointer */ + huart->RxISR = NULL; + 8006516: 687b ldr r3, [r7, #4] + 8006518: 2200 movs r2, #0 + 800651a: 675a str r2, [r3, #116] @ 0x74 +} + 800651c: bf00 nop + 800651e: 3754 adds r7, #84 @ 0x54 + 8006520: 46bd mov sp, r7 + 8006522: bc80 pop {r7} + 8006524: 4770 bx lr + +08006526 : + * @brief DMA UART transmit process complete callback. + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma) +{ + 8006526: b580 push {r7, lr} + 8006528: b090 sub sp, #64 @ 0x40 + 800652a: af00 add r7, sp, #0 + 800652c: 6078 str r0, [r7, #4] + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + 800652e: 687b ldr r3, [r7, #4] + 8006530: 6a9b ldr r3, [r3, #40] @ 0x28 + 8006532: 63fb str r3, [r7, #60] @ 0x3c + + /* DMA Normal mode */ + if (HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC)) + 8006534: 687b ldr r3, [r7, #4] + 8006536: 681b ldr r3, [r3, #0] + 8006538: 681b ldr r3, [r3, #0] + 800653a: f003 0320 and.w r3, r3, #32 + 800653e: 2b00 cmp r3, #0 + 8006540: d133 bne.n 80065aa + { + /* Disable the DMA transfer for transmit request by resetting the DMAT bit + in the UART CR3 register */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + 8006542: 6bfb ldr r3, [r7, #60] @ 0x3c + 8006544: 681b ldr r3, [r3, #0] + 8006546: 3308 adds r3, #8 + 8006548: 627b str r3, [r7, #36] @ 0x24 + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 800654a: 6a7b ldr r3, [r7, #36] @ 0x24 + 800654c: e853 3f00 ldrex r3, [r3] + 8006550: 623b str r3, [r7, #32] + return(result); + 8006552: 6a3b ldr r3, [r7, #32] + 8006554: f023 0380 bic.w r3, r3, #128 @ 0x80 + 8006558: 63bb str r3, [r7, #56] @ 0x38 + 800655a: 6bfb ldr r3, [r7, #60] @ 0x3c + 800655c: 681b ldr r3, [r3, #0] + 800655e: 3308 adds r3, #8 + 8006560: 6bba ldr r2, [r7, #56] @ 0x38 + 8006562: 633a str r2, [r7, #48] @ 0x30 + 8006564: 62fb str r3, [r7, #44] @ 0x2c + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 8006566: 6af9 ldr r1, [r7, #44] @ 0x2c + 8006568: 6b3a ldr r2, [r7, #48] @ 0x30 + 800656a: e841 2300 strex r3, r2, [r1] + 800656e: 62bb str r3, [r7, #40] @ 0x28 + return(result); + 8006570: 6abb ldr r3, [r7, #40] @ 0x28 + 8006572: 2b00 cmp r3, #0 + 8006574: d1e5 bne.n 8006542 + + /* Enable the UART Transmit Complete Interrupt */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); + 8006576: 6bfb ldr r3, [r7, #60] @ 0x3c + 8006578: 681b ldr r3, [r3, #0] + 800657a: 613b str r3, [r7, #16] + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 800657c: 693b ldr r3, [r7, #16] + 800657e: e853 3f00 ldrex r3, [r3] + 8006582: 60fb str r3, [r7, #12] + return(result); + 8006584: 68fb ldr r3, [r7, #12] + 8006586: f043 0340 orr.w r3, r3, #64 @ 0x40 + 800658a: 637b str r3, [r7, #52] @ 0x34 + 800658c: 6bfb ldr r3, [r7, #60] @ 0x3c + 800658e: 681b ldr r3, [r3, #0] + 8006590: 461a mov r2, r3 + 8006592: 6b7b ldr r3, [r7, #52] @ 0x34 + 8006594: 61fb str r3, [r7, #28] + 8006596: 61ba str r2, [r7, #24] + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 8006598: 69b9 ldr r1, [r7, #24] + 800659a: 69fa ldr r2, [r7, #28] + 800659c: e841 2300 strex r3, r2, [r1] + 80065a0: 617b str r3, [r7, #20] + return(result); + 80065a2: 697b ldr r3, [r7, #20] + 80065a4: 2b00 cmp r3, #0 + 80065a6: d1e6 bne.n 8006576 +#else + /*Call legacy weak Tx complete callback*/ + HAL_UART_TxCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } +} + 80065a8: e002 b.n 80065b0 + HAL_UART_TxCpltCallback(huart); + 80065aa: 6bf8 ldr r0, [r7, #60] @ 0x3c + 80065ac: f7fa ffba bl 8001524 +} + 80065b0: bf00 nop + 80065b2: 3740 adds r7, #64 @ 0x40 + 80065b4: 46bd mov sp, r7 + 80065b6: bd80 pop {r7, pc} + +080065b8 : + * @brief DMA UART transmit process half complete callback. + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma) +{ + 80065b8: b580 push {r7, lr} + 80065ba: b084 sub sp, #16 + 80065bc: af00 add r7, sp, #0 + 80065be: 6078 str r0, [r7, #4] + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + 80065c0: 687b ldr r3, [r7, #4] + 80065c2: 6a9b ldr r3, [r3, #40] @ 0x28 + 80065c4: 60fb str r3, [r7, #12] +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Tx Half complete callback*/ + huart->TxHalfCpltCallback(huart); +#else + /*Call legacy weak Tx Half complete callback*/ + HAL_UART_TxHalfCpltCallback(huart); + 80065c6: 68f8 ldr r0, [r7, #12] + 80065c8: f7ff f99e bl 8005908 +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + 80065cc: bf00 nop + 80065ce: 3710 adds r7, #16 + 80065d0: 46bd mov sp, r7 + 80065d2: bd80 pop {r7, pc} + +080065d4 : + * @brief DMA UART communication error callback. + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMAError(DMA_HandleTypeDef *hdma) +{ + 80065d4: b580 push {r7, lr} + 80065d6: b086 sub sp, #24 + 80065d8: af00 add r7, sp, #0 + 80065da: 6078 str r0, [r7, #4] + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + 80065dc: 687b ldr r3, [r7, #4] + 80065de: 6a9b ldr r3, [r3, #40] @ 0x28 + 80065e0: 617b str r3, [r7, #20] + + const HAL_UART_StateTypeDef gstate = huart->gState; + 80065e2: 697b ldr r3, [r7, #20] + 80065e4: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 + 80065e8: 613b str r3, [r7, #16] + const HAL_UART_StateTypeDef rxstate = huart->RxState; + 80065ea: 697b ldr r3, [r7, #20] + 80065ec: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c + 80065f0: 60fb str r3, [r7, #12] + + /* Stop UART DMA Tx request if ongoing */ + if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) && + 80065f2: 697b ldr r3, [r7, #20] + 80065f4: 681b ldr r3, [r3, #0] + 80065f6: 689b ldr r3, [r3, #8] + 80065f8: f003 0380 and.w r3, r3, #128 @ 0x80 + 80065fc: 2b80 cmp r3, #128 @ 0x80 + 80065fe: d105 bne.n 800660c + 8006600: 693b ldr r3, [r7, #16] + 8006602: 2b21 cmp r3, #33 @ 0x21 + 8006604: d102 bne.n 800660c + (gstate == HAL_UART_STATE_BUSY_TX)) + { + UART_EndTxTransfer(huart); + 8006606: 6978 ldr r0, [r7, #20] + 8006608: f7ff fee8 bl 80063dc + } + + /* Stop UART DMA Rx request if ongoing */ + if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) && + 800660c: 697b ldr r3, [r7, #20] + 800660e: 681b ldr r3, [r3, #0] + 8006610: 689b ldr r3, [r3, #8] + 8006612: f003 0340 and.w r3, r3, #64 @ 0x40 + 8006616: 2b40 cmp r3, #64 @ 0x40 + 8006618: d105 bne.n 8006626 + 800661a: 68fb ldr r3, [r7, #12] + 800661c: 2b22 cmp r3, #34 @ 0x22 + 800661e: d102 bne.n 8006626 + (rxstate == HAL_UART_STATE_BUSY_RX)) + { + UART_EndRxTransfer(huart); + 8006620: 6978 ldr r0, [r7, #20] + 8006622: f7ff ff1b bl 800645c + } + + huart->ErrorCode |= HAL_UART_ERROR_DMA; + 8006626: 697b ldr r3, [r7, #20] + 8006628: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 800662c: f043 0210 orr.w r2, r3, #16 + 8006630: 697b ldr r3, [r7, #20] + 8006632: f8c3 2090 str.w r2, [r3, #144] @ 0x90 +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); + 8006636: 6978 ldr r0, [r7, #20] + 8006638: f7ff f96f bl 800591a +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + 800663c: bf00 nop + 800663e: 3718 adds r7, #24 + 8006640: 46bd mov sp, r7 + 8006642: bd80 pop {r7, pc} + +08006644 : + * (To be called at end of DMA Abort procedure following error occurrence). + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma) +{ + 8006644: b580 push {r7, lr} + 8006646: b084 sub sp, #16 + 8006648: af00 add r7, sp, #0 + 800664a: 6078 str r0, [r7, #4] + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + 800664c: 687b ldr r3, [r7, #4] + 800664e: 6a9b ldr r3, [r3, #40] @ 0x28 + 8006650: 60fb str r3, [r7, #12] +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); + 8006652: 68f8 ldr r0, [r7, #12] + 8006654: f7ff f961 bl 800591a +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + 8006658: bf00 nop + 800665a: 3710 adds r7, #16 + 800665c: 46bd mov sp, r7 + 800665e: bd80 pop {r7, pc} + +08006660 : + * @param huart pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval None + */ +static void UART_EndTransmit_IT(UART_HandleTypeDef *huart) +{ + 8006660: b580 push {r7, lr} + 8006662: b088 sub sp, #32 + 8006664: af00 add r7, sp, #0 + 8006666: 6078 str r0, [r7, #4] + /* Disable the UART Transmit Complete Interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE); + 8006668: 687b ldr r3, [r7, #4] + 800666a: 681b ldr r3, [r3, #0] + 800666c: 60fb str r3, [r7, #12] + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 800666e: 68fb ldr r3, [r7, #12] + 8006670: e853 3f00 ldrex r3, [r3] + 8006674: 60bb str r3, [r7, #8] + return(result); + 8006676: 68bb ldr r3, [r7, #8] + 8006678: f023 0340 bic.w r3, r3, #64 @ 0x40 + 800667c: 61fb str r3, [r7, #28] + 800667e: 687b ldr r3, [r7, #4] + 8006680: 681b ldr r3, [r3, #0] + 8006682: 461a mov r2, r3 + 8006684: 69fb ldr r3, [r7, #28] + 8006686: 61bb str r3, [r7, #24] + 8006688: 617a str r2, [r7, #20] + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 800668a: 6979 ldr r1, [r7, #20] + 800668c: 69ba ldr r2, [r7, #24] + 800668e: e841 2300 strex r3, r2, [r1] + 8006692: 613b str r3, [r7, #16] + return(result); + 8006694: 693b ldr r3, [r7, #16] + 8006696: 2b00 cmp r3, #0 + 8006698: d1e6 bne.n 8006668 + + /* Tx process is ended, restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + 800669a: 687b ldr r3, [r7, #4] + 800669c: 2220 movs r2, #32 + 800669e: f8c3 2088 str.w r2, [r3, #136] @ 0x88 + + /* Cleat TxISR function pointer */ + huart->TxISR = NULL; + 80066a2: 687b ldr r3, [r7, #4] + 80066a4: 2200 movs r2, #0 + 80066a6: 679a str r2, [r3, #120] @ 0x78 +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Tx complete callback*/ + huart->TxCpltCallback(huart); +#else + /*Call legacy weak Tx complete callback*/ + HAL_UART_TxCpltCallback(huart); + 80066a8: 6878 ldr r0, [r7, #4] + 80066aa: f7fa ff3b bl 8001524 +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + 80066ae: bf00 nop + 80066b0: 3720 adds r7, #32 + 80066b2: 46bd mov sp, r7 + 80066b4: bd80 pop {r7, pc} + ... + +080066b8 : + * @brief RX interrupt handler for 7 or 8 bits data word length . + * @param huart UART handle. + * @retval None + */ +static void UART_RxISR_8BIT(UART_HandleTypeDef *huart) +{ + 80066b8: b580 push {r7, lr} + 80066ba: b09c sub sp, #112 @ 0x70 + 80066bc: af00 add r7, sp, #0 + 80066be: 6078 str r0, [r7, #4] + uint16_t uhMask = huart->Mask; + 80066c0: 687b ldr r3, [r7, #4] + 80066c2: f8b3 3060 ldrh.w r3, [r3, #96] @ 0x60 + 80066c6: f8a7 306e strh.w r3, [r7, #110] @ 0x6e + uint16_t uhdata; + + /* Check that a Rx process is ongoing */ + if (huart->RxState == HAL_UART_STATE_BUSY_RX) + 80066ca: 687b ldr r3, [r7, #4] + 80066cc: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c + 80066d0: 2b22 cmp r3, #34 @ 0x22 + 80066d2: f040 80be bne.w 8006852 + { + uhdata = (uint16_t) READ_REG(huart->Instance->RDR); + 80066d6: 687b ldr r3, [r7, #4] + 80066d8: 681b ldr r3, [r3, #0] + 80066da: 6a5b ldr r3, [r3, #36] @ 0x24 + 80066dc: f8a7 306c strh.w r3, [r7, #108] @ 0x6c + *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask); + 80066e0: f8b7 306c ldrh.w r3, [r7, #108] @ 0x6c + 80066e4: b2d9 uxtb r1, r3 + 80066e6: f8b7 306e ldrh.w r3, [r7, #110] @ 0x6e + 80066ea: b2da uxtb r2, r3 + 80066ec: 687b ldr r3, [r7, #4] + 80066ee: 6d9b ldr r3, [r3, #88] @ 0x58 + 80066f0: 400a ands r2, r1 + 80066f2: b2d2 uxtb r2, r2 + 80066f4: 701a strb r2, [r3, #0] + huart->pRxBuffPtr++; + 80066f6: 687b ldr r3, [r7, #4] + 80066f8: 6d9b ldr r3, [r3, #88] @ 0x58 + 80066fa: 1c5a adds r2, r3, #1 + 80066fc: 687b ldr r3, [r7, #4] + 80066fe: 659a str r2, [r3, #88] @ 0x58 + huart->RxXferCount--; + 8006700: 687b ldr r3, [r7, #4] + 8006702: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e + 8006706: b29b uxth r3, r3 + 8006708: 3b01 subs r3, #1 + 800670a: b29a uxth r2, r3 + 800670c: 687b ldr r3, [r7, #4] + 800670e: f8a3 205e strh.w r2, [r3, #94] @ 0x5e + + if (huart->RxXferCount == 0U) + 8006712: 687b ldr r3, [r7, #4] + 8006714: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e + 8006718: b29b uxth r3, r3 + 800671a: 2b00 cmp r3, #0 + 800671c: f040 80a1 bne.w 8006862 + { + /* Disable the UART Parity Error Interrupt and RXNE interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); + 8006720: 687b ldr r3, [r7, #4] + 8006722: 681b ldr r3, [r3, #0] + 8006724: 64fb str r3, [r7, #76] @ 0x4c + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 8006726: 6cfb ldr r3, [r7, #76] @ 0x4c + 8006728: e853 3f00 ldrex r3, [r3] + 800672c: 64bb str r3, [r7, #72] @ 0x48 + return(result); + 800672e: 6cbb ldr r3, [r7, #72] @ 0x48 + 8006730: f423 7390 bic.w r3, r3, #288 @ 0x120 + 8006734: 66bb str r3, [r7, #104] @ 0x68 + 8006736: 687b ldr r3, [r7, #4] + 8006738: 681b ldr r3, [r3, #0] + 800673a: 461a mov r2, r3 + 800673c: 6ebb ldr r3, [r7, #104] @ 0x68 + 800673e: 65bb str r3, [r7, #88] @ 0x58 + 8006740: 657a str r2, [r7, #84] @ 0x54 + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 8006742: 6d79 ldr r1, [r7, #84] @ 0x54 + 8006744: 6dba ldr r2, [r7, #88] @ 0x58 + 8006746: e841 2300 strex r3, r2, [r1] + 800674a: 653b str r3, [r7, #80] @ 0x50 + return(result); + 800674c: 6d3b ldr r3, [r7, #80] @ 0x50 + 800674e: 2b00 cmp r3, #0 + 8006750: d1e6 bne.n 8006720 + + /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 8006752: 687b ldr r3, [r7, #4] + 8006754: 681b ldr r3, [r3, #0] + 8006756: 3308 adds r3, #8 + 8006758: 63bb str r3, [r7, #56] @ 0x38 + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 800675a: 6bbb ldr r3, [r7, #56] @ 0x38 + 800675c: e853 3f00 ldrex r3, [r3] + 8006760: 637b str r3, [r7, #52] @ 0x34 + return(result); + 8006762: 6b7b ldr r3, [r7, #52] @ 0x34 + 8006764: f023 0301 bic.w r3, r3, #1 + 8006768: 667b str r3, [r7, #100] @ 0x64 + 800676a: 687b ldr r3, [r7, #4] + 800676c: 681b ldr r3, [r3, #0] + 800676e: 3308 adds r3, #8 + 8006770: 6e7a ldr r2, [r7, #100] @ 0x64 + 8006772: 647a str r2, [r7, #68] @ 0x44 + 8006774: 643b str r3, [r7, #64] @ 0x40 + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 8006776: 6c39 ldr r1, [r7, #64] @ 0x40 + 8006778: 6c7a ldr r2, [r7, #68] @ 0x44 + 800677a: e841 2300 strex r3, r2, [r1] + 800677e: 63fb str r3, [r7, #60] @ 0x3c + return(result); + 8006780: 6bfb ldr r3, [r7, #60] @ 0x3c + 8006782: 2b00 cmp r3, #0 + 8006784: d1e5 bne.n 8006752 + + /* Rx process is completed, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + 8006786: 687b ldr r3, [r7, #4] + 8006788: 2220 movs r2, #32 + 800678a: f8c3 208c str.w r2, [r3, #140] @ 0x8c + + /* Clear RxISR function pointer */ + huart->RxISR = NULL; + 800678e: 687b ldr r3, [r7, #4] + 8006790: 2200 movs r2, #0 + 8006792: 675a str r2, [r3, #116] @ 0x74 + + /* Initialize type of RxEvent to Transfer Complete */ + huart->RxEventType = HAL_UART_RXEVENT_TC; + 8006794: 687b ldr r3, [r7, #4] + 8006796: 2200 movs r2, #0 + 8006798: 671a str r2, [r3, #112] @ 0x70 + + if (!(IS_LPUART_INSTANCE(huart->Instance))) + 800679a: 687b ldr r3, [r7, #4] + 800679c: 681b ldr r3, [r3, #0] + 800679e: 4a33 ldr r2, [pc, #204] @ (800686c ) + 80067a0: 4293 cmp r3, r2 + 80067a2: d01f beq.n 80067e4 + { + /* Check that USART RTOEN bit is set */ + if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) + 80067a4: 687b ldr r3, [r7, #4] + 80067a6: 681b ldr r3, [r3, #0] + 80067a8: 685b ldr r3, [r3, #4] + 80067aa: f403 0300 and.w r3, r3, #8388608 @ 0x800000 + 80067ae: 2b00 cmp r3, #0 + 80067b0: d018 beq.n 80067e4 + { + /* Enable the UART Receiver Timeout Interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); + 80067b2: 687b ldr r3, [r7, #4] + 80067b4: 681b ldr r3, [r3, #0] + 80067b6: 627b str r3, [r7, #36] @ 0x24 + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 80067b8: 6a7b ldr r3, [r7, #36] @ 0x24 + 80067ba: e853 3f00 ldrex r3, [r3] + 80067be: 623b str r3, [r7, #32] + return(result); + 80067c0: 6a3b ldr r3, [r7, #32] + 80067c2: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000 + 80067c6: 663b str r3, [r7, #96] @ 0x60 + 80067c8: 687b ldr r3, [r7, #4] + 80067ca: 681b ldr r3, [r3, #0] + 80067cc: 461a mov r2, r3 + 80067ce: 6e3b ldr r3, [r7, #96] @ 0x60 + 80067d0: 633b str r3, [r7, #48] @ 0x30 + 80067d2: 62fa str r2, [r7, #44] @ 0x2c + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 80067d4: 6af9 ldr r1, [r7, #44] @ 0x2c + 80067d6: 6b3a ldr r2, [r7, #48] @ 0x30 + 80067d8: e841 2300 strex r3, r2, [r1] + 80067dc: 62bb str r3, [r7, #40] @ 0x28 + return(result); + 80067de: 6abb ldr r3, [r7, #40] @ 0x28 + 80067e0: 2b00 cmp r3, #0 + 80067e2: d1e6 bne.n 80067b2 + } + } + + /* Check current reception Mode : + If Reception till IDLE event has been selected : */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + 80067e4: 687b ldr r3, [r7, #4] + 80067e6: 6edb ldr r3, [r3, #108] @ 0x6c + 80067e8: 2b01 cmp r3, #1 + 80067ea: d12e bne.n 800684a + { + /* Set reception type to Standard */ + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + 80067ec: 687b ldr r3, [r7, #4] + 80067ee: 2200 movs r2, #0 + 80067f0: 66da str r2, [r3, #108] @ 0x6c + + /* Disable IDLE interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + 80067f2: 687b ldr r3, [r7, #4] + 80067f4: 681b ldr r3, [r3, #0] + 80067f6: 613b str r3, [r7, #16] + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 80067f8: 693b ldr r3, [r7, #16] + 80067fa: e853 3f00 ldrex r3, [r3] + 80067fe: 60fb str r3, [r7, #12] + return(result); + 8006800: 68fb ldr r3, [r7, #12] + 8006802: f023 0310 bic.w r3, r3, #16 + 8006806: 65fb str r3, [r7, #92] @ 0x5c + 8006808: 687b ldr r3, [r7, #4] + 800680a: 681b ldr r3, [r3, #0] + 800680c: 461a mov r2, r3 + 800680e: 6dfb ldr r3, [r7, #92] @ 0x5c + 8006810: 61fb str r3, [r7, #28] + 8006812: 61ba str r2, [r7, #24] + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 8006814: 69b9 ldr r1, [r7, #24] + 8006816: 69fa ldr r2, [r7, #28] + 8006818: e841 2300 strex r3, r2, [r1] + 800681c: 617b str r3, [r7, #20] + return(result); + 800681e: 697b ldr r3, [r7, #20] + 8006820: 2b00 cmp r3, #0 + 8006822: d1e6 bne.n 80067f2 + + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) + 8006824: 687b ldr r3, [r7, #4] + 8006826: 681b ldr r3, [r3, #0] + 8006828: 69db ldr r3, [r3, #28] + 800682a: f003 0310 and.w r3, r3, #16 + 800682e: 2b10 cmp r3, #16 + 8006830: d103 bne.n 800683a + { + /* Clear IDLE Flag */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + 8006832: 687b ldr r3, [r7, #4] + 8006834: 681b ldr r3, [r3, #0] + 8006836: 2210 movs r2, #16 + 8006838: 621a str r2, [r3, #32] +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, huart->RxXferSize); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); + 800683a: 687b ldr r3, [r7, #4] + 800683c: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c + 8006840: 4619 mov r1, r3 + 8006842: 6878 ldr r0, [r7, #4] + 8006844: f7ff f872 bl 800592c + else + { + /* Clear RXNE interrupt flag */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + } +} + 8006848: e00b b.n 8006862 + HAL_UART_RxCpltCallback(huart); + 800684a: 6878 ldr r0, [r7, #4] + 800684c: f7fa fe80 bl 8001550 +} + 8006850: e007 b.n 8006862 + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + 8006852: 687b ldr r3, [r7, #4] + 8006854: 681b ldr r3, [r3, #0] + 8006856: 699a ldr r2, [r3, #24] + 8006858: 687b ldr r3, [r7, #4] + 800685a: 681b ldr r3, [r3, #0] + 800685c: f042 0208 orr.w r2, r2, #8 + 8006860: 619a str r2, [r3, #24] +} + 8006862: bf00 nop + 8006864: 3770 adds r7, #112 @ 0x70 + 8006866: 46bd mov sp, r7 + 8006868: bd80 pop {r7, pc} + 800686a: bf00 nop + 800686c: 40008000 .word 0x40008000 + +08006870 : + * interruptions have been enabled by HAL_UART_Receive_IT() + * @param huart UART handle. + * @retval None + */ +static void UART_RxISR_16BIT(UART_HandleTypeDef *huart) +{ + 8006870: b580 push {r7, lr} + 8006872: b09c sub sp, #112 @ 0x70 + 8006874: af00 add r7, sp, #0 + 8006876: 6078 str r0, [r7, #4] + uint16_t *tmp; + uint16_t uhMask = huart->Mask; + 8006878: 687b ldr r3, [r7, #4] + 800687a: f8b3 3060 ldrh.w r3, [r3, #96] @ 0x60 + 800687e: f8a7 306e strh.w r3, [r7, #110] @ 0x6e + uint16_t uhdata; + + /* Check that a Rx process is ongoing */ + if (huart->RxState == HAL_UART_STATE_BUSY_RX) + 8006882: 687b ldr r3, [r7, #4] + 8006884: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c + 8006888: 2b22 cmp r3, #34 @ 0x22 + 800688a: f040 80be bne.w 8006a0a + { + uhdata = (uint16_t) READ_REG(huart->Instance->RDR); + 800688e: 687b ldr r3, [r7, #4] + 8006890: 681b ldr r3, [r3, #0] + 8006892: 6a5b ldr r3, [r3, #36] @ 0x24 + 8006894: f8a7 306c strh.w r3, [r7, #108] @ 0x6c + tmp = (uint16_t *) huart->pRxBuffPtr ; + 8006898: 687b ldr r3, [r7, #4] + 800689a: 6d9b ldr r3, [r3, #88] @ 0x58 + 800689c: 66bb str r3, [r7, #104] @ 0x68 + *tmp = (uint16_t)(uhdata & uhMask); + 800689e: f8b7 206c ldrh.w r2, [r7, #108] @ 0x6c + 80068a2: f8b7 306e ldrh.w r3, [r7, #110] @ 0x6e + 80068a6: 4013 ands r3, r2 + 80068a8: b29a uxth r2, r3 + 80068aa: 6ebb ldr r3, [r7, #104] @ 0x68 + 80068ac: 801a strh r2, [r3, #0] + huart->pRxBuffPtr += 2U; + 80068ae: 687b ldr r3, [r7, #4] + 80068b0: 6d9b ldr r3, [r3, #88] @ 0x58 + 80068b2: 1c9a adds r2, r3, #2 + 80068b4: 687b ldr r3, [r7, #4] + 80068b6: 659a str r2, [r3, #88] @ 0x58 + huart->RxXferCount--; + 80068b8: 687b ldr r3, [r7, #4] + 80068ba: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e + 80068be: b29b uxth r3, r3 + 80068c0: 3b01 subs r3, #1 + 80068c2: b29a uxth r2, r3 + 80068c4: 687b ldr r3, [r7, #4] + 80068c6: f8a3 205e strh.w r2, [r3, #94] @ 0x5e + + if (huart->RxXferCount == 0U) + 80068ca: 687b ldr r3, [r7, #4] + 80068cc: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e + 80068d0: b29b uxth r3, r3 + 80068d2: 2b00 cmp r3, #0 + 80068d4: f040 80a1 bne.w 8006a1a + { + /* Disable the UART Parity Error Interrupt and RXNE interrupt*/ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); + 80068d8: 687b ldr r3, [r7, #4] + 80068da: 681b ldr r3, [r3, #0] + 80068dc: 64bb str r3, [r7, #72] @ 0x48 + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 80068de: 6cbb ldr r3, [r7, #72] @ 0x48 + 80068e0: e853 3f00 ldrex r3, [r3] + 80068e4: 647b str r3, [r7, #68] @ 0x44 + return(result); + 80068e6: 6c7b ldr r3, [r7, #68] @ 0x44 + 80068e8: f423 7390 bic.w r3, r3, #288 @ 0x120 + 80068ec: 667b str r3, [r7, #100] @ 0x64 + 80068ee: 687b ldr r3, [r7, #4] + 80068f0: 681b ldr r3, [r3, #0] + 80068f2: 461a mov r2, r3 + 80068f4: 6e7b ldr r3, [r7, #100] @ 0x64 + 80068f6: 657b str r3, [r7, #84] @ 0x54 + 80068f8: 653a str r2, [r7, #80] @ 0x50 + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 80068fa: 6d39 ldr r1, [r7, #80] @ 0x50 + 80068fc: 6d7a ldr r2, [r7, #84] @ 0x54 + 80068fe: e841 2300 strex r3, r2, [r1] + 8006902: 64fb str r3, [r7, #76] @ 0x4c + return(result); + 8006904: 6cfb ldr r3, [r7, #76] @ 0x4c + 8006906: 2b00 cmp r3, #0 + 8006908: d1e6 bne.n 80068d8 + + /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 800690a: 687b ldr r3, [r7, #4] + 800690c: 681b ldr r3, [r3, #0] + 800690e: 3308 adds r3, #8 + 8006910: 637b str r3, [r7, #52] @ 0x34 + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 8006912: 6b7b ldr r3, [r7, #52] @ 0x34 + 8006914: e853 3f00 ldrex r3, [r3] + 8006918: 633b str r3, [r7, #48] @ 0x30 + return(result); + 800691a: 6b3b ldr r3, [r7, #48] @ 0x30 + 800691c: f023 0301 bic.w r3, r3, #1 + 8006920: 663b str r3, [r7, #96] @ 0x60 + 8006922: 687b ldr r3, [r7, #4] + 8006924: 681b ldr r3, [r3, #0] + 8006926: 3308 adds r3, #8 + 8006928: 6e3a ldr r2, [r7, #96] @ 0x60 + 800692a: 643a str r2, [r7, #64] @ 0x40 + 800692c: 63fb str r3, [r7, #60] @ 0x3c + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 800692e: 6bf9 ldr r1, [r7, #60] @ 0x3c + 8006930: 6c3a ldr r2, [r7, #64] @ 0x40 + 8006932: e841 2300 strex r3, r2, [r1] + 8006936: 63bb str r3, [r7, #56] @ 0x38 + return(result); + 8006938: 6bbb ldr r3, [r7, #56] @ 0x38 + 800693a: 2b00 cmp r3, #0 + 800693c: d1e5 bne.n 800690a + + /* Rx process is completed, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + 800693e: 687b ldr r3, [r7, #4] + 8006940: 2220 movs r2, #32 + 8006942: f8c3 208c str.w r2, [r3, #140] @ 0x8c + + /* Clear RxISR function pointer */ + huart->RxISR = NULL; + 8006946: 687b ldr r3, [r7, #4] + 8006948: 2200 movs r2, #0 + 800694a: 675a str r2, [r3, #116] @ 0x74 + + /* Initialize type of RxEvent to Transfer Complete */ + huart->RxEventType = HAL_UART_RXEVENT_TC; + 800694c: 687b ldr r3, [r7, #4] + 800694e: 2200 movs r2, #0 + 8006950: 671a str r2, [r3, #112] @ 0x70 + + if (!(IS_LPUART_INSTANCE(huart->Instance))) + 8006952: 687b ldr r3, [r7, #4] + 8006954: 681b ldr r3, [r3, #0] + 8006956: 4a33 ldr r2, [pc, #204] @ (8006a24 ) + 8006958: 4293 cmp r3, r2 + 800695a: d01f beq.n 800699c + { + /* Check that USART RTOEN bit is set */ + if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) + 800695c: 687b ldr r3, [r7, #4] + 800695e: 681b ldr r3, [r3, #0] + 8006960: 685b ldr r3, [r3, #4] + 8006962: f403 0300 and.w r3, r3, #8388608 @ 0x800000 + 8006966: 2b00 cmp r3, #0 + 8006968: d018 beq.n 800699c + { + /* Enable the UART Receiver Timeout Interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); + 800696a: 687b ldr r3, [r7, #4] + 800696c: 681b ldr r3, [r3, #0] + 800696e: 623b str r3, [r7, #32] + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 8006970: 6a3b ldr r3, [r7, #32] + 8006972: e853 3f00 ldrex r3, [r3] + 8006976: 61fb str r3, [r7, #28] + return(result); + 8006978: 69fb ldr r3, [r7, #28] + 800697a: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000 + 800697e: 65fb str r3, [r7, #92] @ 0x5c + 8006980: 687b ldr r3, [r7, #4] + 8006982: 681b ldr r3, [r3, #0] + 8006984: 461a mov r2, r3 + 8006986: 6dfb ldr r3, [r7, #92] @ 0x5c + 8006988: 62fb str r3, [r7, #44] @ 0x2c + 800698a: 62ba str r2, [r7, #40] @ 0x28 + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 800698c: 6ab9 ldr r1, [r7, #40] @ 0x28 + 800698e: 6afa ldr r2, [r7, #44] @ 0x2c + 8006990: e841 2300 strex r3, r2, [r1] + 8006994: 627b str r3, [r7, #36] @ 0x24 + return(result); + 8006996: 6a7b ldr r3, [r7, #36] @ 0x24 + 8006998: 2b00 cmp r3, #0 + 800699a: d1e6 bne.n 800696a + } + } + + /* Check current reception Mode : + If Reception till IDLE event has been selected : */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + 800699c: 687b ldr r3, [r7, #4] + 800699e: 6edb ldr r3, [r3, #108] @ 0x6c + 80069a0: 2b01 cmp r3, #1 + 80069a2: d12e bne.n 8006a02 + { + /* Set reception type to Standard */ + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + 80069a4: 687b ldr r3, [r7, #4] + 80069a6: 2200 movs r2, #0 + 80069a8: 66da str r2, [r3, #108] @ 0x6c + + /* Disable IDLE interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + 80069aa: 687b ldr r3, [r7, #4] + 80069ac: 681b ldr r3, [r3, #0] + 80069ae: 60fb str r3, [r7, #12] + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 80069b0: 68fb ldr r3, [r7, #12] + 80069b2: e853 3f00 ldrex r3, [r3] + 80069b6: 60bb str r3, [r7, #8] + return(result); + 80069b8: 68bb ldr r3, [r7, #8] + 80069ba: f023 0310 bic.w r3, r3, #16 + 80069be: 65bb str r3, [r7, #88] @ 0x58 + 80069c0: 687b ldr r3, [r7, #4] + 80069c2: 681b ldr r3, [r3, #0] + 80069c4: 461a mov r2, r3 + 80069c6: 6dbb ldr r3, [r7, #88] @ 0x58 + 80069c8: 61bb str r3, [r7, #24] + 80069ca: 617a str r2, [r7, #20] + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 80069cc: 6979 ldr r1, [r7, #20] + 80069ce: 69ba ldr r2, [r7, #24] + 80069d0: e841 2300 strex r3, r2, [r1] + 80069d4: 613b str r3, [r7, #16] + return(result); + 80069d6: 693b ldr r3, [r7, #16] + 80069d8: 2b00 cmp r3, #0 + 80069da: d1e6 bne.n 80069aa + + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) + 80069dc: 687b ldr r3, [r7, #4] + 80069de: 681b ldr r3, [r3, #0] + 80069e0: 69db ldr r3, [r3, #28] + 80069e2: f003 0310 and.w r3, r3, #16 + 80069e6: 2b10 cmp r3, #16 + 80069e8: d103 bne.n 80069f2 + { + /* Clear IDLE Flag */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + 80069ea: 687b ldr r3, [r7, #4] + 80069ec: 681b ldr r3, [r3, #0] + 80069ee: 2210 movs r2, #16 + 80069f0: 621a str r2, [r3, #32] +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, huart->RxXferSize); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); + 80069f2: 687b ldr r3, [r7, #4] + 80069f4: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c + 80069f8: 4619 mov r1, r3 + 80069fa: 6878 ldr r0, [r7, #4] + 80069fc: f7fe ff96 bl 800592c + else + { + /* Clear RXNE interrupt flag */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + } +} + 8006a00: e00b b.n 8006a1a + HAL_UART_RxCpltCallback(huart); + 8006a02: 6878 ldr r0, [r7, #4] + 8006a04: f7fa fda4 bl 8001550 +} + 8006a08: e007 b.n 8006a1a + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + 8006a0a: 687b ldr r3, [r7, #4] + 8006a0c: 681b ldr r3, [r3, #0] + 8006a0e: 699a ldr r2, [r3, #24] + 8006a10: 687b ldr r3, [r7, #4] + 8006a12: 681b ldr r3, [r3, #0] + 8006a14: f042 0208 orr.w r2, r2, #8 + 8006a18: 619a str r2, [r3, #24] +} + 8006a1a: bf00 nop + 8006a1c: 3770 adds r7, #112 @ 0x70 + 8006a1e: 46bd mov sp, r7 + 8006a20: bd80 pop {r7, pc} + 8006a22: bf00 nop + 8006a24: 40008000 .word 0x40008000 + +08006a28 : + * interruptions have been enabled by HAL_UART_Receive_IT() + * @param huart UART handle. + * @retval None + */ +static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) +{ + 8006a28: b580 push {r7, lr} + 8006a2a: b0ac sub sp, #176 @ 0xb0 + 8006a2c: af00 add r7, sp, #0 + 8006a2e: 6078 str r0, [r7, #4] + uint16_t uhMask = huart->Mask; + 8006a30: 687b ldr r3, [r7, #4] + 8006a32: f8b3 3060 ldrh.w r3, [r3, #96] @ 0x60 + 8006a36: f8a7 30aa strh.w r3, [r7, #170] @ 0xaa + uint16_t uhdata; + uint16_t nb_rx_data; + uint16_t rxdatacount; + uint32_t isrflags = READ_REG(huart->Instance->ISR); + 8006a3a: 687b ldr r3, [r7, #4] + 8006a3c: 681b ldr r3, [r3, #0] + 8006a3e: 69db ldr r3, [r3, #28] + 8006a40: f8c7 30ac str.w r3, [r7, #172] @ 0xac + uint32_t cr1its = READ_REG(huart->Instance->CR1); + 8006a44: 687b ldr r3, [r7, #4] + 8006a46: 681b ldr r3, [r3, #0] + 8006a48: 681b ldr r3, [r3, #0] + 8006a4a: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4 + uint32_t cr3its = READ_REG(huart->Instance->CR3); + 8006a4e: 687b ldr r3, [r7, #4] + 8006a50: 681b ldr r3, [r3, #0] + 8006a52: 689b ldr r3, [r3, #8] + 8006a54: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0 + + /* Check that a Rx process is ongoing */ + if (huart->RxState == HAL_UART_STATE_BUSY_RX) + 8006a58: 687b ldr r3, [r7, #4] + 8006a5a: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c + 8006a5e: 2b22 cmp r3, #34 @ 0x22 + 8006a60: f040 8183 bne.w 8006d6a + { + nb_rx_data = huart->NbRxDataToProcess; + 8006a64: 687b ldr r3, [r7, #4] + 8006a66: f8b3 3068 ldrh.w r3, [r3, #104] @ 0x68 + 8006a6a: f8a7 309e strh.w r3, [r7, #158] @ 0x9e + while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U)) + 8006a6e: e126 b.n 8006cbe + { + uhdata = (uint16_t) READ_REG(huart->Instance->RDR); + 8006a70: 687b ldr r3, [r7, #4] + 8006a72: 681b ldr r3, [r3, #0] + 8006a74: 6a5b ldr r3, [r3, #36] @ 0x24 + 8006a76: f8a7 309c strh.w r3, [r7, #156] @ 0x9c + *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask); + 8006a7a: f8b7 309c ldrh.w r3, [r7, #156] @ 0x9c + 8006a7e: b2d9 uxtb r1, r3 + 8006a80: f8b7 30aa ldrh.w r3, [r7, #170] @ 0xaa + 8006a84: b2da uxtb r2, r3 + 8006a86: 687b ldr r3, [r7, #4] + 8006a88: 6d9b ldr r3, [r3, #88] @ 0x58 + 8006a8a: 400a ands r2, r1 + 8006a8c: b2d2 uxtb r2, r2 + 8006a8e: 701a strb r2, [r3, #0] + huart->pRxBuffPtr++; + 8006a90: 687b ldr r3, [r7, #4] + 8006a92: 6d9b ldr r3, [r3, #88] @ 0x58 + 8006a94: 1c5a adds r2, r3, #1 + 8006a96: 687b ldr r3, [r7, #4] + 8006a98: 659a str r2, [r3, #88] @ 0x58 + huart->RxXferCount--; + 8006a9a: 687b ldr r3, [r7, #4] + 8006a9c: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e + 8006aa0: b29b uxth r3, r3 + 8006aa2: 3b01 subs r3, #1 + 8006aa4: b29a uxth r2, r3 + 8006aa6: 687b ldr r3, [r7, #4] + 8006aa8: f8a3 205e strh.w r2, [r3, #94] @ 0x5e + isrflags = READ_REG(huart->Instance->ISR); + 8006aac: 687b ldr r3, [r7, #4] + 8006aae: 681b ldr r3, [r3, #0] + 8006ab0: 69db ldr r3, [r3, #28] + 8006ab2: f8c7 30ac str.w r3, [r7, #172] @ 0xac + + /* If some non blocking errors occurred */ + if ((isrflags & (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE)) != 0U) + 8006ab6: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac + 8006aba: f003 0307 and.w r3, r3, #7 + 8006abe: 2b00 cmp r3, #0 + 8006ac0: d053 beq.n 8006b6a + { + /* UART parity error interrupt occurred -------------------------------------*/ + if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) + 8006ac2: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac + 8006ac6: f003 0301 and.w r3, r3, #1 + 8006aca: 2b00 cmp r3, #0 + 8006acc: d011 beq.n 8006af2 + 8006ace: f8d7 30a4 ldr.w r3, [r7, #164] @ 0xa4 + 8006ad2: f403 7380 and.w r3, r3, #256 @ 0x100 + 8006ad6: 2b00 cmp r3, #0 + 8006ad8: d00b beq.n 8006af2 + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF); + 8006ada: 687b ldr r3, [r7, #4] + 8006adc: 681b ldr r3, [r3, #0] + 8006ade: 2201 movs r2, #1 + 8006ae0: 621a str r2, [r3, #32] + + huart->ErrorCode |= HAL_UART_ERROR_PE; + 8006ae2: 687b ldr r3, [r7, #4] + 8006ae4: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 8006ae8: f043 0201 orr.w r2, r3, #1 + 8006aec: 687b ldr r3, [r7, #4] + 8006aee: f8c3 2090 str.w r2, [r3, #144] @ 0x90 + } + + /* UART frame error interrupt occurred --------------------------------------*/ + if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) + 8006af2: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac + 8006af6: f003 0302 and.w r3, r3, #2 + 8006afa: 2b00 cmp r3, #0 + 8006afc: d011 beq.n 8006b22 + 8006afe: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0 + 8006b02: f003 0301 and.w r3, r3, #1 + 8006b06: 2b00 cmp r3, #0 + 8006b08: d00b beq.n 8006b22 + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF); + 8006b0a: 687b ldr r3, [r7, #4] + 8006b0c: 681b ldr r3, [r3, #0] + 8006b0e: 2202 movs r2, #2 + 8006b10: 621a str r2, [r3, #32] + + huart->ErrorCode |= HAL_UART_ERROR_FE; + 8006b12: 687b ldr r3, [r7, #4] + 8006b14: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 8006b18: f043 0204 orr.w r2, r3, #4 + 8006b1c: 687b ldr r3, [r7, #4] + 8006b1e: f8c3 2090 str.w r2, [r3, #144] @ 0x90 + } + + /* UART noise error interrupt occurred --------------------------------------*/ + if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) + 8006b22: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac + 8006b26: f003 0304 and.w r3, r3, #4 + 8006b2a: 2b00 cmp r3, #0 + 8006b2c: d011 beq.n 8006b52 + 8006b2e: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0 + 8006b32: f003 0301 and.w r3, r3, #1 + 8006b36: 2b00 cmp r3, #0 + 8006b38: d00b beq.n 8006b52 + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF); + 8006b3a: 687b ldr r3, [r7, #4] + 8006b3c: 681b ldr r3, [r3, #0] + 8006b3e: 2204 movs r2, #4 + 8006b40: 621a str r2, [r3, #32] + + huart->ErrorCode |= HAL_UART_ERROR_NE; + 8006b42: 687b ldr r3, [r7, #4] + 8006b44: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 8006b48: f043 0202 orr.w r2, r3, #2 + 8006b4c: 687b ldr r3, [r7, #4] + 8006b4e: f8c3 2090 str.w r2, [r3, #144] @ 0x90 + } + + /* Call UART Error Call back function if need be ----------------------------*/ + if (huart->ErrorCode != HAL_UART_ERROR_NONE) + 8006b52: 687b ldr r3, [r7, #4] + 8006b54: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 8006b58: 2b00 cmp r3, #0 + 8006b5a: d006 beq.n 8006b6a +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); + 8006b5c: 6878 ldr r0, [r7, #4] + 8006b5e: f7fe fedc bl 800591a +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + 8006b62: 687b ldr r3, [r7, #4] + 8006b64: 2200 movs r2, #0 + 8006b66: f8c3 2090 str.w r2, [r3, #144] @ 0x90 + } + } + + if (huart->RxXferCount == 0U) + 8006b6a: 687b ldr r3, [r7, #4] + 8006b6c: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e + 8006b70: b29b uxth r3, r3 + 8006b72: 2b00 cmp r3, #0 + 8006b74: f040 80a3 bne.w 8006cbe + { + /* Disable the UART Parity Error Interrupt and RXFT interrupt*/ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); + 8006b78: 687b ldr r3, [r7, #4] + 8006b7a: 681b ldr r3, [r3, #0] + 8006b7c: 673b str r3, [r7, #112] @ 0x70 + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 8006b7e: 6f3b ldr r3, [r7, #112] @ 0x70 + 8006b80: e853 3f00 ldrex r3, [r3] + 8006b84: 66fb str r3, [r7, #108] @ 0x6c + return(result); + 8006b86: 6efb ldr r3, [r7, #108] @ 0x6c + 8006b88: f423 7380 bic.w r3, r3, #256 @ 0x100 + 8006b8c: f8c7 3098 str.w r3, [r7, #152] @ 0x98 + 8006b90: 687b ldr r3, [r7, #4] + 8006b92: 681b ldr r3, [r3, #0] + 8006b94: 461a mov r2, r3 + 8006b96: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98 + 8006b9a: 67fb str r3, [r7, #124] @ 0x7c + 8006b9c: 67ba str r2, [r7, #120] @ 0x78 + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 8006b9e: 6fb9 ldr r1, [r7, #120] @ 0x78 + 8006ba0: 6ffa ldr r2, [r7, #124] @ 0x7c + 8006ba2: e841 2300 strex r3, r2, [r1] + 8006ba6: 677b str r3, [r7, #116] @ 0x74 + return(result); + 8006ba8: 6f7b ldr r3, [r7, #116] @ 0x74 + 8006baa: 2b00 cmp r3, #0 + 8006bac: d1e4 bne.n 8006b78 + + /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) + and RX FIFO Threshold interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); + 8006bae: 687b ldr r3, [r7, #4] + 8006bb0: 681b ldr r3, [r3, #0] + 8006bb2: 3308 adds r3, #8 + 8006bb4: 65fb str r3, [r7, #92] @ 0x5c + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 8006bb6: 6dfb ldr r3, [r7, #92] @ 0x5c + 8006bb8: e853 3f00 ldrex r3, [r3] + 8006bbc: 65bb str r3, [r7, #88] @ 0x58 + return(result); + 8006bbe: 6dbb ldr r3, [r7, #88] @ 0x58 + 8006bc0: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 + 8006bc4: f023 0301 bic.w r3, r3, #1 + 8006bc8: f8c7 3094 str.w r3, [r7, #148] @ 0x94 + 8006bcc: 687b ldr r3, [r7, #4] + 8006bce: 681b ldr r3, [r3, #0] + 8006bd0: 3308 adds r3, #8 + 8006bd2: f8d7 2094 ldr.w r2, [r7, #148] @ 0x94 + 8006bd6: 66ba str r2, [r7, #104] @ 0x68 + 8006bd8: 667b str r3, [r7, #100] @ 0x64 + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 8006bda: 6e79 ldr r1, [r7, #100] @ 0x64 + 8006bdc: 6eba ldr r2, [r7, #104] @ 0x68 + 8006bde: e841 2300 strex r3, r2, [r1] + 8006be2: 663b str r3, [r7, #96] @ 0x60 + return(result); + 8006be4: 6e3b ldr r3, [r7, #96] @ 0x60 + 8006be6: 2b00 cmp r3, #0 + 8006be8: d1e1 bne.n 8006bae + + /* Rx process is completed, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + 8006bea: 687b ldr r3, [r7, #4] + 8006bec: 2220 movs r2, #32 + 8006bee: f8c3 208c str.w r2, [r3, #140] @ 0x8c + + /* Clear RxISR function pointer */ + huart->RxISR = NULL; + 8006bf2: 687b ldr r3, [r7, #4] + 8006bf4: 2200 movs r2, #0 + 8006bf6: 675a str r2, [r3, #116] @ 0x74 + + /* Initialize type of RxEvent to Transfer Complete */ + huart->RxEventType = HAL_UART_RXEVENT_TC; + 8006bf8: 687b ldr r3, [r7, #4] + 8006bfa: 2200 movs r2, #0 + 8006bfc: 671a str r2, [r3, #112] @ 0x70 + + if (!(IS_LPUART_INSTANCE(huart->Instance))) + 8006bfe: 687b ldr r3, [r7, #4] + 8006c00: 681b ldr r3, [r3, #0] + 8006c02: 4a60 ldr r2, [pc, #384] @ (8006d84 ) + 8006c04: 4293 cmp r3, r2 + 8006c06: d021 beq.n 8006c4c + { + /* Check that USART RTOEN bit is set */ + if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) + 8006c08: 687b ldr r3, [r7, #4] + 8006c0a: 681b ldr r3, [r3, #0] + 8006c0c: 685b ldr r3, [r3, #4] + 8006c0e: f403 0300 and.w r3, r3, #8388608 @ 0x800000 + 8006c12: 2b00 cmp r3, #0 + 8006c14: d01a beq.n 8006c4c + { + /* Enable the UART Receiver Timeout Interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); + 8006c16: 687b ldr r3, [r7, #4] + 8006c18: 681b ldr r3, [r3, #0] + 8006c1a: 64bb str r3, [r7, #72] @ 0x48 + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 8006c1c: 6cbb ldr r3, [r7, #72] @ 0x48 + 8006c1e: e853 3f00 ldrex r3, [r3] + 8006c22: 647b str r3, [r7, #68] @ 0x44 + return(result); + 8006c24: 6c7b ldr r3, [r7, #68] @ 0x44 + 8006c26: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000 + 8006c2a: f8c7 3090 str.w r3, [r7, #144] @ 0x90 + 8006c2e: 687b ldr r3, [r7, #4] + 8006c30: 681b ldr r3, [r3, #0] + 8006c32: 461a mov r2, r3 + 8006c34: f8d7 3090 ldr.w r3, [r7, #144] @ 0x90 + 8006c38: 657b str r3, [r7, #84] @ 0x54 + 8006c3a: 653a str r2, [r7, #80] @ 0x50 + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 8006c3c: 6d39 ldr r1, [r7, #80] @ 0x50 + 8006c3e: 6d7a ldr r2, [r7, #84] @ 0x54 + 8006c40: e841 2300 strex r3, r2, [r1] + 8006c44: 64fb str r3, [r7, #76] @ 0x4c + return(result); + 8006c46: 6cfb ldr r3, [r7, #76] @ 0x4c + 8006c48: 2b00 cmp r3, #0 + 8006c4a: d1e4 bne.n 8006c16 + } + } + + /* Check current reception Mode : + If Reception till IDLE event has been selected : */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + 8006c4c: 687b ldr r3, [r7, #4] + 8006c4e: 6edb ldr r3, [r3, #108] @ 0x6c + 8006c50: 2b01 cmp r3, #1 + 8006c52: d130 bne.n 8006cb6 + { + /* Set reception type to Standard */ + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + 8006c54: 687b ldr r3, [r7, #4] + 8006c56: 2200 movs r2, #0 + 8006c58: 66da str r2, [r3, #108] @ 0x6c + + /* Disable IDLE interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + 8006c5a: 687b ldr r3, [r7, #4] + 8006c5c: 681b ldr r3, [r3, #0] + 8006c5e: 637b str r3, [r7, #52] @ 0x34 + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 8006c60: 6b7b ldr r3, [r7, #52] @ 0x34 + 8006c62: e853 3f00 ldrex r3, [r3] + 8006c66: 633b str r3, [r7, #48] @ 0x30 + return(result); + 8006c68: 6b3b ldr r3, [r7, #48] @ 0x30 + 8006c6a: f023 0310 bic.w r3, r3, #16 + 8006c6e: f8c7 308c str.w r3, [r7, #140] @ 0x8c + 8006c72: 687b ldr r3, [r7, #4] + 8006c74: 681b ldr r3, [r3, #0] + 8006c76: 461a mov r2, r3 + 8006c78: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c + 8006c7c: 643b str r3, [r7, #64] @ 0x40 + 8006c7e: 63fa str r2, [r7, #60] @ 0x3c + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 8006c80: 6bf9 ldr r1, [r7, #60] @ 0x3c + 8006c82: 6c3a ldr r2, [r7, #64] @ 0x40 + 8006c84: e841 2300 strex r3, r2, [r1] + 8006c88: 63bb str r3, [r7, #56] @ 0x38 + return(result); + 8006c8a: 6bbb ldr r3, [r7, #56] @ 0x38 + 8006c8c: 2b00 cmp r3, #0 + 8006c8e: d1e4 bne.n 8006c5a + + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) + 8006c90: 687b ldr r3, [r7, #4] + 8006c92: 681b ldr r3, [r3, #0] + 8006c94: 69db ldr r3, [r3, #28] + 8006c96: f003 0310 and.w r3, r3, #16 + 8006c9a: 2b10 cmp r3, #16 + 8006c9c: d103 bne.n 8006ca6 + { + /* Clear IDLE Flag */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + 8006c9e: 687b ldr r3, [r7, #4] + 8006ca0: 681b ldr r3, [r3, #0] + 8006ca2: 2210 movs r2, #16 + 8006ca4: 621a str r2, [r3, #32] +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, huart->RxXferSize); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); + 8006ca6: 687b ldr r3, [r7, #4] + 8006ca8: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c + 8006cac: 4619 mov r1, r3 + 8006cae: 6878 ldr r0, [r7, #4] + 8006cb0: f7fe fe3c bl 800592c +#else + /*Call legacy weak Rx complete callback*/ + HAL_UART_RxCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + break; + 8006cb4: e00e b.n 8006cd4 + HAL_UART_RxCpltCallback(huart); + 8006cb6: 6878 ldr r0, [r7, #4] + 8006cb8: f7fa fc4a bl 8001550 + break; + 8006cbc: e00a b.n 8006cd4 + while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U)) + 8006cbe: f8b7 309e ldrh.w r3, [r7, #158] @ 0x9e + 8006cc2: 2b00 cmp r3, #0 + 8006cc4: d006 beq.n 8006cd4 + 8006cc6: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac + 8006cca: f003 0320 and.w r3, r3, #32 + 8006cce: 2b00 cmp r3, #0 + 8006cd0: f47f aece bne.w 8006a70 + + /* When remaining number of bytes to receive is less than the RX FIFO + threshold, next incoming frames are processed as if FIFO mode was + disabled (i.e. one interrupt per received frame). + */ + rxdatacount = huart->RxXferCount; + 8006cd4: 687b ldr r3, [r7, #4] + 8006cd6: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e + 8006cda: f8a7 308a strh.w r3, [r7, #138] @ 0x8a + if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess)) + 8006cde: f8b7 308a ldrh.w r3, [r7, #138] @ 0x8a + 8006ce2: 2b00 cmp r3, #0 + 8006ce4: d049 beq.n 8006d7a + 8006ce6: 687b ldr r3, [r7, #4] + 8006ce8: f8b3 3068 ldrh.w r3, [r3, #104] @ 0x68 + 8006cec: f8b7 208a ldrh.w r2, [r7, #138] @ 0x8a + 8006cf0: 429a cmp r2, r3 + 8006cf2: d242 bcs.n 8006d7a + { + /* Disable the UART RXFT interrupt*/ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); + 8006cf4: 687b ldr r3, [r7, #4] + 8006cf6: 681b ldr r3, [r3, #0] + 8006cf8: 3308 adds r3, #8 + 8006cfa: 623b str r3, [r7, #32] + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 8006cfc: 6a3b ldr r3, [r7, #32] + 8006cfe: e853 3f00 ldrex r3, [r3] + 8006d02: 61fb str r3, [r7, #28] + return(result); + 8006d04: 69fb ldr r3, [r7, #28] + 8006d06: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 + 8006d0a: f8c7 3084 str.w r3, [r7, #132] @ 0x84 + 8006d0e: 687b ldr r3, [r7, #4] + 8006d10: 681b ldr r3, [r3, #0] + 8006d12: 3308 adds r3, #8 + 8006d14: f8d7 2084 ldr.w r2, [r7, #132] @ 0x84 + 8006d18: 62fa str r2, [r7, #44] @ 0x2c + 8006d1a: 62bb str r3, [r7, #40] @ 0x28 + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 8006d1c: 6ab9 ldr r1, [r7, #40] @ 0x28 + 8006d1e: 6afa ldr r2, [r7, #44] @ 0x2c + 8006d20: e841 2300 strex r3, r2, [r1] + 8006d24: 627b str r3, [r7, #36] @ 0x24 + return(result); + 8006d26: 6a7b ldr r3, [r7, #36] @ 0x24 + 8006d28: 2b00 cmp r3, #0 + 8006d2a: d1e3 bne.n 8006cf4 + + /* Update the RxISR function pointer */ + huart->RxISR = UART_RxISR_8BIT; + 8006d2c: 687b ldr r3, [r7, #4] + 8006d2e: 4a16 ldr r2, [pc, #88] @ (8006d88 ) + 8006d30: 675a str r2, [r3, #116] @ 0x74 + + /* Enable the UART Data Register Not Empty interrupt */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); + 8006d32: 687b ldr r3, [r7, #4] + 8006d34: 681b ldr r3, [r3, #0] + 8006d36: 60fb str r3, [r7, #12] + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 8006d38: 68fb ldr r3, [r7, #12] + 8006d3a: e853 3f00 ldrex r3, [r3] + 8006d3e: 60bb str r3, [r7, #8] + return(result); + 8006d40: 68bb ldr r3, [r7, #8] + 8006d42: f043 0320 orr.w r3, r3, #32 + 8006d46: f8c7 3080 str.w r3, [r7, #128] @ 0x80 + 8006d4a: 687b ldr r3, [r7, #4] + 8006d4c: 681b ldr r3, [r3, #0] + 8006d4e: 461a mov r2, r3 + 8006d50: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80 + 8006d54: 61bb str r3, [r7, #24] + 8006d56: 617a str r2, [r7, #20] + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 8006d58: 6979 ldr r1, [r7, #20] + 8006d5a: 69ba ldr r2, [r7, #24] + 8006d5c: e841 2300 strex r3, r2, [r1] + 8006d60: 613b str r3, [r7, #16] + return(result); + 8006d62: 693b ldr r3, [r7, #16] + 8006d64: 2b00 cmp r3, #0 + 8006d66: d1e4 bne.n 8006d32 + else + { + /* Clear RXNE interrupt flag */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + } +} + 8006d68: e007 b.n 8006d7a + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + 8006d6a: 687b ldr r3, [r7, #4] + 8006d6c: 681b ldr r3, [r3, #0] + 8006d6e: 699a ldr r2, [r3, #24] + 8006d70: 687b ldr r3, [r7, #4] + 8006d72: 681b ldr r3, [r3, #0] + 8006d74: f042 0208 orr.w r2, r2, #8 + 8006d78: 619a str r2, [r3, #24] +} + 8006d7a: bf00 nop + 8006d7c: 37b0 adds r7, #176 @ 0xb0 + 8006d7e: 46bd mov sp, r7 + 8006d80: bd80 pop {r7, pc} + 8006d82: bf00 nop + 8006d84: 40008000 .word 0x40008000 + 8006d88: 080066b9 .word 0x080066b9 + +08006d8c : + * interruptions have been enabled by HAL_UART_Receive_IT() + * @param huart UART handle. + * @retval None + */ +static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) +{ + 8006d8c: b580 push {r7, lr} + 8006d8e: b0ae sub sp, #184 @ 0xb8 + 8006d90: af00 add r7, sp, #0 + 8006d92: 6078 str r0, [r7, #4] + uint16_t *tmp; + uint16_t uhMask = huart->Mask; + 8006d94: 687b ldr r3, [r7, #4] + 8006d96: f8b3 3060 ldrh.w r3, [r3, #96] @ 0x60 + 8006d9a: f8a7 30b2 strh.w r3, [r7, #178] @ 0xb2 + uint16_t uhdata; + uint16_t nb_rx_data; + uint16_t rxdatacount; + uint32_t isrflags = READ_REG(huart->Instance->ISR); + 8006d9e: 687b ldr r3, [r7, #4] + 8006da0: 681b ldr r3, [r3, #0] + 8006da2: 69db ldr r3, [r3, #28] + 8006da4: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 + uint32_t cr1its = READ_REG(huart->Instance->CR1); + 8006da8: 687b ldr r3, [r7, #4] + 8006daa: 681b ldr r3, [r3, #0] + 8006dac: 681b ldr r3, [r3, #0] + 8006dae: f8c7 30ac str.w r3, [r7, #172] @ 0xac + uint32_t cr3its = READ_REG(huart->Instance->CR3); + 8006db2: 687b ldr r3, [r7, #4] + 8006db4: 681b ldr r3, [r3, #0] + 8006db6: 689b ldr r3, [r3, #8] + 8006db8: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8 + + /* Check that a Rx process is ongoing */ + if (huart->RxState == HAL_UART_STATE_BUSY_RX) + 8006dbc: 687b ldr r3, [r7, #4] + 8006dbe: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c + 8006dc2: 2b22 cmp r3, #34 @ 0x22 + 8006dc4: f040 8187 bne.w 80070d6 + { + nb_rx_data = huart->NbRxDataToProcess; + 8006dc8: 687b ldr r3, [r7, #4] + 8006dca: f8b3 3068 ldrh.w r3, [r3, #104] @ 0x68 + 8006dce: f8a7 30a6 strh.w r3, [r7, #166] @ 0xa6 + while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U)) + 8006dd2: e12a b.n 800702a + { + uhdata = (uint16_t) READ_REG(huart->Instance->RDR); + 8006dd4: 687b ldr r3, [r7, #4] + 8006dd6: 681b ldr r3, [r3, #0] + 8006dd8: 6a5b ldr r3, [r3, #36] @ 0x24 + 8006dda: f8a7 30a4 strh.w r3, [r7, #164] @ 0xa4 + tmp = (uint16_t *) huart->pRxBuffPtr ; + 8006dde: 687b ldr r3, [r7, #4] + 8006de0: 6d9b ldr r3, [r3, #88] @ 0x58 + 8006de2: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0 + *tmp = (uint16_t)(uhdata & uhMask); + 8006de6: f8b7 20a4 ldrh.w r2, [r7, #164] @ 0xa4 + 8006dea: f8b7 30b2 ldrh.w r3, [r7, #178] @ 0xb2 + 8006dee: 4013 ands r3, r2 + 8006df0: b29a uxth r2, r3 + 8006df2: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0 + 8006df6: 801a strh r2, [r3, #0] + huart->pRxBuffPtr += 2U; + 8006df8: 687b ldr r3, [r7, #4] + 8006dfa: 6d9b ldr r3, [r3, #88] @ 0x58 + 8006dfc: 1c9a adds r2, r3, #2 + 8006dfe: 687b ldr r3, [r7, #4] + 8006e00: 659a str r2, [r3, #88] @ 0x58 + huart->RxXferCount--; + 8006e02: 687b ldr r3, [r7, #4] + 8006e04: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e + 8006e08: b29b uxth r3, r3 + 8006e0a: 3b01 subs r3, #1 + 8006e0c: b29a uxth r2, r3 + 8006e0e: 687b ldr r3, [r7, #4] + 8006e10: f8a3 205e strh.w r2, [r3, #94] @ 0x5e + isrflags = READ_REG(huart->Instance->ISR); + 8006e14: 687b ldr r3, [r7, #4] + 8006e16: 681b ldr r3, [r3, #0] + 8006e18: 69db ldr r3, [r3, #28] + 8006e1a: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 + + /* If some non blocking errors occurred */ + if ((isrflags & (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE)) != 0U) + 8006e1e: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4 + 8006e22: f003 0307 and.w r3, r3, #7 + 8006e26: 2b00 cmp r3, #0 + 8006e28: d053 beq.n 8006ed2 + { + /* UART parity error interrupt occurred -------------------------------------*/ + if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) + 8006e2a: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4 + 8006e2e: f003 0301 and.w r3, r3, #1 + 8006e32: 2b00 cmp r3, #0 + 8006e34: d011 beq.n 8006e5a + 8006e36: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac + 8006e3a: f403 7380 and.w r3, r3, #256 @ 0x100 + 8006e3e: 2b00 cmp r3, #0 + 8006e40: d00b beq.n 8006e5a + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF); + 8006e42: 687b ldr r3, [r7, #4] + 8006e44: 681b ldr r3, [r3, #0] + 8006e46: 2201 movs r2, #1 + 8006e48: 621a str r2, [r3, #32] + + huart->ErrorCode |= HAL_UART_ERROR_PE; + 8006e4a: 687b ldr r3, [r7, #4] + 8006e4c: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 8006e50: f043 0201 orr.w r2, r3, #1 + 8006e54: 687b ldr r3, [r7, #4] + 8006e56: f8c3 2090 str.w r2, [r3, #144] @ 0x90 + } + + /* UART frame error interrupt occurred --------------------------------------*/ + if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) + 8006e5a: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4 + 8006e5e: f003 0302 and.w r3, r3, #2 + 8006e62: 2b00 cmp r3, #0 + 8006e64: d011 beq.n 8006e8a + 8006e66: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8 + 8006e6a: f003 0301 and.w r3, r3, #1 + 8006e6e: 2b00 cmp r3, #0 + 8006e70: d00b beq.n 8006e8a + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF); + 8006e72: 687b ldr r3, [r7, #4] + 8006e74: 681b ldr r3, [r3, #0] + 8006e76: 2202 movs r2, #2 + 8006e78: 621a str r2, [r3, #32] + + huart->ErrorCode |= HAL_UART_ERROR_FE; + 8006e7a: 687b ldr r3, [r7, #4] + 8006e7c: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 8006e80: f043 0204 orr.w r2, r3, #4 + 8006e84: 687b ldr r3, [r7, #4] + 8006e86: f8c3 2090 str.w r2, [r3, #144] @ 0x90 + } + + /* UART noise error interrupt occurred --------------------------------------*/ + if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) + 8006e8a: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4 + 8006e8e: f003 0304 and.w r3, r3, #4 + 8006e92: 2b00 cmp r3, #0 + 8006e94: d011 beq.n 8006eba + 8006e96: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8 + 8006e9a: f003 0301 and.w r3, r3, #1 + 8006e9e: 2b00 cmp r3, #0 + 8006ea0: d00b beq.n 8006eba + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF); + 8006ea2: 687b ldr r3, [r7, #4] + 8006ea4: 681b ldr r3, [r3, #0] + 8006ea6: 2204 movs r2, #4 + 8006ea8: 621a str r2, [r3, #32] + + huart->ErrorCode |= HAL_UART_ERROR_NE; + 8006eaa: 687b ldr r3, [r7, #4] + 8006eac: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 8006eb0: f043 0202 orr.w r2, r3, #2 + 8006eb4: 687b ldr r3, [r7, #4] + 8006eb6: f8c3 2090 str.w r2, [r3, #144] @ 0x90 + } + + /* Call UART Error Call back function if need be ----------------------------*/ + if (huart->ErrorCode != HAL_UART_ERROR_NONE) + 8006eba: 687b ldr r3, [r7, #4] + 8006ebc: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 8006ec0: 2b00 cmp r3, #0 + 8006ec2: d006 beq.n 8006ed2 +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); + 8006ec4: 6878 ldr r0, [r7, #4] + 8006ec6: f7fe fd28 bl 800591a +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + 8006eca: 687b ldr r3, [r7, #4] + 8006ecc: 2200 movs r2, #0 + 8006ece: f8c3 2090 str.w r2, [r3, #144] @ 0x90 + } + } + + if (huart->RxXferCount == 0U) + 8006ed2: 687b ldr r3, [r7, #4] + 8006ed4: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e + 8006ed8: b29b uxth r3, r3 + 8006eda: 2b00 cmp r3, #0 + 8006edc: f040 80a5 bne.w 800702a + { + /* Disable the UART Parity Error Interrupt and RXFT interrupt*/ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); + 8006ee0: 687b ldr r3, [r7, #4] + 8006ee2: 681b ldr r3, [r3, #0] + 8006ee4: 677b str r3, [r7, #116] @ 0x74 + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 8006ee6: 6f7b ldr r3, [r7, #116] @ 0x74 + 8006ee8: e853 3f00 ldrex r3, [r3] + 8006eec: 673b str r3, [r7, #112] @ 0x70 + return(result); + 8006eee: 6f3b ldr r3, [r7, #112] @ 0x70 + 8006ef0: f423 7380 bic.w r3, r3, #256 @ 0x100 + 8006ef4: f8c7 309c str.w r3, [r7, #156] @ 0x9c + 8006ef8: 687b ldr r3, [r7, #4] + 8006efa: 681b ldr r3, [r3, #0] + 8006efc: 461a mov r2, r3 + 8006efe: f8d7 309c ldr.w r3, [r7, #156] @ 0x9c + 8006f02: f8c7 3080 str.w r3, [r7, #128] @ 0x80 + 8006f06: 67fa str r2, [r7, #124] @ 0x7c + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 8006f08: 6ff9 ldr r1, [r7, #124] @ 0x7c + 8006f0a: f8d7 2080 ldr.w r2, [r7, #128] @ 0x80 + 8006f0e: e841 2300 strex r3, r2, [r1] + 8006f12: 67bb str r3, [r7, #120] @ 0x78 + return(result); + 8006f14: 6fbb ldr r3, [r7, #120] @ 0x78 + 8006f16: 2b00 cmp r3, #0 + 8006f18: d1e2 bne.n 8006ee0 + + /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) + and RX FIFO Threshold interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); + 8006f1a: 687b ldr r3, [r7, #4] + 8006f1c: 681b ldr r3, [r3, #0] + 8006f1e: 3308 adds r3, #8 + 8006f20: 663b str r3, [r7, #96] @ 0x60 + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 8006f22: 6e3b ldr r3, [r7, #96] @ 0x60 + 8006f24: e853 3f00 ldrex r3, [r3] + 8006f28: 65fb str r3, [r7, #92] @ 0x5c + return(result); + 8006f2a: 6dfb ldr r3, [r7, #92] @ 0x5c + 8006f2c: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 + 8006f30: f023 0301 bic.w r3, r3, #1 + 8006f34: f8c7 3098 str.w r3, [r7, #152] @ 0x98 + 8006f38: 687b ldr r3, [r7, #4] + 8006f3a: 681b ldr r3, [r3, #0] + 8006f3c: 3308 adds r3, #8 + 8006f3e: f8d7 2098 ldr.w r2, [r7, #152] @ 0x98 + 8006f42: 66fa str r2, [r7, #108] @ 0x6c + 8006f44: 66bb str r3, [r7, #104] @ 0x68 + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 8006f46: 6eb9 ldr r1, [r7, #104] @ 0x68 + 8006f48: 6efa ldr r2, [r7, #108] @ 0x6c + 8006f4a: e841 2300 strex r3, r2, [r1] + 8006f4e: 667b str r3, [r7, #100] @ 0x64 + return(result); + 8006f50: 6e7b ldr r3, [r7, #100] @ 0x64 + 8006f52: 2b00 cmp r3, #0 + 8006f54: d1e1 bne.n 8006f1a + + /* Rx process is completed, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + 8006f56: 687b ldr r3, [r7, #4] + 8006f58: 2220 movs r2, #32 + 8006f5a: f8c3 208c str.w r2, [r3, #140] @ 0x8c + + /* Clear RxISR function pointer */ + huart->RxISR = NULL; + 8006f5e: 687b ldr r3, [r7, #4] + 8006f60: 2200 movs r2, #0 + 8006f62: 675a str r2, [r3, #116] @ 0x74 + + /* Initialize type of RxEvent to Transfer Complete */ + huart->RxEventType = HAL_UART_RXEVENT_TC; + 8006f64: 687b ldr r3, [r7, #4] + 8006f66: 2200 movs r2, #0 + 8006f68: 671a str r2, [r3, #112] @ 0x70 + + if (!(IS_LPUART_INSTANCE(huart->Instance))) + 8006f6a: 687b ldr r3, [r7, #4] + 8006f6c: 681b ldr r3, [r3, #0] + 8006f6e: 4a60 ldr r2, [pc, #384] @ (80070f0 ) + 8006f70: 4293 cmp r3, r2 + 8006f72: d021 beq.n 8006fb8 + { + /* Check that USART RTOEN bit is set */ + if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) + 8006f74: 687b ldr r3, [r7, #4] + 8006f76: 681b ldr r3, [r3, #0] + 8006f78: 685b ldr r3, [r3, #4] + 8006f7a: f403 0300 and.w r3, r3, #8388608 @ 0x800000 + 8006f7e: 2b00 cmp r3, #0 + 8006f80: d01a beq.n 8006fb8 + { + /* Enable the UART Receiver Timeout Interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); + 8006f82: 687b ldr r3, [r7, #4] + 8006f84: 681b ldr r3, [r3, #0] + 8006f86: 64fb str r3, [r7, #76] @ 0x4c + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 8006f88: 6cfb ldr r3, [r7, #76] @ 0x4c + 8006f8a: e853 3f00 ldrex r3, [r3] + 8006f8e: 64bb str r3, [r7, #72] @ 0x48 + return(result); + 8006f90: 6cbb ldr r3, [r7, #72] @ 0x48 + 8006f92: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000 + 8006f96: f8c7 3094 str.w r3, [r7, #148] @ 0x94 + 8006f9a: 687b ldr r3, [r7, #4] + 8006f9c: 681b ldr r3, [r3, #0] + 8006f9e: 461a mov r2, r3 + 8006fa0: f8d7 3094 ldr.w r3, [r7, #148] @ 0x94 + 8006fa4: 65bb str r3, [r7, #88] @ 0x58 + 8006fa6: 657a str r2, [r7, #84] @ 0x54 + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 8006fa8: 6d79 ldr r1, [r7, #84] @ 0x54 + 8006faa: 6dba ldr r2, [r7, #88] @ 0x58 + 8006fac: e841 2300 strex r3, r2, [r1] + 8006fb0: 653b str r3, [r7, #80] @ 0x50 + return(result); + 8006fb2: 6d3b ldr r3, [r7, #80] @ 0x50 + 8006fb4: 2b00 cmp r3, #0 + 8006fb6: d1e4 bne.n 8006f82 + } + } + + /* Check current reception Mode : + If Reception till IDLE event has been selected : */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + 8006fb8: 687b ldr r3, [r7, #4] + 8006fba: 6edb ldr r3, [r3, #108] @ 0x6c + 8006fbc: 2b01 cmp r3, #1 + 8006fbe: d130 bne.n 8007022 + { + /* Set reception type to Standard */ + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + 8006fc0: 687b ldr r3, [r7, #4] + 8006fc2: 2200 movs r2, #0 + 8006fc4: 66da str r2, [r3, #108] @ 0x6c + + /* Disable IDLE interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + 8006fc6: 687b ldr r3, [r7, #4] + 8006fc8: 681b ldr r3, [r3, #0] + 8006fca: 63bb str r3, [r7, #56] @ 0x38 + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 8006fcc: 6bbb ldr r3, [r7, #56] @ 0x38 + 8006fce: e853 3f00 ldrex r3, [r3] + 8006fd2: 637b str r3, [r7, #52] @ 0x34 + return(result); + 8006fd4: 6b7b ldr r3, [r7, #52] @ 0x34 + 8006fd6: f023 0310 bic.w r3, r3, #16 + 8006fda: f8c7 3090 str.w r3, [r7, #144] @ 0x90 + 8006fde: 687b ldr r3, [r7, #4] + 8006fe0: 681b ldr r3, [r3, #0] + 8006fe2: 461a mov r2, r3 + 8006fe4: f8d7 3090 ldr.w r3, [r7, #144] @ 0x90 + 8006fe8: 647b str r3, [r7, #68] @ 0x44 + 8006fea: 643a str r2, [r7, #64] @ 0x40 + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 8006fec: 6c39 ldr r1, [r7, #64] @ 0x40 + 8006fee: 6c7a ldr r2, [r7, #68] @ 0x44 + 8006ff0: e841 2300 strex r3, r2, [r1] + 8006ff4: 63fb str r3, [r7, #60] @ 0x3c + return(result); + 8006ff6: 6bfb ldr r3, [r7, #60] @ 0x3c + 8006ff8: 2b00 cmp r3, #0 + 8006ffa: d1e4 bne.n 8006fc6 + + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) + 8006ffc: 687b ldr r3, [r7, #4] + 8006ffe: 681b ldr r3, [r3, #0] + 8007000: 69db ldr r3, [r3, #28] + 8007002: f003 0310 and.w r3, r3, #16 + 8007006: 2b10 cmp r3, #16 + 8007008: d103 bne.n 8007012 + { + /* Clear IDLE Flag */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + 800700a: 687b ldr r3, [r7, #4] + 800700c: 681b ldr r3, [r3, #0] + 800700e: 2210 movs r2, #16 + 8007010: 621a str r2, [r3, #32] +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, huart->RxXferSize); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); + 8007012: 687b ldr r3, [r7, #4] + 8007014: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c + 8007018: 4619 mov r1, r3 + 800701a: 6878 ldr r0, [r7, #4] + 800701c: f7fe fc86 bl 800592c +#else + /*Call legacy weak Rx complete callback*/ + HAL_UART_RxCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + break; + 8007020: e00e b.n 8007040 + HAL_UART_RxCpltCallback(huart); + 8007022: 6878 ldr r0, [r7, #4] + 8007024: f7fa fa94 bl 8001550 + break; + 8007028: e00a b.n 8007040 + while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U)) + 800702a: f8b7 30a6 ldrh.w r3, [r7, #166] @ 0xa6 + 800702e: 2b00 cmp r3, #0 + 8007030: d006 beq.n 8007040 + 8007032: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4 + 8007036: f003 0320 and.w r3, r3, #32 + 800703a: 2b00 cmp r3, #0 + 800703c: f47f aeca bne.w 8006dd4 + + /* When remaining number of bytes to receive is less than the RX FIFO + threshold, next incoming frames are processed as if FIFO mode was + disabled (i.e. one interrupt per received frame). + */ + rxdatacount = huart->RxXferCount; + 8007040: 687b ldr r3, [r7, #4] + 8007042: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e + 8007046: f8a7 308e strh.w r3, [r7, #142] @ 0x8e + if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess)) + 800704a: f8b7 308e ldrh.w r3, [r7, #142] @ 0x8e + 800704e: 2b00 cmp r3, #0 + 8007050: d049 beq.n 80070e6 + 8007052: 687b ldr r3, [r7, #4] + 8007054: f8b3 3068 ldrh.w r3, [r3, #104] @ 0x68 + 8007058: f8b7 208e ldrh.w r2, [r7, #142] @ 0x8e + 800705c: 429a cmp r2, r3 + 800705e: d242 bcs.n 80070e6 + { + /* Disable the UART RXFT interrupt*/ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); + 8007060: 687b ldr r3, [r7, #4] + 8007062: 681b ldr r3, [r3, #0] + 8007064: 3308 adds r3, #8 + 8007066: 627b str r3, [r7, #36] @ 0x24 + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 8007068: 6a7b ldr r3, [r7, #36] @ 0x24 + 800706a: e853 3f00 ldrex r3, [r3] + 800706e: 623b str r3, [r7, #32] + return(result); + 8007070: 6a3b ldr r3, [r7, #32] + 8007072: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 + 8007076: f8c7 3088 str.w r3, [r7, #136] @ 0x88 + 800707a: 687b ldr r3, [r7, #4] + 800707c: 681b ldr r3, [r3, #0] + 800707e: 3308 adds r3, #8 + 8007080: f8d7 2088 ldr.w r2, [r7, #136] @ 0x88 + 8007084: 633a str r2, [r7, #48] @ 0x30 + 8007086: 62fb str r3, [r7, #44] @ 0x2c + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 8007088: 6af9 ldr r1, [r7, #44] @ 0x2c + 800708a: 6b3a ldr r2, [r7, #48] @ 0x30 + 800708c: e841 2300 strex r3, r2, [r1] + 8007090: 62bb str r3, [r7, #40] @ 0x28 + return(result); + 8007092: 6abb ldr r3, [r7, #40] @ 0x28 + 8007094: 2b00 cmp r3, #0 + 8007096: d1e3 bne.n 8007060 + + /* Update the RxISR function pointer */ + huart->RxISR = UART_RxISR_16BIT; + 8007098: 687b ldr r3, [r7, #4] + 800709a: 4a16 ldr r2, [pc, #88] @ (80070f4 ) + 800709c: 675a str r2, [r3, #116] @ 0x74 + + /* Enable the UART Data Register Not Empty interrupt */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); + 800709e: 687b ldr r3, [r7, #4] + 80070a0: 681b ldr r3, [r3, #0] + 80070a2: 613b str r3, [r7, #16] + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 80070a4: 693b ldr r3, [r7, #16] + 80070a6: e853 3f00 ldrex r3, [r3] + 80070aa: 60fb str r3, [r7, #12] + return(result); + 80070ac: 68fb ldr r3, [r7, #12] + 80070ae: f043 0320 orr.w r3, r3, #32 + 80070b2: f8c7 3084 str.w r3, [r7, #132] @ 0x84 + 80070b6: 687b ldr r3, [r7, #4] + 80070b8: 681b ldr r3, [r3, #0] + 80070ba: 461a mov r2, r3 + 80070bc: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84 + 80070c0: 61fb str r3, [r7, #28] + 80070c2: 61ba str r2, [r7, #24] + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 80070c4: 69b9 ldr r1, [r7, #24] + 80070c6: 69fa ldr r2, [r7, #28] + 80070c8: e841 2300 strex r3, r2, [r1] + 80070cc: 617b str r3, [r7, #20] + return(result); + 80070ce: 697b ldr r3, [r7, #20] + 80070d0: 2b00 cmp r3, #0 + 80070d2: d1e4 bne.n 800709e + else + { + /* Clear RXNE interrupt flag */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + } +} + 80070d4: e007 b.n 80070e6 + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + 80070d6: 687b ldr r3, [r7, #4] + 80070d8: 681b ldr r3, [r3, #0] + 80070da: 699a ldr r2, [r3, #24] + 80070dc: 687b ldr r3, [r7, #4] + 80070de: 681b ldr r3, [r3, #0] + 80070e0: f042 0208 orr.w r2, r2, #8 + 80070e4: 619a str r2, [r3, #24] +} + 80070e6: bf00 nop + 80070e8: 37b8 adds r7, #184 @ 0xb8 + 80070ea: 46bd mov sp, r7 + 80070ec: bd80 pop {r7, pc} + 80070ee: bf00 nop + 80070f0: 40008000 .word 0x40008000 + 80070f4: 08006871 .word 0x08006871 + +080070f8 : + * @brief UART wakeup from Stop mode callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart) +{ + 80070f8: b480 push {r7} + 80070fa: b083 sub sp, #12 + 80070fc: af00 add r7, sp, #0 + 80070fe: 6078 str r0, [r7, #4] + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UARTEx_WakeupCallback can be implemented in the user file. + */ +} + 8007100: bf00 nop + 8007102: 370c adds r7, #12 + 8007104: 46bd mov sp, r7 + 8007106: bc80 pop {r7} + 8007108: 4770 bx lr + +0800710a : + * @brief UART RX Fifo full callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UARTEx_RxFifoFullCallback(UART_HandleTypeDef *huart) +{ + 800710a: b480 push {r7} + 800710c: b083 sub sp, #12 + 800710e: af00 add r7, sp, #0 + 8007110: 6078 str r0, [r7, #4] + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UARTEx_RxFifoFullCallback can be implemented in the user file. + */ +} + 8007112: bf00 nop + 8007114: 370c adds r7, #12 + 8007116: 46bd mov sp, r7 + 8007118: bc80 pop {r7} + 800711a: 4770 bx lr + +0800711c : + * @brief UART TX Fifo empty callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart) +{ + 800711c: b480 push {r7} + 800711e: b083 sub sp, #12 + 8007120: af00 add r7, sp, #0 + 8007122: 6078 str r0, [r7, #4] + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UARTEx_TxFifoEmptyCallback can be implemented in the user file. + */ +} + 8007124: bf00 nop + 8007126: 370c adds r7, #12 + 8007128: 46bd mov sp, r7 + 800712a: bc80 pop {r7} + 800712c: 4770 bx lr + +0800712e : + * @arg @ref UART_WAKEUP_ON_STARTBIT + * @arg @ref UART_WAKEUP_ON_READDATA_NONEMPTY + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection) +{ + 800712e: b580 push {r7, lr} + 8007130: b088 sub sp, #32 + 8007132: af02 add r7, sp, #8 + 8007134: 60f8 str r0, [r7, #12] + 8007136: 1d3b adds r3, r7, #4 + 8007138: e883 0006 stmia.w r3, {r1, r2} + HAL_StatusTypeDef status = HAL_OK; + 800713c: 2300 movs r3, #0 + 800713e: 75fb strb r3, [r7, #23] + assert_param(IS_UART_WAKEUP_FROMSTOP_INSTANCE(huart->Instance)); + /* check the wake-up selection parameter */ + assert_param(IS_UART_WAKEUP_SELECTION(WakeUpSelection.WakeUpEvent)); + + /* Process Locked */ + __HAL_LOCK(huart); + 8007140: 68fb ldr r3, [r7, #12] + 8007142: f893 3084 ldrb.w r3, [r3, #132] @ 0x84 + 8007146: 2b01 cmp r3, #1 + 8007148: d101 bne.n 800714e + 800714a: 2302 movs r3, #2 + 800714c: e046 b.n 80071dc + 800714e: 68fb ldr r3, [r7, #12] + 8007150: 2201 movs r2, #1 + 8007152: f883 2084 strb.w r2, [r3, #132] @ 0x84 + + huart->gState = HAL_UART_STATE_BUSY; + 8007156: 68fb ldr r3, [r7, #12] + 8007158: 2224 movs r2, #36 @ 0x24 + 800715a: f8c3 2088 str.w r2, [r3, #136] @ 0x88 + + /* Disable the Peripheral */ + __HAL_UART_DISABLE(huart); + 800715e: 68fb ldr r3, [r7, #12] + 8007160: 681b ldr r3, [r3, #0] + 8007162: 681a ldr r2, [r3, #0] + 8007164: 68fb ldr r3, [r7, #12] + 8007166: 681b ldr r3, [r3, #0] + 8007168: f022 0201 bic.w r2, r2, #1 + 800716c: 601a str r2, [r3, #0] + + /* Set the wake-up selection scheme */ + MODIFY_REG(huart->Instance->CR3, USART_CR3_WUS, WakeUpSelection.WakeUpEvent); + 800716e: 68fb ldr r3, [r7, #12] + 8007170: 681b ldr r3, [r3, #0] + 8007172: 689b ldr r3, [r3, #8] + 8007174: f423 1140 bic.w r1, r3, #3145728 @ 0x300000 + 8007178: 687a ldr r2, [r7, #4] + 800717a: 68fb ldr r3, [r7, #12] + 800717c: 681b ldr r3, [r3, #0] + 800717e: 430a orrs r2, r1 + 8007180: 609a str r2, [r3, #8] + + if (WakeUpSelection.WakeUpEvent == UART_WAKEUP_ON_ADDRESS) + 8007182: 687b ldr r3, [r7, #4] + 8007184: 2b00 cmp r3, #0 + 8007186: d105 bne.n 8007194 + { + UARTEx_Wakeup_AddressConfig(huart, WakeUpSelection); + 8007188: 1d3b adds r3, r7, #4 + 800718a: e893 0006 ldmia.w r3, {r1, r2} + 800718e: 68f8 ldr r0, [r7, #12] + 8007190: f000 f911 bl 80073b6 + } + + /* Enable the Peripheral */ + __HAL_UART_ENABLE(huart); + 8007194: 68fb ldr r3, [r7, #12] + 8007196: 681b ldr r3, [r3, #0] + 8007198: 681a ldr r2, [r3, #0] + 800719a: 68fb ldr r3, [r7, #12] + 800719c: 681b ldr r3, [r3, #0] + 800719e: f042 0201 orr.w r2, r2, #1 + 80071a2: 601a str r2, [r3, #0] + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + 80071a4: f7f9 fcec bl 8000b80 + 80071a8: 6138 str r0, [r7, #16] + + /* Wait until REACK flag is set */ + if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) + 80071aa: f06f 437e mvn.w r3, #4261412864 @ 0xfe000000 + 80071ae: 9300 str r3, [sp, #0] + 80071b0: 693b ldr r3, [r7, #16] + 80071b2: 2200 movs r2, #0 + 80071b4: f44f 0180 mov.w r1, #4194304 @ 0x400000 + 80071b8: 68f8 ldr r0, [r7, #12] + 80071ba: f7fe ff82 bl 80060c2 + 80071be: 4603 mov r3, r0 + 80071c0: 2b00 cmp r3, #0 + 80071c2: d002 beq.n 80071ca + { + status = HAL_TIMEOUT; + 80071c4: 2303 movs r3, #3 + 80071c6: 75fb strb r3, [r7, #23] + 80071c8: e003 b.n 80071d2 + } + else + { + /* Initialize the UART State */ + huart->gState = HAL_UART_STATE_READY; + 80071ca: 68fb ldr r3, [r7, #12] + 80071cc: 2220 movs r2, #32 + 80071ce: f8c3 2088 str.w r2, [r3, #136] @ 0x88 + } + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + 80071d2: 68fb ldr r3, [r7, #12] + 80071d4: 2200 movs r2, #0 + 80071d6: f883 2084 strb.w r2, [r3, #132] @ 0x84 + + return status; + 80071da: 7dfb ldrb r3, [r7, #23] +} + 80071dc: 4618 mov r0, r3 + 80071de: 3718 adds r7, #24 + 80071e0: 46bd mov sp, r7 + 80071e2: bd80 pop {r7, pc} + +080071e4 : + * @note The UART is able to wake up the MCU from Stop 1 mode as long as UART clock is HSI or LSE. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart) +{ + 80071e4: b480 push {r7} + 80071e6: b089 sub sp, #36 @ 0x24 + 80071e8: af00 add r7, sp, #0 + 80071ea: 6078 str r0, [r7, #4] + /* Process Locked */ + __HAL_LOCK(huart); + 80071ec: 687b ldr r3, [r7, #4] + 80071ee: f893 3084 ldrb.w r3, [r3, #132] @ 0x84 + 80071f2: 2b01 cmp r3, #1 + 80071f4: d101 bne.n 80071fa + 80071f6: 2302 movs r3, #2 + 80071f8: e021 b.n 800723e + 80071fa: 687b ldr r3, [r7, #4] + 80071fc: 2201 movs r2, #1 + 80071fe: f883 2084 strb.w r2, [r3, #132] @ 0x84 + + /* Set UESM bit */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_UESM); + 8007202: 687b ldr r3, [r7, #4] + 8007204: 681b ldr r3, [r3, #0] + 8007206: 60fb str r3, [r7, #12] + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 8007208: 68fb ldr r3, [r7, #12] + 800720a: e853 3f00 ldrex r3, [r3] + 800720e: 60bb str r3, [r7, #8] + return(result); + 8007210: 68bb ldr r3, [r7, #8] + 8007212: f043 0302 orr.w r3, r3, #2 + 8007216: 61fb str r3, [r7, #28] + 8007218: 687b ldr r3, [r7, #4] + 800721a: 681b ldr r3, [r3, #0] + 800721c: 461a mov r2, r3 + 800721e: 69fb ldr r3, [r7, #28] + 8007220: 61bb str r3, [r7, #24] + 8007222: 617a str r2, [r7, #20] + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 8007224: 6979 ldr r1, [r7, #20] + 8007226: 69ba ldr r2, [r7, #24] + 8007228: e841 2300 strex r3, r2, [r1] + 800722c: 613b str r3, [r7, #16] + return(result); + 800722e: 693b ldr r3, [r7, #16] + 8007230: 2b00 cmp r3, #0 + 8007232: d1e6 bne.n 8007202 + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + 8007234: 687b ldr r3, [r7, #4] + 8007236: 2200 movs r2, #0 + 8007238: f883 2084 strb.w r2, [r3, #132] @ 0x84 + + return HAL_OK; + 800723c: 2300 movs r3, #0 +} + 800723e: 4618 mov r0, r3 + 8007240: 3724 adds r7, #36 @ 0x24 + 8007242: 46bd mov sp, r7 + 8007244: bc80 pop {r7} + 8007246: 4770 bx lr + +08007248 : + * @brief Enable the FIFO mode. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_EnableFifoMode(UART_HandleTypeDef *huart) +{ + 8007248: b580 push {r7, lr} + 800724a: b084 sub sp, #16 + 800724c: af00 add r7, sp, #0 + 800724e: 6078 str r0, [r7, #4] + + /* Check parameters */ + assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); + + /* Process Locked */ + __HAL_LOCK(huart); + 8007250: 687b ldr r3, [r7, #4] + 8007252: f893 3084 ldrb.w r3, [r3, #132] @ 0x84 + 8007256: 2b01 cmp r3, #1 + 8007258: d101 bne.n 800725e + 800725a: 2302 movs r3, #2 + 800725c: e02b b.n 80072b6 + 800725e: 687b ldr r3, [r7, #4] + 8007260: 2201 movs r2, #1 + 8007262: f883 2084 strb.w r2, [r3, #132] @ 0x84 + + huart->gState = HAL_UART_STATE_BUSY; + 8007266: 687b ldr r3, [r7, #4] + 8007268: 2224 movs r2, #36 @ 0x24 + 800726a: f8c3 2088 str.w r2, [r3, #136] @ 0x88 + + /* Save actual UART configuration */ + tmpcr1 = READ_REG(huart->Instance->CR1); + 800726e: 687b ldr r3, [r7, #4] + 8007270: 681b ldr r3, [r3, #0] + 8007272: 681b ldr r3, [r3, #0] + 8007274: 60fb str r3, [r7, #12] + + /* Disable UART */ + __HAL_UART_DISABLE(huart); + 8007276: 687b ldr r3, [r7, #4] + 8007278: 681b ldr r3, [r3, #0] + 800727a: 681a ldr r2, [r3, #0] + 800727c: 687b ldr r3, [r7, #4] + 800727e: 681b ldr r3, [r3, #0] + 8007280: f022 0201 bic.w r2, r2, #1 + 8007284: 601a str r2, [r3, #0] + + /* Enable FIFO mode */ + SET_BIT(tmpcr1, USART_CR1_FIFOEN); + 8007286: 68fb ldr r3, [r7, #12] + 8007288: f043 5300 orr.w r3, r3, #536870912 @ 0x20000000 + 800728c: 60fb str r3, [r7, #12] + huart->FifoMode = UART_FIFOMODE_ENABLE; + 800728e: 687b ldr r3, [r7, #4] + 8007290: f04f 5200 mov.w r2, #536870912 @ 0x20000000 + 8007294: 665a str r2, [r3, #100] @ 0x64 + + /* Restore UART configuration */ + WRITE_REG(huart->Instance->CR1, tmpcr1); + 8007296: 687b ldr r3, [r7, #4] + 8007298: 681b ldr r3, [r3, #0] + 800729a: 68fa ldr r2, [r7, #12] + 800729c: 601a str r2, [r3, #0] + + /* Determine the number of data to process during RX/TX ISR execution */ + UARTEx_SetNbDataToProcess(huart); + 800729e: 6878 ldr r0, [r7, #4] + 80072a0: f000 f8ac bl 80073fc + + huart->gState = HAL_UART_STATE_READY; + 80072a4: 687b ldr r3, [r7, #4] + 80072a6: 2220 movs r2, #32 + 80072a8: f8c3 2088 str.w r2, [r3, #136] @ 0x88 + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + 80072ac: 687b ldr r3, [r7, #4] + 80072ae: 2200 movs r2, #0 + 80072b0: f883 2084 strb.w r2, [r3, #132] @ 0x84 + + return HAL_OK; + 80072b4: 2300 movs r3, #0 +} + 80072b6: 4618 mov r0, r3 + 80072b8: 3710 adds r7, #16 + 80072ba: 46bd mov sp, r7 + 80072bc: bd80 pop {r7, pc} + +080072be : + * @arg @ref UART_TXFIFO_THRESHOLD_7_8 + * @arg @ref UART_TXFIFO_THRESHOLD_8_8 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold) +{ + 80072be: b580 push {r7, lr} + 80072c0: b084 sub sp, #16 + 80072c2: af00 add r7, sp, #0 + 80072c4: 6078 str r0, [r7, #4] + 80072c6: 6039 str r1, [r7, #0] + /* Check parameters */ + assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); + assert_param(IS_UART_TXFIFO_THRESHOLD(Threshold)); + + /* Process Locked */ + __HAL_LOCK(huart); + 80072c8: 687b ldr r3, [r7, #4] + 80072ca: f893 3084 ldrb.w r3, [r3, #132] @ 0x84 + 80072ce: 2b01 cmp r3, #1 + 80072d0: d101 bne.n 80072d6 + 80072d2: 2302 movs r3, #2 + 80072d4: e02d b.n 8007332 + 80072d6: 687b ldr r3, [r7, #4] + 80072d8: 2201 movs r2, #1 + 80072da: f883 2084 strb.w r2, [r3, #132] @ 0x84 + + huart->gState = HAL_UART_STATE_BUSY; + 80072de: 687b ldr r3, [r7, #4] + 80072e0: 2224 movs r2, #36 @ 0x24 + 80072e2: f8c3 2088 str.w r2, [r3, #136] @ 0x88 + + /* Save actual UART configuration */ + tmpcr1 = READ_REG(huart->Instance->CR1); + 80072e6: 687b ldr r3, [r7, #4] + 80072e8: 681b ldr r3, [r3, #0] + 80072ea: 681b ldr r3, [r3, #0] + 80072ec: 60fb str r3, [r7, #12] + + /* Disable UART */ + __HAL_UART_DISABLE(huart); + 80072ee: 687b ldr r3, [r7, #4] + 80072f0: 681b ldr r3, [r3, #0] + 80072f2: 681a ldr r2, [r3, #0] + 80072f4: 687b ldr r3, [r7, #4] + 80072f6: 681b ldr r3, [r3, #0] + 80072f8: f022 0201 bic.w r2, r2, #1 + 80072fc: 601a str r2, [r3, #0] + + /* Update TX threshold configuration */ + MODIFY_REG(huart->Instance->CR3, USART_CR3_TXFTCFG, Threshold); + 80072fe: 687b ldr r3, [r7, #4] + 8007300: 681b ldr r3, [r3, #0] + 8007302: 689b ldr r3, [r3, #8] + 8007304: f023 4160 bic.w r1, r3, #3758096384 @ 0xe0000000 + 8007308: 687b ldr r3, [r7, #4] + 800730a: 681b ldr r3, [r3, #0] + 800730c: 683a ldr r2, [r7, #0] + 800730e: 430a orrs r2, r1 + 8007310: 609a str r2, [r3, #8] + + /* Determine the number of data to process during RX/TX ISR execution */ + UARTEx_SetNbDataToProcess(huart); + 8007312: 6878 ldr r0, [r7, #4] + 8007314: f000 f872 bl 80073fc + + /* Restore UART configuration */ + WRITE_REG(huart->Instance->CR1, tmpcr1); + 8007318: 687b ldr r3, [r7, #4] + 800731a: 681b ldr r3, [r3, #0] + 800731c: 68fa ldr r2, [r7, #12] + 800731e: 601a str r2, [r3, #0] + + huart->gState = HAL_UART_STATE_READY; + 8007320: 687b ldr r3, [r7, #4] + 8007322: 2220 movs r2, #32 + 8007324: f8c3 2088 str.w r2, [r3, #136] @ 0x88 + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + 8007328: 687b ldr r3, [r7, #4] + 800732a: 2200 movs r2, #0 + 800732c: f883 2084 strb.w r2, [r3, #132] @ 0x84 + + return HAL_OK; + 8007330: 2300 movs r3, #0 +} + 8007332: 4618 mov r0, r3 + 8007334: 3710 adds r7, #16 + 8007336: 46bd mov sp, r7 + 8007338: bd80 pop {r7, pc} + +0800733a : + * @arg @ref UART_RXFIFO_THRESHOLD_7_8 + * @arg @ref UART_RXFIFO_THRESHOLD_8_8 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold) +{ + 800733a: b580 push {r7, lr} + 800733c: b084 sub sp, #16 + 800733e: af00 add r7, sp, #0 + 8007340: 6078 str r0, [r7, #4] + 8007342: 6039 str r1, [r7, #0] + /* Check the parameters */ + assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); + assert_param(IS_UART_RXFIFO_THRESHOLD(Threshold)); + + /* Process Locked */ + __HAL_LOCK(huart); + 8007344: 687b ldr r3, [r7, #4] + 8007346: f893 3084 ldrb.w r3, [r3, #132] @ 0x84 + 800734a: 2b01 cmp r3, #1 + 800734c: d101 bne.n 8007352 + 800734e: 2302 movs r3, #2 + 8007350: e02d b.n 80073ae + 8007352: 687b ldr r3, [r7, #4] + 8007354: 2201 movs r2, #1 + 8007356: f883 2084 strb.w r2, [r3, #132] @ 0x84 + + huart->gState = HAL_UART_STATE_BUSY; + 800735a: 687b ldr r3, [r7, #4] + 800735c: 2224 movs r2, #36 @ 0x24 + 800735e: f8c3 2088 str.w r2, [r3, #136] @ 0x88 + + /* Save actual UART configuration */ + tmpcr1 = READ_REG(huart->Instance->CR1); + 8007362: 687b ldr r3, [r7, #4] + 8007364: 681b ldr r3, [r3, #0] + 8007366: 681b ldr r3, [r3, #0] + 8007368: 60fb str r3, [r7, #12] + + /* Disable UART */ + __HAL_UART_DISABLE(huart); + 800736a: 687b ldr r3, [r7, #4] + 800736c: 681b ldr r3, [r3, #0] + 800736e: 681a ldr r2, [r3, #0] + 8007370: 687b ldr r3, [r7, #4] + 8007372: 681b ldr r3, [r3, #0] + 8007374: f022 0201 bic.w r2, r2, #1 + 8007378: 601a str r2, [r3, #0] + + /* Update RX threshold configuration */ + MODIFY_REG(huart->Instance->CR3, USART_CR3_RXFTCFG, Threshold); + 800737a: 687b ldr r3, [r7, #4] + 800737c: 681b ldr r3, [r3, #0] + 800737e: 689b ldr r3, [r3, #8] + 8007380: f023 6160 bic.w r1, r3, #234881024 @ 0xe000000 + 8007384: 687b ldr r3, [r7, #4] + 8007386: 681b ldr r3, [r3, #0] + 8007388: 683a ldr r2, [r7, #0] + 800738a: 430a orrs r2, r1 + 800738c: 609a str r2, [r3, #8] + + /* Determine the number of data to process during RX/TX ISR execution */ + UARTEx_SetNbDataToProcess(huart); + 800738e: 6878 ldr r0, [r7, #4] + 8007390: f000 f834 bl 80073fc + + /* Restore UART configuration */ + WRITE_REG(huart->Instance->CR1, tmpcr1); + 8007394: 687b ldr r3, [r7, #4] + 8007396: 681b ldr r3, [r3, #0] + 8007398: 68fa ldr r2, [r7, #12] + 800739a: 601a str r2, [r3, #0] + + huart->gState = HAL_UART_STATE_READY; + 800739c: 687b ldr r3, [r7, #4] + 800739e: 2220 movs r2, #32 + 80073a0: f8c3 2088 str.w r2, [r3, #136] @ 0x88 + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + 80073a4: 687b ldr r3, [r7, #4] + 80073a6: 2200 movs r2, #0 + 80073a8: f883 2084 strb.w r2, [r3, #132] @ 0x84 + + return HAL_OK; + 80073ac: 2300 movs r3, #0 +} + 80073ae: 4618 mov r0, r3 + 80073b0: 3710 adds r7, #16 + 80073b2: 46bd mov sp, r7 + 80073b4: bd80 pop {r7, pc} + +080073b6 : + * @param huart UART handle. + * @param WakeUpSelection UART wake up from stop mode parameters. + * @retval None + */ +static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection) +{ + 80073b6: b480 push {r7} + 80073b8: b085 sub sp, #20 + 80073ba: af00 add r7, sp, #0 + 80073bc: 60f8 str r0, [r7, #12] + 80073be: 1d3b adds r3, r7, #4 + 80073c0: e883 0006 stmia.w r3, {r1, r2} + assert_param(IS_UART_ADDRESSLENGTH_DETECT(WakeUpSelection.AddressLength)); + + /* Set the USART address length */ + MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, WakeUpSelection.AddressLength); + 80073c4: 68fb ldr r3, [r7, #12] + 80073c6: 681b ldr r3, [r3, #0] + 80073c8: 685b ldr r3, [r3, #4] + 80073ca: f023 0210 bic.w r2, r3, #16 + 80073ce: 893b ldrh r3, [r7, #8] + 80073d0: 4619 mov r1, r3 + 80073d2: 68fb ldr r3, [r7, #12] + 80073d4: 681b ldr r3, [r3, #0] + 80073d6: 430a orrs r2, r1 + 80073d8: 605a str r2, [r3, #4] + + /* Set the USART address node */ + MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)WakeUpSelection.Address << UART_CR2_ADDRESS_LSB_POS)); + 80073da: 68fb ldr r3, [r7, #12] + 80073dc: 681b ldr r3, [r3, #0] + 80073de: 685b ldr r3, [r3, #4] + 80073e0: f023 417f bic.w r1, r3, #4278190080 @ 0xff000000 + 80073e4: 7abb ldrb r3, [r7, #10] + 80073e6: 061a lsls r2, r3, #24 + 80073e8: 68fb ldr r3, [r7, #12] + 80073ea: 681b ldr r3, [r3, #0] + 80073ec: 430a orrs r2, r1 + 80073ee: 605a str r2, [r3, #4] +} + 80073f0: bf00 nop + 80073f2: 3714 adds r7, #20 + 80073f4: 46bd mov sp, r7 + 80073f6: bc80 pop {r7} + 80073f8: 4770 bx lr + ... + +080073fc : + * the UART configuration registers. + * @param huart UART handle. + * @retval None + */ +static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart) +{ + 80073fc: b480 push {r7} + 80073fe: b085 sub sp, #20 + 8007400: af00 add r7, sp, #0 + 8007402: 6078 str r0, [r7, #4] + uint8_t rx_fifo_threshold; + uint8_t tx_fifo_threshold; + static const uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U}; + static const uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U}; + + if (huart->FifoMode == UART_FIFOMODE_DISABLE) + 8007404: 687b ldr r3, [r7, #4] + 8007406: 6e5b ldr r3, [r3, #100] @ 0x64 + 8007408: 2b00 cmp r3, #0 + 800740a: d108 bne.n 800741e + { + huart->NbTxDataToProcess = 1U; + 800740c: 687b ldr r3, [r7, #4] + 800740e: 2201 movs r2, #1 + 8007410: f8a3 206a strh.w r2, [r3, #106] @ 0x6a + huart->NbRxDataToProcess = 1U; + 8007414: 687b ldr r3, [r7, #4] + 8007416: 2201 movs r2, #1 + 8007418: f8a3 2068 strh.w r2, [r3, #104] @ 0x68 + huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / + (uint16_t)denominator[tx_fifo_threshold]; + huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / + (uint16_t)denominator[rx_fifo_threshold]; + } +} + 800741c: e031 b.n 8007482 + rx_fifo_depth = RX_FIFO_DEPTH; + 800741e: 2308 movs r3, #8 + 8007420: 73fb strb r3, [r7, #15] + tx_fifo_depth = TX_FIFO_DEPTH; + 8007422: 2308 movs r3, #8 + 8007424: 73bb strb r3, [r7, #14] + rx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos); + 8007426: 687b ldr r3, [r7, #4] + 8007428: 681b ldr r3, [r3, #0] + 800742a: 689b ldr r3, [r3, #8] + 800742c: 0e5b lsrs r3, r3, #25 + 800742e: b2db uxtb r3, r3 + 8007430: f003 0307 and.w r3, r3, #7 + 8007434: 737b strb r3, [r7, #13] + tx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos); + 8007436: 687b ldr r3, [r7, #4] + 8007438: 681b ldr r3, [r3, #0] + 800743a: 689b ldr r3, [r3, #8] + 800743c: 0f5b lsrs r3, r3, #29 + 800743e: b2db uxtb r3, r3 + 8007440: f003 0307 and.w r3, r3, #7 + 8007444: 733b strb r3, [r7, #12] + huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / + 8007446: 7bbb ldrb r3, [r7, #14] + 8007448: 7b3a ldrb r2, [r7, #12] + 800744a: 4910 ldr r1, [pc, #64] @ (800748c ) + 800744c: 5c8a ldrb r2, [r1, r2] + 800744e: fb02 f303 mul.w r3, r2, r3 + (uint16_t)denominator[tx_fifo_threshold]; + 8007452: 7b3a ldrb r2, [r7, #12] + 8007454: 490e ldr r1, [pc, #56] @ (8007490 ) + 8007456: 5c8a ldrb r2, [r1, r2] + huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / + 8007458: fb93 f3f2 sdiv r3, r3, r2 + 800745c: b29a uxth r2, r3 + 800745e: 687b ldr r3, [r7, #4] + 8007460: f8a3 206a strh.w r2, [r3, #106] @ 0x6a + huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / + 8007464: 7bfb ldrb r3, [r7, #15] + 8007466: 7b7a ldrb r2, [r7, #13] + 8007468: 4908 ldr r1, [pc, #32] @ (800748c ) + 800746a: 5c8a ldrb r2, [r1, r2] + 800746c: fb02 f303 mul.w r3, r2, r3 + (uint16_t)denominator[rx_fifo_threshold]; + 8007470: 7b7a ldrb r2, [r7, #13] + 8007472: 4907 ldr r1, [pc, #28] @ (8007490 ) + 8007474: 5c8a ldrb r2, [r1, r2] + huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / + 8007476: fb93 f3f2 sdiv r3, r3, r2 + 800747a: b29a uxth r2, r3 + 800747c: 687b ldr r3, [r7, #4] + 800747e: f8a3 2068 strh.w r2, [r3, #104] @ 0x68 +} + 8007482: bf00 nop + 8007484: 3714 adds r7, #20 + 8007486: 46bd mov sp, r7 + 8007488: bc80 pop {r7} + 800748a: 4770 bx lr + 800748c: 0800d9d0 .word 0x0800d9d0 + 8007490: 0800d9d8 .word 0x0800d9d8 + +08007494 : + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + 8007494: b480 push {r7} + 8007496: b083 sub sp, #12 + 8007498: af00 add r7, sp, #0 + 800749a: 6078 str r0, [r7, #4] + 800749c: 6039 str r1, [r7, #0] + WRITE_REG(GPIOx->BSRR, PinMask); + 800749e: 687b ldr r3, [r7, #4] + 80074a0: 683a ldr r2, [r7, #0] + 80074a2: 619a str r2, [r3, #24] +} + 80074a4: bf00 nop + 80074a6: 370c adds r7, #12 + 80074a8: 46bd mov sp, r7 + 80074aa: bc80 pop {r7} + 80074ac: 4770 bx lr + +080074ae : + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void LL_GPIO_ResetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + 80074ae: b480 push {r7} + 80074b0: b083 sub sp, #12 + 80074b2: af00 add r7, sp, #0 + 80074b4: 6078 str r0, [r7, #4] + 80074b6: 6039 str r1, [r7, #0] + WRITE_REG(GPIOx->BRR, PinMask); + 80074b8: 687b ldr r3, [r7, #4] + 80074ba: 683a ldr r2, [r7, #0] + 80074bc: 629a str r2, [r3, #40] @ 0x28 +} + 80074be: bf00 nop + 80074c0: 370c adds r7, #12 + 80074c2: 46bd mov sp, r7 + 80074c4: bc80 pop {r7} + 80074c6: 4770 bx lr + +080074c8 : +TimerEvent_t RxTimeoutTimer; + +/* Private functions ---------------------------------------------------------*/ + +static void RadioInit( RadioEvents_t *events ) +{ + 80074c8: b580 push {r7, lr} + 80074ca: b084 sub sp, #16 + 80074cc: af02 add r7, sp, #8 + 80074ce: 6078 str r0, [r7, #4] + RadioEvents = events; + 80074d0: 4a24 ldr r2, [pc, #144] @ (8007564 ) + 80074d2: 687b ldr r3, [r7, #4] + 80074d4: 6013 str r3, [r2, #0] + + SubgRf.RxContinuous = false; + 80074d6: 4b24 ldr r3, [pc, #144] @ (8007568 ) + 80074d8: 2200 movs r2, #0 + 80074da: 705a strb r2, [r3, #1] + SubgRf.TxTimeout = 0; + 80074dc: 4b22 ldr r3, [pc, #136] @ (8007568 ) + 80074de: 2200 movs r2, #0 + 80074e0: 605a str r2, [r3, #4] + SubgRf.RxTimeout = 0; + 80074e2: 4b21 ldr r3, [pc, #132] @ (8007568 ) + 80074e4: 2200 movs r2, #0 + 80074e6: 609a str r2, [r3, #8] + /*See STM32WL Errata: RadioSetRxDutyCycle*/ + SubgRf.RxDcPreambleDetectTimeout = 0; + 80074e8: 4b1f ldr r3, [pc, #124] @ (8007568 ) + 80074ea: 2200 movs r2, #0 + 80074ec: 659a str r2, [r3, #88] @ 0x58 +#if( RADIO_LR_FHSS_IS_ON == 1 ) + SubgRf.lr_fhss.is_lr_fhss_on = false; +#endif /* RADIO_LR_FHSS_IS_ON == 1 */ + SUBGRF_Init( RadioOnDioIrq ); + 80074ee: 481f ldr r0, [pc, #124] @ (800756c ) + 80074f0: f001 fffa bl 80094e8 + /*SubgRf.publicNetwork set to false*/ + SubgRf.PublicNetwork.Current = false; + 80074f4: 4b1c ldr r3, [pc, #112] @ (8007568 ) + 80074f6: 2200 movs r2, #0 + 80074f8: 735a strb r2, [r3, #13] + SubgRf.PublicNetwork.Previous = false; + 80074fa: 4b1b ldr r3, [pc, #108] @ (8007568 ) + 80074fc: 2200 movs r2, #0 + 80074fe: 731a strb r2, [r3, #12] + + RADIO_IRQ_PROCESS_INIT(); + + SUBGRF_SetRegulatorMode( ); + 8007500: f002 fa90 bl 8009a24 + + SUBGRF_SetBufferBaseAddress( 0x00, 0x00 ); + 8007504: 2100 movs r1, #0 + 8007506: 2000 movs r0, #0 + 8007508: f002 fe5c bl 800a1c4 + SUBGRF_SetTxParams( RFO_LP, 0, RADIO_RAMP_200_US ); + 800750c: 2204 movs r2, #4 + 800750e: 2100 movs r1, #0 + 8007510: 2001 movs r0, #1 + 8007512: f002 fc1f bl 8009d54 + SUBGRF_SetDioIrqParams( IRQ_RADIO_ALL, IRQ_RADIO_ALL, IRQ_RADIO_NONE, IRQ_RADIO_NONE ); + 8007516: 2300 movs r3, #0 + 8007518: 2200 movs r2, #0 + 800751a: f64f 71ff movw r1, #65535 @ 0xffff + 800751e: f64f 70ff movw r0, #65535 @ 0xffff + 8007522: f002 fb4f bl 8009bc4 + + RadioSleep(); + 8007526: f000 fe9f bl 8008268 + // Initialize driver timeout timers + TimerInit( &TxTimeoutTimer, RadioOnTxTimeoutIrq ); + 800752a: 2300 movs r3, #0 + 800752c: 9300 str r3, [sp, #0] + 800752e: 4b10 ldr r3, [pc, #64] @ (8007570 ) + 8007530: 2200 movs r2, #0 + 8007532: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff + 8007536: 480f ldr r0, [pc, #60] @ (8007574 ) + 8007538: f005 fa88 bl 800ca4c + TimerInit( &RxTimeoutTimer, RadioOnRxTimeoutIrq ); + 800753c: 2300 movs r3, #0 + 800753e: 9300 str r3, [sp, #0] + 8007540: 4b0d ldr r3, [pc, #52] @ (8007578 ) + 8007542: 2200 movs r2, #0 + 8007544: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff + 8007548: 480c ldr r0, [pc, #48] @ (800757c ) + 800754a: f005 fa7f bl 800ca4c + TimerStop( &TxTimeoutTimer ); + 800754e: 4809 ldr r0, [pc, #36] @ (8007574 ) + 8007550: f005 fb20 bl 800cb94 + TimerStop( &RxTimeoutTimer ); + 8007554: 4809 ldr r0, [pc, #36] @ (800757c ) + 8007556: f005 fb1d bl 800cb94 +} + 800755a: bf00 nop + 800755c: 3708 adds r7, #8 + 800755e: 46bd mov sp, r7 + 8007560: bd80 pop {r7, pc} + 8007562: bf00 nop + 8007564: 2000028c .word 0x2000028c + 8007568: 20000290 .word 0x20000290 + 800756c: 0800868d .word 0x0800868d + 8007570: 080085fd .word 0x080085fd + 8007574: 200002ec .word 0x200002ec + 8007578: 08008611 .word 0x08008611 + 800757c: 20000304 .word 0x20000304 + +08007580 : + +static RadioState_t RadioGetStatus( void ) +{ + 8007580: b580 push {r7, lr} + 8007582: af00 add r7, sp, #0 + switch( SUBGRF_GetOperatingMode( ) ) + 8007584: f001 fff8 bl 8009578 + 8007588: 4603 mov r3, r0 + 800758a: 2b07 cmp r3, #7 + 800758c: d00a beq.n 80075a4 + 800758e: 2b07 cmp r3, #7 + 8007590: dc0a bgt.n 80075a8 + 8007592: 2b04 cmp r3, #4 + 8007594: d002 beq.n 800759c + 8007596: 2b05 cmp r3, #5 + 8007598: d002 beq.n 80075a0 + 800759a: e005 b.n 80075a8 + { + case MODE_TX: + return RF_TX_RUNNING; + 800759c: 2302 movs r3, #2 + 800759e: e004 b.n 80075aa + case MODE_RX: + return RF_RX_RUNNING; + 80075a0: 2301 movs r3, #1 + 80075a2: e002 b.n 80075aa + case MODE_CAD: + return RF_CAD; + 80075a4: 2303 movs r3, #3 + 80075a6: e000 b.n 80075aa + default: + return RF_IDLE; + 80075a8: 2300 movs r3, #0 + } +} + 80075aa: 4618 mov r0, r3 + 80075ac: bd80 pop {r7, pc} + ... + +080075b0 : + +static void RadioSetModem( RadioModems_t modem ) +{ + 80075b0: b580 push {r7, lr} + 80075b2: b082 sub sp, #8 + 80075b4: af00 add r7, sp, #0 + 80075b6: 4603 mov r3, r0 + 80075b8: 71fb strb r3, [r7, #7] + SubgRf.Modem = modem; + 80075ba: 4a2a ldr r2, [pc, #168] @ (8007664 ) + 80075bc: 79fb ldrb r3, [r7, #7] + 80075be: 7013 strb r3, [r2, #0] + RFW_SetRadioModem( modem ); + 80075c0: 79fb ldrb r3, [r7, #7] + 80075c2: 4618 mov r0, r3 + 80075c4: f003 fd82 bl 800b0cc + switch( modem ) + 80075c8: 79fb ldrb r3, [r7, #7] + 80075ca: 2b05 cmp r3, #5 + 80075cc: d80e bhi.n 80075ec + 80075ce: a201 add r2, pc, #4 @ (adr r2, 80075d4 ) + 80075d0: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 80075d4: 080075fb .word 0x080075fb + 80075d8: 08007609 .word 0x08007609 + 80075dc: 080075ed .word 0x080075ed + 80075e0: 0800762f .word 0x0800762f + 80075e4: 0800763d .word 0x0800763d + 80075e8: 0800764b .word 0x0800764b + { + default: + case MODEM_MSK: + SUBGRF_SetPacketType( PACKET_TYPE_GMSK ); + 80075ec: 2003 movs r0, #3 + 80075ee: f002 fb8b bl 8009d08 + // When switching to GFSK mode the LoRa SyncWord register value is reset + // Thus, we also reset the RadioPublicNetwork variable + SubgRf.PublicNetwork.Current = false; + 80075f2: 4b1c ldr r3, [pc, #112] @ (8007664 ) + 80075f4: 2200 movs r2, #0 + 80075f6: 735a strb r2, [r3, #13] + break; + 80075f8: e02f b.n 800765a + case MODEM_FSK: + SUBGRF_SetPacketType( PACKET_TYPE_GFSK ); + 80075fa: 2000 movs r0, #0 + 80075fc: f002 fb84 bl 8009d08 + // When switching to GFSK mode the LoRa SyncWord register value is reset + // Thus, we also reset the RadioPublicNetwork variable + SubgRf.PublicNetwork.Current = false; + 8007600: 4b18 ldr r3, [pc, #96] @ (8007664 ) + 8007602: 2200 movs r2, #0 + 8007604: 735a strb r2, [r3, #13] + break; + 8007606: e028 b.n 800765a + case MODEM_LORA: + SUBGRF_SetPacketType( PACKET_TYPE_LORA ); + 8007608: 2001 movs r0, #1 + 800760a: f002 fb7d bl 8009d08 + // Public/Private network register is reset when switching modems + if( SubgRf.PublicNetwork.Current != SubgRf.PublicNetwork.Previous ) + 800760e: 4b15 ldr r3, [pc, #84] @ (8007664 ) + 8007610: 7b5a ldrb r2, [r3, #13] + 8007612: 4b14 ldr r3, [pc, #80] @ (8007664 ) + 8007614: 7b1b ldrb r3, [r3, #12] + 8007616: 429a cmp r2, r3 + 8007618: d01e beq.n 8007658 + { + SubgRf.PublicNetwork.Current = SubgRf.PublicNetwork.Previous; + 800761a: 4b12 ldr r3, [pc, #72] @ (8007664 ) + 800761c: 7b1a ldrb r2, [r3, #12] + 800761e: 4b11 ldr r3, [pc, #68] @ (8007664 ) + 8007620: 735a strb r2, [r3, #13] + RadioSetPublicNetwork( SubgRf.PublicNetwork.Current ); + 8007622: 4b10 ldr r3, [pc, #64] @ (8007664 ) + 8007624: 7b5b ldrb r3, [r3, #13] + 8007626: 4618 mov r0, r3 + 8007628: f000 ffb2 bl 8008590 + } + break; + 800762c: e014 b.n 8007658 + case MODEM_BPSK: + SUBGRF_SetPacketType( PACKET_TYPE_BPSK ); + 800762e: 2002 movs r0, #2 + 8007630: f002 fb6a bl 8009d08 + // When switching to BPSK mode the LoRa SyncWord register value is reset + // Thus, we also reset the RadioPublicNetwork variable + SubgRf.PublicNetwork.Current = false; + 8007634: 4b0b ldr r3, [pc, #44] @ (8007664 ) + 8007636: 2200 movs r2, #0 + 8007638: 735a strb r2, [r3, #13] + break; + 800763a: e00e b.n 800765a +#if (RADIO_SIGFOX_ENABLE == 1) + case MODEM_SIGFOX_TX: + SUBGRF_SetPacketType( PACKET_TYPE_BPSK ); + 800763c: 2002 movs r0, #2 + 800763e: f002 fb63 bl 8009d08 + // When switching to BPSK mode the LoRa SyncWord register value is reset + // Thus, we also reset the RadioPublicNetwork variable + SubgRf.PublicNetwork.Current = false; + 8007642: 4b08 ldr r3, [pc, #32] @ (8007664 ) + 8007644: 2200 movs r2, #0 + 8007646: 735a strb r2, [r3, #13] + break; + 8007648: e007 b.n 800765a + case MODEM_SIGFOX_RX: + SUBGRF_SetPacketType( PACKET_TYPE_GFSK ); + 800764a: 2000 movs r0, #0 + 800764c: f002 fb5c bl 8009d08 + // When switching to GFSK mode the LoRa SyncWord register value is reset + // Thus, we also reset the RadioPublicNetwork variable + SubgRf.PublicNetwork.Current = false; + 8007650: 4b04 ldr r3, [pc, #16] @ (8007664 ) + 8007652: 2200 movs r2, #0 + 8007654: 735a strb r2, [r3, #13] + break; + 8007656: e000 b.n 800765a + break; + 8007658: bf00 nop +#endif /*RADIO_SIGFOX_ENABLE == 1*/ + } +} + 800765a: bf00 nop + 800765c: 3708 adds r7, #8 + 800765e: 46bd mov sp, r7 + 8007660: bd80 pop {r7, pc} + 8007662: bf00 nop + 8007664: 20000290 .word 0x20000290 + +08007668 : + +static void RadioSetChannel( uint32_t freq ) +{ + 8007668: b580 push {r7, lr} + 800766a: b082 sub sp, #8 + 800766c: af00 add r7, sp, #0 + 800766e: 6078 str r0, [r7, #4] + SUBGRF_SetRfFrequency( freq ); + 8007670: 6878 ldr r0, [r7, #4] + 8007672: f002 fb03 bl 8009c7c +} + 8007676: bf00 nop + 8007678: 3708 adds r7, #8 + 800767a: 46bd mov sp, r7 + 800767c: bd80 pop {r7, pc} + +0800767e : + +static bool RadioIsChannelFree( uint32_t freq, uint32_t rxBandwidth, int16_t rssiThresh, uint32_t maxCarrierSenseTime ) +{ + 800767e: b580 push {r7, lr} + 8007680: b090 sub sp, #64 @ 0x40 + 8007682: af0a add r7, sp, #40 @ 0x28 + 8007684: 60f8 str r0, [r7, #12] + 8007686: 60b9 str r1, [r7, #8] + 8007688: 603b str r3, [r7, #0] + 800768a: 4613 mov r3, r2 + 800768c: 80fb strh r3, [r7, #6] + bool status = true; + 800768e: 2301 movs r3, #1 + 8007690: 75fb strb r3, [r7, #23] + int16_t rssi = 0; + 8007692: 2300 movs r3, #0 + 8007694: 82bb strh r3, [r7, #20] + uint32_t carrierSenseTime = 0; + 8007696: 2300 movs r3, #0 + 8007698: 613b str r3, [r7, #16] + + RadioStandby( ); + 800769a: f000 fdf8 bl 800828e + + RadioSetModem( MODEM_FSK ); + 800769e: 2000 movs r0, #0 + 80076a0: f7ff ff86 bl 80075b0 + + RadioSetChannel( freq ); + 80076a4: 68f8 ldr r0, [r7, #12] + 80076a6: f7ff ffdf bl 8007668 + + // Set Rx bandwidth. Other parameters are not used. + RadioSetRxConfig( MODEM_FSK, rxBandwidth, 600, 0, rxBandwidth, 3, 0, false, + 80076aa: 2301 movs r3, #1 + 80076ac: 9309 str r3, [sp, #36] @ 0x24 + 80076ae: 2300 movs r3, #0 + 80076b0: 9308 str r3, [sp, #32] + 80076b2: 2300 movs r3, #0 + 80076b4: 9307 str r3, [sp, #28] + 80076b6: 2300 movs r3, #0 + 80076b8: 9306 str r3, [sp, #24] + 80076ba: 2300 movs r3, #0 + 80076bc: 9305 str r3, [sp, #20] + 80076be: 2300 movs r3, #0 + 80076c0: 9304 str r3, [sp, #16] + 80076c2: 2300 movs r3, #0 + 80076c4: 9303 str r3, [sp, #12] + 80076c6: 2300 movs r3, #0 + 80076c8: 9302 str r3, [sp, #8] + 80076ca: 2303 movs r3, #3 + 80076cc: 9301 str r3, [sp, #4] + 80076ce: 68bb ldr r3, [r7, #8] + 80076d0: 9300 str r3, [sp, #0] + 80076d2: 2300 movs r3, #0 + 80076d4: f44f 7216 mov.w r2, #600 @ 0x258 + 80076d8: 68b9 ldr r1, [r7, #8] + 80076da: 2000 movs r0, #0 + 80076dc: f000 f83c bl 8007758 + 0, false, 0, 0, false, true ); + RadioRx( 0 ); + 80076e0: 2000 movs r0, #0 + 80076e2: f000 fddb bl 800829c + + RADIO_DELAY_MS( RadioGetWakeupTime( ) ); + 80076e6: f000 ff81 bl 80085ec + 80076ea: 4603 mov r3, r0 + 80076ec: 4618 mov r0, r3 + 80076ee: f7f9 fa5b bl 8000ba8 + + carrierSenseTime = TimerGetCurrentTime( ); + 80076f2: f005 fb69 bl 800cdc8 + 80076f6: 6138 str r0, [r7, #16] + + // Perform carrier sense for maxCarrierSenseTime + while( TimerGetElapsedTime( carrierSenseTime ) < maxCarrierSenseTime ) + 80076f8: e00d b.n 8007716 + { + rssi = RadioRssi( MODEM_FSK ); + 80076fa: 2000 movs r0, #0 + 80076fc: f000 fec8 bl 8008490 + 8007700: 4603 mov r3, r0 + 8007702: 82bb strh r3, [r7, #20] + + if( rssi > rssiThresh ) + 8007704: f9b7 2014 ldrsh.w r2, [r7, #20] + 8007708: f9b7 3006 ldrsh.w r3, [r7, #6] + 800770c: 429a cmp r2, r3 + 800770e: dd02 ble.n 8007716 + { + status = false; + 8007710: 2300 movs r3, #0 + 8007712: 75fb strb r3, [r7, #23] + break; + 8007714: e006 b.n 8007724 + while( TimerGetElapsedTime( carrierSenseTime ) < maxCarrierSenseTime ) + 8007716: 6938 ldr r0, [r7, #16] + 8007718: f005 fb68 bl 800cdec + 800771c: 4602 mov r2, r0 + 800771e: 683b ldr r3, [r7, #0] + 8007720: 4293 cmp r3, r2 + 8007722: d8ea bhi.n 80076fa + } + } + RadioStandby( ); + 8007724: f000 fdb3 bl 800828e + + return status; + 8007728: 7dfb ldrb r3, [r7, #23] +} + 800772a: 4618 mov r0, r3 + 800772c: 3718 adds r7, #24 + 800772e: 46bd mov sp, r7 + 8007730: bd80 pop {r7, pc} + +08007732 : + +static uint32_t RadioRandom( void ) +{ + 8007732: b580 push {r7, lr} + 8007734: b082 sub sp, #8 + 8007736: af00 add r7, sp, #0 + uint32_t rnd = 0; + 8007738: 2300 movs r3, #0 + 800773a: 607b str r3, [r7, #4] + + /* + * Radio setup for random number generation + */ + // Disable modem interrupts + SUBGRF_SetDioIrqParams( IRQ_RADIO_NONE, IRQ_RADIO_NONE, IRQ_RADIO_NONE, IRQ_RADIO_NONE ); + 800773c: 2300 movs r3, #0 + 800773e: 2200 movs r2, #0 + 8007740: 2100 movs r1, #0 + 8007742: 2000 movs r0, #0 + 8007744: f002 fa3e bl 8009bc4 + + rnd = SUBGRF_GetRandom(); + 8007748: f001 ffe7 bl 800971a + 800774c: 6078 str r0, [r7, #4] + + return rnd; + 800774e: 687b ldr r3, [r7, #4] +} + 8007750: 4618 mov r0, r3 + 8007752: 3708 adds r7, #8 + 8007754: 46bd mov sp, r7 + 8007756: bd80 pop {r7, pc} + +08007758 : + uint32_t bandwidthAfc, uint16_t preambleLen, + uint16_t symbTimeout, bool fixLen, + uint8_t payloadLen, + bool crcOn, bool freqHopOn, uint8_t hopPeriod, + bool iqInverted, bool rxContinuous ) +{ + 8007758: b580 push {r7, lr} + 800775a: b08a sub sp, #40 @ 0x28 + 800775c: af00 add r7, sp, #0 + 800775e: 60b9 str r1, [r7, #8] + 8007760: 607a str r2, [r7, #4] + 8007762: 461a mov r2, r3 + 8007764: 4603 mov r3, r0 + 8007766: 73fb strb r3, [r7, #15] + 8007768: 4613 mov r3, r2 + 800776a: 73bb strb r3, [r7, #14] +#if (RADIO_SIGFOX_ENABLE == 1) + uint8_t modReg; +#endif + SubgRf.RxContinuous = rxContinuous; + 800776c: 4ab9 ldr r2, [pc, #740] @ (8007a54 ) + 800776e: f897 3054 ldrb.w r3, [r7, #84] @ 0x54 + 8007772: 7053 strb r3, [r2, #1] + RFW_DeInit(); + 8007774: f003 fb40 bl 800adf8 + if( rxContinuous == true ) + 8007778: f897 3054 ldrb.w r3, [r7, #84] @ 0x54 + 800777c: 2b00 cmp r3, #0 + 800777e: d001 beq.n 8007784 + { + symbTimeout = 0; + 8007780: 2300 movs r3, #0 + 8007782: 873b strh r3, [r7, #56] @ 0x38 + } + if( fixLen == true ) + 8007784: f897 303c ldrb.w r3, [r7, #60] @ 0x3c + 8007788: 2b00 cmp r3, #0 + 800778a: d004 beq.n 8007796 + { + MaxPayloadLength = payloadLen; + 800778c: 4ab2 ldr r2, [pc, #712] @ (8007a58 ) + 800778e: f897 3040 ldrb.w r3, [r7, #64] @ 0x40 + 8007792: 7013 strb r3, [r2, #0] + 8007794: e002 b.n 800779c + } + else + { + MaxPayloadLength = 0xFF; + 8007796: 4bb0 ldr r3, [pc, #704] @ (8007a58 ) + 8007798: 22ff movs r2, #255 @ 0xff + 800779a: 701a strb r2, [r3, #0] + } + + switch( modem ) + 800779c: 7bfb ldrb r3, [r7, #15] + 800779e: 2b05 cmp r3, #5 + 80077a0: d009 beq.n 80077b6 + 80077a2: 2b05 cmp r3, #5 + 80077a4: f300 81d7 bgt.w 8007b56 + 80077a8: 2b00 cmp r3, #0 + 80077aa: f000 80bf beq.w 800792c + 80077ae: 2b01 cmp r3, #1 + 80077b0: f000 8124 beq.w 80079fc + // Timeout Max, Timeout handled directly in SetRx function + SubgRf.RxTimeout = 0xFFFF; + + break; + default: + break; + 80077b4: e1cf b.n 8007b56 + SUBGRF_SetStopRxTimerOnPreambleDetect( true ); + 80077b6: 2001 movs r0, #1 + 80077b8: f002 f8f6 bl 80099a8 + SubgRf.ModulationParams.PacketType = PACKET_TYPE_GFSK; + 80077bc: 4ba5 ldr r3, [pc, #660] @ (8007a54 ) + 80077be: 2200 movs r2, #0 + 80077c0: f883 2038 strb.w r2, [r3, #56] @ 0x38 + SubgRf.ModulationParams.Params.Gfsk.BitRate = datarate; + 80077c4: 4aa3 ldr r2, [pc, #652] @ (8007a54 ) + 80077c6: 687b ldr r3, [r7, #4] + 80077c8: 63d3 str r3, [r2, #60] @ 0x3c + SubgRf.ModulationParams.Params.Gfsk.ModulationShaping = MOD_SHAPING_G_BT_05; + 80077ca: 4ba2 ldr r3, [pc, #648] @ (8007a54 ) + 80077cc: 2209 movs r2, #9 + 80077ce: f883 2044 strb.w r2, [r3, #68] @ 0x44 + SubgRf.ModulationParams.Params.Gfsk.Fdev = 800; + 80077d2: 4ba0 ldr r3, [pc, #640] @ (8007a54 ) + 80077d4: f44f 7248 mov.w r2, #800 @ 0x320 + 80077d8: 641a str r2, [r3, #64] @ 0x40 + SubgRf.ModulationParams.Params.Gfsk.Bandwidth = SUBGRF_GetFskBandwidthRegValue( bandwidth ); + 80077da: 68b8 ldr r0, [r7, #8] + 80077dc: f002 ffd0 bl 800a780 + 80077e0: 4603 mov r3, r0 + 80077e2: 461a mov r2, r3 + 80077e4: 4b9b ldr r3, [pc, #620] @ (8007a54 ) + 80077e6: f883 2045 strb.w r2, [r3, #69] @ 0x45 + SubgRf.PacketParams.PacketType = PACKET_TYPE_GFSK; + 80077ea: 4b9a ldr r3, [pc, #616] @ (8007a54 ) + 80077ec: 2200 movs r2, #0 + 80077ee: 739a strb r2, [r3, #14] + SubgRf.PacketParams.Params.Gfsk.PreambleLength = ( preambleLen << 3 ); // convert byte into bit + 80077f0: 8ebb ldrh r3, [r7, #52] @ 0x34 + 80077f2: 00db lsls r3, r3, #3 + 80077f4: b29a uxth r2, r3 + 80077f6: 4b97 ldr r3, [pc, #604] @ (8007a54 ) + 80077f8: 821a strh r2, [r3, #16] + SubgRf.PacketParams.Params.Gfsk.PreambleMinDetect = RADIO_PREAMBLE_DETECTOR_OFF; + 80077fa: 4b96 ldr r3, [pc, #600] @ (8007a54 ) + 80077fc: 2200 movs r2, #0 + 80077fe: 749a strb r2, [r3, #18] + SubgRf.PacketParams.Params.Gfsk.SyncWordLength = 2 << 3; // convert byte into bit + 8007800: 4b94 ldr r3, [pc, #592] @ (8007a54 ) + 8007802: 2210 movs r2, #16 + 8007804: 74da strb r2, [r3, #19] + SubgRf.PacketParams.Params.Gfsk.AddrComp = RADIO_ADDRESSCOMP_FILT_OFF; + 8007806: 4b93 ldr r3, [pc, #588] @ (8007a54 ) + 8007808: 2200 movs r2, #0 + 800780a: 751a strb r2, [r3, #20] + SubgRf.PacketParams.Params.Gfsk.HeaderType = RADIO_PACKET_FIXED_LENGTH; + 800780c: 4b91 ldr r3, [pc, #580] @ (8007a54 ) + 800780e: 2200 movs r2, #0 + 8007810: 755a strb r2, [r3, #21] + SubgRf.PacketParams.Params.Gfsk.PayloadLength = MaxPayloadLength; + 8007812: 4b91 ldr r3, [pc, #580] @ (8007a58 ) + 8007814: 781a ldrb r2, [r3, #0] + 8007816: 4b8f ldr r3, [pc, #572] @ (8007a54 ) + 8007818: 759a strb r2, [r3, #22] + SubgRf.PacketParams.Params.Gfsk.CrcLength = RADIO_CRC_OFF; + 800781a: 4b8e ldr r3, [pc, #568] @ (8007a54 ) + 800781c: 2201 movs r2, #1 + 800781e: 75da strb r2, [r3, #23] + SubgRf.PacketParams.Params.Gfsk.DcFree = RADIO_DC_FREE_OFF; + 8007820: 4b8c ldr r3, [pc, #560] @ (8007a54 ) + 8007822: 2200 movs r2, #0 + 8007824: 761a strb r2, [r3, #24] + RadioSetModem( MODEM_SIGFOX_RX ); + 8007826: 2005 movs r0, #5 + 8007828: f7ff fec2 bl 80075b0 + SUBGRF_SetModulationParams( &SubgRf.ModulationParams ); + 800782c: 488b ldr r0, [pc, #556] @ (8007a5c ) + 800782e: f002 fb5f bl 8009ef0 + SUBGRF_SetPacketParams( &SubgRf.PacketParams ); + 8007832: 488b ldr r0, [pc, #556] @ (8007a60 ) + 8007834: f002 fc2a bl 800a08c + SUBGRF_SetSyncWord( ( uint8_t[] ){0xB2, 0x27, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 } ); + 8007838: 4a8a ldr r2, [pc, #552] @ (8007a64 ) + 800783a: f107 031c add.w r3, r7, #28 + 800783e: e892 0003 ldmia.w r2, {r0, r1} + 8007842: e883 0003 stmia.w r3, {r0, r1} + 8007846: f107 031c add.w r3, r7, #28 + 800784a: 4618 mov r0, r3 + 800784c: f001 fee3 bl 8009616 + SUBGRF_SetWhiteningSeed( 0x01FF ); + 8007850: f240 10ff movw r0, #511 @ 0x1ff + 8007854: f001 ff2e bl 80096b4 + modReg= RadioRead(SUBGHZ_AGCGFORSTCFGR); + 8007858: f640 00b8 movw r0, #2232 @ 0x8b8 + 800785c: f000 fe36 bl 80084cc + 8007860: 4603 mov r3, r0 + 8007862: f887 3027 strb.w r3, [r7, #39] @ 0x27 + modReg&=RADIO_BIT_MASK(4); + 8007866: f897 3027 ldrb.w r3, [r7, #39] @ 0x27 + 800786a: f023 0310 bic.w r3, r3, #16 + 800786e: f887 3027 strb.w r3, [r7, #39] @ 0x27 + RadioWrite(SUBGHZ_AGCGFORSTCFGR, modReg); + 8007872: f897 3027 ldrb.w r3, [r7, #39] @ 0x27 + 8007876: 4619 mov r1, r3 + 8007878: f640 00b8 movw r0, #2232 @ 0x8b8 + 800787c: f000 fe14 bl 80084a8 + RadioWrite(SUBGHZ_AGCGFORSTPOWTHR, 0x4 ); + 8007880: 2104 movs r1, #4 + 8007882: f640 00b9 movw r0, #2233 @ 0x8b9 + 8007886: f000 fe0f bl 80084a8 + modReg= RadioRead(SUBGHZ_AGCRSSICTL0R); + 800788a: f640 009b movw r0, #2203 @ 0x89b + 800788e: f000 fe1d bl 80084cc + 8007892: 4603 mov r3, r0 + 8007894: f887 3027 strb.w r3, [r7, #39] @ 0x27 + modReg&=( RADIO_BIT_MASK(2) & RADIO_BIT_MASK(3) & RADIO_BIT_MASK(4) ); + 8007898: f897 3027 ldrb.w r3, [r7, #39] @ 0x27 + 800789c: f023 031c bic.w r3, r3, #28 + 80078a0: f887 3027 strb.w r3, [r7, #39] @ 0x27 + RadioWrite(SUBGHZ_AGCRSSICTL0R, (modReg| (0x1<<3) ) ); + 80078a4: f897 3027 ldrb.w r3, [r7, #39] @ 0x27 + 80078a8: f043 0308 orr.w r3, r3, #8 + 80078ac: b2db uxtb r3, r3 + 80078ae: 4619 mov r1, r3 + 80078b0: f640 009b movw r0, #2203 @ 0x89b + 80078b4: f000 fdf8 bl 80084a8 + modReg= RadioRead(SUBGHZ_GAFCR); + 80078b8: f240 60d1 movw r0, #1745 @ 0x6d1 + 80078bc: f000 fe06 bl 80084cc + 80078c0: 4603 mov r3, r0 + 80078c2: f887 3027 strb.w r3, [r7, #39] @ 0x27 + modReg&=( RADIO_BIT_MASK(3) & RADIO_BIT_MASK(4) ); + 80078c6: f897 3027 ldrb.w r3, [r7, #39] @ 0x27 + 80078ca: f023 0318 bic.w r3, r3, #24 + 80078ce: f887 3027 strb.w r3, [r7, #39] @ 0x27 + RadioWrite(SUBGHZ_GAFCR, (modReg| (0x3<<3) )); + 80078d2: f897 3027 ldrb.w r3, [r7, #39] @ 0x27 + 80078d6: f043 0318 orr.w r3, r3, #24 + 80078da: b2db uxtb r3, r3 + 80078dc: 4619 mov r1, r3 + 80078de: f240 60d1 movw r0, #1745 @ 0x6d1 + 80078e2: f000 fde1 bl 80084a8 + modReg= RadioRead(SUBGHZ_GBSYNCR); + 80078e6: f240 60ac movw r0, #1708 @ 0x6ac + 80078ea: f000 fdef bl 80084cc + 80078ee: 4603 mov r3, r0 + 80078f0: f887 3027 strb.w r3, [r7, #39] @ 0x27 + modReg&=( RADIO_BIT_MASK(4) & RADIO_BIT_MASK(5) & RADIO_BIT_MASK(6) ); + 80078f4: f897 3027 ldrb.w r3, [r7, #39] @ 0x27 + 80078f8: f023 0370 bic.w r3, r3, #112 @ 0x70 + 80078fc: f887 3027 strb.w r3, [r7, #39] @ 0x27 + RadioWrite(SUBGHZ_GBSYNCR, (modReg| (0x5<<4) )); + 8007900: f897 3027 ldrb.w r3, [r7, #39] @ 0x27 + 8007904: f043 0350 orr.w r3, r3, #80 @ 0x50 + 8007908: b2db uxtb r3, r3 + 800790a: 4619 mov r1, r3 + 800790c: f240 60ac movw r0, #1708 @ 0x6ac + 8007910: f000 fdca bl 80084a8 + SubgRf.RxTimeout = ( uint32_t )(( symbTimeout * 8 * 1000 ) /datarate); + 8007914: 8f3b ldrh r3, [r7, #56] @ 0x38 + 8007916: f44f 52fa mov.w r2, #8000 @ 0x1f40 + 800791a: fb02 f303 mul.w r3, r2, r3 + 800791e: 461a mov r2, r3 + 8007920: 687b ldr r3, [r7, #4] + 8007922: fbb2 f3f3 udiv r3, r2, r3 + 8007926: 4a4b ldr r2, [pc, #300] @ (8007a54 ) + 8007928: 6093 str r3, [r2, #8] + break; + 800792a: e115 b.n 8007b58 + SUBGRF_SetStopRxTimerOnPreambleDetect( false ); + 800792c: 2000 movs r0, #0 + 800792e: f002 f83b bl 80099a8 + SubgRf.ModulationParams.PacketType = PACKET_TYPE_GFSK; + 8007932: 4b48 ldr r3, [pc, #288] @ (8007a54 ) + 8007934: 2200 movs r2, #0 + 8007936: f883 2038 strb.w r2, [r3, #56] @ 0x38 + SubgRf.ModulationParams.Params.Gfsk.BitRate = datarate; + 800793a: 4a46 ldr r2, [pc, #280] @ (8007a54 ) + 800793c: 687b ldr r3, [r7, #4] + 800793e: 63d3 str r3, [r2, #60] @ 0x3c + SubgRf.ModulationParams.Params.Gfsk.ModulationShaping = MOD_SHAPING_G_BT_1; + 8007940: 4b44 ldr r3, [pc, #272] @ (8007a54 ) + 8007942: 220b movs r2, #11 + 8007944: f883 2044 strb.w r2, [r3, #68] @ 0x44 + SubgRf.ModulationParams.Params.Gfsk.Bandwidth = SUBGRF_GetFskBandwidthRegValue( bandwidth ); + 8007948: 68b8 ldr r0, [r7, #8] + 800794a: f002 ff19 bl 800a780 + 800794e: 4603 mov r3, r0 + 8007950: 461a mov r2, r3 + 8007952: 4b40 ldr r3, [pc, #256] @ (8007a54 ) + 8007954: f883 2045 strb.w r2, [r3, #69] @ 0x45 + SubgRf.PacketParams.PacketType = PACKET_TYPE_GFSK; + 8007958: 4b3e ldr r3, [pc, #248] @ (8007a54 ) + 800795a: 2200 movs r2, #0 + 800795c: 739a strb r2, [r3, #14] + SubgRf.PacketParams.Params.Gfsk.PreambleLength = ( preambleLen << 3 ); // convert byte into bit + 800795e: 8ebb ldrh r3, [r7, #52] @ 0x34 + 8007960: 00db lsls r3, r3, #3 + 8007962: b29a uxth r2, r3 + 8007964: 4b3b ldr r3, [pc, #236] @ (8007a54 ) + 8007966: 821a strh r2, [r3, #16] + SubgRf.PacketParams.Params.Gfsk.PreambleMinDetect = RADIO_PREAMBLE_DETECTOR_08_BITS; + 8007968: 4b3a ldr r3, [pc, #232] @ (8007a54 ) + 800796a: 2204 movs r2, #4 + 800796c: 749a strb r2, [r3, #18] + SubgRf.PacketParams.Params.Gfsk.SyncWordLength = 3 << 3; // convert byte into bit + 800796e: 4b39 ldr r3, [pc, #228] @ (8007a54 ) + 8007970: 2218 movs r2, #24 + 8007972: 74da strb r2, [r3, #19] + SubgRf.PacketParams.Params.Gfsk.AddrComp = RADIO_ADDRESSCOMP_FILT_OFF; + 8007974: 4b37 ldr r3, [pc, #220] @ (8007a54 ) + 8007976: 2200 movs r2, #0 + 8007978: 751a strb r2, [r3, #20] + SubgRf.PacketParams.Params.Gfsk.HeaderType = ( fixLen == true ) ? RADIO_PACKET_FIXED_LENGTH : RADIO_PACKET_VARIABLE_LENGTH; + 800797a: f897 303c ldrb.w r3, [r7, #60] @ 0x3c + 800797e: f083 0301 eor.w r3, r3, #1 + 8007982: b2db uxtb r3, r3 + 8007984: 461a mov r2, r3 + 8007986: 4b33 ldr r3, [pc, #204] @ (8007a54 ) + 8007988: 755a strb r2, [r3, #21] + SubgRf.PacketParams.Params.Gfsk.PayloadLength = MaxPayloadLength; + 800798a: 4b33 ldr r3, [pc, #204] @ (8007a58 ) + 800798c: 781a ldrb r2, [r3, #0] + 800798e: 4b31 ldr r3, [pc, #196] @ (8007a54 ) + 8007990: 759a strb r2, [r3, #22] + if( crcOn == true ) + 8007992: f897 3044 ldrb.w r3, [r7, #68] @ 0x44 + 8007996: 2b00 cmp r3, #0 + 8007998: d003 beq.n 80079a2 + SubgRf.PacketParams.Params.Gfsk.CrcLength = RADIO_CRC_2_BYTES_CCIT; + 800799a: 4b2e ldr r3, [pc, #184] @ (8007a54 ) + 800799c: 22f2 movs r2, #242 @ 0xf2 + 800799e: 75da strb r2, [r3, #23] + 80079a0: e002 b.n 80079a8 + SubgRf.PacketParams.Params.Gfsk.CrcLength = RADIO_CRC_OFF; + 80079a2: 4b2c ldr r3, [pc, #176] @ (8007a54 ) + 80079a4: 2201 movs r2, #1 + 80079a6: 75da strb r2, [r3, #23] + SubgRf.PacketParams.Params.Gfsk.DcFree = RADIO_DC_FREEWHITENING; + 80079a8: 4b2a ldr r3, [pc, #168] @ (8007a54 ) + 80079aa: 2201 movs r2, #1 + 80079ac: 761a strb r2, [r3, #24] + RadioStandby( ); + 80079ae: f000 fc6e bl 800828e + RadioSetModem( MODEM_FSK ); + 80079b2: 2000 movs r0, #0 + 80079b4: f7ff fdfc bl 80075b0 + SUBGRF_SetModulationParams( &SubgRf.ModulationParams ); + 80079b8: 4828 ldr r0, [pc, #160] @ (8007a5c ) + 80079ba: f002 fa99 bl 8009ef0 + SUBGRF_SetPacketParams( &SubgRf.PacketParams ); + 80079be: 4828 ldr r0, [pc, #160] @ (8007a60 ) + 80079c0: f002 fb64 bl 800a08c + SUBGRF_SetSyncWord( ( uint8_t[] ){ 0xC1, 0x94, 0xC1, 0x00, 0x00, 0x00, 0x00, 0x00 } ); + 80079c4: 4a28 ldr r2, [pc, #160] @ (8007a68 ) + 80079c6: f107 0314 add.w r3, r7, #20 + 80079ca: e892 0003 ldmia.w r2, {r0, r1} + 80079ce: e883 0003 stmia.w r3, {r0, r1} + 80079d2: f107 0314 add.w r3, r7, #20 + 80079d6: 4618 mov r0, r3 + 80079d8: f001 fe1d bl 8009616 + SUBGRF_SetWhiteningSeed( 0x01FF ); + 80079dc: f240 10ff movw r0, #511 @ 0x1ff + 80079e0: f001 fe68 bl 80096b4 + SubgRf.RxTimeout = ( uint32_t )(( symbTimeout * 8 * 1000 ) /datarate); + 80079e4: 8f3b ldrh r3, [r7, #56] @ 0x38 + 80079e6: f44f 52fa mov.w r2, #8000 @ 0x1f40 + 80079ea: fb02 f303 mul.w r3, r2, r3 + 80079ee: 461a mov r2, r3 + 80079f0: 687b ldr r3, [r7, #4] + 80079f2: fbb2 f3f3 udiv r3, r2, r3 + 80079f6: 4a17 ldr r2, [pc, #92] @ (8007a54 ) + 80079f8: 6093 str r3, [r2, #8] + break; + 80079fa: e0ad b.n 8007b58 + SUBGRF_SetStopRxTimerOnPreambleDetect( false ); + 80079fc: 2000 movs r0, #0 + 80079fe: f001 ffd3 bl 80099a8 + SubgRf.ModulationParams.PacketType = PACKET_TYPE_LORA; + 8007a02: 4b14 ldr r3, [pc, #80] @ (8007a54 ) + 8007a04: 2201 movs r2, #1 + 8007a06: f883 2038 strb.w r2, [r3, #56] @ 0x38 + SubgRf.ModulationParams.Params.LoRa.SpreadingFactor = ( RadioLoRaSpreadingFactors_t )datarate; + 8007a0a: 687b ldr r3, [r7, #4] + 8007a0c: b2da uxtb r2, r3 + 8007a0e: 4b11 ldr r3, [pc, #68] @ (8007a54 ) + 8007a10: f883 2050 strb.w r2, [r3, #80] @ 0x50 + SubgRf.ModulationParams.Params.LoRa.Bandwidth = Bandwidths[bandwidth]; + 8007a14: 4a15 ldr r2, [pc, #84] @ (8007a6c ) + 8007a16: 68bb ldr r3, [r7, #8] + 8007a18: 4413 add r3, r2 + 8007a1a: 781a ldrb r2, [r3, #0] + 8007a1c: 4b0d ldr r3, [pc, #52] @ (8007a54 ) + 8007a1e: f883 2051 strb.w r2, [r3, #81] @ 0x51 + SubgRf.ModulationParams.Params.LoRa.CodingRate = ( RadioLoRaCodingRates_t )coderate; + 8007a22: 4a0c ldr r2, [pc, #48] @ (8007a54 ) + 8007a24: 7bbb ldrb r3, [r7, #14] + 8007a26: f882 3052 strb.w r3, [r2, #82] @ 0x52 + if( ( ( bandwidth == 0 ) && ( ( datarate == 11 ) || ( datarate == 12 ) ) ) || + 8007a2a: 68bb ldr r3, [r7, #8] + 8007a2c: 2b00 cmp r3, #0 + 8007a2e: d105 bne.n 8007a3c + 8007a30: 687b ldr r3, [r7, #4] + 8007a32: 2b0b cmp r3, #11 + 8007a34: d008 beq.n 8007a48 + 8007a36: 687b ldr r3, [r7, #4] + 8007a38: 2b0c cmp r3, #12 + 8007a3a: d005 beq.n 8007a48 + 8007a3c: 68bb ldr r3, [r7, #8] + 8007a3e: 2b01 cmp r3, #1 + 8007a40: d116 bne.n 8007a70 + ( ( bandwidth == 1 ) && ( datarate == 12 ) ) ) + 8007a42: 687b ldr r3, [r7, #4] + 8007a44: 2b0c cmp r3, #12 + 8007a46: d113 bne.n 8007a70 + SubgRf.ModulationParams.Params.LoRa.LowDatarateOptimize = 0x01; + 8007a48: 4b02 ldr r3, [pc, #8] @ (8007a54 ) + 8007a4a: 2201 movs r2, #1 + 8007a4c: f883 2053 strb.w r2, [r3, #83] @ 0x53 + 8007a50: e012 b.n 8007a78 + 8007a52: bf00 nop + 8007a54: 20000290 .word 0x20000290 + 8007a58: 20000008 .word 0x20000008 + 8007a5c: 200002c8 .word 0x200002c8 + 8007a60: 2000029e .word 0x2000029e + 8007a64: 0800d528 .word 0x0800d528 + 8007a68: 0800d530 .word 0x0800d530 + 8007a6c: 0800da6c .word 0x0800da6c + SubgRf.ModulationParams.Params.LoRa.LowDatarateOptimize = 0x00; + 8007a70: 4b3b ldr r3, [pc, #236] @ (8007b60 ) + 8007a72: 2200 movs r2, #0 + 8007a74: f883 2053 strb.w r2, [r3, #83] @ 0x53 + SubgRf.PacketParams.PacketType = PACKET_TYPE_LORA; + 8007a78: 4b39 ldr r3, [pc, #228] @ (8007b60 ) + 8007a7a: 2201 movs r2, #1 + 8007a7c: 739a strb r2, [r3, #14] + if( ( SubgRf.ModulationParams.Params.LoRa.SpreadingFactor == LORA_SF5 ) || + 8007a7e: 4b38 ldr r3, [pc, #224] @ (8007b60 ) + 8007a80: f893 3050 ldrb.w r3, [r3, #80] @ 0x50 + 8007a84: 2b05 cmp r3, #5 + 8007a86: d004 beq.n 8007a92 + ( SubgRf.ModulationParams.Params.LoRa.SpreadingFactor == LORA_SF6 ) ) + 8007a88: 4b35 ldr r3, [pc, #212] @ (8007b60 ) + 8007a8a: f893 3050 ldrb.w r3, [r3, #80] @ 0x50 + if( ( SubgRf.ModulationParams.Params.LoRa.SpreadingFactor == LORA_SF5 ) || + 8007a8e: 2b06 cmp r3, #6 + 8007a90: d10a bne.n 8007aa8 + if( preambleLen < 12 ) + 8007a92: 8ebb ldrh r3, [r7, #52] @ 0x34 + 8007a94: 2b0b cmp r3, #11 + 8007a96: d803 bhi.n 8007aa0 + SubgRf.PacketParams.Params.LoRa.PreambleLength = 12; + 8007a98: 4b31 ldr r3, [pc, #196] @ (8007b60 ) + 8007a9a: 220c movs r2, #12 + 8007a9c: 839a strh r2, [r3, #28] + if( preambleLen < 12 ) + 8007a9e: e006 b.n 8007aae + SubgRf.PacketParams.Params.LoRa.PreambleLength = preambleLen; + 8007aa0: 4a2f ldr r2, [pc, #188] @ (8007b60 ) + 8007aa2: 8ebb ldrh r3, [r7, #52] @ 0x34 + 8007aa4: 8393 strh r3, [r2, #28] + if( preambleLen < 12 ) + 8007aa6: e002 b.n 8007aae + SubgRf.PacketParams.Params.LoRa.PreambleLength = preambleLen; + 8007aa8: 4a2d ldr r2, [pc, #180] @ (8007b60 ) + 8007aaa: 8ebb ldrh r3, [r7, #52] @ 0x34 + 8007aac: 8393 strh r3, [r2, #28] + SubgRf.PacketParams.Params.LoRa.HeaderType = ( RadioLoRaPacketLengthsMode_t )fixLen; + 8007aae: f897 203c ldrb.w r2, [r7, #60] @ 0x3c + 8007ab2: 4b2b ldr r3, [pc, #172] @ (8007b60 ) + 8007ab4: 779a strb r2, [r3, #30] + SubgRf.PacketParams.Params.LoRa.PayloadLength = MaxPayloadLength; + 8007ab6: 4b2b ldr r3, [pc, #172] @ (8007b64 ) + 8007ab8: 781a ldrb r2, [r3, #0] + 8007aba: 4b29 ldr r3, [pc, #164] @ (8007b60 ) + 8007abc: 77da strb r2, [r3, #31] + SubgRf.PacketParams.Params.LoRa.CrcMode = ( RadioLoRaCrcModes_t )crcOn; + 8007abe: f897 2044 ldrb.w r2, [r7, #68] @ 0x44 + 8007ac2: 4b27 ldr r3, [pc, #156] @ (8007b60 ) + 8007ac4: f883 2020 strb.w r2, [r3, #32] + SubgRf.PacketParams.Params.LoRa.InvertIQ = ( RadioLoRaIQModes_t )iqInverted; + 8007ac8: f897 2050 ldrb.w r2, [r7, #80] @ 0x50 + 8007acc: 4b24 ldr r3, [pc, #144] @ (8007b60 ) + 8007ace: f883 2021 strb.w r2, [r3, #33] @ 0x21 + RadioStandby( ); + 8007ad2: f000 fbdc bl 800828e + RadioSetModem( MODEM_LORA ); + 8007ad6: 2001 movs r0, #1 + 8007ad8: f7ff fd6a bl 80075b0 + SUBGRF_SetModulationParams( &SubgRf.ModulationParams ); + 8007adc: 4822 ldr r0, [pc, #136] @ (8007b68 ) + 8007ade: f002 fa07 bl 8009ef0 + SUBGRF_SetPacketParams( &SubgRf.PacketParams ); + 8007ae2: 4822 ldr r0, [pc, #136] @ (8007b6c ) + 8007ae4: f002 fad2 bl 800a08c + SUBGRF_SetLoRaSymbNumTimeout( symbTimeout ); + 8007ae8: 8f3b ldrh r3, [r7, #56] @ 0x38 + 8007aea: b2db uxtb r3, r3 + 8007aec: 4618 mov r0, r3 + 8007aee: f001 ff6a bl 80099c6 + SUBGRF_WriteRegister(SUBGHZ_AGCCFG,SUBGRF_ReadRegister(SUBGHZ_AGCCFG)&0x1); + 8007af2: f640 00a3 movw r0, #2211 @ 0x8a3 + 8007af6: f002 fc31 bl 800a35c + 8007afa: 4603 mov r3, r0 + 8007afc: f003 0301 and.w r3, r3, #1 + 8007b00: b2db uxtb r3, r3 + 8007b02: 4619 mov r1, r3 + 8007b04: f640 00a3 movw r0, #2211 @ 0x8a3 + 8007b08: f002 fc06 bl 800a318 + if( SubgRf.PacketParams.Params.LoRa.InvertIQ == LORA_IQ_INVERTED ) + 8007b0c: 4b14 ldr r3, [pc, #80] @ (8007b60 ) + 8007b0e: f893 3021 ldrb.w r3, [r3, #33] @ 0x21 + 8007b12: 2b01 cmp r3, #1 + 8007b14: d10d bne.n 8007b32 + SUBGRF_WriteRegister( SUBGHZ_LIQPOLR, SUBGRF_ReadRegister( SUBGHZ_LIQPOLR ) & ~( 1 << 2 ) ); + 8007b16: f240 7036 movw r0, #1846 @ 0x736 + 8007b1a: f002 fc1f bl 800a35c + 8007b1e: 4603 mov r3, r0 + 8007b20: f023 0304 bic.w r3, r3, #4 + 8007b24: b2db uxtb r3, r3 + 8007b26: 4619 mov r1, r3 + 8007b28: f240 7036 movw r0, #1846 @ 0x736 + 8007b2c: f002 fbf4 bl 800a318 + 8007b30: e00c b.n 8007b4c + SUBGRF_WriteRegister( SUBGHZ_LIQPOLR, SUBGRF_ReadRegister( SUBGHZ_LIQPOLR ) | ( 1 << 2 ) ); + 8007b32: f240 7036 movw r0, #1846 @ 0x736 + 8007b36: f002 fc11 bl 800a35c + 8007b3a: 4603 mov r3, r0 + 8007b3c: f043 0304 orr.w r3, r3, #4 + 8007b40: b2db uxtb r3, r3 + 8007b42: 4619 mov r1, r3 + 8007b44: f240 7036 movw r0, #1846 @ 0x736 + 8007b48: f002 fbe6 bl 800a318 + SubgRf.RxTimeout = 0xFFFF; + 8007b4c: 4b04 ldr r3, [pc, #16] @ (8007b60 ) + 8007b4e: f64f 72ff movw r2, #65535 @ 0xffff + 8007b52: 609a str r2, [r3, #8] + break; + 8007b54: e000 b.n 8007b58 + break; + 8007b56: bf00 nop + } +} + 8007b58: bf00 nop + 8007b5a: 3728 adds r7, #40 @ 0x28 + 8007b5c: 46bd mov sp, r7 + 8007b5e: bd80 pop {r7, pc} + 8007b60: 20000290 .word 0x20000290 + 8007b64: 20000008 .word 0x20000008 + 8007b68: 200002c8 .word 0x200002c8 + 8007b6c: 2000029e .word 0x2000029e + +08007b70 : +static void RadioSetTxConfig( RadioModems_t modem, int8_t power, uint32_t fdev, + uint32_t bandwidth, uint32_t datarate, + uint8_t coderate, uint16_t preambleLen, + bool fixLen, bool crcOn, bool freqHopOn, + uint8_t hopPeriod, bool iqInverted, uint32_t timeout ) +{ + 8007b70: b580 push {r7, lr} + 8007b72: b086 sub sp, #24 + 8007b74: af00 add r7, sp, #0 + 8007b76: 60ba str r2, [r7, #8] + 8007b78: 607b str r3, [r7, #4] + 8007b7a: 4603 mov r3, r0 + 8007b7c: 73fb strb r3, [r7, #15] + 8007b7e: 460b mov r3, r1 + 8007b80: 73bb strb r3, [r7, #14] +#if( RADIO_LR_FHSS_IS_ON == 1 ) + /*disable LrFhss*/ + SubgRf.lr_fhss.is_lr_fhss_on = false; +#endif /* RADIO_LR_FHSS_IS_ON == 1 */ + RFW_DeInit(); + 8007b82: f003 f939 bl 800adf8 + switch( modem ) + 8007b86: 7bfb ldrb r3, [r7, #15] + 8007b88: 2b04 cmp r3, #4 + 8007b8a: f000 80c7 beq.w 8007d1c + 8007b8e: 2b04 cmp r3, #4 + 8007b90: f300 80d6 bgt.w 8007d40 + 8007b94: 2b00 cmp r3, #0 + 8007b96: d002 beq.n 8007b9e + 8007b98: 2b01 cmp r3, #1 + 8007b9a: d059 beq.n 8007c50 + SubgRf.ModulationParams.Params.Bpsk.ModulationShaping = MOD_SHAPING_DBPSK; + SUBGRF_SetModulationParams( &SubgRf.ModulationParams ); + break; +#endif /*RADIO_SIGFOX_ENABLE == 1*/ + default: + break; + 8007b9c: e0d0 b.n 8007d40 + SubgRf.ModulationParams.PacketType = PACKET_TYPE_GFSK; + 8007b9e: 4b77 ldr r3, [pc, #476] @ (8007d7c ) + 8007ba0: 2200 movs r2, #0 + 8007ba2: f883 2038 strb.w r2, [r3, #56] @ 0x38 + SubgRf.ModulationParams.Params.Gfsk.BitRate = datarate; + 8007ba6: 4a75 ldr r2, [pc, #468] @ (8007d7c ) + 8007ba8: 6a3b ldr r3, [r7, #32] + 8007baa: 63d3 str r3, [r2, #60] @ 0x3c + SubgRf.ModulationParams.Params.Gfsk.ModulationShaping = MOD_SHAPING_G_BT_1; + 8007bac: 4b73 ldr r3, [pc, #460] @ (8007d7c ) + 8007bae: 220b movs r2, #11 + 8007bb0: f883 2044 strb.w r2, [r3, #68] @ 0x44 + SubgRf.ModulationParams.Params.Gfsk.Bandwidth = SUBGRF_GetFskBandwidthRegValue( bandwidth ); + 8007bb4: 6878 ldr r0, [r7, #4] + 8007bb6: f002 fde3 bl 800a780 + 8007bba: 4603 mov r3, r0 + 8007bbc: 461a mov r2, r3 + 8007bbe: 4b6f ldr r3, [pc, #444] @ (8007d7c ) + 8007bc0: f883 2045 strb.w r2, [r3, #69] @ 0x45 + SubgRf.ModulationParams.Params.Gfsk.Fdev = fdev; + 8007bc4: 4a6d ldr r2, [pc, #436] @ (8007d7c ) + 8007bc6: 68bb ldr r3, [r7, #8] + 8007bc8: 6413 str r3, [r2, #64] @ 0x40 + SubgRf.PacketParams.PacketType = PACKET_TYPE_GFSK; + 8007bca: 4b6c ldr r3, [pc, #432] @ (8007d7c ) + 8007bcc: 2200 movs r2, #0 + 8007bce: 739a strb r2, [r3, #14] + SubgRf.PacketParams.Params.Gfsk.PreambleLength = ( preambleLen << 3 ); // convert byte into bit + 8007bd0: 8d3b ldrh r3, [r7, #40] @ 0x28 + 8007bd2: 00db lsls r3, r3, #3 + 8007bd4: b29a uxth r2, r3 + 8007bd6: 4b69 ldr r3, [pc, #420] @ (8007d7c ) + 8007bd8: 821a strh r2, [r3, #16] + SubgRf.PacketParams.Params.Gfsk.PreambleMinDetect = RADIO_PREAMBLE_DETECTOR_08_BITS; + 8007bda: 4b68 ldr r3, [pc, #416] @ (8007d7c ) + 8007bdc: 2204 movs r2, #4 + 8007bde: 749a strb r2, [r3, #18] + SubgRf.PacketParams.Params.Gfsk.SyncWordLength = 3 << 3 ; // convert byte into bit + 8007be0: 4b66 ldr r3, [pc, #408] @ (8007d7c ) + 8007be2: 2218 movs r2, #24 + 8007be4: 74da strb r2, [r3, #19] + SubgRf.PacketParams.Params.Gfsk.AddrComp = RADIO_ADDRESSCOMP_FILT_OFF; + 8007be6: 4b65 ldr r3, [pc, #404] @ (8007d7c ) + 8007be8: 2200 movs r2, #0 + 8007bea: 751a strb r2, [r3, #20] + SubgRf.PacketParams.Params.Gfsk.HeaderType = ( fixLen == true ) ? RADIO_PACKET_FIXED_LENGTH : RADIO_PACKET_VARIABLE_LENGTH; + 8007bec: f897 302c ldrb.w r3, [r7, #44] @ 0x2c + 8007bf0: f083 0301 eor.w r3, r3, #1 + 8007bf4: b2db uxtb r3, r3 + 8007bf6: 461a mov r2, r3 + 8007bf8: 4b60 ldr r3, [pc, #384] @ (8007d7c ) + 8007bfa: 755a strb r2, [r3, #21] + if( crcOn == true ) + 8007bfc: f897 3030 ldrb.w r3, [r7, #48] @ 0x30 + 8007c00: 2b00 cmp r3, #0 + 8007c02: d003 beq.n 8007c0c + SubgRf.PacketParams.Params.Gfsk.CrcLength = RADIO_CRC_2_BYTES_CCIT; + 8007c04: 4b5d ldr r3, [pc, #372] @ (8007d7c ) + 8007c06: 22f2 movs r2, #242 @ 0xf2 + 8007c08: 75da strb r2, [r3, #23] + 8007c0a: e002 b.n 8007c12 + SubgRf.PacketParams.Params.Gfsk.CrcLength = RADIO_CRC_OFF; + 8007c0c: 4b5b ldr r3, [pc, #364] @ (8007d7c ) + 8007c0e: 2201 movs r2, #1 + 8007c10: 75da strb r2, [r3, #23] + SubgRf.PacketParams.Params.Gfsk.DcFree = RADIO_DC_FREEWHITENING; + 8007c12: 4b5a ldr r3, [pc, #360] @ (8007d7c ) + 8007c14: 2201 movs r2, #1 + 8007c16: 761a strb r2, [r3, #24] + RadioStandby( ); + 8007c18: f000 fb39 bl 800828e + RadioSetModem( MODEM_FSK ); + 8007c1c: 2000 movs r0, #0 + 8007c1e: f7ff fcc7 bl 80075b0 + SUBGRF_SetModulationParams( &SubgRf.ModulationParams ); + 8007c22: 4857 ldr r0, [pc, #348] @ (8007d80 ) + 8007c24: f002 f964 bl 8009ef0 + SUBGRF_SetPacketParams( &SubgRf.PacketParams ); + 8007c28: 4856 ldr r0, [pc, #344] @ (8007d84 ) + 8007c2a: f002 fa2f bl 800a08c + SUBGRF_SetSyncWord( ( uint8_t[] ){ 0xC1, 0x94, 0xC1, 0x00, 0x00, 0x00, 0x00, 0x00 } ); + 8007c2e: 4a56 ldr r2, [pc, #344] @ (8007d88 ) + 8007c30: f107 0310 add.w r3, r7, #16 + 8007c34: e892 0003 ldmia.w r2, {r0, r1} + 8007c38: e883 0003 stmia.w r3, {r0, r1} + 8007c3c: f107 0310 add.w r3, r7, #16 + 8007c40: 4618 mov r0, r3 + 8007c42: f001 fce8 bl 8009616 + SUBGRF_SetWhiteningSeed( 0x01FF ); + 8007c46: f240 10ff movw r0, #511 @ 0x1ff + 8007c4a: f001 fd33 bl 80096b4 + break; + 8007c4e: e078 b.n 8007d42 + SubgRf.ModulationParams.PacketType = PACKET_TYPE_LORA; + 8007c50: 4b4a ldr r3, [pc, #296] @ (8007d7c ) + 8007c52: 2201 movs r2, #1 + 8007c54: f883 2038 strb.w r2, [r3, #56] @ 0x38 + SubgRf.ModulationParams.Params.LoRa.SpreadingFactor = ( RadioLoRaSpreadingFactors_t ) datarate; + 8007c58: 6a3b ldr r3, [r7, #32] + 8007c5a: b2da uxtb r2, r3 + 8007c5c: 4b47 ldr r3, [pc, #284] @ (8007d7c ) + 8007c5e: f883 2050 strb.w r2, [r3, #80] @ 0x50 + SubgRf.ModulationParams.Params.LoRa.Bandwidth = Bandwidths[bandwidth]; + 8007c62: 4a4a ldr r2, [pc, #296] @ (8007d8c ) + 8007c64: 687b ldr r3, [r7, #4] + 8007c66: 4413 add r3, r2 + 8007c68: 781a ldrb r2, [r3, #0] + 8007c6a: 4b44 ldr r3, [pc, #272] @ (8007d7c ) + 8007c6c: f883 2051 strb.w r2, [r3, #81] @ 0x51 + SubgRf.ModulationParams.Params.LoRa.CodingRate= ( RadioLoRaCodingRates_t )coderate; + 8007c70: 4a42 ldr r2, [pc, #264] @ (8007d7c ) + 8007c72: f897 3024 ldrb.w r3, [r7, #36] @ 0x24 + 8007c76: f882 3052 strb.w r3, [r2, #82] @ 0x52 + if( ( ( bandwidth == 0 ) && ( ( datarate == 11 ) || ( datarate == 12 ) ) ) || + 8007c7a: 687b ldr r3, [r7, #4] + 8007c7c: 2b00 cmp r3, #0 + 8007c7e: d105 bne.n 8007c8c + 8007c80: 6a3b ldr r3, [r7, #32] + 8007c82: 2b0b cmp r3, #11 + 8007c84: d008 beq.n 8007c98 + 8007c86: 6a3b ldr r3, [r7, #32] + 8007c88: 2b0c cmp r3, #12 + 8007c8a: d005 beq.n 8007c98 + 8007c8c: 687b ldr r3, [r7, #4] + 8007c8e: 2b01 cmp r3, #1 + 8007c90: d107 bne.n 8007ca2 + ( ( bandwidth == 1 ) && ( datarate == 12 ) ) ) + 8007c92: 6a3b ldr r3, [r7, #32] + 8007c94: 2b0c cmp r3, #12 + 8007c96: d104 bne.n 8007ca2 + SubgRf.ModulationParams.Params.LoRa.LowDatarateOptimize = 0x01; + 8007c98: 4b38 ldr r3, [pc, #224] @ (8007d7c ) + 8007c9a: 2201 movs r2, #1 + 8007c9c: f883 2053 strb.w r2, [r3, #83] @ 0x53 + 8007ca0: e003 b.n 8007caa + SubgRf.ModulationParams.Params.LoRa.LowDatarateOptimize = 0x00; + 8007ca2: 4b36 ldr r3, [pc, #216] @ (8007d7c ) + 8007ca4: 2200 movs r2, #0 + 8007ca6: f883 2053 strb.w r2, [r3, #83] @ 0x53 + SubgRf.PacketParams.PacketType = PACKET_TYPE_LORA; + 8007caa: 4b34 ldr r3, [pc, #208] @ (8007d7c ) + 8007cac: 2201 movs r2, #1 + 8007cae: 739a strb r2, [r3, #14] + if( ( SubgRf.ModulationParams.Params.LoRa.SpreadingFactor == LORA_SF5 ) || + 8007cb0: 4b32 ldr r3, [pc, #200] @ (8007d7c ) + 8007cb2: f893 3050 ldrb.w r3, [r3, #80] @ 0x50 + 8007cb6: 2b05 cmp r3, #5 + 8007cb8: d004 beq.n 8007cc4 + ( SubgRf.ModulationParams.Params.LoRa.SpreadingFactor == LORA_SF6 ) ) + 8007cba: 4b30 ldr r3, [pc, #192] @ (8007d7c ) + 8007cbc: f893 3050 ldrb.w r3, [r3, #80] @ 0x50 + if( ( SubgRf.ModulationParams.Params.LoRa.SpreadingFactor == LORA_SF5 ) || + 8007cc0: 2b06 cmp r3, #6 + 8007cc2: d10a bne.n 8007cda + if( preambleLen < 12 ) + 8007cc4: 8d3b ldrh r3, [r7, #40] @ 0x28 + 8007cc6: 2b0b cmp r3, #11 + 8007cc8: d803 bhi.n 8007cd2 + SubgRf.PacketParams.Params.LoRa.PreambleLength = 12; + 8007cca: 4b2c ldr r3, [pc, #176] @ (8007d7c ) + 8007ccc: 220c movs r2, #12 + 8007cce: 839a strh r2, [r3, #28] + if( preambleLen < 12 ) + 8007cd0: e006 b.n 8007ce0 + SubgRf.PacketParams.Params.LoRa.PreambleLength = preambleLen; + 8007cd2: 4a2a ldr r2, [pc, #168] @ (8007d7c ) + 8007cd4: 8d3b ldrh r3, [r7, #40] @ 0x28 + 8007cd6: 8393 strh r3, [r2, #28] + if( preambleLen < 12 ) + 8007cd8: e002 b.n 8007ce0 + SubgRf.PacketParams.Params.LoRa.PreambleLength = preambleLen; + 8007cda: 4a28 ldr r2, [pc, #160] @ (8007d7c ) + 8007cdc: 8d3b ldrh r3, [r7, #40] @ 0x28 + 8007cde: 8393 strh r3, [r2, #28] + SubgRf.PacketParams.Params.LoRa.HeaderType = ( RadioLoRaPacketLengthsMode_t )fixLen; + 8007ce0: f897 202c ldrb.w r2, [r7, #44] @ 0x2c + 8007ce4: 4b25 ldr r3, [pc, #148] @ (8007d7c ) + 8007ce6: 779a strb r2, [r3, #30] + SubgRf.PacketParams.Params.LoRa.PayloadLength = MaxPayloadLength; + 8007ce8: 4b29 ldr r3, [pc, #164] @ (8007d90 ) + 8007cea: 781a ldrb r2, [r3, #0] + 8007cec: 4b23 ldr r3, [pc, #140] @ (8007d7c ) + 8007cee: 77da strb r2, [r3, #31] + SubgRf.PacketParams.Params.LoRa.CrcMode = ( RadioLoRaCrcModes_t )crcOn; + 8007cf0: f897 2030 ldrb.w r2, [r7, #48] @ 0x30 + 8007cf4: 4b21 ldr r3, [pc, #132] @ (8007d7c ) + 8007cf6: f883 2020 strb.w r2, [r3, #32] + SubgRf.PacketParams.Params.LoRa.InvertIQ = ( RadioLoRaIQModes_t )iqInverted; + 8007cfa: f897 203c ldrb.w r2, [r7, #60] @ 0x3c + 8007cfe: 4b1f ldr r3, [pc, #124] @ (8007d7c ) + 8007d00: f883 2021 strb.w r2, [r3, #33] @ 0x21 + RadioStandby( ); + 8007d04: f000 fac3 bl 800828e + RadioSetModem( MODEM_LORA ); + 8007d08: 2001 movs r0, #1 + 8007d0a: f7ff fc51 bl 80075b0 + SUBGRF_SetModulationParams( &SubgRf.ModulationParams ); + 8007d0e: 481c ldr r0, [pc, #112] @ (8007d80 ) + 8007d10: f002 f8ee bl 8009ef0 + SUBGRF_SetPacketParams( &SubgRf.PacketParams ); + 8007d14: 481b ldr r0, [pc, #108] @ (8007d84 ) + 8007d16: f002 f9b9 bl 800a08c + break; + 8007d1a: e012 b.n 8007d42 + RadioSetModem(MODEM_SIGFOX_TX); + 8007d1c: 2004 movs r0, #4 + 8007d1e: f7ff fc47 bl 80075b0 + SubgRf.ModulationParams.PacketType = PACKET_TYPE_BPSK; + 8007d22: 4b16 ldr r3, [pc, #88] @ (8007d7c ) + 8007d24: 2202 movs r2, #2 + 8007d26: f883 2038 strb.w r2, [r3, #56] @ 0x38 + SubgRf.ModulationParams.Params.Bpsk.BitRate = datarate; + 8007d2a: 4a14 ldr r2, [pc, #80] @ (8007d7c ) + 8007d2c: 6a3b ldr r3, [r7, #32] + 8007d2e: 6493 str r3, [r2, #72] @ 0x48 + SubgRf.ModulationParams.Params.Bpsk.ModulationShaping = MOD_SHAPING_DBPSK; + 8007d30: 4b12 ldr r3, [pc, #72] @ (8007d7c ) + 8007d32: 2216 movs r2, #22 + 8007d34: f883 204c strb.w r2, [r3, #76] @ 0x4c + SUBGRF_SetModulationParams( &SubgRf.ModulationParams ); + 8007d38: 4811 ldr r0, [pc, #68] @ (8007d80 ) + 8007d3a: f002 f8d9 bl 8009ef0 + break; + 8007d3e: e000 b.n 8007d42 + break; + 8007d40: bf00 nop + } + + SubgRf.AntSwitchPaSelect = SUBGRF_SetRfTxPower( power ); + 8007d42: f997 300e ldrsb.w r3, [r7, #14] + 8007d46: 4618 mov r0, r3 + 8007d48: f002 fc1c bl 800a584 + 8007d4c: 4603 mov r3, r0 + 8007d4e: 461a mov r2, r3 + 8007d50: 4b0a ldr r3, [pc, #40] @ (8007d7c ) + 8007d52: f883 2056 strb.w r2, [r3, #86] @ 0x56 + /* WORKAROUND - Trimming the output voltage power_ldo to 3.3V */ + SUBGRF_WriteRegister(REG_DRV_CTRL, 0x7 << 1); + 8007d56: 210e movs r1, #14 + 8007d58: f640 101f movw r0, #2335 @ 0x91f + 8007d5c: f002 fadc bl 800a318 + RFW_SetAntSwitch( SubgRf.AntSwitchPaSelect ); + 8007d60: 4b06 ldr r3, [pc, #24] @ (8007d7c ) + 8007d62: f893 3056 ldrb.w r3, [r3, #86] @ 0x56 + 8007d66: 4618 mov r0, r3 + 8007d68: f003 f866 bl 800ae38 + SubgRf.TxTimeout = timeout; + 8007d6c: 4a03 ldr r2, [pc, #12] @ (8007d7c ) + 8007d6e: 6c3b ldr r3, [r7, #64] @ 0x40 + 8007d70: 6053 str r3, [r2, #4] +} + 8007d72: bf00 nop + 8007d74: 3718 adds r7, #24 + 8007d76: 46bd mov sp, r7 + 8007d78: bd80 pop {r7, pc} + 8007d7a: bf00 nop + 8007d7c: 20000290 .word 0x20000290 + 8007d80: 200002c8 .word 0x200002c8 + 8007d84: 2000029e .word 0x2000029e + 8007d88: 0800d530 .word 0x0800d530 + 8007d8c: 0800da6c .word 0x0800da6c + 8007d90: 20000008 .word 0x20000008 + +08007d94 : + +static bool RadioCheckRfFrequency( uint32_t frequency ) +{ + 8007d94: b480 push {r7} + 8007d96: b083 sub sp, #12 + 8007d98: af00 add r7, sp, #0 + 8007d9a: 6078 str r0, [r7, #4] + return true; + 8007d9c: 2301 movs r3, #1 +} + 8007d9e: 4618 mov r0, r3 + 8007da0: 370c adds r7, #12 + 8007da2: 46bd mov sp, r7 + 8007da4: bc80 pop {r7} + 8007da6: 4770 bx lr + +08007da8 : + +static uint32_t RadioGetLoRaBandwidthInHz( RadioLoRaBandwidths_t bw ) +{ + 8007da8: b480 push {r7} + 8007daa: b085 sub sp, #20 + 8007dac: af00 add r7, sp, #0 + 8007dae: 4603 mov r3, r0 + 8007db0: 71fb strb r3, [r7, #7] + uint32_t bandwidthInHz = 0; + 8007db2: 2300 movs r3, #0 + 8007db4: 60fb str r3, [r7, #12] + + switch( bw ) + 8007db6: 79fb ldrb r3, [r7, #7] + 8007db8: 2b0a cmp r3, #10 + 8007dba: d83e bhi.n 8007e3a + 8007dbc: a201 add r2, pc, #4 @ (adr r2, 8007dc4 ) + 8007dbe: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 8007dc2: bf00 nop + 8007dc4: 08007df1 .word 0x08007df1 + 8007dc8: 08007e01 .word 0x08007e01 + 8007dcc: 08007e11 .word 0x08007e11 + 8007dd0: 08007e21 .word 0x08007e21 + 8007dd4: 08007e29 .word 0x08007e29 + 8007dd8: 08007e2f .word 0x08007e2f + 8007ddc: 08007e35 .word 0x08007e35 + 8007de0: 08007e3b .word 0x08007e3b + 8007de4: 08007df9 .word 0x08007df9 + 8007de8: 08007e09 .word 0x08007e09 + 8007dec: 08007e19 .word 0x08007e19 + { + case LORA_BW_007: + bandwidthInHz = 7812UL; + 8007df0: f641 6384 movw r3, #7812 @ 0x1e84 + 8007df4: 60fb str r3, [r7, #12] + break; + 8007df6: e020 b.n 8007e3a + case LORA_BW_010: + bandwidthInHz = 10417UL; + 8007df8: f642 03b1 movw r3, #10417 @ 0x28b1 + 8007dfc: 60fb str r3, [r7, #12] + break; + 8007dfe: e01c b.n 8007e3a + case LORA_BW_015: + bandwidthInHz = 15625UL; + 8007e00: f643 5309 movw r3, #15625 @ 0x3d09 + 8007e04: 60fb str r3, [r7, #12] + break; + 8007e06: e018 b.n 8007e3a + case LORA_BW_020: + bandwidthInHz = 20833UL; + 8007e08: f245 1361 movw r3, #20833 @ 0x5161 + 8007e0c: 60fb str r3, [r7, #12] + break; + 8007e0e: e014 b.n 8007e3a + case LORA_BW_031: + bandwidthInHz = 31250UL; + 8007e10: f647 2312 movw r3, #31250 @ 0x7a12 + 8007e14: 60fb str r3, [r7, #12] + break; + 8007e16: e010 b.n 8007e3a + case LORA_BW_041: + bandwidthInHz = 41667UL; + 8007e18: f24a 23c3 movw r3, #41667 @ 0xa2c3 + 8007e1c: 60fb str r3, [r7, #12] + break; + 8007e1e: e00c b.n 8007e3a + case LORA_BW_062: + bandwidthInHz = 62500UL; + 8007e20: f24f 4324 movw r3, #62500 @ 0xf424 + 8007e24: 60fb str r3, [r7, #12] + break; + 8007e26: e008 b.n 8007e3a + case LORA_BW_125: + bandwidthInHz = 125000UL; + 8007e28: 4b07 ldr r3, [pc, #28] @ (8007e48 ) + 8007e2a: 60fb str r3, [r7, #12] + break; + 8007e2c: e005 b.n 8007e3a + case LORA_BW_250: + bandwidthInHz = 250000UL; + 8007e2e: 4b07 ldr r3, [pc, #28] @ (8007e4c ) + 8007e30: 60fb str r3, [r7, #12] + break; + 8007e32: e002 b.n 8007e3a + case LORA_BW_500: + bandwidthInHz = 500000UL; + 8007e34: 4b06 ldr r3, [pc, #24] @ (8007e50 ) + 8007e36: 60fb str r3, [r7, #12] + break; + 8007e38: bf00 nop + } + + return bandwidthInHz; + 8007e3a: 68fb ldr r3, [r7, #12] +} + 8007e3c: 4618 mov r0, r3 + 8007e3e: 3714 adds r7, #20 + 8007e40: 46bd mov sp, r7 + 8007e42: bc80 pop {r7} + 8007e44: 4770 bx lr + 8007e46: bf00 nop + 8007e48: 0001e848 .word 0x0001e848 + 8007e4c: 0003d090 .word 0x0003d090 + 8007e50: 0007a120 .word 0x0007a120 + +08007e54 : + +static uint32_t RadioGetGfskTimeOnAirNumerator( uint32_t datarate, uint8_t coderate, + uint16_t preambleLen, bool fixLen, uint8_t payloadLen, + bool crcOn ) +{ + 8007e54: b480 push {r7} + 8007e56: b083 sub sp, #12 + 8007e58: af00 add r7, sp, #0 + 8007e5a: 6078 str r0, [r7, #4] + 8007e5c: 4608 mov r0, r1 + 8007e5e: 4611 mov r1, r2 + 8007e60: 461a mov r2, r3 + 8007e62: 4603 mov r3, r0 + 8007e64: 70fb strb r3, [r7, #3] + 8007e66: 460b mov r3, r1 + 8007e68: 803b strh r3, [r7, #0] + 8007e6a: 4613 mov r3, r2 + 8007e6c: 70bb strb r3, [r7, #2] + return ( preambleLen << 3 ) + + 8007e6e: 883b ldrh r3, [r7, #0] + 8007e70: 00db lsls r3, r3, #3 + ( ( fixLen == false ) ? 8 : 0 ) + 24 + + 8007e72: 78ba ldrb r2, [r7, #2] + 8007e74: f082 0201 eor.w r2, r2, #1 + 8007e78: b2d2 uxtb r2, r2 + 8007e7a: 2a00 cmp r2, #0 + 8007e7c: d001 beq.n 8007e82 + 8007e7e: 2208 movs r2, #8 + 8007e80: e000 b.n 8007e84 + 8007e82: 2200 movs r2, #0 + return ( preambleLen << 3 ) + + 8007e84: 4413 add r3, r2 + ( ( fixLen == false ) ? 8 : 0 ) + 24 + + 8007e86: f103 0218 add.w r2, r3, #24 + ( ( payloadLen + ( ( crcOn == true ) ? 2 : 0 ) ) << 3 ); + 8007e8a: 7c3b ldrb r3, [r7, #16] + 8007e8c: 7d39 ldrb r1, [r7, #20] + 8007e8e: 2900 cmp r1, #0 + 8007e90: d001 beq.n 8007e96 + 8007e92: 2102 movs r1, #2 + 8007e94: e000 b.n 8007e98 + 8007e96: 2100 movs r1, #0 + 8007e98: 440b add r3, r1 + 8007e9a: 00db lsls r3, r3, #3 + ( ( fixLen == false ) ? 8 : 0 ) + 24 + + 8007e9c: 4413 add r3, r2 +} + 8007e9e: 4618 mov r0, r3 + 8007ea0: 370c adds r7, #12 + 8007ea2: 46bd mov sp, r7 + 8007ea4: bc80 pop {r7} + 8007ea6: 4770 bx lr + +08007ea8 : + +static uint32_t RadioGetLoRaTimeOnAirNumerator( uint32_t bandwidth, + uint32_t datarate, uint8_t coderate, + uint16_t preambleLen, bool fixLen, uint8_t payloadLen, + bool crcOn ) +{ + 8007ea8: b480 push {r7} + 8007eaa: b08b sub sp, #44 @ 0x2c + 8007eac: af00 add r7, sp, #0 + 8007eae: 60f8 str r0, [r7, #12] + 8007eb0: 60b9 str r1, [r7, #8] + 8007eb2: 4611 mov r1, r2 + 8007eb4: 461a mov r2, r3 + 8007eb6: 460b mov r3, r1 + 8007eb8: 71fb strb r3, [r7, #7] + 8007eba: 4613 mov r3, r2 + 8007ebc: 80bb strh r3, [r7, #4] + int32_t crDenom = coderate + 4; + 8007ebe: 79fb ldrb r3, [r7, #7] + 8007ec0: 3304 adds r3, #4 + 8007ec2: 617b str r3, [r7, #20] + bool lowDatareOptimize = false; + 8007ec4: 2300 movs r3, #0 + 8007ec6: f887 3027 strb.w r3, [r7, #39] @ 0x27 + + // Ensure that the preamble length is at least 12 symbols when using SF5 or SF6 + if( ( datarate == 5 ) || ( datarate == 6 ) ) + 8007eca: 68bb ldr r3, [r7, #8] + 8007ecc: 2b05 cmp r3, #5 + 8007ece: d002 beq.n 8007ed6 + 8007ed0: 68bb ldr r3, [r7, #8] + 8007ed2: 2b06 cmp r3, #6 + 8007ed4: d104 bne.n 8007ee0 + { + if( preambleLen < 12 ) + 8007ed6: 88bb ldrh r3, [r7, #4] + 8007ed8: 2b0b cmp r3, #11 + 8007eda: d801 bhi.n 8007ee0 + { + preambleLen = 12; + 8007edc: 230c movs r3, #12 + 8007ede: 80bb strh r3, [r7, #4] + } + } + + if( ( ( bandwidth == 0 ) && ( ( datarate == 11 ) || ( datarate == 12 ) ) ) || + 8007ee0: 68fb ldr r3, [r7, #12] + 8007ee2: 2b00 cmp r3, #0 + 8007ee4: d105 bne.n 8007ef2 + 8007ee6: 68bb ldr r3, [r7, #8] + 8007ee8: 2b0b cmp r3, #11 + 8007eea: d008 beq.n 8007efe + 8007eec: 68bb ldr r3, [r7, #8] + 8007eee: 2b0c cmp r3, #12 + 8007ef0: d005 beq.n 8007efe + 8007ef2: 68fb ldr r3, [r7, #12] + 8007ef4: 2b01 cmp r3, #1 + 8007ef6: d105 bne.n 8007f04 + ( ( bandwidth == 1 ) && ( datarate == 12 ) ) ) + 8007ef8: 68bb ldr r3, [r7, #8] + 8007efa: 2b0c cmp r3, #12 + 8007efc: d102 bne.n 8007f04 + { + lowDatareOptimize = true; + 8007efe: 2301 movs r3, #1 + 8007f00: f887 3027 strb.w r3, [r7, #39] @ 0x27 + } + + int32_t ceilDenominator; + int32_t ceilNumerator = ( payloadLen << 3 ) + + 8007f04: f897 3034 ldrb.w r3, [r7, #52] @ 0x34 + 8007f08: 00db lsls r3, r3, #3 + ( crcOn ? 16 : 0 ) - + 8007f0a: f897 2038 ldrb.w r2, [r7, #56] @ 0x38 + 8007f0e: 2a00 cmp r2, #0 + 8007f10: d001 beq.n 8007f16 + 8007f12: 2210 movs r2, #16 + 8007f14: e000 b.n 8007f18 + 8007f16: 2200 movs r2, #0 + int32_t ceilNumerator = ( payloadLen << 3 ) + + 8007f18: 4413 add r3, r2 + 8007f1a: 461a mov r2, r3 + ( 4 * datarate ) + + 8007f1c: 68bb ldr r3, [r7, #8] + 8007f1e: 009b lsls r3, r3, #2 + ( crcOn ? 16 : 0 ) - + 8007f20: 1ad3 subs r3, r2, r3 + ( fixLen ? 0 : 20 ); + 8007f22: f897 2030 ldrb.w r2, [r7, #48] @ 0x30 + 8007f26: 2a00 cmp r2, #0 + 8007f28: d001 beq.n 8007f2e + 8007f2a: 2200 movs r2, #0 + 8007f2c: e000 b.n 8007f30 + 8007f2e: 2214 movs r2, #20 + ( 4 * datarate ) + + 8007f30: 4413 add r3, r2 + int32_t ceilNumerator = ( payloadLen << 3 ) + + 8007f32: 61fb str r3, [r7, #28] + + if( datarate <= 6 ) + 8007f34: 68bb ldr r3, [r7, #8] + 8007f36: 2b06 cmp r3, #6 + 8007f38: d803 bhi.n 8007f42 + { + ceilDenominator = 4 * datarate; + 8007f3a: 68bb ldr r3, [r7, #8] + 8007f3c: 009b lsls r3, r3, #2 + 8007f3e: 623b str r3, [r7, #32] + 8007f40: e00e b.n 8007f60 + } + else + { + ceilNumerator += 8; + 8007f42: 69fb ldr r3, [r7, #28] + 8007f44: 3308 adds r3, #8 + 8007f46: 61fb str r3, [r7, #28] + + if( lowDatareOptimize == true ) + 8007f48: f897 3027 ldrb.w r3, [r7, #39] @ 0x27 + 8007f4c: 2b00 cmp r3, #0 + 8007f4e: d004 beq.n 8007f5a + { + ceilDenominator = 4 * ( datarate - 2 ); + 8007f50: 68bb ldr r3, [r7, #8] + 8007f52: 3b02 subs r3, #2 + 8007f54: 009b lsls r3, r3, #2 + 8007f56: 623b str r3, [r7, #32] + 8007f58: e002 b.n 8007f60 + } + else + { + ceilDenominator = 4 * datarate; + 8007f5a: 68bb ldr r3, [r7, #8] + 8007f5c: 009b lsls r3, r3, #2 + 8007f5e: 623b str r3, [r7, #32] + } + } + + if( ceilNumerator < 0 ) + 8007f60: 69fb ldr r3, [r7, #28] + 8007f62: 2b00 cmp r3, #0 + 8007f64: da01 bge.n 8007f6a + { + ceilNumerator = 0; + 8007f66: 2300 movs r3, #0 + 8007f68: 61fb str r3, [r7, #28] + } + + // Perform integral ceil() + int32_t intermediate = + ( ( ceilNumerator + ceilDenominator - 1 ) / ceilDenominator ) * crDenom + preambleLen + 12; + 8007f6a: 69fa ldr r2, [r7, #28] + 8007f6c: 6a3b ldr r3, [r7, #32] + 8007f6e: 4413 add r3, r2 + 8007f70: 1e5a subs r2, r3, #1 + 8007f72: 6a3b ldr r3, [r7, #32] + 8007f74: fb92 f3f3 sdiv r3, r2, r3 + 8007f78: 697a ldr r2, [r7, #20] + 8007f7a: fb03 f202 mul.w r2, r3, r2 + 8007f7e: 88bb ldrh r3, [r7, #4] + 8007f80: 4413 add r3, r2 + int32_t intermediate = + 8007f82: 330c adds r3, #12 + 8007f84: 61bb str r3, [r7, #24] + + if( datarate <= 6 ) + 8007f86: 68bb ldr r3, [r7, #8] + 8007f88: 2b06 cmp r3, #6 + 8007f8a: d802 bhi.n 8007f92 + { + intermediate += 2; + 8007f8c: 69bb ldr r3, [r7, #24] + 8007f8e: 3302 adds r3, #2 + 8007f90: 61bb str r3, [r7, #24] + } + + return ( uint32_t )( ( 4 * intermediate + 1 ) * ( 1 << ( datarate - 2 ) ) ); + 8007f92: 69bb ldr r3, [r7, #24] + 8007f94: 009b lsls r3, r3, #2 + 8007f96: 1c5a adds r2, r3, #1 + 8007f98: 68bb ldr r3, [r7, #8] + 8007f9a: 3b02 subs r3, #2 + 8007f9c: fa02 f303 lsl.w r3, r2, r3 +} + 8007fa0: 4618 mov r0, r3 + 8007fa2: 372c adds r7, #44 @ 0x2c + 8007fa4: 46bd mov sp, r7 + 8007fa6: bc80 pop {r7} + 8007fa8: 4770 bx lr + ... + +08007fac : + +static uint32_t RadioTimeOnAir( RadioModems_t modem, uint32_t bandwidth, + uint32_t datarate, uint8_t coderate, + uint16_t preambleLen, bool fixLen, uint8_t payloadLen, + bool crcOn ) +{ + 8007fac: b580 push {r7, lr} + 8007fae: b08a sub sp, #40 @ 0x28 + 8007fb0: af04 add r7, sp, #16 + 8007fb2: 60b9 str r1, [r7, #8] + 8007fb4: 607a str r2, [r7, #4] + 8007fb6: 461a mov r2, r3 + 8007fb8: 4603 mov r3, r0 + 8007fba: 73fb strb r3, [r7, #15] + 8007fbc: 4613 mov r3, r2 + 8007fbe: 73bb strb r3, [r7, #14] + uint32_t numerator = 0; + 8007fc0: 2300 movs r3, #0 + 8007fc2: 617b str r3, [r7, #20] + uint32_t denominator = 1; + 8007fc4: 2301 movs r3, #1 + 8007fc6: 613b str r3, [r7, #16] + + switch( modem ) + 8007fc8: 7bfb ldrb r3, [r7, #15] + 8007fca: 2b00 cmp r3, #0 + 8007fcc: d002 beq.n 8007fd4 + 8007fce: 2b01 cmp r3, #1 + 8007fd0: d017 beq.n 8008002 + fixLen, payloadLen, crcOn ); + denominator = RadioGetLoRaBandwidthInHz( Bandwidths[bandwidth] ); + } + break; + default: + break; + 8007fd2: e035 b.n 8008040 + numerator = 1000U * RadioGetGfskTimeOnAirNumerator( datarate, coderate, + 8007fd4: f897 0024 ldrb.w r0, [r7, #36] @ 0x24 + 8007fd8: 8c3a ldrh r2, [r7, #32] + 8007fda: 7bb9 ldrb r1, [r7, #14] + 8007fdc: f897 302c ldrb.w r3, [r7, #44] @ 0x2c + 8007fe0: 9301 str r3, [sp, #4] + 8007fe2: f897 3028 ldrb.w r3, [r7, #40] @ 0x28 + 8007fe6: 9300 str r3, [sp, #0] + 8007fe8: 4603 mov r3, r0 + 8007fea: 6878 ldr r0, [r7, #4] + 8007fec: f7ff ff32 bl 8007e54 + 8007ff0: 4603 mov r3, r0 + 8007ff2: f44f 727a mov.w r2, #1000 @ 0x3e8 + 8007ff6: fb02 f303 mul.w r3, r2, r3 + 8007ffa: 617b str r3, [r7, #20] + denominator = datarate; + 8007ffc: 687b ldr r3, [r7, #4] + 8007ffe: 613b str r3, [r7, #16] + break; + 8008000: e01e b.n 8008040 + numerator = 1000U * RadioGetLoRaTimeOnAirNumerator( bandwidth, datarate, + 8008002: 8c39 ldrh r1, [r7, #32] + 8008004: 7bba ldrb r2, [r7, #14] + 8008006: f897 302c ldrb.w r3, [r7, #44] @ 0x2c + 800800a: 9302 str r3, [sp, #8] + 800800c: f897 3028 ldrb.w r3, [r7, #40] @ 0x28 + 8008010: 9301 str r3, [sp, #4] + 8008012: f897 3024 ldrb.w r3, [r7, #36] @ 0x24 + 8008016: 9300 str r3, [sp, #0] + 8008018: 460b mov r3, r1 + 800801a: 6879 ldr r1, [r7, #4] + 800801c: 68b8 ldr r0, [r7, #8] + 800801e: f7ff ff43 bl 8007ea8 + 8008022: 4603 mov r3, r0 + 8008024: f44f 727a mov.w r2, #1000 @ 0x3e8 + 8008028: fb02 f303 mul.w r3, r2, r3 + 800802c: 617b str r3, [r7, #20] + denominator = RadioGetLoRaBandwidthInHz( Bandwidths[bandwidth] ); + 800802e: 4a0a ldr r2, [pc, #40] @ (8008058 ) + 8008030: 68bb ldr r3, [r7, #8] + 8008032: 4413 add r3, r2 + 8008034: 781b ldrb r3, [r3, #0] + 8008036: 4618 mov r0, r3 + 8008038: f7ff feb6 bl 8007da8 + 800803c: 6138 str r0, [r7, #16] + break; + 800803e: bf00 nop + } + // Perform integral ceil() + return DIVC( numerator, denominator ); + 8008040: 697a ldr r2, [r7, #20] + 8008042: 693b ldr r3, [r7, #16] + 8008044: 4413 add r3, r2 + 8008046: 1e5a subs r2, r3, #1 + 8008048: 693b ldr r3, [r7, #16] + 800804a: fbb2 f3f3 udiv r3, r2, r3 +} + 800804e: 4618 mov r0, r3 + 8008050: 3718 adds r7, #24 + 8008052: 46bd mov sp, r7 + 8008054: bd80 pop {r7, pc} + 8008056: bf00 nop + 8008058: 0800da6c .word 0x0800da6c + +0800805c : + +static radio_status_t RadioSend( uint8_t *buffer, uint8_t size ) +{ + 800805c: b580 push {r7, lr} + 800805e: b084 sub sp, #16 + 8008060: af00 add r7, sp, #0 + 8008062: 6078 str r0, [r7, #4] + 8008064: 460b mov r3, r1 + 8008066: 70fb strb r3, [r7, #3] + SUBGRF_SetDioIrqParams( IRQ_TX_DONE | IRQ_RX_TX_TIMEOUT | IRQ_TX_DBG, + 8008068: 2300 movs r3, #0 + 800806a: 2200 movs r2, #0 + 800806c: f240 2101 movw r1, #513 @ 0x201 + 8008070: f240 2001 movw r0, #513 @ 0x201 + 8008074: f001 fda6 bl 8009bc4 + IRQ_TX_DONE | IRQ_RX_TX_TIMEOUT | IRQ_TX_DBG, + IRQ_RADIO_NONE, + IRQ_RADIO_NONE ); + + /* Set DBG pin */ + DBG_GPIO_RADIO_TX( SET ); + 8008078: f44f 5100 mov.w r1, #8192 @ 0x2000 + 800807c: 4874 ldr r0, [pc, #464] @ (8008250 ) + 800807e: f7ff fa09 bl 8007494 + + /* Set RF switch */ + SUBGRF_SetSwitch( SubgRf.AntSwitchPaSelect, RFSWITCH_TX ); + 8008082: 4b74 ldr r3, [pc, #464] @ (8008254 ) + 8008084: f893 3056 ldrb.w r3, [r3, #86] @ 0x56 + 8008088: 2101 movs r1, #1 + 800808a: 4618 mov r0, r3 + 800808c: f002 fa52 bl 800a534 + /* WORKAROUND - Modulation Quality with 500 kHz LoRaTM Bandwidth*/ + /* RegTxModulation = @address 0x0889 */ + if( ( SubgRf.Modem == MODEM_LORA ) && ( SubgRf.ModulationParams.Params.LoRa.Bandwidth == LORA_BW_500 ) ) + 8008090: 4b70 ldr r3, [pc, #448] @ (8008254 ) + 8008092: 781b ldrb r3, [r3, #0] + 8008094: 2b01 cmp r3, #1 + 8008096: d112 bne.n 80080be + 8008098: 4b6e ldr r3, [pc, #440] @ (8008254 ) + 800809a: f893 3051 ldrb.w r3, [r3, #81] @ 0x51 + 800809e: 2b06 cmp r3, #6 + 80080a0: d10d bne.n 80080be + { + SUBGRF_WriteRegister( SUBGHZ_SDCFG0R, SUBGRF_ReadRegister( SUBGHZ_SDCFG0R ) & ~( 1 << 2 ) ); + 80080a2: f640 0089 movw r0, #2185 @ 0x889 + 80080a6: f002 f959 bl 800a35c + 80080aa: 4603 mov r3, r0 + 80080ac: f023 0304 bic.w r3, r3, #4 + 80080b0: b2db uxtb r3, r3 + 80080b2: 4619 mov r1, r3 + 80080b4: f640 0089 movw r0, #2185 @ 0x889 + 80080b8: f002 f92e bl 800a318 + 80080bc: e00c b.n 80080d8 + } + else + { + SUBGRF_WriteRegister( SUBGHZ_SDCFG0R, SUBGRF_ReadRegister( SUBGHZ_SDCFG0R ) | ( 1 << 2 ) ); + 80080be: f640 0089 movw r0, #2185 @ 0x889 + 80080c2: f002 f94b bl 800a35c + 80080c6: 4603 mov r3, r0 + 80080c8: f043 0304 orr.w r3, r3, #4 + 80080cc: b2db uxtb r3, r3 + 80080ce: 4619 mov r1, r3 + 80080d0: f640 0089 movw r0, #2185 @ 0x889 + 80080d4: f002 f920 bl 800a318 + } + else +#endif /* RADIO_LR_FHSS_IS_ON == 1 */ + { + /* WORKAROUND END */ + switch( SubgRf.Modem ) + 80080d8: 4b5e ldr r3, [pc, #376] @ (8008254 ) + 80080da: 781b ldrb r3, [r3, #0] + 80080dc: 2b04 cmp r3, #4 + 80080de: f200 80a7 bhi.w 8008230 + 80080e2: a201 add r2, pc, #4 @ (adr r2, 80080e8 ) + 80080e4: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 80080e8: 08008117 .word 0x08008117 + 80080ec: 080080fd .word 0x080080fd + 80080f0: 08008117 .word 0x08008117 + 80080f4: 08008179 .word 0x08008179 + 80080f8: 08008199 .word 0x08008199 + { + case MODEM_LORA: + { + SubgRf.PacketParams.Params.LoRa.PayloadLength = size; + 80080fc: 4a55 ldr r2, [pc, #340] @ (8008254 ) + 80080fe: 78fb ldrb r3, [r7, #3] + 8008100: 77d3 strb r3, [r2, #31] + SUBGRF_SetPacketParams( &SubgRf.PacketParams ); + 8008102: 4855 ldr r0, [pc, #340] @ (8008258 ) + 8008104: f001 ffc2 bl 800a08c + SUBGRF_SendPayload( buffer, size, 0 ); + 8008108: 78fb ldrb r3, [r7, #3] + 800810a: 2200 movs r2, #0 + 800810c: 4619 mov r1, r3 + 800810e: 6878 ldr r0, [r7, #4] + 8008110: f001 fa6e bl 80095f0 + break; + 8008114: e08d b.n 8008232 + } + case MODEM_MSK: + case MODEM_FSK: + { + if ( 1UL == RFW_Is_Init( ) ) + 8008116: f002 fe7b bl 800ae10 + 800811a: 4603 mov r3, r0 + 800811c: 2b01 cmp r3, #1 + 800811e: d11e bne.n 800815e + { + uint8_t outsize; + if ( 0UL == RFW_TransmitInit( buffer,size, &outsize ) ) + 8008120: f107 020d add.w r2, r7, #13 + 8008124: 78fb ldrb r3, [r7, #3] + 8008126: 4619 mov r1, r3 + 8008128: 6878 ldr r0, [r7, #4] + 800812a: f002 fe95 bl 800ae58 + 800812e: 4603 mov r3, r0 + 8008130: 2b00 cmp r3, #0 + 8008132: d10c bne.n 800814e + { + SubgRf.PacketParams.Params.Gfsk.PayloadLength = outsize; + 8008134: 7b7a ldrb r2, [r7, #13] + 8008136: 4b47 ldr r3, [pc, #284] @ (8008254 ) + 8008138: 759a strb r2, [r3, #22] + SUBGRF_SetPacketParams( &SubgRf.PacketParams ); + 800813a: 4847 ldr r0, [pc, #284] @ (8008258 ) + 800813c: f001 ffa6 bl 800a08c + SUBGRF_SendPayload( buffer, outsize, 0 ); + 8008140: 7b7b ldrb r3, [r7, #13] + 8008142: 2200 movs r2, #0 + 8008144: 4619 mov r1, r3 + 8008146: 6878 ldr r0, [r7, #4] + 8008148: f001 fa52 bl 80095f0 + { + SubgRf.PacketParams.Params.Gfsk.PayloadLength = size; + SUBGRF_SetPacketParams( &SubgRf.PacketParams ); + SUBGRF_SendPayload( buffer, size, 0 ); + } + break; + 800814c: e071 b.n 8008232 + MW_LOG( TS_ON, VLEVEL_M, "RadioSend Oversize\r\n" ); + 800814e: 4b43 ldr r3, [pc, #268] @ (800825c ) + 8008150: 2201 movs r2, #1 + 8008152: 2100 movs r1, #0 + 8008154: 2002 movs r0, #2 + 8008156: f004 ff15 bl 800cf84 + return RADIO_STATUS_ERROR; + 800815a: 2303 movs r3, #3 + 800815c: e073 b.n 8008246 + SubgRf.PacketParams.Params.Gfsk.PayloadLength = size; + 800815e: 4a3d ldr r2, [pc, #244] @ (8008254 ) + 8008160: 78fb ldrb r3, [r7, #3] + 8008162: 7593 strb r3, [r2, #22] + SUBGRF_SetPacketParams( &SubgRf.PacketParams ); + 8008164: 483c ldr r0, [pc, #240] @ (8008258 ) + 8008166: f001 ff91 bl 800a08c + SUBGRF_SendPayload( buffer, size, 0 ); + 800816a: 78fb ldrb r3, [r7, #3] + 800816c: 2200 movs r2, #0 + 800816e: 4619 mov r1, r3 + 8008170: 6878 ldr r0, [r7, #4] + 8008172: f001 fa3d bl 80095f0 + break; + 8008176: e05c b.n 8008232 + } + case MODEM_BPSK: + { + SubgRf.PacketParams.PacketType = PACKET_TYPE_BPSK; + 8008178: 4b36 ldr r3, [pc, #216] @ (8008254 ) + 800817a: 2202 movs r2, #2 + 800817c: 739a strb r2, [r3, #14] + SubgRf.PacketParams.Params.Bpsk.PayloadLength = size; + 800817e: 4a35 ldr r2, [pc, #212] @ (8008254 ) + 8008180: 78fb ldrb r3, [r7, #3] + 8008182: 7693 strb r3, [r2, #26] + SUBGRF_SetPacketParams( &SubgRf.PacketParams ); + 8008184: 4834 ldr r0, [pc, #208] @ (8008258 ) + 8008186: f001 ff81 bl 800a08c + SUBGRF_SendPayload( buffer, size, 0 ); + 800818a: 78fb ldrb r3, [r7, #3] + 800818c: 2200 movs r2, #0 + 800818e: 4619 mov r1, r3 + 8008190: 6878 ldr r0, [r7, #4] + 8008192: f001 fa2d bl 80095f0 + break; + 8008196: e04c b.n 8008232 + case MODEM_SIGFOX_TX: + { + /* from bpsk to dbpsk */ + /* first 1 bit duplicated */ + /* RadioBuffer is 1 bytes more */ + payload_integration( RadioBuffer, buffer, size ); + 8008198: 78fb ldrb r3, [r7, #3] + 800819a: 461a mov r2, r3 + 800819c: 6879 ldr r1, [r7, #4] + 800819e: 4830 ldr r0, [pc, #192] @ (8008260 ) + 80081a0: f000 fcfa bl 8008b98 + + SubgRf.PacketParams.PacketType = PACKET_TYPE_BPSK; + 80081a4: 4b2b ldr r3, [pc, #172] @ (8008254 ) + 80081a6: 2202 movs r2, #2 + 80081a8: 739a strb r2, [r3, #14] + SubgRf.PacketParams.Params.Bpsk.PayloadLength = size + 1; + 80081aa: 78fb ldrb r3, [r7, #3] + 80081ac: 3301 adds r3, #1 + 80081ae: b2da uxtb r2, r3 + 80081b0: 4b28 ldr r3, [pc, #160] @ (8008254 ) + 80081b2: 769a strb r2, [r3, #26] + SUBGRF_SetPacketParams( &SubgRf.PacketParams ); + 80081b4: 4828 ldr r0, [pc, #160] @ (8008258 ) + 80081b6: f001 ff69 bl 800a08c + + RadioWrite( SUBGHZ_RAM_RAMPUPL, 0 ); // clean start-up LSB + 80081ba: 2100 movs r1, #0 + 80081bc: 20f1 movs r0, #241 @ 0xf1 + 80081be: f000 f973 bl 80084a8 + RadioWrite( SUBGHZ_RAM_RAMPUPH, 0 ); // clean start-up MSB + 80081c2: 2100 movs r1, #0 + 80081c4: 20f0 movs r0, #240 @ 0xf0 + 80081c6: f000 f96f bl 80084a8 + if( SubgRf.ModulationParams.Params.Bpsk.BitRate == 100 ) + 80081ca: 4b22 ldr r3, [pc, #136] @ (8008254 ) + 80081cc: 6c9b ldr r3, [r3, #72] @ 0x48 + 80081ce: 2b64 cmp r3, #100 @ 0x64 + 80081d0: d108 bne.n 80081e4 + { + RadioWrite( SUBGHZ_RAM_RAMPDNL, 0x70 ); // clean end of frame LSB + 80081d2: 2170 movs r1, #112 @ 0x70 + 80081d4: 20f3 movs r0, #243 @ 0xf3 + 80081d6: f000 f967 bl 80084a8 + RadioWrite( SUBGHZ_RAM_RAMPDNH, 0x1D ); // clean end of frame MSB + 80081da: 211d movs r1, #29 + 80081dc: 20f2 movs r0, #242 @ 0xf2 + 80081de: f000 f963 bl 80084a8 + 80081e2: e007 b.n 80081f4 + } + else // 600 bps + { + RadioWrite( SUBGHZ_RAM_RAMPDNL, 0xE1 ); // clean end of frame LSB + 80081e4: 21e1 movs r1, #225 @ 0xe1 + 80081e6: 20f3 movs r0, #243 @ 0xf3 + 80081e8: f000 f95e bl 80084a8 + RadioWrite( SUBGHZ_RAM_RAMPDNH, 0x04 ); // clean end of frame MSB + 80081ec: 2104 movs r1, #4 + 80081ee: 20f2 movs r0, #242 @ 0xf2 + 80081f0: f000 f95a bl 80084a8 + } + + uint16_t bitNum = ( size * 8 ) + 2; + 80081f4: 78fb ldrb r3, [r7, #3] + 80081f6: b29b uxth r3, r3 + 80081f8: 00db lsls r3, r3, #3 + 80081fa: b29b uxth r3, r3 + 80081fc: 3302 adds r3, #2 + 80081fe: 81fb strh r3, [r7, #14] + RadioWrite( SUBGHZ_RAM_FRAMELIMH, ( bitNum >> 8 ) & 0x00FF ); // limit frame + 8008200: 89fb ldrh r3, [r7, #14] + 8008202: 0a1b lsrs r3, r3, #8 + 8008204: b29b uxth r3, r3 + 8008206: b2db uxtb r3, r3 + 8008208: 4619 mov r1, r3 + 800820a: 20f4 movs r0, #244 @ 0xf4 + 800820c: f000 f94c bl 80084a8 + RadioWrite( SUBGHZ_RAM_FRAMELIML, bitNum & 0x00FF ); // limit frame + 8008210: 89fb ldrh r3, [r7, #14] + 8008212: b2db uxtb r3, r3 + 8008214: 4619 mov r1, r3 + 8008216: 20f5 movs r0, #245 @ 0xf5 + 8008218: f000 f946 bl 80084a8 + SUBGRF_SendPayload( RadioBuffer, size + 1, 0xFFFFFF ); + 800821c: 78fb ldrb r3, [r7, #3] + 800821e: 3301 adds r3, #1 + 8008220: b2db uxtb r3, r3 + 8008222: f06f 427f mvn.w r2, #4278190080 @ 0xff000000 + 8008226: 4619 mov r1, r3 + 8008228: 480d ldr r0, [pc, #52] @ (8008260 ) + 800822a: f001 f9e1 bl 80095f0 + break; + 800822e: e000 b.n 8008232 + } +#endif /*RADIO_SIGFOX_ENABLE == 1*/ + default: + break; + 8008230: bf00 nop + } + + TimerSetValue( &TxTimeoutTimer, SubgRf.TxTimeout ); + 8008232: 4b08 ldr r3, [pc, #32] @ (8008254 ) + 8008234: 685b ldr r3, [r3, #4] + 8008236: 4619 mov r1, r3 + 8008238: 480a ldr r0, [pc, #40] @ (8008264 ) + 800823a: f004 fd1b bl 800cc74 + TimerStart( &TxTimeoutTimer ); + 800823e: 4809 ldr r0, [pc, #36] @ (8008264 ) + 8008240: f004 fc3a bl 800cab8 + } + + return RADIO_STATUS_OK; + 8008244: 2300 movs r3, #0 +} + 8008246: 4618 mov r0, r3 + 8008248: 3710 adds r7, #16 + 800824a: 46bd mov sp, r7 + 800824c: bd80 pop {r7, pc} + 800824e: bf00 nop + 8008250: 48000400 .word 0x48000400 + 8008254: 20000290 .word 0x20000290 + 8008258: 2000029e .word 0x2000029e + 800825c: 0800d538 .word 0x0800d538 + 8008260: 2000018c .word 0x2000018c + 8008264: 200002ec .word 0x200002ec + +08008268 : + +static void RadioSleep( void ) +{ + 8008268: b580 push {r7, lr} + 800826a: b082 sub sp, #8 + 800826c: af00 add r7, sp, #0 + SleepParams_t params = { 0 }; + 800826e: 2300 movs r3, #0 + 8008270: 713b strb r3, [r7, #4] + + params.Fields.WarmStart = 1; + 8008272: 793b ldrb r3, [r7, #4] + 8008274: f043 0304 orr.w r3, r3, #4 + 8008278: 713b strb r3, [r7, #4] + SUBGRF_SetSleep( params ); + 800827a: 7938 ldrb r0, [r7, #4] + 800827c: f001 fa94 bl 80097a8 + + RADIO_DELAY_MS( 2 ); + 8008280: 2002 movs r0, #2 + 8008282: f7f8 fc91 bl 8000ba8 +} + 8008286: bf00 nop + 8008288: 3708 adds r7, #8 + 800828a: 46bd mov sp, r7 + 800828c: bd80 pop {r7, pc} + +0800828e : + +static void RadioStandby( void ) +{ + 800828e: b580 push {r7, lr} + 8008290: af00 add r7, sp, #0 + SUBGRF_SetStandby( STDBY_RC ); + 8008292: 2000 movs r0, #0 + 8008294: f001 fabc bl 8009810 +} + 8008298: bf00 nop + 800829a: bd80 pop {r7, pc} + +0800829c : + +static void RadioRx( uint32_t timeout ) +{ + 800829c: b580 push {r7, lr} + 800829e: b082 sub sp, #8 + 80082a0: af00 add r7, sp, #0 + 80082a2: 6078 str r0, [r7, #4] + if( SubgRf.lr_fhss.is_lr_fhss_on == true ) + { + //return LORAMAC_RADIO_STATUS_ERROR; + } +#endif /* RADIO_LR_FHSS_IS_ON == 1 */ + if( 1UL == RFW_Is_Init( ) ) + 80082a4: f002 fdb4 bl 800ae10 + 80082a8: 4603 mov r3, r0 + 80082aa: 2b01 cmp r3, #1 + 80082ac: d102 bne.n 80082b4 + { + RFW_ReceiveInit( ); + 80082ae: f002 fe59 bl 800af64 + 80082b2: e007 b.n 80082c4 + } + else + { + SUBGRF_SetDioIrqParams( IRQ_RX_DONE | IRQ_RX_TX_TIMEOUT | IRQ_CRC_ERROR | IRQ_HEADER_ERROR | IRQ_RX_DBG, + 80082b4: 2300 movs r3, #0 + 80082b6: 2200 movs r2, #0 + 80082b8: f240 2162 movw r1, #610 @ 0x262 + 80082bc: f240 2062 movw r0, #610 @ 0x262 + 80082c0: f001 fc80 bl 8009bc4 + IRQ_RX_DONE | IRQ_RX_TX_TIMEOUT | IRQ_CRC_ERROR | IRQ_HEADER_ERROR | IRQ_RX_DBG, + IRQ_RADIO_NONE, + IRQ_RADIO_NONE ); + } + + if( timeout != 0 ) + 80082c4: 687b ldr r3, [r7, #4] + 80082c6: 2b00 cmp r3, #0 + 80082c8: d006 beq.n 80082d8 + { + TimerSetValue( &RxTimeoutTimer, timeout ); + 80082ca: 6879 ldr r1, [r7, #4] + 80082cc: 4813 ldr r0, [pc, #76] @ (800831c ) + 80082ce: f004 fcd1 bl 800cc74 + TimerStart( &RxTimeoutTimer ); + 80082d2: 4812 ldr r0, [pc, #72] @ (800831c ) + 80082d4: f004 fbf0 bl 800cab8 + } + /* switch off RxDcPreambleDetect See STM32WL Errata: RadioSetRxDutyCycle*/ + SubgRf.RxDcPreambleDetectTimeout = 0; + 80082d8: 4b11 ldr r3, [pc, #68] @ (8008320 ) + 80082da: 2200 movs r2, #0 + 80082dc: 659a str r2, [r3, #88] @ 0x58 + /* Set DBG pin */ + DBG_GPIO_RADIO_RX( SET ); + 80082de: f44f 5180 mov.w r1, #4096 @ 0x1000 + 80082e2: 4810 ldr r0, [pc, #64] @ (8008324 ) + 80082e4: f7ff f8d6 bl 8007494 + /* RF switch configuration */ + SUBGRF_SetSwitch( SubgRf.AntSwitchPaSelect, RFSWITCH_RX ); + 80082e8: 4b0d ldr r3, [pc, #52] @ (8008320 ) + 80082ea: f893 3056 ldrb.w r3, [r3, #86] @ 0x56 + 80082ee: 2100 movs r1, #0 + 80082f0: 4618 mov r0, r3 + 80082f2: f002 f91f bl 800a534 + + if( SubgRf.RxContinuous == true ) + 80082f6: 4b0a ldr r3, [pc, #40] @ (8008320 ) + 80082f8: 785b ldrb r3, [r3, #1] + 80082fa: 2b00 cmp r3, #0 + 80082fc: d004 beq.n 8008308 + { + SUBGRF_SetRx( 0xFFFFFF ); // Rx Continuous + 80082fe: f06f 407f mvn.w r0, #4278190080 @ 0xff000000 + 8008302: f001 fac1 bl 8009888 + } + else + { + SUBGRF_SetRx( SubgRf.RxTimeout << 6 ); + } +} + 8008306: e005 b.n 8008314 + SUBGRF_SetRx( SubgRf.RxTimeout << 6 ); + 8008308: 4b05 ldr r3, [pc, #20] @ (8008320 ) + 800830a: 689b ldr r3, [r3, #8] + 800830c: 019b lsls r3, r3, #6 + 800830e: 4618 mov r0, r3 + 8008310: f001 faba bl 8009888 +} + 8008314: bf00 nop + 8008316: 3708 adds r7, #8 + 8008318: 46bd mov sp, r7 + 800831a: bd80 pop {r7, pc} + 800831c: 20000304 .word 0x20000304 + 8008320: 20000290 .word 0x20000290 + 8008324: 48000400 .word 0x48000400 + +08008328 : + +static void RadioRxBoosted( uint32_t timeout ) +{ + 8008328: b580 push {r7, lr} + 800832a: b082 sub sp, #8 + 800832c: af00 add r7, sp, #0 + 800832e: 6078 str r0, [r7, #4] + if( SubgRf.lr_fhss.is_lr_fhss_on == true ) + { + //return LORAMAC_RADIO_STATUS_ERROR; + } +#endif /* RADIO_LR_FHSS_IS_ON == 1 */ + if( 1UL == RFW_Is_Init() ) + 8008330: f002 fd6e bl 800ae10 + 8008334: 4603 mov r3, r0 + 8008336: 2b01 cmp r3, #1 + 8008338: d102 bne.n 8008340 + { + RFW_ReceiveInit(); + 800833a: f002 fe13 bl 800af64 + 800833e: e007 b.n 8008350 + } + else + { + SUBGRF_SetDioIrqParams( IRQ_RX_DONE | IRQ_RX_TX_TIMEOUT | IRQ_CRC_ERROR | IRQ_HEADER_ERROR | IRQ_RX_DBG, + 8008340: 2300 movs r3, #0 + 8008342: 2200 movs r2, #0 + 8008344: f240 2162 movw r1, #610 @ 0x262 + 8008348: f240 2062 movw r0, #610 @ 0x262 + 800834c: f001 fc3a bl 8009bc4 + IRQ_RX_DONE | IRQ_RX_TX_TIMEOUT | IRQ_CRC_ERROR | IRQ_HEADER_ERROR | IRQ_RX_DBG, + IRQ_RADIO_NONE, + IRQ_RADIO_NONE ); + } + if( timeout != 0 ) + 8008350: 687b ldr r3, [r7, #4] + 8008352: 2b00 cmp r3, #0 + 8008354: d006 beq.n 8008364 + { + TimerSetValue( &RxTimeoutTimer, timeout ); + 8008356: 6879 ldr r1, [r7, #4] + 8008358: 4813 ldr r0, [pc, #76] @ (80083a8 ) + 800835a: f004 fc8b bl 800cc74 + TimerStart( &RxTimeoutTimer ); + 800835e: 4812 ldr r0, [pc, #72] @ (80083a8 ) + 8008360: f004 fbaa bl 800cab8 + } + /* switch off RxDcPreambleDetect See STM32WL Errata: RadioSetRxDutyCycle*/ + SubgRf.RxDcPreambleDetectTimeout = 0; + 8008364: 4b11 ldr r3, [pc, #68] @ (80083ac ) + 8008366: 2200 movs r2, #0 + 8008368: 659a str r2, [r3, #88] @ 0x58 + /* Set DBG pin */ + DBG_GPIO_RADIO_RX( SET ); + 800836a: f44f 5180 mov.w r1, #4096 @ 0x1000 + 800836e: 4810 ldr r0, [pc, #64] @ (80083b0 ) + 8008370: f7ff f890 bl 8007494 + /* RF switch configuration */ + SUBGRF_SetSwitch( SubgRf.AntSwitchPaSelect, RFSWITCH_RX ); + 8008374: 4b0d ldr r3, [pc, #52] @ (80083ac ) + 8008376: f893 3056 ldrb.w r3, [r3, #86] @ 0x56 + 800837a: 2100 movs r1, #0 + 800837c: 4618 mov r0, r3 + 800837e: f002 f8d9 bl 800a534 + + if( SubgRf.RxContinuous == true ) + 8008382: 4b0a ldr r3, [pc, #40] @ (80083ac ) + 8008384: 785b ldrb r3, [r3, #1] + 8008386: 2b00 cmp r3, #0 + 8008388: d004 beq.n 8008394 + { + SUBGRF_SetRxBoosted( 0xFFFFFF ); // Rx Continuous + 800838a: f06f 407f mvn.w r0, #4278190080 @ 0xff000000 + 800838e: f001 fa9b bl 80098c8 + } + else + { + SUBGRF_SetRxBoosted( SubgRf.RxTimeout << 6 ); + } +} + 8008392: e005 b.n 80083a0 + SUBGRF_SetRxBoosted( SubgRf.RxTimeout << 6 ); + 8008394: 4b05 ldr r3, [pc, #20] @ (80083ac ) + 8008396: 689b ldr r3, [r3, #8] + 8008398: 019b lsls r3, r3, #6 + 800839a: 4618 mov r0, r3 + 800839c: f001 fa94 bl 80098c8 +} + 80083a0: bf00 nop + 80083a2: 3708 adds r7, #8 + 80083a4: 46bd mov sp, r7 + 80083a6: bd80 pop {r7, pc} + 80083a8: 20000304 .word 0x20000304 + 80083ac: 20000290 .word 0x20000290 + 80083b0: 48000400 .word 0x48000400 + +080083b4 : + +static void RadioSetRxDutyCycle( uint32_t rxTime, uint32_t sleepTime ) +{ + 80083b4: b580 push {r7, lr} + 80083b6: b082 sub sp, #8 + 80083b8: af00 add r7, sp, #0 + 80083ba: 6078 str r0, [r7, #4] + 80083bc: 6039 str r1, [r7, #0] + /*See STM32WL Errata: RadioSetRxDutyCycle*/ + SubgRf.RxDcPreambleDetectTimeout = 2 * rxTime + sleepTime; + 80083be: 687b ldr r3, [r7, #4] + 80083c0: 005a lsls r2, r3, #1 + 80083c2: 683b ldr r3, [r7, #0] + 80083c4: 4413 add r3, r2 + 80083c6: 4a0c ldr r2, [pc, #48] @ (80083f8 ) + 80083c8: 6593 str r3, [r2, #88] @ 0x58 + /*Enable also the IRQ_PREAMBLE_DETECTED*/ + SUBGRF_SetDioIrqParams( IRQ_RADIO_ALL, IRQ_RADIO_ALL, IRQ_RADIO_NONE, IRQ_RADIO_NONE ); + 80083ca: 2300 movs r3, #0 + 80083cc: 2200 movs r2, #0 + 80083ce: f64f 71ff movw r1, #65535 @ 0xffff + 80083d2: f64f 70ff movw r0, #65535 @ 0xffff + 80083d6: f001 fbf5 bl 8009bc4 + /* RF switch configuration */ + SUBGRF_SetSwitch( SubgRf.AntSwitchPaSelect, RFSWITCH_RX ); + 80083da: 4b07 ldr r3, [pc, #28] @ (80083f8 ) + 80083dc: f893 3056 ldrb.w r3, [r3, #86] @ 0x56 + 80083e0: 2100 movs r1, #0 + 80083e2: 4618 mov r0, r3 + 80083e4: f002 f8a6 bl 800a534 + /* Start Rx DutyCycle*/ + SUBGRF_SetRxDutyCycle( rxTime, sleepTime ); + 80083e8: 6839 ldr r1, [r7, #0] + 80083ea: 6878 ldr r0, [r7, #4] + 80083ec: f001 fa90 bl 8009910 +} + 80083f0: bf00 nop + 80083f2: 3708 adds r7, #8 + 80083f4: 46bd mov sp, r7 + 80083f6: bd80 pop {r7, pc} + 80083f8: 20000290 .word 0x20000290 + +080083fc : + +static void RadioStartCad( void ) +{ + 80083fc: b580 push {r7, lr} + 80083fe: af00 add r7, sp, #0 + /* RF switch configuration */ + SUBGRF_SetSwitch( SubgRf.AntSwitchPaSelect, RFSWITCH_RX ); + 8008400: 4b09 ldr r3, [pc, #36] @ (8008428 ) + 8008402: f893 3056 ldrb.w r3, [r3, #86] @ 0x56 + 8008406: 2100 movs r1, #0 + 8008408: 4618 mov r0, r3 + 800840a: f002 f893 bl 800a534 + + SUBGRF_SetDioIrqParams( IRQ_CAD_CLEAR | IRQ_CAD_DETECTED, + 800840e: 2300 movs r3, #0 + 8008410: 2200 movs r2, #0 + 8008412: f44f 71c0 mov.w r1, #384 @ 0x180 + 8008416: f44f 70c0 mov.w r0, #384 @ 0x180 + 800841a: f001 fbd3 bl 8009bc4 + IRQ_CAD_CLEAR | IRQ_CAD_DETECTED, + IRQ_RADIO_NONE, + IRQ_RADIO_NONE ); + SUBGRF_SetCad( ); + 800841e: f001 faa3 bl 8009968 +} + 8008422: bf00 nop + 8008424: bd80 pop {r7, pc} + 8008426: bf00 nop + 8008428: 20000290 .word 0x20000290 + +0800842c : + +static void RadioSetTxContinuousWave( uint32_t freq, int8_t power, uint16_t time ) +{ + 800842c: b580 push {r7, lr} + 800842e: b084 sub sp, #16 + 8008430: af00 add r7, sp, #0 + 8008432: 6078 str r0, [r7, #4] + 8008434: 460b mov r3, r1 + 8008436: 70fb strb r3, [r7, #3] + 8008438: 4613 mov r3, r2 + 800843a: 803b strh r3, [r7, #0] + if( SubgRf.lr_fhss.is_lr_fhss_on == true ) + { + //return LORAMAC_RADIO_STATUS_ERROR; + } +#endif /* RADIO_LR_FHSS_IS_ON == 1 */ + uint32_t timeout = ( uint32_t )time * 1000; + 800843c: 883b ldrh r3, [r7, #0] + 800843e: f44f 727a mov.w r2, #1000 @ 0x3e8 + 8008442: fb02 f303 mul.w r3, r2, r3 + 8008446: 60fb str r3, [r7, #12] + uint8_t antswitchpow; + + SUBGRF_SetRfFrequency( freq ); + 8008448: 6878 ldr r0, [r7, #4] + 800844a: f001 fc17 bl 8009c7c + + antswitchpow = SUBGRF_SetRfTxPower( power ); + 800844e: f997 3003 ldrsb.w r3, [r7, #3] + 8008452: 4618 mov r0, r3 + 8008454: f002 f896 bl 800a584 + 8008458: 4603 mov r3, r0 + 800845a: 72fb strb r3, [r7, #11] + + /* WORKAROUND - Trimming the output voltage power_ldo to 3.3V */ + SUBGRF_WriteRegister(REG_DRV_CTRL, 0x7 << 1); + 800845c: 210e movs r1, #14 + 800845e: f640 101f movw r0, #2335 @ 0x91f + 8008462: f001 ff59 bl 800a318 + + /* Set RF switch */ + SUBGRF_SetSwitch( antswitchpow, RFSWITCH_TX ); + 8008466: 7afb ldrb r3, [r7, #11] + 8008468: 2101 movs r1, #1 + 800846a: 4618 mov r0, r3 + 800846c: f002 f862 bl 800a534 + + SUBGRF_SetTxContinuousWave( ); + 8008470: f001 fa88 bl 8009984 + + TimerSetValue( &TxTimeoutTimer, timeout ); + 8008474: 68f9 ldr r1, [r7, #12] + 8008476: 4805 ldr r0, [pc, #20] @ (800848c ) + 8008478: f004 fbfc bl 800cc74 + TimerStart( &TxTimeoutTimer ); + 800847c: 4803 ldr r0, [pc, #12] @ (800848c ) + 800847e: f004 fb1b bl 800cab8 +} + 8008482: bf00 nop + 8008484: 3710 adds r7, #16 + 8008486: 46bd mov sp, r7 + 8008488: bd80 pop {r7, pc} + 800848a: bf00 nop + 800848c: 200002ec .word 0x200002ec + +08008490 : + +static int16_t RadioRssi( RadioModems_t modem ) +{ + 8008490: b580 push {r7, lr} + 8008492: b082 sub sp, #8 + 8008494: af00 add r7, sp, #0 + 8008496: 4603 mov r3, r0 + 8008498: 71fb strb r3, [r7, #7] + return SUBGRF_GetRssiInst( ); + 800849a: f001 feaa bl 800a1f2 + 800849e: 4603 mov r3, r0 +} + 80084a0: 4618 mov r0, r3 + 80084a2: 3708 adds r7, #8 + 80084a4: 46bd mov sp, r7 + 80084a6: bd80 pop {r7, pc} + +080084a8 : + +static void RadioWrite( uint16_t addr, uint8_t data ) +{ + 80084a8: b580 push {r7, lr} + 80084aa: b082 sub sp, #8 + 80084ac: af00 add r7, sp, #0 + 80084ae: 4603 mov r3, r0 + 80084b0: 460a mov r2, r1 + 80084b2: 80fb strh r3, [r7, #6] + 80084b4: 4613 mov r3, r2 + 80084b6: 717b strb r3, [r7, #5] + SUBGRF_WriteRegister( addr, data ); + 80084b8: 797a ldrb r2, [r7, #5] + 80084ba: 88fb ldrh r3, [r7, #6] + 80084bc: 4611 mov r1, r2 + 80084be: 4618 mov r0, r3 + 80084c0: f001 ff2a bl 800a318 +} + 80084c4: bf00 nop + 80084c6: 3708 adds r7, #8 + 80084c8: 46bd mov sp, r7 + 80084ca: bd80 pop {r7, pc} + +080084cc : + +static uint8_t RadioRead( uint16_t addr ) +{ + 80084cc: b580 push {r7, lr} + 80084ce: b082 sub sp, #8 + 80084d0: af00 add r7, sp, #0 + 80084d2: 4603 mov r3, r0 + 80084d4: 80fb strh r3, [r7, #6] + return SUBGRF_ReadRegister( addr ); + 80084d6: 88fb ldrh r3, [r7, #6] + 80084d8: 4618 mov r0, r3 + 80084da: f001 ff3f bl 800a35c + 80084de: 4603 mov r3, r0 +} + 80084e0: 4618 mov r0, r3 + 80084e2: 3708 adds r7, #8 + 80084e4: 46bd mov sp, r7 + 80084e6: bd80 pop {r7, pc} + +080084e8 : + +static void RadioWriteRegisters( uint16_t addr, uint8_t *buffer, uint8_t size ) +{ + 80084e8: b580 push {r7, lr} + 80084ea: b082 sub sp, #8 + 80084ec: af00 add r7, sp, #0 + 80084ee: 4603 mov r3, r0 + 80084f0: 6039 str r1, [r7, #0] + 80084f2: 80fb strh r3, [r7, #6] + 80084f4: 4613 mov r3, r2 + 80084f6: 717b strb r3, [r7, #5] + SUBGRF_WriteRegisters( addr, buffer, size ); + 80084f8: 797b ldrb r3, [r7, #5] + 80084fa: b29a uxth r2, r3 + 80084fc: 88fb ldrh r3, [r7, #6] + 80084fe: 6839 ldr r1, [r7, #0] + 8008500: 4618 mov r0, r3 + 8008502: f001 ff4b bl 800a39c +} + 8008506: bf00 nop + 8008508: 3708 adds r7, #8 + 800850a: 46bd mov sp, r7 + 800850c: bd80 pop {r7, pc} + +0800850e : + +static void RadioReadRegisters( uint16_t addr, uint8_t *buffer, uint8_t size ) +{ + 800850e: b580 push {r7, lr} + 8008510: b082 sub sp, #8 + 8008512: af00 add r7, sp, #0 + 8008514: 4603 mov r3, r0 + 8008516: 6039 str r1, [r7, #0] + 8008518: 80fb strh r3, [r7, #6] + 800851a: 4613 mov r3, r2 + 800851c: 717b strb r3, [r7, #5] + SUBGRF_ReadRegisters( addr, buffer, size ); + 800851e: 797b ldrb r3, [r7, #5] + 8008520: b29a uxth r2, r3 + 8008522: 88fb ldrh r3, [r7, #6] + 8008524: 6839 ldr r1, [r7, #0] + 8008526: 4618 mov r0, r3 + 8008528: f001 ff5a bl 800a3e0 +} + 800852c: bf00 nop + 800852e: 3708 adds r7, #8 + 8008530: 46bd mov sp, r7 + 8008532: bd80 pop {r7, pc} + +08008534 : + +static void RadioSetMaxPayloadLength( RadioModems_t modem, uint8_t max ) +{ + 8008534: b580 push {r7, lr} + 8008536: b082 sub sp, #8 + 8008538: af00 add r7, sp, #0 + 800853a: 4603 mov r3, r0 + 800853c: 460a mov r2, r1 + 800853e: 71fb strb r3, [r7, #7] + 8008540: 4613 mov r3, r2 + 8008542: 71bb strb r3, [r7, #6] + if( modem == MODEM_LORA ) + 8008544: 79fb ldrb r3, [r7, #7] + 8008546: 2b01 cmp r3, #1 + 8008548: d10a bne.n 8008560 + { + SubgRf.PacketParams.Params.LoRa.PayloadLength = MaxPayloadLength = max; + 800854a: 4a0e ldr r2, [pc, #56] @ (8008584 ) + 800854c: 79bb ldrb r3, [r7, #6] + 800854e: 7013 strb r3, [r2, #0] + 8008550: 4b0c ldr r3, [pc, #48] @ (8008584 ) + 8008552: 781a ldrb r2, [r3, #0] + 8008554: 4b0c ldr r3, [pc, #48] @ (8008588 ) + 8008556: 77da strb r2, [r3, #31] + SUBGRF_SetPacketParams( &SubgRf.PacketParams ); + 8008558: 480c ldr r0, [pc, #48] @ (800858c ) + 800855a: f001 fd97 bl 800a08c + { + SubgRf.PacketParams.Params.Gfsk.PayloadLength = MaxPayloadLength = max; + SUBGRF_SetPacketParams( &SubgRf.PacketParams ); + } + } +} + 800855e: e00d b.n 800857c + if( SubgRf.PacketParams.Params.Gfsk.HeaderType == RADIO_PACKET_VARIABLE_LENGTH ) + 8008560: 4b09 ldr r3, [pc, #36] @ (8008588 ) + 8008562: 7d5b ldrb r3, [r3, #21] + 8008564: 2b01 cmp r3, #1 + 8008566: d109 bne.n 800857c + SubgRf.PacketParams.Params.Gfsk.PayloadLength = MaxPayloadLength = max; + 8008568: 4a06 ldr r2, [pc, #24] @ (8008584 ) + 800856a: 79bb ldrb r3, [r7, #6] + 800856c: 7013 strb r3, [r2, #0] + 800856e: 4b05 ldr r3, [pc, #20] @ (8008584 ) + 8008570: 781a ldrb r2, [r3, #0] + 8008572: 4b05 ldr r3, [pc, #20] @ (8008588 ) + 8008574: 759a strb r2, [r3, #22] + SUBGRF_SetPacketParams( &SubgRf.PacketParams ); + 8008576: 4805 ldr r0, [pc, #20] @ (800858c ) + 8008578: f001 fd88 bl 800a08c +} + 800857c: bf00 nop + 800857e: 3708 adds r7, #8 + 8008580: 46bd mov sp, r7 + 8008582: bd80 pop {r7, pc} + 8008584: 20000008 .word 0x20000008 + 8008588: 20000290 .word 0x20000290 + 800858c: 2000029e .word 0x2000029e + +08008590 : + +static void RadioSetPublicNetwork( bool enable ) +{ + 8008590: b580 push {r7, lr} + 8008592: b082 sub sp, #8 + 8008594: af00 add r7, sp, #0 + 8008596: 4603 mov r3, r0 + 8008598: 71fb strb r3, [r7, #7] + SubgRf.PublicNetwork.Current = SubgRf.PublicNetwork.Previous = enable; + 800859a: 4a13 ldr r2, [pc, #76] @ (80085e8 ) + 800859c: 79fb ldrb r3, [r7, #7] + 800859e: 7313 strb r3, [r2, #12] + 80085a0: 4b11 ldr r3, [pc, #68] @ (80085e8 ) + 80085a2: 7b1a ldrb r2, [r3, #12] + 80085a4: 4b10 ldr r3, [pc, #64] @ (80085e8 ) + 80085a6: 735a strb r2, [r3, #13] + + RadioSetModem( MODEM_LORA ); + 80085a8: 2001 movs r0, #1 + 80085aa: f7ff f801 bl 80075b0 + if( enable == true ) + 80085ae: 79fb ldrb r3, [r7, #7] + 80085b0: 2b00 cmp r3, #0 + 80085b2: d00a beq.n 80085ca + { + // Change LoRa modem SyncWord + SUBGRF_WriteRegister( REG_LR_SYNCWORD, ( LORA_MAC_PUBLIC_SYNCWORD >> 8 ) & 0xFF ); + 80085b4: 2134 movs r1, #52 @ 0x34 + 80085b6: f44f 60e8 mov.w r0, #1856 @ 0x740 + 80085ba: f001 fead bl 800a318 + SUBGRF_WriteRegister( REG_LR_SYNCWORD + 1, LORA_MAC_PUBLIC_SYNCWORD & 0xFF ); + 80085be: 2144 movs r1, #68 @ 0x44 + 80085c0: f240 7041 movw r0, #1857 @ 0x741 + 80085c4: f001 fea8 bl 800a318 + { + // Change LoRa modem SyncWord + SUBGRF_WriteRegister( REG_LR_SYNCWORD, ( LORA_MAC_PRIVATE_SYNCWORD >> 8 ) & 0xFF ); + SUBGRF_WriteRegister( REG_LR_SYNCWORD + 1, LORA_MAC_PRIVATE_SYNCWORD & 0xFF ); + } +} + 80085c8: e009 b.n 80085de + SUBGRF_WriteRegister( REG_LR_SYNCWORD, ( LORA_MAC_PRIVATE_SYNCWORD >> 8 ) & 0xFF ); + 80085ca: 2114 movs r1, #20 + 80085cc: f44f 60e8 mov.w r0, #1856 @ 0x740 + 80085d0: f001 fea2 bl 800a318 + SUBGRF_WriteRegister( REG_LR_SYNCWORD + 1, LORA_MAC_PRIVATE_SYNCWORD & 0xFF ); + 80085d4: 2124 movs r1, #36 @ 0x24 + 80085d6: f240 7041 movw r0, #1857 @ 0x741 + 80085da: f001 fe9d bl 800a318 +} + 80085de: bf00 nop + 80085e0: 3708 adds r7, #8 + 80085e2: 46bd mov sp, r7 + 80085e4: bd80 pop {r7, pc} + 80085e6: bf00 nop + 80085e8: 20000290 .word 0x20000290 + +080085ec : + +static uint32_t RadioGetWakeupTime( void ) +{ + 80085ec: b580 push {r7, lr} + 80085ee: af00 add r7, sp, #0 + return SUBGRF_GetRadioWakeUpTime() + RADIO_WAKEUP_TIME; + 80085f0: f001 fffc bl 800a5ec + 80085f4: 4603 mov r3, r0 + 80085f6: 3303 adds r3, #3 +} + 80085f8: 4618 mov r0, r3 + 80085fa: bd80 pop {r7, pc} + +080085fc : + +static void RadioOnTxTimeoutIrq( void *context ) +{ + 80085fc: b580 push {r7, lr} + 80085fe: b082 sub sp, #8 + 8008600: af00 add r7, sp, #0 + 8008602: 6078 str r0, [r7, #4] + RADIO_TX_TIMEOUT_PROCESS(); + 8008604: f000 f80e bl 8008624 +} + 8008608: bf00 nop + 800860a: 3708 adds r7, #8 + 800860c: 46bd mov sp, r7 + 800860e: bd80 pop {r7, pc} + +08008610 : + +static void RadioOnRxTimeoutIrq( void *context ) +{ + 8008610: b580 push {r7, lr} + 8008612: b082 sub sp, #8 + 8008614: af00 add r7, sp, #0 + 8008616: 6078 str r0, [r7, #4] + RADIO_RX_TIMEOUT_PROCESS(); + 8008618: f000 f81e bl 8008658 +} + 800861c: bf00 nop + 800861e: 3708 adds r7, #8 + 8008620: 46bd mov sp, r7 + 8008622: bd80 pop {r7, pc} + +08008624 : + +static void RadioOnTxTimeoutProcess( void ) +{ + 8008624: b580 push {r7, lr} + 8008626: af00 add r7, sp, #0 + DBG_GPIO_RADIO_TX( RST ); + 8008628: f44f 5100 mov.w r1, #8192 @ 0x2000 + 800862c: 4808 ldr r0, [pc, #32] @ (8008650 ) + 800862e: f7fe ff3e bl 80074ae + + if( ( RadioEvents != NULL ) && ( RadioEvents->TxTimeout != NULL ) ) + 8008632: 4b08 ldr r3, [pc, #32] @ (8008654 ) + 8008634: 681b ldr r3, [r3, #0] + 8008636: 2b00 cmp r3, #0 + 8008638: d008 beq.n 800864c + 800863a: 4b06 ldr r3, [pc, #24] @ (8008654 ) + 800863c: 681b ldr r3, [r3, #0] + 800863e: 685b ldr r3, [r3, #4] + 8008640: 2b00 cmp r3, #0 + 8008642: d003 beq.n 800864c + { + RadioEvents->TxTimeout( ); + 8008644: 4b03 ldr r3, [pc, #12] @ (8008654 ) + 8008646: 681b ldr r3, [r3, #0] + 8008648: 685b ldr r3, [r3, #4] + 800864a: 4798 blx r3 + } +} + 800864c: bf00 nop + 800864e: bd80 pop {r7, pc} + 8008650: 48000400 .word 0x48000400 + 8008654: 2000028c .word 0x2000028c + +08008658 : + +static void RadioOnRxTimeoutProcess( void ) +{ + 8008658: b580 push {r7, lr} + 800865a: af00 add r7, sp, #0 + DBG_GPIO_RADIO_RX( RST ); + 800865c: f44f 5180 mov.w r1, #4096 @ 0x1000 + 8008660: 4808 ldr r0, [pc, #32] @ (8008684 ) + 8008662: f7fe ff24 bl 80074ae + + if( ( RadioEvents != NULL ) && ( RadioEvents->RxTimeout != NULL ) ) + 8008666: 4b08 ldr r3, [pc, #32] @ (8008688 ) + 8008668: 681b ldr r3, [r3, #0] + 800866a: 2b00 cmp r3, #0 + 800866c: d008 beq.n 8008680 + 800866e: 4b06 ldr r3, [pc, #24] @ (8008688 ) + 8008670: 681b ldr r3, [r3, #0] + 8008672: 68db ldr r3, [r3, #12] + 8008674: 2b00 cmp r3, #0 + 8008676: d003 beq.n 8008680 + { + RadioEvents->RxTimeout( ); + 8008678: 4b03 ldr r3, [pc, #12] @ (8008688 ) + 800867a: 681b ldr r3, [r3, #0] + 800867c: 68db ldr r3, [r3, #12] + 800867e: 4798 blx r3 + } +} + 8008680: bf00 nop + 8008682: bd80 pop {r7, pc} + 8008684: 48000400 .word 0x48000400 + 8008688: 2000028c .word 0x2000028c + +0800868c : + +static void RadioOnDioIrq( RadioIrqMasks_t radioIrq ) +{ + 800868c: b580 push {r7, lr} + 800868e: b082 sub sp, #8 + 8008690: af00 add r7, sp, #0 + 8008692: 4603 mov r3, r0 + 8008694: 80fb strh r3, [r7, #6] + SubgRf.RadioIrq = radioIrq; + 8008696: 4a05 ldr r2, [pc, #20] @ (80086ac ) + 8008698: 88fb ldrh r3, [r7, #6] + 800869a: f8a2 3054 strh.w r3, [r2, #84] @ 0x54 + + RADIO_IRQ_PROCESS(); + 800869e: f000 f807 bl 80086b0 +} + 80086a2: bf00 nop + 80086a4: 3708 adds r7, #8 + 80086a6: 46bd mov sp, r7 + 80086a8: bd80 pop {r7, pc} + 80086aa: bf00 nop + 80086ac: 20000290 .word 0x20000290 + +080086b0 : + +static void RadioIrqProcess( void ) +{ + 80086b0: b5b0 push {r4, r5, r7, lr} + 80086b2: b082 sub sp, #8 + 80086b4: af00 add r7, sp, #0 + uint8_t size = 0; + 80086b6: 2300 movs r3, #0 + 80086b8: 71fb strb r3, [r7, #7] + int32_t cfo = 0; + 80086ba: 2300 movs r3, #0 + 80086bc: 603b str r3, [r7, #0] + + switch( SubgRf.RadioIrq ) + 80086be: 4bb2 ldr r3, [pc, #712] @ (8008988 ) + 80086c0: f8b3 3054 ldrh.w r3, [r3, #84] @ 0x54 + 80086c4: f5b3 7f00 cmp.w r3, #512 @ 0x200 + 80086c8: f000 8117 beq.w 80088fa + 80086cc: f5b3 7f00 cmp.w r3, #512 @ 0x200 + 80086d0: f300 81fe bgt.w 8008ad0 + 80086d4: f5b3 7f80 cmp.w r3, #256 @ 0x100 + 80086d8: f000 80fb beq.w 80088d2 + 80086dc: f5b3 7f80 cmp.w r3, #256 @ 0x100 + 80086e0: f300 81f6 bgt.w 8008ad0 + 80086e4: 2b80 cmp r3, #128 @ 0x80 + 80086e6: f000 80e0 beq.w 80088aa + 80086ea: 2b80 cmp r3, #128 @ 0x80 + 80086ec: f300 81f0 bgt.w 8008ad0 + 80086f0: 2b20 cmp r3, #32 + 80086f2: dc49 bgt.n 8008788 + 80086f4: 2b00 cmp r3, #0 + 80086f6: f340 81eb ble.w 8008ad0 + 80086fa: 3b01 subs r3, #1 + 80086fc: 2b1f cmp r3, #31 + 80086fe: f200 81e7 bhi.w 8008ad0 + 8008702: a201 add r2, pc, #4 @ (adr r2, 8008708 ) + 8008704: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 8008708: 08008791 .word 0x08008791 + 800870c: 080087d5 .word 0x080087d5 + 8008710: 08008ad1 .word 0x08008ad1 + 8008714: 080089ad .word 0x080089ad + 8008718: 08008ad1 .word 0x08008ad1 + 800871c: 08008ad1 .word 0x08008ad1 + 8008720: 08008ad1 .word 0x08008ad1 + 8008724: 08008a29 .word 0x08008a29 + 8008728: 08008ad1 .word 0x08008ad1 + 800872c: 08008ad1 .word 0x08008ad1 + 8008730: 08008ad1 .word 0x08008ad1 + 8008734: 08008ad1 .word 0x08008ad1 + 8008738: 08008ad1 .word 0x08008ad1 + 800873c: 08008ad1 .word 0x08008ad1 + 8008740: 08008ad1 .word 0x08008ad1 + 8008744: 08008a45 .word 0x08008a45 + 8008748: 08008ad1 .word 0x08008ad1 + 800874c: 08008ad1 .word 0x08008ad1 + 8008750: 08008ad1 .word 0x08008ad1 + 8008754: 08008ad1 .word 0x08008ad1 + 8008758: 08008ad1 .word 0x08008ad1 + 800875c: 08008ad1 .word 0x08008ad1 + 8008760: 08008ad1 .word 0x08008ad1 + 8008764: 08008ad1 .word 0x08008ad1 + 8008768: 08008ad1 .word 0x08008ad1 + 800876c: 08008ad1 .word 0x08008ad1 + 8008770: 08008ad1 .word 0x08008ad1 + 8008774: 08008ad1 .word 0x08008ad1 + 8008778: 08008ad1 .word 0x08008ad1 + 800877c: 08008ad1 .word 0x08008ad1 + 8008780: 08008ad1 .word 0x08008ad1 + 8008784: 08008a53 .word 0x08008a53 + 8008788: 2b40 cmp r3, #64 @ 0x40 + 800878a: f000 8183 beq.w 8008a94 + MW_LOG( TS_ON, VLEVEL_M, "HOP\r\n" ); + break; + } +#endif /* RADIO_LR_FHSS_IS_ON == 1 */ + default: + break; + 800878e: e19f b.n 8008ad0 + DBG_GPIO_RADIO_TX( RST ); + 8008790: f44f 5100 mov.w r1, #8192 @ 0x2000 + 8008794: 487d ldr r0, [pc, #500] @ (800898c ) + 8008796: f7fe fe8a bl 80074ae + TimerStop( &TxTimeoutTimer ); + 800879a: 487d ldr r0, [pc, #500] @ (8008990 ) + 800879c: f004 f9fa bl 800cb94 + SUBGRF_SetStandby( STDBY_RC ); + 80087a0: 2000 movs r0, #0 + 80087a2: f001 f835 bl 8009810 + if( RFW_Is_LongPacketModeEnabled() == 1 ) + 80087a6: f002 fb3d bl 800ae24 + 80087aa: 4603 mov r3, r0 + 80087ac: 2b01 cmp r3, #1 + 80087ae: d101 bne.n 80087b4 + RFW_DeInit_TxLongPacket( ); + 80087b0: f002 fbf4 bl 800af9c + if( ( RadioEvents != NULL ) && ( RadioEvents->TxDone != NULL ) ) + 80087b4: 4b77 ldr r3, [pc, #476] @ (8008994 ) + 80087b6: 681b ldr r3, [r3, #0] + 80087b8: 2b00 cmp r3, #0 + 80087ba: f000 818b beq.w 8008ad4 + 80087be: 4b75 ldr r3, [pc, #468] @ (8008994 ) + 80087c0: 681b ldr r3, [r3, #0] + 80087c2: 681b ldr r3, [r3, #0] + 80087c4: 2b00 cmp r3, #0 + 80087c6: f000 8185 beq.w 8008ad4 + RadioEvents->TxDone( ); + 80087ca: 4b72 ldr r3, [pc, #456] @ (8008994 ) + 80087cc: 681b ldr r3, [r3, #0] + 80087ce: 681b ldr r3, [r3, #0] + 80087d0: 4798 blx r3 + break; + 80087d2: e17f b.n 8008ad4 + DBG_GPIO_RADIO_RX( RST ); + 80087d4: f44f 5180 mov.w r1, #4096 @ 0x1000 + 80087d8: 486c ldr r0, [pc, #432] @ (800898c ) + 80087da: f7fe fe68 bl 80074ae + TimerStop( &RxTimeoutTimer ); + 80087de: 486e ldr r0, [pc, #440] @ (8008998 ) + 80087e0: f004 f9d8 bl 800cb94 + if( SubgRf.RxContinuous == false ) + 80087e4: 4b68 ldr r3, [pc, #416] @ (8008988 ) + 80087e6: 785b ldrb r3, [r3, #1] + 80087e8: f083 0301 eor.w r3, r3, #1 + 80087ec: b2db uxtb r3, r3 + 80087ee: 2b00 cmp r3, #0 + 80087f0: d014 beq.n 800881c + SUBGRF_SetStandby( STDBY_RC ); + 80087f2: 2000 movs r0, #0 + 80087f4: f001 f80c bl 8009810 + SUBGRF_WriteRegister( SUBGHZ_RTCCTLR, 0x00 ); + 80087f8: 2100 movs r1, #0 + 80087fa: f640 1002 movw r0, #2306 @ 0x902 + 80087fe: f001 fd8b bl 800a318 + SUBGRF_WriteRegister( SUBGHZ_EVENTMASKR, SUBGRF_ReadRegister( SUBGHZ_EVENTMASKR ) | ( 1 << 1 ) ); + 8008802: f640 1044 movw r0, #2372 @ 0x944 + 8008806: f001 fda9 bl 800a35c + 800880a: 4603 mov r3, r0 + 800880c: f043 0302 orr.w r3, r3, #2 + 8008810: b2db uxtb r3, r3 + 8008812: 4619 mov r1, r3 + 8008814: f640 1044 movw r0, #2372 @ 0x944 + 8008818: f001 fd7e bl 800a318 + SUBGRF_GetPayload( RadioBuffer, &size, 255 ); + 800881c: 1dfb adds r3, r7, #7 + 800881e: 22ff movs r2, #255 @ 0xff + 8008820: 4619 mov r1, r3 + 8008822: 485e ldr r0, [pc, #376] @ (800899c ) + 8008824: f000 fec2 bl 80095ac + SUBGRF_GetPacketStatus( &( SubgRf.PacketStatus ) ); + 8008828: 485d ldr r0, [pc, #372] @ (80089a0 ) + 800882a: f001 fd23 bl 800a274 + if( ( RadioEvents != NULL ) && ( RadioEvents->RxDone != NULL ) ) + 800882e: 4b59 ldr r3, [pc, #356] @ (8008994 ) + 8008830: 681b ldr r3, [r3, #0] + 8008832: 2b00 cmp r3, #0 + 8008834: f000 8150 beq.w 8008ad8 + 8008838: 4b56 ldr r3, [pc, #344] @ (8008994 ) + 800883a: 681b ldr r3, [r3, #0] + 800883c: 689b ldr r3, [r3, #8] + 800883e: 2b00 cmp r3, #0 + 8008840: f000 814a beq.w 8008ad8 + switch( SubgRf.PacketStatus.packetType ) + 8008844: 4b50 ldr r3, [pc, #320] @ (8008988 ) + 8008846: f893 3024 ldrb.w r3, [r3, #36] @ 0x24 + 800884a: 2b01 cmp r3, #1 + 800884c: d10e bne.n 800886c + RadioEvents->RxDone( RadioBuffer, size, SubgRf.PacketStatus.Params.LoRa.RssiPkt, + 800884e: 4b51 ldr r3, [pc, #324] @ (8008994 ) + 8008850: 681b ldr r3, [r3, #0] + 8008852: 689c ldr r4, [r3, #8] + 8008854: 79fb ldrb r3, [r7, #7] + 8008856: 4619 mov r1, r3 + 8008858: 4b4b ldr r3, [pc, #300] @ (8008988 ) + 800885a: f993 3030 ldrsb.w r3, [r3, #48] @ 0x30 + 800885e: 461a mov r2, r3 + 8008860: 4b49 ldr r3, [pc, #292] @ (8008988 ) + 8008862: f993 3031 ldrsb.w r3, [r3, #49] @ 0x31 + 8008866: 484d ldr r0, [pc, #308] @ (800899c ) + 8008868: 47a0 blx r4 + break; + 800886a: e01d b.n 80088a8 + SUBGRF_GetCFO( SubgRf.ModulationParams.Params.Gfsk.BitRate, &cfo ); + 800886c: 4b46 ldr r3, [pc, #280] @ (8008988 ) + 800886e: 6bdb ldr r3, [r3, #60] @ 0x3c + 8008870: 463a mov r2, r7 + 8008872: 4611 mov r1, r2 + 8008874: 4618 mov r0, r3 + 8008876: f001 ffab bl 800a7d0 + RadioEvents->RxDone( RadioBuffer, size, SubgRf.PacketStatus.Params.Gfsk.RssiAvg, ( int8_t ) DIVR( cfo, 1000 ) ); + 800887a: 4b46 ldr r3, [pc, #280] @ (8008994 ) + 800887c: 681b ldr r3, [r3, #0] + 800887e: 689c ldr r4, [r3, #8] + 8008880: 79fb ldrb r3, [r7, #7] + 8008882: 4619 mov r1, r3 + 8008884: 4b40 ldr r3, [pc, #256] @ (8008988 ) + 8008886: f993 3029 ldrsb.w r3, [r3, #41] @ 0x29 + 800888a: 4618 mov r0, r3 + 800888c: 683b ldr r3, [r7, #0] + 800888e: f503 73fa add.w r3, r3, #500 @ 0x1f4 + 8008892: 4a44 ldr r2, [pc, #272] @ (80089a4 ) + 8008894: fb82 5203 smull r5, r2, r2, r3 + 8008898: 1192 asrs r2, r2, #6 + 800889a: 17db asrs r3, r3, #31 + 800889c: 1ad3 subs r3, r2, r3 + 800889e: b25b sxtb r3, r3 + 80088a0: 4602 mov r2, r0 + 80088a2: 483e ldr r0, [pc, #248] @ (800899c ) + 80088a4: 47a0 blx r4 + break; + 80088a6: bf00 nop + break; + 80088a8: e116 b.n 8008ad8 + SUBGRF_SetStandby( STDBY_RC ); + 80088aa: 2000 movs r0, #0 + 80088ac: f000 ffb0 bl 8009810 + if( ( RadioEvents != NULL ) && ( RadioEvents->CadDone != NULL ) ) + 80088b0: 4b38 ldr r3, [pc, #224] @ (8008994 ) + 80088b2: 681b ldr r3, [r3, #0] + 80088b4: 2b00 cmp r3, #0 + 80088b6: f000 8111 beq.w 8008adc + 80088ba: 4b36 ldr r3, [pc, #216] @ (8008994 ) + 80088bc: 681b ldr r3, [r3, #0] + 80088be: 699b ldr r3, [r3, #24] + 80088c0: 2b00 cmp r3, #0 + 80088c2: f000 810b beq.w 8008adc + RadioEvents->CadDone( false ); + 80088c6: 4b33 ldr r3, [pc, #204] @ (8008994 ) + 80088c8: 681b ldr r3, [r3, #0] + 80088ca: 699b ldr r3, [r3, #24] + 80088cc: 2000 movs r0, #0 + 80088ce: 4798 blx r3 + break; + 80088d0: e104 b.n 8008adc + SUBGRF_SetStandby( STDBY_RC ); + 80088d2: 2000 movs r0, #0 + 80088d4: f000 ff9c bl 8009810 + if( ( RadioEvents != NULL ) && ( RadioEvents->CadDone != NULL ) ) + 80088d8: 4b2e ldr r3, [pc, #184] @ (8008994 ) + 80088da: 681b ldr r3, [r3, #0] + 80088dc: 2b00 cmp r3, #0 + 80088de: f000 80ff beq.w 8008ae0 + 80088e2: 4b2c ldr r3, [pc, #176] @ (8008994 ) + 80088e4: 681b ldr r3, [r3, #0] + 80088e6: 699b ldr r3, [r3, #24] + 80088e8: 2b00 cmp r3, #0 + 80088ea: f000 80f9 beq.w 8008ae0 + RadioEvents->CadDone( true ); + 80088ee: 4b29 ldr r3, [pc, #164] @ (8008994 ) + 80088f0: 681b ldr r3, [r3, #0] + 80088f2: 699b ldr r3, [r3, #24] + 80088f4: 2001 movs r0, #1 + 80088f6: 4798 blx r3 + break; + 80088f8: e0f2 b.n 8008ae0 + MW_LOG( TS_ON, VLEVEL_M, "IRQ_RX_TX_TIMEOUT\r\n" ); + 80088fa: 4b2b ldr r3, [pc, #172] @ (80089a8 ) + 80088fc: 2201 movs r2, #1 + 80088fe: 2100 movs r1, #0 + 8008900: 2002 movs r0, #2 + 8008902: f004 fb3f bl 800cf84 + if( SUBGRF_GetOperatingMode( ) == MODE_TX ) + 8008906: f000 fe37 bl 8009578 + 800890a: 4603 mov r3, r0 + 800890c: 2b04 cmp r3, #4 + 800890e: d11a bne.n 8008946 + DBG_GPIO_RADIO_TX( RST ); + 8008910: f44f 5100 mov.w r1, #8192 @ 0x2000 + 8008914: 481d ldr r0, [pc, #116] @ (800898c ) + 8008916: f7fe fdca bl 80074ae + TimerStop( &TxTimeoutTimer ); + 800891a: 481d ldr r0, [pc, #116] @ (8008990 ) + 800891c: f004 f93a bl 800cb94 + SUBGRF_SetStandby( STDBY_RC ); + 8008920: 2000 movs r0, #0 + 8008922: f000 ff75 bl 8009810 + if( ( RadioEvents != NULL ) && ( RadioEvents->TxTimeout != NULL ) ) + 8008926: 4b1b ldr r3, [pc, #108] @ (8008994 ) + 8008928: 681b ldr r3, [r3, #0] + 800892a: 2b00 cmp r3, #0 + 800892c: f000 80da beq.w 8008ae4 + 8008930: 4b18 ldr r3, [pc, #96] @ (8008994 ) + 8008932: 681b ldr r3, [r3, #0] + 8008934: 685b ldr r3, [r3, #4] + 8008936: 2b00 cmp r3, #0 + 8008938: f000 80d4 beq.w 8008ae4 + RadioEvents->TxTimeout( ); + 800893c: 4b15 ldr r3, [pc, #84] @ (8008994 ) + 800893e: 681b ldr r3, [r3, #0] + 8008940: 685b ldr r3, [r3, #4] + 8008942: 4798 blx r3 + break; + 8008944: e0ce b.n 8008ae4 + else if( SUBGRF_GetOperatingMode( ) == MODE_RX ) + 8008946: f000 fe17 bl 8009578 + 800894a: 4603 mov r3, r0 + 800894c: 2b05 cmp r3, #5 + 800894e: f040 80c9 bne.w 8008ae4 + DBG_GPIO_RADIO_RX( RST ); + 8008952: f44f 5180 mov.w r1, #4096 @ 0x1000 + 8008956: 480d ldr r0, [pc, #52] @ (800898c ) + 8008958: f7fe fda9 bl 80074ae + TimerStop( &RxTimeoutTimer ); + 800895c: 480e ldr r0, [pc, #56] @ (8008998 ) + 800895e: f004 f919 bl 800cb94 + SUBGRF_SetStandby( STDBY_RC ); + 8008962: 2000 movs r0, #0 + 8008964: f000 ff54 bl 8009810 + if( ( RadioEvents != NULL ) && ( RadioEvents->RxTimeout != NULL ) ) + 8008968: 4b0a ldr r3, [pc, #40] @ (8008994 ) + 800896a: 681b ldr r3, [r3, #0] + 800896c: 2b00 cmp r3, #0 + 800896e: f000 80b9 beq.w 8008ae4 + 8008972: 4b08 ldr r3, [pc, #32] @ (8008994 ) + 8008974: 681b ldr r3, [r3, #0] + 8008976: 68db ldr r3, [r3, #12] + 8008978: 2b00 cmp r3, #0 + 800897a: f000 80b3 beq.w 8008ae4 + RadioEvents->RxTimeout( ); + 800897e: 4b05 ldr r3, [pc, #20] @ (8008994 ) + 8008980: 681b ldr r3, [r3, #0] + 8008982: 68db ldr r3, [r3, #12] + 8008984: 4798 blx r3 + break; + 8008986: e0ad b.n 8008ae4 + 8008988: 20000290 .word 0x20000290 + 800898c: 48000400 .word 0x48000400 + 8008990: 200002ec .word 0x200002ec + 8008994: 2000028c .word 0x2000028c + 8008998: 20000304 .word 0x20000304 + 800899c: 2000018c .word 0x2000018c + 80089a0: 200002b4 .word 0x200002b4 + 80089a4: 10624dd3 .word 0x10624dd3 + 80089a8: 0800d550 .word 0x0800d550 + MW_LOG( TS_ON, VLEVEL_M, "PRE OK\r\n" ); + 80089ac: 4b54 ldr r3, [pc, #336] @ (8008b00 ) + 80089ae: 2201 movs r2, #1 + 80089b0: 2100 movs r1, #0 + 80089b2: 2002 movs r0, #2 + 80089b4: f004 fae6 bl 800cf84 + if( SubgRf.RxDcPreambleDetectTimeout != 0 ) + 80089b8: 4b52 ldr r3, [pc, #328] @ (8008b04 ) + 80089ba: 6d9b ldr r3, [r3, #88] @ 0x58 + 80089bc: 2b00 cmp r3, #0 + 80089be: f000 8093 beq.w 8008ae8 + Radio.Write( SUBGHZ_RTCPRDR2, ( SubgRf.RxDcPreambleDetectTimeout >> 16 ) & 0xFF ); /*Update Radio RTC Period MSB*/ + 80089c2: 4a51 ldr r2, [pc, #324] @ (8008b08 ) + 80089c4: 4b4f ldr r3, [pc, #316] @ (8008b04 ) + 80089c6: 6d9b ldr r3, [r3, #88] @ 0x58 + 80089c8: 0c1b lsrs r3, r3, #16 + 80089ca: b2db uxtb r3, r3 + 80089cc: 4619 mov r1, r3 + 80089ce: f640 1003 movw r0, #2307 @ 0x903 + 80089d2: 4790 blx r2 + Radio.Write( SUBGHZ_RTCPRDR1, ( SubgRf.RxDcPreambleDetectTimeout >> 8 ) & 0xFF ); /*Update Radio RTC Period MidByte*/ + 80089d4: 4a4c ldr r2, [pc, #304] @ (8008b08 ) + 80089d6: 4b4b ldr r3, [pc, #300] @ (8008b04 ) + 80089d8: 6d9b ldr r3, [r3, #88] @ 0x58 + 80089da: 0a1b lsrs r3, r3, #8 + 80089dc: b2db uxtb r3, r3 + 80089de: 4619 mov r1, r3 + 80089e0: f640 1004 movw r0, #2308 @ 0x904 + 80089e4: 4790 blx r2 + Radio.Write( SUBGHZ_RTCPRDR0, ( SubgRf.RxDcPreambleDetectTimeout ) & 0xFF ); /*Update Radio RTC Period lsb*/ + 80089e6: 4a48 ldr r2, [pc, #288] @ (8008b08 ) + 80089e8: 4b46 ldr r3, [pc, #280] @ (8008b04 ) + 80089ea: 6d9b ldr r3, [r3, #88] @ 0x58 + 80089ec: b2db uxtb r3, r3 + 80089ee: 4619 mov r1, r3 + 80089f0: f640 1005 movw r0, #2309 @ 0x905 + 80089f4: 4790 blx r2 + Radio.Write( SUBGHZ_RTCCTLR, Radio.Read( SUBGHZ_RTCCTLR ) | 0x1 ); /*restart Radio RTC*/ + 80089f6: 4c44 ldr r4, [pc, #272] @ (8008b08 ) + 80089f8: 4b44 ldr r3, [pc, #272] @ (8008b0c ) + 80089fa: f640 1002 movw r0, #2306 @ 0x902 + 80089fe: 4798 blx r3 + 8008a00: 4603 mov r3, r0 + 8008a02: f043 0301 orr.w r3, r3, #1 + 8008a06: b2db uxtb r3, r3 + 8008a08: 4619 mov r1, r3 + 8008a0a: f640 1002 movw r0, #2306 @ 0x902 + 8008a0e: 47a0 blx r4 + SubgRf.RxDcPreambleDetectTimeout = 0; + 8008a10: 4b3c ldr r3, [pc, #240] @ (8008b04 ) + 8008a12: 2200 movs r2, #0 + 8008a14: 659a str r2, [r3, #88] @ 0x58 + SUBGRF_SetDioIrqParams( IRQ_RX_DONE | IRQ_RX_TX_TIMEOUT | IRQ_CRC_ERROR | IRQ_HEADER_ERROR | IRQ_RX_DBG, + 8008a16: 2300 movs r3, #0 + 8008a18: 2200 movs r2, #0 + 8008a1a: f240 2162 movw r1, #610 @ 0x262 + 8008a1e: f240 2062 movw r0, #610 @ 0x262 + 8008a22: f001 f8cf bl 8009bc4 + break; + 8008a26: e05f b.n 8008ae8 + MW_LOG( TS_ON, VLEVEL_M, "SYNC OK\r\n" ); + 8008a28: 4b39 ldr r3, [pc, #228] @ (8008b10 ) + 8008a2a: 2201 movs r2, #1 + 8008a2c: 2100 movs r1, #0 + 8008a2e: 2002 movs r0, #2 + 8008a30: f004 faa8 bl 800cf84 + if( 1UL == RFW_Is_Init( ) ) + 8008a34: f002 f9ec bl 800ae10 + 8008a38: 4603 mov r3, r0 + 8008a3a: 2b01 cmp r3, #1 + 8008a3c: d156 bne.n 8008aec + RFW_ReceivePayload( ); + 8008a3e: f002 fac9 bl 800afd4 + break; + 8008a42: e053 b.n 8008aec + MW_LOG( TS_ON, VLEVEL_M, "HDR OK\r\n" ); + 8008a44: 4b33 ldr r3, [pc, #204] @ (8008b14 ) + 8008a46: 2201 movs r2, #1 + 8008a48: 2100 movs r1, #0 + 8008a4a: 2002 movs r0, #2 + 8008a4c: f004 fa9a bl 800cf84 + break; + 8008a50: e051 b.n 8008af6 + TimerStop( &RxTimeoutTimer ); + 8008a52: 4831 ldr r0, [pc, #196] @ (8008b18 ) + 8008a54: f004 f89e bl 800cb94 + if( SubgRf.RxContinuous == false ) + 8008a58: 4b2a ldr r3, [pc, #168] @ (8008b04 ) + 8008a5a: 785b ldrb r3, [r3, #1] + 8008a5c: f083 0301 eor.w r3, r3, #1 + 8008a60: b2db uxtb r3, r3 + 8008a62: 2b00 cmp r3, #0 + 8008a64: d002 beq.n 8008a6c + SUBGRF_SetStandby( STDBY_RC ); + 8008a66: 2000 movs r0, #0 + 8008a68: f000 fed2 bl 8009810 + if( ( RadioEvents != NULL ) && ( RadioEvents->RxTimeout != NULL ) ) + 8008a6c: 4b2b ldr r3, [pc, #172] @ (8008b1c ) + 8008a6e: 681b ldr r3, [r3, #0] + 8008a70: 2b00 cmp r3, #0 + 8008a72: d03d beq.n 8008af0 + 8008a74: 4b29 ldr r3, [pc, #164] @ (8008b1c ) + 8008a76: 681b ldr r3, [r3, #0] + 8008a78: 68db ldr r3, [r3, #12] + 8008a7a: 2b00 cmp r3, #0 + 8008a7c: d038 beq.n 8008af0 + RadioEvents->RxTimeout( ); + 8008a7e: 4b27 ldr r3, [pc, #156] @ (8008b1c ) + 8008a80: 681b ldr r3, [r3, #0] + 8008a82: 68db ldr r3, [r3, #12] + 8008a84: 4798 blx r3 + MW_LOG( TS_ON, VLEVEL_M, "HDR KO\r\n" ); + 8008a86: 4b26 ldr r3, [pc, #152] @ (8008b20 ) + 8008a88: 2201 movs r2, #1 + 8008a8a: 2100 movs r1, #0 + 8008a8c: 2002 movs r0, #2 + 8008a8e: f004 fa79 bl 800cf84 + break; + 8008a92: e02d b.n 8008af0 + MW_LOG( TS_ON, VLEVEL_M, "IRQ_CRC_ERROR\r\n" ); + 8008a94: 4b23 ldr r3, [pc, #140] @ (8008b24 ) + 8008a96: 2201 movs r2, #1 + 8008a98: 2100 movs r1, #0 + 8008a9a: 2002 movs r0, #2 + 8008a9c: f004 fa72 bl 800cf84 + if( SubgRf.RxContinuous == false ) + 8008aa0: 4b18 ldr r3, [pc, #96] @ (8008b04 ) + 8008aa2: 785b ldrb r3, [r3, #1] + 8008aa4: f083 0301 eor.w r3, r3, #1 + 8008aa8: b2db uxtb r3, r3 + 8008aaa: 2b00 cmp r3, #0 + 8008aac: d002 beq.n 8008ab4 + SUBGRF_SetStandby( STDBY_RC ); + 8008aae: 2000 movs r0, #0 + 8008ab0: f000 feae bl 8009810 + if( ( RadioEvents != NULL ) && ( RadioEvents->RxError ) ) + 8008ab4: 4b19 ldr r3, [pc, #100] @ (8008b1c ) + 8008ab6: 681b ldr r3, [r3, #0] + 8008ab8: 2b00 cmp r3, #0 + 8008aba: d01b beq.n 8008af4 + 8008abc: 4b17 ldr r3, [pc, #92] @ (8008b1c ) + 8008abe: 681b ldr r3, [r3, #0] + 8008ac0: 691b ldr r3, [r3, #16] + 8008ac2: 2b00 cmp r3, #0 + 8008ac4: d016 beq.n 8008af4 + RadioEvents->RxError( ); + 8008ac6: 4b15 ldr r3, [pc, #84] @ (8008b1c ) + 8008ac8: 681b ldr r3, [r3, #0] + 8008aca: 691b ldr r3, [r3, #16] + 8008acc: 4798 blx r3 + break; + 8008ace: e011 b.n 8008af4 + break; + 8008ad0: bf00 nop + 8008ad2: e010 b.n 8008af6 + break; + 8008ad4: bf00 nop + 8008ad6: e00e b.n 8008af6 + break; + 8008ad8: bf00 nop + 8008ada: e00c b.n 8008af6 + break; + 8008adc: bf00 nop + 8008ade: e00a b.n 8008af6 + break; + 8008ae0: bf00 nop + 8008ae2: e008 b.n 8008af6 + break; + 8008ae4: bf00 nop + 8008ae6: e006 b.n 8008af6 + break; + 8008ae8: bf00 nop + 8008aea: e004 b.n 8008af6 + break; + 8008aec: bf00 nop + 8008aee: e002 b.n 8008af6 + break; + 8008af0: bf00 nop + 8008af2: e000 b.n 8008af6 + break; + 8008af4: bf00 nop + } +} + 8008af6: bf00 nop + 8008af8: 3708 adds r7, #8 + 8008afa: 46bd mov sp, r7 + 8008afc: bdb0 pop {r4, r5, r7, pc} + 8008afe: bf00 nop + 8008b00: 0800d564 .word 0x0800d564 + 8008b04: 20000290 .word 0x20000290 + 8008b08: 080084a9 .word 0x080084a9 + 8008b0c: 080084cd .word 0x080084cd + 8008b10: 0800d570 .word 0x0800d570 + 8008b14: 0800d57c .word 0x0800d57c + 8008b18: 20000304 .word 0x20000304 + 8008b1c: 2000028c .word 0x2000028c + 8008b20: 0800d588 .word 0x0800d588 + 8008b24: 0800d594 .word 0x0800d594 + +08008b28 : + +static void RadioTxPrbs( void ) +{ + 8008b28: b580 push {r7, lr} + 8008b2a: af00 add r7, sp, #0 + SUBGRF_SetSwitch( SubgRf.AntSwitchPaSelect, RFSWITCH_TX ); + 8008b2c: 4b09 ldr r3, [pc, #36] @ (8008b54 ) + 8008b2e: f893 3056 ldrb.w r3, [r3, #86] @ 0x56 + 8008b32: 2101 movs r1, #1 + 8008b34: 4618 mov r0, r3 + 8008b36: f001 fcfd bl 800a534 + Radio.Write( SUBGHZ_GPKTCTL1AR, 0x2d ); // sel mode prbs9 instead of preamble + 8008b3a: 4b07 ldr r3, [pc, #28] @ (8008b58 ) + 8008b3c: 212d movs r1, #45 @ 0x2d + 8008b3e: f44f 60d7 mov.w r0, #1720 @ 0x6b8 + 8008b42: 4798 blx r3 + SUBGRF_SetTxInfinitePreamble( ); + 8008b44: f000 ff27 bl 8009996 + SUBGRF_SetTx( 0x0fffff ); + 8008b48: 4804 ldr r0, [pc, #16] @ (8008b5c ) + 8008b4a: f000 fe7d bl 8009848 +} + 8008b4e: bf00 nop + 8008b50: bd80 pop {r7, pc} + 8008b52: bf00 nop + 8008b54: 20000290 .word 0x20000290 + 8008b58: 080084a9 .word 0x080084a9 + 8008b5c: 000fffff .word 0x000fffff + +08008b60 : + +static void RadioTxCw( int8_t power ) +{ + 8008b60: b580 push {r7, lr} + 8008b62: b084 sub sp, #16 + 8008b64: af00 add r7, sp, #0 + 8008b66: 4603 mov r3, r0 + 8008b68: 71fb strb r3, [r7, #7] + uint8_t paselect = SUBGRF_SetRfTxPower( power ); + 8008b6a: f997 3007 ldrsb.w r3, [r7, #7] + 8008b6e: 4618 mov r0, r3 + 8008b70: f001 fd08 bl 800a584 + 8008b74: 4603 mov r3, r0 + 8008b76: 73fb strb r3, [r7, #15] + /* WORKAROUND - Trimming the output voltage power_ldo to 3.3V */ + SUBGRF_WriteRegister(REG_DRV_CTRL, 0x7 << 1); + 8008b78: 210e movs r1, #14 + 8008b7a: f640 101f movw r0, #2335 @ 0x91f + 8008b7e: f001 fbcb bl 800a318 + SUBGRF_SetSwitch( paselect, RFSWITCH_TX ); + 8008b82: 7bfb ldrb r3, [r7, #15] + 8008b84: 2101 movs r1, #1 + 8008b86: 4618 mov r0, r3 + 8008b88: f001 fcd4 bl 800a534 + SUBGRF_SetTxContinuousWave( ); + 8008b8c: f000 fefa bl 8009984 +} + 8008b90: bf00 nop + 8008b92: 3710 adds r7, #16 + 8008b94: 46bd mov sp, r7 + 8008b96: bd80 pop {r7, pc} + +08008b98 : + +#if (RADIO_SIGFOX_ENABLE == 1) +static void payload_integration( uint8_t *outBuffer, uint8_t *inBuffer, uint8_t size ) +{ + 8008b98: b480 push {r7} + 8008b9a: b089 sub sp, #36 @ 0x24 + 8008b9c: af00 add r7, sp, #0 + 8008b9e: 60f8 str r0, [r7, #12] + 8008ba0: 60b9 str r1, [r7, #8] + 8008ba2: 4613 mov r3, r2 + 8008ba4: 71fb strb r3, [r7, #7] + uint8_t prevInt = 0; + 8008ba6: 2300 movs r3, #0 + 8008ba8: 77fb strb r3, [r7, #31] + uint8_t currBit; + uint8_t index_bit; + uint8_t index_byte; + uint8_t index_bit_out; + uint8_t index_byte_out; + int32_t i = 0; + 8008baa: 2300 movs r3, #0 + 8008bac: 61bb str r3, [r7, #24] + + for( i = 0; i < size; i++ ) + 8008bae: 2300 movs r3, #0 + 8008bb0: 61bb str r3, [r7, #24] + 8008bb2: e011 b.n 8008bd8 + { + /* reverse all inputs */ + inBuffer[i] = ~inBuffer[i]; + 8008bb4: 69bb ldr r3, [r7, #24] + 8008bb6: 68ba ldr r2, [r7, #8] + 8008bb8: 4413 add r3, r2 + 8008bba: 781a ldrb r2, [r3, #0] + 8008bbc: 69bb ldr r3, [r7, #24] + 8008bbe: 68b9 ldr r1, [r7, #8] + 8008bc0: 440b add r3, r1 + 8008bc2: 43d2 mvns r2, r2 + 8008bc4: b2d2 uxtb r2, r2 + 8008bc6: 701a strb r2, [r3, #0] + /* init outBuffer */ + outBuffer[i] = 0; + 8008bc8: 69bb ldr r3, [r7, #24] + 8008bca: 68fa ldr r2, [r7, #12] + 8008bcc: 4413 add r3, r2 + 8008bce: 2200 movs r2, #0 + 8008bd0: 701a strb r2, [r3, #0] + for( i = 0; i < size; i++ ) + 8008bd2: 69bb ldr r3, [r7, #24] + 8008bd4: 3301 adds r3, #1 + 8008bd6: 61bb str r3, [r7, #24] + 8008bd8: 79fb ldrb r3, [r7, #7] + 8008bda: 69ba ldr r2, [r7, #24] + 8008bdc: 429a cmp r2, r3 + 8008bde: dbe9 blt.n 8008bb4 + } + + for( i = 0; i < ( size * 8 ); i++ ) + 8008be0: 2300 movs r3, #0 + 8008be2: 61bb str r3, [r7, #24] + 8008be4: e049 b.n 8008c7a + { + /* index to take bit in inBuffer */ + index_bit = 7 - ( i % 8 ); + 8008be6: 69bb ldr r3, [r7, #24] + 8008be8: 425a negs r2, r3 + 8008bea: f003 0307 and.w r3, r3, #7 + 8008bee: f002 0207 and.w r2, r2, #7 + 8008bf2: bf58 it pl + 8008bf4: 4253 negpl r3, r2 + 8008bf6: b2db uxtb r3, r3 + 8008bf8: f1c3 0307 rsb r3, r3, #7 + 8008bfc: 75fb strb r3, [r7, #23] + index_byte = i / 8; + 8008bfe: 69bb ldr r3, [r7, #24] + 8008c00: 2b00 cmp r3, #0 + 8008c02: da00 bge.n 8008c06 + 8008c04: 3307 adds r3, #7 + 8008c06: 10db asrs r3, r3, #3 + 8008c08: 75bb strb r3, [r7, #22] + /* index to place bit in outBuffer is shifted 1 bit right */ + index_bit_out = 7 - ( ( i + 1 ) % 8 ); + 8008c0a: 69bb ldr r3, [r7, #24] + 8008c0c: 3301 adds r3, #1 + 8008c0e: 425a negs r2, r3 + 8008c10: f003 0307 and.w r3, r3, #7 + 8008c14: f002 0207 and.w r2, r2, #7 + 8008c18: bf58 it pl + 8008c1a: 4253 negpl r3, r2 + 8008c1c: b2db uxtb r3, r3 + 8008c1e: f1c3 0307 rsb r3, r3, #7 + 8008c22: 757b strb r3, [r7, #21] + index_byte_out = ( i + 1 ) / 8; + 8008c24: 69bb ldr r3, [r7, #24] + 8008c26: 3301 adds r3, #1 + 8008c28: 2b00 cmp r3, #0 + 8008c2a: da00 bge.n 8008c2e + 8008c2c: 3307 adds r3, #7 + 8008c2e: 10db asrs r3, r3, #3 + 8008c30: 753b strb r3, [r7, #20] + /* extract current bit from input */ + currBit = ( inBuffer[index_byte] >> index_bit ) & 0x01; + 8008c32: 7dbb ldrb r3, [r7, #22] + 8008c34: 68ba ldr r2, [r7, #8] + 8008c36: 4413 add r3, r2 + 8008c38: 781b ldrb r3, [r3, #0] + 8008c3a: 461a mov r2, r3 + 8008c3c: 7dfb ldrb r3, [r7, #23] + 8008c3e: fa42 f303 asr.w r3, r2, r3 + 8008c42: b2db uxtb r3, r3 + 8008c44: f003 0301 and.w r3, r3, #1 + 8008c48: 74fb strb r3, [r7, #19] + /* integration */ + prevInt ^= currBit; + 8008c4a: 7ffa ldrb r2, [r7, #31] + 8008c4c: 7cfb ldrb r3, [r7, #19] + 8008c4e: 4053 eors r3, r2 + 8008c50: 77fb strb r3, [r7, #31] + /* write result integration in output */ + outBuffer[index_byte_out] |= ( prevInt << index_bit_out ); + 8008c52: 7d3b ldrb r3, [r7, #20] + 8008c54: 68fa ldr r2, [r7, #12] + 8008c56: 4413 add r3, r2 + 8008c58: 781b ldrb r3, [r3, #0] + 8008c5a: b25a sxtb r2, r3 + 8008c5c: 7ff9 ldrb r1, [r7, #31] + 8008c5e: 7d7b ldrb r3, [r7, #21] + 8008c60: fa01 f303 lsl.w r3, r1, r3 + 8008c64: b25b sxtb r3, r3 + 8008c66: 4313 orrs r3, r2 + 8008c68: b259 sxtb r1, r3 + 8008c6a: 7d3b ldrb r3, [r7, #20] + 8008c6c: 68fa ldr r2, [r7, #12] + 8008c6e: 4413 add r3, r2 + 8008c70: b2ca uxtb r2, r1 + 8008c72: 701a strb r2, [r3, #0] + for( i = 0; i < ( size * 8 ); i++ ) + 8008c74: 69bb ldr r3, [r7, #24] + 8008c76: 3301 adds r3, #1 + 8008c78: 61bb str r3, [r7, #24] + 8008c7a: 79fb ldrb r3, [r7, #7] + 8008c7c: 00db lsls r3, r3, #3 + 8008c7e: 69ba ldr r2, [r7, #24] + 8008c80: 429a cmp r2, r3 + 8008c82: dbb0 blt.n 8008be6 + } + + outBuffer[size] = ( prevInt << 7 ) | ( prevInt << 6 ) | ( ( ( !prevInt ) & 0x01 ) << 5 ) ; + 8008c84: f997 301f ldrsb.w r3, [r7, #31] + 8008c88: 01db lsls r3, r3, #7 + 8008c8a: b25a sxtb r2, r3 + 8008c8c: f997 301f ldrsb.w r3, [r7, #31] + 8008c90: 019b lsls r3, r3, #6 + 8008c92: b25b sxtb r3, r3 + 8008c94: 4313 orrs r3, r2 + 8008c96: b25b sxtb r3, r3 + 8008c98: 7ffa ldrb r2, [r7, #31] + 8008c9a: 2a00 cmp r2, #0 + 8008c9c: d101 bne.n 8008ca2 + 8008c9e: 2220 movs r2, #32 + 8008ca0: e000 b.n 8008ca4 + 8008ca2: 2200 movs r2, #0 + 8008ca4: 4313 orrs r3, r2 + 8008ca6: b259 sxtb r1, r3 + 8008ca8: 79fb ldrb r3, [r7, #7] + 8008caa: 68fa ldr r2, [r7, #12] + 8008cac: 4413 add r3, r2 + 8008cae: b2ca uxtb r2, r1 + 8008cb0: 701a strb r2, [r3, #0] +} + 8008cb2: bf00 nop + 8008cb4: 3724 adds r7, #36 @ 0x24 + 8008cb6: 46bd mov sp, r7 + 8008cb8: bc80 pop {r7} + 8008cba: 4770 bx lr + +08008cbc : +#endif /*RADIO_SIGFOX_ENABLE == 1*/ + +static int32_t RadioSetRxGenericConfig( GenericModems_t modem, RxConfigGeneric_t *config, uint32_t rxContinuous, + uint32_t symbTimeout ) +{ + 8008cbc: b580 push {r7, lr} + 8008cbe: b08c sub sp, #48 @ 0x30 + 8008cc0: af00 add r7, sp, #0 + 8008cc2: 60b9 str r1, [r7, #8] + 8008cc4: 607a str r2, [r7, #4] + 8008cc6: 603b str r3, [r7, #0] + 8008cc8: 4603 mov r3, r0 + 8008cca: 73fb strb r3, [r7, #15] +#if (RADIO_GENERIC_CONFIG_ENABLE == 1) + int32_t status = 0; + 8008ccc: 2300 movs r3, #0 + 8008cce: 62bb str r3, [r7, #40] @ 0x28 + uint8_t syncword[8] = {0}; + 8008cd0: f107 0320 add.w r3, r7, #32 + 8008cd4: 2200 movs r2, #0 + 8008cd6: 601a str r2, [r3, #0] + 8008cd8: 605a str r2, [r3, #4] + uint8_t MaxPayloadLength; + + RFW_DeInit( ); /* switch Off FwPacketDecoding by default */ + 8008cda: f002 f88d bl 800adf8 + + if( rxContinuous != 0 ) + 8008cde: 687b ldr r3, [r7, #4] + 8008ce0: 2b00 cmp r3, #0 + 8008ce2: d001 beq.n 8008ce8 + { + symbTimeout = 0; + 8008ce4: 2300 movs r3, #0 + 8008ce6: 603b str r3, [r7, #0] + } + SubgRf.RxContinuous = ( rxContinuous == 0 ) ? false : true; + 8008ce8: 687b ldr r3, [r7, #4] + 8008cea: 2b00 cmp r3, #0 + 8008cec: bf14 ite ne + 8008cee: 2301 movne r3, #1 + 8008cf0: 2300 moveq r3, #0 + 8008cf2: b2da uxtb r2, r3 + 8008cf4: 4ba3 ldr r3, [pc, #652] @ (8008f84 ) + 8008cf6: 705a strb r2, [r3, #1] + + switch( modem ) + 8008cf8: 7bfb ldrb r3, [r7, #15] + 8008cfa: 2b00 cmp r3, #0 + 8008cfc: d003 beq.n 8008d06 + 8008cfe: 2b01 cmp r3, #1 + 8008d00: f000 80dc beq.w 8008ebc + + // Timeout Max, Timeout handled directly in SetRx function + SubgRf.RxTimeout = 0xFFFF; + break; + default: + break; + 8008d04: e195 b.n 8009032 + if( ( config->fsk.BitRate == 0 ) || ( config->fsk.PreambleLen == 0 ) ) + 8008d06: 68bb ldr r3, [r7, #8] + 8008d08: 689b ldr r3, [r3, #8] + 8008d0a: 2b00 cmp r3, #0 + 8008d0c: d003 beq.n 8008d16 + 8008d0e: 68bb ldr r3, [r7, #8] + 8008d10: 68db ldr r3, [r3, #12] + 8008d12: 2b00 cmp r3, #0 + 8008d14: d102 bne.n 8008d1c + return -1; + 8008d16: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff + 8008d1a: e18b b.n 8009034 + if( config->fsk.SyncWordLength > 8 ) + 8008d1c: 68bb ldr r3, [r7, #8] + 8008d1e: 7f9b ldrb r3, [r3, #30] + 8008d20: 2b08 cmp r3, #8 + 8008d22: d902 bls.n 8008d2a + return -1; + 8008d24: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff + 8008d28: e184 b.n 8009034 + RADIO_MEMCPY8( syncword, config->fsk.SyncWord, config->fsk.SyncWordLength ); + 8008d2a: 68bb ldr r3, [r7, #8] + 8008d2c: 6919 ldr r1, [r3, #16] + 8008d2e: 68bb ldr r3, [r7, #8] + 8008d30: 7f9b ldrb r3, [r3, #30] + 8008d32: 461a mov r2, r3 + 8008d34: f107 0320 add.w r3, r7, #32 + 8008d38: 4618 mov r0, r3 + 8008d3a: f003 f9d7 bl 800c0ec + SUBGRF_SetStopRxTimerOnPreambleDetect( ( config->fsk.StopTimerOnPreambleDetect == 0 ) ? false : true ); + 8008d3e: 68bb ldr r3, [r7, #8] + 8008d40: 681b ldr r3, [r3, #0] + 8008d42: 2b00 cmp r3, #0 + 8008d44: bf14 ite ne + 8008d46: 2301 movne r3, #1 + 8008d48: 2300 moveq r3, #0 + 8008d4a: b2db uxtb r3, r3 + 8008d4c: 4618 mov r0, r3 + 8008d4e: f000 fe2b bl 80099a8 + SubgRf.ModulationParams.PacketType = PACKET_TYPE_GFSK; + 8008d52: 4b8c ldr r3, [pc, #560] @ (8008f84 ) + 8008d54: 2200 movs r2, #0 + 8008d56: f883 2038 strb.w r2, [r3, #56] @ 0x38 + SubgRf.ModulationParams.Params.Gfsk.BitRate = config->fsk.BitRate; + 8008d5a: 68bb ldr r3, [r7, #8] + 8008d5c: 689b ldr r3, [r3, #8] + 8008d5e: 4a89 ldr r2, [pc, #548] @ (8008f84 ) + 8008d60: 63d3 str r3, [r2, #60] @ 0x3c + SubgRf.ModulationParams.Params.Gfsk.ModulationShaping = ( RadioModShapings_t ) config->fsk.ModulationShaping; + 8008d62: 68bb ldr r3, [r7, #8] + 8008d64: f893 2020 ldrb.w r2, [r3, #32] + 8008d68: 4b86 ldr r3, [pc, #536] @ (8008f84 ) + 8008d6a: f883 2044 strb.w r2, [r3, #68] @ 0x44 + SubgRf.ModulationParams.Params.Gfsk.Bandwidth = SUBGRF_GetFskBandwidthRegValue( config->fsk.Bandwidth ); + 8008d6e: 68bb ldr r3, [r7, #8] + 8008d70: 685b ldr r3, [r3, #4] + 8008d72: 4618 mov r0, r3 + 8008d74: f001 fd04 bl 800a780 + 8008d78: 4603 mov r3, r0 + 8008d7a: 461a mov r2, r3 + 8008d7c: 4b81 ldr r3, [pc, #516] @ (8008f84 ) + 8008d7e: f883 2045 strb.w r2, [r3, #69] @ 0x45 + SubgRf.PacketParams.PacketType = PACKET_TYPE_GFSK; + 8008d82: 4b80 ldr r3, [pc, #512] @ (8008f84 ) + 8008d84: 2200 movs r2, #0 + 8008d86: 739a strb r2, [r3, #14] + SubgRf.PacketParams.Params.Gfsk.PreambleLength = ( config->fsk.PreambleLen ) << 3 ; // convert byte into bit + 8008d88: 68bb ldr r3, [r7, #8] + 8008d8a: 68db ldr r3, [r3, #12] + 8008d8c: b29b uxth r3, r3 + 8008d8e: 00db lsls r3, r3, #3 + 8008d90: b29a uxth r2, r3 + 8008d92: 4b7c ldr r3, [pc, #496] @ (8008f84 ) + 8008d94: 821a strh r2, [r3, #16] + SubgRf.PacketParams.Params.Gfsk.PreambleMinDetect = ( RadioPreambleDetection_t ) config->fsk.PreambleMinDetect; + 8008d96: 68bb ldr r3, [r7, #8] + 8008d98: 7fda ldrb r2, [r3, #31] + 8008d9a: 4b7a ldr r3, [pc, #488] @ (8008f84 ) + 8008d9c: 749a strb r2, [r3, #18] + SubgRf.PacketParams.Params.Gfsk.SyncWordLength = ( config->fsk.SyncWordLength ) << 3; // convert byte into bit + 8008d9e: 68bb ldr r3, [r7, #8] + 8008da0: 7f9b ldrb r3, [r3, #30] + 8008da2: 00db lsls r3, r3, #3 + 8008da4: b2da uxtb r2, r3 + 8008da6: 4b77 ldr r3, [pc, #476] @ (8008f84 ) + 8008da8: 74da strb r2, [r3, #19] + SubgRf.PacketParams.Params.Gfsk.AddrComp = ( RadioAddressComp_t ) config->fsk.AddrComp; + 8008daa: 68bb ldr r3, [r7, #8] + 8008dac: f893 2021 ldrb.w r2, [r3, #33] @ 0x21 + 8008db0: 4b74 ldr r3, [pc, #464] @ (8008f84 ) + 8008db2: 751a strb r2, [r3, #20] + if( config->fsk.LengthMode == RADIO_FSK_PACKET_FIXED_LENGTH ) + 8008db4: 68bb ldr r3, [r7, #8] + 8008db6: f893 3022 ldrb.w r3, [r3, #34] @ 0x22 + 8008dba: 2b00 cmp r3, #0 + 8008dbc: d105 bne.n 8008dca + SubgRf.PacketParams.Params.Gfsk.PayloadLength = config->fsk.MaxPayloadLength; + 8008dbe: 68bb ldr r3, [r7, #8] + 8008dc0: 695b ldr r3, [r3, #20] + 8008dc2: b2da uxtb r2, r3 + 8008dc4: 4b6f ldr r3, [pc, #444] @ (8008f84 ) + 8008dc6: 759a strb r2, [r3, #22] + 8008dc8: e00b b.n 8008de2 + else if( config->fsk.LengthMode == RADIO_FSK_PACKET_2BYTES_LENGTH ) + 8008dca: 68bb ldr r3, [r7, #8] + 8008dcc: f893 3022 ldrb.w r3, [r3, #34] @ 0x22 + 8008dd0: 2b02 cmp r3, #2 + 8008dd2: d103 bne.n 8008ddc + SubgRf.PacketParams.Params.Gfsk.PayloadLength = 0xFF; + 8008dd4: 4b6b ldr r3, [pc, #428] @ (8008f84 ) + 8008dd6: 22ff movs r2, #255 @ 0xff + 8008dd8: 759a strb r2, [r3, #22] + 8008dda: e002 b.n 8008de2 + SubgRf.PacketParams.Params.Gfsk.PayloadLength = 0xFF; + 8008ddc: 4b69 ldr r3, [pc, #420] @ (8008f84 ) + 8008dde: 22ff movs r2, #255 @ 0xff + 8008de0: 759a strb r2, [r3, #22] + if( ( config->fsk.Whitening == RADIO_FSK_DC_IBM_WHITENING ) + 8008de2: 68bb ldr r3, [r7, #8] + 8008de4: f893 3024 ldrb.w r3, [r3, #36] @ 0x24 + 8008de8: 2b02 cmp r3, #2 + 8008dea: d004 beq.n 8008df6 + || ( config->fsk.LengthMode == RADIO_FSK_PACKET_2BYTES_LENGTH ) ) + 8008dec: 68bb ldr r3, [r7, #8] + 8008dee: f893 3022 ldrb.w r3, [r3, #34] @ 0x22 + 8008df2: 2b02 cmp r3, #2 + 8008df4: d12d bne.n 8008e52 + if( ( config->fsk.CrcLength != RADIO_FSK_CRC_2_BYTES_IBM ) && ( config->fsk.CrcLength != RADIO_FSK_CRC_2_BYTES_CCIT ) + 8008df6: 68bb ldr r3, [r7, #8] + 8008df8: f893 3023 ldrb.w r3, [r3, #35] @ 0x23 + 8008dfc: 2bf1 cmp r3, #241 @ 0xf1 + 8008dfe: d00c beq.n 8008e1a + 8008e00: 68bb ldr r3, [r7, #8] + 8008e02: f893 3023 ldrb.w r3, [r3, #35] @ 0x23 + 8008e06: 2bf2 cmp r3, #242 @ 0xf2 + 8008e08: d007 beq.n 8008e1a + && ( config->fsk.CrcLength != RADIO_FSK_CRC_OFF ) ) + 8008e0a: 68bb ldr r3, [r7, #8] + 8008e0c: f893 3023 ldrb.w r3, [r3, #35] @ 0x23 + 8008e10: 2b01 cmp r3, #1 + 8008e12: d002 beq.n 8008e1a + return -1; + 8008e14: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff + 8008e18: e10c b.n 8009034 + ConfigGeneric.rtx = CONFIG_RX; + 8008e1a: 2300 movs r3, #0 + 8008e1c: 773b strb r3, [r7, #28] + ConfigGeneric.RxConfig = config; + 8008e1e: 68bb ldr r3, [r7, #8] + 8008e20: 61bb str r3, [r7, #24] + if( 0UL != RFW_Init( &ConfigGeneric, RadioEvents, &RxTimeoutTimer ) ) + 8008e22: 4b59 ldr r3, [pc, #356] @ (8008f88 ) + 8008e24: 6819 ldr r1, [r3, #0] + 8008e26: f107 0314 add.w r3, r7, #20 + 8008e2a: 4a58 ldr r2, [pc, #352] @ (8008f8c ) + 8008e2c: 4618 mov r0, r3 + 8008e2e: f001 ff49 bl 800acc4 + 8008e32: 4603 mov r3, r0 + 8008e34: 2b00 cmp r3, #0 + 8008e36: d002 beq.n 8008e3e + return -1; + 8008e38: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff + 8008e3c: e0fa b.n 8009034 + SubgRf.PacketParams.Params.Gfsk.DcFree = ( RadioDcFree_t ) RADIO_FSK_DC_FREE_OFF; + 8008e3e: 4b51 ldr r3, [pc, #324] @ (8008f84 ) + 8008e40: 2200 movs r2, #0 + 8008e42: 761a strb r2, [r3, #24] + SubgRf.PacketParams.Params.Gfsk.CrcLength = ( RadioCrcTypes_t ) RADIO_CRC_OFF; + 8008e44: 4b4f ldr r3, [pc, #316] @ (8008f84 ) + 8008e46: 2201 movs r2, #1 + 8008e48: 75da strb r2, [r3, #23] + SubgRf.PacketParams.Params.Gfsk.HeaderType = ( RadioPacketLengthModes_t ) RADIO_PACKET_FIXED_LENGTH; + 8008e4a: 4b4e ldr r3, [pc, #312] @ (8008f84 ) + 8008e4c: 2200 movs r2, #0 + 8008e4e: 755a strb r2, [r3, #21] + { + 8008e50: e00e b.n 8008e70 + SubgRf.PacketParams.Params.Gfsk.CrcLength = ( RadioCrcTypes_t ) config->fsk.CrcLength; + 8008e52: 68bb ldr r3, [r7, #8] + 8008e54: f893 2023 ldrb.w r2, [r3, #35] @ 0x23 + 8008e58: 4b4a ldr r3, [pc, #296] @ (8008f84 ) + 8008e5a: 75da strb r2, [r3, #23] + SubgRf.PacketParams.Params.Gfsk.DcFree = ( RadioDcFree_t ) config->fsk.Whitening; + 8008e5c: 68bb ldr r3, [r7, #8] + 8008e5e: f893 2024 ldrb.w r2, [r3, #36] @ 0x24 + 8008e62: 4b48 ldr r3, [pc, #288] @ (8008f84 ) + 8008e64: 761a strb r2, [r3, #24] + SubgRf.PacketParams.Params.Gfsk.HeaderType = ( RadioPacketLengthModes_t ) config->fsk.LengthMode; + 8008e66: 68bb ldr r3, [r7, #8] + 8008e68: f893 2022 ldrb.w r2, [r3, #34] @ 0x22 + 8008e6c: 4b45 ldr r3, [pc, #276] @ (8008f84 ) + 8008e6e: 755a strb r2, [r3, #21] + RadioStandby( ); + 8008e70: f7ff fa0d bl 800828e + RadioSetModem( MODEM_FSK ); + 8008e74: 2000 movs r0, #0 + 8008e76: f7fe fb9b bl 80075b0 + SUBGRF_SetModulationParams( &SubgRf.ModulationParams ); + 8008e7a: 4845 ldr r0, [pc, #276] @ (8008f90 ) + 8008e7c: f001 f838 bl 8009ef0 + SUBGRF_SetPacketParams( &SubgRf.PacketParams ); + 8008e80: 4844 ldr r0, [pc, #272] @ (8008f94 ) + 8008e82: f001 f903 bl 800a08c + SUBGRF_SetSyncWord( syncword ); + 8008e86: f107 0320 add.w r3, r7, #32 + 8008e8a: 4618 mov r0, r3 + 8008e8c: f000 fbc3 bl 8009616 + SUBGRF_SetWhiteningSeed( config->fsk.whiteSeed ); + 8008e90: 68bb ldr r3, [r7, #8] + 8008e92: 8b9b ldrh r3, [r3, #28] + 8008e94: 4618 mov r0, r3 + 8008e96: f000 fc0d bl 80096b4 + SUBGRF_SetCrcPolynomial( config->fsk.CrcPolynomial ); + 8008e9a: 68bb ldr r3, [r7, #8] + 8008e9c: 8b1b ldrh r3, [r3, #24] + 8008e9e: 4618 mov r0, r3 + 8008ea0: f000 fbe8 bl 8009674 + SubgRf.RxTimeout = ( uint32_t )( ( symbTimeout * 1000 * 8 ) / config->fsk.BitRate ); + 8008ea4: 683b ldr r3, [r7, #0] + 8008ea6: f44f 52fa mov.w r2, #8000 @ 0x1f40 + 8008eaa: fb03 f202 mul.w r2, r3, r2 + 8008eae: 68bb ldr r3, [r7, #8] + 8008eb0: 689b ldr r3, [r3, #8] + 8008eb2: fbb2 f3f3 udiv r3, r2, r3 + 8008eb6: 4a33 ldr r2, [pc, #204] @ (8008f84 ) + 8008eb8: 6093 str r3, [r2, #8] + break; + 8008eba: e0ba b.n 8009032 + if( config->lora.PreambleLen == 0 ) + 8008ebc: 68bb ldr r3, [r7, #8] + 8008ebe: 8e1b ldrh r3, [r3, #48] @ 0x30 + 8008ec0: 2b00 cmp r3, #0 + 8008ec2: d102 bne.n 8008eca + return -1; + 8008ec4: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff + 8008ec8: e0b4 b.n 8009034 + if( config->lora.LengthMode == RADIO_LORA_PACKET_FIXED_LENGTH ) + 8008eca: 68bb ldr r3, [r7, #8] + 8008ecc: f893 3032 ldrb.w r3, [r3, #50] @ 0x32 + 8008ed0: 2b01 cmp r3, #1 + 8008ed2: d105 bne.n 8008ee0 + MaxPayloadLength = config->lora.MaxPayloadLength; + 8008ed4: 68bb ldr r3, [r7, #8] + 8008ed6: f893 3033 ldrb.w r3, [r3, #51] @ 0x33 + 8008eda: f887 302f strb.w r3, [r7, #47] @ 0x2f + 8008ede: e002 b.n 8008ee6 + MaxPayloadLength = 0xFF; + 8008ee0: 23ff movs r3, #255 @ 0xff + 8008ee2: f887 302f strb.w r3, [r7, #47] @ 0x2f + SUBGRF_SetStopRxTimerOnPreambleDetect( ( config->lora.StopTimerOnPreambleDetect == 0 ) ? false : true ); + 8008ee6: 68bb ldr r3, [r7, #8] + 8008ee8: 6a9b ldr r3, [r3, #40] @ 0x28 + 8008eea: 2b00 cmp r3, #0 + 8008eec: bf14 ite ne + 8008eee: 2301 movne r3, #1 + 8008ef0: 2300 moveq r3, #0 + 8008ef2: b2db uxtb r3, r3 + 8008ef4: 4618 mov r0, r3 + 8008ef6: f000 fd57 bl 80099a8 + SUBGRF_SetLoRaSymbNumTimeout( symbTimeout ); + 8008efa: 683b ldr r3, [r7, #0] + 8008efc: b2db uxtb r3, r3 + 8008efe: 4618 mov r0, r3 + 8008f00: f000 fd61 bl 80099c6 + SubgRf.ModulationParams.PacketType = PACKET_TYPE_LORA; + 8008f04: 4b1f ldr r3, [pc, #124] @ (8008f84 ) + 8008f06: 2201 movs r2, #1 + 8008f08: f883 2038 strb.w r2, [r3, #56] @ 0x38 + SubgRf.ModulationParams.Params.LoRa.SpreadingFactor = ( RadioLoRaSpreadingFactors_t ) config->lora.SpreadingFactor; + 8008f0c: 68bb ldr r3, [r7, #8] + 8008f0e: f893 202c ldrb.w r2, [r3, #44] @ 0x2c + 8008f12: 4b1c ldr r3, [pc, #112] @ (8008f84 ) + 8008f14: f883 2050 strb.w r2, [r3, #80] @ 0x50 + SubgRf.ModulationParams.Params.LoRa.Bandwidth = ( RadioLoRaBandwidths_t ) config->lora.Bandwidth; + 8008f18: 68bb ldr r3, [r7, #8] + 8008f1a: f893 202d ldrb.w r2, [r3, #45] @ 0x2d + 8008f1e: 4b19 ldr r3, [pc, #100] @ (8008f84 ) + 8008f20: f883 2051 strb.w r2, [r3, #81] @ 0x51 + SubgRf.ModulationParams.Params.LoRa.CodingRate = ( RadioLoRaCodingRates_t ) config->lora.Coderate; + 8008f24: 68bb ldr r3, [r7, #8] + 8008f26: f893 202e ldrb.w r2, [r3, #46] @ 0x2e + 8008f2a: 4b16 ldr r3, [pc, #88] @ (8008f84 ) + 8008f2c: f883 2052 strb.w r2, [r3, #82] @ 0x52 + switch( config->lora.LowDatarateOptimize ) + 8008f30: 68bb ldr r3, [r7, #8] + 8008f32: f893 302f ldrb.w r3, [r3, #47] @ 0x2f + 8008f36: 2b02 cmp r3, #2 + 8008f38: d010 beq.n 8008f5c + 8008f3a: 2b02 cmp r3, #2 + 8008f3c: dc2c bgt.n 8008f98 + 8008f3e: 2b00 cmp r3, #0 + 8008f40: d002 beq.n 8008f48 + 8008f42: 2b01 cmp r3, #1 + 8008f44: d005 beq.n 8008f52 + break; + 8008f46: e027 b.n 8008f98 + SubgRf.ModulationParams.Params.LoRa.LowDatarateOptimize = 0; + 8008f48: 4b0e ldr r3, [pc, #56] @ (8008f84 ) + 8008f4a: 2200 movs r2, #0 + 8008f4c: f883 2053 strb.w r2, [r3, #83] @ 0x53 + break; + 8008f50: e023 b.n 8008f9a + SubgRf.ModulationParams.Params.LoRa.LowDatarateOptimize = 1; + 8008f52: 4b0c ldr r3, [pc, #48] @ (8008f84 ) + 8008f54: 2201 movs r2, #1 + 8008f56: f883 2053 strb.w r2, [r3, #83] @ 0x53 + break; + 8008f5a: e01e b.n 8008f9a + if( ( config->lora.SpreadingFactor == RADIO_LORA_SF11 ) || ( config->lora.SpreadingFactor == RADIO_LORA_SF12 ) ) + 8008f5c: 68bb ldr r3, [r7, #8] + 8008f5e: f893 302c ldrb.w r3, [r3, #44] @ 0x2c + 8008f62: 2b0b cmp r3, #11 + 8008f64: d004 beq.n 8008f70 + 8008f66: 68bb ldr r3, [r7, #8] + 8008f68: f893 302c ldrb.w r3, [r3, #44] @ 0x2c + 8008f6c: 2b0c cmp r3, #12 + 8008f6e: d104 bne.n 8008f7a + SubgRf.ModulationParams.Params.LoRa.LowDatarateOptimize = 1; + 8008f70: 4b04 ldr r3, [pc, #16] @ (8008f84 ) + 8008f72: 2201 movs r2, #1 + 8008f74: f883 2053 strb.w r2, [r3, #83] @ 0x53 + break; + 8008f78: e00f b.n 8008f9a + SubgRf.ModulationParams.Params.LoRa.LowDatarateOptimize = 0; + 8008f7a: 4b02 ldr r3, [pc, #8] @ (8008f84 ) + 8008f7c: 2200 movs r2, #0 + 8008f7e: f883 2053 strb.w r2, [r3, #83] @ 0x53 + break; + 8008f82: e00a b.n 8008f9a + 8008f84: 20000290 .word 0x20000290 + 8008f88: 2000028c .word 0x2000028c + 8008f8c: 20000304 .word 0x20000304 + 8008f90: 200002c8 .word 0x200002c8 + 8008f94: 2000029e .word 0x2000029e + break; + 8008f98: bf00 nop + SubgRf.PacketParams.PacketType = PACKET_TYPE_LORA; + 8008f9a: 4b28 ldr r3, [pc, #160] @ (800903c ) + 8008f9c: 2201 movs r2, #1 + 8008f9e: 739a strb r2, [r3, #14] + SubgRf.PacketParams.Params.LoRa.PreambleLength = config->lora.PreambleLen; + 8008fa0: 68bb ldr r3, [r7, #8] + 8008fa2: 8e1a ldrh r2, [r3, #48] @ 0x30 + 8008fa4: 4b25 ldr r3, [pc, #148] @ (800903c ) + 8008fa6: 839a strh r2, [r3, #28] + SubgRf.PacketParams.Params.LoRa.HeaderType = ( RadioLoRaPacketLengthsMode_t ) config->lora.LengthMode; + 8008fa8: 68bb ldr r3, [r7, #8] + 8008faa: f893 2032 ldrb.w r2, [r3, #50] @ 0x32 + 8008fae: 4b23 ldr r3, [pc, #140] @ (800903c ) + 8008fb0: 779a strb r2, [r3, #30] + SubgRf.PacketParams.Params.LoRa.PayloadLength = MaxPayloadLength; + 8008fb2: 4a22 ldr r2, [pc, #136] @ (800903c ) + 8008fb4: f897 302f ldrb.w r3, [r7, #47] @ 0x2f + 8008fb8: 77d3 strb r3, [r2, #31] + SubgRf.PacketParams.Params.LoRa.CrcMode = ( RadioLoRaCrcModes_t ) config->lora.CrcMode; + 8008fba: 68bb ldr r3, [r7, #8] + 8008fbc: f893 2034 ldrb.w r2, [r3, #52] @ 0x34 + 8008fc0: 4b1e ldr r3, [pc, #120] @ (800903c ) + 8008fc2: f883 2020 strb.w r2, [r3, #32] + SubgRf.PacketParams.Params.LoRa.InvertIQ = ( RadioLoRaIQModes_t ) config->lora.IqInverted; + 8008fc6: 68bb ldr r3, [r7, #8] + 8008fc8: f893 2035 ldrb.w r2, [r3, #53] @ 0x35 + 8008fcc: 4b1b ldr r3, [pc, #108] @ (800903c ) + 8008fce: f883 2021 strb.w r2, [r3, #33] @ 0x21 + RadioStandby( ); + 8008fd2: f7ff f95c bl 800828e + RadioSetModem( MODEM_LORA ); + 8008fd6: 2001 movs r0, #1 + 8008fd8: f7fe faea bl 80075b0 + SUBGRF_SetModulationParams( &SubgRf.ModulationParams ); + 8008fdc: 4818 ldr r0, [pc, #96] @ (8009040 ) + 8008fde: f000 ff87 bl 8009ef0 + SUBGRF_SetPacketParams( &SubgRf.PacketParams ); + 8008fe2: 4818 ldr r0, [pc, #96] @ (8009044 ) + 8008fe4: f001 f852 bl 800a08c + if( SubgRf.PacketParams.Params.LoRa.InvertIQ == LORA_IQ_INVERTED ) + 8008fe8: 4b14 ldr r3, [pc, #80] @ (800903c ) + 8008fea: f893 3021 ldrb.w r3, [r3, #33] @ 0x21 + 8008fee: 2b01 cmp r3, #1 + 8008ff0: d10d bne.n 800900e + SUBGRF_WriteRegister( SUBGHZ_LIQPOLR, SUBGRF_ReadRegister( SUBGHZ_LIQPOLR ) & ~( 1 << 2 ) ); + 8008ff2: f240 7036 movw r0, #1846 @ 0x736 + 8008ff6: f001 f9b1 bl 800a35c + 8008ffa: 4603 mov r3, r0 + 8008ffc: f023 0304 bic.w r3, r3, #4 + 8009000: b2db uxtb r3, r3 + 8009002: 4619 mov r1, r3 + 8009004: f240 7036 movw r0, #1846 @ 0x736 + 8009008: f001 f986 bl 800a318 + 800900c: e00c b.n 8009028 + SUBGRF_WriteRegister( SUBGHZ_LIQPOLR, SUBGRF_ReadRegister( SUBGHZ_LIQPOLR ) | ( 1 << 2 ) ); + 800900e: f240 7036 movw r0, #1846 @ 0x736 + 8009012: f001 f9a3 bl 800a35c + 8009016: 4603 mov r3, r0 + 8009018: f043 0304 orr.w r3, r3, #4 + 800901c: b2db uxtb r3, r3 + 800901e: 4619 mov r1, r3 + 8009020: f240 7036 movw r0, #1846 @ 0x736 + 8009024: f001 f978 bl 800a318 + SubgRf.RxTimeout = 0xFFFF; + 8009028: 4b04 ldr r3, [pc, #16] @ (800903c ) + 800902a: f64f 72ff movw r2, #65535 @ 0xffff + 800902e: 609a str r2, [r3, #8] + break; + 8009030: bf00 nop + } + return status; + 8009032: 6abb ldr r3, [r7, #40] @ 0x28 +#else /* RADIO_GENERIC_CONFIG_ENABLE == 1*/ + return -1; +#endif /* RADIO_GENERIC_CONFIG_ENABLE == 0*/ +} + 8009034: 4618 mov r0, r3 + 8009036: 3730 adds r7, #48 @ 0x30 + 8009038: 46bd mov sp, r7 + 800903a: bd80 pop {r7, pc} + 800903c: 20000290 .word 0x20000290 + 8009040: 200002c8 .word 0x200002c8 + 8009044: 2000029e .word 0x2000029e + +08009048 : + +static int32_t RadioSetTxGenericConfig( GenericModems_t modem, TxConfigGeneric_t *config, int8_t power, + uint32_t timeout ) +{ + 8009048: b580 push {r7, lr} + 800904a: b08e sub sp, #56 @ 0x38 + 800904c: af00 add r7, sp, #0 + 800904e: 60b9 str r1, [r7, #8] + 8009050: 607b str r3, [r7, #4] + 8009052: 4603 mov r3, r0 + 8009054: 73fb strb r3, [r7, #15] + 8009056: 4613 mov r3, r2 + 8009058: 73bb strb r3, [r7, #14] +#if( RADIO_LR_FHSS_IS_ON == 1 ) + /*disable LrFhss*/ + SubgRf.lr_fhss.is_lr_fhss_on = false; +#endif /* RADIO_LR_FHSS_IS_ON == 1 */ +#if (RADIO_GENERIC_CONFIG_ENABLE == 1) + uint8_t syncword[8] = {0}; + 800905a: f107 032c add.w r3, r7, #44 @ 0x2c + 800905e: 2200 movs r2, #0 + 8009060: 601a str r2, [r3, #0] + 8009062: 605a str r2, [r3, #4] + RadioModems_t radio_modem; + RFW_DeInit( ); /* switch Off FwPacketDecoding by default */ + 8009064: f001 fec8 bl 800adf8 + switch( modem ) + 8009068: 7bfb ldrb r3, [r7, #15] + 800906a: 2b03 cmp r3, #3 + 800906c: f200 8205 bhi.w 800947a + 8009070: a201 add r2, pc, #4 @ (adr r2, 8009078 ) + 8009072: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 8009076: bf00 nop + 8009078: 080091fd .word 0x080091fd + 800907c: 08009345 .word 0x08009345 + 8009080: 0800943d .word 0x0800943d + 8009084: 08009089 .word 0x08009089 + { + case GENERIC_MSK: + if( config->msk.SyncWordLength > 8 ) + 8009088: 68bb ldr r3, [r7, #8] + 800908a: 7c9b ldrb r3, [r3, #18] + 800908c: 2b08 cmp r3, #8 + 800908e: d902 bls.n 8009096 + { + return -1; + 8009090: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff + 8009094: e206 b.n 80094a4 + } + else + { + RADIO_MEMCPY8( syncword, config->msk.SyncWord, config->msk.SyncWordLength ); + 8009096: 68bb ldr r3, [r7, #8] + 8009098: 6899 ldr r1, [r3, #8] + 800909a: 68bb ldr r3, [r7, #8] + 800909c: 7c9b ldrb r3, [r3, #18] + 800909e: 461a mov r2, r3 + 80090a0: f107 032c add.w r3, r7, #44 @ 0x2c + 80090a4: 4618 mov r0, r3 + 80090a6: f003 f821 bl 800c0ec + } + if( ( config->msk.BitRate == 0 ) ) + 80090aa: 68bb ldr r3, [r7, #8] + 80090ac: 681b ldr r3, [r3, #0] + 80090ae: 2b00 cmp r3, #0 + 80090b0: d102 bne.n 80090b8 + { + return -1; + 80090b2: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff + 80090b6: e1f5 b.n 80094a4 + } + else if( config->msk.BitRate <= 10000 ) + 80090b8: 68bb ldr r3, [r7, #8] + 80090ba: 681b ldr r3, [r3, #0] + 80090bc: f242 7210 movw r2, #10000 @ 0x2710 + 80090c0: 4293 cmp r3, r2 + 80090c2: d813 bhi.n 80090ec + { + /*max msk modulator datarate is 10kbps*/ + radio_modem = MODEM_MSK; + 80090c4: 2302 movs r3, #2 + 80090c6: f887 3037 strb.w r3, [r7, #55] @ 0x37 + SubgRf.PacketParams.PacketType = PACKET_TYPE_GMSK; + 80090ca: 4b99 ldr r3, [pc, #612] @ (8009330 ) + 80090cc: 2203 movs r2, #3 + 80090ce: 739a strb r2, [r3, #14] + SubgRf.ModulationParams.PacketType = PACKET_TYPE_GMSK; + 80090d0: 4b97 ldr r3, [pc, #604] @ (8009330 ) + 80090d2: 2203 movs r2, #3 + 80090d4: f883 2038 strb.w r2, [r3, #56] @ 0x38 + SubgRf.ModulationParams.Params.Gfsk.BitRate = config->msk.BitRate; + 80090d8: 68bb ldr r3, [r7, #8] + 80090da: 681b ldr r3, [r3, #0] + 80090dc: 4a94 ldr r2, [pc, #592] @ (8009330 ) + 80090de: 63d3 str r3, [r2, #60] @ 0x3c + SubgRf.ModulationParams.Params.Gfsk.ModulationShaping = ( RadioModShapings_t ) config->msk.ModulationShaping; + 80090e0: 68bb ldr r3, [r7, #8] + 80090e2: 7cda ldrb r2, [r3, #19] + 80090e4: 4b92 ldr r3, [pc, #584] @ (8009330 ) + 80090e6: f883 2044 strb.w r2, [r3, #68] @ 0x44 + 80090ea: e017 b.n 800911c + } + else + { + radio_modem = MODEM_FSK; + 80090ec: 2300 movs r3, #0 + 80090ee: f887 3037 strb.w r3, [r7, #55] @ 0x37 + SubgRf.PacketParams.PacketType = PACKET_TYPE_GFSK; + 80090f2: 4b8f ldr r3, [pc, #572] @ (8009330 ) + 80090f4: 2200 movs r2, #0 + 80090f6: 739a strb r2, [r3, #14] + SubgRf.ModulationParams.PacketType = PACKET_TYPE_GFSK; + 80090f8: 4b8d ldr r3, [pc, #564] @ (8009330 ) + 80090fa: 2200 movs r2, #0 + 80090fc: f883 2038 strb.w r2, [r3, #56] @ 0x38 + SubgRf.ModulationParams.Params.Gfsk.BitRate = config->msk.BitRate; + 8009100: 68bb ldr r3, [r7, #8] + 8009102: 681b ldr r3, [r3, #0] + 8009104: 4a8a ldr r2, [pc, #552] @ (8009330 ) + 8009106: 63d3 str r3, [r2, #60] @ 0x3c + SubgRf.ModulationParams.Params.Gfsk.ModulationShaping = ( RadioModShapings_t ) config->msk.ModulationShaping; + 8009108: 68bb ldr r3, [r7, #8] + 800910a: 7cda ldrb r2, [r3, #19] + 800910c: 4b88 ldr r3, [pc, #544] @ (8009330 ) + 800910e: f883 2044 strb.w r2, [r3, #68] @ 0x44 + /*do msk with gfsk modulator*/ + SubgRf.ModulationParams.Params.Gfsk.Fdev = config->msk.BitRate / 4; + 8009112: 68bb ldr r3, [r7, #8] + 8009114: 681b ldr r3, [r3, #0] + 8009116: 089b lsrs r3, r3, #2 + 8009118: 4a85 ldr r2, [pc, #532] @ (8009330 ) + 800911a: 6413 str r3, [r2, #64] @ 0x40 + } + + SubgRf.PacketParams.Params.Gfsk.PreambleLength = ( config->msk.PreambleLen ) << 3; // convert byte into bit + 800911c: 68bb ldr r3, [r7, #8] + 800911e: 685b ldr r3, [r3, #4] + 8009120: b29b uxth r3, r3 + 8009122: 00db lsls r3, r3, #3 + 8009124: b29a uxth r2, r3 + 8009126: 4b82 ldr r3, [pc, #520] @ (8009330 ) + 8009128: 821a strh r2, [r3, #16] + SubgRf.PacketParams.Params.Gfsk.PreambleMinDetect = RADIO_PREAMBLE_DETECTOR_08_BITS; // don't care in tx + 800912a: 4b81 ldr r3, [pc, #516] @ (8009330 ) + 800912c: 2204 movs r2, #4 + 800912e: 749a strb r2, [r3, #18] + SubgRf.PacketParams.Params.Gfsk.SyncWordLength = ( config->msk.SyncWordLength ) << 3; // convert byte into bit + 8009130: 68bb ldr r3, [r7, #8] + 8009132: 7c9b ldrb r3, [r3, #18] + 8009134: 00db lsls r3, r3, #3 + 8009136: b2da uxtb r2, r3 + 8009138: 4b7d ldr r3, [pc, #500] @ (8009330 ) + 800913a: 74da strb r2, [r3, #19] + SubgRf.PacketParams.Params.Gfsk.AddrComp = RADIO_ADDRESSCOMP_FILT_OFF; // don't care in tx + 800913c: 4b7c ldr r3, [pc, #496] @ (8009330 ) + 800913e: 2200 movs r2, #0 + 8009140: 751a strb r2, [r3, #20] + + if( ( config->msk.Whitening == RADIO_FSK_DC_IBM_WHITENING ) + 8009142: 68bb ldr r3, [r7, #8] + 8009144: 7d9b ldrb r3, [r3, #22] + 8009146: 2b02 cmp r3, #2 + 8009148: d003 beq.n 8009152 + || ( config->msk.HeaderType == RADIO_FSK_PACKET_2BYTES_LENGTH ) ) + 800914a: 68bb ldr r3, [r7, #8] + 800914c: 7d1b ldrb r3, [r3, #20] + 800914e: 2b02 cmp r3, #2 + 8009150: d12b bne.n 80091aa + { + /* Supports only RADIO_FSK_CRC_2_BYTES_IBM or RADIO_FSK_CRC_2_BYTES_CCIT */ + if( ( config->msk.CrcLength != RADIO_FSK_CRC_2_BYTES_IBM ) && ( config->msk.CrcLength != RADIO_FSK_CRC_2_BYTES_CCIT ) + 8009152: 68bb ldr r3, [r7, #8] + 8009154: 7d5b ldrb r3, [r3, #21] + 8009156: 2bf1 cmp r3, #241 @ 0xf1 + 8009158: d00a beq.n 8009170 + 800915a: 68bb ldr r3, [r7, #8] + 800915c: 7d5b ldrb r3, [r3, #21] + 800915e: 2bf2 cmp r3, #242 @ 0xf2 + 8009160: d006 beq.n 8009170 + && ( config->msk.CrcLength != RADIO_FSK_CRC_OFF ) ) + 8009162: 68bb ldr r3, [r7, #8] + 8009164: 7d5b ldrb r3, [r3, #21] + 8009166: 2b01 cmp r3, #1 + 8009168: d002 beq.n 8009170 + { + return -1; + 800916a: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff + 800916e: e199 b.n 80094a4 + } + ConfigGeneric_t ConfigGeneric; + /*msk and fsk are union, no need for copy as fsk/msk struct are on same address*/ + ConfigGeneric.TxConfig = config; + 8009170: 68bb ldr r3, [r7, #8] + 8009172: 623b str r3, [r7, #32] + ConfigGeneric.rtx = CONFIG_TX; + 8009174: 2301 movs r3, #1 + 8009176: f887 3028 strb.w r3, [r7, #40] @ 0x28 + if( 0UL != RFW_Init( &ConfigGeneric, RadioEvents, &TxTimeoutTimer ) ) + 800917a: 4b6e ldr r3, [pc, #440] @ (8009334 ) + 800917c: 6819 ldr r1, [r3, #0] + 800917e: f107 0320 add.w r3, r7, #32 + 8009182: 4a6d ldr r2, [pc, #436] @ (8009338 ) + 8009184: 4618 mov r0, r3 + 8009186: f001 fd9d bl 800acc4 + 800918a: 4603 mov r3, r0 + 800918c: 2b00 cmp r3, #0 + 800918e: d002 beq.n 8009196 + { + return -1; + 8009190: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff + 8009194: e186 b.n 80094a4 + } + /* whitening off, will be processed by FW, switch off built-in radio whitening */ + SubgRf.PacketParams.Params.Gfsk.DcFree = ( RadioDcFree_t ) RADIO_FSK_DC_FREE_OFF; + 8009196: 4b66 ldr r3, [pc, #408] @ (8009330 ) + 8009198: 2200 movs r2, #0 + 800919a: 761a strb r2, [r3, #24] + /* Crc processed by FW, switch off built-in radio Crc */ + SubgRf.PacketParams.Params.Gfsk.CrcLength = ( RadioCrcTypes_t ) RADIO_CRC_OFF; + 800919c: 4b64 ldr r3, [pc, #400] @ (8009330 ) + 800919e: 2201 movs r2, #1 + 80091a0: 75da strb r2, [r3, #23] + /* length contained in Tx, but will be processed by FW after de-whitening */ + SubgRf.PacketParams.Params.Gfsk.HeaderType = ( RadioPacketLengthModes_t ) RADIO_PACKET_FIXED_LENGTH; + 80091a2: 4b63 ldr r3, [pc, #396] @ (8009330 ) + 80091a4: 2200 movs r2, #0 + 80091a6: 755a strb r2, [r3, #21] + { + 80091a8: e00b b.n 80091c2 + } + else + { + SubgRf.PacketParams.Params.Gfsk.CrcLength = ( RadioCrcTypes_t ) config->msk.CrcLength; + 80091aa: 68bb ldr r3, [r7, #8] + 80091ac: 7d5a ldrb r2, [r3, #21] + 80091ae: 4b60 ldr r3, [pc, #384] @ (8009330 ) + 80091b0: 75da strb r2, [r3, #23] + SubgRf.PacketParams.Params.Gfsk.DcFree = ( RadioDcFree_t ) config->msk.Whitening; + 80091b2: 68bb ldr r3, [r7, #8] + 80091b4: 7d9a ldrb r2, [r3, #22] + 80091b6: 4b5e ldr r3, [pc, #376] @ (8009330 ) + 80091b8: 761a strb r2, [r3, #24] + SubgRf.PacketParams.Params.Gfsk.HeaderType = ( RadioPacketLengthModes_t ) config->msk.HeaderType; + 80091ba: 68bb ldr r3, [r7, #8] + 80091bc: 7d1a ldrb r2, [r3, #20] + 80091be: 4b5c ldr r3, [pc, #368] @ (8009330 ) + 80091c0: 755a strb r2, [r3, #21] + } + + RadioStandby( ); + 80091c2: f7ff f864 bl 800828e + RadioSetModem( radio_modem ); + 80091c6: f897 3037 ldrb.w r3, [r7, #55] @ 0x37 + 80091ca: 4618 mov r0, r3 + 80091cc: f7fe f9f0 bl 80075b0 + + SUBGRF_SetModulationParams( &SubgRf.ModulationParams ); + 80091d0: 485a ldr r0, [pc, #360] @ (800933c ) + 80091d2: f000 fe8d bl 8009ef0 + SUBGRF_SetPacketParams( &SubgRf.PacketParams ); + 80091d6: 485a ldr r0, [pc, #360] @ (8009340 ) + 80091d8: f000 ff58 bl 800a08c + SUBGRF_SetSyncWord( syncword ); + 80091dc: f107 032c add.w r3, r7, #44 @ 0x2c + 80091e0: 4618 mov r0, r3 + 80091e2: f000 fa18 bl 8009616 + SUBGRF_SetWhiteningSeed( config->msk.whiteSeed ); + 80091e6: 68bb ldr r3, [r7, #8] + 80091e8: 8a1b ldrh r3, [r3, #16] + 80091ea: 4618 mov r0, r3 + 80091ec: f000 fa62 bl 80096b4 + SUBGRF_SetCrcPolynomial( config->msk.CrcPolynomial ); + 80091f0: 68bb ldr r3, [r7, #8] + 80091f2: 899b ldrh r3, [r3, #12] + 80091f4: 4618 mov r0, r3 + 80091f6: f000 fa3d bl 8009674 + break; + 80091fa: e13f b.n 800947c + case GENERIC_FSK: + if( config->fsk.BitRate == 0 ) + 80091fc: 68bb ldr r3, [r7, #8] + 80091fe: 681b ldr r3, [r3, #0] + 8009200: 2b00 cmp r3, #0 + 8009202: d102 bne.n 800920a + { + return -1; + 8009204: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff + 8009208: e14c b.n 80094a4 + } + if( config->fsk.SyncWordLength > 8 ) + 800920a: 68bb ldr r3, [r7, #8] + 800920c: 7c9b ldrb r3, [r3, #18] + 800920e: 2b08 cmp r3, #8 + 8009210: d902 bls.n 8009218 + { + return -1; + 8009212: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff + 8009216: e145 b.n 80094a4 + } + else + { + RADIO_MEMCPY8( syncword, config->fsk.SyncWord, config->fsk.SyncWordLength ); + 8009218: 68bb ldr r3, [r7, #8] + 800921a: 6899 ldr r1, [r3, #8] + 800921c: 68bb ldr r3, [r7, #8] + 800921e: 7c9b ldrb r3, [r3, #18] + 8009220: 461a mov r2, r3 + 8009222: f107 032c add.w r3, r7, #44 @ 0x2c + 8009226: 4618 mov r0, r3 + 8009228: f002 ff60 bl 800c0ec + } + SubgRf.ModulationParams.PacketType = PACKET_TYPE_GFSK; + 800922c: 4b40 ldr r3, [pc, #256] @ (8009330 ) + 800922e: 2200 movs r2, #0 + 8009230: f883 2038 strb.w r2, [r3, #56] @ 0x38 + SubgRf.ModulationParams.Params.Gfsk.BitRate = config->fsk.BitRate; + 8009234: 68bb ldr r3, [r7, #8] + 8009236: 681b ldr r3, [r3, #0] + 8009238: 4a3d ldr r2, [pc, #244] @ (8009330 ) + 800923a: 63d3 str r3, [r2, #60] @ 0x3c + SubgRf.ModulationParams.Params.Gfsk.ModulationShaping = ( RadioModShapings_t ) config->fsk.ModulationShaping; + 800923c: 68bb ldr r3, [r7, #8] + 800923e: 7cda ldrb r2, [r3, #19] + 8009240: 4b3b ldr r3, [pc, #236] @ (8009330 ) + 8009242: f883 2044 strb.w r2, [r3, #68] @ 0x44 + SubgRf.ModulationParams.Params.Gfsk.Fdev = config->fsk.FrequencyDeviation; + 8009246: 68bb ldr r3, [r7, #8] + 8009248: 699b ldr r3, [r3, #24] + 800924a: 4a39 ldr r2, [pc, #228] @ (8009330 ) + 800924c: 6413 str r3, [r2, #64] @ 0x40 + + SubgRf.PacketParams.PacketType = PACKET_TYPE_GFSK; + 800924e: 4b38 ldr r3, [pc, #224] @ (8009330 ) + 8009250: 2200 movs r2, #0 + 8009252: 739a strb r2, [r3, #14] + SubgRf.PacketParams.Params.Gfsk.PreambleLength = ( config->fsk.PreambleLen ) << 3; // convert byte into bit + 8009254: 68bb ldr r3, [r7, #8] + 8009256: 685b ldr r3, [r3, #4] + 8009258: b29b uxth r3, r3 + 800925a: 00db lsls r3, r3, #3 + 800925c: b29a uxth r2, r3 + 800925e: 4b34 ldr r3, [pc, #208] @ (8009330 ) + 8009260: 821a strh r2, [r3, #16] + SubgRf.PacketParams.Params.Gfsk.PreambleMinDetect = RADIO_PREAMBLE_DETECTOR_08_BITS; // don't care in tx + 8009262: 4b33 ldr r3, [pc, #204] @ (8009330 ) + 8009264: 2204 movs r2, #4 + 8009266: 749a strb r2, [r3, #18] + SubgRf.PacketParams.Params.Gfsk.SyncWordLength = ( config->fsk.SyncWordLength ) << 3; // convert byte into bit + 8009268: 68bb ldr r3, [r7, #8] + 800926a: 7c9b ldrb r3, [r3, #18] + 800926c: 00db lsls r3, r3, #3 + 800926e: b2da uxtb r2, r3 + 8009270: 4b2f ldr r3, [pc, #188] @ (8009330 ) + 8009272: 74da strb r2, [r3, #19] + SubgRf.PacketParams.Params.Gfsk.AddrComp = RADIO_ADDRESSCOMP_FILT_OFF; // don't care in tx + 8009274: 4b2e ldr r3, [pc, #184] @ (8009330 ) + 8009276: 2200 movs r2, #0 + 8009278: 751a strb r2, [r3, #20] + + if( ( config->fsk.Whitening == RADIO_FSK_DC_IBM_WHITENING ) + 800927a: 68bb ldr r3, [r7, #8] + 800927c: 7d9b ldrb r3, [r3, #22] + 800927e: 2b02 cmp r3, #2 + 8009280: d003 beq.n 800928a + || ( config->fsk.HeaderType == RADIO_FSK_PACKET_2BYTES_LENGTH ) ) + 8009282: 68bb ldr r3, [r7, #8] + 8009284: 7d1b ldrb r3, [r3, #20] + 8009286: 2b02 cmp r3, #2 + 8009288: d12a bne.n 80092e0 + { + /* Supports only RADIO_FSK_CRC_2_BYTES_IBM or RADIO_FSK_CRC_2_BYTES_CCIT */ + if( ( config->fsk.CrcLength != RADIO_FSK_CRC_2_BYTES_IBM ) && ( config->fsk.CrcLength != RADIO_FSK_CRC_2_BYTES_CCIT ) + 800928a: 68bb ldr r3, [r7, #8] + 800928c: 7d5b ldrb r3, [r3, #21] + 800928e: 2bf1 cmp r3, #241 @ 0xf1 + 8009290: d00a beq.n 80092a8 + 8009292: 68bb ldr r3, [r7, #8] + 8009294: 7d5b ldrb r3, [r3, #21] + 8009296: 2bf2 cmp r3, #242 @ 0xf2 + 8009298: d006 beq.n 80092a8 + && ( config->fsk.CrcLength != RADIO_FSK_CRC_OFF ) ) + 800929a: 68bb ldr r3, [r7, #8] + 800929c: 7d5b ldrb r3, [r3, #21] + 800929e: 2b01 cmp r3, #1 + 80092a0: d002 beq.n 80092a8 + { + return -1; + 80092a2: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff + 80092a6: e0fd b.n 80094a4 + } + ConfigGeneric_t ConfigGeneric; + ConfigGeneric.rtx = CONFIG_TX; + 80092a8: 2301 movs r3, #1 + 80092aa: 773b strb r3, [r7, #28] + ConfigGeneric.TxConfig = config; + 80092ac: 68bb ldr r3, [r7, #8] + 80092ae: 617b str r3, [r7, #20] + if( 0UL != RFW_Init( &ConfigGeneric, RadioEvents, &TxTimeoutTimer ) ) + 80092b0: 4b20 ldr r3, [pc, #128] @ (8009334 ) + 80092b2: 6819 ldr r1, [r3, #0] + 80092b4: f107 0314 add.w r3, r7, #20 + 80092b8: 4a1f ldr r2, [pc, #124] @ (8009338 ) + 80092ba: 4618 mov r0, r3 + 80092bc: f001 fd02 bl 800acc4 + 80092c0: 4603 mov r3, r0 + 80092c2: 2b00 cmp r3, #0 + 80092c4: d002 beq.n 80092cc + { + return -1; + 80092c6: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff + 80092ca: e0eb b.n 80094a4 + } + /* whitening off, will be processed by FW, switch off built-in radio whitening */ + SubgRf.PacketParams.Params.Gfsk.DcFree = ( RadioDcFree_t ) RADIO_FSK_DC_FREE_OFF; + 80092cc: 4b18 ldr r3, [pc, #96] @ (8009330 ) + 80092ce: 2200 movs r2, #0 + 80092d0: 761a strb r2, [r3, #24] + /* Crc processed by FW, switch off built-in radio Crc */ + SubgRf.PacketParams.Params.Gfsk.CrcLength = ( RadioCrcTypes_t ) RADIO_CRC_OFF; + 80092d2: 4b17 ldr r3, [pc, #92] @ (8009330 ) + 80092d4: 2201 movs r2, #1 + 80092d6: 75da strb r2, [r3, #23] + /* length contained in Tx, but will be processed by FW after de-whitening */ + SubgRf.PacketParams.Params.Gfsk.HeaderType = ( RadioPacketLengthModes_t ) RADIO_PACKET_FIXED_LENGTH; + 80092d8: 4b15 ldr r3, [pc, #84] @ (8009330 ) + 80092da: 2200 movs r2, #0 + 80092dc: 755a strb r2, [r3, #21] + { + 80092de: e00b b.n 80092f8 + } + else + { + SubgRf.PacketParams.Params.Gfsk.CrcLength = ( RadioCrcTypes_t ) config->fsk.CrcLength; + 80092e0: 68bb ldr r3, [r7, #8] + 80092e2: 7d5a ldrb r2, [r3, #21] + 80092e4: 4b12 ldr r3, [pc, #72] @ (8009330 ) + 80092e6: 75da strb r2, [r3, #23] + SubgRf.PacketParams.Params.Gfsk.DcFree = ( RadioDcFree_t ) config->fsk.Whitening; + 80092e8: 68bb ldr r3, [r7, #8] + 80092ea: 7d9a ldrb r2, [r3, #22] + 80092ec: 4b10 ldr r3, [pc, #64] @ (8009330 ) + 80092ee: 761a strb r2, [r3, #24] + SubgRf.PacketParams.Params.Gfsk.HeaderType = ( RadioPacketLengthModes_t ) config->fsk.HeaderType; + 80092f0: 68bb ldr r3, [r7, #8] + 80092f2: 7d1a ldrb r2, [r3, #20] + 80092f4: 4b0e ldr r3, [pc, #56] @ (8009330 ) + 80092f6: 755a strb r2, [r3, #21] + } + + RadioStandby( ); + 80092f8: f7fe ffc9 bl 800828e + RadioSetModem( MODEM_FSK ); + 80092fc: 2000 movs r0, #0 + 80092fe: f7fe f957 bl 80075b0 + SUBGRF_SetModulationParams( &SubgRf.ModulationParams ); + 8009302: 480e ldr r0, [pc, #56] @ (800933c ) + 8009304: f000 fdf4 bl 8009ef0 + SUBGRF_SetPacketParams( &SubgRf.PacketParams ); + 8009308: 480d ldr r0, [pc, #52] @ (8009340 ) + 800930a: f000 febf bl 800a08c + SUBGRF_SetSyncWord( syncword ); + 800930e: f107 032c add.w r3, r7, #44 @ 0x2c + 8009312: 4618 mov r0, r3 + 8009314: f000 f97f bl 8009616 + SUBGRF_SetWhiteningSeed( config->fsk.whiteSeed ); + 8009318: 68bb ldr r3, [r7, #8] + 800931a: 8a1b ldrh r3, [r3, #16] + 800931c: 4618 mov r0, r3 + 800931e: f000 f9c9 bl 80096b4 + SUBGRF_SetCrcPolynomial( config->fsk.CrcPolynomial ); + 8009322: 68bb ldr r3, [r7, #8] + 8009324: 899b ldrh r3, [r3, #12] + 8009326: 4618 mov r0, r3 + 8009328: f000 f9a4 bl 8009674 + break; + 800932c: e0a6 b.n 800947c + 800932e: bf00 nop + 8009330: 20000290 .word 0x20000290 + 8009334: 2000028c .word 0x2000028c + 8009338: 200002ec .word 0x200002ec + 800933c: 200002c8 .word 0x200002c8 + 8009340: 2000029e .word 0x2000029e + case GENERIC_LORA: + SubgRf.ModulationParams.PacketType = PACKET_TYPE_LORA; + 8009344: 4b59 ldr r3, [pc, #356] @ (80094ac ) + 8009346: 2201 movs r2, #1 + 8009348: f883 2038 strb.w r2, [r3, #56] @ 0x38 + SubgRf.ModulationParams.Params.LoRa.SpreadingFactor = ( RadioLoRaSpreadingFactors_t ) config->lora.SpreadingFactor; + 800934c: 68bb ldr r3, [r7, #8] + 800934e: 781a ldrb r2, [r3, #0] + 8009350: 4b56 ldr r3, [pc, #344] @ (80094ac ) + 8009352: f883 2050 strb.w r2, [r3, #80] @ 0x50 + SubgRf.ModulationParams.Params.LoRa.Bandwidth = ( RadioLoRaBandwidths_t ) config->lora.Bandwidth; + 8009356: 68bb ldr r3, [r7, #8] + 8009358: 785a ldrb r2, [r3, #1] + 800935a: 4b54 ldr r3, [pc, #336] @ (80094ac ) + 800935c: f883 2051 strb.w r2, [r3, #81] @ 0x51 + SubgRf.ModulationParams.Params.LoRa.CodingRate = ( RadioLoRaCodingRates_t ) config->lora.Coderate; + 8009360: 68bb ldr r3, [r7, #8] + 8009362: 789a ldrb r2, [r3, #2] + 8009364: 4b51 ldr r3, [pc, #324] @ (80094ac ) + 8009366: f883 2052 strb.w r2, [r3, #82] @ 0x52 + switch( config->lora.LowDatarateOptimize ) + 800936a: 68bb ldr r3, [r7, #8] + 800936c: 78db ldrb r3, [r3, #3] + 800936e: 2b02 cmp r3, #2 + 8009370: d010 beq.n 8009394 + 8009372: 2b02 cmp r3, #2 + 8009374: dc20 bgt.n 80093b8 + 8009376: 2b00 cmp r3, #0 + 8009378: d002 beq.n 8009380 + 800937a: 2b01 cmp r3, #1 + 800937c: d005 beq.n 800938a + { + SubgRf.ModulationParams.Params.LoRa.LowDatarateOptimize = 0; + } + break; + default: + break; + 800937e: e01b b.n 80093b8 + SubgRf.ModulationParams.Params.LoRa.LowDatarateOptimize = 0; + 8009380: 4b4a ldr r3, [pc, #296] @ (80094ac ) + 8009382: 2200 movs r2, #0 + 8009384: f883 2053 strb.w r2, [r3, #83] @ 0x53 + break; + 8009388: e017 b.n 80093ba + SubgRf.ModulationParams.Params.LoRa.LowDatarateOptimize = 1; + 800938a: 4b48 ldr r3, [pc, #288] @ (80094ac ) + 800938c: 2201 movs r2, #1 + 800938e: f883 2053 strb.w r2, [r3, #83] @ 0x53 + break; + 8009392: e012 b.n 80093ba + if( ( config->lora.SpreadingFactor == RADIO_LORA_SF11 ) || ( config->lora.SpreadingFactor == RADIO_LORA_SF12 ) ) + 8009394: 68bb ldr r3, [r7, #8] + 8009396: 781b ldrb r3, [r3, #0] + 8009398: 2b0b cmp r3, #11 + 800939a: d003 beq.n 80093a4 + 800939c: 68bb ldr r3, [r7, #8] + 800939e: 781b ldrb r3, [r3, #0] + 80093a0: 2b0c cmp r3, #12 + 80093a2: d104 bne.n 80093ae + SubgRf.ModulationParams.Params.LoRa.LowDatarateOptimize = 1; + 80093a4: 4b41 ldr r3, [pc, #260] @ (80094ac ) + 80093a6: 2201 movs r2, #1 + 80093a8: f883 2053 strb.w r2, [r3, #83] @ 0x53 + break; + 80093ac: e005 b.n 80093ba + SubgRf.ModulationParams.Params.LoRa.LowDatarateOptimize = 0; + 80093ae: 4b3f ldr r3, [pc, #252] @ (80094ac ) + 80093b0: 2200 movs r2, #0 + 80093b2: f883 2053 strb.w r2, [r3, #83] @ 0x53 + break; + 80093b6: e000 b.n 80093ba + break; + 80093b8: bf00 nop + } + + SubgRf.PacketParams.PacketType = PACKET_TYPE_LORA; + 80093ba: 4b3c ldr r3, [pc, #240] @ (80094ac ) + 80093bc: 2201 movs r2, #1 + 80093be: 739a strb r2, [r3, #14] + SubgRf.PacketParams.Params.LoRa.PreambleLength = config->lora.PreambleLen; + 80093c0: 68bb ldr r3, [r7, #8] + 80093c2: 889a ldrh r2, [r3, #4] + 80093c4: 4b39 ldr r3, [pc, #228] @ (80094ac ) + 80093c6: 839a strh r2, [r3, #28] + SubgRf.PacketParams.Params.LoRa.HeaderType = ( RadioLoRaPacketLengthsMode_t ) config->lora.LengthMode; + 80093c8: 68bb ldr r3, [r7, #8] + 80093ca: 799a ldrb r2, [r3, #6] + 80093cc: 4b37 ldr r3, [pc, #220] @ (80094ac ) + 80093ce: 779a strb r2, [r3, #30] + SubgRf.PacketParams.Params.LoRa.CrcMode = ( RadioLoRaCrcModes_t ) config->lora.CrcMode; + 80093d0: 68bb ldr r3, [r7, #8] + 80093d2: 79da ldrb r2, [r3, #7] + 80093d4: 4b35 ldr r3, [pc, #212] @ (80094ac ) + 80093d6: f883 2020 strb.w r2, [r3, #32] + SubgRf.PacketParams.Params.LoRa.InvertIQ = ( RadioLoRaIQModes_t ) config->lora.IqInverted; + 80093da: 68bb ldr r3, [r7, #8] + 80093dc: 7a1a ldrb r2, [r3, #8] + 80093de: 4b33 ldr r3, [pc, #204] @ (80094ac ) + 80093e0: f883 2021 strb.w r2, [r3, #33] @ 0x21 + + RadioStandby( ); + 80093e4: f7fe ff53 bl 800828e + RadioSetModem( MODEM_LORA ); + 80093e8: 2001 movs r0, #1 + 80093ea: f7fe f8e1 bl 80075b0 + SUBGRF_SetModulationParams( &SubgRf.ModulationParams ); + 80093ee: 4830 ldr r0, [pc, #192] @ (80094b0 ) + 80093f0: f000 fd7e bl 8009ef0 + SUBGRF_SetPacketParams( &SubgRf.PacketParams ); + 80093f4: 482f ldr r0, [pc, #188] @ (80094b4 ) + 80093f6: f000 fe49 bl 800a08c + + /* WORKAROUND - Modulation Quality with 500 kHz LoRa Bandwidth, see STM32WL Erratasheet */ + if( SubgRf.ModulationParams.Params.LoRa.Bandwidth == LORA_BW_500 ) + 80093fa: 4b2c ldr r3, [pc, #176] @ (80094ac ) + 80093fc: f893 3051 ldrb.w r3, [r3, #81] @ 0x51 + 8009400: 2b06 cmp r3, #6 + 8009402: d10d bne.n 8009420 + { + // RegTxModulation = @address 0x0889 + SUBGRF_WriteRegister( SUBGHZ_SDCFG0R, SUBGRF_ReadRegister( SUBGHZ_SDCFG0R ) & ~( 1 << 2 ) ); + 8009404: f640 0089 movw r0, #2185 @ 0x889 + 8009408: f000 ffa8 bl 800a35c + 800940c: 4603 mov r3, r0 + 800940e: f023 0304 bic.w r3, r3, #4 + 8009412: b2db uxtb r3, r3 + 8009414: 4619 mov r1, r3 + 8009416: f640 0089 movw r0, #2185 @ 0x889 + 800941a: f000 ff7d bl 800a318 + { + // RegTxModulation = @address 0x0889 + SUBGRF_WriteRegister( SUBGHZ_SDCFG0R, SUBGRF_ReadRegister( SUBGHZ_SDCFG0R ) | ( 1 << 2 ) ); + } + /* WORKAROUND END */ + break; + 800941e: e02d b.n 800947c + SUBGRF_WriteRegister( SUBGHZ_SDCFG0R, SUBGRF_ReadRegister( SUBGHZ_SDCFG0R ) | ( 1 << 2 ) ); + 8009420: f640 0089 movw r0, #2185 @ 0x889 + 8009424: f000 ff9a bl 800a35c + 8009428: 4603 mov r3, r0 + 800942a: f043 0304 orr.w r3, r3, #4 + 800942e: b2db uxtb r3, r3 + 8009430: 4619 mov r1, r3 + 8009432: f640 0089 movw r0, #2185 @ 0x889 + 8009436: f000 ff6f bl 800a318 + break; + 800943a: e01f b.n 800947c + case GENERIC_BPSK: + if( ( config->bpsk.BitRate == 0 ) || ( config->bpsk.BitRate > 1000 ) ) + 800943c: 68bb ldr r3, [r7, #8] + 800943e: 681b ldr r3, [r3, #0] + 8009440: 2b00 cmp r3, #0 + 8009442: d004 beq.n 800944e + 8009444: 68bb ldr r3, [r7, #8] + 8009446: 681b ldr r3, [r3, #0] + 8009448: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 + 800944c: d902 bls.n 8009454 + { + return -1; + 800944e: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff + 8009452: e027 b.n 80094a4 + } + RadioSetModem( MODEM_BPSK ); + 8009454: 2003 movs r0, #3 + 8009456: f7fe f8ab bl 80075b0 + SubgRf.ModulationParams.PacketType = PACKET_TYPE_BPSK; + 800945a: 4b14 ldr r3, [pc, #80] @ (80094ac ) + 800945c: 2202 movs r2, #2 + 800945e: f883 2038 strb.w r2, [r3, #56] @ 0x38 + SubgRf.ModulationParams.Params.Bpsk.BitRate = config->bpsk.BitRate; + 8009462: 68bb ldr r3, [r7, #8] + 8009464: 681b ldr r3, [r3, #0] + 8009466: 4a11 ldr r2, [pc, #68] @ (80094ac ) + 8009468: 6493 str r3, [r2, #72] @ 0x48 + SubgRf.ModulationParams.Params.Bpsk.ModulationShaping = MOD_SHAPING_DBPSK; + 800946a: 4b10 ldr r3, [pc, #64] @ (80094ac ) + 800946c: 2216 movs r2, #22 + 800946e: f883 204c strb.w r2, [r3, #76] @ 0x4c + SUBGRF_SetModulationParams( &SubgRf.ModulationParams ); + 8009472: 480f ldr r0, [pc, #60] @ (80094b0 ) + 8009474: f000 fd3c bl 8009ef0 + break; + 8009478: e000 b.n 800947c + default: + break; + 800947a: bf00 nop + } + + SubgRf.AntSwitchPaSelect = SUBGRF_SetRfTxPower( power ); + 800947c: f997 300e ldrsb.w r3, [r7, #14] + 8009480: 4618 mov r0, r3 + 8009482: f001 f87f bl 800a584 + 8009486: 4603 mov r3, r0 + 8009488: 461a mov r2, r3 + 800948a: 4b08 ldr r3, [pc, #32] @ (80094ac ) + 800948c: f883 2056 strb.w r2, [r3, #86] @ 0x56 + RFW_SetAntSwitch( SubgRf.AntSwitchPaSelect ); + 8009490: 4b06 ldr r3, [pc, #24] @ (80094ac ) + 8009492: f893 3056 ldrb.w r3, [r3, #86] @ 0x56 + 8009496: 4618 mov r0, r3 + 8009498: f001 fcce bl 800ae38 + SubgRf.TxTimeout = timeout; + 800949c: 4a03 ldr r2, [pc, #12] @ (80094ac ) + 800949e: 687b ldr r3, [r7, #4] + 80094a0: 6053 str r3, [r2, #4] + return 0; + 80094a2: 2300 movs r3, #0 +#else /* RADIO_GENERIC_CONFIG_ENABLE == 1*/ + return -1; +#endif /* RADIO_GENERIC_CONFIG_ENABLE == 0*/ +} + 80094a4: 4618 mov r0, r3 + 80094a6: 3738 adds r7, #56 @ 0x38 + 80094a8: 46bd mov sp, r7 + 80094aa: bd80 pop {r7, pc} + 80094ac: 20000290 .word 0x20000290 + 80094b0: 200002c8 .word 0x200002c8 + 80094b4: 2000029e .word 0x2000029e + +080094b8 : + return ( prbs31_val - 1 ) % ( max ); +} +#endif /* RADIO_LR_FHSS_IS_ON == 1 */ + +static radio_status_t RadioLrFhssSetCfg( const radio_lr_fhss_cfg_params_t *cfg_params ) +{ + 80094b8: b480 push {r7} + 80094ba: b085 sub sp, #20 + 80094bc: af00 add r7, sp, #0 + 80094be: 6078 str r0, [r7, #4] + radio_status_t status = RADIO_STATUS_UNSUPPORTED_FEATURE; + 80094c0: 2301 movs r3, #1 + 80094c2: 73fb strb r3, [r7, #15] + { + return status; + } + SubgRf.lr_fhss.is_lr_fhss_on = true; +#endif /* RADIO_LR_FHSS_IS_ON == 1 */ + return status; + 80094c4: 7bfb ldrb r3, [r7, #15] +} + 80094c6: 4618 mov r0, r3 + 80094c8: 3714 adds r7, #20 + 80094ca: 46bd mov sp, r7 + 80094cc: bc80 pop {r7} + 80094ce: 4770 bx lr + +080094d0 : + +static radio_status_t RadioLrFhssGetTimeOnAirInMs( const radio_lr_fhss_time_on_air_params_t *params, + uint32_t *time_on_air_in_ms ) +{ + 80094d0: b480 push {r7} + 80094d2: b083 sub sp, #12 + 80094d4: af00 add r7, sp, #0 + 80094d6: 6078 str r0, [r7, #4] + 80094d8: 6039 str r1, [r7, #0] + *time_on_air_in_ms = lr_fhss_get_time_on_air_in_ms( ¶ms->radio_lr_fhss_params.lr_fhss_params, + params->pld_len_in_bytes ); + + return RADIO_STATUS_OK; +#else + return RADIO_STATUS_UNSUPPORTED_FEATURE; + 80094da: 2301 movs r3, #1 +#endif /* RADIO_LR_FHSS_IS_ON */ + 80094dc: 4618 mov r0, r3 + 80094de: 370c adds r7, #12 + 80094e0: 46bd mov sp, r7 + 80094e2: bc80 pop {r7} + 80094e4: 4770 bx lr + ... + +080094e8 : + */ +static DioIrqHandler RadioOnDioIrqCb; + +/* Exported functions ---------------------------------------------------------*/ +void SUBGRF_Init( DioIrqHandler dioIrq ) +{ + 80094e8: b580 push {r7, lr} + 80094ea: b084 sub sp, #16 + 80094ec: af00 add r7, sp, #0 + 80094ee: 6078 str r0, [r7, #4] + if ( dioIrq != NULL) + 80094f0: 687b ldr r3, [r7, #4] + 80094f2: 2b00 cmp r3, #0 + 80094f4: d002 beq.n 80094fc + { + RadioOnDioIrqCb = dioIrq; + 80094f6: 4a1d ldr r2, [pc, #116] @ (800956c ) + 80094f8: 687b ldr r3, [r7, #4] + 80094fa: 6013 str r3, [r2, #0] + } + + RADIO_INIT(); + 80094fc: f7f7 fa8e bl 8000a1c + + /* set default SMPS current drive to default*/ + Radio_SMPS_Set(SMPS_DRIVE_SETTING_DEFAULT); + 8009500: 2002 movs r0, #2 + 8009502: f001 f91b bl 800a73c + + ImageCalibrated = false; + 8009506: 4b1a ldr r3, [pc, #104] @ (8009570 ) + 8009508: 2200 movs r2, #0 + 800950a: 701a strb r2, [r3, #0] + + SUBGRF_SetStandby( STDBY_RC ); + 800950c: 2000 movs r0, #0 + 800950e: f000 f97f bl 8009810 + + // Initialize TCXO control + if (1U == RBI_IsTCXO() ) + 8009512: f002 fd29 bl 800bf68 + 8009516: 4603 mov r3, r0 + 8009518: 2b01 cmp r3, #1 + 800951a: d10e bne.n 800953a + { + SUBGRF_SetTcxoMode( TCXO_CTRL_VOLTAGE, RF_WAKEUP_TIME << 6 );// 100 ms + 800951c: 2140 movs r1, #64 @ 0x40 + 800951e: 2001 movs r0, #1 + 8009520: f000 fb8a bl 8009c38 + SUBGRF_WriteRegister( REG_XTA_TRIM, 0x00 ); + 8009524: 2100 movs r1, #0 + 8009526: f640 1011 movw r0, #2321 @ 0x911 + 800952a: f000 fef5 bl 800a318 + + /*enable calibration for cut1.1 and later*/ + CalibrationParams_t calibParam; + calibParam.Value = 0x7F; + 800952e: 237f movs r3, #127 @ 0x7f + 8009530: 733b strb r3, [r7, #12] + SUBGRF_Calibrate( calibParam ); + 8009532: 7b38 ldrb r0, [r7, #12] + 8009534: f000 fa8d bl 8009a52 + 8009538: e009 b.n 800954e + } + else + { + SUBGRF_WriteRegister( REG_XTA_TRIM, XTAL_DEFAULT_CAP_VALUE ); + 800953a: 2120 movs r1, #32 + 800953c: f640 1011 movw r0, #2321 @ 0x911 + 8009540: f000 feea bl 800a318 + SUBGRF_WriteRegister( REG_XTB_TRIM, XTAL_DEFAULT_CAP_VALUE ); + 8009544: 2120 movs r1, #32 + 8009546: f640 1012 movw r0, #2322 @ 0x912 + 800954a: f000 fee5 bl 800a318 + } + + /* WORKAROUND - Trimming the output voltage power_ldo to 3.3V */ + SUBGRF_WriteRegister(REG_DRV_CTRL, 0x7 << 1); + 800954e: 210e movs r1, #14 + 8009550: f640 101f movw r0, #2335 @ 0x91f + 8009554: f000 fee0 bl 800a318 + + /* Init RF Switch */ + RBI_Init(); + 8009558: f002 fcea bl 800bf30 + + OperatingMode = MODE_STDBY_RC; + 800955c: 4b05 ldr r3, [pc, #20] @ (8009574 ) + 800955e: 2201 movs r2, #1 + 8009560: 701a strb r2, [r3, #0] +} + 8009562: bf00 nop + 8009564: 3710 adds r7, #16 + 8009566: 46bd mov sp, r7 + 8009568: bd80 pop {r7, pc} + 800956a: bf00 nop + 800956c: 20000328 .word 0x20000328 + 8009570: 20000324 .word 0x20000324 + 8009574: 2000031c .word 0x2000031c + +08009578 : + +RadioOperatingModes_t SUBGRF_GetOperatingMode( void ) +{ + 8009578: b480 push {r7} + 800957a: af00 add r7, sp, #0 + return OperatingMode; + 800957c: 4b02 ldr r3, [pc, #8] @ (8009588 ) + 800957e: 781b ldrb r3, [r3, #0] +} + 8009580: 4618 mov r0, r3 + 8009582: 46bd mov sp, r7 + 8009584: bc80 pop {r7} + 8009586: 4770 bx lr + 8009588: 2000031c .word 0x2000031c + +0800958c : + +void SUBGRF_SetPayload( uint8_t *payload, uint8_t size ) +{ + 800958c: b580 push {r7, lr} + 800958e: b082 sub sp, #8 + 8009590: af00 add r7, sp, #0 + 8009592: 6078 str r0, [r7, #4] + 8009594: 460b mov r3, r1 + 8009596: 70fb strb r3, [r7, #3] + SUBGRF_WriteBuffer( 0x00, payload, size ); + 8009598: 78fb ldrb r3, [r7, #3] + 800959a: 461a mov r2, r3 + 800959c: 6879 ldr r1, [r7, #4] + 800959e: 2000 movs r0, #0 + 80095a0: f000 ff40 bl 800a424 +} + 80095a4: bf00 nop + 80095a6: 3708 adds r7, #8 + 80095a8: 46bd mov sp, r7 + 80095aa: bd80 pop {r7, pc} + +080095ac : + +uint8_t SUBGRF_GetPayload( uint8_t *buffer, uint8_t *size, uint8_t maxSize ) +{ + 80095ac: b580 push {r7, lr} + 80095ae: b086 sub sp, #24 + 80095b0: af00 add r7, sp, #0 + 80095b2: 60f8 str r0, [r7, #12] + 80095b4: 60b9 str r1, [r7, #8] + 80095b6: 4613 mov r3, r2 + 80095b8: 71fb strb r3, [r7, #7] + uint8_t offset = 0; + 80095ba: 2300 movs r3, #0 + 80095bc: 75fb strb r3, [r7, #23] + + SUBGRF_GetRxBufferStatus( size, &offset ); + 80095be: f107 0317 add.w r3, r7, #23 + 80095c2: 4619 mov r1, r3 + 80095c4: 68b8 ldr r0, [r7, #8] + 80095c6: f000 fe29 bl 800a21c + if( *size > maxSize ) + 80095ca: 68bb ldr r3, [r7, #8] + 80095cc: 781b ldrb r3, [r3, #0] + 80095ce: 79fa ldrb r2, [r7, #7] + 80095d0: 429a cmp r2, r3 + 80095d2: d201 bcs.n 80095d8 + { + return 1; + 80095d4: 2301 movs r3, #1 + 80095d6: e007 b.n 80095e8 + } + SUBGRF_ReadBuffer( offset, buffer, *size ); + 80095d8: 7df8 ldrb r0, [r7, #23] + 80095da: 68bb ldr r3, [r7, #8] + 80095dc: 781b ldrb r3, [r3, #0] + 80095de: 461a mov r2, r3 + 80095e0: 68f9 ldr r1, [r7, #12] + 80095e2: f000 ff41 bl 800a468 + + return 0; + 80095e6: 2300 movs r3, #0 +} + 80095e8: 4618 mov r0, r3 + 80095ea: 3718 adds r7, #24 + 80095ec: 46bd mov sp, r7 + 80095ee: bd80 pop {r7, pc} + +080095f0 : + +void SUBGRF_SendPayload( uint8_t *payload, uint8_t size, uint32_t timeout) +{ + 80095f0: b580 push {r7, lr} + 80095f2: b084 sub sp, #16 + 80095f4: af00 add r7, sp, #0 + 80095f6: 60f8 str r0, [r7, #12] + 80095f8: 460b mov r3, r1 + 80095fa: 607a str r2, [r7, #4] + 80095fc: 72fb strb r3, [r7, #11] + SUBGRF_SetPayload( payload, size ); + 80095fe: 7afb ldrb r3, [r7, #11] + 8009600: 4619 mov r1, r3 + 8009602: 68f8 ldr r0, [r7, #12] + 8009604: f7ff ffc2 bl 800958c + SUBGRF_SetTx( timeout ); + 8009608: 6878 ldr r0, [r7, #4] + 800960a: f000 f91d bl 8009848 +} + 800960e: bf00 nop + 8009610: 3710 adds r7, #16 + 8009612: 46bd mov sp, r7 + 8009614: bd80 pop {r7, pc} + +08009616 : + +uint8_t SUBGRF_SetSyncWord( uint8_t *syncWord ) +{ + 8009616: b580 push {r7, lr} + 8009618: b082 sub sp, #8 + 800961a: af00 add r7, sp, #0 + 800961c: 6078 str r0, [r7, #4] + SUBGRF_WriteRegisters( REG_LR_SYNCWORDBASEADDRESS, syncWord, 8 ); + 800961e: 2208 movs r2, #8 + 8009620: 6879 ldr r1, [r7, #4] + 8009622: f44f 60d8 mov.w r0, #1728 @ 0x6c0 + 8009626: f000 feb9 bl 800a39c + return 0; + 800962a: 2300 movs r3, #0 +} + 800962c: 4618 mov r0, r3 + 800962e: 3708 adds r7, #8 + 8009630: 46bd mov sp, r7 + 8009632: bd80 pop {r7, pc} + +08009634 : + +void SUBGRF_SetCrcSeed( uint16_t seed ) +{ + 8009634: b580 push {r7, lr} + 8009636: b084 sub sp, #16 + 8009638: af00 add r7, sp, #0 + 800963a: 4603 mov r3, r0 + 800963c: 80fb strh r3, [r7, #6] + uint8_t buf[2]; + + buf[0] = ( uint8_t )( ( seed >> 8 ) & 0xFF ); + 800963e: 88fb ldrh r3, [r7, #6] + 8009640: 0a1b lsrs r3, r3, #8 + 8009642: b29b uxth r3, r3 + 8009644: b2db uxtb r3, r3 + 8009646: 733b strb r3, [r7, #12] + buf[1] = ( uint8_t )( seed & 0xFF ); + 8009648: 88fb ldrh r3, [r7, #6] + 800964a: b2db uxtb r3, r3 + 800964c: 737b strb r3, [r7, #13] + + switch( SUBGRF_GetPacketType( ) ) + 800964e: f000 fb77 bl 8009d40 + 8009652: 4603 mov r3, r0 + 8009654: 2b00 cmp r3, #0 + 8009656: d108 bne.n 800966a + { + case PACKET_TYPE_GFSK: + SUBGRF_WriteRegisters( REG_LR_CRCSEEDBASEADDR, buf, 2 ); + 8009658: f107 030c add.w r3, r7, #12 + 800965c: 2202 movs r2, #2 + 800965e: 4619 mov r1, r3 + 8009660: f240 60bc movw r0, #1724 @ 0x6bc + 8009664: f000 fe9a bl 800a39c + break; + 8009668: e000 b.n 800966c + + default: + break; + 800966a: bf00 nop + } +} + 800966c: bf00 nop + 800966e: 3710 adds r7, #16 + 8009670: 46bd mov sp, r7 + 8009672: bd80 pop {r7, pc} + +08009674 : + +void SUBGRF_SetCrcPolynomial( uint16_t polynomial ) +{ + 8009674: b580 push {r7, lr} + 8009676: b084 sub sp, #16 + 8009678: af00 add r7, sp, #0 + 800967a: 4603 mov r3, r0 + 800967c: 80fb strh r3, [r7, #6] + uint8_t buf[2]; + + buf[0] = ( uint8_t )( ( polynomial >> 8 ) & 0xFF ); + 800967e: 88fb ldrh r3, [r7, #6] + 8009680: 0a1b lsrs r3, r3, #8 + 8009682: b29b uxth r3, r3 + 8009684: b2db uxtb r3, r3 + 8009686: 733b strb r3, [r7, #12] + buf[1] = ( uint8_t )( polynomial & 0xFF ); + 8009688: 88fb ldrh r3, [r7, #6] + 800968a: b2db uxtb r3, r3 + 800968c: 737b strb r3, [r7, #13] + + switch( SUBGRF_GetPacketType( ) ) + 800968e: f000 fb57 bl 8009d40 + 8009692: 4603 mov r3, r0 + 8009694: 2b00 cmp r3, #0 + 8009696: d108 bne.n 80096aa + { + case PACKET_TYPE_GFSK: + SUBGRF_WriteRegisters( REG_LR_CRCPOLYBASEADDR, buf, 2 ); + 8009698: f107 030c add.w r3, r7, #12 + 800969c: 2202 movs r2, #2 + 800969e: 4619 mov r1, r3 + 80096a0: f240 60be movw r0, #1726 @ 0x6be + 80096a4: f000 fe7a bl 800a39c + break; + 80096a8: e000 b.n 80096ac + + default: + break; + 80096aa: bf00 nop + } +} + 80096ac: bf00 nop + 80096ae: 3710 adds r7, #16 + 80096b0: 46bd mov sp, r7 + 80096b2: bd80 pop {r7, pc} + +080096b4 : + +void SUBGRF_SetWhiteningSeed( uint16_t seed ) +{ + 80096b4: b580 push {r7, lr} + 80096b6: b084 sub sp, #16 + 80096b8: af00 add r7, sp, #0 + 80096ba: 4603 mov r3, r0 + 80096bc: 80fb strh r3, [r7, #6] + uint8_t regValue = 0; + 80096be: 2300 movs r3, #0 + 80096c0: 73fb strb r3, [r7, #15] + + switch( SUBGRF_GetPacketType( ) ) + 80096c2: f000 fb3d bl 8009d40 + 80096c6: 4603 mov r3, r0 + 80096c8: 2b00 cmp r3, #0 + 80096ca: d121 bne.n 8009710 + { + case PACKET_TYPE_GFSK: + regValue = SUBGRF_ReadRegister( REG_LR_WHITSEEDBASEADDR_MSB ) & 0xFE; + 80096cc: f44f 60d7 mov.w r0, #1720 @ 0x6b8 + 80096d0: f000 fe44 bl 800a35c + 80096d4: 4603 mov r3, r0 + 80096d6: f023 0301 bic.w r3, r3, #1 + 80096da: 73fb strb r3, [r7, #15] + regValue = ( ( seed >> 8 ) & 0x01 ) | regValue; + 80096dc: 88fb ldrh r3, [r7, #6] + 80096de: 0a1b lsrs r3, r3, #8 + 80096e0: b29b uxth r3, r3 + 80096e2: b25b sxtb r3, r3 + 80096e4: f003 0301 and.w r3, r3, #1 + 80096e8: b25a sxtb r2, r3 + 80096ea: f997 300f ldrsb.w r3, [r7, #15] + 80096ee: 4313 orrs r3, r2 + 80096f0: b25b sxtb r3, r3 + 80096f2: 73fb strb r3, [r7, #15] + SUBGRF_WriteRegister( REG_LR_WHITSEEDBASEADDR_MSB, regValue ); // only 1 bit. + 80096f4: 7bfb ldrb r3, [r7, #15] + 80096f6: 4619 mov r1, r3 + 80096f8: f44f 60d7 mov.w r0, #1720 @ 0x6b8 + 80096fc: f000 fe0c bl 800a318 + SUBGRF_WriteRegister( REG_LR_WHITSEEDBASEADDR_LSB, (uint8_t)seed ); + 8009700: 88fb ldrh r3, [r7, #6] + 8009702: b2db uxtb r3, r3 + 8009704: 4619 mov r1, r3 + 8009706: f240 60b9 movw r0, #1721 @ 0x6b9 + 800970a: f000 fe05 bl 800a318 + break; + 800970e: e000 b.n 8009712 + + default: + break; + 8009710: bf00 nop + } +} + 8009712: bf00 nop + 8009714: 3710 adds r7, #16 + 8009716: 46bd mov sp, r7 + 8009718: bd80 pop {r7, pc} + +0800971a : + +uint32_t SUBGRF_GetRandom( void ) +{ + 800971a: b580 push {r7, lr} + 800971c: b082 sub sp, #8 + 800971e: af00 add r7, sp, #0 + uint32_t number = 0; + 8009720: 2300 movs r3, #0 + 8009722: 603b str r3, [r7, #0] + uint8_t regAnaLna = 0; + 8009724: 2300 movs r3, #0 + 8009726: 71fb strb r3, [r7, #7] + uint8_t regAnaMixer = 0; + 8009728: 2300 movs r3, #0 + 800972a: 71bb strb r3, [r7, #6] + + regAnaLna = SUBGRF_ReadRegister( REG_ANA_LNA ); + 800972c: f640 00e2 movw r0, #2274 @ 0x8e2 + 8009730: f000 fe14 bl 800a35c + 8009734: 4603 mov r3, r0 + 8009736: 71fb strb r3, [r7, #7] + SUBGRF_WriteRegister( REG_ANA_LNA, regAnaLna & ~( 1 << 0 ) ); + 8009738: 79fb ldrb r3, [r7, #7] + 800973a: f023 0301 bic.w r3, r3, #1 + 800973e: b2db uxtb r3, r3 + 8009740: 4619 mov r1, r3 + 8009742: f640 00e2 movw r0, #2274 @ 0x8e2 + 8009746: f000 fde7 bl 800a318 + + regAnaMixer = SUBGRF_ReadRegister( REG_ANA_MIXER ); + 800974a: f640 00e5 movw r0, #2277 @ 0x8e5 + 800974e: f000 fe05 bl 800a35c + 8009752: 4603 mov r3, r0 + 8009754: 71bb strb r3, [r7, #6] + SUBGRF_WriteRegister( REG_ANA_MIXER, regAnaMixer & ~( 1 << 7 ) ); + 8009756: 79bb ldrb r3, [r7, #6] + 8009758: f003 037f and.w r3, r3, #127 @ 0x7f + 800975c: b2db uxtb r3, r3 + 800975e: 4619 mov r1, r3 + 8009760: f640 00e5 movw r0, #2277 @ 0x8e5 + 8009764: f000 fdd8 bl 800a318 + + // Set radio in continuous reception + SUBGRF_SetRx( 0xFFFFFF ); // Rx Continuous + 8009768: f06f 407f mvn.w r0, #4278190080 @ 0xff000000 + 800976c: f000 f88c bl 8009888 + + SUBGRF_ReadRegisters( RANDOM_NUMBER_GENERATORBASEADDR, ( uint8_t* )&number, 4 ); + 8009770: 463b mov r3, r7 + 8009772: 2204 movs r2, #4 + 8009774: 4619 mov r1, r3 + 8009776: f640 0019 movw r0, #2073 @ 0x819 + 800977a: f000 fe31 bl 800a3e0 + + SUBGRF_SetStandby( STDBY_RC ); + 800977e: 2000 movs r0, #0 + 8009780: f000 f846 bl 8009810 + + SUBGRF_WriteRegister( REG_ANA_LNA, regAnaLna ); + 8009784: 79fb ldrb r3, [r7, #7] + 8009786: 4619 mov r1, r3 + 8009788: f640 00e2 movw r0, #2274 @ 0x8e2 + 800978c: f000 fdc4 bl 800a318 + SUBGRF_WriteRegister( REG_ANA_MIXER, regAnaMixer ); + 8009790: 79bb ldrb r3, [r7, #6] + 8009792: 4619 mov r1, r3 + 8009794: f640 00e5 movw r0, #2277 @ 0x8e5 + 8009798: f000 fdbe bl 800a318 + + return number; + 800979c: 683b ldr r3, [r7, #0] +} + 800979e: 4618 mov r0, r3 + 80097a0: 3708 adds r7, #8 + 80097a2: 46bd mov sp, r7 + 80097a4: bd80 pop {r7, pc} + ... + +080097a8 : + +void SUBGRF_SetSleep( SleepParams_t sleepConfig ) +{ + 80097a8: b580 push {r7, lr} + 80097aa: b084 sub sp, #16 + 80097ac: af00 add r7, sp, #0 + 80097ae: 7138 strb r0, [r7, #4] + /* switch the antenna OFF by SW */ + RBI_ConfigRFSwitch(RBI_SWITCH_OFF); + 80097b0: 2000 movs r0, #0 + 80097b2: f002 fbc4 bl 800bf3e + + Radio_SMPS_Set(SMPS_DRIVE_SETTING_DEFAULT); + 80097b6: 2002 movs r0, #2 + 80097b8: f000 ffc0 bl 800a73c + + uint8_t value = ( ( ( uint8_t )sleepConfig.Fields.WarmStart << 2 ) | + 80097bc: 793b ldrb r3, [r7, #4] + 80097be: f3c3 0380 ubfx r3, r3, #2, #1 + 80097c2: b2db uxtb r3, r3 + 80097c4: b25b sxtb r3, r3 + 80097c6: 009b lsls r3, r3, #2 + 80097c8: b25a sxtb r2, r3 + ( ( uint8_t )sleepConfig.Fields.Reset << 1 ) | + 80097ca: 793b ldrb r3, [r7, #4] + 80097cc: f3c3 0340 ubfx r3, r3, #1, #1 + 80097d0: b2db uxtb r3, r3 + uint8_t value = ( ( ( uint8_t )sleepConfig.Fields.WarmStart << 2 ) | + 80097d2: b25b sxtb r3, r3 + 80097d4: 005b lsls r3, r3, #1 + 80097d6: b25b sxtb r3, r3 + 80097d8: 4313 orrs r3, r2 + 80097da: b25a sxtb r2, r3 + ( ( uint8_t )sleepConfig.Fields.WakeUpRTC ) ); + 80097dc: 793b ldrb r3, [r7, #4] + 80097de: f3c3 0300 ubfx r3, r3, #0, #1 + 80097e2: b2db uxtb r3, r3 + 80097e4: b25b sxtb r3, r3 + ( ( uint8_t )sleepConfig.Fields.Reset << 1 ) | + 80097e6: 4313 orrs r3, r2 + 80097e8: b25b sxtb r3, r3 + 80097ea: b2db uxtb r3, r3 + uint8_t value = ( ( ( uint8_t )sleepConfig.Fields.WarmStart << 2 ) | + 80097ec: 73fb strb r3, [r7, #15] + SUBGRF_WriteCommand( RADIO_SET_SLEEP, &value, 1 ); + 80097ee: f107 030f add.w r3, r7, #15 + 80097f2: 2201 movs r2, #1 + 80097f4: 4619 mov r1, r3 + 80097f6: 2084 movs r0, #132 @ 0x84 + 80097f8: f000 fe58 bl 800a4ac + OperatingMode = MODE_SLEEP; + 80097fc: 4b03 ldr r3, [pc, #12] @ (800980c ) + 80097fe: 2200 movs r2, #0 + 8009800: 701a strb r2, [r3, #0] +} + 8009802: bf00 nop + 8009804: 3710 adds r7, #16 + 8009806: 46bd mov sp, r7 + 8009808: bd80 pop {r7, pc} + 800980a: bf00 nop + 800980c: 2000031c .word 0x2000031c + +08009810 : + +void SUBGRF_SetStandby( RadioStandbyModes_t standbyConfig ) +{ + 8009810: b580 push {r7, lr} + 8009812: b082 sub sp, #8 + 8009814: af00 add r7, sp, #0 + 8009816: 4603 mov r3, r0 + 8009818: 71fb strb r3, [r7, #7] + SUBGRF_WriteCommand( RADIO_SET_STANDBY, ( uint8_t* )&standbyConfig, 1 ); + 800981a: 1dfb adds r3, r7, #7 + 800981c: 2201 movs r2, #1 + 800981e: 4619 mov r1, r3 + 8009820: 2080 movs r0, #128 @ 0x80 + 8009822: f000 fe43 bl 800a4ac + if( standbyConfig == STDBY_RC ) + 8009826: 79fb ldrb r3, [r7, #7] + 8009828: 2b00 cmp r3, #0 + 800982a: d103 bne.n 8009834 + { + OperatingMode = MODE_STDBY_RC; + 800982c: 4b05 ldr r3, [pc, #20] @ (8009844 ) + 800982e: 2201 movs r2, #1 + 8009830: 701a strb r2, [r3, #0] + } + else + { + OperatingMode = MODE_STDBY_XOSC; + } +} + 8009832: e002 b.n 800983a + OperatingMode = MODE_STDBY_XOSC; + 8009834: 4b03 ldr r3, [pc, #12] @ (8009844 ) + 8009836: 2202 movs r2, #2 + 8009838: 701a strb r2, [r3, #0] +} + 800983a: bf00 nop + 800983c: 3708 adds r7, #8 + 800983e: 46bd mov sp, r7 + 8009840: bd80 pop {r7, pc} + 8009842: bf00 nop + 8009844: 2000031c .word 0x2000031c + +08009848 : + SUBGRF_WriteCommand( RADIO_SET_FS, 0, 0 ); + OperatingMode = MODE_FS; +} + +void SUBGRF_SetTx( uint32_t timeout ) +{ + 8009848: b580 push {r7, lr} + 800984a: b084 sub sp, #16 + 800984c: af00 add r7, sp, #0 + 800984e: 6078 str r0, [r7, #4] + uint8_t buf[3]; + + OperatingMode = MODE_TX; + 8009850: 4b0c ldr r3, [pc, #48] @ (8009884 ) + 8009852: 2204 movs r2, #4 + 8009854: 701a strb r2, [r3, #0] + + buf[0] = ( uint8_t )( ( timeout >> 16 ) & 0xFF ); + 8009856: 687b ldr r3, [r7, #4] + 8009858: 0c1b lsrs r3, r3, #16 + 800985a: b2db uxtb r3, r3 + 800985c: 733b strb r3, [r7, #12] + buf[1] = ( uint8_t )( ( timeout >> 8 ) & 0xFF ); + 800985e: 687b ldr r3, [r7, #4] + 8009860: 0a1b lsrs r3, r3, #8 + 8009862: b2db uxtb r3, r3 + 8009864: 737b strb r3, [r7, #13] + buf[2] = ( uint8_t )( timeout & 0xFF ); + 8009866: 687b ldr r3, [r7, #4] + 8009868: b2db uxtb r3, r3 + 800986a: 73bb strb r3, [r7, #14] + SUBGRF_WriteCommand( RADIO_SET_TX, buf, 3 ); + 800986c: f107 030c add.w r3, r7, #12 + 8009870: 2203 movs r2, #3 + 8009872: 4619 mov r1, r3 + 8009874: 2083 movs r0, #131 @ 0x83 + 8009876: f000 fe19 bl 800a4ac +} + 800987a: bf00 nop + 800987c: 3710 adds r7, #16 + 800987e: 46bd mov sp, r7 + 8009880: bd80 pop {r7, pc} + 8009882: bf00 nop + 8009884: 2000031c .word 0x2000031c + +08009888 : + +void SUBGRF_SetRx( uint32_t timeout ) +{ + 8009888: b580 push {r7, lr} + 800988a: b084 sub sp, #16 + 800988c: af00 add r7, sp, #0 + 800988e: 6078 str r0, [r7, #4] + uint8_t buf[3]; + + OperatingMode = MODE_RX; + 8009890: 4b0c ldr r3, [pc, #48] @ (80098c4 ) + 8009892: 2205 movs r2, #5 + 8009894: 701a strb r2, [r3, #0] + + buf[0] = ( uint8_t )( ( timeout >> 16 ) & 0xFF ); + 8009896: 687b ldr r3, [r7, #4] + 8009898: 0c1b lsrs r3, r3, #16 + 800989a: b2db uxtb r3, r3 + 800989c: 733b strb r3, [r7, #12] + buf[1] = ( uint8_t )( ( timeout >> 8 ) & 0xFF ); + 800989e: 687b ldr r3, [r7, #4] + 80098a0: 0a1b lsrs r3, r3, #8 + 80098a2: b2db uxtb r3, r3 + 80098a4: 737b strb r3, [r7, #13] + buf[2] = ( uint8_t )( timeout & 0xFF ); + 80098a6: 687b ldr r3, [r7, #4] + 80098a8: b2db uxtb r3, r3 + 80098aa: 73bb strb r3, [r7, #14] + SUBGRF_WriteCommand( RADIO_SET_RX, buf, 3 ); + 80098ac: f107 030c add.w r3, r7, #12 + 80098b0: 2203 movs r2, #3 + 80098b2: 4619 mov r1, r3 + 80098b4: 2082 movs r0, #130 @ 0x82 + 80098b6: f000 fdf9 bl 800a4ac +} + 80098ba: bf00 nop + 80098bc: 3710 adds r7, #16 + 80098be: 46bd mov sp, r7 + 80098c0: bd80 pop {r7, pc} + 80098c2: bf00 nop + 80098c4: 2000031c .word 0x2000031c + +080098c8 : + +void SUBGRF_SetRxBoosted( uint32_t timeout ) +{ + 80098c8: b580 push {r7, lr} + 80098ca: b084 sub sp, #16 + 80098cc: af00 add r7, sp, #0 + 80098ce: 6078 str r0, [r7, #4] + uint8_t buf[3]; + + OperatingMode = MODE_RX; + 80098d0: 4b0e ldr r3, [pc, #56] @ (800990c ) + 80098d2: 2205 movs r2, #5 + 80098d4: 701a strb r2, [r3, #0] + + SUBGRF_WriteRegister( REG_RX_GAIN, 0x97 ); // max LNA gain, increase current by ~2mA for around ~3dB in sensitivity + 80098d6: 2197 movs r1, #151 @ 0x97 + 80098d8: f640 00ac movw r0, #2220 @ 0x8ac + 80098dc: f000 fd1c bl 800a318 + + buf[0] = ( uint8_t )( ( timeout >> 16 ) & 0xFF ); + 80098e0: 687b ldr r3, [r7, #4] + 80098e2: 0c1b lsrs r3, r3, #16 + 80098e4: b2db uxtb r3, r3 + 80098e6: 733b strb r3, [r7, #12] + buf[1] = ( uint8_t )( ( timeout >> 8 ) & 0xFF ); + 80098e8: 687b ldr r3, [r7, #4] + 80098ea: 0a1b lsrs r3, r3, #8 + 80098ec: b2db uxtb r3, r3 + 80098ee: 737b strb r3, [r7, #13] + buf[2] = ( uint8_t )( timeout & 0xFF ); + 80098f0: 687b ldr r3, [r7, #4] + 80098f2: b2db uxtb r3, r3 + 80098f4: 73bb strb r3, [r7, #14] + SUBGRF_WriteCommand( RADIO_SET_RX, buf, 3 ); + 80098f6: f107 030c add.w r3, r7, #12 + 80098fa: 2203 movs r2, #3 + 80098fc: 4619 mov r1, r3 + 80098fe: 2082 movs r0, #130 @ 0x82 + 8009900: f000 fdd4 bl 800a4ac +} + 8009904: bf00 nop + 8009906: 3710 adds r7, #16 + 8009908: 46bd mov sp, r7 + 800990a: bd80 pop {r7, pc} + 800990c: 2000031c .word 0x2000031c + +08009910 : + +void SUBGRF_SetRxDutyCycle( uint32_t rxTime, uint32_t sleepTime ) +{ + 8009910: b580 push {r7, lr} + 8009912: b084 sub sp, #16 + 8009914: af00 add r7, sp, #0 + 8009916: 6078 str r0, [r7, #4] + 8009918: 6039 str r1, [r7, #0] + uint8_t buf[6]; + + buf[0] = ( uint8_t )( ( rxTime >> 16 ) & 0xFF ); + 800991a: 687b ldr r3, [r7, #4] + 800991c: 0c1b lsrs r3, r3, #16 + 800991e: b2db uxtb r3, r3 + 8009920: 723b strb r3, [r7, #8] + buf[1] = ( uint8_t )( ( rxTime >> 8 ) & 0xFF ); + 8009922: 687b ldr r3, [r7, #4] + 8009924: 0a1b lsrs r3, r3, #8 + 8009926: b2db uxtb r3, r3 + 8009928: 727b strb r3, [r7, #9] + buf[2] = ( uint8_t )( rxTime & 0xFF ); + 800992a: 687b ldr r3, [r7, #4] + 800992c: b2db uxtb r3, r3 + 800992e: 72bb strb r3, [r7, #10] + buf[3] = ( uint8_t )( ( sleepTime >> 16 ) & 0xFF ); + 8009930: 683b ldr r3, [r7, #0] + 8009932: 0c1b lsrs r3, r3, #16 + 8009934: b2db uxtb r3, r3 + 8009936: 72fb strb r3, [r7, #11] + buf[4] = ( uint8_t )( ( sleepTime >> 8 ) & 0xFF ); + 8009938: 683b ldr r3, [r7, #0] + 800993a: 0a1b lsrs r3, r3, #8 + 800993c: b2db uxtb r3, r3 + 800993e: 733b strb r3, [r7, #12] + buf[5] = ( uint8_t )( sleepTime & 0xFF ); + 8009940: 683b ldr r3, [r7, #0] + 8009942: b2db uxtb r3, r3 + 8009944: 737b strb r3, [r7, #13] + SUBGRF_WriteCommand( RADIO_SET_RXDUTYCYCLE, buf, 6 ); + 8009946: f107 0308 add.w r3, r7, #8 + 800994a: 2206 movs r2, #6 + 800994c: 4619 mov r1, r3 + 800994e: 2094 movs r0, #148 @ 0x94 + 8009950: f000 fdac bl 800a4ac + OperatingMode = MODE_RX_DC; + 8009954: 4b03 ldr r3, [pc, #12] @ (8009964 ) + 8009956: 2206 movs r2, #6 + 8009958: 701a strb r2, [r3, #0] +} + 800995a: bf00 nop + 800995c: 3710 adds r7, #16 + 800995e: 46bd mov sp, r7 + 8009960: bd80 pop {r7, pc} + 8009962: bf00 nop + 8009964: 2000031c .word 0x2000031c + +08009968 : + +void SUBGRF_SetCad( void ) +{ + 8009968: b580 push {r7, lr} + 800996a: af00 add r7, sp, #0 + SUBGRF_WriteCommand( RADIO_SET_CAD, 0, 0 ); + 800996c: 2200 movs r2, #0 + 800996e: 2100 movs r1, #0 + 8009970: 20c5 movs r0, #197 @ 0xc5 + 8009972: f000 fd9b bl 800a4ac + OperatingMode = MODE_CAD; + 8009976: 4b02 ldr r3, [pc, #8] @ (8009980 ) + 8009978: 2207 movs r2, #7 + 800997a: 701a strb r2, [r3, #0] +} + 800997c: bf00 nop + 800997e: bd80 pop {r7, pc} + 8009980: 2000031c .word 0x2000031c + +08009984 : + +void SUBGRF_SetTxContinuousWave( void ) +{ + 8009984: b580 push {r7, lr} + 8009986: af00 add r7, sp, #0 + SUBGRF_WriteCommand( RADIO_SET_TXCONTINUOUSWAVE, 0, 0 ); + 8009988: 2200 movs r2, #0 + 800998a: 2100 movs r1, #0 + 800998c: 20d1 movs r0, #209 @ 0xd1 + 800998e: f000 fd8d bl 800a4ac +} + 8009992: bf00 nop + 8009994: bd80 pop {r7, pc} + +08009996 : + +void SUBGRF_SetTxInfinitePreamble( void ) +{ + 8009996: b580 push {r7, lr} + 8009998: af00 add r7, sp, #0 + SUBGRF_WriteCommand( RADIO_SET_TXCONTINUOUSPREAMBLE, 0, 0 ); + 800999a: 2200 movs r2, #0 + 800999c: 2100 movs r1, #0 + 800999e: 20d2 movs r0, #210 @ 0xd2 + 80099a0: f000 fd84 bl 800a4ac +} + 80099a4: bf00 nop + 80099a6: bd80 pop {r7, pc} + +080099a8 : + +void SUBGRF_SetStopRxTimerOnPreambleDetect( bool enable ) +{ + 80099a8: b580 push {r7, lr} + 80099aa: b082 sub sp, #8 + 80099ac: af00 add r7, sp, #0 + 80099ae: 4603 mov r3, r0 + 80099b0: 71fb strb r3, [r7, #7] + SUBGRF_WriteCommand( RADIO_SET_STOPRXTIMERONPREAMBLE, ( uint8_t* )&enable, 1 ); + 80099b2: 1dfb adds r3, r7, #7 + 80099b4: 2201 movs r2, #1 + 80099b6: 4619 mov r1, r3 + 80099b8: 209f movs r0, #159 @ 0x9f + 80099ba: f000 fd77 bl 800a4ac +} + 80099be: bf00 nop + 80099c0: 3708 adds r7, #8 + 80099c2: 46bd mov sp, r7 + 80099c4: bd80 pop {r7, pc} + +080099c6 : + +void SUBGRF_SetLoRaSymbNumTimeout( uint8_t symbNum ) +{ + 80099c6: b580 push {r7, lr} + 80099c8: b084 sub sp, #16 + 80099ca: af00 add r7, sp, #0 + 80099cc: 4603 mov r3, r0 + 80099ce: 71fb strb r3, [r7, #7] + SUBGRF_WriteCommand( RADIO_SET_LORASYMBTIMEOUT, &symbNum, 1 ); + 80099d0: 1dfb adds r3, r7, #7 + 80099d2: 2201 movs r2, #1 + 80099d4: 4619 mov r1, r3 + 80099d6: 20a0 movs r0, #160 @ 0xa0 + 80099d8: f000 fd68 bl 800a4ac + + if( symbNum >= 64 ) + 80099dc: 79fb ldrb r3, [r7, #7] + 80099de: 2b3f cmp r3, #63 @ 0x3f + 80099e0: d91c bls.n 8009a1c + { + uint8_t mant = symbNum >> 1; + 80099e2: 79fb ldrb r3, [r7, #7] + 80099e4: 085b lsrs r3, r3, #1 + 80099e6: 73fb strb r3, [r7, #15] + uint8_t exp = 0; + 80099e8: 2300 movs r3, #0 + 80099ea: 73bb strb r3, [r7, #14] + uint8_t reg = 0; + 80099ec: 2300 movs r3, #0 + 80099ee: 737b strb r3, [r7, #13] + + while( mant > 31 ) + 80099f0: e005 b.n 80099fe + { + mant >>= 2; + 80099f2: 7bfb ldrb r3, [r7, #15] + 80099f4: 089b lsrs r3, r3, #2 + 80099f6: 73fb strb r3, [r7, #15] + exp++; + 80099f8: 7bbb ldrb r3, [r7, #14] + 80099fa: 3301 adds r3, #1 + 80099fc: 73bb strb r3, [r7, #14] + while( mant > 31 ) + 80099fe: 7bfb ldrb r3, [r7, #15] + 8009a00: 2b1f cmp r3, #31 + 8009a02: d8f6 bhi.n 80099f2 + } + + reg = exp + ( mant << 3 ); + 8009a04: 7bfb ldrb r3, [r7, #15] + 8009a06: 00db lsls r3, r3, #3 + 8009a08: b2da uxtb r2, r3 + 8009a0a: 7bbb ldrb r3, [r7, #14] + 8009a0c: 4413 add r3, r2 + 8009a0e: 737b strb r3, [r7, #13] + SUBGRF_WriteRegister( REG_LR_SYNCH_TIMEOUT, reg ); + 8009a10: 7b7b ldrb r3, [r7, #13] + 8009a12: 4619 mov r1, r3 + 8009a14: f240 7006 movw r0, #1798 @ 0x706 + 8009a18: f000 fc7e bl 800a318 + } +} + 8009a1c: bf00 nop + 8009a1e: 3710 adds r7, #16 + 8009a20: 46bd mov sp, r7 + 8009a22: bd80 pop {r7, pc} + +08009a24 : + +void SUBGRF_SetRegulatorMode( void ) +{ + 8009a24: b580 push {r7, lr} + 8009a26: b082 sub sp, #8 + 8009a28: af00 add r7, sp, #0 + RadioRegulatorMode_t mode; + + if ( ( 1UL == RBI_IsDCDC() ) && ( 1UL == DCDC_ENABLE ) ) + 8009a2a: f002 faa4 bl 800bf76 + 8009a2e: 4603 mov r3, r0 + 8009a30: 2b01 cmp r3, #1 + 8009a32: d102 bne.n 8009a3a + { + mode = USE_DCDC ; + 8009a34: 2301 movs r3, #1 + 8009a36: 71fb strb r3, [r7, #7] + 8009a38: e001 b.n 8009a3e + } + else + { + mode = USE_LDO ; + 8009a3a: 2300 movs r3, #0 + 8009a3c: 71fb strb r3, [r7, #7] + } + SUBGRF_WriteCommand( RADIO_SET_REGULATORMODE, ( uint8_t* )&mode, 1 ); + 8009a3e: 1dfb adds r3, r7, #7 + 8009a40: 2201 movs r2, #1 + 8009a42: 4619 mov r1, r3 + 8009a44: 2096 movs r0, #150 @ 0x96 + 8009a46: f000 fd31 bl 800a4ac +} + 8009a4a: bf00 nop + 8009a4c: 3708 adds r7, #8 + 8009a4e: 46bd mov sp, r7 + 8009a50: bd80 pop {r7, pc} + +08009a52 : + +void SUBGRF_Calibrate( CalibrationParams_t calibParam ) +{ + 8009a52: b580 push {r7, lr} + 8009a54: b084 sub sp, #16 + 8009a56: af00 add r7, sp, #0 + 8009a58: 7138 strb r0, [r7, #4] + uint8_t value = ( ( ( uint8_t )calibParam.Fields.ImgEnable << 6 ) | + 8009a5a: 793b ldrb r3, [r7, #4] + 8009a5c: f3c3 1380 ubfx r3, r3, #6, #1 + 8009a60: b2db uxtb r3, r3 + 8009a62: b25b sxtb r3, r3 + 8009a64: 019b lsls r3, r3, #6 + 8009a66: b25a sxtb r2, r3 + ( ( uint8_t )calibParam.Fields.ADCBulkPEnable << 5 ) | + 8009a68: 793b ldrb r3, [r7, #4] + 8009a6a: f3c3 1340 ubfx r3, r3, #5, #1 + 8009a6e: b2db uxtb r3, r3 + uint8_t value = ( ( ( uint8_t )calibParam.Fields.ImgEnable << 6 ) | + 8009a70: b25b sxtb r3, r3 + 8009a72: 015b lsls r3, r3, #5 + 8009a74: b25b sxtb r3, r3 + 8009a76: 4313 orrs r3, r2 + 8009a78: b25a sxtb r2, r3 + ( ( uint8_t )calibParam.Fields.ADCBulkNEnable << 4 ) | + 8009a7a: 793b ldrb r3, [r7, #4] + 8009a7c: f3c3 1300 ubfx r3, r3, #4, #1 + 8009a80: b2db uxtb r3, r3 + ( ( uint8_t )calibParam.Fields.ADCBulkPEnable << 5 ) | + 8009a82: b25b sxtb r3, r3 + 8009a84: 011b lsls r3, r3, #4 + 8009a86: b25b sxtb r3, r3 + 8009a88: 4313 orrs r3, r2 + 8009a8a: b25a sxtb r2, r3 + ( ( uint8_t )calibParam.Fields.ADCPulseEnable << 3 ) | + 8009a8c: 793b ldrb r3, [r7, #4] + 8009a8e: f3c3 03c0 ubfx r3, r3, #3, #1 + 8009a92: b2db uxtb r3, r3 + ( ( uint8_t )calibParam.Fields.ADCBulkNEnable << 4 ) | + 8009a94: b25b sxtb r3, r3 + 8009a96: 00db lsls r3, r3, #3 + 8009a98: b25b sxtb r3, r3 + 8009a9a: 4313 orrs r3, r2 + 8009a9c: b25a sxtb r2, r3 + ( ( uint8_t )calibParam.Fields.PLLEnable << 2 ) | + 8009a9e: 793b ldrb r3, [r7, #4] + 8009aa0: f3c3 0380 ubfx r3, r3, #2, #1 + 8009aa4: b2db uxtb r3, r3 + ( ( uint8_t )calibParam.Fields.ADCPulseEnable << 3 ) | + 8009aa6: b25b sxtb r3, r3 + 8009aa8: 009b lsls r3, r3, #2 + 8009aaa: b25b sxtb r3, r3 + 8009aac: 4313 orrs r3, r2 + 8009aae: b25a sxtb r2, r3 + ( ( uint8_t )calibParam.Fields.RC13MEnable << 1 ) | + 8009ab0: 793b ldrb r3, [r7, #4] + 8009ab2: f3c3 0340 ubfx r3, r3, #1, #1 + 8009ab6: b2db uxtb r3, r3 + ( ( uint8_t )calibParam.Fields.PLLEnable << 2 ) | + 8009ab8: b25b sxtb r3, r3 + 8009aba: 005b lsls r3, r3, #1 + 8009abc: b25b sxtb r3, r3 + 8009abe: 4313 orrs r3, r2 + 8009ac0: b25a sxtb r2, r3 + ( ( uint8_t )calibParam.Fields.RC64KEnable ) ); + 8009ac2: 793b ldrb r3, [r7, #4] + 8009ac4: f3c3 0300 ubfx r3, r3, #0, #1 + 8009ac8: b2db uxtb r3, r3 + 8009aca: b25b sxtb r3, r3 + ( ( uint8_t )calibParam.Fields.RC13MEnable << 1 ) | + 8009acc: 4313 orrs r3, r2 + 8009ace: b25b sxtb r3, r3 + 8009ad0: b2db uxtb r3, r3 + uint8_t value = ( ( ( uint8_t )calibParam.Fields.ImgEnable << 6 ) | + 8009ad2: 73fb strb r3, [r7, #15] + + SUBGRF_WriteCommand( RADIO_CALIBRATE, &value, 1 ); + 8009ad4: f107 030f add.w r3, r7, #15 + 8009ad8: 2201 movs r2, #1 + 8009ada: 4619 mov r1, r3 + 8009adc: 2089 movs r0, #137 @ 0x89 + 8009ade: f000 fce5 bl 800a4ac +} + 8009ae2: bf00 nop + 8009ae4: 3710 adds r7, #16 + 8009ae6: 46bd mov sp, r7 + 8009ae8: bd80 pop {r7, pc} + ... + +08009aec : + +void SUBGRF_CalibrateImage( uint32_t freq ) +{ + 8009aec: b580 push {r7, lr} + 8009aee: b084 sub sp, #16 + 8009af0: af00 add r7, sp, #0 + 8009af2: 6078 str r0, [r7, #4] + uint8_t calFreq[2]; + + if( freq > 900000000 ) + 8009af4: 687b ldr r3, [r7, #4] + 8009af6: 4a1d ldr r2, [pc, #116] @ (8009b6c ) + 8009af8: 4293 cmp r3, r2 + 8009afa: d904 bls.n 8009b06 + { + calFreq[0] = 0xE1; + 8009afc: 23e1 movs r3, #225 @ 0xe1 + 8009afe: 733b strb r3, [r7, #12] + calFreq[1] = 0xE9; + 8009b00: 23e9 movs r3, #233 @ 0xe9 + 8009b02: 737b strb r3, [r7, #13] + 8009b04: e027 b.n 8009b56 + } + else if( freq > 850000000 ) + 8009b06: 687b ldr r3, [r7, #4] + 8009b08: 4a19 ldr r2, [pc, #100] @ (8009b70 ) + 8009b0a: 4293 cmp r3, r2 + 8009b0c: d904 bls.n 8009b18 + { + calFreq[0] = 0xD7; + 8009b0e: 23d7 movs r3, #215 @ 0xd7 + 8009b10: 733b strb r3, [r7, #12] + calFreq[1] = 0xDB; + 8009b12: 23db movs r3, #219 @ 0xdb + 8009b14: 737b strb r3, [r7, #13] + 8009b16: e01e b.n 8009b56 + } + else if( freq > 770000000 ) + 8009b18: 687b ldr r3, [r7, #4] + 8009b1a: 4a16 ldr r2, [pc, #88] @ (8009b74 ) + 8009b1c: 4293 cmp r3, r2 + 8009b1e: d904 bls.n 8009b2a + { + calFreq[0] = 0xC1; + 8009b20: 23c1 movs r3, #193 @ 0xc1 + 8009b22: 733b strb r3, [r7, #12] + calFreq[1] = 0xC5; + 8009b24: 23c5 movs r3, #197 @ 0xc5 + 8009b26: 737b strb r3, [r7, #13] + 8009b28: e015 b.n 8009b56 + } + else if( freq > 460000000 ) + 8009b2a: 687b ldr r3, [r7, #4] + 8009b2c: 4a12 ldr r2, [pc, #72] @ (8009b78 ) + 8009b2e: 4293 cmp r3, r2 + 8009b30: d904 bls.n 8009b3c + { + calFreq[0] = 0x75; + 8009b32: 2375 movs r3, #117 @ 0x75 + 8009b34: 733b strb r3, [r7, #12] + calFreq[1] = 0x81; + 8009b36: 2381 movs r3, #129 @ 0x81 + 8009b38: 737b strb r3, [r7, #13] + 8009b3a: e00c b.n 8009b56 + } + else if( freq > 425000000 ) + 8009b3c: 687b ldr r3, [r7, #4] + 8009b3e: 4a0f ldr r2, [pc, #60] @ (8009b7c ) + 8009b40: 4293 cmp r3, r2 + 8009b42: d904 bls.n 8009b4e + { + calFreq[0] = 0x6B; + 8009b44: 236b movs r3, #107 @ 0x6b + 8009b46: 733b strb r3, [r7, #12] + calFreq[1] = 0x6F; + 8009b48: 236f movs r3, #111 @ 0x6f + 8009b4a: 737b strb r3, [r7, #13] + 8009b4c: e003 b.n 8009b56 + } + else /* freq <= 425000000*/ + { + /* [ 156MHz - 171MHz ] */ + calFreq[0] = 0x29; + 8009b4e: 2329 movs r3, #41 @ 0x29 + 8009b50: 733b strb r3, [r7, #12] + calFreq[1] = 0x2B ; + 8009b52: 232b movs r3, #43 @ 0x2b + 8009b54: 737b strb r3, [r7, #13] + } + SUBGRF_WriteCommand( RADIO_CALIBRATEIMAGE, calFreq, 2 ); + 8009b56: f107 030c add.w r3, r7, #12 + 8009b5a: 2202 movs r2, #2 + 8009b5c: 4619 mov r1, r3 + 8009b5e: 2098 movs r0, #152 @ 0x98 + 8009b60: f000 fca4 bl 800a4ac +} + 8009b64: bf00 nop + 8009b66: 3710 adds r7, #16 + 8009b68: 46bd mov sp, r7 + 8009b6a: bd80 pop {r7, pc} + 8009b6c: 35a4e900 .word 0x35a4e900 + 8009b70: 32a9f880 .word 0x32a9f880 + 8009b74: 2de54480 .word 0x2de54480 + 8009b78: 1b6b0b00 .word 0x1b6b0b00 + 8009b7c: 1954fc40 .word 0x1954fc40 + +08009b80 : + +void SUBGRF_SetPaConfig( uint8_t paDutyCycle, uint8_t hpMax, uint8_t deviceSel, uint8_t paLut ) +{ + 8009b80: b590 push {r4, r7, lr} + 8009b82: b085 sub sp, #20 + 8009b84: af00 add r7, sp, #0 + 8009b86: 4604 mov r4, r0 + 8009b88: 4608 mov r0, r1 + 8009b8a: 4611 mov r1, r2 + 8009b8c: 461a mov r2, r3 + 8009b8e: 4623 mov r3, r4 + 8009b90: 71fb strb r3, [r7, #7] + 8009b92: 4603 mov r3, r0 + 8009b94: 71bb strb r3, [r7, #6] + 8009b96: 460b mov r3, r1 + 8009b98: 717b strb r3, [r7, #5] + 8009b9a: 4613 mov r3, r2 + 8009b9c: 713b strb r3, [r7, #4] + uint8_t buf[4]; + + buf[0] = paDutyCycle; + 8009b9e: 79fb ldrb r3, [r7, #7] + 8009ba0: 733b strb r3, [r7, #12] + buf[1] = hpMax; + 8009ba2: 79bb ldrb r3, [r7, #6] + 8009ba4: 737b strb r3, [r7, #13] + buf[2] = deviceSel; + 8009ba6: 797b ldrb r3, [r7, #5] + 8009ba8: 73bb strb r3, [r7, #14] + buf[3] = paLut; + 8009baa: 793b ldrb r3, [r7, #4] + 8009bac: 73fb strb r3, [r7, #15] + SUBGRF_WriteCommand( RADIO_SET_PACONFIG, buf, 4 ); + 8009bae: f107 030c add.w r3, r7, #12 + 8009bb2: 2204 movs r2, #4 + 8009bb4: 4619 mov r1, r3 + 8009bb6: 2095 movs r0, #149 @ 0x95 + 8009bb8: f000 fc78 bl 800a4ac +} + 8009bbc: bf00 nop + 8009bbe: 3714 adds r7, #20 + 8009bc0: 46bd mov sp, r7 + 8009bc2: bd90 pop {r4, r7, pc} + +08009bc4 : +{ + SUBGRF_WriteCommand( RADIO_SET_TXFALLBACKMODE, &fallbackMode, 1 ); +} + +void SUBGRF_SetDioIrqParams( uint16_t irqMask, uint16_t dio1Mask, uint16_t dio2Mask, uint16_t dio3Mask ) +{ + 8009bc4: b590 push {r4, r7, lr} + 8009bc6: b085 sub sp, #20 + 8009bc8: af00 add r7, sp, #0 + 8009bca: 4604 mov r4, r0 + 8009bcc: 4608 mov r0, r1 + 8009bce: 4611 mov r1, r2 + 8009bd0: 461a mov r2, r3 + 8009bd2: 4623 mov r3, r4 + 8009bd4: 80fb strh r3, [r7, #6] + 8009bd6: 4603 mov r3, r0 + 8009bd8: 80bb strh r3, [r7, #4] + 8009bda: 460b mov r3, r1 + 8009bdc: 807b strh r3, [r7, #2] + 8009bde: 4613 mov r3, r2 + 8009be0: 803b strh r3, [r7, #0] + uint8_t buf[8]; + + buf[0] = ( uint8_t )( ( irqMask >> 8 ) & 0x00FF ); + 8009be2: 88fb ldrh r3, [r7, #6] + 8009be4: 0a1b lsrs r3, r3, #8 + 8009be6: b29b uxth r3, r3 + 8009be8: b2db uxtb r3, r3 + 8009bea: 723b strb r3, [r7, #8] + buf[1] = ( uint8_t )( irqMask & 0x00FF ); + 8009bec: 88fb ldrh r3, [r7, #6] + 8009bee: b2db uxtb r3, r3 + 8009bf0: 727b strb r3, [r7, #9] + buf[2] = ( uint8_t )( ( dio1Mask >> 8 ) & 0x00FF ); + 8009bf2: 88bb ldrh r3, [r7, #4] + 8009bf4: 0a1b lsrs r3, r3, #8 + 8009bf6: b29b uxth r3, r3 + 8009bf8: b2db uxtb r3, r3 + 8009bfa: 72bb strb r3, [r7, #10] + buf[3] = ( uint8_t )( dio1Mask & 0x00FF ); + 8009bfc: 88bb ldrh r3, [r7, #4] + 8009bfe: b2db uxtb r3, r3 + 8009c00: 72fb strb r3, [r7, #11] + buf[4] = ( uint8_t )( ( dio2Mask >> 8 ) & 0x00FF ); + 8009c02: 887b ldrh r3, [r7, #2] + 8009c04: 0a1b lsrs r3, r3, #8 + 8009c06: b29b uxth r3, r3 + 8009c08: b2db uxtb r3, r3 + 8009c0a: 733b strb r3, [r7, #12] + buf[5] = ( uint8_t )( dio2Mask & 0x00FF ); + 8009c0c: 887b ldrh r3, [r7, #2] + 8009c0e: b2db uxtb r3, r3 + 8009c10: 737b strb r3, [r7, #13] + buf[6] = ( uint8_t )( ( dio3Mask >> 8 ) & 0x00FF ); + 8009c12: 883b ldrh r3, [r7, #0] + 8009c14: 0a1b lsrs r3, r3, #8 + 8009c16: b29b uxth r3, r3 + 8009c18: b2db uxtb r3, r3 + 8009c1a: 73bb strb r3, [r7, #14] + buf[7] = ( uint8_t )( dio3Mask & 0x00FF ); + 8009c1c: 883b ldrh r3, [r7, #0] + 8009c1e: b2db uxtb r3, r3 + 8009c20: 73fb strb r3, [r7, #15] + SUBGRF_WriteCommand( RADIO_CFG_DIOIRQ, buf, 8 ); + 8009c22: f107 0308 add.w r3, r7, #8 + 8009c26: 2208 movs r2, #8 + 8009c28: 4619 mov r1, r3 + 8009c2a: 2008 movs r0, #8 + 8009c2c: f000 fc3e bl 800a4ac +} + 8009c30: bf00 nop + 8009c32: 3714 adds r7, #20 + 8009c34: 46bd mov sp, r7 + 8009c36: bd90 pop {r4, r7, pc} + +08009c38 : + SUBGRF_ReadCommand( RADIO_GET_IRQSTATUS, irqStatus, 2 ); + return ( irqStatus[0] << 8 ) | irqStatus[1]; +} + +void SUBGRF_SetTcxoMode (RadioTcxoCtrlVoltage_t tcxoVoltage, uint32_t timeout ) +{ + 8009c38: b580 push {r7, lr} + 8009c3a: b084 sub sp, #16 + 8009c3c: af00 add r7, sp, #0 + 8009c3e: 4603 mov r3, r0 + 8009c40: 6039 str r1, [r7, #0] + 8009c42: 71fb strb r3, [r7, #7] + uint8_t buf[4]; + + buf[0] = tcxoVoltage & 0x07; + 8009c44: 79fb ldrb r3, [r7, #7] + 8009c46: f003 0307 and.w r3, r3, #7 + 8009c4a: b2db uxtb r3, r3 + 8009c4c: 733b strb r3, [r7, #12] + buf[1] = ( uint8_t )( ( timeout >> 16 ) & 0xFF ); + 8009c4e: 683b ldr r3, [r7, #0] + 8009c50: 0c1b lsrs r3, r3, #16 + 8009c52: b2db uxtb r3, r3 + 8009c54: 737b strb r3, [r7, #13] + buf[2] = ( uint8_t )( ( timeout >> 8 ) & 0xFF ); + 8009c56: 683b ldr r3, [r7, #0] + 8009c58: 0a1b lsrs r3, r3, #8 + 8009c5a: b2db uxtb r3, r3 + 8009c5c: 73bb strb r3, [r7, #14] + buf[3] = ( uint8_t )( timeout & 0xFF ); + 8009c5e: 683b ldr r3, [r7, #0] + 8009c60: b2db uxtb r3, r3 + 8009c62: 73fb strb r3, [r7, #15] + + SUBGRF_WriteCommand( RADIO_SET_TCXOMODE, buf, 4 ); + 8009c64: f107 030c add.w r3, r7, #12 + 8009c68: 2204 movs r2, #4 + 8009c6a: 4619 mov r1, r3 + 8009c6c: 2097 movs r0, #151 @ 0x97 + 8009c6e: f000 fc1d bl 800a4ac +} + 8009c72: bf00 nop + 8009c74: 3710 adds r7, #16 + 8009c76: 46bd mov sp, r7 + 8009c78: bd80 pop {r7, pc} + ... + +08009c7c : + +void SUBGRF_SetRfFrequency( uint32_t frequency ) +{ + 8009c7c: e92d 43b0 stmdb sp!, {r4, r5, r7, r8, r9, lr} + 8009c80: b084 sub sp, #16 + 8009c82: af00 add r7, sp, #0 + 8009c84: 6078 str r0, [r7, #4] + uint8_t buf[4]; + uint32_t chan = 0; + 8009c86: 2300 movs r3, #0 + 8009c88: 60fb str r3, [r7, #12] + + if( ImageCalibrated == false ) + 8009c8a: 4b1d ldr r3, [pc, #116] @ (8009d00 ) + 8009c8c: 781b ldrb r3, [r3, #0] + 8009c8e: f083 0301 eor.w r3, r3, #1 + 8009c92: b2db uxtb r3, r3 + 8009c94: 2b00 cmp r3, #0 + 8009c96: d005 beq.n 8009ca4 + { + SUBGRF_CalibrateImage( frequency ); + 8009c98: 6878 ldr r0, [r7, #4] + 8009c9a: f7ff ff27 bl 8009aec + ImageCalibrated = true; + 8009c9e: 4b18 ldr r3, [pc, #96] @ (8009d00 ) + 8009ca0: 2201 movs r2, #1 + 8009ca2: 701a strb r2, [r3, #0] + } + SX_FREQ_TO_CHANNEL(chan, frequency); + 8009ca4: 687b ldr r3, [r7, #4] + 8009ca6: 2200 movs r2, #0 + 8009ca8: 461c mov r4, r3 + 8009caa: 4615 mov r5, r2 + 8009cac: ea4f 19d4 mov.w r9, r4, lsr #7 + 8009cb0: ea4f 6844 mov.w r8, r4, lsl #25 + 8009cb4: 4a13 ldr r2, [pc, #76] @ (8009d04 ) + 8009cb6: f04f 0300 mov.w r3, #0 + 8009cba: 4640 mov r0, r8 + 8009cbc: 4649 mov r1, r9 + 8009cbe: f7f6 fa63 bl 8000188 <__aeabi_uldivmod> + 8009cc2: 4602 mov r2, r0 + 8009cc4: 460b mov r3, r1 + 8009cc6: 4613 mov r3, r2 + 8009cc8: 60fb str r3, [r7, #12] + buf[0] = ( uint8_t )( ( chan >> 24 ) & 0xFF ); + 8009cca: 68fb ldr r3, [r7, #12] + 8009ccc: 0e1b lsrs r3, r3, #24 + 8009cce: b2db uxtb r3, r3 + 8009cd0: 723b strb r3, [r7, #8] + buf[1] = ( uint8_t )( ( chan >> 16 ) & 0xFF ); + 8009cd2: 68fb ldr r3, [r7, #12] + 8009cd4: 0c1b lsrs r3, r3, #16 + 8009cd6: b2db uxtb r3, r3 + 8009cd8: 727b strb r3, [r7, #9] + buf[2] = ( uint8_t )( ( chan >> 8 ) & 0xFF ); + 8009cda: 68fb ldr r3, [r7, #12] + 8009cdc: 0a1b lsrs r3, r3, #8 + 8009cde: b2db uxtb r3, r3 + 8009ce0: 72bb strb r3, [r7, #10] + buf[3] = ( uint8_t )( chan & 0xFF ); + 8009ce2: 68fb ldr r3, [r7, #12] + 8009ce4: b2db uxtb r3, r3 + 8009ce6: 72fb strb r3, [r7, #11] + SUBGRF_WriteCommand( RADIO_SET_RFFREQUENCY, buf, 4 ); + 8009ce8: f107 0308 add.w r3, r7, #8 + 8009cec: 2204 movs r2, #4 + 8009cee: 4619 mov r1, r3 + 8009cf0: 2086 movs r0, #134 @ 0x86 + 8009cf2: f000 fbdb bl 800a4ac +} + 8009cf6: bf00 nop + 8009cf8: 3710 adds r7, #16 + 8009cfa: 46bd mov sp, r7 + 8009cfc: e8bd 83b0 ldmia.w sp!, {r4, r5, r7, r8, r9, pc} + 8009d00: 20000324 .word 0x20000324 + 8009d04: 01e84800 .word 0x01e84800 + +08009d08 : + +void SUBGRF_SetPacketType( RadioPacketTypes_t packetType ) +{ + 8009d08: b580 push {r7, lr} + 8009d0a: b082 sub sp, #8 + 8009d0c: af00 add r7, sp, #0 + 8009d0e: 4603 mov r3, r0 + 8009d10: 71fb strb r3, [r7, #7] + // Save packet type internally to avoid questioning the radio + PacketType = packetType; + 8009d12: 79fa ldrb r2, [r7, #7] + 8009d14: 4b09 ldr r3, [pc, #36] @ (8009d3c ) + 8009d16: 701a strb r2, [r3, #0] + + if( packetType == PACKET_TYPE_GFSK ) + 8009d18: 79fb ldrb r3, [r7, #7] + 8009d1a: 2b00 cmp r3, #0 + 8009d1c: d104 bne.n 8009d28 + { + SUBGRF_WriteRegister( REG_BIT_SYNC, 0x00 ); + 8009d1e: 2100 movs r1, #0 + 8009d20: f240 60ac movw r0, #1708 @ 0x6ac + 8009d24: f000 faf8 bl 800a318 + } + SUBGRF_WriteCommand( RADIO_SET_PACKETTYPE, ( uint8_t* )&packetType, 1 ); + 8009d28: 1dfb adds r3, r7, #7 + 8009d2a: 2201 movs r2, #1 + 8009d2c: 4619 mov r1, r3 + 8009d2e: 208a movs r0, #138 @ 0x8a + 8009d30: f000 fbbc bl 800a4ac +} + 8009d34: bf00 nop + 8009d36: 3708 adds r7, #8 + 8009d38: 46bd mov sp, r7 + 8009d3a: bd80 pop {r7, pc} + 8009d3c: 2000031d .word 0x2000031d + +08009d40 : + +RadioPacketTypes_t SUBGRF_GetPacketType( void ) +{ + 8009d40: b480 push {r7} + 8009d42: af00 add r7, sp, #0 + return PacketType; + 8009d44: 4b02 ldr r3, [pc, #8] @ (8009d50 ) + 8009d46: 781b ldrb r3, [r3, #0] +} + 8009d48: 4618 mov r0, r3 + 8009d4a: 46bd mov sp, r7 + 8009d4c: bc80 pop {r7} + 8009d4e: 4770 bx lr + 8009d50: 2000031d .word 0x2000031d + +08009d54 : + +void SUBGRF_SetTxParams( uint8_t paSelect, int8_t power, RadioRampTimes_t rampTime ) +{ + 8009d54: b580 push {r7, lr} + 8009d56: b084 sub sp, #16 + 8009d58: af00 add r7, sp, #0 + 8009d5a: 4603 mov r3, r0 + 8009d5c: 71fb strb r3, [r7, #7] + 8009d5e: 460b mov r3, r1 + 8009d60: 71bb strb r3, [r7, #6] + 8009d62: 4613 mov r3, r2 + 8009d64: 717b strb r3, [r7, #5] + uint8_t buf[2]; + int32_t max_power; + + if (paSelect == RFO_LP) + 8009d66: 79fb ldrb r3, [r7, #7] + 8009d68: 2b01 cmp r3, #1 + 8009d6a: d149 bne.n 8009e00 + { + max_power = RBI_GetRFOMaxPowerConfig(RBI_RFO_LP_MAXPOWER); + 8009d6c: 2000 movs r0, #0 + 8009d6e: f002 f909 bl 800bf84 + 8009d72: 60f8 str r0, [r7, #12] + if (power > max_power) + 8009d74: f997 3006 ldrsb.w r3, [r7, #6] + 8009d78: 68fa ldr r2, [r7, #12] + 8009d7a: 429a cmp r2, r3 + 8009d7c: da01 bge.n 8009d82 + { + power = max_power; + 8009d7e: 68fb ldr r3, [r7, #12] + 8009d80: 71bb strb r3, [r7, #6] + } + if (max_power == 14) + 8009d82: 68fb ldr r3, [r7, #12] + 8009d84: 2b0e cmp r3, #14 + 8009d86: d10e bne.n 8009da6 + { + SUBGRF_SetPaConfig(0x04, 0x00, 0x01, 0x01); + 8009d88: 2301 movs r3, #1 + 8009d8a: 2201 movs r2, #1 + 8009d8c: 2100 movs r1, #0 + 8009d8e: 2004 movs r0, #4 + 8009d90: f7ff fef6 bl 8009b80 + power = 0x0E - (max_power - power); + 8009d94: 79ba ldrb r2, [r7, #6] + 8009d96: 68fb ldr r3, [r7, #12] + 8009d98: b2db uxtb r3, r3 + 8009d9a: 1ad3 subs r3, r2, r3 + 8009d9c: b2db uxtb r3, r3 + 8009d9e: 330e adds r3, #14 + 8009da0: b2db uxtb r3, r3 + 8009da2: 71bb strb r3, [r7, #6] + 8009da4: e01f b.n 8009de6 + } + else if (max_power == 10) + 8009da6: 68fb ldr r3, [r7, #12] + 8009da8: 2b0a cmp r3, #10 + 8009daa: d10e bne.n 8009dca + { + SUBGRF_SetPaConfig(0x01, 0x00, 0x01, 0x01); + 8009dac: 2301 movs r3, #1 + 8009dae: 2201 movs r2, #1 + 8009db0: 2100 movs r1, #0 + 8009db2: 2001 movs r0, #1 + 8009db4: f7ff fee4 bl 8009b80 + power = 0x0D - (max_power - power); + 8009db8: 79ba ldrb r2, [r7, #6] + 8009dba: 68fb ldr r3, [r7, #12] + 8009dbc: b2db uxtb r3, r3 + 8009dbe: 1ad3 subs r3, r2, r3 + 8009dc0: b2db uxtb r3, r3 + 8009dc2: 330d adds r3, #13 + 8009dc4: b2db uxtb r3, r3 + 8009dc6: 71bb strb r3, [r7, #6] + 8009dc8: e00d b.n 8009de6 + } + else /*default 15dBm*/ + { + SUBGRF_SetPaConfig(0x07, 0x00, 0x01, 0x01); + 8009dca: 2301 movs r3, #1 + 8009dcc: 2201 movs r2, #1 + 8009dce: 2100 movs r1, #0 + 8009dd0: 2007 movs r0, #7 + 8009dd2: f7ff fed5 bl 8009b80 + power = 0x0E - (max_power - power); + 8009dd6: 79ba ldrb r2, [r7, #6] + 8009dd8: 68fb ldr r3, [r7, #12] + 8009dda: b2db uxtb r3, r3 + 8009ddc: 1ad3 subs r3, r2, r3 + 8009dde: b2db uxtb r3, r3 + 8009de0: 330e adds r3, #14 + 8009de2: b2db uxtb r3, r3 + 8009de4: 71bb strb r3, [r7, #6] + } + if (power < -17) + 8009de6: f997 3006 ldrsb.w r3, [r7, #6] + 8009dea: f113 0f11 cmn.w r3, #17 + 8009dee: da01 bge.n 8009df4 + { + power = -17; + 8009df0: 23ef movs r3, #239 @ 0xef + 8009df2: 71bb strb r3, [r7, #6] + } + SUBGRF_WriteRegister(REG_OCP, 0x18); /* current max is 80 mA for the whole device*/ + 8009df4: 2118 movs r1, #24 + 8009df6: f640 00e7 movw r0, #2279 @ 0x8e7 + 8009dfa: f000 fa8d bl 800a318 + 8009dfe: e067 b.n 8009ed0 + } + else /* rfo_hp*/ + { + /* WORKAROUND - Better Resistance of the RFO High Power Tx to Antenna Mismatch, see STM32WL Erratasheet*/ + SUBGRF_WriteRegister(REG_TX_CLAMP, SUBGRF_ReadRegister(REG_TX_CLAMP) | (0x0F << 1)); + 8009e00: f640 00d8 movw r0, #2264 @ 0x8d8 + 8009e04: f000 faaa bl 800a35c + 8009e08: 4603 mov r3, r0 + 8009e0a: f043 031e orr.w r3, r3, #30 + 8009e0e: b2db uxtb r3, r3 + 8009e10: 4619 mov r1, r3 + 8009e12: f640 00d8 movw r0, #2264 @ 0x8d8 + 8009e16: f000 fa7f bl 800a318 + /* WORKAROUND END*/ + max_power = RBI_GetRFOMaxPowerConfig(RBI_RFO_HP_MAXPOWER); + 8009e1a: 2001 movs r0, #1 + 8009e1c: f002 f8b2 bl 800bf84 + 8009e20: 60f8 str r0, [r7, #12] + if (power > max_power) + 8009e22: f997 3006 ldrsb.w r3, [r7, #6] + 8009e26: 68fa ldr r2, [r7, #12] + 8009e28: 429a cmp r2, r3 + 8009e2a: da01 bge.n 8009e30 + { + power = max_power; + 8009e2c: 68fb ldr r3, [r7, #12] + 8009e2e: 71bb strb r3, [r7, #6] + } + if (max_power == 20) + 8009e30: 68fb ldr r3, [r7, #12] + 8009e32: 2b14 cmp r3, #20 + 8009e34: d10e bne.n 8009e54 + { + SUBGRF_SetPaConfig(0x03, 0x05, 0x00, 0x01); + 8009e36: 2301 movs r3, #1 + 8009e38: 2200 movs r2, #0 + 8009e3a: 2105 movs r1, #5 + 8009e3c: 2003 movs r0, #3 + 8009e3e: f7ff fe9f bl 8009b80 + power = 0x16 - (max_power - power); + 8009e42: 79ba ldrb r2, [r7, #6] + 8009e44: 68fb ldr r3, [r7, #12] + 8009e46: b2db uxtb r3, r3 + 8009e48: 1ad3 subs r3, r2, r3 + 8009e4a: b2db uxtb r3, r3 + 8009e4c: 3316 adds r3, #22 + 8009e4e: b2db uxtb r3, r3 + 8009e50: 71bb strb r3, [r7, #6] + 8009e52: e031 b.n 8009eb8 + } + else if (max_power == 17) + 8009e54: 68fb ldr r3, [r7, #12] + 8009e56: 2b11 cmp r3, #17 + 8009e58: d10e bne.n 8009e78 + { + SUBGRF_SetPaConfig(0x02, 0x03, 0x00, 0x01); + 8009e5a: 2301 movs r3, #1 + 8009e5c: 2200 movs r2, #0 + 8009e5e: 2103 movs r1, #3 + 8009e60: 2002 movs r0, #2 + 8009e62: f7ff fe8d bl 8009b80 + power = 0x16 - (max_power - power); + 8009e66: 79ba ldrb r2, [r7, #6] + 8009e68: 68fb ldr r3, [r7, #12] + 8009e6a: b2db uxtb r3, r3 + 8009e6c: 1ad3 subs r3, r2, r3 + 8009e6e: b2db uxtb r3, r3 + 8009e70: 3316 adds r3, #22 + 8009e72: b2db uxtb r3, r3 + 8009e74: 71bb strb r3, [r7, #6] + 8009e76: e01f b.n 8009eb8 + } + else if (max_power == 14) + 8009e78: 68fb ldr r3, [r7, #12] + 8009e7a: 2b0e cmp r3, #14 + 8009e7c: d10e bne.n 8009e9c + { + SUBGRF_SetPaConfig(0x02, 0x02, 0x00, 0x01); + 8009e7e: 2301 movs r3, #1 + 8009e80: 2200 movs r2, #0 + 8009e82: 2102 movs r1, #2 + 8009e84: 2002 movs r0, #2 + 8009e86: f7ff fe7b bl 8009b80 + power = 0x0E - (max_power - power); + 8009e8a: 79ba ldrb r2, [r7, #6] + 8009e8c: 68fb ldr r3, [r7, #12] + 8009e8e: b2db uxtb r3, r3 + 8009e90: 1ad3 subs r3, r2, r3 + 8009e92: b2db uxtb r3, r3 + 8009e94: 330e adds r3, #14 + 8009e96: b2db uxtb r3, r3 + 8009e98: 71bb strb r3, [r7, #6] + 8009e9a: e00d b.n 8009eb8 + } + else /*22dBm*/ + { + SUBGRF_SetPaConfig(0x04, 0x07, 0x00, 0x01); + 8009e9c: 2301 movs r3, #1 + 8009e9e: 2200 movs r2, #0 + 8009ea0: 2107 movs r1, #7 + 8009ea2: 2004 movs r0, #4 + 8009ea4: f7ff fe6c bl 8009b80 + power = 0x16 - (max_power - power); + 8009ea8: 79ba ldrb r2, [r7, #6] + 8009eaa: 68fb ldr r3, [r7, #12] + 8009eac: b2db uxtb r3, r3 + 8009eae: 1ad3 subs r3, r2, r3 + 8009eb0: b2db uxtb r3, r3 + 8009eb2: 3316 adds r3, #22 + 8009eb4: b2db uxtb r3, r3 + 8009eb6: 71bb strb r3, [r7, #6] + } + if (power < -9) + 8009eb8: f997 3006 ldrsb.w r3, [r7, #6] + 8009ebc: f113 0f09 cmn.w r3, #9 + 8009ec0: da01 bge.n 8009ec6 + { + power = -9; + 8009ec2: 23f7 movs r3, #247 @ 0xf7 + 8009ec4: 71bb strb r3, [r7, #6] + } + SUBGRF_WriteRegister(REG_OCP, 0x38); /*current max 160mA for the whole device*/ + 8009ec6: 2138 movs r1, #56 @ 0x38 + 8009ec8: f640 00e7 movw r0, #2279 @ 0x8e7 + 8009ecc: f000 fa24 bl 800a318 + } + buf[0] = power; + 8009ed0: 79bb ldrb r3, [r7, #6] + 8009ed2: 723b strb r3, [r7, #8] + buf[1] = (uint8_t)rampTime; + 8009ed4: 797b ldrb r3, [r7, #5] + 8009ed6: 727b strb r3, [r7, #9] + SUBGRF_WriteCommand(RADIO_SET_TXPARAMS, buf, 2); + 8009ed8: f107 0308 add.w r3, r7, #8 + 8009edc: 2202 movs r2, #2 + 8009ede: 4619 mov r1, r3 + 8009ee0: 208e movs r0, #142 @ 0x8e + 8009ee2: f000 fae3 bl 800a4ac +} + 8009ee6: bf00 nop + 8009ee8: 3710 adds r7, #16 + 8009eea: 46bd mov sp, r7 + 8009eec: bd80 pop {r7, pc} + ... + +08009ef0 : + +void SUBGRF_SetModulationParams( ModulationParams_t *modulationParams ) +{ + 8009ef0: e92d 43b0 stmdb sp!, {r4, r5, r7, r8, r9, lr} + 8009ef4: b086 sub sp, #24 + 8009ef6: af00 add r7, sp, #0 + 8009ef8: 6078 str r0, [r7, #4] + uint8_t n; + uint32_t tempVal = 0; + 8009efa: 2300 movs r3, #0 + 8009efc: 617b str r3, [r7, #20] + uint8_t buf[8] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; + 8009efe: f107 0308 add.w r3, r7, #8 + 8009f02: 2200 movs r2, #0 + 8009f04: 601a str r2, [r3, #0] + 8009f06: 605a str r2, [r3, #4] + + // Check if required configuration corresponds to the stored packet type + // If not, silently update radio packet type + if( PacketType != modulationParams->PacketType ) + 8009f08: 687b ldr r3, [r7, #4] + 8009f0a: 781a ldrb r2, [r3, #0] + 8009f0c: 4b5c ldr r3, [pc, #368] @ (800a080 ) + 8009f0e: 781b ldrb r3, [r3, #0] + 8009f10: 429a cmp r2, r3 + 8009f12: d004 beq.n 8009f1e + { + SUBGRF_SetPacketType( modulationParams->PacketType ); + 8009f14: 687b ldr r3, [r7, #4] + 8009f16: 781b ldrb r3, [r3, #0] + 8009f18: 4618 mov r0, r3 + 8009f1a: f7ff fef5 bl 8009d08 + } + + switch( modulationParams->PacketType ) + 8009f1e: 687b ldr r3, [r7, #4] + 8009f20: 781b ldrb r3, [r3, #0] + 8009f22: 2b03 cmp r3, #3 + 8009f24: f200 80a5 bhi.w 800a072 + 8009f28: a201 add r2, pc, #4 @ (adr r2, 8009f30 ) + 8009f2a: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 8009f2e: bf00 nop + 8009f30: 08009f41 .word 0x08009f41 + 8009f34: 0800a001 .word 0x0800a001 + 8009f38: 08009fc3 .word 0x08009fc3 + 8009f3c: 0800a02f .word 0x0800a02f + { + case PACKET_TYPE_GFSK: + n = 8; + 8009f40: 2308 movs r3, #8 + 8009f42: 74fb strb r3, [r7, #19] + tempVal = ( uint32_t )(( 32 * XTAL_FREQ ) / modulationParams->Params.Gfsk.BitRate ); + 8009f44: 687b ldr r3, [r7, #4] + 8009f46: 685b ldr r3, [r3, #4] + 8009f48: 4a4e ldr r2, [pc, #312] @ (800a084 ) + 8009f4a: fbb2 f3f3 udiv r3, r2, r3 + 8009f4e: 617b str r3, [r7, #20] + buf[0] = ( tempVal >> 16 ) & 0xFF; + 8009f50: 697b ldr r3, [r7, #20] + 8009f52: 0c1b lsrs r3, r3, #16 + 8009f54: b2db uxtb r3, r3 + 8009f56: 723b strb r3, [r7, #8] + buf[1] = ( tempVal >> 8 ) & 0xFF; + 8009f58: 697b ldr r3, [r7, #20] + 8009f5a: 0a1b lsrs r3, r3, #8 + 8009f5c: b2db uxtb r3, r3 + 8009f5e: 727b strb r3, [r7, #9] + buf[2] = tempVal & 0xFF; + 8009f60: 697b ldr r3, [r7, #20] + 8009f62: b2db uxtb r3, r3 + 8009f64: 72bb strb r3, [r7, #10] + buf[3] = modulationParams->Params.Gfsk.ModulationShaping; + 8009f66: 687b ldr r3, [r7, #4] + 8009f68: 7b1b ldrb r3, [r3, #12] + 8009f6a: 72fb strb r3, [r7, #11] + buf[4] = modulationParams->Params.Gfsk.Bandwidth; + 8009f6c: 687b ldr r3, [r7, #4] + 8009f6e: 7b5b ldrb r3, [r3, #13] + 8009f70: 733b strb r3, [r7, #12] + SX_FREQ_TO_CHANNEL(tempVal, modulationParams->Params.Gfsk.Fdev); + 8009f72: 687b ldr r3, [r7, #4] + 8009f74: 689b ldr r3, [r3, #8] + 8009f76: 2200 movs r2, #0 + 8009f78: 461c mov r4, r3 + 8009f7a: 4615 mov r5, r2 + 8009f7c: ea4f 19d4 mov.w r9, r4, lsr #7 + 8009f80: ea4f 6844 mov.w r8, r4, lsl #25 + 8009f84: 4a40 ldr r2, [pc, #256] @ (800a088 ) + 8009f86: f04f 0300 mov.w r3, #0 + 8009f8a: 4640 mov r0, r8 + 8009f8c: 4649 mov r1, r9 + 8009f8e: f7f6 f8fb bl 8000188 <__aeabi_uldivmod> + 8009f92: 4602 mov r2, r0 + 8009f94: 460b mov r3, r1 + 8009f96: 4613 mov r3, r2 + 8009f98: 617b str r3, [r7, #20] + buf[5] = ( tempVal >> 16 ) & 0xFF; + 8009f9a: 697b ldr r3, [r7, #20] + 8009f9c: 0c1b lsrs r3, r3, #16 + 8009f9e: b2db uxtb r3, r3 + 8009fa0: 737b strb r3, [r7, #13] + buf[6] = ( tempVal >> 8 ) & 0xFF; + 8009fa2: 697b ldr r3, [r7, #20] + 8009fa4: 0a1b lsrs r3, r3, #8 + 8009fa6: b2db uxtb r3, r3 + 8009fa8: 73bb strb r3, [r7, #14] + buf[7] = ( tempVal& 0xFF ); + 8009faa: 697b ldr r3, [r7, #20] + 8009fac: b2db uxtb r3, r3 + 8009fae: 73fb strb r3, [r7, #15] + SUBGRF_WriteCommand( RADIO_SET_MODULATIONPARAMS, buf, n ); + 8009fb0: 7cfb ldrb r3, [r7, #19] + 8009fb2: b29a uxth r2, r3 + 8009fb4: f107 0308 add.w r3, r7, #8 + 8009fb8: 4619 mov r1, r3 + 8009fba: 208b movs r0, #139 @ 0x8b + 8009fbc: f000 fa76 bl 800a4ac + break; + 8009fc0: e058 b.n 800a074 + case PACKET_TYPE_BPSK: + n = 4; + 8009fc2: 2304 movs r3, #4 + 8009fc4: 74fb strb r3, [r7, #19] + tempVal = ( uint32_t ) (( 32 * XTAL_FREQ) / modulationParams->Params.Bpsk.BitRate ); + 8009fc6: 687b ldr r3, [r7, #4] + 8009fc8: 691b ldr r3, [r3, #16] + 8009fca: 4a2e ldr r2, [pc, #184] @ (800a084 ) + 8009fcc: fbb2 f3f3 udiv r3, r2, r3 + 8009fd0: 617b str r3, [r7, #20] + buf[0] = ( tempVal >> 16 ) & 0xFF; + 8009fd2: 697b ldr r3, [r7, #20] + 8009fd4: 0c1b lsrs r3, r3, #16 + 8009fd6: b2db uxtb r3, r3 + 8009fd8: 723b strb r3, [r7, #8] + buf[1] = ( tempVal >> 8 ) & 0xFF; + 8009fda: 697b ldr r3, [r7, #20] + 8009fdc: 0a1b lsrs r3, r3, #8 + 8009fde: b2db uxtb r3, r3 + 8009fe0: 727b strb r3, [r7, #9] + buf[2] = tempVal & 0xFF; + 8009fe2: 697b ldr r3, [r7, #20] + 8009fe4: b2db uxtb r3, r3 + 8009fe6: 72bb strb r3, [r7, #10] + buf[3] = modulationParams->Params.Bpsk.ModulationShaping; + 8009fe8: 687b ldr r3, [r7, #4] + 8009fea: 7d1b ldrb r3, [r3, #20] + 8009fec: 72fb strb r3, [r7, #11] + SUBGRF_WriteCommand( RADIO_SET_MODULATIONPARAMS, buf, n ); + 8009fee: 7cfb ldrb r3, [r7, #19] + 8009ff0: b29a uxth r2, r3 + 8009ff2: f107 0308 add.w r3, r7, #8 + 8009ff6: 4619 mov r1, r3 + 8009ff8: 208b movs r0, #139 @ 0x8b + 8009ffa: f000 fa57 bl 800a4ac + break; + 8009ffe: e039 b.n 800a074 + case PACKET_TYPE_LORA: + n = 4; + 800a000: 2304 movs r3, #4 + 800a002: 74fb strb r3, [r7, #19] + buf[0] = modulationParams->Params.LoRa.SpreadingFactor; + 800a004: 687b ldr r3, [r7, #4] + 800a006: 7e1b ldrb r3, [r3, #24] + 800a008: 723b strb r3, [r7, #8] + buf[1] = modulationParams->Params.LoRa.Bandwidth; + 800a00a: 687b ldr r3, [r7, #4] + 800a00c: 7e5b ldrb r3, [r3, #25] + 800a00e: 727b strb r3, [r7, #9] + buf[2] = modulationParams->Params.LoRa.CodingRate; + 800a010: 687b ldr r3, [r7, #4] + 800a012: 7e9b ldrb r3, [r3, #26] + 800a014: 72bb strb r3, [r7, #10] + buf[3] = modulationParams->Params.LoRa.LowDatarateOptimize; + 800a016: 687b ldr r3, [r7, #4] + 800a018: 7edb ldrb r3, [r3, #27] + 800a01a: 72fb strb r3, [r7, #11] + + SUBGRF_WriteCommand( RADIO_SET_MODULATIONPARAMS, buf, n ); + 800a01c: 7cfb ldrb r3, [r7, #19] + 800a01e: b29a uxth r2, r3 + 800a020: f107 0308 add.w r3, r7, #8 + 800a024: 4619 mov r1, r3 + 800a026: 208b movs r0, #139 @ 0x8b + 800a028: f000 fa40 bl 800a4ac + + break; + 800a02c: e022 b.n 800a074 + case PACKET_TYPE_GMSK: + n = 5; + 800a02e: 2305 movs r3, #5 + 800a030: 74fb strb r3, [r7, #19] + tempVal = ( uint32_t )(( 32 *XTAL_FREQ) / modulationParams->Params.Gfsk.BitRate ); + 800a032: 687b ldr r3, [r7, #4] + 800a034: 685b ldr r3, [r3, #4] + 800a036: 4a13 ldr r2, [pc, #76] @ (800a084 ) + 800a038: fbb2 f3f3 udiv r3, r2, r3 + 800a03c: 617b str r3, [r7, #20] + buf[0] = ( tempVal >> 16 ) & 0xFF; + 800a03e: 697b ldr r3, [r7, #20] + 800a040: 0c1b lsrs r3, r3, #16 + 800a042: b2db uxtb r3, r3 + 800a044: 723b strb r3, [r7, #8] + buf[1] = ( tempVal >> 8 ) & 0xFF; + 800a046: 697b ldr r3, [r7, #20] + 800a048: 0a1b lsrs r3, r3, #8 + 800a04a: b2db uxtb r3, r3 + 800a04c: 727b strb r3, [r7, #9] + buf[2] = tempVal & 0xFF; + 800a04e: 697b ldr r3, [r7, #20] + 800a050: b2db uxtb r3, r3 + 800a052: 72bb strb r3, [r7, #10] + buf[3] = modulationParams->Params.Gfsk.ModulationShaping; + 800a054: 687b ldr r3, [r7, #4] + 800a056: 7b1b ldrb r3, [r3, #12] + 800a058: 72fb strb r3, [r7, #11] + buf[4] = modulationParams->Params.Gfsk.Bandwidth; + 800a05a: 687b ldr r3, [r7, #4] + 800a05c: 7b5b ldrb r3, [r3, #13] + 800a05e: 733b strb r3, [r7, #12] + SUBGRF_WriteCommand( RADIO_SET_MODULATIONPARAMS, buf, n ); + 800a060: 7cfb ldrb r3, [r7, #19] + 800a062: b29a uxth r2, r3 + 800a064: f107 0308 add.w r3, r7, #8 + 800a068: 4619 mov r1, r3 + 800a06a: 208b movs r0, #139 @ 0x8b + 800a06c: f000 fa1e bl 800a4ac + break; + 800a070: e000 b.n 800a074 + default: + case PACKET_TYPE_NONE: + break; + 800a072: bf00 nop + } +} + 800a074: bf00 nop + 800a076: 3718 adds r7, #24 + 800a078: 46bd mov sp, r7 + 800a07a: e8bd 83b0 ldmia.w sp!, {r4, r5, r7, r8, r9, pc} + 800a07e: bf00 nop + 800a080: 2000031d .word 0x2000031d + 800a084: 3d090000 .word 0x3d090000 + 800a088: 01e84800 .word 0x01e84800 + +0800a08c : + +void SUBGRF_SetPacketParams( PacketParams_t *packetParams ) +{ + 800a08c: b580 push {r7, lr} + 800a08e: b086 sub sp, #24 + 800a090: af00 add r7, sp, #0 + 800a092: 6078 str r0, [r7, #4] + uint8_t n; + uint8_t crcVal = 0; + 800a094: 2300 movs r3, #0 + 800a096: 75bb strb r3, [r7, #22] + uint8_t buf[9] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; + 800a098: f107 030c add.w r3, r7, #12 + 800a09c: 2200 movs r2, #0 + 800a09e: 601a str r2, [r3, #0] + 800a0a0: 605a str r2, [r3, #4] + 800a0a2: 721a strb r2, [r3, #8] + + // Check if required configuration corresponds to the stored packet type + // If not, silently update radio packet type + if( PacketType != packetParams->PacketType ) + 800a0a4: 687b ldr r3, [r7, #4] + 800a0a6: 781a ldrb r2, [r3, #0] + 800a0a8: 4b44 ldr r3, [pc, #272] @ (800a1bc ) + 800a0aa: 781b ldrb r3, [r3, #0] + 800a0ac: 429a cmp r2, r3 + 800a0ae: d004 beq.n 800a0ba + { + SUBGRF_SetPacketType( packetParams->PacketType ); + 800a0b0: 687b ldr r3, [r7, #4] + 800a0b2: 781b ldrb r3, [r3, #0] + 800a0b4: 4618 mov r0, r3 + 800a0b6: f7ff fe27 bl 8009d08 + } + + switch( packetParams->PacketType ) + 800a0ba: 687b ldr r3, [r7, #4] + 800a0bc: 781b ldrb r3, [r3, #0] + 800a0be: 2b03 cmp r3, #3 + 800a0c0: d878 bhi.n 800a1b4 + 800a0c2: a201 add r2, pc, #4 @ (adr r2, 800a0c8 ) + 800a0c4: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 800a0c8: 0800a0d9 .word 0x0800a0d9 + 800a0cc: 0800a169 .word 0x0800a169 + 800a0d0: 0800a15d .word 0x0800a15d + 800a0d4: 0800a0d9 .word 0x0800a0d9 + { + case PACKET_TYPE_GMSK: + case PACKET_TYPE_GFSK: + if( packetParams->Params.Gfsk.CrcLength == RADIO_CRC_2_BYTES_IBM ) + 800a0d8: 687b ldr r3, [r7, #4] + 800a0da: 7a5b ldrb r3, [r3, #9] + 800a0dc: 2bf1 cmp r3, #241 @ 0xf1 + 800a0de: d10a bne.n 800a0f6 + { + SUBGRF_SetCrcSeed( CRC_IBM_SEED ); + 800a0e0: f64f 70ff movw r0, #65535 @ 0xffff + 800a0e4: f7ff faa6 bl 8009634 + SUBGRF_SetCrcPolynomial( CRC_POLYNOMIAL_IBM ); + 800a0e8: f248 0005 movw r0, #32773 @ 0x8005 + 800a0ec: f7ff fac2 bl 8009674 + crcVal = RADIO_CRC_2_BYTES; + 800a0f0: 2302 movs r3, #2 + 800a0f2: 75bb strb r3, [r7, #22] + 800a0f4: e011 b.n 800a11a + } + else if( packetParams->Params.Gfsk.CrcLength == RADIO_CRC_2_BYTES_CCIT ) + 800a0f6: 687b ldr r3, [r7, #4] + 800a0f8: 7a5b ldrb r3, [r3, #9] + 800a0fa: 2bf2 cmp r3, #242 @ 0xf2 + 800a0fc: d10a bne.n 800a114 + { + SUBGRF_SetCrcSeed( CRC_CCITT_SEED ); + 800a0fe: f641 500f movw r0, #7439 @ 0x1d0f + 800a102: f7ff fa97 bl 8009634 + SUBGRF_SetCrcPolynomial( CRC_POLYNOMIAL_CCITT ); + 800a106: f241 0021 movw r0, #4129 @ 0x1021 + 800a10a: f7ff fab3 bl 8009674 + crcVal = RADIO_CRC_2_BYTES_INV; + 800a10e: 2306 movs r3, #6 + 800a110: 75bb strb r3, [r7, #22] + 800a112: e002 b.n 800a11a + } + else + { + crcVal = packetParams->Params.Gfsk.CrcLength; + 800a114: 687b ldr r3, [r7, #4] + 800a116: 7a5b ldrb r3, [r3, #9] + 800a118: 75bb strb r3, [r7, #22] + } + n = 9; + 800a11a: 2309 movs r3, #9 + 800a11c: 75fb strb r3, [r7, #23] + buf[0] = ( packetParams->Params.Gfsk.PreambleLength >> 8 ) & 0xFF; + 800a11e: 687b ldr r3, [r7, #4] + 800a120: 885b ldrh r3, [r3, #2] + 800a122: 0a1b lsrs r3, r3, #8 + 800a124: b29b uxth r3, r3 + 800a126: b2db uxtb r3, r3 + 800a128: 733b strb r3, [r7, #12] + buf[1] = packetParams->Params.Gfsk.PreambleLength; + 800a12a: 687b ldr r3, [r7, #4] + 800a12c: 885b ldrh r3, [r3, #2] + 800a12e: b2db uxtb r3, r3 + 800a130: 737b strb r3, [r7, #13] + buf[2] = packetParams->Params.Gfsk.PreambleMinDetect; + 800a132: 687b ldr r3, [r7, #4] + 800a134: 791b ldrb r3, [r3, #4] + 800a136: 73bb strb r3, [r7, #14] + buf[3] = ( packetParams->Params.Gfsk.SyncWordLength /*<< 3*/ ); // convert from byte to bit + 800a138: 687b ldr r3, [r7, #4] + 800a13a: 795b ldrb r3, [r3, #5] + 800a13c: 73fb strb r3, [r7, #15] + buf[4] = packetParams->Params.Gfsk.AddrComp; + 800a13e: 687b ldr r3, [r7, #4] + 800a140: 799b ldrb r3, [r3, #6] + 800a142: 743b strb r3, [r7, #16] + buf[5] = packetParams->Params.Gfsk.HeaderType; + 800a144: 687b ldr r3, [r7, #4] + 800a146: 79db ldrb r3, [r3, #7] + 800a148: 747b strb r3, [r7, #17] + buf[6] = packetParams->Params.Gfsk.PayloadLength; + 800a14a: 687b ldr r3, [r7, #4] + 800a14c: 7a1b ldrb r3, [r3, #8] + 800a14e: 74bb strb r3, [r7, #18] + buf[7] = crcVal; + 800a150: 7dbb ldrb r3, [r7, #22] + 800a152: 74fb strb r3, [r7, #19] + buf[8] = packetParams->Params.Gfsk.DcFree; + 800a154: 687b ldr r3, [r7, #4] + 800a156: 7a9b ldrb r3, [r3, #10] + 800a158: 753b strb r3, [r7, #20] + break; + 800a15a: e022 b.n 800a1a2 + case PACKET_TYPE_BPSK: + n = 1; + 800a15c: 2301 movs r3, #1 + 800a15e: 75fb strb r3, [r7, #23] + buf[0] = packetParams->Params.Bpsk.PayloadLength; + 800a160: 687b ldr r3, [r7, #4] + 800a162: 7b1b ldrb r3, [r3, #12] + 800a164: 733b strb r3, [r7, #12] + break; + 800a166: e01c b.n 800a1a2 + case PACKET_TYPE_LORA: + n = 6; + 800a168: 2306 movs r3, #6 + 800a16a: 75fb strb r3, [r7, #23] + buf[0] = ( packetParams->Params.LoRa.PreambleLength >> 8 ) & 0xFF; + 800a16c: 687b ldr r3, [r7, #4] + 800a16e: 89db ldrh r3, [r3, #14] + 800a170: 0a1b lsrs r3, r3, #8 + 800a172: b29b uxth r3, r3 + 800a174: b2db uxtb r3, r3 + 800a176: 733b strb r3, [r7, #12] + buf[1] = packetParams->Params.LoRa.PreambleLength; + 800a178: 687b ldr r3, [r7, #4] + 800a17a: 89db ldrh r3, [r3, #14] + 800a17c: b2db uxtb r3, r3 + 800a17e: 737b strb r3, [r7, #13] + buf[2] = LoRaHeaderType = packetParams->Params.LoRa.HeaderType; + 800a180: 687b ldr r3, [r7, #4] + 800a182: 7c1a ldrb r2, [r3, #16] + 800a184: 4b0e ldr r3, [pc, #56] @ (800a1c0 ) + 800a186: 4611 mov r1, r2 + 800a188: 7019 strb r1, [r3, #0] + 800a18a: 4613 mov r3, r2 + 800a18c: 73bb strb r3, [r7, #14] + buf[3] = packetParams->Params.LoRa.PayloadLength; + 800a18e: 687b ldr r3, [r7, #4] + 800a190: 7c5b ldrb r3, [r3, #17] + 800a192: 73fb strb r3, [r7, #15] + buf[4] = packetParams->Params.LoRa.CrcMode; + 800a194: 687b ldr r3, [r7, #4] + 800a196: 7c9b ldrb r3, [r3, #18] + 800a198: 743b strb r3, [r7, #16] + buf[5] = packetParams->Params.LoRa.InvertIQ; + 800a19a: 687b ldr r3, [r7, #4] + 800a19c: 7cdb ldrb r3, [r3, #19] + 800a19e: 747b strb r3, [r7, #17] + break; + 800a1a0: bf00 nop + default: + case PACKET_TYPE_NONE: + return; + } + SUBGRF_WriteCommand( RADIO_SET_PACKETPARAMS, buf, n ); + 800a1a2: 7dfb ldrb r3, [r7, #23] + 800a1a4: b29a uxth r2, r3 + 800a1a6: f107 030c add.w r3, r7, #12 + 800a1aa: 4619 mov r1, r3 + 800a1ac: 208c movs r0, #140 @ 0x8c + 800a1ae: f000 f97d bl 800a4ac + 800a1b2: e000 b.n 800a1b6 + return; + 800a1b4: bf00 nop +} + 800a1b6: 3718 adds r7, #24 + 800a1b8: 46bd mov sp, r7 + 800a1ba: bd80 pop {r7, pc} + 800a1bc: 2000031d .word 0x2000031d + 800a1c0: 2000031e .word 0x2000031e + +0800a1c4 : + SUBGRF_WriteCommand( RADIO_SET_CADPARAMS, buf, 7 ); + OperatingMode = MODE_CAD; +} + +void SUBGRF_SetBufferBaseAddress( uint8_t txBaseAddress, uint8_t rxBaseAddress ) +{ + 800a1c4: b580 push {r7, lr} + 800a1c6: b084 sub sp, #16 + 800a1c8: af00 add r7, sp, #0 + 800a1ca: 4603 mov r3, r0 + 800a1cc: 460a mov r2, r1 + 800a1ce: 71fb strb r3, [r7, #7] + 800a1d0: 4613 mov r3, r2 + 800a1d2: 71bb strb r3, [r7, #6] + uint8_t buf[2]; + + buf[0] = txBaseAddress; + 800a1d4: 79fb ldrb r3, [r7, #7] + 800a1d6: 733b strb r3, [r7, #12] + buf[1] = rxBaseAddress; + 800a1d8: 79bb ldrb r3, [r7, #6] + 800a1da: 737b strb r3, [r7, #13] + SUBGRF_WriteCommand( RADIO_SET_BUFFERBASEADDRESS, buf, 2 ); + 800a1dc: f107 030c add.w r3, r7, #12 + 800a1e0: 2202 movs r2, #2 + 800a1e2: 4619 mov r1, r3 + 800a1e4: 208f movs r0, #143 @ 0x8f + 800a1e6: f000 f961 bl 800a4ac +} + 800a1ea: bf00 nop + 800a1ec: 3710 adds r7, #16 + 800a1ee: 46bd mov sp, r7 + 800a1f0: bd80 pop {r7, pc} + +0800a1f2 : + status.Fields.ChipMode = ( stat & ( 0x07 << 4 ) ) >> 4; + return status; +} + +int8_t SUBGRF_GetRssiInst( void ) +{ + 800a1f2: b580 push {r7, lr} + 800a1f4: b082 sub sp, #8 + 800a1f6: af00 add r7, sp, #0 + uint8_t buf[1]; + int8_t rssi = 0; + 800a1f8: 2300 movs r3, #0 + 800a1fa: 71fb strb r3, [r7, #7] + + SUBGRF_ReadCommand( RADIO_GET_RSSIINST, buf, 1 ); + 800a1fc: 1d3b adds r3, r7, #4 + 800a1fe: 2201 movs r2, #1 + 800a200: 4619 mov r1, r3 + 800a202: 2015 movs r0, #21 + 800a204: f000 f974 bl 800a4f0 + rssi = -buf[0] >> 1; + 800a208: 793b ldrb r3, [r7, #4] + 800a20a: 425b negs r3, r3 + 800a20c: 105b asrs r3, r3, #1 + 800a20e: 71fb strb r3, [r7, #7] + return rssi; + 800a210: f997 3007 ldrsb.w r3, [r7, #7] +} + 800a214: 4618 mov r0, r3 + 800a216: 3708 adds r7, #8 + 800a218: 46bd mov sp, r7 + 800a21a: bd80 pop {r7, pc} + +0800a21c : + +void SUBGRF_GetRxBufferStatus( uint8_t *payloadLength, uint8_t *rxStartBufferPointer ) +{ + 800a21c: b580 push {r7, lr} + 800a21e: b084 sub sp, #16 + 800a220: af00 add r7, sp, #0 + 800a222: 6078 str r0, [r7, #4] + 800a224: 6039 str r1, [r7, #0] + uint8_t status[2]; + + SUBGRF_ReadCommand( RADIO_GET_RXBUFFERSTATUS, status, 2 ); + 800a226: f107 030c add.w r3, r7, #12 + 800a22a: 2202 movs r2, #2 + 800a22c: 4619 mov r1, r3 + 800a22e: 2013 movs r0, #19 + 800a230: f000 f95e bl 800a4f0 + + // In case of LORA fixed header, the payloadLength is obtained by reading + // the register REG_LR_PAYLOADLENGTH + if( ( SUBGRF_GetPacketType( ) == PACKET_TYPE_LORA ) && ( LoRaHeaderType == LORA_PACKET_FIXED_LENGTH ) ) + 800a234: f7ff fd84 bl 8009d40 + 800a238: 4603 mov r3, r0 + 800a23a: 2b01 cmp r3, #1 + 800a23c: d10d bne.n 800a25a + 800a23e: 4b0c ldr r3, [pc, #48] @ (800a270 ) + 800a240: 781b ldrb r3, [r3, #0] + 800a242: b2db uxtb r3, r3 + 800a244: 2b01 cmp r3, #1 + 800a246: d108 bne.n 800a25a + { + *payloadLength = SUBGRF_ReadRegister( REG_LR_PAYLOADLENGTH ); + 800a248: f240 7002 movw r0, #1794 @ 0x702 + 800a24c: f000 f886 bl 800a35c + 800a250: 4603 mov r3, r0 + 800a252: 461a mov r2, r3 + 800a254: 687b ldr r3, [r7, #4] + 800a256: 701a strb r2, [r3, #0] + 800a258: e002 b.n 800a260 + } + else + { + *payloadLength = status[0]; + 800a25a: 7b3a ldrb r2, [r7, #12] + 800a25c: 687b ldr r3, [r7, #4] + 800a25e: 701a strb r2, [r3, #0] + } + *rxStartBufferPointer = status[1]; + 800a260: 7b7a ldrb r2, [r7, #13] + 800a262: 683b ldr r3, [r7, #0] + 800a264: 701a strb r2, [r3, #0] +} + 800a266: bf00 nop + 800a268: 3710 adds r7, #16 + 800a26a: 46bd mov sp, r7 + 800a26c: bd80 pop {r7, pc} + 800a26e: bf00 nop + 800a270: 2000031e .word 0x2000031e + +0800a274 : + +void SUBGRF_GetPacketStatus( PacketStatus_t *pktStatus ) +{ + 800a274: b580 push {r7, lr} + 800a276: b084 sub sp, #16 + 800a278: af00 add r7, sp, #0 + 800a27a: 6078 str r0, [r7, #4] + uint8_t status[3]; + + SUBGRF_ReadCommand( RADIO_GET_PACKETSTATUS, status, 3 ); + 800a27c: f107 030c add.w r3, r7, #12 + 800a280: 2203 movs r2, #3 + 800a282: 4619 mov r1, r3 + 800a284: 2014 movs r0, #20 + 800a286: f000 f933 bl 800a4f0 + + pktStatus->packetType = SUBGRF_GetPacketType( ); + 800a28a: f7ff fd59 bl 8009d40 + 800a28e: 4603 mov r3, r0 + 800a290: 461a mov r2, r3 + 800a292: 687b ldr r3, [r7, #4] + 800a294: 701a strb r2, [r3, #0] + switch( pktStatus->packetType ) + 800a296: 687b ldr r3, [r7, #4] + 800a298: 781b ldrb r3, [r3, #0] + 800a29a: 2b00 cmp r3, #0 + 800a29c: d002 beq.n 800a2a4 + 800a29e: 2b01 cmp r3, #1 + 800a2a0: d013 beq.n 800a2ca + 800a2a2: e02a b.n 800a2fa + { + case PACKET_TYPE_GFSK: + pktStatus->Params.Gfsk.RxStatus = status[0]; + 800a2a4: 7b3a ldrb r2, [r7, #12] + 800a2a6: 687b ldr r3, [r7, #4] + 800a2a8: 711a strb r2, [r3, #4] + pktStatus->Params.Gfsk.RssiSync = -status[1] >> 1; + 800a2aa: 7b7b ldrb r3, [r7, #13] + 800a2ac: 425b negs r3, r3 + 800a2ae: 105b asrs r3, r3, #1 + 800a2b0: b25a sxtb r2, r3 + 800a2b2: 687b ldr r3, [r7, #4] + 800a2b4: 719a strb r2, [r3, #6] + pktStatus->Params.Gfsk.RssiAvg = -status[2] >> 1; + 800a2b6: 7bbb ldrb r3, [r7, #14] + 800a2b8: 425b negs r3, r3 + 800a2ba: 105b asrs r3, r3, #1 + 800a2bc: b25a sxtb r2, r3 + 800a2be: 687b ldr r3, [r7, #4] + 800a2c0: 715a strb r2, [r3, #5] + pktStatus->Params.Gfsk.FreqError = 0; + 800a2c2: 687b ldr r3, [r7, #4] + 800a2c4: 2200 movs r2, #0 + 800a2c6: 609a str r2, [r3, #8] + break; + 800a2c8: e020 b.n 800a30c + + case PACKET_TYPE_LORA: + pktStatus->Params.LoRa.RssiPkt = -status[0] >> 1; + 800a2ca: 7b3b ldrb r3, [r7, #12] + 800a2cc: 425b negs r3, r3 + 800a2ce: 105b asrs r3, r3, #1 + 800a2d0: b25a sxtb r2, r3 + 800a2d2: 687b ldr r3, [r7, #4] + 800a2d4: 731a strb r2, [r3, #12] + // Returns SNR value [dB] rounded to the nearest integer value + pktStatus->Params.LoRa.SnrPkt = ( ( ( int8_t )status[1] ) + 2 ) >> 2; + 800a2d6: 7b7b ldrb r3, [r7, #13] + 800a2d8: b25b sxtb r3, r3 + 800a2da: 3302 adds r3, #2 + 800a2dc: 109b asrs r3, r3, #2 + 800a2de: b25a sxtb r2, r3 + 800a2e0: 687b ldr r3, [r7, #4] + 800a2e2: 735a strb r2, [r3, #13] + pktStatus->Params.LoRa.SignalRssiPkt = -status[2] >> 1; + 800a2e4: 7bbb ldrb r3, [r7, #14] + 800a2e6: 425b negs r3, r3 + 800a2e8: 105b asrs r3, r3, #1 + 800a2ea: b25a sxtb r2, r3 + 800a2ec: 687b ldr r3, [r7, #4] + 800a2ee: 739a strb r2, [r3, #14] + pktStatus->Params.LoRa.FreqError = FrequencyError; + 800a2f0: 4b08 ldr r3, [pc, #32] @ (800a314 ) + 800a2f2: 681a ldr r2, [r3, #0] + 800a2f4: 687b ldr r3, [r7, #4] + 800a2f6: 611a str r2, [r3, #16] + break; + 800a2f8: e008 b.n 800a30c + + default: + case PACKET_TYPE_NONE: + // In that specific case, we set everything in the pktStatus to zeros + // and reset the packet type accordingly + RADIO_MEMSET8( pktStatus, 0, sizeof( PacketStatus_t ) ); + 800a2fa: 2214 movs r2, #20 + 800a2fc: 2100 movs r1, #0 + 800a2fe: 6878 ldr r0, [r7, #4] + 800a300: f001 ff13 bl 800c12a + pktStatus->packetType = PACKET_TYPE_NONE; + 800a304: 687b ldr r3, [r7, #4] + 800a306: 220f movs r2, #15 + 800a308: 701a strb r2, [r3, #0] + break; + 800a30a: bf00 nop + } +} + 800a30c: bf00 nop + 800a30e: 3710 adds r7, #16 + 800a310: 46bd mov sp, r7 + 800a312: bd80 pop {r7, pc} + 800a314: 20000320 .word 0x20000320 + +0800a318 : + buf[1] = ( uint8_t )( ( uint16_t )irq & 0x00FF ); + SUBGRF_WriteCommand( RADIO_CLR_IRQSTATUS, buf, 2 ); +} + +void SUBGRF_WriteRegister( uint16_t addr, uint8_t data ) +{ + 800a318: b580 push {r7, lr} + 800a31a: b086 sub sp, #24 + 800a31c: af00 add r7, sp, #0 + 800a31e: 4603 mov r3, r0 + 800a320: 460a mov r2, r1 + 800a322: 80fb strh r3, [r7, #6] + 800a324: 4613 mov r3, r2 + 800a326: 717b strb r3, [r7, #5] + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 800a328: f3ef 8310 mrs r3, PRIMASK + 800a32c: 60fb str r3, [r7, #12] + return(result); + 800a32e: 68fb ldr r3, [r7, #12] + CRITICAL_SECTION_BEGIN(); + 800a330: 617b str r3, [r7, #20] + __ASM volatile ("cpsid i" : : : "memory"); + 800a332: b672 cpsid i +} + 800a334: bf00 nop + HAL_SUBGHZ_WriteRegisters( &hsubghz, addr, (uint8_t*)&data, 1 ); + 800a336: 1d7a adds r2, r7, #5 + 800a338: 88f9 ldrh r1, [r7, #6] + 800a33a: 2301 movs r3, #1 + 800a33c: 4806 ldr r0, [pc, #24] @ (800a358 ) + 800a33e: f7fa fa95 bl 800486c + 800a342: 697b ldr r3, [r7, #20] + 800a344: 613b str r3, [r7, #16] + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 800a346: 693b ldr r3, [r7, #16] + 800a348: f383 8810 msr PRIMASK, r3 +} + 800a34c: bf00 nop + CRITICAL_SECTION_END(); +} + 800a34e: bf00 nop + 800a350: 3718 adds r7, #24 + 800a352: 46bd mov sp, r7 + 800a354: bd80 pop {r7, pc} + 800a356: bf00 nop + 800a358: 20000078 .word 0x20000078 + +0800a35c : + +uint8_t SUBGRF_ReadRegister( uint16_t addr ) +{ + 800a35c: b580 push {r7, lr} + 800a35e: b086 sub sp, #24 + 800a360: af00 add r7, sp, #0 + 800a362: 4603 mov r3, r0 + 800a364: 80fb strh r3, [r7, #6] + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 800a366: f3ef 8310 mrs r3, PRIMASK + 800a36a: 60fb str r3, [r7, #12] + return(result); + 800a36c: 68fb ldr r3, [r7, #12] + uint8_t data; + CRITICAL_SECTION_BEGIN(); + 800a36e: 617b str r3, [r7, #20] + __ASM volatile ("cpsid i" : : : "memory"); + 800a370: b672 cpsid i +} + 800a372: bf00 nop + HAL_SUBGHZ_ReadRegisters( &hsubghz, addr, &data, 1 ); + 800a374: f107 020b add.w r2, r7, #11 + 800a378: 88f9 ldrh r1, [r7, #6] + 800a37a: 2301 movs r3, #1 + 800a37c: 4806 ldr r0, [pc, #24] @ (800a398 ) + 800a37e: f7fa fad4 bl 800492a + 800a382: 697b ldr r3, [r7, #20] + 800a384: 613b str r3, [r7, #16] + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 800a386: 693b ldr r3, [r7, #16] + 800a388: f383 8810 msr PRIMASK, r3 +} + 800a38c: bf00 nop + CRITICAL_SECTION_END(); + return data; + 800a38e: 7afb ldrb r3, [r7, #11] +} + 800a390: 4618 mov r0, r3 + 800a392: 3718 adds r7, #24 + 800a394: 46bd mov sp, r7 + 800a396: bd80 pop {r7, pc} + 800a398: 20000078 .word 0x20000078 + +0800a39c : + +void SUBGRF_WriteRegisters( uint16_t address, uint8_t *buffer, uint16_t size ) +{ + 800a39c: b580 push {r7, lr} + 800a39e: b086 sub sp, #24 + 800a3a0: af00 add r7, sp, #0 + 800a3a2: 4603 mov r3, r0 + 800a3a4: 6039 str r1, [r7, #0] + 800a3a6: 80fb strh r3, [r7, #6] + 800a3a8: 4613 mov r3, r2 + 800a3aa: 80bb strh r3, [r7, #4] + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 800a3ac: f3ef 8310 mrs r3, PRIMASK + 800a3b0: 60fb str r3, [r7, #12] + return(result); + 800a3b2: 68fb ldr r3, [r7, #12] + CRITICAL_SECTION_BEGIN(); + 800a3b4: 617b str r3, [r7, #20] + __ASM volatile ("cpsid i" : : : "memory"); + 800a3b6: b672 cpsid i +} + 800a3b8: bf00 nop + HAL_SUBGHZ_WriteRegisters( &hsubghz, address, buffer, size ); + 800a3ba: 88bb ldrh r3, [r7, #4] + 800a3bc: 88f9 ldrh r1, [r7, #6] + 800a3be: 683a ldr r2, [r7, #0] + 800a3c0: 4806 ldr r0, [pc, #24] @ (800a3dc ) + 800a3c2: f7fa fa53 bl 800486c + 800a3c6: 697b ldr r3, [r7, #20] + 800a3c8: 613b str r3, [r7, #16] + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 800a3ca: 693b ldr r3, [r7, #16] + 800a3cc: f383 8810 msr PRIMASK, r3 +} + 800a3d0: bf00 nop + CRITICAL_SECTION_END(); +} + 800a3d2: bf00 nop + 800a3d4: 3718 adds r7, #24 + 800a3d6: 46bd mov sp, r7 + 800a3d8: bd80 pop {r7, pc} + 800a3da: bf00 nop + 800a3dc: 20000078 .word 0x20000078 + +0800a3e0 : + +void SUBGRF_ReadRegisters( uint16_t address, uint8_t *buffer, uint16_t size ) +{ + 800a3e0: b580 push {r7, lr} + 800a3e2: b086 sub sp, #24 + 800a3e4: af00 add r7, sp, #0 + 800a3e6: 4603 mov r3, r0 + 800a3e8: 6039 str r1, [r7, #0] + 800a3ea: 80fb strh r3, [r7, #6] + 800a3ec: 4613 mov r3, r2 + 800a3ee: 80bb strh r3, [r7, #4] + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 800a3f0: f3ef 8310 mrs r3, PRIMASK + 800a3f4: 60fb str r3, [r7, #12] + return(result); + 800a3f6: 68fb ldr r3, [r7, #12] + CRITICAL_SECTION_BEGIN(); + 800a3f8: 617b str r3, [r7, #20] + __ASM volatile ("cpsid i" : : : "memory"); + 800a3fa: b672 cpsid i +} + 800a3fc: bf00 nop + HAL_SUBGHZ_ReadRegisters( &hsubghz, address, buffer, size ); + 800a3fe: 88bb ldrh r3, [r7, #4] + 800a400: 88f9 ldrh r1, [r7, #6] + 800a402: 683a ldr r2, [r7, #0] + 800a404: 4806 ldr r0, [pc, #24] @ (800a420 ) + 800a406: f7fa fa90 bl 800492a + 800a40a: 697b ldr r3, [r7, #20] + 800a40c: 613b str r3, [r7, #16] + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 800a40e: 693b ldr r3, [r7, #16] + 800a410: f383 8810 msr PRIMASK, r3 +} + 800a414: bf00 nop + CRITICAL_SECTION_END(); +} + 800a416: bf00 nop + 800a418: 3718 adds r7, #24 + 800a41a: 46bd mov sp, r7 + 800a41c: bd80 pop {r7, pc} + 800a41e: bf00 nop + 800a420: 20000078 .word 0x20000078 + +0800a424 : + +void SUBGRF_WriteBuffer( uint8_t offset, uint8_t *buffer, uint8_t size ) +{ + 800a424: b580 push {r7, lr} + 800a426: b086 sub sp, #24 + 800a428: af00 add r7, sp, #0 + 800a42a: 4603 mov r3, r0 + 800a42c: 6039 str r1, [r7, #0] + 800a42e: 71fb strb r3, [r7, #7] + 800a430: 4613 mov r3, r2 + 800a432: 71bb strb r3, [r7, #6] + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 800a434: f3ef 8310 mrs r3, PRIMASK + 800a438: 60fb str r3, [r7, #12] + return(result); + 800a43a: 68fb ldr r3, [r7, #12] + CRITICAL_SECTION_BEGIN(); + 800a43c: 617b str r3, [r7, #20] + __ASM volatile ("cpsid i" : : : "memory"); + 800a43e: b672 cpsid i +} + 800a440: bf00 nop + HAL_SUBGHZ_WriteBuffer( &hsubghz, offset, buffer, size ); + 800a442: 79bb ldrb r3, [r7, #6] + 800a444: b29b uxth r3, r3 + 800a446: 79f9 ldrb r1, [r7, #7] + 800a448: 683a ldr r2, [r7, #0] + 800a44a: 4806 ldr r0, [pc, #24] @ (800a464 ) + 800a44c: f7fa fb81 bl 8004b52 + 800a450: 697b ldr r3, [r7, #20] + 800a452: 613b str r3, [r7, #16] + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 800a454: 693b ldr r3, [r7, #16] + 800a456: f383 8810 msr PRIMASK, r3 +} + 800a45a: bf00 nop + CRITICAL_SECTION_END(); +} + 800a45c: bf00 nop + 800a45e: 3718 adds r7, #24 + 800a460: 46bd mov sp, r7 + 800a462: bd80 pop {r7, pc} + 800a464: 20000078 .word 0x20000078 + +0800a468 : + +void SUBGRF_ReadBuffer( uint8_t offset, uint8_t *buffer, uint8_t size ) +{ + 800a468: b580 push {r7, lr} + 800a46a: b086 sub sp, #24 + 800a46c: af00 add r7, sp, #0 + 800a46e: 4603 mov r3, r0 + 800a470: 6039 str r1, [r7, #0] + 800a472: 71fb strb r3, [r7, #7] + 800a474: 4613 mov r3, r2 + 800a476: 71bb strb r3, [r7, #6] + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 800a478: f3ef 8310 mrs r3, PRIMASK + 800a47c: 60fb str r3, [r7, #12] + return(result); + 800a47e: 68fb ldr r3, [r7, #12] + CRITICAL_SECTION_BEGIN(); + 800a480: 617b str r3, [r7, #20] + __ASM volatile ("cpsid i" : : : "memory"); + 800a482: b672 cpsid i +} + 800a484: bf00 nop + HAL_SUBGHZ_ReadBuffer( &hsubghz, offset, buffer, size ); + 800a486: 79bb ldrb r3, [r7, #6] + 800a488: b29b uxth r3, r3 + 800a48a: 79f9 ldrb r1, [r7, #7] + 800a48c: 683a ldr r2, [r7, #0] + 800a48e: 4806 ldr r0, [pc, #24] @ (800a4a8 ) + 800a490: f7fa fbb2 bl 8004bf8 + 800a494: 697b ldr r3, [r7, #20] + 800a496: 613b str r3, [r7, #16] + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 800a498: 693b ldr r3, [r7, #16] + 800a49a: f383 8810 msr PRIMASK, r3 +} + 800a49e: bf00 nop + CRITICAL_SECTION_END(); +} + 800a4a0: bf00 nop + 800a4a2: 3718 adds r7, #24 + 800a4a4: 46bd mov sp, r7 + 800a4a6: bd80 pop {r7, pc} + 800a4a8: 20000078 .word 0x20000078 + +0800a4ac : + +void SUBGRF_WriteCommand( SUBGHZ_RadioSetCmd_t Command, uint8_t *pBuffer, + uint16_t Size ) +{ + 800a4ac: b580 push {r7, lr} + 800a4ae: b086 sub sp, #24 + 800a4b0: af00 add r7, sp, #0 + 800a4b2: 4603 mov r3, r0 + 800a4b4: 6039 str r1, [r7, #0] + 800a4b6: 71fb strb r3, [r7, #7] + 800a4b8: 4613 mov r3, r2 + 800a4ba: 80bb strh r3, [r7, #4] + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 800a4bc: f3ef 8310 mrs r3, PRIMASK + 800a4c0: 60fb str r3, [r7, #12] + return(result); + 800a4c2: 68fb ldr r3, [r7, #12] + CRITICAL_SECTION_BEGIN(); + 800a4c4: 617b str r3, [r7, #20] + __ASM volatile ("cpsid i" : : : "memory"); + 800a4c6: b672 cpsid i +} + 800a4c8: bf00 nop + HAL_SUBGHZ_ExecSetCmd( &hsubghz, Command, pBuffer, Size ); + 800a4ca: 88bb ldrh r3, [r7, #4] + 800a4cc: 79f9 ldrb r1, [r7, #7] + 800a4ce: 683a ldr r2, [r7, #0] + 800a4d0: 4806 ldr r0, [pc, #24] @ (800a4ec ) + 800a4d2: f7fa fa8b bl 80049ec + 800a4d6: 697b ldr r3, [r7, #20] + 800a4d8: 613b str r3, [r7, #16] + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 800a4da: 693b ldr r3, [r7, #16] + 800a4dc: f383 8810 msr PRIMASK, r3 +} + 800a4e0: bf00 nop + CRITICAL_SECTION_END(); +} + 800a4e2: bf00 nop + 800a4e4: 3718 adds r7, #24 + 800a4e6: 46bd mov sp, r7 + 800a4e8: bd80 pop {r7, pc} + 800a4ea: bf00 nop + 800a4ec: 20000078 .word 0x20000078 + +0800a4f0 : + +void SUBGRF_ReadCommand( SUBGHZ_RadioGetCmd_t Command, uint8_t *pBuffer, + uint16_t Size ) +{ + 800a4f0: b580 push {r7, lr} + 800a4f2: b086 sub sp, #24 + 800a4f4: af00 add r7, sp, #0 + 800a4f6: 4603 mov r3, r0 + 800a4f8: 6039 str r1, [r7, #0] + 800a4fa: 71fb strb r3, [r7, #7] + 800a4fc: 4613 mov r3, r2 + 800a4fe: 80bb strh r3, [r7, #4] + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 800a500: f3ef 8310 mrs r3, PRIMASK + 800a504: 60fb str r3, [r7, #12] + return(result); + 800a506: 68fb ldr r3, [r7, #12] + CRITICAL_SECTION_BEGIN(); + 800a508: 617b str r3, [r7, #20] + __ASM volatile ("cpsid i" : : : "memory"); + 800a50a: b672 cpsid i +} + 800a50c: bf00 nop + HAL_SUBGHZ_ExecGetCmd( &hsubghz, Command, pBuffer, Size ); + 800a50e: 88bb ldrh r3, [r7, #4] + 800a510: 79f9 ldrb r1, [r7, #7] + 800a512: 683a ldr r2, [r7, #0] + 800a514: 4806 ldr r0, [pc, #24] @ (800a530 ) + 800a516: f7fa fac8 bl 8004aaa + 800a51a: 697b ldr r3, [r7, #20] + 800a51c: 613b str r3, [r7, #16] + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 800a51e: 693b ldr r3, [r7, #16] + 800a520: f383 8810 msr PRIMASK, r3 +} + 800a524: bf00 nop + CRITICAL_SECTION_END(); +} + 800a526: bf00 nop + 800a528: 3718 adds r7, #24 + 800a52a: 46bd mov sp, r7 + 800a52c: bd80 pop {r7, pc} + 800a52e: bf00 nop + 800a530: 20000078 .word 0x20000078 + +0800a534 : + +void SUBGRF_SetSwitch( uint8_t paSelect, RFState_t rxtx ) +{ + 800a534: b580 push {r7, lr} + 800a536: b084 sub sp, #16 + 800a538: af00 add r7, sp, #0 + 800a53a: 4603 mov r3, r0 + 800a53c: 460a mov r2, r1 + 800a53e: 71fb strb r3, [r7, #7] + 800a540: 4613 mov r3, r2 + 800a542: 71bb strb r3, [r7, #6] + RBI_Switch_TypeDef state = RBI_SWITCH_RX; + 800a544: 2301 movs r3, #1 + 800a546: 73fb strb r3, [r7, #15] + + if (rxtx == RFSWITCH_TX) + 800a548: 79bb ldrb r3, [r7, #6] + 800a54a: 2b01 cmp r3, #1 + 800a54c: d10d bne.n 800a56a + { + if (paSelect == RFO_LP) + 800a54e: 79fb ldrb r3, [r7, #7] + 800a550: 2b01 cmp r3, #1 + 800a552: d104 bne.n 800a55e + { + state = RBI_SWITCH_RFO_LP; + 800a554: 2302 movs r3, #2 + 800a556: 73fb strb r3, [r7, #15] + Radio_SMPS_Set(SMPS_DRIVE_SETTING_MAX); + 800a558: 2004 movs r0, #4 + 800a55a: f000 f8ef bl 800a73c + } + if (paSelect == RFO_HP) + 800a55e: 79fb ldrb r3, [r7, #7] + 800a560: 2b02 cmp r3, #2 + 800a562: d107 bne.n 800a574 + { + state = RBI_SWITCH_RFO_HP; + 800a564: 2303 movs r3, #3 + 800a566: 73fb strb r3, [r7, #15] + 800a568: e004 b.n 800a574 + } + } + else + { + if (rxtx == RFSWITCH_RX) + 800a56a: 79bb ldrb r3, [r7, #6] + 800a56c: 2b00 cmp r3, #0 + 800a56e: d101 bne.n 800a574 + { + state = RBI_SWITCH_RX; + 800a570: 2301 movs r3, #1 + 800a572: 73fb strb r3, [r7, #15] + } + } + RBI_ConfigRFSwitch(state); + 800a574: 7bfb ldrb r3, [r7, #15] + 800a576: 4618 mov r0, r3 + 800a578: f001 fce1 bl 800bf3e +} + 800a57c: bf00 nop + 800a57e: 3710 adds r7, #16 + 800a580: 46bd mov sp, r7 + 800a582: bd80 pop {r7, pc} + +0800a584 : + +uint8_t SUBGRF_SetRfTxPower( int8_t power ) +{ + 800a584: b580 push {r7, lr} + 800a586: b084 sub sp, #16 + 800a588: af00 add r7, sp, #0 + 800a58a: 4603 mov r3, r0 + 800a58c: 71fb strb r3, [r7, #7] + uint8_t paSelect= RFO_LP; + 800a58e: 2301 movs r3, #1 + 800a590: 73fb strb r3, [r7, #15] + + int32_t TxConfig = RBI_GetTxConfig(); + 800a592: f001 fce2 bl 800bf5a + 800a596: 60b8 str r0, [r7, #8] + + switch (TxConfig) + 800a598: 68bb ldr r3, [r7, #8] + 800a59a: 2b02 cmp r3, #2 + 800a59c: d016 beq.n 800a5cc + 800a59e: 68bb ldr r3, [r7, #8] + 800a5a0: 2b02 cmp r3, #2 + 800a5a2: dc16 bgt.n 800a5d2 + 800a5a4: 68bb ldr r3, [r7, #8] + 800a5a6: 2b00 cmp r3, #0 + 800a5a8: d003 beq.n 800a5b2 + 800a5aa: 68bb ldr r3, [r7, #8] + 800a5ac: 2b01 cmp r3, #1 + 800a5ae: d00a beq.n 800a5c6 + { + paSelect = RFO_HP; + break; + } + default: + break; + 800a5b0: e00f b.n 800a5d2 + if (power > 15) + 800a5b2: f997 3007 ldrsb.w r3, [r7, #7] + 800a5b6: 2b0f cmp r3, #15 + 800a5b8: dd02 ble.n 800a5c0 + paSelect = RFO_HP; + 800a5ba: 2302 movs r3, #2 + 800a5bc: 73fb strb r3, [r7, #15] + break; + 800a5be: e009 b.n 800a5d4 + paSelect = RFO_LP; + 800a5c0: 2301 movs r3, #1 + 800a5c2: 73fb strb r3, [r7, #15] + break; + 800a5c4: e006 b.n 800a5d4 + paSelect = RFO_LP; + 800a5c6: 2301 movs r3, #1 + 800a5c8: 73fb strb r3, [r7, #15] + break; + 800a5ca: e003 b.n 800a5d4 + paSelect = RFO_HP; + 800a5cc: 2302 movs r3, #2 + 800a5ce: 73fb strb r3, [r7, #15] + break; + 800a5d0: e000 b.n 800a5d4 + break; + 800a5d2: bf00 nop + } + + SUBGRF_SetTxParams( paSelect, power, RADIO_RAMP_40_US ); + 800a5d4: f997 1007 ldrsb.w r1, [r7, #7] + 800a5d8: 7bfb ldrb r3, [r7, #15] + 800a5da: 2202 movs r2, #2 + 800a5dc: 4618 mov r0, r3 + 800a5de: f7ff fbb9 bl 8009d54 + + return paSelect; + 800a5e2: 7bfb ldrb r3, [r7, #15] +} + 800a5e4: 4618 mov r0, r3 + 800a5e6: 3710 adds r7, #16 + 800a5e8: 46bd mov sp, r7 + 800a5ea: bd80 pop {r7, pc} + +0800a5ec : + +uint32_t SUBGRF_GetRadioWakeUpTime( void ) +{ + 800a5ec: b480 push {r7} + 800a5ee: af00 add r7, sp, #0 + return RF_WAKEUP_TIME; + 800a5f0: 2301 movs r3, #1 +} + 800a5f2: 4618 mov r0, r3 + 800a5f4: 46bd mov sp, r7 + 800a5f6: bc80 pop {r7} + 800a5f8: 4770 bx lr + ... + +0800a5fc : + +/* HAL_SUBGHz Callbacks definitions */ +void HAL_SUBGHZ_TxCpltCallback(SUBGHZ_HandleTypeDef *hsubghz) +{ + 800a5fc: b580 push {r7, lr} + 800a5fe: b082 sub sp, #8 + 800a600: af00 add r7, sp, #0 + 800a602: 6078 str r0, [r7, #4] + RadioOnDioIrqCb( IRQ_TX_DONE ); + 800a604: 4b03 ldr r3, [pc, #12] @ (800a614 ) + 800a606: 681b ldr r3, [r3, #0] + 800a608: 2001 movs r0, #1 + 800a60a: 4798 blx r3 +} + 800a60c: bf00 nop + 800a60e: 3708 adds r7, #8 + 800a610: 46bd mov sp, r7 + 800a612: bd80 pop {r7, pc} + 800a614: 20000328 .word 0x20000328 + +0800a618 : + +void HAL_SUBGHZ_RxCpltCallback(SUBGHZ_HandleTypeDef *hsubghz) +{ + 800a618: b580 push {r7, lr} + 800a61a: b082 sub sp, #8 + 800a61c: af00 add r7, sp, #0 + 800a61e: 6078 str r0, [r7, #4] + RadioOnDioIrqCb( IRQ_RX_DONE ); + 800a620: 4b03 ldr r3, [pc, #12] @ (800a630 ) + 800a622: 681b ldr r3, [r3, #0] + 800a624: 2002 movs r0, #2 + 800a626: 4798 blx r3 +} + 800a628: bf00 nop + 800a62a: 3708 adds r7, #8 + 800a62c: 46bd mov sp, r7 + 800a62e: bd80 pop {r7, pc} + 800a630: 20000328 .word 0x20000328 + +0800a634 : + +void HAL_SUBGHZ_CRCErrorCallback (SUBGHZ_HandleTypeDef *hsubghz) +{ + 800a634: b580 push {r7, lr} + 800a636: b082 sub sp, #8 + 800a638: af00 add r7, sp, #0 + 800a63a: 6078 str r0, [r7, #4] + RadioOnDioIrqCb( IRQ_CRC_ERROR); + 800a63c: 4b03 ldr r3, [pc, #12] @ (800a64c ) + 800a63e: 681b ldr r3, [r3, #0] + 800a640: 2040 movs r0, #64 @ 0x40 + 800a642: 4798 blx r3 +} + 800a644: bf00 nop + 800a646: 3708 adds r7, #8 + 800a648: 46bd mov sp, r7 + 800a64a: bd80 pop {r7, pc} + 800a64c: 20000328 .word 0x20000328 + +0800a650 : + +void HAL_SUBGHZ_CADStatusCallback(SUBGHZ_HandleTypeDef *hsubghz, HAL_SUBGHZ_CadStatusTypeDef cadstatus) +{ + 800a650: b580 push {r7, lr} + 800a652: b082 sub sp, #8 + 800a654: af00 add r7, sp, #0 + 800a656: 6078 str r0, [r7, #4] + 800a658: 460b mov r3, r1 + 800a65a: 70fb strb r3, [r7, #3] + switch (cadstatus) + 800a65c: 78fb ldrb r3, [r7, #3] + 800a65e: 2b00 cmp r3, #0 + 800a660: d002 beq.n 800a668 + 800a662: 2b01 cmp r3, #1 + 800a664: d005 beq.n 800a672 + break; + case HAL_SUBGHZ_CAD_DETECTED: + RadioOnDioIrqCb( IRQ_CAD_DETECTED); + break; + default: + break; + 800a666: e00a b.n 800a67e + RadioOnDioIrqCb( IRQ_CAD_CLEAR); + 800a668: 4b07 ldr r3, [pc, #28] @ (800a688 ) + 800a66a: 681b ldr r3, [r3, #0] + 800a66c: 2080 movs r0, #128 @ 0x80 + 800a66e: 4798 blx r3 + break; + 800a670: e005 b.n 800a67e + RadioOnDioIrqCb( IRQ_CAD_DETECTED); + 800a672: 4b05 ldr r3, [pc, #20] @ (800a688 ) + 800a674: 681b ldr r3, [r3, #0] + 800a676: f44f 7080 mov.w r0, #256 @ 0x100 + 800a67a: 4798 blx r3 + break; + 800a67c: bf00 nop + } +} + 800a67e: bf00 nop + 800a680: 3708 adds r7, #8 + 800a682: 46bd mov sp, r7 + 800a684: bd80 pop {r7, pc} + 800a686: bf00 nop + 800a688: 20000328 .word 0x20000328 + +0800a68c : + +void HAL_SUBGHZ_RxTxTimeoutCallback(SUBGHZ_HandleTypeDef *hsubghz) +{ + 800a68c: b580 push {r7, lr} + 800a68e: b082 sub sp, #8 + 800a690: af00 add r7, sp, #0 + 800a692: 6078 str r0, [r7, #4] + RadioOnDioIrqCb( IRQ_RX_TX_TIMEOUT ); + 800a694: 4b04 ldr r3, [pc, #16] @ (800a6a8 ) + 800a696: 681b ldr r3, [r3, #0] + 800a698: f44f 7000 mov.w r0, #512 @ 0x200 + 800a69c: 4798 blx r3 +} + 800a69e: bf00 nop + 800a6a0: 3708 adds r7, #8 + 800a6a2: 46bd mov sp, r7 + 800a6a4: bd80 pop {r7, pc} + 800a6a6: bf00 nop + 800a6a8: 20000328 .word 0x20000328 + +0800a6ac : + +void HAL_SUBGHZ_HeaderErrorCallback(SUBGHZ_HandleTypeDef *hsubghz) +{ + 800a6ac: b580 push {r7, lr} + 800a6ae: b082 sub sp, #8 + 800a6b0: af00 add r7, sp, #0 + 800a6b2: 6078 str r0, [r7, #4] + RadioOnDioIrqCb( IRQ_HEADER_ERROR ); + 800a6b4: 4b03 ldr r3, [pc, #12] @ (800a6c4 ) + 800a6b6: 681b ldr r3, [r3, #0] + 800a6b8: 2020 movs r0, #32 + 800a6ba: 4798 blx r3 +} + 800a6bc: bf00 nop + 800a6be: 3708 adds r7, #8 + 800a6c0: 46bd mov sp, r7 + 800a6c2: bd80 pop {r7, pc} + 800a6c4: 20000328 .word 0x20000328 + +0800a6c8 : + +void HAL_SUBGHZ_PreambleDetectedCallback(SUBGHZ_HandleTypeDef *hsubghz) +{ + 800a6c8: b580 push {r7, lr} + 800a6ca: b082 sub sp, #8 + 800a6cc: af00 add r7, sp, #0 + 800a6ce: 6078 str r0, [r7, #4] + RadioOnDioIrqCb( IRQ_PREAMBLE_DETECTED ); + 800a6d0: 4b03 ldr r3, [pc, #12] @ (800a6e0 ) + 800a6d2: 681b ldr r3, [r3, #0] + 800a6d4: 2004 movs r0, #4 + 800a6d6: 4798 blx r3 +} + 800a6d8: bf00 nop + 800a6da: 3708 adds r7, #8 + 800a6dc: 46bd mov sp, r7 + 800a6de: bd80 pop {r7, pc} + 800a6e0: 20000328 .word 0x20000328 + +0800a6e4 : + +void HAL_SUBGHZ_SyncWordValidCallback(SUBGHZ_HandleTypeDef *hsubghz) +{ + 800a6e4: b580 push {r7, lr} + 800a6e6: b082 sub sp, #8 + 800a6e8: af00 add r7, sp, #0 + 800a6ea: 6078 str r0, [r7, #4] + RadioOnDioIrqCb( IRQ_SYNCWORD_VALID ); + 800a6ec: 4b03 ldr r3, [pc, #12] @ (800a6fc ) + 800a6ee: 681b ldr r3, [r3, #0] + 800a6f0: 2008 movs r0, #8 + 800a6f2: 4798 blx r3 +} + 800a6f4: bf00 nop + 800a6f6: 3708 adds r7, #8 + 800a6f8: 46bd mov sp, r7 + 800a6fa: bd80 pop {r7, pc} + 800a6fc: 20000328 .word 0x20000328 + +0800a700 : + +void HAL_SUBGHZ_HeaderValidCallback(SUBGHZ_HandleTypeDef *hsubghz) +{ + 800a700: b580 push {r7, lr} + 800a702: b082 sub sp, #8 + 800a704: af00 add r7, sp, #0 + 800a706: 6078 str r0, [r7, #4] + RadioOnDioIrqCb( IRQ_HEADER_VALID ); + 800a708: 4b03 ldr r3, [pc, #12] @ (800a718 ) + 800a70a: 681b ldr r3, [r3, #0] + 800a70c: 2010 movs r0, #16 + 800a70e: 4798 blx r3 +} + 800a710: bf00 nop + 800a712: 3708 adds r7, #8 + 800a714: 46bd mov sp, r7 + 800a716: bd80 pop {r7, pc} + 800a718: 20000328 .word 0x20000328 + +0800a71c : + +void HAL_SUBGHZ_LrFhssHopCallback(SUBGHZ_HandleTypeDef *hsubghz) +{ + 800a71c: b580 push {r7, lr} + 800a71e: b082 sub sp, #8 + 800a720: af00 add r7, sp, #0 + 800a722: 6078 str r0, [r7, #4] + RadioOnDioIrqCb( IRQ_LR_FHSS_HOP ); + 800a724: 4b04 ldr r3, [pc, #16] @ (800a738 ) + 800a726: 681b ldr r3, [r3, #0] + 800a728: f44f 4080 mov.w r0, #16384 @ 0x4000 + 800a72c: 4798 blx r3 +} + 800a72e: bf00 nop + 800a730: 3708 adds r7, #8 + 800a732: 46bd mov sp, r7 + 800a734: bd80 pop {r7, pc} + 800a736: bf00 nop + 800a738: 20000328 .word 0x20000328 + +0800a73c : + +static void Radio_SMPS_Set(uint8_t level) +{ + 800a73c: b580 push {r7, lr} + 800a73e: b084 sub sp, #16 + 800a740: af00 add r7, sp, #0 + 800a742: 4603 mov r3, r0 + 800a744: 71fb strb r3, [r7, #7] + if ( 1U == RBI_IsDCDC() ) + 800a746: f001 fc16 bl 800bf76 + 800a74a: 4603 mov r3, r0 + 800a74c: 2b01 cmp r3, #1 + 800a74e: d112 bne.n 800a776 + { + uint8_t modReg; + modReg= SUBGRF_ReadRegister(SUBGHZ_SMPSC2R); + 800a750: f640 1023 movw r0, #2339 @ 0x923 + 800a754: f7ff fe02 bl 800a35c + 800a758: 4603 mov r3, r0 + 800a75a: 73fb strb r3, [r7, #15] + modReg&= (~SMPS_DRV_MASK); + 800a75c: 7bfb ldrb r3, [r7, #15] + 800a75e: f023 0306 bic.w r3, r3, #6 + 800a762: 73fb strb r3, [r7, #15] + SUBGRF_WriteRegister(SUBGHZ_SMPSC2R, modReg | level); + 800a764: 7bfa ldrb r2, [r7, #15] + 800a766: 79fb ldrb r3, [r7, #7] + 800a768: 4313 orrs r3, r2 + 800a76a: b2db uxtb r3, r3 + 800a76c: 4619 mov r1, r3 + 800a76e: f640 1023 movw r0, #2339 @ 0x923 + 800a772: f7ff fdd1 bl 800a318 + } +} + 800a776: bf00 nop + 800a778: 3710 adds r7, #16 + 800a77a: 46bd mov sp, r7 + 800a77c: bd80 pop {r7, pc} + ... + +0800a780 : + +uint8_t SUBGRF_GetFskBandwidthRegValue( uint32_t bandwidth ) +{ + 800a780: b480 push {r7} + 800a782: b085 sub sp, #20 + 800a784: af00 add r7, sp, #0 + 800a786: 6078 str r0, [r7, #4] + uint8_t i; + + if( bandwidth == 0 ) + 800a788: 687b ldr r3, [r7, #4] + 800a78a: 2b00 cmp r3, #0 + 800a78c: d101 bne.n 800a792 + { + return( 0x1F ); + 800a78e: 231f movs r3, #31 + 800a790: e017 b.n 800a7c2 + } + + for( i = 0; i < ( sizeof( FskBandwidths ) / sizeof( FskBandwidth_t ) ); i++ ) + 800a792: 2300 movs r3, #0 + 800a794: 73fb strb r3, [r7, #15] + 800a796: e00f b.n 800a7b8 + { + if ( bandwidth < FskBandwidths[i].bandwidth ) + 800a798: 7bfb ldrb r3, [r7, #15] + 800a79a: 4a0c ldr r2, [pc, #48] @ (800a7cc ) + 800a79c: f852 3033 ldr.w r3, [r2, r3, lsl #3] + 800a7a0: 687a ldr r2, [r7, #4] + 800a7a2: 429a cmp r2, r3 + 800a7a4: d205 bcs.n 800a7b2 + { + return FskBandwidths[i].RegValue; + 800a7a6: 7bfb ldrb r3, [r7, #15] + 800a7a8: 4a08 ldr r2, [pc, #32] @ (800a7cc ) + 800a7aa: 00db lsls r3, r3, #3 + 800a7ac: 4413 add r3, r2 + 800a7ae: 791b ldrb r3, [r3, #4] + 800a7b0: e007 b.n 800a7c2 + for( i = 0; i < ( sizeof( FskBandwidths ) / sizeof( FskBandwidth_t ) ); i++ ) + 800a7b2: 7bfb ldrb r3, [r7, #15] + 800a7b4: 3301 adds r3, #1 + 800a7b6: 73fb strb r3, [r7, #15] + 800a7b8: 7bfb ldrb r3, [r7, #15] + 800a7ba: 2b15 cmp r3, #21 + 800a7bc: d9ec bls.n 800a798 + } + } + // ERROR: Value not found + while( 1 ); + 800a7be: bf00 nop + 800a7c0: e7fd b.n 800a7be +} + 800a7c2: 4618 mov r0, r3 + 800a7c4: 3714 adds r7, #20 + 800a7c6: 46bd mov sp, r7 + 800a7c8: bc80 pop {r7} + 800a7ca: 4770 bx lr + 800a7cc: 0800da70 .word 0x0800da70 + +0800a7d0 : +void SUBGRF_GetCFO( uint32_t bitRate, int32_t *cfo) +{ + 800a7d0: b580 push {r7, lr} + 800a7d2: b08a sub sp, #40 @ 0x28 + 800a7d4: af00 add r7, sp, #0 + 800a7d6: 6078 str r0, [r7, #4] + 800a7d8: 6039 str r1, [r7, #0] + uint8_t BwMant[] = {4, 8, 10, 12}; + 800a7da: 4b35 ldr r3, [pc, #212] @ (800a8b0 ) + 800a7dc: 60fb str r3, [r7, #12] + /* read demod bandwidth: mant bit4:3, exp bits 2:0 */ + uint8_t reg = (SUBGRF_ReadRegister( SUBGHZ_BWSELR )); + 800a7de: f640 0007 movw r0, #2055 @ 0x807 + 800a7e2: f7ff fdbb bl 800a35c + 800a7e6: 4603 mov r3, r0 + 800a7e8: 77fb strb r3, [r7, #31] + uint8_t bandwidth_mant = BwMant[( reg >> 3 ) & 0x3]; + 800a7ea: 7ffb ldrb r3, [r7, #31] + 800a7ec: 08db lsrs r3, r3, #3 + 800a7ee: b2db uxtb r3, r3 + 800a7f0: f003 0303 and.w r3, r3, #3 + 800a7f4: 3328 adds r3, #40 @ 0x28 + 800a7f6: 443b add r3, r7 + 800a7f8: f813 3c1c ldrb.w r3, [r3, #-28] + 800a7fc: 77bb strb r3, [r7, #30] + uint8_t bandwidth_exp = reg & 0x7; + 800a7fe: 7ffb ldrb r3, [r7, #31] + 800a800: f003 0307 and.w r3, r3, #7 + 800a804: 777b strb r3, [r7, #29] + uint32_t cf_fs = XTAL_FREQ / ( bandwidth_mant * ( 1 << ( bandwidth_exp + 1 ))); + 800a806: 7fba ldrb r2, [r7, #30] + 800a808: 7f7b ldrb r3, [r7, #29] + 800a80a: 3301 adds r3, #1 + 800a80c: fa02 f303 lsl.w r3, r2, r3 + 800a810: 461a mov r2, r3 + 800a812: 4b28 ldr r3, [pc, #160] @ (800a8b4 ) + 800a814: fbb3 f3f2 udiv r3, r3, r2 + 800a818: 61bb str r3, [r7, #24] + uint32_t cf_osr = cf_fs / bitRate; + 800a81a: 69ba ldr r2, [r7, #24] + 800a81c: 687b ldr r3, [r7, #4] + 800a81e: fbb2 f3f3 udiv r3, r2, r3 + 800a822: 617b str r3, [r7, #20] + uint8_t interp = 1; + 800a824: 2301 movs r3, #1 + 800a826: f887 3027 strb.w r3, [r7, #39] @ 0x27 + /* calculate demod interpolation factor */ + if (cf_osr * interp < 8) + 800a82a: f897 3027 ldrb.w r3, [r7, #39] @ 0x27 + 800a82e: 697a ldr r2, [r7, #20] + 800a830: fb02 f303 mul.w r3, r2, r3 + 800a834: 2b07 cmp r3, #7 + 800a836: d802 bhi.n 800a83e + { + interp = 2; + 800a838: 2302 movs r3, #2 + 800a83a: f887 3027 strb.w r3, [r7, #39] @ 0x27 + } + if (cf_osr * interp < 4) + 800a83e: f897 3027 ldrb.w r3, [r7, #39] @ 0x27 + 800a842: 697a ldr r2, [r7, #20] + 800a844: fb02 f303 mul.w r3, r2, r3 + 800a848: 2b03 cmp r3, #3 + 800a84a: d802 bhi.n 800a852 + { + interp = 4; + 800a84c: 2304 movs r3, #4 + 800a84e: f887 3027 strb.w r3, [r7, #39] @ 0x27 + } + /* calculate demod sampling frequency */ + uint32_t fs = cf_fs* interp; + 800a852: f897 2027 ldrb.w r2, [r7, #39] @ 0x27 + 800a856: 69bb ldr r3, [r7, #24] + 800a858: fb02 f303 mul.w r3, r2, r3 + 800a85c: 613b str r3, [r7, #16] + /* get the cfo registers */ + int32_t cfo_bin = ( SUBGRF_ReadRegister( SUBGHZ_GCFORH ) & 0xF ) << 8; + 800a85e: f44f 60d6 mov.w r0, #1712 @ 0x6b0 + 800a862: f7ff fd7b bl 800a35c + 800a866: 4603 mov r3, r0 + 800a868: 021b lsls r3, r3, #8 + 800a86a: f403 6370 and.w r3, r3, #3840 @ 0xf00 + 800a86e: 623b str r3, [r7, #32] + cfo_bin |= SUBGRF_ReadRegister( SUBGHZ_GCFORL ); + 800a870: f240 60b1 movw r0, #1713 @ 0x6b1 + 800a874: f7ff fd72 bl 800a35c + 800a878: 4603 mov r3, r0 + 800a87a: 461a mov r2, r3 + 800a87c: 6a3b ldr r3, [r7, #32] + 800a87e: 4313 orrs r3, r2 + 800a880: 623b str r3, [r7, #32] + /* negate if 12 bits sign bit is 1 */ + if (( cfo_bin & 0x800 ) == 0x800 ) + 800a882: 6a3b ldr r3, [r7, #32] + 800a884: f403 6300 and.w r3, r3, #2048 @ 0x800 + 800a888: 2b00 cmp r3, #0 + 800a88a: d005 beq.n 800a898 + { + cfo_bin |= 0xFFFFF000; + 800a88c: 6a3b ldr r3, [r7, #32] + 800a88e: ea6f 5303 mvn.w r3, r3, lsl #20 + 800a892: ea6f 5313 mvn.w r3, r3, lsr #20 + 800a896: 623b str r3, [r7, #32] + } + /* calculate cfo in Hz */ + /* shift by 5 first to not saturate, cfo_bin on 12bits */ + *cfo = ((int32_t)( cfo_bin * ( fs >> 5 ))) >> ( 12 - 5 ); + 800a898: 693b ldr r3, [r7, #16] + 800a89a: 095b lsrs r3, r3, #5 + 800a89c: 6a3a ldr r2, [r7, #32] + 800a89e: fb02 f303 mul.w r3, r2, r3 + 800a8a2: 11da asrs r2, r3, #7 + 800a8a4: 683b ldr r3, [r7, #0] + 800a8a6: 601a str r2, [r3, #0] +} + 800a8a8: bf00 nop + 800a8aa: 3728 adds r7, #40 @ 0x28 + 800a8ac: 46bd mov sp, r7 + 800a8ae: bd80 pop {r7, pc} + 800a8b0: 0c0a0804 .word 0x0c0a0804 + 800a8b4: 01e84800 .word 0x01e84800 + +0800a8b8 : +{ + 800a8b8: b480 push {r7} + 800a8ba: af00 add r7, sp, #0 + return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos); + 800a8bc: 4b03 ldr r3, [pc, #12] @ (800a8cc ) + 800a8be: 681b ldr r3, [r3, #0] + 800a8c0: 0c1b lsrs r3, r3, #16 + 800a8c2: b29b uxth r3, r3 +} + 800a8c4: 4618 mov r0, r3 + 800a8c6: 46bd mov sp, r7 + 800a8c8: bc80 pop {r7} + 800a8ca: 4770 bx lr + 800a8cc: e0042000 .word 0xe0042000 + +0800a8d0 : +{ + 800a8d0: b480 push {r7} + 800a8d2: b083 sub sp, #12 + 800a8d4: af00 add r7, sp, #0 + 800a8d6: 6078 str r0, [r7, #4] + 800a8d8: 6039 str r1, [r7, #0] + WRITE_REG(GPIOx->BSRR, PinMask); + 800a8da: 687b ldr r3, [r7, #4] + 800a8dc: 683a ldr r2, [r7, #0] + 800a8de: 619a str r2, [r3, #24] +} + 800a8e0: bf00 nop + 800a8e2: 370c adds r7, #12 + 800a8e4: 46bd mov sp, r7 + 800a8e6: bc80 pop {r7} + 800a8e8: 4770 bx lr + +0800a8ea : +{ + 800a8ea: b480 push {r7} + 800a8ec: b083 sub sp, #12 + 800a8ee: af00 add r7, sp, #0 + 800a8f0: 6078 str r0, [r7, #4] + 800a8f2: 6039 str r1, [r7, #0] + WRITE_REG(GPIOx->BRR, PinMask); + 800a8f4: 687b ldr r3, [r7, #4] + 800a8f6: 683a ldr r2, [r7, #0] + 800a8f8: 629a str r2, [r3, #40] @ 0x28 +} + 800a8fa: bf00 nop + 800a8fc: 370c adds r7, #12 + 800a8fe: 46bd mov sp, r7 + 800a900: bc80 pop {r7} + 800a902: 4770 bx lr + +0800a904 : +#endif /* RFW_ENABLE == 1 */ + +/* Exported functions --------------------------------------------------------*/ +int32_t RFW_TransmitLongPacket( uint16_t payload_size, uint32_t timeout, + void ( *TxLongPacketGetNextChunkCb )( uint8_t **buffer, uint8_t buffer_size ) ) +{ + 800a904: b580 push {r7, lr} + 800a906: b08e sub sp, #56 @ 0x38 + 800a908: af02 add r7, sp, #8 + 800a90a: 4603 mov r3, r0 + 800a90c: 60b9 str r1, [r7, #8] + 800a90e: 607a str r2, [r7, #4] + 800a910: 81fb strh r3, [r7, #14] + int32_t status = 0; + 800a912: 2300 movs r3, #0 + 800a914: 62fb str r3, [r7, #44] @ 0x2c +#if (RFW_LONGPACKET_ENABLE == 1 ) + uint32_t total_size = payload_size + RFWPacket.Init.PayloadLengthFieldSize + RFWPacket.Init.CrcFieldSize; + 800a916: 89fb ldrh r3, [r7, #14] + 800a918: 4ab0 ldr r2, [pc, #704] @ (800abdc ) + 800a91a: 7852 ldrb r2, [r2, #1] + 800a91c: 4413 add r3, r2 + 800a91e: 4aaf ldr r2, [pc, #700] @ (800abdc ) + 800a920: 78d2 ldrb r2, [r2, #3] + 800a922: 4413 add r3, r2 + 800a924: 627b str r3, [r7, #36] @ 0x24 + + RFW_MW_LOG( TS_ON, VLEVEL_M, "RevID=%04X\r\n", LL_DBGMCU_GetRevisionID() ); + 800a926: f7ff ffc7 bl 800a8b8 + 800a92a: 4603 mov r3, r0 + 800a92c: 9300 str r3, [sp, #0] + 800a92e: 4bac ldr r3, [pc, #688] @ (800abe0 ) + 800a930: 2201 movs r2, #1 + 800a932: 2100 movs r1, #0 + 800a934: 2002 movs r0, #2 + 800a936: f002 fb25 bl 800cf84 + + if( ( TxLongPacketGetNextChunkCb == NULL ) || + 800a93a: 687b ldr r3, [r7, #4] + 800a93c: 2b00 cmp r3, #0 + 800a93e: d012 beq.n 800a966 + ( payload_size > ( 1 << ( 8 * RFWPacket.Init.PayloadLengthFieldSize ) ) - 1 ) || /*check that size fits inside the packetLengthField*/ + 800a940: 4ba6 ldr r3, [pc, #664] @ (800abdc ) + 800a942: 785b ldrb r3, [r3, #1] + 800a944: 00db lsls r3, r3, #3 + 800a946: 2201 movs r2, #1 + 800a948: 409a lsls r2, r3 + 800a94a: 89fb ldrh r3, [r7, #14] + if( ( TxLongPacketGetNextChunkCb == NULL ) || + 800a94c: 429a cmp r2, r3 + 800a94e: dd0a ble.n 800a966 + ( RFWPacket.Init.Enable == 0 ) || /* Can only be used when after RadioSetTxGenericConfig*/ + 800a950: 4ba2 ldr r3, [pc, #648] @ (800abdc ) + 800a952: 781b ldrb r3, [r3, #0] + ( payload_size > ( 1 << ( 8 * RFWPacket.Init.PayloadLengthFieldSize ) ) - 1 ) || /*check that size fits inside the packetLengthField*/ + 800a954: 2b00 cmp r3, #0 + 800a956: d006 beq.n 800a966 + ( LL_DBGMCU_GetRevisionID() < 0x1003 ) ) /* Only available from stm32wl revision Y*/ + 800a958: f7ff ffae bl 800a8b8 + 800a95c: 4603 mov r3, r0 + ( RFWPacket.Init.Enable == 0 ) || /* Can only be used when after RadioSetTxGenericConfig*/ + 800a95e: f241 0202 movw r2, #4098 @ 0x1002 + 800a962: 4293 cmp r3, r2 + 800a964: d803 bhi.n 800a96e + { + status = -1; + 800a966: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff + 800a96a: 62fb str r3, [r7, #44] @ 0x2c + 800a96c: e130 b.n 800abd0 + } + else + { + /*chunk buffer pointer fed by the application*/ + uint8_t *app_chunk_buffer_ptr = NULL; + 800a96e: 2300 movs r3, #0 + 800a970: 61bb str r3, [r7, #24] + uint8_t chunk_size; + uint8_t crc_size; + /*timeout for next chunk*/ + uint32_t chunk_timeout; + /*Records call back*/ + RFWPacket.TxLongPacketGetNextChunkCb = TxLongPacketGetNextChunkCb; + 800a972: 4a9a ldr r2, [pc, #616] @ (800abdc ) + 800a974: 687b ldr r3, [r7, #4] + 800a976: 6413 str r3, [r2, #64] @ 0x40 + + /* Radio IRQ is set to DIO1 by default */ + SUBGRF_SetDioIrqParams( IRQ_TX_DONE | IRQ_RX_TX_TIMEOUT, + 800a978: 2300 movs r3, #0 + 800a97a: 2200 movs r2, #0 + 800a97c: f240 2101 movw r1, #513 @ 0x201 + 800a980: f240 2001 movw r0, #513 @ 0x201 + 800a984: f7ff f91e bl 8009bc4 + IRQ_TX_DONE | IRQ_RX_TX_TIMEOUT, + IRQ_RADIO_NONE, + IRQ_RADIO_NONE ); + + /* Set DBG pin */ + DBG_GPIO_RADIO_TX( SET ); + 800a988: f44f 5100 mov.w r1, #8192 @ 0x2000 + 800a98c: 4895 ldr r0, [pc, #596] @ (800abe4 ) + 800a98e: f7ff ff9f bl 800a8d0 + /* Set RF switch */ + SUBGRF_SetSwitch( RFWPacket.AntSwitchPaSelect, RFSWITCH_TX ); + 800a992: 4b92 ldr r3, [pc, #584] @ (800abdc ) + 800a994: f893 3044 ldrb.w r3, [r3, #68] @ 0x44 + 800a998: 2101 movs r1, #1 + 800a99a: 4618 mov r0, r3 + 800a99c: f7ff fdca bl 800a534 + + switch( RFWPacket.Init.Modem ) + 800a9a0: 4b8e ldr r3, [pc, #568] @ (800abdc ) + 800a9a2: 7b9b ldrb r3, [r3, #14] + 800a9a4: 2b04 cmp r3, #4 + 800a9a6: f200 8110 bhi.w 800abca + 800a9aa: a201 add r2, pc, #4 @ (adr r2, 800a9b0 ) + 800a9ac: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 800a9b0: 0800a9c5 .word 0x0800a9c5 + 800a9b4: 0800abb3 .word 0x0800abb3 + 800a9b8: 0800a9c5 .word 0x0800a9c5 + 800a9bc: 0800abbb .word 0x0800abbb + 800a9c0: 0800abc3 .word 0x0800abc3 + { + case MODEM_FSK: + case MODEM_MSK: + { + if( RFWPacket.Init.Enable == 1 ) + 800a9c4: 4b85 ldr r3, [pc, #532] @ (800abdc ) + 800a9c6: 781b ldrb r3, [r3, #0] + 800a9c8: 2b01 cmp r3, #1 + 800a9ca: f040 80ee bne.w 800abaa + { + /*crc will be calculated on the fly along with packet chunk transmission*/ + uint8_t crc_result[2]; + /*init radio buffer offset*/ + RFWPacket.RadioBufferOffset = 0; + 800a9ce: 4b83 ldr r3, [pc, #524] @ (800abdc ) + 800a9d0: 2200 movs r2, #0 + 800a9d2: f883 2036 strb.w r2, [r3, #54] @ 0x36 + /*long packet mode enable*/ + RFWPacket.LongPacketModeEnable = 1; + 800a9d6: 4b81 ldr r3, [pc, #516] @ (800abdc ) + 800a9d8: 2201 movs r2, #1 + 800a9da: 769a strb r2, [r3, #26] + /*Remaining bytes to transmit*/ + RFWPacket.LongPacketRemainingBytes = total_size; + 800a9dc: 6a7b ldr r3, [r7, #36] @ 0x24 + 800a9de: b29a uxth r2, r3 + 800a9e0: 4b7e ldr r3, [pc, #504] @ (800abdc ) + 800a9e2: 869a strh r2, [r3, #52] @ 0x34 + /*Records total payload bytes to transmit*/ + RFWPacket.PayloadLength = total_size; + 800a9e4: 6a7b ldr r3, [r7, #36] @ 0x24 + 800a9e6: b29a uxth r2, r3 + 800a9e8: 4b7c ldr r3, [pc, #496] @ (800abdc ) + 800a9ea: 831a strh r2, [r3, #24] + if( total_size > RADIO_BUF_SIZE ) + 800a9ec: 6a7b ldr r3, [r7, #36] @ 0x24 + 800a9ee: 2bff cmp r3, #255 @ 0xff + 800a9f0: d919 bls.n 800aa26 + { + /*cut in chunk*/ + if( total_size < RADIO_BUF_SIZE + RFWPacket.Init.CrcFieldSize ) + 800a9f2: 4b7a ldr r3, [pc, #488] @ (800abdc ) + 800a9f4: 78db ldrb r3, [r3, #3] + 800a9f6: 33ff adds r3, #255 @ 0xff + 800a9f8: 461a mov r2, r3 + 800a9fa: 6a7b ldr r3, [r7, #36] @ 0x24 + 800a9fc: 4293 cmp r3, r2 + 800a9fe: d209 bcs.n 800aa14 + { + /*reduce chunk so that crc is treated in the next chunk*/ + chunk_size = RADIO_BUF_SIZE - RFWPacket.Init.PayloadLengthFieldSize - RFWPacket.Init.CrcFieldSize; + 800aa00: 4b76 ldr r3, [pc, #472] @ (800abdc ) + 800aa02: 785b ldrb r3, [r3, #1] + 800aa04: 43db mvns r3, r3 + 800aa06: b2da uxtb r2, r3 + 800aa08: 4b74 ldr r3, [pc, #464] @ (800abdc ) + 800aa0a: 78db ldrb r3, [r3, #3] + 800aa0c: 1ad3 subs r3, r2, r3 + 800aa0e: f887 302b strb.w r3, [r7, #43] @ 0x2b + 800aa12: e004 b.n 800aa1e + } + else + { + chunk_size = RADIO_BUF_SIZE - RFWPacket.Init.PayloadLengthFieldSize; + 800aa14: 4b71 ldr r3, [pc, #452] @ (800abdc ) + 800aa16: 785b ldrb r3, [r3, #1] + 800aa18: 43db mvns r3, r3 + 800aa1a: f887 302b strb.w r3, [r7, #43] @ 0x2b + } + /*Set crc size for the crc calculation: no crc here because it is not the end of the packet*/ + crc_size = 0; + 800aa1e: 2300 movs r3, #0 + 800aa20: f887 302a strb.w r3, [r7, #42] @ 0x2a + 800aa24: e006 b.n 800aa34 + } + else + { + chunk_size = payload_size; + 800aa26: 89fb ldrh r3, [r7, #14] + 800aa28: f887 302b strb.w r3, [r7, #43] @ 0x2b + /*Set crc size for the crc calculation*/ + crc_size = RFWPacket.Init.CrcFieldSize; + 800aa2c: 4b6b ldr r3, [pc, #428] @ (800abdc ) + 800aa2e: 78db ldrb r3, [r3, #3] + 800aa30: f887 302a strb.w r3, [r7, #42] @ 0x2a + } + /* Prepend payload size before Payload*/ + if( RFWPacket.Init.PayloadLengthFieldSize == 1 ) + 800aa34: 4b69 ldr r3, [pc, #420] @ (800abdc ) + 800aa36: 785b ldrb r3, [r3, #1] + 800aa38: 2b01 cmp r3, #1 + 800aa3a: d104 bne.n 800aa46 + { + ChunkBuffer[0] = payload_size; + 800aa3c: 89fb ldrh r3, [r7, #14] + 800aa3e: b2da uxtb r2, r3 + 800aa40: 4b69 ldr r3, [pc, #420] @ (800abe8 ) + 800aa42: 701a strb r2, [r3, #0] + 800aa44: e009 b.n 800aa5a + } + else + { + ChunkBuffer[0] = ( uint8_t )( ( payload_size ) >> 8 ); + 800aa46: 89fb ldrh r3, [r7, #14] + 800aa48: 0a1b lsrs r3, r3, #8 + 800aa4a: b29b uxth r3, r3 + 800aa4c: b2da uxtb r2, r3 + 800aa4e: 4b66 ldr r3, [pc, #408] @ (800abe8 ) + 800aa50: 701a strb r2, [r3, #0] + ChunkBuffer[1] = ( uint8_t )( ( payload_size ) & 0xFF ); + 800aa52: 89fb ldrh r3, [r7, #14] + 800aa54: b2da uxtb r2, r3 + 800aa56: 4b64 ldr r3, [pc, #400] @ (800abe8 ) + 800aa58: 705a strb r2, [r3, #1] + } + /* Get Tx chunk from app*/ + TxLongPacketGetNextChunkCb( &app_chunk_buffer_ptr, chunk_size ); + 800aa5a: f897 102b ldrb.w r1, [r7, #43] @ 0x2b + 800aa5e: f107 0218 add.w r2, r7, #24 + 800aa62: 687b ldr r3, [r7, #4] + 800aa64: 4610 mov r0, r2 + 800aa66: 4798 blx r3 + + /* Copy first chunk in ChunkBuffer Buffer*/ + RADIO_MEMCPY8( &ChunkBuffer[RFWPacket.Init.PayloadLengthFieldSize], app_chunk_buffer_ptr, chunk_size ); + 800aa68: 4b5c ldr r3, [pc, #368] @ (800abdc ) + 800aa6a: 785b ldrb r3, [r3, #1] + 800aa6c: 461a mov r2, r3 + 800aa6e: 4b5e ldr r3, [pc, #376] @ (800abe8 ) + 800aa70: 4413 add r3, r2 + 800aa72: 69b9 ldr r1, [r7, #24] + 800aa74: f897 202b ldrb.w r2, [r7, #43] @ 0x2b + 800aa78: b292 uxth r2, r2 + 800aa7a: 4618 mov r0, r3 + 800aa7c: f001 fb36 bl 800c0ec + + if( RFWPacket.Init.CrcEnable == 1 ) + 800aa80: 4b56 ldr r3, [pc, #344] @ (800abdc ) + 800aa82: 789b ldrb r3, [r3, #2] + 800aa84: 2b01 cmp r3, #1 + 800aa86: d11f bne.n 800aac8 + { + /* Set the state of the Crc to crc_seed*/ + RFW_CrcSetState( &RFWPacket ); + 800aa88: 4854 ldr r0, [pc, #336] @ (800abdc ) + 800aa8a: f000 fc57 bl 800b33c + /* Run the crc calculation on payload length and payload*/ + RFW_CrcRun( &RFWPacket, ChunkBuffer, RFWPacket.Init.PayloadLengthFieldSize + chunk_size, crc_result ); + 800aa8e: 4b53 ldr r3, [pc, #332] @ (800abdc ) + 800aa90: 785b ldrb r3, [r3, #1] + 800aa92: 461a mov r2, r3 + 800aa94: f897 302b ldrb.w r3, [r7, #43] @ 0x2b + 800aa98: 4413 add r3, r2 + 800aa9a: 461a mov r2, r3 + 800aa9c: f107 0314 add.w r3, r7, #20 + 800aaa0: 4951 ldr r1, [pc, #324] @ (800abe8 ) + 800aaa2: 484e ldr r0, [pc, #312] @ (800abdc ) + 800aaa4: f000 fc9f bl 800b3e6 + /* Append the crc result after the payload if total_size<= RADIO_BUF_SIZE*/ + RADIO_MEMCPY8( &ChunkBuffer[RFWPacket.Init.PayloadLengthFieldSize + chunk_size], crc_result, crc_size ); + 800aaa8: 4b4c ldr r3, [pc, #304] @ (800abdc ) + 800aaaa: 785b ldrb r3, [r3, #1] + 800aaac: 461a mov r2, r3 + 800aaae: f897 302b ldrb.w r3, [r7, #43] @ 0x2b + 800aab2: 4413 add r3, r2 + 800aab4: 4a4c ldr r2, [pc, #304] @ (800abe8 ) + 800aab6: 4413 add r3, r2 + 800aab8: f897 202a ldrb.w r2, [r7, #42] @ 0x2a + 800aabc: b292 uxth r2, r2 + 800aabe: f107 0114 add.w r1, r7, #20 + 800aac2: 4618 mov r0, r3 + 800aac4: f001 fb12 bl 800c0ec + } + /* Init whitening at beginning of the packet*/ + RFW_WhiteSetState( &RFWPacket ); + 800aac8: 4844 ldr r0, [pc, #272] @ (800abdc ) + 800aaca: f000 fc0f bl 800b2ec + /* Run the whitening calculation on payload length, payload and crc if crc fits inside 1st chunk*/ + RFW_WhiteRun( &RFWPacket, &ChunkBuffer[0], RFWPacket.Init.PayloadLengthFieldSize + chunk_size + crc_size ); + 800aace: 4b43 ldr r3, [pc, #268] @ (800abdc ) + 800aad0: 785b ldrb r3, [r3, #1] + 800aad2: 461a mov r2, r3 + 800aad4: f897 302b ldrb.w r3, [r7, #43] @ 0x2b + 800aad8: 441a add r2, r3 + 800aada: f897 302a ldrb.w r3, [r7, #42] @ 0x2a + 800aade: 4413 add r3, r2 + 800aae0: 461a mov r2, r3 + 800aae2: 4941 ldr r1, [pc, #260] @ (800abe8 ) + 800aae4: 483d ldr r0, [pc, #244] @ (800abdc ) + 800aae6: f000 fc36 bl 800b356 + /* Configure the Transmitter to send all*/ + /* Init radio buffer */ + SUBGRF_WriteRegister( SUBGHZ_GRTXPLDLEN, RFWPacket.Init.PayloadLengthFieldSize + chunk_size + crc_size ); + 800aaea: 4b3c ldr r3, [pc, #240] @ (800abdc ) + 800aaec: 785a ldrb r2, [r3, #1] + 800aaee: f897 302b ldrb.w r3, [r7, #43] @ 0x2b + 800aaf2: 4413 add r3, r2 + 800aaf4: b2da uxtb r2, r3 + 800aaf6: f897 302a ldrb.w r3, [r7, #42] @ 0x2a + 800aafa: 4413 add r3, r2 + 800aafc: b2db uxtb r3, r3 + 800aafe: 4619 mov r1, r3 + 800ab00: f240 60bb movw r0, #1723 @ 0x6bb + 800ab04: f7ff fc08 bl 800a318 + SUBGRF_WriteRegister( SUBGHZ_TXADRPTR, 0 ); + 800ab08: 2100 movs r1, #0 + 800ab0a: f640 0002 movw r0, #2050 @ 0x802 + 800ab0e: f7ff fc03 bl 800a318 + /* Send*/ + SUBGRF_SendPayload( ChunkBuffer, RFWPacket.Init.PayloadLengthFieldSize + chunk_size + crc_size, 0 ); + 800ab12: 4b32 ldr r3, [pc, #200] @ (800abdc ) + 800ab14: 785a ldrb r2, [r3, #1] + 800ab16: f897 302b ldrb.w r3, [r7, #43] @ 0x2b + 800ab1a: 4413 add r3, r2 + 800ab1c: b2da uxtb r2, r3 + 800ab1e: f897 302a ldrb.w r3, [r7, #42] @ 0x2a + 800ab22: 4413 add r3, r2 + 800ab24: b2db uxtb r3, r3 + 800ab26: 2200 movs r2, #0 + 800ab28: 4619 mov r1, r3 + 800ab2a: 482f ldr r0, [pc, #188] @ (800abe8 ) + 800ab2c: f7fe fd60 bl 80095f0 + if( total_size > RADIO_BUF_SIZE ) + 800ab30: 6a7b ldr r3, [r7, #36] @ 0x24 + 800ab32: 2bff cmp r3, #255 @ 0xff + 800ab34: d94b bls.n 800abce + { + /*in case total size is greater than RADIO_BUF_SIZE, need to program a timer to get next chunk*/ + /*RFWPacket.LongPacketRemainingBytes-= RFWPacket.Init.PayloadLengthFieldSize+ chunk_size+ crc_size;*/ + /*Initialize Timer to get new chunk and update radio ptr*/ + chunk_timeout = ( LONGPACKET_CHUNK_LENGTH_BYTES * 8 * 1000 ) / RFWPacket.BitRate; + 800ab36: 4b29 ldr r3, [pc, #164] @ (800abdc ) + 800ab38: 6c9b ldr r3, [r3, #72] @ 0x48 + 800ab3a: f44f 227a mov.w r2, #1024000 @ 0xfa000 + 800ab3e: fbb2 f3f3 udiv r3, r2, r3 + 800ab42: 623b str r3, [r7, #32] + RFW_MW_LOG( TS_ON, VLEVEL_M, "Timeout=%d,\r\n", chunk_timeout ); + 800ab44: 6a3b ldr r3, [r7, #32] + 800ab46: 9300 str r3, [sp, #0] + 800ab48: 4b28 ldr r3, [pc, #160] @ (800abec ) + 800ab4a: 2201 movs r2, #1 + 800ab4c: 2100 movs r1, #0 + 800ab4e: 2002 movs r0, #2 + 800ab50: f002 fa18 bl 800cf84 + TimerInit( &RFWPacket.Timer, RFW_TransmitLongPacket_NewTxChunkTimerEvent ); + 800ab54: 2300 movs r3, #0 + 800ab56: 9300 str r3, [sp, #0] + 800ab58: 4b25 ldr r3, [pc, #148] @ (800abf0 ) + 800ab5a: 2200 movs r2, #0 + 800ab5c: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff + 800ab60: 4824 ldr r0, [pc, #144] @ (800abf4 ) + 800ab62: f001 ff73 bl 800ca4c + TimerSetValue( &RFWPacket.Timer, chunk_timeout ); + 800ab66: 6a39 ldr r1, [r7, #32] + 800ab68: 4822 ldr r0, [pc, #136] @ (800abf4 ) + 800ab6a: f002 f883 bl 800cc74 + TimerStart( &RFWPacket.Timer ); + 800ab6e: 4821 ldr r0, [pc, #132] @ (800abf4 ) + 800ab70: f001 ffa2 bl 800cab8 + /*Write bit infinite_sequence = 1, required for long packet*/ + uint8_t reg = SUBGRF_ReadRegister( SUBGHZ_GPKTCTL1AR ); + 800ab74: f44f 60d7 mov.w r0, #1720 @ 0x6b8 + 800ab78: f7ff fbf0 bl 800a35c + 800ab7c: 4603 mov r3, r0 + 800ab7e: 77fb strb r3, [r7, #31] + SUBGRF_WriteRegister( SUBGHZ_GPKTCTL1AR, reg | 0x02 ); + 800ab80: 7ffb ldrb r3, [r7, #31] + 800ab82: f043 0302 orr.w r3, r3, #2 + 800ab86: b2db uxtb r3, r3 + 800ab88: 4619 mov r1, r3 + 800ab8a: f44f 60d7 mov.w r0, #1720 @ 0x6b8 + 800ab8e: f7ff fbc3 bl 800a318 + + TimerSetValue( RFWPacket.RxTimeoutTimer, timeout ); + 800ab92: 4b12 ldr r3, [pc, #72] @ (800abdc ) + 800ab94: 6cdb ldr r3, [r3, #76] @ 0x4c + 800ab96: 68b9 ldr r1, [r7, #8] + 800ab98: 4618 mov r0, r3 + 800ab9a: f002 f86b bl 800cc74 + TimerStart( RFWPacket.RxTimeoutTimer ); + 800ab9e: 4b0f ldr r3, [pc, #60] @ (800abdc ) + 800aba0: 6cdb ldr r3, [r3, #76] @ 0x4c + 800aba2: 4618 mov r0, r3 + 800aba4: f001 ff88 bl 800cab8 + else + { + /* error*/ + status = -1; + } + break; + 800aba8: e011 b.n 800abce + status = -1; + 800abaa: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff + 800abae: 62fb str r3, [r7, #44] @ 0x2c + break; + 800abb0: e00d b.n 800abce + } + case MODEM_LORA: + { + /* not supported by the radio Ip*/ + status = -2; + 800abb2: f06f 0301 mvn.w r3, #1 + 800abb6: 62fb str r3, [r7, #44] @ 0x2c + break; + 800abb8: e00a b.n 800abd0 + } + case MODEM_BPSK: + { + /* not supported by the FW*/ + status = -2; + 800abba: f06f 0301 mvn.w r3, #1 + 800abbe: 62fb str r3, [r7, #44] @ 0x2c + break; + 800abc0: e006 b.n 800abd0 + } + case MODEM_SIGFOX_TX: + { + /* not supported by the FW*/ + status = -2; + 800abc2: f06f 0301 mvn.w r3, #1 + 800abc6: 62fb str r3, [r7, #44] @ 0x2c + break; + 800abc8: e002 b.n 800abd0 + } + default: + break; + 800abca: bf00 nop + 800abcc: e000 b.n 800abd0 + break; + 800abce: bf00 nop + } + } +#else + status = -1; +#endif /* RFW_LONGPACKET_ENABLE == 1 */ + return status; + 800abd0: 6afb ldr r3, [r7, #44] @ 0x2c +} + 800abd2: 4618 mov r0, r3 + 800abd4: 3730 adds r7, #48 @ 0x30 + 800abd6: 46bd mov sp, r7 + 800abd8: bd80 pop {r7, pc} + 800abda: bf00 nop + 800abdc: 2000032c .word 0x2000032c + 800abe0: 0800d5a4 .word 0x0800d5a4 + 800abe4: 48000400 .word 0x48000400 + 800abe8: 20000380 .word 0x20000380 + 800abec: 0800d5b4 .word 0x0800d5b4 + 800abf0: 0800b0ed .word 0x0800b0ed + 800abf4: 20000348 .word 0x20000348 + +0800abf8 : + +int32_t RFW_ReceiveLongPacket( uint8_t boosted_mode, uint32_t timeout, + void ( *RxLongPacketStoreChunkCb )( uint8_t *buffer, uint8_t chunk_size ) ) +{ + 800abf8: b580 push {r7, lr} + 800abfa: b086 sub sp, #24 + 800abfc: af00 add r7, sp, #0 + 800abfe: 4603 mov r3, r0 + 800ac00: 60b9 str r1, [r7, #8] + 800ac02: 607a str r2, [r7, #4] + 800ac04: 73fb strb r3, [r7, #15] + int32_t status = 0; + 800ac06: 2300 movs r3, #0 + 800ac08: 617b str r3, [r7, #20] +#if (RFW_LONGPACKET_ENABLE == 1 ) + if( ( RxLongPacketStoreChunkCb == NULL ) || + 800ac0a: 687b ldr r3, [r7, #4] + 800ac0c: 2b00 cmp r3, #0 + 800ac0e: d003 beq.n 800ac18 + ( RFWPacket.Init.Enable == 0 ) ) /* Can only be used when after RadioSetRxGenericConfig*/ + 800ac10: 4b2a ldr r3, [pc, #168] @ (800acbc ) + 800ac12: 781b ldrb r3, [r3, #0] + if( ( RxLongPacketStoreChunkCb == NULL ) || + 800ac14: 2b00 cmp r3, #0 + 800ac16: d103 bne.n 800ac20 + { + status = -1; + 800ac18: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff + 800ac1c: 617b str r3, [r7, #20] + 800ac1e: e047 b.n 800acb0 + } + else + { + /*Records call back*/ + RFWPacket.RxLongPacketStoreChunkCb = RxLongPacketStoreChunkCb; + 800ac20: 4a26 ldr r2, [pc, #152] @ (800acbc ) + 800ac22: 687b ldr r3, [r7, #4] + 800ac24: 63d3 str r3, [r2, #60] @ 0x3c + SUBGRF_SetDioIrqParams( IRQ_SYNCWORD_VALID | IRQ_RX_TX_TIMEOUT, + 800ac26: 2300 movs r3, #0 + 800ac28: 2200 movs r2, #0 + 800ac2a: f44f 7102 mov.w r1, #520 @ 0x208 + 800ac2e: f44f 7002 mov.w r0, #520 @ 0x208 + 800ac32: f7fe ffc7 bl 8009bc4 + IRQ_SYNCWORD_VALID | IRQ_RX_TX_TIMEOUT, + IRQ_RADIO_NONE, + IRQ_RADIO_NONE ); + SUBGRF_SetSwitch( RFWPacket.AntSwitchPaSelect, RFSWITCH_RX ); + 800ac36: 4b21 ldr r3, [pc, #132] @ (800acbc ) + 800ac38: f893 3044 ldrb.w r3, [r3, #68] @ 0x44 + 800ac3c: 2100 movs r1, #0 + 800ac3e: 4618 mov r0, r3 + 800ac40: f7ff fc78 bl 800a534 + /*init radio buffer offset*/ + RFWPacket.RadioBufferOffset = 0; + 800ac44: 4b1d ldr r3, [pc, #116] @ (800acbc ) + 800ac46: 2200 movs r2, #0 + 800ac48: f883 2036 strb.w r2, [r3, #54] @ 0x36 + /* Init whitening at beginning of the packet*/ + RFW_WhiteSetState( &RFWPacket ); + 800ac4c: 481b ldr r0, [pc, #108] @ (800acbc ) + 800ac4e: f000 fb4d bl 800b2ec + /* Set the state of the Crc to crc_seed*/ + RFW_CrcSetState( &RFWPacket ); + 800ac52: 481a ldr r0, [pc, #104] @ (800acbc ) + 800ac54: f000 fb72 bl 800b33c + /* Init radio buffer */ + SUBGRF_WriteRegister( SUBGHZ_GRTXPLDLEN, 255 ); + 800ac58: 21ff movs r1, #255 @ 0xff + 800ac5a: f240 60bb movw r0, #1723 @ 0x6bb + 800ac5e: f7ff fb5b bl 800a318 + SUBGRF_WriteRegister( SUBGHZ_RXADRPTR, 0 ); + 800ac62: 2100 movs r1, #0 + 800ac64: f640 0003 movw r0, #2051 @ 0x803 + 800ac68: f7ff fb56 bl 800a318 + /*enable long packet*/ + RFWPacket.LongPacketModeEnable = 1; + 800ac6c: 4b13 ldr r3, [pc, #76] @ (800acbc ) + 800ac6e: 2201 movs r2, #1 + 800ac70: 769a strb r2, [r3, #26] + + if( timeout != 0 ) + 800ac72: 68bb ldr r3, [r7, #8] + 800ac74: 2b00 cmp r3, #0 + 800ac76: d00a beq.n 800ac8e + { + TimerSetValue( RFWPacket.RxTimeoutTimer, timeout ); + 800ac78: 4b10 ldr r3, [pc, #64] @ (800acbc ) + 800ac7a: 6cdb ldr r3, [r3, #76] @ 0x4c + 800ac7c: 68b9 ldr r1, [r7, #8] + 800ac7e: 4618 mov r0, r3 + 800ac80: f001 fff8 bl 800cc74 + TimerStart( RFWPacket.RxTimeoutTimer ); + 800ac84: 4b0d ldr r3, [pc, #52] @ (800acbc ) + 800ac86: 6cdb ldr r3, [r3, #76] @ 0x4c + 800ac88: 4618 mov r0, r3 + 800ac8a: f001 ff15 bl 800cab8 + } + DBG_GPIO_RADIO_RX( SET ); + 800ac8e: f44f 5180 mov.w r1, #4096 @ 0x1000 + 800ac92: 480b ldr r0, [pc, #44] @ (800acc0 ) + 800ac94: f7ff fe1c bl 800a8d0 + if( boosted_mode == 1 ) + 800ac98: 7bfb ldrb r3, [r7, #15] + 800ac9a: 2b01 cmp r3, #1 + 800ac9c: d104 bne.n 800aca8 + { + SUBGRF_SetRxBoosted( 0xFFFFFF ); /* Rx Continuous */ + 800ac9e: f06f 407f mvn.w r0, #4278190080 @ 0xff000000 + 800aca2: f7fe fe11 bl 80098c8 + 800aca6: e003 b.n 800acb0 + } + else + { + SUBGRF_SetRx( 0xFFFFFF ); /* Rx Continuous */ + 800aca8: f06f 407f mvn.w r0, #4278190080 @ 0xff000000 + 800acac: f7fe fdec bl 8009888 + } + } +#else + status = -1; +#endif /* RFW_LONGPACKET_ENABLE == 1 */ + return status; + 800acb0: 697b ldr r3, [r7, #20] +} + 800acb2: 4618 mov r0, r3 + 800acb4: 3718 adds r7, #24 + 800acb6: 46bd mov sp, r7 + 800acb8: bd80 pop {r7, pc} + 800acba: bf00 nop + 800acbc: 2000032c .word 0x2000032c + 800acc0: 48000400 .word 0x48000400 + +0800acc4 : + +int32_t RFW_Init( ConfigGeneric_t *config, RadioEvents_t *RadioEvents, TimerEvent_t *TimeoutTimerEvent ) +{ + 800acc4: b580 push {r7, lr} + 800acc6: b08a sub sp, #40 @ 0x28 + 800acc8: af02 add r7, sp, #8 + 800acca: 60f8 str r0, [r7, #12] + 800accc: 60b9 str r1, [r7, #8] + 800acce: 607a str r2, [r7, #4] +#if (RFW_ENABLE == 1 ) + RADIO_FSK_PacketLengthModes_t HeaderType; + uint32_t RxMaxPayloadLength = 0; + 800acd0: 2300 movs r3, #0 + 800acd2: 61bb str r3, [r7, #24] + RADIO_FSK_CrcTypes_t CrcLength; + uint16_t whiteSeed; + uint16_t CrcPolynomial; + uint16_t CrcSeed; + if( config->rtx == CONFIG_TX ) + 800acd4: 68fb ldr r3, [r7, #12] + 800acd6: 7a1b ldrb r3, [r3, #8] + 800acd8: 2b01 cmp r3, #1 + 800acda: d11c bne.n 800ad16 + { + HeaderType = config->TxConfig->fsk.HeaderType; + 800acdc: 68fb ldr r3, [r7, #12] + 800acde: 681b ldr r3, [r3, #0] + 800ace0: 7d1b ldrb r3, [r3, #20] + 800ace2: 77fb strb r3, [r7, #31] + CrcLength = config->TxConfig->fsk.CrcLength; + 800ace4: 68fb ldr r3, [r7, #12] + 800ace6: 681b ldr r3, [r3, #0] + 800ace8: 7d5b ldrb r3, [r3, #21] + 800acea: 75fb strb r3, [r7, #23] + whiteSeed = config->TxConfig->fsk.whiteSeed; + 800acec: 68fb ldr r3, [r7, #12] + 800acee: 681b ldr r3, [r3, #0] + 800acf0: 8a1b ldrh r3, [r3, #16] + 800acf2: 82bb strh r3, [r7, #20] + CrcPolynomial = config->TxConfig->fsk.CrcPolynomial; + 800acf4: 68fb ldr r3, [r7, #12] + 800acf6: 681b ldr r3, [r3, #0] + 800acf8: 899b ldrh r3, [r3, #12] + 800acfa: 827b strh r3, [r7, #18] + CrcSeed = config->TxConfig->fsk.CrcSeed; + 800acfc: 68fb ldr r3, [r7, #12] + 800acfe: 681b ldr r3, [r3, #0] + 800ad00: 89db ldrh r3, [r3, #14] + 800ad02: 823b strh r3, [r7, #16] + RFWPacket.BitRate = config->TxConfig->fsk.BitRate; + 800ad04: 68fb ldr r3, [r7, #12] + 800ad06: 681b ldr r3, [r3, #0] + 800ad08: 681b ldr r3, [r3, #0] + 800ad0a: 4a38 ldr r2, [pc, #224] @ (800adec ) + 800ad0c: 6493 str r3, [r2, #72] @ 0x48 + RFWPacket.TxTimeoutTimer = TimeoutTimerEvent; + 800ad0e: 4a37 ldr r2, [pc, #220] @ (800adec ) + 800ad10: 687b ldr r3, [r7, #4] + 800ad12: 6513 str r3, [r2, #80] @ 0x50 + 800ad14: e021 b.n 800ad5a + } + else + { + HeaderType = config->RxConfig->fsk.LengthMode; + 800ad16: 68fb ldr r3, [r7, #12] + 800ad18: 685b ldr r3, [r3, #4] + 800ad1a: f893 3022 ldrb.w r3, [r3, #34] @ 0x22 + 800ad1e: 77fb strb r3, [r7, #31] + CrcLength = config->RxConfig->fsk.CrcLength; + 800ad20: 68fb ldr r3, [r7, #12] + 800ad22: 685b ldr r3, [r3, #4] + 800ad24: f893 3023 ldrb.w r3, [r3, #35] @ 0x23 + 800ad28: 75fb strb r3, [r7, #23] + RxMaxPayloadLength = config->RxConfig->fsk.MaxPayloadLength; + 800ad2a: 68fb ldr r3, [r7, #12] + 800ad2c: 685b ldr r3, [r3, #4] + 800ad2e: 695b ldr r3, [r3, #20] + 800ad30: 61bb str r3, [r7, #24] + whiteSeed = config->RxConfig->fsk.whiteSeed; + 800ad32: 68fb ldr r3, [r7, #12] + 800ad34: 685b ldr r3, [r3, #4] + 800ad36: 8b9b ldrh r3, [r3, #28] + 800ad38: 82bb strh r3, [r7, #20] + CrcPolynomial = config->RxConfig->fsk.CrcPolynomial; + 800ad3a: 68fb ldr r3, [r7, #12] + 800ad3c: 685b ldr r3, [r3, #4] + 800ad3e: 8b1b ldrh r3, [r3, #24] + 800ad40: 827b strh r3, [r7, #18] + CrcSeed = config->RxConfig->fsk.CrcSeed; + 800ad42: 68fb ldr r3, [r7, #12] + 800ad44: 685b ldr r3, [r3, #4] + 800ad46: 8b5b ldrh r3, [r3, #26] + 800ad48: 823b strh r3, [r7, #16] + RFWPacket.BitRate = config->RxConfig->fsk.BitRate; + 800ad4a: 68fb ldr r3, [r7, #12] + 800ad4c: 685b ldr r3, [r3, #4] + 800ad4e: 689b ldr r3, [r3, #8] + 800ad50: 4a26 ldr r2, [pc, #152] @ (800adec ) + 800ad52: 6493 str r3, [r2, #72] @ 0x48 + RFWPacket.RxTimeoutTimer = TimeoutTimerEvent; + 800ad54: 4a25 ldr r2, [pc, #148] @ (800adec ) + 800ad56: 687b ldr r3, [r7, #4] + 800ad58: 64d3 str r3, [r2, #76] @ 0x4c + } + if( ( RadioEvents != NULL ) && ( RadioEvents->RxError ) ) + 800ad5a: 68bb ldr r3, [r7, #8] + 800ad5c: 2b00 cmp r3, #0 + 800ad5e: d00a beq.n 800ad76 + 800ad60: 68bb ldr r3, [r7, #8] + 800ad62: 691b ldr r3, [r3, #16] + 800ad64: 2b00 cmp r3, #0 + 800ad66: d006 beq.n 800ad76 + { + RFWPacket.Init.RadioEvents = RadioEvents; + 800ad68: 4a20 ldr r2, [pc, #128] @ (800adec ) + 800ad6a: 68bb ldr r3, [r7, #8] + 800ad6c: 6113 str r3, [r2, #16] + } + else + { + return -1; + } + if( HeaderType == RADIO_FSK_PACKET_2BYTES_LENGTH ) + 800ad6e: 7ffb ldrb r3, [r7, #31] + 800ad70: 2b02 cmp r3, #2 + 800ad72: d003 beq.n 800ad7c + 800ad74: e006 b.n 800ad84 + return -1; + 800ad76: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff + 800ad7a: e032 b.n 800ade2 + { +#if (RFW_LONGPACKET_ENABLE == 1 ) + RFWPacket.Init.PayloadLengthFieldSize = 2; + 800ad7c: 4b1b ldr r3, [pc, #108] @ (800adec ) + 800ad7e: 2202 movs r2, #2 + 800ad80: 705a strb r2, [r3, #1] + 800ad82: e002 b.n 800ad8a + return -1; +#endif /* RFW_LONGPACKET_ENABLE == 1 */ + } + else + { + RFWPacket.Init.PayloadLengthFieldSize = 1; + 800ad84: 4b19 ldr r3, [pc, #100] @ (800adec ) + 800ad86: 2201 movs r2, #1 + 800ad88: 705a strb r2, [r3, #1] + } + /*record, used to reject packet in length decoded at sync time out greater than LongPacketMaxRxLength*/ + RFWPacket.Init.LongPacketMaxRxLength = RxMaxPayloadLength; + 800ad8a: 69bb ldr r3, [r7, #24] + 800ad8c: b29a uxth r2, r3 + 800ad8e: 4b17 ldr r3, [pc, #92] @ (800adec ) + 800ad90: 819a strh r2, [r3, #12] + if( CrcLength == RADIO_FSK_CRC_OFF ) + 800ad92: 7dfb ldrb r3, [r7, #23] + 800ad94: 2b01 cmp r3, #1 + 800ad96: d106 bne.n 800ada6 + { + RFWPacket.Init.CrcEnable = 0; + 800ad98: 4b14 ldr r3, [pc, #80] @ (800adec ) + 800ad9a: 2200 movs r2, #0 + 800ad9c: 709a strb r2, [r3, #2] + RFWPacket.Init.CrcFieldSize = 0; + 800ad9e: 4b13 ldr r3, [pc, #76] @ (800adec ) + 800ada0: 2200 movs r2, #0 + 800ada2: 70da strb r2, [r3, #3] + 800ada4: e005 b.n 800adb2 + } + else + { + RFWPacket.Init.CrcEnable = 1; + 800ada6: 4b11 ldr r3, [pc, #68] @ (800adec ) + 800ada8: 2201 movs r2, #1 + 800adaa: 709a strb r2, [r3, #2] + RFWPacket.Init.CrcFieldSize = 2; + 800adac: 4b0f ldr r3, [pc, #60] @ (800adec ) + 800adae: 2202 movs r2, #2 + 800adb0: 70da strb r2, [r3, #3] + } + /*Macro can be used to init interrupt behaviour*/ + RFW_IT_INIT(); + /*Initialise whitening Seed*/ + RFW_WhiteInitState( &RFWPacket.Init, whiteSeed ); + 800adb2: 8abb ldrh r3, [r7, #20] + 800adb4: 4619 mov r1, r3 + 800adb6: 480d ldr r0, [pc, #52] @ (800adec ) + 800adb8: f000 fa8a bl 800b2d0 + /*Initialise Crc Seed*/ + RFW_CrcInitState( &RFWPacket.Init, CrcPolynomial, CrcSeed, CrcLength ); + 800adbc: 7dfb ldrb r3, [r7, #23] + 800adbe: 8a3a ldrh r2, [r7, #16] + 800adc0: 8a79 ldrh r1, [r7, #18] + 800adc2: 480a ldr r0, [pc, #40] @ (800adec ) + 800adc4: f000 fa9f bl 800b306 + /*Enable the RFWPacket decoding*/ + RFWPacket.Init.Enable = 1; + 800adc8: 4b08 ldr r3, [pc, #32] @ (800adec ) + 800adca: 2201 movs r2, #1 + 800adcc: 701a strb r2, [r3, #0] + /* Initialize Timer for end of fixed packet, started at sync*/ + TimerInit( &RFWPacket.Timer, RFW_GetPayloadTimerEvent ); + 800adce: 2300 movs r3, #0 + 800add0: 9300 str r3, [sp, #0] + 800add2: 4b07 ldr r3, [pc, #28] @ (800adf0 ) + 800add4: 2200 movs r2, #0 + 800add6: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff + 800adda: 4806 ldr r0, [pc, #24] @ (800adf4 ) + 800addc: f001 fe36 bl 800ca4c + return 0; + 800ade0: 2300 movs r3, #0 +#else + return -1; +#endif /* RFW_ENABLE == 1 */ +} + 800ade2: 4618 mov r0, r3 + 800ade4: 3720 adds r7, #32 + 800ade6: 46bd mov sp, r7 + 800ade8: bd80 pop {r7, pc} + 800adea: bf00 nop + 800adec: 2000032c .word 0x2000032c + 800adf0: 0800b601 .word 0x0800b601 + 800adf4: 20000348 .word 0x20000348 + +0800adf8 : + +void RFW_DeInit( void ) +{ + 800adf8: b480 push {r7} + 800adfa: af00 add r7, sp, #0 +#if (RFW_ENABLE == 1 ) + RFWPacket.Init.Enable = 0; /*Disable the RFWPacket decoding*/ + 800adfc: 4b03 ldr r3, [pc, #12] @ (800ae0c ) + 800adfe: 2200 movs r2, #0 + 800ae00: 701a strb r2, [r3, #0] +#endif /* RFW_ENABLE == 1 */ +} + 800ae02: bf00 nop + 800ae04: 46bd mov sp, r7 + 800ae06: bc80 pop {r7} + 800ae08: 4770 bx lr + 800ae0a: bf00 nop + 800ae0c: 2000032c .word 0x2000032c + +0800ae10 : + +uint8_t RFW_Is_Init( void ) +{ + 800ae10: b480 push {r7} + 800ae12: af00 add r7, sp, #0 +#if (RFW_ENABLE == 1 ) + return RFWPacket.Init.Enable; + 800ae14: 4b02 ldr r3, [pc, #8] @ (800ae20 ) + 800ae16: 781b ldrb r3, [r3, #0] +#else + return 0; +#endif /* RFW_ENABLE == 1 */ +} + 800ae18: 4618 mov r0, r3 + 800ae1a: 46bd mov sp, r7 + 800ae1c: bc80 pop {r7} + 800ae1e: 4770 bx lr + 800ae20: 2000032c .word 0x2000032c + +0800ae24 : + +uint8_t RFW_Is_LongPacketModeEnabled( void ) +{ + 800ae24: b480 push {r7} + 800ae26: af00 add r7, sp, #0 +#if (RFW_ENABLE == 1 ) + return RFWPacket.LongPacketModeEnable; + 800ae28: 4b02 ldr r3, [pc, #8] @ (800ae34 ) + 800ae2a: 7e9b ldrb r3, [r3, #26] +#else + return 0; +#endif /* RFW_ENABLE == 1 */ +} + 800ae2c: 4618 mov r0, r3 + 800ae2e: 46bd mov sp, r7 + 800ae30: bc80 pop {r7} + 800ae32: 4770 bx lr + 800ae34: 2000032c .word 0x2000032c + +0800ae38 : + +void RFW_SetAntSwitch( uint8_t AntSwitch ) +{ + 800ae38: b480 push {r7} + 800ae3a: b083 sub sp, #12 + 800ae3c: af00 add r7, sp, #0 + 800ae3e: 4603 mov r3, r0 + 800ae40: 71fb strb r3, [r7, #7] +#if (RFW_ENABLE == 1 ) + RFWPacket.AntSwitchPaSelect = AntSwitch; + 800ae42: 4a04 ldr r2, [pc, #16] @ (800ae54 ) + 800ae44: 79fb ldrb r3, [r7, #7] + 800ae46: f882 3044 strb.w r3, [r2, #68] @ 0x44 +#endif /* RFW_ENABLE == 1 */ +} + 800ae4a: bf00 nop + 800ae4c: 370c adds r7, #12 + 800ae4e: 46bd mov sp, r7 + 800ae50: bc80 pop {r7} + 800ae52: 4770 bx lr + 800ae54: 2000032c .word 0x2000032c + +0800ae58 : + +int32_t RFW_TransmitInit( uint8_t *inOutBuffer, uint8_t size, uint8_t *outSize ) +{ + 800ae58: b580 push {r7, lr} + 800ae5a: b086 sub sp, #24 + 800ae5c: af00 add r7, sp, #0 + 800ae5e: 60f8 str r0, [r7, #12] + 800ae60: 460b mov r3, r1 + 800ae62: 607a str r2, [r7, #4] + 800ae64: 72fb strb r3, [r7, #11] + int32_t status = -1; + 800ae66: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff + 800ae6a: 617b str r3, [r7, #20] +#if (RFW_ENABLE == 1 ) + uint8_t crc_result[2]; + if( size + RFWPacket.Init.PayloadLengthFieldSize + RFWPacket.Init.CrcFieldSize > RADIO_BUF_SIZE ) + 800ae6c: 7afb ldrb r3, [r7, #11] + 800ae6e: 4a3a ldr r2, [pc, #232] @ (800af58 ) + 800ae70: 7852 ldrb r2, [r2, #1] + 800ae72: 4413 add r3, r2 + 800ae74: 4a38 ldr r2, [pc, #224] @ (800af58 ) + 800ae76: 78d2 ldrb r2, [r2, #3] + 800ae78: 4413 add r3, r2 + 800ae7a: 2bff cmp r3, #255 @ 0xff + 800ae7c: dd09 ble.n 800ae92 + { + RFW_MW_LOG( TS_ON, VLEVEL_M, "RadioSend Oversize\r\n" ); + 800ae7e: 4b37 ldr r3, [pc, #220] @ (800af5c ) + 800ae80: 2201 movs r2, #1 + 800ae82: 2100 movs r1, #0 + 800ae84: 2002 movs r0, #2 + 800ae86: f002 f87d bl 800cf84 + status = -1; + 800ae8a: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff + 800ae8e: 617b str r3, [r7, #20] + 800ae90: e05d b.n 800af4e + } + else + { + /* Copy tx buffer in payload*/ + RADIO_MEMCPY8( &ChunkBuffer[RFWPacket.Init.PayloadLengthFieldSize], inOutBuffer, size ); + 800ae92: 4b31 ldr r3, [pc, #196] @ (800af58 ) + 800ae94: 785b ldrb r3, [r3, #1] + 800ae96: 461a mov r2, r3 + 800ae98: 4b31 ldr r3, [pc, #196] @ (800af60 ) + 800ae9a: 4413 add r3, r2 + 800ae9c: 7afa ldrb r2, [r7, #11] + 800ae9e: b292 uxth r2, r2 + 800aea0: 68f9 ldr r1, [r7, #12] + 800aea2: 4618 mov r0, r3 + 800aea4: f001 f922 bl 800c0ec + /* Calculate the crc on */ + /* Payload Size without the packet length field nor the CRC */ + /* Prepend payload size before Payload*/ + if( RFWPacket.Init.PayloadLengthFieldSize == 1 ) + 800aea8: 4b2b ldr r3, [pc, #172] @ (800af58 ) + 800aeaa: 785b ldrb r3, [r3, #1] + 800aeac: 2b01 cmp r3, #1 + 800aeae: d103 bne.n 800aeb8 + { + ChunkBuffer[0] = size; + 800aeb0: 4a2b ldr r2, [pc, #172] @ (800af60 ) + 800aeb2: 7afb ldrb r3, [r7, #11] + 800aeb4: 7013 strb r3, [r2, #0] + 800aeb6: e005 b.n 800aec4 + } + else + { + ChunkBuffer[0] = 0; + 800aeb8: 4b29 ldr r3, [pc, #164] @ (800af60 ) + 800aeba: 2200 movs r2, #0 + 800aebc: 701a strb r2, [r3, #0] + ChunkBuffer[1] = size; + 800aebe: 4a28 ldr r2, [pc, #160] @ (800af60 ) + 800aec0: 7afb ldrb r3, [r7, #11] + 800aec2: 7053 strb r3, [r2, #1] + } + if( RFWPacket.Init.CrcEnable == 1 ) + 800aec4: 4b24 ldr r3, [pc, #144] @ (800af58 ) + 800aec6: 789b ldrb r3, [r3, #2] + 800aec8: 2b01 cmp r3, #1 + 800aeca: d11a bne.n 800af02 + { + /* Set the state of the Crc to crc_seed*/ + RFW_CrcSetState( &RFWPacket ); + 800aecc: 4822 ldr r0, [pc, #136] @ (800af58 ) + 800aece: f000 fa35 bl 800b33c + /*Run the crc calculation on payload length and payload*/ + RFW_CrcRun( &RFWPacket, &ChunkBuffer[0], size + RFWPacket.Init.PayloadLengthFieldSize, crc_result ); + 800aed2: 7afb ldrb r3, [r7, #11] + 800aed4: 4a20 ldr r2, [pc, #128] @ (800af58 ) + 800aed6: 7852 ldrb r2, [r2, #1] + 800aed8: 4413 add r3, r2 + 800aeda: 461a mov r2, r3 + 800aedc: f107 0310 add.w r3, r7, #16 + 800aee0: 491f ldr r1, [pc, #124] @ (800af60 ) + 800aee2: 481d ldr r0, [pc, #116] @ (800af58 ) + 800aee4: f000 fa7f bl 800b3e6 + /*append the crc result after the payload*/ + RADIO_MEMCPY8( &ChunkBuffer[size + RFWPacket.Init.PayloadLengthFieldSize], crc_result, RFWPacket.Init.CrcFieldSize ); + 800aee8: 7afb ldrb r3, [r7, #11] + 800aeea: 4a1b ldr r2, [pc, #108] @ (800af58 ) + 800aeec: 7852 ldrb r2, [r2, #1] + 800aeee: 4413 add r3, r2 + 800aef0: 4a1b ldr r2, [pc, #108] @ (800af60 ) + 800aef2: 4413 add r3, r2 + 800aef4: 4a18 ldr r2, [pc, #96] @ (800af58 ) + 800aef6: 78d2 ldrb r2, [r2, #3] + 800aef8: f107 0110 add.w r1, r7, #16 + 800aefc: 4618 mov r0, r3 + 800aefe: f001 f8f5 bl 800c0ec + } + /*init whitening at beginning of the packet*/ + RFW_WhiteSetState( &RFWPacket ); + 800af02: 4815 ldr r0, [pc, #84] @ (800af58 ) + 800af04: f000 f9f2 bl 800b2ec + /*Run the whitening calculation on payload length, payload and crc*/ + RFW_WhiteRun( &RFWPacket, &ChunkBuffer[0], size + RFWPacket.Init.PayloadLengthFieldSize + RFWPacket.Init.CrcFieldSize ); + 800af08: 7afb ldrb r3, [r7, #11] + 800af0a: 4a13 ldr r2, [pc, #76] @ (800af58 ) + 800af0c: 7852 ldrb r2, [r2, #1] + 800af0e: 4413 add r3, r2 + 800af10: 4a11 ldr r2, [pc, #68] @ (800af58 ) + 800af12: 78d2 ldrb r2, [r2, #3] + 800af14: 4413 add r3, r2 + 800af16: 461a mov r2, r3 + 800af18: 4911 ldr r1, [pc, #68] @ (800af60 ) + 800af1a: 480f ldr r0, [pc, #60] @ (800af58 ) + 800af1c: f000 fa1b bl 800b356 + /*Configure the Transmitter to send all*/ + *outSize = ( uint8_t ) size + RFWPacket.Init.PayloadLengthFieldSize + RFWPacket.Init.CrcFieldSize; + 800af20: 4b0d ldr r3, [pc, #52] @ (800af58 ) + 800af22: 785a ldrb r2, [r3, #1] + 800af24: 7afb ldrb r3, [r7, #11] + 800af26: 4413 add r3, r2 + 800af28: b2da uxtb r2, r3 + 800af2a: 4b0b ldr r3, [pc, #44] @ (800af58 ) + 800af2c: 78db ldrb r3, [r3, #3] + 800af2e: 4413 add r3, r2 + 800af30: b2da uxtb r2, r3 + 800af32: 687b ldr r3, [r7, #4] + 800af34: 701a strb r2, [r3, #0] + /*copy result*/ + RADIO_MEMCPY8( inOutBuffer, ChunkBuffer, *outSize ); + 800af36: 687b ldr r3, [r7, #4] + 800af38: 781b ldrb r3, [r3, #0] + 800af3a: 461a mov r2, r3 + 800af3c: 4908 ldr r1, [pc, #32] @ (800af60 ) + 800af3e: 68f8 ldr r0, [r7, #12] + 800af40: f001 f8d4 bl 800c0ec + + RFWPacket.LongPacketModeEnable = 0; + 800af44: 4b04 ldr r3, [pc, #16] @ (800af58 ) + 800af46: 2200 movs r2, #0 + 800af48: 769a strb r2, [r3, #26] + + status = 0; + 800af4a: 2300 movs r3, #0 + 800af4c: 617b str r3, [r7, #20] + } +#endif /* RFW_ENABLE == 1 */ + return status; + 800af4e: 697b ldr r3, [r7, #20] +} + 800af50: 4618 mov r0, r3 + 800af52: 3718 adds r7, #24 + 800af54: 46bd mov sp, r7 + 800af56: bd80 pop {r7, pc} + 800af58: 2000032c .word 0x2000032c + 800af5c: 0800d5c4 .word 0x0800d5c4 + 800af60: 20000380 .word 0x20000380 + +0800af64 : + +int32_t RFW_ReceiveInit( void ) +{ + 800af64: b580 push {r7, lr} + 800af66: af00 add r7, sp, #0 +#if (RFW_ENABLE == 1 ) + /* Radio IRQ is set to DIO1 by default */ + SUBGRF_SetDioIrqParams( IRQ_RADIO_ALL & ( ~IRQ_RX_DONE ), /* IRQ_RX_DONE | IRQ_RX_TX_TIMEOUT, */ + 800af68: 2300 movs r3, #0 + 800af6a: 2200 movs r2, #0 + 800af6c: f64f 71fd movw r1, #65533 @ 0xfffd + 800af70: f64f 70fd movw r0, #65533 @ 0xfffd + 800af74: f7fe fe26 bl 8009bc4 + IRQ_RADIO_ALL & ( ~IRQ_RX_DONE ), /* IRQ_RX_DONE | IRQ_RX_TX_TIMEOUT, */ + IRQ_RADIO_NONE, + IRQ_RADIO_NONE ); + + /*init whitening at beginning of the packet*/ + RFW_WhiteSetState( &RFWPacket ); + 800af78: 4807 ldr r0, [pc, #28] @ (800af98 ) + 800af7a: f000 f9b7 bl 800b2ec + /* Set the state of the Crc to crc_seed*/ + RFW_CrcSetState( &RFWPacket ); + 800af7e: 4806 ldr r0, [pc, #24] @ (800af98 ) + 800af80: f000 f9dc bl 800b33c + + RFWPacket.RxPayloadOffset = 0; + 800af84: 4b04 ldr r3, [pc, #16] @ (800af98 ) + 800af86: 2200 movs r2, #0 + 800af88: 871a strh r2, [r3, #56] @ 0x38 + + RFWPacket.LongPacketModeEnable = 0; + 800af8a: 4b03 ldr r3, [pc, #12] @ (800af98 ) + 800af8c: 2200 movs r2, #0 + 800af8e: 769a strb r2, [r3, #26] + return 0; + 800af90: 2300 movs r3, #0 +#else + return -1; +#endif /* RFW_ENABLE == 1 */ +} + 800af92: 4618 mov r0, r3 + 800af94: bd80 pop {r7, pc} + 800af96: bf00 nop + 800af98: 2000032c .word 0x2000032c + +0800af9c : + +void RFW_DeInit_TxLongPacket( void ) +{ + 800af9c: b580 push {r7, lr} + 800af9e: b082 sub sp, #8 + 800afa0: af00 add r7, sp, #0 +#if (RFW_LONGPACKET_ENABLE == 1 ) + /*long packet WA*/ + uint8_t reg = SUBGRF_ReadRegister( SUBGHZ_GPKTCTL1AR ); + 800afa2: f44f 60d7 mov.w r0, #1720 @ 0x6b8 + 800afa6: f7ff f9d9 bl 800a35c + 800afaa: 4603 mov r3, r0 + 800afac: 71fb strb r3, [r7, #7] + SUBGRF_WriteRegister( SUBGHZ_GPKTCTL1AR, reg & ~0x02 ); /* clear infinite_sequence bit */ + 800afae: 79fb ldrb r3, [r7, #7] + 800afb0: f023 0302 bic.w r3, r3, #2 + 800afb4: b2db uxtb r3, r3 + 800afb6: 4619 mov r1, r3 + 800afb8: f44f 60d7 mov.w r0, #1720 @ 0x6b8 + 800afbc: f7ff f9ac bl 800a318 + SUBGRF_WriteRegister( SUBGHZ_GRTXPLDLEN, 0xFF ); /* RxTxPldLen: reset to 0xFF */ + 800afc0: 21ff movs r1, #255 @ 0xff + 800afc2: f240 60bb movw r0, #1723 @ 0x6bb + 800afc6: f7ff f9a7 bl 800a318 +#endif /* RFW_LONGPACKET_ENABLE == 1 */ +} + 800afca: bf00 nop + 800afcc: 3708 adds r7, #8 + 800afce: 46bd mov sp, r7 + 800afd0: bd80 pop {r7, pc} + ... + +0800afd4 : + +void RFW_ReceivePayload( void ) +{ + 800afd4: b580 push {r7, lr} + 800afd6: b086 sub sp, #24 + 800afd8: af02 add r7, sp, #8 +#if (RFW_ENABLE == 1 ) + uint16_t PayloadLength = 0; + 800afda: 2300 movs r3, #0 + 800afdc: 80fb strh r3, [r7, #6] + if( RFW_GetPacketLength( &PayloadLength ) == 0 ) + 800afde: 1dbb adds r3, r7, #6 + 800afe0: 4618 mov r0, r3 + 800afe2: f000 fab7 bl 800b554 + 800afe6: 4603 mov r3, r0 + 800afe8: 2b00 cmp r3, #0 + 800afea: d15e bne.n 800b0aa + { + uint32_t timeout; + uint32_t packet_length = PayloadLength + RFWPacket.Init.CrcFieldSize; + 800afec: 88fb ldrh r3, [r7, #6] + 800afee: 461a mov r2, r3 + 800aff0: 4b33 ldr r3, [pc, #204] @ (800b0c0 ) + 800aff2: 78db ldrb r3, [r3, #3] + 800aff4: 4413 add r3, r2 + 800aff6: 60bb str r3, [r7, #8] + /*record payload length*/ + RFWPacket.PayloadLength = PayloadLength; + 800aff8: 88fa ldrh r2, [r7, #6] + 800affa: 4b31 ldr r3, [pc, #196] @ (800b0c0 ) + 800affc: 831a strh r2, [r3, #24] + /*record remaining payload length*/ + RFWPacket.LongPacketRemainingBytes = ( uint16_t ) packet_length; + 800affe: 68bb ldr r3, [r7, #8] + 800b000: b29a uxth r2, r3 + 800b002: 4b2f ldr r3, [pc, #188] @ (800b0c0 ) + 800b004: 869a strh r2, [r3, #52] @ 0x34 + /*record rx buffer offset*/ + RFWPacket.RadioBufferOffset = RFWPacket.Init.PayloadLengthFieldSize; + 800b006: 4b2e ldr r3, [pc, #184] @ (800b0c0 ) + 800b008: 785a ldrb r2, [r3, #1] + 800b00a: 4b2d ldr r3, [pc, #180] @ (800b0c0 ) + 800b00c: f883 2036 strb.w r2, [r3, #54] @ 0x36 + /*if decoded PayloadLength is longer than LongPacketMaxRxLength, reject packet*/ + if( PayloadLength > RFWPacket.Init.LongPacketMaxRxLength ) + 800b010: 4b2b ldr r3, [pc, #172] @ (800b0c0 ) + 800b012: 899a ldrh r2, [r3, #12] + 800b014: 88fb ldrh r3, [r7, #6] + 800b016: 429a cmp r2, r3 + 800b018: d207 bcs.n 800b02a + { + SUBGRF_SetStandby( STDBY_RC ); + 800b01a: 2000 movs r0, #0 + 800b01c: f7fe fbf8 bl 8009810 + RFWPacket.Init.RadioEvents->RxError( ); + 800b020: 4b27 ldr r3, [pc, #156] @ (800b0c0 ) + 800b022: 691b ldr r3, [r3, #16] + 800b024: 691b ldr r3, [r3, #16] + 800b026: 4798 blx r3 + 800b028: e046 b.n 800b0b8 + return; + } + if( packet_length < LONGPACKET_CHUNK_LENGTH_BYTES ) + 800b02a: 68bb ldr r3, [r7, #8] + 800b02c: 2b7f cmp r3, #127 @ 0x7f + 800b02e: d817 bhi.n 800b060 + { + /* all in one chunks*/ + /* calculate time to end of packet*/ + timeout = DIVC( ( packet_length ) * 8 * 1000, RFWPacket.BitRate ) + 2; + 800b030: 68bb ldr r3, [r7, #8] + 800b032: f44f 52fa mov.w r2, #8000 @ 0x1f40 + 800b036: fb03 f202 mul.w r2, r3, r2 + 800b03a: 4b21 ldr r3, [pc, #132] @ (800b0c0 ) + 800b03c: 6c9b ldr r3, [r3, #72] @ 0x48 + 800b03e: 4413 add r3, r2 + 800b040: 1e5a subs r2, r3, #1 + 800b042: 4b1f ldr r3, [pc, #124] @ (800b0c0 ) + 800b044: 6c9b ldr r3, [r3, #72] @ 0x48 + 800b046: fbb2 f3f3 udiv r3, r2, r3 + 800b04a: 3302 adds r3, #2 + 800b04c: 60fb str r3, [r7, #12] + /**/ + /* start timer at the end of the packet*/ + RFW_MW_LOG( TS_ON, VLEVEL_M, "end packet in %dms\r\n", timeout ); + 800b04e: 68fb ldr r3, [r7, #12] + 800b050: 9300 str r3, [sp, #0] + 800b052: 4b1c ldr r3, [pc, #112] @ (800b0c4 ) + 800b054: 2201 movs r2, #1 + 800b056: 2100 movs r1, #0 + 800b058: 2002 movs r0, #2 + 800b05a: f001 ff93 bl 800cf84 + 800b05e: e01c b.n 800b09a + + } + else if( packet_length < ( 3 * LONGPACKET_CHUNK_LENGTH_BYTES / 2 ) ) + 800b060: 68bb ldr r3, [r7, #8] + 800b062: 2bbf cmp r3, #191 @ 0xbf + 800b064: d80f bhi.n 800b086 + { + /* packet contained in 2 chunks*/ + /* make sure that crc not cut in chunk*/ + timeout = DIVR( ( packet_length * 8 * 1000 ) / 2, RFWPacket.BitRate ); + 800b066: 68bb ldr r3, [r7, #8] + 800b068: f44f 52fa mov.w r2, #8000 @ 0x1f40 + 800b06c: fb02 f303 mul.w r3, r2, r3 + 800b070: 085a lsrs r2, r3, #1 + 800b072: 4b13 ldr r3, [pc, #76] @ (800b0c0 ) + 800b074: 6c9b ldr r3, [r3, #72] @ 0x48 + 800b076: 085b lsrs r3, r3, #1 + 800b078: 441a add r2, r3 + 800b07a: 4b11 ldr r3, [pc, #68] @ (800b0c0 ) + 800b07c: 6c9b ldr r3, [r3, #72] @ 0x48 + 800b07e: fbb2 f3f3 udiv r3, r2, r3 + 800b082: 60fb str r3, [r7, #12] + 800b084: e009 b.n 800b09a + } + else + { + /* packet contained in multiple chunk*/ + /* program radio timer for first chunk*/ + timeout = DIVR( LONGPACKET_CHUNK_LENGTH_BYTES * 8 * 1000, RFWPacket.BitRate ); + 800b086: 4b0e ldr r3, [pc, #56] @ (800b0c0 ) + 800b088: 6c9b ldr r3, [r3, #72] @ 0x48 + 800b08a: 085b lsrs r3, r3, #1 + 800b08c: f503 227a add.w r2, r3, #1024000 @ 0xfa000 + 800b090: 4b0b ldr r3, [pc, #44] @ (800b0c0 ) + 800b092: 6c9b ldr r3, [r3, #72] @ 0x48 + 800b094: fbb2 f3f3 udiv r3, r2, r3 + 800b098: 60fb str r3, [r7, #12] + } + TimerSetValue( &RFWPacket.Timer, timeout ); + 800b09a: 68f9 ldr r1, [r7, #12] + 800b09c: 480a ldr r0, [pc, #40] @ (800b0c8 ) + 800b09e: f001 fde9 bl 800cc74 + TimerStart( &RFWPacket.Timer ); + 800b0a2: 4809 ldr r0, [pc, #36] @ (800b0c8 ) + 800b0a4: f001 fd08 bl 800cab8 + 800b0a8: e006 b.n 800b0b8 + } + else + { + /*timeout*/ + SUBGRF_SetStandby( STDBY_RC ); + 800b0aa: 2000 movs r0, #0 + 800b0ac: f7fe fbb0 bl 8009810 + RFWPacket.Init.RadioEvents->RxTimeout( ); + 800b0b0: 4b03 ldr r3, [pc, #12] @ (800b0c0 ) + 800b0b2: 691b ldr r3, [r3, #16] + 800b0b4: 68db ldr r3, [r3, #12] + 800b0b6: 4798 blx r3 + } +#endif /* RFW_ENABLE == 1 */ +} + 800b0b8: 3710 adds r7, #16 + 800b0ba: 46bd mov sp, r7 + 800b0bc: bd80 pop {r7, pc} + 800b0be: bf00 nop + 800b0c0: 2000032c .word 0x2000032c + 800b0c4: 0800d5dc .word 0x0800d5dc + 800b0c8: 20000348 .word 0x20000348 + +0800b0cc : + +void RFW_SetRadioModem( RadioModems_t Modem ) +{ + 800b0cc: b480 push {r7} + 800b0ce: b083 sub sp, #12 + 800b0d0: af00 add r7, sp, #0 + 800b0d2: 4603 mov r3, r0 + 800b0d4: 71fb strb r3, [r7, #7] +#if (RFW_ENABLE == 1 ) + RFWPacket.Init.Modem = Modem; + 800b0d6: 4a04 ldr r2, [pc, #16] @ (800b0e8 ) + 800b0d8: 79fb ldrb r3, [r7, #7] + 800b0da: 7393 strb r3, [r2, #14] +#endif /* RFW_ENABLE == 1 */ +} + 800b0dc: bf00 nop + 800b0de: 370c adds r7, #12 + 800b0e0: 46bd mov sp, r7 + 800b0e2: bc80 pop {r7} + 800b0e4: 4770 bx lr + 800b0e6: bf00 nop + 800b0e8: 2000032c .word 0x2000032c + +0800b0ec : + +/* Private Functions Definition -----------------------------------------------*/ +#if (RFW_LONGPACKET_ENABLE == 1 ) +static void RFW_TransmitLongPacket_NewTxChunkTimerEvent( void *param ) +{ + 800b0ec: b580 push {r7, lr} + 800b0ee: b082 sub sp, #8 + 800b0f0: af00 add r7, sp, #0 + 800b0f2: 6078 str r0, [r7, #4] + RFW_TRANSMIT_LONGPACKET_TX_CHUNK_PROCESS(); + 800b0f4: f000 f804 bl 800b100 +} + 800b0f8: bf00 nop + 800b0fa: 3708 adds r7, #8 + 800b0fc: 46bd mov sp, r7 + 800b0fe: bd80 pop {r7, pc} + +0800b100 : + +static void RFW_TransmitLongPacket_TxChunkProcess( void ) +{ + 800b100: b590 push {r4, r7, lr} + 800b102: b08d sub sp, #52 @ 0x34 + 800b104: af06 add r7, sp, #24 + uint8_t *app_chunk_buffer_ptr = NULL; + 800b106: 2300 movs r3, #0 + 800b108: 60bb str r3, [r7, #8] + uint8_t chunk_size = 0; + 800b10a: 2300 movs r3, #0 + 800b10c: 75fb strb r3, [r7, #23] + uint8_t crc_result[2] = {0}; + 800b10e: 2300 movs r3, #0 + 800b110: 80bb strh r3, [r7, #4] + uint8_t crc_size; + uint32_t timeout;/*timeout for next chunk*/ + /*records how much has been sent*/ + uint8_t read_ptr = SUBGRF_ReadRegister( SUBGHZ_TXADRPTR ); /*radio has transmitted up to read_ptr*/ + 800b112: f640 0002 movw r0, #2050 @ 0x802 + 800b116: f7ff f921 bl 800a35c + 800b11a: 4603 mov r3, r0 + 800b11c: 757b strb r3, [r7, #21] + uint8_t write_ptr = SUBGRF_ReadRegister( SUBGHZ_GRTXPLDLEN ); /*from read_ptr to write_ptr still to be transmitted*/ + 800b11e: f240 60bb movw r0, #1723 @ 0x6bb + 800b122: f7ff f91b bl 800a35c + 800b126: 4603 mov r3, r0 + 800b128: 753b strb r3, [r7, #20] + /*calculates how much bytes were sent since previous radio loading*/ + uint8_t bytes_sent = read_ptr - RFWPacket.RadioBufferOffset; + 800b12a: 4b64 ldr r3, [pc, #400] @ (800b2bc ) + 800b12c: f893 3036 ldrb.w r3, [r3, #54] @ 0x36 + 800b130: 7d7a ldrb r2, [r7, #21] + 800b132: 1ad3 subs r3, r2, r3 + 800b134: 74fb strb r3, [r7, #19] + /*bytes already loaded in the radio to send*/ + uint8_t bytes_loaded = write_ptr - read_ptr; + 800b136: 7d3a ldrb r2, [r7, #20] + 800b138: 7d7b ldrb r3, [r7, #21] + 800b13a: 1ad3 subs r3, r2, r3 + 800b13c: 74bb strb r3, [r7, #18] + + /* Update offset tx, intentional wrap around*/ + RFWPacket.RadioBufferOffset += bytes_sent; + 800b13e: 4b5f ldr r3, [pc, #380] @ (800b2bc ) + 800b140: f893 2036 ldrb.w r2, [r3, #54] @ 0x36 + 800b144: 7cfb ldrb r3, [r7, #19] + 800b146: 4413 add r3, r2 + 800b148: b2da uxtb r2, r3 + 800b14a: 4b5c ldr r3, [pc, #368] @ (800b2bc ) + 800b14c: f883 2036 strb.w r2, [r3, #54] @ 0x36 + /*record payload remaining bytes to send*/ + RFWPacket.LongPacketRemainingBytes -= bytes_sent; + 800b150: 4b5a ldr r3, [pc, #360] @ (800b2bc ) + 800b152: 8e9a ldrh r2, [r3, #52] @ 0x34 + 800b154: 7cfb ldrb r3, [r7, #19] + 800b156: b29b uxth r3, r3 + 800b158: 1ad3 subs r3, r2, r3 + 800b15a: b29a uxth r2, r3 + 800b15c: 4b57 ldr r3, [pc, #348] @ (800b2bc ) + 800b15e: 869a strh r2, [r3, #52] @ 0x34 + RFW_MW_LOG( TS_ON, VLEVEL_M, "read_ptr=%d, write_ptr=%d, bytes_sent=%d, bytes_loaded=%d,remaining to send=%d\r\n", + 800b160: 7d7b ldrb r3, [r7, #21] + 800b162: 7d3a ldrb r2, [r7, #20] + 800b164: 7cf9 ldrb r1, [r7, #19] + 800b166: 7cb8 ldrb r0, [r7, #18] + 800b168: 4c54 ldr r4, [pc, #336] @ (800b2bc ) + 800b16a: 8ea4 ldrh r4, [r4, #52] @ 0x34 + 800b16c: 9404 str r4, [sp, #16] + 800b16e: 9003 str r0, [sp, #12] + 800b170: 9102 str r1, [sp, #8] + 800b172: 9201 str r2, [sp, #4] + 800b174: 9300 str r3, [sp, #0] + 800b176: 4b52 ldr r3, [pc, #328] @ (800b2c0 ) + 800b178: 2201 movs r2, #1 + 800b17a: 2100 movs r1, #0 + 800b17c: 2002 movs r0, #2 + 800b17e: f001 ff01 bl 800cf84 + read_ptr, write_ptr, bytes_sent, bytes_loaded, RFWPacket.LongPacketRemainingBytes ); + if( RFWPacket.LongPacketRemainingBytes > 256 ) + 800b182: 4b4e ldr r3, [pc, #312] @ (800b2bc ) + 800b184: 8e9b ldrh r3, [r3, #52] @ 0x34 + 800b186: f5b3 7f80 cmp.w r3, #256 @ 0x100 + 800b18a: d929 bls.n 800b1e0 + { + /*get next chunk */ + /*make sure that at least full CrcFieldSize will be loaded for the last chunk*/ + if( RFWPacket.LongPacketRemainingBytes > 256 + RFWPacket.Init.CrcFieldSize ) + 800b18c: 4b4b ldr r3, [pc, #300] @ (800b2bc ) + 800b18e: 8e9b ldrh r3, [r3, #52] @ 0x34 + 800b190: 461a mov r2, r3 + 800b192: 4b4a ldr r3, [pc, #296] @ (800b2bc ) + 800b194: 78db ldrb r3, [r3, #3] + 800b196: f503 7380 add.w r3, r3, #256 @ 0x100 + 800b19a: 429a cmp r2, r3 + 800b19c: dd02 ble.n 800b1a4 + { + chunk_size = bytes_sent; + 800b19e: 7cfb ldrb r3, [r7, #19] + 800b1a0: 75fb strb r3, [r7, #23] + 800b1a2: e004 b.n 800b1ae + } + else + { + chunk_size = bytes_sent - RFWPacket.Init.CrcFieldSize; + 800b1a4: 4b45 ldr r3, [pc, #276] @ (800b2bc ) + 800b1a6: 78db ldrb r3, [r3, #3] + 800b1a8: 7cfa ldrb r2, [r7, #19] + 800b1aa: 1ad3 subs r3, r2, r3 + 800b1ac: 75fb strb r3, [r7, #23] + } + /*no crc since it is not the last chunk*/ + crc_size = 0; + 800b1ae: 2300 movs r3, #0 + 800b1b0: 75bb strb r3, [r7, #22] + /*calculate timeout for next chunk*/ + timeout = DIVR( chunk_size * 8 * 1000, RFWPacket.BitRate ); + 800b1b2: 7dfb ldrb r3, [r7, #23] + 800b1b4: f44f 52fa mov.w r2, #8000 @ 0x1f40 + 800b1b8: fb02 f303 mul.w r3, r2, r3 + 800b1bc: 461a mov r2, r3 + 800b1be: 4b3f ldr r3, [pc, #252] @ (800b2bc ) + 800b1c0: 6c9b ldr r3, [r3, #72] @ 0x48 + 800b1c2: 085b lsrs r3, r3, #1 + 800b1c4: 441a add r2, r3 + 800b1c6: 4b3d ldr r3, [pc, #244] @ (800b2bc ) + 800b1c8: 6c9b ldr r3, [r3, #72] @ 0x48 + 800b1ca: fbb2 f3f3 udiv r3, r2, r3 + 800b1ce: 60fb str r3, [r7, #12] + + TimerSetValue( &RFWPacket.Timer, timeout ); + 800b1d0: 68f9 ldr r1, [r7, #12] + 800b1d2: 483c ldr r0, [pc, #240] @ (800b2c4 ) + 800b1d4: f001 fd4e bl 800cc74 + TimerStart( &RFWPacket.Timer ); + 800b1d8: 483a ldr r0, [pc, #232] @ (800b2c4 ) + 800b1da: f001 fc6d bl 800cab8 + 800b1de: e015 b.n 800b20c + } + else + { + /*last chunk to send*/ + + if( RFWPacket.LongPacketRemainingBytes > bytes_loaded ) + 800b1e0: 4b36 ldr r3, [pc, #216] @ (800b2bc ) + 800b1e2: 8e9a ldrh r2, [r3, #52] @ 0x34 + 800b1e4: 7cbb ldrb r3, [r7, #18] + 800b1e6: b29b uxth r3, r3 + 800b1e8: 429a cmp r2, r3 + 800b1ea: d906 bls.n 800b1fa + { + chunk_size = RFWPacket.LongPacketRemainingBytes - bytes_loaded; + 800b1ec: 4b33 ldr r3, [pc, #204] @ (800b2bc ) + 800b1ee: 8e9b ldrh r3, [r3, #52] @ 0x34 + 800b1f0: b2da uxtb r2, r3 + 800b1f2: 7cbb ldrb r3, [r7, #18] + 800b1f4: 1ad3 subs r3, r2, r3 + 800b1f6: 75fb strb r3, [r7, #23] + 800b1f8: e002 b.n 800b200 + } + else/* nothing to load anymore*/ + { + chunk_size = RFWPacket.Init.CrcFieldSize; + 800b1fa: 4b30 ldr r3, [pc, #192] @ (800b2bc ) + 800b1fc: 78db ldrb r3, [r3, #3] + 800b1fe: 75fb strb r3, [r7, #23] + } + /* crc, since it is the last chunk*/ + crc_size = RFWPacket.Init.CrcFieldSize; + 800b200: 4b2e ldr r3, [pc, #184] @ (800b2bc ) + 800b202: 78db ldrb r3, [r3, #3] + 800b204: 75bb strb r3, [r7, #22] + /*no more bytes to send*/ + RFWPacket.LongPacketRemainingBytes = 0; + 800b206: 4b2d ldr r3, [pc, #180] @ (800b2bc ) + 800b208: 2200 movs r2, #0 + 800b20a: 869a strh r2, [r3, #52] @ 0x34 + /*no need to program another timer, Tx done will complete the Tx process*/ + } + /*get new chunk from the app*/ + RFWPacket.TxLongPacketGetNextChunkCb( &app_chunk_buffer_ptr, chunk_size - crc_size ); + 800b20c: 4b2b ldr r3, [pc, #172] @ (800b2bc ) + 800b20e: 6c1b ldr r3, [r3, #64] @ 0x40 + 800b210: 7df9 ldrb r1, [r7, #23] + 800b212: 7dba ldrb r2, [r7, #22] + 800b214: 1a8a subs r2, r1, r2 + 800b216: b2d1 uxtb r1, r2 + 800b218: f107 0208 add.w r2, r7, #8 + 800b21c: 4610 mov r0, r2 + 800b21e: 4798 blx r3 + /* Copy app_chunk_buffer_ptr in ChunkBuffer Buffer*/ + RADIO_MEMCPY8( ChunkBuffer, app_chunk_buffer_ptr, chunk_size - crc_size ); + 800b220: 68b9 ldr r1, [r7, #8] + 800b222: 7dfb ldrb r3, [r7, #23] + 800b224: b29a uxth r2, r3 + 800b226: 7dbb ldrb r3, [r7, #22] + 800b228: b29b uxth r3, r3 + 800b22a: 1ad3 subs r3, r2, r3 + 800b22c: b29b uxth r3, r3 + 800b22e: 461a mov r2, r3 + 800b230: 4825 ldr r0, [pc, #148] @ (800b2c8 ) + 800b232: f000 ff5b bl 800c0ec + if( RFWPacket.Init.CrcEnable == 1 ) + 800b236: 4b21 ldr r3, [pc, #132] @ (800b2bc ) + 800b238: 789b ldrb r3, [r3, #2] + 800b23a: 2b01 cmp r3, #1 + 800b23c: d113 bne.n 800b266 + { + /* Run the crc calculation on payload length and payload*/ + RFW_CrcRun( &RFWPacket, ChunkBuffer, chunk_size - crc_size, crc_result ); + 800b23e: 7dfa ldrb r2, [r7, #23] + 800b240: 7dbb ldrb r3, [r7, #22] + 800b242: 1ad3 subs r3, r2, r3 + 800b244: 461a mov r2, r3 + 800b246: 1d3b adds r3, r7, #4 + 800b248: 491f ldr r1, [pc, #124] @ (800b2c8 ) + 800b24a: 481c ldr r0, [pc, #112] @ (800b2bc ) + 800b24c: f000 f8cb bl 800b3e6 + /* Append the crc result after the payload (if last chunk)*/ + RADIO_MEMCPY8( &ChunkBuffer[chunk_size - crc_size], crc_result, crc_size ); + 800b250: 7dfa ldrb r2, [r7, #23] + 800b252: 7dbb ldrb r3, [r7, #22] + 800b254: 1ad3 subs r3, r2, r3 + 800b256: 4a1c ldr r2, [pc, #112] @ (800b2c8 ) + 800b258: 4413 add r3, r2 + 800b25a: 7dba ldrb r2, [r7, #22] + 800b25c: b292 uxth r2, r2 + 800b25e: 1d39 adds r1, r7, #4 + 800b260: 4618 mov r0, r3 + 800b262: f000 ff43 bl 800c0ec + } + /* Run the whitening calculation on payload length, payload and crc*/ + RFW_WhiteRun( &RFWPacket, ChunkBuffer, chunk_size ); + 800b266: 7dfb ldrb r3, [r7, #23] + 800b268: 461a mov r2, r3 + 800b26a: 4917 ldr r1, [pc, #92] @ (800b2c8 ) + 800b26c: 4813 ldr r0, [pc, #76] @ (800b2bc ) + 800b26e: f000 f872 bl 800b356 + /*write next chunk*/ + SUBGRF_WriteBuffer( write_ptr, ChunkBuffer, chunk_size ); + 800b272: 7dfa ldrb r2, [r7, #23] + 800b274: 7d3b ldrb r3, [r7, #20] + 800b276: 4914 ldr r1, [pc, #80] @ (800b2c8 ) + 800b278: 4618 mov r0, r3 + 800b27a: f7ff f8d3 bl 800a424 + + /*update end ptr*/ + SUBGRF_WriteRegister( SUBGHZ_GRTXPLDLEN, ( uint8_t )( chunk_size + write_ptr ) ); + 800b27e: 7dfa ldrb r2, [r7, #23] + 800b280: 7d3b ldrb r3, [r7, #20] + 800b282: 4413 add r3, r2 + 800b284: b2db uxtb r3, r3 + 800b286: 4619 mov r1, r3 + 800b288: f240 60bb movw r0, #1723 @ 0x6bb + 800b28c: f7ff f844 bl 800a318 + + RFW_MW_LOG( TS_ON, VLEVEL_M, "next chunk size=%d, new write ptr=%d\n\r", chunk_size + crc_size, + 800b290: 7dfa ldrb r2, [r7, #23] + 800b292: 7dbb ldrb r3, [r7, #22] + 800b294: 4413 add r3, r2 + 800b296: 7df9 ldrb r1, [r7, #23] + 800b298: 7dba ldrb r2, [r7, #22] + 800b29a: 440a add r2, r1 + 800b29c: b2d1 uxtb r1, r2 + 800b29e: 7d3a ldrb r2, [r7, #20] + 800b2a0: 440a add r2, r1 + 800b2a2: b2d2 uxtb r2, r2 + 800b2a4: 9201 str r2, [sp, #4] + 800b2a6: 9300 str r3, [sp, #0] + 800b2a8: 4b08 ldr r3, [pc, #32] @ (800b2cc ) + 800b2aa: 2201 movs r2, #1 + 800b2ac: 2100 movs r1, #0 + 800b2ae: 2002 movs r0, #2 + 800b2b0: f001 fe68 bl 800cf84 + ( uint8_t )( chunk_size + crc_size + write_ptr ) ); +} + 800b2b4: bf00 nop + 800b2b6: 371c adds r7, #28 + 800b2b8: 46bd mov sp, r7 + 800b2ba: bd90 pop {r4, r7, pc} + 800b2bc: 2000032c .word 0x2000032c + 800b2c0: 0800d5f4 .word 0x0800d5f4 + 800b2c4: 20000348 .word 0x20000348 + 800b2c8: 20000380 .word 0x20000380 + 800b2cc: 0800d648 .word 0x0800d648 + +0800b2d0 : +#endif /* RFW_LONGPACKET_ENABLE == 1 */ + +#if (RFW_ENABLE == 1 ) +static void RFW_WhiteInitState( RFwInit_t *Init, uint16_t WhiteSeed ) +{ + 800b2d0: b480 push {r7} + 800b2d2: b083 sub sp, #12 + 800b2d4: af00 add r7, sp, #0 + 800b2d6: 6078 str r0, [r7, #4] + 800b2d8: 460b mov r3, r1 + 800b2da: 807b strh r3, [r7, #2] + Init->WhiteSeed = WhiteSeed; + 800b2dc: 687b ldr r3, [r7, #4] + 800b2de: 887a ldrh r2, [r7, #2] + 800b2e0: 815a strh r2, [r3, #10] +} + 800b2e2: bf00 nop + 800b2e4: 370c adds r7, #12 + 800b2e6: 46bd mov sp, r7 + 800b2e8: bc80 pop {r7} + 800b2ea: 4770 bx lr + +0800b2ec : + +static void RFW_WhiteSetState( RadioFw_t *RFWPacket ) +{ + 800b2ec: b480 push {r7} + 800b2ee: b083 sub sp, #12 + 800b2f0: af00 add r7, sp, #0 + 800b2f2: 6078 str r0, [r7, #4] + RFWPacket->WhiteLfsrState = RFWPacket->Init.WhiteSeed; + 800b2f4: 687b ldr r3, [r7, #4] + 800b2f6: 895a ldrh r2, [r3, #10] + 800b2f8: 687b ldr r3, [r7, #4] + 800b2fa: 82da strh r2, [r3, #22] +} + 800b2fc: bf00 nop + 800b2fe: 370c adds r7, #12 + 800b300: 46bd mov sp, r7 + 800b302: bc80 pop {r7} + 800b304: 4770 bx lr + +0800b306 : + +static void RFW_CrcInitState( RFwInit_t *Init, const uint16_t CrcPolynomial, const uint16_t CrcSeed, + const RADIO_FSK_CrcTypes_t CrcType ) +{ + 800b306: b480 push {r7} + 800b308: b085 sub sp, #20 + 800b30a: af00 add r7, sp, #0 + 800b30c: 60f8 str r0, [r7, #12] + 800b30e: 4608 mov r0, r1 + 800b310: 4611 mov r1, r2 + 800b312: 461a mov r2, r3 + 800b314: 4603 mov r3, r0 + 800b316: 817b strh r3, [r7, #10] + 800b318: 460b mov r3, r1 + 800b31a: 813b strh r3, [r7, #8] + 800b31c: 4613 mov r3, r2 + 800b31e: 71fb strb r3, [r7, #7] + Init->CrcPolynomial = CrcPolynomial; + 800b320: 68fb ldr r3, [r7, #12] + 800b322: 897a ldrh r2, [r7, #10] + 800b324: 809a strh r2, [r3, #4] + Init->CrcSeed = CrcSeed; + 800b326: 68fb ldr r3, [r7, #12] + 800b328: 893a ldrh r2, [r7, #8] + 800b32a: 80da strh r2, [r3, #6] + Init->CrcType = CrcType; + 800b32c: 68fb ldr r3, [r7, #12] + 800b32e: 79fa ldrb r2, [r7, #7] + 800b330: 721a strb r2, [r3, #8] +} + 800b332: bf00 nop + 800b334: 3714 adds r7, #20 + 800b336: 46bd mov sp, r7 + 800b338: bc80 pop {r7} + 800b33a: 4770 bx lr + +0800b33c : + +static void RFW_CrcSetState( RadioFw_t *RFWPacket ) +{ + 800b33c: b480 push {r7} + 800b33e: b083 sub sp, #12 + 800b340: af00 add r7, sp, #0 + 800b342: 6078 str r0, [r7, #4] + RFWPacket->CrcLfsrState = RFWPacket->Init.CrcSeed; + 800b344: 687b ldr r3, [r7, #4] + 800b346: 88da ldrh r2, [r3, #6] + 800b348: 687b ldr r3, [r7, #4] + 800b34a: 829a strh r2, [r3, #20] +} + 800b34c: bf00 nop + 800b34e: 370c adds r7, #12 + 800b350: 46bd mov sp, r7 + 800b352: bc80 pop {r7} + 800b354: 4770 bx lr + +0800b356 : + +static void RFW_WhiteRun( RadioFw_t *RFWPacket, uint8_t *Payload, uint32_t Size ) +{ + 800b356: b480 push {r7} + 800b358: b089 sub sp, #36 @ 0x24 + 800b35a: af00 add r7, sp, #0 + 800b35c: 60f8 str r0, [r7, #12] + 800b35e: 60b9 str r1, [r7, #8] + 800b360: 607a str r2, [r7, #4] + /*run the whitening algo on Size bytes*/ + uint16_t ibmwhite_state = RFWPacket->WhiteLfsrState; + 800b362: 68fb ldr r3, [r7, #12] + 800b364: 8adb ldrh r3, [r3, #22] + 800b366: 83fb strh r3, [r7, #30] + for( int32_t i = 0; i < Size; i++ ) + 800b368: 2300 movs r3, #0 + 800b36a: 61bb str r3, [r7, #24] + 800b36c: e02f b.n 800b3ce + { + Payload[i] ^= ibmwhite_state & 0xFF; + 800b36e: 69bb ldr r3, [r7, #24] + 800b370: 68ba ldr r2, [r7, #8] + 800b372: 4413 add r3, r2 + 800b374: 781b ldrb r3, [r3, #0] + 800b376: b25a sxtb r2, r3 + 800b378: 8bfb ldrh r3, [r7, #30] + 800b37a: b25b sxtb r3, r3 + 800b37c: 4053 eors r3, r2 + 800b37e: b259 sxtb r1, r3 + 800b380: 69bb ldr r3, [r7, #24] + 800b382: 68ba ldr r2, [r7, #8] + 800b384: 4413 add r3, r2 + 800b386: b2ca uxtb r2, r1 + 800b388: 701a strb r2, [r3, #0] + for( int32_t j = 0; j < 8; j++ ) + 800b38a: 2300 movs r3, #0 + 800b38c: 617b str r3, [r7, #20] + 800b38e: e018 b.n 800b3c2 + { + uint8_t msb = ( ( ibmwhite_state >> 5 ) & 0x1 ) ^ ( ( ibmwhite_state >> 0 ) & 0x1 ); + 800b390: 8bfb ldrh r3, [r7, #30] + 800b392: 095b lsrs r3, r3, #5 + 800b394: b29b uxth r3, r3 + 800b396: b2da uxtb r2, r3 + 800b398: 8bfb ldrh r3, [r7, #30] + 800b39a: b2db uxtb r3, r3 + 800b39c: 4053 eors r3, r2 + 800b39e: b2db uxtb r3, r3 + 800b3a0: f003 0301 and.w r3, r3, #1 + 800b3a4: 74fb strb r3, [r7, #19] + ibmwhite_state = ( ( msb << 8 ) | ( ibmwhite_state >> 1 ) ); + 800b3a6: 7cfb ldrb r3, [r7, #19] + 800b3a8: b21b sxth r3, r3 + 800b3aa: 021b lsls r3, r3, #8 + 800b3ac: b21a sxth r2, r3 + 800b3ae: 8bfb ldrh r3, [r7, #30] + 800b3b0: 085b lsrs r3, r3, #1 + 800b3b2: b29b uxth r3, r3 + 800b3b4: b21b sxth r3, r3 + 800b3b6: 4313 orrs r3, r2 + 800b3b8: b21b sxth r3, r3 + 800b3ba: 83fb strh r3, [r7, #30] + for( int32_t j = 0; j < 8; j++ ) + 800b3bc: 697b ldr r3, [r7, #20] + 800b3be: 3301 adds r3, #1 + 800b3c0: 617b str r3, [r7, #20] + 800b3c2: 697b ldr r3, [r7, #20] + 800b3c4: 2b07 cmp r3, #7 + 800b3c6: dde3 ble.n 800b390 + for( int32_t i = 0; i < Size; i++ ) + 800b3c8: 69bb ldr r3, [r7, #24] + 800b3ca: 3301 adds r3, #1 + 800b3cc: 61bb str r3, [r7, #24] + 800b3ce: 69bb ldr r3, [r7, #24] + 800b3d0: 687a ldr r2, [r7, #4] + 800b3d2: 429a cmp r2, r3 + 800b3d4: d8cb bhi.n 800b36e + } + } + RFWPacket->WhiteLfsrState = ibmwhite_state; + 800b3d6: 68fb ldr r3, [r7, #12] + 800b3d8: 8bfa ldrh r2, [r7, #30] + 800b3da: 82da strh r2, [r3, #22] +} + 800b3dc: bf00 nop + 800b3de: 3724 adds r7, #36 @ 0x24 + 800b3e0: 46bd mov sp, r7 + 800b3e2: bc80 pop {r7} + 800b3e4: 4770 bx lr + +0800b3e6 : + +static int32_t RFW_CrcRun( RadioFw_t *const RFWPacket, const uint8_t *Payload, const uint32_t Size, + uint8_t CrcResult[2] ) +{ + 800b3e6: b580 push {r7, lr} + 800b3e8: b088 sub sp, #32 + 800b3ea: af00 add r7, sp, #0 + 800b3ec: 60f8 str r0, [r7, #12] + 800b3ee: 60b9 str r1, [r7, #8] + 800b3f0: 607a str r2, [r7, #4] + 800b3f2: 603b str r3, [r7, #0] + int32_t status = 0; + 800b3f4: 2300 movs r3, #0 + 800b3f6: 617b str r3, [r7, #20] + int32_t i = 0; + 800b3f8: 2300 movs r3, #0 + 800b3fa: 61fb str r3, [r7, #28] + uint16_t polynomial = RFWPacket->Init.CrcPolynomial; + 800b3fc: 68fb ldr r3, [r7, #12] + 800b3fe: 889b ldrh r3, [r3, #4] + 800b400: 827b strh r3, [r7, #18] + /* Restore state from previous chunk*/ + uint16_t crc = RFWPacket->CrcLfsrState; + 800b402: 68fb ldr r3, [r7, #12] + 800b404: 8a9b ldrh r3, [r3, #20] + 800b406: 837b strh r3, [r7, #26] + for( i = 0; i < Size; i++ ) + 800b408: 2300 movs r3, #0 + 800b40a: 61fb str r3, [r7, #28] + 800b40c: e00d b.n 800b42a + { + crc = RFW_CrcRun1Byte( crc, Payload[i], polynomial ); + 800b40e: 69fb ldr r3, [r7, #28] + 800b410: 68ba ldr r2, [r7, #8] + 800b412: 4413 add r3, r2 + 800b414: 7819 ldrb r1, [r3, #0] + 800b416: 8a7a ldrh r2, [r7, #18] + 800b418: 8b7b ldrh r3, [r7, #26] + 800b41a: 4618 mov r0, r3 + 800b41c: f000 f82f bl 800b47e + 800b420: 4603 mov r3, r0 + 800b422: 837b strh r3, [r7, #26] + for( i = 0; i < Size; i++ ) + 800b424: 69fb ldr r3, [r7, #28] + 800b426: 3301 adds r3, #1 + 800b428: 61fb str r3, [r7, #28] + 800b42a: 69fb ldr r3, [r7, #28] + 800b42c: 687a ldr r2, [r7, #4] + 800b42e: 429a cmp r2, r3 + 800b430: d8ed bhi.n 800b40e + } + /*Save state for next chunk*/ + RFWPacket->CrcLfsrState = crc; + 800b432: 68fb ldr r3, [r7, #12] + 800b434: 8b7a ldrh r2, [r7, #26] + 800b436: 829a strh r2, [r3, #20] + + if( RFWPacket->Init.CrcType == RADIO_FSK_CRC_2_BYTES_IBM ) + 800b438: 68fb ldr r3, [r7, #12] + 800b43a: 7a1b ldrb r3, [r3, #8] + 800b43c: 2bf1 cmp r3, #241 @ 0xf1 + 800b43e: d10b bne.n 800b458 + { + CrcResult[1] = crc & 0xFF; + 800b440: 683b ldr r3, [r7, #0] + 800b442: 3301 adds r3, #1 + 800b444: 8b7a ldrh r2, [r7, #26] + 800b446: b2d2 uxtb r2, r2 + 800b448: 701a strb r2, [r3, #0] + CrcResult[0] = crc >> 8; + 800b44a: 8b7b ldrh r3, [r7, #26] + 800b44c: 0a1b lsrs r3, r3, #8 + 800b44e: b29b uxth r3, r3 + 800b450: b2da uxtb r2, r3 + 800b452: 683b ldr r3, [r7, #0] + 800b454: 701a strb r2, [r3, #0] + 800b456: e00d b.n 800b474 + } + else + { + crc = ~crc ; + 800b458: 8b7b ldrh r3, [r7, #26] + 800b45a: 43db mvns r3, r3 + 800b45c: 837b strh r3, [r7, #26] + CrcResult[1] = crc & 0xFF; + 800b45e: 683b ldr r3, [r7, #0] + 800b460: 3301 adds r3, #1 + 800b462: 8b7a ldrh r2, [r7, #26] + 800b464: b2d2 uxtb r2, r2 + 800b466: 701a strb r2, [r3, #0] + CrcResult[0] = crc >> 8; + 800b468: 8b7b ldrh r3, [r7, #26] + 800b46a: 0a1b lsrs r3, r3, #8 + 800b46c: b29b uxth r3, r3 + 800b46e: b2da uxtb r2, r3 + 800b470: 683b ldr r3, [r7, #0] + 800b472: 701a strb r2, [r3, #0] + } + return status; + 800b474: 697b ldr r3, [r7, #20] +} + 800b476: 4618 mov r0, r3 + 800b478: 3720 adds r7, #32 + 800b47a: 46bd mov sp, r7 + 800b47c: bd80 pop {r7, pc} + +0800b47e : + +uint16_t RFW_CrcRun1Byte( uint16_t Crc, uint8_t DataByte, uint16_t Polynomial ) +{ + 800b47e: b480 push {r7} + 800b480: b085 sub sp, #20 + 800b482: af00 add r7, sp, #0 + 800b484: 4603 mov r3, r0 + 800b486: 80fb strh r3, [r7, #6] + 800b488: 460b mov r3, r1 + 800b48a: 717b strb r3, [r7, #5] + 800b48c: 4613 mov r3, r2 + 800b48e: 807b strh r3, [r7, #2] + uint8_t i; + for( i = 0; i < 8; i++ ) + 800b490: 2300 movs r3, #0 + 800b492: 73fb strb r3, [r7, #15] + 800b494: e018 b.n 800b4c8 + { + if( ( ( ( Crc & 0x8000 ) >> 8 ) ^ ( DataByte & 0x80 ) ) != 0 ) + 800b496: 88fb ldrh r3, [r7, #6] + 800b498: 121a asrs r2, r3, #8 + 800b49a: 797b ldrb r3, [r7, #5] + 800b49c: 4053 eors r3, r2 + 800b49e: f003 0380 and.w r3, r3, #128 @ 0x80 + 800b4a2: 2b00 cmp r3, #0 + 800b4a4: d007 beq.n 800b4b6 + { + Crc <<= 1; + 800b4a6: 88fb ldrh r3, [r7, #6] + 800b4a8: 005b lsls r3, r3, #1 + 800b4aa: 80fb strh r3, [r7, #6] + Crc ^= Polynomial; + 800b4ac: 88fa ldrh r2, [r7, #6] + 800b4ae: 887b ldrh r3, [r7, #2] + 800b4b0: 4053 eors r3, r2 + 800b4b2: 80fb strh r3, [r7, #6] + 800b4b4: e002 b.n 800b4bc + } + else + { + Crc <<= 1; + 800b4b6: 88fb ldrh r3, [r7, #6] + 800b4b8: 005b lsls r3, r3, #1 + 800b4ba: 80fb strh r3, [r7, #6] + } + DataByte <<= 1; + 800b4bc: 797b ldrb r3, [r7, #5] + 800b4be: 005b lsls r3, r3, #1 + 800b4c0: 717b strb r3, [r7, #5] + for( i = 0; i < 8; i++ ) + 800b4c2: 7bfb ldrb r3, [r7, #15] + 800b4c4: 3301 adds r3, #1 + 800b4c6: 73fb strb r3, [r7, #15] + 800b4c8: 7bfb ldrb r3, [r7, #15] + 800b4ca: 2b07 cmp r3, #7 + 800b4cc: d9e3 bls.n 800b496 + } + return Crc; + 800b4ce: 88fb ldrh r3, [r7, #6] +} + 800b4d0: 4618 mov r0, r3 + 800b4d2: 3714 adds r7, #20 + 800b4d4: 46bd mov sp, r7 + 800b4d6: bc80 pop {r7} + 800b4d8: 4770 bx lr + ... + +0800b4dc : + +static int32_t RFW_PollRxBytes( uint32_t bytes ) +{ + 800b4dc: b580 push {r7, lr} + 800b4de: b086 sub sp, #24 + 800b4e0: af00 add r7, sp, #0 + 800b4e2: 6078 str r0, [r7, #4] + uint32_t now = TimerGetCurrentTime( ); + 800b4e4: f001 fc70 bl 800cdc8 + 800b4e8: 6138 str r0, [r7, #16] + uint8_t reg_buff_ptr_ref = SUBGRF_ReadRegister( SUBGHZ_RXADRPTR ); + 800b4ea: f640 0003 movw r0, #2051 @ 0x803 + 800b4ee: f7fe ff35 bl 800a35c + 800b4f2: 4603 mov r3, r0 + 800b4f4: 73fb strb r3, [r7, #15] + uint8_t reg_buff_ptr = reg_buff_ptr_ref; + 800b4f6: 7bfb ldrb r3, [r7, #15] + 800b4f8: 75fb strb r3, [r7, #23] + uint32_t timeout = DIVC( bytes * 8 * 1000, RFWPacket.BitRate ); + 800b4fa: 687b ldr r3, [r7, #4] + 800b4fc: f44f 52fa mov.w r2, #8000 @ 0x1f40 + 800b500: fb03 f202 mul.w r2, r3, r2 + 800b504: 4b12 ldr r3, [pc, #72] @ (800b550 ) + 800b506: 6c9b ldr r3, [r3, #72] @ 0x48 + 800b508: 4413 add r3, r2 + 800b50a: 1e5a subs r2, r3, #1 + 800b50c: 4b10 ldr r3, [pc, #64] @ (800b550 ) + 800b50e: 6c9b ldr r3, [r3, #72] @ 0x48 + 800b510: fbb2 f3f3 udiv r3, r2, r3 + 800b514: 60bb str r3, [r7, #8] + /* Wait that packet length is received */ + while( ( reg_buff_ptr - reg_buff_ptr_ref ) < bytes ) + 800b516: e00f b.n 800b538 + { + /*reading rx address pointer*/ + reg_buff_ptr = SUBGRF_ReadRegister( SUBGHZ_RXADRPTR ); + 800b518: f640 0003 movw r0, #2051 @ 0x803 + 800b51c: f7fe ff1e bl 800a35c + 800b520: 4603 mov r3, r0 + 800b522: 75fb strb r3, [r7, #23] + if( TimerGetElapsedTime( now ) > timeout ) + 800b524: 6938 ldr r0, [r7, #16] + 800b526: f001 fc61 bl 800cdec + 800b52a: 4602 mov r2, r0 + 800b52c: 68bb ldr r3, [r7, #8] + 800b52e: 4293 cmp r3, r2 + 800b530: d202 bcs.n 800b538 + { + /*timeout*/ + return -1; + 800b532: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff + 800b536: e007 b.n 800b548 + while( ( reg_buff_ptr - reg_buff_ptr_ref ) < bytes ) + 800b538: 7dfa ldrb r2, [r7, #23] + 800b53a: 7bfb ldrb r3, [r7, #15] + 800b53c: 1ad3 subs r3, r2, r3 + 800b53e: 461a mov r2, r3 + 800b540: 687b ldr r3, [r7, #4] + 800b542: 4293 cmp r3, r2 + 800b544: d8e8 bhi.n 800b518 + } + } + return 0; + 800b546: 2300 movs r3, #0 +} + 800b548: 4618 mov r0, r3 + 800b54a: 3718 adds r7, #24 + 800b54c: 46bd mov sp, r7 + 800b54e: bd80 pop {r7, pc} + 800b550: 2000032c .word 0x2000032c + +0800b554 : + +static int32_t RFW_GetPacketLength( uint16_t *PayloadLength ) +{ + 800b554: b580 push {r7, lr} + 800b556: b086 sub sp, #24 + 800b558: af02 add r7, sp, #8 + 800b55a: 6078 str r0, [r7, #4] + if( 0UL != RFW_PollRxBytes( RFWPacket.Init.PayloadLengthFieldSize ) ) + 800b55c: 4b25 ldr r3, [pc, #148] @ (800b5f4 ) + 800b55e: 785b ldrb r3, [r3, #1] + 800b560: 4618 mov r0, r3 + 800b562: f7ff ffbb bl 800b4dc + 800b566: 4603 mov r3, r0 + 800b568: 2b00 cmp r3, #0 + 800b56a: d002 beq.n 800b572 + { + return -1; + 800b56c: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff + 800b570: e03b b.n 800b5ea + } + /* Get buffer from Radio*/ + SUBGRF_ReadBuffer( 0, ChunkBuffer, RFWPacket.Init.PayloadLengthFieldSize ); + 800b572: 4b20 ldr r3, [pc, #128] @ (800b5f4 ) + 800b574: 785b ldrb r3, [r3, #1] + 800b576: 461a mov r2, r3 + 800b578: 491f ldr r1, [pc, #124] @ (800b5f8 ) + 800b57a: 2000 movs r0, #0 + 800b57c: f7fe ff74 bl 800a468 + /* De-whiten packet length*/ + RFW_WhiteRun( &RFWPacket, ChunkBuffer, RFWPacket.Init.PayloadLengthFieldSize ); + 800b580: 4b1c ldr r3, [pc, #112] @ (800b5f4 ) + 800b582: 785b ldrb r3, [r3, #1] + 800b584: 461a mov r2, r3 + 800b586: 491c ldr r1, [pc, #112] @ (800b5f8 ) + 800b588: 481a ldr r0, [pc, #104] @ (800b5f4 ) + 800b58a: f7ff fee4 bl 800b356 + /*do crc 1st calculation packetLengthField and store intermediate result */ + if( RFWPacket.Init.CrcEnable == 1 ) + 800b58e: 4b19 ldr r3, [pc, #100] @ (800b5f4 ) + 800b590: 789b ldrb r3, [r3, #2] + 800b592: 2b01 cmp r3, #1 + 800b594: d108 bne.n 800b5a8 + { + /*run Crc algo on payloadLengthField*/ + uint8_t crc_dummy[2]; + RFW_CrcRun( &RFWPacket, ChunkBuffer, RFWPacket.Init.PayloadLengthFieldSize, crc_dummy ); + 800b596: 4b17 ldr r3, [pc, #92] @ (800b5f4 ) + 800b598: 785b ldrb r3, [r3, #1] + 800b59a: 461a mov r2, r3 + 800b59c: f107 030c add.w r3, r7, #12 + 800b5a0: 4915 ldr r1, [pc, #84] @ (800b5f8 ) + 800b5a2: 4814 ldr r0, [pc, #80] @ (800b5f4 ) + 800b5a4: f7ff ff1f bl 800b3e6 + } + if( RFWPacket.Init.PayloadLengthFieldSize == 1 ) + 800b5a8: 4b12 ldr r3, [pc, #72] @ (800b5f4 ) + 800b5aa: 785b ldrb r3, [r3, #1] + 800b5ac: 2b01 cmp r3, #1 + 800b5ae: d105 bne.n 800b5bc + { + *PayloadLength = ( uint16_t ) ChunkBuffer[0]; + 800b5b0: 4b11 ldr r3, [pc, #68] @ (800b5f8 ) + 800b5b2: 781b ldrb r3, [r3, #0] + 800b5b4: 461a mov r2, r3 + 800b5b6: 687b ldr r3, [r7, #4] + 800b5b8: 801a strh r2, [r3, #0] + 800b5ba: e00c b.n 800b5d6 + } + else + { + /*packet length is 2 bytes*/ + *PayloadLength = ( ( ( uint16_t ) ChunkBuffer[0] ) << 8 ) | ChunkBuffer[1]; + 800b5bc: 4b0e ldr r3, [pc, #56] @ (800b5f8 ) + 800b5be: 781b ldrb r3, [r3, #0] + 800b5c0: b21b sxth r3, r3 + 800b5c2: 021b lsls r3, r3, #8 + 800b5c4: b21a sxth r2, r3 + 800b5c6: 4b0c ldr r3, [pc, #48] @ (800b5f8 ) + 800b5c8: 785b ldrb r3, [r3, #1] + 800b5ca: b21b sxth r3, r3 + 800b5cc: 4313 orrs r3, r2 + 800b5ce: b21b sxth r3, r3 + 800b5d0: b29a uxth r2, r3 + 800b5d2: 687b ldr r3, [r7, #4] + 800b5d4: 801a strh r2, [r3, #0] + } + RFW_MW_LOG( TS_ON, VLEVEL_M, "PayloadLength=%d,\r\n", *PayloadLength ); + 800b5d6: 687b ldr r3, [r7, #4] + 800b5d8: 881b ldrh r3, [r3, #0] + 800b5da: 9300 str r3, [sp, #0] + 800b5dc: 4b07 ldr r3, [pc, #28] @ (800b5fc ) + 800b5de: 2201 movs r2, #1 + 800b5e0: 2100 movs r1, #0 + 800b5e2: 2002 movs r0, #2 + 800b5e4: f001 fcce bl 800cf84 + return 0; + 800b5e8: 2300 movs r3, #0 +} + 800b5ea: 4618 mov r0, r3 + 800b5ec: 3710 adds r7, #16 + 800b5ee: 46bd mov sp, r7 + 800b5f0: bd80 pop {r7, pc} + 800b5f2: bf00 nop + 800b5f4: 2000032c .word 0x2000032c + 800b5f8: 20000380 .word 0x20000380 + 800b5fc: 0800d670 .word 0x0800d670 + +0800b600 : + +static void RFW_GetPayloadTimerEvent( void *context ) +{ + 800b600: b580 push {r7, lr} + 800b602: b082 sub sp, #8 + 800b604: af00 add r7, sp, #0 + 800b606: 6078 str r0, [r7, #4] + RFW_GET_PAYLOAD_PROCESS(); + 800b608: f000 f804 bl 800b614 +} + 800b60c: bf00 nop + 800b60e: 3708 adds r7, #8 + 800b610: 46bd mov sp, r7 + 800b612: bd80 pop {r7, pc} + +0800b614 : + +static void RFW_GetPayloadProcess( void ) +{ + 800b614: b580 push {r7, lr} + 800b616: b086 sub sp, #24 + 800b618: af04 add r7, sp, #16 + /*long packet mode*/ + uint8_t read_ptr = SUBGRF_ReadRegister( SUBGHZ_RXADRPTR ); + 800b61a: f640 0003 movw r0, #2051 @ 0x803 + 800b61e: f7fe fe9d bl 800a35c + 800b622: 4603 mov r3, r0 + 800b624: 70fb strb r3, [r7, #3] + uint8_t size = read_ptr - RFWPacket.RadioBufferOffset; + 800b626: 4b83 ldr r3, [pc, #524] @ (800b834 ) + 800b628: f893 3036 ldrb.w r3, [r3, #54] @ 0x36 + 800b62c: 78fa ldrb r2, [r7, #3] + 800b62e: 1ad3 subs r3, r2, r3 + 800b630: 70bb strb r3, [r7, #2] + uint32_t Timeout; + /*check remaining size*/ + if( RFWPacket.LongPacketRemainingBytes > size ) + 800b632: 4b80 ldr r3, [pc, #512] @ (800b834 ) + 800b634: 8e9a ldrh r2, [r3, #52] @ 0x34 + 800b636: 78bb ldrb r3, [r7, #2] + 800b638: b29b uxth r3, r3 + 800b63a: 429a cmp r2, r3 + 800b63c: f240 80cd bls.w 800b7da + { + /* update LongPacketRemainingBytes*/ + RFWPacket.LongPacketRemainingBytes -= size; + 800b640: 4b7c ldr r3, [pc, #496] @ (800b834 ) + 800b642: 8e9a ldrh r2, [r3, #52] @ 0x34 + 800b644: 78bb ldrb r3, [r7, #2] + 800b646: b29b uxth r3, r3 + 800b648: 1ad3 subs r3, r2, r3 + 800b64a: b29a uxth r2, r3 + 800b64c: 4b79 ldr r3, [pc, #484] @ (800b834 ) + 800b64e: 869a strh r2, [r3, #52] @ 0x34 + /*intermediate chunk*/ + RFW_MW_LOG( TS_ON, VLEVEL_M, "RxTxPldLen=0x%02X,\r\n", SUBGRF_ReadRegister( SUBGHZ_GRTXPLDLEN ) ); + 800b650: f240 60bb movw r0, #1723 @ 0x6bb + 800b654: f7fe fe82 bl 800a35c + 800b658: 4603 mov r3, r0 + 800b65a: 9300 str r3, [sp, #0] + 800b65c: 4b76 ldr r3, [pc, #472] @ (800b838 ) + 800b65e: 2201 movs r2, #1 + 800b660: 2100 movs r1, #0 + 800b662: 2002 movs r0, #2 + 800b664: f001 fc8e bl 800cf84 + RFW_MW_LOG( TS_ON, VLEVEL_M, "RxAddrPtr=0x%02X,\r\n", read_ptr ); + 800b668: 78fb ldrb r3, [r7, #3] + 800b66a: 9300 str r3, [sp, #0] + 800b66c: 4b73 ldr r3, [pc, #460] @ (800b83c ) + 800b66e: 2201 movs r2, #1 + 800b670: 2100 movs r1, #0 + 800b672: 2002 movs r0, #2 + 800b674: f001 fc86 bl 800cf84 + RFW_MW_LOG( TS_ON, VLEVEL_M, "offset= %d, size=%d, remaining=%d,\r\n", RFWPacket.RadioBufferOffset, size, + 800b678: 4b6e ldr r3, [pc, #440] @ (800b834 ) + 800b67a: f893 3036 ldrb.w r3, [r3, #54] @ 0x36 + 800b67e: 4619 mov r1, r3 + 800b680: 78bb ldrb r3, [r7, #2] + 800b682: 4a6c ldr r2, [pc, #432] @ (800b834 ) + 800b684: 8e92 ldrh r2, [r2, #52] @ 0x34 + 800b686: 9202 str r2, [sp, #8] + 800b688: 9301 str r3, [sp, #4] + 800b68a: 9100 str r1, [sp, #0] + 800b68c: 4b6c ldr r3, [pc, #432] @ (800b840 ) + 800b68e: 2201 movs r2, #1 + 800b690: 2100 movs r1, #0 + 800b692: 2002 movs r0, #2 + 800b694: f001 fc76 bl 800cf84 + RFWPacket.LongPacketRemainingBytes ); + /*update pld length so that not reached*/ + SUBGRF_WriteRegister( SUBGHZ_GRTXPLDLEN, read_ptr - 1 ); + 800b698: 78fb ldrb r3, [r7, #3] + 800b69a: 3b01 subs r3, #1 + 800b69c: b2db uxtb r3, r3 + 800b69e: 4619 mov r1, r3 + 800b6a0: f240 60bb movw r0, #1723 @ 0x6bb + 800b6a4: f7fe fe38 bl 800a318 + /* read data from radio*/ + SUBGRF_ReadBuffer( RFWPacket.RadioBufferOffset, ChunkBuffer, size ); + 800b6a8: 4b62 ldr r3, [pc, #392] @ (800b834 ) + 800b6aa: f893 3036 ldrb.w r3, [r3, #54] @ 0x36 + 800b6ae: 78ba ldrb r2, [r7, #2] + 800b6b0: 4964 ldr r1, [pc, #400] @ (800b844 ) + 800b6b2: 4618 mov r0, r3 + 800b6b4: f7fe fed8 bl 800a468 + /* update buffer Offset, with intentional wrap around*/ + RFWPacket.RadioBufferOffset += size; + 800b6b8: 4b5e ldr r3, [pc, #376] @ (800b834 ) + 800b6ba: f893 2036 ldrb.w r2, [r3, #54] @ 0x36 + 800b6be: 78bb ldrb r3, [r7, #2] + 800b6c0: 4413 add r3, r2 + 800b6c2: b2da uxtb r2, r3 + 800b6c4: 4b5b ldr r3, [pc, #364] @ (800b834 ) + 800b6c6: f883 2036 strb.w r2, [r3, #54] @ 0x36 + /*Run the de-whitening on current chunk*/ + RFW_WhiteRun( &RFWPacket, ChunkBuffer, size ); + 800b6ca: 78bb ldrb r3, [r7, #2] + 800b6cc: 461a mov r2, r3 + 800b6ce: 495d ldr r1, [pc, #372] @ (800b844 ) + 800b6d0: 4858 ldr r0, [pc, #352] @ (800b834 ) + 800b6d2: f7ff fe40 bl 800b356 + if( RFWPacket.Init.CrcEnable == 1 ) + 800b6d6: 4b57 ldr r3, [pc, #348] @ (800b834 ) + 800b6d8: 789b ldrb r3, [r3, #2] + 800b6da: 2b01 cmp r3, #1 + 800b6dc: d105 bne.n 800b6ea + { + /*run Crc algo on partial chunk*/ + uint8_t crc_dummy[2]; + RFW_CrcRun( &RFWPacket, ChunkBuffer, size, crc_dummy ); + 800b6de: 78ba ldrb r2, [r7, #2] + 800b6e0: 463b mov r3, r7 + 800b6e2: 4958 ldr r1, [pc, #352] @ (800b844 ) + 800b6e4: 4853 ldr r0, [pc, #332] @ (800b834 ) + 800b6e6: f7ff fe7e bl 800b3e6 + } + + if( RFWPacket.LongPacketModeEnable == 1 ) + 800b6ea: 4b52 ldr r3, [pc, #328] @ (800b834 ) + 800b6ec: 7e9b ldrb r3, [r3, #26] + 800b6ee: 2b01 cmp r3, #1 + 800b6f0: d106 bne.n 800b700 + { + /*report rx data chunk to application*/ + RFWPacket.RxLongPacketStoreChunkCb( ChunkBuffer, size ); + 800b6f2: 4b50 ldr r3, [pc, #320] @ (800b834 ) + 800b6f4: 6bdb ldr r3, [r3, #60] @ 0x3c + 800b6f6: 78ba ldrb r2, [r7, #2] + 800b6f8: 4611 mov r1, r2 + 800b6fa: 4852 ldr r0, [pc, #328] @ (800b844 ) + 800b6fc: 4798 blx r3 + 800b6fe: e02b b.n 800b758 + } + else + { + if( RFWPacket.RxPayloadOffset += size < RADIO_BUF_SIZE ) + 800b700: 4b4c ldr r3, [pc, #304] @ (800b834 ) + 800b702: 8f1b ldrh r3, [r3, #56] @ 0x38 + 800b704: 78ba ldrb r2, [r7, #2] + 800b706: 2aff cmp r2, #255 @ 0xff + 800b708: bf14 ite ne + 800b70a: 2201 movne r2, #1 + 800b70c: 2200 moveq r2, #0 + 800b70e: b2d2 uxtb r2, r2 + 800b710: 4413 add r3, r2 + 800b712: b29a uxth r2, r3 + 800b714: 4b47 ldr r3, [pc, #284] @ (800b834 ) + 800b716: 871a strh r2, [r3, #56] @ 0x38 + 800b718: 4b46 ldr r3, [pc, #280] @ (800b834 ) + 800b71a: 8f1b ldrh r3, [r3, #56] @ 0x38 + 800b71c: 2b00 cmp r3, #0 + 800b71e: d013 beq.n 800b748 + { + RADIO_MEMCPY8( &RxBuffer[RFWPacket.RxPayloadOffset], ChunkBuffer, size ); + 800b720: 4b44 ldr r3, [pc, #272] @ (800b834 ) + 800b722: 8f1b ldrh r3, [r3, #56] @ 0x38 + 800b724: 461a mov r2, r3 + 800b726: 4b48 ldr r3, [pc, #288] @ (800b848 ) + 800b728: 4413 add r3, r2 + 800b72a: 78ba ldrb r2, [r7, #2] + 800b72c: b292 uxth r2, r2 + 800b72e: 4945 ldr r1, [pc, #276] @ (800b844 ) + 800b730: 4618 mov r0, r3 + 800b732: f000 fcdb bl 800c0ec + RFWPacket.RxPayloadOffset += size; + 800b736: 4b3f ldr r3, [pc, #252] @ (800b834 ) + 800b738: 8f1a ldrh r2, [r3, #56] @ 0x38 + 800b73a: 78bb ldrb r3, [r7, #2] + 800b73c: b29b uxth r3, r3 + 800b73e: 4413 add r3, r2 + 800b740: b29a uxth r2, r3 + 800b742: 4b3c ldr r3, [pc, #240] @ (800b834 ) + 800b744: 871a strh r2, [r3, #56] @ 0x38 + 800b746: e007 b.n 800b758 + } + else + { + /*stop the radio*/ + SUBGRF_SetStandby( STDBY_RC ); + 800b748: 2000 movs r0, #0 + 800b74a: f7fe f861 bl 8009810 + /*report CRC error*/ + RFWPacket.Init.RadioEvents->RxError( ); + 800b74e: 4b39 ldr r3, [pc, #228] @ (800b834 ) + 800b750: 691b ldr r3, [r3, #16] + 800b752: 691b ldr r3, [r3, #16] + 800b754: 4798 blx r3 + return; + 800b756: e069 b.n 800b82c + } + } + /*calculate next timer timeout*/ + if( RFWPacket.LongPacketRemainingBytes < LONGPACKET_CHUNK_LENGTH_BYTES ) + 800b758: 4b36 ldr r3, [pc, #216] @ (800b834 ) + 800b75a: 8e9b ldrh r3, [r3, #52] @ 0x34 + 800b75c: 2b7f cmp r3, #127 @ 0x7f + 800b75e: d812 bhi.n 800b786 + { + /*for the next and last chunk DIVC +1 to make sure crc is received.*/ + Timeout = DIVC( ( RFWPacket.LongPacketRemainingBytes ) * 8 * 1000, RFWPacket.BitRate ) + 2; + 800b760: 4b34 ldr r3, [pc, #208] @ (800b834 ) + 800b762: 8e9b ldrh r3, [r3, #52] @ 0x34 + 800b764: 461a mov r2, r3 + 800b766: f44f 53fa mov.w r3, #8000 @ 0x1f40 + 800b76a: fb02 f303 mul.w r3, r2, r3 + 800b76e: 461a mov r2, r3 + 800b770: 4b30 ldr r3, [pc, #192] @ (800b834 ) + 800b772: 6c9b ldr r3, [r3, #72] @ 0x48 + 800b774: 4413 add r3, r2 + 800b776: 1e5a subs r2, r3, #1 + 800b778: 4b2e ldr r3, [pc, #184] @ (800b834 ) + 800b77a: 6c9b ldr r3, [r3, #72] @ 0x48 + 800b77c: fbb2 f3f3 udiv r3, r2, r3 + 800b780: 3302 adds r3, #2 + 800b782: 607b str r3, [r7, #4] + 800b784: e021 b.n 800b7ca + } + else if( RFWPacket.LongPacketRemainingBytes < ( 3 * LONGPACKET_CHUNK_LENGTH_BYTES ) / 2 ) + 800b786: 4b2b ldr r3, [pc, #172] @ (800b834 ) + 800b788: 8e9b ldrh r3, [r3, #52] @ 0x34 + 800b78a: 2bbf cmp r3, #191 @ 0xbf + 800b78c: d813 bhi.n 800b7b6 + { + /*this is to make sure that last chunk will always be greater than LONGPACKET_CHUNK_LENGTH_BYTES/2 */ + Timeout = DIVR( ( RFWPacket.LongPacketRemainingBytes / 2 ) * 8 * 1000, RFWPacket.BitRate ); + 800b78e: 4b29 ldr r3, [pc, #164] @ (800b834 ) + 800b790: 8e9b ldrh r3, [r3, #52] @ 0x34 + 800b792: 085b lsrs r3, r3, #1 + 800b794: b29b uxth r3, r3 + 800b796: 461a mov r2, r3 + 800b798: f44f 53fa mov.w r3, #8000 @ 0x1f40 + 800b79c: fb02 f303 mul.w r3, r2, r3 + 800b7a0: 461a mov r2, r3 + 800b7a2: 4b24 ldr r3, [pc, #144] @ (800b834 ) + 800b7a4: 6c9b ldr r3, [r3, #72] @ 0x48 + 800b7a6: 085b lsrs r3, r3, #1 + 800b7a8: 441a add r2, r3 + 800b7aa: 4b22 ldr r3, [pc, #136] @ (800b834 ) + 800b7ac: 6c9b ldr r3, [r3, #72] @ 0x48 + 800b7ae: fbb2 f3f3 udiv r3, r2, r3 + 800b7b2: 607b str r3, [r7, #4] + 800b7b4: e009 b.n 800b7ca + } + else + { + /*size value is close to LONGPACKET_CHUNK_LENGTH_BYTES with +/- errors compensated in closed loop here*/ + Timeout = DIVR( ( LONGPACKET_CHUNK_LENGTH_BYTES ) * 8 * 1000, RFWPacket.BitRate ); + 800b7b6: 4b1f ldr r3, [pc, #124] @ (800b834 ) + 800b7b8: 6c9b ldr r3, [r3, #72] @ 0x48 + 800b7ba: 085b lsrs r3, r3, #1 + 800b7bc: f503 227a add.w r2, r3, #1024000 @ 0xfa000 + 800b7c0: 4b1c ldr r3, [pc, #112] @ (800b834 ) + 800b7c2: 6c9b ldr r3, [r3, #72] @ 0x48 + 800b7c4: fbb2 f3f3 udiv r3, r2, r3 + 800b7c8: 607b str r3, [r7, #4] + } + TimerSetValue( &RFWPacket.Timer, Timeout ); + 800b7ca: 6879 ldr r1, [r7, #4] + 800b7cc: 481f ldr r0, [pc, #124] @ (800b84c ) + 800b7ce: f001 fa51 bl 800cc74 + TimerStart( &RFWPacket.Timer ); + 800b7d2: 481e ldr r0, [pc, #120] @ (800b84c ) + 800b7d4: f001 f970 bl 800cab8 + 800b7d8: e028 b.n 800b82c + } + else + { + if( RFWPacket.LongPacketRemainingBytes < RFWPacket.Init.CrcFieldSize ) + 800b7da: 4b16 ldr r3, [pc, #88] @ (800b834 ) + 800b7dc: 8e9b ldrh r3, [r3, #52] @ 0x34 + 800b7de: 4a15 ldr r2, [pc, #84] @ (800b834 ) + 800b7e0: 78d2 ldrb r2, [r2, #3] + 800b7e2: 4293 cmp r3, r2 + 800b7e4: d204 bcs.n 800b7f0 + { + /* force LongPacketRemainingBytes to CrcFieldSize: this should never happen*/ + RFWPacket.LongPacketRemainingBytes = RFWPacket.Init.CrcFieldSize; + 800b7e6: 4b13 ldr r3, [pc, #76] @ (800b834 ) + 800b7e8: 78db ldrb r3, [r3, #3] + 800b7ea: 461a mov r2, r3 + 800b7ec: 4b11 ldr r3, [pc, #68] @ (800b834 ) + 800b7ee: 869a strh r2, [r3, #52] @ 0x34 + } + /*last chunk*/ + RFW_MW_LOG( TS_ON, VLEVEL_M, "LastChunk. offset= %d, size=%d, remaining=%d,\r\n", RFWPacket.RadioBufferOffset, size, + 800b7f0: 4b10 ldr r3, [pc, #64] @ (800b834 ) + 800b7f2: f893 3036 ldrb.w r3, [r3, #54] @ 0x36 + 800b7f6: 4619 mov r1, r3 + 800b7f8: 78bb ldrb r3, [r7, #2] + 800b7fa: 4a0e ldr r2, [pc, #56] @ (800b834 ) + 800b7fc: 8e92 ldrh r2, [r2, #52] @ 0x34 + 800b7fe: 9202 str r2, [sp, #8] + 800b800: 9301 str r3, [sp, #4] + 800b802: 9100 str r1, [sp, #0] + 800b804: 4b12 ldr r3, [pc, #72] @ (800b850 ) + 800b806: 2201 movs r2, #1 + 800b808: 2100 movs r1, #0 + 800b80a: 2002 movs r0, #2 + 800b80c: f001 fbba bl 800cf84 + RFWPacket.LongPacketRemainingBytes ); + size = RFWPacket.LongPacketRemainingBytes; + 800b810: 4b08 ldr r3, [pc, #32] @ (800b834 ) + 800b812: 8e9b ldrh r3, [r3, #52] @ 0x34 + 800b814: 70bb strb r3, [r7, #2] + /* update LongPacketRemainingBytes*/ + RFWPacket.LongPacketRemainingBytes = 0; + 800b816: 4b07 ldr r3, [pc, #28] @ (800b834 ) + 800b818: 2200 movs r2, #0 + 800b81a: 869a strh r2, [r3, #52] @ 0x34 + /*Process last chunk*/ + RFW_GetPayload( RFWPacket.RadioBufferOffset, size ); + 800b81c: 4b05 ldr r3, [pc, #20] @ (800b834 ) + 800b81e: f893 3036 ldrb.w r3, [r3, #54] @ 0x36 + 800b822: 78ba ldrb r2, [r7, #2] + 800b824: 4611 mov r1, r2 + 800b826: 4618 mov r0, r3 + 800b828: f000 f814 bl 800b854 + } +} + 800b82c: 3708 adds r7, #8 + 800b82e: 46bd mov sp, r7 + 800b830: bd80 pop {r7, pc} + 800b832: bf00 nop + 800b834: 2000032c .word 0x2000032c + 800b838: 0800d684 .word 0x0800d684 + 800b83c: 0800d69c .word 0x0800d69c + 800b840: 0800d6b0 .word 0x0800d6b0 + 800b844: 20000380 .word 0x20000380 + 800b848: 20000480 .word 0x20000480 + 800b84c: 20000348 .word 0x20000348 + 800b850: 0800d6d8 .word 0x0800d6d8 + +0800b854 : + +static void RFW_GetPayload( uint8_t Offset, uint8_t Length ) +{ + 800b854: b5b0 push {r4, r5, r7, lr} + 800b856: b088 sub sp, #32 + 800b858: af04 add r7, sp, #16 + 800b85a: 4603 mov r3, r0 + 800b85c: 460a mov r2, r1 + 800b85e: 71fb strb r3, [r7, #7] + 800b860: 4613 mov r3, r2 + 800b862: 71bb strb r3, [r7, #6] + uint8_t crc_result[2]; + /*stop the radio*/ + SUBGRF_SetStandby( STDBY_RC ); + 800b864: 2000 movs r0, #0 + 800b866: f7fd ffd3 bl 8009810 + /*read data buffer*/ + SUBGRF_ReadBuffer( Offset, ChunkBuffer, Length ); + 800b86a: 79ba ldrb r2, [r7, #6] + 800b86c: 79fb ldrb r3, [r7, #7] + 800b86e: 495a ldr r1, [pc, #360] @ (800b9d8 ) + 800b870: 4618 mov r0, r3 + 800b872: f7fe fdf9 bl 800a468 + /*Run the de-whitening on all packet*/ + RFW_WhiteRun( &RFWPacket, ChunkBuffer, Length ); + 800b876: 79bb ldrb r3, [r7, #6] + 800b878: 461a mov r2, r3 + 800b87a: 4957 ldr r1, [pc, #348] @ (800b9d8 ) + 800b87c: 4857 ldr r0, [pc, #348] @ (800b9dc ) + 800b87e: f7ff fd6a bl 800b356 + if( RFWPacket.Init.CrcEnable == 1 ) + 800b882: 4b56 ldr r3, [pc, #344] @ (800b9dc ) + 800b884: 789b ldrb r3, [r3, #2] + 800b886: 2b01 cmp r3, #1 + 800b888: d10a bne.n 800b8a0 + { + RFW_CrcRun( &RFWPacket, ChunkBuffer, Length - RFWPacket.Init.CrcFieldSize, crc_result ); + 800b88a: 79bb ldrb r3, [r7, #6] + 800b88c: 4a53 ldr r2, [pc, #332] @ (800b9dc ) + 800b88e: 78d2 ldrb r2, [r2, #3] + 800b890: 1a9b subs r3, r3, r2 + 800b892: 461a mov r2, r3 + 800b894: f107 030c add.w r3, r7, #12 + 800b898: 494f ldr r1, [pc, #316] @ (800b9d8 ) + 800b89a: 4850 ldr r0, [pc, #320] @ (800b9dc ) + 800b89c: f7ff fda3 bl 800b3e6 + } + if( RFWPacket.LongPacketModeEnable == 1 ) + 800b8a0: 4b4e ldr r3, [pc, #312] @ (800b9dc ) + 800b8a2: 7e9b ldrb r3, [r3, #26] + 800b8a4: 2b01 cmp r3, #1 + 800b8a6: d10a bne.n 800b8be + { + /*report rx data chunk to application*/ + + RFWPacket.RxLongPacketStoreChunkCb( ChunkBuffer, Length - RFWPacket.Init.CrcFieldSize ); + 800b8a8: 4b4c ldr r3, [pc, #304] @ (800b9dc ) + 800b8aa: 6bdb ldr r3, [r3, #60] @ 0x3c + 800b8ac: 4a4b ldr r2, [pc, #300] @ (800b9dc ) + 800b8ae: 78d2 ldrb r2, [r2, #3] + 800b8b0: 79b9 ldrb r1, [r7, #6] + 800b8b2: 1a8a subs r2, r1, r2 + 800b8b4: b2d2 uxtb r2, r2 + 800b8b6: 4611 mov r1, r2 + 800b8b8: 4847 ldr r0, [pc, #284] @ (800b9d8 ) + 800b8ba: 4798 blx r3 + 800b8bc: e02a b.n 800b914 + } + else + { + if( RFWPacket.RxPayloadOffset + Length - RFWPacket.Init.CrcFieldSize < RADIO_BUF_SIZE ) + 800b8be: 4b47 ldr r3, [pc, #284] @ (800b9dc ) + 800b8c0: 8f1b ldrh r3, [r3, #56] @ 0x38 + 800b8c2: 461a mov r2, r3 + 800b8c4: 79bb ldrb r3, [r7, #6] + 800b8c6: 4413 add r3, r2 + 800b8c8: 4a44 ldr r2, [pc, #272] @ (800b9dc ) + 800b8ca: 78d2 ldrb r2, [r2, #3] + 800b8cc: 1a9b subs r3, r3, r2 + 800b8ce: 2bfe cmp r3, #254 @ 0xfe + 800b8d0: dc1b bgt.n 800b90a + { + RADIO_MEMCPY8( &RxBuffer[RFWPacket.RxPayloadOffset], ChunkBuffer, Length - RFWPacket.Init.CrcFieldSize ); + 800b8d2: 4b42 ldr r3, [pc, #264] @ (800b9dc ) + 800b8d4: 8f1b ldrh r3, [r3, #56] @ 0x38 + 800b8d6: 461a mov r2, r3 + 800b8d8: 4b41 ldr r3, [pc, #260] @ (800b9e0 ) + 800b8da: 18d0 adds r0, r2, r3 + 800b8dc: 79bb ldrb r3, [r7, #6] + 800b8de: b29b uxth r3, r3 + 800b8e0: 4a3e ldr r2, [pc, #248] @ (800b9dc ) + 800b8e2: 78d2 ldrb r2, [r2, #3] + 800b8e4: 1a9b subs r3, r3, r2 + 800b8e6: b29b uxth r3, r3 + 800b8e8: 461a mov r2, r3 + 800b8ea: 493b ldr r1, [pc, #236] @ (800b9d8 ) + 800b8ec: f000 fbfe bl 800c0ec + RFWPacket.RxPayloadOffset += Length - RFWPacket.Init.CrcFieldSize; + 800b8f0: 4b3a ldr r3, [pc, #232] @ (800b9dc ) + 800b8f2: 8f1a ldrh r2, [r3, #56] @ 0x38 + 800b8f4: 79bb ldrb r3, [r7, #6] + 800b8f6: b29b uxth r3, r3 + 800b8f8: 4938 ldr r1, [pc, #224] @ (800b9dc ) + 800b8fa: 78c9 ldrb r1, [r1, #3] + 800b8fc: 1a5b subs r3, r3, r1 + 800b8fe: b29b uxth r3, r3 + 800b900: 4413 add r3, r2 + 800b902: b29a uxth r2, r3 + 800b904: 4b35 ldr r3, [pc, #212] @ (800b9dc ) + 800b906: 871a strh r2, [r3, #56] @ 0x38 + 800b908: e004 b.n 800b914 + } + else + { + /*report CRC error*/ + RFWPacket.Init.RadioEvents->RxError( ); + 800b90a: 4b34 ldr r3, [pc, #208] @ (800b9dc ) + 800b90c: 691b ldr r3, [r3, #16] + 800b90e: 691b ldr r3, [r3, #16] + 800b910: 4798 blx r3 + 800b912: e05d b.n 800b9d0 + return; + } + } + TimerStop( RFWPacket.RxTimeoutTimer ); + 800b914: 4b31 ldr r3, [pc, #196] @ (800b9dc ) + 800b916: 6cdb ldr r3, [r3, #76] @ 0x4c + 800b918: 4618 mov r0, r3 + 800b91a: f001 f93b bl 800cb94 + /* CRC check*/ + RFW_MW_LOG( TS_ON, VLEVEL_M, "crc_result= 0x%02X%02X, crc_payload=0x%02X%02X\r\n", crc_result[0], crc_result[1], + 800b91e: 7b3b ldrb r3, [r7, #12] + 800b920: 4619 mov r1, r3 + 800b922: 7b7b ldrb r3, [r7, #13] + 800b924: 4618 mov r0, r3 + 800b926: 79bb ldrb r3, [r7, #6] + 800b928: 3b02 subs r3, #2 + 800b92a: 4a2b ldr r2, [pc, #172] @ (800b9d8 ) + 800b92c: 5cd3 ldrb r3, [r2, r3] + 800b92e: 461c mov r4, r3 + 800b930: 79bb ldrb r3, [r7, #6] + 800b932: 3b01 subs r3, #1 + 800b934: 4a28 ldr r2, [pc, #160] @ (800b9d8 ) + 800b936: 5cd3 ldrb r3, [r2, r3] + 800b938: 9303 str r3, [sp, #12] + 800b93a: 9402 str r4, [sp, #8] + 800b93c: 9001 str r0, [sp, #4] + 800b93e: 9100 str r1, [sp, #0] + 800b940: 4b28 ldr r3, [pc, #160] @ (800b9e4 ) + 800b942: 2201 movs r2, #1 + 800b944: 2100 movs r1, #0 + 800b946: 2002 movs r0, #2 + 800b948: f001 fb1c bl 800cf84 + ChunkBuffer[Length - 2], ChunkBuffer[Length - 1] ); + if( ( ( crc_result[0] == ChunkBuffer[Length - 2] ) && + 800b94c: 7b3a ldrb r2, [r7, #12] + 800b94e: 79bb ldrb r3, [r7, #6] + 800b950: 3b02 subs r3, #2 + 800b952: 4921 ldr r1, [pc, #132] @ (800b9d8 ) + 800b954: 5ccb ldrb r3, [r1, r3] + 800b956: 429a cmp r2, r3 + 800b958: d106 bne.n 800b968 + ( crc_result[1] == ChunkBuffer[Length - 1] ) ) || + 800b95a: 7b7a ldrb r2, [r7, #13] + 800b95c: 79bb ldrb r3, [r7, #6] + 800b95e: 3b01 subs r3, #1 + 800b960: 491d ldr r1, [pc, #116] @ (800b9d8 ) + 800b962: 5ccb ldrb r3, [r1, r3] + if( ( ( crc_result[0] == ChunkBuffer[Length - 2] ) && + 800b964: 429a cmp r2, r3 + 800b966: d003 beq.n 800b970 + ( RFWPacket.Init.CrcEnable == 0 ) ) + 800b968: 4b1c ldr r3, [pc, #112] @ (800b9dc ) + 800b96a: 789b ldrb r3, [r3, #2] + ( crc_result[1] == ChunkBuffer[Length - 1] ) ) || + 800b96c: 2b00 cmp r3, #0 + 800b96e: d126 bne.n 800b9be + { + /*read Rssi sampled at Sync*/ + uint8_t rssi_sync = SUBGRF_ReadRegister( 0x06CA ); + 800b970: f240 60ca movw r0, #1738 @ 0x6ca + 800b974: f7fe fcf2 bl 800a35c + 800b978: 4603 mov r3, r0 + 800b97a: 73fb strb r3, [r7, #15] + /* Get Carrier Frequency Offset*/ + int32_t cfo; + SUBGRF_GetCFO( RFWPacket.BitRate, &cfo ); + 800b97c: 4b17 ldr r3, [pc, #92] @ (800b9dc ) + 800b97e: 6c9b ldr r3, [r3, #72] @ 0x48 + 800b980: f107 0208 add.w r2, r7, #8 + 800b984: 4611 mov r1, r2 + 800b986: 4618 mov r0, r3 + 800b988: f7fe ff22 bl 800a7d0 + /*ChunkBuffer[1] to remove packet Length*/ + RFWPacket.Init.RadioEvents->RxDone( RxBuffer, + 800b98c: 4b13 ldr r3, [pc, #76] @ (800b9dc ) + 800b98e: 691b ldr r3, [r3, #16] + 800b990: 689c ldr r4, [r3, #8] + 800b992: 4b12 ldr r3, [pc, #72] @ (800b9dc ) + 800b994: 8f19 ldrh r1, [r3, #56] @ 0x38 + 800b996: 7bfb ldrb r3, [r7, #15] + 800b998: 085b lsrs r3, r3, #1 + 800b99a: b2db uxtb r3, r3 + 800b99c: 425b negs r3, r3 + 800b99e: b29b uxth r3, r3 + 800b9a0: b218 sxth r0, r3 + RFWPacket.RxPayloadOffset, + -( rssi_sync >> 1 ), + ( int8_t ) DIVR( cfo, 1000 ) ); + 800b9a2: 68bb ldr r3, [r7, #8] + 800b9a4: f503 73fa add.w r3, r3, #500 @ 0x1f4 + 800b9a8: 4a0f ldr r2, [pc, #60] @ (800b9e8 ) + 800b9aa: fb82 5203 smull r5, r2, r2, r3 + 800b9ae: 1192 asrs r2, r2, #6 + 800b9b0: 17db asrs r3, r3, #31 + 800b9b2: 1ad3 subs r3, r2, r3 + RFWPacket.Init.RadioEvents->RxDone( RxBuffer, + 800b9b4: b25b sxtb r3, r3 + 800b9b6: 4602 mov r2, r0 + 800b9b8: 4809 ldr r0, [pc, #36] @ (800b9e0 ) + 800b9ba: 47a0 blx r4 + { + 800b9bc: e003 b.n 800b9c6 + } + else + { + /*report CRC error*/ + RFWPacket.Init.RadioEvents->RxError( ); + 800b9be: 4b07 ldr r3, [pc, #28] @ (800b9dc ) + 800b9c0: 691b ldr r3, [r3, #16] + 800b9c2: 691b ldr r3, [r3, #16] + 800b9c4: 4798 blx r3 + } + DBG_GPIO_RADIO_RX( RST ); + 800b9c6: f44f 5180 mov.w r1, #4096 @ 0x1000 + 800b9ca: 4808 ldr r0, [pc, #32] @ (800b9ec ) + 800b9cc: f7fe ff8d bl 800a8ea +} + 800b9d0: 3710 adds r7, #16 + 800b9d2: 46bd mov sp, r7 + 800b9d4: bdb0 pop {r4, r5, r7, pc} + 800b9d6: bf00 nop + 800b9d8: 20000380 .word 0x20000380 + 800b9dc: 2000032c .word 0x2000032c + 800b9e0: 20000480 .word 0x20000480 + 800b9e4: 0800d708 .word 0x0800d708 + 800b9e8: 10624dd3 .word 0x10624dd3 + 800b9ec: 48000400 .word 0x48000400 + +0800b9f0 : +/* USER CODE END PFP */ + +/* Exported functions --------------------------------------------------------*/ + +void MX_SubGHz_Phy_Init(void) +{ + 800b9f0: b580 push {r7, lr} + 800b9f2: af00 add r7, sp, #0 + /* USER CODE BEGIN MX_SubGHz_Phy_Init_1 */ + + /* USER CODE END MX_SubGHz_Phy_Init_1 */ + SystemApp_Init(); + 800b9f4: f7f5 f84a bl 8000a8c + /* USER CODE BEGIN MX_SubGHz_Phy_Init_1_1 */ + + /* USER CODE END MX_SubGHz_Phy_Init_1_1 */ + SubghzApp_Init(); + 800b9f8: f000 f80a bl 800ba10 + /* USER CODE BEGIN MX_SubGHz_Phy_Init_2 */ + + /* USER CODE END MX_SubGHz_Phy_Init_2 */ +} + 800b9fc: bf00 nop + 800b9fe: bd80 pop {r7, pc} + +0800ba00 : + +void MX_SubGHz_Phy_Process(void) +{ + 800ba00: b580 push {r7, lr} + 800ba02: af00 add r7, sp, #0 + /* USER CODE BEGIN MX_SubGHz_Phy_Process_1 */ + + /* USER CODE END MX_SubGHz_Phy_Process_1 */ + UTIL_SEQ_Run(UTIL_SEQ_DEFAULT); + 800ba04: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff + 800ba08: f000 fe82 bl 800c710 + /* USER CODE BEGIN MX_SubGHz_Phy_Process_2 */ + + /* USER CODE END MX_SubGHz_Phy_Process_2 */ +} + 800ba0c: bf00 nop + 800ba0e: bd80 pop {r7, pc} + +0800ba10 : + +/* USER CODE END PFP */ + +/* Exported functions ---------------------------------------------------------*/ +void SubghzApp_Init(void) +{ + 800ba10: b590 push {r4, r7, lr} + 800ba12: b08d sub sp, #52 @ 0x34 + 800ba14: af04 add r7, sp, #16 +#elif (( USE_MODEM_LORA == 0 ) && ( USE_MODEM_FSK == 1 ) && (TEST_MODE == RADIO_TX)) + TxConfigGeneric_t TxConfig; +#else +#endif /* TEST_MODE */ + /* Get SubGHY_Phy APP version*/ + APP_LOG(TS_OFF, VLEVEL_M, "APPLICATION_VERSION: V%X.%X.%X\r\n", + 800ba16: 2300 movs r3, #0 + 800ba18: 9302 str r3, [sp, #8] + 800ba1a: 2304 movs r3, #4 + 800ba1c: 9301 str r3, [sp, #4] + 800ba1e: 2301 movs r3, #1 + 800ba20: 9300 str r3, [sp, #0] + 800ba22: 4b48 ldr r3, [pc, #288] @ (800bb44 ) + 800ba24: 2200 movs r2, #0 + 800ba26: 2100 movs r1, #0 + 800ba28: 2002 movs r0, #2 + 800ba2a: f001 faab bl 800cf84 + (uint8_t)(APP_VERSION_MAIN), + (uint8_t)(APP_VERSION_SUB1), + (uint8_t)(APP_VERSION_SUB2)); + + /* Get MW SubGhz_Phy info */ + APP_LOG(TS_OFF, VLEVEL_M, "MW_RADIO_VERSION: V%X.%X.%X\r\n", + 800ba2e: 2301 movs r3, #1 + 800ba30: 9302 str r3, [sp, #8] + 800ba32: 2303 movs r3, #3 + 800ba34: 9301 str r3, [sp, #4] + 800ba36: 2301 movs r3, #1 + 800ba38: 9300 str r3, [sp, #0] + 800ba3a: 4b43 ldr r3, [pc, #268] @ (800bb48 ) + 800ba3c: 2200 movs r2, #0 + 800ba3e: 2100 movs r1, #0 + 800ba40: 2002 movs r0, #2 + 800ba42: f001 fa9f bl 800cf84 + (uint8_t)(SUBGHZ_PHY_VERSION_MAIN), + (uint8_t)(SUBGHZ_PHY_VERSION_SUB1), + (uint8_t)(SUBGHZ_PHY_VERSION_SUB2)); + + APP_LOG(TS_OFF, VLEVEL_M, "---------------\n\r"); + 800ba46: 4b41 ldr r3, [pc, #260] @ (800bb4c ) + 800ba48: 2200 movs r2, #0 + 800ba4a: 2100 movs r1, #0 + 800ba4c: 2002 movs r0, #2 + 800ba4e: f001 fa99 bl 800cf84 +#if (( USE_MODEM_LORA == 1 ) && ( USE_MODEM_FSK == 0 )) + APP_LOG(TS_OFF, VLEVEL_M, "LORA_MODULATION\n\r"); + APP_LOG(TS_OFF, VLEVEL_M, "LORA_BW=%d Hz\n\r", 125000); +#elif (( USE_MODEM_LORA == 0 ) && ( USE_MODEM_FSK == 1 )) + APP_LOG(TS_OFF, VLEVEL_M, "FSK_MODULATION\n\r"); + 800ba52: 4b3f ldr r3, [pc, #252] @ (800bb50 ) + 800ba54: 2200 movs r2, #0 + 800ba56: 2100 movs r1, #0 + 800ba58: 2002 movs r0, #2 + 800ba5a: f001 fa93 bl 800cf84 + APP_LOG(TS_OFF, VLEVEL_M, "FSK_BW=%d Hz\n\r", FSK_BANDWIDTH); + 800ba5e: f246 13a8 movw r3, #25000 @ 0x61a8 + 800ba62: 9300 str r3, [sp, #0] + 800ba64: 4b3b ldr r3, [pc, #236] @ (800bb54 ) + 800ba66: 2200 movs r2, #0 + 800ba68: 2100 movs r1, #0 + 800ba6a: 2002 movs r0, #2 + 800ba6c: f001 fa8a bl 800cf84 + APP_LOG(TS_OFF, VLEVEL_M, "FSK_DR=%d bits/s\n\r", FSK_DATARATE); + 800ba70: f242 7310 movw r3, #10000 @ 0x2710 + 800ba74: 9300 str r3, [sp, #0] + 800ba76: 4b38 ldr r3, [pc, #224] @ (800bb58 ) + 800ba78: 2200 movs r2, #0 + 800ba7a: 2100 movs r1, #0 + 800ba7c: 2002 movs r0, #2 + 800ba7e: f001 fa81 bl 800cf84 +#if (TEST_MODE == RADIO_RX) + APP_LOG(TS_OFF, VLEVEL_M, "Rx Mode\n\r", FSK_DATARATE); +#elif (TEST_MODE == RADIO_TX) + APP_LOG(TS_OFF, VLEVEL_M, "Tx Mode\n\r", FSK_DATARATE); + 800ba82: f242 7310 movw r3, #10000 @ 0x2710 + 800ba86: 9300 str r3, [sp, #0] + 800ba88: 4b34 ldr r3, [pc, #208] @ (800bb5c ) + 800ba8a: 2200 movs r2, #0 + 800ba8c: 2100 movs r1, #0 + 800ba8e: 2002 movs r0, #2 + 800ba90: f001 fa78 bl 800cf84 +#error "Please define a modem in the compiler subghz_phy_app.h." +#endif /* USE_MODEM_LORA | USE_MODEM_FSK */ + /* USER CODE END SubghzApp_Init_1 */ + + /* Radio initialization */ + RadioEvents.TxDone = OnTxDone; + 800ba94: 4b32 ldr r3, [pc, #200] @ (800bb60 ) + 800ba96: 4a33 ldr r2, [pc, #204] @ (800bb64 ) + 800ba98: 601a str r2, [r3, #0] + RadioEvents.RxDone = OnRxDone; + 800ba9a: 4b31 ldr r3, [pc, #196] @ (800bb60 ) + 800ba9c: 4a32 ldr r2, [pc, #200] @ (800bb68 ) + 800ba9e: 609a str r2, [r3, #8] + RadioEvents.TxTimeout = OnTxTimeout; + 800baa0: 4b2f ldr r3, [pc, #188] @ (800bb60 ) + 800baa2: 4a32 ldr r2, [pc, #200] @ (800bb6c ) + 800baa4: 605a str r2, [r3, #4] + RadioEvents.RxTimeout = OnRxTimeout; + 800baa6: 4b2e ldr r3, [pc, #184] @ (800bb60 ) + 800baa8: 4a31 ldr r2, [pc, #196] @ (800bb70 ) + 800baaa: 60da str r2, [r3, #12] + RadioEvents.RxError = OnRxError; + 800baac: 4b2c ldr r3, [pc, #176] @ (800bb60 ) + 800baae: 4a31 ldr r2, [pc, #196] @ (800bb74 ) + 800bab0: 611a str r2, [r3, #16] + + Radio.Init(&RadioEvents); + 800bab2: 4b31 ldr r3, [pc, #196] @ (800bb78 ) + 800bab4: 681b ldr r3, [r3, #0] + 800bab6: 482a ldr r0, [pc, #168] @ (800bb60 ) + 800bab8: 4798 blx r3 + + /* USER CODE BEGIN SubghzApp_Init_2 */ + /* Radio Set frequency */ + Radio.SetChannel(RF_FREQUENCY); + 800baba: 4b2f ldr r3, [pc, #188] @ (800bb78 ) + 800babc: 68db ldr r3, [r3, #12] + 800babe: 482f ldr r0, [pc, #188] @ (800bb7c ) + 800bac0: 4798 blx r3 + + data_offset = 0; + 800bac2: 4b2f ldr r3, [pc, #188] @ (800bb80 ) + 800bac4: 2200 movs r2, #0 + 800bac6: 801a strh r2, [r3, #0] +#else + (void) Radio.ReceiveLongPacket(0, RX_TIMEOUT_VALUE, RxLongPacketChunk); +#endif /* APP_LONG_PACKET */ + +#elif (TEST_MODE == RADIO_TX) + tx_payload_generator(); + 800bac8: f000 f9ba bl 800be40 + true, 0, 0, LORA_IQ_INVERSION_ON, TX_TIMEOUT_VALUE); + + Radio.SetMaxPayloadLength(MODEM_LORA, MAX_APP_BUFFER_SIZE); +#elif (( USE_MODEM_LORA == 0 ) && ( USE_MODEM_FSK == 1 )) + /*fsk modulation*/ + TxConfig.fsk.ModulationShaping = RADIO_FSK_MOD_SHAPING_G_BT_05; + 800bacc: 2309 movs r3, #9 + 800bace: 75fb strb r3, [r7, #23] + TxConfig.fsk.FrequencyDeviation = FSK_FDEV; + 800bad0: f246 13a8 movw r3, #25000 @ 0x61a8 + 800bad4: 61fb str r3, [r7, #28] + TxConfig.fsk.BitRate = FSK_DATARATE; /*BitRate*/ + 800bad6: f242 7310 movw r3, #10000 @ 0x2710 + 800bada: 607b str r3, [r7, #4] + TxConfig.fsk.PreambleLen = 4; /*in Byte */ + 800badc: 2304 movs r3, #4 + 800bade: 60bb str r3, [r7, #8] + TxConfig.fsk.SyncWordLength = sizeof(syncword); /*in Byte */ + 800bae0: 2303 movs r3, #3 + 800bae2: 75bb strb r3, [r7, #22] + TxConfig.fsk.SyncWord = syncword; /*SyncWord Buffer*/ + 800bae4: 4b27 ldr r3, [pc, #156] @ (800bb84 ) + 800bae6: 60fb str r3, [r7, #12] + TxConfig.fsk.whiteSeed = 0x01FF; /*WhiteningSeed */ + 800bae8: f240 13ff movw r3, #511 @ 0x1ff + 800baec: 82bb strh r3, [r7, #20] +#if (APP_LONG_PACKET==0) + TxConfig.fsk.HeaderType = RADIO_FSK_PACKET_VARIABLE_LENGTH; /*legacy: payload length field is 1 byte long*/ + 800baee: 2301 movs r3, #1 + 800baf0: 763b strb r3, [r7, #24] +#else + TxConfig.fsk.HeaderType = RADIO_FSK_PACKET_2BYTES_LENGTH; /* payload length field is 2 bytes long */ +#endif /* APP_LONG_PACKET */ + TxConfig.fsk.CrcLength = RADIO_FSK_CRC_2_BYTES_IBM; /* Size of the CRC block in the GFSK packet*/ + 800baf2: 23f1 movs r3, #241 @ 0xf1 + 800baf4: 767b strb r3, [r7, #25] + TxConfig.fsk.CrcPolynomial = 0x8005; + 800baf6: f248 0305 movw r3, #32773 @ 0x8005 + 800bafa: 823b strh r3, [r7, #16] + TxConfig.fsk.CrcSeed = 0xFFFF; + 800bafc: f64f 73ff movw r3, #65535 @ 0xffff + 800bb00: 827b strh r3, [r7, #18] + TxConfig.fsk.Whitening = RADIO_FSK_DC_FREEWHITENING; + 800bb02: 2301 movs r3, #1 + 800bb04: 76bb strb r3, [r7, #26] + if (0UL != Radio.RadioSetTxGenericConfig(GENERIC_FSK, &TxConfig, TX_OUTPUT_POWER, TX_TIMEOUT_VALUE)) + 800bb06: 4b1c ldr r3, [pc, #112] @ (800bb78 ) + 800bb08: 6f9c ldr r4, [r3, #120] @ 0x78 + 800bb0a: 1d39 adds r1, r7, #4 + 800bb0c: f640 33b8 movw r3, #3000 @ 0xbb8 + 800bb10: 2210 movs r2, #16 + 800bb12: 2000 movs r0, #0 + 800bb14: 47a0 blx r4 + 800bb16: 4603 mov r3, r0 + 800bb18: 2b00 cmp r3, #0 + 800bb1a: d001 beq.n 800bb20 + { + while (1); + 800bb1c: bf00 nop + 800bb1e: e7fd b.n 800bb1c +#else +#error "Please define a modem in the compiler subghz_phy_app.h." +#endif /* USE_MODEM_LORA | USE_MODEM_FSK */ + +#if (APP_LONG_PACKET==0) + Radio.Send(data_buffer, payloadLen); + 800bb20: 4b15 ldr r3, [pc, #84] @ (800bb78 ) + 800bb22: 6a9b ldr r3, [r3, #40] @ 0x28 + 800bb24: 4a18 ldr r2, [pc, #96] @ (800bb88 ) + 800bb26: 8812 ldrh r2, [r2, #0] + 800bb28: b292 uxth r2, r2 + 800bb2a: b2d2 uxtb r2, r2 + 800bb2c: 4611 mov r1, r2 + 800bb2e: 4817 ldr r0, [pc, #92] @ (800bb8c ) + 800bb30: 4798 blx r3 +#else +#error should be either Tx or Rx +#endif /* TEST_MODE */ + + /*register task to to be run in while(1) after Radio IT*/ + UTIL_SEQ_RegTask((1 << CFG_SEQ_Task_SubGHz_Phy_App_Process), UTIL_SEQ_RFU, Per_Process); + 800bb32: 4a17 ldr r2, [pc, #92] @ (800bb90 ) + 800bb34: 2100 movs r1, #0 + 800bb36: 2001 movs r0, #1 + 800bb38: f000 fee6 bl 800c908 + /* USER CODE END SubghzApp_Init_2 */ +} + 800bb3c: bf00 nop + 800bb3e: 3724 adds r7, #36 @ 0x24 + 800bb40: 46bd mov sp, r7 + 800bb42: bd90 pop {r4, r7, pc} + 800bb44: 0800d73c .word 0x0800d73c + 800bb48: 0800d760 .word 0x0800d760 + 800bb4c: 0800d784 .word 0x0800d784 + 800bb50: 0800d798 .word 0x0800d798 + 800bb54: 0800d7ac .word 0x0800d7ac + 800bb58: 0800d7bc .word 0x0800d7bc + 800bb5c: 0800d7d0 .word 0x0800d7d0 + 800bb60: 20000580 .word 0x20000580 + 800bb64: 0800bb95 .word 0x0800bb95 + 800bb68: 0800bbb1 .word 0x0800bbb1 + 800bb6c: 0800bc15 .word 0x0800bc15 + 800bb70: 0800bc31 .word 0x0800bc31 + 800bb74: 0800bc4d .word 0x0800bc4d + 800bb78: 0800d9e0 .word 0x0800d9e0 + 800bb7c: 19d094e0 .word 0x19d094e0 + 800bb80: 2000099c .word 0x2000099c + 800bb84: 20000010 .word 0x20000010 + 800bb88: 2000000a .word 0x2000000a + 800bb8c: 200005b4 .word 0x200005b4 + 800bb90: 0800bc69 .word 0x0800bc69 + +0800bb94 : + +/* USER CODE END EF */ + +/* Private functions ---------------------------------------------------------*/ +static void OnTxDone(void) +{ + 800bb94: b580 push {r7, lr} + 800bb96: af00 add r7, sp, #0 + /* USER CODE BEGIN OnTxDone */ + RadioTxDone_flag = 1; + 800bb98: 4b04 ldr r3, [pc, #16] @ (800bbac ) + 800bb9a: 2201 movs r2, #1 + 800bb9c: 601a str r2, [r3, #0] + UTIL_SEQ_SetTask((1 << CFG_SEQ_Task_SubGHz_Phy_App_Process), CFG_SEQ_Prio_0); + 800bb9e: 2100 movs r1, #0 + 800bba0: 2001 movs r0, #1 + 800bba2: f000 fed3 bl 800c94c + /* USER CODE END OnTxDone */ +} + 800bba6: bf00 nop + 800bba8: bd80 pop {r7, pc} + 800bbaa: bf00 nop + 800bbac: 2000059c .word 0x2000059c + +0800bbb0 : + +static void OnRxDone(uint8_t *payload, uint16_t size, int16_t rssi, int8_t LoraSnr_FskCfo) +{ + 800bbb0: b580 push {r7, lr} + 800bbb2: b084 sub sp, #16 + 800bbb4: af00 add r7, sp, #0 + 800bbb6: 60f8 str r0, [r7, #12] + 800bbb8: 4608 mov r0, r1 + 800bbba: 4611 mov r1, r2 + 800bbbc: 461a mov r2, r3 + 800bbbe: 4603 mov r3, r0 + 800bbc0: 817b strh r3, [r7, #10] + 800bbc2: 460b mov r3, r1 + 800bbc4: 813b strh r3, [r7, #8] + 800bbc6: 4613 mov r3, r2 + 800bbc8: 71fb strb r3, [r7, #7] + /* USER CODE BEGIN OnRxDone */ + last_rx_rssi = rssi; + 800bbca: 4a0d ldr r2, [pc, #52] @ (800bc00 ) + 800bbcc: 893b ldrh r3, [r7, #8] + 800bbce: 8013 strh r3, [r2, #0] + last_rx_cfo = LoraSnr_FskCfo; + 800bbd0: 4a0c ldr r2, [pc, #48] @ (800bc04 ) + 800bbd2: 79fb ldrb r3, [r7, #7] + 800bbd4: 7013 strb r3, [r2, #0] + + /* Set Rxdone flag */ + RadioRxDone_flag = 1; + 800bbd6: 4b0c ldr r3, [pc, #48] @ (800bc08 ) + 800bbd8: 2201 movs r2, #1 + 800bbda: 601a str r2, [r3, #0] + /* Run Per process in background*/ + UTIL_SEQ_SetTask((1 << CFG_SEQ_Task_SubGHz_Phy_App_Process), CFG_SEQ_Prio_0); + 800bbdc: 2100 movs r1, #0 + 800bbde: 2001 movs r0, #1 + 800bbe0: f000 feb4 bl 800c94c +#if (APP_LONG_PACKET==0) + memcpy(data_buffer, payload, size); + 800bbe4: 897b ldrh r3, [r7, #10] + 800bbe6: 461a mov r2, r3 + 800bbe8: 68f9 ldr r1, [r7, #12] + 800bbea: 4808 ldr r0, [pc, #32] @ (800bc0c ) + 800bbec: f001 fc6e bl 800d4cc + payloadLen = size; + 800bbf0: 4a07 ldr r2, [pc, #28] @ (800bc10 ) + 800bbf2: 897b ldrh r3, [r7, #10] + 800bbf4: 8013 strh r3, [r2, #0] + /*from chunk*/ + payloadLen = data_offset; + /*payload data are not relevant in long packet mode*/ +#endif /* APP_LONG_PACKET */ + /* USER CODE END OnRxDone */ +} + 800bbf6: bf00 nop + 800bbf8: 3710 adds r7, #16 + 800bbfa: 46bd mov sp, r7 + 800bbfc: bd80 pop {r7, pc} + 800bbfe: bf00 nop + 800bc00: 200005b0 .word 0x200005b0 + 800bc04: 200005b2 .word 0x200005b2 + 800bc08: 200005a4 .word 0x200005a4 + 800bc0c: 200005b4 .word 0x200005b4 + 800bc10: 2000000a .word 0x2000000a + +0800bc14 : + +static void OnTxTimeout(void) +{ + 800bc14: b580 push {r7, lr} + 800bc16: af00 add r7, sp, #0 + /* USER CODE BEGIN OnTxTimeout */ + RadioTxTimeout_flag = 1; + 800bc18: 4b04 ldr r3, [pc, #16] @ (800bc2c ) + 800bc1a: 2201 movs r2, #1 + 800bc1c: 601a str r2, [r3, #0] + /* Run process in background*/ + UTIL_SEQ_SetTask((1 << CFG_SEQ_Task_SubGHz_Phy_App_Process), CFG_SEQ_Prio_0); + 800bc1e: 2100 movs r1, #0 + 800bc20: 2001 movs r0, #1 + 800bc22: f000 fe93 bl 800c94c + /* USER CODE END OnTxTimeout */ +} + 800bc26: bf00 nop + 800bc28: bd80 pop {r7, pc} + 800bc2a: bf00 nop + 800bc2c: 200005a0 .word 0x200005a0 + +0800bc30 : + +static void OnRxTimeout(void) +{ + 800bc30: b580 push {r7, lr} + 800bc32: af00 add r7, sp, #0 + /* USER CODE BEGIN OnRxTimeout */ + RadioRxTimeout_flag = 1; + 800bc34: 4b04 ldr r3, [pc, #16] @ (800bc48 ) + 800bc36: 2201 movs r2, #1 + 800bc38: 601a str r2, [r3, #0] + /* Run Per process in background*/ + UTIL_SEQ_SetTask((1 << CFG_SEQ_Task_SubGHz_Phy_App_Process), CFG_SEQ_Prio_0); + 800bc3a: 2100 movs r1, #0 + 800bc3c: 2001 movs r0, #1 + 800bc3e: f000 fe85 bl 800c94c + /* USER CODE END OnRxTimeout */ +} + 800bc42: bf00 nop + 800bc44: bd80 pop {r7, pc} + 800bc46: bf00 nop + 800bc48: 200005a8 .word 0x200005a8 + +0800bc4c : + +static void OnRxError(void) +{ + 800bc4c: b580 push {r7, lr} + 800bc4e: af00 add r7, sp, #0 + /* USER CODE BEGIN OnRxError */ + RadioError_flag = 1; + 800bc50: 4b04 ldr r3, [pc, #16] @ (800bc64 ) + 800bc52: 2201 movs r2, #1 + 800bc54: 601a str r2, [r3, #0] + /* Run Per process in background*/ + UTIL_SEQ_SetTask((1 << CFG_SEQ_Task_SubGHz_Phy_App_Process), CFG_SEQ_Prio_0); + 800bc56: 2100 movs r1, #0 + 800bc58: 2001 movs r0, #1 + 800bc5a: f000 fe77 bl 800c94c + /* USER CODE END OnRxError */ +} + 800bc5e: bf00 nop + 800bc60: bd80 pop {r7, pc} + 800bc62: bf00 nop + 800bc64: 200005ac .word 0x200005ac + +0800bc68 : + /* APP_TPRINTF("Tx chunk: chunk_size=%d, data_offset=%d\r\n",chunk_size, data_offset); */ +} +#endif /* APP_LONG_PACKET */ +uint8_t buffer_error = 0; +static void Per_Process(void) +{ + 800bc68: b580 push {r7, lr} + 800bc6a: b082 sub sp, #8 + 800bc6c: af02 add r7, sp, #8 + packetCnt++; + 800bc6e: 4b2b ldr r3, [pc, #172] @ (800bd1c ) + 800bc70: 681b ldr r3, [r3, #0] + 800bc72: 3301 adds r3, #1 + 800bc74: 4a29 ldr r2, [pc, #164] @ (800bd1c ) + 800bc76: 6013 str r3, [r2, #0] + data_offset = 0; + 800bc78: 4b29 ldr r3, [pc, #164] @ (800bd20 ) + 800bc7a: 2200 movs r2, #0 + 800bc7c: 801a strh r2, [r3, #0] +#endif /* APP_LONG_PACKET */ + HAL_Delay(10); + HAL_GPIO_WritePin(LED2_GPIO_Port, LED2_Pin, GPIO_PIN_RESET); /* LED_GREEN */ + HAL_GPIO_WritePin(LED3_GPIO_Port, LED3_Pin, GPIO_PIN_RESET); /* LED_RED */ +#elif (TEST_MODE == RADIO_TX) + HAL_GPIO_WritePin(LED1_GPIO_Port, LED1_Pin, GPIO_PIN_RESET); /* LED_BLUE */ + 800bc7e: 2200 movs r2, #0 + 800bc80: f44f 4100 mov.w r1, #32768 @ 0x8000 + 800bc84: 4827 ldr r0, [pc, #156] @ (800bd24 ) + 800bc86: f7f6 fd5d bl 8002744 + if (RadioTxDone_flag == 1) + 800bc8a: 4b27 ldr r3, [pc, #156] @ (800bd28 ) + 800bc8c: 681b ldr r3, [r3, #0] + 800bc8e: 2b01 cmp r3, #1 + 800bc90: d105 bne.n 800bc9e + { + APP_TPRINTF("OnTxDone\r\n"); + 800bc92: 4b26 ldr r3, [pc, #152] @ (800bd2c ) + 800bc94: 2201 movs r2, #1 + 800bc96: 2100 movs r1, #0 + 800bc98: 2000 movs r0, #0 + 800bc9a: f001 f973 bl 800cf84 + } + + if (RadioTxTimeout_flag == 1) + 800bc9e: 4b24 ldr r3, [pc, #144] @ (800bd30 ) + 800bca0: 681b ldr r3, [r3, #0] + 800bca2: 2b01 cmp r3, #1 + 800bca4: d105 bne.n 800bcb2 + { + APP_TPRINTF("OnTxTimeout\r\n"); + 800bca6: 4b23 ldr r3, [pc, #140] @ (800bd34 ) + 800bca8: 2201 movs r2, #1 + 800bcaa: 2100 movs r1, #0 + 800bcac: 2000 movs r0, #0 + 800bcae: f001 f969 bl 800cf84 + } + + if (RadioError_flag == 1) + 800bcb2: 4b21 ldr r3, [pc, #132] @ (800bd38 ) + 800bcb4: 681b ldr r3, [r3, #0] + 800bcb6: 2b01 cmp r3, #1 + 800bcb8: d105 bne.n 800bcc6 + { + APP_TPRINTF("OnRxError\r\n"); + 800bcba: 4b20 ldr r3, [pc, #128] @ (800bd3c ) + 800bcbc: 2201 movs r2, #1 + 800bcbe: 2100 movs r1, #0 + 800bcc0: 2000 movs r0, #0 + 800bcc2: f001 f95f bl 800cf84 + } + /* This delay is only to give enough time to allow DMA to empty printf queue*/ + HAL_Delay(500); + 800bcc6: f44f 70fa mov.w r0, #500 @ 0x1f4 + 800bcca: f7f4 ff6d bl 8000ba8 + /* Reset TX Done or timeout flags */ + RadioTxDone_flag = 0; + 800bcce: 4b16 ldr r3, [pc, #88] @ (800bd28 ) + 800bcd0: 2200 movs r2, #0 + 800bcd2: 601a str r2, [r3, #0] + RadioTxTimeout_flag = 0; + 800bcd4: 4b16 ldr r3, [pc, #88] @ (800bd30 ) + 800bcd6: 2200 movs r2, #0 + 800bcd8: 601a str r2, [r3, #0] + RadioError_flag = 0; + 800bcda: 4b17 ldr r3, [pc, #92] @ (800bd38 ) + 800bcdc: 2200 movs r2, #0 + 800bcde: 601a str r2, [r3, #0] + + tx_payload_generator(); + 800bce0: f000 f8ae bl 800be40 +#if (APP_LONG_PACKET==0) + Radio.Send(data_buffer, payloadLen); + 800bce4: 4b16 ldr r3, [pc, #88] @ (800bd40 ) + 800bce6: 6a9b ldr r3, [r3, #40] @ 0x28 + 800bce8: 4a16 ldr r2, [pc, #88] @ (800bd44 ) + 800bcea: 8812 ldrh r2, [r2, #0] + 800bcec: b292 uxth r2, r2 + 800bcee: b2d2 uxtb r2, r2 + 800bcf0: 4611 mov r1, r2 + 800bcf2: 4815 ldr r0, [pc, #84] @ (800bd48 ) + 800bcf4: 4798 blx r3 + if (0UL != Radio.TransmitLongPacket(payloadLen, TX_TIMEOUT_VALUE, TxLongPacketGetNextChunk)) + { + while (1); + } +#endif /* APP_LONG_PACKET */ + APP_TPRINTF("Tx %d \r\n", packetCnt); + 800bcf6: 4b09 ldr r3, [pc, #36] @ (800bd1c ) + 800bcf8: 681b ldr r3, [r3, #0] + 800bcfa: 9300 str r3, [sp, #0] + 800bcfc: 4b13 ldr r3, [pc, #76] @ (800bd4c ) + 800bcfe: 2201 movs r2, #1 + 800bd00: 2100 movs r1, #0 + 800bd02: 2000 movs r0, #0 + 800bd04: f001 f93e bl 800cf84 + HAL_GPIO_WritePin(LED1_GPIO_Port, LED1_Pin, GPIO_PIN_SET); /* LED_BLUE */ + 800bd08: 2201 movs r2, #1 + 800bd0a: f44f 4100 mov.w r1, #32768 @ 0x8000 + 800bd0e: 4805 ldr r0, [pc, #20] @ (800bd24 ) + 800bd10: f7f6 fd18 bl 8002744 +#endif /* TEST_MODE */ +} + 800bd14: bf00 nop + 800bd16: 46bd mov sp, r7 + 800bd18: bd80 pop {r7, pc} + 800bd1a: bf00 nop + 800bd1c: 200009a0 .word 0x200009a0 + 800bd20: 2000099c .word 0x2000099c + 800bd24: 48000400 .word 0x48000400 + 800bd28: 2000059c .word 0x2000059c + 800bd2c: 0800d7dc .word 0x0800d7dc + 800bd30: 200005a0 .word 0x200005a0 + 800bd34: 0800d7e8 .word 0x0800d7e8 + 800bd38: 200005ac .word 0x200005ac + 800bd3c: 0800d7f8 .word 0x0800d7f8 + 800bd40: 0800d9e0 .word 0x0800d9e0 + 800bd44: 2000000a .word 0x2000000a + 800bd48: 200005b4 .word 0x200005b4 + 800bd4c: 0800d804 .word 0x0800d804 + +0800bd50 : + +#if (TEST_MODE == RADIO_TX) +void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) +{ + 800bd50: b580 push {r7, lr} + 800bd52: b084 sub sp, #16 + 800bd54: af02 add r7, sp, #8 + 800bd56: 4603 mov r3, r0 + 800bd58: 80fb strh r3, [r7, #6] + switch (GPIO_Pin) + 800bd5a: 88fb ldrh r3, [r7, #6] + 800bd5c: 2b40 cmp r3, #64 @ 0x40 + 800bd5e: d03e beq.n 800bdde + 800bd60: 2b40 cmp r3, #64 @ 0x40 + 800bd62: dc5b bgt.n 800be1c + 800bd64: 2b01 cmp r3, #1 + 800bd66: d002 beq.n 800bd6e + 800bd68: 2b02 cmp r3, #2 + 800bd6a: d01c beq.n 800bda6 + { + APP_TPRINTF("Payload Inc mode\r\n"); + } + break; + default: + break; + 800bd6c: e056 b.n 800be1c + payloadLen += 16; + 800bd6e: 4b2e ldr r3, [pc, #184] @ (800be28 ) + 800bd70: 881b ldrh r3, [r3, #0] + 800bd72: b29b uxth r3, r3 + 800bd74: 3310 adds r3, #16 + 800bd76: b29a uxth r2, r3 + 800bd78: 4b2b ldr r3, [pc, #172] @ (800be28 ) + 800bd7a: 801a strh r2, [r3, #0] + if (payloadLen > payloadLenMax) + 800bd7c: 4b2a ldr r3, [pc, #168] @ (800be28 ) + 800bd7e: 881b ldrh r3, [r3, #0] + 800bd80: b29a uxth r2, r3 + 800bd82: 4b2a ldr r3, [pc, #168] @ (800be2c ) + 800bd84: 881b ldrh r3, [r3, #0] + 800bd86: 429a cmp r2, r3 + 800bd88: d902 bls.n 800bd90 + payloadLen = 16; + 800bd8a: 4b27 ldr r3, [pc, #156] @ (800be28 ) + 800bd8c: 2210 movs r2, #16 + 800bd8e: 801a strh r2, [r3, #0] + APP_TPRINTF("New Tx Payload Length= %d\r\n", payloadLen); + 800bd90: 4b25 ldr r3, [pc, #148] @ (800be28 ) + 800bd92: 881b ldrh r3, [r3, #0] + 800bd94: b29b uxth r3, r3 + 800bd96: 9300 str r3, [sp, #0] + 800bd98: 4b25 ldr r3, [pc, #148] @ (800be30 ) + 800bd9a: 2201 movs r2, #1 + 800bd9c: 2100 movs r1, #0 + 800bd9e: 2000 movs r0, #0 + 800bda0: f001 f8f0 bl 800cf84 + break; + 800bda4: e03b b.n 800be1e + payloadLen += 1; + 800bda6: 4b20 ldr r3, [pc, #128] @ (800be28 ) + 800bda8: 881b ldrh r3, [r3, #0] + 800bdaa: b29b uxth r3, r3 + 800bdac: 3301 adds r3, #1 + 800bdae: b29a uxth r2, r3 + 800bdb0: 4b1d ldr r3, [pc, #116] @ (800be28 ) + 800bdb2: 801a strh r2, [r3, #0] + if (payloadLen > payloadLenMax) + 800bdb4: 4b1c ldr r3, [pc, #112] @ (800be28 ) + 800bdb6: 881b ldrh r3, [r3, #0] + 800bdb8: b29a uxth r2, r3 + 800bdba: 4b1c ldr r3, [pc, #112] @ (800be2c ) + 800bdbc: 881b ldrh r3, [r3, #0] + 800bdbe: 429a cmp r2, r3 + 800bdc0: d902 bls.n 800bdc8 + payloadLen = 1; + 800bdc2: 4b19 ldr r3, [pc, #100] @ (800be28 ) + 800bdc4: 2201 movs r2, #1 + 800bdc6: 801a strh r2, [r3, #0] + APP_TPRINTF("New Tx Payload Length= %d\r\n", payloadLen); + 800bdc8: 4b17 ldr r3, [pc, #92] @ (800be28 ) + 800bdca: 881b ldrh r3, [r3, #0] + 800bdcc: b29b uxth r3, r3 + 800bdce: 9300 str r3, [sp, #0] + 800bdd0: 4b17 ldr r3, [pc, #92] @ (800be30 ) + 800bdd2: 2201 movs r2, #1 + 800bdd4: 2100 movs r1, #0 + 800bdd6: 2000 movs r0, #0 + 800bdd8: f001 f8d4 bl 800cf84 + break; + 800bddc: e01f b.n 800be1e + TxPayloadMode = (TxPayloadMode + 1) % 2; + 800bdde: 4b15 ldr r3, [pc, #84] @ (800be34 ) + 800bde0: 781b ldrb r3, [r3, #0] + 800bde2: b2db uxtb r3, r3 + 800bde4: 3301 adds r3, #1 + 800bde6: 2b00 cmp r3, #0 + 800bde8: f003 0301 and.w r3, r3, #1 + 800bdec: bfb8 it lt + 800bdee: 425b neglt r3, r3 + 800bdf0: b2da uxtb r2, r3 + 800bdf2: 4b10 ldr r3, [pc, #64] @ (800be34 ) + 800bdf4: 701a strb r2, [r3, #0] + if (TxPayloadMode == 1) + 800bdf6: 4b0f ldr r3, [pc, #60] @ (800be34 ) + 800bdf8: 781b ldrb r3, [r3, #0] + 800bdfa: b2db uxtb r3, r3 + 800bdfc: 2b01 cmp r3, #1 + 800bdfe: d106 bne.n 800be0e + APP_TPRINTF("Payload PRBS9 mode\r\n"); + 800be00: 4b0d ldr r3, [pc, #52] @ (800be38 ) + 800be02: 2201 movs r2, #1 + 800be04: 2100 movs r1, #0 + 800be06: 2000 movs r0, #0 + 800be08: f001 f8bc bl 800cf84 + break; + 800be0c: e007 b.n 800be1e + APP_TPRINTF("Payload Inc mode\r\n"); + 800be0e: 4b0b ldr r3, [pc, #44] @ (800be3c ) + 800be10: 2201 movs r2, #1 + 800be12: 2100 movs r1, #0 + 800be14: 2000 movs r0, #0 + 800be16: f001 f8b5 bl 800cf84 + break; + 800be1a: e000 b.n 800be1e + break; + 800be1c: bf00 nop + } +} + 800be1e: bf00 nop + 800be20: 3708 adds r7, #8 + 800be22: 46bd mov sp, r7 + 800be24: bd80 pop {r7, pc} + 800be26: bf00 nop + 800be28: 2000000a .word 0x2000000a + 800be2c: 2000000c .word 0x2000000c + 800be30: 0800d810 .word 0x0800d810 + 800be34: 200009a4 .word 0x200009a4 + 800be38: 0800d82c .word 0x0800d82c + 800be3c: 0800d844 .word 0x0800d844 + +0800be40 : + +static int32_t tx_payload_generator(void) +{ + 800be40: b480 push {r7} + 800be42: b087 sub sp, #28 + 800be44: af00 add r7, sp, #0 + if (TxPayloadMode == 1) + 800be46: 4b37 ldr r3, [pc, #220] @ (800bf24 ) + 800be48: 781b ldrb r3, [r3, #0] + 800be4a: b2db uxtb r3, r3 + 800be4c: 2b01 cmp r3, #1 + 800be4e: d14e bne.n 800beee + { + uint16_t prbs9_val = PRBS9_INIT; + 800be50: 2302 movs r3, #2 + 800be52: 82fb strh r3, [r7, #22] + for (int32_t i = 0; i < payloadLen; i++) + 800be54: 2300 movs r3, #0 + 800be56: 613b str r3, [r7, #16] + 800be58: e007 b.n 800be6a + { + data_buffer[i] = 0; + 800be5a: 4a33 ldr r2, [pc, #204] @ (800bf28 ) + 800be5c: 693b ldr r3, [r7, #16] + 800be5e: 4413 add r3, r2 + 800be60: 2200 movs r2, #0 + 800be62: 701a strb r2, [r3, #0] + for (int32_t i = 0; i < payloadLen; i++) + 800be64: 693b ldr r3, [r7, #16] + 800be66: 3301 adds r3, #1 + 800be68: 613b str r3, [r7, #16] + 800be6a: 4b30 ldr r3, [pc, #192] @ (800bf2c ) + 800be6c: 881b ldrh r3, [r3, #0] + 800be6e: b29b uxth r3, r3 + 800be70: 461a mov r2, r3 + 800be72: 693b ldr r3, [r7, #16] + 800be74: 4293 cmp r3, r2 + 800be76: dbf0 blt.n 800be5a + } + for (int32_t i = 0; i < payloadLen * 8; i++) + 800be78: 2300 movs r3, #0 + 800be7a: 60fb str r3, [r7, #12] + 800be7c: e02f b.n 800bede + { + /*fill buffer with prbs9 sequence*/ + int32_t newbit = (((prbs9_val >> 8) ^ (prbs9_val >> 4)) & 1); + 800be7e: 8afb ldrh r3, [r7, #22] + 800be80: 0a1b lsrs r3, r3, #8 + 800be82: b29a uxth r2, r3 + 800be84: 8afb ldrh r3, [r7, #22] + 800be86: 091b lsrs r3, r3, #4 + 800be88: b29b uxth r3, r3 + 800be8a: 4053 eors r3, r2 + 800be8c: b29b uxth r3, r3 + 800be8e: f003 0301 and.w r3, r3, #1 + 800be92: 607b str r3, [r7, #4] + prbs9_val = ((prbs9_val << 1) | newbit) & 0x01ff; + 800be94: f9b7 3016 ldrsh.w r3, [r7, #22] + 800be98: 005b lsls r3, r3, #1 + 800be9a: b21a sxth r2, r3 + 800be9c: 687b ldr r3, [r7, #4] + 800be9e: b21b sxth r3, r3 + 800bea0: 4313 orrs r3, r2 + 800bea2: b21b sxth r3, r3 + 800bea4: b29b uxth r3, r3 + 800bea6: f3c3 0308 ubfx r3, r3, #0, #9 + 800beaa: 82fb strh r3, [r7, #22] + data_buffer[i / 8] |= ((prbs9_val & 0x1) << (i % 8)); + 800beac: 68fb ldr r3, [r7, #12] + 800beae: 2b00 cmp r3, #0 + 800beb0: da00 bge.n 800beb4 + 800beb2: 3307 adds r3, #7 + 800beb4: 10db asrs r3, r3, #3 + 800beb6: 4a1c ldr r2, [pc, #112] @ (800bf28 ) + 800beb8: 5cd2 ldrb r2, [r2, r3] + 800beba: b251 sxtb r1, r2 + 800bebc: 8afa ldrh r2, [r7, #22] + 800bebe: f002 0001 and.w r0, r2, #1 + 800bec2: 68fa ldr r2, [r7, #12] + 800bec4: f002 0207 and.w r2, r2, #7 + 800bec8: fa00 f202 lsl.w r2, r0, r2 + 800becc: b252 sxtb r2, r2 + 800bece: 430a orrs r2, r1 + 800bed0: b252 sxtb r2, r2 + 800bed2: b2d1 uxtb r1, r2 + 800bed4: 4a14 ldr r2, [pc, #80] @ (800bf28 ) + 800bed6: 54d1 strb r1, [r2, r3] + for (int32_t i = 0; i < payloadLen * 8; i++) + 800bed8: 68fb ldr r3, [r7, #12] + 800beda: 3301 adds r3, #1 + 800bedc: 60fb str r3, [r7, #12] + 800bede: 4b13 ldr r3, [pc, #76] @ (800bf2c ) + 800bee0: 881b ldrh r3, [r3, #0] + 800bee2: b29b uxth r3, r3 + 800bee4: 00db lsls r3, r3, #3 + 800bee6: 68fa ldr r2, [r7, #12] + 800bee8: 429a cmp r2, r3 + 800beea: dbc8 blt.n 800be7e + 800beec: e013 b.n 800bf16 + } + } + else + { + for (int32_t i = 0; i < payloadLen; i++) + 800beee: 2300 movs r3, #0 + 800bef0: 60bb str r3, [r7, #8] + 800bef2: e009 b.n 800bf08 + { + data_buffer[i] = i; + 800bef4: 68bb ldr r3, [r7, #8] + 800bef6: b2d9 uxtb r1, r3 + 800bef8: 4a0b ldr r2, [pc, #44] @ (800bf28 ) + 800befa: 68bb ldr r3, [r7, #8] + 800befc: 4413 add r3, r2 + 800befe: 460a mov r2, r1 + 800bf00: 701a strb r2, [r3, #0] + for (int32_t i = 0; i < payloadLen; i++) + 800bf02: 68bb ldr r3, [r7, #8] + 800bf04: 3301 adds r3, #1 + 800bf06: 60bb str r3, [r7, #8] + 800bf08: 4b08 ldr r3, [pc, #32] @ (800bf2c ) + 800bf0a: 881b ldrh r3, [r3, #0] + 800bf0c: b29b uxth r3, r3 + 800bf0e: 461a mov r2, r3 + 800bf10: 68bb ldr r3, [r7, #8] + 800bf12: 4293 cmp r3, r2 + 800bf14: dbee blt.n 800bef4 + } + } + return 0; + 800bf16: 2300 movs r3, #0 +} + 800bf18: 4618 mov r0, r3 + 800bf1a: 371c adds r7, #28 + 800bf1c: 46bd mov sp, r7 + 800bf1e: bc80 pop {r7} + 800bf20: 4770 bx lr + 800bf22: bf00 nop + 800bf24: 200009a4 .word 0x200009a4 + 800bf28: 200005b4 .word 0x200005b4 + 800bf2c: 2000000a .word 0x2000000a + +0800bf30 : + +/* USER CODE END PFP */ + +/* Exported functions --------------------------------------------------------*/ +int32_t RBI_Init(void) +{ + 800bf30: b580 push {r7, lr} + 800bf32: af00 add r7, sp, #0 + * 1/ For User boards, the BSP/STM32WLxx_Nucleo/ directory can be copied and replaced in the project. The copy must then be updated depending: + * on board RF switch configuration (pin control, number of port etc) + * on TCXO configuration + * on DC/DC configuration + * on maximum output power that the board can deliver*/ + return BSP_RADIO_Init(); + 800bf34: f7f5 fb76 bl 8001624 + 800bf38: 4603 mov r3, r0 + /* USER CODE BEGIN RBI_Init_2 */ +#warning user to provide its board code or to call his board driver functions + /* USER CODE END RBI_Init_2 */ + return retcode; +#endif /* USE_BSP_DRIVER */ +} + 800bf3a: 4618 mov r0, r3 + 800bf3c: bd80 pop {r7, pc} + +0800bf3e : + return retcode; +#endif /* USE_BSP_DRIVER */ +} + +int32_t RBI_ConfigRFSwitch(RBI_Switch_TypeDef Config) +{ + 800bf3e: b580 push {r7, lr} + 800bf40: b082 sub sp, #8 + 800bf42: af00 add r7, sp, #0 + 800bf44: 4603 mov r3, r0 + 800bf46: 71fb strb r3, [r7, #7] + * 1/ For User boards, the BSP/STM32WLxx_Nucleo/ directory can be copied and replaced in the project. The copy must then be updated depending: + * on board RF switch configuration (pin control, number of port etc) + * on TCXO configuration + * on DC/DC configuration + * on maximum output power that the board can deliver*/ + return BSP_RADIO_ConfigRFSwitch((BSP_RADIO_Switch_TypeDef) Config); + 800bf48: 79fb ldrb r3, [r7, #7] + 800bf4a: 4618 mov r0, r3 + 800bf4c: f7f5 fba8 bl 80016a0 + 800bf50: 4603 mov r3, r0 + /* USER CODE BEGIN RBI_ConfigRFSwitch_2 */ +#warning user to provide its board code or to call his board driver functions + /* USER CODE END RBI_ConfigRFSwitch_2 */ + return retcode; +#endif /* USE_BSP_DRIVER */ +} + 800bf52: 4618 mov r0, r3 + 800bf54: 3708 adds r7, #8 + 800bf56: 46bd mov sp, r7 + 800bf58: bd80 pop {r7, pc} + +0800bf5a : + +int32_t RBI_GetTxConfig(void) +{ + 800bf5a: b580 push {r7, lr} + 800bf5c: af00 add r7, sp, #0 + * 1/ For User boards, the BSP/STM32WLxx_Nucleo/ directory can be copied and replaced in the project. The copy must then be updated depending: + * on board RF switch configuration (pin control, number of port etc) + * on TCXO configuration + * on DC/DC configuration + * on maximum output power that the board can deliver*/ + return BSP_RADIO_GetTxConfig(); + 800bf5e: f7f5 fbfb bl 8001758 + 800bf62: 4603 mov r3, r0 + /* USER CODE BEGIN RBI_GetTxConfig_2 */ +#warning user to provide its board code or to call his board driver functions + /* USER CODE END RBI_GetTxConfig_2 */ + return retcode; +#endif /* USE_BSP_DRIVER */ +} + 800bf64: 4618 mov r0, r3 + 800bf66: bd80 pop {r7, pc} + +0800bf68 : + +int32_t RBI_IsTCXO(void) +{ + 800bf68: b580 push {r7, lr} + 800bf6a: af00 add r7, sp, #0 + * 1/ For User boards, the BSP/STM32WLxx_Nucleo/ directory can be copied and replaced in the project. The copy must then be updated depending: + * on board RF switch configuration (pin control, number of port etc) + * on TCXO configuration + * on DC/DC configuration + * on maximum output power that the board can deliver*/ + return BSP_RADIO_IsTCXO(); + 800bf6c: f7f5 fbfb bl 8001766 + 800bf70: 4603 mov r3, r0 + /* USER CODE BEGIN RBI_IsTCXO_2 */ +#warning user to provide its board code or to call his board driver functions + /* USER CODE END RBI_IsTCXO_2 */ + return retcode; +#endif /* USE_BSP_DRIVER */ +} + 800bf72: 4618 mov r0, r3 + 800bf74: bd80 pop {r7, pc} + +0800bf76 : + +int32_t RBI_IsDCDC(void) +{ + 800bf76: b580 push {r7, lr} + 800bf78: af00 add r7, sp, #0 + * 1/ For User boards, the BSP/STM32WLxx_Nucleo/ directory can be copied and replaced in the project. The copy must then be updated depending: + * on board RF switch configuration (pin control, number of port etc) + * on TCXO configuration + * on DC/DC configuration + * on maximum output power that the board can deliver*/ + return BSP_RADIO_IsDCDC(); + 800bf7a: f7f5 fbfb bl 8001774 + 800bf7e: 4603 mov r3, r0 + /* USER CODE BEGIN RBI_IsDCDC_2 */ +#warning user to provide its board code or to call his board driver functions + /* USER CODE END RBI_IsDCDC_2 */ + return retcode; +#endif /* USE_BSP_DRIVER */ +} + 800bf80: 4618 mov r0, r3 + 800bf82: bd80 pop {r7, pc} + +0800bf84 : + +int32_t RBI_GetRFOMaxPowerConfig(RBI_RFOMaxPowerConfig_TypeDef Config) +{ + 800bf84: b580 push {r7, lr} + 800bf86: b082 sub sp, #8 + 800bf88: af00 add r7, sp, #0 + 800bf8a: 4603 mov r3, r0 + 800bf8c: 71fb strb r3, [r7, #7] + * 1/ For User boards, the BSP/STM32WLxx_Nucleo/ directory can be copied and replaced in the project. The copy must then be updated depending: + * on board RF switch configuration (pin control, number of port etc) + * on TCXO configuration + * on DC/DC configuration + * on maximum output power that the board can deliver*/ + return BSP_RADIO_GetRFOMaxPowerConfig((BSP_RADIO_RFOMaxPowerConfig_TypeDef) Config); + 800bf8e: 79fb ldrb r3, [r7, #7] + 800bf90: 4618 mov r0, r3 + 800bf92: f7f5 fbf6 bl 8001782 + 800bf96: 4603 mov r3, r0 + ret = 22; /*dBm*/ + } + /* USER CODE END RBI_GetRFOMaxPowerConfig_2 */ + return ret; +#endif /* USE_BSP_DRIVER */ +} + 800bf98: 4618 mov r0, r3 + 800bf9a: 3708 adds r7, #8 + 800bf9c: 46bd mov sp, r7 + 800bf9e: bd80 pop {r7, pc} + +0800bfa0 : + +/** @addtogroup TINY_LPM_Exported_function + * @{ + */ +void UTIL_LPM_Init( void ) +{ + 800bfa0: b480 push {r7} + 800bfa2: af00 add r7, sp, #0 + StopModeDisable = UTIL_LPM_NO_BIT_SET; + 800bfa4: 4b04 ldr r3, [pc, #16] @ (800bfb8 ) + 800bfa6: 2200 movs r2, #0 + 800bfa8: 601a str r2, [r3, #0] + OffModeDisable = UTIL_LPM_NO_BIT_SET; + 800bfaa: 4b04 ldr r3, [pc, #16] @ (800bfbc ) + 800bfac: 2200 movs r2, #0 + 800bfae: 601a str r2, [r3, #0] + UTIL_LPM_INIT_CRITICAL_SECTION( ); +} + 800bfb0: bf00 nop + 800bfb2: 46bd mov sp, r7 + 800bfb4: bc80 pop {r7} + 800bfb6: 4770 bx lr + 800bfb8: 200009a8 .word 0x200009a8 + 800bfbc: 200009ac .word 0x200009ac + +0800bfc0 : +void UTIL_LPM_DeInit( void ) +{ +} + +void UTIL_LPM_SetStopMode( UTIL_LPM_bm_t lpm_id_bm, UTIL_LPM_State_t state ) +{ + 800bfc0: b480 push {r7} + 800bfc2: b087 sub sp, #28 + 800bfc4: af00 add r7, sp, #0 + 800bfc6: 6078 str r0, [r7, #4] + 800bfc8: 460b mov r3, r1 + 800bfca: 70fb strb r3, [r7, #3] + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 800bfcc: f3ef 8310 mrs r3, PRIMASK + 800bfd0: 613b str r3, [r7, #16] + return(result); + 800bfd2: 693b ldr r3, [r7, #16] + UTIL_LPM_ENTER_CRITICAL_SECTION( ); + 800bfd4: 617b str r3, [r7, #20] + __ASM volatile ("cpsid i" : : : "memory"); + 800bfd6: b672 cpsid i +} + 800bfd8: bf00 nop + + switch( state ) + 800bfda: 78fb ldrb r3, [r7, #3] + 800bfdc: 2b00 cmp r3, #0 + 800bfde: d008 beq.n 800bff2 + 800bfe0: 2b01 cmp r3, #1 + 800bfe2: d10e bne.n 800c002 + { + case UTIL_LPM_DISABLE: + { + StopModeDisable |= lpm_id_bm; + 800bfe4: 4b0d ldr r3, [pc, #52] @ (800c01c ) + 800bfe6: 681a ldr r2, [r3, #0] + 800bfe8: 687b ldr r3, [r7, #4] + 800bfea: 4313 orrs r3, r2 + 800bfec: 4a0b ldr r2, [pc, #44] @ (800c01c ) + 800bfee: 6013 str r3, [r2, #0] + break; + 800bff0: e008 b.n 800c004 + } + case UTIL_LPM_ENABLE: + { + StopModeDisable &= ( ~lpm_id_bm ); + 800bff2: 687b ldr r3, [r7, #4] + 800bff4: 43da mvns r2, r3 + 800bff6: 4b09 ldr r3, [pc, #36] @ (800c01c ) + 800bff8: 681b ldr r3, [r3, #0] + 800bffa: 4013 ands r3, r2 + 800bffc: 4a07 ldr r2, [pc, #28] @ (800c01c ) + 800bffe: 6013 str r3, [r2, #0] + break; + 800c000: e000 b.n 800c004 + } + default : + { + break; + 800c002: bf00 nop + 800c004: 697b ldr r3, [r7, #20] + 800c006: 60fb str r3, [r7, #12] + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 800c008: 68fb ldr r3, [r7, #12] + 800c00a: f383 8810 msr PRIMASK, r3 +} + 800c00e: bf00 nop + } + } + + UTIL_LPM_EXIT_CRITICAL_SECTION( ); +} + 800c010: bf00 nop + 800c012: 371c adds r7, #28 + 800c014: 46bd mov sp, r7 + 800c016: bc80 pop {r7} + 800c018: 4770 bx lr + 800c01a: bf00 nop + 800c01c: 200009a8 .word 0x200009a8 + +0800c020 : + +void UTIL_LPM_SetOffMode( UTIL_LPM_bm_t lpm_id_bm, UTIL_LPM_State_t state ) +{ + 800c020: b480 push {r7} + 800c022: b087 sub sp, #28 + 800c024: af00 add r7, sp, #0 + 800c026: 6078 str r0, [r7, #4] + 800c028: 460b mov r3, r1 + 800c02a: 70fb strb r3, [r7, #3] + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 800c02c: f3ef 8310 mrs r3, PRIMASK + 800c030: 613b str r3, [r7, #16] + return(result); + 800c032: 693b ldr r3, [r7, #16] + UTIL_LPM_ENTER_CRITICAL_SECTION( ); + 800c034: 617b str r3, [r7, #20] + __ASM volatile ("cpsid i" : : : "memory"); + 800c036: b672 cpsid i +} + 800c038: bf00 nop + + switch(state) + 800c03a: 78fb ldrb r3, [r7, #3] + 800c03c: 2b00 cmp r3, #0 + 800c03e: d008 beq.n 800c052 + 800c040: 2b01 cmp r3, #1 + 800c042: d10e bne.n 800c062 + { + case UTIL_LPM_DISABLE: + { + OffModeDisable |= lpm_id_bm; + 800c044: 4b0d ldr r3, [pc, #52] @ (800c07c ) + 800c046: 681a ldr r2, [r3, #0] + 800c048: 687b ldr r3, [r7, #4] + 800c04a: 4313 orrs r3, r2 + 800c04c: 4a0b ldr r2, [pc, #44] @ (800c07c ) + 800c04e: 6013 str r3, [r2, #0] + break; + 800c050: e008 b.n 800c064 + } + case UTIL_LPM_ENABLE: + { + OffModeDisable &= ( ~lpm_id_bm ); + 800c052: 687b ldr r3, [r7, #4] + 800c054: 43da mvns r2, r3 + 800c056: 4b09 ldr r3, [pc, #36] @ (800c07c ) + 800c058: 681b ldr r3, [r3, #0] + 800c05a: 4013 ands r3, r2 + 800c05c: 4a07 ldr r2, [pc, #28] @ (800c07c ) + 800c05e: 6013 str r3, [r2, #0] + break; + 800c060: e000 b.n 800c064 + } + default : + { + break; + 800c062: bf00 nop + 800c064: 697b ldr r3, [r7, #20] + 800c066: 60fb str r3, [r7, #12] + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 800c068: 68fb ldr r3, [r7, #12] + 800c06a: f383 8810 msr PRIMASK, r3 +} + 800c06e: bf00 nop + } + } + + UTIL_LPM_EXIT_CRITICAL_SECTION( ); +} + 800c070: bf00 nop + 800c072: 371c adds r7, #28 + 800c074: 46bd mov sp, r7 + 800c076: bc80 pop {r7} + 800c078: 4770 bx lr + 800c07a: bf00 nop + 800c07c: 200009ac .word 0x200009ac + +0800c080 : + + return mode_selected; +} + +void UTIL_LPM_EnterLowPower( void ) +{ + 800c080: b580 push {r7, lr} + 800c082: b084 sub sp, #16 + 800c084: af00 add r7, sp, #0 + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 800c086: f3ef 8310 mrs r3, PRIMASK + 800c08a: 60bb str r3, [r7, #8] + return(result); + 800c08c: 68bb ldr r3, [r7, #8] + UTIL_LPM_ENTER_CRITICAL_SECTION_ELP( ); + 800c08e: 60fb str r3, [r7, #12] + __ASM volatile ("cpsid i" : : : "memory"); + 800c090: b672 cpsid i +} + 800c092: bf00 nop + + if( StopModeDisable != UTIL_LPM_NO_BIT_SET ) + 800c094: 4b12 ldr r3, [pc, #72] @ (800c0e0 ) + 800c096: 681b ldr r3, [r3, #0] + 800c098: 2b00 cmp r3, #0 + 800c09a: d006 beq.n 800c0aa + { + /** + * At least one user disallows Stop Mode + * SLEEP mode is required + */ + UTIL_PowerDriver.EnterSleepMode( ); + 800c09c: 4b11 ldr r3, [pc, #68] @ (800c0e4 ) + 800c09e: 681b ldr r3, [r3, #0] + 800c0a0: 4798 blx r3 + UTIL_PowerDriver.ExitSleepMode( ); + 800c0a2: 4b10 ldr r3, [pc, #64] @ (800c0e4 ) + 800c0a4: 685b ldr r3, [r3, #4] + 800c0a6: 4798 blx r3 + 800c0a8: e010 b.n 800c0cc + } + else + { + if( OffModeDisable != UTIL_LPM_NO_BIT_SET ) + 800c0aa: 4b0f ldr r3, [pc, #60] @ (800c0e8 ) + 800c0ac: 681b ldr r3, [r3, #0] + 800c0ae: 2b00 cmp r3, #0 + 800c0b0: d006 beq.n 800c0c0 + { + /** + * At least one user disallows Off Mode + * STOP mode is required + */ + UTIL_PowerDriver.EnterStopMode( ); + 800c0b2: 4b0c ldr r3, [pc, #48] @ (800c0e4 ) + 800c0b4: 689b ldr r3, [r3, #8] + 800c0b6: 4798 blx r3 + UTIL_PowerDriver.ExitStopMode( ); + 800c0b8: 4b0a ldr r3, [pc, #40] @ (800c0e4 ) + 800c0ba: 68db ldr r3, [r3, #12] + 800c0bc: 4798 blx r3 + 800c0be: e005 b.n 800c0cc + else + { + /** + * OFF mode is required + */ + UTIL_PowerDriver.EnterOffMode( ); + 800c0c0: 4b08 ldr r3, [pc, #32] @ (800c0e4 ) + 800c0c2: 691b ldr r3, [r3, #16] + 800c0c4: 4798 blx r3 + UTIL_PowerDriver.ExitOffMode( ); + 800c0c6: 4b07 ldr r3, [pc, #28] @ (800c0e4 ) + 800c0c8: 695b ldr r3, [r3, #20] + 800c0ca: 4798 blx r3 + 800c0cc: 68fb ldr r3, [r7, #12] + 800c0ce: 607b str r3, [r7, #4] + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 800c0d0: 687b ldr r3, [r7, #4] + 800c0d2: f383 8810 msr PRIMASK, r3 +} + 800c0d6: bf00 nop + } + } + + UTIL_LPM_EXIT_CRITICAL_SECTION_ELP( ); +} + 800c0d8: bf00 nop + 800c0da: 3710 adds r7, #16 + 800c0dc: 46bd mov sp, r7 + 800c0de: bd80 pop {r7, pc} + 800c0e0: 200009a8 .word 0x200009a8 + 800c0e4: 0800d8b0 .word 0x0800d8b0 + 800c0e8: 200009ac .word 0x200009ac + +0800c0ec : +/* Global variables ----------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Functions Definition ------------------------------------------------------*/ + +void UTIL_MEM_cpy_8( void *dst, const void *src, uint16_t size ) +{ + 800c0ec: b480 push {r7} + 800c0ee: b087 sub sp, #28 + 800c0f0: af00 add r7, sp, #0 + 800c0f2: 60f8 str r0, [r7, #12] + 800c0f4: 60b9 str r1, [r7, #8] + 800c0f6: 4613 mov r3, r2 + 800c0f8: 80fb strh r3, [r7, #6] + uint8_t* dst8= (uint8_t *) dst; + 800c0fa: 68fb ldr r3, [r7, #12] + 800c0fc: 617b str r3, [r7, #20] + uint8_t* src8= (uint8_t *) src; + 800c0fe: 68bb ldr r3, [r7, #8] + 800c100: 613b str r3, [r7, #16] + + while( size-- ) + 800c102: e007 b.n 800c114 + { + *dst8++ = *src8++; + 800c104: 693a ldr r2, [r7, #16] + 800c106: 1c53 adds r3, r2, #1 + 800c108: 613b str r3, [r7, #16] + 800c10a: 697b ldr r3, [r7, #20] + 800c10c: 1c59 adds r1, r3, #1 + 800c10e: 6179 str r1, [r7, #20] + 800c110: 7812 ldrb r2, [r2, #0] + 800c112: 701a strb r2, [r3, #0] + while( size-- ) + 800c114: 88fb ldrh r3, [r7, #6] + 800c116: 1e5a subs r2, r3, #1 + 800c118: 80fa strh r2, [r7, #6] + 800c11a: 2b00 cmp r3, #0 + 800c11c: d1f2 bne.n 800c104 + } +} + 800c11e: bf00 nop + 800c120: bf00 nop + 800c122: 371c adds r7, #28 + 800c124: 46bd mov sp, r7 + 800c126: bc80 pop {r7} + 800c128: 4770 bx lr + +0800c12a : + *dst8-- = *src8++; + } +} + +void UTIL_MEM_set_8( void *dst, uint8_t value, uint16_t size ) +{ + 800c12a: b480 push {r7} + 800c12c: b085 sub sp, #20 + 800c12e: af00 add r7, sp, #0 + 800c130: 6078 str r0, [r7, #4] + 800c132: 460b mov r3, r1 + 800c134: 70fb strb r3, [r7, #3] + 800c136: 4613 mov r3, r2 + 800c138: 803b strh r3, [r7, #0] + uint8_t* dst8= (uint8_t *) dst; + 800c13a: 687b ldr r3, [r7, #4] + 800c13c: 60fb str r3, [r7, #12] + while( size-- ) + 800c13e: e004 b.n 800c14a + { + *dst8++ = value; + 800c140: 68fb ldr r3, [r7, #12] + 800c142: 1c5a adds r2, r3, #1 + 800c144: 60fa str r2, [r7, #12] + 800c146: 78fa ldrb r2, [r7, #3] + 800c148: 701a strb r2, [r3, #0] + while( size-- ) + 800c14a: 883b ldrh r3, [r7, #0] + 800c14c: 1e5a subs r2, r3, #1 + 800c14e: 803a strh r2, [r7, #0] + 800c150: 2b00 cmp r3, #0 + 800c152: d1f5 bne.n 800c140 + } +} + 800c154: bf00 nop + 800c156: bf00 nop + 800c158: 3714 adds r7, #20 + 800c15a: 46bd mov sp, r7 + 800c15c: bc80 pop {r7} + 800c15e: 4770 bx lr + +0800c160 : + * @addtogroup SYSTIME_exported_function + * @{ + */ + +SysTime_t SysTimeAdd( SysTime_t a, SysTime_t b ) +{ + 800c160: b082 sub sp, #8 + 800c162: b480 push {r7} + 800c164: b087 sub sp, #28 + 800c166: af00 add r7, sp, #0 + 800c168: 60f8 str r0, [r7, #12] + 800c16a: 1d38 adds r0, r7, #4 + 800c16c: e880 0006 stmia.w r0, {r1, r2} + 800c170: 627b str r3, [r7, #36] @ 0x24 + SysTime_t c = { .Seconds = 0, .SubSeconds = 0 }; + 800c172: 2300 movs r3, #0 + 800c174: 613b str r3, [r7, #16] + 800c176: 2300 movs r3, #0 + 800c178: 82bb strh r3, [r7, #20] + + c.Seconds = a.Seconds + b.Seconds; + 800c17a: 687a ldr r2, [r7, #4] + 800c17c: 6a7b ldr r3, [r7, #36] @ 0x24 + 800c17e: 4413 add r3, r2 + 800c180: 613b str r3, [r7, #16] + c.SubSeconds = a.SubSeconds + b.SubSeconds; + 800c182: f9b7 3008 ldrsh.w r3, [r7, #8] + 800c186: b29a uxth r2, r3 + 800c188: f9b7 3028 ldrsh.w r3, [r7, #40] @ 0x28 + 800c18c: b29b uxth r3, r3 + 800c18e: 4413 add r3, r2 + 800c190: b29b uxth r3, r3 + 800c192: b21b sxth r3, r3 + 800c194: 82bb strh r3, [r7, #20] + if( c.SubSeconds >= 1000 ) + 800c196: f9b7 3014 ldrsh.w r3, [r7, #20] + 800c19a: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 + 800c19e: db0a blt.n 800c1b6 + { + c.Seconds++; + 800c1a0: 693b ldr r3, [r7, #16] + 800c1a2: 3301 adds r3, #1 + 800c1a4: 613b str r3, [r7, #16] + c.SubSeconds -= 1000; + 800c1a6: f9b7 3014 ldrsh.w r3, [r7, #20] + 800c1aa: b29b uxth r3, r3 + 800c1ac: f5a3 737a sub.w r3, r3, #1000 @ 0x3e8 + 800c1b0: b29b uxth r3, r3 + 800c1b2: b21b sxth r3, r3 + 800c1b4: 82bb strh r3, [r7, #20] + } + return c; + 800c1b6: 68fb ldr r3, [r7, #12] + 800c1b8: 461a mov r2, r3 + 800c1ba: f107 0310 add.w r3, r7, #16 + 800c1be: e893 0003 ldmia.w r3, {r0, r1} + 800c1c2: e882 0003 stmia.w r2, {r0, r1} +} + 800c1c6: 68f8 ldr r0, [r7, #12] + 800c1c8: 371c adds r7, #28 + 800c1ca: 46bd mov sp, r7 + 800c1cc: bc80 pop {r7} + 800c1ce: b002 add sp, #8 + 800c1d0: 4770 bx lr + ... + +0800c1d4 : + UTIL_SYSTIMDriver.BKUPWrite_Seconds( DeltaTime.Seconds ); + UTIL_SYSTIMDriver.BKUPWrite_SubSeconds( ( uint32_t ) DeltaTime.SubSeconds ); +} + +SysTime_t SysTimeGet( void ) +{ + 800c1d4: b580 push {r7, lr} + 800c1d6: b08a sub sp, #40 @ 0x28 + 800c1d8: af02 add r7, sp, #8 + 800c1da: 6078 str r0, [r7, #4] + SysTime_t calendarTime = { .Seconds = 0, .SubSeconds = 0 }; + 800c1dc: 2300 movs r3, #0 + 800c1de: 61bb str r3, [r7, #24] + 800c1e0: 2300 movs r3, #0 + 800c1e2: 83bb strh r3, [r7, #28] + SysTime_t sysTime = { .Seconds = 0, .SubSeconds = 0 }; + 800c1e4: 2300 movs r3, #0 + 800c1e6: 613b str r3, [r7, #16] + 800c1e8: 2300 movs r3, #0 + 800c1ea: 82bb strh r3, [r7, #20] + SysTime_t DeltaTime; + + calendarTime.Seconds = UTIL_SYSTIMDriver.GetCalendarTime( ( uint16_t* )&calendarTime.SubSeconds ); + 800c1ec: 4b14 ldr r3, [pc, #80] @ (800c240 ) + 800c1ee: 691b ldr r3, [r3, #16] + 800c1f0: f107 0218 add.w r2, r7, #24 + 800c1f4: 3204 adds r2, #4 + 800c1f6: 4610 mov r0, r2 + 800c1f8: 4798 blx r3 + 800c1fa: 4603 mov r3, r0 + 800c1fc: 61bb str r3, [r7, #24] + + DeltaTime.SubSeconds = (int16_t)UTIL_SYSTIMDriver.BKUPRead_SubSeconds(); + 800c1fe: 4b10 ldr r3, [pc, #64] @ (800c240 ) + 800c200: 68db ldr r3, [r3, #12] + 800c202: 4798 blx r3 + 800c204: 4603 mov r3, r0 + 800c206: b21b sxth r3, r3 + 800c208: 81bb strh r3, [r7, #12] + DeltaTime.Seconds = UTIL_SYSTIMDriver.BKUPRead_Seconds(); + 800c20a: 4b0d ldr r3, [pc, #52] @ (800c240 ) + 800c20c: 685b ldr r3, [r3, #4] + 800c20e: 4798 blx r3 + 800c210: 4603 mov r3, r0 + 800c212: 60bb str r3, [r7, #8] + + sysTime = SysTimeAdd( DeltaTime, calendarTime ); + 800c214: f107 0010 add.w r0, r7, #16 + 800c218: 69fb ldr r3, [r7, #28] + 800c21a: 9300 str r3, [sp, #0] + 800c21c: 69bb ldr r3, [r7, #24] + 800c21e: f107 0208 add.w r2, r7, #8 + 800c222: ca06 ldmia r2, {r1, r2} + 800c224: f7ff ff9c bl 800c160 + + return sysTime; + 800c228: 687b ldr r3, [r7, #4] + 800c22a: 461a mov r2, r3 + 800c22c: f107 0310 add.w r3, r7, #16 + 800c230: e893 0003 ldmia.w r3, {r0, r1} + 800c234: e882 0003 stmia.w r2, {r0, r1} +} + 800c238: 6878 ldr r0, [r7, #4] + 800c23a: 3720 adds r7, #32 + 800c23c: 46bd mov sp, r7 + 800c23e: bd80 pop {r7, pc} + 800c240: 0800d994 .word 0x0800d994 + +0800c244 : + return sc - s; +} +#endif + +static int ee_skip_atoi(const char **s) +{ + 800c244: b480 push {r7} + 800c246: b085 sub sp, #20 + 800c248: af00 add r7, sp, #0 + 800c24a: 6078 str r0, [r7, #4] + int i = 0; + 800c24c: 2300 movs r3, #0 + 800c24e: 60fb str r3, [r7, #12] + while (is_digit(**s)) i = i*10 + *((*s)++) - '0'; + 800c250: e00e b.n 800c270 + 800c252: 68fa ldr r2, [r7, #12] + 800c254: 4613 mov r3, r2 + 800c256: 009b lsls r3, r3, #2 + 800c258: 4413 add r3, r2 + 800c25a: 005b lsls r3, r3, #1 + 800c25c: 4618 mov r0, r3 + 800c25e: 687b ldr r3, [r7, #4] + 800c260: 681b ldr r3, [r3, #0] + 800c262: 1c59 adds r1, r3, #1 + 800c264: 687a ldr r2, [r7, #4] + 800c266: 6011 str r1, [r2, #0] + 800c268: 781b ldrb r3, [r3, #0] + 800c26a: 4403 add r3, r0 + 800c26c: 3b30 subs r3, #48 @ 0x30 + 800c26e: 60fb str r3, [r7, #12] + 800c270: 687b ldr r3, [r7, #4] + 800c272: 681b ldr r3, [r3, #0] + 800c274: 781b ldrb r3, [r3, #0] + 800c276: 2b2f cmp r3, #47 @ 0x2f + 800c278: d904 bls.n 800c284 + 800c27a: 687b ldr r3, [r7, #4] + 800c27c: 681b ldr r3, [r3, #0] + 800c27e: 781b ldrb r3, [r3, #0] + 800c280: 2b39 cmp r3, #57 @ 0x39 + 800c282: d9e6 bls.n 800c252 + return i; + 800c284: 68fb ldr r3, [r7, #12] +} + 800c286: 4618 mov r0, r3 + 800c288: 3714 adds r7, #20 + 800c28a: 46bd mov sp, r7 + 800c28c: bc80 pop {r7} + 800c28e: 4770 bx lr + +0800c290 : + +#define ASSIGN_STR(_c) do { *str++ = (_c); max_size--; if (max_size == 0) return str; } while (0) + +static char *ee_number(char *str, int max_size, long num, int base, int size, int precision, int type) +{ + 800c290: b480 push {r7} + 800c292: b099 sub sp, #100 @ 0x64 + 800c294: af00 add r7, sp, #0 + 800c296: 60f8 str r0, [r7, #12] + 800c298: 60b9 str r1, [r7, #8] + 800c29a: 607a str r2, [r7, #4] + 800c29c: 603b str r3, [r7, #0] + char c; + char sign, tmp[66]; + char *dig = lower_digits; + 800c29e: 4b71 ldr r3, [pc, #452] @ (800c464 ) + 800c2a0: 681b ldr r3, [r3, #0] + 800c2a2: 65bb str r3, [r7, #88] @ 0x58 + int i; + + if (type & UPPERCASE) dig = upper_digits; + 800c2a4: 6f3b ldr r3, [r7, #112] @ 0x70 + 800c2a6: f003 0340 and.w r3, r3, #64 @ 0x40 + 800c2aa: 2b00 cmp r3, #0 + 800c2ac: d002 beq.n 800c2b4 + 800c2ae: 4b6e ldr r3, [pc, #440] @ (800c468 ) + 800c2b0: 681b ldr r3, [r3, #0] + 800c2b2: 65bb str r3, [r7, #88] @ 0x58 +#ifdef TINY_PRINTF +#else + if (type & LEFT) type &= ~ZEROPAD; +#endif + if (base < 2 || base > 36) return 0; + 800c2b4: 683b ldr r3, [r7, #0] + 800c2b6: 2b01 cmp r3, #1 + 800c2b8: dd02 ble.n 800c2c0 + 800c2ba: 683b ldr r3, [r7, #0] + 800c2bc: 2b24 cmp r3, #36 @ 0x24 + 800c2be: dd01 ble.n 800c2c4 + 800c2c0: 2300 movs r3, #0 + 800c2c2: e0ca b.n 800c45a + + c = (type & ZEROPAD) ? '0' : ' '; + 800c2c4: 6f3b ldr r3, [r7, #112] @ 0x70 + 800c2c6: f003 0301 and.w r3, r3, #1 + 800c2ca: 2b00 cmp r3, #0 + 800c2cc: d001 beq.n 800c2d2 + 800c2ce: 2330 movs r3, #48 @ 0x30 + 800c2d0: e000 b.n 800c2d4 + 800c2d2: 2320 movs r3, #32 + 800c2d4: f887 3053 strb.w r3, [r7, #83] @ 0x53 + sign = 0; + 800c2d8: 2300 movs r3, #0 + 800c2da: f887 305f strb.w r3, [r7, #95] @ 0x5f + if (type & SIGN) + 800c2de: 6f3b ldr r3, [r7, #112] @ 0x70 + 800c2e0: f003 0302 and.w r3, r3, #2 + 800c2e4: 2b00 cmp r3, #0 + 800c2e6: d00b beq.n 800c300 + { + if (num < 0) + 800c2e8: 687b ldr r3, [r7, #4] + 800c2ea: 2b00 cmp r3, #0 + 800c2ec: da08 bge.n 800c300 + { + sign = '-'; + 800c2ee: 232d movs r3, #45 @ 0x2d + 800c2f0: f887 305f strb.w r3, [r7, #95] @ 0x5f + num = -num; + 800c2f4: 687b ldr r3, [r7, #4] + 800c2f6: 425b negs r3, r3 + 800c2f8: 607b str r3, [r7, #4] + size--; + 800c2fa: 6ebb ldr r3, [r7, #104] @ 0x68 + 800c2fc: 3b01 subs r3, #1 + 800c2fe: 66bb str r3, [r7, #104] @ 0x68 + else if (base == 8) + size--; + } +#endif + + i = 0; + 800c300: 2300 movs r3, #0 + 800c302: 657b str r3, [r7, #84] @ 0x54 + + if (num == 0) + 800c304: 687b ldr r3, [r7, #4] + 800c306: 2b00 cmp r3, #0 + 800c308: d11e bne.n 800c348 + tmp[i++] = '0'; + 800c30a: 6d7b ldr r3, [r7, #84] @ 0x54 + 800c30c: 1c5a adds r2, r3, #1 + 800c30e: 657a str r2, [r7, #84] @ 0x54 + 800c310: 3360 adds r3, #96 @ 0x60 + 800c312: 443b add r3, r7 + 800c314: 2230 movs r2, #48 @ 0x30 + 800c316: f803 2c50 strb.w r2, [r3, #-80] + 800c31a: e018 b.n 800c34e + else + { + while (num != 0) + { + tmp[i++] = dig[((unsigned long) num) % (unsigned) base]; + 800c31c: 687b ldr r3, [r7, #4] + 800c31e: 683a ldr r2, [r7, #0] + 800c320: fbb3 f1f2 udiv r1, r3, r2 + 800c324: fb01 f202 mul.w r2, r1, r2 + 800c328: 1a9b subs r3, r3, r2 + 800c32a: 6dba ldr r2, [r7, #88] @ 0x58 + 800c32c: 441a add r2, r3 + 800c32e: 6d7b ldr r3, [r7, #84] @ 0x54 + 800c330: 1c59 adds r1, r3, #1 + 800c332: 6579 str r1, [r7, #84] @ 0x54 + 800c334: 7812 ldrb r2, [r2, #0] + 800c336: 3360 adds r3, #96 @ 0x60 + 800c338: 443b add r3, r7 + 800c33a: f803 2c50 strb.w r2, [r3, #-80] + num = ((unsigned long) num) / (unsigned) base; + 800c33e: 687a ldr r2, [r7, #4] + 800c340: 683b ldr r3, [r7, #0] + 800c342: fbb2 f3f3 udiv r3, r2, r3 + 800c346: 607b str r3, [r7, #4] + while (num != 0) + 800c348: 687b ldr r3, [r7, #4] + 800c34a: 2b00 cmp r3, #0 + 800c34c: d1e6 bne.n 800c31c + } + } + + if (i > precision) precision = i; + 800c34e: 6d7a ldr r2, [r7, #84] @ 0x54 + 800c350: 6efb ldr r3, [r7, #108] @ 0x6c + 800c352: 429a cmp r2, r3 + 800c354: dd01 ble.n 800c35a + 800c356: 6d7b ldr r3, [r7, #84] @ 0x54 + 800c358: 66fb str r3, [r7, #108] @ 0x6c + size -= precision; + 800c35a: 6eba ldr r2, [r7, #104] @ 0x68 + 800c35c: 6efb ldr r3, [r7, #108] @ 0x6c + 800c35e: 1ad3 subs r3, r2, r3 + 800c360: 66bb str r3, [r7, #104] @ 0x68 + if (!(type & (ZEROPAD /* TINY option | LEFT */))) while (size-- > 0) ASSIGN_STR(' '); + 800c362: 6f3b ldr r3, [r7, #112] @ 0x70 + 800c364: f003 0301 and.w r3, r3, #1 + 800c368: 2b00 cmp r3, #0 + 800c36a: d112 bne.n 800c392 + 800c36c: e00c b.n 800c388 + 800c36e: 68fb ldr r3, [r7, #12] + 800c370: 1c5a adds r2, r3, #1 + 800c372: 60fa str r2, [r7, #12] + 800c374: 2220 movs r2, #32 + 800c376: 701a strb r2, [r3, #0] + 800c378: 68bb ldr r3, [r7, #8] + 800c37a: 3b01 subs r3, #1 + 800c37c: 60bb str r3, [r7, #8] + 800c37e: 68bb ldr r3, [r7, #8] + 800c380: 2b00 cmp r3, #0 + 800c382: d101 bne.n 800c388 + 800c384: 68fb ldr r3, [r7, #12] + 800c386: e068 b.n 800c45a + 800c388: 6ebb ldr r3, [r7, #104] @ 0x68 + 800c38a: 1e5a subs r2, r3, #1 + 800c38c: 66ba str r2, [r7, #104] @ 0x68 + 800c38e: 2b00 cmp r3, #0 + 800c390: dced bgt.n 800c36e + if (sign) ASSIGN_STR(sign); + 800c392: f897 305f ldrb.w r3, [r7, #95] @ 0x5f + 800c396: 2b00 cmp r3, #0 + 800c398: d01b beq.n 800c3d2 + 800c39a: 68fb ldr r3, [r7, #12] + 800c39c: 1c5a adds r2, r3, #1 + 800c39e: 60fa str r2, [r7, #12] + 800c3a0: f897 205f ldrb.w r2, [r7, #95] @ 0x5f + 800c3a4: 701a strb r2, [r3, #0] + 800c3a6: 68bb ldr r3, [r7, #8] + 800c3a8: 3b01 subs r3, #1 + 800c3aa: 60bb str r3, [r7, #8] + 800c3ac: 68bb ldr r3, [r7, #8] + 800c3ae: 2b00 cmp r3, #0 + 800c3b0: d10f bne.n 800c3d2 + 800c3b2: 68fb ldr r3, [r7, #12] + 800c3b4: e051 b.n 800c45a + } + } +#endif + +#ifdef TINY_PRINTF + while (size-- > 0) ASSIGN_STR(c); + 800c3b6: 68fb ldr r3, [r7, #12] + 800c3b8: 1c5a adds r2, r3, #1 + 800c3ba: 60fa str r2, [r7, #12] + 800c3bc: f897 2053 ldrb.w r2, [r7, #83] @ 0x53 + 800c3c0: 701a strb r2, [r3, #0] + 800c3c2: 68bb ldr r3, [r7, #8] + 800c3c4: 3b01 subs r3, #1 + 800c3c6: 60bb str r3, [r7, #8] + 800c3c8: 68bb ldr r3, [r7, #8] + 800c3ca: 2b00 cmp r3, #0 + 800c3cc: d101 bne.n 800c3d2 + 800c3ce: 68fb ldr r3, [r7, #12] + 800c3d0: e043 b.n 800c45a + 800c3d2: 6ebb ldr r3, [r7, #104] @ 0x68 + 800c3d4: 1e5a subs r2, r3, #1 + 800c3d6: 66ba str r2, [r7, #104] @ 0x68 + 800c3d8: 2b00 cmp r3, #0 + 800c3da: dcec bgt.n 800c3b6 +#else + if (!(type & LEFT)) while (size-- > 0) ASSIGN_STR(c); +#endif + while (i < precision--) ASSIGN_STR('0'); + 800c3dc: e00c b.n 800c3f8 + 800c3de: 68fb ldr r3, [r7, #12] + 800c3e0: 1c5a adds r2, r3, #1 + 800c3e2: 60fa str r2, [r7, #12] + 800c3e4: 2230 movs r2, #48 @ 0x30 + 800c3e6: 701a strb r2, [r3, #0] + 800c3e8: 68bb ldr r3, [r7, #8] + 800c3ea: 3b01 subs r3, #1 + 800c3ec: 60bb str r3, [r7, #8] + 800c3ee: 68bb ldr r3, [r7, #8] + 800c3f0: 2b00 cmp r3, #0 + 800c3f2: d101 bne.n 800c3f8 + 800c3f4: 68fb ldr r3, [r7, #12] + 800c3f6: e030 b.n 800c45a + 800c3f8: 6efb ldr r3, [r7, #108] @ 0x6c + 800c3fa: 1e5a subs r2, r3, #1 + 800c3fc: 66fa str r2, [r7, #108] @ 0x6c + 800c3fe: 6d7a ldr r2, [r7, #84] @ 0x54 + 800c400: 429a cmp r2, r3 + 800c402: dbec blt.n 800c3de + while (i-- > 0) ASSIGN_STR(tmp[i]); + 800c404: e010 b.n 800c428 + 800c406: 68fb ldr r3, [r7, #12] + 800c408: 1c5a adds r2, r3, #1 + 800c40a: 60fa str r2, [r7, #12] + 800c40c: f107 0110 add.w r1, r7, #16 + 800c410: 6d7a ldr r2, [r7, #84] @ 0x54 + 800c412: 440a add r2, r1 + 800c414: 7812 ldrb r2, [r2, #0] + 800c416: 701a strb r2, [r3, #0] + 800c418: 68bb ldr r3, [r7, #8] + 800c41a: 3b01 subs r3, #1 + 800c41c: 60bb str r3, [r7, #8] + 800c41e: 68bb ldr r3, [r7, #8] + 800c420: 2b00 cmp r3, #0 + 800c422: d101 bne.n 800c428 + 800c424: 68fb ldr r3, [r7, #12] + 800c426: e018 b.n 800c45a + 800c428: 6d7b ldr r3, [r7, #84] @ 0x54 + 800c42a: 1e5a subs r2, r3, #1 + 800c42c: 657a str r2, [r7, #84] @ 0x54 + 800c42e: 2b00 cmp r3, #0 + 800c430: dce9 bgt.n 800c406 + while (size-- > 0) ASSIGN_STR(' '); + 800c432: e00c b.n 800c44e + 800c434: 68fb ldr r3, [r7, #12] + 800c436: 1c5a adds r2, r3, #1 + 800c438: 60fa str r2, [r7, #12] + 800c43a: 2220 movs r2, #32 + 800c43c: 701a strb r2, [r3, #0] + 800c43e: 68bb ldr r3, [r7, #8] + 800c440: 3b01 subs r3, #1 + 800c442: 60bb str r3, [r7, #8] + 800c444: 68bb ldr r3, [r7, #8] + 800c446: 2b00 cmp r3, #0 + 800c448: d101 bne.n 800c44e + 800c44a: 68fb ldr r3, [r7, #12] + 800c44c: e005 b.n 800c45a + 800c44e: 6ebb ldr r3, [r7, #104] @ 0x68 + 800c450: 1e5a subs r2, r3, #1 + 800c452: 66ba str r2, [r7, #104] @ 0x68 + 800c454: 2b00 cmp r3, #0 + 800c456: dced bgt.n 800c434 + + return str; + 800c458: 68fb ldr r3, [r7, #12] +} + 800c45a: 4618 mov r0, r3 + 800c45c: 3764 adds r7, #100 @ 0x64 + 800c45e: 46bd mov sp, r7 + 800c460: bc80 pop {r7} + 800c462: 4770 bx lr + 800c464: 20000014 .word 0x20000014 + 800c468: 20000018 .word 0x20000018 + +0800c46c : + +#define CHECK_STR_SIZE(_buf, _str, _size) \ + if ((((_str) - (_buf)) >= ((_size)-1))) { break; } + +int tiny_vsnprintf_like(char *buf, const int size, const char *fmt, va_list args) +{ + 800c46c: b580 push {r7, lr} + 800c46e: b092 sub sp, #72 @ 0x48 + 800c470: af04 add r7, sp, #16 + 800c472: 60f8 str r0, [r7, #12] + 800c474: 60b9 str r1, [r7, #8] + 800c476: 607a str r2, [r7, #4] + 800c478: 603b str r3, [r7, #0] + + int field_width; // Width of output field + int precision; // Min. # of digits for integers; max number of chars for from string + int qualifier; // 'h', 'l', or 'L' for integer fields + + if (size <= 0) + 800c47a: 68bb ldr r3, [r7, #8] + 800c47c: 2b00 cmp r3, #0 + 800c47e: dc01 bgt.n 800c484 + { + return 0; + 800c480: 2300 movs r3, #0 + 800c482: e13e b.n 800c702 + } + + for (str = buf; *fmt || ((str - buf) >= size-1); fmt++) + 800c484: 68fb ldr r3, [r7, #12] + 800c486: 62fb str r3, [r7, #44] @ 0x2c + 800c488: e128 b.n 800c6dc + { + CHECK_STR_SIZE(buf, str, size); + 800c48a: 6afa ldr r2, [r7, #44] @ 0x2c + 800c48c: 68fb ldr r3, [r7, #12] + 800c48e: 1ad2 subs r2, r2, r3 + 800c490: 68bb ldr r3, [r7, #8] + 800c492: 3b01 subs r3, #1 + 800c494: 429a cmp r2, r3 + 800c496: f280 812e bge.w 800c6f6 + + if (*fmt != '%') + 800c49a: 687b ldr r3, [r7, #4] + 800c49c: 781b ldrb r3, [r3, #0] + 800c49e: 2b25 cmp r3, #37 @ 0x25 + 800c4a0: d006 beq.n 800c4b0 + { + *str++ = *fmt; + 800c4a2: 687a ldr r2, [r7, #4] + 800c4a4: 6afb ldr r3, [r7, #44] @ 0x2c + 800c4a6: 1c59 adds r1, r3, #1 + 800c4a8: 62f9 str r1, [r7, #44] @ 0x2c + 800c4aa: 7812 ldrb r2, [r2, #0] + 800c4ac: 701a strb r2, [r3, #0] + continue; + 800c4ae: e112 b.n 800c6d6 + } + + // Process flags + flags = 0; + 800c4b0: 2300 movs r3, #0 + 800c4b2: 623b str r3, [r7, #32] +#ifdef TINY_PRINTF + /* Support %0, but not %-, %+, %space and %# */ + fmt++; + 800c4b4: 687b ldr r3, [r7, #4] + 800c4b6: 3301 adds r3, #1 + 800c4b8: 607b str r3, [r7, #4] + if (*fmt == '0') + 800c4ba: 687b ldr r3, [r7, #4] + 800c4bc: 781b ldrb r3, [r3, #0] + 800c4be: 2b30 cmp r3, #48 @ 0x30 + 800c4c0: d103 bne.n 800c4ca + { + flags |= ZEROPAD; + 800c4c2: 6a3b ldr r3, [r7, #32] + 800c4c4: f043 0301 orr.w r3, r3, #1 + 800c4c8: 623b str r3, [r7, #32] + case '0': flags |= ZEROPAD; goto repeat; + } +#endif + + // Get field width + field_width = -1; + 800c4ca: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff + 800c4ce: 61fb str r3, [r7, #28] + if (is_digit(*fmt)) + 800c4d0: 687b ldr r3, [r7, #4] + 800c4d2: 781b ldrb r3, [r3, #0] + 800c4d4: 2b2f cmp r3, #47 @ 0x2f + 800c4d6: d908 bls.n 800c4ea + 800c4d8: 687b ldr r3, [r7, #4] + 800c4da: 781b ldrb r3, [r3, #0] + 800c4dc: 2b39 cmp r3, #57 @ 0x39 + 800c4de: d804 bhi.n 800c4ea + field_width = ee_skip_atoi(&fmt); + 800c4e0: 1d3b adds r3, r7, #4 + 800c4e2: 4618 mov r0, r3 + 800c4e4: f7ff feae bl 800c244 + 800c4e8: 61f8 str r0, [r7, #28] + } + } +#endif + + // Get the precision + precision = -1; + 800c4ea: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff + 800c4ee: 61bb str r3, [r7, #24] + if (precision < 0) precision = 0; + } +#endif + + // Get the conversion qualifier + qualifier = -1; + 800c4f0: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff + 800c4f4: 617b str r3, [r7, #20] + fmt++; + } +#endif + + // Default base + base = 10; + 800c4f6: 230a movs r3, #10 + 800c4f8: 633b str r3, [r7, #48] @ 0x30 + + switch (*fmt) + 800c4fa: 687b ldr r3, [r7, #4] + 800c4fc: 781b ldrb r3, [r3, #0] + 800c4fe: 3b58 subs r3, #88 @ 0x58 + 800c500: 2b20 cmp r3, #32 + 800c502: f200 8094 bhi.w 800c62e + 800c506: a201 add r2, pc, #4 @ (adr r2, 800c50c ) + 800c508: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 800c50c: 0800c617 .word 0x0800c617 + 800c510: 0800c62f .word 0x0800c62f + 800c514: 0800c62f .word 0x0800c62f + 800c518: 0800c62f .word 0x0800c62f + 800c51c: 0800c62f .word 0x0800c62f + 800c520: 0800c62f .word 0x0800c62f + 800c524: 0800c62f .word 0x0800c62f + 800c528: 0800c62f .word 0x0800c62f + 800c52c: 0800c62f .word 0x0800c62f + 800c530: 0800c62f .word 0x0800c62f + 800c534: 0800c62f .word 0x0800c62f + 800c538: 0800c59b .word 0x0800c59b + 800c53c: 0800c625 .word 0x0800c625 + 800c540: 0800c62f .word 0x0800c62f + 800c544: 0800c62f .word 0x0800c62f + 800c548: 0800c62f .word 0x0800c62f + 800c54c: 0800c62f .word 0x0800c62f + 800c550: 0800c625 .word 0x0800c625 + 800c554: 0800c62f .word 0x0800c62f + 800c558: 0800c62f .word 0x0800c62f + 800c55c: 0800c62f .word 0x0800c62f + 800c560: 0800c62f .word 0x0800c62f + 800c564: 0800c62f .word 0x0800c62f + 800c568: 0800c62f .word 0x0800c62f + 800c56c: 0800c62f .word 0x0800c62f + 800c570: 0800c62f .word 0x0800c62f + 800c574: 0800c62f .word 0x0800c62f + 800c578: 0800c5bb .word 0x0800c5bb + 800c57c: 0800c62f .word 0x0800c62f + 800c580: 0800c67b .word 0x0800c67b + 800c584: 0800c62f .word 0x0800c62f + 800c588: 0800c62f .word 0x0800c62f + 800c58c: 0800c61f .word 0x0800c61f + case 'c': +#ifdef TINY_PRINTF +#else + if (!(flags & LEFT)) +#endif + while (--field_width > 0) *str++ = ' '; + 800c590: 6afb ldr r3, [r7, #44] @ 0x2c + 800c592: 1c5a adds r2, r3, #1 + 800c594: 62fa str r2, [r7, #44] @ 0x2c + 800c596: 2220 movs r2, #32 + 800c598: 701a strb r2, [r3, #0] + 800c59a: 69fb ldr r3, [r7, #28] + 800c59c: 3b01 subs r3, #1 + 800c59e: 61fb str r3, [r7, #28] + 800c5a0: 69fb ldr r3, [r7, #28] + 800c5a2: 2b00 cmp r3, #0 + 800c5a4: dcf4 bgt.n 800c590 + *str++ = (unsigned char) va_arg(args, int); + 800c5a6: 683b ldr r3, [r7, #0] + 800c5a8: 1d1a adds r2, r3, #4 + 800c5aa: 603a str r2, [r7, #0] + 800c5ac: 6819 ldr r1, [r3, #0] + 800c5ae: 6afb ldr r3, [r7, #44] @ 0x2c + 800c5b0: 1c5a adds r2, r3, #1 + 800c5b2: 62fa str r2, [r7, #44] @ 0x2c + 800c5b4: b2ca uxtb r2, r1 + 800c5b6: 701a strb r2, [r3, #0] +#ifdef TINY_PRINTF +#else + while (--field_width > 0) *str++ = ' '; +#endif + continue; + 800c5b8: e08d b.n 800c6d6 + + case 's': + s = va_arg(args, char *); + 800c5ba: 683b ldr r3, [r7, #0] + 800c5bc: 1d1a adds r2, r3, #4 + 800c5be: 603a str r2, [r7, #0] + 800c5c0: 681b ldr r3, [r3, #0] + 800c5c2: 627b str r3, [r7, #36] @ 0x24 + if (!s) s = ""; + 800c5c4: 6a7b ldr r3, [r7, #36] @ 0x24 + 800c5c6: 2b00 cmp r3, #0 + 800c5c8: d101 bne.n 800c5ce + 800c5ca: 4b50 ldr r3, [pc, #320] @ (800c70c ) + 800c5cc: 627b str r3, [r7, #36] @ 0x24 +#ifdef TINY_PRINTF + len = strlen(s); + 800c5ce: 6a78 ldr r0, [r7, #36] @ 0x24 + 800c5d0: f7f3 fdd2 bl 8000178 + 800c5d4: 4603 mov r3, r0 + 800c5d6: 613b str r3, [r7, #16] +#else + len = strnlen(s, precision); + if (!(flags & LEFT)) +#endif + while (len < field_width--) *str++ = ' '; + 800c5d8: e004 b.n 800c5e4 + 800c5da: 6afb ldr r3, [r7, #44] @ 0x2c + 800c5dc: 1c5a adds r2, r3, #1 + 800c5de: 62fa str r2, [r7, #44] @ 0x2c + 800c5e0: 2220 movs r2, #32 + 800c5e2: 701a strb r2, [r3, #0] + 800c5e4: 69fb ldr r3, [r7, #28] + 800c5e6: 1e5a subs r2, r3, #1 + 800c5e8: 61fa str r2, [r7, #28] + 800c5ea: 693a ldr r2, [r7, #16] + 800c5ec: 429a cmp r2, r3 + 800c5ee: dbf4 blt.n 800c5da + for (i = 0; i < len; ++i) *str++ = *s++; + 800c5f0: 2300 movs r3, #0 + 800c5f2: 62bb str r3, [r7, #40] @ 0x28 + 800c5f4: e00a b.n 800c60c + 800c5f6: 6a7a ldr r2, [r7, #36] @ 0x24 + 800c5f8: 1c53 adds r3, r2, #1 + 800c5fa: 627b str r3, [r7, #36] @ 0x24 + 800c5fc: 6afb ldr r3, [r7, #44] @ 0x2c + 800c5fe: 1c59 adds r1, r3, #1 + 800c600: 62f9 str r1, [r7, #44] @ 0x2c + 800c602: 7812 ldrb r2, [r2, #0] + 800c604: 701a strb r2, [r3, #0] + 800c606: 6abb ldr r3, [r7, #40] @ 0x28 + 800c608: 3301 adds r3, #1 + 800c60a: 62bb str r3, [r7, #40] @ 0x28 + 800c60c: 6aba ldr r2, [r7, #40] @ 0x28 + 800c60e: 693b ldr r3, [r7, #16] + 800c610: 429a cmp r2, r3 + 800c612: dbf0 blt.n 800c5f6 +#ifdef TINY_PRINTF +#else + while (len < field_width--) *str++ = ' '; +#endif + continue; + 800c614: e05f b.n 800c6d6 + base = 8; + break; +#endif + + case 'X': + flags |= UPPERCASE; + 800c616: 6a3b ldr r3, [r7, #32] + 800c618: f043 0340 orr.w r3, r3, #64 @ 0x40 + 800c61c: 623b str r3, [r7, #32] + + case 'x': + base = 16; + 800c61e: 2310 movs r3, #16 + 800c620: 633b str r3, [r7, #48] @ 0x30 + break; + 800c622: e02b b.n 800c67c + + case 'd': + case 'i': + flags |= SIGN; + 800c624: 6a3b ldr r3, [r7, #32] + 800c626: f043 0302 orr.w r3, r3, #2 + 800c62a: 623b str r3, [r7, #32] + + case 'u': + break; + 800c62c: e025 b.n 800c67a + continue; + +#endif + + default: + if (*fmt != '%') *str++ = '%'; + 800c62e: 687b ldr r3, [r7, #4] + 800c630: 781b ldrb r3, [r3, #0] + 800c632: 2b25 cmp r3, #37 @ 0x25 + 800c634: d004 beq.n 800c640 + 800c636: 6afb ldr r3, [r7, #44] @ 0x2c + 800c638: 1c5a adds r2, r3, #1 + 800c63a: 62fa str r2, [r7, #44] @ 0x2c + 800c63c: 2225 movs r2, #37 @ 0x25 + 800c63e: 701a strb r2, [r3, #0] + CHECK_STR_SIZE(buf, str, size); + 800c640: 6afa ldr r2, [r7, #44] @ 0x2c + 800c642: 68fb ldr r3, [r7, #12] + 800c644: 1ad2 subs r2, r2, r3 + 800c646: 68bb ldr r3, [r7, #8] + 800c648: 3b01 subs r3, #1 + 800c64a: 429a cmp r2, r3 + 800c64c: da16 bge.n 800c67c + if (*fmt) + 800c64e: 687b ldr r3, [r7, #4] + 800c650: 781b ldrb r3, [r3, #0] + 800c652: 2b00 cmp r3, #0 + 800c654: d006 beq.n 800c664 + *str++ = *fmt; + 800c656: 687a ldr r2, [r7, #4] + 800c658: 6afb ldr r3, [r7, #44] @ 0x2c + 800c65a: 1c59 adds r1, r3, #1 + 800c65c: 62f9 str r1, [r7, #44] @ 0x2c + 800c65e: 7812 ldrb r2, [r2, #0] + 800c660: 701a strb r2, [r3, #0] + 800c662: e002 b.n 800c66a + else + --fmt; + 800c664: 687b ldr r3, [r7, #4] + 800c666: 3b01 subs r3, #1 + 800c668: 607b str r3, [r7, #4] + CHECK_STR_SIZE(buf, str, size); + 800c66a: 6afa ldr r2, [r7, #44] @ 0x2c + 800c66c: 68fb ldr r3, [r7, #12] + 800c66e: 1ad2 subs r2, r2, r3 + 800c670: 68bb ldr r3, [r7, #8] + 800c672: 3b01 subs r3, #1 + 800c674: 429a cmp r2, r3 + 800c676: db2d blt.n 800c6d4 + 800c678: e000 b.n 800c67c + break; + 800c67a: bf00 nop + continue; + } + + if (qualifier == 'l') + 800c67c: 697b ldr r3, [r7, #20] + 800c67e: 2b6c cmp r3, #108 @ 0x6c + 800c680: d105 bne.n 800c68e + num = va_arg(args, unsigned long); + 800c682: 683b ldr r3, [r7, #0] + 800c684: 1d1a adds r2, r3, #4 + 800c686: 603a str r2, [r7, #0] + 800c688: 681b ldr r3, [r3, #0] + 800c68a: 637b str r3, [r7, #52] @ 0x34 + 800c68c: e00f b.n 800c6ae + else if (flags & SIGN) + 800c68e: 6a3b ldr r3, [r7, #32] + 800c690: f003 0302 and.w r3, r3, #2 + 800c694: 2b00 cmp r3, #0 + 800c696: d005 beq.n 800c6a4 + num = va_arg(args, int); + 800c698: 683b ldr r3, [r7, #0] + 800c69a: 1d1a adds r2, r3, #4 + 800c69c: 603a str r2, [r7, #0] + 800c69e: 681b ldr r3, [r3, #0] + 800c6a0: 637b str r3, [r7, #52] @ 0x34 + 800c6a2: e004 b.n 800c6ae + else + num = va_arg(args, unsigned int); + 800c6a4: 683b ldr r3, [r7, #0] + 800c6a6: 1d1a adds r2, r3, #4 + 800c6a8: 603a str r2, [r7, #0] + 800c6aa: 681b ldr r3, [r3, #0] + 800c6ac: 637b str r3, [r7, #52] @ 0x34 + + str = ee_number(str, ((size - 1) - (str - buf)), num, base, field_width, precision, flags); + 800c6ae: 68bb ldr r3, [r7, #8] + 800c6b0: 1e5a subs r2, r3, #1 + 800c6b2: 6af9 ldr r1, [r7, #44] @ 0x2c + 800c6b4: 68fb ldr r3, [r7, #12] + 800c6b6: 1acb subs r3, r1, r3 + 800c6b8: 1ad1 subs r1, r2, r3 + 800c6ba: 6b7a ldr r2, [r7, #52] @ 0x34 + 800c6bc: 6a3b ldr r3, [r7, #32] + 800c6be: 9302 str r3, [sp, #8] + 800c6c0: 69bb ldr r3, [r7, #24] + 800c6c2: 9301 str r3, [sp, #4] + 800c6c4: 69fb ldr r3, [r7, #28] + 800c6c6: 9300 str r3, [sp, #0] + 800c6c8: 6b3b ldr r3, [r7, #48] @ 0x30 + 800c6ca: 6af8 ldr r0, [r7, #44] @ 0x2c + 800c6cc: f7ff fde0 bl 800c290 + 800c6d0: 62f8 str r0, [r7, #44] @ 0x2c + 800c6d2: e000 b.n 800c6d6 + continue; + 800c6d4: bf00 nop + for (str = buf; *fmt || ((str - buf) >= size-1); fmt++) + 800c6d6: 687b ldr r3, [r7, #4] + 800c6d8: 3301 adds r3, #1 + 800c6da: 607b str r3, [r7, #4] + 800c6dc: 687b ldr r3, [r7, #4] + 800c6de: 781b ldrb r3, [r3, #0] + 800c6e0: 2b00 cmp r3, #0 + 800c6e2: f47f aed2 bne.w 800c48a + 800c6e6: 6afa ldr r2, [r7, #44] @ 0x2c + 800c6e8: 68fb ldr r3, [r7, #12] + 800c6ea: 1ad2 subs r2, r2, r3 + 800c6ec: 68bb ldr r3, [r7, #8] + 800c6ee: 3b01 subs r3, #1 + 800c6f0: 429a cmp r2, r3 + 800c6f2: f6bf aeca bge.w 800c48a + } + + *str = '\0'; + 800c6f6: 6afb ldr r3, [r7, #44] @ 0x2c + 800c6f8: 2200 movs r2, #0 + 800c6fa: 701a strb r2, [r3, #0] + return str - buf; + 800c6fc: 6afa ldr r2, [r7, #44] @ 0x2c + 800c6fe: 68fb ldr r3, [r7, #12] + 800c700: 1ad3 subs r3, r2, r3 +} + 800c702: 4618 mov r0, r3 + 800c704: 3738 adds r7, #56 @ 0x38 + 800c706: 46bd mov sp, r7 + 800c708: bd80 pop {r7, pc} + 800c70a: bf00 nop + 800c70c: 0800d8a8 .word 0x0800d8a8 + +0800c710 : + * That is the reason why many variables that are used only in that function are declared static. + * Note: These variables could have been declared static in the function. + * + */ +void UTIL_SEQ_Run( UTIL_SEQ_bm_t Mask_bm ) +{ + 800c710: b580 push {r7, lr} + 800c712: b090 sub sp, #64 @ 0x40 + 800c714: af00 add r7, sp, #0 + 800c716: 6078 str r0, [r7, #4] + /* + * When this function is nested, the mask to be applied cannot be larger than the first call + * The mask is always getting smaller and smaller + * A copy is made of the mask set by UTIL_SEQ_Run() in case it is called again in the task + */ + super_mask_backup = SuperMask; + 800c718: 4b73 ldr r3, [pc, #460] @ (800c8e8 ) + 800c71a: 681b ldr r3, [r3, #0] + 800c71c: 62bb str r3, [r7, #40] @ 0x28 + SuperMask &= Mask_bm; + 800c71e: 4b72 ldr r3, [pc, #456] @ (800c8e8 ) + 800c720: 681a ldr r2, [r3, #0] + 800c722: 687b ldr r3, [r7, #4] + 800c724: 4013 ands r3, r2 + 800c726: 4a70 ldr r2, [pc, #448] @ (800c8e8 ) + 800c728: 6013 str r3, [r2, #0] + * TaskMask that comes from UTIL_SEQ_PauseTask() / UTIL_SEQ_ResumeTask + * SuperMask that comes from UTIL_SEQ_Run + * If the waited event is there, exit from UTIL_SEQ_Run() to return to the + * waiting task + */ + local_taskset = TaskSet; + 800c72a: 4b70 ldr r3, [pc, #448] @ (800c8ec ) + 800c72c: 681b ldr r3, [r3, #0] + 800c72e: 63bb str r3, [r7, #56] @ 0x38 + local_evtset = EvtSet; + 800c730: 4b6f ldr r3, [pc, #444] @ (800c8f0 ) + 800c732: 681b ldr r3, [r3, #0] + 800c734: 637b str r3, [r7, #52] @ 0x34 + local_taskmask = TaskMask; + 800c736: 4b6f ldr r3, [pc, #444] @ (800c8f4 ) + 800c738: 681b ldr r3, [r3, #0] + 800c73a: 633b str r3, [r7, #48] @ 0x30 + local_evtwaited = EvtWaited; + 800c73c: 4b6e ldr r3, [pc, #440] @ (800c8f8 ) + 800c73e: 681b ldr r3, [r3, #0] + 800c740: 62fb str r3, [r7, #44] @ 0x2c + while(((local_taskset & local_taskmask & SuperMask) != 0U) && ((local_evtset & local_evtwaited)==0U)) + 800c742: e08d b.n 800c860 + { + counter = 0U; + 800c744: 2300 movs r3, #0 + 800c746: 63fb str r3, [r7, #60] @ 0x3c + /* + * When a flag is set, the associated bit is set in TaskPrio[counter].priority mask depending + * on the priority parameter given from UTIL_SEQ_SetTask() + * The while loop is looking for a flag set from the highest priority maskr to the lower + */ + while((TaskPrio[counter].priority & local_taskmask & SuperMask)== 0U) + 800c748: e002 b.n 800c750 + { + counter++; + 800c74a: 6bfb ldr r3, [r7, #60] @ 0x3c + 800c74c: 3301 adds r3, #1 + 800c74e: 63fb str r3, [r7, #60] @ 0x3c + while((TaskPrio[counter].priority & local_taskmask & SuperMask)== 0U) + 800c750: 4a6a ldr r2, [pc, #424] @ (800c8fc ) + 800c752: 6bfb ldr r3, [r7, #60] @ 0x3c + 800c754: f852 2033 ldr.w r2, [r2, r3, lsl #3] + 800c758: 6b3b ldr r3, [r7, #48] @ 0x30 + 800c75a: 401a ands r2, r3 + 800c75c: 4b62 ldr r3, [pc, #392] @ (800c8e8 ) + 800c75e: 681b ldr r3, [r3, #0] + 800c760: 4013 ands r3, r2 + 800c762: 2b00 cmp r3, #0 + 800c764: d0f1 beq.n 800c74a + } + + current_task_set = TaskPrio[counter].priority & local_taskmask & SuperMask; + 800c766: 4a65 ldr r2, [pc, #404] @ (800c8fc ) + 800c768: 6bfb ldr r3, [r7, #60] @ 0x3c + 800c76a: f852 2033 ldr.w r2, [r2, r3, lsl #3] + 800c76e: 6b3b ldr r3, [r7, #48] @ 0x30 + 800c770: 401a ands r2, r3 + 800c772: 4b5d ldr r3, [pc, #372] @ (800c8e8 ) + 800c774: 681b ldr r3, [r3, #0] + 800c776: 4013 ands r3, r2 + 800c778: 627b str r3, [r7, #36] @ 0x24 + * so that the second one can be executed. + * Note that the first flag is not removed from the list of pending task but just masked by the round_robin mask + * + * In the check below, the round_robin mask is reinitialize in case all pending tasks haven been executed at least once + */ + if ((TaskPrio[counter].round_robin & current_task_set) == 0U) + 800c77a: 4a60 ldr r2, [pc, #384] @ (800c8fc ) + 800c77c: 6bfb ldr r3, [r7, #60] @ 0x3c + 800c77e: 00db lsls r3, r3, #3 + 800c780: 4413 add r3, r2 + 800c782: 685a ldr r2, [r3, #4] + 800c784: 6a7b ldr r3, [r7, #36] @ 0x24 + 800c786: 4013 ands r3, r2 + 800c788: 2b00 cmp r3, #0 + 800c78a: d106 bne.n 800c79a + { + TaskPrio[counter].round_robin = UTIL_SEQ_ALL_BIT_SET; + 800c78c: 4a5b ldr r2, [pc, #364] @ (800c8fc ) + 800c78e: 6bfb ldr r3, [r7, #60] @ 0x3c + 800c790: 00db lsls r3, r3, #3 + 800c792: 4413 add r3, r2 + 800c794: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff + 800c798: 605a str r2, [r3, #4] + /* + * Read the flag index of the task to be executed + * Once the index is read, the associated task will be executed even though a higher priority stack is requested + * before task execution. + */ + CurrentTaskIdx = (SEQ_BitPosition(current_task_set & TaskPrio[counter].round_robin)); + 800c79a: 4a58 ldr r2, [pc, #352] @ (800c8fc ) + 800c79c: 6bfb ldr r3, [r7, #60] @ 0x3c + 800c79e: 00db lsls r3, r3, #3 + 800c7a0: 4413 add r3, r2 + 800c7a2: 685a ldr r2, [r3, #4] + 800c7a4: 6a7b ldr r3, [r7, #36] @ 0x24 + 800c7a6: 4013 ands r3, r2 + 800c7a8: 4618 mov r0, r3 + 800c7aa: f000 f907 bl 800c9bc + 800c7ae: 4603 mov r3, r0 + 800c7b0: 461a mov r2, r3 + 800c7b2: 4b53 ldr r3, [pc, #332] @ (800c900 ) + 800c7b4: 601a str r2, [r3, #0] + + /* + * remove from the roun_robin mask the task that has been selected to be executed + */ + TaskPrio[counter].round_robin &= ~(1U << CurrentTaskIdx); + 800c7b6: 4a51 ldr r2, [pc, #324] @ (800c8fc ) + 800c7b8: 6bfb ldr r3, [r7, #60] @ 0x3c + 800c7ba: 00db lsls r3, r3, #3 + 800c7bc: 4413 add r3, r2 + 800c7be: 685a ldr r2, [r3, #4] + 800c7c0: 4b4f ldr r3, [pc, #316] @ (800c900 ) + 800c7c2: 681b ldr r3, [r3, #0] + 800c7c4: 2101 movs r1, #1 + 800c7c6: fa01 f303 lsl.w r3, r1, r3 + 800c7ca: 43db mvns r3, r3 + 800c7cc: 401a ands r2, r3 + 800c7ce: 494b ldr r1, [pc, #300] @ (800c8fc ) + 800c7d0: 6bfb ldr r3, [r7, #60] @ 0x3c + 800c7d2: 00db lsls r3, r3, #3 + 800c7d4: 440b add r3, r1 + 800c7d6: 605a str r2, [r3, #4] + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 800c7d8: f3ef 8310 mrs r3, PRIMASK + 800c7dc: 61bb str r3, [r7, #24] + return(result); + 800c7de: 69bb ldr r3, [r7, #24] + + UTIL_SEQ_ENTER_CRITICAL_SECTION( ); + 800c7e0: 623b str r3, [r7, #32] + __ASM volatile ("cpsid i" : : : "memory"); + 800c7e2: b672 cpsid i +} + 800c7e4: bf00 nop + /* remove from the list or pending task the one that has been selected to be executed */ + TaskSet &= ~(1U << CurrentTaskIdx); + 800c7e6: 4b46 ldr r3, [pc, #280] @ (800c900 ) + 800c7e8: 681b ldr r3, [r3, #0] + 800c7ea: 2201 movs r2, #1 + 800c7ec: fa02 f303 lsl.w r3, r2, r3 + 800c7f0: 43da mvns r2, r3 + 800c7f2: 4b3e ldr r3, [pc, #248] @ (800c8ec ) + 800c7f4: 681b ldr r3, [r3, #0] + 800c7f6: 4013 ands r3, r2 + 800c7f8: 4a3c ldr r2, [pc, #240] @ (800c8ec ) + 800c7fa: 6013 str r3, [r2, #0] + /* remove from all priority mask the task that has been selected to be executed */ + for (counter = UTIL_SEQ_CONF_PRIO_NBR; counter != 0U; counter--) + 800c7fc: 2301 movs r3, #1 + 800c7fe: 63fb str r3, [r7, #60] @ 0x3c + 800c800: e013 b.n 800c82a + { + TaskPrio[counter - 1U].priority &= ~(1U << CurrentTaskIdx); + 800c802: 6bfb ldr r3, [r7, #60] @ 0x3c + 800c804: 3b01 subs r3, #1 + 800c806: 4a3d ldr r2, [pc, #244] @ (800c8fc ) + 800c808: f852 1033 ldr.w r1, [r2, r3, lsl #3] + 800c80c: 4b3c ldr r3, [pc, #240] @ (800c900 ) + 800c80e: 681b ldr r3, [r3, #0] + 800c810: 2201 movs r2, #1 + 800c812: fa02 f303 lsl.w r3, r2, r3 + 800c816: 43da mvns r2, r3 + 800c818: 6bfb ldr r3, [r7, #60] @ 0x3c + 800c81a: 3b01 subs r3, #1 + 800c81c: 400a ands r2, r1 + 800c81e: 4937 ldr r1, [pc, #220] @ (800c8fc ) + 800c820: f841 2033 str.w r2, [r1, r3, lsl #3] + for (counter = UTIL_SEQ_CONF_PRIO_NBR; counter != 0U; counter--) + 800c824: 6bfb ldr r3, [r7, #60] @ 0x3c + 800c826: 3b01 subs r3, #1 + 800c828: 63fb str r3, [r7, #60] @ 0x3c + 800c82a: 6bfb ldr r3, [r7, #60] @ 0x3c + 800c82c: 2b00 cmp r3, #0 + 800c82e: d1e8 bne.n 800c802 + 800c830: 6a3b ldr r3, [r7, #32] + 800c832: 617b str r3, [r7, #20] + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 800c834: 697b ldr r3, [r7, #20] + 800c836: f383 8810 msr PRIMASK, r3 +} + 800c83a: bf00 nop + } + UTIL_SEQ_EXIT_CRITICAL_SECTION( ); + + /* Execute the task */ + TaskCb[CurrentTaskIdx]( ); + 800c83c: 4b30 ldr r3, [pc, #192] @ (800c900 ) + 800c83e: 681b ldr r3, [r3, #0] + 800c840: 4a30 ldr r2, [pc, #192] @ (800c904 ) + 800c842: f852 3023 ldr.w r3, [r2, r3, lsl #2] + 800c846: 4798 blx r3 + + local_taskset = TaskSet; + 800c848: 4b28 ldr r3, [pc, #160] @ (800c8ec ) + 800c84a: 681b ldr r3, [r3, #0] + 800c84c: 63bb str r3, [r7, #56] @ 0x38 + local_evtset = EvtSet; + 800c84e: 4b28 ldr r3, [pc, #160] @ (800c8f0 ) + 800c850: 681b ldr r3, [r3, #0] + 800c852: 637b str r3, [r7, #52] @ 0x34 + local_taskmask = TaskMask; + 800c854: 4b27 ldr r3, [pc, #156] @ (800c8f4 ) + 800c856: 681b ldr r3, [r3, #0] + 800c858: 633b str r3, [r7, #48] @ 0x30 + local_evtwaited = EvtWaited; + 800c85a: 4b27 ldr r3, [pc, #156] @ (800c8f8 ) + 800c85c: 681b ldr r3, [r3, #0] + 800c85e: 62fb str r3, [r7, #44] @ 0x2c + while(((local_taskset & local_taskmask & SuperMask) != 0U) && ((local_evtset & local_evtwaited)==0U)) + 800c860: 6bba ldr r2, [r7, #56] @ 0x38 + 800c862: 6b3b ldr r3, [r7, #48] @ 0x30 + 800c864: 401a ands r2, r3 + 800c866: 4b20 ldr r3, [pc, #128] @ (800c8e8 ) + 800c868: 681b ldr r3, [r3, #0] + 800c86a: 4013 ands r3, r2 + 800c86c: 2b00 cmp r3, #0 + 800c86e: d005 beq.n 800c87c + 800c870: 6b7a ldr r2, [r7, #52] @ 0x34 + 800c872: 6afb ldr r3, [r7, #44] @ 0x2c + 800c874: 4013 ands r3, r2 + 800c876: 2b00 cmp r3, #0 + 800c878: f43f af64 beq.w 800c744 + } + + /* the set of CurrentTaskIdx to no task running allows to call WaitEvt in the Pre/Post ilde context */ + CurrentTaskIdx = UTIL_SEQ_NOTASKRUNNING; + 800c87c: 4b20 ldr r3, [pc, #128] @ (800c900 ) + 800c87e: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff + 800c882: 601a str r2, [r3, #0] + UTIL_SEQ_PreIdle( ); + 800c884: f000 f88e bl 800c9a4 + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 800c888: f3ef 8310 mrs r3, PRIMASK + 800c88c: 613b str r3, [r7, #16] + return(result); + 800c88e: 693b ldr r3, [r7, #16] + + UTIL_SEQ_ENTER_CRITICAL_SECTION_IDLE( ); + 800c890: 61fb str r3, [r7, #28] + __ASM volatile ("cpsid i" : : : "memory"); + 800c892: b672 cpsid i +} + 800c894: bf00 nop + local_taskset = TaskSet; + 800c896: 4b15 ldr r3, [pc, #84] @ (800c8ec ) + 800c898: 681b ldr r3, [r3, #0] + 800c89a: 63bb str r3, [r7, #56] @ 0x38 + local_evtset = EvtSet; + 800c89c: 4b14 ldr r3, [pc, #80] @ (800c8f0 ) + 800c89e: 681b ldr r3, [r3, #0] + 800c8a0: 637b str r3, [r7, #52] @ 0x34 + local_taskmask = TaskMask; + 800c8a2: 4b14 ldr r3, [pc, #80] @ (800c8f4 ) + 800c8a4: 681b ldr r3, [r3, #0] + 800c8a6: 633b str r3, [r7, #48] @ 0x30 + if ((local_taskset & local_taskmask & SuperMask) == 0U) + 800c8a8: 6bba ldr r2, [r7, #56] @ 0x38 + 800c8aa: 6b3b ldr r3, [r7, #48] @ 0x30 + 800c8ac: 401a ands r2, r3 + 800c8ae: 4b0e ldr r3, [pc, #56] @ (800c8e8 ) + 800c8b0: 681b ldr r3, [r3, #0] + 800c8b2: 4013 ands r3, r2 + 800c8b4: 2b00 cmp r3, #0 + 800c8b6: d107 bne.n 800c8c8 + { + if ((local_evtset & EvtWaited)== 0U) + 800c8b8: 4b0f ldr r3, [pc, #60] @ (800c8f8 ) + 800c8ba: 681a ldr r2, [r3, #0] + 800c8bc: 6b7b ldr r3, [r7, #52] @ 0x34 + 800c8be: 4013 ands r3, r2 + 800c8c0: 2b00 cmp r3, #0 + 800c8c2: d101 bne.n 800c8c8 + { + UTIL_SEQ_Idle( ); + 800c8c4: f7f4 f906 bl 8000ad4 + 800c8c8: 69fb ldr r3, [r7, #28] + 800c8ca: 60fb str r3, [r7, #12] + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 800c8cc: 68fb ldr r3, [r7, #12] + 800c8ce: f383 8810 msr PRIMASK, r3 +} + 800c8d2: bf00 nop + } + } + UTIL_SEQ_EXIT_CRITICAL_SECTION_IDLE( ); + + UTIL_SEQ_PostIdle( ); + 800c8d4: f000 f86c bl 800c9b0 + + /* restore the mask from UTIL_SEQ_Run() */ + SuperMask = super_mask_backup; + 800c8d8: 4a03 ldr r2, [pc, #12] @ (800c8e8 ) + 800c8da: 6abb ldr r3, [r7, #40] @ 0x28 + 800c8dc: 6013 str r3, [r2, #0] + + return; + 800c8de: bf00 nop +} + 800c8e0: 3740 adds r7, #64 @ 0x40 + 800c8e2: 46bd mov sp, r7 + 800c8e4: bd80 pop {r7, pc} + 800c8e6: bf00 nop + 800c8e8: 20000020 .word 0x20000020 + 800c8ec: 200009b0 .word 0x200009b0 + 800c8f0: 200009b4 .word 0x200009b4 + 800c8f4: 2000001c .word 0x2000001c + 800c8f8: 200009b8 .word 0x200009b8 + 800c8fc: 200009c4 .word 0x200009c4 + 800c900: 200009bc .word 0x200009bc + 800c904: 200009c0 .word 0x200009c0 + +0800c908 : + +void UTIL_SEQ_RegTask(UTIL_SEQ_bm_t TaskId_bm, uint32_t Flags, void (*Task)( void )) +{ + 800c908: b580 push {r7, lr} + 800c90a: b088 sub sp, #32 + 800c90c: af00 add r7, sp, #0 + 800c90e: 60f8 str r0, [r7, #12] + 800c910: 60b9 str r1, [r7, #8] + 800c912: 607a str r2, [r7, #4] + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 800c914: f3ef 8310 mrs r3, PRIMASK + 800c918: 617b str r3, [r7, #20] + return(result); + 800c91a: 697b ldr r3, [r7, #20] + (void)Flags; + UTIL_SEQ_ENTER_CRITICAL_SECTION(); + 800c91c: 61fb str r3, [r7, #28] + __ASM volatile ("cpsid i" : : : "memory"); + 800c91e: b672 cpsid i +} + 800c920: bf00 nop + + TaskCb[SEQ_BitPosition(TaskId_bm)] = Task; + 800c922: 68f8 ldr r0, [r7, #12] + 800c924: f000 f84a bl 800c9bc + 800c928: 4603 mov r3, r0 + 800c92a: 4619 mov r1, r3 + 800c92c: 4a06 ldr r2, [pc, #24] @ (800c948 ) + 800c92e: 687b ldr r3, [r7, #4] + 800c930: f842 3021 str.w r3, [r2, r1, lsl #2] + 800c934: 69fb ldr r3, [r7, #28] + 800c936: 61bb str r3, [r7, #24] + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 800c938: 69bb ldr r3, [r7, #24] + 800c93a: f383 8810 msr PRIMASK, r3 +} + 800c93e: bf00 nop + + UTIL_SEQ_EXIT_CRITICAL_SECTION(); + + return; + 800c940: bf00 nop +} + 800c942: 3720 adds r7, #32 + 800c944: 46bd mov sp, r7 + 800c946: bd80 pop {r7, pc} + 800c948: 200009c0 .word 0x200009c0 + +0800c94c : + +void UTIL_SEQ_SetTask( UTIL_SEQ_bm_t TaskId_bm , uint32_t Task_Prio ) +{ + 800c94c: b480 push {r7} + 800c94e: b087 sub sp, #28 + 800c950: af00 add r7, sp, #0 + 800c952: 6078 str r0, [r7, #4] + 800c954: 6039 str r1, [r7, #0] + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 800c956: f3ef 8310 mrs r3, PRIMASK + 800c95a: 60fb str r3, [r7, #12] + return(result); + 800c95c: 68fb ldr r3, [r7, #12] + UTIL_SEQ_ENTER_CRITICAL_SECTION( ); + 800c95e: 617b str r3, [r7, #20] + __ASM volatile ("cpsid i" : : : "memory"); + 800c960: b672 cpsid i +} + 800c962: bf00 nop + + TaskSet |= TaskId_bm; + 800c964: 4b0d ldr r3, [pc, #52] @ (800c99c ) + 800c966: 681a ldr r2, [r3, #0] + 800c968: 687b ldr r3, [r7, #4] + 800c96a: 4313 orrs r3, r2 + 800c96c: 4a0b ldr r2, [pc, #44] @ (800c99c ) + 800c96e: 6013 str r3, [r2, #0] + TaskPrio[Task_Prio].priority |= TaskId_bm; + 800c970: 4a0b ldr r2, [pc, #44] @ (800c9a0 ) + 800c972: 683b ldr r3, [r7, #0] + 800c974: f852 2033 ldr.w r2, [r2, r3, lsl #3] + 800c978: 687b ldr r3, [r7, #4] + 800c97a: 431a orrs r2, r3 + 800c97c: 4908 ldr r1, [pc, #32] @ (800c9a0 ) + 800c97e: 683b ldr r3, [r7, #0] + 800c980: f841 2033 str.w r2, [r1, r3, lsl #3] + 800c984: 697b ldr r3, [r7, #20] + 800c986: 613b str r3, [r7, #16] + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 800c988: 693b ldr r3, [r7, #16] + 800c98a: f383 8810 msr PRIMASK, r3 +} + 800c98e: bf00 nop + + UTIL_SEQ_EXIT_CRITICAL_SECTION( ); + + return; + 800c990: bf00 nop +} + 800c992: 371c adds r7, #28 + 800c994: 46bd mov sp, r7 + 800c996: bc80 pop {r7} + 800c998: 4770 bx lr + 800c99a: bf00 nop + 800c99c: 200009b0 .word 0x200009b0 + 800c9a0: 200009c4 .word 0x200009c4 + +0800c9a4 : +{ + return; +} + +__WEAK void UTIL_SEQ_PreIdle( void ) +{ + 800c9a4: b480 push {r7} + 800c9a6: af00 add r7, sp, #0 + /* + * Unless specified by the application, there is nothing to be done + */ + return; + 800c9a8: bf00 nop +} + 800c9aa: 46bd mov sp, r7 + 800c9ac: bc80 pop {r7} + 800c9ae: 4770 bx lr + +0800c9b0 : + +__WEAK void UTIL_SEQ_PostIdle( void ) +{ + 800c9b0: b480 push {r7} + 800c9b2: af00 add r7, sp, #0 + /* + * Unless specified by the application, there is nothing to be done + */ + return; + 800c9b4: bf00 nop +} + 800c9b6: 46bd mov sp, r7 + 800c9b8: bc80 pop {r7} + 800c9ba: 4770 bx lr + +0800c9bc : + * @brief return the position of the first bit set to 1 + * @param Value 32 bit value + * @retval bit position + */ +uint8_t SEQ_BitPosition(uint32_t Value) +{ + 800c9bc: b480 push {r7} + 800c9be: b085 sub sp, #20 + 800c9c0: af00 add r7, sp, #0 + 800c9c2: 6078 str r0, [r7, #4] +uint8_t n = 0U; + 800c9c4: 2300 movs r3, #0 + 800c9c6: 73fb strb r3, [r7, #15] +uint32_t lvalue = Value; + 800c9c8: 687b ldr r3, [r7, #4] + 800c9ca: 60bb str r3, [r7, #8] + + if ((lvalue & 0xFFFF0000U) == 0U) { n = 16U; lvalue <<= 16U; } + 800c9cc: 68bb ldr r3, [r7, #8] + 800c9ce: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 + 800c9d2: d204 bcs.n 800c9de + 800c9d4: 2310 movs r3, #16 + 800c9d6: 73fb strb r3, [r7, #15] + 800c9d8: 68bb ldr r3, [r7, #8] + 800c9da: 041b lsls r3, r3, #16 + 800c9dc: 60bb str r3, [r7, #8] + if ((lvalue & 0xFF000000U) == 0U) { n += 8U; lvalue <<= 8U; } + 800c9de: 68bb ldr r3, [r7, #8] + 800c9e0: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000 + 800c9e4: d205 bcs.n 800c9f2 + 800c9e6: 7bfb ldrb r3, [r7, #15] + 800c9e8: 3308 adds r3, #8 + 800c9ea: 73fb strb r3, [r7, #15] + 800c9ec: 68bb ldr r3, [r7, #8] + 800c9ee: 021b lsls r3, r3, #8 + 800c9f0: 60bb str r3, [r7, #8] + if ((lvalue & 0xF0000000U) == 0U) { n += 4U; lvalue <<= 4U; } + 800c9f2: 68bb ldr r3, [r7, #8] + 800c9f4: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 + 800c9f8: d205 bcs.n 800ca06 + 800c9fa: 7bfb ldrb r3, [r7, #15] + 800c9fc: 3304 adds r3, #4 + 800c9fe: 73fb strb r3, [r7, #15] + 800ca00: 68bb ldr r3, [r7, #8] + 800ca02: 011b lsls r3, r3, #4 + 800ca04: 60bb str r3, [r7, #8] + + n += SEQ_clz_table_4bit[lvalue >> (32-4)]; + 800ca06: 68bb ldr r3, [r7, #8] + 800ca08: 0f1b lsrs r3, r3, #28 + 800ca0a: 4a07 ldr r2, [pc, #28] @ (800ca28 ) + 800ca0c: 5cd2 ldrb r2, [r2, r3] + 800ca0e: 7bfb ldrb r3, [r7, #15] + 800ca10: 4413 add r3, r2 + 800ca12: 73fb strb r3, [r7, #15] + + return (uint8_t)(31U-n); + 800ca14: 7bfb ldrb r3, [r7, #15] + 800ca16: f1c3 031f rsb r3, r3, #31 + 800ca1a: b2db uxtb r3, r3 +} + 800ca1c: 4618 mov r0, r3 + 800ca1e: 3714 adds r7, #20 + 800ca20: 46bd mov sp, r7 + 800ca22: bc80 pop {r7} + 800ca24: 4770 bx lr + 800ca26: bf00 nop + 800ca28: 0800db20 .word 0x0800db20 + +0800ca2c : + * @addtogroup TIMER_SERVER_exported_function + * @{ + */ + +UTIL_TIMER_Status_t UTIL_TIMER_Init(void) +{ + 800ca2c: b580 push {r7, lr} + 800ca2e: af00 add r7, sp, #0 + UTIL_TIMER_INIT_CRITICAL_SECTION(); + TimerListHead = NULL; + 800ca30: 4b04 ldr r3, [pc, #16] @ (800ca44 ) + 800ca32: 2200 movs r2, #0 + 800ca34: 601a str r2, [r3, #0] + return UTIL_TimerDriver.InitTimer(); + 800ca36: 4b04 ldr r3, [pc, #16] @ (800ca48 ) + 800ca38: 681b ldr r3, [r3, #0] + 800ca3a: 4798 blx r3 + 800ca3c: 4603 mov r3, r0 +} + 800ca3e: 4618 mov r0, r3 + 800ca40: bd80 pop {r7, pc} + 800ca42: bf00 nop + 800ca44: 200009cc .word 0x200009cc + 800ca48: 0800d968 .word 0x0800d968 + +0800ca4c : +{ + return UTIL_TimerDriver.DeInitTimer(); +} + +UTIL_TIMER_Status_t UTIL_TIMER_Create( UTIL_TIMER_Object_t *TimerObject, uint32_t PeriodValue, UTIL_TIMER_Mode_t Mode, void ( *Callback )( void *), void *Argument) +{ + 800ca4c: b580 push {r7, lr} + 800ca4e: b084 sub sp, #16 + 800ca50: af00 add r7, sp, #0 + 800ca52: 60f8 str r0, [r7, #12] + 800ca54: 60b9 str r1, [r7, #8] + 800ca56: 603b str r3, [r7, #0] + 800ca58: 4613 mov r3, r2 + 800ca5a: 71fb strb r3, [r7, #7] + if((TimerObject != NULL) && (Callback != NULL)) + 800ca5c: 68fb ldr r3, [r7, #12] + 800ca5e: 2b00 cmp r3, #0 + 800ca60: d023 beq.n 800caaa + 800ca62: 683b ldr r3, [r7, #0] + 800ca64: 2b00 cmp r3, #0 + 800ca66: d020 beq.n 800caaa + { + TimerObject->Timestamp = 0U; + 800ca68: 68fb ldr r3, [r7, #12] + 800ca6a: 2200 movs r2, #0 + 800ca6c: 601a str r2, [r3, #0] + TimerObject->ReloadValue = UTIL_TimerDriver.ms2Tick(PeriodValue); + 800ca6e: 4b11 ldr r3, [pc, #68] @ (800cab4 ) + 800ca70: 6a5b ldr r3, [r3, #36] @ 0x24 + 800ca72: 68b8 ldr r0, [r7, #8] + 800ca74: 4798 blx r3 + 800ca76: 4602 mov r2, r0 + 800ca78: 68fb ldr r3, [r7, #12] + 800ca7a: 605a str r2, [r3, #4] + TimerObject->IsPending = 0U; + 800ca7c: 68fb ldr r3, [r7, #12] + 800ca7e: 2200 movs r2, #0 + 800ca80: 721a strb r2, [r3, #8] + TimerObject->IsRunning = 0U; + 800ca82: 68fb ldr r3, [r7, #12] + 800ca84: 2200 movs r2, #0 + 800ca86: 725a strb r2, [r3, #9] + TimerObject->IsReloadStopped = 0U; + 800ca88: 68fb ldr r3, [r7, #12] + 800ca8a: 2200 movs r2, #0 + 800ca8c: 729a strb r2, [r3, #10] + TimerObject->Callback = Callback; + 800ca8e: 68fb ldr r3, [r7, #12] + 800ca90: 683a ldr r2, [r7, #0] + 800ca92: 60da str r2, [r3, #12] + TimerObject->argument = Argument; + 800ca94: 68fb ldr r3, [r7, #12] + 800ca96: 69ba ldr r2, [r7, #24] + 800ca98: 611a str r2, [r3, #16] + TimerObject->Mode = Mode; + 800ca9a: 68fb ldr r3, [r7, #12] + 800ca9c: 79fa ldrb r2, [r7, #7] + 800ca9e: 72da strb r2, [r3, #11] + TimerObject->Next = NULL; + 800caa0: 68fb ldr r3, [r7, #12] + 800caa2: 2200 movs r2, #0 + 800caa4: 615a str r2, [r3, #20] + return UTIL_TIMER_OK; + 800caa6: 2300 movs r3, #0 + 800caa8: e000 b.n 800caac + } + else + { + return UTIL_TIMER_INVALID_PARAM; + 800caaa: 2301 movs r3, #1 + } +} + 800caac: 4618 mov r0, r3 + 800caae: 3710 adds r7, #16 + 800cab0: 46bd mov sp, r7 + 800cab2: bd80 pop {r7, pc} + 800cab4: 0800d968 .word 0x0800d968 + +0800cab8 : + +UTIL_TIMER_Status_t UTIL_TIMER_Start( UTIL_TIMER_Object_t *TimerObject) +{ + 800cab8: b580 push {r7, lr} + 800caba: b08a sub sp, #40 @ 0x28 + 800cabc: af00 add r7, sp, #0 + 800cabe: 6078 str r0, [r7, #4] + UTIL_TIMER_Status_t ret = UTIL_TIMER_OK; + 800cac0: 2300 movs r3, #0 + 800cac2: f887 3027 strb.w r3, [r7, #39] @ 0x27 + uint32_t elapsedTime; + uint32_t minValue; + uint32_t ticks; + + if(( TimerObject != NULL ) && ( TimerExists( TimerObject ) == false ) && (TimerObject->IsRunning == 0U)) + 800cac6: 687b ldr r3, [r7, #4] + 800cac8: 2b00 cmp r3, #0 + 800caca: d056 beq.n 800cb7a + 800cacc: 6878 ldr r0, [r7, #4] + 800cace: f000 f9a9 bl 800ce24 + 800cad2: 4603 mov r3, r0 + 800cad4: f083 0301 eor.w r3, r3, #1 + 800cad8: b2db uxtb r3, r3 + 800cada: 2b00 cmp r3, #0 + 800cadc: d04d beq.n 800cb7a + 800cade: 687b ldr r3, [r7, #4] + 800cae0: 7a5b ldrb r3, [r3, #9] + 800cae2: 2b00 cmp r3, #0 + 800cae4: d149 bne.n 800cb7a + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 800cae6: f3ef 8310 mrs r3, PRIMASK + 800caea: 613b str r3, [r7, #16] + return(result); + 800caec: 693b ldr r3, [r7, #16] + { + UTIL_TIMER_ENTER_CRITICAL_SECTION(); + 800caee: 61fb str r3, [r7, #28] + __ASM volatile ("cpsid i" : : : "memory"); + 800caf0: b672 cpsid i +} + 800caf2: bf00 nop + ticks = TimerObject->ReloadValue; + 800caf4: 687b ldr r3, [r7, #4] + 800caf6: 685b ldr r3, [r3, #4] + 800caf8: 623b str r3, [r7, #32] + minValue = UTIL_TimerDriver.GetMinimumTimeout( ); + 800cafa: 4b24 ldr r3, [pc, #144] @ (800cb8c ) + 800cafc: 6a1b ldr r3, [r3, #32] + 800cafe: 4798 blx r3 + 800cb00: 61b8 str r0, [r7, #24] + + if( ticks < minValue ) + 800cb02: 6a3a ldr r2, [r7, #32] + 800cb04: 69bb ldr r3, [r7, #24] + 800cb06: 429a cmp r2, r3 + 800cb08: d201 bcs.n 800cb0e + { + ticks = minValue; + 800cb0a: 69bb ldr r3, [r7, #24] + 800cb0c: 623b str r3, [r7, #32] + } + + TimerObject->Timestamp = ticks; + 800cb0e: 687b ldr r3, [r7, #4] + 800cb10: 6a3a ldr r2, [r7, #32] + 800cb12: 601a str r2, [r3, #0] + TimerObject->IsPending = 0U; + 800cb14: 687b ldr r3, [r7, #4] + 800cb16: 2200 movs r2, #0 + 800cb18: 721a strb r2, [r3, #8] + TimerObject->IsRunning = 1U; + 800cb1a: 687b ldr r3, [r7, #4] + 800cb1c: 2201 movs r2, #1 + 800cb1e: 725a strb r2, [r3, #9] + TimerObject->IsReloadStopped = 0U; + 800cb20: 687b ldr r3, [r7, #4] + 800cb22: 2200 movs r2, #0 + 800cb24: 729a strb r2, [r3, #10] + if( TimerListHead == NULL ) + 800cb26: 4b1a ldr r3, [pc, #104] @ (800cb90 ) + 800cb28: 681b ldr r3, [r3, #0] + 800cb2a: 2b00 cmp r3, #0 + 800cb2c: d106 bne.n 800cb3c + { + UTIL_TimerDriver.SetTimerContext(); + 800cb2e: 4b17 ldr r3, [pc, #92] @ (800cb8c ) + 800cb30: 691b ldr r3, [r3, #16] + 800cb32: 4798 blx r3 + TimerInsertNewHeadTimer( TimerObject ); /* insert a timeout at now+obj->Timestamp */ + 800cb34: 6878 ldr r0, [r7, #4] + 800cb36: f000 f9eb bl 800cf10 + 800cb3a: e017 b.n 800cb6c + } + else + { + elapsedTime = UTIL_TimerDriver.GetTimerElapsedTime( ); + 800cb3c: 4b13 ldr r3, [pc, #76] @ (800cb8c ) + 800cb3e: 699b ldr r3, [r3, #24] + 800cb40: 4798 blx r3 + 800cb42: 6178 str r0, [r7, #20] + TimerObject->Timestamp += elapsedTime; + 800cb44: 687b ldr r3, [r7, #4] + 800cb46: 681a ldr r2, [r3, #0] + 800cb48: 697b ldr r3, [r7, #20] + 800cb4a: 441a add r2, r3 + 800cb4c: 687b ldr r3, [r7, #4] + 800cb4e: 601a str r2, [r3, #0] + + if( TimerObject->Timestamp < TimerListHead->Timestamp ) + 800cb50: 687b ldr r3, [r7, #4] + 800cb52: 681a ldr r2, [r3, #0] + 800cb54: 4b0e ldr r3, [pc, #56] @ (800cb90 ) + 800cb56: 681b ldr r3, [r3, #0] + 800cb58: 681b ldr r3, [r3, #0] + 800cb5a: 429a cmp r2, r3 + 800cb5c: d203 bcs.n 800cb66 + { + TimerInsertNewHeadTimer( TimerObject); + 800cb5e: 6878 ldr r0, [r7, #4] + 800cb60: f000 f9d6 bl 800cf10 + 800cb64: e002 b.n 800cb6c + } + else + { + TimerInsertTimer( TimerObject); + 800cb66: 6878 ldr r0, [r7, #4] + 800cb68: f000 f9a2 bl 800ceb0 + 800cb6c: 69fb ldr r3, [r7, #28] + 800cb6e: 60fb str r3, [r7, #12] + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 800cb70: 68fb ldr r3, [r7, #12] + 800cb72: f383 8810 msr PRIMASK, r3 +} + 800cb76: bf00 nop + { + 800cb78: e002 b.n 800cb80 + } + UTIL_TIMER_EXIT_CRITICAL_SECTION(); + } + else + { + ret = UTIL_TIMER_INVALID_PARAM; + 800cb7a: 2301 movs r3, #1 + 800cb7c: f887 3027 strb.w r3, [r7, #39] @ 0x27 + } + return ret; + 800cb80: f897 3027 ldrb.w r3, [r7, #39] @ 0x27 +} + 800cb84: 4618 mov r0, r3 + 800cb86: 3728 adds r7, #40 @ 0x28 + 800cb88: 46bd mov sp, r7 + 800cb8a: bd80 pop {r7, pc} + 800cb8c: 0800d968 .word 0x0800d968 + 800cb90: 200009cc .word 0x200009cc + +0800cb94 : + } + return ret; +} + +UTIL_TIMER_Status_t UTIL_TIMER_Stop( UTIL_TIMER_Object_t *TimerObject ) +{ + 800cb94: b580 push {r7, lr} + 800cb96: b088 sub sp, #32 + 800cb98: af00 add r7, sp, #0 + 800cb9a: 6078 str r0, [r7, #4] + UTIL_TIMER_Status_t ret = UTIL_TIMER_OK; + 800cb9c: 2300 movs r3, #0 + 800cb9e: 77fb strb r3, [r7, #31] + + if (NULL != TimerObject) + 800cba0: 687b ldr r3, [r7, #4] + 800cba2: 2b00 cmp r3, #0 + 800cba4: d05b beq.n 800cc5e + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 800cba6: f3ef 8310 mrs r3, PRIMASK + 800cbaa: 60fb str r3, [r7, #12] + return(result); + 800cbac: 68fb ldr r3, [r7, #12] + { + UTIL_TIMER_ENTER_CRITICAL_SECTION(); + 800cbae: 613b str r3, [r7, #16] + __ASM volatile ("cpsid i" : : : "memory"); + 800cbb0: b672 cpsid i +} + 800cbb2: bf00 nop + UTIL_TIMER_Object_t* prev = TimerListHead; + 800cbb4: 4b2d ldr r3, [pc, #180] @ (800cc6c ) + 800cbb6: 681b ldr r3, [r3, #0] + 800cbb8: 61bb str r3, [r7, #24] + UTIL_TIMER_Object_t* cur = TimerListHead; + 800cbba: 4b2c ldr r3, [pc, #176] @ (800cc6c ) + 800cbbc: 681b ldr r3, [r3, #0] + 800cbbe: 617b str r3, [r7, #20] + TimerObject->IsReloadStopped = 1U; + 800cbc0: 687b ldr r3, [r7, #4] + 800cbc2: 2201 movs r2, #1 + 800cbc4: 729a strb r2, [r3, #10] + + /* List is empty or the Obj to stop does not exist */ + if(NULL != TimerListHead) + 800cbc6: 4b29 ldr r3, [pc, #164] @ (800cc6c ) + 800cbc8: 681b ldr r3, [r3, #0] + 800cbca: 2b00 cmp r3, #0 + 800cbcc: d041 beq.n 800cc52 + { + TimerObject->IsRunning = 0U; + 800cbce: 687b ldr r3, [r7, #4] + 800cbd0: 2200 movs r2, #0 + 800cbd2: 725a strb r2, [r3, #9] + + if( TimerListHead == TimerObject ) /* Stop the Head */ + 800cbd4: 4b25 ldr r3, [pc, #148] @ (800cc6c ) + 800cbd6: 681b ldr r3, [r3, #0] + 800cbd8: 687a ldr r2, [r7, #4] + 800cbda: 429a cmp r2, r3 + 800cbdc: d134 bne.n 800cc48 + { + TimerListHead->IsPending = 0; + 800cbde: 4b23 ldr r3, [pc, #140] @ (800cc6c ) + 800cbe0: 681b ldr r3, [r3, #0] + 800cbe2: 2200 movs r2, #0 + 800cbe4: 721a strb r2, [r3, #8] + if( TimerListHead->Next != NULL ) + 800cbe6: 4b21 ldr r3, [pc, #132] @ (800cc6c ) + 800cbe8: 681b ldr r3, [r3, #0] + 800cbea: 695b ldr r3, [r3, #20] + 800cbec: 2b00 cmp r3, #0 + 800cbee: d00a beq.n 800cc06 + { + TimerListHead = TimerListHead->Next; + 800cbf0: 4b1e ldr r3, [pc, #120] @ (800cc6c ) + 800cbf2: 681b ldr r3, [r3, #0] + 800cbf4: 695b ldr r3, [r3, #20] + 800cbf6: 4a1d ldr r2, [pc, #116] @ (800cc6c ) + 800cbf8: 6013 str r3, [r2, #0] + TimerSetTimeout( TimerListHead ); + 800cbfa: 4b1c ldr r3, [pc, #112] @ (800cc6c ) + 800cbfc: 681b ldr r3, [r3, #0] + 800cbfe: 4618 mov r0, r3 + 800cc00: f000 f92c bl 800ce5c + 800cc04: e023 b.n 800cc4e + } + else + { + UTIL_TimerDriver.StopTimerEvt( ); + 800cc06: 4b1a ldr r3, [pc, #104] @ (800cc70 ) + 800cc08: 68db ldr r3, [r3, #12] + 800cc0a: 4798 blx r3 + TimerListHead = NULL; + 800cc0c: 4b17 ldr r3, [pc, #92] @ (800cc6c ) + 800cc0e: 2200 movs r2, #0 + 800cc10: 601a str r2, [r3, #0] + 800cc12: e01c b.n 800cc4e + } + else /* Stop an object within the list */ + { + while( cur != NULL ) + { + if( cur == TimerObject ) + 800cc14: 697a ldr r2, [r7, #20] + 800cc16: 687b ldr r3, [r7, #4] + 800cc18: 429a cmp r2, r3 + 800cc1a: d110 bne.n 800cc3e + { + if( cur->Next != NULL ) + 800cc1c: 697b ldr r3, [r7, #20] + 800cc1e: 695b ldr r3, [r3, #20] + 800cc20: 2b00 cmp r3, #0 + 800cc22: d006 beq.n 800cc32 + { + cur = cur->Next; + 800cc24: 697b ldr r3, [r7, #20] + 800cc26: 695b ldr r3, [r3, #20] + 800cc28: 617b str r3, [r7, #20] + prev->Next = cur; + 800cc2a: 69bb ldr r3, [r7, #24] + 800cc2c: 697a ldr r2, [r7, #20] + 800cc2e: 615a str r2, [r3, #20] + else + { + cur = NULL; + prev->Next = cur; + } + break; + 800cc30: e00d b.n 800cc4e + cur = NULL; + 800cc32: 2300 movs r3, #0 + 800cc34: 617b str r3, [r7, #20] + prev->Next = cur; + 800cc36: 69bb ldr r3, [r7, #24] + 800cc38: 697a ldr r2, [r7, #20] + 800cc3a: 615a str r2, [r3, #20] + break; + 800cc3c: e007 b.n 800cc4e + } + else + { + prev = cur; + 800cc3e: 697b ldr r3, [r7, #20] + 800cc40: 61bb str r3, [r7, #24] + cur = cur->Next; + 800cc42: 697b ldr r3, [r7, #20] + 800cc44: 695b ldr r3, [r3, #20] + 800cc46: 617b str r3, [r7, #20] + while( cur != NULL ) + 800cc48: 697b ldr r3, [r7, #20] + 800cc4a: 2b00 cmp r3, #0 + 800cc4c: d1e2 bne.n 800cc14 + } + } + } + ret = UTIL_TIMER_OK; + 800cc4e: 2300 movs r3, #0 + 800cc50: 77fb strb r3, [r7, #31] + 800cc52: 693b ldr r3, [r7, #16] + 800cc54: 60bb str r3, [r7, #8] + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 800cc56: 68bb ldr r3, [r7, #8] + 800cc58: f383 8810 msr PRIMASK, r3 +} + 800cc5c: e001 b.n 800cc62 + } + UTIL_TIMER_EXIT_CRITICAL_SECTION(); + } + else + { + ret = UTIL_TIMER_INVALID_PARAM; + 800cc5e: 2301 movs r3, #1 + 800cc60: 77fb strb r3, [r7, #31] + } + return ret; + 800cc62: 7ffb ldrb r3, [r7, #31] +} + 800cc64: 4618 mov r0, r3 + 800cc66: 3720 adds r7, #32 + 800cc68: 46bd mov sp, r7 + 800cc6a: bd80 pop {r7, pc} + 800cc6c: 200009cc .word 0x200009cc + 800cc70: 0800d968 .word 0x0800d968 + +0800cc74 : + +UTIL_TIMER_Status_t UTIL_TIMER_SetPeriod(UTIL_TIMER_Object_t *TimerObject, uint32_t NewPeriodValue) +{ + 800cc74: b580 push {r7, lr} + 800cc76: b084 sub sp, #16 + 800cc78: af00 add r7, sp, #0 + 800cc7a: 6078 str r0, [r7, #4] + 800cc7c: 6039 str r1, [r7, #0] + UTIL_TIMER_Status_t ret = UTIL_TIMER_OK; + 800cc7e: 2300 movs r3, #0 + 800cc80: 73fb strb r3, [r7, #15] + + if(NULL == TimerObject) + 800cc82: 687b ldr r3, [r7, #4] + 800cc84: 2b00 cmp r3, #0 + 800cc86: d102 bne.n 800cc8e + { + ret = UTIL_TIMER_INVALID_PARAM; + 800cc88: 2301 movs r3, #1 + 800cc8a: 73fb strb r3, [r7, #15] + 800cc8c: e014 b.n 800ccb8 + } + else + { + TimerObject->ReloadValue = UTIL_TimerDriver.ms2Tick(NewPeriodValue); + 800cc8e: 4b0d ldr r3, [pc, #52] @ (800ccc4 ) + 800cc90: 6a5b ldr r3, [r3, #36] @ 0x24 + 800cc92: 6838 ldr r0, [r7, #0] + 800cc94: 4798 blx r3 + 800cc96: 4602 mov r2, r0 + 800cc98: 687b ldr r3, [r7, #4] + 800cc9a: 605a str r2, [r3, #4] + if(TimerExists(TimerObject)) + 800cc9c: 6878 ldr r0, [r7, #4] + 800cc9e: f000 f8c1 bl 800ce24 + 800cca2: 4603 mov r3, r0 + 800cca4: 2b00 cmp r3, #0 + 800cca6: d007 beq.n 800ccb8 + { + (void)UTIL_TIMER_Stop(TimerObject); + 800cca8: 6878 ldr r0, [r7, #4] + 800ccaa: f7ff ff73 bl 800cb94 + ret = UTIL_TIMER_Start(TimerObject); + 800ccae: 6878 ldr r0, [r7, #4] + 800ccb0: f7ff ff02 bl 800cab8 + 800ccb4: 4603 mov r3, r0 + 800ccb6: 73fb strb r3, [r7, #15] + } + } + return ret; + 800ccb8: 7bfb ldrb r3, [r7, #15] +} + 800ccba: 4618 mov r0, r3 + 800ccbc: 3710 adds r7, #16 + 800ccbe: 46bd mov sp, r7 + 800ccc0: bd80 pop {r7, pc} + 800ccc2: bf00 nop + 800ccc4: 0800d968 .word 0x0800d968 + +0800ccc8 : + } + return NextTimer; +} + +void UTIL_TIMER_IRQ_Handler( void ) +{ + 800ccc8: b590 push {r4, r7, lr} + 800ccca: b089 sub sp, #36 @ 0x24 + 800cccc: af00 add r7, sp, #0 + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 800ccce: f3ef 8310 mrs r3, PRIMASK + 800ccd2: 60bb str r3, [r7, #8] + return(result); + 800ccd4: 68bb ldr r3, [r7, #8] + UTIL_TIMER_Object_t* cur; + uint32_t old, now, DeltaContext; + + UTIL_TIMER_ENTER_CRITICAL_SECTION(); + 800ccd6: 61bb str r3, [r7, #24] + __ASM volatile ("cpsid i" : : : "memory"); + 800ccd8: b672 cpsid i +} + 800ccda: bf00 nop + + old = UTIL_TimerDriver.GetTimerContext( ); + 800ccdc: 4b38 ldr r3, [pc, #224] @ (800cdc0 ) + 800ccde: 695b ldr r3, [r3, #20] + 800cce0: 4798 blx r3 + 800cce2: 6178 str r0, [r7, #20] + now = UTIL_TimerDriver.SetTimerContext( ); + 800cce4: 4b36 ldr r3, [pc, #216] @ (800cdc0 ) + 800cce6: 691b ldr r3, [r3, #16] + 800cce8: 4798 blx r3 + 800ccea: 6138 str r0, [r7, #16] + + DeltaContext = now - old; /*intentional wrap around */ + 800ccec: 693a ldr r2, [r7, #16] + 800ccee: 697b ldr r3, [r7, #20] + 800ccf0: 1ad3 subs r3, r2, r3 + 800ccf2: 60fb str r3, [r7, #12] + + /* update timeStamp based upon new Time Reference*/ + /* because delta context should never exceed 2^32*/ + if ( TimerListHead != NULL ) + 800ccf4: 4b33 ldr r3, [pc, #204] @ (800cdc4 ) + 800ccf6: 681b ldr r3, [r3, #0] + 800ccf8: 2b00 cmp r3, #0 + 800ccfa: d037 beq.n 800cd6c + { + cur = TimerListHead; + 800ccfc: 4b31 ldr r3, [pc, #196] @ (800cdc4 ) + 800ccfe: 681b ldr r3, [r3, #0] + 800cd00: 61fb str r3, [r7, #28] + do { + if (cur->Timestamp > DeltaContext) + 800cd02: 69fb ldr r3, [r7, #28] + 800cd04: 681b ldr r3, [r3, #0] + 800cd06: 68fa ldr r2, [r7, #12] + 800cd08: 429a cmp r2, r3 + 800cd0a: d206 bcs.n 800cd1a + { + cur->Timestamp -= DeltaContext; + 800cd0c: 69fb ldr r3, [r7, #28] + 800cd0e: 681a ldr r2, [r3, #0] + 800cd10: 68fb ldr r3, [r7, #12] + 800cd12: 1ad2 subs r2, r2, r3 + 800cd14: 69fb ldr r3, [r7, #28] + 800cd16: 601a str r2, [r3, #0] + 800cd18: e002 b.n 800cd20 + } + else + { + cur->Timestamp = 0; + 800cd1a: 69fb ldr r3, [r7, #28] + 800cd1c: 2200 movs r2, #0 + 800cd1e: 601a str r2, [r3, #0] + } + cur = cur->Next; + 800cd20: 69fb ldr r3, [r7, #28] + 800cd22: 695b ldr r3, [r3, #20] + 800cd24: 61fb str r3, [r7, #28] + } while(cur != NULL); + 800cd26: 69fb ldr r3, [r7, #28] + 800cd28: 2b00 cmp r3, #0 + 800cd2a: d1ea bne.n 800cd02 + } + + /* Execute expired timer and update the list */ + while ((TimerListHead != NULL) && ((TimerListHead->Timestamp == 0U) || (TimerListHead->Timestamp < UTIL_TimerDriver.GetTimerElapsedTime( )))) + 800cd2c: e01e b.n 800cd6c + { + cur = TimerListHead; + 800cd2e: 4b25 ldr r3, [pc, #148] @ (800cdc4 ) + 800cd30: 681b ldr r3, [r3, #0] + 800cd32: 61fb str r3, [r7, #28] + TimerListHead = TimerListHead->Next; + 800cd34: 4b23 ldr r3, [pc, #140] @ (800cdc4 ) + 800cd36: 681b ldr r3, [r3, #0] + 800cd38: 695b ldr r3, [r3, #20] + 800cd3a: 4a22 ldr r2, [pc, #136] @ (800cdc4 ) + 800cd3c: 6013 str r3, [r2, #0] + cur->IsPending = 0; + 800cd3e: 69fb ldr r3, [r7, #28] + 800cd40: 2200 movs r2, #0 + 800cd42: 721a strb r2, [r3, #8] + cur->IsRunning = 0; + 800cd44: 69fb ldr r3, [r7, #28] + 800cd46: 2200 movs r2, #0 + 800cd48: 725a strb r2, [r3, #9] + cur->Callback(cur->argument); + 800cd4a: 69fb ldr r3, [r7, #28] + 800cd4c: 68db ldr r3, [r3, #12] + 800cd4e: 69fa ldr r2, [r7, #28] + 800cd50: 6912 ldr r2, [r2, #16] + 800cd52: 4610 mov r0, r2 + 800cd54: 4798 blx r3 + if(( cur->Mode == UTIL_TIMER_PERIODIC) && (cur->IsReloadStopped == 0U)) + 800cd56: 69fb ldr r3, [r7, #28] + 800cd58: 7adb ldrb r3, [r3, #11] + 800cd5a: 2b01 cmp r3, #1 + 800cd5c: d106 bne.n 800cd6c + 800cd5e: 69fb ldr r3, [r7, #28] + 800cd60: 7a9b ldrb r3, [r3, #10] + 800cd62: 2b00 cmp r3, #0 + 800cd64: d102 bne.n 800cd6c + { + (void)UTIL_TIMER_Start(cur); + 800cd66: 69f8 ldr r0, [r7, #28] + 800cd68: f7ff fea6 bl 800cab8 + while ((TimerListHead != NULL) && ((TimerListHead->Timestamp == 0U) || (TimerListHead->Timestamp < UTIL_TimerDriver.GetTimerElapsedTime( )))) + 800cd6c: 4b15 ldr r3, [pc, #84] @ (800cdc4 ) + 800cd6e: 681b ldr r3, [r3, #0] + 800cd70: 2b00 cmp r3, #0 + 800cd72: d00d beq.n 800cd90 + 800cd74: 4b13 ldr r3, [pc, #76] @ (800cdc4 ) + 800cd76: 681b ldr r3, [r3, #0] + 800cd78: 681b ldr r3, [r3, #0] + 800cd7a: 2b00 cmp r3, #0 + 800cd7c: d0d7 beq.n 800cd2e + 800cd7e: 4b11 ldr r3, [pc, #68] @ (800cdc4 ) + 800cd80: 681b ldr r3, [r3, #0] + 800cd82: 681c ldr r4, [r3, #0] + 800cd84: 4b0e ldr r3, [pc, #56] @ (800cdc0 ) + 800cd86: 699b ldr r3, [r3, #24] + 800cd88: 4798 blx r3 + 800cd8a: 4603 mov r3, r0 + 800cd8c: 429c cmp r4, r3 + 800cd8e: d3ce bcc.n 800cd2e + } + } + + /* start the next TimerListHead if it exists and it is not pending*/ + if(( TimerListHead != NULL ) && (TimerListHead->IsPending == 0U)) + 800cd90: 4b0c ldr r3, [pc, #48] @ (800cdc4 ) + 800cd92: 681b ldr r3, [r3, #0] + 800cd94: 2b00 cmp r3, #0 + 800cd96: d009 beq.n 800cdac + 800cd98: 4b0a ldr r3, [pc, #40] @ (800cdc4 ) + 800cd9a: 681b ldr r3, [r3, #0] + 800cd9c: 7a1b ldrb r3, [r3, #8] + 800cd9e: 2b00 cmp r3, #0 + 800cda0: d104 bne.n 800cdac + { + TimerSetTimeout( TimerListHead ); + 800cda2: 4b08 ldr r3, [pc, #32] @ (800cdc4 ) + 800cda4: 681b ldr r3, [r3, #0] + 800cda6: 4618 mov r0, r3 + 800cda8: f000 f858 bl 800ce5c + 800cdac: 69bb ldr r3, [r7, #24] + 800cdae: 607b str r3, [r7, #4] + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 800cdb0: 687b ldr r3, [r7, #4] + 800cdb2: f383 8810 msr PRIMASK, r3 +} + 800cdb6: bf00 nop + } + UTIL_TIMER_EXIT_CRITICAL_SECTION(); +} + 800cdb8: bf00 nop + 800cdba: 3724 adds r7, #36 @ 0x24 + 800cdbc: 46bd mov sp, r7 + 800cdbe: bd90 pop {r4, r7, pc} + 800cdc0: 0800d968 .word 0x0800d968 + 800cdc4: 200009cc .word 0x200009cc + +0800cdc8 : + +UTIL_TIMER_Time_t UTIL_TIMER_GetCurrentTime(void) +{ + 800cdc8: b580 push {r7, lr} + 800cdca: b082 sub sp, #8 + 800cdcc: af00 add r7, sp, #0 + uint32_t now = UTIL_TimerDriver.GetTimerValue( ); + 800cdce: 4b06 ldr r3, [pc, #24] @ (800cde8 ) + 800cdd0: 69db ldr r3, [r3, #28] + 800cdd2: 4798 blx r3 + 800cdd4: 6078 str r0, [r7, #4] + return UTIL_TimerDriver.Tick2ms(now); + 800cdd6: 4b04 ldr r3, [pc, #16] @ (800cde8 ) + 800cdd8: 6a9b ldr r3, [r3, #40] @ 0x28 + 800cdda: 6878 ldr r0, [r7, #4] + 800cddc: 4798 blx r3 + 800cdde: 4603 mov r3, r0 +} + 800cde0: 4618 mov r0, r3 + 800cde2: 3708 adds r7, #8 + 800cde4: 46bd mov sp, r7 + 800cde6: bd80 pop {r7, pc} + 800cde8: 0800d968 .word 0x0800d968 + +0800cdec : + +UTIL_TIMER_Time_t UTIL_TIMER_GetElapsedTime(UTIL_TIMER_Time_t past ) +{ + 800cdec: b580 push {r7, lr} + 800cdee: b084 sub sp, #16 + 800cdf0: af00 add r7, sp, #0 + 800cdf2: 6078 str r0, [r7, #4] + uint32_t nowInTicks = UTIL_TimerDriver.GetTimerValue( ); + 800cdf4: 4b0a ldr r3, [pc, #40] @ (800ce20 ) + 800cdf6: 69db ldr r3, [r3, #28] + 800cdf8: 4798 blx r3 + 800cdfa: 60f8 str r0, [r7, #12] + uint32_t pastInTicks = UTIL_TimerDriver.ms2Tick( past ); + 800cdfc: 4b08 ldr r3, [pc, #32] @ (800ce20 ) + 800cdfe: 6a5b ldr r3, [r3, #36] @ 0x24 + 800ce00: 6878 ldr r0, [r7, #4] + 800ce02: 4798 blx r3 + 800ce04: 60b8 str r0, [r7, #8] + /* intentional wrap around. Works Ok if tick duation below 1ms */ + return UTIL_TimerDriver.Tick2ms( nowInTicks- pastInTicks ); + 800ce06: 4b06 ldr r3, [pc, #24] @ (800ce20 ) + 800ce08: 6a9b ldr r3, [r3, #40] @ 0x28 + 800ce0a: 68f9 ldr r1, [r7, #12] + 800ce0c: 68ba ldr r2, [r7, #8] + 800ce0e: 1a8a subs r2, r1, r2 + 800ce10: 4610 mov r0, r2 + 800ce12: 4798 blx r3 + 800ce14: 4603 mov r3, r0 +} + 800ce16: 4618 mov r0, r3 + 800ce18: 3710 adds r7, #16 + 800ce1a: 46bd mov sp, r7 + 800ce1c: bd80 pop {r7, pc} + 800ce1e: bf00 nop + 800ce20: 0800d968 .word 0x0800d968 + +0800ce24 : + * + * @param TimerObject Structure containing the timer object parameters + * @retval 1 (the object is already in the list) or 0 + */ +bool TimerExists( UTIL_TIMER_Object_t *TimerObject ) +{ + 800ce24: b480 push {r7} + 800ce26: b085 sub sp, #20 + 800ce28: af00 add r7, sp, #0 + 800ce2a: 6078 str r0, [r7, #4] + UTIL_TIMER_Object_t* cur = TimerListHead; + 800ce2c: 4b0a ldr r3, [pc, #40] @ (800ce58 ) + 800ce2e: 681b ldr r3, [r3, #0] + 800ce30: 60fb str r3, [r7, #12] + + while( cur != NULL ) + 800ce32: e008 b.n 800ce46 + { + if( cur == TimerObject ) + 800ce34: 68fa ldr r2, [r7, #12] + 800ce36: 687b ldr r3, [r7, #4] + 800ce38: 429a cmp r2, r3 + 800ce3a: d101 bne.n 800ce40 + { + return true; + 800ce3c: 2301 movs r3, #1 + 800ce3e: e006 b.n 800ce4e + } + cur = cur->Next; + 800ce40: 68fb ldr r3, [r7, #12] + 800ce42: 695b ldr r3, [r3, #20] + 800ce44: 60fb str r3, [r7, #12] + while( cur != NULL ) + 800ce46: 68fb ldr r3, [r7, #12] + 800ce48: 2b00 cmp r3, #0 + 800ce4a: d1f3 bne.n 800ce34 + } + return false; + 800ce4c: 2300 movs r3, #0 +} + 800ce4e: 4618 mov r0, r3 + 800ce50: 3714 adds r7, #20 + 800ce52: 46bd mov sp, r7 + 800ce54: bc80 pop {r7} + 800ce56: 4770 bx lr + 800ce58: 200009cc .word 0x200009cc + +0800ce5c : + * @brief Sets a timeout with the duration "timestamp" + * + * @param TimerObject Structure containing the timer object parameters + */ +void TimerSetTimeout( UTIL_TIMER_Object_t *TimerObject ) +{ + 800ce5c: b590 push {r4, r7, lr} + 800ce5e: b085 sub sp, #20 + 800ce60: af00 add r7, sp, #0 + 800ce62: 6078 str r0, [r7, #4] + uint32_t minTicks= UTIL_TimerDriver.GetMinimumTimeout( ); + 800ce64: 4b11 ldr r3, [pc, #68] @ (800ceac ) + 800ce66: 6a1b ldr r3, [r3, #32] + 800ce68: 4798 blx r3 + 800ce6a: 60f8 str r0, [r7, #12] + TimerObject->IsPending = 1; + 800ce6c: 687b ldr r3, [r7, #4] + 800ce6e: 2201 movs r2, #1 + 800ce70: 721a strb r2, [r3, #8] + + /* In case deadline too soon */ + if(TimerObject->Timestamp < (UTIL_TimerDriver.GetTimerElapsedTime( ) + minTicks) ) + 800ce72: 687b ldr r3, [r7, #4] + 800ce74: 681c ldr r4, [r3, #0] + 800ce76: 4b0d ldr r3, [pc, #52] @ (800ceac ) + 800ce78: 699b ldr r3, [r3, #24] + 800ce7a: 4798 blx r3 + 800ce7c: 4602 mov r2, r0 + 800ce7e: 68fb ldr r3, [r7, #12] + 800ce80: 4413 add r3, r2 + 800ce82: 429c cmp r4, r3 + 800ce84: d207 bcs.n 800ce96 + { + TimerObject->Timestamp = UTIL_TimerDriver.GetTimerElapsedTime( ) + minTicks; + 800ce86: 4b09 ldr r3, [pc, #36] @ (800ceac ) + 800ce88: 699b ldr r3, [r3, #24] + 800ce8a: 4798 blx r3 + 800ce8c: 4602 mov r2, r0 + 800ce8e: 68fb ldr r3, [r7, #12] + 800ce90: 441a add r2, r3 + 800ce92: 687b ldr r3, [r7, #4] + 800ce94: 601a str r2, [r3, #0] + } + UTIL_TimerDriver.StartTimerEvt( TimerObject->Timestamp ); + 800ce96: 4b05 ldr r3, [pc, #20] @ (800ceac ) + 800ce98: 689b ldr r3, [r3, #8] + 800ce9a: 687a ldr r2, [r7, #4] + 800ce9c: 6812 ldr r2, [r2, #0] + 800ce9e: 4610 mov r0, r2 + 800cea0: 4798 blx r3 +} + 800cea2: bf00 nop + 800cea4: 3714 adds r7, #20 + 800cea6: 46bd mov sp, r7 + 800cea8: bd90 pop {r4, r7, pc} + 800ceaa: bf00 nop + 800ceac: 0800d968 .word 0x0800d968 + +0800ceb0 : + * next timer to expire. + * + * @param TimerObject Structure containing the timer object parameters + */ +void TimerInsertTimer( UTIL_TIMER_Object_t *TimerObject) +{ + 800ceb0: b480 push {r7} + 800ceb2: b085 sub sp, #20 + 800ceb4: af00 add r7, sp, #0 + 800ceb6: 6078 str r0, [r7, #4] + UTIL_TIMER_Object_t* cur = TimerListHead; + 800ceb8: 4b14 ldr r3, [pc, #80] @ (800cf0c ) + 800ceba: 681b ldr r3, [r3, #0] + 800cebc: 60fb str r3, [r7, #12] + UTIL_TIMER_Object_t* next = TimerListHead->Next; + 800cebe: 4b13 ldr r3, [pc, #76] @ (800cf0c ) + 800cec0: 681b ldr r3, [r3, #0] + 800cec2: 695b ldr r3, [r3, #20] + 800cec4: 60bb str r3, [r7, #8] + + while (cur->Next != NULL ) + 800cec6: e012 b.n 800ceee + { + if( TimerObject->Timestamp > next->Timestamp ) + 800cec8: 687b ldr r3, [r7, #4] + 800ceca: 681a ldr r2, [r3, #0] + 800cecc: 68bb ldr r3, [r7, #8] + 800cece: 681b ldr r3, [r3, #0] + 800ced0: 429a cmp r2, r3 + 800ced2: d905 bls.n 800cee0 + { + cur = next; + 800ced4: 68bb ldr r3, [r7, #8] + 800ced6: 60fb str r3, [r7, #12] + next = next->Next; + 800ced8: 68bb ldr r3, [r7, #8] + 800ceda: 695b ldr r3, [r3, #20] + 800cedc: 60bb str r3, [r7, #8] + 800cede: e006 b.n 800ceee + } + else + { + cur->Next = TimerObject; + 800cee0: 68fb ldr r3, [r7, #12] + 800cee2: 687a ldr r2, [r7, #4] + 800cee4: 615a str r2, [r3, #20] + TimerObject->Next = next; + 800cee6: 687b ldr r3, [r7, #4] + 800cee8: 68ba ldr r2, [r7, #8] + 800ceea: 615a str r2, [r3, #20] + return; + 800ceec: e009 b.n 800cf02 + while (cur->Next != NULL ) + 800ceee: 68fb ldr r3, [r7, #12] + 800cef0: 695b ldr r3, [r3, #20] + 800cef2: 2b00 cmp r3, #0 + 800cef4: d1e8 bne.n 800cec8 + + } + } + cur->Next = TimerObject; + 800cef6: 68fb ldr r3, [r7, #12] + 800cef8: 687a ldr r2, [r7, #4] + 800cefa: 615a str r2, [r3, #20] + TimerObject->Next = NULL; + 800cefc: 687b ldr r3, [r7, #4] + 800cefe: 2200 movs r2, #0 + 800cf00: 615a str r2, [r3, #20] +} + 800cf02: 3714 adds r7, #20 + 800cf04: 46bd mov sp, r7 + 800cf06: bc80 pop {r7} + 800cf08: 4770 bx lr + 800cf0a: bf00 nop + 800cf0c: 200009cc .word 0x200009cc + +0800cf10 : + * + * @remark The list is automatically sorted. The list head always contains the + * next timer to expire. + */ +void TimerInsertNewHeadTimer( UTIL_TIMER_Object_t *TimerObject ) +{ + 800cf10: b580 push {r7, lr} + 800cf12: b084 sub sp, #16 + 800cf14: af00 add r7, sp, #0 + 800cf16: 6078 str r0, [r7, #4] + UTIL_TIMER_Object_t* cur = TimerListHead; + 800cf18: 4b0b ldr r3, [pc, #44] @ (800cf48 ) + 800cf1a: 681b ldr r3, [r3, #0] + 800cf1c: 60fb str r3, [r7, #12] + + if( cur != NULL ) + 800cf1e: 68fb ldr r3, [r7, #12] + 800cf20: 2b00 cmp r3, #0 + 800cf22: d002 beq.n 800cf2a + { + cur->IsPending = 0; + 800cf24: 68fb ldr r3, [r7, #12] + 800cf26: 2200 movs r2, #0 + 800cf28: 721a strb r2, [r3, #8] + } + + TimerObject->Next = cur; + 800cf2a: 687b ldr r3, [r7, #4] + 800cf2c: 68fa ldr r2, [r7, #12] + 800cf2e: 615a str r2, [r3, #20] + TimerListHead = TimerObject; + 800cf30: 4a05 ldr r2, [pc, #20] @ (800cf48 ) + 800cf32: 687b ldr r3, [r7, #4] + 800cf34: 6013 str r3, [r2, #0] + TimerSetTimeout( TimerListHead ); + 800cf36: 4b04 ldr r3, [pc, #16] @ (800cf48 ) + 800cf38: 681b ldr r3, [r3, #0] + 800cf3a: 4618 mov r0, r3 + 800cf3c: f7ff ff8e bl 800ce5c +} + 800cf40: bf00 nop + 800cf42: 3710 adds r7, #16 + 800cf44: 46bd mov sp, r7 + 800cf46: bd80 pop {r7, pc} + 800cf48: 200009cc .word 0x200009cc + +0800cf4c : + +/** @addtogroup ADV_TRACE_exported_function + * @{ + */ +UTIL_ADV_TRACE_Status_t UTIL_ADV_TRACE_Init(void) +{ + 800cf4c: b580 push {r7, lr} + 800cf4e: af00 add r7, sp, #0 + /* initialize the Ptr for Read/Write */ + (void)UTIL_ADV_TRACE_MEMSET8(&ADV_TRACE_Ctx, 0x0, sizeof(ADV_TRACE_Context)); + 800cf50: 2218 movs r2, #24 + 800cf52: 2100 movs r1, #0 + 800cf54: 4807 ldr r0, [pc, #28] @ (800cf74 ) + 800cf56: f7ff f8e8 bl 800c12a + (void)UTIL_ADV_TRACE_MEMSET8(&ADV_TRACE_Buffer, 0x0, sizeof(ADV_TRACE_Buffer)); + 800cf5a: f44f 7200 mov.w r2, #512 @ 0x200 + 800cf5e: 2100 movs r1, #0 + 800cf60: 4805 ldr r0, [pc, #20] @ (800cf78 ) + 800cf62: f7ff f8e2 bl 800c12a +#endif + /* Allocate Lock resource */ + UTIL_ADV_TRACE_INIT_CRITICAL_SECTION(); + + /* Initialize the Low Level interface */ + return UTIL_TraceDriver.Init(TRACE_TxCpltCallback); + 800cf66: 4b05 ldr r3, [pc, #20] @ (800cf7c ) + 800cf68: 681b ldr r3, [r3, #0] + 800cf6a: 4805 ldr r0, [pc, #20] @ (800cf80 ) + 800cf6c: 4798 blx r3 + 800cf6e: 4603 mov r3, r0 +} + 800cf70: 4618 mov r0, r3 + 800cf72: bd80 pop {r7, pc} + 800cf74: 200009d0 .word 0x200009d0 + 800cf78: 200009e8 .word 0x200009e8 + 800cf7c: 0800d9a8 .word 0x0800d9a8 + 800cf80: 0800d1c9 .word 0x0800d1c9 + +0800cf84 : + return UTIL_TraceDriver.StartRx(UserCallback); +} + +#if defined(UTIL_ADV_TRACE_CONDITIONNAL) +UTIL_ADV_TRACE_Status_t UTIL_ADV_TRACE_COND_FSend(uint32_t VerboseLevel, uint32_t Region, uint32_t TimeStampState, const char *strFormat, ...) +{ + 800cf84: b408 push {r3} + 800cf86: b580 push {r7, lr} + 800cf88: b08d sub sp, #52 @ 0x34 + 800cf8a: af00 add r7, sp, #0 + 800cf8c: 60f8 str r0, [r7, #12] + 800cf8e: 60b9 str r1, [r7, #8] + 800cf90: 607a str r2, [r7, #4] + va_list vaArgs; +#if defined(UTIL_ADV_TRACE_UNCHUNK_MODE) + uint8_t buf[UTIL_ADV_TRACE_TMP_MAX_TIMESTMAP_SIZE]; + uint16_t timestamp_size = 0u; + 800cf92: 2300 movs r3, #0 + 800cf94: 82fb strh r3, [r7, #22] + uint16_t writepos; + uint16_t idx; +#else + uint8_t buf[UTIL_ADV_TRACE_TMP_BUF_SIZE+UTIL_ADV_TRACE_TMP_MAX_TIMESTMAP_SIZE]; +#endif + uint16_t buff_size = 0u; + 800cf96: 2300 movs r3, #0 + 800cf98: 85bb strh r3, [r7, #44] @ 0x2c + + /* check verbose level */ + if(!(ADV_TRACE_Ctx.CurrentVerboseLevel >= VerboseLevel)) + 800cf9a: 4b37 ldr r3, [pc, #220] @ (800d078 ) + 800cf9c: 7a1b ldrb r3, [r3, #8] + 800cf9e: 461a mov r2, r3 + 800cfa0: 68fb ldr r3, [r7, #12] + 800cfa2: 4293 cmp r3, r2 + 800cfa4: d902 bls.n 800cfac + { + return UTIL_ADV_TRACE_GIVEUP; + 800cfa6: f06f 0304 mvn.w r3, #4 + 800cfaa: e05e b.n 800d06a + } + + if((Region & ADV_TRACE_Ctx.RegionMask) != Region) + 800cfac: 4b32 ldr r3, [pc, #200] @ (800d078 ) + 800cfae: 68da ldr r2, [r3, #12] + 800cfb0: 68bb ldr r3, [r7, #8] + 800cfb2: 4013 ands r3, r2 + 800cfb4: 68ba ldr r2, [r7, #8] + 800cfb6: 429a cmp r2, r3 + 800cfb8: d002 beq.n 800cfc0 + { + return UTIL_ADV_TRACE_REGIONMASKED; + 800cfba: f06f 0305 mvn.w r3, #5 + 800cfbe: e054 b.n 800d06a + } + +#if defined(UTIL_ADV_TRACE_UNCHUNK_MODE) + if((ADV_TRACE_Ctx.timestamp_func != NULL) && (TimeStampState != 0u)) + 800cfc0: 4b2d ldr r3, [pc, #180] @ (800d078 ) + 800cfc2: 685b ldr r3, [r3, #4] + 800cfc4: 2b00 cmp r3, #0 + 800cfc6: d00a beq.n 800cfde + 800cfc8: 687b ldr r3, [r7, #4] + 800cfca: 2b00 cmp r3, #0 + 800cfcc: d007 beq.n 800cfde + { + ADV_TRACE_Ctx.timestamp_func(buf,×tamp_size); + 800cfce: 4b2a ldr r3, [pc, #168] @ (800d078 ) + 800cfd0: 685b ldr r3, [r3, #4] + 800cfd2: f107 0116 add.w r1, r7, #22 + 800cfd6: f107 0218 add.w r2, r7, #24 + 800cfda: 4610 mov r0, r2 + 800cfdc: 4798 blx r3 + } + + va_start( vaArgs, strFormat); + 800cfde: f107 0340 add.w r3, r7, #64 @ 0x40 + 800cfe2: 62bb str r3, [r7, #40] @ 0x28 + buff_size =(uint16_t)UTIL_ADV_TRACE_VSNPRINTF((char *)sztmp,UTIL_ADV_TRACE_TMP_BUF_SIZE, strFormat, vaArgs); + 800cfe4: 6abb ldr r3, [r7, #40] @ 0x28 + 800cfe6: 6bfa ldr r2, [r7, #60] @ 0x3c + 800cfe8: f44f 7180 mov.w r1, #256 @ 0x100 + 800cfec: 4823 ldr r0, [pc, #140] @ (800d07c ) + 800cfee: f7ff fa3d bl 800c46c + 800cff2: 4603 mov r3, r0 + 800cff4: 85bb strh r3, [r7, #44] @ 0x2c + + TRACE_Lock(); + 800cff6: f000 f9f1 bl 800d3dc + + /* if allocation is ok, write data into the buffer */ + if (TRACE_AllocateBufer((buff_size+timestamp_size),&writepos) != -1) + 800cffa: 8afa ldrh r2, [r7, #22] + 800cffc: 8dbb ldrh r3, [r7, #44] @ 0x2c + 800cffe: 4413 add r3, r2 + 800d000: b29b uxth r3, r3 + 800d002: f107 0214 add.w r2, r7, #20 + 800d006: 4611 mov r1, r2 + 800d008: 4618 mov r0, r3 + 800d00a: f000 f969 bl 800d2e0 + 800d00e: 4603 mov r3, r0 + 800d010: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff + 800d014: d025 beq.n 800d062 + } + UTIL_ADV_TRACE_EXIT_CRITICAL_SECTION(); +#endif + + /* copy the timestamp */ + for (idx = 0u; idx < timestamp_size; idx++) + 800d016: 2300 movs r3, #0 + 800d018: 85fb strh r3, [r7, #46] @ 0x2e + 800d01a: e00e b.n 800d03a + { + ADV_TRACE_Buffer[writepos] = buf[idx]; + 800d01c: 8dfb ldrh r3, [r7, #46] @ 0x2e + 800d01e: 8aba ldrh r2, [r7, #20] + 800d020: 3330 adds r3, #48 @ 0x30 + 800d022: 443b add r3, r7 + 800d024: f813 1c18 ldrb.w r1, [r3, #-24] + 800d028: 4b15 ldr r3, [pc, #84] @ (800d080 ) + 800d02a: 5499 strb r1, [r3, r2] + writepos = writepos + 1u; + 800d02c: 8abb ldrh r3, [r7, #20] + 800d02e: 3301 adds r3, #1 + 800d030: b29b uxth r3, r3 + 800d032: 82bb strh r3, [r7, #20] + for (idx = 0u; idx < timestamp_size; idx++) + 800d034: 8dfb ldrh r3, [r7, #46] @ 0x2e + 800d036: 3301 adds r3, #1 + 800d038: 85fb strh r3, [r7, #46] @ 0x2e + 800d03a: 8afb ldrh r3, [r7, #22] + 800d03c: 8dfa ldrh r2, [r7, #46] @ 0x2e + 800d03e: 429a cmp r2, r3 + 800d040: d3ec bcc.n 800d01c + } + + /* copy the data */ + (void)UTIL_ADV_TRACE_VSNPRINTF((char *)(&ADV_TRACE_Buffer[writepos]), UTIL_ADV_TRACE_TMP_BUF_SIZE, strFormat, vaArgs); + 800d042: 8abb ldrh r3, [r7, #20] + 800d044: 461a mov r2, r3 + 800d046: 4b0e ldr r3, [pc, #56] @ (800d080 ) + 800d048: 18d0 adds r0, r2, r3 + 800d04a: 6abb ldr r3, [r7, #40] @ 0x28 + 800d04c: 6bfa ldr r2, [r7, #60] @ 0x3c + 800d04e: f44f 7180 mov.w r1, #256 @ 0x100 + 800d052: f7ff fa0b bl 800c46c + va_end(vaArgs); + + TRACE_UnLock(); + 800d056: f000 f9df bl 800d418 + + return TRACE_Send(); + 800d05a: f000 f831 bl 800d0c0 + 800d05e: 4603 mov r3, r0 + 800d060: e003 b.n 800d06a + } + + va_end(vaArgs); + TRACE_UnLock(); + 800d062: f000 f9d9 bl 800d418 + ADV_TRACE_Ctx.OverRunStatus = TRACE_OVERRUN_INDICATION; + } + UTIL_ADV_TRACE_EXIT_CRITICAL_SECTION(); +#endif + + return UTIL_ADV_TRACE_MEM_FULL; + 800d066: f06f 0302 mvn.w r3, #2 + buff_size += (uint16_t) UTIL_ADV_TRACE_VSNPRINTF((char* )(buf + buff_size), UTIL_ADV_TRACE_TMP_BUF_SIZE, strFormat, vaArgs); + va_end(vaArgs); + + return UTIL_ADV_TRACE_Send(buf, buff_size); +#endif +} + 800d06a: 4618 mov r0, r3 + 800d06c: 3734 adds r7, #52 @ 0x34 + 800d06e: 46bd mov sp, r7 + 800d070: e8bd 4080 ldmia.w sp!, {r7, lr} + 800d074: b001 add sp, #4 + 800d076: 4770 bx lr + 800d078: 200009d0 .word 0x200009d0 + 800d07c: 20000be8 .word 0x20000be8 + 800d080: 200009e8 .word 0x200009e8 + +0800d084 : +} +#endif + +#if defined(UTIL_ADV_TRACE_CONDITIONNAL) +void UTIL_ADV_TRACE_RegisterTimeStampFunction(cb_timestamp *cb) +{ + 800d084: b480 push {r7} + 800d086: b083 sub sp, #12 + 800d088: af00 add r7, sp, #0 + 800d08a: 6078 str r0, [r7, #4] + ADV_TRACE_Ctx.timestamp_func = *cb; + 800d08c: 4a03 ldr r2, [pc, #12] @ (800d09c ) + 800d08e: 687b ldr r3, [r7, #4] + 800d090: 6053 str r3, [r2, #4] +} + 800d092: bf00 nop + 800d094: 370c adds r7, #12 + 800d096: 46bd mov sp, r7 + 800d098: bc80 pop {r7} + 800d09a: 4770 bx lr + 800d09c: 200009d0 .word 0x200009d0 + +0800d0a0 : + +void UTIL_ADV_TRACE_SetVerboseLevel(uint8_t Level) +{ + 800d0a0: b480 push {r7} + 800d0a2: b083 sub sp, #12 + 800d0a4: af00 add r7, sp, #0 + 800d0a6: 4603 mov r3, r0 + 800d0a8: 71fb strb r3, [r7, #7] + ADV_TRACE_Ctx.CurrentVerboseLevel = Level; + 800d0aa: 4a04 ldr r2, [pc, #16] @ (800d0bc ) + 800d0ac: 79fb ldrb r3, [r7, #7] + 800d0ae: 7213 strb r3, [r2, #8] +} + 800d0b0: bf00 nop + 800d0b2: 370c adds r7, #12 + 800d0b4: 46bd mov sp, r7 + 800d0b6: bc80 pop {r7} + 800d0b8: 4770 bx lr + 800d0ba: bf00 nop + 800d0bc: 200009d0 .word 0x200009d0 + +0800d0c0 : +/** + * @brief send the data of the trace to low layer + * @retval Status based on @ref UTIL_ADV_TRACE_Status_t + */ +static UTIL_ADV_TRACE_Status_t TRACE_Send(void) +{ + 800d0c0: b580 push {r7, lr} + 800d0c2: b088 sub sp, #32 + 800d0c4: af00 add r7, sp, #0 + UTIL_ADV_TRACE_Status_t ret = UTIL_ADV_TRACE_OK; + 800d0c6: 2300 movs r3, #0 + 800d0c8: 77fb strb r3, [r7, #31] + uint8_t *ptr = NULL; + 800d0ca: 2300 movs r3, #0 + 800d0cc: 61bb str r3, [r7, #24] + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 800d0ce: f3ef 8310 mrs r3, PRIMASK + 800d0d2: 613b str r3, [r7, #16] + return(result); + 800d0d4: 693b ldr r3, [r7, #16] + + UTIL_ADV_TRACE_ENTER_CRITICAL_SECTION(); + 800d0d6: 617b str r3, [r7, #20] + __ASM volatile ("cpsid i" : : : "memory"); + 800d0d8: b672 cpsid i +} + 800d0da: bf00 nop + + if(TRACE_IsLocked() == 0u) + 800d0dc: f000 f9ba bl 800d454 + 800d0e0: 4603 mov r3, r0 + 800d0e2: 2b00 cmp r3, #0 + 800d0e4: d15d bne.n 800d1a2 + { + TRACE_Lock(); + 800d0e6: f000 f979 bl 800d3dc + + if(ADV_TRACE_Ctx.TraceRdPtr != ADV_TRACE_Ctx.TraceWrPtr) + 800d0ea: 4b34 ldr r3, [pc, #208] @ (800d1bc ) + 800d0ec: 8a1a ldrh r2, [r3, #16] + 800d0ee: 4b33 ldr r3, [pc, #204] @ (800d1bc ) + 800d0f0: 8a5b ldrh r3, [r3, #18] + 800d0f2: 429a cmp r2, r3 + 800d0f4: d04d beq.n 800d192 + { +#ifdef UTIL_ADV_TRACE_UNCHUNK_MODE + if(TRACE_UNCHUNK_DETECTED == ADV_TRACE_Ctx.unchunk_status) + 800d0f6: 4b31 ldr r3, [pc, #196] @ (800d1bc ) + 800d0f8: 789b ldrb r3, [r3, #2] + 800d0fa: 2b01 cmp r3, #1 + 800d0fc: d117 bne.n 800d12e + { + ADV_TRACE_Ctx.TraceSentSize = (uint16_t) (ADV_TRACE_Ctx.unchunk_enabled - ADV_TRACE_Ctx.TraceRdPtr); + 800d0fe: 4b2f ldr r3, [pc, #188] @ (800d1bc ) + 800d100: 881a ldrh r2, [r3, #0] + 800d102: 4b2e ldr r3, [pc, #184] @ (800d1bc ) + 800d104: 8a1b ldrh r3, [r3, #16] + 800d106: 1ad3 subs r3, r2, r3 + 800d108: b29a uxth r2, r3 + 800d10a: 4b2c ldr r3, [pc, #176] @ (800d1bc ) + 800d10c: 829a strh r2, [r3, #20] + ADV_TRACE_Ctx.unchunk_status = TRACE_UNCHUNK_TRANSFER; + 800d10e: 4b2b ldr r3, [pc, #172] @ (800d1bc ) + 800d110: 2202 movs r2, #2 + 800d112: 709a strb r2, [r3, #2] + ADV_TRACE_Ctx.unchunk_enabled = 0; + 800d114: 4b29 ldr r3, [pc, #164] @ (800d1bc ) + 800d116: 2200 movs r2, #0 + 800d118: 801a strh r2, [r3, #0] + + UTIL_ADV_TRACE_DEBUG("\nTRACE_TxCpltCallback::unchunk start(%d,%d)\n", ADV_TRACE_Ctx.unchunk_enabled, ADV_TRACE_Ctx.TraceRdPtr); + + if(0u == ADV_TRACE_Ctx.TraceSentSize) + 800d11a: 4b28 ldr r3, [pc, #160] @ (800d1bc ) + 800d11c: 8a9b ldrh r3, [r3, #20] + 800d11e: 2b00 cmp r3, #0 + 800d120: d105 bne.n 800d12e + { + ADV_TRACE_Ctx.unchunk_status = TRACE_UNCHUNK_NONE; + 800d122: 4b26 ldr r3, [pc, #152] @ (800d1bc ) + 800d124: 2200 movs r2, #0 + 800d126: 709a strb r2, [r3, #2] + ADV_TRACE_Ctx.TraceRdPtr = 0; + 800d128: 4b24 ldr r3, [pc, #144] @ (800d1bc ) + 800d12a: 2200 movs r2, #0 + 800d12c: 821a strh r2, [r3, #16] + } + } + + if(TRACE_UNCHUNK_NONE == ADV_TRACE_Ctx.unchunk_status) + 800d12e: 4b23 ldr r3, [pc, #140] @ (800d1bc ) + 800d130: 789b ldrb r3, [r3, #2] + 800d132: 2b00 cmp r3, #0 + 800d134: d115 bne.n 800d162 + { +#endif + if(ADV_TRACE_Ctx.TraceWrPtr > ADV_TRACE_Ctx.TraceRdPtr) + 800d136: 4b21 ldr r3, [pc, #132] @ (800d1bc ) + 800d138: 8a5a ldrh r2, [r3, #18] + 800d13a: 4b20 ldr r3, [pc, #128] @ (800d1bc ) + 800d13c: 8a1b ldrh r3, [r3, #16] + 800d13e: 429a cmp r2, r3 + 800d140: d908 bls.n 800d154 + { + ADV_TRACE_Ctx.TraceSentSize = ADV_TRACE_Ctx.TraceWrPtr - ADV_TRACE_Ctx.TraceRdPtr; + 800d142: 4b1e ldr r3, [pc, #120] @ (800d1bc ) + 800d144: 8a5a ldrh r2, [r3, #18] + 800d146: 4b1d ldr r3, [pc, #116] @ (800d1bc ) + 800d148: 8a1b ldrh r3, [r3, #16] + 800d14a: 1ad3 subs r3, r2, r3 + 800d14c: b29a uxth r2, r3 + 800d14e: 4b1b ldr r3, [pc, #108] @ (800d1bc ) + 800d150: 829a strh r2, [r3, #20] + 800d152: e006 b.n 800d162 + } + else /* TraceRdPtr > TraceWrPtr */ + { + ADV_TRACE_Ctx.TraceSentSize = UTIL_ADV_TRACE_FIFO_SIZE - ADV_TRACE_Ctx.TraceRdPtr; + 800d154: 4b19 ldr r3, [pc, #100] @ (800d1bc ) + 800d156: 8a1b ldrh r3, [r3, #16] + 800d158: f5c3 7300 rsb r3, r3, #512 @ 0x200 + 800d15c: b29a uxth r2, r3 + 800d15e: 4b17 ldr r3, [pc, #92] @ (800d1bc ) + 800d160: 829a strh r2, [r3, #20] + + } +#ifdef UTIL_ADV_TRACE_UNCHUNK_MODE + } +#endif + ptr = &ADV_TRACE_Buffer[ADV_TRACE_Ctx.TraceRdPtr]; + 800d162: 4b16 ldr r3, [pc, #88] @ (800d1bc ) + 800d164: 8a1b ldrh r3, [r3, #16] + 800d166: 461a mov r2, r3 + 800d168: 4b15 ldr r3, [pc, #84] @ (800d1c0 ) + 800d16a: 4413 add r3, r2 + 800d16c: 61bb str r3, [r7, #24] + 800d16e: 697b ldr r3, [r7, #20] + 800d170: 60fb str r3, [r7, #12] + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 800d172: 68fb ldr r3, [r7, #12] + 800d174: f383 8810 msr PRIMASK, r3 +} + 800d178: bf00 nop + + UTIL_ADV_TRACE_EXIT_CRITICAL_SECTION(); + UTIL_ADV_TRACE_PreSendHook(); + 800d17a: f7f3 fcd1 bl 8000b20 + + UTIL_ADV_TRACE_DEBUG("\n--TRACE_Send(%d-%d)--\n", ADV_TRACE_Ctx.TraceRdPtr, ADV_TRACE_Ctx.TraceSentSize); + ret = UTIL_TraceDriver.Send(ptr, ADV_TRACE_Ctx.TraceSentSize); + 800d17e: 4b11 ldr r3, [pc, #68] @ (800d1c4 ) + 800d180: 68db ldr r3, [r3, #12] + 800d182: 4a0e ldr r2, [pc, #56] @ (800d1bc ) + 800d184: 8a92 ldrh r2, [r2, #20] + 800d186: 4611 mov r1, r2 + 800d188: 69b8 ldr r0, [r7, #24] + 800d18a: 4798 blx r3 + 800d18c: 4603 mov r3, r0 + 800d18e: 77fb strb r3, [r7, #31] + 800d190: e00d b.n 800d1ae + } + else + { + TRACE_UnLock(); + 800d192: f000 f941 bl 800d418 + 800d196: 697b ldr r3, [r7, #20] + 800d198: 60bb str r3, [r7, #8] + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 800d19a: 68bb ldr r3, [r7, #8] + 800d19c: f383 8810 msr PRIMASK, r3 +} + 800d1a0: e005 b.n 800d1ae + 800d1a2: 697b ldr r3, [r7, #20] + 800d1a4: 607b str r3, [r7, #4] + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 800d1a6: 687b ldr r3, [r7, #4] + 800d1a8: f383 8810 msr PRIMASK, r3 +} + 800d1ac: bf00 nop + else + { + UTIL_ADV_TRACE_EXIT_CRITICAL_SECTION(); + } + + return ret; + 800d1ae: f997 301f ldrsb.w r3, [r7, #31] +} + 800d1b2: 4618 mov r0, r3 + 800d1b4: 3720 adds r7, #32 + 800d1b6: 46bd mov sp, r7 + 800d1b8: bd80 pop {r7, pc} + 800d1ba: bf00 nop + 800d1bc: 200009d0 .word 0x200009d0 + 800d1c0: 200009e8 .word 0x200009e8 + 800d1c4: 0800d9a8 .word 0x0800d9a8 + +0800d1c8 : + * @brief Tx callback called by the low layer level to inform a transfer complete + * @param Ptr pointer not used only for HAL compatibility + * @retval none + */ +static void TRACE_TxCpltCallback(void *Ptr) +{ + 800d1c8: b580 push {r7, lr} + 800d1ca: b088 sub sp, #32 + 800d1cc: af00 add r7, sp, #0 + 800d1ce: 6078 str r0, [r7, #4] + uint8_t *ptr = NULL; + 800d1d0: 2300 movs r3, #0 + 800d1d2: 61fb str r3, [r7, #28] + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 800d1d4: f3ef 8310 mrs r3, PRIMASK + 800d1d8: 617b str r3, [r7, #20] + return(result); + 800d1da: 697b ldr r3, [r7, #20] + UTIL_ADV_TRACE_ENTER_CRITICAL_SECTION(); + 800d1dc: 61bb str r3, [r7, #24] + __ASM volatile ("cpsid i" : : : "memory"); + 800d1de: b672 cpsid i +} + 800d1e0: bf00 nop + ADV_TRACE_Ctx.TraceSentSize = 0u; + } +#endif + +#if defined(UTIL_ADV_TRACE_UNCHUNK_MODE) + if(TRACE_UNCHUNK_TRANSFER == ADV_TRACE_Ctx.unchunk_status) + 800d1e2: 4b3c ldr r3, [pc, #240] @ (800d2d4 ) + 800d1e4: 789b ldrb r3, [r3, #2] + 800d1e6: 2b02 cmp r3, #2 + 800d1e8: d106 bne.n 800d1f8 + { + ADV_TRACE_Ctx.unchunk_status = TRACE_UNCHUNK_NONE; + 800d1ea: 4b3a ldr r3, [pc, #232] @ (800d2d4 ) + 800d1ec: 2200 movs r2, #0 + 800d1ee: 709a strb r2, [r3, #2] + ADV_TRACE_Ctx.TraceRdPtr = 0; + 800d1f0: 4b38 ldr r3, [pc, #224] @ (800d2d4 ) + 800d1f2: 2200 movs r2, #0 + 800d1f4: 821a strh r2, [r3, #16] + 800d1f6: e00a b.n 800d20e + UTIL_ADV_TRACE_DEBUG("\nTRACE_TxCpltCallback::unchunk complete\n"); + } + else + { + ADV_TRACE_Ctx.TraceRdPtr = (ADV_TRACE_Ctx.TraceRdPtr + ADV_TRACE_Ctx.TraceSentSize) % UTIL_ADV_TRACE_FIFO_SIZE; + 800d1f8: 4b36 ldr r3, [pc, #216] @ (800d2d4 ) + 800d1fa: 8a1a ldrh r2, [r3, #16] + 800d1fc: 4b35 ldr r3, [pc, #212] @ (800d2d4 ) + 800d1fe: 8a9b ldrh r3, [r3, #20] + 800d200: 4413 add r3, r2 + 800d202: b29b uxth r3, r3 + 800d204: f3c3 0308 ubfx r3, r3, #0, #9 + 800d208: b29a uxth r2, r3 + 800d20a: 4b32 ldr r3, [pc, #200] @ (800d2d4 ) + 800d20c: 821a strh r2, [r3, #16] + UTIL_TraceDriver.Send(ptr, ADV_TRACE_Ctx.TraceSentSize); + return; + } +#endif + + if((ADV_TRACE_Ctx.TraceRdPtr != ADV_TRACE_Ctx.TraceWrPtr) && (1u == ADV_TRACE_Ctx.TraceLock)) + 800d20e: 4b31 ldr r3, [pc, #196] @ (800d2d4 ) + 800d210: 8a1a ldrh r2, [r3, #16] + 800d212: 4b30 ldr r3, [pc, #192] @ (800d2d4 ) + 800d214: 8a5b ldrh r3, [r3, #18] + 800d216: 429a cmp r2, r3 + 800d218: d04d beq.n 800d2b6 + 800d21a: 4b2e ldr r3, [pc, #184] @ (800d2d4 ) + 800d21c: 8adb ldrh r3, [r3, #22] + 800d21e: 2b01 cmp r3, #1 + 800d220: d149 bne.n 800d2b6 + { +#ifdef UTIL_ADV_TRACE_UNCHUNK_MODE + if(TRACE_UNCHUNK_DETECTED == ADV_TRACE_Ctx.unchunk_status) + 800d222: 4b2c ldr r3, [pc, #176] @ (800d2d4 ) + 800d224: 789b ldrb r3, [r3, #2] + 800d226: 2b01 cmp r3, #1 + 800d228: d117 bne.n 800d25a + { + ADV_TRACE_Ctx.TraceSentSize = ADV_TRACE_Ctx.unchunk_enabled - ADV_TRACE_Ctx.TraceRdPtr; + 800d22a: 4b2a ldr r3, [pc, #168] @ (800d2d4 ) + 800d22c: 881a ldrh r2, [r3, #0] + 800d22e: 4b29 ldr r3, [pc, #164] @ (800d2d4 ) + 800d230: 8a1b ldrh r3, [r3, #16] + 800d232: 1ad3 subs r3, r2, r3 + 800d234: b29a uxth r2, r3 + 800d236: 4b27 ldr r3, [pc, #156] @ (800d2d4 ) + 800d238: 829a strh r2, [r3, #20] + ADV_TRACE_Ctx.unchunk_status = TRACE_UNCHUNK_TRANSFER; + 800d23a: 4b26 ldr r3, [pc, #152] @ (800d2d4 ) + 800d23c: 2202 movs r2, #2 + 800d23e: 709a strb r2, [r3, #2] + ADV_TRACE_Ctx.unchunk_enabled = 0; + 800d240: 4b24 ldr r3, [pc, #144] @ (800d2d4 ) + 800d242: 2200 movs r2, #0 + 800d244: 801a strh r2, [r3, #0] + + UTIL_ADV_TRACE_DEBUG("\nTRACE_TxCpltCallback::unchunk start(%d,%d)\n", ADV_TRACE_Ctx.unchunk_enabled, ADV_TRACE_Ctx.TraceRdPtr); + + if(0u == ADV_TRACE_Ctx.TraceSentSize) + 800d246: 4b23 ldr r3, [pc, #140] @ (800d2d4 ) + 800d248: 8a9b ldrh r3, [r3, #20] + 800d24a: 2b00 cmp r3, #0 + 800d24c: d105 bne.n 800d25a + { + /* this case occurs when an ongoing write aligned the Rd position with chunk position */ + /* in that case the unchunk is forgot */ + ADV_TRACE_Ctx.unchunk_status = TRACE_UNCHUNK_NONE; + 800d24e: 4b21 ldr r3, [pc, #132] @ (800d2d4 ) + 800d250: 2200 movs r2, #0 + 800d252: 709a strb r2, [r3, #2] + ADV_TRACE_Ctx.TraceRdPtr = 0; + 800d254: 4b1f ldr r3, [pc, #124] @ (800d2d4 ) + 800d256: 2200 movs r2, #0 + 800d258: 821a strh r2, [r3, #16] + } + } + + if(TRACE_UNCHUNK_NONE == ADV_TRACE_Ctx.unchunk_status) + 800d25a: 4b1e ldr r3, [pc, #120] @ (800d2d4 ) + 800d25c: 789b ldrb r3, [r3, #2] + 800d25e: 2b00 cmp r3, #0 + 800d260: d115 bne.n 800d28e + { +#endif + if(ADV_TRACE_Ctx.TraceWrPtr > ADV_TRACE_Ctx.TraceRdPtr) + 800d262: 4b1c ldr r3, [pc, #112] @ (800d2d4 ) + 800d264: 8a5a ldrh r2, [r3, #18] + 800d266: 4b1b ldr r3, [pc, #108] @ (800d2d4 ) + 800d268: 8a1b ldrh r3, [r3, #16] + 800d26a: 429a cmp r2, r3 + 800d26c: d908 bls.n 800d280 + { + ADV_TRACE_Ctx.TraceSentSize = ADV_TRACE_Ctx.TraceWrPtr - ADV_TRACE_Ctx.TraceRdPtr; + 800d26e: 4b19 ldr r3, [pc, #100] @ (800d2d4 ) + 800d270: 8a5a ldrh r2, [r3, #18] + 800d272: 4b18 ldr r3, [pc, #96] @ (800d2d4 ) + 800d274: 8a1b ldrh r3, [r3, #16] + 800d276: 1ad3 subs r3, r2, r3 + 800d278: b29a uxth r2, r3 + 800d27a: 4b16 ldr r3, [pc, #88] @ (800d2d4 ) + 800d27c: 829a strh r2, [r3, #20] + 800d27e: e006 b.n 800d28e + } + else /* TraceRdPtr > TraceWrPtr */ + { + ADV_TRACE_Ctx.TraceSentSize = UTIL_ADV_TRACE_FIFO_SIZE - ADV_TRACE_Ctx.TraceRdPtr; + 800d280: 4b14 ldr r3, [pc, #80] @ (800d2d4 ) + 800d282: 8a1b ldrh r3, [r3, #16] + 800d284: f5c3 7300 rsb r3, r3, #512 @ 0x200 + 800d288: b29a uxth r2, r3 + 800d28a: 4b12 ldr r3, [pc, #72] @ (800d2d4 ) + 800d28c: 829a strh r2, [r3, #20] + } +#ifdef UTIL_ADV_TRACE_UNCHUNK_MODE + } +#endif + ptr = &ADV_TRACE_Buffer[ADV_TRACE_Ctx.TraceRdPtr]; + 800d28e: 4b11 ldr r3, [pc, #68] @ (800d2d4 ) + 800d290: 8a1b ldrh r3, [r3, #16] + 800d292: 461a mov r2, r3 + 800d294: 4b10 ldr r3, [pc, #64] @ (800d2d8 ) + 800d296: 4413 add r3, r2 + 800d298: 61fb str r3, [r7, #28] + 800d29a: 69bb ldr r3, [r7, #24] + 800d29c: 613b str r3, [r7, #16] + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 800d29e: 693b ldr r3, [r7, #16] + 800d2a0: f383 8810 msr PRIMASK, r3 +} + 800d2a4: bf00 nop + UTIL_ADV_TRACE_EXIT_CRITICAL_SECTION(); + UTIL_ADV_TRACE_DEBUG("\n--TRACE_Send(%d-%d)--\n", ADV_TRACE_Ctx.TraceRdPtr, ADV_TRACE_Ctx.TraceSentSize); + UTIL_TraceDriver.Send(ptr, ADV_TRACE_Ctx.TraceSentSize); + 800d2a6: 4b0d ldr r3, [pc, #52] @ (800d2dc ) + 800d2a8: 68db ldr r3, [r3, #12] + 800d2aa: 4a0a ldr r2, [pc, #40] @ (800d2d4 ) + 800d2ac: 8a92 ldrh r2, [r2, #20] + 800d2ae: 4611 mov r1, r2 + 800d2b0: 69f8 ldr r0, [r7, #28] + 800d2b2: 4798 blx r3 + 800d2b4: e00a b.n 800d2cc + 800d2b6: 69bb ldr r3, [r7, #24] + 800d2b8: 60fb str r3, [r7, #12] + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 800d2ba: 68fb ldr r3, [r7, #12] + 800d2bc: f383 8810 msr PRIMASK, r3 +} + 800d2c0: bf00 nop + } + else + { + UTIL_ADV_TRACE_EXIT_CRITICAL_SECTION(); + UTIL_ADV_TRACE_PostSendHook(); + 800d2c2: f7f3 fc35 bl 8000b30 + TRACE_UnLock(); + 800d2c6: f000 f8a7 bl 800d418 + } +} + 800d2ca: bf00 nop + 800d2cc: bf00 nop + 800d2ce: 3720 adds r7, #32 + 800d2d0: 46bd mov sp, r7 + 800d2d2: bd80 pop {r7, pc} + 800d2d4: 200009d0 .word 0x200009d0 + 800d2d8: 200009e8 .word 0x200009e8 + 800d2dc: 0800d9a8 .word 0x0800d9a8 + +0800d2e0 : + * @param Size to allocate within fifo + * @param Pos position within the fifo + * @retval write position inside the buffer is -1 no space available. + */ +static int16_t TRACE_AllocateBufer(uint16_t Size, uint16_t *Pos) +{ + 800d2e0: b480 push {r7} + 800d2e2: b087 sub sp, #28 + 800d2e4: af00 add r7, sp, #0 + 800d2e6: 4603 mov r3, r0 + 800d2e8: 6039 str r1, [r7, #0] + 800d2ea: 80fb strh r3, [r7, #6] + uint16_t freesize; + int16_t ret = -1; + 800d2ec: f64f 73ff movw r3, #65535 @ 0xffff + 800d2f0: 82bb strh r3, [r7, #20] + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 800d2f2: f3ef 8310 mrs r3, PRIMASK + 800d2f6: 60fb str r3, [r7, #12] + return(result); + 800d2f8: 68fb ldr r3, [r7, #12] + + UTIL_ADV_TRACE_ENTER_CRITICAL_SECTION(); + 800d2fa: 613b str r3, [r7, #16] + __ASM volatile ("cpsid i" : : : "memory"); + 800d2fc: b672 cpsid i +} + 800d2fe: bf00 nop + + if(ADV_TRACE_Ctx.TraceWrPtr == ADV_TRACE_Ctx.TraceRdPtr) + 800d300: 4b35 ldr r3, [pc, #212] @ (800d3d8 ) + 800d302: 8a5a ldrh r2, [r3, #18] + 800d304: 4b34 ldr r3, [pc, #208] @ (800d3d8 ) + 800d306: 8a1b ldrh r3, [r3, #16] + 800d308: 429a cmp r2, r3 + 800d30a: d11b bne.n 800d344 + { +#ifdef UTIL_ADV_TRACE_UNCHUNK_MODE + freesize = (uint16_t)(UTIL_ADV_TRACE_FIFO_SIZE - ADV_TRACE_Ctx.TraceWrPtr); + 800d30c: 4b32 ldr r3, [pc, #200] @ (800d3d8 ) + 800d30e: 8a5b ldrh r3, [r3, #18] + 800d310: f5c3 7300 rsb r3, r3, #512 @ 0x200 + 800d314: 82fb strh r3, [r7, #22] + if((Size >= freesize) && (ADV_TRACE_Ctx.TraceRdPtr > Size)) + 800d316: 88fa ldrh r2, [r7, #6] + 800d318: 8afb ldrh r3, [r7, #22] + 800d31a: 429a cmp r2, r3 + 800d31c: d33a bcc.n 800d394 + 800d31e: 4b2e ldr r3, [pc, #184] @ (800d3d8 ) + 800d320: 8a1b ldrh r3, [r3, #16] + 800d322: 88fa ldrh r2, [r7, #6] + 800d324: 429a cmp r2, r3 + 800d326: d235 bcs.n 800d394 + { + ADV_TRACE_Ctx.unchunk_status = TRACE_UNCHUNK_DETECTED; + 800d328: 4b2b ldr r3, [pc, #172] @ (800d3d8 ) + 800d32a: 2201 movs r2, #1 + 800d32c: 709a strb r2, [r3, #2] + ADV_TRACE_Ctx.unchunk_enabled = ADV_TRACE_Ctx.TraceWrPtr; + 800d32e: 4b2a ldr r3, [pc, #168] @ (800d3d8 ) + 800d330: 8a5a ldrh r2, [r3, #18] + 800d332: 4b29 ldr r3, [pc, #164] @ (800d3d8 ) + 800d334: 801a strh r2, [r3, #0] + freesize = ADV_TRACE_Ctx.TraceRdPtr; + 800d336: 4b28 ldr r3, [pc, #160] @ (800d3d8 ) + 800d338: 8a1b ldrh r3, [r3, #16] + 800d33a: 82fb strh r3, [r7, #22] + ADV_TRACE_Ctx.TraceWrPtr = 0; + 800d33c: 4b26 ldr r3, [pc, #152] @ (800d3d8 ) + 800d33e: 2200 movs r2, #0 + 800d340: 825a strh r2, [r3, #18] + 800d342: e027 b.n 800d394 +#endif + } + else + { +#ifdef UTIL_ADV_TRACE_UNCHUNK_MODE + if (ADV_TRACE_Ctx.TraceWrPtr > ADV_TRACE_Ctx.TraceRdPtr) + 800d344: 4b24 ldr r3, [pc, #144] @ (800d3d8 ) + 800d346: 8a5a ldrh r2, [r3, #18] + 800d348: 4b23 ldr r3, [pc, #140] @ (800d3d8 ) + 800d34a: 8a1b ldrh r3, [r3, #16] + 800d34c: 429a cmp r2, r3 + 800d34e: d91b bls.n 800d388 + { + freesize = (uint16_t)(UTIL_ADV_TRACE_FIFO_SIZE - ADV_TRACE_Ctx.TraceWrPtr); + 800d350: 4b21 ldr r3, [pc, #132] @ (800d3d8 ) + 800d352: 8a5b ldrh r3, [r3, #18] + 800d354: f5c3 7300 rsb r3, r3, #512 @ 0x200 + 800d358: 82fb strh r3, [r7, #22] + if((Size >= freesize) && (ADV_TRACE_Ctx.TraceRdPtr > Size)) + 800d35a: 88fa ldrh r2, [r7, #6] + 800d35c: 8afb ldrh r3, [r7, #22] + 800d35e: 429a cmp r2, r3 + 800d360: d318 bcc.n 800d394 + 800d362: 4b1d ldr r3, [pc, #116] @ (800d3d8 ) + 800d364: 8a1b ldrh r3, [r3, #16] + 800d366: 88fa ldrh r2, [r7, #6] + 800d368: 429a cmp r2, r3 + 800d36a: d213 bcs.n 800d394 + { + ADV_TRACE_Ctx.unchunk_status = TRACE_UNCHUNK_DETECTED; + 800d36c: 4b1a ldr r3, [pc, #104] @ (800d3d8 ) + 800d36e: 2201 movs r2, #1 + 800d370: 709a strb r2, [r3, #2] + ADV_TRACE_Ctx.unchunk_enabled = ADV_TRACE_Ctx.TraceWrPtr; + 800d372: 4b19 ldr r3, [pc, #100] @ (800d3d8 ) + 800d374: 8a5a ldrh r2, [r3, #18] + 800d376: 4b18 ldr r3, [pc, #96] @ (800d3d8 ) + 800d378: 801a strh r2, [r3, #0] + freesize = ADV_TRACE_Ctx.TraceRdPtr; + 800d37a: 4b17 ldr r3, [pc, #92] @ (800d3d8 ) + 800d37c: 8a1b ldrh r3, [r3, #16] + 800d37e: 82fb strh r3, [r7, #22] + ADV_TRACE_Ctx.TraceWrPtr = 0; + 800d380: 4b15 ldr r3, [pc, #84] @ (800d3d8 ) + 800d382: 2200 movs r2, #0 + 800d384: 825a strh r2, [r3, #18] + 800d386: e005 b.n 800d394 + } + } + else + { + freesize = (uint16_t)(ADV_TRACE_Ctx.TraceRdPtr - ADV_TRACE_Ctx.TraceWrPtr); + 800d388: 4b13 ldr r3, [pc, #76] @ (800d3d8 ) + 800d38a: 8a1a ldrh r2, [r3, #16] + 800d38c: 4b12 ldr r3, [pc, #72] @ (800d3d8 ) + 800d38e: 8a5b ldrh r3, [r3, #18] + 800d390: 1ad3 subs r3, r2, r3 + 800d392: 82fb strh r3, [r7, #22] + freesize = ADV_TRACE_Ctx.TraceRdPtr - ADV_TRACE_Ctx.TraceWrPtr; + } +#endif + } + + if(freesize > Size) + 800d394: 8afa ldrh r2, [r7, #22] + 800d396: 88fb ldrh r3, [r7, #6] + 800d398: 429a cmp r2, r3 + 800d39a: d90f bls.n 800d3bc + { + *Pos = ADV_TRACE_Ctx.TraceWrPtr; + 800d39c: 4b0e ldr r3, [pc, #56] @ (800d3d8 ) + 800d39e: 8a5a ldrh r2, [r3, #18] + 800d3a0: 683b ldr r3, [r7, #0] + 800d3a2: 801a strh r2, [r3, #0] + ADV_TRACE_Ctx.TraceWrPtr = (ADV_TRACE_Ctx.TraceWrPtr + Size) % UTIL_ADV_TRACE_FIFO_SIZE; + 800d3a4: 4b0c ldr r3, [pc, #48] @ (800d3d8 ) + 800d3a6: 8a5a ldrh r2, [r3, #18] + 800d3a8: 88fb ldrh r3, [r7, #6] + 800d3aa: 4413 add r3, r2 + 800d3ac: b29b uxth r3, r3 + 800d3ae: f3c3 0308 ubfx r3, r3, #0, #9 + 800d3b2: b29a uxth r2, r3 + 800d3b4: 4b08 ldr r3, [pc, #32] @ (800d3d8 ) + 800d3b6: 825a strh r2, [r3, #18] + ret = 0; + 800d3b8: 2300 movs r3, #0 + 800d3ba: 82bb strh r3, [r7, #20] + 800d3bc: 693b ldr r3, [r7, #16] + 800d3be: 60bb str r3, [r7, #8] + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 800d3c0: 68bb ldr r3, [r7, #8] + 800d3c2: f383 8810 msr PRIMASK, r3 +} + 800d3c6: bf00 nop + } + } +#endif + + UTIL_ADV_TRACE_EXIT_CRITICAL_SECTION(); + return ret; + 800d3c8: f9b7 3014 ldrsh.w r3, [r7, #20] +} + 800d3cc: 4618 mov r0, r3 + 800d3ce: 371c adds r7, #28 + 800d3d0: 46bd mov sp, r7 + 800d3d2: bc80 pop {r7} + 800d3d4: 4770 bx lr + 800d3d6: bf00 nop + 800d3d8: 200009d0 .word 0x200009d0 + +0800d3dc : +/** + * @brief Lock the trace buffer. + * @retval None. + */ +static void TRACE_Lock(void) +{ + 800d3dc: b480 push {r7} + 800d3de: b085 sub sp, #20 + 800d3e0: af00 add r7, sp, #0 + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 800d3e2: f3ef 8310 mrs r3, PRIMASK + 800d3e6: 607b str r3, [r7, #4] + return(result); + 800d3e8: 687b ldr r3, [r7, #4] + UTIL_ADV_TRACE_ENTER_CRITICAL_SECTION(); + 800d3ea: 60fb str r3, [r7, #12] + __ASM volatile ("cpsid i" : : : "memory"); + 800d3ec: b672 cpsid i +} + 800d3ee: bf00 nop + ADV_TRACE_Ctx.TraceLock++; + 800d3f0: 4b08 ldr r3, [pc, #32] @ (800d414 ) + 800d3f2: 8adb ldrh r3, [r3, #22] + 800d3f4: 3301 adds r3, #1 + 800d3f6: b29a uxth r2, r3 + 800d3f8: 4b06 ldr r3, [pc, #24] @ (800d414 ) + 800d3fa: 82da strh r2, [r3, #22] + 800d3fc: 68fb ldr r3, [r7, #12] + 800d3fe: 60bb str r3, [r7, #8] + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 800d400: 68bb ldr r3, [r7, #8] + 800d402: f383 8810 msr PRIMASK, r3 +} + 800d406: bf00 nop + UTIL_ADV_TRACE_EXIT_CRITICAL_SECTION(); +} + 800d408: bf00 nop + 800d40a: 3714 adds r7, #20 + 800d40c: 46bd mov sp, r7 + 800d40e: bc80 pop {r7} + 800d410: 4770 bx lr + 800d412: bf00 nop + 800d414: 200009d0 .word 0x200009d0 + +0800d418 : +/** + * @brief UnLock the trace buffer. + * @retval None. + */ +static void TRACE_UnLock(void) +{ + 800d418: b480 push {r7} + 800d41a: b085 sub sp, #20 + 800d41c: af00 add r7, sp, #0 + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 800d41e: f3ef 8310 mrs r3, PRIMASK + 800d422: 607b str r3, [r7, #4] + return(result); + 800d424: 687b ldr r3, [r7, #4] + UTIL_ADV_TRACE_ENTER_CRITICAL_SECTION(); + 800d426: 60fb str r3, [r7, #12] + __ASM volatile ("cpsid i" : : : "memory"); + 800d428: b672 cpsid i +} + 800d42a: bf00 nop + ADV_TRACE_Ctx.TraceLock--; + 800d42c: 4b08 ldr r3, [pc, #32] @ (800d450 ) + 800d42e: 8adb ldrh r3, [r3, #22] + 800d430: 3b01 subs r3, #1 + 800d432: b29a uxth r2, r3 + 800d434: 4b06 ldr r3, [pc, #24] @ (800d450 ) + 800d436: 82da strh r2, [r3, #22] + 800d438: 68fb ldr r3, [r7, #12] + 800d43a: 60bb str r3, [r7, #8] + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 800d43c: 68bb ldr r3, [r7, #8] + 800d43e: f383 8810 msr PRIMASK, r3 +} + 800d442: bf00 nop + UTIL_ADV_TRACE_EXIT_CRITICAL_SECTION(); +} + 800d444: bf00 nop + 800d446: 3714 adds r7, #20 + 800d448: 46bd mov sp, r7 + 800d44a: bc80 pop {r7} + 800d44c: 4770 bx lr + 800d44e: bf00 nop + 800d450: 200009d0 .word 0x200009d0 + +0800d454 : +/** + * @brief UnLock the trace buffer. + * @retval None. + */ +static uint32_t TRACE_IsLocked(void) +{ + 800d454: b480 push {r7} + 800d456: af00 add r7, sp, #0 + return (ADV_TRACE_Ctx.TraceLock == 0u? 0u: 1u); + 800d458: 4b05 ldr r3, [pc, #20] @ (800d470 ) + 800d45a: 8adb ldrh r3, [r3, #22] + 800d45c: 2b00 cmp r3, #0 + 800d45e: bf14 ite ne + 800d460: 2301 movne r3, #1 + 800d462: 2300 moveq r3, #0 + 800d464: b2db uxtb r3, r3 +} + 800d466: 4618 mov r0, r3 + 800d468: 46bd mov sp, r7 + 800d46a: bc80 pop {r7} + 800d46c: 4770 bx lr + 800d46e: bf00 nop + 800d470: 200009d0 .word 0x200009d0 + +0800d474 : + 800d474: 4402 add r2, r0 + 800d476: 4603 mov r3, r0 + 800d478: 4293 cmp r3, r2 + 800d47a: d100 bne.n 800d47e + 800d47c: 4770 bx lr + 800d47e: f803 1b01 strb.w r1, [r3], #1 + 800d482: e7f9 b.n 800d478 + +0800d484 <__libc_init_array>: + 800d484: b570 push {r4, r5, r6, lr} + 800d486: 4d0d ldr r5, [pc, #52] @ (800d4bc <__libc_init_array+0x38>) + 800d488: 4c0d ldr r4, [pc, #52] @ (800d4c0 <__libc_init_array+0x3c>) + 800d48a: 1b64 subs r4, r4, r5 + 800d48c: 10a4 asrs r4, r4, #2 + 800d48e: 2600 movs r6, #0 + 800d490: 42a6 cmp r6, r4 + 800d492: d109 bne.n 800d4a8 <__libc_init_array+0x24> + 800d494: 4d0b ldr r5, [pc, #44] @ (800d4c4 <__libc_init_array+0x40>) + 800d496: 4c0c ldr r4, [pc, #48] @ (800d4c8 <__libc_init_array+0x44>) + 800d498: f000 f826 bl 800d4e8 <_init> + 800d49c: 1b64 subs r4, r4, r5 + 800d49e: 10a4 asrs r4, r4, #2 + 800d4a0: 2600 movs r6, #0 + 800d4a2: 42a6 cmp r6, r4 + 800d4a4: d105 bne.n 800d4b2 <__libc_init_array+0x2e> + 800d4a6: bd70 pop {r4, r5, r6, pc} + 800d4a8: f855 3b04 ldr.w r3, [r5], #4 + 800d4ac: 4798 blx r3 + 800d4ae: 3601 adds r6, #1 + 800d4b0: e7ee b.n 800d490 <__libc_init_array+0xc> + 800d4b2: f855 3b04 ldr.w r3, [r5], #4 + 800d4b6: 4798 blx r3 + 800d4b8: 3601 adds r6, #1 + 800d4ba: e7f2 b.n 800d4a2 <__libc_init_array+0x1e> + 800d4bc: 0800db38 .word 0x0800db38 + 800d4c0: 0800db38 .word 0x0800db38 + 800d4c4: 0800db38 .word 0x0800db38 + 800d4c8: 0800db3c .word 0x0800db3c + +0800d4cc : + 800d4cc: 440a add r2, r1 + 800d4ce: 4291 cmp r1, r2 + 800d4d0: f100 33ff add.w r3, r0, #4294967295 @ 0xffffffff + 800d4d4: d100 bne.n 800d4d8 + 800d4d6: 4770 bx lr + 800d4d8: b510 push {r4, lr} + 800d4da: f811 4b01 ldrb.w r4, [r1], #1 + 800d4de: f803 4f01 strb.w r4, [r3, #1]! + 800d4e2: 4291 cmp r1, r2 + 800d4e4: d1f9 bne.n 800d4da + 800d4e6: bd10 pop {r4, pc} + +0800d4e8 <_init>: + 800d4e8: b5f8 push {r3, r4, r5, r6, r7, lr} + 800d4ea: bf00 nop + 800d4ec: bcf8 pop {r3, r4, r5, r6, r7} + 800d4ee: bc08 pop {r3} + 800d4f0: 469e mov lr, r3 + 800d4f2: 4770 bx lr + +0800d4f4 <_fini>: + 800d4f4: b5f8 push {r3, r4, r5, r6, r7, lr} + 800d4f6: bf00 nop + 800d4f8: bcf8 pop {r3, r4, r5, r6, r7} + 800d4fa: bc08 pop {r3} + 800d4fc: 469e mov lr, r3 + 800d4fe: 4770 bx lr diff --git a/Debug/SubGHz_Phy_Per.map b/Debug/SubGHz_Phy_Per.map new file mode 100644 index 0000000..c3afc1f --- /dev/null +++ b/Debug/SubGHz_Phy_Per.map @@ -0,0 +1,9485 @@ +Archive member included to satisfy reference by file (symbol) + +/opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(libc_a-exit.o) + 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/opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(libc_a-fflush.o) + .text.__sflush_r + 0x00000000 0x100 /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(libc_a-fflush.o) + .text._fflush_r + 0x00000000 0x50 /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(libc_a-fflush.o) + .text.fflush 0x00000000 0x28 /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(libc_a-fflush.o) + .debug_frame 0x00000000 0x5c /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(libc_a-fflush.o) + .ARM.attributes + 0x00000000 0x2e /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(libc_a-fflush.o) + .text 0x00000000 0x0 /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(libc_a-sbrkr.o) + .data 0x00000000 0x0 /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(libc_a-sbrkr.o) + .bss 0x00000000 0x0 /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(libc_a-sbrkr.o) + .text._sbrk_r 0x00000000 0x20 /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(libc_a-sbrkr.o) + .debug_frame 0x00000000 0x2c /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(libc_a-sbrkr.o) + .ARM.attributes + 0x00000000 0x2e /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(libc_a-sbrkr.o) + .data 0x00000000 0x0 /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m/nofp/libgcc.a(_aeabi_uldivmod.o) + .bss 0x00000000 0x0 /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m/nofp/libgcc.a(_aeabi_uldivmod.o) + .data 0x00000000 0x0 /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m/nofp/libgcc.a(_udivmoddi4.o) + .bss 0x00000000 0x0 /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m/nofp/libgcc.a(_udivmoddi4.o) + .ARM.extab 0x00000000 0x0 /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m/nofp/libgcc.a(_udivmoddi4.o) + .data 0x00000000 0x0 /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m/nofp/libgcc.a(_dvmd_tls.o) + .bss 0x00000000 0x0 /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m/nofp/libgcc.a(_dvmd_tls.o) + .text 0x00000000 0x0 /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m/nofp/crtend.o + .data 0x00000000 0x0 /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m/nofp/crtend.o + .bss 0x00000000 0x0 /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m/nofp/crtend.o + .rodata 0x00000000 0x24 /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m/nofp/crtend.o + .eh_frame 0x00000000 0x4 /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m/nofp/crtend.o + .ARM.attributes + 0x00000000 0x2e /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m/nofp/crtend.o + .text 0x00000000 0x0 /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m/nofp/crtn.o + .data 0x00000000 0x0 /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m/nofp/crtn.o + .bss 0x00000000 0x0 /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m/nofp/crtn.o + +Memory Configuration + +Name Origin Length Attributes +RAM 0x20000000 0x00010000 xrw +RAM2 0x10000000 0x00008000 xrw +FLASH 0x08000000 0x00040000 xr +*default* 0x00000000 0xffffffff + +Linker script and memory map + +LOAD /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m/nofp/crti.o +LOAD /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m/nofp/crtbegin.o +LOAD /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/crt0.o +LOAD ./Core/Src/dma.o +LOAD ./Core/Src/gpio.o +LOAD ./Core/Src/main.o +LOAD ./Core/Src/rtc.o +LOAD ./Core/Src/stm32_lpm_if.o +LOAD ./Core/Src/stm32wlxx_hal_msp.o +LOAD ./Core/Src/stm32wlxx_it.o +LOAD ./Core/Src/subghz.o +LOAD ./Core/Src/sys_app.o +LOAD ./Core/Src/sys_debug.o +LOAD ./Core/Src/syscalls.o +LOAD ./Core/Src/sysmem.o +LOAD ./Core/Src/system_stm32wlxx.o +LOAD ./Core/Src/timer_if.o +LOAD ./Core/Src/usart.o +LOAD ./Core/Src/usart_if.o +LOAD ./Core/Startup/startup_stm32wl55jcix.o +LOAD ./Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo.o +LOAD ./Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo_radio.o +LOAD ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.o +LOAD ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.o +LOAD ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.o +LOAD ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma_ex.o +LOAD ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_exti.o +LOAD ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash.o +LOAD ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.o +LOAD ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_gpio.o +LOAD ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.o +LOAD ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.o +LOAD ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.o +LOAD ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.o +LOAD ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.o +LOAD ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.o +LOAD ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.o +LOAD ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.o +LOAD ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.o +LOAD ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.o +LOAD ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o +LOAD ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o +LOAD ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.o +LOAD ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/wl_lr_fhss.o +LOAD ./SubGHz_Phy/App/app_subghz_phy.o +LOAD ./SubGHz_Phy/App/subghz_phy_app.o +LOAD ./SubGHz_Phy/Target/radio_board_if.o +LOAD ./Utilities/lpm/tiny_lpm/stm32_lpm.o +LOAD ./Utilities/misc/stm32_mem.o +LOAD ./Utilities/misc/stm32_systime.o +LOAD ./Utilities/misc/stm32_tiny_sscanf.o +LOAD ./Utilities/misc/stm32_tiny_vsnprintf.o +LOAD ./Utilities/sequencer/stm32_seq.o +LOAD ./Utilities/timer/stm32_timer.o +LOAD ./Utilities/trace/adv_trace/stm32_adv_trace.o +START GROUP +LOAD /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a +LOAD /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libm.a +END GROUP +START GROUP +LOAD /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m/nofp/libgcc.a +LOAD /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a +END GROUP +START GROUP +LOAD /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m/nofp/libgcc.a +LOAD /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a +LOAD /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libnosys.a +END GROUP +START GROUP +LOAD /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m/nofp/libgcc.a +LOAD /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a +LOAD /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libnosys.a +END GROUP +LOAD /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m/nofp/crtend.o +LOAD /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m/nofp/crtn.o + 0x20010000 _estack = (ORIGIN (RAM) + LENGTH (RAM)) + 0x00000200 _Min_Heap_Size = 0x200 + 0x00000800 _Min_Stack_Size = 0x800 + +.isr_vector 0x08000000 0x138 + 0x08000000 . = ALIGN (0x4) + *(.isr_vector) + .isr_vector 0x08000000 0x138 ./Core/Startup/startup_stm32wl55jcix.o + 0x08000000 g_pfnVectors + 0x08000138 . = ALIGN (0x4) + +.text 0x08000138 0xd3c8 + 0x08000138 . = ALIGN (0x4) + *(.text) + .text 0x08000138 0x40 /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m/nofp/crtbegin.o + .text 0x08000178 0x10 /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(libc_a-strlen.o) + 0x08000178 strlen + .text 0x08000188 0x30 /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m/nofp/libgcc.a(_aeabi_uldivmod.o) + 0x08000188 __aeabi_uldivmod + .text 0x080001b8 0x2f8 /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m/nofp/libgcc.a(_udivmoddi4.o) + 0x080001b8 __udivmoddi4 + .text 0x080004b0 0x4 /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m/nofp/libgcc.a(_dvmd_tls.o) + 0x080004b0 __aeabi_ldiv0 + 0x080004b0 __aeabi_idiv0 + *(.text*) + .text.LL_AHB1_GRP1_EnableClock + 0x080004b4 0x30 ./Core/Src/dma.o + .text.MX_DMA_Init + 0x080004e4 0x24 ./Core/Src/dma.o + 0x080004e4 MX_DMA_Init + .text.LL_AHB2_GRP1_EnableClock + 0x08000508 0x30 ./Core/Src/gpio.o + .text.MX_GPIO_Init + 0x08000538 0xdc ./Core/Src/gpio.o + 0x08000538 MX_GPIO_Init + .text.LL_RCC_LSE_SetDriveCapability + 0x08000614 0x2a ./Core/Src/main.o + .text.main 0x0800063e 0x1a ./Core/Src/main.o + 0x0800063e main + .text.SystemClock_Config + 0x08000658 0xb0 ./Core/Src/main.o + 0x08000658 SystemClock_Config + .text.Error_Handler + 0x08000708 0xc ./Core/Src/main.o + 0x08000708 Error_Handler + .text.LL_RCC_EnableRTC + 0x08000714 0x20 ./Core/Src/rtc.o + .text.LL_APB1_GRP1_EnableClock + 0x08000734 0x30 ./Core/Src/rtc.o + .text.MX_RTC_Init + 0x08000764 0xa4 ./Core/Src/rtc.o + 0x08000764 MX_RTC_Init + .text.HAL_RTC_MspInit + 0x08000808 0x78 ./Core/Src/rtc.o + 0x08000808 HAL_RTC_MspInit + .text.LL_PWR_ClearFlag_C1STOP_C1STB + 0x08000880 0x18 ./Core/Src/stm32_lpm_if.o + .text.PWR_EnterOffMode + 0x08000898 0xc ./Core/Src/stm32_lpm_if.o + 0x08000898 PWR_EnterOffMode + .text.PWR_ExitOffMode + 0x080008a4 0xc ./Core/Src/stm32_lpm_if.o + 0x080008a4 PWR_ExitOffMode + .text.PWR_EnterStopMode + 0x080008b0 0x16 ./Core/Src/stm32_lpm_if.o + 0x080008b0 PWR_EnterStopMode + .text.PWR_ExitStopMode + 0x080008c6 0x10 ./Core/Src/stm32_lpm_if.o + 0x080008c6 PWR_ExitStopMode + .text.PWR_EnterSleepMode + 0x080008d6 0x14 ./Core/Src/stm32_lpm_if.o + 0x080008d6 PWR_EnterSleepMode + .text.PWR_ExitSleepMode + 0x080008ea 0xc ./Core/Src/stm32_lpm_if.o + 0x080008ea PWR_ExitSleepMode + .text.HAL_MspInit + 0x080008f6 0xc ./Core/Src/stm32wlxx_hal_msp.o + 0x080008f6 HAL_MspInit + .text.NMI_Handler + 0x08000902 0x8 ./Core/Src/stm32wlxx_it.o + 0x08000902 NMI_Handler + .text.HardFault_Handler + 0x0800090a 0x8 ./Core/Src/stm32wlxx_it.o + 0x0800090a HardFault_Handler + .text.MemManage_Handler + 0x08000912 0x8 ./Core/Src/stm32wlxx_it.o + 0x08000912 MemManage_Handler + .text.BusFault_Handler + 0x0800091a 0x8 ./Core/Src/stm32wlxx_it.o + 0x0800091a BusFault_Handler + .text.UsageFault_Handler + 0x08000922 0x8 ./Core/Src/stm32wlxx_it.o + 0x08000922 UsageFault_Handler + .text.SVC_Handler + 0x0800092a 0xc ./Core/Src/stm32wlxx_it.o + 0x0800092a SVC_Handler + .text.DebugMon_Handler + 0x08000936 0xc ./Core/Src/stm32wlxx_it.o + 0x08000936 DebugMon_Handler + .text.PendSV_Handler + 0x08000942 0xc ./Core/Src/stm32wlxx_it.o + 0x08000942 PendSV_Handler + .text.SysTick_Handler + 0x0800094e 0xc ./Core/Src/stm32wlxx_it.o + 0x0800094e SysTick_Handler + *fill* 0x0800095a 0x2 + .text.TAMP_STAMP_LSECSS_SSRU_IRQHandler + 0x0800095c 0x14 ./Core/Src/stm32wlxx_it.o + 0x0800095c TAMP_STAMP_LSECSS_SSRU_IRQHandler + .text.EXTI0_IRQHandler + 0x08000970 0xe ./Core/Src/stm32wlxx_it.o + 0x08000970 EXTI0_IRQHandler + .text.EXTI1_IRQHandler + 0x0800097e 0xe ./Core/Src/stm32wlxx_it.o + 0x0800097e EXTI1_IRQHandler + .text.DMA1_Channel5_IRQHandler + 0x0800098c 0x14 ./Core/Src/stm32wlxx_it.o + 0x0800098c DMA1_Channel5_IRQHandler + .text.EXTI9_5_IRQHandler + 0x080009a0 0xe ./Core/Src/stm32wlxx_it.o + 0x080009a0 EXTI9_5_IRQHandler + *fill* 0x080009ae 0x2 + .text.USART2_IRQHandler + 0x080009b0 0x14 ./Core/Src/stm32wlxx_it.o + 0x080009b0 USART2_IRQHandler + .text.RTC_Alarm_IRQHandler + 0x080009c4 0x14 ./Core/Src/stm32wlxx_it.o + 0x080009c4 RTC_Alarm_IRQHandler + .text.SUBGHZ_Radio_IRQHandler + 0x080009d8 0x14 ./Core/Src/stm32wlxx_it.o + 0x080009d8 SUBGHZ_Radio_IRQHandler + .text.LL_APB3_GRP1_EnableClock + 0x080009ec 0x30 ./Core/Src/subghz.o + .text.MX_SUBGHZ_Init + 0x08000a1c 0x24 ./Core/Src/subghz.o + 0x08000a1c MX_SUBGHZ_Init + .text.HAL_SUBGHZ_MspInit + 0x08000a40 0x26 ./Core/Src/subghz.o + 0x08000a40 HAL_SUBGHZ_MspInit + .text.LL_RCC_SetClkAfterWakeFromStop + 0x08000a66 0x26 ./Core/Src/sys_app.o + .text.SystemApp_Init + 0x08000a8c 0x48 ./Core/Src/sys_app.o + 0x08000a8c SystemApp_Init + .text.UTIL_SEQ_Idle + 0x08000ad4 0xc ./Core/Src/sys_app.o + 0x08000ad4 UTIL_SEQ_Idle + .text.TimestampNow + 0x08000ae0 0x40 ./Core/Src/sys_app.o + .text.UTIL_ADV_TRACE_PreSendHook + 0x08000b20 0x10 ./Core/Src/sys_app.o + 0x08000b20 UTIL_ADV_TRACE_PreSendHook + .text.UTIL_ADV_TRACE_PostSendHook + 0x08000b30 0x10 ./Core/Src/sys_app.o + 0x08000b30 UTIL_ADV_TRACE_PostSendHook + .text.tiny_snprintf_like + 0x08000b40 0x2c ./Core/Src/sys_app.o + .text.HAL_InitTick + 0x08000b6c 0x14 ./Core/Src/sys_app.o + 0x08000b6c HAL_InitTick + .text.HAL_GetTick + 0x08000b80 0x28 ./Core/Src/sys_app.o + 0x08000b80 HAL_GetTick + .text.HAL_Delay + 0x08000ba8 0x18 ./Core/Src/sys_app.o + 0x08000ba8 HAL_Delay + .text.LL_AHB2_GRP1_EnableClock + 0x08000bc0 0x30 ./Core/Src/sys_debug.o + .text.LL_EXTI_EnableIT_32_63 + 0x08000bf0 0x28 ./Core/Src/sys_debug.o + .text.DBG_Init + 0x08000c18 0x84 ./Core/Src/sys_debug.o + 0x08000c18 DBG_Init + .text.SystemInit + 0x08000c9c 0xc ./Core/Src/system_stm32wlxx.o + 0x08000c9c SystemInit + .text.LL_RTC_TIME_GetSubSecond + 0x08000ca8 0x16 ./Core/Src/timer_if.o + *fill* 0x08000cbe 0x2 + .text.TIMER_IF_Init + 0x08000cc0 0x64 ./Core/Src/timer_if.o + 0x08000cc0 TIMER_IF_Init + .text.TIMER_IF_StartTimer + 0x08000d24 0x70 ./Core/Src/timer_if.o + 0x08000d24 TIMER_IF_StartTimer + .text.TIMER_IF_StopTimer + 0x08000d94 0x34 ./Core/Src/timer_if.o + 0x08000d94 TIMER_IF_StopTimer + .text.TIMER_IF_SetTimerContext + 0x08000dc8 0x1c ./Core/Src/timer_if.o + 0x08000dc8 TIMER_IF_SetTimerContext + .text.TIMER_IF_GetTimerContext + 0x08000de4 0x14 ./Core/Src/timer_if.o + 0x08000de4 TIMER_IF_GetTimerContext + .text.TIMER_IF_GetTimerElapsedTime + 0x08000df8 0x28 ./Core/Src/timer_if.o + 0x08000df8 TIMER_IF_GetTimerElapsedTime + .text.TIMER_IF_GetTimerValue + 0x08000e20 0x28 ./Core/Src/timer_if.o + 0x08000e20 TIMER_IF_GetTimerValue + .text.TIMER_IF_GetMinimumTimeout + 0x08000e48 0x1a ./Core/Src/timer_if.o + 0x08000e48 TIMER_IF_GetMinimumTimeout + .text.TIMER_IF_Convert_ms2Tick + 0x08000e62 0x3a ./Core/Src/timer_if.o + 0x08000e62 TIMER_IF_Convert_ms2Tick + .text.TIMER_IF_Convert_Tick2ms + 0x08000e9c 0x92 ./Core/Src/timer_if.o + 0x08000e9c TIMER_IF_Convert_Tick2ms + .text.TIMER_IF_DelayMs + 0x08000f2e 0x34 ./Core/Src/timer_if.o + 0x08000f2e TIMER_IF_DelayMs + .text.HAL_RTC_AlarmAEventCallback + 0x08000f62 0x14 ./Core/Src/timer_if.o + 0x08000f62 HAL_RTC_AlarmAEventCallback + .text.HAL_RTCEx_SSRUEventCallback + 0x08000f76 0x20 ./Core/Src/timer_if.o + 0x08000f76 HAL_RTCEx_SSRUEventCallback + .text.TIMER_IF_GetTime + 0x08000f96 0x8e ./Core/Src/timer_if.o + 0x08000f96 TIMER_IF_GetTime + .text.TIMER_IF_BkUp_Write_Seconds + 0x08001024 0x20 ./Core/Src/timer_if.o + 0x08001024 TIMER_IF_BkUp_Write_Seconds + .text.TIMER_IF_BkUp_Write_SubSeconds + 0x08001044 0x20 ./Core/Src/timer_if.o + 0x08001044 TIMER_IF_BkUp_Write_SubSeconds + .text.TIMER_IF_BkUp_Read_Seconds + 0x08001064 0x24 ./Core/Src/timer_if.o + 0x08001064 TIMER_IF_BkUp_Read_Seconds + .text.TIMER_IF_BkUp_Read_SubSeconds + 0x08001088 0x24 ./Core/Src/timer_if.o + 0x08001088 TIMER_IF_BkUp_Read_SubSeconds + .text.TIMER_IF_BkUp_Write_MSBticks + 0x080010ac 0x20 ./Core/Src/timer_if.o + .text.TIMER_IF_BkUp_Read_MSBticks + 0x080010cc 0x20 ./Core/Src/timer_if.o + .text.GetTimerTicks + 0x080010ec 0x38 ./Core/Src/timer_if.o + .text.LL_AHB2_GRP1_EnableClock + 0x08001124 0x30 ./Core/Src/usart.o + .text.LL_APB1_GRP1_EnableClock + 0x08001154 0x30 ./Core/Src/usart.o + .text.LL_APB1_GRP1_DisableClock + 0x08001184 0x24 ./Core/Src/usart.o + .text.MX_USART2_UART_Init + 0x080011a8 0x98 ./Core/Src/usart.o + 0x080011a8 MX_USART2_UART_Init + .text.HAL_UART_MspInit + 0x08001240 0x108 ./Core/Src/usart.o + 0x08001240 HAL_UART_MspInit + .text.HAL_UART_MspDeInit + 0x08001348 0x40 ./Core/Src/usart.o + 0x08001348 HAL_UART_MspDeInit + .text.LL_APB1_GRP1_ForceReset + 0x08001388 0x22 ./Core/Src/usart_if.o + .text.LL_APB1_GRP1_ReleaseReset + 0x080013aa 0x24 ./Core/Src/usart_if.o + *fill* 0x080013ce 0x2 + .text.LL_EXTI_EnableIT_0_31 + 0x080013d0 0x28 ./Core/Src/usart_if.o + .text.vcom_Init + 0x080013f8 0x2c ./Core/Src/usart_if.o + 0x080013f8 vcom_Init + .text.vcom_DeInit + 0x08001424 0x2c ./Core/Src/usart_if.o + 0x08001424 vcom_DeInit + .text.vcom_Trace_DMA + 0x08001450 0x28 ./Core/Src/usart_if.o + 0x08001450 vcom_Trace_DMA + .text.vcom_ReceiveInit + 0x08001478 0x7c ./Core/Src/usart_if.o + 0x08001478 vcom_ReceiveInit + .text.vcom_Resume + 0x080014f4 0x30 ./Core/Src/usart_if.o + 0x080014f4 vcom_Resume + .text.HAL_UART_TxCpltCallback + 0x08001524 0x2c ./Core/Src/usart_if.o + 0x08001524 HAL_UART_TxCpltCallback + .text.HAL_UART_RxCpltCallback + 0x08001550 0x50 ./Core/Src/usart_if.o + 0x08001550 HAL_UART_RxCpltCallback + .text.Reset_Handler + 0x080015a0 0x50 ./Core/Startup/startup_stm32wl55jcix.o + 0x080015a0 Reset_Handler + .text.Default_Handler + 0x080015f0 0x2 ./Core/Startup/startup_stm32wl55jcix.o + 0x080015f0 EXTI2_IRQHandler + 0x080015f0 TIM1_CC_IRQHandler + 0x080015f0 EXTI3_IRQHandler + 0x080015f0 LPTIM2_IRQHandler + 0x080015f0 I2C3_ER_IRQHandler + 0x080015f0 LPTIM3_IRQHandler + 0x080015f0 I2C2_EV_IRQHandler + 0x080015f0 SPI1_IRQHandler + 0x080015f0 DMA2_Channel2_IRQHandler + 0x080015f0 DMA1_Channel4_IRQHandler + 0x080015f0 PKA_IRQHandler + 0x080015f0 TIM17_IRQHandler + 0x080015f0 DMA1_Channel7_IRQHandler + 0x080015f0 SUBGHZSPI_IRQHandler + 0x080015f0 IPCC_C1_TX_IRQHandler + 0x080015f0 DMA2_Channel1_IRQHandler + 0x080015f0 I2C1_EV_IRQHandler + 0x080015f0 DMAMUX1_OVR_IRQHandler + 0x080015f0 DMA1_Channel6_IRQHandler + 0x080015f0 TIM16_IRQHandler + 0x080015f0 DMA2_Channel4_IRQHandler + 0x080015f0 RCC_IRQHandler + 0x080015f0 TIM1_TRG_COM_IRQHandler + 0x080015f0 DMA1_Channel1_IRQHandler + 0x080015f0 Default_Handler + 0x080015f0 DMA2_Channel7_IRQHandler + 0x080015f0 EXTI15_10_IRQHandler + 0x080015f0 IPCC_C1_RX_IRQHandler + 0x080015f0 ADC_IRQHandler + 0x080015f0 C2SEV_PWR_C2H_IRQHandler + 0x080015f0 I2C3_EV_IRQHandler + 0x080015f0 RTC_WKUP_IRQHandler + 0x080015f0 PVD_PVM_IRQHandler + 0x080015f0 SPI2_IRQHandler + 0x080015f0 DMA2_Channel5_IRQHandler + 0x080015f0 EXTI4_IRQHandler + 0x080015f0 RNG_IRQHandler + 0x080015f0 DMA1_Channel3_IRQHandler + 0x080015f0 COMP_IRQHandler + 0x080015f0 HSEM_IRQHandler + 0x080015f0 TIM1_UP_IRQHandler + 0x080015f0 WWDG_IRQHandler + 0x080015f0 LPUART1_IRQHandler + 0x080015f0 DMA2_Channel6_IRQHandler + 0x080015f0 TIM2_IRQHandler + 0x080015f0 TIM1_BRK_IRQHandler + 0x080015f0 DAC_IRQHandler + 0x080015f0 AES_IRQHandler + 0x080015f0 I2C2_ER_IRQHandler + 0x080015f0 DMA1_Channel2_IRQHandler + 0x080015f0 FLASH_IRQHandler + 0x080015f0 USART1_IRQHandler + 0x080015f0 I2C1_ER_IRQHandler + 0x080015f0 LPTIM1_IRQHandler + 0x080015f0 DMA2_Channel3_IRQHandler + .text.LL_AHB2_GRP1_EnableClock + 0x080015f2 0x30 ./Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo_radio.o + *fill* 0x08001622 0x2 + .text.BSP_RADIO_Init + 0x08001624 0x7c ./Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo_radio.o + 0x08001624 BSP_RADIO_Init + .text.BSP_RADIO_ConfigRFSwitch + 0x080016a0 0xb8 ./Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo_radio.o + 0x080016a0 BSP_RADIO_ConfigRFSwitch + .text.BSP_RADIO_GetTxConfig + 0x08001758 0xe ./Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo_radio.o + 0x08001758 BSP_RADIO_GetTxConfig + .text.BSP_RADIO_IsTCXO + 0x08001766 0xe ./Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo_radio.o + 0x08001766 BSP_RADIO_IsTCXO + .text.BSP_RADIO_IsDCDC + 0x08001774 0xe ./Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo_radio.o + 0x08001774 BSP_RADIO_IsDCDC + .text.BSP_RADIO_GetRFOMaxPowerConfig + 0x08001782 0x26 ./Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo_radio.o + 0x08001782 BSP_RADIO_GetRFOMaxPowerConfig + .text.LL_DBGMCU_EnableDBGSleepMode + 0x080017a8 0x1c ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.o + .text.LL_DBGMCU_EnableDBGStopMode + 0x080017c4 0x1c ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.o + .text.LL_DBGMCU_EnableDBGStandbyMode + 0x080017e0 0x1c ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.o + .text.HAL_Init + 0x080017fc 0x40 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.o + 0x080017fc HAL_Init + .text.HAL_SuspendTick + 0x0800183c 0x1c ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.o + 0x0800183c HAL_SuspendTick + .text.HAL_ResumeTick + 0x08001858 0x1c ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.o + 0x08001858 HAL_ResumeTick + .text.HAL_DBGMCU_EnableDBGSleepMode + 0x08001874 0xc ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.o + 0x08001874 HAL_DBGMCU_EnableDBGSleepMode + .text.HAL_DBGMCU_EnableDBGStopMode + 0x08001880 0xc ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.o + 0x08001880 HAL_DBGMCU_EnableDBGStopMode + .text.HAL_DBGMCU_EnableDBGStandbyMode + 0x0800188c 0xc ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.o + 0x0800188c HAL_DBGMCU_EnableDBGStandbyMode + .text.__NVIC_SetPriorityGrouping + 0x08001898 0x48 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.o + .text.__NVIC_GetPriorityGrouping + 0x080018e0 0x1c ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.o + .text.__NVIC_EnableIRQ + 0x080018fc 0x38 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.o + .text.__NVIC_DisableIRQ + 0x08001934 0x48 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.o + .text.__NVIC_SetPriority + 0x0800197c 0x54 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.o + .text.NVIC_EncodePriority + 0x080019d0 0x64 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.o + .text.HAL_NVIC_SetPriorityGrouping + 0x08001a34 0x16 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.o + 0x08001a34 HAL_NVIC_SetPriorityGrouping + .text.HAL_NVIC_SetPriority + 0x08001a4a 0x34 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.o + 0x08001a4a HAL_NVIC_SetPriority + .text.HAL_NVIC_EnableIRQ + 0x08001a7e 0x1c ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.o + 0x08001a7e HAL_NVIC_EnableIRQ + .text.HAL_NVIC_DisableIRQ + 0x08001a9a 0x1c ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.o + 0x08001a9a HAL_NVIC_DisableIRQ + *fill* 0x08001ab6 0x2 + .text.HAL_DMA_Init + 0x08001ab8 0x150 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.o + 0x08001ab8 HAL_DMA_Init + .text.HAL_DMA_DeInit + 0x08001c08 0x12c ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.o + 0x08001c08 HAL_DMA_DeInit + .text.HAL_DMA_Start_IT + 0x08001d34 0xfc ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.o + 0x08001d34 HAL_DMA_Start_IT + .text.HAL_DMA_Abort + 0x08001e30 0xbc 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.text.HAL_SUBGHZ_ReadRegisters + 0x0800492a 0xc2 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.o + 0x0800492a HAL_SUBGHZ_ReadRegisters + .text.HAL_SUBGHZ_ExecSetCmd + 0x080049ec 0xbe ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.o + 0x080049ec HAL_SUBGHZ_ExecSetCmd + .text.HAL_SUBGHZ_ExecGetCmd + 0x08004aaa 0xa8 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.o + 0x08004aaa HAL_SUBGHZ_ExecGetCmd + .text.HAL_SUBGHZ_WriteBuffer + 0x08004b52 0xa6 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.o + 0x08004b52 HAL_SUBGHZ_WriteBuffer + .text.HAL_SUBGHZ_ReadBuffer + 0x08004bf8 0xb0 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.o + 0x08004bf8 HAL_SUBGHZ_ReadBuffer + .text.HAL_SUBGHZ_IRQHandler + 0x08004ca8 0x128 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.o + 0x08004ca8 HAL_SUBGHZ_IRQHandler + .text.SUBGHZSPI_Init + 0x08004dd0 0x40 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.o + 0x08004dd0 SUBGHZSPI_Init + .text.SUBGHZSPI_Transmit + 0x08004e10 0xac ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.o + 0x08004e10 SUBGHZSPI_Transmit + .text.SUBGHZSPI_Receive + 0x08004ebc 0xb0 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.o + 0x08004ebc SUBGHZSPI_Receive + .text.SUBGHZ_CheckDeviceReady + 0x08004f6c 0x40 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.o + 0x08004f6c SUBGHZ_CheckDeviceReady + .text.SUBGHZ_WaitOnBusy + 0x08004fac 0x5c ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.o + 0x08004fac SUBGHZ_WaitOnBusy + .text.LL_RCC_GetUSARTClockSource + 0x08005008 0x24 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.o + .text.LL_RCC_GetLPUARTClockSource + 0x0800502c 0x1e ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.o + .text.HAL_UART_Init + 0x0800504a 0xa0 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.o + 0x0800504a HAL_UART_Init + *fill* 0x080050ea 0x2 + .text.HAL_UART_Receive_IT + 0x080050ec 0x98 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.o + 0x080050ec HAL_UART_Receive_IT + .text.HAL_UART_Transmit_DMA + 0x08005184 0x100 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.o + 0x08005184 HAL_UART_Transmit_DMA + .text.HAL_UART_IRQHandler + 0x08005284 0x684 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.o + 0x08005284 HAL_UART_IRQHandler + .text.HAL_UART_TxHalfCpltCallback + 0x08005908 0x12 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.o + 0x08005908 HAL_UART_TxHalfCpltCallback + .text.HAL_UART_ErrorCallback + 0x0800591a 0x12 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.o + 0x0800591a HAL_UART_ErrorCallback + .text.HAL_UARTEx_RxEventCallback + 0x0800592c 0x16 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.o + 0x0800592c HAL_UARTEx_RxEventCallback + *fill* 0x08005942 0x2 + .text.UART_SetConfig + 0x08005944 0x4e8 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.o + 0x08005944 UART_SetConfig + .text.UART_AdvFeatureConfig + 0x08005e2c 0x142 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.o + 0x08005e2c UART_AdvFeatureConfig + .text.UART_CheckIdleState + 0x08005f6e 0x154 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.o + 0x08005f6e UART_CheckIdleState + .text.UART_WaitOnFlagUntilTimeout + 0x080060c2 0xda ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.o + 0x080060c2 UART_WaitOnFlagUntilTimeout + .text.UART_Start_Receive_IT + 0x0800619c 0x240 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.o + 0x0800619c UART_Start_Receive_IT + .text.UART_EndTxTransfer + 0x080063dc 0x80 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.o + .text.UART_EndRxTransfer + 0x0800645c 0xca ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.o + .text.UART_DMATransmitCplt + 0x08006526 0x92 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.o + .text.UART_DMATxHalfCplt + 0x080065b8 0x1c ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.o + .text.UART_DMAError + 0x080065d4 0x70 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.o + .text.UART_DMAAbortOnError + 0x08006644 0x1c ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.o + .text.UART_EndTransmit_IT + 0x08006660 0x56 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.o + *fill* 0x080066b6 0x2 + .text.UART_RxISR_8BIT + 0x080066b8 0x1b8 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.o + .text.UART_RxISR_16BIT + 0x08006870 0x1b8 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.o + .text.UART_RxISR_8BIT_FIFOEN + 0x08006a28 0x364 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.o + .text.UART_RxISR_16BIT_FIFOEN + 0x08006d8c 0x36c ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.o + .text.HAL_UARTEx_WakeupCallback + 0x080070f8 0x12 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.o + 0x080070f8 HAL_UARTEx_WakeupCallback + .text.HAL_UARTEx_RxFifoFullCallback + 0x0800710a 0x12 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.o + 0x0800710a HAL_UARTEx_RxFifoFullCallback + .text.HAL_UARTEx_TxFifoEmptyCallback + 0x0800711c 0x12 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.o + 0x0800711c HAL_UARTEx_TxFifoEmptyCallback + .text.HAL_UARTEx_StopModeWakeUpSourceConfig + 0x0800712e 0xb6 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.o + 0x0800712e HAL_UARTEx_StopModeWakeUpSourceConfig + .text.HAL_UARTEx_EnableStopMode + 0x080071e4 0x64 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.o + 0x080071e4 HAL_UARTEx_EnableStopMode + .text.HAL_UARTEx_EnableFifoMode + 0x08007248 0x76 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.o + 0x08007248 HAL_UARTEx_EnableFifoMode + .text.HAL_UARTEx_SetTxFifoThreshold + 0x080072be 0x7c ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.o + 0x080072be HAL_UARTEx_SetTxFifoThreshold + .text.HAL_UARTEx_SetRxFifoThreshold + 0x0800733a 0x7c ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.o + 0x0800733a HAL_UARTEx_SetRxFifoThreshold + .text.UARTEx_Wakeup_AddressConfig + 0x080073b6 0x44 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.o + *fill* 0x080073fa 0x2 + .text.UARTEx_SetNbDataToProcess + 0x080073fc 0x98 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.o + .text.LL_GPIO_SetOutputPin + 0x08007494 0x1a ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + .text.LL_GPIO_ResetOutputPin + 0x080074ae 0x1a ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + .text.RadioInit + 0x080074c8 0xb8 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + .text.RadioGetStatus + 0x08007580 0x2e ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + *fill* 0x080075ae 0x2 + .text.RadioSetModem + 0x080075b0 0xb8 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + .text.RadioSetChannel + 0x08007668 0x16 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + .text.RadioIsChannelFree + 0x0800767e 0xb4 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + .text.RadioRandom + 0x08007732 0x26 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + .text.RadioSetRxConfig + 0x08007758 0x418 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + .text.RadioSetTxConfig + 0x08007b70 0x224 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + .text.RadioCheckRfFrequency + 0x08007d94 0x14 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + .text.RadioGetLoRaBandwidthInHz + 0x08007da8 0xac ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + .text.RadioGetGfskTimeOnAirNumerator + 0x08007e54 0x54 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + .text.RadioGetLoRaTimeOnAirNumerator + 0x08007ea8 0x102 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + *fill* 0x08007faa 0x2 + .text.RadioTimeOnAir + 0x08007fac 0xb0 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + .text.RadioSend + 0x0800805c 0x20c ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + .text.RadioSleep + 0x08008268 0x26 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + .text.RadioStandby + 0x0800828e 0xe ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + .text.RadioRx 0x0800829c 0x8c ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + .text.RadioRxBoosted + 0x08008328 0x8c ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + .text.RadioSetRxDutyCycle + 0x080083b4 0x48 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + .text.RadioStartCad + 0x080083fc 0x30 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + .text.RadioSetTxContinuousWave + 0x0800842c 0x64 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + .text.RadioRssi + 0x08008490 0x18 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + .text.RadioWrite + 0x080084a8 0x24 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + .text.RadioRead + 0x080084cc 0x1c ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + .text.RadioWriteRegisters + 0x080084e8 0x26 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + .text.RadioReadRegisters + 0x0800850e 0x26 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + .text.RadioSetMaxPayloadLength + 0x08008534 0x5c ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + .text.RadioSetPublicNetwork + 0x08008590 0x5c ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + .text.RadioGetWakeupTime + 0x080085ec 0x10 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + .text.RadioOnTxTimeoutIrq + 0x080085fc 0x14 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + .text.RadioOnRxTimeoutIrq + 0x08008610 0x14 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + .text.RadioOnTxTimeoutProcess + 0x08008624 0x34 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + .text.RadioOnRxTimeoutProcess + 0x08008658 0x34 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + .text.RadioOnDioIrq + 0x0800868c 0x24 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + .text.RadioIrqProcess + 0x080086b0 0x478 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + .text.RadioTxPrbs + 0x08008b28 0x38 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + .text.RadioTxCw + 0x08008b60 0x38 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + .text.payload_integration + 0x08008b98 0x124 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + .text.RadioSetRxGenericConfig + 0x08008cbc 0x38c ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + .text.RadioSetTxGenericConfig + 0x08009048 0x470 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + .text.RadioLrFhssSetCfg + 0x080094b8 0x18 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + .text.RadioLrFhssGetTimeOnAirInMs + 0x080094d0 0x16 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + *fill* 0x080094e6 0x2 + .text.SUBGRF_Init + 0x080094e8 0x90 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x080094e8 SUBGRF_Init + .text.SUBGRF_GetOperatingMode + 0x08009578 0x14 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x08009578 SUBGRF_GetOperatingMode + .text.SUBGRF_SetPayload + 0x0800958c 0x20 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x0800958c SUBGRF_SetPayload + .text.SUBGRF_GetPayload + 0x080095ac 0x44 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x080095ac SUBGRF_GetPayload + .text.SUBGRF_SendPayload + 0x080095f0 0x26 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x080095f0 SUBGRF_SendPayload + .text.SUBGRF_SetSyncWord + 0x08009616 0x1e ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x08009616 SUBGRF_SetSyncWord + .text.SUBGRF_SetCrcSeed + 0x08009634 0x40 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x08009634 SUBGRF_SetCrcSeed + .text.SUBGRF_SetCrcPolynomial + 0x08009674 0x40 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x08009674 SUBGRF_SetCrcPolynomial + .text.SUBGRF_SetWhiteningSeed + 0x080096b4 0x66 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x080096b4 SUBGRF_SetWhiteningSeed + .text.SUBGRF_GetRandom + 0x0800971a 0x8c ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x0800971a SUBGRF_GetRandom + *fill* 0x080097a6 0x2 + .text.SUBGRF_SetSleep + 0x080097a8 0x68 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x080097a8 SUBGRF_SetSleep + .text.SUBGRF_SetStandby + 0x08009810 0x38 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x08009810 SUBGRF_SetStandby + .text.SUBGRF_SetTx + 0x08009848 0x40 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x08009848 SUBGRF_SetTx + .text.SUBGRF_SetRx + 0x08009888 0x40 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x08009888 SUBGRF_SetRx + .text.SUBGRF_SetRxBoosted + 0x080098c8 0x48 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x080098c8 SUBGRF_SetRxBoosted + .text.SUBGRF_SetRxDutyCycle + 0x08009910 0x58 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x08009910 SUBGRF_SetRxDutyCycle + .text.SUBGRF_SetCad + 0x08009968 0x1c ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x08009968 SUBGRF_SetCad + .text.SUBGRF_SetTxContinuousWave + 0x08009984 0x12 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x08009984 SUBGRF_SetTxContinuousWave + .text.SUBGRF_SetTxInfinitePreamble + 0x08009996 0x12 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x08009996 SUBGRF_SetTxInfinitePreamble + .text.SUBGRF_SetStopRxTimerOnPreambleDetect + 0x080099a8 0x1e ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x080099a8 SUBGRF_SetStopRxTimerOnPreambleDetect + .text.SUBGRF_SetLoRaSymbNumTimeout + 0x080099c6 0x5e ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x080099c6 SUBGRF_SetLoRaSymbNumTimeout + .text.SUBGRF_SetRegulatorMode + 0x08009a24 0x2e ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x08009a24 SUBGRF_SetRegulatorMode + .text.SUBGRF_Calibrate + 0x08009a52 0x98 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x08009a52 SUBGRF_Calibrate + *fill* 0x08009aea 0x2 + .text.SUBGRF_CalibrateImage + 0x08009aec 0x94 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x08009aec SUBGRF_CalibrateImage + .text.SUBGRF_SetPaConfig + 0x08009b80 0x44 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x08009b80 SUBGRF_SetPaConfig + .text.SUBGRF_SetDioIrqParams + 0x08009bc4 0x74 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x08009bc4 SUBGRF_SetDioIrqParams + .text.SUBGRF_SetTcxoMode + 0x08009c38 0x42 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x08009c38 SUBGRF_SetTcxoMode + *fill* 0x08009c7a 0x2 + .text.SUBGRF_SetRfFrequency + 0x08009c7c 0x8c ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x08009c7c SUBGRF_SetRfFrequency + .text.SUBGRF_SetPacketType + 0x08009d08 0x38 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x08009d08 SUBGRF_SetPacketType + .text.SUBGRF_GetPacketType + 0x08009d40 0x14 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x08009d40 SUBGRF_GetPacketType + .text.SUBGRF_SetTxParams + 0x08009d54 0x19a ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x08009d54 SUBGRF_SetTxParams + *fill* 0x08009eee 0x2 + .text.SUBGRF_SetModulationParams + 0x08009ef0 0x19c ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x08009ef0 SUBGRF_SetModulationParams + .text.SUBGRF_SetPacketParams + 0x0800a08c 0x138 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x0800a08c SUBGRF_SetPacketParams + .text.SUBGRF_SetBufferBaseAddress + 0x0800a1c4 0x2e ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x0800a1c4 SUBGRF_SetBufferBaseAddress + .text.SUBGRF_GetRssiInst + 0x0800a1f2 0x2a ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x0800a1f2 SUBGRF_GetRssiInst + .text.SUBGRF_GetRxBufferStatus + 0x0800a21c 0x58 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x0800a21c SUBGRF_GetRxBufferStatus + .text.SUBGRF_GetPacketStatus + 0x0800a274 0xa4 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x0800a274 SUBGRF_GetPacketStatus + .text.SUBGRF_WriteRegister + 0x0800a318 0x44 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x0800a318 SUBGRF_WriteRegister + .text.SUBGRF_ReadRegister + 0x0800a35c 0x40 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x0800a35c SUBGRF_ReadRegister + .text.SUBGRF_WriteRegisters + 0x0800a39c 0x44 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x0800a39c SUBGRF_WriteRegisters + .text.SUBGRF_ReadRegisters + 0x0800a3e0 0x44 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x0800a3e0 SUBGRF_ReadRegisters + .text.SUBGRF_WriteBuffer + 0x0800a424 0x44 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x0800a424 SUBGRF_WriteBuffer + .text.SUBGRF_ReadBuffer + 0x0800a468 0x44 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x0800a468 SUBGRF_ReadBuffer + .text.SUBGRF_WriteCommand + 0x0800a4ac 0x44 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x0800a4ac SUBGRF_WriteCommand + .text.SUBGRF_ReadCommand + 0x0800a4f0 0x44 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x0800a4f0 SUBGRF_ReadCommand + .text.SUBGRF_SetSwitch + 0x0800a534 0x50 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x0800a534 SUBGRF_SetSwitch + .text.SUBGRF_SetRfTxPower + 0x0800a584 0x68 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x0800a584 SUBGRF_SetRfTxPower + .text.SUBGRF_GetRadioWakeUpTime + 0x0800a5ec 0xe ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x0800a5ec SUBGRF_GetRadioWakeUpTime + *fill* 0x0800a5fa 0x2 + .text.HAL_SUBGHZ_TxCpltCallback + 0x0800a5fc 0x1c ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x0800a5fc HAL_SUBGHZ_TxCpltCallback + .text.HAL_SUBGHZ_RxCpltCallback + 0x0800a618 0x1c ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x0800a618 HAL_SUBGHZ_RxCpltCallback + .text.HAL_SUBGHZ_CRCErrorCallback + 0x0800a634 0x1c ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x0800a634 HAL_SUBGHZ_CRCErrorCallback + .text.HAL_SUBGHZ_CADStatusCallback + 0x0800a650 0x3c ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x0800a650 HAL_SUBGHZ_CADStatusCallback + .text.HAL_SUBGHZ_RxTxTimeoutCallback + 0x0800a68c 0x20 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x0800a68c HAL_SUBGHZ_RxTxTimeoutCallback + .text.HAL_SUBGHZ_HeaderErrorCallback + 0x0800a6ac 0x1c ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x0800a6ac HAL_SUBGHZ_HeaderErrorCallback + .text.HAL_SUBGHZ_PreambleDetectedCallback + 0x0800a6c8 0x1c ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x0800a6c8 HAL_SUBGHZ_PreambleDetectedCallback + .text.HAL_SUBGHZ_SyncWordValidCallback + 0x0800a6e4 0x1c ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x0800a6e4 HAL_SUBGHZ_SyncWordValidCallback + .text.HAL_SUBGHZ_HeaderValidCallback + 0x0800a700 0x1c ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x0800a700 HAL_SUBGHZ_HeaderValidCallback + .text.HAL_SUBGHZ_LrFhssHopCallback + 0x0800a71c 0x20 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x0800a71c HAL_SUBGHZ_LrFhssHopCallback + .text.Radio_SMPS_Set + 0x0800a73c 0x42 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + *fill* 0x0800a77e 0x2 + .text.SUBGRF_GetFskBandwidthRegValue + 0x0800a780 0x50 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x0800a780 SUBGRF_GetFskBandwidthRegValue + .text.SUBGRF_GetCFO + 0x0800a7d0 0xe8 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x0800a7d0 SUBGRF_GetCFO + .text.LL_DBGMCU_GetRevisionID + 0x0800a8b8 0x18 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.o + .text.LL_GPIO_SetOutputPin + 0x0800a8d0 0x1a ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.o + .text.LL_GPIO_ResetOutputPin + 0x0800a8ea 0x1a ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.o + .text.RFW_TransmitLongPacket + 0x0800a904 0x2f4 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.o + 0x0800a904 RFW_TransmitLongPacket + .text.RFW_ReceiveLongPacket + 0x0800abf8 0xcc ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.o + 0x0800abf8 RFW_ReceiveLongPacket + .text.RFW_Init + 0x0800acc4 0x134 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.o + 0x0800acc4 RFW_Init + .text.RFW_DeInit + 0x0800adf8 0x18 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.o + 0x0800adf8 RFW_DeInit + .text.RFW_Is_Init + 0x0800ae10 0x14 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.o + 0x0800ae10 RFW_Is_Init + .text.RFW_Is_LongPacketModeEnabled + 0x0800ae24 0x14 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.o + 0x0800ae24 RFW_Is_LongPacketModeEnabled + .text.RFW_SetAntSwitch + 0x0800ae38 0x20 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.o + 0x0800ae38 RFW_SetAntSwitch + .text.RFW_TransmitInit + 0x0800ae58 0x10c ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.o + 0x0800ae58 RFW_TransmitInit + .text.RFW_ReceiveInit + 0x0800af64 0x38 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.o + 0x0800af64 RFW_ReceiveInit + .text.RFW_DeInit_TxLongPacket + 0x0800af9c 0x36 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.o + 0x0800af9c RFW_DeInit_TxLongPacket + *fill* 0x0800afd2 0x2 + .text.RFW_ReceivePayload + 0x0800afd4 0xf8 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.o + 0x0800afd4 RFW_ReceivePayload + .text.RFW_SetRadioModem + 0x0800b0cc 0x20 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.o + 0x0800b0cc RFW_SetRadioModem + .text.RFW_TransmitLongPacket_NewTxChunkTimerEvent + 0x0800b0ec 0x14 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.o + .text.RFW_TransmitLongPacket_TxChunkProcess + 0x0800b100 0x1d0 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.o + .text.RFW_WhiteInitState + 0x0800b2d0 0x1c ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.o + .text.RFW_WhiteSetState + 0x0800b2ec 0x1a ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.o + .text.RFW_CrcInitState + 0x0800b306 0x36 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.o + .text.RFW_CrcSetState + 0x0800b33c 0x1a ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.o + .text.RFW_WhiteRun + 0x0800b356 0x90 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.o + .text.RFW_CrcRun + 0x0800b3e6 0x98 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.o + .text.RFW_CrcRun1Byte + 0x0800b47e 0x5c ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.o + 0x0800b47e RFW_CrcRun1Byte + *fill* 0x0800b4da 0x2 + .text.RFW_PollRxBytes + 0x0800b4dc 0x78 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.o + .text.RFW_GetPacketLength + 0x0800b554 0xac ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.o + .text.RFW_GetPayloadTimerEvent + 0x0800b600 0x14 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.o + .text.RFW_GetPayloadProcess + 0x0800b614 0x240 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.o + .text.RFW_GetPayload + 0x0800b854 0x19c ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.o + .text.MX_SubGHz_Phy_Init + 0x0800b9f0 0x10 ./SubGHz_Phy/App/app_subghz_phy.o + 0x0800b9f0 MX_SubGHz_Phy_Init + .text.MX_SubGHz_Phy_Process + 0x0800ba00 0x10 ./SubGHz_Phy/App/app_subghz_phy.o + 0x0800ba00 MX_SubGHz_Phy_Process + .text.SubghzApp_Init + 0x0800ba10 0x184 ./SubGHz_Phy/App/subghz_phy_app.o + 0x0800ba10 SubghzApp_Init + .text.OnTxDone + 0x0800bb94 0x1c ./SubGHz_Phy/App/subghz_phy_app.o + .text.OnRxDone + 0x0800bbb0 0x64 ./SubGHz_Phy/App/subghz_phy_app.o + .text.OnTxTimeout + 0x0800bc14 0x1c ./SubGHz_Phy/App/subghz_phy_app.o + .text.OnRxTimeout + 0x0800bc30 0x1c ./SubGHz_Phy/App/subghz_phy_app.o + .text.OnRxError + 0x0800bc4c 0x1c ./SubGHz_Phy/App/subghz_phy_app.o + .text.Per_Process + 0x0800bc68 0xe8 ./SubGHz_Phy/App/subghz_phy_app.o + .text.HAL_GPIO_EXTI_Callback + 0x0800bd50 0xf0 ./SubGHz_Phy/App/subghz_phy_app.o + 0x0800bd50 HAL_GPIO_EXTI_Callback + .text.tx_payload_generator + 0x0800be40 0xf0 ./SubGHz_Phy/App/subghz_phy_app.o + .text.RBI_Init + 0x0800bf30 0xe ./SubGHz_Phy/Target/radio_board_if.o + 0x0800bf30 RBI_Init + .text.RBI_ConfigRFSwitch + 0x0800bf3e 0x1c ./SubGHz_Phy/Target/radio_board_if.o + 0x0800bf3e RBI_ConfigRFSwitch + .text.RBI_GetTxConfig + 0x0800bf5a 0xe ./SubGHz_Phy/Target/radio_board_if.o + 0x0800bf5a RBI_GetTxConfig + .text.RBI_IsTCXO + 0x0800bf68 0xe ./SubGHz_Phy/Target/radio_board_if.o + 0x0800bf68 RBI_IsTCXO + .text.RBI_IsDCDC + 0x0800bf76 0xe ./SubGHz_Phy/Target/radio_board_if.o + 0x0800bf76 RBI_IsDCDC + .text.RBI_GetRFOMaxPowerConfig + 0x0800bf84 0x1c ./SubGHz_Phy/Target/radio_board_if.o + 0x0800bf84 RBI_GetRFOMaxPowerConfig + .text.UTIL_LPM_Init + 0x0800bfa0 0x20 ./Utilities/lpm/tiny_lpm/stm32_lpm.o + 0x0800bfa0 UTIL_LPM_Init + .text.UTIL_LPM_SetStopMode + 0x0800bfc0 0x60 ./Utilities/lpm/tiny_lpm/stm32_lpm.o + 0x0800bfc0 UTIL_LPM_SetStopMode + .text.UTIL_LPM_SetOffMode + 0x0800c020 0x60 ./Utilities/lpm/tiny_lpm/stm32_lpm.o + 0x0800c020 UTIL_LPM_SetOffMode + .text.UTIL_LPM_EnterLowPower + 0x0800c080 0x6c ./Utilities/lpm/tiny_lpm/stm32_lpm.o + 0x0800c080 UTIL_LPM_EnterLowPower + .text.UTIL_MEM_cpy_8 + 0x0800c0ec 0x3e ./Utilities/misc/stm32_mem.o + 0x0800c0ec UTIL_MEM_cpy_8 + .text.UTIL_MEM_set_8 + 0x0800c12a 0x36 ./Utilities/misc/stm32_mem.o + 0x0800c12a UTIL_MEM_set_8 + .text.SysTimeAdd + 0x0800c160 0x72 ./Utilities/misc/stm32_systime.o + 0x0800c160 SysTimeAdd + *fill* 0x0800c1d2 0x2 + .text.SysTimeGet + 0x0800c1d4 0x70 ./Utilities/misc/stm32_systime.o + 0x0800c1d4 SysTimeGet + .text.ee_skip_atoi + 0x0800c244 0x4c ./Utilities/misc/stm32_tiny_vsnprintf.o + .text.ee_number + 0x0800c290 0x1dc ./Utilities/misc/stm32_tiny_vsnprintf.o + .text.tiny_vsnprintf_like + 0x0800c46c 0x2a4 ./Utilities/misc/stm32_tiny_vsnprintf.o + 0x0800c46c tiny_vsnprintf_like + .text.UTIL_SEQ_Run + 0x0800c710 0x1f8 ./Utilities/sequencer/stm32_seq.o + 0x0800c710 UTIL_SEQ_Run + .text.UTIL_SEQ_RegTask + 0x0800c908 0x44 ./Utilities/sequencer/stm32_seq.o + 0x0800c908 UTIL_SEQ_RegTask + .text.UTIL_SEQ_SetTask + 0x0800c94c 0x58 ./Utilities/sequencer/stm32_seq.o + 0x0800c94c UTIL_SEQ_SetTask + .text.UTIL_SEQ_PreIdle + 0x0800c9a4 0xc ./Utilities/sequencer/stm32_seq.o + 0x0800c9a4 UTIL_SEQ_PreIdle + .text.UTIL_SEQ_PostIdle + 0x0800c9b0 0xc ./Utilities/sequencer/stm32_seq.o + 0x0800c9b0 UTIL_SEQ_PostIdle + .text.SEQ_BitPosition + 0x0800c9bc 0x70 ./Utilities/sequencer/stm32_seq.o + 0x0800c9bc SEQ_BitPosition + .text.UTIL_TIMER_Init + 0x0800ca2c 0x20 ./Utilities/timer/stm32_timer.o + 0x0800ca2c UTIL_TIMER_Init + .text.UTIL_TIMER_Create + 0x0800ca4c 0x6c ./Utilities/timer/stm32_timer.o + 0x0800ca4c UTIL_TIMER_Create + .text.UTIL_TIMER_Start + 0x0800cab8 0xdc ./Utilities/timer/stm32_timer.o + 0x0800cab8 UTIL_TIMER_Start + .text.UTIL_TIMER_Stop + 0x0800cb94 0xe0 ./Utilities/timer/stm32_timer.o + 0x0800cb94 UTIL_TIMER_Stop + .text.UTIL_TIMER_SetPeriod + 0x0800cc74 0x54 ./Utilities/timer/stm32_timer.o + 0x0800cc74 UTIL_TIMER_SetPeriod + .text.UTIL_TIMER_IRQ_Handler + 0x0800ccc8 0x100 ./Utilities/timer/stm32_timer.o + 0x0800ccc8 UTIL_TIMER_IRQ_Handler + .text.UTIL_TIMER_GetCurrentTime + 0x0800cdc8 0x24 ./Utilities/timer/stm32_timer.o + 0x0800cdc8 UTIL_TIMER_GetCurrentTime + .text.UTIL_TIMER_GetElapsedTime + 0x0800cdec 0x38 ./Utilities/timer/stm32_timer.o + 0x0800cdec UTIL_TIMER_GetElapsedTime + .text.TimerExists + 0x0800ce24 0x38 ./Utilities/timer/stm32_timer.o + 0x0800ce24 TimerExists + .text.TimerSetTimeout + 0x0800ce5c 0x54 ./Utilities/timer/stm32_timer.o + 0x0800ce5c TimerSetTimeout + .text.TimerInsertTimer + 0x0800ceb0 0x60 ./Utilities/timer/stm32_timer.o + 0x0800ceb0 TimerInsertTimer + .text.TimerInsertNewHeadTimer + 0x0800cf10 0x3c ./Utilities/timer/stm32_timer.o + 0x0800cf10 TimerInsertNewHeadTimer + .text.UTIL_ADV_TRACE_Init + 0x0800cf4c 0x38 ./Utilities/trace/adv_trace/stm32_adv_trace.o + 0x0800cf4c UTIL_ADV_TRACE_Init + .text.UTIL_ADV_TRACE_COND_FSend + 0x0800cf84 0x100 ./Utilities/trace/adv_trace/stm32_adv_trace.o + 0x0800cf84 UTIL_ADV_TRACE_COND_FSend + .text.UTIL_ADV_TRACE_RegisterTimeStampFunction + 0x0800d084 0x1c ./Utilities/trace/adv_trace/stm32_adv_trace.o + 0x0800d084 UTIL_ADV_TRACE_RegisterTimeStampFunction + .text.UTIL_ADV_TRACE_SetVerboseLevel + 0x0800d0a0 0x20 ./Utilities/trace/adv_trace/stm32_adv_trace.o + 0x0800d0a0 UTIL_ADV_TRACE_SetVerboseLevel + .text.TRACE_Send + 0x0800d0c0 0x108 ./Utilities/trace/adv_trace/stm32_adv_trace.o + .text.TRACE_TxCpltCallback + 0x0800d1c8 0x118 ./Utilities/trace/adv_trace/stm32_adv_trace.o + .text.TRACE_AllocateBufer + 0x0800d2e0 0xfc ./Utilities/trace/adv_trace/stm32_adv_trace.o + .text.TRACE_Lock + 0x0800d3dc 0x3c ./Utilities/trace/adv_trace/stm32_adv_trace.o + .text.TRACE_UnLock + 0x0800d418 0x3c ./Utilities/trace/adv_trace/stm32_adv_trace.o + .text.TRACE_IsLocked + 0x0800d454 0x20 ./Utilities/trace/adv_trace/stm32_adv_trace.o + .text.memset 0x0800d474 0x10 /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(libc_a-memset.o) + 0x0800d474 memset + .text.__libc_init_array + 0x0800d484 0x48 /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(libc_a-init.o) + 0x0800d484 __libc_init_array + .text.memcpy 0x0800d4cc 0x1c /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(libc_a-memcpy-stub.o) + 0x0800d4cc memcpy + *(.glue_7) + .glue_7 0x0800d4e8 0x0 linker stubs + *(.glue_7t) + .glue_7t 0x0800d4e8 0x0 linker stubs + *(.eh_frame) + .eh_frame 0x0800d4e8 0x0 /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m/nofp/crtbegin.o + *(.init) + .init 0x0800d4e8 0x4 /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m/nofp/crti.o + 0x0800d4e8 _init + .init 0x0800d4ec 0x8 /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m/nofp/crtn.o + *(.fini) + .fini 0x0800d4f4 0x4 /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m/nofp/crti.o + 0x0800d4f4 _fini + .fini 0x0800d4f8 0x8 /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m/nofp/crtn.o + 0x0800d500 . = ALIGN (0x4) + 0x0800d500 _etext = . + +.vfp11_veneer 0x0800d500 0x0 + .vfp11_veneer 0x0800d500 0x0 linker stubs + +.v4_bx 0x0800d500 0x0 + .v4_bx 0x0800d500 0x0 linker stubs + +.iplt 0x0800d500 0x0 + .iplt 0x0800d500 0x0 /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m/nofp/crtbegin.o + +.rodata 0x0800d500 0x630 + 0x0800d500 . = ALIGN (0x4) + *(.rodata) + .rodata 0x0800d500 0x9 ./Core/Src/sys_app.o + *fill* 0x0800d509 0x3 + .rodata 0x0800d50c 0x1c ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.o + .rodata 0x0800d528 0x7c ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + .rodata 0x0800d5a4 0x195 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.o + *fill* 0x0800d739 0x3 + .rodata 0x0800d73c 0x11b ./SubGHz_Phy/App/subghz_phy_app.o + *fill* 0x0800d857 0x1 + .rodata 0x0800d858 0x57 ./Utilities/misc/stm32_tiny_vsnprintf.o + *(.rodata*) + *fill* 0x0800d8af 0x1 + .rodata.UTIL_PowerDriver + 0x0800d8b0 0x18 ./Core/Src/stm32_lpm_if.o + 0x0800d8b0 UTIL_PowerDriver + .rodata.AHBPrescTable + 0x0800d8c8 0x40 ./Core/Src/system_stm32wlxx.o + 0x0800d8c8 AHBPrescTable + .rodata.APBPrescTable + 0x0800d908 0x20 ./Core/Src/system_stm32wlxx.o + 0x0800d908 APBPrescTable + .rodata.MSIRangeTable + 0x0800d928 0x40 ./Core/Src/system_stm32wlxx.o + 0x0800d928 MSIRangeTable + .rodata.UTIL_TimerDriver + 0x0800d968 0x2c ./Core/Src/timer_if.o + 0x0800d968 UTIL_TimerDriver + .rodata.UTIL_SYSTIMDriver + 0x0800d994 0x14 ./Core/Src/timer_if.o + 0x0800d994 UTIL_SYSTIMDriver + .rodata.UTIL_TraceDriver + 0x0800d9a8 0x10 ./Core/Src/usart_if.o + 0x0800d9a8 UTIL_TraceDriver + .rodata.UARTPrescTable + 0x0800d9b8 0x18 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.o + 0x0800d9b8 UARTPrescTable + .rodata.numerator.1 + 0x0800d9d0 0x8 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.o + .rodata.denominator.0 + 0x0800d9d8 0x8 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.o + .rodata.Radio 0x0800d9e0 0x8c ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + 0x0800d9e0 Radio + .rodata.Bandwidths + 0x0800da6c 0x3 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + 0x0800da6c Bandwidths + *fill* 0x0800da6f 0x1 + .rodata.FskBandwidths + 0x0800da70 0xb0 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + .rodata.SEQ_clz_table_4bit + 0x0800db20 0x10 ./Utilities/sequencer/stm32_seq.o + 0x0800db20 SEQ_clz_table_4bit + 0x0800db30 . = ALIGN (0x4) + +.ARM.extab 0x0800db30 0x0 + 0x0800db30 . = ALIGN (0x4) + *(.ARM.extab* .gnu.linkonce.armextab.*) + 0x0800db30 . = ALIGN (0x4) + +.ARM 0x0800db30 0x8 + 0x0800db30 . = ALIGN (0x4) + 0x0800db30 __exidx_start = . + *(.ARM.exidx*) + .ARM.exidx 0x0800db30 0x8 /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(libc_a-strlen.o) + .ARM.exidx 0x0800db38 0x0 /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m/nofp/libgcc.a(_udivmoddi4.o) + 0x8 (size before relaxing) + 0x0800db38 __exidx_end = . + 0x0800db38 . = ALIGN (0x4) + +.preinit_array 0x0800db38 0x0 + 0x0800db38 . = ALIGN (0x4) + 0x0800db38 PROVIDE (__preinit_array_start = .) + *(.preinit_array*) + 0x0800db38 PROVIDE (__preinit_array_end = .) + 0x0800db38 . = ALIGN (0x4) + +.init_array 0x0800db38 0x4 + 0x0800db38 . = ALIGN (0x4) + 0x0800db38 PROVIDE (__init_array_start = .) + *(SORT_BY_NAME(.init_array.*)) + *(.init_array*) + .init_array 0x0800db38 0x4 /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m/nofp/crtbegin.o + 0x0800db3c PROVIDE (__init_array_end = .) + 0x0800db3c . = ALIGN (0x4) + +.fini_array 0x0800db3c 0x4 + 0x0800db3c . = ALIGN (0x4) + [!provide] PROVIDE (__fini_array_start = .) + *(SORT_BY_NAME(.fini_array.*)) + *(.fini_array*) + .fini_array 0x0800db3c 0x4 /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m/nofp/crtbegin.o + [!provide] PROVIDE (__fini_array_end = .) + 0x0800db40 . = ALIGN (0x4) + 0x0800db40 _sidata = LOADADDR (.data) + +.rel.dyn 0x0800db40 0x0 + .rel.iplt 0x0800db40 0x0 /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m/nofp/crtbegin.o + +.data 0x20000000 0x24 load address 0x0800db40 + 0x20000000 . = ALIGN (0x4) + 0x20000000 _sdata = . + *(.data) + *(.data*) + .data.SystemCoreClock + 0x20000000 0x4 ./Core/Src/system_stm32wlxx.o + 0x20000000 SystemCoreClock + .data.uwTickPrio + 0x20000004 0x4 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.o + 0x20000004 uwTickPrio + .data.MaxPayloadLength + 0x20000008 0x1 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + *fill* 0x20000009 0x1 + .data.payloadLen + 0x2000000a 0x2 ./SubGHz_Phy/App/subghz_phy_app.o + .data.payloadLenMax + 0x2000000c 0x2 ./SubGHz_Phy/App/subghz_phy_app.o + *fill* 0x2000000e 0x2 + .data.syncword + 0x20000010 0x3 ./SubGHz_Phy/App/subghz_phy_app.o + *fill* 0x20000013 0x1 + .data.lower_digits + 0x20000014 0x4 ./Utilities/misc/stm32_tiny_vsnprintf.o + .data.upper_digits + 0x20000018 0x4 ./Utilities/misc/stm32_tiny_vsnprintf.o + .data.TaskMask + 0x2000001c 0x4 ./Utilities/sequencer/stm32_seq.o + .data.SuperMask + 0x20000020 0x4 ./Utilities/sequencer/stm32_seq.o + *(.RamFunc) + *(.RamFunc*) + 0x20000024 . = ALIGN (0x4) + 0x20000024 _edata = . + +.igot.plt 0x20000024 0x0 load address 0x0800db64 + .igot.plt 0x20000024 0x0 /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m/nofp/crtbegin.o + 0x20000024 . = ALIGN (0x4) + +.bss 0x20000024 0xcc4 load address 0x0800db64 + 0x20000024 _sbss = . + 0x20000024 __bss_start__ = _sbss + *(.bss) + .bss 0x20000024 0x1c /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m/nofp/crtbegin.o + *(.bss*) + .bss.hrtc 0x20000040 0x38 ./Core/Src/rtc.o + 0x20000040 hrtc + .bss.hsubghz 0x20000078 0xc ./Core/Src/subghz.o + 0x20000078 hsubghz + .bss.SYS_TimerInitialisedFlag + 0x20000084 0x1 ./Core/Src/sys_app.o + .bss.RTC_Initialized + 0x20000085 0x1 ./Core/Src/timer_if.o + *fill* 0x20000086 0x2 + .bss.RtcTimerContext + 0x20000088 0x4 ./Core/Src/timer_if.o + .bss.huart2 0x2000008c 0x94 ./Core/Src/usart.o + 0x2000008c huart2 + .bss.hdma_usart2_tx + 0x20000120 0x60 ./Core/Src/usart.o + 0x20000120 hdma_usart2_tx + .bss.charRx 0x20000180 0x1 ./Core/Src/usart_if.o + 0x20000180 charRx + *fill* 0x20000181 0x3 + .bss.TxCpltCallback + 0x20000184 0x4 ./Core/Src/usart_if.o + .bss.RxCpltCallback + 0x20000188 0x4 ./Core/Src/usart_if.o + .bss.RadioBuffer + 0x2000018c 0xff ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + *fill* 0x2000028b 0x1 + .bss.RadioEvents + 0x2000028c 0x4 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + .bss.SubgRf 0x20000290 0x5c ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + 0x20000290 SubgRf + .bss.TxTimeoutTimer + 0x200002ec 0x18 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + 0x200002ec TxTimeoutTimer + .bss.RxTimeoutTimer + 0x20000304 0x18 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + 0x20000304 RxTimeoutTimer + .bss.OperatingMode + 0x2000031c 0x1 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + .bss.PacketType + 0x2000031d 0x1 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + .bss.LoRaHeaderType + 0x2000031e 0x1 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + *fill* 0x2000031f 0x1 + .bss.FrequencyError + 0x20000320 0x4 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x20000320 FrequencyError + .bss.ImageCalibrated + 0x20000324 0x1 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + *fill* 0x20000325 0x3 + .bss.RadioOnDioIrqCb + 0x20000328 0x4 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + .bss.RFWPacket + 0x2000032c 0x54 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.o + .bss.ChunkBuffer + 0x20000380 0xff ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.o + *fill* 0x2000047f 0x1 + .bss.RxBuffer 0x20000480 0xff ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.o + *fill* 0x2000057f 0x1 + .bss.RadioEvents + 0x20000580 0x1c ./SubGHz_Phy/App/subghz_phy_app.o + .bss.RadioTxDone_flag + 0x2000059c 0x4 ./SubGHz_Phy/App/subghz_phy_app.o + .bss.RadioTxTimeout_flag + 0x200005a0 0x4 ./SubGHz_Phy/App/subghz_phy_app.o + .bss.RadioRxDone_flag + 0x200005a4 0x4 ./SubGHz_Phy/App/subghz_phy_app.o + .bss.RadioRxTimeout_flag + 0x200005a8 0x4 ./SubGHz_Phy/App/subghz_phy_app.o + .bss.RadioError_flag + 0x200005ac 0x4 ./SubGHz_Phy/App/subghz_phy_app.o + .bss.last_rx_rssi + 0x200005b0 0x2 ./SubGHz_Phy/App/subghz_phy_app.o + .bss.last_rx_cfo + 0x200005b2 0x1 ./SubGHz_Phy/App/subghz_phy_app.o + *fill* 0x200005b3 0x1 + .bss.data_buffer + 0x200005b4 0x3e8 ./SubGHz_Phy/App/subghz_phy_app.o + 0x200005b4 data_buffer + .bss.data_offset + 0x2000099c 0x2 ./SubGHz_Phy/App/subghz_phy_app.o + 0x2000099c data_offset + *fill* 0x2000099e 0x2 + .bss.packetCnt + 0x200009a0 0x4 ./SubGHz_Phy/App/subghz_phy_app.o + .bss.TxPayloadMode + 0x200009a4 0x1 ./SubGHz_Phy/App/subghz_phy_app.o + *fill* 0x200009a5 0x3 + .bss.StopModeDisable + 0x200009a8 0x4 ./Utilities/lpm/tiny_lpm/stm32_lpm.o + .bss.OffModeDisable + 0x200009ac 0x4 ./Utilities/lpm/tiny_lpm/stm32_lpm.o + .bss.TaskSet 0x200009b0 0x4 ./Utilities/sequencer/stm32_seq.o + .bss.EvtSet 0x200009b4 0x4 ./Utilities/sequencer/stm32_seq.o + .bss.EvtWaited + 0x200009b8 0x4 ./Utilities/sequencer/stm32_seq.o + .bss.CurrentTaskIdx + 0x200009bc 0x4 ./Utilities/sequencer/stm32_seq.o + .bss.TaskCb 0x200009c0 0x4 ./Utilities/sequencer/stm32_seq.o + .bss.TaskPrio 0x200009c4 0x8 ./Utilities/sequencer/stm32_seq.o + .bss.TimerListHead + 0x200009cc 0x4 ./Utilities/timer/stm32_timer.o + .bss.ADV_TRACE_Ctx + 0x200009d0 0x18 ./Utilities/trace/adv_trace/stm32_adv_trace.o + .bss.ADV_TRACE_Buffer + 0x200009e8 0x200 ./Utilities/trace/adv_trace/stm32_adv_trace.o + .bss.sztmp 0x20000be8 0x100 ./Utilities/trace/adv_trace/stm32_adv_trace.o + *(COMMON) + 0x20000ce8 . = ALIGN (0x4) + 0x20000ce8 _ebss = . + 0x20000ce8 __bss_end__ = _ebss + +._user_heap_stack + 0x20000ce8 0xa00 load address 0x0800db64 + 0x20000ce8 . = ALIGN (0x8) + [!provide] PROVIDE (end = .) + 0x20000ce8 PROVIDE (_end = .) + 0x20000ee8 . = (. + _Min_Heap_Size) + *fill* 0x20000ce8 0x200 + 0x200016e8 . = (. + _Min_Stack_Size) + *fill* 0x20000ee8 0x800 + 0x200016e8 . = ALIGN (0x8) + +/DISCARD/ + libc.a(*) + libm.a(*) + libgcc.a(*) + +.ARM.attributes + 0x00000000 0x2a + *(.ARM.attributes) + .ARM.attributes + 0x00000000 0x1e /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m/nofp/crti.o + .ARM.attributes + 0x0000001e 0x2e /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m/nofp/crtbegin.o + .ARM.attributes + 0x0000004c 0x2e ./Core/Src/dma.o + .ARM.attributes + 0x0000007a 0x2e ./Core/Src/gpio.o + .ARM.attributes + 0x000000a8 0x2e ./Core/Src/main.o + .ARM.attributes + 0x000000d6 0x2e ./Core/Src/rtc.o + .ARM.attributes + 0x00000104 0x2e ./Core/Src/stm32_lpm_if.o + .ARM.attributes + 0x00000132 0x2e ./Core/Src/stm32wlxx_hal_msp.o + .ARM.attributes + 0x00000160 0x2e ./Core/Src/stm32wlxx_it.o + .ARM.attributes + 0x0000018e 0x2e ./Core/Src/subghz.o + .ARM.attributes + 0x000001bc 0x2e ./Core/Src/sys_app.o + .ARM.attributes + 0x000001ea 0x2e ./Core/Src/sys_debug.o + .ARM.attributes + 0x00000218 0x2e ./Core/Src/system_stm32wlxx.o + .ARM.attributes + 0x00000246 0x2e ./Core/Src/timer_if.o + .ARM.attributes + 0x00000274 0x2e ./Core/Src/usart.o + .ARM.attributes + 0x000002a2 0x2e ./Core/Src/usart_if.o + .ARM.attributes + 0x000002d0 0x21 ./Core/Startup/startup_stm32wl55jcix.o + .ARM.attributes + 0x000002f1 0x2e ./Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo_radio.o + .ARM.attributes + 0x0000031f 0x2e ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.o + .ARM.attributes + 0x0000034d 0x2e ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.o + .ARM.attributes + 0x0000037b 0x2e ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.o + .ARM.attributes + 0x000003a9 0x2e ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_gpio.o + .ARM.attributes + 0x000003d7 0x2e ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.o + .ARM.attributes + 0x00000405 0x2e ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.o + .ARM.attributes + 0x00000433 0x2e ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.o + .ARM.attributes + 0x00000461 0x2e ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.o + .ARM.attributes + 0x0000048f 0x2e ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.o + .ARM.attributes + 0x000004bd 0x2e ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.o + .ARM.attributes + 0x000004eb 0x2e ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.o + .ARM.attributes + 0x00000519 0x2e ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.o + .ARM.attributes + 0x00000547 0x2e ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.o + .ARM.attributes + 0x00000575 0x2e ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + .ARM.attributes + 0x000005a3 0x2e ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + .ARM.attributes + 0x000005d1 0x2e ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.o + .ARM.attributes + 0x000005ff 0x2e ./SubGHz_Phy/App/app_subghz_phy.o + .ARM.attributes + 0x0000062d 0x2e ./SubGHz_Phy/App/subghz_phy_app.o + .ARM.attributes + 0x0000065b 0x2e ./SubGHz_Phy/Target/radio_board_if.o + .ARM.attributes + 0x00000689 0x2e ./Utilities/lpm/tiny_lpm/stm32_lpm.o + .ARM.attributes + 0x000006b7 0x2e ./Utilities/misc/stm32_mem.o + .ARM.attributes + 0x000006e5 0x2e ./Utilities/misc/stm32_systime.o + .ARM.attributes + 0x00000713 0x2e ./Utilities/misc/stm32_tiny_vsnprintf.o + .ARM.attributes + 0x00000741 0x2e ./Utilities/sequencer/stm32_seq.o + .ARM.attributes + 0x0000076f 0x2e ./Utilities/timer/stm32_timer.o + .ARM.attributes + 0x0000079d 0x2e ./Utilities/trace/adv_trace/stm32_adv_trace.o + .ARM.attributes + 0x000007cb 0x2e /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(libc_a-memset.o) + .ARM.attributes + 0x000007f9 0x2e /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(libc_a-init.o) + .ARM.attributes + 0x00000827 0x2e /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(libc_a-memcpy-stub.o) + .ARM.attributes + 0x00000855 0x17 /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(libc_a-strlen.o) + .ARM.attributes + 0x0000086c 0x1e /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m/nofp/libgcc.a(_aeabi_uldivmod.o) + .ARM.attributes + 0x0000088a 0x2e /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m/nofp/libgcc.a(_udivmoddi4.o) + .ARM.attributes + 0x000008b8 0x1e /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m/nofp/libgcc.a(_dvmd_tls.o) + .ARM.attributes + 0x000008d6 0x1e /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m/nofp/crtn.o +OUTPUT(SubGHz_Phy_Per.elf elf32-littlearm) +LOAD linker stubs +LOAD /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc.a +LOAD /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libm.a +LOAD /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m/nofp/libgcc.a + +.debug_info 0x00000000 0x233f6 + .debug_info 0x00000000 0x642 ./Core/Src/dma.o + .debug_info 0x00000642 0x7cf ./Core/Src/gpio.o + .debug_info 0x00000e11 0x8a2 ./Core/Src/main.o + .debug_info 0x000016b3 0xc77 ./Core/Src/rtc.o + .debug_info 0x0000232a 0x35c ./Core/Src/stm32_lpm_if.o + .debug_info 0x00002686 0xce ./Core/Src/stm32wlxx_hal_msp.o + .debug_info 0x00002754 0xd06 ./Core/Src/stm32wlxx_it.o + .debug_info 0x0000345a 0x7f8 ./Core/Src/subghz.o + .debug_info 0x00003c52 0x841 ./Core/Src/sys_app.o + .debug_info 0x00004493 0x794 ./Core/Src/sys_debug.o + .debug_info 0x00004c27 0x515 ./Core/Src/system_stm32wlxx.o + .debug_info 0x0000513c 0xbc3 ./Core/Src/timer_if.o + .debug_info 0x00005cff 0x1144 ./Core/Src/usart.o + .debug_info 0x00006e43 0x130f ./Core/Src/usart_if.o + .debug_info 0x00008152 0x30 ./Core/Startup/startup_stm32wl55jcix.o + .debug_info 0x00008182 0x70c ./Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo_radio.o + .debug_info 0x0000888e 0x116a ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.o + .debug_info 0x000099f8 0xd39 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.o + .debug_info 0x0000a731 0x91b ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.o + .debug_info 0x0000b04c 0x717 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_gpio.o + .debug_info 0x0000b763 0x8ed ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.o + .debug_info 0x0000c050 0xdec ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.o + .debug_info 0x0000ce3c 0x13f4 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.o + .debug_info 0x0000e230 0xf21 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.o + .debug_info 0x0000f151 0xefa ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.o + .debug_info 0x0001004b 0x14a6 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.o + .debug_info 0x000114f1 0x1397 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.o + .debug_info 0x00012888 0x4a46 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.o + .debug_info 0x000172ce 0x1003 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.o + .debug_info 0x000182d1 0x2e4f ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + .debug_info 0x0001b120 0x22ae ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + .debug_info 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0x00000028 0x28 ./Core/Src/gpio.o + .debug_aranges + 0x00000050 0x38 ./Core/Src/main.o + .debug_aranges + 0x00000088 0x50 ./Core/Src/rtc.o + .debug_aranges + 0x000000d8 0x50 ./Core/Src/stm32_lpm_if.o + .debug_aranges + 0x00000128 0x20 ./Core/Src/stm32wlxx_hal_msp.o + .debug_aranges + 0x00000148 0xa0 ./Core/Src/stm32wlxx_it.o + .debug_aranges + 0x000001e8 0x40 ./Core/Src/subghz.o + .debug_aranges + 0x00000228 0x68 ./Core/Src/sys_app.o + .debug_aranges + 0x00000290 0x30 ./Core/Src/sys_debug.o + .debug_aranges + 0x000002c0 0x28 ./Core/Src/system_stm32wlxx.o + .debug_aranges + 0x000002e8 0xc8 ./Core/Src/timer_if.o + .debug_aranges + 0x000003b0 0x48 ./Core/Src/usart.o + .debug_aranges + 0x000003f8 0x70 ./Core/Src/usart_if.o + .debug_aranges + 0x00000468 0x28 ./Core/Startup/startup_stm32wl55jcix.o + .debug_aranges + 0x00000490 0x58 ./Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo_radio.o + .debug_aranges + 0x000004e8 0x240 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.o + .debug_aranges + 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.debug_aranges + 0x00001688 0xa8 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.o + .debug_aranges + 0x00001730 0x178 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + .debug_aranges + 0x000018a8 0x240 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + .debug_aranges + 0x00001ae8 0x100 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.o + .debug_aranges + 0x00001be8 0x28 ./SubGHz_Phy/App/app_subghz_phy.o + .debug_aranges + 0x00001c10 0x60 ./SubGHz_Phy/App/subghz_phy_app.o + .debug_aranges + 0x00001c70 0x50 ./SubGHz_Phy/Target/radio_board_if.o + .debug_aranges + 0x00001cc0 0x48 ./Utilities/lpm/tiny_lpm/stm32_lpm.o + .debug_aranges + 0x00001d08 0x30 ./Utilities/misc/stm32_mem.o + .debug_aranges + 0x00001d38 0x80 ./Utilities/misc/stm32_systime.o + .debug_aranges + 0x00001db8 0x30 ./Utilities/misc/stm32_tiny_vsnprintf.o + .debug_aranges + 0x00001de8 0xa8 ./Utilities/sequencer/stm32_seq.o + .debug_aranges + 0x00001e90 0xb0 ./Utilities/timer/stm32_timer.o + .debug_aranges + 0x00001f40 0xe8 ./Utilities/trace/adv_trace/stm32_adv_trace.o + +.debug_rnglists + 0x00000000 0x182b + .debug_rnglists + 0x00000000 0x19 ./Core/Src/dma.o + .debug_rnglists + 0x00000019 0x1a ./Core/Src/gpio.o + .debug_rnglists + 0x00000033 0x26 ./Core/Src/main.o + .debug_rnglists + 0x00000059 0x38 ./Core/Src/rtc.o + .debug_rnglists + 0x00000091 0x37 ./Core/Src/stm32_lpm_if.o + .debug_rnglists + 0x000000c8 0x13 ./Core/Src/stm32wlxx_hal_msp.o + .debug_rnglists + 0x000000db 0x73 ./Core/Src/stm32wlxx_it.o + .debug_rnglists + 0x0000014e 0x2b ./Core/Src/subghz.o + .debug_rnglists + 0x00000179 0x49 ./Core/Src/sys_app.o + .debug_rnglists + 0x000001c2 0x20 ./Core/Src/sys_debug.o + .debug_rnglists + 0x000001e2 0x1a ./Core/Src/system_stm32wlxx.o + .debug_rnglists + 0x000001fc 0x93 ./Core/Src/timer_if.o + .debug_rnglists + 0x0000028f 0x33 ./Core/Src/usart.o + .debug_rnglists + 0x000002c2 0x4f ./Core/Src/usart_if.o + .debug_rnglists + 0x00000311 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0xe0 ./Core/Src/stm32_lpm_if.o + .debug_frame 0x0000032c 0x30 ./Core/Src/stm32wlxx_hal_msp.o + .debug_frame 0x0000035c 0x1e8 ./Core/Src/stm32wlxx_it.o + .debug_frame 0x00000544 0xc4 ./Core/Src/subghz.o + .debug_frame 0x00000608 0x170 ./Core/Src/sys_app.o + .debug_frame 0x00000778 0x84 ./Core/Src/sys_debug.o + .debug_frame 0x000007fc 0x58 ./Core/Src/system_stm32wlxx.o + .debug_frame 0x00000854 0x348 ./Core/Src/timer_if.o + .debug_frame 0x00000b9c 0xec ./Core/Src/usart.o + .debug_frame 0x00000c88 0x198 ./Core/Src/usart_if.o + .debug_frame 0x00000e20 0x124 ./Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo_radio.o + .debug_frame 0x00000f44 0x948 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.o + .debug_frame 0x0000188c 0x4e8 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.o + .debug_frame 0x00001d74 0x29c ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.o + .debug_frame 0x00002010 0x174 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_gpio.o + .debug_frame 0x00002184 0x31c ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.o + .debug_frame 0x000024a0 0x894 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.o + .debug_frame 0x00002d34 0x8fc ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.o + .debug_frame 0x00003630 0x7ec ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.o + .debug_frame 0x00003e1c 0x3f8 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.o + .debug_frame 0x00004214 0x7c4 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.o + .debug_frame 0x000049d8 0x624 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.o + .debug_frame 0x00004ffc 0xae4 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.o + .debug_frame 0x00005ae0 0x2c0 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.o + .debug_frame 0x00005da0 0x650 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + .debug_frame 0x000063f0 0x9b8 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + .debug_frame 0x00006da8 0x454 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.o + .debug_frame 0x000071fc 0x48 ./SubGHz_Phy/App/app_subghz_phy.o + .debug_frame 0x00007244 0x140 ./SubGHz_Phy/App/subghz_phy_app.o + .debug_frame 0x00007384 0xe4 ./SubGHz_Phy/Target/radio_board_if.o + .debug_frame 0x00007468 0xec ./Utilities/lpm/tiny_lpm/stm32_lpm.o + .debug_frame 0x00007554 0x88 ./Utilities/misc/stm32_mem.o + .debug_frame 0x000075dc 0x20c ./Utilities/misc/stm32_systime.o + .debug_frame 0x000077e8 0x88 ./Utilities/misc/stm32_tiny_vsnprintf.o + .debug_frame 0x00007870 0x2ac ./Utilities/sequencer/stm32_seq.o + .debug_frame 0x00007b1c 0x2c0 ./Utilities/timer/stm32_timer.o + .debug_frame 0x00007ddc 0x3c4 ./Utilities/trace/adv_trace/stm32_adv_trace.o + .debug_frame 0x000081a0 0x20 /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(libc_a-memset.o) + .debug_frame 0x000081c0 0x2c /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(libc_a-init.o) + .debug_frame 0x000081ec 0x28 /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(libc_a-memcpy-stub.o) + .debug_frame 0x00008214 0x2c /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m/nofp/libgcc.a(_aeabi_uldivmod.o) + .debug_frame 0x00008240 0x34 /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m/nofp/libgcc.a(_udivmoddi4.o) + +.debug_line_str + 0x00000000 0x5f + .debug_line_str + 0x00000000 0x5f ./Core/Startup/startup_stm32wl55jcix.o diff --git a/Debug/SubGHz_Phy_Per_My_Test.elf b/Debug/SubGHz_Phy_Per_My_Test.elf new file mode 100755 index 0000000..15dd558 Binary files /dev/null and b/Debug/SubGHz_Phy_Per_My_Test.elf differ diff --git a/Debug/SubGHz_Phy_Per_My_Test.list b/Debug/SubGHz_Phy_Per_My_Test.list new file mode 100644 index 0000000..17cfe92 --- /dev/null +++ b/Debug/SubGHz_Phy_Per_My_Test.list @@ -0,0 +1,40296 @@ + +SubGHz_Phy_Per_My_Test.elf: file format elf32-littlearm + +Sections: +Idx Name Size VMA LMA File off Algn + 0 .isr_vector 00000138 08000000 08000000 00001000 2**0 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 1 .text 0000ef80 08000140 08000140 00001140 2**4 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 2 .rodata 00000d40 0800f0c0 0800f0c0 000100c0 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 3 .ARM.extab 00000000 0800fe00 0800fe00 0001108c 2**0 + CONTENTS, READONLY + 4 .ARM 00000008 0800fe00 0800fe00 00010e00 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 5 .preinit_array 00000000 0800fe08 0800fe08 0001108c 2**0 + CONTENTS, ALLOC, LOAD, DATA + 6 .init_array 00000004 0800fe08 0800fe08 00010e08 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 7 .fini_array 00000004 0800fe0c 0800fe0c 00010e0c 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 8 .data 0000008c 20000000 0800fe10 00011000 2**2 + CONTENTS, ALLOC, LOAD, DATA + 9 .bss 00000fdc 2000008c 0800fe9c 0001108c 2**2 + ALLOC + 10 ._user_heap_stack 00000a00 20001068 0800fe9c 00012068 2**0 + ALLOC + 11 .ARM.attributes 0000002a 00000000 00000000 0001108c 2**0 + CONTENTS, READONLY + 12 .debug_info 00024226 00000000 00000000 000110b6 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 13 .debug_abbrev 00006081 00000000 00000000 000352dc 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 14 .debug_aranges 00002108 00000000 00000000 0003b360 2**3 + CONTENTS, READONLY, DEBUGGING, OCTETS + 15 .debug_rnglists 000018d7 00000000 00000000 0003d468 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 16 .debug_macro 00023a3b 00000000 00000000 0003ed3f 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 17 .debug_line 00022f57 00000000 00000000 0006277a 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 18 .debug_str 000c680e 00000000 00000000 000856d1 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 19 .comment 00000043 00000000 00000000 0014bedf 2**0 + CONTENTS, READONLY + 20 .debug_frame 00008bd0 00000000 00000000 0014bf24 2**2 + CONTENTS, READONLY, DEBUGGING, OCTETS + 21 .debug_line_str 0000005f 00000000 00000000 00154af4 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + +Disassembly of section .text: + +08000140 <__do_global_dtors_aux>: + 8000140: b510 push {r4, lr} + 8000142: 4c05 ldr r4, [pc, #20] @ (8000158 <__do_global_dtors_aux+0x18>) + 8000144: 7823 ldrb r3, [r4, #0] + 8000146: b933 cbnz r3, 8000156 <__do_global_dtors_aux+0x16> + 8000148: 4b04 ldr r3, [pc, #16] @ (800015c <__do_global_dtors_aux+0x1c>) + 800014a: b113 cbz r3, 8000152 <__do_global_dtors_aux+0x12> + 800014c: 4804 ldr r0, [pc, #16] @ (8000160 <__do_global_dtors_aux+0x20>) + 800014e: f3af 8000 nop.w + 8000152: 2301 movs r3, #1 + 8000154: 7023 strb r3, [r4, #0] + 8000156: bd10 pop {r4, pc} + 8000158: 2000008c .word 0x2000008c + 800015c: 00000000 .word 0x00000000 + 8000160: 0800f0a8 .word 0x0800f0a8 + +08000164 : + 8000164: b508 push {r3, lr} + 8000166: 4b03 ldr r3, [pc, #12] @ (8000174 ) + 8000168: b11b cbz r3, 8000172 + 800016a: 4903 ldr r1, [pc, #12] @ (8000178 ) + 800016c: 4803 ldr r0, [pc, #12] @ (800017c ) + 800016e: f3af 8000 nop.w + 8000172: bd08 pop {r3, pc} + 8000174: 00000000 .word 0x00000000 + 8000178: 20000090 .word 0x20000090 + 800017c: 0800f0a8 .word 0x0800f0a8 + +08000180 : + 8000180: f810 2b01 ldrb.w r2, [r0], #1 + 8000184: f811 3b01 ldrb.w r3, [r1], #1 + 8000188: 2a01 cmp r2, #1 + 800018a: bf28 it cs + 800018c: 429a cmpcs r2, r3 + 800018e: d0f7 beq.n 8000180 + 8000190: 1ad0 subs r0, r2, r3 + 8000192: 4770 bx lr + +08000194 : + 8000194: 4603 mov r3, r0 + 8000196: f813 2b01 ldrb.w r2, [r3], #1 + 800019a: 2a00 cmp r2, #0 + 800019c: d1fb bne.n 8000196 + 800019e: 1a18 subs r0, r3, r0 + 80001a0: 3801 subs r0, #1 + 80001a2: 4770 bx lr + ... + +080001b0 : + 80001b0: f001 01ff and.w r1, r1, #255 @ 0xff + 80001b4: 2a10 cmp r2, #16 + 80001b6: db2b blt.n 8000210 + 80001b8: f010 0f07 tst.w r0, #7 + 80001bc: d008 beq.n 80001d0 + 80001be: f810 3b01 ldrb.w r3, [r0], #1 + 80001c2: 3a01 subs r2, #1 + 80001c4: 428b cmp r3, r1 + 80001c6: d02d beq.n 8000224 + 80001c8: f010 0f07 tst.w r0, #7 + 80001cc: b342 cbz r2, 8000220 + 80001ce: d1f6 bne.n 80001be + 80001d0: b4f0 push {r4, r5, r6, r7} + 80001d2: ea41 2101 orr.w r1, r1, r1, lsl #8 + 80001d6: ea41 4101 orr.w r1, r1, r1, lsl #16 + 80001da: f022 0407 bic.w r4, r2, #7 + 80001de: f07f 0700 mvns.w r7, #0 + 80001e2: 2300 movs r3, #0 + 80001e4: e8f0 5602 ldrd r5, r6, [r0], #8 + 80001e8: 3c08 subs r4, #8 + 80001ea: ea85 0501 eor.w r5, r5, r1 + 80001ee: ea86 0601 eor.w r6, r6, r1 + 80001f2: fa85 f547 uadd8 r5, r5, r7 + 80001f6: faa3 f587 sel r5, r3, r7 + 80001fa: fa86 f647 uadd8 r6, r6, r7 + 80001fe: faa5 f687 sel r6, r5, r7 + 8000202: b98e cbnz r6, 8000228 + 8000204: d1ee bne.n 80001e4 + 8000206: bcf0 pop {r4, r5, r6, r7} + 8000208: f001 01ff and.w r1, r1, #255 @ 0xff + 800020c: f002 0207 and.w r2, r2, #7 + 8000210: b132 cbz r2, 8000220 + 8000212: f810 3b01 ldrb.w r3, [r0], #1 + 8000216: 3a01 subs r2, #1 + 8000218: ea83 0301 eor.w r3, r3, r1 + 800021c: b113 cbz r3, 8000224 + 800021e: d1f8 bne.n 8000212 + 8000220: 2000 movs r0, #0 + 8000222: 4770 bx lr + 8000224: 3801 subs r0, #1 + 8000226: 4770 bx lr + 8000228: 2d00 cmp r5, #0 + 800022a: bf06 itte eq + 800022c: 4635 moveq r5, r6 + 800022e: 3803 subeq r0, #3 + 8000230: 3807 subne r0, #7 + 8000232: f015 0f01 tst.w r5, #1 + 8000236: d107 bne.n 8000248 + 8000238: 3001 adds r0, #1 + 800023a: f415 7f80 tst.w r5, #256 @ 0x100 + 800023e: bf02 ittt eq + 8000240: 3001 addeq r0, #1 + 8000242: f415 3fc0 tsteq.w r5, #98304 @ 0x18000 + 8000246: 3001 addeq r0, #1 + 8000248: bcf0 pop {r4, r5, r6, r7} + 800024a: 3801 subs r0, #1 + 800024c: 4770 bx lr + 800024e: bf00 nop + +08000250 <__aeabi_uldivmod>: + 8000250: b953 cbnz r3, 8000268 <__aeabi_uldivmod+0x18> + 8000252: b94a cbnz r2, 8000268 <__aeabi_uldivmod+0x18> + 8000254: 2900 cmp r1, #0 + 8000256: bf08 it eq + 8000258: 2800 cmpeq r0, #0 + 800025a: bf1c itt ne + 800025c: f04f 31ff movne.w r1, #4294967295 @ 0xffffffff + 8000260: f04f 30ff movne.w r0, #4294967295 @ 0xffffffff + 8000264: f000 b988 b.w 8000578 <__aeabi_idiv0> + 8000268: f1ad 0c08 sub.w ip, sp, #8 + 800026c: e96d ce04 strd ip, lr, [sp, #-16]! + 8000270: f000 f806 bl 8000280 <__udivmoddi4> + 8000274: f8dd e004 ldr.w lr, [sp, #4] + 8000278: e9dd 2302 ldrd r2, r3, [sp, #8] + 800027c: b004 add sp, #16 + 800027e: 4770 bx lr + +08000280 <__udivmoddi4>: + 8000280: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} + 8000284: 9d08 ldr r5, [sp, #32] + 8000286: 468e mov lr, r1 + 8000288: 4604 mov r4, r0 + 800028a: 4688 mov r8, r1 + 800028c: 2b00 cmp r3, #0 + 800028e: d14a bne.n 8000326 <__udivmoddi4+0xa6> + 8000290: 428a cmp r2, r1 + 8000292: 4617 mov r7, r2 + 8000294: d962 bls.n 800035c <__udivmoddi4+0xdc> + 8000296: fab2 f682 clz r6, r2 + 800029a: b14e cbz r6, 80002b0 <__udivmoddi4+0x30> + 800029c: f1c6 0320 rsb r3, r6, #32 + 80002a0: fa01 f806 lsl.w r8, r1, r6 + 80002a4: fa20 f303 lsr.w r3, r0, r3 + 80002a8: 40b7 lsls r7, r6 + 80002aa: ea43 0808 orr.w r8, r3, r8 + 80002ae: 40b4 lsls r4, r6 + 80002b0: ea4f 4e17 mov.w lr, r7, lsr #16 + 80002b4: fa1f fc87 uxth.w ip, r7 + 80002b8: fbb8 f1fe udiv r1, r8, lr + 80002bc: 0c23 lsrs r3, r4, #16 + 80002be: fb0e 8811 mls r8, lr, r1, r8 + 80002c2: ea43 4308 orr.w r3, r3, r8, lsl #16 + 80002c6: fb01 f20c mul.w r2, r1, ip + 80002ca: 429a cmp r2, r3 + 80002cc: d909 bls.n 80002e2 <__udivmoddi4+0x62> + 80002ce: 18fb adds r3, r7, r3 + 80002d0: f101 30ff add.w r0, r1, #4294967295 @ 0xffffffff + 80002d4: f080 80ea bcs.w 80004ac <__udivmoddi4+0x22c> + 80002d8: 429a cmp r2, r3 + 80002da: f240 80e7 bls.w 80004ac <__udivmoddi4+0x22c> + 80002de: 3902 subs r1, #2 + 80002e0: 443b add r3, r7 + 80002e2: 1a9a subs r2, r3, r2 + 80002e4: b2a3 uxth r3, r4 + 80002e6: fbb2 f0fe udiv r0, r2, lr + 80002ea: fb0e 2210 mls r2, lr, r0, r2 + 80002ee: ea43 4302 orr.w r3, r3, r2, lsl #16 + 80002f2: fb00 fc0c mul.w ip, r0, ip + 80002f6: 459c cmp ip, r3 + 80002f8: d909 bls.n 800030e <__udivmoddi4+0x8e> + 80002fa: 18fb adds r3, r7, r3 + 80002fc: f100 32ff add.w r2, r0, #4294967295 @ 0xffffffff + 8000300: f080 80d6 bcs.w 80004b0 <__udivmoddi4+0x230> + 8000304: 459c cmp ip, r3 + 8000306: f240 80d3 bls.w 80004b0 <__udivmoddi4+0x230> + 800030a: 443b add r3, r7 + 800030c: 3802 subs r0, #2 + 800030e: ea40 4001 orr.w r0, r0, r1, lsl #16 + 8000312: eba3 030c sub.w r3, r3, ip + 8000316: 2100 movs r1, #0 + 8000318: b11d cbz r5, 8000322 <__udivmoddi4+0xa2> + 800031a: 40f3 lsrs r3, r6 + 800031c: 2200 movs r2, #0 + 800031e: e9c5 3200 strd r3, r2, [r5] + 8000322: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} + 8000326: 428b cmp r3, r1 + 8000328: d905 bls.n 8000336 <__udivmoddi4+0xb6> + 800032a: b10d cbz r5, 8000330 <__udivmoddi4+0xb0> + 800032c: e9c5 0100 strd r0, r1, [r5] + 8000330: 2100 movs r1, #0 + 8000332: 4608 mov r0, r1 + 8000334: e7f5 b.n 8000322 <__udivmoddi4+0xa2> + 8000336: fab3 f183 clz r1, r3 + 800033a: 2900 cmp r1, #0 + 800033c: d146 bne.n 80003cc <__udivmoddi4+0x14c> + 800033e: 4573 cmp r3, lr + 8000340: d302 bcc.n 8000348 <__udivmoddi4+0xc8> + 8000342: 4282 cmp r2, r0 + 8000344: f200 8105 bhi.w 8000552 <__udivmoddi4+0x2d2> + 8000348: 1a84 subs r4, r0, r2 + 800034a: eb6e 0203 sbc.w r2, lr, r3 + 800034e: 2001 movs r0, #1 + 8000350: 4690 mov r8, r2 + 8000352: 2d00 cmp r5, #0 + 8000354: d0e5 beq.n 8000322 <__udivmoddi4+0xa2> + 8000356: e9c5 4800 strd r4, r8, [r5] + 800035a: e7e2 b.n 8000322 <__udivmoddi4+0xa2> + 800035c: 2a00 cmp r2, #0 + 800035e: f000 8090 beq.w 8000482 <__udivmoddi4+0x202> + 8000362: fab2 f682 clz r6, r2 + 8000366: 2e00 cmp r6, #0 + 8000368: f040 80a4 bne.w 80004b4 <__udivmoddi4+0x234> + 800036c: 1a8a subs r2, r1, r2 + 800036e: 0c03 lsrs r3, r0, #16 + 8000370: ea4f 4e17 mov.w lr, r7, lsr #16 + 8000374: b280 uxth r0, r0 + 8000376: b2bc uxth r4, r7 + 8000378: 2101 movs r1, #1 + 800037a: fbb2 fcfe udiv ip, r2, lr + 800037e: fb0e 221c mls r2, lr, ip, r2 + 8000382: ea43 4302 orr.w r3, r3, r2, lsl #16 + 8000386: fb04 f20c mul.w r2, r4, ip + 800038a: 429a cmp r2, r3 + 800038c: d907 bls.n 800039e <__udivmoddi4+0x11e> + 800038e: 18fb adds r3, r7, r3 + 8000390: f10c 38ff add.w r8, ip, #4294967295 @ 0xffffffff + 8000394: d202 bcs.n 800039c <__udivmoddi4+0x11c> + 8000396: 429a cmp r2, r3 + 8000398: f200 80e0 bhi.w 800055c <__udivmoddi4+0x2dc> + 800039c: 46c4 mov ip, r8 + 800039e: 1a9b subs r3, r3, r2 + 80003a0: fbb3 f2fe udiv r2, r3, lr + 80003a4: fb0e 3312 mls r3, lr, r2, r3 + 80003a8: ea40 4303 orr.w r3, r0, r3, lsl #16 + 80003ac: fb02 f404 mul.w r4, r2, r4 + 80003b0: 429c cmp r4, r3 + 80003b2: d907 bls.n 80003c4 <__udivmoddi4+0x144> + 80003b4: 18fb adds r3, r7, r3 + 80003b6: f102 30ff add.w r0, r2, #4294967295 @ 0xffffffff + 80003ba: d202 bcs.n 80003c2 <__udivmoddi4+0x142> + 80003bc: 429c cmp r4, r3 + 80003be: f200 80ca bhi.w 8000556 <__udivmoddi4+0x2d6> + 80003c2: 4602 mov r2, r0 + 80003c4: 1b1b subs r3, r3, r4 + 80003c6: ea42 400c orr.w r0, r2, ip, lsl #16 + 80003ca: e7a5 b.n 8000318 <__udivmoddi4+0x98> + 80003cc: f1c1 0620 rsb r6, r1, #32 + 80003d0: 408b lsls r3, r1 + 80003d2: fa22 f706 lsr.w r7, r2, r6 + 80003d6: 431f orrs r7, r3 + 80003d8: fa0e f401 lsl.w r4, lr, r1 + 80003dc: fa20 f306 lsr.w r3, r0, r6 + 80003e0: fa2e fe06 lsr.w lr, lr, r6 + 80003e4: ea4f 4917 mov.w r9, r7, lsr #16 + 80003e8: 4323 orrs r3, r4 + 80003ea: fa00 f801 lsl.w r8, r0, r1 + 80003ee: fa1f fc87 uxth.w ip, r7 + 80003f2: fbbe f0f9 udiv r0, lr, r9 + 80003f6: 0c1c lsrs r4, r3, #16 + 80003f8: fb09 ee10 mls lr, r9, r0, lr + 80003fc: ea44 440e orr.w r4, r4, lr, lsl #16 + 8000400: fb00 fe0c mul.w lr, r0, ip + 8000404: 45a6 cmp lr, r4 + 8000406: fa02 f201 lsl.w r2, r2, r1 + 800040a: d909 bls.n 8000420 <__udivmoddi4+0x1a0> + 800040c: 193c adds r4, r7, r4 + 800040e: f100 3aff add.w sl, r0, #4294967295 @ 0xffffffff + 8000412: f080 809c bcs.w 800054e <__udivmoddi4+0x2ce> + 8000416: 45a6 cmp lr, r4 + 8000418: f240 8099 bls.w 800054e <__udivmoddi4+0x2ce> + 800041c: 3802 subs r0, #2 + 800041e: 443c add r4, r7 + 8000420: eba4 040e sub.w r4, r4, lr + 8000424: fa1f fe83 uxth.w lr, r3 + 8000428: fbb4 f3f9 udiv r3, r4, r9 + 800042c: fb09 4413 mls r4, r9, r3, r4 + 8000430: ea4e 4404 orr.w r4, lr, r4, lsl #16 + 8000434: fb03 fc0c mul.w ip, r3, ip + 8000438: 45a4 cmp ip, r4 + 800043a: d908 bls.n 800044e <__udivmoddi4+0x1ce> + 800043c: 193c adds r4, r7, r4 + 800043e: f103 3eff add.w lr, r3, #4294967295 @ 0xffffffff + 8000442: f080 8082 bcs.w 800054a <__udivmoddi4+0x2ca> + 8000446: 45a4 cmp ip, r4 + 8000448: d97f bls.n 800054a <__udivmoddi4+0x2ca> + 800044a: 3b02 subs r3, #2 + 800044c: 443c add r4, r7 + 800044e: ea43 4000 orr.w r0, r3, r0, lsl #16 + 8000452: eba4 040c sub.w r4, r4, ip + 8000456: fba0 ec02 umull lr, ip, r0, r2 + 800045a: 4564 cmp r4, ip + 800045c: 4673 mov r3, lr + 800045e: 46e1 mov r9, ip + 8000460: d362 bcc.n 8000528 <__udivmoddi4+0x2a8> + 8000462: d05f beq.n 8000524 <__udivmoddi4+0x2a4> + 8000464: b15d cbz r5, 800047e <__udivmoddi4+0x1fe> + 8000466: ebb8 0203 subs.w r2, r8, r3 + 800046a: eb64 0409 sbc.w r4, r4, r9 + 800046e: fa04 f606 lsl.w r6, r4, r6 + 8000472: fa22 f301 lsr.w r3, r2, r1 + 8000476: 431e orrs r6, r3 + 8000478: 40cc lsrs r4, r1 + 800047a: e9c5 6400 strd r6, r4, [r5] + 800047e: 2100 movs r1, #0 + 8000480: e74f b.n 8000322 <__udivmoddi4+0xa2> + 8000482: fbb1 fcf2 udiv ip, r1, r2 + 8000486: 0c01 lsrs r1, r0, #16 + 8000488: ea41 410e orr.w r1, r1, lr, lsl #16 + 800048c: b280 uxth r0, r0 + 800048e: ea40 4201 orr.w r2, r0, r1, lsl #16 + 8000492: 463b mov r3, r7 + 8000494: 4638 mov r0, r7 + 8000496: 463c mov r4, r7 + 8000498: 46b8 mov r8, r7 + 800049a: 46be mov lr, r7 + 800049c: 2620 movs r6, #32 + 800049e: fbb1 f1f7 udiv r1, r1, r7 + 80004a2: eba2 0208 sub.w r2, r2, r8 + 80004a6: ea41 410c orr.w r1, r1, ip, lsl #16 + 80004aa: e766 b.n 800037a <__udivmoddi4+0xfa> + 80004ac: 4601 mov r1, r0 + 80004ae: e718 b.n 80002e2 <__udivmoddi4+0x62> + 80004b0: 4610 mov r0, r2 + 80004b2: e72c b.n 800030e <__udivmoddi4+0x8e> + 80004b4: f1c6 0220 rsb r2, r6, #32 + 80004b8: fa2e f302 lsr.w r3, lr, r2 + 80004bc: 40b7 lsls r7, r6 + 80004be: 40b1 lsls r1, r6 + 80004c0: fa20 f202 lsr.w r2, r0, r2 + 80004c4: ea4f 4e17 mov.w lr, r7, lsr #16 + 80004c8: 430a orrs r2, r1 + 80004ca: fbb3 f8fe udiv r8, r3, lr + 80004ce: b2bc uxth r4, r7 + 80004d0: fb0e 3318 mls r3, lr, r8, r3 + 80004d4: 0c11 lsrs r1, r2, #16 + 80004d6: ea41 4103 orr.w r1, r1, r3, lsl #16 + 80004da: fb08 f904 mul.w r9, r8, r4 + 80004de: 40b0 lsls r0, r6 + 80004e0: 4589 cmp r9, r1 + 80004e2: ea4f 4310 mov.w r3, r0, lsr #16 + 80004e6: b280 uxth r0, r0 + 80004e8: d93e bls.n 8000568 <__udivmoddi4+0x2e8> + 80004ea: 1879 adds r1, r7, r1 + 80004ec: f108 3cff add.w ip, r8, #4294967295 @ 0xffffffff + 80004f0: d201 bcs.n 80004f6 <__udivmoddi4+0x276> + 80004f2: 4589 cmp r9, r1 + 80004f4: d81f bhi.n 8000536 <__udivmoddi4+0x2b6> + 80004f6: eba1 0109 sub.w r1, r1, r9 + 80004fa: fbb1 f9fe udiv r9, r1, lr + 80004fe: fb09 f804 mul.w r8, r9, r4 + 8000502: fb0e 1119 mls r1, lr, r9, r1 + 8000506: b292 uxth r2, r2 + 8000508: ea42 4201 orr.w r2, r2, r1, lsl #16 + 800050c: 4542 cmp r2, r8 + 800050e: d229 bcs.n 8000564 <__udivmoddi4+0x2e4> + 8000510: 18ba adds r2, r7, r2 + 8000512: f109 31ff add.w r1, r9, #4294967295 @ 0xffffffff + 8000516: d2c4 bcs.n 80004a2 <__udivmoddi4+0x222> + 8000518: 4542 cmp r2, r8 + 800051a: d2c2 bcs.n 80004a2 <__udivmoddi4+0x222> + 800051c: f1a9 0102 sub.w r1, r9, #2 + 8000520: 443a add r2, r7 + 8000522: e7be b.n 80004a2 <__udivmoddi4+0x222> + 8000524: 45f0 cmp r8, lr + 8000526: d29d bcs.n 8000464 <__udivmoddi4+0x1e4> + 8000528: ebbe 0302 subs.w r3, lr, r2 + 800052c: eb6c 0c07 sbc.w ip, ip, r7 + 8000530: 3801 subs r0, #1 + 8000532: 46e1 mov r9, ip + 8000534: e796 b.n 8000464 <__udivmoddi4+0x1e4> + 8000536: eba7 0909 sub.w r9, r7, r9 + 800053a: 4449 add r1, r9 + 800053c: f1a8 0c02 sub.w ip, r8, #2 + 8000540: fbb1 f9fe udiv r9, r1, lr + 8000544: fb09 f804 mul.w r8, r9, r4 + 8000548: e7db b.n 8000502 <__udivmoddi4+0x282> + 800054a: 4673 mov r3, lr + 800054c: e77f b.n 800044e <__udivmoddi4+0x1ce> + 800054e: 4650 mov r0, sl + 8000550: e766 b.n 8000420 <__udivmoddi4+0x1a0> + 8000552: 4608 mov r0, r1 + 8000554: e6fd b.n 8000352 <__udivmoddi4+0xd2> + 8000556: 443b add r3, r7 + 8000558: 3a02 subs r2, #2 + 800055a: e733 b.n 80003c4 <__udivmoddi4+0x144> + 800055c: f1ac 0c02 sub.w ip, ip, #2 + 8000560: 443b add r3, r7 + 8000562: e71c b.n 800039e <__udivmoddi4+0x11e> + 8000564: 4649 mov r1, r9 + 8000566: e79c b.n 80004a2 <__udivmoddi4+0x222> + 8000568: eba1 0109 sub.w r1, r1, r9 + 800056c: 46c4 mov ip, r8 + 800056e: fbb1 f9fe udiv r9, r1, lr + 8000572: fb09 f804 mul.w r8, r9, r4 + 8000576: e7c4 b.n 8000502 <__udivmoddi4+0x282> + +08000578 <__aeabi_idiv0>: + 8000578: 4770 bx lr + 800057a: bf00 nop + +0800057c : + * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1 + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @retval None + */ +__STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) +{ + 800057c: b480 push {r7} + 800057e: b085 sub sp, #20 + 8000580: af00 add r7, sp, #0 + 8000582: 6078 str r0, [r7, #4] + __IO uint32_t tmpreg; + SET_BIT(RCC->AHB1ENR, Periphs); + 8000584: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8000588: 6c9a ldr r2, [r3, #72] @ 0x48 + 800058a: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 800058e: 687b ldr r3, [r7, #4] + 8000590: 4313 orrs r3, r2 + 8000592: 648b str r3, [r1, #72] @ 0x48 + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHB1ENR, Periphs); + 8000594: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8000598: 6c9a ldr r2, [r3, #72] @ 0x48 + 800059a: 687b ldr r3, [r7, #4] + 800059c: 4013 ands r3, r2 + 800059e: 60fb str r3, [r7, #12] + (void)tmpreg; + 80005a0: 68fb ldr r3, [r7, #12] +} + 80005a2: bf00 nop + 80005a4: 3714 adds r7, #20 + 80005a6: 46bd mov sp, r7 + 80005a8: bc80 pop {r7} + 80005aa: 4770 bx lr + +080005ac : + +/** + * Enable DMA controller clock + */ +void MX_DMA_Init(void) +{ + 80005ac: b580 push {r7, lr} + 80005ae: af00 add r7, sp, #0 + + /* DMA controller clock enable */ + __HAL_RCC_DMAMUX1_CLK_ENABLE(); + 80005b0: 2004 movs r0, #4 + 80005b2: f7ff ffe3 bl 800057c + __HAL_RCC_DMA1_CLK_ENABLE(); + 80005b6: 2001 movs r0, #1 + 80005b8: f7ff ffe0 bl 800057c + + /* DMA interrupt init */ + /* DMA1_Channel5_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(DMA1_Channel5_IRQn, 2, 0); + 80005bc: 2200 movs r2, #0 + 80005be: 2102 movs r1, #2 + 80005c0: 200f movs r0, #15 + 80005c2: f001 fadc bl 8001b7e + HAL_NVIC_EnableIRQ(DMA1_Channel5_IRQn); + 80005c6: 200f movs r0, #15 + 80005c8: f001 faf3 bl 8001bb2 + +} + 80005cc: bf00 nop + 80005ce: bd80 pop {r7, pc} + +080005d0 : + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH + * @retval None + */ +__STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs) +{ + 80005d0: b480 push {r7} + 80005d2: b085 sub sp, #20 + 80005d4: af00 add r7, sp, #0 + 80005d6: 6078 str r0, [r7, #4] + __IO uint32_t tmpreg; + SET_BIT(RCC->AHB2ENR, Periphs); + 80005d8: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 80005dc: 6cda ldr r2, [r3, #76] @ 0x4c + 80005de: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 80005e2: 687b ldr r3, [r7, #4] + 80005e4: 4313 orrs r3, r2 + 80005e6: 64cb str r3, [r1, #76] @ 0x4c + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHB2ENR, Periphs); + 80005e8: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 80005ec: 6cda ldr r2, [r3, #76] @ 0x4c + 80005ee: 687b ldr r3, [r7, #4] + 80005f0: 4013 ands r3, r2 + 80005f2: 60fb str r3, [r7, #12] + (void)tmpreg; + 80005f4: 68fb ldr r3, [r7, #12] +} + 80005f6: bf00 nop + 80005f8: 3714 adds r7, #20 + 80005fa: 46bd mov sp, r7 + 80005fc: bc80 pop {r7} + 80005fe: 4770 bx lr + +08000600 : + * Output + * EVENT_OUT + * EXTI +*/ +void MX_GPIO_Init(void) +{ + 8000600: b580 push {r7, lr} + 8000602: b086 sub sp, #24 + 8000604: af00 add r7, sp, #0 + + GPIO_InitTypeDef GPIO_InitStruct = {0}; + 8000606: 1d3b adds r3, r7, #4 + 8000608: 2200 movs r2, #0 + 800060a: 601a str r2, [r3, #0] + 800060c: 605a str r2, [r3, #4] + 800060e: 609a str r2, [r3, #8] + 8000610: 60da str r2, [r3, #12] + 8000612: 611a str r2, [r3, #16] + + /* GPIO Ports Clock Enable */ + __HAL_RCC_GPIOB_CLK_ENABLE(); + 8000614: 2002 movs r0, #2 + 8000616: f7ff ffdb bl 80005d0 + __HAL_RCC_GPIOC_CLK_ENABLE(); + 800061a: 2004 movs r0, #4 + 800061c: f7ff ffd8 bl 80005d0 + __HAL_RCC_GPIOA_CLK_ENABLE(); + 8000620: 2001 movs r0, #1 + 8000622: f7ff ffd5 bl 80005d0 + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(GPIOB, LED1_Pin|LED2_Pin|PROB2_Pin|PROB1_Pin + 8000626: 2200 movs r2, #0 + 8000628: f44f 413a mov.w r1, #47616 @ 0xba00 + 800062c: 4829 ldr r0, [pc, #164] @ (80006d4 ) + 800062e: f002 f92f bl 8002890 + |LED3_Pin, GPIO_PIN_RESET); + + /*Configure GPIO pins : LED1_Pin LED2_Pin LED3_Pin */ + GPIO_InitStruct.Pin = LED1_Pin|LED2_Pin|LED3_Pin; + 8000632: f44f 430a mov.w r3, #35328 @ 0x8a00 + 8000636: 607b str r3, [r7, #4] + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + 8000638: 2301 movs r3, #1 + 800063a: 60bb str r3, [r7, #8] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 800063c: 2300 movs r3, #0 + 800063e: 60fb str r3, [r7, #12] + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; + 8000640: 2302 movs r3, #2 + 8000642: 613b str r3, [r7, #16] + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + 8000644: 1d3b adds r3, r7, #4 + 8000646: 4619 mov r1, r3 + 8000648: 4822 ldr r0, [pc, #136] @ (80006d4 ) + 800064a: f001 fef3 bl 8002434 + + /*Configure GPIO pins : BUT1_Pin BUT2_Pin */ + GPIO_InitStruct.Pin = BUT1_Pin|BUT2_Pin; + 800064e: 2303 movs r3, #3 + 8000650: 607b str r3, [r7, #4] + GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING; + 8000652: f44f 1304 mov.w r3, #2162688 @ 0x210000 + 8000656: 60bb str r3, [r7, #8] + GPIO_InitStruct.Pull = GPIO_PULLUP; + 8000658: 2301 movs r3, #1 + 800065a: 60fb str r3, [r7, #12] + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 800065c: 1d3b adds r3, r7, #4 + 800065e: 4619 mov r1, r3 + 8000660: f04f 4090 mov.w r0, #1207959552 @ 0x48000000 + 8000664: f001 fee6 bl 8002434 + + /*Configure GPIO pins : PROB2_Pin PROB1_Pin */ + GPIO_InitStruct.Pin = PROB2_Pin|PROB1_Pin; + 8000668: f44f 5340 mov.w r3, #12288 @ 0x3000 + 800066c: 607b str r3, [r7, #4] + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + 800066e: 2301 movs r3, #1 + 8000670: 60bb str r3, [r7, #8] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8000672: 2300 movs r3, #0 + 8000674: 60fb str r3, [r7, #12] + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + 8000676: 2303 movs r3, #3 + 8000678: 613b str r3, [r7, #16] + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + 800067a: 1d3b adds r3, r7, #4 + 800067c: 4619 mov r1, r3 + 800067e: 4815 ldr r0, [pc, #84] @ (80006d4 ) + 8000680: f001 fed8 bl 8002434 + + /*Configure GPIO pin : BUT3_Pin */ + GPIO_InitStruct.Pin = BUT3_Pin; + 8000684: 2340 movs r3, #64 @ 0x40 + 8000686: 607b str r3, [r7, #4] + GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING; + 8000688: f44f 1304 mov.w r3, #2162688 @ 0x210000 + 800068c: 60bb str r3, [r7, #8] + GPIO_InitStruct.Pull = GPIO_PULLUP; + 800068e: 2301 movs r3, #1 + 8000690: 60fb str r3, [r7, #12] + HAL_GPIO_Init(BUT3_GPIO_Port, &GPIO_InitStruct); + 8000692: 1d3b adds r3, r7, #4 + 8000694: 4619 mov r1, r3 + 8000696: 4810 ldr r0, [pc, #64] @ (80006d8 ) + 8000698: f001 fecc bl 8002434 + + /* EXTI interrupt init*/ + HAL_NVIC_SetPriority(EXTI0_IRQn, 0, 0); + 800069c: 2200 movs r2, #0 + 800069e: 2100 movs r1, #0 + 80006a0: 2006 movs r0, #6 + 80006a2: f001 fa6c bl 8001b7e + HAL_NVIC_EnableIRQ(EXTI0_IRQn); + 80006a6: 2006 movs r0, #6 + 80006a8: f001 fa83 bl 8001bb2 + + HAL_NVIC_SetPriority(EXTI1_IRQn, 0, 0); + 80006ac: 2200 movs r2, #0 + 80006ae: 2100 movs r1, #0 + 80006b0: 2007 movs r0, #7 + 80006b2: f001 fa64 bl 8001b7e + HAL_NVIC_EnableIRQ(EXTI1_IRQn); + 80006b6: 2007 movs r0, #7 + 80006b8: f001 fa7b bl 8001bb2 + + HAL_NVIC_SetPriority(EXTI9_5_IRQn, 0, 0); + 80006bc: 2200 movs r2, #0 + 80006be: 2100 movs r1, #0 + 80006c0: 2016 movs r0, #22 + 80006c2: f001 fa5c bl 8001b7e + HAL_NVIC_EnableIRQ(EXTI9_5_IRQn); + 80006c6: 2016 movs r0, #22 + 80006c8: f001 fa73 bl 8001bb2 + +} + 80006cc: bf00 nop + 80006ce: 3718 adds r7, #24 + 80006d0: 46bd mov sp, r7 + 80006d2: bd80 pop {r7, pc} + 80006d4: 48000400 .word 0x48000400 + 80006d8: 48000800 .word 0x48000800 + +080006dc : + * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH + * @arg @ref LL_RCC_LSEDRIVE_HIGH + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive) +{ + 80006dc: b480 push {r7} + 80006de: b083 sub sp, #12 + 80006e0: af00 add r7, sp, #0 + 80006e2: 6078 str r0, [r7, #4] + MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, LSEDrive); + 80006e4: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 80006e8: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 80006ec: f023 0218 bic.w r2, r3, #24 + 80006f0: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 80006f4: 687b ldr r3, [r7, #4] + 80006f6: 4313 orrs r3, r2 + 80006f8: f8c1 3090 str.w r3, [r1, #144] @ 0x90 +} + 80006fc: bf00 nop + 80006fe: 370c adds r7, #12 + 8000700: 46bd mov sp, r7 + 8000702: bc80 pop {r7} + 8000704: 4770 bx lr + +08000706
: +/** + * @brief The application entry point. + * @retval int + */ +int main(void) +{ + 8000706: b580 push {r7, lr} + 8000708: af00 add r7, sp, #0 + /* USER CODE END 1 */ + + /* MCU Configuration--------------------------------------------------------*/ + + /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ + HAL_Init(); + 800070a: f001 f911 bl 8001930 + /* USER CODE BEGIN Init */ + + /* USER CODE END Init */ + + /* Configure the system clock */ + SystemClock_Config(); + 800070e: f000 f807 bl 8000720 + /* USER CODE BEGIN SysInit */ + + /* USER CODE END SysInit */ + + /* Initialize all configured peripherals */ + MX_GPIO_Init(); + 8000712: f7ff ff75 bl 8000600 + MX_SubGHz_Phy_Init(); + 8000716: f00b fb65 bl 800bde4 + /* Infinite loop */ + /* USER CODE BEGIN WHILE */ + while (1) + { + /* USER CODE END WHILE */ + MX_SubGHz_Phy_Process(); + 800071a: f00b fb6b bl 800bdf4 + 800071e: e7fc b.n 800071a + +08000720 : +/** + * @brief System Clock Configuration + * @retval None + */ +void SystemClock_Config(void) +{ + 8000720: b580 push {r7, lr} + 8000722: b09a sub sp, #104 @ 0x68 + 8000724: af00 add r7, sp, #0 + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + 8000726: f107 0320 add.w r3, r7, #32 + 800072a: 2248 movs r2, #72 @ 0x48 + 800072c: 2100 movs r1, #0 + 800072e: 4618 mov r0, r3 + 8000730: f00e f82a bl 800e788 + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + 8000734: 1d3b adds r3, r7, #4 + 8000736: 2200 movs r2, #0 + 8000738: 601a str r2, [r3, #0] + 800073a: 605a str r2, [r3, #4] + 800073c: 609a str r2, [r3, #8] + 800073e: 60da str r2, [r3, #12] + 8000740: 611a str r2, [r3, #16] + 8000742: 615a str r2, [r3, #20] + 8000744: 619a str r2, [r3, #24] + + /** Configure LSE Drive Capability + */ + HAL_PWR_EnableBkUpAccess(); + 8000746: f002 f8dd bl 8002904 + __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW); + 800074a: 2000 movs r0, #0 + 800074c: f7ff ffc6 bl 80006dc + + /** Configure the main internal regulator output voltage + */ + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + 8000750: 4b1e ldr r3, [pc, #120] @ (80007cc ) + 8000752: 681b ldr r3, [r3, #0] + 8000754: f423 63c0 bic.w r3, r3, #1536 @ 0x600 + 8000758: 4a1c ldr r2, [pc, #112] @ (80007cc ) + 800075a: f443 7300 orr.w r3, r3, #512 @ 0x200 + 800075e: 6013 str r3, [r2, #0] + 8000760: 4b1a ldr r3, [pc, #104] @ (80007cc ) + 8000762: 681b ldr r3, [r3, #0] + 8000764: f403 63c0 and.w r3, r3, #1536 @ 0x600 + 8000768: 603b str r3, [r7, #0] + 800076a: 683b ldr r3, [r7, #0] + + /** Initializes the CPU, AHB and APB buses clocks + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE|RCC_OSCILLATORTYPE_MSI; + 800076c: 2324 movs r3, #36 @ 0x24 + 800076e: 623b str r3, [r7, #32] + RCC_OscInitStruct.LSEState = RCC_LSE_ON; + 8000770: 2381 movs r3, #129 @ 0x81 + 8000772: 62fb str r3, [r7, #44] @ 0x2c + RCC_OscInitStruct.MSIState = RCC_MSI_ON; + 8000774: 2301 movs r3, #1 + 8000776: 643b str r3, [r7, #64] @ 0x40 + RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT; + 8000778: 2300 movs r3, #0 + 800077a: 647b str r3, [r7, #68] @ 0x44 + RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_11; + 800077c: 23b0 movs r3, #176 @ 0xb0 + 800077e: 64bb str r3, [r7, #72] @ 0x48 + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; + 8000780: 2300 movs r3, #0 + 8000782: 64fb str r3, [r7, #76] @ 0x4c + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + 8000784: f107 0320 add.w r3, r7, #32 + 8000788: 4618 mov r0, r3 + 800078a: f002 fc2f bl 8002fec + 800078e: 4603 mov r3, r0 + 8000790: 2b00 cmp r3, #0 + 8000792: d001 beq.n 8000798 + { + Error_Handler(); + 8000794: f000 f81c bl 80007d0 + } + + /** Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK3|RCC_CLOCKTYPE_HCLK + 8000798: 234f movs r3, #79 @ 0x4f + 800079a: 607b str r3, [r7, #4] + |RCC_CLOCKTYPE_SYSCLK|RCC_CLOCKTYPE_PCLK1 + |RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI; + 800079c: 2300 movs r3, #0 + 800079e: 60bb str r3, [r7, #8] + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + 80007a0: 2300 movs r3, #0 + 80007a2: 60fb str r3, [r7, #12] + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; + 80007a4: 2300 movs r3, #0 + 80007a6: 613b str r3, [r7, #16] + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + 80007a8: 2300 movs r3, #0 + 80007aa: 617b str r3, [r7, #20] + RCC_ClkInitStruct.AHBCLK3Divider = RCC_SYSCLK_DIV1; + 80007ac: 2300 movs r3, #0 + 80007ae: 61fb str r3, [r7, #28] + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) + 80007b0: 1d3b adds r3, r7, #4 + 80007b2: 2102 movs r1, #2 + 80007b4: 4618 mov r0, r3 + 80007b6: f002 ff9b bl 80036f0 + 80007ba: 4603 mov r3, r0 + 80007bc: 2b00 cmp r3, #0 + 80007be: d001 beq.n 80007c4 + { + Error_Handler(); + 80007c0: f000 f806 bl 80007d0 + } +} + 80007c4: bf00 nop + 80007c6: 3768 adds r7, #104 @ 0x68 + 80007c8: 46bd mov sp, r7 + 80007ca: bd80 pop {r7, pc} + 80007cc: 58000400 .word 0x58000400 + +080007d0 : +/** + * @brief This function is executed in case of error occurrence. + * @retval None + */ +void Error_Handler(void) +{ + 80007d0: b480 push {r7} + 80007d2: af00 add r7, sp, #0 + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); + 80007d4: b672 cpsid i +} + 80007d6: bf00 nop + /* USER CODE BEGIN Error_Handler_Debug */ + /* User can add his own implementation to report the HAL error return state */ + __disable_irq(); + while (1) + 80007d8: bf00 nop + 80007da: e7fd b.n 80007d8 + +080007dc : + * @brief Enable RTC + * @rmtoll BDCR RTCEN LL_RCC_EnableRTC + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableRTC(void) +{ + 80007dc: b480 push {r7} + 80007de: af00 add r7, sp, #0 + SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN); + 80007e0: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 80007e4: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 80007e8: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 80007ec: f443 4300 orr.w r3, r3, #32768 @ 0x8000 + 80007f0: f8c2 3090 str.w r3, [r2, #144] @ 0x90 +} + 80007f4: bf00 nop + 80007f6: 46bd mov sp, r7 + 80007f8: bc80 pop {r7} + 80007fa: 4770 bx lr + +080007fc : + * @arg @ref LL_APB1_GRP1_PERIPH_DAC + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + * @retval None + */ +__STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs) +{ + 80007fc: b480 push {r7} + 80007fe: b085 sub sp, #20 + 8000800: af00 add r7, sp, #0 + 8000802: 6078 str r0, [r7, #4] + __IO uint32_t tmpreg; + SET_BIT(RCC->APB1ENR1, Periphs); + 8000804: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8000808: 6d9a ldr r2, [r3, #88] @ 0x58 + 800080a: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 800080e: 687b ldr r3, [r7, #4] + 8000810: 4313 orrs r3, r2 + 8000812: 658b str r3, [r1, #88] @ 0x58 + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB1ENR1, Periphs); + 8000814: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8000818: 6d9a ldr r2, [r3, #88] @ 0x58 + 800081a: 687b ldr r3, [r7, #4] + 800081c: 4013 ands r3, r2 + 800081e: 60fb str r3, [r7, #12] + (void)tmpreg; + 8000820: 68fb ldr r3, [r7, #12] +} + 8000822: bf00 nop + 8000824: 3714 adds r7, #20 + 8000826: 46bd mov sp, r7 + 8000828: bc80 pop {r7} + 800082a: 4770 bx lr + +0800082c : + +RTC_HandleTypeDef hrtc; + +/* RTC init function */ +void MX_RTC_Init(void) +{ + 800082c: b580 push {r7, lr} + 800082e: b08c sub sp, #48 @ 0x30 + 8000830: af00 add r7, sp, #0 + + /* USER CODE BEGIN RTC_Init 0 */ + + /* USER CODE END RTC_Init 0 */ + + RTC_AlarmTypeDef sAlarm = {0}; + 8000832: 1d3b adds r3, r7, #4 + 8000834: 222c movs r2, #44 @ 0x2c + 8000836: 2100 movs r1, #0 + 8000838: 4618 mov r0, r3 + 800083a: f00d ffa5 bl 800e788 + + /* USER CODE END RTC_Init 1 */ + + /** Initialize RTC Only + */ + hrtc.Instance = RTC; + 800083e: 4b22 ldr r3, [pc, #136] @ (80008c8 ) + 8000840: 4a22 ldr r2, [pc, #136] @ (80008cc ) + 8000842: 601a str r2, [r3, #0] + hrtc.Init.AsynchPrediv = RTC_PREDIV_A; + 8000844: 4b20 ldr r3, [pc, #128] @ (80008c8 ) + 8000846: 221f movs r2, #31 + 8000848: 609a str r2, [r3, #8] + hrtc.Init.OutPut = RTC_OUTPUT_DISABLE; + 800084a: 4b1f ldr r3, [pc, #124] @ (80008c8 ) + 800084c: 2200 movs r2, #0 + 800084e: 611a str r2, [r3, #16] + hrtc.Init.OutPutRemap = RTC_OUTPUT_REMAP_NONE; + 8000850: 4b1d ldr r3, [pc, #116] @ (80008c8 ) + 8000852: 2200 movs r2, #0 + 8000854: 615a str r2, [r3, #20] + hrtc.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH; + 8000856: 4b1c ldr r3, [pc, #112] @ (80008c8 ) + 8000858: 2200 movs r2, #0 + 800085a: 619a str r2, [r3, #24] + hrtc.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN; + 800085c: 4b1a ldr r3, [pc, #104] @ (80008c8 ) + 800085e: f04f 4280 mov.w r2, #1073741824 @ 0x40000000 + 8000862: 61da str r2, [r3, #28] + hrtc.Init.OutPutPullUp = RTC_OUTPUT_PULLUP_NONE; + 8000864: 4b18 ldr r3, [pc, #96] @ (80008c8 ) + 8000866: 2200 movs r2, #0 + 8000868: 621a str r2, [r3, #32] + hrtc.Init.BinMode = RTC_BINARY_ONLY; + 800086a: 4b17 ldr r3, [pc, #92] @ (80008c8 ) + 800086c: f44f 7280 mov.w r2, #256 @ 0x100 + 8000870: 625a str r2, [r3, #36] @ 0x24 + if (HAL_RTC_Init(&hrtc) != HAL_OK) + 8000872: 4815 ldr r0, [pc, #84] @ (80008c8 ) + 8000874: f003 fc16 bl 80040a4 + 8000878: 4603 mov r3, r0 + 800087a: 2b00 cmp r3, #0 + 800087c: d001 beq.n 8000882 + { + Error_Handler(); + 800087e: f7ff ffa7 bl 80007d0 + + /* USER CODE END Check_RTC_BKUP */ + + /** Initialize RTC and set the Time and Date + */ + if (HAL_RTCEx_SetSSRU_IT(&hrtc) != HAL_OK) + 8000882: 4811 ldr r0, [pc, #68] @ (80008c8 ) + 8000884: f003 ff16 bl 80046b4 + 8000888: 4603 mov r3, r0 + 800088a: 2b00 cmp r3, #0 + 800088c: d001 beq.n 8000892 + { + Error_Handler(); + 800088e: f7ff ff9f bl 80007d0 + } + + /** Enable the Alarm A + */ + sAlarm.BinaryAutoClr = RTC_ALARMSUBSECONDBIN_AUTOCLR_NO; + 8000892: 2300 movs r3, #0 + 8000894: 623b str r3, [r7, #32] + sAlarm.AlarmTime.SubSeconds = 0x0; + 8000896: 2300 movs r3, #0 + 8000898: 60bb str r3, [r7, #8] + sAlarm.AlarmMask = RTC_ALARMMASK_NONE; + 800089a: 2300 movs r3, #0 + 800089c: 61bb str r3, [r7, #24] + sAlarm.AlarmSubSecondMask = RTC_ALARMSUBSECONDBINMASK_NONE; + 800089e: f04f 5300 mov.w r3, #536870912 @ 0x20000000 + 80008a2: 61fb str r3, [r7, #28] + sAlarm.Alarm = RTC_ALARM_A; + 80008a4: f44f 7380 mov.w r3, #256 @ 0x100 + 80008a8: 62fb str r3, [r7, #44] @ 0x2c + if (HAL_RTC_SetAlarm_IT(&hrtc, &sAlarm, 0) != HAL_OK) + 80008aa: 1d3b adds r3, r7, #4 + 80008ac: 2200 movs r2, #0 + 80008ae: 4619 mov r1, r3 + 80008b0: 4805 ldr r0, [pc, #20] @ (80008c8 ) + 80008b2: f003 fc83 bl 80041bc + 80008b6: 4603 mov r3, r0 + 80008b8: 2b00 cmp r3, #0 + 80008ba: d001 beq.n 80008c0 + { + Error_Handler(); + 80008bc: f7ff ff88 bl 80007d0 + } + /* USER CODE BEGIN RTC_Init 2 */ + + /* USER CODE END RTC_Init 2 */ + +} + 80008c0: bf00 nop + 80008c2: 3730 adds r7, #48 @ 0x30 + 80008c4: 46bd mov sp, r7 + 80008c6: bd80 pop {r7, pc} + 80008c8: 200000a8 .word 0x200000a8 + 80008cc: 40002800 .word 0x40002800 + +080008d0 : + +void HAL_RTC_MspInit(RTC_HandleTypeDef* rtcHandle) +{ + 80008d0: b580 push {r7, lr} + 80008d2: b090 sub sp, #64 @ 0x40 + 80008d4: af00 add r7, sp, #0 + 80008d6: 6078 str r0, [r7, #4] + + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; + 80008d8: f107 0308 add.w r3, r7, #8 + 80008dc: 2238 movs r2, #56 @ 0x38 + 80008de: 2100 movs r1, #0 + 80008e0: 4618 mov r0, r3 + 80008e2: f00d ff51 bl 800e788 + if(rtcHandle->Instance==RTC) + 80008e6: 687b ldr r3, [r7, #4] + 80008e8: 681b ldr r3, [r3, #0] + 80008ea: 4a16 ldr r2, [pc, #88] @ (8000944 ) + 80008ec: 4293 cmp r3, r2 + 80008ee: d125 bne.n 800093c + + /* USER CODE END RTC_MspInit 0 */ + + /** Initializes the peripherals clocks + */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC; + 80008f0: f44f 3380 mov.w r3, #65536 @ 0x10000 + 80008f4: 60bb str r3, [r7, #8] + PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE; + 80008f6: f44f 7380 mov.w r3, #256 @ 0x100 + 80008fa: 63fb str r3, [r7, #60] @ 0x3c + + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) + 80008fc: f107 0308 add.w r3, r7, #8 + 8000900: 4618 mov r0, r3 + 8000902: f003 fab5 bl 8003e70 + 8000906: 4603 mov r3, r0 + 8000908: 2b00 cmp r3, #0 + 800090a: d001 beq.n 8000910 + { + Error_Handler(); + 800090c: f7ff ff60 bl 80007d0 + } + + /* RTC clock enable */ + __HAL_RCC_RTC_ENABLE(); + 8000910: f7ff ff64 bl 80007dc + __HAL_RCC_RTCAPB_CLK_ENABLE(); + 8000914: f44f 6080 mov.w r0, #1024 @ 0x400 + 8000918: f7ff ff70 bl 80007fc + + /* RTC interrupt Init */ + HAL_NVIC_SetPriority(TAMP_STAMP_LSECSS_SSRU_IRQn, 0, 0); + 800091c: 2200 movs r2, #0 + 800091e: 2100 movs r1, #0 + 8000920: 2002 movs r0, #2 + 8000922: f001 f92c bl 8001b7e + HAL_NVIC_EnableIRQ(TAMP_STAMP_LSECSS_SSRU_IRQn); + 8000926: 2002 movs r0, #2 + 8000928: f001 f943 bl 8001bb2 + HAL_NVIC_SetPriority(RTC_Alarm_IRQn, 0, 0); + 800092c: 2200 movs r2, #0 + 800092e: 2100 movs r1, #0 + 8000930: 202a movs r0, #42 @ 0x2a + 8000932: f001 f924 bl 8001b7e + HAL_NVIC_EnableIRQ(RTC_Alarm_IRQn); + 8000936: 202a movs r0, #42 @ 0x2a + 8000938: f001 f93b bl 8001bb2 + /* USER CODE BEGIN RTC_MspInit 1 */ + + /* USER CODE END RTC_MspInit 1 */ + } +} + 800093c: bf00 nop + 800093e: 3740 adds r7, #64 @ 0x40 + 8000940: 46bd mov sp, r7 + 8000942: bd80 pop {r7, pc} + 8000944: 40002800 .word 0x40002800 + +08000948 : + * @brief Clear standby and stop flags for CPU1 + * @rmtoll EXTSCR C1CSSF LL_PWR_ClearFlag_C1STOP_C1STB + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_C1STOP_C1STB(void) +{ + 8000948: b480 push {r7} + 800094a: af00 add r7, sp, #0 + WRITE_REG(PWR->EXTSCR, PWR_EXTSCR_C1CSSF); + 800094c: 4b03 ldr r3, [pc, #12] @ (800095c ) + 800094e: 2201 movs r2, #1 + 8000950: f8c3 2088 str.w r2, [r3, #136] @ 0x88 +} + 8000954: bf00 nop + 8000956: 46bd mov sp, r7 + 8000958: bc80 pop {r7} + 800095a: 4770 bx lr + 800095c: 58000400 .word 0x58000400 + +08000960 : +/* USER CODE END PFP */ + +/* Exported functions --------------------------------------------------------*/ + +void PWR_EnterOffMode(void) +{ + 8000960: b480 push {r7} + 8000962: af00 add r7, sp, #0 + /* USER CODE BEGIN EnterOffMode_1 */ + + /* USER CODE END EnterOffMode_1 */ +} + 8000964: bf00 nop + 8000966: 46bd mov sp, r7 + 8000968: bc80 pop {r7} + 800096a: 4770 bx lr + +0800096c : + +void PWR_ExitOffMode(void) +{ + 800096c: b480 push {r7} + 800096e: af00 add r7, sp, #0 + /* USER CODE BEGIN ExitOffMode_1 */ + + /* USER CODE END ExitOffMode_1 */ +} + 8000970: bf00 nop + 8000972: 46bd mov sp, r7 + 8000974: bc80 pop {r7} + 8000976: 4770 bx lr + +08000978 : + +void PWR_EnterStopMode(void) +{ + 8000978: b580 push {r7, lr} + 800097a: af00 add r7, sp, #0 + /* USER CODE BEGIN EnterStopMode_1 */ + + /* USER CODE END EnterStopMode_1 */ + HAL_SuspendTick(); + 800097c: f000 fff8 bl 8001970 + /* Clear Status Flag before entering STOP/STANDBY Mode */ + LL_PWR_ClearFlag_C1STOP_C1STB(); + 8000980: f7ff ffe2 bl 8000948 + + /* USER CODE BEGIN EnterStopMode_2 */ + + /* USER CODE END EnterStopMode_2 */ + HAL_PWREx_EnterSTOP2Mode(PWR_STOPENTRY_WFI); + 8000984: 2001 movs r0, #1 + 8000986: f002 f84f bl 8002a28 + /* USER CODE BEGIN EnterStopMode_3 */ + + /* USER CODE END EnterStopMode_3 */ +} + 800098a: bf00 nop + 800098c: bd80 pop {r7, pc} + +0800098e : + +void PWR_ExitStopMode(void) +{ + 800098e: b580 push {r7, lr} + 8000990: af00 add r7, sp, #0 + /* USER CODE BEGIN ExitStopMode_1 */ + + /* USER CODE END ExitStopMode_1 */ + /* Resume sysTick : work around for debugger problem in dual core */ + HAL_ResumeTick(); + 8000992: f000 fffb bl 800198c + ADC interface + DAC interface USARTx, TIMx, i2Cx, SPIx + SRAM ctrls, DMAx, DMAMux, AES, RNG, HSEM */ + + /* Resume not retained USARTx and DMA */ + vcom_Resume(); + 8000996: f000 fe47 bl 8001628 + /* USER CODE BEGIN ExitStopMode_2 */ + + /* USER CODE END ExitStopMode_2 */ +} + 800099a: bf00 nop + 800099c: bd80 pop {r7, pc} + +0800099e : + +void PWR_EnterSleepMode(void) +{ + 800099e: b580 push {r7, lr} + 80009a0: af00 add r7, sp, #0 + /* USER CODE BEGIN EnterSleepMode_1 */ + + /* USER CODE END EnterSleepMode_1 */ + /* Suspend sysTick */ + HAL_SuspendTick(); + 80009a2: f000 ffe5 bl 8001970 + /* USER CODE BEGIN EnterSleepMode_2 */ + + /* USER CODE END EnterSleepMode_2 */ + HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI); + 80009a6: 2101 movs r1, #1 + 80009a8: 2000 movs r0, #0 + 80009aa: f001 ffb9 bl 8002920 + /* USER CODE BEGIN EnterSleepMode_3 */ + + /* USER CODE END EnterSleepMode_3 */ +} + 80009ae: bf00 nop + 80009b0: bd80 pop {r7, pc} + +080009b2 : + +void PWR_ExitSleepMode(void) +{ + 80009b2: b580 push {r7, lr} + 80009b4: af00 add r7, sp, #0 + /* USER CODE BEGIN ExitSleepMode_1 */ + + /* USER CODE END ExitSleepMode_1 */ + /* Resume sysTick */ + HAL_ResumeTick(); + 80009b6: f000 ffe9 bl 800198c + + /* USER CODE BEGIN ExitSleepMode_2 */ + + /* USER CODE END ExitSleepMode_2 */ +} + 80009ba: bf00 nop + 80009bc: bd80 pop {r7, pc} + +080009be : +/* USER CODE END 0 */ +/** + * Initializes the Global MSP. + */ +void HAL_MspInit(void) +{ + 80009be: b480 push {r7} + 80009c0: af00 add r7, sp, #0 + /* System interrupt init*/ + + /* USER CODE BEGIN MspInit 1 */ + + /* USER CODE END MspInit 1 */ +} + 80009c2: bf00 nop + 80009c4: 46bd mov sp, r7 + 80009c6: bc80 pop {r7} + 80009c8: 4770 bx lr + +080009ca : +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + 80009ca: b480 push {r7} + 80009cc: af00 add r7, sp, #0 + /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ + + /* USER CODE END NonMaskableInt_IRQn 0 */ + /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ + while (1) + 80009ce: bf00 nop + 80009d0: e7fd b.n 80009ce + +080009d2 : + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + 80009d2: b480 push {r7} + 80009d4: af00 add r7, sp, #0 + /* USER CODE BEGIN HardFault_IRQn 0 */ + + /* USER CODE END HardFault_IRQn 0 */ + while (1) + 80009d6: bf00 nop + 80009d8: e7fd b.n 80009d6 + +080009da : + +/** + * @brief This function handles Memory management fault. + */ +void MemManage_Handler(void) +{ + 80009da: b480 push {r7} + 80009dc: af00 add r7, sp, #0 + /* USER CODE BEGIN MemoryManagement_IRQn 0 */ + + /* USER CODE END MemoryManagement_IRQn 0 */ + while (1) + 80009de: bf00 nop + 80009e0: e7fd b.n 80009de + +080009e2 : + +/** + * @brief This function handles Prefetch fault, memory access fault. + */ +void BusFault_Handler(void) +{ + 80009e2: b480 push {r7} + 80009e4: af00 add r7, sp, #0 + /* USER CODE BEGIN BusFault_IRQn 0 */ + + /* USER CODE END BusFault_IRQn 0 */ + while (1) + 80009e6: bf00 nop + 80009e8: e7fd b.n 80009e6 + +080009ea : + +/** + * @brief This function handles Undefined instruction or illegal state. + */ +void UsageFault_Handler(void) +{ + 80009ea: b480 push {r7} + 80009ec: af00 add r7, sp, #0 + /* USER CODE BEGIN UsageFault_IRQn 0 */ + + /* USER CODE END UsageFault_IRQn 0 */ + while (1) + 80009ee: bf00 nop + 80009f0: e7fd b.n 80009ee + +080009f2 : + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + 80009f2: b480 push {r7} + 80009f4: af00 add r7, sp, #0 + + /* USER CODE END SVCall_IRQn 0 */ + /* USER CODE BEGIN SVCall_IRQn 1 */ + + /* USER CODE END SVCall_IRQn 1 */ +} + 80009f6: bf00 nop + 80009f8: 46bd mov sp, r7 + 80009fa: bc80 pop {r7} + 80009fc: 4770 bx lr + +080009fe : + +/** + * @brief This function handles Debug monitor. + */ +void DebugMon_Handler(void) +{ + 80009fe: b480 push {r7} + 8000a00: af00 add r7, sp, #0 + + /* USER CODE END DebugMonitor_IRQn 0 */ + /* USER CODE BEGIN DebugMonitor_IRQn 1 */ + + /* USER CODE END DebugMonitor_IRQn 1 */ +} + 8000a02: bf00 nop + 8000a04: 46bd mov sp, r7 + 8000a06: bc80 pop {r7} + 8000a08: 4770 bx lr + +08000a0a : + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + 8000a0a: b480 push {r7} + 8000a0c: af00 add r7, sp, #0 + + /* USER CODE END PendSV_IRQn 0 */ + /* USER CODE BEGIN PendSV_IRQn 1 */ + + /* USER CODE END PendSV_IRQn 1 */ +} + 8000a0e: bf00 nop + 8000a10: 46bd mov sp, r7 + 8000a12: bc80 pop {r7} + 8000a14: 4770 bx lr + +08000a16 : + +/** + * @brief This function handles System tick timer. + */ +void SysTick_Handler(void) +{ + 8000a16: b480 push {r7} + 8000a18: af00 add r7, sp, #0 + + /* USER CODE END SysTick_IRQn 0 */ + /* USER CODE BEGIN SysTick_IRQn 1 */ + + /* USER CODE END SysTick_IRQn 1 */ +} + 8000a1a: bf00 nop + 8000a1c: 46bd mov sp, r7 + 8000a1e: bc80 pop {r7} + 8000a20: 4770 bx lr + ... + +08000a24 : + +/** + * @brief This function handles RTC Tamper, RTC TimeStamp, LSECSS and RTC SSRU Interrupts. + */ +void TAMP_STAMP_LSECSS_SSRU_IRQHandler(void) +{ + 8000a24: b580 push {r7, lr} + 8000a26: af00 add r7, sp, #0 + /* USER CODE BEGIN TAMP_STAMP_LSECSS_SSRU_IRQn 0 */ + + /* USER CODE END TAMP_STAMP_LSECSS_SSRU_IRQn 0 */ + HAL_RTCEx_SSRUIRQHandler(&hrtc); + 8000a28: 4802 ldr r0, [pc, #8] @ (8000a34 ) + 8000a2a: f003 fe7f bl 800472c + /* USER CODE BEGIN TAMP_STAMP_LSECSS_SSRU_IRQn 1 */ + + /* USER CODE END TAMP_STAMP_LSECSS_SSRU_IRQn 1 */ +} + 8000a2e: bf00 nop + 8000a30: bd80 pop {r7, pc} + 8000a32: bf00 nop + 8000a34: 200000a8 .word 0x200000a8 + +08000a38 : + +/** + * @brief This function handles EXTI Line 0 Interrupt. + */ +void EXTI0_IRQHandler(void) +{ + 8000a38: b580 push {r7, lr} + 8000a3a: af00 add r7, sp, #0 + /* USER CODE BEGIN EXTI0_IRQn 0 */ + + /* USER CODE END EXTI0_IRQn 0 */ + HAL_GPIO_EXTI_IRQHandler(BUT1_Pin); + 8000a3c: 2001 movs r0, #1 + 8000a3e: f001 ff3f bl 80028c0 + /* USER CODE BEGIN EXTI0_IRQn 1 */ + + /* USER CODE END EXTI0_IRQn 1 */ +} + 8000a42: bf00 nop + 8000a44: bd80 pop {r7, pc} + +08000a46 : + +/** + * @brief This function handles EXTI Line 1 Interrupt. + */ +void EXTI1_IRQHandler(void) +{ + 8000a46: b580 push {r7, lr} + 8000a48: af00 add r7, sp, #0 + /* USER CODE BEGIN EXTI1_IRQn 0 */ + + /* USER CODE END EXTI1_IRQn 0 */ + HAL_GPIO_EXTI_IRQHandler(BUT2_Pin); + 8000a4a: 2002 movs r0, #2 + 8000a4c: f001 ff38 bl 80028c0 + /* USER CODE BEGIN EXTI1_IRQn 1 */ + + /* USER CODE END EXTI1_IRQn 1 */ +} + 8000a50: bf00 nop + 8000a52: bd80 pop {r7, pc} + +08000a54 : + +/** + * @brief This function handles DMA1 Channel 5 Interrupt. + */ +void DMA1_Channel5_IRQHandler(void) +{ + 8000a54: b580 push {r7, lr} + 8000a56: af00 add r7, sp, #0 + /* USER CODE BEGIN DMA1_Channel5_IRQn 0 */ + + /* USER CODE END DMA1_Channel5_IRQn 0 */ + HAL_DMA_IRQHandler(&hdma_usart2_tx); + 8000a58: 4802 ldr r0, [pc, #8] @ (8000a64 ) + 8000a5a: f001 fb41 bl 80020e0 + /* USER CODE BEGIN DMA1_Channel5_IRQn 1 */ + + /* USER CODE END DMA1_Channel5_IRQn 1 */ +} + 8000a5e: bf00 nop + 8000a60: bd80 pop {r7, pc} + 8000a62: bf00 nop + 8000a64: 20000190 .word 0x20000190 + +08000a68 : + +/** + * @brief This function handles EXTI Lines [9:5] Interrupt. + */ +void EXTI9_5_IRQHandler(void) +{ + 8000a68: b580 push {r7, lr} + 8000a6a: af00 add r7, sp, #0 + /* USER CODE BEGIN EXTI9_5_IRQn 0 */ + + /* USER CODE END EXTI9_5_IRQn 0 */ + HAL_GPIO_EXTI_IRQHandler(BUT3_Pin); + 8000a6c: 2040 movs r0, #64 @ 0x40 + 8000a6e: f001 ff27 bl 80028c0 + /* USER CODE BEGIN EXTI9_5_IRQn 1 */ + + /* USER CODE END EXTI9_5_IRQn 1 */ +} + 8000a72: bf00 nop + 8000a74: bd80 pop {r7, pc} + ... + +08000a78 : + +/** + * @brief This function handles USART2 Interrupt. + */ +void USART2_IRQHandler(void) +{ + 8000a78: b580 push {r7, lr} + 8000a7a: af00 add r7, sp, #0 + /* USER CODE BEGIN USART2_IRQn 0 */ + + /* USER CODE END USART2_IRQn 0 */ + HAL_UART_IRQHandler(&huart2); + 8000a7c: 4802 ldr r0, [pc, #8] @ (8000a88 ) + 8000a7e: f004 fdfb bl 8005678 + /* USER CODE BEGIN USART2_IRQn 1 */ + + /* USER CODE END USART2_IRQn 1 */ +} + 8000a82: bf00 nop + 8000a84: bd80 pop {r7, pc} + 8000a86: bf00 nop + 8000a88: 200000fc .word 0x200000fc + +08000a8c : + +/** + * @brief This function handles RTC Alarms (A and B) Interrupt. + */ +void RTC_Alarm_IRQHandler(void) +{ + 8000a8c: b580 push {r7, lr} + 8000a8e: af00 add r7, sp, #0 + /* USER CODE BEGIN RTC_Alarm_IRQn 0 */ + + /* USER CODE END RTC_Alarm_IRQn 0 */ + HAL_RTC_AlarmIRQHandler(&hrtc); + 8000a90: 4802 ldr r0, [pc, #8] @ (8000a9c ) + 8000a92: f003 fcfb bl 800448c + /* USER CODE BEGIN RTC_Alarm_IRQn 1 */ + + /* USER CODE END RTC_Alarm_IRQn 1 */ +} + 8000a96: bf00 nop + 8000a98: bd80 pop {r7, pc} + 8000a9a: bf00 nop + 8000a9c: 200000a8 .word 0x200000a8 + +08000aa0 : + +/** + * @brief This function handles SUBGHZ Radio Interrupt. + */ +void SUBGHZ_Radio_IRQHandler(void) +{ + 8000aa0: b580 push {r7, lr} + 8000aa2: af00 add r7, sp, #0 + /* USER CODE BEGIN SUBGHZ_Radio_IRQn 0 */ + + /* USER CODE END SUBGHZ_Radio_IRQn 0 */ + HAL_SUBGHZ_IRQHandler(&hsubghz); + 8000aa4: 4802 ldr r0, [pc, #8] @ (8000ab0 ) + 8000aa6: f004 f9af bl 8004e08 + /* USER CODE BEGIN SUBGHZ_Radio_IRQn 1 */ + + /* USER CODE END SUBGHZ_Radio_IRQn 1 */ +} + 8000aaa: bf00 nop + 8000aac: bd80 pop {r7, pc} + 8000aae: bf00 nop + 8000ab0: 200000e0 .word 0x200000e0 + +08000ab4 : + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB3_GRP1_PERIPH_SUBGHZSPI + * @retval None + */ +__STATIC_INLINE void LL_APB3_GRP1_EnableClock(uint32_t Periphs) +{ + 8000ab4: b480 push {r7} + 8000ab6: b085 sub sp, #20 + 8000ab8: af00 add r7, sp, #0 + 8000aba: 6078 str r0, [r7, #4] + __IO uint32_t tmpreg; + SET_BIT(RCC->APB3ENR, Periphs); + 8000abc: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8000ac0: 6e5a ldr r2, [r3, #100] @ 0x64 + 8000ac2: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 8000ac6: 687b ldr r3, [r7, #4] + 8000ac8: 4313 orrs r3, r2 + 8000aca: 664b str r3, [r1, #100] @ 0x64 + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB3ENR, Periphs); + 8000acc: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8000ad0: 6e5a ldr r2, [r3, #100] @ 0x64 + 8000ad2: 687b ldr r3, [r7, #4] + 8000ad4: 4013 ands r3, r2 + 8000ad6: 60fb str r3, [r7, #12] + (void)tmpreg; + 8000ad8: 68fb ldr r3, [r7, #12] +} + 8000ada: bf00 nop + 8000adc: 3714 adds r7, #20 + 8000ade: 46bd mov sp, r7 + 8000ae0: bc80 pop {r7} + 8000ae2: 4770 bx lr + +08000ae4 : + +SUBGHZ_HandleTypeDef hsubghz; + +/* SUBGHZ init function */ +void MX_SUBGHZ_Init(void) +{ + 8000ae4: b580 push {r7, lr} + 8000ae6: af00 add r7, sp, #0 + /* USER CODE END SUBGHZ_Init 0 */ + + /* USER CODE BEGIN SUBGHZ_Init 1 */ + + /* USER CODE END SUBGHZ_Init 1 */ + hsubghz.Init.BaudratePrescaler = SUBGHZSPI_BAUDRATEPRESCALER_4; + 8000ae8: 4b06 ldr r3, [pc, #24] @ (8000b04 ) + 8000aea: 2208 movs r2, #8 + 8000aec: 601a str r2, [r3, #0] + if (HAL_SUBGHZ_Init(&hsubghz) != HAL_OK) + 8000aee: 4805 ldr r0, [pc, #20] @ (8000b04 ) + 8000af0: f003 ff08 bl 8004904 + 8000af4: 4603 mov r3, r0 + 8000af6: 2b00 cmp r3, #0 + 8000af8: d001 beq.n 8000afe + { + Error_Handler(); + 8000afa: f7ff fe69 bl 80007d0 + } + /* USER CODE BEGIN SUBGHZ_Init 2 */ + + /* USER CODE END SUBGHZ_Init 2 */ + +} + 8000afe: bf00 nop + 8000b00: bd80 pop {r7, pc} + 8000b02: bf00 nop + 8000b04: 200000e0 .word 0x200000e0 + +08000b08 : + +void HAL_SUBGHZ_MspInit(SUBGHZ_HandleTypeDef* subghzHandle) +{ + 8000b08: b580 push {r7, lr} + 8000b0a: b082 sub sp, #8 + 8000b0c: af00 add r7, sp, #0 + 8000b0e: 6078 str r0, [r7, #4] + + /* USER CODE BEGIN SUBGHZ_MspInit 0 */ + + /* USER CODE END SUBGHZ_MspInit 0 */ + /* SUBGHZ clock enable */ + __HAL_RCC_SUBGHZSPI_CLK_ENABLE(); + 8000b10: 2001 movs r0, #1 + 8000b12: f7ff ffcf bl 8000ab4 + + /* SUBGHZ interrupt Init */ + HAL_NVIC_SetPriority(SUBGHZ_Radio_IRQn, 0, 0); + 8000b16: 2200 movs r2, #0 + 8000b18: 2100 movs r1, #0 + 8000b1a: 2032 movs r0, #50 @ 0x32 + 8000b1c: f001 f82f bl 8001b7e + HAL_NVIC_EnableIRQ(SUBGHZ_Radio_IRQn); + 8000b20: 2032 movs r0, #50 @ 0x32 + 8000b22: f001 f846 bl 8001bb2 + /* USER CODE BEGIN SUBGHZ_MspInit 1 */ + + /* USER CODE END SUBGHZ_MspInit 1 */ +} + 8000b26: bf00 nop + 8000b28: 3708 adds r7, #8 + 8000b2a: 46bd mov sp, r7 + 8000b2c: bd80 pop {r7, pc} + +08000b2e : +{ + 8000b2e: b480 push {r7} + 8000b30: b083 sub sp, #12 + 8000b32: af00 add r7, sp, #0 + 8000b34: 6078 str r0, [r7, #4] + MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, Clock); + 8000b36: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8000b3a: 689b ldr r3, [r3, #8] + 8000b3c: f423 4200 bic.w r2, r3, #32768 @ 0x8000 + 8000b40: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 8000b44: 687b ldr r3, [r7, #4] + 8000b46: 4313 orrs r3, r2 + 8000b48: 608b str r3, [r1, #8] +} + 8000b4a: bf00 nop + 8000b4c: 370c adds r7, #12 + 8000b4e: 46bd mov sp, r7 + 8000b50: bc80 pop {r7} + 8000b52: 4770 bx lr + +08000b54 : + +/* USER CODE END PFP */ + +/* Exported functions ---------------------------------------------------------*/ +void SystemApp_Init(void) +{ + 8000b54: b580 push {r7, lr} + 8000b56: af00 add r7, sp, #0 + /* USER CODE BEGIN SystemApp_Init_1 */ + + /* USER CODE END SystemApp_Init_1 */ + + /* Ensure that MSI is wake-up system clock */ + __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(RCC_STOP_WAKEUPCLOCK_MSI); + 8000b58: 2000 movs r0, #0 + 8000b5a: f7ff ffe8 bl 8000b2e + + /*Initialize timer and RTC*/ + UTIL_TIMER_Init(); + 8000b5e: f00c ffb7 bl 800dad0 + SYS_TimerInitialisedFlag = 1; + 8000b62: 4b0c ldr r3, [pc, #48] @ (8000b94 ) + 8000b64: 2201 movs r2, #1 + 8000b66: 701a strb r2, [r3, #0] + /* Initializes the SW probes pins and the monitor RF pins via Alternate Function */ + DBG_Init(); + 8000b68: f000 f8ba bl 8000ce0 + + /*Initialize the terminal */ + UTIL_ADV_TRACE_Init(); + 8000b6c: f00d fa40 bl 800dff0 + UTIL_ADV_TRACE_RegisterTimeStampFunction(TimestampNow); + 8000b70: 4809 ldr r0, [pc, #36] @ (8000b98 ) + 8000b72: f00d fad9 bl 800e128 + + /*Set verbose LEVEL*/ + UTIL_ADV_TRACE_SetVerboseLevel(VERBOSE_LEVEL); + 8000b76: 2002 movs r0, #2 + 8000b78: f00d fae4 bl 800e144 + + /*Init low power manager*/ + UTIL_LPM_Init(); + 8000b7c: f00c fab0 bl 800d0e0 + /* Disable Stand-by mode */ + UTIL_LPM_SetOffMode((1 << CFG_LPM_APPLI_Id), UTIL_LPM_DISABLE); + 8000b80: 2101 movs r1, #1 + 8000b82: 2001 movs r0, #1 + 8000b84: f00c faec bl 800d160 + +#if defined (LOW_POWER_DISABLE) && (LOW_POWER_DISABLE == 1) + /* Disable Stop Mode */ + UTIL_LPM_SetStopMode((1 << CFG_LPM_APPLI_Id), UTIL_LPM_DISABLE); + 8000b88: 2101 movs r1, #1 + 8000b8a: 2001 movs r0, #1 + 8000b8c: f00c fab8 bl 800d100 +#endif /* LOW_POWER_DISABLE */ + + /* USER CODE BEGIN SystemApp_Init_2 */ + + /* USER CODE END SystemApp_Init_2 */ +} + 8000b90: bf00 nop + 8000b92: bd80 pop {r7, pc} + 8000b94: 200000ec .word 0x200000ec + 8000b98: 08000ba9 .word 0x08000ba9 + +08000b9c : + +/** + * @brief redefines __weak function in stm32_seq.c such to enter low power + */ +void UTIL_SEQ_Idle(void) +{ + 8000b9c: b580 push {r7, lr} + 8000b9e: af00 add r7, sp, #0 + /* USER CODE BEGIN UTIL_SEQ_Idle_1 */ + + /* USER CODE END UTIL_SEQ_Idle_1 */ + UTIL_LPM_EnterLowPower(); + 8000ba0: f00c fb0e bl 800d1c0 + /* USER CODE BEGIN UTIL_SEQ_Idle_2 */ + + /* USER CODE END UTIL_SEQ_Idle_2 */ +} + 8000ba4: bf00 nop + 8000ba6: bd80 pop {r7, pc} + +08000ba8 : +/* USER CODE END EF */ + +/* Private functions ---------------------------------------------------------*/ + +static void TimestampNow(uint8_t *buff, uint16_t *size) +{ + 8000ba8: b580 push {r7, lr} + 8000baa: b086 sub sp, #24 + 8000bac: af02 add r7, sp, #8 + 8000bae: 6078 str r0, [r7, #4] + 8000bb0: 6039 str r1, [r7, #0] + /* USER CODE BEGIN TimestampNow_1 */ + + /* USER CODE END TimestampNow_1 */ + SysTime_t curtime = SysTimeGet(); + 8000bb2: f107 0308 add.w r3, r7, #8 + 8000bb6: 4618 mov r0, r3 + 8000bb8: f00c fbac bl 800d314 + tiny_snprintf_like((char *)buff, MAX_TS_SIZE, "%ds%03d:", curtime.Seconds, curtime.SubSeconds); + 8000bbc: 68bb ldr r3, [r7, #8] + 8000bbe: f9b7 200c ldrsh.w r2, [r7, #12] + 8000bc2: 9200 str r2, [sp, #0] + 8000bc4: 4a07 ldr r2, [pc, #28] @ (8000be4 ) + 8000bc6: 2110 movs r1, #16 + 8000bc8: 6878 ldr r0, [r7, #4] + 8000bca: f000 f81d bl 8000c08 + *size = strlen((char *)buff); + 8000bce: 6878 ldr r0, [r7, #4] + 8000bd0: f7ff fae0 bl 8000194 + 8000bd4: 4603 mov r3, r0 + 8000bd6: b29a uxth r2, r3 + 8000bd8: 683b ldr r3, [r7, #0] + 8000bda: 801a strh r2, [r3, #0] + /* USER CODE BEGIN TimestampNow_2 */ + + /* USER CODE END TimestampNow_2 */ +} + 8000bdc: bf00 nop + 8000bde: 3710 adds r7, #16 + 8000be0: 46bd mov sp, r7 + 8000be2: bd80 pop {r7, pc} + 8000be4: 0800f0c0 .word 0x0800f0c0 + +08000be8 : + +/* Disable StopMode when traces need to be printed */ +void UTIL_ADV_TRACE_PreSendHook(void) +{ + 8000be8: b580 push {r7, lr} + 8000bea: af00 add r7, sp, #0 + /* USER CODE BEGIN UTIL_ADV_TRACE_PreSendHook_1 */ + + /* USER CODE END UTIL_ADV_TRACE_PreSendHook_1 */ + UTIL_LPM_SetStopMode((1 << CFG_LPM_UART_TX_Id), UTIL_LPM_DISABLE); + 8000bec: 2101 movs r1, #1 + 8000bee: 2002 movs r0, #2 + 8000bf0: f00c fa86 bl 800d100 + /* USER CODE BEGIN UTIL_ADV_TRACE_PreSendHook_2 */ + + /* USER CODE END UTIL_ADV_TRACE_PreSendHook_2 */ +} + 8000bf4: bf00 nop + 8000bf6: bd80 pop {r7, pc} + +08000bf8 : +/* Re-enable StopMode when traces have been printed */ +void UTIL_ADV_TRACE_PostSendHook(void) +{ + 8000bf8: b580 push {r7, lr} + 8000bfa: af00 add r7, sp, #0 + /* USER CODE BEGIN UTIL_LPM_SetStopMode_1 */ + + /* USER CODE END UTIL_LPM_SetStopMode_1 */ + UTIL_LPM_SetStopMode((1 << CFG_LPM_UART_TX_Id), UTIL_LPM_ENABLE); + 8000bfc: 2100 movs r1, #0 + 8000bfe: 2002 movs r0, #2 + 8000c00: f00c fa7e bl 800d100 + /* USER CODE BEGIN UTIL_LPM_SetStopMode_2 */ + + /* USER CODE END UTIL_LPM_SetStopMode_2 */ +} + 8000c04: bf00 nop + 8000c06: bd80 pop {r7, pc} + +08000c08 : + +static void tiny_snprintf_like(char *buf, uint32_t maxsize, const char *strFormat, ...) +{ + 8000c08: b40c push {r2, r3} + 8000c0a: b580 push {r7, lr} + 8000c0c: b084 sub sp, #16 + 8000c0e: af00 add r7, sp, #0 + 8000c10: 6078 str r0, [r7, #4] + 8000c12: 6039 str r1, [r7, #0] + /* USER CODE BEGIN tiny_snprintf_like_1 */ + + /* USER CODE END tiny_snprintf_like_1 */ + va_list vaArgs; + va_start(vaArgs, strFormat); + 8000c14: f107 031c add.w r3, r7, #28 + 8000c18: 60fb str r3, [r7, #12] + UTIL_ADV_TRACE_VSNPRINTF(buf, maxsize, strFormat, vaArgs); + 8000c1a: 6839 ldr r1, [r7, #0] + 8000c1c: 68fb ldr r3, [r7, #12] + 8000c1e: 69ba ldr r2, [r7, #24] + 8000c20: 6878 ldr r0, [r7, #4] + 8000c22: f00c fcc3 bl 800d5ac + va_end(vaArgs); + /* USER CODE BEGIN tiny_snprintf_like_2 */ + + /* USER CODE END tiny_snprintf_like_2 */ +} + 8000c26: bf00 nop + 8000c28: 3710 adds r7, #16 + 8000c2a: 46bd mov sp, r7 + 8000c2c: e8bd 4080 ldmia.w sp!, {r7, lr} + 8000c30: b002 add sp, #8 + 8000c32: 4770 bx lr + +08000c34 : + +/** + * @note This function overwrites the __weak one from HAL + */ +HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) +{ + 8000c34: b480 push {r7} + 8000c36: b083 sub sp, #12 + 8000c38: af00 add r7, sp, #0 + 8000c3a: 6078 str r0, [r7, #4] + /*Don't enable SysTick if TIMER_IF is based on other counters (e.g. RTC) */ + /* USER CODE BEGIN HAL_InitTick_1 */ + + /* USER CODE END HAL_InitTick_1 */ + return HAL_OK; + 8000c3c: 2300 movs r3, #0 + /* USER CODE BEGIN HAL_InitTick_2 */ + + /* USER CODE END HAL_InitTick_2 */ +} + 8000c3e: 4618 mov r0, r3 + 8000c40: 370c adds r7, #12 + 8000c42: 46bd mov sp, r7 + 8000c44: bc80 pop {r7} + 8000c46: 4770 bx lr + +08000c48 : + +/** + * @note This function overwrites the __weak one from HAL + */ +uint32_t HAL_GetTick(void) +{ + 8000c48: b580 push {r7, lr} + 8000c4a: b082 sub sp, #8 + 8000c4c: af00 add r7, sp, #0 + uint32_t ret = 0; + 8000c4e: 2300 movs r3, #0 + 8000c50: 607b str r3, [r7, #4] + /* TIMER_IF can be based on other counter the SysTick e.g. RTC */ + /* USER CODE BEGIN HAL_GetTick_1 */ + + /* USER CODE END HAL_GetTick_1 */ + if (SYS_TimerInitialisedFlag == 0) + 8000c52: 4b06 ldr r3, [pc, #24] @ (8000c6c ) + 8000c54: 781b ldrb r3, [r3, #0] + 8000c56: 2b00 cmp r3, #0 + 8000c58: d002 beq.n 8000c60 + + /* USER CODE END HAL_GetTick_EarlyCall */ + } + else + { + ret = TIMER_IF_GetTimerValue(); + 8000c5a: f000 f97b bl 8000f54 + 8000c5e: 6078 str r0, [r7, #4] + } + /* USER CODE BEGIN HAL_GetTick_2 */ + + /* USER CODE END HAL_GetTick_2 */ + return ret; + 8000c60: 687b ldr r3, [r7, #4] +} + 8000c62: 4618 mov r0, r3 + 8000c64: 3708 adds r7, #8 + 8000c66: 46bd mov sp, r7 + 8000c68: bd80 pop {r7, pc} + 8000c6a: bf00 nop + 8000c6c: 200000ec .word 0x200000ec + +08000c70 : + +/** + * @note This function overwrites the __weak one from HAL + */ +void HAL_Delay(__IO uint32_t Delay) +{ + 8000c70: b580 push {r7, lr} + 8000c72: b082 sub sp, #8 + 8000c74: af00 add r7, sp, #0 + 8000c76: 6078 str r0, [r7, #4] + /* TIMER_IF can be based on other counter the SysTick e.g. RTC */ + /* USER CODE BEGIN HAL_Delay_1 */ + + /* USER CODE END HAL_Delay_1 */ + TIMER_IF_DelayMs(Delay); + 8000c78: 687b ldr r3, [r7, #4] + 8000c7a: 4618 mov r0, r3 + 8000c7c: f000 f9f1 bl 8001062 + /* USER CODE BEGIN HAL_Delay_2 */ + + /* USER CODE END HAL_Delay_2 */ +} + 8000c80: bf00 nop + 8000c82: 3708 adds r7, #8 + 8000c84: 46bd mov sp, r7 + 8000c86: bd80 pop {r7, pc} + +08000c88 : +{ + 8000c88: b480 push {r7} + 8000c8a: b085 sub sp, #20 + 8000c8c: af00 add r7, sp, #0 + 8000c8e: 6078 str r0, [r7, #4] + SET_BIT(RCC->AHB2ENR, Periphs); + 8000c90: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8000c94: 6cda ldr r2, [r3, #76] @ 0x4c + 8000c96: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 8000c9a: 687b ldr r3, [r7, #4] + 8000c9c: 4313 orrs r3, r2 + 8000c9e: 64cb str r3, [r1, #76] @ 0x4c + tmpreg = READ_BIT(RCC->AHB2ENR, Periphs); + 8000ca0: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8000ca4: 6cda ldr r2, [r3, #76] @ 0x4c + 8000ca6: 687b ldr r3, [r7, #4] + 8000ca8: 4013 ands r3, r2 + 8000caa: 60fb str r3, [r7, #12] + (void)tmpreg; + 8000cac: 68fb ldr r3, [r7, #12] +} + 8000cae: bf00 nop + 8000cb0: 3714 adds r7, #20 + 8000cb2: 46bd mov sp, r7 + 8000cb4: bc80 pop {r7} + 8000cb6: 4770 bx lr + +08000cb8 : + * @arg @ref LL_EXTI_LINE_ALL_32_63 + * (*) value not defined in all devices + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableIT_32_63(uint32_t ExtiLine) +{ + 8000cb8: b480 push {r7} + 8000cba: b083 sub sp, #12 + 8000cbc: af00 add r7, sp, #0 + 8000cbe: 6078 str r0, [r7, #4] + SET_BIT(EXTI->IMR2, ExtiLine); + 8000cc0: 4b06 ldr r3, [pc, #24] @ (8000cdc ) + 8000cc2: f8d3 2090 ldr.w r2, [r3, #144] @ 0x90 + 8000cc6: 4905 ldr r1, [pc, #20] @ (8000cdc ) + 8000cc8: 687b ldr r3, [r7, #4] + 8000cca: 4313 orrs r3, r2 + 8000ccc: f8c1 3090 str.w r3, [r1, #144] @ 0x90 +} + 8000cd0: bf00 nop + 8000cd2: 370c adds r7, #12 + 8000cd4: 46bd mov sp, r7 + 8000cd6: bc80 pop {r7} + 8000cd8: 4770 bx lr + 8000cda: bf00 nop + 8000cdc: 58000800 .word 0x58000800 + +08000ce0 : + +/** + * @brief Initializes the SW probes pins and the monitor RF pins via Alternate Function + */ +void DBG_Init(void) +{ + 8000ce0: b580 push {r7, lr} + 8000ce2: b086 sub sp, #24 + 8000ce4: af00 add r7, sp, #0 + HAL_DBGMCU_DisableDBGSleepMode(); + HAL_DBGMCU_DisableDBGStopMode(); + HAL_DBGMCU_DisableDBGStandbyMode(); +#elif defined (DEBUGGER_ENABLED) && ( DEBUGGER_ENABLED == 1 ) + /*Debug power up request wakeup CBDGPWRUPREQ*/ + LL_EXTI_EnableIT_32_63(LL_EXTI_LINE_46); + 8000ce6: f44f 4080 mov.w r0, #16384 @ 0x4000 + 8000cea: f7ff ffe5 bl 8000cb8 + /* Disabled HAL_DBGMCU_ */ + HAL_DBGMCU_EnableDBGSleepMode(); + 8000cee: f000 fe5b bl 80019a8 + HAL_DBGMCU_EnableDBGStopMode(); + 8000cf2: f000 fe5f bl 80019b4 + HAL_DBGMCU_EnableDBGStandbyMode(); + 8000cf6: f000 fe63 bl 80019c0 +#elif !defined (DEBUGGER_ENABLED) +#error "DEBUGGER_ENABLED not defined or out of range <0,1>" +#endif /* DEBUGGER_OFF */ + + GPIO_InitTypeDef GPIO_InitStruct = {0}; + 8000cfa: 1d3b adds r3, r7, #4 + 8000cfc: 2200 movs r2, #0 + 8000cfe: 601a str r2, [r3, #0] + 8000d00: 605a str r2, [r3, #4] + 8000d02: 609a str r2, [r3, #8] + 8000d04: 60da str r2, [r3, #12] + 8000d06: 611a str r2, [r3, #16] + + /* Configure the GPIO pin */ + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + 8000d08: 2301 movs r3, #1 + 8000d0a: 60bb str r3, [r7, #8] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8000d0c: 2300 movs r3, #0 + 8000d0e: 60fb str r3, [r7, #12] + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + 8000d10: 2303 movs r3, #3 + 8000d12: 613b str r3, [r7, #16] + + /* Enable the GPIO Clock */ + PROBE_LINE1_CLK_ENABLE(); + 8000d14: 2002 movs r0, #2 + 8000d16: f7ff ffb7 bl 8000c88 + PROBE_LINE2_CLK_ENABLE(); + 8000d1a: 2002 movs r0, #2 + 8000d1c: f7ff ffb4 bl 8000c88 + + GPIO_InitStruct.Pin = PROBE_LINE1_PIN; + 8000d20: f44f 5380 mov.w r3, #4096 @ 0x1000 + 8000d24: 607b str r3, [r7, #4] + HAL_GPIO_Init(PROBE_LINE1_PORT, &GPIO_InitStruct); + 8000d26: 1d3b adds r3, r7, #4 + 8000d28: 4619 mov r1, r3 + 8000d2a: 480d ldr r0, [pc, #52] @ (8000d60 ) + 8000d2c: f001 fb82 bl 8002434 + GPIO_InitStruct.Pin = PROBE_LINE2_PIN; + 8000d30: f44f 5300 mov.w r3, #8192 @ 0x2000 + 8000d34: 607b str r3, [r7, #4] + HAL_GPIO_Init(PROBE_LINE2_PORT, &GPIO_InitStruct); + 8000d36: 1d3b adds r3, r7, #4 + 8000d38: 4619 mov r1, r3 + 8000d3a: 4809 ldr r0, [pc, #36] @ (8000d60 ) + 8000d3c: f001 fb7a bl 8002434 + + /* Reset probe Pins */ + HAL_GPIO_WritePin(PROBE_LINE1_PORT, PROBE_LINE1_PIN, GPIO_PIN_RESET); + 8000d40: 2200 movs r2, #0 + 8000d42: f44f 5180 mov.w r1, #4096 @ 0x1000 + 8000d46: 4806 ldr r0, [pc, #24] @ (8000d60 ) + 8000d48: f001 fda2 bl 8002890 + HAL_GPIO_WritePin(PROBE_LINE2_PORT, PROBE_LINE2_PIN, GPIO_PIN_RESET); + 8000d4c: 2200 movs r2, #0 + 8000d4e: f44f 5100 mov.w r1, #8192 @ 0x2000 + 8000d52: 4803 ldr r0, [pc, #12] @ (8000d60 ) + 8000d54: f001 fd9c bl 8002890 +#endif /* DEBUG_RF_BUSY_ENABLED */ + + /* USER CODE BEGIN DBG_Init_3 */ + + /* USER CODE END DBG_Init_3 */ +} + 8000d58: bf00 nop + 8000d5a: 3718 adds r7, #24 + 8000d5c: 46bd mov sp, r7 + 8000d5e: bd80 pop {r7, pc} + 8000d60: 48000400 .word 0x48000400 + +08000d64 <_sbrk>: + * + * @param incr Memory size + * @return Pointer to allocated memory + */ +void *_sbrk(ptrdiff_t incr) +{ + 8000d64: b580 push {r7, lr} + 8000d66: b086 sub sp, #24 + 8000d68: af00 add r7, sp, #0 + 8000d6a: 6078 str r0, [r7, #4] + extern uint8_t _end; /* Symbol defined in the linker script */ + extern uint8_t _estack; /* Symbol defined in the linker script */ + extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */ + const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size; + 8000d6c: 4a14 ldr r2, [pc, #80] @ (8000dc0 <_sbrk+0x5c>) + 8000d6e: 4b15 ldr r3, [pc, #84] @ (8000dc4 <_sbrk+0x60>) + 8000d70: 1ad3 subs r3, r2, r3 + 8000d72: 617b str r3, [r7, #20] + const uint8_t *max_heap = (uint8_t *)stack_limit; + 8000d74: 697b ldr r3, [r7, #20] + 8000d76: 613b str r3, [r7, #16] + uint8_t *prev_heap_end; + + /* Initialize heap end at first call */ + if (NULL == __sbrk_heap_end) + 8000d78: 4b13 ldr r3, [pc, #76] @ (8000dc8 <_sbrk+0x64>) + 8000d7a: 681b ldr r3, [r3, #0] + 8000d7c: 2b00 cmp r3, #0 + 8000d7e: d102 bne.n 8000d86 <_sbrk+0x22> + { + __sbrk_heap_end = &_end; + 8000d80: 4b11 ldr r3, [pc, #68] @ (8000dc8 <_sbrk+0x64>) + 8000d82: 4a12 ldr r2, [pc, #72] @ (8000dcc <_sbrk+0x68>) + 8000d84: 601a str r2, [r3, #0] + } + + /* Protect heap from growing into the reserved MSP stack */ + if (__sbrk_heap_end + incr > max_heap) + 8000d86: 4b10 ldr r3, [pc, #64] @ (8000dc8 <_sbrk+0x64>) + 8000d88: 681a ldr r2, [r3, #0] + 8000d8a: 687b ldr r3, [r7, #4] + 8000d8c: 4413 add r3, r2 + 8000d8e: 693a ldr r2, [r7, #16] + 8000d90: 429a cmp r2, r3 + 8000d92: d207 bcs.n 8000da4 <_sbrk+0x40> + { + errno = ENOMEM; + 8000d94: f00d fd12 bl 800e7bc <__errno> + 8000d98: 4603 mov r3, r0 + 8000d9a: 220c movs r2, #12 + 8000d9c: 601a str r2, [r3, #0] + return (void *)-1; + 8000d9e: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff + 8000da2: e009 b.n 8000db8 <_sbrk+0x54> + } + + prev_heap_end = __sbrk_heap_end; + 8000da4: 4b08 ldr r3, [pc, #32] @ (8000dc8 <_sbrk+0x64>) + 8000da6: 681b ldr r3, [r3, #0] + 8000da8: 60fb str r3, [r7, #12] + __sbrk_heap_end += incr; + 8000daa: 4b07 ldr r3, [pc, #28] @ (8000dc8 <_sbrk+0x64>) + 8000dac: 681a ldr r2, [r3, #0] + 8000dae: 687b ldr r3, [r7, #4] + 8000db0: 4413 add r3, r2 + 8000db2: 4a05 ldr r2, [pc, #20] @ (8000dc8 <_sbrk+0x64>) + 8000db4: 6013 str r3, [r2, #0] + + return (void *)prev_heap_end; + 8000db6: 68fb ldr r3, [r7, #12] +} + 8000db8: 4618 mov r0, r3 + 8000dba: 3718 adds r7, #24 + 8000dbc: 46bd mov sp, r7 + 8000dbe: bd80 pop {r7, pc} + 8000dc0: 20010000 .word 0x20010000 + 8000dc4: 00000800 .word 0x00000800 + 8000dc8: 200000f0 .word 0x200000f0 + 8000dcc: 20001068 .word 0x20001068 + +08000dd0 : + * @brief Setup the microcontroller system. + * @param None + * @retval None + */ +void SystemInit(void) +{ + 8000dd0: b480 push {r7} + 8000dd2: af00 add r7, sp, #0 + + /* FPU settings ------------------------------------------------------------*/ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << (10UL*2UL))|(3UL << (11UL*2UL))); /* set CP10 and CP11 Full Access */ +#endif +} + 8000dd4: bf00 nop + 8000dd6: 46bd mov sp, r7 + 8000dd8: bc80 pop {r7} + 8000dda: 4770 bx lr + +08000ddc : + * @param RTCx RTC Instance + * @retval If binary mode is none, Value between Min_Data=0x0 and Max_Data=0x7FFF + * else Value between Min_Data=0x0 and Max_Data=0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_RTC_TIME_GetSubSecond(const RTC_TypeDef *RTCx) +{ + 8000ddc: b480 push {r7} + 8000dde: b083 sub sp, #12 + 8000de0: af00 add r7, sp, #0 + 8000de2: 6078 str r0, [r7, #4] + return (uint32_t)(READ_BIT(RTCx->SSR, RTC_SSR_SS)); + 8000de4: 687b ldr r3, [r7, #4] + 8000de6: 689b ldr r3, [r3, #8] +} + 8000de8: 4618 mov r0, r3 + 8000dea: 370c adds r7, #12 + 8000dec: 46bd mov sp, r7 + 8000dee: bc80 pop {r7} + 8000df0: 4770 bx lr + ... + +08000df4 : + +/* USER CODE END PFP */ + +/* Exported functions ---------------------------------------------------------*/ +UTIL_TIMER_Status_t TIMER_IF_Init(void) +{ + 8000df4: b580 push {r7, lr} + 8000df6: b082 sub sp, #8 + 8000df8: af00 add r7, sp, #0 + UTIL_TIMER_Status_t ret = UTIL_TIMER_OK; + 8000dfa: 2300 movs r3, #0 + 8000dfc: 71fb strb r3, [r7, #7] + /* USER CODE BEGIN TIMER_IF_Init */ + + /* USER CODE END TIMER_IF_Init */ + if (RTC_Initialized == false) + 8000dfe: 4b14 ldr r3, [pc, #80] @ (8000e50 ) + 8000e00: 781b ldrb r3, [r3, #0] + 8000e02: f083 0301 eor.w r3, r3, #1 + 8000e06: b2db uxtb r3, r3 + 8000e08: 2b00 cmp r3, #0 + 8000e0a: d01b beq.n 8000e44 + { + hrtc.IsEnabled.RtcFeatures = UINT32_MAX; + 8000e0c: 4b11 ldr r3, [pc, #68] @ (8000e54 ) + 8000e0e: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff + 8000e12: 631a str r2, [r3, #48] @ 0x30 + /*Init RTC*/ + MX_RTC_Init(); + 8000e14: f7ff fd0a bl 800082c + /*Stop Timer */ + TIMER_IF_StopTimer(); + 8000e18: f000 f856 bl 8000ec8 + /** DeActivate the Alarm A enabled by STM32CubeMX during MX_RTC_Init() */ + HAL_RTC_DeactivateAlarm(&hrtc, RTC_ALARM_A); + 8000e1c: f44f 7180 mov.w r1, #256 @ 0x100 + 8000e20: 480c ldr r0, [pc, #48] @ (8000e54 ) + 8000e22: f003 fad7 bl 80043d4 + /*overload RTC feature enable*/ + hrtc.IsEnabled.RtcFeatures = UINT32_MAX; + 8000e26: 4b0b ldr r3, [pc, #44] @ (8000e54 ) + 8000e28: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff + 8000e2c: 631a str r2, [r3, #48] @ 0x30 + + /*Enable Direct Read of the calendar registers (not through Shadow) */ + HAL_RTCEx_EnableBypassShadow(&hrtc); + 8000e2e: 4809 ldr r0, [pc, #36] @ (8000e54 ) + 8000e30: f003 fc0e bl 8004650 + /*Initialize MSB ticks*/ + TIMER_IF_BkUp_Write_MSBticks(0); + 8000e34: 2000 movs r0, #0 + 8000e36: f000 f9d3 bl 80011e0 + + TIMER_IF_SetTimerContext(); + 8000e3a: f000 f85f bl 8000efc + + /* Register a task to associate to UTIL_TIMER_Irq() interrupt */ + UTIL_TIMER_IRQ_MAP_INIT(); + + RTC_Initialized = true; + 8000e3e: 4b04 ldr r3, [pc, #16] @ (8000e50 ) + 8000e40: 2201 movs r2, #1 + 8000e42: 701a strb r2, [r3, #0] + } + + /* USER CODE BEGIN TIMER_IF_Init_Last */ + + /* USER CODE END TIMER_IF_Init_Last */ + return ret; + 8000e44: 79fb ldrb r3, [r7, #7] +} + 8000e46: 4618 mov r0, r3 + 8000e48: 3708 adds r7, #8 + 8000e4a: 46bd mov sp, r7 + 8000e4c: bd80 pop {r7, pc} + 8000e4e: bf00 nop + 8000e50: 200000f4 .word 0x200000f4 + 8000e54: 200000a8 .word 0x200000a8 + +08000e58 : + +UTIL_TIMER_Status_t TIMER_IF_StartTimer(uint32_t timeout) +{ + 8000e58: b580 push {r7, lr} + 8000e5a: b08e sub sp, #56 @ 0x38 + 8000e5c: af00 add r7, sp, #0 + 8000e5e: 6078 str r0, [r7, #4] + UTIL_TIMER_Status_t ret = UTIL_TIMER_OK; + 8000e60: 2300 movs r3, #0 + 8000e62: f887 3037 strb.w r3, [r7, #55] @ 0x37 + /* USER CODE BEGIN TIMER_IF_StartTimer */ + + /* USER CODE END TIMER_IF_StartTimer */ + RTC_AlarmTypeDef sAlarm = {0}; + 8000e66: f107 0308 add.w r3, r7, #8 + 8000e6a: 222c movs r2, #44 @ 0x2c + 8000e6c: 2100 movs r1, #0 + 8000e6e: 4618 mov r0, r3 + 8000e70: f00d fc8a bl 800e788 + /*Stop timer if one is already started*/ + TIMER_IF_StopTimer(); + 8000e74: f000 f828 bl 8000ec8 + timeout += RtcTimerContext; + 8000e78: 4b11 ldr r3, [pc, #68] @ (8000ec0 ) + 8000e7a: 681b ldr r3, [r3, #0] + 8000e7c: 687a ldr r2, [r7, #4] + 8000e7e: 4413 add r3, r2 + 8000e80: 607b str r3, [r7, #4] + + TIMER_IF_DBG_PRINTF("Start timer: time=%d, alarm=%d\n\r", GetTimerTicks(), timeout); + /* starts timer*/ + sAlarm.BinaryAutoClr = RTC_ALARMSUBSECONDBIN_AUTOCLR_NO; + 8000e82: 2300 movs r3, #0 + 8000e84: 627b str r3, [r7, #36] @ 0x24 + sAlarm.AlarmTime.SubSeconds = UINT32_MAX - timeout; + 8000e86: 687b ldr r3, [r7, #4] + 8000e88: 43db mvns r3, r3 + 8000e8a: 60fb str r3, [r7, #12] + sAlarm.AlarmMask = RTC_ALARMMASK_NONE; + 8000e8c: 2300 movs r3, #0 + 8000e8e: 61fb str r3, [r7, #28] + sAlarm.AlarmSubSecondMask = RTC_ALARMSUBSECONDBINMASK_NONE; + 8000e90: f04f 5300 mov.w r3, #536870912 @ 0x20000000 + 8000e94: 623b str r3, [r7, #32] + sAlarm.Alarm = RTC_ALARM_A; + 8000e96: f44f 7380 mov.w r3, #256 @ 0x100 + 8000e9a: 633b str r3, [r7, #48] @ 0x30 + if (HAL_RTC_SetAlarm_IT(&hrtc, &sAlarm, RTC_FORMAT_BCD) != HAL_OK) + 8000e9c: f107 0308 add.w r3, r7, #8 + 8000ea0: 2201 movs r2, #1 + 8000ea2: 4619 mov r1, r3 + 8000ea4: 4807 ldr r0, [pc, #28] @ (8000ec4 ) + 8000ea6: f003 f989 bl 80041bc + 8000eaa: 4603 mov r3, r0 + 8000eac: 2b00 cmp r3, #0 + 8000eae: d001 beq.n 8000eb4 + { + Error_Handler(); + 8000eb0: f7ff fc8e bl 80007d0 + } + /* USER CODE BEGIN TIMER_IF_StartTimer_Last */ + + /* USER CODE END TIMER_IF_StartTimer_Last */ + return ret; + 8000eb4: f897 3037 ldrb.w r3, [r7, #55] @ 0x37 +} + 8000eb8: 4618 mov r0, r3 + 8000eba: 3738 adds r7, #56 @ 0x38 + 8000ebc: 46bd mov sp, r7 + 8000ebe: bd80 pop {r7, pc} + 8000ec0: 200000f8 .word 0x200000f8 + 8000ec4: 200000a8 .word 0x200000a8 + +08000ec8 : + +UTIL_TIMER_Status_t TIMER_IF_StopTimer(void) +{ + 8000ec8: b580 push {r7, lr} + 8000eca: b082 sub sp, #8 + 8000ecc: af00 add r7, sp, #0 + UTIL_TIMER_Status_t ret = UTIL_TIMER_OK; + 8000ece: 2300 movs r3, #0 + 8000ed0: 71fb strb r3, [r7, #7] + /* USER CODE BEGIN TIMER_IF_StopTimer */ + + /* USER CODE END TIMER_IF_StopTimer */ + /* Clear RTC Alarm Flag */ + __HAL_RTC_ALARM_CLEAR_FLAG(&hrtc, RTC_FLAG_ALRAF); + 8000ed2: 4b08 ldr r3, [pc, #32] @ (8000ef4 ) + 8000ed4: 2201 movs r2, #1 + 8000ed6: 65da str r2, [r3, #92] @ 0x5c + /* Disable the Alarm A interrupt */ + HAL_RTC_DeactivateAlarm(&hrtc, RTC_ALARM_A); + 8000ed8: f44f 7180 mov.w r1, #256 @ 0x100 + 8000edc: 4806 ldr r0, [pc, #24] @ (8000ef8 ) + 8000ede: f003 fa79 bl 80043d4 + /*overload RTC feature enable*/ + hrtc.IsEnabled.RtcFeatures = UINT32_MAX; + 8000ee2: 4b05 ldr r3, [pc, #20] @ (8000ef8 ) + 8000ee4: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff + 8000ee8: 631a str r2, [r3, #48] @ 0x30 + /* USER CODE BEGIN TIMER_IF_StopTimer_Last */ + + /* USER CODE END TIMER_IF_StopTimer_Last */ + return ret; + 8000eea: 79fb ldrb r3, [r7, #7] +} + 8000eec: 4618 mov r0, r3 + 8000eee: 3708 adds r7, #8 + 8000ef0: 46bd mov sp, r7 + 8000ef2: bd80 pop {r7, pc} + 8000ef4: 40002800 .word 0x40002800 + 8000ef8: 200000a8 .word 0x200000a8 + +08000efc : + +uint32_t TIMER_IF_SetTimerContext(void) +{ + 8000efc: b580 push {r7, lr} + 8000efe: af00 add r7, sp, #0 + /*store time context*/ + RtcTimerContext = GetTimerTicks(); + 8000f00: f000 f98e bl 8001220 + 8000f04: 4603 mov r3, r0 + 8000f06: 4a03 ldr r2, [pc, #12] @ (8000f14 ) + 8000f08: 6013 str r3, [r2, #0] + + /* USER CODE END TIMER_IF_SetTimerContext */ + + TIMER_IF_DBG_PRINTF("TIMER_IF_SetTimerContext=%d\n\r", RtcTimerContext); + /*return time context*/ + return RtcTimerContext; + 8000f0a: 4b02 ldr r3, [pc, #8] @ (8000f14 ) + 8000f0c: 681b ldr r3, [r3, #0] +} + 8000f0e: 4618 mov r0, r3 + 8000f10: bd80 pop {r7, pc} + 8000f12: bf00 nop + 8000f14: 200000f8 .word 0x200000f8 + +08000f18 : + +uint32_t TIMER_IF_GetTimerContext(void) +{ + 8000f18: b480 push {r7} + 8000f1a: af00 add r7, sp, #0 + + /* USER CODE END TIMER_IF_GetTimerContext */ + + TIMER_IF_DBG_PRINTF("TIMER_IF_GetTimerContext=%d\n\r", RtcTimerContext); + /*return time context*/ + return RtcTimerContext; + 8000f1c: 4b02 ldr r3, [pc, #8] @ (8000f28 ) + 8000f1e: 681b ldr r3, [r3, #0] +} + 8000f20: 4618 mov r0, r3 + 8000f22: 46bd mov sp, r7 + 8000f24: bc80 pop {r7} + 8000f26: 4770 bx lr + 8000f28: 200000f8 .word 0x200000f8 + +08000f2c : + +uint32_t TIMER_IF_GetTimerElapsedTime(void) +{ + 8000f2c: b580 push {r7, lr} + 8000f2e: b082 sub sp, #8 + 8000f30: af00 add r7, sp, #0 + uint32_t ret = 0; + 8000f32: 2300 movs r3, #0 + 8000f34: 607b str r3, [r7, #4] + /* USER CODE BEGIN TIMER_IF_GetTimerElapsedTime */ + + /* USER CODE END TIMER_IF_GetTimerElapsedTime */ + ret = ((uint32_t)(GetTimerTicks() - RtcTimerContext)); + 8000f36: f000 f973 bl 8001220 + 8000f3a: 4602 mov r2, r0 + 8000f3c: 4b04 ldr r3, [pc, #16] @ (8000f50 ) + 8000f3e: 681b ldr r3, [r3, #0] + 8000f40: 1ad3 subs r3, r2, r3 + 8000f42: 607b str r3, [r7, #4] + /* USER CODE BEGIN TIMER_IF_GetTimerElapsedTime_Last */ + + /* USER CODE END TIMER_IF_GetTimerElapsedTime_Last */ + return ret; + 8000f44: 687b ldr r3, [r7, #4] +} + 8000f46: 4618 mov r0, r3 + 8000f48: 3708 adds r7, #8 + 8000f4a: 46bd mov sp, r7 + 8000f4c: bd80 pop {r7, pc} + 8000f4e: bf00 nop + 8000f50: 200000f8 .word 0x200000f8 + +08000f54 : + +uint32_t TIMER_IF_GetTimerValue(void) +{ + 8000f54: b580 push {r7, lr} + 8000f56: b082 sub sp, #8 + 8000f58: af00 add r7, sp, #0 + uint32_t ret = 0; + 8000f5a: 2300 movs r3, #0 + 8000f5c: 607b str r3, [r7, #4] + /* USER CODE BEGIN TIMER_IF_GetTimerValue */ + + /* USER CODE END TIMER_IF_GetTimerValue */ + if (RTC_Initialized == true) + 8000f5e: 4b06 ldr r3, [pc, #24] @ (8000f78 ) + 8000f60: 781b ldrb r3, [r3, #0] + 8000f62: 2b00 cmp r3, #0 + 8000f64: d002 beq.n 8000f6c + { + ret = GetTimerTicks(); + 8000f66: f000 f95b bl 8001220 + 8000f6a: 6078 str r0, [r7, #4] + } + /* USER CODE BEGIN TIMER_IF_GetTimerValue_Last */ + + /* USER CODE END TIMER_IF_GetTimerValue_Last */ + return ret; + 8000f6c: 687b ldr r3, [r7, #4] +} + 8000f6e: 4618 mov r0, r3 + 8000f70: 3708 adds r7, #8 + 8000f72: 46bd mov sp, r7 + 8000f74: bd80 pop {r7, pc} + 8000f76: bf00 nop + 8000f78: 200000f4 .word 0x200000f4 + +08000f7c : + +uint32_t TIMER_IF_GetMinimumTimeout(void) +{ + 8000f7c: b480 push {r7} + 8000f7e: b083 sub sp, #12 + 8000f80: af00 add r7, sp, #0 + uint32_t ret = 0; + 8000f82: 2300 movs r3, #0 + 8000f84: 607b str r3, [r7, #4] + /* USER CODE BEGIN TIMER_IF_GetMinimumTimeout */ + + /* USER CODE END TIMER_IF_GetMinimumTimeout */ + ret = (MIN_ALARM_DELAY); + 8000f86: 2303 movs r3, #3 + 8000f88: 607b str r3, [r7, #4] + /* USER CODE BEGIN TIMER_IF_GetMinimumTimeout_Last */ + + /* USER CODE END TIMER_IF_GetMinimumTimeout_Last */ + return ret; + 8000f8a: 687b ldr r3, [r7, #4] +} + 8000f8c: 4618 mov r0, r3 + 8000f8e: 370c adds r7, #12 + 8000f90: 46bd mov sp, r7 + 8000f92: bc80 pop {r7} + 8000f94: 4770 bx lr + +08000f96 : + +uint32_t TIMER_IF_Convert_ms2Tick(uint32_t timeMilliSec) +{ + 8000f96: b5b0 push {r4, r5, r7, lr} + 8000f98: b084 sub sp, #16 + 8000f9a: af00 add r7, sp, #0 + 8000f9c: 6078 str r0, [r7, #4] + uint32_t ret = 0; + 8000f9e: 2100 movs r1, #0 + 8000fa0: 60f9 str r1, [r7, #12] + /* USER CODE BEGIN TIMER_IF_Convert_ms2Tick */ + + /* USER CODE END TIMER_IF_Convert_ms2Tick */ + ret = ((uint32_t)((((uint64_t) timeMilliSec) << RTC_N_PREDIV_S) / 1000)); + 8000fa2: 6879 ldr r1, [r7, #4] + 8000fa4: 2000 movs r0, #0 + 8000fa6: 460a mov r2, r1 + 8000fa8: 4603 mov r3, r0 + 8000faa: 0d95 lsrs r5, r2, #22 + 8000fac: 0294 lsls r4, r2, #10 + 8000fae: f44f 727a mov.w r2, #1000 @ 0x3e8 + 8000fb2: f04f 0300 mov.w r3, #0 + 8000fb6: 4620 mov r0, r4 + 8000fb8: 4629 mov r1, r5 + 8000fba: f7ff f949 bl 8000250 <__aeabi_uldivmod> + 8000fbe: 4602 mov r2, r0 + 8000fc0: 460b mov r3, r1 + 8000fc2: 4613 mov r3, r2 + 8000fc4: 60fb str r3, [r7, #12] + /* USER CODE BEGIN TIMER_IF_Convert_ms2Tick_Last */ + + /* USER CODE END TIMER_IF_Convert_ms2Tick_Last */ + return ret; + 8000fc6: 68fb ldr r3, [r7, #12] +} + 8000fc8: 4618 mov r0, r3 + 8000fca: 3710 adds r7, #16 + 8000fcc: 46bd mov sp, r7 + 8000fce: bdb0 pop {r4, r5, r7, pc} + +08000fd0 : + +uint32_t TIMER_IF_Convert_Tick2ms(uint32_t tick) +{ + 8000fd0: e92d 0fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp} + 8000fd4: b085 sub sp, #20 + 8000fd6: af00 add r7, sp, #0 + 8000fd8: 6078 str r0, [r7, #4] + uint32_t ret = 0; + 8000fda: 2100 movs r1, #0 + 8000fdc: 60f9 str r1, [r7, #12] + /* USER CODE BEGIN TIMER_IF_Convert_Tick2ms */ + + /* USER CODE END TIMER_IF_Convert_Tick2ms */ + ret = ((uint32_t)((((uint64_t)(tick)) * 1000) >> RTC_N_PREDIV_S)); + 8000fde: 6879 ldr r1, [r7, #4] + 8000fe0: 2000 movs r0, #0 + 8000fe2: 460c mov r4, r1 + 8000fe4: 4605 mov r5, r0 + 8000fe6: 4620 mov r0, r4 + 8000fe8: 4629 mov r1, r5 + 8000fea: f04f 0a00 mov.w sl, #0 + 8000fee: f04f 0b00 mov.w fp, #0 + 8000ff2: ea4f 1b41 mov.w fp, r1, lsl #5 + 8000ff6: ea4b 6bd0 orr.w fp, fp, r0, lsr #27 + 8000ffa: ea4f 1a40 mov.w sl, r0, lsl #5 + 8000ffe: 4650 mov r0, sl + 8001000: 4659 mov r1, fp + 8001002: 1b02 subs r2, r0, r4 + 8001004: eb61 0305 sbc.w r3, r1, r5 + 8001008: f04f 0000 mov.w r0, #0 + 800100c: f04f 0100 mov.w r1, #0 + 8001010: 0099 lsls r1, r3, #2 + 8001012: ea41 7192 orr.w r1, r1, r2, lsr #30 + 8001016: 0090 lsls r0, r2, #2 + 8001018: 4602 mov r2, r0 + 800101a: 460b mov r3, r1 + 800101c: eb12 0804 adds.w r8, r2, r4 + 8001020: eb43 0905 adc.w r9, r3, r5 + 8001024: f04f 0200 mov.w r2, #0 + 8001028: f04f 0300 mov.w r3, #0 + 800102c: ea4f 03c9 mov.w r3, r9, lsl #3 + 8001030: ea43 7358 orr.w r3, r3, r8, lsr #29 + 8001034: ea4f 02c8 mov.w r2, r8, lsl #3 + 8001038: 4690 mov r8, r2 + 800103a: 4699 mov r9, r3 + 800103c: 4640 mov r0, r8 + 800103e: 4649 mov r1, r9 + 8001040: f04f 0200 mov.w r2, #0 + 8001044: f04f 0300 mov.w r3, #0 + 8001048: 0a82 lsrs r2, r0, #10 + 800104a: ea42 5281 orr.w r2, r2, r1, lsl #22 + 800104e: 0a8b lsrs r3, r1, #10 + 8001050: 4613 mov r3, r2 + 8001052: 60fb str r3, [r7, #12] + /* USER CODE BEGIN TIMER_IF_Convert_Tick2ms_Last */ + + /* USER CODE END TIMER_IF_Convert_Tick2ms_Last */ + return ret; + 8001054: 68fb ldr r3, [r7, #12] +} + 8001056: 4618 mov r0, r3 + 8001058: 3714 adds r7, #20 + 800105a: 46bd mov sp, r7 + 800105c: e8bd 0fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp} + 8001060: 4770 bx lr + +08001062 : + +void TIMER_IF_DelayMs(uint32_t delay) +{ + 8001062: b580 push {r7, lr} + 8001064: b084 sub sp, #16 + 8001066: af00 add r7, sp, #0 + 8001068: 6078 str r0, [r7, #4] + /* USER CODE BEGIN TIMER_IF_DelayMs */ + + /* USER CODE END TIMER_IF_DelayMs */ + uint32_t delayTicks = TIMER_IF_Convert_ms2Tick(delay); + 800106a: 6878 ldr r0, [r7, #4] + 800106c: f7ff ff93 bl 8000f96 + 8001070: 60f8 str r0, [r7, #12] + uint32_t timeout = GetTimerTicks(); + 8001072: f000 f8d5 bl 8001220 + 8001076: 60b8 str r0, [r7, #8] + + /* Wait delay ms */ + while (((GetTimerTicks() - timeout)) < delayTicks) + 8001078: e000 b.n 800107c + { + __NOP(); + 800107a: bf00 nop + while (((GetTimerTicks() - timeout)) < delayTicks) + 800107c: f000 f8d0 bl 8001220 + 8001080: 4602 mov r2, r0 + 8001082: 68bb ldr r3, [r7, #8] + 8001084: 1ad3 subs r3, r2, r3 + 8001086: 68fa ldr r2, [r7, #12] + 8001088: 429a cmp r2, r3 + 800108a: d8f6 bhi.n 800107a + } + /* USER CODE BEGIN TIMER_IF_DelayMs_Last */ + + /* USER CODE END TIMER_IF_DelayMs_Last */ +} + 800108c: bf00 nop + 800108e: bf00 nop + 8001090: 3710 adds r7, #16 + 8001092: 46bd mov sp, r7 + 8001094: bd80 pop {r7, pc} + +08001096 : + +void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc) +{ + 8001096: b580 push {r7, lr} + 8001098: b082 sub sp, #8 + 800109a: af00 add r7, sp, #0 + 800109c: 6078 str r0, [r7, #4] + /* USER CODE BEGIN HAL_RTC_AlarmAEventCallback */ + + /* USER CODE END HAL_RTC_AlarmAEventCallback */ + UTIL_TIMER_IRQ_MAP_PROCESS(); + 800109e: f00c fe65 bl 800dd6c + /* USER CODE BEGIN HAL_RTC_AlarmAEventCallback_Last */ + + /* USER CODE END HAL_RTC_AlarmAEventCallback_Last */ +} + 80010a2: bf00 nop + 80010a4: 3708 adds r7, #8 + 80010a6: 46bd mov sp, r7 + 80010a8: bd80 pop {r7, pc} + +080010aa : + +void HAL_RTCEx_SSRUEventCallback(RTC_HandleTypeDef *hrtc) +{ + 80010aa: b580 push {r7, lr} + 80010ac: b084 sub sp, #16 + 80010ae: af00 add r7, sp, #0 + 80010b0: 6078 str r0, [r7, #4] + + /* USER CODE END HAL_RTCEx_SSRUEventCallback */ + /*called every 48 days with 1024 ticks per seconds*/ + TIMER_IF_DBG_PRINTF(">>Handler SSRUnderflow at %d\n\r", GetTimerTicks()); + /*Increment MSBticks*/ + uint32_t MSB_ticks = TIMER_IF_BkUp_Read_MSBticks(); + 80010b2: f000 f8a5 bl 8001200 + 80010b6: 60f8 str r0, [r7, #12] + TIMER_IF_BkUp_Write_MSBticks(MSB_ticks + 1); + 80010b8: 68fb ldr r3, [r7, #12] + 80010ba: 3301 adds r3, #1 + 80010bc: 4618 mov r0, r3 + 80010be: f000 f88f bl 80011e0 + /* USER CODE BEGIN HAL_RTCEx_SSRUEventCallback_Last */ + + /* USER CODE END HAL_RTCEx_SSRUEventCallback_Last */ +} + 80010c2: bf00 nop + 80010c4: 3710 adds r7, #16 + 80010c6: 46bd mov sp, r7 + 80010c8: bd80 pop {r7, pc} + +080010ca : + +uint32_t TIMER_IF_GetTime(uint16_t *mSeconds) +{ + 80010ca: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr} + 80010ce: b08c sub sp, #48 @ 0x30 + 80010d0: af00 add r7, sp, #0 + 80010d2: 6178 str r0, [r7, #20] + uint32_t seconds = 0; + 80010d4: 2300 movs r3, #0 + 80010d6: 62fb str r3, [r7, #44] @ 0x2c + /* USER CODE BEGIN TIMER_IF_GetTime */ + + /* USER CODE END TIMER_IF_GetTime */ + uint64_t ticks; + uint32_t timerValueLsb = GetTimerTicks(); + 80010d8: f000 f8a2 bl 8001220 + 80010dc: 62b8 str r0, [r7, #40] @ 0x28 + uint32_t timerValueMSB = TIMER_IF_BkUp_Read_MSBticks(); + 80010de: f000 f88f bl 8001200 + 80010e2: 6278 str r0, [r7, #36] @ 0x24 + + ticks = (((uint64_t) timerValueMSB) << 32) + timerValueLsb; + 80010e4: 6a7b ldr r3, [r7, #36] @ 0x24 + 80010e6: 2200 movs r2, #0 + 80010e8: 60bb str r3, [r7, #8] + 80010ea: 60fa str r2, [r7, #12] + 80010ec: f04f 0200 mov.w r2, #0 + 80010f0: f04f 0300 mov.w r3, #0 + 80010f4: 68b9 ldr r1, [r7, #8] + 80010f6: 000b movs r3, r1 + 80010f8: 2200 movs r2, #0 + 80010fa: 6ab9 ldr r1, [r7, #40] @ 0x28 + 80010fc: 2000 movs r0, #0 + 80010fe: 460c mov r4, r1 + 8001100: 4605 mov r5, r0 + 8001102: eb12 0804 adds.w r8, r2, r4 + 8001106: eb43 0905 adc.w r9, r3, r5 + 800110a: e9c7 8906 strd r8, r9, [r7, #24] + + seconds = (uint32_t)(ticks >> RTC_N_PREDIV_S); + 800110e: e9d7 0106 ldrd r0, r1, [r7, #24] + 8001112: f04f 0200 mov.w r2, #0 + 8001116: f04f 0300 mov.w r3, #0 + 800111a: 0a82 lsrs r2, r0, #10 + 800111c: ea42 5281 orr.w r2, r2, r1, lsl #22 + 8001120: 0a8b lsrs r3, r1, #10 + 8001122: 4613 mov r3, r2 + 8001124: 62fb str r3, [r7, #44] @ 0x2c + + ticks = (uint32_t) ticks & RTC_PREDIV_S; + 8001126: 69bb ldr r3, [r7, #24] + 8001128: 2200 movs r2, #0 + 800112a: 603b str r3, [r7, #0] + 800112c: 607a str r2, [r7, #4] + 800112e: 683b ldr r3, [r7, #0] + 8001130: f3c3 0a09 ubfx sl, r3, #0, #10 + 8001134: f04f 0b00 mov.w fp, #0 + 8001138: e9c7 ab06 strd sl, fp, [r7, #24] + + *mSeconds = TIMER_IF_Convert_Tick2ms(ticks); + 800113c: 69bb ldr r3, [r7, #24] + 800113e: 4618 mov r0, r3 + 8001140: f7ff ff46 bl 8000fd0 + 8001144: 4603 mov r3, r0 + 8001146: b29a uxth r2, r3 + 8001148: 697b ldr r3, [r7, #20] + 800114a: 801a strh r2, [r3, #0] + + /* USER CODE BEGIN TIMER_IF_GetTime_Last */ + + /* USER CODE END TIMER_IF_GetTime_Last */ + return seconds; + 800114c: 6afb ldr r3, [r7, #44] @ 0x2c +} + 800114e: 4618 mov r0, r3 + 8001150: 3730 adds r7, #48 @ 0x30 + 8001152: 46bd mov sp, r7 + 8001154: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc} + +08001158 : + +void TIMER_IF_BkUp_Write_Seconds(uint32_t Seconds) +{ + 8001158: b580 push {r7, lr} + 800115a: b082 sub sp, #8 + 800115c: af00 add r7, sp, #0 + 800115e: 6078 str r0, [r7, #4] + /* USER CODE BEGIN TIMER_IF_BkUp_Write_Seconds */ + + /* USER CODE END TIMER_IF_BkUp_Write_Seconds */ + HAL_RTCEx_BKUPWrite(&hrtc, RTC_BKP_SECONDS, Seconds); + 8001160: 687a ldr r2, [r7, #4] + 8001162: 2100 movs r1, #0 + 8001164: 4803 ldr r0, [pc, #12] @ (8001174 ) + 8001166: f003 fb05 bl 8004774 + /* USER CODE BEGIN TIMER_IF_BkUp_Write_Seconds_Last */ + + /* USER CODE END TIMER_IF_BkUp_Write_Seconds_Last */ +} + 800116a: bf00 nop + 800116c: 3708 adds r7, #8 + 800116e: 46bd mov sp, r7 + 8001170: bd80 pop {r7, pc} + 8001172: bf00 nop + 8001174: 200000a8 .word 0x200000a8 + +08001178 : + +void TIMER_IF_BkUp_Write_SubSeconds(uint32_t SubSeconds) +{ + 8001178: b580 push {r7, lr} + 800117a: b082 sub sp, #8 + 800117c: af00 add r7, sp, #0 + 800117e: 6078 str r0, [r7, #4] + /* USER CODE BEGIN TIMER_IF_BkUp_Write_SubSeconds */ + + /* USER CODE END TIMER_IF_BkUp_Write_SubSeconds */ + HAL_RTCEx_BKUPWrite(&hrtc, RTC_BKP_SUBSECONDS, SubSeconds); + 8001180: 687a ldr r2, [r7, #4] + 8001182: 2101 movs r1, #1 + 8001184: 4803 ldr r0, [pc, #12] @ (8001194 ) + 8001186: f003 faf5 bl 8004774 + /* USER CODE BEGIN TIMER_IF_BkUp_Write_SubSeconds_Last */ + + /* USER CODE END TIMER_IF_BkUp_Write_SubSeconds_Last */ +} + 800118a: bf00 nop + 800118c: 3708 adds r7, #8 + 800118e: 46bd mov sp, r7 + 8001190: bd80 pop {r7, pc} + 8001192: bf00 nop + 8001194: 200000a8 .word 0x200000a8 + +08001198 : + +uint32_t TIMER_IF_BkUp_Read_Seconds(void) +{ + 8001198: b580 push {r7, lr} + 800119a: b082 sub sp, #8 + 800119c: af00 add r7, sp, #0 + uint32_t ret = 0; + 800119e: 2300 movs r3, #0 + 80011a0: 607b str r3, [r7, #4] + /* USER CODE BEGIN TIMER_IF_BkUp_Read_Seconds */ + + /* USER CODE END TIMER_IF_BkUp_Read_Seconds */ + ret = HAL_RTCEx_BKUPRead(&hrtc, RTC_BKP_SECONDS); + 80011a2: 2100 movs r1, #0 + 80011a4: 4804 ldr r0, [pc, #16] @ (80011b8 ) + 80011a6: f003 fafd bl 80047a4 + 80011aa: 6078 str r0, [r7, #4] + /* USER CODE BEGIN TIMER_IF_BkUp_Read_Seconds_Last */ + + /* USER CODE END TIMER_IF_BkUp_Read_Seconds_Last */ + return ret; + 80011ac: 687b ldr r3, [r7, #4] +} + 80011ae: 4618 mov r0, r3 + 80011b0: 3708 adds r7, #8 + 80011b2: 46bd mov sp, r7 + 80011b4: bd80 pop {r7, pc} + 80011b6: bf00 nop + 80011b8: 200000a8 .word 0x200000a8 + +080011bc : + +uint32_t TIMER_IF_BkUp_Read_SubSeconds(void) +{ + 80011bc: b580 push {r7, lr} + 80011be: b082 sub sp, #8 + 80011c0: af00 add r7, sp, #0 + uint32_t ret = 0; + 80011c2: 2300 movs r3, #0 + 80011c4: 607b str r3, [r7, #4] + /* USER CODE BEGIN TIMER_IF_BkUp_Read_SubSeconds */ + + /* USER CODE END TIMER_IF_BkUp_Read_SubSeconds */ + ret = HAL_RTCEx_BKUPRead(&hrtc, RTC_BKP_SUBSECONDS); + 80011c6: 2101 movs r1, #1 + 80011c8: 4804 ldr r0, [pc, #16] @ (80011dc ) + 80011ca: f003 faeb bl 80047a4 + 80011ce: 6078 str r0, [r7, #4] + /* USER CODE BEGIN TIMER_IF_BkUp_Read_SubSeconds_Last */ + + /* USER CODE END TIMER_IF_BkUp_Read_SubSeconds_Last */ + return ret; + 80011d0: 687b ldr r3, [r7, #4] +} + 80011d2: 4618 mov r0, r3 + 80011d4: 3708 adds r7, #8 + 80011d6: 46bd mov sp, r7 + 80011d8: bd80 pop {r7, pc} + 80011da: bf00 nop + 80011dc: 200000a8 .word 0x200000a8 + +080011e0 : + +/* USER CODE END EF */ + +/* Private functions ---------------------------------------------------------*/ +static void TIMER_IF_BkUp_Write_MSBticks(uint32_t MSBticks) +{ + 80011e0: b580 push {r7, lr} + 80011e2: b082 sub sp, #8 + 80011e4: af00 add r7, sp, #0 + 80011e6: 6078 str r0, [r7, #4] + /* USER CODE BEGIN TIMER_IF_BkUp_Write_MSBticks */ + + /* USER CODE END TIMER_IF_BkUp_Write_MSBticks */ + HAL_RTCEx_BKUPWrite(&hrtc, RTC_BKP_MSBTICKS, MSBticks); + 80011e8: 687a ldr r2, [r7, #4] + 80011ea: 2102 movs r1, #2 + 80011ec: 4803 ldr r0, [pc, #12] @ (80011fc ) + 80011ee: f003 fac1 bl 8004774 + /* USER CODE BEGIN TIMER_IF_BkUp_Write_MSBticks_Last */ + + /* USER CODE END TIMER_IF_BkUp_Write_MSBticks_Last */ +} + 80011f2: bf00 nop + 80011f4: 3708 adds r7, #8 + 80011f6: 46bd mov sp, r7 + 80011f8: bd80 pop {r7, pc} + 80011fa: bf00 nop + 80011fc: 200000a8 .word 0x200000a8 + +08001200 : + +static uint32_t TIMER_IF_BkUp_Read_MSBticks(void) +{ + 8001200: b580 push {r7, lr} + 8001202: b082 sub sp, #8 + 8001204: af00 add r7, sp, #0 + /* USER CODE BEGIN TIMER_IF_BkUp_Read_MSBticks */ + + /* USER CODE END TIMER_IF_BkUp_Read_MSBticks */ + uint32_t MSBticks; + MSBticks = HAL_RTCEx_BKUPRead(&hrtc, RTC_BKP_MSBTICKS); + 8001206: 2102 movs r1, #2 + 8001208: 4804 ldr r0, [pc, #16] @ (800121c ) + 800120a: f003 facb bl 80047a4 + 800120e: 6078 str r0, [r7, #4] + return MSBticks; + 8001210: 687b ldr r3, [r7, #4] + /* USER CODE BEGIN TIMER_IF_BkUp_Read_MSBticks_Last */ + + /* USER CODE END TIMER_IF_BkUp_Read_MSBticks_Last */ +} + 8001212: 4618 mov r0, r3 + 8001214: 3708 adds r7, #8 + 8001216: 46bd mov sp, r7 + 8001218: bd80 pop {r7, pc} + 800121a: bf00 nop + 800121c: 200000a8 .word 0x200000a8 + +08001220 : + +static inline uint32_t GetTimerTicks(void) +{ + 8001220: b580 push {r7, lr} + 8001222: b082 sub sp, #8 + 8001224: af00 add r7, sp, #0 + /* USER CODE BEGIN GetTimerTicks */ + + /* USER CODE END GetTimerTicks */ + uint32_t ssr = LL_RTC_TIME_GetSubSecond(RTC); + 8001226: 480b ldr r0, [pc, #44] @ (8001254 ) + 8001228: f7ff fdd8 bl 8000ddc + 800122c: 6078 str r0, [r7, #4] + /* read twice to make sure value it valid*/ + while (ssr != LL_RTC_TIME_GetSubSecond(RTC)) + 800122e: e003 b.n 8001238 + { + ssr = LL_RTC_TIME_GetSubSecond(RTC); + 8001230: 4808 ldr r0, [pc, #32] @ (8001254 ) + 8001232: f7ff fdd3 bl 8000ddc + 8001236: 6078 str r0, [r7, #4] + while (ssr != LL_RTC_TIME_GetSubSecond(RTC)) + 8001238: 4806 ldr r0, [pc, #24] @ (8001254 ) + 800123a: f7ff fdcf bl 8000ddc + 800123e: 4602 mov r2, r0 + 8001240: 687b ldr r3, [r7, #4] + 8001242: 4293 cmp r3, r2 + 8001244: d1f4 bne.n 8001230 + } + return UINT32_MAX - ssr; + 8001246: 687b ldr r3, [r7, #4] + 8001248: 43db mvns r3, r3 + /* USER CODE BEGIN GetTimerTicks_Last */ + + /* USER CODE END GetTimerTicks_Last */ +} + 800124a: 4618 mov r0, r3 + 800124c: 3708 adds r7, #8 + 800124e: 46bd mov sp, r7 + 8001250: bd80 pop {r7, pc} + 8001252: bf00 nop + 8001254: 40002800 .word 0x40002800 + +08001258 : +{ + 8001258: b480 push {r7} + 800125a: b085 sub sp, #20 + 800125c: af00 add r7, sp, #0 + 800125e: 6078 str r0, [r7, #4] + SET_BIT(RCC->AHB2ENR, Periphs); + 8001260: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8001264: 6cda ldr r2, [r3, #76] @ 0x4c + 8001266: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 800126a: 687b ldr r3, [r7, #4] + 800126c: 4313 orrs r3, r2 + 800126e: 64cb str r3, [r1, #76] @ 0x4c + tmpreg = READ_BIT(RCC->AHB2ENR, Periphs); + 8001270: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8001274: 6cda ldr r2, [r3, #76] @ 0x4c + 8001276: 687b ldr r3, [r7, #4] + 8001278: 4013 ands r3, r2 + 800127a: 60fb str r3, [r7, #12] + (void)tmpreg; + 800127c: 68fb ldr r3, [r7, #12] +} + 800127e: bf00 nop + 8001280: 3714 adds r7, #20 + 8001282: 46bd mov sp, r7 + 8001284: bc80 pop {r7} + 8001286: 4770 bx lr + +08001288 : +{ + 8001288: b480 push {r7} + 800128a: b085 sub sp, #20 + 800128c: af00 add r7, sp, #0 + 800128e: 6078 str r0, [r7, #4] + SET_BIT(RCC->APB1ENR1, Periphs); + 8001290: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8001294: 6d9a ldr r2, [r3, #88] @ 0x58 + 8001296: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 800129a: 687b ldr r3, [r7, #4] + 800129c: 4313 orrs r3, r2 + 800129e: 658b str r3, [r1, #88] @ 0x58 + tmpreg = READ_BIT(RCC->APB1ENR1, Periphs); + 80012a0: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 80012a4: 6d9a ldr r2, [r3, #88] @ 0x58 + 80012a6: 687b ldr r3, [r7, #4] + 80012a8: 4013 ands r3, r2 + 80012aa: 60fb str r3, [r7, #12] + (void)tmpreg; + 80012ac: 68fb ldr r3, [r7, #12] +} + 80012ae: bf00 nop + 80012b0: 3714 adds r7, #20 + 80012b2: 46bd mov sp, r7 + 80012b4: bc80 pop {r7} + 80012b6: 4770 bx lr + +080012b8 : +{ + 80012b8: b480 push {r7} + 80012ba: b083 sub sp, #12 + 80012bc: af00 add r7, sp, #0 + 80012be: 6078 str r0, [r7, #4] + CLEAR_BIT(RCC->APB1ENR1, Periphs); + 80012c0: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 80012c4: 6d9a ldr r2, [r3, #88] @ 0x58 + 80012c6: 687b ldr r3, [r7, #4] + 80012c8: 43db mvns r3, r3 + 80012ca: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 80012ce: 4013 ands r3, r2 + 80012d0: 658b str r3, [r1, #88] @ 0x58 +} + 80012d2: bf00 nop + 80012d4: 370c adds r7, #12 + 80012d6: 46bd mov sp, r7 + 80012d8: bc80 pop {r7} + 80012da: 4770 bx lr + +080012dc : +DMA_HandleTypeDef hdma_usart2_tx; + +/* USART2 init function */ + +void MX_USART2_UART_Init(void) +{ + 80012dc: b580 push {r7, lr} + 80012de: af00 add r7, sp, #0 + /* USER CODE END USART2_Init 0 */ + + /* USER CODE BEGIN USART2_Init 1 */ + + /* USER CODE END USART2_Init 1 */ + huart2.Instance = USART2; + 80012e0: 4b22 ldr r3, [pc, #136] @ (800136c ) + 80012e2: 4a23 ldr r2, [pc, #140] @ (8001370 ) + 80012e4: 601a str r2, [r3, #0] + huart2.Init.BaudRate = 115200; + 80012e6: 4b21 ldr r3, [pc, #132] @ (800136c ) + 80012e8: f44f 32e1 mov.w r2, #115200 @ 0x1c200 + 80012ec: 605a str r2, [r3, #4] + huart2.Init.WordLength = UART_WORDLENGTH_8B; + 80012ee: 4b1f ldr r3, [pc, #124] @ (800136c ) + 80012f0: 2200 movs r2, #0 + 80012f2: 609a str r2, [r3, #8] + huart2.Init.StopBits = UART_STOPBITS_1; + 80012f4: 4b1d ldr r3, [pc, #116] @ (800136c ) + 80012f6: 2200 movs r2, #0 + 80012f8: 60da str r2, [r3, #12] + huart2.Init.Parity = UART_PARITY_NONE; + 80012fa: 4b1c ldr r3, [pc, #112] @ (800136c ) + 80012fc: 2200 movs r2, #0 + 80012fe: 611a str r2, [r3, #16] + huart2.Init.Mode = UART_MODE_TX_RX; + 8001300: 4b1a ldr r3, [pc, #104] @ (800136c ) + 8001302: 220c movs r2, #12 + 8001304: 615a str r2, [r3, #20] + huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE; + 8001306: 4b19 ldr r3, [pc, #100] @ (800136c ) + 8001308: 2200 movs r2, #0 + 800130a: 619a str r2, [r3, #24] + huart2.Init.OverSampling = UART_OVERSAMPLING_16; + 800130c: 4b17 ldr r3, [pc, #92] @ (800136c ) + 800130e: 2200 movs r2, #0 + 8001310: 61da str r2, [r3, #28] + huart2.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; + 8001312: 4b16 ldr r3, [pc, #88] @ (800136c ) + 8001314: 2200 movs r2, #0 + 8001316: 621a str r2, [r3, #32] + huart2.Init.ClockPrescaler = UART_PRESCALER_DIV1; + 8001318: 4b14 ldr r3, [pc, #80] @ (800136c ) + 800131a: 2200 movs r2, #0 + 800131c: 625a str r2, [r3, #36] @ 0x24 + huart2.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; + 800131e: 4b13 ldr r3, [pc, #76] @ (800136c ) + 8001320: 2200 movs r2, #0 + 8001322: 629a str r2, [r3, #40] @ 0x28 + if (HAL_UART_Init(&huart2) != HAL_OK) + 8001324: 4811 ldr r0, [pc, #68] @ (800136c ) + 8001326: f003 ff40 bl 80051aa + 800132a: 4603 mov r3, r0 + 800132c: 2b00 cmp r3, #0 + 800132e: d001 beq.n 8001334 + { + Error_Handler(); + 8001330: f7ff fa4e bl 80007d0 + } + if (HAL_UARTEx_SetTxFifoThreshold(&huart2, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK) + 8001334: 2100 movs r1, #0 + 8001336: 480d ldr r0, [pc, #52] @ (800136c ) + 8001338: f006 f9bb bl 80076b2 + 800133c: 4603 mov r3, r0 + 800133e: 2b00 cmp r3, #0 + 8001340: d001 beq.n 8001346 + { + Error_Handler(); + 8001342: f7ff fa45 bl 80007d0 + } + if (HAL_UARTEx_SetRxFifoThreshold(&huart2, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK) + 8001346: 2100 movs r1, #0 + 8001348: 4808 ldr r0, [pc, #32] @ (800136c ) + 800134a: f006 f9f0 bl 800772e + 800134e: 4603 mov r3, r0 + 8001350: 2b00 cmp r3, #0 + 8001352: d001 beq.n 8001358 + { + Error_Handler(); + 8001354: f7ff fa3c bl 80007d0 + } + if (HAL_UARTEx_EnableFifoMode(&huart2) != HAL_OK) + 8001358: 4804 ldr r0, [pc, #16] @ (800136c ) + 800135a: f006 f96f bl 800763c + 800135e: 4603 mov r3, r0 + 8001360: 2b00 cmp r3, #0 + 8001362: d001 beq.n 8001368 + { + Error_Handler(); + 8001364: f7ff fa34 bl 80007d0 + } + /* USER CODE BEGIN USART2_Init 2 */ + + /* USER CODE END USART2_Init 2 */ + +} + 8001368: bf00 nop + 800136a: bd80 pop {r7, pc} + 800136c: 200000fc .word 0x200000fc + 8001370: 40004400 .word 0x40004400 + +08001374 : + +void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle) +{ + 8001374: b580 push {r7, lr} + 8001376: b096 sub sp, #88 @ 0x58 + 8001378: af00 add r7, sp, #0 + 800137a: 6078 str r0, [r7, #4] + + GPIO_InitTypeDef GPIO_InitStruct = {0}; + 800137c: f107 0344 add.w r3, r7, #68 @ 0x44 + 8001380: 2200 movs r2, #0 + 8001382: 601a str r2, [r3, #0] + 8001384: 605a str r2, [r3, #4] + 8001386: 609a str r2, [r3, #8] + 8001388: 60da str r2, [r3, #12] + 800138a: 611a str r2, [r3, #16] + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; + 800138c: f107 030c add.w r3, r7, #12 + 8001390: 2238 movs r2, #56 @ 0x38 + 8001392: 2100 movs r1, #0 + 8001394: 4618 mov r0, r3 + 8001396: f00d f9f7 bl 800e788 + if(uartHandle->Instance==USART2) + 800139a: 687b ldr r3, [r7, #4] + 800139c: 681b ldr r3, [r3, #0] + 800139e: 4a33 ldr r2, [pc, #204] @ (800146c ) + 80013a0: 4293 cmp r3, r2 + 80013a2: d15f bne.n 8001464 + + /* USER CODE END USART2_MspInit 0 */ + + /** Initializes the peripherals clocks + */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USART2; + 80013a4: 2302 movs r3, #2 + 80013a6: 60fb str r3, [r7, #12] + PeriphClkInitStruct.Usart2ClockSelection = RCC_USART2CLKSOURCE_SYSCLK; + 80013a8: 4b31 ldr r3, [pc, #196] @ (8001470 ) + 80013aa: 617b str r3, [r7, #20] + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) + 80013ac: f107 030c add.w r3, r7, #12 + 80013b0: 4618 mov r0, r3 + 80013b2: f002 fd5d bl 8003e70 + 80013b6: 4603 mov r3, r0 + 80013b8: 2b00 cmp r3, #0 + 80013ba: d001 beq.n 80013c0 + { + Error_Handler(); + 80013bc: f7ff fa08 bl 80007d0 + } + + /* USART2 clock enable */ + __HAL_RCC_USART2_CLK_ENABLE(); + 80013c0: f44f 3000 mov.w r0, #131072 @ 0x20000 + 80013c4: f7ff ff60 bl 8001288 + + __HAL_RCC_GPIOA_CLK_ENABLE(); + 80013c8: 2001 movs r0, #1 + 80013ca: f7ff ff45 bl 8001258 + /**USART2 GPIO Configuration + PA3 ------> USART2_RX + PA2 ------> USART2_TX + */ + GPIO_InitStruct.Pin = USARTx_RX_Pin|USARTx_TX_Pin; + 80013ce: 230c movs r3, #12 + 80013d0: 647b str r3, [r7, #68] @ 0x44 + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 80013d2: 2302 movs r3, #2 + 80013d4: 64bb str r3, [r7, #72] @ 0x48 + GPIO_InitStruct.Pull = GPIO_NOPULL; + 80013d6: 2300 movs r3, #0 + 80013d8: 64fb str r3, [r7, #76] @ 0x4c + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + 80013da: 2303 movs r3, #3 + 80013dc: 653b str r3, [r7, #80] @ 0x50 + GPIO_InitStruct.Alternate = GPIO_AF7_USART2; + 80013de: 2307 movs r3, #7 + 80013e0: 657b str r3, [r7, #84] @ 0x54 + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 80013e2: f107 0344 add.w r3, r7, #68 @ 0x44 + 80013e6: 4619 mov r1, r3 + 80013e8: f04f 4090 mov.w r0, #1207959552 @ 0x48000000 + 80013ec: f001 f822 bl 8002434 + + /* USART2 DMA Init */ + /* USART2_TX Init */ + hdma_usart2_tx.Instance = DMA1_Channel5; + 80013f0: 4b20 ldr r3, [pc, #128] @ (8001474 ) + 80013f2: 4a21 ldr r2, [pc, #132] @ (8001478 ) + 80013f4: 601a str r2, [r3, #0] + hdma_usart2_tx.Init.Request = DMA_REQUEST_USART2_TX; + 80013f6: 4b1f ldr r3, [pc, #124] @ (8001474 ) + 80013f8: 2214 movs r2, #20 + 80013fa: 605a str r2, [r3, #4] + hdma_usart2_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; + 80013fc: 4b1d ldr r3, [pc, #116] @ (8001474 ) + 80013fe: 2210 movs r2, #16 + 8001400: 609a str r2, [r3, #8] + hdma_usart2_tx.Init.PeriphInc = DMA_PINC_DISABLE; + 8001402: 4b1c ldr r3, [pc, #112] @ (8001474 ) + 8001404: 2200 movs r2, #0 + 8001406: 60da str r2, [r3, #12] + hdma_usart2_tx.Init.MemInc = DMA_MINC_ENABLE; + 8001408: 4b1a ldr r3, [pc, #104] @ (8001474 ) + 800140a: 2280 movs r2, #128 @ 0x80 + 800140c: 611a str r2, [r3, #16] + hdma_usart2_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; + 800140e: 4b19 ldr r3, [pc, #100] @ (8001474 ) + 8001410: 2200 movs r2, #0 + 8001412: 615a str r2, [r3, #20] + hdma_usart2_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; + 8001414: 4b17 ldr r3, [pc, #92] @ (8001474 ) + 8001416: 2200 movs r2, #0 + 8001418: 619a str r2, [r3, #24] + hdma_usart2_tx.Init.Mode = DMA_NORMAL; + 800141a: 4b16 ldr r3, [pc, #88] @ (8001474 ) + 800141c: 2200 movs r2, #0 + 800141e: 61da str r2, [r3, #28] + hdma_usart2_tx.Init.Priority = DMA_PRIORITY_LOW; + 8001420: 4b14 ldr r3, [pc, #80] @ (8001474 ) + 8001422: 2200 movs r2, #0 + 8001424: 621a str r2, [r3, #32] + if (HAL_DMA_Init(&hdma_usart2_tx) != HAL_OK) + 8001426: 4813 ldr r0, [pc, #76] @ (8001474 ) + 8001428: f000 fbe0 bl 8001bec + 800142c: 4603 mov r3, r0 + 800142e: 2b00 cmp r3, #0 + 8001430: d001 beq.n 8001436 + { + Error_Handler(); + 8001432: f7ff f9cd bl 80007d0 + } + + if (HAL_DMA_ConfigChannelAttributes(&hdma_usart2_tx, DMA_CHANNEL_NPRIV) != HAL_OK) + 8001436: 2110 movs r1, #16 + 8001438: 480e ldr r0, [pc, #56] @ (8001474 ) + 800143a: f000 ff22 bl 8002282 + 800143e: 4603 mov r3, r0 + 8001440: 2b00 cmp r3, #0 + 8001442: d001 beq.n 8001448 + { + Error_Handler(); + 8001444: f7ff f9c4 bl 80007d0 + } + + __HAL_LINKDMA(uartHandle,hdmatx,hdma_usart2_tx); + 8001448: 687b ldr r3, [r7, #4] + 800144a: 4a0a ldr r2, [pc, #40] @ (8001474 ) + 800144c: 67da str r2, [r3, #124] @ 0x7c + 800144e: 4a09 ldr r2, [pc, #36] @ (8001474 ) + 8001450: 687b ldr r3, [r7, #4] + 8001452: 6293 str r3, [r2, #40] @ 0x28 + + /* USART2 interrupt Init */ + HAL_NVIC_SetPriority(USART2_IRQn, 2, 0); + 8001454: 2200 movs r2, #0 + 8001456: 2102 movs r1, #2 + 8001458: 2025 movs r0, #37 @ 0x25 + 800145a: f000 fb90 bl 8001b7e + HAL_NVIC_EnableIRQ(USART2_IRQn); + 800145e: 2025 movs r0, #37 @ 0x25 + 8001460: f000 fba7 bl 8001bb2 + /* USER CODE BEGIN USART2_MspInit 1 */ + + /* USER CODE END USART2_MspInit 1 */ + } +} + 8001464: bf00 nop + 8001466: 3758 adds r7, #88 @ 0x58 + 8001468: 46bd mov sp, r7 + 800146a: bd80 pop {r7, pc} + 800146c: 40004400 .word 0x40004400 + 8001470: 000c0004 .word 0x000c0004 + 8001474: 20000190 .word 0x20000190 + 8001478: 40020058 .word 0x40020058 + +0800147c : + +void HAL_UART_MspDeInit(UART_HandleTypeDef* uartHandle) +{ + 800147c: b580 push {r7, lr} + 800147e: b082 sub sp, #8 + 8001480: af00 add r7, sp, #0 + 8001482: 6078 str r0, [r7, #4] + + if(uartHandle->Instance==USART2) + 8001484: 687b ldr r3, [r7, #4] + 8001486: 681b ldr r3, [r3, #0] + 8001488: 4a0b ldr r2, [pc, #44] @ (80014b8 ) + 800148a: 4293 cmp r3, r2 + 800148c: d110 bne.n 80014b0 + { + /* USER CODE BEGIN USART2_MspDeInit 0 */ + + /* USER CODE END USART2_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_USART2_CLK_DISABLE(); + 800148e: f44f 3000 mov.w r0, #131072 @ 0x20000 + 8001492: f7ff ff11 bl 80012b8 + + /**USART2 GPIO Configuration + PA3 ------> USART2_RX + PA2 ------> USART2_TX + */ + HAL_GPIO_DeInit(GPIOA, USARTx_RX_Pin|USARTx_TX_Pin); + 8001496: 210c movs r1, #12 + 8001498: f04f 4090 mov.w r0, #1207959552 @ 0x48000000 + 800149c: f001 f92a bl 80026f4 + + /* USART2 DMA DeInit */ + HAL_DMA_DeInit(uartHandle->hdmatx); + 80014a0: 687b ldr r3, [r7, #4] + 80014a2: 6fdb ldr r3, [r3, #124] @ 0x7c + 80014a4: 4618 mov r0, r3 + 80014a6: f000 fc49 bl 8001d3c + + /* USART2 interrupt Deinit */ + HAL_NVIC_DisableIRQ(USART2_IRQn); + 80014aa: 2025 movs r0, #37 @ 0x25 + 80014ac: f000 fb8f bl 8001bce + /* USER CODE BEGIN USART2_MspDeInit 1 */ + + /* USER CODE END USART2_MspDeInit 1 */ + } +} + 80014b0: bf00 nop + 80014b2: 3708 adds r7, #8 + 80014b4: 46bd mov sp, r7 + 80014b6: bd80 pop {r7, pc} + 80014b8: 40004400 .word 0x40004400 + +080014bc : +{ + 80014bc: b480 push {r7} + 80014be: b083 sub sp, #12 + 80014c0: af00 add r7, sp, #0 + 80014c2: 6078 str r0, [r7, #4] + SET_BIT(RCC->APB1RSTR1, Periphs); + 80014c4: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 80014c8: 6b9a ldr r2, [r3, #56] @ 0x38 + 80014ca: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 80014ce: 687b ldr r3, [r7, #4] + 80014d0: 4313 orrs r3, r2 + 80014d2: 638b str r3, [r1, #56] @ 0x38 +} + 80014d4: bf00 nop + 80014d6: 370c adds r7, #12 + 80014d8: 46bd mov sp, r7 + 80014da: bc80 pop {r7} + 80014dc: 4770 bx lr + +080014de : +{ + 80014de: b480 push {r7} + 80014e0: b083 sub sp, #12 + 80014e2: af00 add r7, sp, #0 + 80014e4: 6078 str r0, [r7, #4] + CLEAR_BIT(RCC->APB1RSTR1, Periphs); + 80014e6: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 80014ea: 6b9a ldr r2, [r3, #56] @ 0x38 + 80014ec: 687b ldr r3, [r7, #4] + 80014ee: 43db mvns r3, r3 + 80014f0: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 80014f4: 4013 ands r3, r2 + 80014f6: 638b str r3, [r1, #56] @ 0x38 +} + 80014f8: bf00 nop + 80014fa: 370c adds r7, #12 + 80014fc: 46bd mov sp, r7 + 80014fe: bc80 pop {r7} + 8001500: 4770 bx lr + ... + +08001504 : +{ + 8001504: b480 push {r7} + 8001506: b083 sub sp, #12 + 8001508: af00 add r7, sp, #0 + 800150a: 6078 str r0, [r7, #4] + SET_BIT(EXTI->IMR1, ExtiLine); + 800150c: 4b06 ldr r3, [pc, #24] @ (8001528 ) + 800150e: f8d3 2080 ldr.w r2, [r3, #128] @ 0x80 + 8001512: 4905 ldr r1, [pc, #20] @ (8001528 ) + 8001514: 687b ldr r3, [r7, #4] + 8001516: 4313 orrs r3, r2 + 8001518: f8c1 3080 str.w r3, [r1, #128] @ 0x80 +} + 800151c: bf00 nop + 800151e: 370c adds r7, #12 + 8001520: 46bd mov sp, r7 + 8001522: bc80 pop {r7} + 8001524: 4770 bx lr + 8001526: bf00 nop + 8001528: 58000800 .word 0x58000800 + +0800152c : +/* USER CODE END PFP */ + +/* Exported functions --------------------------------------------------------*/ + +UTIL_ADV_TRACE_Status_t vcom_Init(void (*cb)(void *)) +{ + 800152c: b580 push {r7, lr} + 800152e: b082 sub sp, #8 + 8001530: af00 add r7, sp, #0 + 8001532: 6078 str r0, [r7, #4] + /* USER CODE BEGIN vcom_Init_1 */ + + /* USER CODE END vcom_Init_1 */ + TxCpltCallback = cb; + 8001534: 4a07 ldr r2, [pc, #28] @ (8001554 ) + 8001536: 687b ldr r3, [r7, #4] + 8001538: 6013 str r3, [r2, #0] + MX_DMA_Init(); + 800153a: f7ff f837 bl 80005ac + MX_USART2_UART_Init(); + 800153e: f7ff fecd bl 80012dc + LL_EXTI_EnableIT_0_31(LL_EXTI_LINE_27); + 8001542: f04f 6000 mov.w r0, #134217728 @ 0x8000000 + 8001546: f7ff ffdd bl 8001504 + return UTIL_ADV_TRACE_OK; + 800154a: 2300 movs r3, #0 + /* USER CODE BEGIN vcom_Init_2 */ + + /* USER CODE END vcom_Init_2 */ +} + 800154c: 4618 mov r0, r3 + 800154e: 3708 adds r7, #8 + 8001550: 46bd mov sp, r7 + 8001552: bd80 pop {r7, pc} + 8001554: 200001f4 .word 0x200001f4 + +08001558 : + +UTIL_ADV_TRACE_Status_t vcom_DeInit(void) +{ + 8001558: b580 push {r7, lr} + 800155a: af00 add r7, sp, #0 + /* USER CODE BEGIN vcom_DeInit_1 */ + + /* USER CODE END vcom_DeInit_1 */ + /* ##-1- Reset peripherals ################################################## */ + __HAL_RCC_USART2_FORCE_RESET(); + 800155c: f44f 3000 mov.w r0, #131072 @ 0x20000 + 8001560: f7ff ffac bl 80014bc + __HAL_RCC_USART2_RELEASE_RESET(); + 8001564: f44f 3000 mov.w r0, #131072 @ 0x20000 + 8001568: f7ff ffb9 bl 80014de + + /* ##-2- MspDeInit ################################################## */ + HAL_UART_MspDeInit(&huart2); + 800156c: 4804 ldr r0, [pc, #16] @ (8001580 ) + 800156e: f7ff ff85 bl 800147c + + /* ##-3- Disable the NVIC for DMA ########################################### */ + /* USER CODE BEGIN 1 */ + HAL_NVIC_DisableIRQ(DMA1_Channel5_IRQn); + 8001572: 200f movs r0, #15 + 8001574: f000 fb2b bl 8001bce + + return UTIL_ADV_TRACE_OK; + 8001578: 2300 movs r3, #0 + /* USER CODE END 1 */ + /* USER CODE BEGIN vcom_DeInit_2 */ + + /* USER CODE END vcom_DeInit_2 */ +} + 800157a: 4618 mov r0, r3 + 800157c: bd80 pop {r7, pc} + 800157e: bf00 nop + 8001580: 200000fc .word 0x200000fc + +08001584 : + + /* USER CODE END vcom_Trace_2 */ +} + +UTIL_ADV_TRACE_Status_t vcom_Trace_DMA(uint8_t *p_data, uint16_t size) +{ + 8001584: b580 push {r7, lr} + 8001586: b082 sub sp, #8 + 8001588: af00 add r7, sp, #0 + 800158a: 6078 str r0, [r7, #4] + 800158c: 460b mov r3, r1 + 800158e: 807b strh r3, [r7, #2] + /* USER CODE BEGIN vcom_Trace_DMA_1 */ + + /* USER CODE END vcom_Trace_DMA_1 */ + HAL_UART_Transmit_DMA(&huart2, p_data, size); + 8001590: 887b ldrh r3, [r7, #2] + 8001592: 461a mov r2, r3 + 8001594: 6879 ldr r1, [r7, #4] + 8001596: 4804 ldr r0, [pc, #16] @ (80015a8 ) + 8001598: f003 ff3c bl 8005414 + return UTIL_ADV_TRACE_OK; + 800159c: 2300 movs r3, #0 + /* USER CODE BEGIN vcom_Trace_DMA_2 */ + + /* USER CODE END vcom_Trace_DMA_2 */ +} + 800159e: 4618 mov r0, r3 + 80015a0: 3708 adds r7, #8 + 80015a2: 46bd mov sp, r7 + 80015a4: bd80 pop {r7, pc} + 80015a6: bf00 nop + 80015a8: 200000fc .word 0x200000fc + +080015ac : + +UTIL_ADV_TRACE_Status_t vcom_ReceiveInit(void (*RxCb)(uint8_t *rxChar, uint16_t size, uint8_t error)) +{ + 80015ac: b580 push {r7, lr} + 80015ae: b084 sub sp, #16 + 80015b0: af00 add r7, sp, #0 + 80015b2: 6078 str r0, [r7, #4] + + /* USER CODE END vcom_ReceiveInit_1 */ + UART_WakeUpTypeDef WakeUpSelection; + + /*record call back*/ + RxCpltCallback = RxCb; + 80015b4: 4a19 ldr r2, [pc, #100] @ (800161c ) + 80015b6: 687b ldr r3, [r7, #4] + 80015b8: 6013 str r3, [r2, #0] + + /*Set wakeUp event on start bit*/ + WakeUpSelection.WakeUpEvent = UART_WAKEUP_ON_STARTBIT; + 80015ba: f44f 1300 mov.w r3, #2097152 @ 0x200000 + 80015be: 60bb str r3, [r7, #8] + + HAL_UARTEx_StopModeWakeUpSourceConfig(&huart2, WakeUpSelection); + 80015c0: f107 0308 add.w r3, r7, #8 + 80015c4: e893 0006 ldmia.w r3, {r1, r2} + 80015c8: 4815 ldr r0, [pc, #84] @ (8001620 ) + 80015ca: f005 ffaa bl 8007522 + + /* Make sure that no UART transfer is on-going */ + while (__HAL_UART_GET_FLAG(&huart2, USART_ISR_BUSY) == SET); + 80015ce: bf00 nop + 80015d0: 4b13 ldr r3, [pc, #76] @ (8001620 ) + 80015d2: 681b ldr r3, [r3, #0] + 80015d4: 69db ldr r3, [r3, #28] + 80015d6: f403 3380 and.w r3, r3, #65536 @ 0x10000 + 80015da: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 + 80015de: d0f7 beq.n 80015d0 + + /* Make sure that UART is ready to receive) */ + while (__HAL_UART_GET_FLAG(&huart2, USART_ISR_REACK) == RESET); + 80015e0: bf00 nop + 80015e2: 4b0f ldr r3, [pc, #60] @ (8001620 ) + 80015e4: 681b ldr r3, [r3, #0] + 80015e6: 69db ldr r3, [r3, #28] + 80015e8: f403 0380 and.w r3, r3, #4194304 @ 0x400000 + 80015ec: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 + 80015f0: d1f7 bne.n 80015e2 + + /* Enable USART interrupt */ + __HAL_UART_ENABLE_IT(&huart2, UART_IT_WUF); + 80015f2: 4b0b ldr r3, [pc, #44] @ (8001620 ) + 80015f4: 681b ldr r3, [r3, #0] + 80015f6: 689a ldr r2, [r3, #8] + 80015f8: 4b09 ldr r3, [pc, #36] @ (8001620 ) + 80015fa: 681b ldr r3, [r3, #0] + 80015fc: f442 0280 orr.w r2, r2, #4194304 @ 0x400000 + 8001600: 609a str r2, [r3, #8] + + /*Enable wakeup from stop mode*/ + HAL_UARTEx_EnableStopMode(&huart2); + 8001602: 4807 ldr r0, [pc, #28] @ (8001620 ) + 8001604: f005 ffe8 bl 80075d8 + + /*Start LPUART receive on IT*/ + HAL_UART_Receive_IT(&huart2, &charRx, 1); + 8001608: 2201 movs r2, #1 + 800160a: 4906 ldr r1, [pc, #24] @ (8001624 ) + 800160c: 4804 ldr r0, [pc, #16] @ (8001620 ) + 800160e: f003 feb5 bl 800537c + + return UTIL_ADV_TRACE_OK; + 8001612: 2300 movs r3, #0 + /* USER CODE BEGIN vcom_ReceiveInit_2 */ + + /* USER CODE END vcom_ReceiveInit_2 */ +} + 8001614: 4618 mov r0, r3 + 8001616: 3710 adds r7, #16 + 8001618: 46bd mov sp, r7 + 800161a: bd80 pop {r7, pc} + 800161c: 200001f8 .word 0x200001f8 + 8001620: 200000fc .word 0x200000fc + 8001624: 200001f0 .word 0x200001f0 + +08001628 : + +void vcom_Resume(void) +{ + 8001628: b580 push {r7, lr} + 800162a: af00 add r7, sp, #0 + /* USER CODE BEGIN vcom_Resume_1 */ + + /* USER CODE END vcom_Resume_1 */ + /*to re-enable lost UART settings*/ + if (HAL_UART_Init(&huart2) != HAL_OK) + 800162c: 4808 ldr r0, [pc, #32] @ (8001650 ) + 800162e: f003 fdbc bl 80051aa + 8001632: 4603 mov r3, r0 + 8001634: 2b00 cmp r3, #0 + 8001636: d001 beq.n 800163c + { + Error_Handler(); + 8001638: f7ff f8ca bl 80007d0 + } + + /*to re-enable lost DMA settings*/ + if (HAL_DMA_Init(&hdma_usart2_tx) != HAL_OK) + 800163c: 4805 ldr r0, [pc, #20] @ (8001654 ) + 800163e: f000 fad5 bl 8001bec + 8001642: 4603 mov r3, r0 + 8001644: 2b00 cmp r3, #0 + 8001646: d001 beq.n 800164c + { + Error_Handler(); + 8001648: f7ff f8c2 bl 80007d0 + } + /* USER CODE BEGIN vcom_Resume_2 */ + + /* USER CODE END vcom_Resume_2 */ +} + 800164c: bf00 nop + 800164e: bd80 pop {r7, pc} + 8001650: 200000fc .word 0x200000fc + 8001654: 20000190 .word 0x20000190 + +08001658 : + +void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) +{ + 8001658: b580 push {r7, lr} + 800165a: b082 sub sp, #8 + 800165c: af00 add r7, sp, #0 + 800165e: 6078 str r0, [r7, #4] + /* USER CODE BEGIN HAL_UART_TxCpltCallback_1 */ + + /* USER CODE END HAL_UART_TxCpltCallback_1 */ + /* buffer transmission complete*/ + if (huart->Instance == USART2) + 8001660: 687b ldr r3, [r7, #4] + 8001662: 681b ldr r3, [r3, #0] + 8001664: 4a05 ldr r2, [pc, #20] @ (800167c ) + 8001666: 4293 cmp r3, r2 + 8001668: d103 bne.n 8001672 + { + TxCpltCallback(NULL); + 800166a: 4b05 ldr r3, [pc, #20] @ (8001680 ) + 800166c: 681b ldr r3, [r3, #0] + 800166e: 2000 movs r0, #0 + 8001670: 4798 blx r3 + } + /* USER CODE BEGIN HAL_UART_TxCpltCallback_2 */ + + /* USER CODE END HAL_UART_TxCpltCallback_2 */ +} + 8001672: bf00 nop + 8001674: 3708 adds r7, #8 + 8001676: 46bd mov sp, r7 + 8001678: bd80 pop {r7, pc} + 800167a: bf00 nop + 800167c: 40004400 .word 0x40004400 + 8001680: 200001f4 .word 0x200001f4 + +08001684 : + +void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) +{ + 8001684: b580 push {r7, lr} + 8001686: b082 sub sp, #8 + 8001688: af00 add r7, sp, #0 + 800168a: 6078 str r0, [r7, #4] + /* USER CODE BEGIN HAL_UART_RxCpltCallback_1 */ + + /* USER CODE END HAL_UART_RxCpltCallback_1 */ + if (huart->Instance == USART2) + 800168c: 687b ldr r3, [r7, #4] + 800168e: 681b ldr r3, [r3, #0] + 8001690: 4a0d ldr r2, [pc, #52] @ (80016c8 ) + 8001692: 4293 cmp r3, r2 + 8001694: d113 bne.n 80016be + { + if ((NULL != RxCpltCallback) && (HAL_UART_ERROR_NONE == huart->ErrorCode)) + 8001696: 4b0d ldr r3, [pc, #52] @ (80016cc ) + 8001698: 681b ldr r3, [r3, #0] + 800169a: 2b00 cmp r3, #0 + 800169c: d00a beq.n 80016b4 + 800169e: 687b ldr r3, [r7, #4] + 80016a0: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 80016a4: 2b00 cmp r3, #0 + 80016a6: d105 bne.n 80016b4 + { + RxCpltCallback(&charRx, 1, 0); + 80016a8: 4b08 ldr r3, [pc, #32] @ (80016cc ) + 80016aa: 681b ldr r3, [r3, #0] + 80016ac: 2200 movs r2, #0 + 80016ae: 2101 movs r1, #1 + 80016b0: 4807 ldr r0, [pc, #28] @ (80016d0 ) + 80016b2: 4798 blx r3 + } + HAL_UART_Receive_IT(huart, &charRx, 1); + 80016b4: 2201 movs r2, #1 + 80016b6: 4906 ldr r1, [pc, #24] @ (80016d0 ) + 80016b8: 6878 ldr r0, [r7, #4] + 80016ba: f003 fe5f bl 800537c + } + /* USER CODE BEGIN HAL_UART_RxCpltCallback_2 */ + + /* USER CODE END HAL_UART_RxCpltCallback_2 */ +} + 80016be: bf00 nop + 80016c0: 3708 adds r7, #8 + 80016c2: 46bd mov sp, r7 + 80016c4: bd80 pop {r7, pc} + 80016c6: bf00 nop + 80016c8: 40004400 .word 0x40004400 + 80016cc: 200001f8 .word 0x200001f8 + 80016d0: 200001f0 .word 0x200001f0 + +080016d4 : + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr r0, =_estack + 80016d4: 480d ldr r0, [pc, #52] @ (800170c ) + mov sp, r0 /* set stack pointer */ + 80016d6: 4685 mov sp, r0 + +/* Call the clock system initialization function.*/ + bl SystemInit + 80016d8: f7ff fb7a bl 8000dd0 + +/* Copy the data segment initializers from flash to SRAM */ + ldr r0, =_sdata + 80016dc: 480c ldr r0, [pc, #48] @ (8001710 ) + ldr r1, =_edata + 80016de: 490d ldr r1, [pc, #52] @ (8001714 ) + ldr r2, =_sidata + 80016e0: 4a0d ldr r2, [pc, #52] @ (8001718 ) + movs r3, #0 + 80016e2: 2300 movs r3, #0 + b LoopCopyDataInit + 80016e4: e002 b.n 80016ec + +080016e6 : + +CopyDataInit: + ldr r4, [r2, r3] + 80016e6: 58d4 ldr r4, [r2, r3] + str r4, [r0, r3] + 80016e8: 50c4 str r4, [r0, r3] + adds r3, r3, #4 + 80016ea: 3304 adds r3, #4 + +080016ec : + +LoopCopyDataInit: + adds r4, r0, r3 + 80016ec: 18c4 adds r4, r0, r3 + cmp r4, r1 + 80016ee: 428c cmp r4, r1 + bcc CopyDataInit + 80016f0: d3f9 bcc.n 80016e6 + +/* Zero fill the bss segment. */ + ldr r2, =_sbss + 80016f2: 4a0a ldr r2, [pc, #40] @ (800171c ) + ldr r4, =_ebss + 80016f4: 4c0a ldr r4, [pc, #40] @ (8001720 ) + movs r3, #0 + 80016f6: 2300 movs r3, #0 + b LoopFillZerobss + 80016f8: e001 b.n 80016fe + +080016fa : + +FillZerobss: + str r3, [r2] + 80016fa: 6013 str r3, [r2, #0] + adds r2, r2, #4 + 80016fc: 3204 adds r2, #4 + +080016fe : + +LoopFillZerobss: + cmp r2, r4 + 80016fe: 42a2 cmp r2, r4 + bcc FillZerobss + 8001700: d3fb bcc.n 80016fa + +/* Call static constructors */ + bl __libc_init_array + 8001702: f00d f861 bl 800e7c8 <__libc_init_array> +/* Call the application's entry point.*/ + bl main + 8001706: f7fe fffe bl 8000706
+ +0800170a : + +LoopForever: + b LoopForever + 800170a: e7fe b.n 800170a + ldr r0, =_estack + 800170c: 20010000 .word 0x20010000 + ldr r0, =_sdata + 8001710: 20000000 .word 0x20000000 + ldr r1, =_edata + 8001714: 2000008c .word 0x2000008c + ldr r2, =_sidata + 8001718: 0800fe10 .word 0x0800fe10 + ldr r2, =_sbss + 800171c: 2000008c .word 0x2000008c + ldr r4, =_ebss + 8001720: 20001068 .word 0x20001068 + +08001724 : + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + 8001724: e7fe b.n 8001724 + +08001726 : +{ + 8001726: b480 push {r7} + 8001728: b085 sub sp, #20 + 800172a: af00 add r7, sp, #0 + 800172c: 6078 str r0, [r7, #4] + SET_BIT(RCC->AHB2ENR, Periphs); + 800172e: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8001732: 6cda ldr r2, [r3, #76] @ 0x4c + 8001734: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 8001738: 687b ldr r3, [r7, #4] + 800173a: 4313 orrs r3, r2 + 800173c: 64cb str r3, [r1, #76] @ 0x4c + tmpreg = READ_BIT(RCC->AHB2ENR, Periphs); + 800173e: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8001742: 6cda ldr r2, [r3, #76] @ 0x4c + 8001744: 687b ldr r3, [r7, #4] + 8001746: 4013 ands r3, r2 + 8001748: 60fb str r3, [r7, #12] + (void)tmpreg; + 800174a: 68fb ldr r3, [r7, #12] +} + 800174c: bf00 nop + 800174e: 3714 adds r7, #20 + 8001750: 46bd mov sp, r7 + 8001752: bc80 pop {r7} + 8001754: 4770 bx lr + ... + +08001758 : +/** + * @brief Init Radio Switch + * @retval BSP status + */ +int32_t BSP_RADIO_Init(void) +{ + 8001758: b580 push {r7, lr} + 800175a: b086 sub sp, #24 + 800175c: af00 add r7, sp, #0 + GPIO_InitTypeDef gpio_init_structure = {0}; + 800175e: 1d3b adds r3, r7, #4 + 8001760: 2200 movs r2, #0 + 8001762: 601a str r2, [r3, #0] + 8001764: 605a str r2, [r3, #4] + 8001766: 609a str r2, [r3, #8] + 8001768: 60da str r2, [r3, #12] + 800176a: 611a str r2, [r3, #16] + + /* Enable the Radio Switch Clock */ + RF_SW_CTRL3_GPIO_CLK_ENABLE(); + 800176c: 2004 movs r0, #4 + 800176e: f7ff ffda bl 8001726 + + /* Configure the Radio Switch pin */ + gpio_init_structure.Pin = RF_SW_CTRL1_PIN; + 8001772: 2310 movs r3, #16 + 8001774: 607b str r3, [r7, #4] + gpio_init_structure.Mode = GPIO_MODE_OUTPUT_PP; + 8001776: 2301 movs r3, #1 + 8001778: 60bb str r3, [r7, #8] + gpio_init_structure.Pull = GPIO_NOPULL; + 800177a: 2300 movs r3, #0 + 800177c: 60fb str r3, [r7, #12] + gpio_init_structure.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + 800177e: 2303 movs r3, #3 + 8001780: 613b str r3, [r7, #16] + + HAL_GPIO_Init(RF_SW_CTRL1_GPIO_PORT, &gpio_init_structure); + 8001782: 1d3b adds r3, r7, #4 + 8001784: 4619 mov r1, r3 + 8001786: 4812 ldr r0, [pc, #72] @ (80017d0 ) + 8001788: f000 fe54 bl 8002434 + + gpio_init_structure.Pin = RF_SW_CTRL2_PIN; + 800178c: 2320 movs r3, #32 + 800178e: 607b str r3, [r7, #4] + HAL_GPIO_Init(RF_SW_CTRL2_GPIO_PORT, &gpio_init_structure); + 8001790: 1d3b adds r3, r7, #4 + 8001792: 4619 mov r1, r3 + 8001794: 480e ldr r0, [pc, #56] @ (80017d0 ) + 8001796: f000 fe4d bl 8002434 + + gpio_init_structure.Pin = RF_SW_CTRL3_PIN; + 800179a: 2308 movs r3, #8 + 800179c: 607b str r3, [r7, #4] + HAL_GPIO_Init(RF_SW_CTRL3_GPIO_PORT, &gpio_init_structure); + 800179e: 1d3b adds r3, r7, #4 + 80017a0: 4619 mov r1, r3 + 80017a2: 480b ldr r0, [pc, #44] @ (80017d0 ) + 80017a4: f000 fe46 bl 8002434 + + HAL_GPIO_WritePin(RF_SW_CTRL2_GPIO_PORT, RF_SW_CTRL2_PIN, GPIO_PIN_RESET); + 80017a8: 2200 movs r2, #0 + 80017aa: 2120 movs r1, #32 + 80017ac: 4808 ldr r0, [pc, #32] @ (80017d0 ) + 80017ae: f001 f86f bl 8002890 + HAL_GPIO_WritePin(RF_SW_CTRL1_GPIO_PORT, RF_SW_CTRL1_PIN, GPIO_PIN_RESET); + 80017b2: 2200 movs r2, #0 + 80017b4: 2110 movs r1, #16 + 80017b6: 4806 ldr r0, [pc, #24] @ (80017d0 ) + 80017b8: f001 f86a bl 8002890 + HAL_GPIO_WritePin(RF_SW_CTRL3_GPIO_PORT, RF_SW_CTRL3_PIN, GPIO_PIN_RESET); + 80017bc: 2200 movs r2, #0 + 80017be: 2108 movs r1, #8 + 80017c0: 4803 ldr r0, [pc, #12] @ (80017d0 ) + 80017c2: f001 f865 bl 8002890 + + return BSP_ERROR_NONE; + 80017c6: 2300 movs r3, #0 +} + 80017c8: 4618 mov r0, r3 + 80017ca: 3718 adds r7, #24 + 80017cc: 46bd mov sp, r7 + 80017ce: bd80 pop {r7, pc} + 80017d0: 48000800 .word 0x48000800 + +080017d4 : + * @arg RADIO_SWITCH_RFO_LP + * @arg RADIO_SWITCH_RFO_HP + * @retval BSP status + */ +int32_t BSP_RADIO_ConfigRFSwitch(BSP_RADIO_Switch_TypeDef Config) +{ + 80017d4: b580 push {r7, lr} + 80017d6: b082 sub sp, #8 + 80017d8: af00 add r7, sp, #0 + 80017da: 4603 mov r3, r0 + 80017dc: 71fb strb r3, [r7, #7] + switch (Config) + 80017de: 79fb ldrb r3, [r7, #7] + 80017e0: 2b03 cmp r3, #3 + 80017e2: d84b bhi.n 800187c + 80017e4: a201 add r2, pc, #4 @ (adr r2, 80017ec ) + 80017e6: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 80017ea: bf00 nop + 80017ec: 080017fd .word 0x080017fd + 80017f0: 0800181d .word 0x0800181d + 80017f4: 0800183d .word 0x0800183d + 80017f8: 0800185d .word 0x0800185d + { + case RADIO_SWITCH_OFF: + { + /* Turn off switch */ + HAL_GPIO_WritePin(RF_SW_CTRL3_GPIO_PORT, RF_SW_CTRL3_PIN, GPIO_PIN_RESET); + 80017fc: 2200 movs r2, #0 + 80017fe: 2108 movs r1, #8 + 8001800: 4821 ldr r0, [pc, #132] @ (8001888 ) + 8001802: f001 f845 bl 8002890 + HAL_GPIO_WritePin(RF_SW_CTRL1_GPIO_PORT, RF_SW_CTRL1_PIN, GPIO_PIN_RESET); + 8001806: 2200 movs r2, #0 + 8001808: 2110 movs r1, #16 + 800180a: 481f ldr r0, [pc, #124] @ (8001888 ) + 800180c: f001 f840 bl 8002890 + HAL_GPIO_WritePin(RF_SW_CTRL2_GPIO_PORT, RF_SW_CTRL2_PIN, GPIO_PIN_RESET); + 8001810: 2200 movs r2, #0 + 8001812: 2120 movs r1, #32 + 8001814: 481c ldr r0, [pc, #112] @ (8001888 ) + 8001816: f001 f83b bl 8002890 + break; + 800181a: e030 b.n 800187e + } + case RADIO_SWITCH_RX: + { + /*Turns On in Rx Mode the RF Switch */ + HAL_GPIO_WritePin(RF_SW_CTRL3_GPIO_PORT, RF_SW_CTRL3_PIN, GPIO_PIN_SET); + 800181c: 2201 movs r2, #1 + 800181e: 2108 movs r1, #8 + 8001820: 4819 ldr r0, [pc, #100] @ (8001888 ) + 8001822: f001 f835 bl 8002890 + HAL_GPIO_WritePin(RF_SW_CTRL1_GPIO_PORT, RF_SW_CTRL1_PIN, GPIO_PIN_SET); + 8001826: 2201 movs r2, #1 + 8001828: 2110 movs r1, #16 + 800182a: 4817 ldr r0, [pc, #92] @ (8001888 ) + 800182c: f001 f830 bl 8002890 + HAL_GPIO_WritePin(RF_SW_CTRL2_GPIO_PORT, RF_SW_CTRL2_PIN, GPIO_PIN_RESET); + 8001830: 2200 movs r2, #0 + 8001832: 2120 movs r1, #32 + 8001834: 4814 ldr r0, [pc, #80] @ (8001888 ) + 8001836: f001 f82b bl 8002890 + break; + 800183a: e020 b.n 800187e + } + case RADIO_SWITCH_RFO_LP: + { + /*Turns On in Tx Low Power the RF Switch */ + HAL_GPIO_WritePin(RF_SW_CTRL3_GPIO_PORT, RF_SW_CTRL3_PIN, GPIO_PIN_SET); + 800183c: 2201 movs r2, #1 + 800183e: 2108 movs r1, #8 + 8001840: 4811 ldr r0, [pc, #68] @ (8001888 ) + 8001842: f001 f825 bl 8002890 + HAL_GPIO_WritePin(RF_SW_CTRL1_GPIO_PORT, RF_SW_CTRL1_PIN, GPIO_PIN_SET); + 8001846: 2201 movs r2, #1 + 8001848: 2110 movs r1, #16 + 800184a: 480f ldr r0, [pc, #60] @ (8001888 ) + 800184c: f001 f820 bl 8002890 + HAL_GPIO_WritePin(RF_SW_CTRL2_GPIO_PORT, RF_SW_CTRL2_PIN, GPIO_PIN_SET); + 8001850: 2201 movs r2, #1 + 8001852: 2120 movs r1, #32 + 8001854: 480c ldr r0, [pc, #48] @ (8001888 ) + 8001856: f001 f81b bl 8002890 + break; + 800185a: e010 b.n 800187e + } + case RADIO_SWITCH_RFO_HP: + { + /*Turns On in Tx High Power the RF Switch */ + HAL_GPIO_WritePin(RF_SW_CTRL3_GPIO_PORT, RF_SW_CTRL3_PIN, GPIO_PIN_SET); + 800185c: 2201 movs r2, #1 + 800185e: 2108 movs r1, #8 + 8001860: 4809 ldr r0, [pc, #36] @ (8001888 ) + 8001862: f001 f815 bl 8002890 + HAL_GPIO_WritePin(RF_SW_CTRL1_GPIO_PORT, RF_SW_CTRL1_PIN, GPIO_PIN_RESET); + 8001866: 2200 movs r2, #0 + 8001868: 2110 movs r1, #16 + 800186a: 4807 ldr r0, [pc, #28] @ (8001888 ) + 800186c: f001 f810 bl 8002890 + HAL_GPIO_WritePin(RF_SW_CTRL2_GPIO_PORT, RF_SW_CTRL2_PIN, GPIO_PIN_SET); + 8001870: 2201 movs r2, #1 + 8001872: 2120 movs r1, #32 + 8001874: 4804 ldr r0, [pc, #16] @ (8001888 ) + 8001876: f001 f80b bl 8002890 + break; + 800187a: e000 b.n 800187e + } + default: + break; + 800187c: bf00 nop + } + + return BSP_ERROR_NONE; + 800187e: 2300 movs r3, #0 +} + 8001880: 4618 mov r0, r3 + 8001882: 3708 adds r7, #8 + 8001884: 46bd mov sp, r7 + 8001886: bd80 pop {r7, pc} + 8001888: 48000800 .word 0x48000800 + +0800188c : + * RADIO_CONF_RFO_LP_HP + * RADIO_CONF_RFO_LP + * RADIO_CONF_RFO_HP + */ +int32_t BSP_RADIO_GetTxConfig(void) +{ + 800188c: b480 push {r7} + 800188e: af00 add r7, sp, #0 + return RADIO_CONF_RFO_LP_HP; + 8001890: 2300 movs r3, #0 +} + 8001892: 4618 mov r0, r3 + 8001894: 46bd mov sp, r7 + 8001896: bc80 pop {r7} + 8001898: 4770 bx lr + +0800189a : + * @retval + * RADIO_CONF_TCXO_NOT_SUPPORTED + * RADIO_CONF_TCXO_SUPPORTED + */ +int32_t BSP_RADIO_IsTCXO(void) +{ + 800189a: b480 push {r7} + 800189c: af00 add r7, sp, #0 + return RADIO_CONF_TCXO_SUPPORTED; + 800189e: 2301 movs r3, #1 +} + 80018a0: 4618 mov r0, r3 + 80018a2: 46bd mov sp, r7 + 80018a4: bc80 pop {r7} + 80018a6: 4770 bx lr + +080018a8 : + * @retval + * RADIO_CONF_DCDC_NOT_SUPPORTED + * RADIO_CONF_DCDC_SUPPORTED + */ +int32_t BSP_RADIO_IsDCDC(void) +{ + 80018a8: b480 push {r7} + 80018aa: af00 add r7, sp, #0 + return RADIO_CONF_DCDC_SUPPORTED; + 80018ac: 2301 movs r3, #1 +} + 80018ae: 4618 mov r0, r3 + 80018b0: 46bd mov sp, r7 + 80018b2: bc80 pop {r7} + 80018b4: 4770 bx lr + +080018b6 : + * @retval + * RADIO_CONF_RFO_LP_MAX_15_dBm for LP mode + * RADIO_CONF_RFO_HP_MAX_22_dBm for HP mode + */ +int32_t BSP_RADIO_GetRFOMaxPowerConfig(BSP_RADIO_RFOMaxPowerConfig_TypeDef Config) +{ + 80018b6: b480 push {r7} + 80018b8: b085 sub sp, #20 + 80018ba: af00 add r7, sp, #0 + 80018bc: 4603 mov r3, r0 + 80018be: 71fb strb r3, [r7, #7] + int32_t ret; + + if(Config == RADIO_RFO_LP_MAXPOWER) + 80018c0: 79fb ldrb r3, [r7, #7] + 80018c2: 2b00 cmp r3, #0 + 80018c4: d102 bne.n 80018cc + { + ret = RADIO_CONF_RFO_LP_MAX_15_dBm; + 80018c6: 230f movs r3, #15 + 80018c8: 60fb str r3, [r7, #12] + 80018ca: e001 b.n 80018d0 + } + else + { + ret = RADIO_CONF_RFO_HP_MAX_22_dBm; + 80018cc: 2316 movs r3, #22 + 80018ce: 60fb str r3, [r7, #12] + } + + return ret; + 80018d0: 68fb ldr r3, [r7, #12] +} + 80018d2: 4618 mov r0, r3 + 80018d4: 3714 adds r7, #20 + 80018d6: 46bd mov sp, r7 + 80018d8: bc80 pop {r7} + 80018da: 4770 bx lr + +080018dc : + * @brief Enable the CPU1 Debug Module during SLEEP mode + * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_EnableDBGSleepMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_EnableDBGSleepMode(void) +{ + 80018dc: b480 push {r7} + 80018de: af00 add r7, sp, #0 + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); + 80018e0: 4b04 ldr r3, [pc, #16] @ (80018f4 ) + 80018e2: 685b ldr r3, [r3, #4] + 80018e4: 4a03 ldr r2, [pc, #12] @ (80018f4 ) + 80018e6: f043 0301 orr.w r3, r3, #1 + 80018ea: 6053 str r3, [r2, #4] +} + 80018ec: bf00 nop + 80018ee: 46bd mov sp, r7 + 80018f0: bc80 pop {r7} + 80018f2: 4770 bx lr + 80018f4: e0042000 .word 0xe0042000 + +080018f8 : + * in Stop mode even when this bit is enabled + * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void) +{ + 80018f8: b480 push {r7} + 80018fa: af00 add r7, sp, #0 + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); + 80018fc: 4b04 ldr r3, [pc, #16] @ (8001910 ) + 80018fe: 685b ldr r3, [r3, #4] + 8001900: 4a03 ldr r2, [pc, #12] @ (8001910 ) + 8001902: f043 0302 orr.w r3, r3, #2 + 8001906: 6053 str r3, [r2, #4] +} + 8001908: bf00 nop + 800190a: 46bd mov sp, r7 + 800190c: bc80 pop {r7} + 800190e: 4770 bx lr + 8001910: e0042000 .word 0xe0042000 + +08001914 : + * in Standby mode even when this bit is enabled + * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void) +{ + 8001914: b480 push {r7} + 8001916: af00 add r7, sp, #0 + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); + 8001918: 4b04 ldr r3, [pc, #16] @ (800192c ) + 800191a: 685b ldr r3, [r3, #4] + 800191c: 4a03 ldr r2, [pc, #12] @ (800192c ) + 800191e: f043 0304 orr.w r3, r3, #4 + 8001922: 6053 str r3, [r2, #4] +} + 8001924: bf00 nop + 8001926: 46bd mov sp, r7 + 8001928: bc80 pop {r7} + 800192a: 4770 bx lr + 800192c: e0042000 .word 0xe0042000 + +08001930 : + * need to ensure that the SysTick time base is always set to 1 millisecond + * to have correct HAL operation. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_Init(void) +{ + 8001930: b580 push {r7, lr} + 8001932: b082 sub sp, #8 + 8001934: af00 add r7, sp, #0 + HAL_StatusTypeDef status = HAL_OK; + 8001936: 2300 movs r3, #0 + 8001938: 71fb strb r3, [r7, #7] +#endif /* PREFETCH_ENABLE */ + +#ifdef CORE_CM0PLUS +#else + /* Set Interrupt Group Priority */ + HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); + 800193a: 2003 movs r0, #3 + 800193c: f000 f914 bl 8001b68 + + /* Update the SystemCoreClock global variable */ +#if defined(DUAL_CORE) && defined(CORE_CM0PLUS) + SystemCoreClock = HAL_RCC_GetHCLK2Freq(); +#else + SystemCoreClock = HAL_RCC_GetHCLKFreq(); + 8001940: f002 f8b8 bl 8003ab4 + 8001944: 4603 mov r3, r0 + 8001946: 4a09 ldr r2, [pc, #36] @ (800196c ) + 8001948: 6013 str r3, [r2, #0] +#endif + + /* Use SysTick as time base source and configure 1ms tick (default clock after Reset is MSI) */ + if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) + 800194a: 200f movs r0, #15 + 800194c: f7ff f972 bl 8000c34 + 8001950: 4603 mov r3, r0 + 8001952: 2b00 cmp r3, #0 + 8001954: d002 beq.n 800195c + { + status = HAL_ERROR; + 8001956: 2301 movs r3, #1 + 8001958: 71fb strb r3, [r7, #7] + 800195a: e001 b.n 8001960 + } + else + { + /* Init the low level hardware */ + HAL_MspInit(); + 800195c: f7ff f82f bl 80009be + } + + /* Return function status */ + return status; + 8001960: 79fb ldrb r3, [r7, #7] +} + 8001962: 4618 mov r0, r3 + 8001964: 3708 adds r7, #8 + 8001966: 46bd mov sp, r7 + 8001968: bd80 pop {r7, pc} + 800196a: bf00 nop + 800196c: 20000000 .word 0x20000000 + +08001970 : + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void HAL_SuspendTick(void) +{ + 8001970: b480 push {r7} + 8001972: af00 add r7, sp, #0 + /* Disable SysTick Interrupt */ + CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); + 8001974: 4b04 ldr r3, [pc, #16] @ (8001988 ) + 8001976: 681b ldr r3, [r3, #0] + 8001978: 4a03 ldr r2, [pc, #12] @ (8001988 ) + 800197a: f023 0302 bic.w r3, r3, #2 + 800197e: 6013 str r3, [r2, #0] +} + 8001980: bf00 nop + 8001982: 46bd mov sp, r7 + 8001984: bc80 pop {r7} + 8001986: 4770 bx lr + 8001988: e000e010 .word 0xe000e010 + +0800198c : + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void HAL_ResumeTick(void) +{ + 800198c: b480 push {r7} + 800198e: af00 add r7, sp, #0 + /* Enable SysTick Interrupt */ + SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); + 8001990: 4b04 ldr r3, [pc, #16] @ (80019a4 ) + 8001992: 681b ldr r3, [r3, #0] + 8001994: 4a03 ldr r2, [pc, #12] @ (80019a4 ) + 8001996: f043 0302 orr.w r3, r3, #2 + 800199a: 6013 str r3, [r2, #0] +} + 800199c: bf00 nop + 800199e: 46bd mov sp, r7 + 80019a0: bc80 pop {r7} + 80019a2: 4770 bx lr + 80019a4: e000e010 .word 0xe000e010 + +080019a8 : +/** + * @brief Enable the CPU1 Debug Module during SLEEP mode + * @retval None + */ +void HAL_DBGMCU_EnableDBGSleepMode(void) +{ + 80019a8: b580 push {r7, lr} + 80019aa: af00 add r7, sp, #0 + LL_DBGMCU_EnableDBGSleepMode(); + 80019ac: f7ff ff96 bl 80018dc +} + 80019b0: bf00 nop + 80019b2: bd80 pop {r7, pc} + +080019b4 : + * @note This functionality does not influence CPU2 operation, CPU2 cannot be debugged + * in Stop mode even when this bit is enabled + * @retval None + */ +void HAL_DBGMCU_EnableDBGStopMode(void) +{ + 80019b4: b580 push {r7, lr} + 80019b6: af00 add r7, sp, #0 + LL_DBGMCU_EnableDBGStopMode(); + 80019b8: f7ff ff9e bl 80018f8 +} + 80019bc: bf00 nop + 80019be: bd80 pop {r7, pc} + +080019c0 : + * @note This functionality does not influence CPU2 operation, CPU2 cannot be debugged + * in Standby mode even when this bit is enabled + * @retval None + */ +void HAL_DBGMCU_EnableDBGStandbyMode(void) +{ + 80019c0: b580 push {r7, lr} + 80019c2: af00 add r7, sp, #0 + LL_DBGMCU_EnableDBGStandbyMode(); + 80019c4: f7ff ffa6 bl 8001914 +} + 80019c8: bf00 nop + 80019ca: bd80 pop {r7, pc} + +080019cc <__NVIC_SetPriorityGrouping>: + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + 80019cc: b480 push {r7} + 80019ce: b085 sub sp, #20 + 80019d0: af00 add r7, sp, #0 + 80019d2: 6078 str r0, [r7, #4] + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + 80019d4: 687b ldr r3, [r7, #4] + 80019d6: f003 0307 and.w r3, r3, #7 + 80019da: 60fb str r3, [r7, #12] + + reg_value = SCB->AIRCR; /* read old register configuration */ + 80019dc: 4b0c ldr r3, [pc, #48] @ (8001a10 <__NVIC_SetPriorityGrouping+0x44>) + 80019de: 68db ldr r3, [r3, #12] + 80019e0: 60bb str r3, [r7, #8] + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + 80019e2: 68ba ldr r2, [r7, #8] + 80019e4: f64f 03ff movw r3, #63743 @ 0xf8ff + 80019e8: 4013 ands r3, r2 + 80019ea: 60bb str r3, [r7, #8] + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + 80019ec: 68fb ldr r3, [r7, #12] + 80019ee: 021a lsls r2, r3, #8 + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + 80019f0: 68bb ldr r3, [r7, #8] + 80019f2: 4313 orrs r3, r2 + reg_value = (reg_value | + 80019f4: f043 63bf orr.w r3, r3, #100139008 @ 0x5f80000 + 80019f8: f443 3300 orr.w r3, r3, #131072 @ 0x20000 + 80019fc: 60bb str r3, [r7, #8] + SCB->AIRCR = reg_value; + 80019fe: 4a04 ldr r2, [pc, #16] @ (8001a10 <__NVIC_SetPriorityGrouping+0x44>) + 8001a00: 68bb ldr r3, [r7, #8] + 8001a02: 60d3 str r3, [r2, #12] +} + 8001a04: bf00 nop + 8001a06: 3714 adds r7, #20 + 8001a08: 46bd mov sp, r7 + 8001a0a: bc80 pop {r7} + 8001a0c: 4770 bx lr + 8001a0e: bf00 nop + 8001a10: e000ed00 .word 0xe000ed00 + +08001a14 <__NVIC_GetPriorityGrouping>: + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + 8001a14: b480 push {r7} + 8001a16: af00 add r7, sp, #0 + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); + 8001a18: 4b04 ldr r3, [pc, #16] @ (8001a2c <__NVIC_GetPriorityGrouping+0x18>) + 8001a1a: 68db ldr r3, [r3, #12] + 8001a1c: 0a1b lsrs r3, r3, #8 + 8001a1e: f003 0307 and.w r3, r3, #7 +} + 8001a22: 4618 mov r0, r3 + 8001a24: 46bd mov sp, r7 + 8001a26: bc80 pop {r7} + 8001a28: 4770 bx lr + 8001a2a: bf00 nop + 8001a2c: e000ed00 .word 0xe000ed00 + +08001a30 <__NVIC_EnableIRQ>: + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + 8001a30: b480 push {r7} + 8001a32: b083 sub sp, #12 + 8001a34: af00 add r7, sp, #0 + 8001a36: 4603 mov r3, r0 + 8001a38: 71fb strb r3, [r7, #7] + if ((int32_t)(IRQn) >= 0) + 8001a3a: f997 3007 ldrsb.w r3, [r7, #7] + 8001a3e: 2b00 cmp r3, #0 + 8001a40: db0b blt.n 8001a5a <__NVIC_EnableIRQ+0x2a> + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + 8001a42: 79fb ldrb r3, [r7, #7] + 8001a44: f003 021f and.w r2, r3, #31 + 8001a48: 4906 ldr r1, [pc, #24] @ (8001a64 <__NVIC_EnableIRQ+0x34>) + 8001a4a: f997 3007 ldrsb.w r3, [r7, #7] + 8001a4e: 095b lsrs r3, r3, #5 + 8001a50: 2001 movs r0, #1 + 8001a52: fa00 f202 lsl.w r2, r0, r2 + 8001a56: f841 2023 str.w r2, [r1, r3, lsl #2] + __COMPILER_BARRIER(); + } +} + 8001a5a: bf00 nop + 8001a5c: 370c adds r7, #12 + 8001a5e: 46bd mov sp, r7 + 8001a60: bc80 pop {r7} + 8001a62: 4770 bx lr + 8001a64: e000e100 .word 0xe000e100 + +08001a68 <__NVIC_DisableIRQ>: + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + 8001a68: b480 push {r7} + 8001a6a: b083 sub sp, #12 + 8001a6c: af00 add r7, sp, #0 + 8001a6e: 4603 mov r3, r0 + 8001a70: 71fb strb r3, [r7, #7] + if ((int32_t)(IRQn) >= 0) + 8001a72: f997 3007 ldrsb.w r3, [r7, #7] + 8001a76: 2b00 cmp r3, #0 + 8001a78: db12 blt.n 8001aa0 <__NVIC_DisableIRQ+0x38> + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + 8001a7a: 79fb ldrb r3, [r7, #7] + 8001a7c: f003 021f and.w r2, r3, #31 + 8001a80: 490a ldr r1, [pc, #40] @ (8001aac <__NVIC_DisableIRQ+0x44>) + 8001a82: f997 3007 ldrsb.w r3, [r7, #7] + 8001a86: 095b lsrs r3, r3, #5 + 8001a88: 2001 movs r0, #1 + 8001a8a: fa00 f202 lsl.w r2, r0, r2 + 8001a8e: 3320 adds r3, #32 + 8001a90: f841 2023 str.w r2, [r1, r3, lsl #2] + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); + 8001a94: f3bf 8f4f dsb sy +} + 8001a98: bf00 nop + __ASM volatile ("isb 0xF":::"memory"); + 8001a9a: f3bf 8f6f isb sy +} + 8001a9e: bf00 nop + __DSB(); + __ISB(); + } +} + 8001aa0: bf00 nop + 8001aa2: 370c adds r7, #12 + 8001aa4: 46bd mov sp, r7 + 8001aa6: bc80 pop {r7} + 8001aa8: 4770 bx lr + 8001aaa: bf00 nop + 8001aac: e000e100 .word 0xe000e100 + +08001ab0 <__NVIC_SetPriority>: + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + 8001ab0: b480 push {r7} + 8001ab2: b083 sub sp, #12 + 8001ab4: af00 add r7, sp, #0 + 8001ab6: 4603 mov r3, r0 + 8001ab8: 6039 str r1, [r7, #0] + 8001aba: 71fb strb r3, [r7, #7] + if ((int32_t)(IRQn) >= 0) + 8001abc: f997 3007 ldrsb.w r3, [r7, #7] + 8001ac0: 2b00 cmp r3, #0 + 8001ac2: db0a blt.n 8001ada <__NVIC_SetPriority+0x2a> + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + 8001ac4: 683b ldr r3, [r7, #0] + 8001ac6: b2da uxtb r2, r3 + 8001ac8: 490c ldr r1, [pc, #48] @ (8001afc <__NVIC_SetPriority+0x4c>) + 8001aca: f997 3007 ldrsb.w r3, [r7, #7] + 8001ace: 0112 lsls r2, r2, #4 + 8001ad0: b2d2 uxtb r2, r2 + 8001ad2: 440b add r3, r1 + 8001ad4: f883 2300 strb.w r2, [r3, #768] @ 0x300 + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + 8001ad8: e00a b.n 8001af0 <__NVIC_SetPriority+0x40> + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + 8001ada: 683b ldr r3, [r7, #0] + 8001adc: b2da uxtb r2, r3 + 8001ade: 4908 ldr r1, [pc, #32] @ (8001b00 <__NVIC_SetPriority+0x50>) + 8001ae0: 79fb ldrb r3, [r7, #7] + 8001ae2: f003 030f and.w r3, r3, #15 + 8001ae6: 3b04 subs r3, #4 + 8001ae8: 0112 lsls r2, r2, #4 + 8001aea: b2d2 uxtb r2, r2 + 8001aec: 440b add r3, r1 + 8001aee: 761a strb r2, [r3, #24] +} + 8001af0: bf00 nop + 8001af2: 370c adds r7, #12 + 8001af4: 46bd mov sp, r7 + 8001af6: bc80 pop {r7} + 8001af8: 4770 bx lr + 8001afa: bf00 nop + 8001afc: e000e100 .word 0xe000e100 + 8001b00: e000ed00 .word 0xe000ed00 + +08001b04 : + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + 8001b04: b480 push {r7} + 8001b06: b089 sub sp, #36 @ 0x24 + 8001b08: af00 add r7, sp, #0 + 8001b0a: 60f8 str r0, [r7, #12] + 8001b0c: 60b9 str r1, [r7, #8] + 8001b0e: 607a str r2, [r7, #4] + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + 8001b10: 68fb ldr r3, [r7, #12] + 8001b12: f003 0307 and.w r3, r3, #7 + 8001b16: 61fb str r3, [r7, #28] + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + 8001b18: 69fb ldr r3, [r7, #28] + 8001b1a: f1c3 0307 rsb r3, r3, #7 + 8001b1e: 2b04 cmp r3, #4 + 8001b20: bf28 it cs + 8001b22: 2304 movcs r3, #4 + 8001b24: 61bb str r3, [r7, #24] + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + 8001b26: 69fb ldr r3, [r7, #28] + 8001b28: 3304 adds r3, #4 + 8001b2a: 2b06 cmp r3, #6 + 8001b2c: d902 bls.n 8001b34 + 8001b2e: 69fb ldr r3, [r7, #28] + 8001b30: 3b03 subs r3, #3 + 8001b32: e000 b.n 8001b36 + 8001b34: 2300 movs r3, #0 + 8001b36: 617b str r3, [r7, #20] + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + 8001b38: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff + 8001b3c: 69bb ldr r3, [r7, #24] + 8001b3e: fa02 f303 lsl.w r3, r2, r3 + 8001b42: 43da mvns r2, r3 + 8001b44: 68bb ldr r3, [r7, #8] + 8001b46: 401a ands r2, r3 + 8001b48: 697b ldr r3, [r7, #20] + 8001b4a: 409a lsls r2, r3 + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + 8001b4c: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff + 8001b50: 697b ldr r3, [r7, #20] + 8001b52: fa01 f303 lsl.w r3, r1, r3 + 8001b56: 43d9 mvns r1, r3 + 8001b58: 687b ldr r3, [r7, #4] + 8001b5a: 400b ands r3, r1 + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + 8001b5c: 4313 orrs r3, r2 + ); +} + 8001b5e: 4618 mov r0, r3 + 8001b60: 3724 adds r7, #36 @ 0x24 + 8001b62: 46bd mov sp, r7 + 8001b64: bc80 pop {r7} + 8001b66: 4770 bx lr + +08001b68 : + * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. + * The pending IRQ priority will be managed only by the subpriority. + * @retval None + */ +void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + 8001b68: b580 push {r7, lr} + 8001b6a: b082 sub sp, #8 + 8001b6c: af00 add r7, sp, #0 + 8001b6e: 6078 str r0, [r7, #4] + /* Check the parameters */ + assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); + + /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ + NVIC_SetPriorityGrouping(PriorityGroup); + 8001b70: 6878 ldr r0, [r7, #4] + 8001b72: f7ff ff2b bl 80019cc <__NVIC_SetPriorityGrouping> +} + 8001b76: bf00 nop + 8001b78: 3708 adds r7, #8 + 8001b7a: 46bd mov sp, r7 + 8001b7c: bd80 pop {r7, pc} + +08001b7e : + * This parameter can be a value between 0 and 15 + * A lower priority value indicates a higher priority. + * @retval None + */ +void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) +{ + 8001b7e: b580 push {r7, lr} + 8001b80: b086 sub sp, #24 + 8001b82: af00 add r7, sp, #0 + 8001b84: 4603 mov r3, r0 + 8001b86: 60b9 str r1, [r7, #8] + 8001b88: 607a str r2, [r7, #4] + 8001b8a: 73fb strb r3, [r7, #15] + + /* Check the parameters */ + assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); + assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); + + prioritygroup = NVIC_GetPriorityGrouping(); + 8001b8c: f7ff ff42 bl 8001a14 <__NVIC_GetPriorityGrouping> + 8001b90: 6178 str r0, [r7, #20] + + NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); + 8001b92: 687a ldr r2, [r7, #4] + 8001b94: 68b9 ldr r1, [r7, #8] + 8001b96: 6978 ldr r0, [r7, #20] + 8001b98: f7ff ffb4 bl 8001b04 + 8001b9c: 4602 mov r2, r0 + 8001b9e: f997 300f ldrsb.w r3, [r7, #15] + 8001ba2: 4611 mov r1, r2 + 8001ba4: 4618 mov r0, r3 + 8001ba6: f7ff ff83 bl 8001ab0 <__NVIC_SetPriority> +} + 8001baa: bf00 nop + 8001bac: 3718 adds r7, #24 + 8001bae: 46bd mov sp, r7 + 8001bb0: bd80 pop {r7, pc} + +08001bb2 : + * (For the complete STM32 Devices IRQ Channels list, please refer + * to the appropriate CMSIS device file (stm32wlxxxx.h)) + * @retval None + */ +void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) +{ + 8001bb2: b580 push {r7, lr} + 8001bb4: b082 sub sp, #8 + 8001bb6: af00 add r7, sp, #0 + 8001bb8: 4603 mov r3, r0 + 8001bba: 71fb strb r3, [r7, #7] + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Enable interrupt */ + NVIC_EnableIRQ(IRQn); + 8001bbc: f997 3007 ldrsb.w r3, [r7, #7] + 8001bc0: 4618 mov r0, r3 + 8001bc2: f7ff ff35 bl 8001a30 <__NVIC_EnableIRQ> +} + 8001bc6: bf00 nop + 8001bc8: 3708 adds r7, #8 + 8001bca: 46bd mov sp, r7 + 8001bcc: bd80 pop {r7, pc} + +08001bce : + * (For the complete STM32 Devices IRQ Channels list, please refer + * to the appropriate CMSIS device file (stm32wlxxxx.h)) + * @retval None + */ +void HAL_NVIC_DisableIRQ(IRQn_Type IRQn) +{ + 8001bce: b580 push {r7, lr} + 8001bd0: b082 sub sp, #8 + 8001bd2: af00 add r7, sp, #0 + 8001bd4: 4603 mov r3, r0 + 8001bd6: 71fb strb r3, [r7, #7] + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Disable interrupt */ + NVIC_DisableIRQ(IRQn); + 8001bd8: f997 3007 ldrsb.w r3, [r7, #7] + 8001bdc: 4618 mov r0, r3 + 8001bde: f7ff ff43 bl 8001a68 <__NVIC_DisableIRQ> +} + 8001be2: bf00 nop + 8001be4: 3708 adds r7, #8 + 8001be6: 46bd mov sp, r7 + 8001be8: bd80 pop {r7, pc} + ... + +08001bec : + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) +{ + 8001bec: b580 push {r7, lr} + 8001bee: b082 sub sp, #8 + 8001bf0: af00 add r7, sp, #0 + 8001bf2: 6078 str r0, [r7, #4] + /* Check the DMA handle allocation */ + if (hdma == NULL) + 8001bf4: 687b ldr r3, [r7, #4] + 8001bf6: 2b00 cmp r3, #0 + 8001bf8: d101 bne.n 8001bfe + { + return HAL_ERROR; + 8001bfa: 2301 movs r3, #1 + 8001bfc: e08e b.n 8001d1c + assert_param(IS_DMA_PRIORITY(hdma->Init.Priority)); + + assert_param(IS_DMA_ALL_REQUEST(hdma->Init.Request)); + + /* Compute the channel index */ + if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1)) + 8001bfe: 687b ldr r3, [r7, #4] + 8001c00: 681b ldr r3, [r3, #0] + 8001c02: 461a mov r2, r3 + 8001c04: 4b47 ldr r3, [pc, #284] @ (8001d24 ) + 8001c06: 429a cmp r2, r3 + 8001c08: d80f bhi.n 8001c2a + { + /* DMA1 */ + hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U; + 8001c0a: 687b ldr r3, [r7, #4] + 8001c0c: 681b ldr r3, [r3, #0] + 8001c0e: 461a mov r2, r3 + 8001c10: 4b45 ldr r3, [pc, #276] @ (8001d28 ) + 8001c12: 4413 add r3, r2 + 8001c14: 4a45 ldr r2, [pc, #276] @ (8001d2c ) + 8001c16: fba2 2303 umull r2, r3, r2, r3 + 8001c1a: 091b lsrs r3, r3, #4 + 8001c1c: 009a lsls r2, r3, #2 + 8001c1e: 687b ldr r3, [r7, #4] + 8001c20: 645a str r2, [r3, #68] @ 0x44 + hdma->DmaBaseAddress = DMA1; + 8001c22: 687b ldr r3, [r7, #4] + 8001c24: 4a42 ldr r2, [pc, #264] @ (8001d30 ) + 8001c26: 641a str r2, [r3, #64] @ 0x40 + 8001c28: e00e b.n 8001c48 + } + else + { + /* DMA2 */ + hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2U; + 8001c2a: 687b ldr r3, [r7, #4] + 8001c2c: 681b ldr r3, [r3, #0] + 8001c2e: 461a mov r2, r3 + 8001c30: 4b40 ldr r3, [pc, #256] @ (8001d34 ) + 8001c32: 4413 add r3, r2 + 8001c34: 4a3d ldr r2, [pc, #244] @ (8001d2c ) + 8001c36: fba2 2303 umull r2, r3, r2, r3 + 8001c3a: 091b lsrs r3, r3, #4 + 8001c3c: 009a lsls r2, r3, #2 + 8001c3e: 687b ldr r3, [r7, #4] + 8001c40: 645a str r2, [r3, #68] @ 0x44 + hdma->DmaBaseAddress = DMA2; + 8001c42: 687b ldr r3, [r7, #4] + 8001c44: 4a3c ldr r2, [pc, #240] @ (8001d38 ) + 8001c46: 641a str r2, [r3, #64] @ 0x40 + } + + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_BUSY; + 8001c48: 687b ldr r3, [r7, #4] + 8001c4a: 2202 movs r2, #2 + 8001c4c: f883 2025 strb.w r2, [r3, #37] @ 0x25 + + /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR and MEM2MEM bits */ + CLEAR_BIT(hdma->Instance->CCR, (DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | \ + 8001c50: 687b ldr r3, [r7, #4] + 8001c52: 681b ldr r3, [r3, #0] + 8001c54: 681b ldr r3, [r3, #0] + 8001c56: 687a ldr r2, [r7, #4] + 8001c58: 6812 ldr r2, [r2, #0] + 8001c5a: f423 43ff bic.w r3, r3, #32640 @ 0x7f80 + 8001c5e: f023 0370 bic.w r3, r3, #112 @ 0x70 + 8001c62: 6013 str r3, [r2, #0] + DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | \ + DMA_CCR_DIR | DMA_CCR_MEM2MEM)); + + /* Set the DMA Channel configuration */ + SET_BIT(hdma->Instance->CCR, (hdma->Init.Direction | \ + 8001c64: 687b ldr r3, [r7, #4] + 8001c66: 681b ldr r3, [r3, #0] + 8001c68: 6819 ldr r1, [r3, #0] + 8001c6a: 687b ldr r3, [r7, #4] + 8001c6c: 689a ldr r2, [r3, #8] + 8001c6e: 687b ldr r3, [r7, #4] + 8001c70: 68db ldr r3, [r3, #12] + 8001c72: 431a orrs r2, r3 + 8001c74: 687b ldr r3, [r7, #4] + 8001c76: 691b ldr r3, [r3, #16] + 8001c78: 431a orrs r2, r3 + 8001c7a: 687b ldr r3, [r7, #4] + 8001c7c: 695b ldr r3, [r3, #20] + 8001c7e: 431a orrs r2, r3 + 8001c80: 687b ldr r3, [r7, #4] + 8001c82: 699b ldr r3, [r3, #24] + 8001c84: 431a orrs r2, r3 + 8001c86: 687b ldr r3, [r7, #4] + 8001c88: 69db ldr r3, [r3, #28] + 8001c8a: 431a orrs r2, r3 + 8001c8c: 687b ldr r3, [r7, #4] + 8001c8e: 6a1b ldr r3, [r3, #32] + 8001c90: 431a orrs r2, r3 + 8001c92: 687b ldr r3, [r7, #4] + 8001c94: 681b ldr r3, [r3, #0] + 8001c96: 430a orrs r2, r1 + 8001c98: 601a str r2, [r3, #0] + hdma->Init.Mode | hdma->Init.Priority)); + + /* Initialize parameters for DMAMUX channel : + DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask + */ + DMA_CalcDMAMUXChannelBaseAndMask(hdma); + 8001c9a: 6878 ldr r0, [r7, #4] + 8001c9c: f000 fb5e bl 800235c + + if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY) + 8001ca0: 687b ldr r3, [r7, #4] + 8001ca2: 689b ldr r3, [r3, #8] + 8001ca4: f5b3 4f80 cmp.w r3, #16384 @ 0x4000 + 8001ca8: d102 bne.n 8001cb0 + { + /* if memory to memory force the request to 0*/ + hdma->Init.Request = DMA_REQUEST_MEM2MEM; + 8001caa: 687b ldr r3, [r7, #4] + 8001cac: 2200 movs r2, #0 + 8001cae: 605a str r2, [r3, #4] + } + + /* Set peripheral request to DMAMUX channel */ + hdma->DMAmuxChannel->CCR = (hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID); + 8001cb0: 687b ldr r3, [r7, #4] + 8001cb2: 685a ldr r2, [r3, #4] + 8001cb4: 687b ldr r3, [r7, #4] + 8001cb6: 6c9b ldr r3, [r3, #72] @ 0x48 + 8001cb8: f002 027f and.w r2, r2, #127 @ 0x7f + 8001cbc: 601a str r2, [r3, #0] + + /* Clear the DMAMUX synchro overrun flag */ + hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; + 8001cbe: 687b ldr r3, [r7, #4] + 8001cc0: 6cdb ldr r3, [r3, #76] @ 0x4c + 8001cc2: 687a ldr r2, [r7, #4] + 8001cc4: 6d12 ldr r2, [r2, #80] @ 0x50 + 8001cc6: 605a str r2, [r3, #4] + + if (((hdma->Init.Request > 0UL) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR3))) + 8001cc8: 687b ldr r3, [r7, #4] + 8001cca: 685b ldr r3, [r3, #4] + 8001ccc: 2b00 cmp r3, #0 + 8001cce: d010 beq.n 8001cf2 + 8001cd0: 687b ldr r3, [r7, #4] + 8001cd2: 685b ldr r3, [r3, #4] + 8001cd4: 2b04 cmp r3, #4 + 8001cd6: d80c bhi.n 8001cf2 + { + /* Initialize parameters for DMAMUX request generator : + DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask + */ + DMA_CalcDMAMUXRequestGenBaseAndMask(hdma); + 8001cd8: 6878 ldr r0, [r7, #4] + 8001cda: f000 fb87 bl 80023ec + + /* Reset the DMAMUX request generator register*/ + hdma->DMAmuxRequestGen->RGCR = 0U; + 8001cde: 687b ldr r3, [r7, #4] + 8001ce0: 6d5b ldr r3, [r3, #84] @ 0x54 + 8001ce2: 2200 movs r2, #0 + 8001ce4: 601a str r2, [r3, #0] + + /* Clear the DMAMUX request generator overrun flag */ + hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; + 8001ce6: 687b ldr r3, [r7, #4] + 8001ce8: 6d9b ldr r3, [r3, #88] @ 0x58 + 8001cea: 687a ldr r2, [r7, #4] + 8001cec: 6dd2 ldr r2, [r2, #92] @ 0x5c + 8001cee: 605a str r2, [r3, #4] + 8001cf0: e008 b.n 8001d04 + } + else + { + hdma->DMAmuxRequestGen = NULL; + 8001cf2: 687b ldr r3, [r7, #4] + 8001cf4: 2200 movs r2, #0 + 8001cf6: 655a str r2, [r3, #84] @ 0x54 + hdma->DMAmuxRequestGenStatus = NULL; + 8001cf8: 687b ldr r3, [r7, #4] + 8001cfa: 2200 movs r2, #0 + 8001cfc: 659a str r2, [r3, #88] @ 0x58 + hdma->DMAmuxRequestGenStatusMask = 0U; + 8001cfe: 687b ldr r3, [r7, #4] + 8001d00: 2200 movs r2, #0 + 8001d02: 65da str r2, [r3, #92] @ 0x5c + } + + /* Initialize the error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + 8001d04: 687b ldr r3, [r7, #4] + 8001d06: 2200 movs r2, #0 + 8001d08: 63da str r2, [r3, #60] @ 0x3c + + /* Initialize the DMA state*/ + hdma->State = HAL_DMA_STATE_READY; + 8001d0a: 687b ldr r3, [r7, #4] + 8001d0c: 2201 movs r2, #1 + 8001d0e: f883 2025 strb.w r2, [r3, #37] @ 0x25 + + /* Release Lock */ + __HAL_UNLOCK(hdma); + 8001d12: 687b ldr r3, [r7, #4] + 8001d14: 2200 movs r2, #0 + 8001d16: f883 2024 strb.w r2, [r3, #36] @ 0x24 + + return HAL_OK; + 8001d1a: 2300 movs r3, #0 +} + 8001d1c: 4618 mov r0, r3 + 8001d1e: 3708 adds r7, #8 + 8001d20: 46bd mov sp, r7 + 8001d22: bd80 pop {r7, pc} + 8001d24: 40020407 .word 0x40020407 + 8001d28: bffdfff8 .word 0xbffdfff8 + 8001d2c: cccccccd .word 0xcccccccd + 8001d30: 40020000 .word 0x40020000 + 8001d34: bffdfbf8 .word 0xbffdfbf8 + 8001d38: 40020400 .word 0x40020400 + +08001d3c : + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) +{ + 8001d3c: b580 push {r7, lr} + 8001d3e: b082 sub sp, #8 + 8001d40: af00 add r7, sp, #0 + 8001d42: 6078 str r0, [r7, #4] + /* Check the DMA handle allocation */ + if (NULL == hdma) + 8001d44: 687b ldr r3, [r7, #4] + 8001d46: 2b00 cmp r3, #0 + 8001d48: d101 bne.n 8001d4e + { + return HAL_ERROR; + 8001d4a: 2301 movs r3, #1 + 8001d4c: e07b b.n 8001e46 + + /* Check the parameters */ + assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); + + /* Disable the selected DMA Channelx */ + __HAL_DMA_DISABLE(hdma); + 8001d4e: 687b ldr r3, [r7, #4] + 8001d50: 681b ldr r3, [r3, #0] + 8001d52: 681a ldr r2, [r3, #0] + 8001d54: 687b ldr r3, [r7, #4] + 8001d56: 681b ldr r3, [r3, #0] + 8001d58: f022 0201 bic.w r2, r2, #1 + 8001d5c: 601a str r2, [r3, #0] + + /* Compute the channel index */ + if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1)) + 8001d5e: 687b ldr r3, [r7, #4] + 8001d60: 681b ldr r3, [r3, #0] + 8001d62: 461a mov r2, r3 + 8001d64: 4b3a ldr r3, [pc, #232] @ (8001e50 ) + 8001d66: 429a cmp r2, r3 + 8001d68: d80f bhi.n 8001d8a + { + /* DMA1 */ + hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U; + 8001d6a: 687b ldr r3, [r7, #4] + 8001d6c: 681b ldr r3, [r3, #0] + 8001d6e: 461a mov r2, r3 + 8001d70: 4b38 ldr r3, [pc, #224] @ (8001e54 ) + 8001d72: 4413 add r3, r2 + 8001d74: 4a38 ldr r2, [pc, #224] @ (8001e58 ) + 8001d76: fba2 2303 umull r2, r3, r2, r3 + 8001d7a: 091b lsrs r3, r3, #4 + 8001d7c: 009a lsls r2, r3, #2 + 8001d7e: 687b ldr r3, [r7, #4] + 8001d80: 645a str r2, [r3, #68] @ 0x44 + hdma->DmaBaseAddress = DMA1; + 8001d82: 687b ldr r3, [r7, #4] + 8001d84: 4a35 ldr r2, [pc, #212] @ (8001e5c ) + 8001d86: 641a str r2, [r3, #64] @ 0x40 + 8001d88: e00e b.n 8001da8 + } + else + { + /* DMA2 */ + hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2U; + 8001d8a: 687b ldr r3, [r7, #4] + 8001d8c: 681b ldr r3, [r3, #0] + 8001d8e: 461a mov r2, r3 + 8001d90: 4b33 ldr r3, [pc, #204] @ (8001e60 ) + 8001d92: 4413 add r3, r2 + 8001d94: 4a30 ldr r2, [pc, #192] @ (8001e58 ) + 8001d96: fba2 2303 umull r2, r3, r2, r3 + 8001d9a: 091b lsrs r3, r3, #4 + 8001d9c: 009a lsls r2, r3, #2 + 8001d9e: 687b ldr r3, [r7, #4] + 8001da0: 645a str r2, [r3, #68] @ 0x44 + hdma->DmaBaseAddress = DMA2; + 8001da2: 687b ldr r3, [r7, #4] + 8001da4: 4a2f ldr r2, [pc, #188] @ (8001e64 ) + 8001da6: 641a str r2, [r3, #64] @ 0x40 + } + + /* Reset DMA Channel control register */ + hdma->Instance->CCR = 0U; + 8001da8: 687b ldr r3, [r7, #4] + 8001daa: 681b ldr r3, [r3, #0] + 8001dac: 2200 movs r2, #0 + 8001dae: 601a str r2, [r3, #0] + + /* Clear all flags */ + hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU)); + 8001db0: 687b ldr r3, [r7, #4] + 8001db2: 6c5b ldr r3, [r3, #68] @ 0x44 + 8001db4: f003 021c and.w r2, r3, #28 + 8001db8: 687b ldr r3, [r7, #4] + 8001dba: 6c1b ldr r3, [r3, #64] @ 0x40 + 8001dbc: 2101 movs r1, #1 + 8001dbe: fa01 f202 lsl.w r2, r1, r2 + 8001dc2: 605a str r2, [r3, #4] + + /* Initialize parameters for DMAMUX channel : + DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask */ + + DMA_CalcDMAMUXChannelBaseAndMask(hdma); + 8001dc4: 6878 ldr r0, [r7, #4] + 8001dc6: f000 fac9 bl 800235c + + /* Reset the DMAMUX channel that corresponds to the DMA channel */ + hdma->DMAmuxChannel->CCR = 0U; + 8001dca: 687b ldr r3, [r7, #4] + 8001dcc: 6c9b ldr r3, [r3, #72] @ 0x48 + 8001dce: 2200 movs r2, #0 + 8001dd0: 601a str r2, [r3, #0] + + /* Clear the DMAMUX synchro overrun flag */ + hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; + 8001dd2: 687b ldr r3, [r7, #4] + 8001dd4: 6cdb ldr r3, [r3, #76] @ 0x4c + 8001dd6: 687a ldr r2, [r7, #4] + 8001dd8: 6d12 ldr r2, [r2, #80] @ 0x50 + 8001dda: 605a str r2, [r3, #4] + + /* Reset Request generator parameters if any */ + if (((hdma->Init.Request > 0UL) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR3))) + 8001ddc: 687b ldr r3, [r7, #4] + 8001dde: 685b ldr r3, [r3, #4] + 8001de0: 2b00 cmp r3, #0 + 8001de2: d00f beq.n 8001e04 + 8001de4: 687b ldr r3, [r7, #4] + 8001de6: 685b ldr r3, [r3, #4] + 8001de8: 2b04 cmp r3, #4 + 8001dea: d80b bhi.n 8001e04 + { + /* Initialize parameters for DMAMUX request generator : + DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask + */ + DMA_CalcDMAMUXRequestGenBaseAndMask(hdma); + 8001dec: 6878 ldr r0, [r7, #4] + 8001dee: f000 fafd bl 80023ec + + /* Reset the DMAMUX request generator register*/ + hdma->DMAmuxRequestGen->RGCR = 0U; + 8001df2: 687b ldr r3, [r7, #4] + 8001df4: 6d5b ldr r3, [r3, #84] @ 0x54 + 8001df6: 2200 movs r2, #0 + 8001df8: 601a str r2, [r3, #0] + + /* Clear the DMAMUX request generator overrun flag */ + hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; + 8001dfa: 687b ldr r3, [r7, #4] + 8001dfc: 6d9b ldr r3, [r3, #88] @ 0x58 + 8001dfe: 687a ldr r2, [r7, #4] + 8001e00: 6dd2 ldr r2, [r2, #92] @ 0x5c + 8001e02: 605a str r2, [r3, #4] + } + + hdma->DMAmuxRequestGen = NULL; + 8001e04: 687b ldr r3, [r7, #4] + 8001e06: 2200 movs r2, #0 + 8001e08: 655a str r2, [r3, #84] @ 0x54 + hdma->DMAmuxRequestGenStatus = NULL; + 8001e0a: 687b ldr r3, [r7, #4] + 8001e0c: 2200 movs r2, #0 + 8001e0e: 659a str r2, [r3, #88] @ 0x58 + hdma->DMAmuxRequestGenStatusMask = 0U; + 8001e10: 687b ldr r3, [r7, #4] + 8001e12: 2200 movs r2, #0 + 8001e14: 65da str r2, [r3, #92] @ 0x5c + + /* Clean callbacks */ + hdma->XferCpltCallback = NULL; + 8001e16: 687b ldr r3, [r7, #4] + 8001e18: 2200 movs r2, #0 + 8001e1a: 62da str r2, [r3, #44] @ 0x2c + hdma->XferHalfCpltCallback = NULL; + 8001e1c: 687b ldr r3, [r7, #4] + 8001e1e: 2200 movs r2, #0 + 8001e20: 631a str r2, [r3, #48] @ 0x30 + hdma->XferErrorCallback = NULL; + 8001e22: 687b ldr r3, [r7, #4] + 8001e24: 2200 movs r2, #0 + 8001e26: 635a str r2, [r3, #52] @ 0x34 + hdma->XferAbortCallback = NULL; + 8001e28: 687b ldr r3, [r7, #4] + 8001e2a: 2200 movs r2, #0 + 8001e2c: 639a str r2, [r3, #56] @ 0x38 + + /* Initialize the error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + 8001e2e: 687b ldr r3, [r7, #4] + 8001e30: 2200 movs r2, #0 + 8001e32: 63da str r2, [r3, #60] @ 0x3c + + /* Initialize the DMA state */ + hdma->State = HAL_DMA_STATE_RESET; + 8001e34: 687b ldr r3, [r7, #4] + 8001e36: 2200 movs r2, #0 + 8001e38: f883 2025 strb.w r2, [r3, #37] @ 0x25 + + /* Release Lock */ + __HAL_UNLOCK(hdma); + 8001e3c: 687b ldr r3, [r7, #4] + 8001e3e: 2200 movs r2, #0 + 8001e40: f883 2024 strb.w r2, [r3, #36] @ 0x24 + + return HAL_OK; + 8001e44: 2300 movs r3, #0 +} + 8001e46: 4618 mov r0, r3 + 8001e48: 3708 adds r7, #8 + 8001e4a: 46bd mov sp, r7 + 8001e4c: bd80 pop {r7, pc} + 8001e4e: bf00 nop + 8001e50: 40020407 .word 0x40020407 + 8001e54: bffdfff8 .word 0xbffdfff8 + 8001e58: cccccccd .word 0xcccccccd + 8001e5c: 40020000 .word 0x40020000 + 8001e60: bffdfbf8 .word 0xbffdfbf8 + 8001e64: 40020400 .word 0x40020400 + +08001e68 : + * @param DataLength The length of data to be transferred from source to destination + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, + uint32_t DataLength) +{ + 8001e68: b580 push {r7, lr} + 8001e6a: b086 sub sp, #24 + 8001e6c: af00 add r7, sp, #0 + 8001e6e: 60f8 str r0, [r7, #12] + 8001e70: 60b9 str r1, [r7, #8] + 8001e72: 607a str r2, [r7, #4] + 8001e74: 603b str r3, [r7, #0] + HAL_StatusTypeDef status = HAL_OK; + 8001e76: 2300 movs r3, #0 + 8001e78: 75fb strb r3, [r7, #23] + + /* Check the parameters */ + assert_param(IS_DMA_BUFFER_SIZE(DataLength)); + + /* Process locked */ + __HAL_LOCK(hdma); + 8001e7a: 68fb ldr r3, [r7, #12] + 8001e7c: f893 3024 ldrb.w r3, [r3, #36] @ 0x24 + 8001e80: 2b01 cmp r3, #1 + 8001e82: d101 bne.n 8001e88 + 8001e84: 2302 movs r3, #2 + 8001e86: e069 b.n 8001f5c + 8001e88: 68fb ldr r3, [r7, #12] + 8001e8a: 2201 movs r2, #1 + 8001e8c: f883 2024 strb.w r2, [r3, #36] @ 0x24 + + if (hdma->State == HAL_DMA_STATE_READY) + 8001e90: 68fb ldr r3, [r7, #12] + 8001e92: f893 3025 ldrb.w r3, [r3, #37] @ 0x25 + 8001e96: b2db uxtb r3, r3 + 8001e98: 2b01 cmp r3, #1 + 8001e9a: d155 bne.n 8001f48 + { + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_BUSY; + 8001e9c: 68fb ldr r3, [r7, #12] + 8001e9e: 2202 movs r2, #2 + 8001ea0: f883 2025 strb.w r2, [r3, #37] @ 0x25 + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + 8001ea4: 68fb ldr r3, [r7, #12] + 8001ea6: 2200 movs r2, #0 + 8001ea8: 63da str r2, [r3, #60] @ 0x3c + + /* Disable the peripheral */ + __HAL_DMA_DISABLE(hdma); + 8001eaa: 68fb ldr r3, [r7, #12] + 8001eac: 681b ldr r3, [r3, #0] + 8001eae: 681a ldr r2, [r3, #0] + 8001eb0: 68fb ldr r3, [r7, #12] + 8001eb2: 681b ldr r3, [r3, #0] + 8001eb4: f022 0201 bic.w r2, r2, #1 + 8001eb8: 601a str r2, [r3, #0] + + /* Configure the source, destination address and the data length & clear flags*/ + DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); + 8001eba: 683b ldr r3, [r7, #0] + 8001ebc: 687a ldr r2, [r7, #4] + 8001ebe: 68b9 ldr r1, [r7, #8] + 8001ec0: 68f8 ldr r0, [r7, #12] + 8001ec2: f000 fa0d bl 80022e0 + + /* Enable the transfer complete interrupt */ + /* Enable the transfer Error interrupt */ + if (NULL != hdma->XferHalfCpltCallback) + 8001ec6: 68fb ldr r3, [r7, #12] + 8001ec8: 6b1b ldr r3, [r3, #48] @ 0x30 + 8001eca: 2b00 cmp r3, #0 + 8001ecc: d008 beq.n 8001ee0 + { + /* Enable the Half transfer complete interrupt as well */ + __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); + 8001ece: 68fb ldr r3, [r7, #12] + 8001ed0: 681b ldr r3, [r3, #0] + 8001ed2: 681a ldr r2, [r3, #0] + 8001ed4: 68fb ldr r3, [r7, #12] + 8001ed6: 681b ldr r3, [r3, #0] + 8001ed8: f042 020e orr.w r2, r2, #14 + 8001edc: 601a str r2, [r3, #0] + 8001ede: e00f b.n 8001f00 + } + else + { + __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); + 8001ee0: 68fb ldr r3, [r7, #12] + 8001ee2: 681b ldr r3, [r3, #0] + 8001ee4: 681a ldr r2, [r3, #0] + 8001ee6: 68fb ldr r3, [r7, #12] + 8001ee8: 681b ldr r3, [r3, #0] + 8001eea: f022 0204 bic.w r2, r2, #4 + 8001eee: 601a str r2, [r3, #0] + __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE)); + 8001ef0: 68fb ldr r3, [r7, #12] + 8001ef2: 681b ldr r3, [r3, #0] + 8001ef4: 681a ldr r2, [r3, #0] + 8001ef6: 68fb ldr r3, [r7, #12] + 8001ef8: 681b ldr r3, [r3, #0] + 8001efa: f042 020a orr.w r2, r2, #10 + 8001efe: 601a str r2, [r3, #0] + } + + /* Check if DMAMUX Synchronization is enabled*/ + if ((hdma->DMAmuxChannel->CCR & DMAMUX_CxCR_SE) != 0U) + 8001f00: 68fb ldr r3, [r7, #12] + 8001f02: 6c9b ldr r3, [r3, #72] @ 0x48 + 8001f04: 681b ldr r3, [r3, #0] + 8001f06: f403 3380 and.w r3, r3, #65536 @ 0x10000 + 8001f0a: 2b00 cmp r3, #0 + 8001f0c: d007 beq.n 8001f1e + { + /* Enable DMAMUX sync overrun IT*/ + hdma->DMAmuxChannel->CCR |= DMAMUX_CxCR_SOIE; + 8001f0e: 68fb ldr r3, [r7, #12] + 8001f10: 6c9b ldr r3, [r3, #72] @ 0x48 + 8001f12: 681a ldr r2, [r3, #0] + 8001f14: 68fb ldr r3, [r7, #12] + 8001f16: 6c9b ldr r3, [r3, #72] @ 0x48 + 8001f18: f442 7280 orr.w r2, r2, #256 @ 0x100 + 8001f1c: 601a str r2, [r3, #0] + } + + if (hdma->DMAmuxRequestGen != NULL) + 8001f1e: 68fb ldr r3, [r7, #12] + 8001f20: 6d5b ldr r3, [r3, #84] @ 0x54 + 8001f22: 2b00 cmp r3, #0 + 8001f24: d007 beq.n 8001f36 + { + /* if using DMAMUX request generator, enable the DMAMUX request generator overrun IT*/ + /* enable the request gen overrun IT*/ + hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE; + 8001f26: 68fb ldr r3, [r7, #12] + 8001f28: 6d5b ldr r3, [r3, #84] @ 0x54 + 8001f2a: 681a ldr r2, [r3, #0] + 8001f2c: 68fb ldr r3, [r7, #12] + 8001f2e: 6d5b ldr r3, [r3, #84] @ 0x54 + 8001f30: f442 7280 orr.w r2, r2, #256 @ 0x100 + 8001f34: 601a str r2, [r3, #0] + } + + /* Enable the Peripheral */ + __HAL_DMA_ENABLE(hdma); + 8001f36: 68fb ldr r3, [r7, #12] + 8001f38: 681b ldr r3, [r3, #0] + 8001f3a: 681a ldr r2, [r3, #0] + 8001f3c: 68fb ldr r3, [r7, #12] + 8001f3e: 681b ldr r3, [r3, #0] + 8001f40: f042 0201 orr.w r2, r2, #1 + 8001f44: 601a str r2, [r3, #0] + 8001f46: e008 b.n 8001f5a + } + else + { + /* Change the error code */ + hdma->ErrorCode = HAL_DMA_ERROR_BUSY; + 8001f48: 68fb ldr r3, [r7, #12] + 8001f4a: 2280 movs r2, #128 @ 0x80 + 8001f4c: 63da str r2, [r3, #60] @ 0x3c + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + 8001f4e: 68fb ldr r3, [r7, #12] + 8001f50: 2200 movs r2, #0 + 8001f52: f883 2024 strb.w r2, [r3, #36] @ 0x24 + + /* Return error status */ + status = HAL_ERROR; + 8001f56: 2301 movs r3, #1 + 8001f58: 75fb strb r3, [r7, #23] + } + + return status; + 8001f5a: 7dfb ldrb r3, [r7, #23] +} + 8001f5c: 4618 mov r0, r3 + 8001f5e: 3718 adds r7, #24 + 8001f60: 46bd mov sp, r7 + 8001f62: bd80 pop {r7, pc} + +08001f64 : + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) +{ + 8001f64: b480 push {r7} + 8001f66: b083 sub sp, #12 + 8001f68: af00 add r7, sp, #0 + 8001f6a: 6078 str r0, [r7, #4] + /* Check the DMA peripheral handle */ + if (NULL == hdma) + 8001f6c: 687b ldr r3, [r7, #4] + 8001f6e: 2b00 cmp r3, #0 + 8001f70: d101 bne.n 8001f76 + { + return HAL_ERROR; + 8001f72: 2301 movs r3, #1 + 8001f74: e04f b.n 8002016 + } + + /* Check the DMA peripheral state */ + if (hdma->State != HAL_DMA_STATE_BUSY) + 8001f76: 687b ldr r3, [r7, #4] + 8001f78: f893 3025 ldrb.w r3, [r3, #37] @ 0x25 + 8001f7c: b2db uxtb r3, r3 + 8001f7e: 2b02 cmp r3, #2 + 8001f80: d008 beq.n 8001f94 + { + hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + 8001f82: 687b ldr r3, [r7, #4] + 8001f84: 2204 movs r2, #4 + 8001f86: 63da str r2, [r3, #60] @ 0x3c + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + 8001f88: 687b ldr r3, [r7, #4] + 8001f8a: 2200 movs r2, #0 + 8001f8c: f883 2024 strb.w r2, [r3, #36] @ 0x24 + + return HAL_ERROR; + 8001f90: 2301 movs r3, #1 + 8001f92: e040 b.n 8002016 + } + else + { + /* Disable the channel */ + __HAL_DMA_DISABLE(hdma); + 8001f94: 687b ldr r3, [r7, #4] + 8001f96: 681b ldr r3, [r3, #0] + 8001f98: 681a ldr r2, [r3, #0] + 8001f9a: 687b ldr r3, [r7, #4] + 8001f9c: 681b ldr r3, [r3, #0] + 8001f9e: f022 0201 bic.w r2, r2, #1 + 8001fa2: 601a str r2, [r3, #0] + + /* Disable DMA IT */ + __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); + 8001fa4: 687b ldr r3, [r7, #4] + 8001fa6: 681b ldr r3, [r3, #0] + 8001fa8: 681a ldr r2, [r3, #0] + 8001faa: 687b ldr r3, [r7, #4] + 8001fac: 681b ldr r3, [r3, #0] + 8001fae: f022 020e bic.w r2, r2, #14 + 8001fb2: 601a str r2, [r3, #0] + + /* disable the DMAMUX sync overrun IT*/ + hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; + 8001fb4: 687b ldr r3, [r7, #4] + 8001fb6: 6c9b ldr r3, [r3, #72] @ 0x48 + 8001fb8: 681a ldr r2, [r3, #0] + 8001fba: 687b ldr r3, [r7, #4] + 8001fbc: 6c9b ldr r3, [r3, #72] @ 0x48 + 8001fbe: f422 7280 bic.w r2, r2, #256 @ 0x100 + 8001fc2: 601a str r2, [r3, #0] + + /* Clear all flags */ + hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU)); + 8001fc4: 687b ldr r3, [r7, #4] + 8001fc6: 6c5b ldr r3, [r3, #68] @ 0x44 + 8001fc8: f003 021c and.w r2, r3, #28 + 8001fcc: 687b ldr r3, [r7, #4] + 8001fce: 6c1b ldr r3, [r3, #64] @ 0x40 + 8001fd0: 2101 movs r1, #1 + 8001fd2: fa01 f202 lsl.w r2, r1, r2 + 8001fd6: 605a str r2, [r3, #4] + + /* Clear the DMAMUX synchro overrun flag */ + hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; + 8001fd8: 687b ldr r3, [r7, #4] + 8001fda: 6cdb ldr r3, [r3, #76] @ 0x4c + 8001fdc: 687a ldr r2, [r7, #4] + 8001fde: 6d12 ldr r2, [r2, #80] @ 0x50 + 8001fe0: 605a str r2, [r3, #4] + + if (hdma->DMAmuxRequestGen != NULL) + 8001fe2: 687b ldr r3, [r7, #4] + 8001fe4: 6d5b ldr r3, [r3, #84] @ 0x54 + 8001fe6: 2b00 cmp r3, #0 + 8001fe8: d00c beq.n 8002004 + { + /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/ + /* disable the request gen overrun IT*/ + hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE; + 8001fea: 687b ldr r3, [r7, #4] + 8001fec: 6d5b ldr r3, [r3, #84] @ 0x54 + 8001fee: 681a ldr r2, [r3, #0] + 8001ff0: 687b ldr r3, [r7, #4] + 8001ff2: 6d5b ldr r3, [r3, #84] @ 0x54 + 8001ff4: f422 7280 bic.w r2, r2, #256 @ 0x100 + 8001ff8: 601a str r2, [r3, #0] + + /* Clear the DMAMUX request generator overrun flag */ + hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; + 8001ffa: 687b ldr r3, [r7, #4] + 8001ffc: 6d9b ldr r3, [r3, #88] @ 0x58 + 8001ffe: 687a ldr r2, [r7, #4] + 8002000: 6dd2 ldr r2, [r2, #92] @ 0x5c + 8002002: 605a str r2, [r3, #4] + } + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + 8002004: 687b ldr r3, [r7, #4] + 8002006: 2201 movs r2, #1 + 8002008: f883 2025 strb.w r2, [r3, #37] @ 0x25 + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + 800200c: 687b ldr r3, [r7, #4] + 800200e: 2200 movs r2, #0 + 8002010: f883 2024 strb.w r2, [r3, #36] @ 0x24 + } + + return HAL_OK; + 8002014: 2300 movs r3, #0 +} + 8002016: 4618 mov r0, r3 + 8002018: 370c adds r7, #12 + 800201a: 46bd mov sp, r7 + 800201c: bc80 pop {r7} + 800201e: 4770 bx lr + +08002020 : + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) +{ + 8002020: b580 push {r7, lr} + 8002022: b084 sub sp, #16 + 8002024: af00 add r7, sp, #0 + 8002026: 6078 str r0, [r7, #4] + HAL_StatusTypeDef status = HAL_OK; + 8002028: 2300 movs r3, #0 + 800202a: 73fb strb r3, [r7, #15] + + if (hdma->State != HAL_DMA_STATE_BUSY) + 800202c: 687b ldr r3, [r7, #4] + 800202e: f893 3025 ldrb.w r3, [r3, #37] @ 0x25 + 8002032: b2db uxtb r3, r3 + 8002034: 2b02 cmp r3, #2 + 8002036: d005 beq.n 8002044 + { + /* no transfer ongoing */ + hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + 8002038: 687b ldr r3, [r7, #4] + 800203a: 2204 movs r2, #4 + 800203c: 63da str r2, [r3, #60] @ 0x3c + + status = HAL_ERROR; + 800203e: 2301 movs r3, #1 + 8002040: 73fb strb r3, [r7, #15] + 8002042: e047 b.n 80020d4 + } + else + { + /* Disable the channel */ + __HAL_DMA_DISABLE(hdma); + 8002044: 687b ldr r3, [r7, #4] + 8002046: 681b ldr r3, [r3, #0] + 8002048: 681a ldr r2, [r3, #0] + 800204a: 687b ldr r3, [r7, #4] + 800204c: 681b ldr r3, [r3, #0] + 800204e: f022 0201 bic.w r2, r2, #1 + 8002052: 601a str r2, [r3, #0] + + /* Disable DMA IT */ + __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); + 8002054: 687b ldr r3, [r7, #4] + 8002056: 681b ldr r3, [r3, #0] + 8002058: 681a ldr r2, [r3, #0] + 800205a: 687b ldr r3, [r7, #4] + 800205c: 681b ldr r3, [r3, #0] + 800205e: f022 020e bic.w r2, r2, #14 + 8002062: 601a str r2, [r3, #0] + + /* disable the DMAMUX sync overrun IT*/ + hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; + 8002064: 687b ldr r3, [r7, #4] + 8002066: 6c9b ldr r3, [r3, #72] @ 0x48 + 8002068: 681a ldr r2, [r3, #0] + 800206a: 687b ldr r3, [r7, #4] + 800206c: 6c9b ldr r3, [r3, #72] @ 0x48 + 800206e: f422 7280 bic.w r2, r2, #256 @ 0x100 + 8002072: 601a str r2, [r3, #0] + + /* Clear all flags */ + hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU)); + 8002074: 687b ldr r3, [r7, #4] + 8002076: 6c5b ldr r3, [r3, #68] @ 0x44 + 8002078: f003 021c and.w r2, r3, #28 + 800207c: 687b ldr r3, [r7, #4] + 800207e: 6c1b ldr r3, [r3, #64] @ 0x40 + 8002080: 2101 movs r1, #1 + 8002082: fa01 f202 lsl.w r2, r1, r2 + 8002086: 605a str r2, [r3, #4] + + /* Clear the DMAMUX synchro overrun flag */ + hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; + 8002088: 687b ldr r3, [r7, #4] + 800208a: 6cdb ldr r3, [r3, #76] @ 0x4c + 800208c: 687a ldr r2, [r7, #4] + 800208e: 6d12 ldr r2, [r2, #80] @ 0x50 + 8002090: 605a str r2, [r3, #4] + + if (hdma->DMAmuxRequestGen != NULL) + 8002092: 687b ldr r3, [r7, #4] + 8002094: 6d5b ldr r3, [r3, #84] @ 0x54 + 8002096: 2b00 cmp r3, #0 + 8002098: d00c beq.n 80020b4 + { + /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/ + /* disable the request gen overrun IT*/ + hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE; + 800209a: 687b ldr r3, [r7, #4] + 800209c: 6d5b ldr r3, [r3, #84] @ 0x54 + 800209e: 681a ldr r2, [r3, #0] + 80020a0: 687b ldr r3, [r7, #4] + 80020a2: 6d5b ldr r3, [r3, #84] @ 0x54 + 80020a4: f422 7280 bic.w r2, r2, #256 @ 0x100 + 80020a8: 601a str r2, [r3, #0] + + /* Clear the DMAMUX request generator overrun flag */ + hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; + 80020aa: 687b ldr r3, [r7, #4] + 80020ac: 6d9b ldr r3, [r3, #88] @ 0x58 + 80020ae: 687a ldr r2, [r7, #4] + 80020b0: 6dd2 ldr r2, [r2, #92] @ 0x5c + 80020b2: 605a str r2, [r3, #4] + } + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + 80020b4: 687b ldr r3, [r7, #4] + 80020b6: 2201 movs r2, #1 + 80020b8: f883 2025 strb.w r2, [r3, #37] @ 0x25 + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + 80020bc: 687b ldr r3, [r7, #4] + 80020be: 2200 movs r2, #0 + 80020c0: f883 2024 strb.w r2, [r3, #36] @ 0x24 + + /* Call User Abort callback */ + if (hdma->XferAbortCallback != NULL) + 80020c4: 687b ldr r3, [r7, #4] + 80020c6: 6b9b ldr r3, [r3, #56] @ 0x38 + 80020c8: 2b00 cmp r3, #0 + 80020ca: d003 beq.n 80020d4 + { + hdma->XferAbortCallback(hdma); + 80020cc: 687b ldr r3, [r7, #4] + 80020ce: 6b9b ldr r3, [r3, #56] @ 0x38 + 80020d0: 6878 ldr r0, [r7, #4] + 80020d2: 4798 blx r3 + } + } + return status; + 80020d4: 7bfb ldrb r3, [r7, #15] +} + 80020d6: 4618 mov r0, r3 + 80020d8: 3710 adds r7, #16 + 80020da: 46bd mov sp, r7 + 80020dc: bd80 pop {r7, pc} + ... + +080020e0 : + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @retval None + */ +void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) +{ + 80020e0: b580 push {r7, lr} + 80020e2: b084 sub sp, #16 + 80020e4: af00 add r7, sp, #0 + 80020e6: 6078 str r0, [r7, #4] + uint32_t flag_it = hdma->DmaBaseAddress->ISR; + 80020e8: 687b ldr r3, [r7, #4] + 80020ea: 6c1b ldr r3, [r3, #64] @ 0x40 + 80020ec: 681b ldr r3, [r3, #0] + 80020ee: 60fb str r3, [r7, #12] + uint32_t source_it = hdma->Instance->CCR; + 80020f0: 687b ldr r3, [r7, #4] + 80020f2: 681b ldr r3, [r3, #0] + 80020f4: 681b ldr r3, [r3, #0] + 80020f6: 60bb str r3, [r7, #8] + + /* Half Transfer Complete Interrupt management ******************************/ + if (((flag_it & (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1CU))) != 0U) && ((source_it & DMA_IT_HT) != 0U)) + 80020f8: 687b ldr r3, [r7, #4] + 80020fa: 6c5b ldr r3, [r3, #68] @ 0x44 + 80020fc: f003 031c and.w r3, r3, #28 + 8002100: 2204 movs r2, #4 + 8002102: 409a lsls r2, r3 + 8002104: 68fb ldr r3, [r7, #12] + 8002106: 4013 ands r3, r2 + 8002108: 2b00 cmp r3, #0 + 800210a: d027 beq.n 800215c + 800210c: 68bb ldr r3, [r7, #8] + 800210e: f003 0304 and.w r3, r3, #4 + 8002112: 2b00 cmp r3, #0 + 8002114: d022 beq.n 800215c + { + /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */ + if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) + 8002116: 687b ldr r3, [r7, #4] + 8002118: 681b ldr r3, [r3, #0] + 800211a: 681b ldr r3, [r3, #0] + 800211c: f003 0320 and.w r3, r3, #32 + 8002120: 2b00 cmp r3, #0 + 8002122: d107 bne.n 8002134 + { + /* Disable the half transfer interrupt */ + __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); + 8002124: 687b ldr r3, [r7, #4] + 8002126: 681b ldr r3, [r3, #0] + 8002128: 681a ldr r2, [r3, #0] + 800212a: 687b ldr r3, [r7, #4] + 800212c: 681b ldr r3, [r3, #0] + 800212e: f022 0204 bic.w r2, r2, #4 + 8002132: 601a str r2, [r3, #0] + } + /* Clear the half transfer complete flag */ + hdma->DmaBaseAddress->IFCR = DMA_ISR_HTIF1 << (hdma->ChannelIndex & 0x1CU); + 8002134: 687b ldr r3, [r7, #4] + 8002136: 6c5b ldr r3, [r3, #68] @ 0x44 + 8002138: f003 021c and.w r2, r3, #28 + 800213c: 687b ldr r3, [r7, #4] + 800213e: 6c1b ldr r3, [r3, #64] @ 0x40 + 8002140: 2104 movs r1, #4 + 8002142: fa01 f202 lsl.w r2, r1, r2 + 8002146: 605a str r2, [r3, #4] + + /* DMA peripheral state is not updated in Half Transfer */ + /* but in Transfer Complete case */ + + if (hdma->XferHalfCpltCallback != NULL) + 8002148: 687b ldr r3, [r7, #4] + 800214a: 6b1b ldr r3, [r3, #48] @ 0x30 + 800214c: 2b00 cmp r3, #0 + 800214e: f000 8081 beq.w 8002254 + { + /* Half transfer callback */ + hdma->XferHalfCpltCallback(hdma); + 8002152: 687b ldr r3, [r7, #4] + 8002154: 6b1b ldr r3, [r3, #48] @ 0x30 + 8002156: 6878 ldr r0, [r7, #4] + 8002158: 4798 blx r3 + if (hdma->XferHalfCpltCallback != NULL) + 800215a: e07b b.n 8002254 + } + } + + /* Transfer Complete Interrupt management ***********************************/ + else if ((0U != (flag_it & (DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1CU)))) && (0U != (source_it & DMA_IT_TC))) + 800215c: 687b ldr r3, [r7, #4] + 800215e: 6c5b ldr r3, [r3, #68] @ 0x44 + 8002160: f003 031c and.w r3, r3, #28 + 8002164: 2202 movs r2, #2 + 8002166: 409a lsls r2, r3 + 8002168: 68fb ldr r3, [r7, #12] + 800216a: 4013 ands r3, r2 + 800216c: 2b00 cmp r3, #0 + 800216e: d03d beq.n 80021ec + 8002170: 68bb ldr r3, [r7, #8] + 8002172: f003 0302 and.w r3, r3, #2 + 8002176: 2b00 cmp r3, #0 + 8002178: d038 beq.n 80021ec + { + if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) + 800217a: 687b ldr r3, [r7, #4] + 800217c: 681b ldr r3, [r3, #0] + 800217e: 681b ldr r3, [r3, #0] + 8002180: f003 0320 and.w r3, r3, #32 + 8002184: 2b00 cmp r3, #0 + 8002186: d10b bne.n 80021a0 + { + /* Disable the transfer complete and error interrupt */ + __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC); + 8002188: 687b ldr r3, [r7, #4] + 800218a: 681b ldr r3, [r3, #0] + 800218c: 681a ldr r2, [r3, #0] + 800218e: 687b ldr r3, [r7, #4] + 8002190: 681b ldr r3, [r3, #0] + 8002192: f022 020a bic.w r2, r2, #10 + 8002196: 601a str r2, [r3, #0] + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + 8002198: 687b ldr r3, [r7, #4] + 800219a: 2201 movs r2, #1 + 800219c: f883 2025 strb.w r2, [r3, #37] @ 0x25 + } + /* Clear the transfer complete flag */ + __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1CU))); + 80021a0: 687b ldr r3, [r7, #4] + 80021a2: 681b ldr r3, [r3, #0] + 80021a4: 461a mov r2, r3 + 80021a6: 4b2e ldr r3, [pc, #184] @ (8002260 ) + 80021a8: 429a cmp r2, r3 + 80021aa: d909 bls.n 80021c0 + 80021ac: 687b ldr r3, [r7, #4] + 80021ae: 6c5b ldr r3, [r3, #68] @ 0x44 + 80021b0: f003 031c and.w r3, r3, #28 + 80021b4: 4a2b ldr r2, [pc, #172] @ (8002264 ) + 80021b6: 2102 movs r1, #2 + 80021b8: fa01 f303 lsl.w r3, r1, r3 + 80021bc: 6053 str r3, [r2, #4] + 80021be: e008 b.n 80021d2 + 80021c0: 687b ldr r3, [r7, #4] + 80021c2: 6c5b ldr r3, [r3, #68] @ 0x44 + 80021c4: f003 031c and.w r3, r3, #28 + 80021c8: 4a27 ldr r2, [pc, #156] @ (8002268 ) + 80021ca: 2102 movs r1, #2 + 80021cc: fa01 f303 lsl.w r3, r1, r3 + 80021d0: 6053 str r3, [r2, #4] + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + 80021d2: 687b ldr r3, [r7, #4] + 80021d4: 2200 movs r2, #0 + 80021d6: f883 2024 strb.w r2, [r3, #36] @ 0x24 + + if (hdma->XferCpltCallback != NULL) + 80021da: 687b ldr r3, [r7, #4] + 80021dc: 6adb ldr r3, [r3, #44] @ 0x2c + 80021de: 2b00 cmp r3, #0 + 80021e0: d038 beq.n 8002254 + { + /* Transfer complete callback */ + hdma->XferCpltCallback(hdma); + 80021e2: 687b ldr r3, [r7, #4] + 80021e4: 6adb ldr r3, [r3, #44] @ 0x2c + 80021e6: 6878 ldr r0, [r7, #4] + 80021e8: 4798 blx r3 + if (hdma->XferCpltCallback != NULL) + 80021ea: e033 b.n 8002254 + } + } + + /* Transfer Error Interrupt management **************************************/ + else if (((flag_it & (DMA_FLAG_TE1 << (hdma->ChannelIndex & 0x1CU))) != 0U) && ((source_it & DMA_IT_TE) != 0U)) + 80021ec: 687b ldr r3, [r7, #4] + 80021ee: 6c5b ldr r3, [r3, #68] @ 0x44 + 80021f0: f003 031c and.w r3, r3, #28 + 80021f4: 2208 movs r2, #8 + 80021f6: 409a lsls r2, r3 + 80021f8: 68fb ldr r3, [r7, #12] + 80021fa: 4013 ands r3, r2 + 80021fc: 2b00 cmp r3, #0 + 80021fe: d02a beq.n 8002256 + 8002200: 68bb ldr r3, [r7, #8] + 8002202: f003 0308 and.w r3, r3, #8 + 8002206: 2b00 cmp r3, #0 + 8002208: d025 beq.n 8002256 + { + /* When a DMA transfer error occurs */ + /* A hardware clear of its EN bits is performed */ + /* Disable ALL DMA IT */ + __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); + 800220a: 687b ldr r3, [r7, #4] + 800220c: 681b ldr r3, [r3, #0] + 800220e: 681a ldr r2, [r3, #0] + 8002210: 687b ldr r3, [r7, #4] + 8002212: 681b ldr r3, [r3, #0] + 8002214: f022 020e bic.w r2, r2, #14 + 8002218: 601a str r2, [r3, #0] + + /* Clear all flags */ + hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU)); + 800221a: 687b ldr r3, [r7, #4] + 800221c: 6c5b ldr r3, [r3, #68] @ 0x44 + 800221e: f003 021c and.w r2, r3, #28 + 8002222: 687b ldr r3, [r7, #4] + 8002224: 6c1b ldr r3, [r3, #64] @ 0x40 + 8002226: 2101 movs r1, #1 + 8002228: fa01 f202 lsl.w r2, r1, r2 + 800222c: 605a str r2, [r3, #4] + + /* Update error code */ + hdma->ErrorCode = HAL_DMA_ERROR_TE; + 800222e: 687b ldr r3, [r7, #4] + 8002230: 2201 movs r2, #1 + 8002232: 63da str r2, [r3, #60] @ 0x3c + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + 8002234: 687b ldr r3, [r7, #4] + 8002236: 2201 movs r2, #1 + 8002238: f883 2025 strb.w r2, [r3, #37] @ 0x25 + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + 800223c: 687b ldr r3, [r7, #4] + 800223e: 2200 movs r2, #0 + 8002240: f883 2024 strb.w r2, [r3, #36] @ 0x24 + + if (hdma->XferErrorCallback != NULL) + 8002244: 687b ldr r3, [r7, #4] + 8002246: 6b5b ldr r3, [r3, #52] @ 0x34 + 8002248: 2b00 cmp r3, #0 + 800224a: d004 beq.n 8002256 + { + /* Transfer error callback */ + hdma->XferErrorCallback(hdma); + 800224c: 687b ldr r3, [r7, #4] + 800224e: 6b5b ldr r3, [r3, #52] @ 0x34 + 8002250: 6878 ldr r0, [r7, #4] + 8002252: 4798 blx r3 + } + else + { + /* Nothing To Do */ + } + return; + 8002254: bf00 nop + 8002256: bf00 nop +} + 8002258: 3710 adds r7, #16 + 800225a: 46bd mov sp, r7 + 800225c: bd80 pop {r7, pc} + 800225e: bf00 nop + 8002260: 40020080 .word 0x40020080 + 8002264: 40020400 .word 0x40020400 + 8002268: 40020000 .word 0x40020000 + +0800226c : + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @retval DMA Error Code + */ +uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma) +{ + 800226c: b480 push {r7} + 800226e: b083 sub sp, #12 + 8002270: af00 add r7, sp, #0 + 8002272: 6078 str r0, [r7, #4] + /* Return the DMA error code */ + return hdma->ErrorCode; + 8002274: 687b ldr r3, [r7, #4] + 8002276: 6bdb ldr r3, [r3, #60] @ 0x3c +} + 8002278: 4618 mov r0, r3 + 800227a: 370c adds r7, #12 + 800227c: 46bd mov sp, r7 + 800227e: bc80 pop {r7} + 8002280: 4770 bx lr + +08002282 : + * @param ChannelAttributes specifies the DMA channel secure/privilege attributes. + * This parameter can be a one or a combination of @ref DMA_Channel_Attributes + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_DMA_ConfigChannelAttributes(DMA_HandleTypeDef *hdma, uint32_t ChannelAttributes) +{ + 8002282: b480 push {r7} + 8002284: b085 sub sp, #20 + 8002286: af00 add r7, sp, #0 + 8002288: 6078 str r0, [r7, #4] + 800228a: 6039 str r1, [r7, #0] + HAL_StatusTypeDef status = HAL_OK; + 800228c: 2300 movs r3, #0 + 800228e: 72fb strb r3, [r7, #11] +#if defined (CORE_CM0PLUS) + uint32_t ccr_SECM; +#endif /* CORE_CM0PLUS */ + + /* Check the DMA peripheral handle */ + if (hdma == NULL) + 8002290: 687b ldr r3, [r7, #4] + 8002292: 2b00 cmp r3, #0 + 8002294: d103 bne.n 800229e + { + status = HAL_ERROR; + 8002296: 2301 movs r3, #1 + 8002298: 72fb strb r3, [r7, #11] + return status; + 800229a: 7afb ldrb r3, [r7, #11] + 800229c: e01b b.n 80022d6 + + /* Check the parameters */ + assert_param(IS_DMA_ATTRIBUTES(ChannelAttributes)); + + /* Read CCR register */ + ccr = READ_REG(hdma->Instance->CCR); + 800229e: 687b ldr r3, [r7, #4] + 80022a0: 681b ldr r3, [r3, #0] + 80022a2: 681b ldr r3, [r3, #0] + 80022a4: 60fb str r3, [r7, #12] + + /* Apply any requested privilege/non-privilege attributes */ + if ((ChannelAttributes & DMA_CHANNEL_ATTR_PRIV_MASK) != 0U) + 80022a6: 683b ldr r3, [r7, #0] + 80022a8: f003 0310 and.w r3, r3, #16 + 80022ac: 2b00 cmp r3, #0 + 80022ae: d00d beq.n 80022cc + { + if ((ChannelAttributes & DMA_CCR_PRIV) != 0U) + 80022b0: 683b ldr r3, [r7, #0] + 80022b2: f403 1380 and.w r3, r3, #1048576 @ 0x100000 + 80022b6: 2b00 cmp r3, #0 + 80022b8: d004 beq.n 80022c4 + { + SET_BIT(ccr, DMA_CCR_PRIV); + 80022ba: 68fb ldr r3, [r7, #12] + 80022bc: f443 1380 orr.w r3, r3, #1048576 @ 0x100000 + 80022c0: 60fb str r3, [r7, #12] + 80022c2: e003 b.n 80022cc + } + else + { + CLEAR_BIT(ccr, DMA_CCR_PRIV); + 80022c4: 68fb ldr r3, [r7, #12] + 80022c6: f423 1380 bic.w r3, r3, #1048576 @ 0x100000 + 80022ca: 60fb str r3, [r7, #12] + } + +#endif /* CORE_CM0PLUS */ + + /* Update CCR Register: PRIV, SECM, SCEC, DSEC bits */ + WRITE_REG(hdma->Instance->CCR, ccr); + 80022cc: 687b ldr r3, [r7, #4] + 80022ce: 681b ldr r3, [r3, #0] + 80022d0: 68fa ldr r2, [r7, #12] + 80022d2: 601a str r2, [r3, #0] + + return status; + 80022d4: 7afb ldrb r3, [r7, #11] +} + 80022d6: 4618 mov r0, r3 + 80022d8: 3714 adds r7, #20 + 80022da: 46bd mov sp, r7 + 80022dc: bc80 pop {r7} + 80022de: 4770 bx lr + +080022e0 : + * @param DstAddress The destination memory Buffer address + * @param DataLength The length of data to be transferred from source to destination + * @retval HAL status + */ +static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) +{ + 80022e0: b480 push {r7} + 80022e2: b085 sub sp, #20 + 80022e4: af00 add r7, sp, #0 + 80022e6: 60f8 str r0, [r7, #12] + 80022e8: 60b9 str r1, [r7, #8] + 80022ea: 607a str r2, [r7, #4] + 80022ec: 603b str r3, [r7, #0] + /* Clear the DMAMUX synchro overrun flag */ + hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; + 80022ee: 68fb ldr r3, [r7, #12] + 80022f0: 6cdb ldr r3, [r3, #76] @ 0x4c + 80022f2: 68fa ldr r2, [r7, #12] + 80022f4: 6d12 ldr r2, [r2, #80] @ 0x50 + 80022f6: 605a str r2, [r3, #4] + + if (hdma->DMAmuxRequestGen != NULL) + 80022f8: 68fb ldr r3, [r7, #12] + 80022fa: 6d5b ldr r3, [r3, #84] @ 0x54 + 80022fc: 2b00 cmp r3, #0 + 80022fe: d004 beq.n 800230a + { + /* Clear the DMAMUX request generator overrun flag */ + hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; + 8002300: 68fb ldr r3, [r7, #12] + 8002302: 6d9b ldr r3, [r3, #88] @ 0x58 + 8002304: 68fa ldr r2, [r7, #12] + 8002306: 6dd2 ldr r2, [r2, #92] @ 0x5c + 8002308: 605a str r2, [r3, #4] + } + + /* Clear all flags */ + hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU)); + 800230a: 68fb ldr r3, [r7, #12] + 800230c: 6c5b ldr r3, [r3, #68] @ 0x44 + 800230e: f003 021c and.w r2, r3, #28 + 8002312: 68fb ldr r3, [r7, #12] + 8002314: 6c1b ldr r3, [r3, #64] @ 0x40 + 8002316: 2101 movs r1, #1 + 8002318: fa01 f202 lsl.w r2, r1, r2 + 800231c: 605a str r2, [r3, #4] + + /* Configure DMA Channel data length */ + hdma->Instance->CNDTR = DataLength; + 800231e: 68fb ldr r3, [r7, #12] + 8002320: 681b ldr r3, [r3, #0] + 8002322: 683a ldr r2, [r7, #0] + 8002324: 605a str r2, [r3, #4] + + /* Memory to Peripheral */ + if ((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) + 8002326: 68fb ldr r3, [r7, #12] + 8002328: 689b ldr r3, [r3, #8] + 800232a: 2b10 cmp r3, #16 + 800232c: d108 bne.n 8002340 + { + /* Configure DMA Channel destination address */ + hdma->Instance->CPAR = DstAddress; + 800232e: 68fb ldr r3, [r7, #12] + 8002330: 681b ldr r3, [r3, #0] + 8002332: 687a ldr r2, [r7, #4] + 8002334: 609a str r2, [r3, #8] + + /* Configure DMA Channel source address */ + hdma->Instance->CMAR = SrcAddress; + 8002336: 68fb ldr r3, [r7, #12] + 8002338: 681b ldr r3, [r3, #0] + 800233a: 68ba ldr r2, [r7, #8] + 800233c: 60da str r2, [r3, #12] + hdma->Instance->CPAR = SrcAddress; + + /* Configure DMA Channel destination address */ + hdma->Instance->CMAR = DstAddress; + } +} + 800233e: e007 b.n 8002350 + hdma->Instance->CPAR = SrcAddress; + 8002340: 68fb ldr r3, [r7, #12] + 8002342: 681b ldr r3, [r3, #0] + 8002344: 68ba ldr r2, [r7, #8] + 8002346: 609a str r2, [r3, #8] + hdma->Instance->CMAR = DstAddress; + 8002348: 68fb ldr r3, [r7, #12] + 800234a: 681b ldr r3, [r3, #0] + 800234c: 687a ldr r2, [r7, #4] + 800234e: 60da str r2, [r3, #12] +} + 8002350: bf00 nop + 8002352: 3714 adds r7, #20 + 8002354: 46bd mov sp, r7 + 8002356: bc80 pop {r7} + 8002358: 4770 bx lr + ... + +0800235c : + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @retval None + */ +static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma) +{ + 800235c: b480 push {r7} + 800235e: b085 sub sp, #20 + 8002360: af00 add r7, sp, #0 + 8002362: 6078 str r0, [r7, #4] + uint32_t channel_number; + + /* check if instance is not outside the DMA channel range */ + if ((uint32_t)hdma->Instance < (uint32_t)DMA2_Channel1) + 8002364: 687b ldr r3, [r7, #4] + 8002366: 681b ldr r3, [r3, #0] + 8002368: 461a mov r2, r3 + 800236a: 4b1c ldr r3, [pc, #112] @ (80023dc ) + 800236c: 429a cmp r2, r3 + 800236e: d813 bhi.n 8002398 + { + /* DMA1 */ + /* Associate a DMA Channel to a DMAMUX channel */ + hdma->DMAmuxChannel = (DMAMUX1_Channel0 + (hdma->ChannelIndex >> 2U)); + 8002370: 687b ldr r3, [r7, #4] + 8002372: 6c5b ldr r3, [r3, #68] @ 0x44 + 8002374: 089b lsrs r3, r3, #2 + 8002376: 009b lsls r3, r3, #2 + 8002378: f103 4380 add.w r3, r3, #1073741824 @ 0x40000000 + 800237c: f503 3302 add.w r3, r3, #133120 @ 0x20800 + 8002380: 687a ldr r2, [r7, #4] + 8002382: 6493 str r3, [r2, #72] @ 0x48 + + /* Prepare channel_number used for DMAmuxChannelStatusMask computation */ + channel_number = (((uint32_t)hdma->Instance & 0xFFU) - 8U) / 20U; + 8002384: 687b ldr r3, [r7, #4] + 8002386: 681b ldr r3, [r3, #0] + 8002388: b2db uxtb r3, r3 + 800238a: 3b08 subs r3, #8 + 800238c: 4a14 ldr r2, [pc, #80] @ (80023e0 ) + 800238e: fba2 2303 umull r2, r3, r2, r3 + 8002392: 091b lsrs r3, r3, #4 + 8002394: 60fb str r3, [r7, #12] + 8002396: e011 b.n 80023bc + } + else + { + /* DMA2 */ + /* Associate a DMA Channel to a DMAMUX channel */ + hdma->DMAmuxChannel = (DMAMUX1_Channel7 + (hdma->ChannelIndex >> 2U)); + 8002398: 687b ldr r3, [r7, #4] + 800239a: 6c5b ldr r3, [r3, #68] @ 0x44 + 800239c: 089b lsrs r3, r3, #2 + 800239e: 009a lsls r2, r3, #2 + 80023a0: 4b10 ldr r3, [pc, #64] @ (80023e4 ) + 80023a2: 4413 add r3, r2 + 80023a4: 687a ldr r2, [r7, #4] + 80023a6: 6493 str r3, [r2, #72] @ 0x48 + + /* Prepare channel_number used for DMAmuxChannelStatusMask computation */ + channel_number = (((((uint32_t)hdma->Instance & 0xFFU) - 8U) / 20U) + 7U); + 80023a8: 687b ldr r3, [r7, #4] + 80023aa: 681b ldr r3, [r3, #0] + 80023ac: b2db uxtb r3, r3 + 80023ae: 3b08 subs r3, #8 + 80023b0: 4a0b ldr r2, [pc, #44] @ (80023e0 ) + 80023b2: fba2 2303 umull r2, r3, r2, r3 + 80023b6: 091b lsrs r3, r3, #4 + 80023b8: 3307 adds r3, #7 + 80023ba: 60fb str r3, [r7, #12] + } + + /* Initialize the field DMAmuxChannelStatus to DMAMUX1_ChannelStatus base */ + hdma->DMAmuxChannelStatus = DMAMUX1_ChannelStatus; + 80023bc: 687b ldr r3, [r7, #4] + 80023be: 4a0a ldr r2, [pc, #40] @ (80023e8 ) + 80023c0: 64da str r2, [r3, #76] @ 0x4c + + /* Initialize the field DMAmuxChannelStatusMask with the corresponding index of the DMAMUX channel selected for the current ChannelIndex */ + hdma->DMAmuxChannelStatusMask = 1UL << (channel_number & 0x1FU); + 80023c2: 68fb ldr r3, [r7, #12] + 80023c4: f003 031f and.w r3, r3, #31 + 80023c8: 2201 movs r2, #1 + 80023ca: 409a lsls r2, r3 + 80023cc: 687b ldr r3, [r7, #4] + 80023ce: 651a str r2, [r3, #80] @ 0x50 +} + 80023d0: bf00 nop + 80023d2: 3714 adds r7, #20 + 80023d4: 46bd mov sp, r7 + 80023d6: bc80 pop {r7} + 80023d8: 4770 bx lr + 80023da: bf00 nop + 80023dc: 40020407 .word 0x40020407 + 80023e0: cccccccd .word 0xcccccccd + 80023e4: 4002081c .word 0x4002081c + 80023e8: 40020880 .word 0x40020880 + +080023ec : + * the configuration information for the specified DMA Channel. + * @retval None + */ + +static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma) +{ + 80023ec: b480 push {r7} + 80023ee: b085 sub sp, #20 + 80023f0: af00 add r7, sp, #0 + 80023f2: 6078 str r0, [r7, #4] + uint32_t request = hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID; + 80023f4: 687b ldr r3, [r7, #4] + 80023f6: 685b ldr r3, [r3, #4] + 80023f8: f003 037f and.w r3, r3, #127 @ 0x7f + 80023fc: 60fb str r3, [r7, #12] + + /* DMA Channels are connected to DMAMUX1 request generator blocks*/ + hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_RequestGenerator0) + ((request - 1U) * 4U))); + 80023fe: 68fa ldr r2, [r7, #12] + 8002400: 4b0a ldr r3, [pc, #40] @ (800242c ) + 8002402: 4413 add r3, r2 + 8002404: 009b lsls r3, r3, #2 + 8002406: 461a mov r2, r3 + 8002408: 687b ldr r3, [r7, #4] + 800240a: 655a str r2, [r3, #84] @ 0x54 + + hdma->DMAmuxRequestGenStatus = DMAMUX1_RequestGenStatus; + 800240c: 687b ldr r3, [r7, #4] + 800240e: 4a08 ldr r2, [pc, #32] @ (8002430 ) + 8002410: 659a str r2, [r3, #88] @ 0x58 + + /* here "Request" is either DMA_REQUEST_GENERATOR0 to DMA_REQUEST_GENERATOR3, i.e. <= 4*/ + hdma->DMAmuxRequestGenStatusMask = 1UL << ((request - 1U) & 0x3U); + 8002412: 68fb ldr r3, [r7, #12] + 8002414: 3b01 subs r3, #1 + 8002416: f003 0303 and.w r3, r3, #3 + 800241a: 2201 movs r2, #1 + 800241c: 409a lsls r2, r3 + 800241e: 687b ldr r3, [r7, #4] + 8002420: 65da str r2, [r3, #92] @ 0x5c +} + 8002422: bf00 nop + 8002424: 3714 adds r7, #20 + 8002426: 46bd mov sp, r7 + 8002428: bc80 pop {r7} + 800242a: 4770 bx lr + 800242c: 1000823f .word 0x1000823f + 8002430: 40020940 .word 0x40020940 + +08002434 : + * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains + * the configuration information for the specified GPIO peripheral. + * @retval None + */ +void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, const GPIO_InitTypeDef *GPIO_Init) +{ + 8002434: b480 push {r7} + 8002436: b087 sub sp, #28 + 8002438: af00 add r7, sp, #0 + 800243a: 6078 str r0, [r7, #4] + 800243c: 6039 str r1, [r7, #0] + uint32_t position = 0x00u; + 800243e: 2300 movs r3, #0 + 8002440: 617b str r3, [r7, #20] + assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); + assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); + assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); + + /* Configure the port pins */ + while (((GPIO_Init->Pin) >> position) != 0x00u) + 8002442: e140 b.n 80026c6 + { + /* Get current io position */ + iocurrent = (GPIO_Init->Pin) & (1uL << position); + 8002444: 683b ldr r3, [r7, #0] + 8002446: 681a ldr r2, [r3, #0] + 8002448: 2101 movs r1, #1 + 800244a: 697b ldr r3, [r7, #20] + 800244c: fa01 f303 lsl.w r3, r1, r3 + 8002450: 4013 ands r3, r2 + 8002452: 60fb str r3, [r7, #12] + + if (iocurrent != 0x00u) + 8002454: 68fb ldr r3, [r7, #12] + 8002456: 2b00 cmp r3, #0 + 8002458: f000 8132 beq.w 80026c0 + { + /*--------------------- GPIO Mode Configuration ------------------------*/ + /* In case of Output or Alternate function mode selection */ + if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)) + 800245c: 683b ldr r3, [r7, #0] + 800245e: 685b ldr r3, [r3, #4] + 8002460: f003 0303 and.w r3, r3, #3 + 8002464: 2b01 cmp r3, #1 + 8002466: d005 beq.n 8002474 + 8002468: 683b ldr r3, [r7, #0] + 800246a: 685b ldr r3, [r3, #4] + 800246c: f003 0303 and.w r3, r3, #3 + 8002470: 2b02 cmp r3, #2 + 8002472: d130 bne.n 80024d6 + { + /* Check the Speed parameter */ + assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); + /* Configure the IO Speed */ + temp = GPIOx->OSPEEDR; + 8002474: 687b ldr r3, [r7, #4] + 8002476: 689b ldr r3, [r3, #8] + 8002478: 613b str r3, [r7, #16] + temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U)); + 800247a: 697b ldr r3, [r7, #20] + 800247c: 005b lsls r3, r3, #1 + 800247e: 2203 movs r2, #3 + 8002480: fa02 f303 lsl.w r3, r2, r3 + 8002484: 43db mvns r3, r3 + 8002486: 693a ldr r2, [r7, #16] + 8002488: 4013 ands r3, r2 + 800248a: 613b str r3, [r7, #16] + temp |= (GPIO_Init->Speed << (position * 2U)); + 800248c: 683b ldr r3, [r7, #0] + 800248e: 68da ldr r2, [r3, #12] + 8002490: 697b ldr r3, [r7, #20] + 8002492: 005b lsls r3, r3, #1 + 8002494: fa02 f303 lsl.w r3, r2, r3 + 8002498: 693a ldr r2, [r7, #16] + 800249a: 4313 orrs r3, r2 + 800249c: 613b str r3, [r7, #16] + GPIOx->OSPEEDR = temp; + 800249e: 687b ldr r3, [r7, #4] + 80024a0: 693a ldr r2, [r7, #16] + 80024a2: 609a str r2, [r3, #8] + + /* Configure the IO Output Type */ + temp = GPIOx->OTYPER; + 80024a4: 687b ldr r3, [r7, #4] + 80024a6: 685b ldr r3, [r3, #4] + 80024a8: 613b str r3, [r7, #16] + temp &= ~(GPIO_OTYPER_OT0 << position) ; + 80024aa: 2201 movs r2, #1 + 80024ac: 697b ldr r3, [r7, #20] + 80024ae: fa02 f303 lsl.w r3, r2, r3 + 80024b2: 43db mvns r3, r3 + 80024b4: 693a ldr r2, [r7, #16] + 80024b6: 4013 ands r3, r2 + 80024b8: 613b str r3, [r7, #16] + temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position); + 80024ba: 683b ldr r3, [r7, #0] + 80024bc: 685b ldr r3, [r3, #4] + 80024be: 091b lsrs r3, r3, #4 + 80024c0: f003 0201 and.w r2, r3, #1 + 80024c4: 697b ldr r3, [r7, #20] + 80024c6: fa02 f303 lsl.w r3, r2, r3 + 80024ca: 693a ldr r2, [r7, #16] + 80024cc: 4313 orrs r3, r2 + 80024ce: 613b str r3, [r7, #16] + GPIOx->OTYPER = temp; + 80024d0: 687b ldr r3, [r7, #4] + 80024d2: 693a ldr r2, [r7, #16] + 80024d4: 605a str r2, [r3, #4] + } + + /* Activate the Pull-up or Pull down resistor for the current IO */ + if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) + 80024d6: 683b ldr r3, [r7, #0] + 80024d8: 685b ldr r3, [r3, #4] + 80024da: f003 0303 and.w r3, r3, #3 + 80024de: 2b03 cmp r3, #3 + 80024e0: d017 beq.n 8002512 + { + temp = GPIOx->PUPDR; + 80024e2: 687b ldr r3, [r7, #4] + 80024e4: 68db ldr r3, [r3, #12] + 80024e6: 613b str r3, [r7, #16] + temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U)); + 80024e8: 697b ldr r3, [r7, #20] + 80024ea: 005b lsls r3, r3, #1 + 80024ec: 2203 movs r2, #3 + 80024ee: fa02 f303 lsl.w r3, r2, r3 + 80024f2: 43db mvns r3, r3 + 80024f4: 693a ldr r2, [r7, #16] + 80024f6: 4013 ands r3, r2 + 80024f8: 613b str r3, [r7, #16] + temp |= ((GPIO_Init->Pull) << (position * 2U)); + 80024fa: 683b ldr r3, [r7, #0] + 80024fc: 689a ldr r2, [r3, #8] + 80024fe: 697b ldr r3, [r7, #20] + 8002500: 005b lsls r3, r3, #1 + 8002502: fa02 f303 lsl.w r3, r2, r3 + 8002506: 693a ldr r2, [r7, #16] + 8002508: 4313 orrs r3, r2 + 800250a: 613b str r3, [r7, #16] + GPIOx->PUPDR = temp; + 800250c: 687b ldr r3, [r7, #4] + 800250e: 693a ldr r2, [r7, #16] + 8002510: 60da str r2, [r3, #12] + } + + /* In case of Alternate function mode selection */ + if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF) + 8002512: 683b ldr r3, [r7, #0] + 8002514: 685b ldr r3, [r3, #4] + 8002516: f003 0303 and.w r3, r3, #3 + 800251a: 2b02 cmp r3, #2 + 800251c: d123 bne.n 8002566 + /* Check the Alternate function parameters */ + assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); + assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); + + /* Configure Alternate function mapped with the current IO */ + temp = GPIOx->AFR[position >> 3U]; + 800251e: 697b ldr r3, [r7, #20] + 8002520: 08da lsrs r2, r3, #3 + 8002522: 687b ldr r3, [r7, #4] + 8002524: 3208 adds r2, #8 + 8002526: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 800252a: 613b str r3, [r7, #16] + temp &= ~(0xFU << ((position & 0x07U) * 4U)); + 800252c: 697b ldr r3, [r7, #20] + 800252e: f003 0307 and.w r3, r3, #7 + 8002532: 009b lsls r3, r3, #2 + 8002534: 220f movs r2, #15 + 8002536: fa02 f303 lsl.w r3, r2, r3 + 800253a: 43db mvns r3, r3 + 800253c: 693a ldr r2, [r7, #16] + 800253e: 4013 ands r3, r2 + 8002540: 613b str r3, [r7, #16] + temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * 4U)); + 8002542: 683b ldr r3, [r7, #0] + 8002544: 691a ldr r2, [r3, #16] + 8002546: 697b ldr r3, [r7, #20] + 8002548: f003 0307 and.w r3, r3, #7 + 800254c: 009b lsls r3, r3, #2 + 800254e: fa02 f303 lsl.w r3, r2, r3 + 8002552: 693a ldr r2, [r7, #16] + 8002554: 4313 orrs r3, r2 + 8002556: 613b str r3, [r7, #16] + GPIOx->AFR[position >> 3u] = temp; + 8002558: 697b ldr r3, [r7, #20] + 800255a: 08da lsrs r2, r3, #3 + 800255c: 687b ldr r3, [r7, #4] + 800255e: 3208 adds r2, #8 + 8002560: 6939 ldr r1, [r7, #16] + 8002562: f843 1022 str.w r1, [r3, r2, lsl #2] + } + + /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ + temp = GPIOx->MODER; + 8002566: 687b ldr r3, [r7, #4] + 8002568: 681b ldr r3, [r3, #0] + 800256a: 613b str r3, [r7, #16] + temp &= ~(GPIO_MODER_MODE0 << (position * 2U)); + 800256c: 697b ldr r3, [r7, #20] + 800256e: 005b lsls r3, r3, #1 + 8002570: 2203 movs r2, #3 + 8002572: fa02 f303 lsl.w r3, r2, r3 + 8002576: 43db mvns r3, r3 + 8002578: 693a ldr r2, [r7, #16] + 800257a: 4013 ands r3, r2 + 800257c: 613b str r3, [r7, #16] + temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U)); + 800257e: 683b ldr r3, [r7, #0] + 8002580: 685b ldr r3, [r3, #4] + 8002582: f003 0203 and.w r2, r3, #3 + 8002586: 697b ldr r3, [r7, #20] + 8002588: 005b lsls r3, r3, #1 + 800258a: fa02 f303 lsl.w r3, r2, r3 + 800258e: 693a ldr r2, [r7, #16] + 8002590: 4313 orrs r3, r2 + 8002592: 613b str r3, [r7, #16] + GPIOx->MODER = temp; + 8002594: 687b ldr r3, [r7, #4] + 8002596: 693a ldr r2, [r7, #16] + 8002598: 601a str r2, [r3, #0] + + /*--------------------- EXTI Mode Configuration ------------------------*/ + /* Configure the External Interrupt or event for the current IO */ + if ((GPIO_Init->Mode & EXTI_MODE) != 0x00u) + 800259a: 683b ldr r3, [r7, #0] + 800259c: 685b ldr r3, [r3, #4] + 800259e: f403 3340 and.w r3, r3, #196608 @ 0x30000 + 80025a2: 2b00 cmp r3, #0 + 80025a4: f000 808c beq.w 80026c0 + { + temp = SYSCFG->EXTICR[position >> 2u]; + 80025a8: 4a4e ldr r2, [pc, #312] @ (80026e4 ) + 80025aa: 697b ldr r3, [r7, #20] + 80025ac: 089b lsrs r3, r3, #2 + 80025ae: 3302 adds r3, #2 + 80025b0: f852 3023 ldr.w r3, [r2, r3, lsl #2] + 80025b4: 613b str r3, [r7, #16] + temp &= ~(0x07uL << (4U * (position & 0x03U))); + 80025b6: 697b ldr r3, [r7, #20] + 80025b8: f003 0303 and.w r3, r3, #3 + 80025bc: 009b lsls r3, r3, #2 + 80025be: 2207 movs r2, #7 + 80025c0: fa02 f303 lsl.w r3, r2, r3 + 80025c4: 43db mvns r3, r3 + 80025c6: 693a ldr r2, [r7, #16] + 80025c8: 4013 ands r3, r2 + 80025ca: 613b str r3, [r7, #16] + temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U))); + 80025cc: 687b ldr r3, [r7, #4] + 80025ce: f1b3 4f90 cmp.w r3, #1207959552 @ 0x48000000 + 80025d2: d00d beq.n 80025f0 + 80025d4: 687b ldr r3, [r7, #4] + 80025d6: 4a44 ldr r2, [pc, #272] @ (80026e8 ) + 80025d8: 4293 cmp r3, r2 + 80025da: d007 beq.n 80025ec + 80025dc: 687b ldr r3, [r7, #4] + 80025de: 4a43 ldr r2, [pc, #268] @ (80026ec ) + 80025e0: 4293 cmp r3, r2 + 80025e2: d101 bne.n 80025e8 + 80025e4: 2302 movs r3, #2 + 80025e6: e004 b.n 80025f2 + 80025e8: 2307 movs r3, #7 + 80025ea: e002 b.n 80025f2 + 80025ec: 2301 movs r3, #1 + 80025ee: e000 b.n 80025f2 + 80025f0: 2300 movs r3, #0 + 80025f2: 697a ldr r2, [r7, #20] + 80025f4: f002 0203 and.w r2, r2, #3 + 80025f8: 0092 lsls r2, r2, #2 + 80025fa: 4093 lsls r3, r2 + 80025fc: 693a ldr r2, [r7, #16] + 80025fe: 4313 orrs r3, r2 + 8002600: 613b str r3, [r7, #16] + SYSCFG->EXTICR[position >> 2u] = temp; + 8002602: 4938 ldr r1, [pc, #224] @ (80026e4 ) + 8002604: 697b ldr r3, [r7, #20] + 8002606: 089b lsrs r3, r3, #2 + 8002608: 3302 adds r3, #2 + 800260a: 693a ldr r2, [r7, #16] + 800260c: f841 2023 str.w r2, [r1, r3, lsl #2] + + /* Clear Rising Falling edge configuration */ + temp = EXTI->RTSR1; + 8002610: 4b37 ldr r3, [pc, #220] @ (80026f0 ) + 8002612: 681b ldr r3, [r3, #0] + 8002614: 613b str r3, [r7, #16] + temp &= ~(iocurrent); + 8002616: 68fb ldr r3, [r7, #12] + 8002618: 43db mvns r3, r3 + 800261a: 693a ldr r2, [r7, #16] + 800261c: 4013 ands r3, r2 + 800261e: 613b str r3, [r7, #16] + if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00u) + 8002620: 683b ldr r3, [r7, #0] + 8002622: 685b ldr r3, [r3, #4] + 8002624: f403 1380 and.w r3, r3, #1048576 @ 0x100000 + 8002628: 2b00 cmp r3, #0 + 800262a: d003 beq.n 8002634 + { + temp |= iocurrent; + 800262c: 693a ldr r2, [r7, #16] + 800262e: 68fb ldr r3, [r7, #12] + 8002630: 4313 orrs r3, r2 + 8002632: 613b str r3, [r7, #16] + } + EXTI->RTSR1 = temp; + 8002634: 4a2e ldr r2, [pc, #184] @ (80026f0 ) + 8002636: 693b ldr r3, [r7, #16] + 8002638: 6013 str r3, [r2, #0] + + temp = EXTI->FTSR1; + 800263a: 4b2d ldr r3, [pc, #180] @ (80026f0 ) + 800263c: 685b ldr r3, [r3, #4] + 800263e: 613b str r3, [r7, #16] + temp &= ~(iocurrent); + 8002640: 68fb ldr r3, [r7, #12] + 8002642: 43db mvns r3, r3 + 8002644: 693a ldr r2, [r7, #16] + 8002646: 4013 ands r3, r2 + 8002648: 613b str r3, [r7, #16] + if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00u) + 800264a: 683b ldr r3, [r7, #0] + 800264c: 685b ldr r3, [r3, #4] + 800264e: f403 1300 and.w r3, r3, #2097152 @ 0x200000 + 8002652: 2b00 cmp r3, #0 + 8002654: d003 beq.n 800265e + { + temp |= iocurrent; + 8002656: 693a ldr r2, [r7, #16] + 8002658: 68fb ldr r3, [r7, #12] + 800265a: 4313 orrs r3, r2 + 800265c: 613b str r3, [r7, #16] + } + EXTI->FTSR1 = temp; + 800265e: 4a24 ldr r2, [pc, #144] @ (80026f0 ) + 8002660: 693b ldr r3, [r7, #16] + 8002662: 6053 str r3, [r2, #4] + + /* Clear EXTI line configuration */ +#ifdef CORE_CM0PLUS + temp = EXTI->C2IMR1; +#else + temp = EXTI->IMR1; + 8002664: 4b22 ldr r3, [pc, #136] @ (80026f0 ) + 8002666: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 + 800266a: 613b str r3, [r7, #16] +#endif /* CORE_CM0PLUS */ + temp &= ~(iocurrent); + 800266c: 68fb ldr r3, [r7, #12] + 800266e: 43db mvns r3, r3 + 8002670: 693a ldr r2, [r7, #16] + 8002672: 4013 ands r3, r2 + 8002674: 613b str r3, [r7, #16] + if ((GPIO_Init->Mode & EXTI_IT) != 0x00u) + 8002676: 683b ldr r3, [r7, #0] + 8002678: 685b ldr r3, [r3, #4] + 800267a: f403 3380 and.w r3, r3, #65536 @ 0x10000 + 800267e: 2b00 cmp r3, #0 + 8002680: d003 beq.n 800268a + { + temp |= iocurrent; + 8002682: 693a ldr r2, [r7, #16] + 8002684: 68fb ldr r3, [r7, #12] + 8002686: 4313 orrs r3, r2 + 8002688: 613b str r3, [r7, #16] + } +#ifdef CORE_CM0PLUS + EXTI->C2IMR1 = temp; +#else + EXTI->IMR1 = temp; + 800268a: 4a19 ldr r2, [pc, #100] @ (80026f0 ) + 800268c: 693b ldr r3, [r7, #16] + 800268e: f8c2 3080 str.w r3, [r2, #128] @ 0x80 +#endif /* CORE_CM0PLUS */ + +#ifdef CORE_CM0PLUS + temp = EXTI->C2EMR1; +#else + temp = EXTI->EMR1; + 8002692: 4b17 ldr r3, [pc, #92] @ (80026f0 ) + 8002694: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 + 8002698: 613b str r3, [r7, #16] +#endif /* CORE_CM0PLUS */ + temp &= ~(iocurrent); + 800269a: 68fb ldr r3, [r7, #12] + 800269c: 43db mvns r3, r3 + 800269e: 693a ldr r2, [r7, #16] + 80026a0: 4013 ands r3, r2 + 80026a2: 613b str r3, [r7, #16] + if ((GPIO_Init->Mode & EXTI_EVT) != 0x00u) + 80026a4: 683b ldr r3, [r7, #0] + 80026a6: 685b ldr r3, [r3, #4] + 80026a8: f403 3300 and.w r3, r3, #131072 @ 0x20000 + 80026ac: 2b00 cmp r3, #0 + 80026ae: d003 beq.n 80026b8 + { + temp |= iocurrent; + 80026b0: 693a ldr r2, [r7, #16] + 80026b2: 68fb ldr r3, [r7, #12] + 80026b4: 4313 orrs r3, r2 + 80026b6: 613b str r3, [r7, #16] + } +#ifdef CORE_CM0PLUS + EXTI->C2EMR1 = temp; +#else + EXTI->EMR1 = temp; + 80026b8: 4a0d ldr r2, [pc, #52] @ (80026f0 ) + 80026ba: 693b ldr r3, [r7, #16] + 80026bc: f8c2 3084 str.w r3, [r2, #132] @ 0x84 +#endif /* CORE_CM0PLUS */ + } + } + + position++; + 80026c0: 697b ldr r3, [r7, #20] + 80026c2: 3301 adds r3, #1 + 80026c4: 617b str r3, [r7, #20] + while (((GPIO_Init->Pin) >> position) != 0x00u) + 80026c6: 683b ldr r3, [r7, #0] + 80026c8: 681a ldr r2, [r3, #0] + 80026ca: 697b ldr r3, [r7, #20] + 80026cc: fa22 f303 lsr.w r3, r2, r3 + 80026d0: 2b00 cmp r3, #0 + 80026d2: f47f aeb7 bne.w 8002444 + } +} + 80026d6: bf00 nop + 80026d8: bf00 nop + 80026da: 371c adds r7, #28 + 80026dc: 46bd mov sp, r7 + 80026de: bc80 pop {r7} + 80026e0: 4770 bx lr + 80026e2: bf00 nop + 80026e4: 40010000 .word 0x40010000 + 80026e8: 48000400 .word 0x48000400 + 80026ec: 48000800 .word 0x48000800 + 80026f0: 58000800 .word 0x58000800 + +080026f4 : + * @param GPIO_Pin specifies the port bit to be written. + * This parameter can be any combination of GPIO_PIN_x where x can be (0..15). + * @retval None + */ +void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) +{ + 80026f4: b480 push {r7} + 80026f6: b087 sub sp, #28 + 80026f8: af00 add r7, sp, #0 + 80026fa: 6078 str r0, [r7, #4] + 80026fc: 6039 str r1, [r7, #0] + uint32_t position = 0x00u; + 80026fe: 2300 movs r3, #0 + 8002700: 617b str r3, [r7, #20] + /* Check the parameters */ + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + /* Configure the port pins */ + while ((GPIO_Pin >> position) != 0x00u) + 8002702: e0af b.n 8002864 + { + /* Get current io position */ + iocurrent = (GPIO_Pin) & (1uL << position); + 8002704: 2201 movs r2, #1 + 8002706: 697b ldr r3, [r7, #20] + 8002708: fa02 f303 lsl.w r3, r2, r3 + 800270c: 683a ldr r2, [r7, #0] + 800270e: 4013 ands r3, r2 + 8002710: 613b str r3, [r7, #16] + + if (iocurrent != 0x00u) + 8002712: 693b ldr r3, [r7, #16] + 8002714: 2b00 cmp r3, #0 + 8002716: f000 80a2 beq.w 800285e + { + /*------------------------- EXTI Mode Configuration --------------------*/ + /* Clear the External Interrupt or Event for the current IO */ + + tmp = SYSCFG->EXTICR[position >> 2u]; + 800271a: 4a59 ldr r2, [pc, #356] @ (8002880 ) + 800271c: 697b ldr r3, [r7, #20] + 800271e: 089b lsrs r3, r3, #2 + 8002720: 3302 adds r3, #2 + 8002722: f852 3023 ldr.w r3, [r2, r3, lsl #2] + 8002726: 60fb str r3, [r7, #12] + tmp &= (0x07uL << (4U * (position & 0x03U))); + 8002728: 697b ldr r3, [r7, #20] + 800272a: f003 0303 and.w r3, r3, #3 + 800272e: 009b lsls r3, r3, #2 + 8002730: 2207 movs r2, #7 + 8002732: fa02 f303 lsl.w r3, r2, r3 + 8002736: 68fa ldr r2, [r7, #12] + 8002738: 4013 ands r3, r2 + 800273a: 60fb str r3, [r7, #12] + if (tmp == (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U)))) + 800273c: 687b ldr r3, [r7, #4] + 800273e: f1b3 4f90 cmp.w r3, #1207959552 @ 0x48000000 + 8002742: d00d beq.n 8002760 + 8002744: 687b ldr r3, [r7, #4] + 8002746: 4a4f ldr r2, [pc, #316] @ (8002884 ) + 8002748: 4293 cmp r3, r2 + 800274a: d007 beq.n 800275c + 800274c: 687b ldr r3, [r7, #4] + 800274e: 4a4e ldr r2, [pc, #312] @ (8002888 ) + 8002750: 4293 cmp r3, r2 + 8002752: d101 bne.n 8002758 + 8002754: 2302 movs r3, #2 + 8002756: e004 b.n 8002762 + 8002758: 2307 movs r3, #7 + 800275a: e002 b.n 8002762 + 800275c: 2301 movs r3, #1 + 800275e: e000 b.n 8002762 + 8002760: 2300 movs r3, #0 + 8002762: 697a ldr r2, [r7, #20] + 8002764: f002 0203 and.w r2, r2, #3 + 8002768: 0092 lsls r2, r2, #2 + 800276a: 4093 lsls r3, r2 + 800276c: 68fa ldr r2, [r7, #12] + 800276e: 429a cmp r2, r3 + 8002770: d136 bne.n 80027e0 + /* Clear EXTI line configuration */ +#ifdef CORE_CM0PLUS + EXTI->C2IMR1 &= ~(iocurrent); + EXTI->C2EMR1 &= ~(iocurrent); +#else + EXTI->IMR1 &= ~(iocurrent); + 8002772: 4b46 ldr r3, [pc, #280] @ (800288c ) + 8002774: f8d3 2080 ldr.w r2, [r3, #128] @ 0x80 + 8002778: 693b ldr r3, [r7, #16] + 800277a: 43db mvns r3, r3 + 800277c: 4943 ldr r1, [pc, #268] @ (800288c ) + 800277e: 4013 ands r3, r2 + 8002780: f8c1 3080 str.w r3, [r1, #128] @ 0x80 + EXTI->EMR1 &= ~(iocurrent); + 8002784: 4b41 ldr r3, [pc, #260] @ (800288c ) + 8002786: f8d3 2084 ldr.w r2, [r3, #132] @ 0x84 + 800278a: 693b ldr r3, [r7, #16] + 800278c: 43db mvns r3, r3 + 800278e: 493f ldr r1, [pc, #252] @ (800288c ) + 8002790: 4013 ands r3, r2 + 8002792: f8c1 3084 str.w r3, [r1, #132] @ 0x84 +#endif /* CORE_CM0PLUS */ + + /* Clear Rising Falling edge configuration */ + EXTI->RTSR1 &= ~(iocurrent); + 8002796: 4b3d ldr r3, [pc, #244] @ (800288c ) + 8002798: 681a ldr r2, [r3, #0] + 800279a: 693b ldr r3, [r7, #16] + 800279c: 43db mvns r3, r3 + 800279e: 493b ldr r1, [pc, #236] @ (800288c ) + 80027a0: 4013 ands r3, r2 + 80027a2: 600b str r3, [r1, #0] + EXTI->FTSR1 &= ~(iocurrent); + 80027a4: 4b39 ldr r3, [pc, #228] @ (800288c ) + 80027a6: 685a ldr r2, [r3, #4] + 80027a8: 693b ldr r3, [r7, #16] + 80027aa: 43db mvns r3, r3 + 80027ac: 4937 ldr r1, [pc, #220] @ (800288c ) + 80027ae: 4013 ands r3, r2 + 80027b0: 604b str r3, [r1, #4] + + /* Clear EXTICR configuration */ + tmp = 0x07uL << (4u * (position & 0x03U)); + 80027b2: 697b ldr r3, [r7, #20] + 80027b4: f003 0303 and.w r3, r3, #3 + 80027b8: 009b lsls r3, r3, #2 + 80027ba: 2207 movs r2, #7 + 80027bc: fa02 f303 lsl.w r3, r2, r3 + 80027c0: 60fb str r3, [r7, #12] + SYSCFG->EXTICR[position >> 2u] &= ~tmp; + 80027c2: 4a2f ldr r2, [pc, #188] @ (8002880 ) + 80027c4: 697b ldr r3, [r7, #20] + 80027c6: 089b lsrs r3, r3, #2 + 80027c8: 3302 adds r3, #2 + 80027ca: f852 1023 ldr.w r1, [r2, r3, lsl #2] + 80027ce: 68fb ldr r3, [r7, #12] + 80027d0: 43da mvns r2, r3 + 80027d2: 482b ldr r0, [pc, #172] @ (8002880 ) + 80027d4: 697b ldr r3, [r7, #20] + 80027d6: 089b lsrs r3, r3, #2 + 80027d8: 400a ands r2, r1 + 80027da: 3302 adds r3, #2 + 80027dc: f840 2023 str.w r2, [r0, r3, lsl #2] + } + + /*------------------------- GPIO Mode Configuration --------------------*/ + /* Configure IO in Analog Mode */ + GPIOx->MODER |= (GPIO_MODER_MODE0 << (position * 2U)); + 80027e0: 687b ldr r3, [r7, #4] + 80027e2: 681a ldr r2, [r3, #0] + 80027e4: 697b ldr r3, [r7, #20] + 80027e6: 005b lsls r3, r3, #1 + 80027e8: 2103 movs r1, #3 + 80027ea: fa01 f303 lsl.w r3, r1, r3 + 80027ee: 431a orrs r2, r3 + 80027f0: 687b ldr r3, [r7, #4] + 80027f2: 601a str r2, [r3, #0] + + /* Configure the default Alternate Function in current IO */ + GPIOx->AFR[position >> 3U] &= ~(0xFU << ((position & 0x07U) * 4U)) ; + 80027f4: 697b ldr r3, [r7, #20] + 80027f6: 08da lsrs r2, r3, #3 + 80027f8: 687b ldr r3, [r7, #4] + 80027fa: 3208 adds r2, #8 + 80027fc: f853 1022 ldr.w r1, [r3, r2, lsl #2] + 8002800: 697b ldr r3, [r7, #20] + 8002802: f003 0307 and.w r3, r3, #7 + 8002806: 009b lsls r3, r3, #2 + 8002808: 220f movs r2, #15 + 800280a: fa02 f303 lsl.w r3, r2, r3 + 800280e: 43db mvns r3, r3 + 8002810: 697a ldr r2, [r7, #20] + 8002812: 08d2 lsrs r2, r2, #3 + 8002814: 4019 ands r1, r3 + 8002816: 687b ldr r3, [r7, #4] + 8002818: 3208 adds r2, #8 + 800281a: f843 1022 str.w r1, [r3, r2, lsl #2] + + /* Configure the default value for IO Speed */ + GPIOx->OSPEEDR &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U)); + 800281e: 687b ldr r3, [r7, #4] + 8002820: 689a ldr r2, [r3, #8] + 8002822: 697b ldr r3, [r7, #20] + 8002824: 005b lsls r3, r3, #1 + 8002826: 2103 movs r1, #3 + 8002828: fa01 f303 lsl.w r3, r1, r3 + 800282c: 43db mvns r3, r3 + 800282e: 401a ands r2, r3 + 8002830: 687b ldr r3, [r7, #4] + 8002832: 609a str r2, [r3, #8] + + /* Configure the default value IO Output Type */ + GPIOx->OTYPER &= ~(GPIO_OTYPER_OT0 << position) ; + 8002834: 687b ldr r3, [r7, #4] + 8002836: 685a ldr r2, [r3, #4] + 8002838: 2101 movs r1, #1 + 800283a: 697b ldr r3, [r7, #20] + 800283c: fa01 f303 lsl.w r3, r1, r3 + 8002840: 43db mvns r3, r3 + 8002842: 401a ands r2, r3 + 8002844: 687b ldr r3, [r7, #4] + 8002846: 605a str r2, [r3, #4] + + /* Deactivate the Pull-up and Pull-down resistor for the current IO */ + GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPD0 << (position * 2U)); + 8002848: 687b ldr r3, [r7, #4] + 800284a: 68da ldr r2, [r3, #12] + 800284c: 697b ldr r3, [r7, #20] + 800284e: 005b lsls r3, r3, #1 + 8002850: 2103 movs r1, #3 + 8002852: fa01 f303 lsl.w r3, r1, r3 + 8002856: 43db mvns r3, r3 + 8002858: 401a ands r2, r3 + 800285a: 687b ldr r3, [r7, #4] + 800285c: 60da str r2, [r3, #12] + } + + position++; + 800285e: 697b ldr r3, [r7, #20] + 8002860: 3301 adds r3, #1 + 8002862: 617b str r3, [r7, #20] + while ((GPIO_Pin >> position) != 0x00u) + 8002864: 683a ldr r2, [r7, #0] + 8002866: 697b ldr r3, [r7, #20] + 8002868: fa22 f303 lsr.w r3, r2, r3 + 800286c: 2b00 cmp r3, #0 + 800286e: f47f af49 bne.w 8002704 + } +} + 8002872: bf00 nop + 8002874: bf00 nop + 8002876: 371c adds r7, #28 + 8002878: 46bd mov sp, r7 + 800287a: bc80 pop {r7} + 800287c: 4770 bx lr + 800287e: bf00 nop + 8002880: 40010000 .word 0x40010000 + 8002884: 48000400 .word 0x48000400 + 8002888: 48000800 .word 0x48000800 + 800288c: 58000800 .word 0x58000800 + +08002890 : + * @arg GPIO_PIN_RESET: to clear the port pin + * @arg GPIO_PIN_SET: to set the port pin + * @retval None + */ +void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) +{ + 8002890: b480 push {r7} + 8002892: b083 sub sp, #12 + 8002894: af00 add r7, sp, #0 + 8002896: 6078 str r0, [r7, #4] + 8002898: 460b mov r3, r1 + 800289a: 807b strh r3, [r7, #2] + 800289c: 4613 mov r3, r2 + 800289e: 707b strb r3, [r7, #1] + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + assert_param(IS_GPIO_PIN_ACTION(PinState)); + + if (PinState != GPIO_PIN_RESET) + 80028a0: 787b ldrb r3, [r7, #1] + 80028a2: 2b00 cmp r3, #0 + 80028a4: d003 beq.n 80028ae + { + GPIOx->BSRR = (uint32_t)GPIO_Pin; + 80028a6: 887a ldrh r2, [r7, #2] + 80028a8: 687b ldr r3, [r7, #4] + 80028aa: 619a str r2, [r3, #24] + } + else + { + GPIOx->BRR = (uint32_t)GPIO_Pin; + } +} + 80028ac: e002 b.n 80028b4 + GPIOx->BRR = (uint32_t)GPIO_Pin; + 80028ae: 887a ldrh r2, [r7, #2] + 80028b0: 687b ldr r3, [r7, #4] + 80028b2: 629a str r2, [r3, #40] @ 0x28 +} + 80028b4: bf00 nop + 80028b6: 370c adds r7, #12 + 80028b8: 46bd mov sp, r7 + 80028ba: bc80 pop {r7} + 80028bc: 4770 bx lr + ... + +080028c0 : + * @brief Handle EXTI interrupt request. + * @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line. + * @retval None + */ +void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) +{ + 80028c0: b580 push {r7, lr} + 80028c2: b082 sub sp, #8 + 80028c4: af00 add r7, sp, #0 + 80028c6: 4603 mov r3, r0 + 80028c8: 80fb strh r3, [r7, #6] + /* EXTI line interrupt detected */ + if (__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != 0x00u) + 80028ca: 4b08 ldr r3, [pc, #32] @ (80028ec ) + 80028cc: 68da ldr r2, [r3, #12] + 80028ce: 88fb ldrh r3, [r7, #6] + 80028d0: 4013 ands r3, r2 + 80028d2: 2b00 cmp r3, #0 + 80028d4: d006 beq.n 80028e4 + { + __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin); + 80028d6: 4a05 ldr r2, [pc, #20] @ (80028ec ) + 80028d8: 88fb ldrh r3, [r7, #6] + 80028da: 60d3 str r3, [r2, #12] + HAL_GPIO_EXTI_Callback(GPIO_Pin); + 80028dc: 88fb ldrh r3, [r7, #6] + 80028de: 4618 mov r0, r3 + 80028e0: f000 f806 bl 80028f0 + } +} + 80028e4: bf00 nop + 80028e6: 3708 adds r7, #8 + 80028e8: 46bd mov sp, r7 + 80028ea: bd80 pop {r7, pc} + 80028ec: 58000800 .word 0x58000800 + +080028f0 : + * @brief EXTI line detection callback. + * @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line. + * @retval None + */ +__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) +{ + 80028f0: b480 push {r7} + 80028f2: b083 sub sp, #12 + 80028f4: af00 add r7, sp, #0 + 80028f6: 4603 mov r3, r0 + 80028f8: 80fb strh r3, [r7, #6] + UNUSED(GPIO_Pin); + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_GPIO_EXTI_Callback could be implemented in the user file + */ +} + 80028fa: bf00 nop + 80028fc: 370c adds r7, #12 + 80028fe: 46bd mov sp, r7 + 8002900: bc80 pop {r7} + 8002902: 4770 bx lr + +08002904 : + * @note LSEON bit that switches on and off the LSE crystal belongs as well to the + * backup domain. + * @retval None + */ +void HAL_PWR_EnableBkUpAccess(void) +{ + 8002904: b480 push {r7} + 8002906: af00 add r7, sp, #0 + SET_BIT(PWR->CR1, PWR_CR1_DBP); + 8002908: 4b04 ldr r3, [pc, #16] @ (800291c ) + 800290a: 681b ldr r3, [r3, #0] + 800290c: 4a03 ldr r2, [pc, #12] @ (800291c ) + 800290e: f443 7380 orr.w r3, r3, #256 @ 0x100 + 8002912: 6013 str r3, [r2, #0] +} + 8002914: bf00 nop + 8002916: 46bd mov sp, r7 + 8002918: bc80 pop {r7} + 800291a: 4770 bx lr + 800291c: 58000400 .word 0x58000400 + +08002920 : + * @note When WFI entry is used, tick interrupt have to be disabled if not desired as + * the interrupt wake up source. + * @retval None + */ +void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry) +{ + 8002920: b580 push {r7, lr} + 8002922: b082 sub sp, #8 + 8002924: af00 add r7, sp, #0 + 8002926: 6078 str r0, [r7, #4] + 8002928: 460b mov r3, r1 + 800292a: 70fb strb r3, [r7, #3] + /* Check the parameters */ + assert_param(IS_PWR_REGULATOR(Regulator)); + assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry)); + + /* Set Regulator parameter */ + if (Regulator == PWR_MAINREGULATOR_ON) + 800292c: 687b ldr r3, [r7, #4] + 800292e: 2b00 cmp r3, #0 + 8002930: d10c bne.n 800294c + { + /* If in low-power run mode at this point, exit it */ + if (HAL_IS_BIT_SET(PWR->SR2, (PWR_SR2_REGLPF))) + 8002932: 4b13 ldr r3, [pc, #76] @ (8002980 ) + 8002934: 695b ldr r3, [r3, #20] + 8002936: f403 7300 and.w r3, r3, #512 @ 0x200 + 800293a: f5b3 7f00 cmp.w r3, #512 @ 0x200 + 800293e: d10d bne.n 800295c + { + if (HAL_PWREx_DisableLowPowerRunMode() != HAL_OK) + 8002940: f000 f83c bl 80029bc + 8002944: 4603 mov r3, r0 + 8002946: 2b00 cmp r3, #0 + 8002948: d008 beq.n 800295c + { + return ; + 800294a: e015 b.n 8002978 + } + else + { + /* If in run mode, first move to low-power run mode. + The system clock frequency must be below 2 MHz at this point. */ + if (HAL_IS_BIT_CLR(PWR->SR2, (PWR_SR2_REGLPF))) + 800294c: 4b0c ldr r3, [pc, #48] @ (8002980 ) + 800294e: 695b ldr r3, [r3, #20] + 8002950: f403 7300 and.w r3, r3, #512 @ 0x200 + 8002954: 2b00 cmp r3, #0 + 8002956: d101 bne.n 800295c + { + HAL_PWREx_EnableLowPowerRunMode(); + 8002958: f000 f822 bl 80029a0 + } + } + + /* Clear SLEEPDEEP bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); + 800295c: 4b09 ldr r3, [pc, #36] @ (8002984 ) + 800295e: 691b ldr r3, [r3, #16] + 8002960: 4a08 ldr r2, [pc, #32] @ (8002984 ) + 8002962: f023 0304 bic.w r3, r3, #4 + 8002966: 6113 str r3, [r2, #16] + + /* Select SLEEP mode entry -------------------------------------------------*/ + if (SLEEPEntry == PWR_SLEEPENTRY_WFI) + 8002968: 78fb ldrb r3, [r7, #3] + 800296a: 2b01 cmp r3, #1 + 800296c: d101 bne.n 8002972 + { + /* Request Wait For Interrupt */ + __WFI(); + 800296e: bf30 wfi + 8002970: e002 b.n 8002978 + } + else + { + /* Request Wait For Event */ + __SEV(); + 8002972: bf40 sev + __WFE(); + 8002974: bf20 wfe + __WFE(); + 8002976: bf20 wfe + } +} + 8002978: 3708 adds r7, #8 + 800297a: 46bd mov sp, r7 + 800297c: bd80 pop {r7, pc} + 800297e: bf00 nop + 8002980: 58000400 .word 0x58000400 + 8002984: e000ed00 .word 0xe000ed00 + +08002988 : +/** + * @brief Return Voltage Scaling Range. + * @retval VOS bit field (PWR_REGULATOR_VOLTAGE_SCALE1 or PWPWR_REGULATOR_VOLTAGE_SCALE2) + */ +uint32_t HAL_PWREx_GetVoltageRange(void) +{ + 8002988: b480 push {r7} + 800298a: af00 add r7, sp, #0 + return (PWR->CR1 & PWR_CR1_VOS); + 800298c: 4b03 ldr r3, [pc, #12] @ (800299c ) + 800298e: 681b ldr r3, [r3, #0] + 8002990: f403 63c0 and.w r3, r3, #1536 @ 0x600 +} + 8002994: 4618 mov r0, r3 + 8002996: 46bd mov sp, r7 + 8002998: bc80 pop {r7} + 800299a: 4770 bx lr + 800299c: 58000400 .word 0x58000400 + +080029a0 : + * @note In Low-power Run mode, all I/O pins keep the same state as in Run mode. + * @note Clock frequency must be reduced below 2 MHz. + * @retval None + */ +void HAL_PWREx_EnableLowPowerRunMode(void) +{ + 80029a0: b480 push {r7} + 80029a2: af00 add r7, sp, #0 + /* Set Regulator parameter */ + SET_BIT(PWR->CR1, PWR_CR1_LPR); + 80029a4: 4b04 ldr r3, [pc, #16] @ (80029b8 ) + 80029a6: 681b ldr r3, [r3, #0] + 80029a8: 4a03 ldr r2, [pc, #12] @ (80029b8 ) + 80029aa: f443 4380 orr.w r3, r3, #16384 @ 0x4000 + 80029ae: 6013 str r3, [r2, #0] +} + 80029b0: bf00 nop + 80029b2: 46bd mov sp, r7 + 80029b4: bc80 pop {r7} + 80029b6: 4770 bx lr + 80029b8: 58000400 .word 0x58000400 + +080029bc : + * returns HAL_TIMEOUT status). The system clock frequency can then be + * increased above 2 MHz. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void) +{ + 80029bc: b480 push {r7} + 80029be: b083 sub sp, #12 + 80029c0: af00 add r7, sp, #0 + uint32_t wait_loop_index; + + /* Clear LPR bit */ + CLEAR_BIT(PWR->CR1, PWR_CR1_LPR); + 80029c2: 4b16 ldr r3, [pc, #88] @ (8002a1c ) + 80029c4: 681b ldr r3, [r3, #0] + 80029c6: 4a15 ldr r2, [pc, #84] @ (8002a1c ) + 80029c8: f423 4380 bic.w r3, r3, #16384 @ 0x4000 + 80029cc: 6013 str r3, [r2, #0] + + /* Wait until REGLPF is reset */ + wait_loop_index = ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000UL); + 80029ce: 4b14 ldr r3, [pc, #80] @ (8002a20 ) + 80029d0: 681b ldr r3, [r3, #0] + 80029d2: 2232 movs r2, #50 @ 0x32 + 80029d4: fb02 f303 mul.w r3, r2, r3 + 80029d8: 4a12 ldr r2, [pc, #72] @ (8002a24 ) + 80029da: fba2 2303 umull r2, r3, r2, r3 + 80029de: 0c9b lsrs r3, r3, #18 + 80029e0: 607b str r3, [r7, #4] + while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF)) && (wait_loop_index != 0U)) + 80029e2: e002 b.n 80029ea + { + wait_loop_index--; + 80029e4: 687b ldr r3, [r7, #4] + 80029e6: 3b01 subs r3, #1 + 80029e8: 607b str r3, [r7, #4] + while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF)) && (wait_loop_index != 0U)) + 80029ea: 4b0c ldr r3, [pc, #48] @ (8002a1c ) + 80029ec: 695b ldr r3, [r3, #20] + 80029ee: f403 7300 and.w r3, r3, #512 @ 0x200 + 80029f2: f5b3 7f00 cmp.w r3, #512 @ 0x200 + 80029f6: d102 bne.n 80029fe + 80029f8: 687b ldr r3, [r7, #4] + 80029fa: 2b00 cmp r3, #0 + 80029fc: d1f2 bne.n 80029e4 + } + if (HAL_IS_BIT_SET(PWR->SR2, (PWR_SR2_REGLPF))) + 80029fe: 4b07 ldr r3, [pc, #28] @ (8002a1c ) + 8002a00: 695b ldr r3, [r3, #20] + 8002a02: f403 7300 and.w r3, r3, #512 @ 0x200 + 8002a06: f5b3 7f00 cmp.w r3, #512 @ 0x200 + 8002a0a: d101 bne.n 8002a10 + { + return HAL_TIMEOUT; + 8002a0c: 2303 movs r3, #3 + 8002a0e: e000 b.n 8002a12 + } + + return HAL_OK; + 8002a10: 2300 movs r3, #0 +} + 8002a12: 4618 mov r0, r3 + 8002a14: 370c adds r7, #12 + 8002a16: 46bd mov sp, r7 + 8002a18: bc80 pop {r7} + 8002a1a: 4770 bx lr + 8002a1c: 58000400 .word 0x58000400 + 8002a20: 20000000 .word 0x20000000 + 8002a24: 431bde83 .word 0x431bde83 + +08002a28 : + * @arg @ref PWR_STOPENTRY_WFI Enter Stop mode with WFI instruction + * @arg @ref PWR_STOPENTRY_WFE Enter Stop mode with WFE instruction + * @retval None + */ +void HAL_PWREx_EnterSTOP2Mode(uint8_t STOPEntry) +{ + 8002a28: b480 push {r7} + 8002a2a: b083 sub sp, #12 + 8002a2c: af00 add r7, sp, #0 + 8002a2e: 4603 mov r3, r0 + 8002a30: 71fb strb r3, [r7, #7] +#ifdef CORE_CM0PLUS + /* Set Stop mode 2 */ + MODIFY_REG(PWR->C2CR1, PWR_C2CR1_LPMS, PWR_LOWPOWERMODE_STOP2); +#else + /* Set Stop mode 2 */ + MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_LOWPOWERMODE_STOP2); + 8002a32: 4b10 ldr r3, [pc, #64] @ (8002a74 ) + 8002a34: 681b ldr r3, [r3, #0] + 8002a36: f023 0307 bic.w r3, r3, #7 + 8002a3a: 4a0e ldr r2, [pc, #56] @ (8002a74 ) + 8002a3c: f043 0302 orr.w r3, r3, #2 + 8002a40: 6013 str r3, [r2, #0] +#endif /* CORE_CM0PLUS */ + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); + 8002a42: 4b0d ldr r3, [pc, #52] @ (8002a78 ) + 8002a44: 691b ldr r3, [r3, #16] + 8002a46: 4a0c ldr r2, [pc, #48] @ (8002a78 ) + 8002a48: f043 0304 orr.w r3, r3, #4 + 8002a4c: 6113 str r3, [r2, #16] + + /* Select Stop mode entry --------------------------------------------------*/ + if (STOPEntry == PWR_STOPENTRY_WFI) + 8002a4e: 79fb ldrb r3, [r7, #7] + 8002a50: 2b01 cmp r3, #1 + 8002a52: d101 bne.n 8002a58 + { + /* Request Wait For Interrupt */ + __WFI(); + 8002a54: bf30 wfi + 8002a56: e002 b.n 8002a5e + } + else + { + /* Request Wait For Event */ + __SEV(); + 8002a58: bf40 sev + __WFE(); + 8002a5a: bf20 wfe + __WFE(); + 8002a5c: bf20 wfe + } + + /* Reset SLEEPDEEP bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); + 8002a5e: 4b06 ldr r3, [pc, #24] @ (8002a78 ) + 8002a60: 691b ldr r3, [r3, #16] + 8002a62: 4a05 ldr r2, [pc, #20] @ (8002a78 ) + 8002a64: f023 0304 bic.w r3, r3, #4 + 8002a68: 6113 str r3, [r2, #16] +} + 8002a6a: bf00 nop + 8002a6c: 370c adds r7, #12 + 8002a6e: 46bd mov sp, r7 + 8002a70: bc80 pop {r7} + 8002a72: 4770 bx lr + 8002a74: 58000400 .word 0x58000400 + 8002a78: e000ed00 .word 0xe000ed00 + +08002a7c : +{ + 8002a7c: b480 push {r7} + 8002a7e: af00 add r7, sp, #0 + return ((READ_BIT(PWR->CR1, PWR_CR1_DBP) == (PWR_CR1_DBP)) ? 1UL : 0UL); + 8002a80: 4b06 ldr r3, [pc, #24] @ (8002a9c ) + 8002a82: 681b ldr r3, [r3, #0] + 8002a84: f403 7380 and.w r3, r3, #256 @ 0x100 + 8002a88: f5b3 7f80 cmp.w r3, #256 @ 0x100 + 8002a8c: d101 bne.n 8002a92 + 8002a8e: 2301 movs r3, #1 + 8002a90: e000 b.n 8002a94 + 8002a92: 2300 movs r3, #0 +} + 8002a94: 4618 mov r0, r3 + 8002a96: 46bd mov sp, r7 + 8002a98: bc80 pop {r7} + 8002a9a: 4770 bx lr + 8002a9c: 58000400 .word 0x58000400 + +08002aa0 : +{ + 8002aa0: b480 push {r7} + 8002aa2: af00 add r7, sp, #0 + SET_BIT(RCC->CR, RCC_CR_HSEBYPPWR); + 8002aa4: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002aa8: 681b ldr r3, [r3, #0] + 8002aaa: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 8002aae: f443 1300 orr.w r3, r3, #2097152 @ 0x200000 + 8002ab2: 6013 str r3, [r2, #0] +} + 8002ab4: bf00 nop + 8002ab6: 46bd mov sp, r7 + 8002ab8: bc80 pop {r7} + 8002aba: 4770 bx lr + +08002abc : +{ + 8002abc: b480 push {r7} + 8002abe: af00 add r7, sp, #0 + CLEAR_BIT(RCC->CR, RCC_CR_HSEBYPPWR); + 8002ac0: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002ac4: 681b ldr r3, [r3, #0] + 8002ac6: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 8002aca: f423 1300 bic.w r3, r3, #2097152 @ 0x200000 + 8002ace: 6013 str r3, [r2, #0] +} + 8002ad0: bf00 nop + 8002ad2: 46bd mov sp, r7 + 8002ad4: bc80 pop {r7} + 8002ad6: 4770 bx lr + +08002ad8 : +{ + 8002ad8: b480 push {r7} + 8002ada: af00 add r7, sp, #0 + return ((READ_BIT(RCC->CR, RCC_CR_HSEPRE) == (RCC_CR_HSEPRE)) ? 1UL : 0UL); + 8002adc: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002ae0: 681b ldr r3, [r3, #0] + 8002ae2: f403 1380 and.w r3, r3, #1048576 @ 0x100000 + 8002ae6: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 + 8002aea: d101 bne.n 8002af0 + 8002aec: 2301 movs r3, #1 + 8002aee: e000 b.n 8002af2 + 8002af0: 2300 movs r3, #0 +} + 8002af2: 4618 mov r0, r3 + 8002af4: 46bd mov sp, r7 + 8002af6: bc80 pop {r7} + 8002af8: 4770 bx lr + +08002afa : +{ + 8002afa: b480 push {r7} + 8002afc: af00 add r7, sp, #0 + SET_BIT(RCC->CR, RCC_CR_HSEON); + 8002afe: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002b02: 681b ldr r3, [r3, #0] + 8002b04: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 8002b08: f443 3380 orr.w r3, r3, #65536 @ 0x10000 + 8002b0c: 6013 str r3, [r2, #0] +} + 8002b0e: bf00 nop + 8002b10: 46bd mov sp, r7 + 8002b12: bc80 pop {r7} + 8002b14: 4770 bx lr + +08002b16 : +{ + 8002b16: b480 push {r7} + 8002b18: af00 add r7, sp, #0 + CLEAR_BIT(RCC->CR, RCC_CR_HSEON); + 8002b1a: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002b1e: 681b ldr r3, [r3, #0] + 8002b20: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 8002b24: f423 3380 bic.w r3, r3, #65536 @ 0x10000 + 8002b28: 6013 str r3, [r2, #0] +} + 8002b2a: bf00 nop + 8002b2c: 46bd mov sp, r7 + 8002b2e: bc80 pop {r7} + 8002b30: 4770 bx lr + +08002b32 : +{ + 8002b32: b480 push {r7} + 8002b34: af00 add r7, sp, #0 + return ((READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY)) ? 1UL : 0UL); + 8002b36: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002b3a: 681b ldr r3, [r3, #0] + 8002b3c: f403 3300 and.w r3, r3, #131072 @ 0x20000 + 8002b40: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 + 8002b44: d101 bne.n 8002b4a + 8002b46: 2301 movs r3, #1 + 8002b48: e000 b.n 8002b4c + 8002b4a: 2300 movs r3, #0 +} + 8002b4c: 4618 mov r0, r3 + 8002b4e: 46bd mov sp, r7 + 8002b50: bc80 pop {r7} + 8002b52: 4770 bx lr + +08002b54 : +{ + 8002b54: b480 push {r7} + 8002b56: af00 add r7, sp, #0 + SET_BIT(RCC->CR, RCC_CR_HSION); + 8002b58: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002b5c: 681b ldr r3, [r3, #0] + 8002b5e: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 8002b62: f443 7380 orr.w r3, r3, #256 @ 0x100 + 8002b66: 6013 str r3, [r2, #0] +} + 8002b68: bf00 nop + 8002b6a: 46bd mov sp, r7 + 8002b6c: bc80 pop {r7} + 8002b6e: 4770 bx lr + +08002b70 : +{ + 8002b70: b480 push {r7} + 8002b72: af00 add r7, sp, #0 + CLEAR_BIT(RCC->CR, RCC_CR_HSION); + 8002b74: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002b78: 681b ldr r3, [r3, #0] + 8002b7a: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 8002b7e: f423 7380 bic.w r3, r3, #256 @ 0x100 + 8002b82: 6013 str r3, [r2, #0] +} + 8002b84: bf00 nop + 8002b86: 46bd mov sp, r7 + 8002b88: bc80 pop {r7} + 8002b8a: 4770 bx lr + +08002b8c : +{ + 8002b8c: b480 push {r7} + 8002b8e: af00 add r7, sp, #0 + return ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY)) ? 1UL : 0UL); + 8002b90: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002b94: 681b ldr r3, [r3, #0] + 8002b96: f403 6380 and.w r3, r3, #1024 @ 0x400 + 8002b9a: f5b3 6f80 cmp.w r3, #1024 @ 0x400 + 8002b9e: d101 bne.n 8002ba4 + 8002ba0: 2301 movs r3, #1 + 8002ba2: e000 b.n 8002ba6 + 8002ba4: 2300 movs r3, #0 +} + 8002ba6: 4618 mov r0, r3 + 8002ba8: 46bd mov sp, r7 + 8002baa: bc80 pop {r7} + 8002bac: 4770 bx lr + +08002bae : +{ + 8002bae: b480 push {r7} + 8002bb0: b083 sub sp, #12 + 8002bb2: af00 add r7, sp, #0 + 8002bb4: 6078 str r0, [r7, #4] + MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, Value << RCC_ICSCR_HSITRIM_Pos); + 8002bb6: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002bba: 685b ldr r3, [r3, #4] + 8002bbc: f023 42fe bic.w r2, r3, #2130706432 @ 0x7f000000 + 8002bc0: 687b ldr r3, [r7, #4] + 8002bc2: 061b lsls r3, r3, #24 + 8002bc4: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 8002bc8: 4313 orrs r3, r2 + 8002bca: 604b str r3, [r1, #4] +} + 8002bcc: bf00 nop + 8002bce: 370c adds r7, #12 + 8002bd0: 46bd mov sp, r7 + 8002bd2: bc80 pop {r7} + 8002bd4: 4770 bx lr + +08002bd6 : +{ + 8002bd6: b480 push {r7} + 8002bd8: af00 add r7, sp, #0 + return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY)) ? 1UL : 0UL); + 8002bda: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002bde: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 8002be2: f003 0302 and.w r3, r3, #2 + 8002be6: 2b02 cmp r3, #2 + 8002be8: d101 bne.n 8002bee + 8002bea: 2301 movs r3, #1 + 8002bec: e000 b.n 8002bf0 + 8002bee: 2300 movs r3, #0 +} + 8002bf0: 4618 mov r0, r3 + 8002bf2: 46bd mov sp, r7 + 8002bf4: bc80 pop {r7} + 8002bf6: 4770 bx lr + +08002bf8 : +{ + 8002bf8: b480 push {r7} + 8002bfa: af00 add r7, sp, #0 + SET_BIT(RCC->CSR, RCC_CSR_LSION); + 8002bfc: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002c00: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 + 8002c04: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 8002c08: f043 0301 orr.w r3, r3, #1 + 8002c0c: f8c2 3094 str.w r3, [r2, #148] @ 0x94 +} + 8002c10: bf00 nop + 8002c12: 46bd mov sp, r7 + 8002c14: bc80 pop {r7} + 8002c16: 4770 bx lr + +08002c18 : +{ + 8002c18: b480 push {r7} + 8002c1a: af00 add r7, sp, #0 + CLEAR_BIT(RCC->CSR, RCC_CSR_LSION); + 8002c1c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002c20: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 + 8002c24: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 8002c28: f023 0301 bic.w r3, r3, #1 + 8002c2c: f8c2 3094 str.w r3, [r2, #148] @ 0x94 +} + 8002c30: bf00 nop + 8002c32: 46bd mov sp, r7 + 8002c34: bc80 pop {r7} + 8002c36: 4770 bx lr + +08002c38 : +{ + 8002c38: b480 push {r7} + 8002c3a: af00 add r7, sp, #0 + return ((READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY)) ? 1UL : 0UL); + 8002c3c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002c40: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 + 8002c44: f003 0302 and.w r3, r3, #2 + 8002c48: 2b02 cmp r3, #2 + 8002c4a: d101 bne.n 8002c50 + 8002c4c: 2301 movs r3, #1 + 8002c4e: e000 b.n 8002c52 + 8002c50: 2300 movs r3, #0 +} + 8002c52: 4618 mov r0, r3 + 8002c54: 46bd mov sp, r7 + 8002c56: bc80 pop {r7} + 8002c58: 4770 bx lr + +08002c5a : +{ + 8002c5a: b480 push {r7} + 8002c5c: af00 add r7, sp, #0 + SET_BIT(RCC->CR, RCC_CR_MSION); + 8002c5e: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002c62: 681b ldr r3, [r3, #0] + 8002c64: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 8002c68: f043 0301 orr.w r3, r3, #1 + 8002c6c: 6013 str r3, [r2, #0] +} + 8002c6e: bf00 nop + 8002c70: 46bd mov sp, r7 + 8002c72: bc80 pop {r7} + 8002c74: 4770 bx lr + +08002c76 : +{ + 8002c76: b480 push {r7} + 8002c78: af00 add r7, sp, #0 + CLEAR_BIT(RCC->CR, RCC_CR_MSION); + 8002c7a: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002c7e: 681b ldr r3, [r3, #0] + 8002c80: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 8002c84: f023 0301 bic.w r3, r3, #1 + 8002c88: 6013 str r3, [r2, #0] +} + 8002c8a: bf00 nop + 8002c8c: 46bd mov sp, r7 + 8002c8e: bc80 pop {r7} + 8002c90: 4770 bx lr + +08002c92 : +{ + 8002c92: b480 push {r7} + 8002c94: af00 add r7, sp, #0 + return ((READ_BIT(RCC->CR, RCC_CR_MSIRDY) == (RCC_CR_MSIRDY)) ? 1UL : 0UL); + 8002c96: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002c9a: 681b ldr r3, [r3, #0] + 8002c9c: f003 0302 and.w r3, r3, #2 + 8002ca0: 2b02 cmp r3, #2 + 8002ca2: d101 bne.n 8002ca8 + 8002ca4: 2301 movs r3, #1 + 8002ca6: e000 b.n 8002caa + 8002ca8: 2300 movs r3, #0 +} + 8002caa: 4618 mov r0, r3 + 8002cac: 46bd mov sp, r7 + 8002cae: bc80 pop {r7} + 8002cb0: 4770 bx lr + +08002cb2 : +{ + 8002cb2: b480 push {r7} + 8002cb4: af00 add r7, sp, #0 + return ((READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) == (RCC_CR_MSIRGSEL)) ? 1UL : 0UL); + 8002cb6: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002cba: 681b ldr r3, [r3, #0] + 8002cbc: f003 0308 and.w r3, r3, #8 + 8002cc0: 2b08 cmp r3, #8 + 8002cc2: d101 bne.n 8002cc8 + 8002cc4: 2301 movs r3, #1 + 8002cc6: e000 b.n 8002cca + 8002cc8: 2300 movs r3, #0 +} + 8002cca: 4618 mov r0, r3 + 8002ccc: 46bd mov sp, r7 + 8002cce: bc80 pop {r7} + 8002cd0: 4770 bx lr + +08002cd2 : +{ + 8002cd2: b480 push {r7} + 8002cd4: af00 add r7, sp, #0 + return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_MSIRANGE)); + 8002cd6: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002cda: 681b ldr r3, [r3, #0] + 8002cdc: f003 03f0 and.w r3, r3, #240 @ 0xf0 +} + 8002ce0: 4618 mov r0, r3 + 8002ce2: 46bd mov sp, r7 + 8002ce4: bc80 pop {r7} + 8002ce6: 4770 bx lr + +08002ce8 : +{ + 8002ce8: b480 push {r7} + 8002cea: af00 add r7, sp, #0 + return (uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_MSISRANGE)); + 8002cec: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002cf0: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 + 8002cf4: f403 6370 and.w r3, r3, #3840 @ 0xf00 +} + 8002cf8: 4618 mov r0, r3 + 8002cfa: 46bd mov sp, r7 + 8002cfc: bc80 pop {r7} + 8002cfe: 4770 bx lr + +08002d00 : +{ + 8002d00: b480 push {r7} + 8002d02: b083 sub sp, #12 + 8002d04: af00 add r7, sp, #0 + 8002d06: 6078 str r0, [r7, #4] + MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, Value << RCC_ICSCR_MSITRIM_Pos); + 8002d08: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002d0c: 685b ldr r3, [r3, #4] + 8002d0e: f423 427f bic.w r2, r3, #65280 @ 0xff00 + 8002d12: 687b ldr r3, [r7, #4] + 8002d14: 021b lsls r3, r3, #8 + 8002d16: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 8002d1a: 4313 orrs r3, r2 + 8002d1c: 604b str r3, [r1, #4] +} + 8002d1e: bf00 nop + 8002d20: 370c adds r7, #12 + 8002d22: 46bd mov sp, r7 + 8002d24: bc80 pop {r7} + 8002d26: 4770 bx lr + +08002d28 : +{ + 8002d28: b480 push {r7} + 8002d2a: b083 sub sp, #12 + 8002d2c: af00 add r7, sp, #0 + 8002d2e: 6078 str r0, [r7, #4] + MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source); + 8002d30: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002d34: 689b ldr r3, [r3, #8] + 8002d36: f023 0203 bic.w r2, r3, #3 + 8002d3a: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 8002d3e: 687b ldr r3, [r7, #4] + 8002d40: 4313 orrs r3, r2 + 8002d42: 608b str r3, [r1, #8] +} + 8002d44: bf00 nop + 8002d46: 370c adds r7, #12 + 8002d48: 46bd mov sp, r7 + 8002d4a: bc80 pop {r7} + 8002d4c: 4770 bx lr + +08002d4e : +{ + 8002d4e: b480 push {r7} + 8002d50: af00 add r7, sp, #0 + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS)); + 8002d52: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002d56: 689b ldr r3, [r3, #8] + 8002d58: f003 030c and.w r3, r3, #12 +} + 8002d5c: 4618 mov r0, r3 + 8002d5e: 46bd mov sp, r7 + 8002d60: bc80 pop {r7} + 8002d62: 4770 bx lr + +08002d64 : +{ + 8002d64: b480 push {r7} + 8002d66: b083 sub sp, #12 + 8002d68: af00 add r7, sp, #0 + 8002d6a: 6078 str r0, [r7, #4] + MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler); + 8002d6c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002d70: 689b ldr r3, [r3, #8] + 8002d72: f023 02f0 bic.w r2, r3, #240 @ 0xf0 + 8002d76: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 8002d7a: 687b ldr r3, [r7, #4] + 8002d7c: 4313 orrs r3, r2 + 8002d7e: 608b str r3, [r1, #8] +} + 8002d80: bf00 nop + 8002d82: 370c adds r7, #12 + 8002d84: 46bd mov sp, r7 + 8002d86: bc80 pop {r7} + 8002d88: 4770 bx lr + +08002d8a : +{ + 8002d8a: b480 push {r7} + 8002d8c: b083 sub sp, #12 + 8002d8e: af00 add r7, sp, #0 + 8002d90: 6078 str r0, [r7, #4] + MODIFY_REG(RCC->EXTCFGR, RCC_EXTCFGR_C2HPRE, Prescaler); + 8002d92: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002d96: f8d3 3108 ldr.w r3, [r3, #264] @ 0x108 + 8002d9a: f023 02f0 bic.w r2, r3, #240 @ 0xf0 + 8002d9e: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 8002da2: 687b ldr r3, [r7, #4] + 8002da4: 4313 orrs r3, r2 + 8002da6: f8c1 3108 str.w r3, [r1, #264] @ 0x108 +} + 8002daa: bf00 nop + 8002dac: 370c adds r7, #12 + 8002dae: 46bd mov sp, r7 + 8002db0: bc80 pop {r7} + 8002db2: 4770 bx lr + +08002db4 : +{ + 8002db4: b480 push {r7} + 8002db6: b083 sub sp, #12 + 8002db8: af00 add r7, sp, #0 + 8002dba: 6078 str r0, [r7, #4] + MODIFY_REG(RCC->EXTCFGR, RCC_EXTCFGR_SHDHPRE, Prescaler >> 4); + 8002dbc: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002dc0: f8d3 3108 ldr.w r3, [r3, #264] @ 0x108 + 8002dc4: f023 020f bic.w r2, r3, #15 + 8002dc8: 687b ldr r3, [r7, #4] + 8002dca: 091b lsrs r3, r3, #4 + 8002dcc: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 8002dd0: 4313 orrs r3, r2 + 8002dd2: f8c1 3108 str.w r3, [r1, #264] @ 0x108 +} + 8002dd6: bf00 nop + 8002dd8: 370c adds r7, #12 + 8002dda: 46bd mov sp, r7 + 8002ddc: bc80 pop {r7} + 8002dde: 4770 bx lr + +08002de0 : +{ + 8002de0: b480 push {r7} + 8002de2: b083 sub sp, #12 + 8002de4: af00 add r7, sp, #0 + 8002de6: 6078 str r0, [r7, #4] + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler); + 8002de8: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002dec: 689b ldr r3, [r3, #8] + 8002dee: f423 62e0 bic.w r2, r3, #1792 @ 0x700 + 8002df2: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 8002df6: 687b ldr r3, [r7, #4] + 8002df8: 4313 orrs r3, r2 + 8002dfa: 608b str r3, [r1, #8] +} + 8002dfc: bf00 nop + 8002dfe: 370c adds r7, #12 + 8002e00: 46bd mov sp, r7 + 8002e02: bc80 pop {r7} + 8002e04: 4770 bx lr + +08002e06 : +{ + 8002e06: b480 push {r7} + 8002e08: b083 sub sp, #12 + 8002e0a: af00 add r7, sp, #0 + 8002e0c: 6078 str r0, [r7, #4] + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler); + 8002e0e: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002e12: 689b ldr r3, [r3, #8] + 8002e14: f423 5260 bic.w r2, r3, #14336 @ 0x3800 + 8002e18: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 8002e1c: 687b ldr r3, [r7, #4] + 8002e1e: 4313 orrs r3, r2 + 8002e20: 608b str r3, [r1, #8] +} + 8002e22: bf00 nop + 8002e24: 370c adds r7, #12 + 8002e26: 46bd mov sp, r7 + 8002e28: bc80 pop {r7} + 8002e2a: 4770 bx lr + +08002e2c : +{ + 8002e2c: b480 push {r7} + 8002e2e: af00 add r7, sp, #0 + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE)); + 8002e30: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002e34: 689b ldr r3, [r3, #8] + 8002e36: f003 03f0 and.w r3, r3, #240 @ 0xf0 +} + 8002e3a: 4618 mov r0, r3 + 8002e3c: 46bd mov sp, r7 + 8002e3e: bc80 pop {r7} + 8002e40: 4770 bx lr + +08002e42 : +{ + 8002e42: b480 push {r7} + 8002e44: af00 add r7, sp, #0 + return (uint32_t)(READ_BIT(RCC->EXTCFGR, RCC_EXTCFGR_SHDHPRE) << 4); + 8002e46: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002e4a: f8d3 3108 ldr.w r3, [r3, #264] @ 0x108 + 8002e4e: 011b lsls r3, r3, #4 + 8002e50: f003 03f0 and.w r3, r3, #240 @ 0xf0 +} + 8002e54: 4618 mov r0, r3 + 8002e56: 46bd mov sp, r7 + 8002e58: bc80 pop {r7} + 8002e5a: 4770 bx lr + +08002e5c : +{ + 8002e5c: b480 push {r7} + 8002e5e: af00 add r7, sp, #0 + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1)); + 8002e60: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002e64: 689b ldr r3, [r3, #8] + 8002e66: f403 63e0 and.w r3, r3, #1792 @ 0x700 +} + 8002e6a: 4618 mov r0, r3 + 8002e6c: 46bd mov sp, r7 + 8002e6e: bc80 pop {r7} + 8002e70: 4770 bx lr + +08002e72 : +{ + 8002e72: b480 push {r7} + 8002e74: af00 add r7, sp, #0 + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2)); + 8002e76: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002e7a: 689b ldr r3, [r3, #8] + 8002e7c: f403 5360 and.w r3, r3, #14336 @ 0x3800 +} + 8002e80: 4618 mov r0, r3 + 8002e82: 46bd mov sp, r7 + 8002e84: bc80 pop {r7} + 8002e86: 4770 bx lr + +08002e88 : + * @brief Enable PLL + * @rmtoll CR PLLON LL_RCC_PLL_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_Enable(void) +{ + 8002e88: b480 push {r7} + 8002e8a: af00 add r7, sp, #0 + SET_BIT(RCC->CR, RCC_CR_PLLON); + 8002e8c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002e90: 681b ldr r3, [r3, #0] + 8002e92: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 8002e96: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000 + 8002e9a: 6013 str r3, [r2, #0] +} + 8002e9c: bf00 nop + 8002e9e: 46bd mov sp, r7 + 8002ea0: bc80 pop {r7} + 8002ea2: 4770 bx lr + +08002ea4 : + * @note Cannot be disabled if the PLL clock is used as the system clock + * @rmtoll CR PLLON LL_RCC_PLL_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_Disable(void) +{ + 8002ea4: b480 push {r7} + 8002ea6: af00 add r7, sp, #0 + CLEAR_BIT(RCC->CR, RCC_CR_PLLON); + 8002ea8: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002eac: 681b ldr r3, [r3, #0] + 8002eae: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 8002eb2: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000 + 8002eb6: 6013 str r3, [r2, #0] +} + 8002eb8: bf00 nop + 8002eba: 46bd mov sp, r7 + 8002ebc: bc80 pop {r7} + 8002ebe: 4770 bx lr + +08002ec0 : + * @brief Check if PLL Ready + * @rmtoll CR PLLRDY LL_RCC_PLL_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void) +{ + 8002ec0: b480 push {r7} + 8002ec2: af00 add r7, sp, #0 + return ((READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY)) ? 1UL : 0UL); + 8002ec4: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002ec8: 681b ldr r3, [r3, #0] + 8002eca: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 + 8002ece: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 + 8002ed2: d101 bne.n 8002ed8 + 8002ed4: 2301 movs r3, #1 + 8002ed6: e000 b.n 8002eda + 8002ed8: 2300 movs r3, #0 +} + 8002eda: 4618 mov r0, r3 + 8002edc: 46bd mov sp, r7 + 8002ede: bc80 pop {r7} + 8002ee0: 4770 bx lr + +08002ee2 : + * @brief Get Main PLL multiplication factor for VCO + * @rmtoll PLLCFGR PLLN LL_RCC_PLL_GetN + * @retval Between 6 and 127 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_GetN(void) +{ + 8002ee2: b480 push {r7} + 8002ee4: af00 add r7, sp, #0 + return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); + 8002ee6: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002eea: 68db ldr r3, [r3, #12] + 8002eec: 0a1b lsrs r3, r3, #8 + 8002eee: f003 037f and.w r3, r3, #127 @ 0x7f +} + 8002ef2: 4618 mov r0, r3 + 8002ef4: 46bd mov sp, r7 + 8002ef6: bc80 pop {r7} + 8002ef8: 4770 bx lr + +08002efa : + * @arg @ref LL_RCC_PLLR_DIV_6 + * @arg @ref LL_RCC_PLLR_DIV_7 + * @arg @ref LL_RCC_PLLR_DIV_8 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_GetR(void) +{ + 8002efa: b480 push {r7} + 8002efc: af00 add r7, sp, #0 + return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR)); + 8002efe: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002f02: 68db ldr r3, [r3, #12] + 8002f04: f003 4360 and.w r3, r3, #3758096384 @ 0xe0000000 +} + 8002f08: 4618 mov r0, r3 + 8002f0a: 46bd mov sp, r7 + 8002f0c: bc80 pop {r7} + 8002f0e: 4770 bx lr + +08002f10 : + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_GetDivider(void) +{ + 8002f10: b480 push {r7} + 8002f12: af00 add r7, sp, #0 + return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM)); + 8002f14: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002f18: 68db ldr r3, [r3, #12] + 8002f1a: f003 0370 and.w r3, r3, #112 @ 0x70 +} + 8002f1e: 4618 mov r0, r3 + 8002f20: 46bd mov sp, r7 + 8002f22: bc80 pop {r7} + 8002f24: 4770 bx lr + +08002f26 : + * @arg @ref LL_RCC_PLLSOURCE_MSI + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void) +{ + 8002f26: b480 push {r7} + 8002f28: af00 add r7, sp, #0 + return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC)); + 8002f2a: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002f2e: 68db ldr r3, [r3, #12] + 8002f30: f003 0303 and.w r3, r3, #3 +} + 8002f34: 4618 mov r0, r3 + 8002f36: 46bd mov sp, r7 + 8002f38: bc80 pop {r7} + 8002f3a: 4770 bx lr + +08002f3c : + * @brief Check if HCLK1 prescaler flag value has been applied or not + * @rmtoll CFGR HPREF LL_RCC_IsActiveFlag_HPRE + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HPRE(void) +{ + 8002f3c: b480 push {r7} + 8002f3e: af00 add r7, sp, #0 + return ((READ_BIT(RCC->CFGR, RCC_CFGR_HPREF) == (RCC_CFGR_HPREF)) ? 1UL : 0UL); + 8002f40: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002f44: 689b ldr r3, [r3, #8] + 8002f46: f403 3380 and.w r3, r3, #65536 @ 0x10000 + 8002f4a: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 + 8002f4e: d101 bne.n 8002f54 + 8002f50: 2301 movs r3, #1 + 8002f52: e000 b.n 8002f56 + 8002f54: 2300 movs r3, #0 +} + 8002f56: 4618 mov r0, r3 + 8002f58: 46bd mov sp, r7 + 8002f5a: bc80 pop {r7} + 8002f5c: 4770 bx lr + +08002f5e : + * @brief Check if HCLK2 prescaler flag value has been applied or not + * @rmtoll EXTCFGR C2HPREF LL_RCC_IsActiveFlag_C2HPRE + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_C2HPRE(void) +{ + 8002f5e: b480 push {r7} + 8002f60: af00 add r7, sp, #0 + return ((READ_BIT(RCC->EXTCFGR, RCC_EXTCFGR_C2HPREF) == (RCC_EXTCFGR_C2HPREF)) ? 1UL : 0UL); + 8002f62: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002f66: f8d3 3108 ldr.w r3, [r3, #264] @ 0x108 + 8002f6a: f403 3300 and.w r3, r3, #131072 @ 0x20000 + 8002f6e: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 + 8002f72: d101 bne.n 8002f78 + 8002f74: 2301 movs r3, #1 + 8002f76: e000 b.n 8002f7a + 8002f78: 2300 movs r3, #0 +} + 8002f7a: 4618 mov r0, r3 + 8002f7c: 46bd mov sp, r7 + 8002f7e: bc80 pop {r7} + 8002f80: 4770 bx lr + +08002f82 : + * @brief Check if HCLK3 prescaler flag value has been applied or not + * @rmtoll EXTCFGR SHDHPREF LL_RCC_IsActiveFlag_SHDHPRE + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SHDHPRE(void) +{ + 8002f82: b480 push {r7} + 8002f84: af00 add r7, sp, #0 + return ((READ_BIT(RCC->EXTCFGR, RCC_EXTCFGR_SHDHPREF) == (RCC_EXTCFGR_SHDHPREF)) ? 1UL : 0UL); + 8002f86: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002f8a: f8d3 3108 ldr.w r3, [r3, #264] @ 0x108 + 8002f8e: f403 3380 and.w r3, r3, #65536 @ 0x10000 + 8002f92: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 + 8002f96: d101 bne.n 8002f9c + 8002f98: 2301 movs r3, #1 + 8002f9a: e000 b.n 8002f9e + 8002f9c: 2300 movs r3, #0 +} + 8002f9e: 4618 mov r0, r3 + 8002fa0: 46bd mov sp, r7 + 8002fa2: bc80 pop {r7} + 8002fa4: 4770 bx lr + +08002fa6 : + * @brief Check if PLCK1 prescaler flag value has been applied or not + * @rmtoll CFGR PPRE1F LL_RCC_IsActiveFlag_PPRE1 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PPRE1(void) +{ + 8002fa6: b480 push {r7} + 8002fa8: af00 add r7, sp, #0 + return ((READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1F) == (RCC_CFGR_PPRE1F)) ? 1UL : 0UL); + 8002faa: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002fae: 689b ldr r3, [r3, #8] + 8002fb0: f403 3300 and.w r3, r3, #131072 @ 0x20000 + 8002fb4: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 + 8002fb8: d101 bne.n 8002fbe + 8002fba: 2301 movs r3, #1 + 8002fbc: e000 b.n 8002fc0 + 8002fbe: 2300 movs r3, #0 +} + 8002fc0: 4618 mov r0, r3 + 8002fc2: 46bd mov sp, r7 + 8002fc4: bc80 pop {r7} + 8002fc6: 4770 bx lr + +08002fc8 : + * @brief Check if PLCK2 prescaler flag value has been applied or not + * @rmtoll CFGR PPRE2F LL_RCC_IsActiveFlag_PPRE2 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PPRE2(void) +{ + 8002fc8: b480 push {r7} + 8002fca: af00 add r7, sp, #0 + return ((READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2F) == (RCC_CFGR_PPRE2F)) ? 1UL : 0UL); + 8002fcc: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002fd0: 689b ldr r3, [r3, #8] + 8002fd2: f403 2380 and.w r3, r3, #262144 @ 0x40000 + 8002fd6: f5b3 2f80 cmp.w r3, #262144 @ 0x40000 + 8002fda: d101 bne.n 8002fe0 + 8002fdc: 2301 movs r3, #1 + 8002fde: e000 b.n 8002fe2 + 8002fe0: 2300 movs r3, #0 +} + 8002fe2: 4618 mov r0, r3 + 8002fe4: 46bd mov sp, r7 + 8002fe6: bc80 pop {r7} + 8002fe8: 4770 bx lr + ... + +08002fec : + * contains the configuration information for the RCC Oscillators. + * @note The PLL is not disabled when used as system clock. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) +{ + 8002fec: b580 push {r7, lr} + 8002fee: b088 sub sp, #32 + 8002ff0: af00 add r7, sp, #0 + 8002ff2: 6078 str r0, [r7, #4] + uint32_t sysclk_source; + uint32_t pll_config; + HAL_StatusTypeDef status; + + /* Check Null pointer */ + if (RCC_OscInitStruct == NULL) + 8002ff4: 687b ldr r3, [r7, #4] + 8002ff6: 2b00 cmp r3, #0 + 8002ff8: d101 bne.n 8002ffe + { + return HAL_ERROR; + 8002ffa: 2301 movs r3, #1 + 8002ffc: e36f b.n 80036de + } + + /* Check the parameters */ + assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); + + sysclk_source = __HAL_RCC_GET_SYSCLK_SOURCE(); + 8002ffe: f7ff fea6 bl 8002d4e + 8003002: 61f8 str r0, [r7, #28] + pll_config = __HAL_RCC_GET_PLL_OSCSOURCE(); + 8003004: f7ff ff8f bl 8002f26 + 8003008: 61b8 str r0, [r7, #24] + + /*----------------------------- MSI Configuration --------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI) + 800300a: 687b ldr r3, [r7, #4] + 800300c: 681b ldr r3, [r3, #0] + 800300e: f003 0320 and.w r3, r3, #32 + 8003012: 2b00 cmp r3, #0 + 8003014: f000 80c4 beq.w 80031a0 + assert_param(IS_RCC_MSI(RCC_OscInitStruct->MSIState)); + assert_param(IS_RCC_MSI_CALIBRATION_VALUE(RCC_OscInitStruct->MSICalibrationValue)); + assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange)); + + /* When the MSI is used as system clock it will not be disabled */ + if ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_MSI) || + 8003018: 69fb ldr r3, [r7, #28] + 800301a: 2b00 cmp r3, #0 + 800301c: d005 beq.n 800302a + 800301e: 69fb ldr r3, [r7, #28] + 8003020: 2b0c cmp r3, #12 + 8003022: d176 bne.n 8003112 + ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_MSI))) + 8003024: 69bb ldr r3, [r7, #24] + 8003026: 2b01 cmp r3, #1 + 8003028: d173 bne.n 8003112 + { + if (RCC_OscInitStruct->MSIState == RCC_MSI_OFF) + 800302a: 687b ldr r3, [r7, #4] + 800302c: 6a1b ldr r3, [r3, #32] + 800302e: 2b00 cmp r3, #0 + 8003030: d101 bne.n 8003036 + { + return HAL_ERROR; + 8003032: 2301 movs r3, #1 + 8003034: e353 b.n 80036de + else + { + /* To correctly read data from FLASH memory, the number of wait states (LATENCY) + must be correctly programmed according to the frequency of the AHB3 clock + and the supply voltage of the device. */ + if (RCC_OscInitStruct->MSIClockRange > __HAL_RCC_GET_MSI_RANGE()) + 8003036: 687b ldr r3, [r7, #4] + 8003038: 6a9a ldr r2, [r3, #40] @ 0x28 + 800303a: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 800303e: 681b ldr r3, [r3, #0] + 8003040: f003 0308 and.w r3, r3, #8 + 8003044: 2b00 cmp r3, #0 + 8003046: d005 beq.n 8003054 + 8003048: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 800304c: 681b ldr r3, [r3, #0] + 800304e: f003 03f0 and.w r3, r3, #240 @ 0xf0 + 8003052: e006 b.n 8003062 + 8003054: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8003058: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 + 800305c: 091b lsrs r3, r3, #4 + 800305e: f003 03f0 and.w r3, r3, #240 @ 0xf0 + 8003062: 4293 cmp r3, r2 + 8003064: d222 bcs.n 80030ac + { + /* First increase number of wait states update if necessary */ + if (RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK) + 8003066: 687b ldr r3, [r7, #4] + 8003068: 6a9b ldr r3, [r3, #40] @ 0x28 + 800306a: 4618 mov r0, r3 + 800306c: f000 fd5a bl 8003b24 + 8003070: 4603 mov r3, r0 + 8003072: 2b00 cmp r3, #0 + 8003074: d001 beq.n 800307a + { + return HAL_ERROR; + 8003076: 2301 movs r3, #1 + 8003078: e331 b.n 80036de + } + + /* Selects the Multiple Speed oscillator (MSI) clock range .*/ + __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange); + 800307a: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 800307e: 681b ldr r3, [r3, #0] + 8003080: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 8003084: f043 0308 orr.w r3, r3, #8 + 8003088: 6013 str r3, [r2, #0] + 800308a: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 800308e: 681b ldr r3, [r3, #0] + 8003090: f023 02f0 bic.w r2, r3, #240 @ 0xf0 + 8003094: 687b ldr r3, [r7, #4] + 8003096: 6a9b ldr r3, [r3, #40] @ 0x28 + 8003098: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 800309c: 4313 orrs r3, r2 + 800309e: 600b str r3, [r1, #0] + /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/ + __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue); + 80030a0: 687b ldr r3, [r7, #4] + 80030a2: 6a5b ldr r3, [r3, #36] @ 0x24 + 80030a4: 4618 mov r0, r3 + 80030a6: f7ff fe2b bl 8002d00 + 80030aa: e021 b.n 80030f0 + } + else + { + /* Else, keep current flash latency while decreasing applies */ + /* Selects the Multiple Speed oscillator (MSI) clock range. */ + __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange); + 80030ac: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 80030b0: 681b ldr r3, [r3, #0] + 80030b2: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 80030b6: f043 0308 orr.w r3, r3, #8 + 80030ba: 6013 str r3, [r2, #0] + 80030bc: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 80030c0: 681b ldr r3, [r3, #0] + 80030c2: f023 02f0 bic.w r2, r3, #240 @ 0xf0 + 80030c6: 687b ldr r3, [r7, #4] + 80030c8: 6a9b ldr r3, [r3, #40] @ 0x28 + 80030ca: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 80030ce: 4313 orrs r3, r2 + 80030d0: 600b str r3, [r1, #0] + /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/ + __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue); + 80030d2: 687b ldr r3, [r7, #4] + 80030d4: 6a5b ldr r3, [r3, #36] @ 0x24 + 80030d6: 4618 mov r0, r3 + 80030d8: f7ff fe12 bl 8002d00 + + /* Decrease number of wait states update if necessary */ + if (RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK) + 80030dc: 687b ldr r3, [r7, #4] + 80030de: 6a9b ldr r3, [r3, #40] @ 0x28 + 80030e0: 4618 mov r0, r3 + 80030e2: f000 fd1f bl 8003b24 + 80030e6: 4603 mov r3, r0 + 80030e8: 2b00 cmp r3, #0 + 80030ea: d001 beq.n 80030f0 + { + return HAL_ERROR; + 80030ec: 2301 movs r3, #1 + 80030ee: e2f6 b.n 80036de + } + } + + /* Update the SystemCoreClock global variable */ + SystemCoreClock = HAL_RCC_GetHCLKFreq(); + 80030f0: f000 fce0 bl 8003ab4 + 80030f4: 4603 mov r3, r0 + 80030f6: 4aa7 ldr r2, [pc, #668] @ (8003394 ) + 80030f8: 6013 str r3, [r2, #0] + + /* Configure the source of time base considering new system clocks settings */ + status = HAL_InitTick(uwTickPrio); + 80030fa: 4ba7 ldr r3, [pc, #668] @ (8003398 ) + 80030fc: 681b ldr r3, [r3, #0] + 80030fe: 4618 mov r0, r3 + 8003100: f7fd fd98 bl 8000c34 + 8003104: 4603 mov r3, r0 + 8003106: 74fb strb r3, [r7, #19] + if (status != HAL_OK) + 8003108: 7cfb ldrb r3, [r7, #19] + 800310a: 2b00 cmp r3, #0 + 800310c: d047 beq.n 800319e + { + return status; + 800310e: 7cfb ldrb r3, [r7, #19] + 8003110: e2e5 b.n 80036de + } + } + else + { + /* Check the MSI State */ + if (RCC_OscInitStruct->MSIState != RCC_MSI_OFF) + 8003112: 687b ldr r3, [r7, #4] + 8003114: 6a1b ldr r3, [r3, #32] + 8003116: 2b00 cmp r3, #0 + 8003118: d02c beq.n 8003174 + { + /* Enable the Internal High Speed oscillator (MSI). */ + __HAL_RCC_MSI_ENABLE(); + 800311a: f7ff fd9e bl 8002c5a + + /* Get timeout */ + tickstart = HAL_GetTick(); + 800311e: f7fd fd93 bl 8000c48 + 8003122: 6178 str r0, [r7, #20] + + /* Wait till MSI is ready */ + while (LL_RCC_MSI_IsReady() == 0U) + 8003124: e008 b.n 8003138 + { + if ((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE) + 8003126: f7fd fd8f bl 8000c48 + 800312a: 4602 mov r2, r0 + 800312c: 697b ldr r3, [r7, #20] + 800312e: 1ad3 subs r3, r2, r3 + 8003130: 2b02 cmp r3, #2 + 8003132: d901 bls.n 8003138 + { + return HAL_TIMEOUT; + 8003134: 2303 movs r3, #3 + 8003136: e2d2 b.n 80036de + while (LL_RCC_MSI_IsReady() == 0U) + 8003138: f7ff fdab bl 8002c92 + 800313c: 4603 mov r3, r0 + 800313e: 2b00 cmp r3, #0 + 8003140: d0f1 beq.n 8003126 + } + } + + /* Selects the Multiple Speed oscillator (MSI) clock range. */ + __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange); + 8003142: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8003146: 681b ldr r3, [r3, #0] + 8003148: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 800314c: f043 0308 orr.w r3, r3, #8 + 8003150: 6013 str r3, [r2, #0] + 8003152: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8003156: 681b ldr r3, [r3, #0] + 8003158: f023 02f0 bic.w r2, r3, #240 @ 0xf0 + 800315c: 687b ldr r3, [r7, #4] + 800315e: 6a9b ldr r3, [r3, #40] @ 0x28 + 8003160: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 8003164: 4313 orrs r3, r2 + 8003166: 600b str r3, [r1, #0] + /* Adjusts the Multiple Speed oscillator (MSI) calibration value. */ + __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue); + 8003168: 687b ldr r3, [r7, #4] + 800316a: 6a5b ldr r3, [r3, #36] @ 0x24 + 800316c: 4618 mov r0, r3 + 800316e: f7ff fdc7 bl 8002d00 + 8003172: e015 b.n 80031a0 + + } + else + { + /* Disable the Internal High Speed oscillator (MSI). */ + __HAL_RCC_MSI_DISABLE(); + 8003174: f7ff fd7f bl 8002c76 + + /* Get timeout */ + tickstart = HAL_GetTick(); + 8003178: f7fd fd66 bl 8000c48 + 800317c: 6178 str r0, [r7, #20] + + /* Wait till MSI is disabled */ + while (LL_RCC_MSI_IsReady() != 0U) + 800317e: e008 b.n 8003192 + { + if ((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE) + 8003180: f7fd fd62 bl 8000c48 + 8003184: 4602 mov r2, r0 + 8003186: 697b ldr r3, [r7, #20] + 8003188: 1ad3 subs r3, r2, r3 + 800318a: 2b02 cmp r3, #2 + 800318c: d901 bls.n 8003192 + { + return HAL_TIMEOUT; + 800318e: 2303 movs r3, #3 + 8003190: e2a5 b.n 80036de + while (LL_RCC_MSI_IsReady() != 0U) + 8003192: f7ff fd7e bl 8002c92 + 8003196: 4603 mov r3, r0 + 8003198: 2b00 cmp r3, #0 + 800319a: d1f1 bne.n 8003180 + 800319c: e000 b.n 80031a0 + if (RCC_OscInitStruct->MSIState == RCC_MSI_OFF) + 800319e: bf00 nop + } + } + } + + /*------------------------------- HSE Configuration ------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) + 80031a0: 687b ldr r3, [r7, #4] + 80031a2: 681b ldr r3, [r3, #0] + 80031a4: f003 0301 and.w r3, r3, #1 + 80031a8: 2b00 cmp r3, #0 + 80031aa: d058 beq.n 800325e + { + /* Check the parameters */ + assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); + + /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ + if ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSE) || + 80031ac: 69fb ldr r3, [r7, #28] + 80031ae: 2b08 cmp r3, #8 + 80031b0: d005 beq.n 80031be + 80031b2: 69fb ldr r3, [r7, #28] + 80031b4: 2b0c cmp r3, #12 + 80031b6: d108 bne.n 80031ca + ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_HSE))) + 80031b8: 69bb ldr r3, [r7, #24] + 80031ba: 2b03 cmp r3, #3 + 80031bc: d105 bne.n 80031ca + { + if (RCC_OscInitStruct->HSEState == RCC_HSE_OFF) + 80031be: 687b ldr r3, [r7, #4] + 80031c0: 685b ldr r3, [r3, #4] + 80031c2: 2b00 cmp r3, #0 + 80031c4: d14b bne.n 800325e + { + return HAL_ERROR; + 80031c6: 2301 movs r3, #1 + 80031c8: e289 b.n 80036de + /* Set the new HSE configuration ---------------------------------------*/ + /* Check HSE division factor */ + assert_param(IS_RCC_HSEDIV(RCC_OscInitStruct->HSEDiv)); + + /* Set HSE division factor */ + MODIFY_REG(RCC->CR, RCC_CR_HSEPRE, RCC_OscInitStruct->HSEDiv); + 80031ca: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 80031ce: 681b ldr r3, [r3, #0] + 80031d0: f423 1280 bic.w r2, r3, #1048576 @ 0x100000 + 80031d4: 687b ldr r3, [r7, #4] + 80031d6: 689b ldr r3, [r3, #8] + 80031d8: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 80031dc: 4313 orrs r3, r2 + 80031de: 600b str r3, [r1, #0] + + __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); + 80031e0: 687b ldr r3, [r7, #4] + 80031e2: 685b ldr r3, [r3, #4] + 80031e4: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 + 80031e8: d102 bne.n 80031f0 + 80031ea: f7ff fc86 bl 8002afa + 80031ee: e00d b.n 800320c + 80031f0: 687b ldr r3, [r7, #4] + 80031f2: 685b ldr r3, [r3, #4] + 80031f4: f5b3 1f04 cmp.w r3, #2162688 @ 0x210000 + 80031f8: d104 bne.n 8003204 + 80031fa: f7ff fc51 bl 8002aa0 + 80031fe: f7ff fc7c bl 8002afa + 8003202: e003 b.n 800320c + 8003204: f7ff fc87 bl 8002b16 + 8003208: f7ff fc58 bl 8002abc + + /* Check the HSE State */ + if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF) + 800320c: 687b ldr r3, [r7, #4] + 800320e: 685b ldr r3, [r3, #4] + 8003210: 2b00 cmp r3, #0 + 8003212: d012 beq.n 800323a + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8003214: f7fd fd18 bl 8000c48 + 8003218: 6178 str r0, [r7, #20] + + /* Wait till HSE is ready */ + while (LL_RCC_HSE_IsReady() == 0U) + 800321a: e008 b.n 800322e + { + if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) + 800321c: f7fd fd14 bl 8000c48 + 8003220: 4602 mov r2, r0 + 8003222: 697b ldr r3, [r7, #20] + 8003224: 1ad3 subs r3, r2, r3 + 8003226: 2b64 cmp r3, #100 @ 0x64 + 8003228: d901 bls.n 800322e + { + return HAL_TIMEOUT; + 800322a: 2303 movs r3, #3 + 800322c: e257 b.n 80036de + while (LL_RCC_HSE_IsReady() == 0U) + 800322e: f7ff fc80 bl 8002b32 + 8003232: 4603 mov r3, r0 + 8003234: 2b00 cmp r3, #0 + 8003236: d0f1 beq.n 800321c + 8003238: e011 b.n 800325e + } + } + else + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 800323a: f7fd fd05 bl 8000c48 + 800323e: 6178 str r0, [r7, #20] + + /* Wait till HSE is disabled */ + while (LL_RCC_HSE_IsReady() != 0U) + 8003240: e008 b.n 8003254 + { + if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) + 8003242: f7fd fd01 bl 8000c48 + 8003246: 4602 mov r2, r0 + 8003248: 697b ldr r3, [r7, #20] + 800324a: 1ad3 subs r3, r2, r3 + 800324c: 2b64 cmp r3, #100 @ 0x64 + 800324e: d901 bls.n 8003254 + { + return HAL_TIMEOUT; + 8003250: 2303 movs r3, #3 + 8003252: e244 b.n 80036de + while (LL_RCC_HSE_IsReady() != 0U) + 8003254: f7ff fc6d bl 8002b32 + 8003258: 4603 mov r3, r0 + 800325a: 2b00 cmp r3, #0 + 800325c: d1f1 bne.n 8003242 + } + } + } + + /*----------------------------- HSI Configuration --------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) + 800325e: 687b ldr r3, [r7, #4] + 8003260: 681b ldr r3, [r3, #0] + 8003262: f003 0302 and.w r3, r3, #2 + 8003266: 2b00 cmp r3, #0 + 8003268: d046 beq.n 80032f8 + /* Check the parameters */ + assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); + assert_param(IS_RCC_HSI_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); + + /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ + if ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSI) || + 800326a: 69fb ldr r3, [r7, #28] + 800326c: 2b04 cmp r3, #4 + 800326e: d005 beq.n 800327c + 8003270: 69fb ldr r3, [r7, #28] + 8003272: 2b0c cmp r3, #12 + 8003274: d10e bne.n 8003294 + ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_HSI))) + 8003276: 69bb ldr r3, [r7, #24] + 8003278: 2b02 cmp r3, #2 + 800327a: d10b bne.n 8003294 + { + /* When HSI is used as system clock it will not be disabled */ + if (RCC_OscInitStruct->HSIState == RCC_HSI_OFF) + 800327c: 687b ldr r3, [r7, #4] + 800327e: 691b ldr r3, [r3, #16] + 8003280: 2b00 cmp r3, #0 + 8003282: d101 bne.n 8003288 + { + return HAL_ERROR; + 8003284: 2301 movs r3, #1 + 8003286: e22a b.n 80036de + } + /* Otherwise, just the calibration is allowed */ + else + { + /* Adjusts the Internal High Speed oscillator (HSI) calibration value. */ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + 8003288: 687b ldr r3, [r7, #4] + 800328a: 695b ldr r3, [r3, #20] + 800328c: 4618 mov r0, r3 + 800328e: f7ff fc8e bl 8002bae + if (RCC_OscInitStruct->HSIState == RCC_HSI_OFF) + 8003292: e031 b.n 80032f8 + } + } + else + { + /* Check the HSI State */ + if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF) + 8003294: 687b ldr r3, [r7, #4] + 8003296: 691b ldr r3, [r3, #16] + 8003298: 2b00 cmp r3, #0 + 800329a: d019 beq.n 80032d0 + { + /* Enable the Internal High Speed oscillator (HSI). */ + __HAL_RCC_HSI_ENABLE(); + 800329c: f7ff fc5a bl 8002b54 + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 80032a0: f7fd fcd2 bl 8000c48 + 80032a4: 6178 str r0, [r7, #20] + + /* Wait till HSI is ready */ + while (LL_RCC_HSI_IsReady() == 0U) + 80032a6: e008 b.n 80032ba + { + if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) + 80032a8: f7fd fcce bl 8000c48 + 80032ac: 4602 mov r2, r0 + 80032ae: 697b ldr r3, [r7, #20] + 80032b0: 1ad3 subs r3, r2, r3 + 80032b2: 2b02 cmp r3, #2 + 80032b4: d901 bls.n 80032ba + { + return HAL_TIMEOUT; + 80032b6: 2303 movs r3, #3 + 80032b8: e211 b.n 80036de + while (LL_RCC_HSI_IsReady() == 0U) + 80032ba: f7ff fc67 bl 8002b8c + 80032be: 4603 mov r3, r0 + 80032c0: 2b00 cmp r3, #0 + 80032c2: d0f1 beq.n 80032a8 + } + } + + /* Adjusts the Internal High Speed oscillator (HSI) calibration value. */ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + 80032c4: 687b ldr r3, [r7, #4] + 80032c6: 695b ldr r3, [r3, #20] + 80032c8: 4618 mov r0, r3 + 80032ca: f7ff fc70 bl 8002bae + 80032ce: e013 b.n 80032f8 + } + else + { + /* Disable the Internal High Speed oscillator (HSI). */ + __HAL_RCC_HSI_DISABLE(); + 80032d0: f7ff fc4e bl 8002b70 + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 80032d4: f7fd fcb8 bl 8000c48 + 80032d8: 6178 str r0, [r7, #20] + + /* Wait till HSI is disabled */ + while (LL_RCC_HSI_IsReady() != 0U) + 80032da: e008 b.n 80032ee + { + if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) + 80032dc: f7fd fcb4 bl 8000c48 + 80032e0: 4602 mov r2, r0 + 80032e2: 697b ldr r3, [r7, #20] + 80032e4: 1ad3 subs r3, r2, r3 + 80032e6: 2b02 cmp r3, #2 + 80032e8: d901 bls.n 80032ee + { + return HAL_TIMEOUT; + 80032ea: 2303 movs r3, #3 + 80032ec: e1f7 b.n 80036de + while (LL_RCC_HSI_IsReady() != 0U) + 80032ee: f7ff fc4d bl 8002b8c + 80032f2: 4603 mov r3, r0 + 80032f4: 2b00 cmp r3, #0 + 80032f6: d1f1 bne.n 80032dc + } + } + } + + /*------------------------------ LSI Configuration -------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) + 80032f8: 687b ldr r3, [r7, #4] + 80032fa: 681b ldr r3, [r3, #0] + 80032fc: f003 0308 and.w r3, r3, #8 + 8003300: 2b00 cmp r3, #0 + 8003302: d06e beq.n 80033e2 + { + /* Check the parameters */ + assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); + + /* Check the LSI State */ + if (RCC_OscInitStruct->LSIState != RCC_LSI_OFF) + 8003304: 687b ldr r3, [r7, #4] + 8003306: 699b ldr r3, [r3, #24] + 8003308: 2b00 cmp r3, #0 + 800330a: d056 beq.n 80033ba + { + uint32_t csr_temp = RCC->CSR; + 800330c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8003310: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 + 8003314: 60fb str r3, [r7, #12] + + /* Check LSI division factor */ + assert_param(IS_RCC_LSIDIV(RCC_OscInitStruct->LSIDiv)); + + if (RCC_OscInitStruct->LSIDiv != (csr_temp & RCC_CSR_LSIPRE)) + 8003316: 687b ldr r3, [r7, #4] + 8003318: 69da ldr r2, [r3, #28] + 800331a: 68fb ldr r3, [r7, #12] + 800331c: f003 0310 and.w r3, r3, #16 + 8003320: 429a cmp r2, r3 + 8003322: d031 beq.n 8003388 + { + if (((csr_temp & RCC_CSR_LSIRDY) == RCC_CSR_LSIRDY) && \ + 8003324: 68fb ldr r3, [r7, #12] + 8003326: f003 0302 and.w r3, r3, #2 + 800332a: 2b00 cmp r3, #0 + 800332c: d006 beq.n 800333c + ((csr_temp & RCC_CSR_LSION) != RCC_CSR_LSION)) + 800332e: 68fb ldr r3, [r7, #12] + 8003330: f003 0301 and.w r3, r3, #1 + if (((csr_temp & RCC_CSR_LSIRDY) == RCC_CSR_LSIRDY) && \ + 8003334: 2b00 cmp r3, #0 + 8003336: d101 bne.n 800333c + { + /* If LSIRDY is set while LSION is not enabled, + LSIPRE can't be updated */ + return HAL_ERROR; + 8003338: 2301 movs r3, #1 + 800333a: e1d0 b.n 80036de + } + + /* Turn off LSI before changing RCC_CSR_LSIPRE */ + if ((csr_temp & RCC_CSR_LSION) == RCC_CSR_LSION) + 800333c: 68fb ldr r3, [r7, #12] + 800333e: f003 0301 and.w r3, r3, #1 + 8003342: 2b00 cmp r3, #0 + 8003344: d013 beq.n 800336e + { + __HAL_RCC_LSI_DISABLE(); + 8003346: f7ff fc67 bl 8002c18 + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 800334a: f7fd fc7d bl 8000c48 + 800334e: 6178 str r0, [r7, #20] + + /* Wait till LSI is disabled */ + while (LL_RCC_LSI_IsReady() != 0U) + 8003350: e008 b.n 8003364 + { + if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) + 8003352: f7fd fc79 bl 8000c48 + 8003356: 4602 mov r2, r0 + 8003358: 697b ldr r3, [r7, #20] + 800335a: 1ad3 subs r3, r2, r3 + 800335c: 2b11 cmp r3, #17 + 800335e: d901 bls.n 8003364 + { + return HAL_TIMEOUT; + 8003360: 2303 movs r3, #3 + 8003362: e1bc b.n 80036de + while (LL_RCC_LSI_IsReady() != 0U) + 8003364: f7ff fc68 bl 8002c38 + 8003368: 4603 mov r3, r0 + 800336a: 2b00 cmp r3, #0 + 800336c: d1f1 bne.n 8003352 + } + } + } + + /* Set LSI division factor */ + MODIFY_REG(RCC->CSR, RCC_CSR_LSIPRE, RCC_OscInitStruct->LSIDiv); + 800336e: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8003372: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 + 8003376: f023 0210 bic.w r2, r3, #16 + 800337a: 687b ldr r3, [r7, #4] + 800337c: 69db ldr r3, [r3, #28] + 800337e: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 8003382: 4313 orrs r3, r2 + 8003384: f8c1 3094 str.w r3, [r1, #148] @ 0x94 + } + + /* Enable the Internal Low Speed oscillator (LSI). */ + __HAL_RCC_LSI_ENABLE(); + 8003388: f7ff fc36 bl 8002bf8 + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 800338c: f7fd fc5c bl 8000c48 + 8003390: 6178 str r0, [r7, #20] + + /* Wait till LSI is ready */ + while (LL_RCC_LSI_IsReady() == 0U) + 8003392: e00c b.n 80033ae + 8003394: 20000000 .word 0x20000000 + 8003398: 20000004 .word 0x20000004 + { + if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) + 800339c: f7fd fc54 bl 8000c48 + 80033a0: 4602 mov r2, r0 + 80033a2: 697b ldr r3, [r7, #20] + 80033a4: 1ad3 subs r3, r2, r3 + 80033a6: 2b11 cmp r3, #17 + 80033a8: d901 bls.n 80033ae + { + return HAL_TIMEOUT; + 80033aa: 2303 movs r3, #3 + 80033ac: e197 b.n 80036de + while (LL_RCC_LSI_IsReady() == 0U) + 80033ae: f7ff fc43 bl 8002c38 + 80033b2: 4603 mov r3, r0 + 80033b4: 2b00 cmp r3, #0 + 80033b6: d0f1 beq.n 800339c + 80033b8: e013 b.n 80033e2 + } + } + else + { + /* Disable the Internal Low Speed oscillator (LSI). */ + __HAL_RCC_LSI_DISABLE(); + 80033ba: f7ff fc2d bl 8002c18 + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 80033be: f7fd fc43 bl 8000c48 + 80033c2: 6178 str r0, [r7, #20] + + /* Wait till LSI is disabled */ + while (LL_RCC_LSI_IsReady() != 0U) + 80033c4: e008 b.n 80033d8 + { + if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) + 80033c6: f7fd fc3f bl 8000c48 + 80033ca: 4602 mov r2, r0 + 80033cc: 697b ldr r3, [r7, #20] + 80033ce: 1ad3 subs r3, r2, r3 + 80033d0: 2b11 cmp r3, #17 + 80033d2: d901 bls.n 80033d8 + { + return HAL_TIMEOUT; + 80033d4: 2303 movs r3, #3 + 80033d6: e182 b.n 80036de + while (LL_RCC_LSI_IsReady() != 0U) + 80033d8: f7ff fc2e bl 8002c38 + 80033dc: 4603 mov r3, r0 + 80033de: 2b00 cmp r3, #0 + 80033e0: d1f1 bne.n 80033c6 + } + } + } + + /*------------------------------ LSE Configuration -------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) + 80033e2: 687b ldr r3, [r7, #4] + 80033e4: 681b ldr r3, [r3, #0] + 80033e6: f003 0304 and.w r3, r3, #4 + 80033ea: 2b00 cmp r3, #0 + 80033ec: f000 80d8 beq.w 80035a0 + assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); + + /* Update LSE configuration in Backup Domain control register */ + /* Requires to enable write access to Backup Domain of necessary */ + + if (LL_PWR_IsEnabledBkUpAccess() == 0U) + 80033f0: f7ff fb44 bl 8002a7c + 80033f4: 4603 mov r3, r0 + 80033f6: 2b00 cmp r3, #0 + 80033f8: d113 bne.n 8003422 + { + /* Enable write access to Backup domain */ + HAL_PWR_EnableBkUpAccess(); + 80033fa: f7ff fa83 bl 8002904 + + /* Wait for Backup domain Write protection disable */ + tickstart = HAL_GetTick(); + 80033fe: f7fd fc23 bl 8000c48 + 8003402: 6178 str r0, [r7, #20] + + while (LL_PWR_IsEnabledBkUpAccess() == 0U) + 8003404: e008 b.n 8003418 + { + if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + 8003406: f7fd fc1f bl 8000c48 + 800340a: 4602 mov r2, r0 + 800340c: 697b ldr r3, [r7, #20] + 800340e: 1ad3 subs r3, r2, r3 + 8003410: 2b02 cmp r3, #2 + 8003412: d901 bls.n 8003418 + { + return HAL_TIMEOUT; + 8003414: 2303 movs r3, #3 + 8003416: e162 b.n 80036de + while (LL_PWR_IsEnabledBkUpAccess() == 0U) + 8003418: f7ff fb30 bl 8002a7c + 800341c: 4603 mov r3, r0 + 800341e: 2b00 cmp r3, #0 + 8003420: d0f1 beq.n 8003406 + } + } + } + + /* Set the new LSE configuration -----------------------------------------*/ + if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF) + 8003422: 687b ldr r3, [r7, #4] + 8003424: 68db ldr r3, [r3, #12] + 8003426: 2b00 cmp r3, #0 + 8003428: d07b beq.n 8003522 + { + /* Enable LSE bypasss (if requested) */ + if ((RCC_OscInitStruct->LSEState == RCC_LSE_BYPASS) + 800342a: 687b ldr r3, [r7, #4] + 800342c: 68db ldr r3, [r3, #12] + 800342e: 2b85 cmp r3, #133 @ 0x85 + 8003430: d003 beq.n 800343a + || (RCC_OscInitStruct->LSEState == RCC_LSE_BYPASS_RTC_ONLY)) + 8003432: 687b ldr r3, [r7, #4] + 8003434: 68db ldr r3, [r3, #12] + 8003436: 2b05 cmp r3, #5 + 8003438: d109 bne.n 800344e + { + /* LSE oscillator bypass enable */ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); + 800343a: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 800343e: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 8003442: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 8003446: f043 0304 orr.w r3, r3, #4 + 800344a: f8c2 3090 str.w r3, [r2, #144] @ 0x90 + } + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 800344e: f7fd fbfb bl 8000c48 + 8003452: 6178 str r0, [r7, #20] + + /* LSE oscillator enable */ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); + 8003454: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8003458: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 800345c: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 8003460: f043 0301 orr.w r3, r3, #1 + 8003464: f8c2 3090 str.w r3, [r2, #144] @ 0x90 + + /* Wait till LSE is ready */ + while (LL_RCC_LSE_IsReady() == 0U) + 8003468: e00a b.n 8003480 + { + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + 800346a: f7fd fbed bl 8000c48 + 800346e: 4602 mov r2, r0 + 8003470: 697b ldr r3, [r7, #20] + 8003472: 1ad3 subs r3, r2, r3 + 8003474: f241 3288 movw r2, #5000 @ 0x1388 + 8003478: 4293 cmp r3, r2 + 800347a: d901 bls.n 8003480 + { + return HAL_TIMEOUT; + 800347c: 2303 movs r3, #3 + 800347e: e12e b.n 80036de + while (LL_RCC_LSE_IsReady() == 0U) + 8003480: f7ff fba9 bl 8002bd6 + 8003484: 4603 mov r3, r0 + 8003486: 2b00 cmp r3, #0 + 8003488: d0ef beq.n 800346a + } + } + + /* Enable LSE system clock (if requested) */ + if ((RCC_OscInitStruct->LSEState == RCC_LSE_ON) + 800348a: 687b ldr r3, [r7, #4] + 800348c: 68db ldr r3, [r3, #12] + 800348e: 2b81 cmp r3, #129 @ 0x81 + 8003490: d003 beq.n 800349a + || (RCC_OscInitStruct->LSEState == RCC_LSE_BYPASS)) + 8003492: 687b ldr r3, [r7, #4] + 8003494: 68db ldr r3, [r3, #12] + 8003496: 2b85 cmp r3, #133 @ 0x85 + 8003498: d121 bne.n 80034de + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 800349a: f7fd fbd5 bl 8000c48 + 800349e: 6178 str r0, [r7, #20] + + SET_BIT(RCC->BDCR, RCC_BDCR_LSESYSEN); + 80034a0: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 80034a4: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 80034a8: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 80034ac: f043 0380 orr.w r3, r3, #128 @ 0x80 + 80034b0: f8c2 3090 str.w r3, [r2, #144] @ 0x90 + + /* Wait till LSESYS is ready */ + while (READ_BIT(RCC->BDCR, RCC_BDCR_LSESYSRDY) == 0U) + 80034b4: e00a b.n 80034cc + { + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + 80034b6: f7fd fbc7 bl 8000c48 + 80034ba: 4602 mov r2, r0 + 80034bc: 697b ldr r3, [r7, #20] + 80034be: 1ad3 subs r3, r2, r3 + 80034c0: f241 3288 movw r2, #5000 @ 0x1388 + 80034c4: 4293 cmp r3, r2 + 80034c6: d901 bls.n 80034cc + { + return HAL_TIMEOUT; + 80034c8: 2303 movs r3, #3 + 80034ca: e108 b.n 80036de + while (READ_BIT(RCC->BDCR, RCC_BDCR_LSESYSRDY) == 0U) + 80034cc: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 80034d0: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 80034d4: f403 6300 and.w r3, r3, #2048 @ 0x800 + 80034d8: 2b00 cmp r3, #0 + 80034da: d0ec beq.n 80034b6 + if ((RCC_OscInitStruct->LSEState == RCC_LSE_ON) + 80034dc: e060 b.n 80035a0 + } + } + else + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 80034de: f7fd fbb3 bl 8000c48 + 80034e2: 6178 str r0, [r7, #20] + + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSESYSEN); + 80034e4: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 80034e8: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 80034ec: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 80034f0: f023 0380 bic.w r3, r3, #128 @ 0x80 + 80034f4: f8c2 3090 str.w r3, [r2, #144] @ 0x90 + + /* Wait till LSESYSRDY is cleared */ + while (READ_BIT(RCC->BDCR, RCC_BDCR_LSESYSRDY) != 0U) + 80034f8: e00a b.n 8003510 + { + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + 80034fa: f7fd fba5 bl 8000c48 + 80034fe: 4602 mov r2, r0 + 8003500: 697b ldr r3, [r7, #20] + 8003502: 1ad3 subs r3, r2, r3 + 8003504: f241 3288 movw r2, #5000 @ 0x1388 + 8003508: 4293 cmp r3, r2 + 800350a: d901 bls.n 8003510 + { + return HAL_TIMEOUT; + 800350c: 2303 movs r3, #3 + 800350e: e0e6 b.n 80036de + while (READ_BIT(RCC->BDCR, RCC_BDCR_LSESYSRDY) != 0U) + 8003510: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8003514: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 8003518: f403 6300 and.w r3, r3, #2048 @ 0x800 + 800351c: 2b00 cmp r3, #0 + 800351e: d1ec bne.n 80034fa + 8003520: e03e b.n 80035a0 + } + } + else + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8003522: f7fd fb91 bl 8000c48 + 8003526: 6178 str r0, [r7, #20] + + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSESYSEN); + 8003528: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 800352c: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 8003530: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 8003534: f023 0380 bic.w r3, r3, #128 @ 0x80 + 8003538: f8c2 3090 str.w r3, [r2, #144] @ 0x90 + + /* Wait till LSESYSRDY is cleared */ + while (READ_BIT(RCC->BDCR, RCC_BDCR_LSESYSRDY) != 0U) + 800353c: e00a b.n 8003554 + { + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + 800353e: f7fd fb83 bl 8000c48 + 8003542: 4602 mov r2, r0 + 8003544: 697b ldr r3, [r7, #20] + 8003546: 1ad3 subs r3, r2, r3 + 8003548: f241 3288 movw r2, #5000 @ 0x1388 + 800354c: 4293 cmp r3, r2 + 800354e: d901 bls.n 8003554 + { + return HAL_TIMEOUT; + 8003550: 2303 movs r3, #3 + 8003552: e0c4 b.n 80036de + while (READ_BIT(RCC->BDCR, RCC_BDCR_LSESYSRDY) != 0U) + 8003554: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8003558: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 800355c: f403 6300 and.w r3, r3, #2048 @ 0x800 + 8003560: 2b00 cmp r3, #0 + 8003562: d1ec bne.n 800353e + } + } + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8003564: f7fd fb70 bl 8000c48 + 8003568: 6178 str r0, [r7, #20] + + /* LSE oscillator disable */ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); + 800356a: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 800356e: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 8003572: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 8003576: f023 0301 bic.w r3, r3, #1 + 800357a: f8c2 3090 str.w r3, [r2, #144] @ 0x90 + + /* Wait till LSE is disabled */ + while (LL_RCC_LSE_IsReady() != 0U) + 800357e: e00a b.n 8003596 + { + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + 8003580: f7fd fb62 bl 8000c48 + 8003584: 4602 mov r2, r0 + 8003586: 697b ldr r3, [r7, #20] + 8003588: 1ad3 subs r3, r2, r3 + 800358a: f241 3288 movw r2, #5000 @ 0x1388 + 800358e: 4293 cmp r3, r2 + 8003590: d901 bls.n 8003596 + { + return HAL_TIMEOUT; + 8003592: 2303 movs r3, #3 + 8003594: e0a3 b.n 80036de + while (LL_RCC_LSE_IsReady() != 0U) + 8003596: f7ff fb1e bl 8002bd6 + 800359a: 4603 mov r3, r0 + 800359c: 2b00 cmp r3, #0 + 800359e: d1ef bne.n 8003580 + + /*-------------------------------- PLL Configuration -----------------------*/ + /* Check the parameters */ + assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); + + if (RCC_OscInitStruct->PLL.PLLState != RCC_PLL_NONE) + 80035a0: 687b ldr r3, [r7, #4] + 80035a2: 6adb ldr r3, [r3, #44] @ 0x2c + 80035a4: 2b00 cmp r3, #0 + 80035a6: f000 8099 beq.w 80036dc + { + /* Check if the PLL is used as system clock or not */ + if (sysclk_source != RCC_SYSCLKSOURCE_STATUS_PLLCLK) + 80035aa: 69fb ldr r3, [r7, #28] + 80035ac: 2b0c cmp r3, #12 + 80035ae: d06c beq.n 800368a + { + if (RCC_OscInitStruct->PLL.PLLState == RCC_PLL_ON) + 80035b0: 687b ldr r3, [r7, #4] + 80035b2: 6adb ldr r3, [r3, #44] @ 0x2c + 80035b4: 2b02 cmp r3, #2 + 80035b6: d14b bne.n 8003650 + assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP)); + assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ)); + assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR)); + + /* Disable the main PLL. */ + __HAL_RCC_PLL_DISABLE(); + 80035b8: f7ff fc74 bl 8002ea4 + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 80035bc: f7fd fb44 bl 8000c48 + 80035c0: 6178 str r0, [r7, #20] + + /* Wait till PLL is ready */ + while (LL_RCC_PLL_IsReady() != 0U) + 80035c2: e008 b.n 80035d6 + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + 80035c4: f7fd fb40 bl 8000c48 + 80035c8: 4602 mov r2, r0 + 80035ca: 697b ldr r3, [r7, #20] + 80035cc: 1ad3 subs r3, r2, r3 + 80035ce: 2b0a cmp r3, #10 + 80035d0: d901 bls.n 80035d6 + { + return HAL_TIMEOUT; + 80035d2: 2303 movs r3, #3 + 80035d4: e083 b.n 80036de + while (LL_RCC_PLL_IsReady() != 0U) + 80035d6: f7ff fc73 bl 8002ec0 + 80035da: 4603 mov r3, r0 + 80035dc: 2b00 cmp r3, #0 + 80035de: d1f1 bne.n 80035c4 + } + } + + /* Configure the main PLL clock source, multiplication and division factors. */ + __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, + 80035e0: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 80035e4: 68da ldr r2, [r3, #12] + 80035e6: 4b40 ldr r3, [pc, #256] @ (80036e8 ) + 80035e8: 4013 ands r3, r2 + 80035ea: 687a ldr r2, [r7, #4] + 80035ec: 6b11 ldr r1, [r2, #48] @ 0x30 + 80035ee: 687a ldr r2, [r7, #4] + 80035f0: 6b52 ldr r2, [r2, #52] @ 0x34 + 80035f2: 4311 orrs r1, r2 + 80035f4: 687a ldr r2, [r7, #4] + 80035f6: 6b92 ldr r2, [r2, #56] @ 0x38 + 80035f8: 0212 lsls r2, r2, #8 + 80035fa: 4311 orrs r1, r2 + 80035fc: 687a ldr r2, [r7, #4] + 80035fe: 6bd2 ldr r2, [r2, #60] @ 0x3c + 8003600: 4311 orrs r1, r2 + 8003602: 687a ldr r2, [r7, #4] + 8003604: 6c12 ldr r2, [r2, #64] @ 0x40 + 8003606: 4311 orrs r1, r2 + 8003608: 687a ldr r2, [r7, #4] + 800360a: 6c52 ldr r2, [r2, #68] @ 0x44 + 800360c: 430a orrs r2, r1 + 800360e: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 8003612: 4313 orrs r3, r2 + 8003614: 60cb str r3, [r1, #12] + RCC_OscInitStruct->PLL.PLLP, + RCC_OscInitStruct->PLL.PLLQ, + RCC_OscInitStruct->PLL.PLLR); + + /* Enable the main PLL. */ + __HAL_RCC_PLL_ENABLE(); + 8003616: f7ff fc37 bl 8002e88 + + /* Enable PLL System Clock output. */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SYSCLK); + 800361a: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 800361e: 68db ldr r3, [r3, #12] + 8003620: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 8003624: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 + 8003628: 60d3 str r3, [r2, #12] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 800362a: f7fd fb0d bl 8000c48 + 800362e: 6178 str r0, [r7, #20] + + /* Wait till PLL is ready */ + while (LL_RCC_PLL_IsReady() == 0U) + 8003630: e008 b.n 8003644 + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + 8003632: f7fd fb09 bl 8000c48 + 8003636: 4602 mov r2, r0 + 8003638: 697b ldr r3, [r7, #20] + 800363a: 1ad3 subs r3, r2, r3 + 800363c: 2b0a cmp r3, #10 + 800363e: d901 bls.n 8003644 + { + return HAL_TIMEOUT; + 8003640: 2303 movs r3, #3 + 8003642: e04c b.n 80036de + while (LL_RCC_PLL_IsReady() == 0U) + 8003644: f7ff fc3c bl 8002ec0 + 8003648: 4603 mov r3, r0 + 800364a: 2b00 cmp r3, #0 + 800364c: d0f1 beq.n 8003632 + 800364e: e045 b.n 80036dc + } + } + else + { + /* Disable the main PLL. */ + __HAL_RCC_PLL_DISABLE(); + 8003650: f7ff fc28 bl 8002ea4 + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8003654: f7fd faf8 bl 8000c48 + 8003658: 6178 str r0, [r7, #20] + + /* Wait till PLL is disabled */ + while (LL_RCC_PLL_IsReady() != 0U) + 800365a: e008 b.n 800366e + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + 800365c: f7fd faf4 bl 8000c48 + 8003660: 4602 mov r2, r0 + 8003662: 697b ldr r3, [r7, #20] + 8003664: 1ad3 subs r3, r2, r3 + 8003666: 2b0a cmp r3, #10 + 8003668: d901 bls.n 800366e + { + return HAL_TIMEOUT; + 800366a: 2303 movs r3, #3 + 800366c: e037 b.n 80036de + while (LL_RCC_PLL_IsReady() != 0U) + 800366e: f7ff fc27 bl 8002ec0 + 8003672: 4603 mov r3, r0 + 8003674: 2b00 cmp r3, #0 + 8003676: d1f1 bne.n 800365c + } + } + + /* Disable the PLL source and outputs to save power when PLL is off */ + CLEAR_BIT(RCC->PLLCFGR, (RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLPEN | RCC_PLLCFGR_PLLQEN | RCC_PLLCFGR_PLLREN)); + 8003678: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 800367c: 68da ldr r2, [r3, #12] + 800367e: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 8003682: 4b1a ldr r3, [pc, #104] @ (80036ec ) + 8003684: 4013 ands r3, r2 + 8003686: 60cb str r3, [r1, #12] + 8003688: e028 b.n 80036dc + } + } + else + { + /* Check if there is a request to disable the PLL used as System clock source */ + if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) + 800368a: 687b ldr r3, [r7, #4] + 800368c: 6adb ldr r3, [r3, #44] @ 0x2c + 800368e: 2b01 cmp r3, #1 + 8003690: d101 bne.n 8003696 + { + return HAL_ERROR; + 8003692: 2301 movs r3, #1 + 8003694: e023 b.n 80036de + } + else + { + /* Do not return HAL_ERROR if request repeats the current configuration */ + pll_config = RCC->PLLCFGR; + 8003696: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 800369a: 68db ldr r3, [r3, #12] + 800369c: 61bb str r3, [r7, #24] + if ((READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) + 800369e: 69bb ldr r3, [r7, #24] + 80036a0: f003 0203 and.w r2, r3, #3 + 80036a4: 687b ldr r3, [r7, #4] + 80036a6: 6b1b ldr r3, [r3, #48] @ 0x30 + 80036a8: 429a cmp r2, r3 + 80036aa: d115 bne.n 80036d8 + || (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) + 80036ac: 69bb ldr r3, [r7, #24] + 80036ae: f003 0270 and.w r2, r3, #112 @ 0x70 + 80036b2: 687b ldr r3, [r7, #4] + 80036b4: 6b5b ldr r3, [r3, #52] @ 0x34 + 80036b6: 429a cmp r2, r3 + 80036b8: d10e bne.n 80036d8 + || (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) + 80036ba: 69bb ldr r3, [r7, #24] + 80036bc: f403 42fe and.w r2, r3, #32512 @ 0x7f00 + 80036c0: 687b ldr r3, [r7, #4] + 80036c2: 6b9b ldr r3, [r3, #56] @ 0x38 + 80036c4: 021b lsls r3, r3, #8 + 80036c6: 429a cmp r2, r3 + 80036c8: d106 bne.n 80036d8 + || (READ_BIT(pll_config, RCC_PLLCFGR_PLLR) != RCC_OscInitStruct->PLL.PLLR)) + 80036ca: 69bb ldr r3, [r7, #24] + 80036cc: f003 4260 and.w r2, r3, #3758096384 @ 0xe0000000 + 80036d0: 687b ldr r3, [r7, #4] + 80036d2: 6c5b ldr r3, [r3, #68] @ 0x44 + 80036d4: 429a cmp r2, r3 + 80036d6: d001 beq.n 80036dc + { + return HAL_ERROR; + 80036d8: 2301 movs r3, #1 + 80036da: e000 b.n 80036de + } + } + } + } + return HAL_OK; + 80036dc: 2300 movs r3, #0 +} + 80036de: 4618 mov r0, r3 + 80036e0: 3720 adds r7, #32 + 80036e2: 46bd mov sp, r7 + 80036e4: bd80 pop {r7, pc} + 80036e6: bf00 nop + 80036e8: 11c1808c .word 0x11c1808c + 80036ec: eefefffc .word 0xeefefffc + +080036f0 : + * HPRE[3:0] bits to ensure that HCLK1 not exceed the maximum allowed frequency + * (for more details refer to section above "Initialization/de-initialization functions") + * @retval None + */ +HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) +{ + 80036f0: b580 push {r7, lr} + 80036f2: b084 sub sp, #16 + 80036f4: af00 add r7, sp, #0 + 80036f6: 6078 str r0, [r7, #4] + 80036f8: 6039 str r1, [r7, #0] + uint32_t tickstart; + + /* Check Null pointer */ + if (RCC_ClkInitStruct == NULL) + 80036fa: 687b ldr r3, [r7, #4] + 80036fc: 2b00 cmp r3, #0 + 80036fe: d101 bne.n 8003704 + { + return HAL_ERROR; + 8003700: 2301 movs r3, #1 + 8003702: e12c b.n 800395e + /* To correctly read data from FLASH memory, the number of wait states (LATENCY) + must be correctly programmed according to the frequency of the FLASH clock + (HCLK3) and the supply voltage of the device. */ + + /* Increasing the number of wait states because of higher CPU frequency */ + if (FLatency > __HAL_FLASH_GET_LATENCY()) + 8003704: 4b98 ldr r3, [pc, #608] @ (8003968 ) + 8003706: 681b ldr r3, [r3, #0] + 8003708: f003 0307 and.w r3, r3, #7 + 800370c: 683a ldr r2, [r7, #0] + 800370e: 429a cmp r2, r3 + 8003710: d91b bls.n 800374a + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLatency); + 8003712: 4b95 ldr r3, [pc, #596] @ (8003968 ) + 8003714: 681b ldr r3, [r3, #0] + 8003716: f023 0207 bic.w r2, r3, #7 + 800371a: 4993 ldr r1, [pc, #588] @ (8003968 ) + 800371c: 683b ldr r3, [r7, #0] + 800371e: 4313 orrs r3, r2 + 8003720: 600b str r3, [r1, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8003722: f7fd fa91 bl 8000c48 + 8003726: 60f8 str r0, [r7, #12] + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + while (__HAL_FLASH_GET_LATENCY() != FLatency) + 8003728: e008 b.n 800373c + { + if ((HAL_GetTick() - tickstart) > LATENCY_TIMEOUT_VALUE) + 800372a: f7fd fa8d bl 8000c48 + 800372e: 4602 mov r2, r0 + 8003730: 68fb ldr r3, [r7, #12] + 8003732: 1ad3 subs r3, r2, r3 + 8003734: 2b02 cmp r3, #2 + 8003736: d901 bls.n 800373c + { + return HAL_TIMEOUT; + 8003738: 2303 movs r3, #3 + 800373a: e110 b.n 800395e + while (__HAL_FLASH_GET_LATENCY() != FLatency) + 800373c: 4b8a ldr r3, [pc, #552] @ (8003968 ) + 800373e: 681b ldr r3, [r3, #0] + 8003740: f003 0307 and.w r3, r3, #7 + 8003744: 683a ldr r2, [r7, #0] + 8003746: 429a cmp r2, r3 + 8003748: d1ef bne.n 800372a + } + } + } + + /*-------------------------- HCLK1 Configuration ---------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) + 800374a: 687b ldr r3, [r7, #4] + 800374c: 681b ldr r3, [r3, #0] + 800374e: f003 0302 and.w r3, r3, #2 + 8003752: 2b00 cmp r3, #0 + 8003754: d016 beq.n 8003784 + { + assert_param(IS_RCC_HCLKx(RCC_ClkInitStruct->AHBCLKDivider)); + LL_RCC_SetAHBPrescaler(RCC_ClkInitStruct->AHBCLKDivider); + 8003756: 687b ldr r3, [r7, #4] + 8003758: 689b ldr r3, [r3, #8] + 800375a: 4618 mov r0, r3 + 800375c: f7ff fb02 bl 8002d64 + + /* HCLK1 prescaler flag when value applied */ + tickstart = HAL_GetTick(); + 8003760: f7fd fa72 bl 8000c48 + 8003764: 60f8 str r0, [r7, #12] + while (LL_RCC_IsActiveFlag_HPRE() == 0U) + 8003766: e008 b.n 800377a + { + if ((HAL_GetTick() - tickstart) > PRESCALER_TIMEOUT_VALUE) + 8003768: f7fd fa6e bl 8000c48 + 800376c: 4602 mov r2, r0 + 800376e: 68fb ldr r3, [r7, #12] + 8003770: 1ad3 subs r3, r2, r3 + 8003772: 2b02 cmp r3, #2 + 8003774: d901 bls.n 800377a + { + return HAL_TIMEOUT; + 8003776: 2303 movs r3, #3 + 8003778: e0f1 b.n 800395e + while (LL_RCC_IsActiveFlag_HPRE() == 0U) + 800377a: f7ff fbdf bl 8002f3c + 800377e: 4603 mov r3, r0 + 8003780: 2b00 cmp r3, #0 + 8003782: d0f1 beq.n 8003768 + } + } + +#if defined(DUAL_CORE) + /*-------------------------- HCLK2 Configuration ---------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK2) == RCC_CLOCKTYPE_HCLK2) + 8003784: 687b ldr r3, [r7, #4] + 8003786: 681b ldr r3, [r3, #0] + 8003788: f003 0320 and.w r3, r3, #32 + 800378c: 2b00 cmp r3, #0 + 800378e: d016 beq.n 80037be + { + assert_param(IS_RCC_HCLKx(RCC_ClkInitStruct->AHBCLK2Divider)); + LL_C2_RCC_SetAHBPrescaler(RCC_ClkInitStruct->AHBCLK2Divider); + 8003790: 687b ldr r3, [r7, #4] + 8003792: 695b ldr r3, [r3, #20] + 8003794: 4618 mov r0, r3 + 8003796: f7ff faf8 bl 8002d8a + + /* HCLK2 prescaler flag when value applied */ + tickstart = HAL_GetTick(); + 800379a: f7fd fa55 bl 8000c48 + 800379e: 60f8 str r0, [r7, #12] + while (LL_RCC_IsActiveFlag_C2HPRE() == 0U) + 80037a0: e008 b.n 80037b4 + { + if ((HAL_GetTick() - tickstart) > PRESCALER_TIMEOUT_VALUE) + 80037a2: f7fd fa51 bl 8000c48 + 80037a6: 4602 mov r2, r0 + 80037a8: 68fb ldr r3, [r7, #12] + 80037aa: 1ad3 subs r3, r2, r3 + 80037ac: 2b02 cmp r3, #2 + 80037ae: d901 bls.n 80037b4 + { + return HAL_TIMEOUT; + 80037b0: 2303 movs r3, #3 + 80037b2: e0d4 b.n 800395e + while (LL_RCC_IsActiveFlag_C2HPRE() == 0U) + 80037b4: f7ff fbd3 bl 8002f5e + 80037b8: 4603 mov r3, r0 + 80037ba: 2b00 cmp r3, #0 + 80037bc: d0f1 beq.n 80037a2 + } + } +#endif /* DUAL_CORE */ + + /*-------------------------- HCLK3 Configuration ---------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK3) == RCC_CLOCKTYPE_HCLK3) + 80037be: 687b ldr r3, [r7, #4] + 80037c0: 681b ldr r3, [r3, #0] + 80037c2: f003 0340 and.w r3, r3, #64 @ 0x40 + 80037c6: 2b00 cmp r3, #0 + 80037c8: d016 beq.n 80037f8 + { + assert_param(IS_RCC_HCLKx(RCC_ClkInitStruct->AHBCLK3Divider)); + LL_RCC_SetAHB3Prescaler(RCC_ClkInitStruct->AHBCLK3Divider); + 80037ca: 687b ldr r3, [r7, #4] + 80037cc: 699b ldr r3, [r3, #24] + 80037ce: 4618 mov r0, r3 + 80037d0: f7ff faf0 bl 8002db4 + + /* AHB shared prescaler flag when value applied */ + tickstart = HAL_GetTick(); + 80037d4: f7fd fa38 bl 8000c48 + 80037d8: 60f8 str r0, [r7, #12] + while (LL_RCC_IsActiveFlag_SHDHPRE() == 0U) + 80037da: e008 b.n 80037ee + { + if ((HAL_GetTick() - tickstart) > PRESCALER_TIMEOUT_VALUE) + 80037dc: f7fd fa34 bl 8000c48 + 80037e0: 4602 mov r2, r0 + 80037e2: 68fb ldr r3, [r7, #12] + 80037e4: 1ad3 subs r3, r2, r3 + 80037e6: 2b02 cmp r3, #2 + 80037e8: d901 bls.n 80037ee + { + return HAL_TIMEOUT; + 80037ea: 2303 movs r3, #3 + 80037ec: e0b7 b.n 800395e + while (LL_RCC_IsActiveFlag_SHDHPRE() == 0U) + 80037ee: f7ff fbc8 bl 8002f82 + 80037f2: 4603 mov r3, r0 + 80037f4: 2b00 cmp r3, #0 + 80037f6: d0f1 beq.n 80037dc + } + } + } + + /*-------------------------- PCLK1 Configuration ---------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) + 80037f8: 687b ldr r3, [r7, #4] + 80037fa: 681b ldr r3, [r3, #0] + 80037fc: f003 0304 and.w r3, r3, #4 + 8003800: 2b00 cmp r3, #0 + 8003802: d016 beq.n 8003832 + { + assert_param(IS_RCC_PCLKx(RCC_ClkInitStruct->APB1CLKDivider)); + LL_RCC_SetAPB1Prescaler(RCC_ClkInitStruct->APB1CLKDivider); + 8003804: 687b ldr r3, [r7, #4] + 8003806: 68db ldr r3, [r3, #12] + 8003808: 4618 mov r0, r3 + 800380a: f7ff fae9 bl 8002de0 + + /* APB1 prescaler flag when value applied */ + tickstart = HAL_GetTick(); + 800380e: f7fd fa1b bl 8000c48 + 8003812: 60f8 str r0, [r7, #12] + while (LL_RCC_IsActiveFlag_PPRE1() == 0U) + 8003814: e008 b.n 8003828 + { + if ((HAL_GetTick() - tickstart) > PRESCALER_TIMEOUT_VALUE) + 8003816: f7fd fa17 bl 8000c48 + 800381a: 4602 mov r2, r0 + 800381c: 68fb ldr r3, [r7, #12] + 800381e: 1ad3 subs r3, r2, r3 + 8003820: 2b02 cmp r3, #2 + 8003822: d901 bls.n 8003828 + { + return HAL_TIMEOUT; + 8003824: 2303 movs r3, #3 + 8003826: e09a b.n 800395e + while (LL_RCC_IsActiveFlag_PPRE1() == 0U) + 8003828: f7ff fbbd bl 8002fa6 + 800382c: 4603 mov r3, r0 + 800382e: 2b00 cmp r3, #0 + 8003830: d0f1 beq.n 8003816 + } + } + } + + /*-------------------------- PCLK2 Configuration ---------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) + 8003832: 687b ldr r3, [r7, #4] + 8003834: 681b ldr r3, [r3, #0] + 8003836: f003 0308 and.w r3, r3, #8 + 800383a: 2b00 cmp r3, #0 + 800383c: d017 beq.n 800386e + { + assert_param(IS_RCC_PCLKx(RCC_ClkInitStruct->APB2CLKDivider)); + LL_RCC_SetAPB2Prescaler((RCC_ClkInitStruct->APB2CLKDivider) << 3U); + 800383e: 687b ldr r3, [r7, #4] + 8003840: 691b ldr r3, [r3, #16] + 8003842: 00db lsls r3, r3, #3 + 8003844: 4618 mov r0, r3 + 8003846: f7ff fade bl 8002e06 + + /* APB2 prescaler flag when value applied */ + tickstart = HAL_GetTick(); + 800384a: f7fd f9fd bl 8000c48 + 800384e: 60f8 str r0, [r7, #12] + while (LL_RCC_IsActiveFlag_PPRE2() == 0U) + 8003850: e008 b.n 8003864 + { + if ((HAL_GetTick() - tickstart) > PRESCALER_TIMEOUT_VALUE) + 8003852: f7fd f9f9 bl 8000c48 + 8003856: 4602 mov r2, r0 + 8003858: 68fb ldr r3, [r7, #12] + 800385a: 1ad3 subs r3, r2, r3 + 800385c: 2b02 cmp r3, #2 + 800385e: d901 bls.n 8003864 + { + return HAL_TIMEOUT; + 8003860: 2303 movs r3, #3 + 8003862: e07c b.n 800395e + while (LL_RCC_IsActiveFlag_PPRE2() == 0U) + 8003864: f7ff fbb0 bl 8002fc8 + 8003868: 4603 mov r3, r0 + 800386a: 2b00 cmp r3, #0 + 800386c: d0f1 beq.n 8003852 + } + } + } + + /*------------------------- SYSCLK Configuration ---------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) + 800386e: 687b ldr r3, [r7, #4] + 8003870: 681b ldr r3, [r3, #0] + 8003872: f003 0301 and.w r3, r3, #1 + 8003876: 2b00 cmp r3, #0 + 8003878: d043 beq.n 8003902 + { + assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); + + /* HSE is selected as System Clock Source */ + if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) + 800387a: 687b ldr r3, [r7, #4] + 800387c: 685b ldr r3, [r3, #4] + 800387e: 2b02 cmp r3, #2 + 8003880: d106 bne.n 8003890 + { + /* Check the HSE ready flag */ + if (LL_RCC_HSE_IsReady() == 0U) + 8003882: f7ff f956 bl 8002b32 + 8003886: 4603 mov r3, r0 + 8003888: 2b00 cmp r3, #0 + 800388a: d11e bne.n 80038ca + { + return HAL_ERROR; + 800388c: 2301 movs r3, #1 + 800388e: e066 b.n 800395e + } + } + /* PLL is selected as System Clock Source */ + else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) + 8003890: 687b ldr r3, [r7, #4] + 8003892: 685b ldr r3, [r3, #4] + 8003894: 2b03 cmp r3, #3 + 8003896: d106 bne.n 80038a6 + { + /* Check the PLL ready flag */ + if (LL_RCC_PLL_IsReady() == 0U) + 8003898: f7ff fb12 bl 8002ec0 + 800389c: 4603 mov r3, r0 + 800389e: 2b00 cmp r3, #0 + 80038a0: d113 bne.n 80038ca + { + return HAL_ERROR; + 80038a2: 2301 movs r3, #1 + 80038a4: e05b b.n 800395e + } + } + /* MSI is selected as System Clock Source */ + else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_MSI) + 80038a6: 687b ldr r3, [r7, #4] + 80038a8: 685b ldr r3, [r3, #4] + 80038aa: 2b00 cmp r3, #0 + 80038ac: d106 bne.n 80038bc + { + /* Check the MSI ready flag */ + if (LL_RCC_MSI_IsReady() == 0U) + 80038ae: f7ff f9f0 bl 8002c92 + 80038b2: 4603 mov r3, r0 + 80038b4: 2b00 cmp r3, #0 + 80038b6: d108 bne.n 80038ca + { + return HAL_ERROR; + 80038b8: 2301 movs r3, #1 + 80038ba: e050 b.n 800395e + } + /* HSI is selected as System Clock Source */ + else + { + /* Check the HSI ready flag */ + if (LL_RCC_HSI_IsReady() == 0U) + 80038bc: f7ff f966 bl 8002b8c + 80038c0: 4603 mov r3, r0 + 80038c2: 2b00 cmp r3, #0 + 80038c4: d101 bne.n 80038ca + { + return HAL_ERROR; + 80038c6: 2301 movs r3, #1 + 80038c8: e049 b.n 800395e + } + + } + + /* apply system clock switch */ + LL_RCC_SetSysClkSource(RCC_ClkInitStruct->SYSCLKSource); + 80038ca: 687b ldr r3, [r7, #4] + 80038cc: 685b ldr r3, [r3, #4] + 80038ce: 4618 mov r0, r3 + 80038d0: f7ff fa2a bl 8002d28 + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 80038d4: f7fd f9b8 bl 8000c48 + 80038d8: 60f8 str r0, [r7, #12] + + /* check system clock source switch status */ + while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) + 80038da: e00a b.n 80038f2 + { + if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) + 80038dc: f7fd f9b4 bl 8000c48 + 80038e0: 4602 mov r2, r0 + 80038e2: 68fb ldr r3, [r7, #12] + 80038e4: 1ad3 subs r3, r2, r3 + 80038e6: f241 3288 movw r2, #5000 @ 0x1388 + 80038ea: 4293 cmp r3, r2 + 80038ec: d901 bls.n 80038f2 + { + return HAL_TIMEOUT; + 80038ee: 2303 movs r3, #3 + 80038f0: e035 b.n 800395e + while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) + 80038f2: f7ff fa2c bl 8002d4e + 80038f6: 4602 mov r2, r0 + 80038f8: 687b ldr r3, [r7, #4] + 80038fa: 685b ldr r3, [r3, #4] + 80038fc: 009b lsls r3, r3, #2 + 80038fe: 429a cmp r2, r3 + 8003900: d1ec bne.n 80038dc + } + } + } + + /* Decreasing the number of wait states because of lower CPU frequency */ + if (FLatency < __HAL_FLASH_GET_LATENCY()) + 8003902: 4b19 ldr r3, [pc, #100] @ (8003968 ) + 8003904: 681b ldr r3, [r3, #0] + 8003906: f003 0307 and.w r3, r3, #7 + 800390a: 683a ldr r2, [r7, #0] + 800390c: 429a cmp r2, r3 + 800390e: d21b bcs.n 8003948 + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLatency); + 8003910: 4b15 ldr r3, [pc, #84] @ (8003968 ) + 8003912: 681b ldr r3, [r3, #0] + 8003914: f023 0207 bic.w r2, r3, #7 + 8003918: 4913 ldr r1, [pc, #76] @ (8003968 ) + 800391a: 683b ldr r3, [r7, #0] + 800391c: 4313 orrs r3, r2 + 800391e: 600b str r3, [r1, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8003920: f7fd f992 bl 8000c48 + 8003924: 60f8 str r0, [r7, #12] + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + while (__HAL_FLASH_GET_LATENCY() != FLatency) + 8003926: e008 b.n 800393a + { + if ((HAL_GetTick() - tickstart) > LATENCY_TIMEOUT_VALUE) + 8003928: f7fd f98e bl 8000c48 + 800392c: 4602 mov r2, r0 + 800392e: 68fb ldr r3, [r7, #12] + 8003930: 1ad3 subs r3, r2, r3 + 8003932: 2b02 cmp r3, #2 + 8003934: d901 bls.n 800393a + { + return HAL_TIMEOUT; + 8003936: 2303 movs r3, #3 + 8003938: e011 b.n 800395e + while (__HAL_FLASH_GET_LATENCY() != FLatency) + 800393a: 4b0b ldr r3, [pc, #44] @ (8003968 ) + 800393c: 681b ldr r3, [r3, #0] + 800393e: f003 0307 and.w r3, r3, #7 + 8003942: 683a ldr r2, [r7, #0] + 8003944: 429a cmp r2, r3 + 8003946: d1ef bne.n 8003928 + } + + /*--------------------------------------------------------------------------*/ + + /* Update the SystemCoreClock global variable */ + SystemCoreClock = HAL_RCC_GetHCLKFreq(); + 8003948: f000 f8b4 bl 8003ab4 + 800394c: 4603 mov r3, r0 + 800394e: 4a07 ldr r2, [pc, #28] @ (800396c ) + 8003950: 6013 str r3, [r2, #0] + + /* Configure the source of time base considering new system clocks settings */ + return HAL_InitTick(uwTickPrio); + 8003952: 4b07 ldr r3, [pc, #28] @ (8003970 ) + 8003954: 681b ldr r3, [r3, #0] + 8003956: 4618 mov r0, r3 + 8003958: f7fd f96c bl 8000c34 + 800395c: 4603 mov r3, r0 +} + 800395e: 4618 mov r0, r3 + 8003960: 3710 adds r7, #16 + 8003962: 46bd mov sp, r7 + 8003964: bd80 pop {r7, pc} + 8003966: bf00 nop + 8003968: 58004000 .word 0x58004000 + 800396c: 20000000 .word 0x20000000 + 8003970: 20000004 .word 0x20000004 + +08003974 : + * + * + * @retval SYSCLK frequency + */ +uint32_t HAL_RCC_GetSysClockFreq(void) +{ + 8003974: b590 push {r4, r7, lr} + 8003976: b087 sub sp, #28 + 8003978: af00 add r7, sp, #0 + uint32_t sysclk_source; + uint32_t pllsource; + uint32_t sysclockfreq = 0U; + 800397a: 2300 movs r3, #0 + 800397c: 617b str r3, [r7, #20] + uint32_t msifreq = 0U; + 800397e: 2300 movs r3, #0 + 8003980: 613b str r3, [r7, #16] + uint32_t pllinputfreq; + + sysclk_source = __HAL_RCC_GET_SYSCLK_SOURCE(); + 8003982: f7ff f9e4 bl 8002d4e + 8003986: 60b8 str r0, [r7, #8] + pllsource = __HAL_RCC_GET_PLL_OSCSOURCE(); + 8003988: f7ff facd bl 8002f26 + 800398c: 6078 str r0, [r7, #4] + + if ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_MSI) || + 800398e: 68bb ldr r3, [r7, #8] + 8003990: 2b00 cmp r3, #0 + 8003992: d005 beq.n 80039a0 + 8003994: 68bb ldr r3, [r7, #8] + 8003996: 2b0c cmp r3, #12 + 8003998: d139 bne.n 8003a0e + ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pllsource == RCC_PLLSOURCE_MSI))) + 800399a: 687b ldr r3, [r7, #4] + 800399c: 2b01 cmp r3, #1 + 800399e: d136 bne.n 8003a0e + { + /* MSI or PLL with MSI source used as system clock source */ + /* Retrieve MSI frequency range in Hz */ + msifreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), + 80039a0: f7ff f987 bl 8002cb2 + 80039a4: 4603 mov r3, r0 + 80039a6: 2b00 cmp r3, #0 + 80039a8: d115 bne.n 80039d6 + 80039aa: f7ff f982 bl 8002cb2 + 80039ae: 4603 mov r3, r0 + 80039b0: 2b01 cmp r3, #1 + 80039b2: d106 bne.n 80039c2 + 80039b4: f7ff f98d bl 8002cd2 + 80039b8: 4603 mov r3, r0 + 80039ba: 0a1b lsrs r3, r3, #8 + 80039bc: f003 030f and.w r3, r3, #15 + 80039c0: e005 b.n 80039ce + 80039c2: f7ff f991 bl 8002ce8 + 80039c6: 4603 mov r3, r0 + 80039c8: 0a1b lsrs r3, r3, #8 + 80039ca: f003 030f and.w r3, r3, #15 + 80039ce: 4a36 ldr r2, [pc, #216] @ (8003aa8 ) + 80039d0: f852 3023 ldr.w r3, [r2, r3, lsl #2] + 80039d4: e014 b.n 8003a00 + 80039d6: f7ff f96c bl 8002cb2 + 80039da: 4603 mov r3, r0 + 80039dc: 2b01 cmp r3, #1 + 80039de: d106 bne.n 80039ee + 80039e0: f7ff f977 bl 8002cd2 + 80039e4: 4603 mov r3, r0 + 80039e6: 091b lsrs r3, r3, #4 + 80039e8: f003 030f and.w r3, r3, #15 + 80039ec: e005 b.n 80039fa + 80039ee: f7ff f97b bl 8002ce8 + 80039f2: 4603 mov r3, r0 + 80039f4: 091b lsrs r3, r3, #4 + 80039f6: f003 030f and.w r3, r3, #15 + 80039fa: 4a2b ldr r2, [pc, #172] @ (8003aa8 ) + 80039fc: f852 3023 ldr.w r3, [r2, r3, lsl #2] + 8003a00: 613b str r3, [r7, #16] + ((LL_RCC_MSI_IsEnabledRangeSelect() == 1U) ? + LL_RCC_MSI_GetRange() : + LL_RCC_MSI_GetRangeAfterStandby())); + + /* Get SYSCLK source */ + if (sysclk_source == RCC_SYSCLKSOURCE_STATUS_MSI) + 8003a02: 68bb ldr r3, [r7, #8] + 8003a04: 2b00 cmp r3, #0 + 8003a06: d115 bne.n 8003a34 + { + /* MSI used as system clock source */ + sysclockfreq = msifreq; + 8003a08: 693b ldr r3, [r7, #16] + 8003a0a: 617b str r3, [r7, #20] + if (sysclk_source == RCC_SYSCLKSOURCE_STATUS_MSI) + 8003a0c: e012 b.n 8003a34 + } + } + else if (sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSI) + 8003a0e: 68bb ldr r3, [r7, #8] + 8003a10: 2b04 cmp r3, #4 + 8003a12: d102 bne.n 8003a1a + { + /* HSI used as system clock source */ + sysclockfreq = HSI_VALUE; + 8003a14: 4b25 ldr r3, [pc, #148] @ (8003aac ) + 8003a16: 617b str r3, [r7, #20] + 8003a18: e00c b.n 8003a34 + } + else if (sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSE) + 8003a1a: 68bb ldr r3, [r7, #8] + 8003a1c: 2b08 cmp r3, #8 + 8003a1e: d109 bne.n 8003a34 + { + /* HSE used as system clock source */ + if (LL_RCC_HSE_IsEnabledDiv2() == 1U) + 8003a20: f7ff f85a bl 8002ad8 + 8003a24: 4603 mov r3, r0 + 8003a26: 2b01 cmp r3, #1 + 8003a28: d102 bne.n 8003a30 + { + sysclockfreq = HSE_VALUE / 2U; + 8003a2a: 4b20 ldr r3, [pc, #128] @ (8003aac ) + 8003a2c: 617b str r3, [r7, #20] + 8003a2e: e001 b.n 8003a34 + } + else + { + sysclockfreq = HSE_VALUE; + 8003a30: 4b1f ldr r3, [pc, #124] @ (8003ab0 ) + 8003a32: 617b str r3, [r7, #20] + else + { + /* Nothing to do */ + } + + if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) + 8003a34: f7ff f98b bl 8002d4e + 8003a38: 4603 mov r3, r0 + 8003a3a: 2b0c cmp r3, #12 + 8003a3c: d12f bne.n 8003a9e + { + /* PLL used as system clock source */ + pllsource = LL_RCC_PLL_GetMainSource(); + 8003a3e: f7ff fa72 bl 8002f26 + 8003a42: 6078 str r0, [r7, #4] + + switch (pllsource) + 8003a44: 687b ldr r3, [r7, #4] + 8003a46: 2b02 cmp r3, #2 + 8003a48: d003 beq.n 8003a52 + 8003a4a: 687b ldr r3, [r7, #4] + 8003a4c: 2b03 cmp r3, #3 + 8003a4e: d003 beq.n 8003a58 + 8003a50: e00d b.n 8003a6e + { + case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ + pllinputfreq = HSI_VALUE; + 8003a52: 4b16 ldr r3, [pc, #88] @ (8003aac ) + 8003a54: 60fb str r3, [r7, #12] + break; + 8003a56: e00d b.n 8003a74 + case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ + if (LL_RCC_HSE_IsEnabledDiv2() == 1U) + 8003a58: f7ff f83e bl 8002ad8 + 8003a5c: 4603 mov r3, r0 + 8003a5e: 2b01 cmp r3, #1 + 8003a60: d102 bne.n 8003a68 + { + pllinputfreq = HSE_VALUE / 2U; + 8003a62: 4b12 ldr r3, [pc, #72] @ (8003aac ) + 8003a64: 60fb str r3, [r7, #12] + } + else + { + pllinputfreq = HSE_VALUE; + } + break; + 8003a66: e005 b.n 8003a74 + pllinputfreq = HSE_VALUE; + 8003a68: 4b11 ldr r3, [pc, #68] @ (8003ab0 ) + 8003a6a: 60fb str r3, [r7, #12] + break; + 8003a6c: e002 b.n 8003a74 + case RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */ + default: + pllinputfreq = msifreq; + 8003a6e: 693b ldr r3, [r7, #16] + 8003a70: 60fb str r3, [r7, #12] + break; + 8003a72: bf00 nop + } + sysclockfreq = __LL_RCC_CALC_PLLCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(), + 8003a74: f7ff fa35 bl 8002ee2 + 8003a78: 4602 mov r2, r0 + 8003a7a: 68fb ldr r3, [r7, #12] + 8003a7c: fb03 f402 mul.w r4, r3, r2 + 8003a80: f7ff fa46 bl 8002f10 + 8003a84: 4603 mov r3, r0 + 8003a86: 091b lsrs r3, r3, #4 + 8003a88: 3301 adds r3, #1 + 8003a8a: fbb4 f4f3 udiv r4, r4, r3 + 8003a8e: f7ff fa34 bl 8002efa + 8003a92: 4603 mov r3, r0 + 8003a94: 0f5b lsrs r3, r3, #29 + 8003a96: 3301 adds r3, #1 + 8003a98: fbb4 f3f3 udiv r3, r4, r3 + 8003a9c: 617b str r3, [r7, #20] + LL_RCC_PLL_GetN(), LL_RCC_PLL_GetR()); + } + + return sysclockfreq; + 8003a9e: 697b ldr r3, [r7, #20] +} + 8003aa0: 4618 mov r0, r3 + 8003aa2: 371c adds r7, #28 + 8003aa4: 46bd mov sp, r7 + 8003aa6: bd90 pop {r4, r7, pc} + 8003aa8: 0800fac4 .word 0x0800fac4 + 8003aac: 00f42400 .word 0x00f42400 + 8003ab0: 01e84800 .word 0x01e84800 + +08003ab4 : +/** + * @brief Return the HCLK frequency. + * @retval HCLK frequency in Hz + */ +uint32_t HAL_RCC_GetHCLKFreq(void) +{ + 8003ab4: b598 push {r3, r4, r7, lr} + 8003ab6: af00 add r7, sp, #0 + /* Get SysClock and Compute HCLK1 frequency --------------------------------*/ + return ((uint32_t)(__LL_RCC_CALC_HCLK1_FREQ(HAL_RCC_GetSysClockFreq(), LL_RCC_GetAHBPrescaler()))); + 8003ab8: f7ff ff5c bl 8003974 + 8003abc: 4604 mov r4, r0 + 8003abe: f7ff f9b5 bl 8002e2c + 8003ac2: 4603 mov r3, r0 + 8003ac4: 091b lsrs r3, r3, #4 + 8003ac6: f003 030f and.w r3, r3, #15 + 8003aca: 4a03 ldr r2, [pc, #12] @ (8003ad8 ) + 8003acc: f852 3023 ldr.w r3, [r2, r3, lsl #2] + 8003ad0: fbb4 f3f3 udiv r3, r4, r3 +} + 8003ad4: 4618 mov r0, r3 + 8003ad6: bd98 pop {r3, r4, r7, pc} + 8003ad8: 0800fa64 .word 0x0800fa64 + +08003adc : +/** + * @brief Return the PCLK1 frequency. + * @retval PCLK1 frequency in Hz + */ +uint32_t HAL_RCC_GetPCLK1Freq(void) +{ + 8003adc: b598 push {r3, r4, r7, lr} + 8003ade: af00 add r7, sp, #0 + /* Get HCLK source and Compute PCLK1 frequency -----------------------------*/ + return ((uint32_t)(__LL_RCC_CALC_PCLK1_FREQ(HAL_RCC_GetHCLKFreq(), LL_RCC_GetAPB1Prescaler()))); + 8003ae0: f7ff ffe8 bl 8003ab4 + 8003ae4: 4604 mov r4, r0 + 8003ae6: f7ff f9b9 bl 8002e5c + 8003aea: 4603 mov r3, r0 + 8003aec: 0a1b lsrs r3, r3, #8 + 8003aee: 4a03 ldr r2, [pc, #12] @ (8003afc ) + 8003af0: f852 3023 ldr.w r3, [r2, r3, lsl #2] + 8003af4: fa24 f303 lsr.w r3, r4, r3 +} + 8003af8: 4618 mov r0, r3 + 8003afa: bd98 pop {r3, r4, r7, pc} + 8003afc: 0800faa4 .word 0x0800faa4 + +08003b00 : +/** + * @brief Return the PCLK2 frequency. + * @retval PCLK2 frequency in Hz + */ +uint32_t HAL_RCC_GetPCLK2Freq(void) +{ + 8003b00: b598 push {r3, r4, r7, lr} + 8003b02: af00 add r7, sp, #0 + /* Get HCLK source and Compute PCLK2 frequency -----------------------------*/ + return ((uint32_t)(__LL_RCC_CALC_PCLK2_FREQ(HAL_RCC_GetHCLKFreq(), LL_RCC_GetAPB2Prescaler()))); + 8003b04: f7ff ffd6 bl 8003ab4 + 8003b08: 4604 mov r4, r0 + 8003b0a: f7ff f9b2 bl 8002e72 + 8003b0e: 4603 mov r3, r0 + 8003b10: 0adb lsrs r3, r3, #11 + 8003b12: 4a03 ldr r2, [pc, #12] @ (8003b20 ) + 8003b14: f852 3023 ldr.w r3, [r2, r3, lsl #2] + 8003b18: fa24 f303 lsr.w r3, r4, r3 +} + 8003b1c: 4618 mov r0, r3 + 8003b1e: bd98 pop {r3, r4, r7, pc} + 8003b20: 0800faa4 .word 0x0800faa4 + +08003b24 : + voltage range. + * @param MSI_Range MSI range value from @ref RCC_MSIRANGE_0 to @ref RCC_MSIRANGE_11 + * @retval HAL status + */ +static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t MSI_Range) +{ + 8003b24: b590 push {r4, r7, lr} + 8003b26: b085 sub sp, #20 + 8003b28: af00 add r7, sp, #0 + 8003b2a: 6078 str r0, [r7, #4] + uint32_t flash_clksrcfreq; + uint32_t msifreq; + + /* MSI frequency range in Hz */ + msifreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSIRANGESEL_RUN, MSI_Range); + 8003b2c: 687b ldr r3, [r7, #4] + 8003b2e: 091b lsrs r3, r3, #4 + 8003b30: f003 030f and.w r3, r3, #15 + 8003b34: 4a10 ldr r2, [pc, #64] @ (8003b78 ) + 8003b36: f852 3023 ldr.w r3, [r2, r3, lsl #2] + 8003b3a: 60fb str r3, [r7, #12] + flash_clksrcfreq = __LL_RCC_CALC_HCLK3_FREQ(msifreq, LL_RCC_GetAHB3Prescaler()); + 8003b3c: f7ff f981 bl 8002e42 + 8003b40: 4603 mov r3, r0 + 8003b42: 091b lsrs r3, r3, #4 + 8003b44: f003 030f and.w r3, r3, #15 + 8003b48: 4a0c ldr r2, [pc, #48] @ (8003b7c ) + 8003b4a: f852 3023 ldr.w r3, [r2, r3, lsl #2] + 8003b4e: 68fa ldr r2, [r7, #12] + 8003b50: fbb2 f3f3 udiv r3, r2, r3 + 8003b54: 60bb str r3, [r7, #8] + + return RCC_SetFlashLatency((flash_clksrcfreq / MEGA_HZ), HAL_PWREx_GetVoltageRange()); + 8003b56: 68bb ldr r3, [r7, #8] + 8003b58: 4a09 ldr r2, [pc, #36] @ (8003b80 ) + 8003b5a: fba2 2303 umull r2, r3, r2, r3 + 8003b5e: 0c9c lsrs r4, r3, #18 + 8003b60: f7fe ff12 bl 8002988 + 8003b64: 4603 mov r3, r0 + 8003b66: 4619 mov r1, r3 + 8003b68: 4620 mov r0, r4 + 8003b6a: f000 f80b bl 8003b84 + 8003b6e: 4603 mov r3, r0 +} + 8003b70: 4618 mov r0, r3 + 8003b72: 3714 adds r7, #20 + 8003b74: 46bd mov sp, r7 + 8003b76: bd90 pop {r4, r7, pc} + 8003b78: 0800fac4 .word 0x0800fac4 + 8003b7c: 0800fa64 .word 0x0800fa64 + 8003b80: 431bde83 .word 0x431bde83 + +08003b84 : + * @arg PWR_REGULATOR_VOLTAGE_SCALE1 Regulator voltage output range 1 mode + * @arg PWR_REGULATOR_VOLTAGE_SCALE2 Regulator voltage output range 2 mode + * @retval HAL status + */ +static HAL_StatusTypeDef RCC_SetFlashLatency(uint32_t Flash_ClkSrcFreq, uint32_t VCORE_Voltage) +{ + 8003b84: b580 push {r7, lr} + 8003b86: b08e sub sp, #56 @ 0x38 + 8003b88: af00 add r7, sp, #0 + 8003b8a: 6078 str r0, [r7, #4] + 8003b8c: 6039 str r1, [r7, #0] + /* Flash Clock source (HCLK3) range in MHz for VCORE range1 */ + const uint16_t FLASH_CLK_SRC_RANGE_VOS1[] = {18, 36, 48}; + 8003b8e: 4a3a ldr r2, [pc, #232] @ (8003c78 ) + 8003b90: f107 0320 add.w r3, r7, #32 + 8003b94: e892 0003 ldmia.w r2, {r0, r1} + 8003b98: 6018 str r0, [r3, #0] + 8003b9a: 3304 adds r3, #4 + 8003b9c: 8019 strh r1, [r3, #0] + + /* Flash Clock source (HCLK3) range in MHz for VCORE range2 */ + const uint16_t FLASH_CLK_SRC_RANGE_VOS2[] = {6, 12, 16}; + 8003b9e: 4a37 ldr r2, [pc, #220] @ (8003c7c ) + 8003ba0: f107 0318 add.w r3, r7, #24 + 8003ba4: e892 0003 ldmia.w r2, {r0, r1} + 8003ba8: 6018 str r0, [r3, #0] + 8003baa: 3304 adds r3, #4 + 8003bac: 8019 strh r1, [r3, #0] + + /* Flash Latency range */ + const uint32_t FLASH_LATENCY_RANGE[] = {FLASH_LATENCY_0, FLASH_LATENCY_1, FLASH_LATENCY_2}; + 8003bae: 4a34 ldr r2, [pc, #208] @ (8003c80 ) + 8003bb0: f107 030c add.w r3, r7, #12 + 8003bb4: ca07 ldmia r2, {r0, r1, r2} + 8003bb6: e883 0007 stmia.w r3, {r0, r1, r2} + + uint32_t latency = FLASH_LATENCY_0; /* default value 0WS */ + 8003bba: 2300 movs r3, #0 + 8003bbc: 637b str r3, [r7, #52] @ 0x34 + uint32_t tickstart; + + if (VCORE_Voltage == PWR_REGULATOR_VOLTAGE_SCALE1) + 8003bbe: 683b ldr r3, [r7, #0] + 8003bc0: f5b3 7f00 cmp.w r3, #512 @ 0x200 + 8003bc4: d11b bne.n 8003bfe + { + for (uint32_t index = 0; index < __COUNTOF(FLASH_CLK_SRC_RANGE_VOS1); index++) + 8003bc6: 2300 movs r3, #0 + 8003bc8: 633b str r3, [r7, #48] @ 0x30 + 8003bca: e014 b.n 8003bf6 + { + if (Flash_ClkSrcFreq <= FLASH_CLK_SRC_RANGE_VOS1[index]) + 8003bcc: 6b3b ldr r3, [r7, #48] @ 0x30 + 8003bce: 005b lsls r3, r3, #1 + 8003bd0: 3338 adds r3, #56 @ 0x38 + 8003bd2: 443b add r3, r7 + 8003bd4: f833 3c18 ldrh.w r3, [r3, #-24] + 8003bd8: 461a mov r2, r3 + 8003bda: 687b ldr r3, [r7, #4] + 8003bdc: 4293 cmp r3, r2 + 8003bde: d807 bhi.n 8003bf0 + { + latency = FLASH_LATENCY_RANGE[index]; + 8003be0: 6b3b ldr r3, [r7, #48] @ 0x30 + 8003be2: 009b lsls r3, r3, #2 + 8003be4: 3338 adds r3, #56 @ 0x38 + 8003be6: 443b add r3, r7 + 8003be8: f853 3c2c ldr.w r3, [r3, #-44] + 8003bec: 637b str r3, [r7, #52] @ 0x34 + break; + 8003bee: e021 b.n 8003c34 + for (uint32_t index = 0; index < __COUNTOF(FLASH_CLK_SRC_RANGE_VOS1); index++) + 8003bf0: 6b3b ldr r3, [r7, #48] @ 0x30 + 8003bf2: 3301 adds r3, #1 + 8003bf4: 633b str r3, [r7, #48] @ 0x30 + 8003bf6: 6b3b ldr r3, [r7, #48] @ 0x30 + 8003bf8: 2b02 cmp r3, #2 + 8003bfa: d9e7 bls.n 8003bcc + 8003bfc: e01a b.n 8003c34 + } + } + } + else /* PWR_REGULATOR_VOLTAGE_SCALE2 */ + { + for (uint32_t index = 0; index < __COUNTOF(FLASH_CLK_SRC_RANGE_VOS2); index++) + 8003bfe: 2300 movs r3, #0 + 8003c00: 62fb str r3, [r7, #44] @ 0x2c + 8003c02: e014 b.n 8003c2e + { + if (Flash_ClkSrcFreq <= FLASH_CLK_SRC_RANGE_VOS2[index]) + 8003c04: 6afb ldr r3, [r7, #44] @ 0x2c + 8003c06: 005b lsls r3, r3, #1 + 8003c08: 3338 adds r3, #56 @ 0x38 + 8003c0a: 443b add r3, r7 + 8003c0c: f833 3c20 ldrh.w r3, [r3, #-32] + 8003c10: 461a mov r2, r3 + 8003c12: 687b ldr r3, [r7, #4] + 8003c14: 4293 cmp r3, r2 + 8003c16: d807 bhi.n 8003c28 + { + latency = FLASH_LATENCY_RANGE[index]; + 8003c18: 6afb ldr r3, [r7, #44] @ 0x2c + 8003c1a: 009b lsls r3, r3, #2 + 8003c1c: 3338 adds r3, #56 @ 0x38 + 8003c1e: 443b add r3, r7 + 8003c20: f853 3c2c ldr.w r3, [r3, #-44] + 8003c24: 637b str r3, [r7, #52] @ 0x34 + break; + 8003c26: e005 b.n 8003c34 + for (uint32_t index = 0; index < __COUNTOF(FLASH_CLK_SRC_RANGE_VOS2); index++) + 8003c28: 6afb ldr r3, [r7, #44] @ 0x2c + 8003c2a: 3301 adds r3, #1 + 8003c2c: 62fb str r3, [r7, #44] @ 0x2c + 8003c2e: 6afb ldr r3, [r7, #44] @ 0x2c + 8003c30: 2b02 cmp r3, #2 + 8003c32: d9e7 bls.n 8003c04 + } + } + } + + __HAL_FLASH_SET_LATENCY(latency); + 8003c34: 4b13 ldr r3, [pc, #76] @ (8003c84 ) + 8003c36: 681b ldr r3, [r3, #0] + 8003c38: f023 0207 bic.w r2, r3, #7 + 8003c3c: 4911 ldr r1, [pc, #68] @ (8003c84 ) + 8003c3e: 6b7b ldr r3, [r7, #52] @ 0x34 + 8003c40: 4313 orrs r3, r2 + 8003c42: 600b str r3, [r1, #0] + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8003c44: f7fd f800 bl 8000c48 + 8003c48: 62b8 str r0, [r7, #40] @ 0x28 + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + while (__HAL_FLASH_GET_LATENCY() != latency) + 8003c4a: e008 b.n 8003c5e + { + if ((HAL_GetTick() - tickstart) > LATENCY_TIMEOUT_VALUE) + 8003c4c: f7fc fffc bl 8000c48 + 8003c50: 4602 mov r2, r0 + 8003c52: 6abb ldr r3, [r7, #40] @ 0x28 + 8003c54: 1ad3 subs r3, r2, r3 + 8003c56: 2b02 cmp r3, #2 + 8003c58: d901 bls.n 8003c5e + { + return HAL_TIMEOUT; + 8003c5a: 2303 movs r3, #3 + 8003c5c: e007 b.n 8003c6e + while (__HAL_FLASH_GET_LATENCY() != latency) + 8003c5e: 4b09 ldr r3, [pc, #36] @ (8003c84 ) + 8003c60: 681b ldr r3, [r3, #0] + 8003c62: f003 0307 and.w r3, r3, #7 + 8003c66: 6b7a ldr r2, [r7, #52] @ 0x34 + 8003c68: 429a cmp r2, r3 + 8003c6a: d1ef bne.n 8003c4c + } + } + return HAL_OK; + 8003c6c: 2300 movs r3, #0 +} + 8003c6e: 4618 mov r0, r3 + 8003c70: 3738 adds r7, #56 @ 0x38 + 8003c72: 46bd mov sp, r7 + 8003c74: bd80 pop {r7, pc} + 8003c76: bf00 nop + 8003c78: 0800f0cc .word 0x0800f0cc + 8003c7c: 0800f0d4 .word 0x0800f0d4 + 8003c80: 0800f0dc .word 0x0800f0dc + 8003c84: 58004000 .word 0x58004000 + +08003c88 : +{ + 8003c88: b480 push {r7} + 8003c8a: af00 add r7, sp, #0 + return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY)) ? 1UL : 0UL); + 8003c8c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8003c90: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 8003c94: f003 0302 and.w r3, r3, #2 + 8003c98: 2b02 cmp r3, #2 + 8003c9a: d101 bne.n 8003ca0 + 8003c9c: 2301 movs r3, #1 + 8003c9e: e000 b.n 8003ca2 + 8003ca0: 2300 movs r3, #0 +} + 8003ca2: 4618 mov r0, r3 + 8003ca4: 46bd mov sp, r7 + 8003ca6: bc80 pop {r7} + 8003ca8: 4770 bx lr + +08003caa : +{ + 8003caa: b480 push {r7} + 8003cac: b083 sub sp, #12 + 8003cae: af00 add r7, sp, #0 + 8003cb0: 6078 str r0, [r7, #4] + MODIFY_REG(RCC->CCIPR, (USARTxSource >> 16), (USARTxSource & 0x0000FFFFU)); + 8003cb2: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8003cb6: f8d3 2088 ldr.w r2, [r3, #136] @ 0x88 + 8003cba: 687b ldr r3, [r7, #4] + 8003cbc: 0c1b lsrs r3, r3, #16 + 8003cbe: 43db mvns r3, r3 + 8003cc0: 401a ands r2, r3 + 8003cc2: 687b ldr r3, [r7, #4] + 8003cc4: b29b uxth r3, r3 + 8003cc6: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 8003cca: 4313 orrs r3, r2 + 8003ccc: f8c1 3088 str.w r3, [r1, #136] @ 0x88 +} + 8003cd0: bf00 nop + 8003cd2: 370c adds r7, #12 + 8003cd4: 46bd mov sp, r7 + 8003cd6: bc80 pop {r7} + 8003cd8: 4770 bx lr + +08003cda : +{ + 8003cda: b480 push {r7} + 8003cdc: b083 sub sp, #12 + 8003cde: af00 add r7, sp, #0 + 8003ce0: 6078 str r0, [r7, #4] + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2S2SEL, I2SxSource); + 8003ce2: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8003ce6: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 + 8003cea: f423 7240 bic.w r2, r3, #768 @ 0x300 + 8003cee: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 8003cf2: 687b ldr r3, [r7, #4] + 8003cf4: 4313 orrs r3, r2 + 8003cf6: f8c1 3088 str.w r3, [r1, #136] @ 0x88 +} + 8003cfa: bf00 nop + 8003cfc: 370c adds r7, #12 + 8003cfe: 46bd mov sp, r7 + 8003d00: bc80 pop {r7} + 8003d02: 4770 bx lr + +08003d04 : +{ + 8003d04: b480 push {r7} + 8003d06: b083 sub sp, #12 + 8003d08: af00 add r7, sp, #0 + 8003d0a: 6078 str r0, [r7, #4] + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, LPUARTxSource); + 8003d0c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8003d10: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 + 8003d14: f423 6240 bic.w r2, r3, #3072 @ 0xc00 + 8003d18: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 8003d1c: 687b ldr r3, [r7, #4] + 8003d1e: 4313 orrs r3, r2 + 8003d20: f8c1 3088 str.w r3, [r1, #136] @ 0x88 +} + 8003d24: bf00 nop + 8003d26: 370c adds r7, #12 + 8003d28: 46bd mov sp, r7 + 8003d2a: bc80 pop {r7} + 8003d2c: 4770 bx lr + +08003d2e : +{ + 8003d2e: b480 push {r7} + 8003d30: b083 sub sp, #12 + 8003d32: af00 add r7, sp, #0 + 8003d34: 6078 str r0, [r7, #4] + MODIFY_REG(RCC->CCIPR, ((I2CxSource >> 4) & 0x000FF000U), ((I2CxSource << 4) & 0x000FF000U)); + 8003d36: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8003d3a: f8d3 2088 ldr.w r2, [r3, #136] @ 0x88 + 8003d3e: 687b ldr r3, [r7, #4] + 8003d40: 091b lsrs r3, r3, #4 + 8003d42: f403 237f and.w r3, r3, #1044480 @ 0xff000 + 8003d46: 43db mvns r3, r3 + 8003d48: 401a ands r2, r3 + 8003d4a: 687b ldr r3, [r7, #4] + 8003d4c: 011b lsls r3, r3, #4 + 8003d4e: f403 237f and.w r3, r3, #1044480 @ 0xff000 + 8003d52: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 8003d56: 4313 orrs r3, r2 + 8003d58: f8c1 3088 str.w r3, [r1, #136] @ 0x88 +} + 8003d5c: bf00 nop + 8003d5e: 370c adds r7, #12 + 8003d60: 46bd mov sp, r7 + 8003d62: bc80 pop {r7} + 8003d64: 4770 bx lr + +08003d66 : +{ + 8003d66: b480 push {r7} + 8003d68: b083 sub sp, #12 + 8003d6a: af00 add r7, sp, #0 + 8003d6c: 6078 str r0, [r7, #4] + MODIFY_REG(RCC->CCIPR, (LPTIMxSource & 0xFFFF0000U), (LPTIMxSource << 16)); + 8003d6e: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8003d72: f8d3 2088 ldr.w r2, [r3, #136] @ 0x88 + 8003d76: 687b ldr r3, [r7, #4] + 8003d78: 0c1b lsrs r3, r3, #16 + 8003d7a: 041b lsls r3, r3, #16 + 8003d7c: 43db mvns r3, r3 + 8003d7e: 401a ands r2, r3 + 8003d80: 687b ldr r3, [r7, #4] + 8003d82: 041b lsls r3, r3, #16 + 8003d84: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 8003d88: 4313 orrs r3, r2 + 8003d8a: f8c1 3088 str.w r3, [r1, #136] @ 0x88 +} + 8003d8e: bf00 nop + 8003d90: 370c adds r7, #12 + 8003d92: 46bd mov sp, r7 + 8003d94: bc80 pop {r7} + 8003d96: 4770 bx lr + +08003d98 : +{ + 8003d98: b480 push {r7} + 8003d9a: b083 sub sp, #12 + 8003d9c: af00 add r7, sp, #0 + 8003d9e: 6078 str r0, [r7, #4] + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_RNGSEL, RNGxSource); + 8003da0: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8003da4: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 + 8003da8: f023 4240 bic.w r2, r3, #3221225472 @ 0xc0000000 + 8003dac: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 8003db0: 687b ldr r3, [r7, #4] + 8003db2: 4313 orrs r3, r2 + 8003db4: f8c1 3088 str.w r3, [r1, #136] @ 0x88 +} + 8003db8: bf00 nop + 8003dba: 370c adds r7, #12 + 8003dbc: 46bd mov sp, r7 + 8003dbe: bc80 pop {r7} + 8003dc0: 4770 bx lr + +08003dc2 : +{ + 8003dc2: b480 push {r7} + 8003dc4: b083 sub sp, #12 + 8003dc6: af00 add r7, sp, #0 + 8003dc8: 6078 str r0, [r7, #4] + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADCSEL, ADCxSource); + 8003dca: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8003dce: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 + 8003dd2: f023 5240 bic.w r2, r3, #805306368 @ 0x30000000 + 8003dd6: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 8003dda: 687b ldr r3, [r7, #4] + 8003ddc: 4313 orrs r3, r2 + 8003dde: f8c1 3088 str.w r3, [r1, #136] @ 0x88 +} + 8003de2: bf00 nop + 8003de4: 370c adds r7, #12 + 8003de6: 46bd mov sp, r7 + 8003de8: bc80 pop {r7} + 8003dea: 4770 bx lr + +08003dec : +{ + 8003dec: b480 push {r7} + 8003dee: b083 sub sp, #12 + 8003df0: af00 add r7, sp, #0 + 8003df2: 6078 str r0, [r7, #4] + MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source); + 8003df4: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8003df8: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 8003dfc: f423 7240 bic.w r2, r3, #768 @ 0x300 + 8003e00: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 8003e04: 687b ldr r3, [r7, #4] + 8003e06: 4313 orrs r3, r2 + 8003e08: f8c1 3090 str.w r3, [r1, #144] @ 0x90 +} + 8003e0c: bf00 nop + 8003e0e: 370c adds r7, #12 + 8003e10: 46bd mov sp, r7 + 8003e12: bc80 pop {r7} + 8003e14: 4770 bx lr + +08003e16 : +{ + 8003e16: b480 push {r7} + 8003e18: af00 add r7, sp, #0 + return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)); + 8003e1a: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8003e1e: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 8003e22: f403 7340 and.w r3, r3, #768 @ 0x300 +} + 8003e26: 4618 mov r0, r3 + 8003e28: 46bd mov sp, r7 + 8003e2a: bc80 pop {r7} + 8003e2c: 4770 bx lr + +08003e2e : +{ + 8003e2e: b480 push {r7} + 8003e30: af00 add r7, sp, #0 + SET_BIT(RCC->BDCR, RCC_BDCR_BDRST); + 8003e32: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8003e36: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 8003e3a: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 8003e3e: f443 3380 orr.w r3, r3, #65536 @ 0x10000 + 8003e42: f8c2 3090 str.w r3, [r2, #144] @ 0x90 +} + 8003e46: bf00 nop + 8003e48: 46bd mov sp, r7 + 8003e4a: bc80 pop {r7} + 8003e4c: 4770 bx lr + +08003e4e : +{ + 8003e4e: b480 push {r7} + 8003e50: af00 add r7, sp, #0 + CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST); + 8003e52: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8003e56: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 8003e5a: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 8003e5e: f423 3380 bic.w r3, r3, #65536 @ 0x10000 + 8003e62: f8c2 3090 str.w r3, [r2, #144] @ 0x90 +} + 8003e66: bf00 nop + 8003e68: 46bd mov sp, r7 + 8003e6a: bc80 pop {r7} + 8003e6c: 4770 bx lr + ... + +08003e70 : + * the RTC clock source: in this case the access to Backup domain is enabled. + * + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) +{ + 8003e70: b580 push {r7, lr} + 8003e72: b086 sub sp, #24 + 8003e74: af00 add r7, sp, #0 + 8003e76: 6078 str r0, [r7, #4] + uint32_t tmpregister = 0; + 8003e78: 2300 movs r3, #0 + 8003e7a: 617b str r3, [r7, #20] + uint32_t tickstart; + HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */ + 8003e7c: 2300 movs r3, #0 + 8003e7e: 74fb strb r3, [r7, #19] + HAL_StatusTypeDef status = HAL_OK; /* Final status */ + 8003e80: 2300 movs r3, #0 + 8003e82: 74bb strb r3, [r7, #18] + + /* Check the parameters */ + assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); + + /*-------------------------- RTC clock source configuration ----------------------*/ + if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) + 8003e84: 687b ldr r3, [r7, #4] + 8003e86: 681b ldr r3, [r3, #0] + 8003e88: f403 3380 and.w r3, r3, #65536 @ 0x10000 + 8003e8c: 2b00 cmp r3, #0 + 8003e8e: d058 beq.n 8003f42 + /* Check for RTC Parameters used to output RTCCLK */ + assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); + + + /* Enable write access to Backup domain */ + HAL_PWR_EnableBkUpAccess(); + 8003e90: f7fe fd38 bl 8002904 + + /* Wait for Backup domain Write protection disable */ + tickstart = HAL_GetTick(); + 8003e94: f7fc fed8 bl 8000c48 + 8003e98: 60f8 str r0, [r7, #12] + + while (!(READ_BIT(PWR->CR1, PWR_CR1_DBP) == (PWR_CR1_DBP))) + 8003e9a: e009 b.n 8003eb0 + { + if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + 8003e9c: f7fc fed4 bl 8000c48 + 8003ea0: 4602 mov r2, r0 + 8003ea2: 68fb ldr r3, [r7, #12] + 8003ea4: 1ad3 subs r3, r2, r3 + 8003ea6: 2b02 cmp r3, #2 + 8003ea8: d902 bls.n 8003eb0 + { + ret = HAL_TIMEOUT; + 8003eaa: 2303 movs r3, #3 + 8003eac: 74fb strb r3, [r7, #19] + break; + 8003eae: e006 b.n 8003ebe + while (!(READ_BIT(PWR->CR1, PWR_CR1_DBP) == (PWR_CR1_DBP))) + 8003eb0: 4b7b ldr r3, [pc, #492] @ (80040a0 ) + 8003eb2: 681b ldr r3, [r3, #0] + 8003eb4: f403 7380 and.w r3, r3, #256 @ 0x100 + 8003eb8: f5b3 7f80 cmp.w r3, #256 @ 0x100 + 8003ebc: d1ee bne.n 8003e9c + } + } + + if (ret == HAL_OK) + 8003ebe: 7cfb ldrb r3, [r7, #19] + 8003ec0: 2b00 cmp r3, #0 + 8003ec2: d13c bne.n 8003f3e + { + /* Reset the Backup domain only if the RTC Clock source selection is modified */ + if (LL_RCC_GetRTCClockSource() != PeriphClkInit->RTCClockSelection) + 8003ec4: f7ff ffa7 bl 8003e16 + 8003ec8: 4602 mov r2, r0 + 8003eca: 687b ldr r3, [r7, #4] + 8003ecc: 6b5b ldr r3, [r3, #52] @ 0x34 + 8003ece: 429a cmp r2, r3 + 8003ed0: d00f beq.n 8003ef2 + { + /* Store the content of BDCR register before the reset of Backup Domain */ + tmpregister = READ_BIT(RCC->BDCR, ~(RCC_BDCR_RTCSEL)); + 8003ed2: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8003ed6: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 8003eda: f423 7340 bic.w r3, r3, #768 @ 0x300 + 8003ede: 617b str r3, [r7, #20] + + /* RTC Clock selection can be changed only if the Backup Domain is reset */ + __HAL_RCC_BACKUPRESET_FORCE(); + 8003ee0: f7ff ffa5 bl 8003e2e + __HAL_RCC_BACKUPRESET_RELEASE(); + 8003ee4: f7ff ffb3 bl 8003e4e + + /* Restore the Content of BDCR register */ + RCC->BDCR = tmpregister; + 8003ee8: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 8003eec: 697b ldr r3, [r7, #20] + 8003eee: f8c2 3090 str.w r3, [r2, #144] @ 0x90 + } + + /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */ + if (HAL_IS_BIT_SET(tmpregister, RCC_BDCR_LSERDY)) + 8003ef2: 697b ldr r3, [r7, #20] + 8003ef4: f003 0302 and.w r3, r3, #2 + 8003ef8: 2b00 cmp r3, #0 + 8003efa: d014 beq.n 8003f26 + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8003efc: f7fc fea4 bl 8000c48 + 8003f00: 60f8 str r0, [r7, #12] + + /* Wait till LSE is ready */ + while (LL_RCC_LSE_IsReady() != 1U) + 8003f02: e00b b.n 8003f1c + { + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + 8003f04: f7fc fea0 bl 8000c48 + 8003f08: 4602 mov r2, r0 + 8003f0a: 68fb ldr r3, [r7, #12] + 8003f0c: 1ad3 subs r3, r2, r3 + 8003f0e: f241 3288 movw r2, #5000 @ 0x1388 + 8003f12: 4293 cmp r3, r2 + 8003f14: d902 bls.n 8003f1c + { + ret = HAL_TIMEOUT; + 8003f16: 2303 movs r3, #3 + 8003f18: 74fb strb r3, [r7, #19] + break; + 8003f1a: e004 b.n 8003f26 + while (LL_RCC_LSE_IsReady() != 1U) + 8003f1c: f7ff feb4 bl 8003c88 + 8003f20: 4603 mov r3, r0 + 8003f22: 2b01 cmp r3, #1 + 8003f24: d1ee bne.n 8003f04 + } + } + } + + if (ret == HAL_OK) + 8003f26: 7cfb ldrb r3, [r7, #19] + 8003f28: 2b00 cmp r3, #0 + 8003f2a: d105 bne.n 8003f38 + { + /* Apply new RTC clock source selection */ + __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); + 8003f2c: 687b ldr r3, [r7, #4] + 8003f2e: 6b5b ldr r3, [r3, #52] @ 0x34 + 8003f30: 4618 mov r0, r3 + 8003f32: f7ff ff5b bl 8003dec + 8003f36: e004 b.n 8003f42 + } + else + { + /* set overall return value */ + status = ret; + 8003f38: 7cfb ldrb r3, [r7, #19] + 8003f3a: 74bb strb r3, [r7, #18] + 8003f3c: e001 b.n 8003f42 + } + } + else + { + /* set overall return value */ + status = ret; + 8003f3e: 7cfb ldrb r3, [r7, #19] + 8003f40: 74bb strb r3, [r7, #18] + } + + } + + /*-------------------- USART1 clock source configuration -------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) + 8003f42: 687b ldr r3, [r7, #4] + 8003f44: 681b ldr r3, [r3, #0] + 8003f46: f003 0301 and.w r3, r3, #1 + 8003f4a: 2b00 cmp r3, #0 + 8003f4c: d004 beq.n 8003f58 + { + /* Check the parameters */ + assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection)); + + /* Configure the USART1 clock source */ + __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection); + 8003f4e: 687b ldr r3, [r7, #4] + 8003f50: 685b ldr r3, [r3, #4] + 8003f52: 4618 mov r0, r3 + 8003f54: f7ff fea9 bl 8003caa + } + + /*-------------------- USART2 clock source configuration -------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) + 8003f58: 687b ldr r3, [r7, #4] + 8003f5a: 681b ldr r3, [r3, #0] + 8003f5c: f003 0302 and.w r3, r3, #2 + 8003f60: 2b00 cmp r3, #0 + 8003f62: d004 beq.n 8003f6e + { + /* Check the parameters */ + assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection)); + + /* Configure the USART2 clock source */ + __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection); + 8003f64: 687b ldr r3, [r7, #4] + 8003f66: 689b ldr r3, [r3, #8] + 8003f68: 4618 mov r0, r3 + 8003f6a: f7ff fe9e bl 8003caa + } + + /*-------------------- LPUART1 clock source configuration ------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) + 8003f6e: 687b ldr r3, [r7, #4] + 8003f70: 681b ldr r3, [r3, #0] + 8003f72: f003 0320 and.w r3, r3, #32 + 8003f76: 2b00 cmp r3, #0 + 8003f78: d004 beq.n 8003f84 + { + /* Check the parameters */ + assert_param(IS_RCC_LPUART1CLKSOURCE(PeriphClkInit->Lpuart1ClockSelection)); + + /* Configure the LPUAR1 clock source */ + __HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection); + 8003f7a: 687b ldr r3, [r7, #4] + 8003f7c: 691b ldr r3, [r3, #16] + 8003f7e: 4618 mov r0, r3 + 8003f80: f7ff fec0 bl 8003d04 + } + + /*-------------------- LPTIM1 clock source configuration -------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == (RCC_PERIPHCLK_LPTIM1)) + 8003f84: 687b ldr r3, [r7, #4] + 8003f86: 681b ldr r3, [r3, #0] + 8003f88: f403 7300 and.w r3, r3, #512 @ 0x200 + 8003f8c: 2b00 cmp r3, #0 + 8003f8e: d004 beq.n 8003f9a + { + /* Check the parameters */ + assert_param(IS_RCC_LPTIM1CLKSOURCE(PeriphClkInit->Lptim1ClockSelection)); + + /* Configure the LPTIM1 clock source */ + __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection); + 8003f90: 687b ldr r3, [r7, #4] + 8003f92: 6a1b ldr r3, [r3, #32] + 8003f94: 4618 mov r0, r3 + 8003f96: f7ff fee6 bl 8003d66 + } + + /*-------------------- LPTIM2 clock source configuration -------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM2) == (RCC_PERIPHCLK_LPTIM2)) + 8003f9a: 687b ldr r3, [r7, #4] + 8003f9c: 681b ldr r3, [r3, #0] + 8003f9e: f403 6380 and.w r3, r3, #1024 @ 0x400 + 8003fa2: 2b00 cmp r3, #0 + 8003fa4: d004 beq.n 8003fb0 + { + /* Check the parameters */ + assert_param(IS_RCC_LPTIM2CLKSOURCE(PeriphClkInit->Lptim2ClockSelection)); + + /* Configure the LPTIM2 clock source */ + __HAL_RCC_LPTIM2_CONFIG(PeriphClkInit->Lptim2ClockSelection); + 8003fa6: 687b ldr r3, [r7, #4] + 8003fa8: 6a5b ldr r3, [r3, #36] @ 0x24 + 8003faa: 4618 mov r0, r3 + 8003fac: f7ff fedb bl 8003d66 + } + + /*-------------------- LPTIM3 clock source configuration -------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM3) == (RCC_PERIPHCLK_LPTIM3)) + 8003fb0: 687b ldr r3, [r7, #4] + 8003fb2: 681b ldr r3, [r3, #0] + 8003fb4: f403 6300 and.w r3, r3, #2048 @ 0x800 + 8003fb8: 2b00 cmp r3, #0 + 8003fba: d004 beq.n 8003fc6 + { + /* Check the parameters */ + assert_param(IS_RCC_LPTIM3CLKSOURCE(PeriphClkInit->Lptim3ClockSelection)); + + /* Configure the LPTIM3 clock source */ + __HAL_RCC_LPTIM3_CONFIG(PeriphClkInit->Lptim3ClockSelection); + 8003fbc: 687b ldr r3, [r7, #4] + 8003fbe: 6a9b ldr r3, [r3, #40] @ 0x28 + 8003fc0: 4618 mov r0, r3 + 8003fc2: f7ff fed0 bl 8003d66 + } + + /*-------------------- I2C1 clock source configuration ---------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) + 8003fc6: 687b ldr r3, [r7, #4] + 8003fc8: 681b ldr r3, [r3, #0] + 8003fca: f003 0340 and.w r3, r3, #64 @ 0x40 + 8003fce: 2b00 cmp r3, #0 + 8003fd0: d004 beq.n 8003fdc + { + /* Check the parameters */ + assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection)); + + /* Configure the I2C1 clock source */ + __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection); + 8003fd2: 687b ldr r3, [r7, #4] + 8003fd4: 695b ldr r3, [r3, #20] + 8003fd6: 4618 mov r0, r3 + 8003fd8: f7ff fea9 bl 8003d2e + } + + /*-------------------- I2C2 clock source configuration ---------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) + 8003fdc: 687b ldr r3, [r7, #4] + 8003fde: 681b ldr r3, [r3, #0] + 8003fe0: f003 0380 and.w r3, r3, #128 @ 0x80 + 8003fe4: 2b00 cmp r3, #0 + 8003fe6: d004 beq.n 8003ff2 + { + /* Check the parameters */ + assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection)); + + /* Configure the I2C2 clock source */ + __HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection); + 8003fe8: 687b ldr r3, [r7, #4] + 8003fea: 699b ldr r3, [r3, #24] + 8003fec: 4618 mov r0, r3 + 8003fee: f7ff fe9e bl 8003d2e + } + + /*-------------------- I2C3 clock source configuration ---------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) + 8003ff2: 687b ldr r3, [r7, #4] + 8003ff4: 681b ldr r3, [r3, #0] + 8003ff6: f403 7380 and.w r3, r3, #256 @ 0x100 + 8003ffa: 2b00 cmp r3, #0 + 8003ffc: d004 beq.n 8004008 + { + /* Check the parameters */ + assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection)); + + /* Configure the I2C3 clock source */ + __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection); + 8003ffe: 687b ldr r3, [r7, #4] + 8004000: 69db ldr r3, [r3, #28] + 8004002: 4618 mov r0, r3 + 8004004: f7ff fe93 bl 8003d2e + } + + /*-------------------- I2S2 clock source configuration ---------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S2) == (RCC_PERIPHCLK_I2S2)) + 8004008: 687b ldr r3, [r7, #4] + 800400a: 681b ldr r3, [r3, #0] + 800400c: f003 0310 and.w r3, r3, #16 + 8004010: 2b00 cmp r3, #0 + 8004012: d011 beq.n 8004038 + { + /* Check the parameters */ + assert_param(IS_RCC_I2S2CLKSOURCE(PeriphClkInit->I2s2ClockSelection)); + + /* Configure the I2S2 clock source */ + __HAL_RCC_I2S2_CONFIG(PeriphClkInit->I2s2ClockSelection); + 8004014: 687b ldr r3, [r7, #4] + 8004016: 68db ldr r3, [r3, #12] + 8004018: 4618 mov r0, r3 + 800401a: f7ff fe5e bl 8003cda + + if (PeriphClkInit->I2s2ClockSelection == RCC_I2S2CLKSOURCE_PLL) + 800401e: 687b ldr r3, [r7, #4] + 8004020: 68db ldr r3, [r3, #12] + 8004022: f5b3 7f80 cmp.w r3, #256 @ 0x100 + 8004026: d107 bne.n 8004038 + { + /* Enable RCC_PLL_I2S2CLK output */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_I2S2CLK); + 8004028: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 800402c: 68db ldr r3, [r3, #12] + 800402e: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 8004032: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000 + 8004036: 60d3 str r3, [r2, #12] + } + } + + /*-------------------- RNG clock source configuration ----------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == (RCC_PERIPHCLK_RNG)) + 8004038: 687b ldr r3, [r7, #4] + 800403a: 681b ldr r3, [r3, #0] + 800403c: f403 4300 and.w r3, r3, #32768 @ 0x8000 + 8004040: 2b00 cmp r3, #0 + 8004042: d010 beq.n 8004066 + { + assert_param(IS_RCC_RNGCLKSOURCE(PeriphClkInit->RngClockSelection)); + __HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection); + 8004044: 687b ldr r3, [r7, #4] + 8004046: 6b1b ldr r3, [r3, #48] @ 0x30 + 8004048: 4618 mov r0, r3 + 800404a: f7ff fea5 bl 8003d98 + + if (PeriphClkInit->RngClockSelection == RCC_RNGCLKSOURCE_PLL) + 800404e: 687b ldr r3, [r7, #4] + 8004050: 6b1b ldr r3, [r3, #48] @ 0x30 + 8004052: 2b00 cmp r3, #0 + 8004054: d107 bne.n 8004066 + { + /* Enable RCC_PLL_RNGCLK output */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_RNGCLK); + 8004056: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 800405a: 68db ldr r3, [r3, #12] + 800405c: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 8004060: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000 + 8004064: 60d3 str r3, [r2, #12] + } + } + + /*-------------------- ADC clock source configuration ----------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) + 8004066: 687b ldr r3, [r7, #4] + 8004068: 681b ldr r3, [r3, #0] + 800406a: f403 4380 and.w r3, r3, #16384 @ 0x4000 + 800406e: 2b00 cmp r3, #0 + 8004070: d011 beq.n 8004096 + { + /* Check the parameters */ + assert_param(IS_RCC_ADCCLKSOURCE(PeriphClkInit->AdcClockSelection)); + + /* Configure the ADC interface clock source */ + __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection); + 8004072: 687b ldr r3, [r7, #4] + 8004074: 6adb ldr r3, [r3, #44] @ 0x2c + 8004076: 4618 mov r0, r3 + 8004078: f7ff fea3 bl 8003dc2 + + if (PeriphClkInit->AdcClockSelection == RCC_ADCCLKSOURCE_PLL) + 800407c: 687b ldr r3, [r7, #4] + 800407e: 6adb ldr r3, [r3, #44] @ 0x2c + 8004080: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 + 8004084: d107 bne.n 8004096 + { + /* Enable RCC_PLL_RNGCLK output */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_ADCCLK); + 8004086: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 800408a: 68db ldr r3, [r3, #12] + 800408c: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 8004090: f443 3380 orr.w r3, r3, #65536 @ 0x10000 + 8004094: 60d3 str r3, [r2, #12] + } + } + + return status; + 8004096: 7cbb ldrb r3, [r7, #18] +} + 8004098: 4618 mov r0, r3 + 800409a: 3718 adds r7, #24 + 800409c: 46bd mov sp, r7 + 800409e: bd80 pop {r7, pc} + 80040a0: 58000400 .word 0x58000400 + +080040a4 : + * @brief Initialize the RTC peripheral + * @param hrtc RTC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc) +{ + 80040a4: b580 push {r7, lr} + 80040a6: b084 sub sp, #16 + 80040a8: af00 add r7, sp, #0 + 80040aa: 6078 str r0, [r7, #4] + HAL_StatusTypeDef status = HAL_ERROR; + 80040ac: 2301 movs r3, #1 + 80040ae: 73fb strb r3, [r7, #15] + + /* Check the RTC peripheral state */ + if (hrtc != NULL) + 80040b0: 687b ldr r3, [r7, #4] + 80040b2: 2b00 cmp r3, #0 + 80040b4: d07b beq.n 80041ae + { + hrtc->MspDeInitCallback = HAL_RTC_MspDeInit; + } + } +#else + if (hrtc->State == HAL_RTC_STATE_RESET) + 80040b6: 687b ldr r3, [r7, #4] + 80040b8: f893 302d ldrb.w r3, [r3, #45] @ 0x2d + 80040bc: b2db uxtb r3, r3 + 80040be: 2b00 cmp r3, #0 + 80040c0: d106 bne.n 80040d0 + { + /* Allocate lock resource and initialize it */ + hrtc->Lock = HAL_UNLOCKED; + 80040c2: 687b ldr r3, [r7, #4] + 80040c4: 2200 movs r2, #0 + 80040c6: f883 202c strb.w r2, [r3, #44] @ 0x2c + + /* Initialize RTC MSP */ + HAL_RTC_MspInit(hrtc); + 80040ca: 6878 ldr r0, [r7, #4] + 80040cc: f7fc fc00 bl 80008d0 + } +#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */ + + /* Set RTC state */ + hrtc->State = HAL_RTC_STATE_BUSY; + 80040d0: 687b ldr r3, [r7, #4] + 80040d2: 2202 movs r2, #2 + 80040d4: f883 202d strb.w r2, [r3, #45] @ 0x2d + + /* Check whether the calendar needs to be initialized */ + if (__HAL_RTC_IS_CALENDAR_INITIALIZED(hrtc) == 0U) + 80040d8: 4b37 ldr r3, [pc, #220] @ (80041b8 ) + 80040da: 68db ldr r3, [r3, #12] + 80040dc: f003 0310 and.w r3, r3, #16 + 80040e0: 2b10 cmp r3, #16 + 80040e2: d05b beq.n 800419c + { + /* Check that the RTC mode is not 'binary only' */ + if (__HAL_RTC_GET_BINARY_MODE(hrtc) != RTC_BINARY_ONLY) + 80040e4: 4b34 ldr r3, [pc, #208] @ (80041b8 ) + 80040e6: 68db ldr r3, [r3, #12] + 80040e8: f403 7340 and.w r3, r3, #768 @ 0x300 + 80040ec: f5b3 7f80 cmp.w r3, #256 @ 0x100 + 80040f0: d051 beq.n 8004196 + { + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + 80040f2: 4b31 ldr r3, [pc, #196] @ (80041b8 ) + 80040f4: 22ca movs r2, #202 @ 0xca + 80040f6: 625a str r2, [r3, #36] @ 0x24 + 80040f8: 4b2f ldr r3, [pc, #188] @ (80041b8 ) + 80040fa: 2253 movs r2, #83 @ 0x53 + 80040fc: 625a str r2, [r3, #36] @ 0x24 + + /* Enter Initialization mode */ + status = RTC_EnterInitMode(hrtc); + 80040fe: 6878 ldr r0, [r7, #4] + 8004100: f000 fa14 bl 800452c + 8004104: 4603 mov r3, r0 + 8004106: 73fb strb r3, [r7, #15] + + if (status == HAL_OK) + 8004108: 7bfb ldrb r3, [r7, #15] + 800410a: 2b00 cmp r3, #0 + 800410c: d13f bne.n 800418e + { + /* Clear RTC_CR FMT, OSEL and POL Bits */ + CLEAR_BIT(RTC->CR, (RTC_CR_FMT | RTC_CR_POL | RTC_CR_OSEL | RTC_CR_TAMPOE)); + 800410e: 4b2a ldr r3, [pc, #168] @ (80041b8 ) + 8004110: 699b ldr r3, [r3, #24] + 8004112: 4a29 ldr r2, [pc, #164] @ (80041b8 ) + 8004114: f023 638e bic.w r3, r3, #74448896 @ 0x4700000 + 8004118: f023 0340 bic.w r3, r3, #64 @ 0x40 + 800411c: 6193 str r3, [r2, #24] + /* Set RTC_CR register */ + SET_BIT(RTC->CR, (hrtc->Init.HourFormat | hrtc->Init.OutPut | hrtc->Init.OutPutPolarity)); + 800411e: 4b26 ldr r3, [pc, #152] @ (80041b8 ) + 8004120: 699a ldr r2, [r3, #24] + 8004122: 687b ldr r3, [r7, #4] + 8004124: 6859 ldr r1, [r3, #4] + 8004126: 687b ldr r3, [r7, #4] + 8004128: 691b ldr r3, [r3, #16] + 800412a: 4319 orrs r1, r3 + 800412c: 687b ldr r3, [r7, #4] + 800412e: 699b ldr r3, [r3, #24] + 8004130: 430b orrs r3, r1 + 8004132: 4921 ldr r1, [pc, #132] @ (80041b8 ) + 8004134: 4313 orrs r3, r2 + 8004136: 618b str r3, [r1, #24] + + /* Configure the RTC PRER */ + WRITE_REG(RTC->PRER, ((hrtc->Init.SynchPrediv) | (hrtc->Init.AsynchPrediv << RTC_PRER_PREDIV_A_Pos))); + 8004138: 687b ldr r3, [r7, #4] + 800413a: 68da ldr r2, [r3, #12] + 800413c: 687b ldr r3, [r7, #4] + 800413e: 689b ldr r3, [r3, #8] + 8004140: 041b lsls r3, r3, #16 + 8004142: 491d ldr r1, [pc, #116] @ (80041b8 ) + 8004144: 4313 orrs r3, r2 + 8004146: 610b str r3, [r1, #16] + + /* Configure the Binary mode */ + MODIFY_REG(RTC->ICSR, RTC_ICSR_BIN | RTC_ICSR_BCDU, hrtc->Init.BinMode | hrtc->Init.BinMixBcdU); + 8004148: 4b1b ldr r3, [pc, #108] @ (80041b8 ) + 800414a: 68db ldr r3, [r3, #12] + 800414c: f423 52f8 bic.w r2, r3, #7936 @ 0x1f00 + 8004150: 687b ldr r3, [r7, #4] + 8004152: 6a59 ldr r1, [r3, #36] @ 0x24 + 8004154: 687b ldr r3, [r7, #4] + 8004156: 6a9b ldr r3, [r3, #40] @ 0x28 + 8004158: 430b orrs r3, r1 + 800415a: 4917 ldr r1, [pc, #92] @ (80041b8 ) + 800415c: 4313 orrs r3, r2 + 800415e: 60cb str r3, [r1, #12] + + /* Exit Initialization mode */ + status = RTC_ExitInitMode(hrtc); + 8004160: 6878 ldr r0, [r7, #4] + 8004162: f000 fa17 bl 8004594 + 8004166: 4603 mov r3, r0 + 8004168: 73fb strb r3, [r7, #15] + + if (status == HAL_OK) + 800416a: 7bfb ldrb r3, [r7, #15] + 800416c: 2b00 cmp r3, #0 + 800416e: d10e bne.n 800418e + { + MODIFY_REG(RTC->CR, \ + 8004170: 4b11 ldr r3, [pc, #68] @ (80041b8 ) + 8004172: 699b ldr r3, [r3, #24] + 8004174: f023 4260 bic.w r2, r3, #3758096384 @ 0xe0000000 + 8004178: 687b ldr r3, [r7, #4] + 800417a: 6a19 ldr r1, [r3, #32] + 800417c: 687b ldr r3, [r7, #4] + 800417e: 69db ldr r3, [r3, #28] + 8004180: 4319 orrs r1, r3 + 8004182: 687b ldr r3, [r7, #4] + 8004184: 695b ldr r3, [r3, #20] + 8004186: 430b orrs r3, r1 + 8004188: 490b ldr r1, [pc, #44] @ (80041b8 ) + 800418a: 4313 orrs r3, r2 + 800418c: 618b str r3, [r1, #24] + hrtc->Init.OutPutPullUp | hrtc->Init.OutPutType | hrtc->Init.OutPutRemap); + } + } + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + 800418e: 4b0a ldr r3, [pc, #40] @ (80041b8 ) + 8004190: 22ff movs r2, #255 @ 0xff + 8004192: 625a str r2, [r3, #36] @ 0x24 + 8004194: e004 b.n 80041a0 + } + else + { + /* The calendar does not need to be initialized as the 'binary only' mode is selected */ + status = HAL_OK; + 8004196: 2300 movs r3, #0 + 8004198: 73fb strb r3, [r7, #15] + 800419a: e001 b.n 80041a0 + } + } + else + { + /* The calendar is already initialized */ + status = HAL_OK; + 800419c: 2300 movs r3, #0 + 800419e: 73fb strb r3, [r7, #15] + } + + if (status == HAL_OK) + 80041a0: 7bfb ldrb r3, [r7, #15] + 80041a2: 2b00 cmp r3, #0 + 80041a4: d103 bne.n 80041ae + { + hrtc->State = HAL_RTC_STATE_READY; + 80041a6: 687b ldr r3, [r7, #4] + 80041a8: 2201 movs r2, #1 + 80041aa: f883 202d strb.w r2, [r3, #45] @ 0x2d + } + } + + return status; + 80041ae: 7bfb ldrb r3, [r7, #15] +} + 80041b0: 4618 mov r0, r3 + 80041b2: 3710 adds r7, #16 + 80041b4: 46bd mov sp, r7 + 80041b6: bd80 pop {r7, pc} + 80041b8: 40002800 .word 0x40002800 + +080041bc : + * @arg RTC_FORMAT_BIN: Binary format + * @arg RTC_FORMAT_BCD: BCD format + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format) +{ + 80041bc: b590 push {r4, r7, lr} + 80041be: b087 sub sp, #28 + 80041c0: af00 add r7, sp, #0 + 80041c2: 60f8 str r0, [r7, #12] + 80041c4: 60b9 str r1, [r7, #8] + 80041c6: 607a str r2, [r7, #4] + uint32_t tmpreg = 0; + 80041c8: 2300 movs r3, #0 + 80041ca: 617b str r3, [r7, #20] + uint32_t binaryMode; + + /* Process Locked */ + __HAL_LOCK(hrtc); + 80041cc: 68fb ldr r3, [r7, #12] + 80041ce: f893 302c ldrb.w r3, [r3, #44] @ 0x2c + 80041d2: 2b01 cmp r3, #1 + 80041d4: d101 bne.n 80041da + 80041d6: 2302 movs r3, #2 + 80041d8: e0f3 b.n 80043c2 + 80041da: 68fb ldr r3, [r7, #12] + 80041dc: 2201 movs r2, #1 + 80041de: f883 202c strb.w r2, [r3, #44] @ 0x2c + hrtc->State = HAL_RTC_STATE_BUSY; + 80041e2: 68fb ldr r3, [r7, #12] + 80041e4: 2202 movs r2, #2 + 80041e6: f883 202d strb.w r2, [r3, #45] @ 0x2d + RTC_ICSR_BCDU) >> RTC_ICSR_BCDU_Pos))); + } +#endif /* USE_FULL_ASSERT */ + + /* Get Binary mode (32-bit free-running counter configuration) */ + binaryMode = READ_BIT(RTC->ICSR, RTC_ICSR_BIN); + 80041ea: 4b78 ldr r3, [pc, #480] @ (80043cc ) + 80041ec: 68db ldr r3, [r3, #12] + 80041ee: f403 7340 and.w r3, r3, #768 @ 0x300 + 80041f2: 613b str r3, [r7, #16] + + if (binaryMode != RTC_BINARY_ONLY) + 80041f4: 693b ldr r3, [r7, #16] + 80041f6: f5b3 7f80 cmp.w r3, #256 @ 0x100 + 80041fa: d06a beq.n 80042d2 + { + if (Format == RTC_FORMAT_BIN) + 80041fc: 687b ldr r3, [r7, #4] + 80041fe: 2b00 cmp r3, #0 + 8004200: d13a bne.n 8004278 + { + if (READ_BIT(RTC->CR, RTC_CR_FMT) != 0U) + 8004202: 4b72 ldr r3, [pc, #456] @ (80043cc ) + 8004204: 699b ldr r3, [r3, #24] + 8004206: f003 0340 and.w r3, r3, #64 @ 0x40 + 800420a: 2b00 cmp r3, #0 + 800420c: d102 bne.n 8004214 + assert_param(IS_RTC_HOUR12(sAlarm->AlarmTime.Hours)); + assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat)); + } + else + { + sAlarm->AlarmTime.TimeFormat = 0x00U; + 800420e: 68bb ldr r3, [r7, #8] + 8004210: 2200 movs r2, #0 + 8004212: 70da strb r2, [r3, #3] + assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours)); + } + assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes)); + assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds)); + + if (sAlarm->AlarmMask != RTC_ALARMMASK_DATEWEEKDAY) + 8004214: 68bb ldr r3, [r7, #8] + 8004216: 695b ldr r3, [r3, #20] + 8004218: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 + { + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay)); + } + } + + tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << RTC_ALRMAR_HU_Pos) | \ + 800421c: 68bb ldr r3, [r7, #8] + 800421e: 781b ldrb r3, [r3, #0] + 8004220: 4618 mov r0, r3 + 8004222: f000 f9f5 bl 8004610 + 8004226: 4603 mov r3, r0 + 8004228: 041c lsls r4, r3, #16 + ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << RTC_ALRMAR_MNU_Pos) | \ + 800422a: 68bb ldr r3, [r7, #8] + 800422c: 785b ldrb r3, [r3, #1] + 800422e: 4618 mov r0, r3 + 8004230: f000 f9ee bl 8004610 + 8004234: 4603 mov r3, r0 + 8004236: 021b lsls r3, r3, #8 + tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << RTC_ALRMAR_HU_Pos) | \ + 8004238: 431c orrs r4, r3 + ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds) << RTC_ALRMAR_SU_Pos) | \ + 800423a: 68bb ldr r3, [r7, #8] + 800423c: 789b ldrb r3, [r3, #2] + 800423e: 4618 mov r0, r3 + 8004240: f000 f9e6 bl 8004610 + 8004244: 4603 mov r3, r0 + ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << RTC_ALRMAR_MNU_Pos) | \ + 8004246: ea44 0203 orr.w r2, r4, r3 + ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_ALRMAR_PM_Pos) | \ + 800424a: 68bb ldr r3, [r7, #8] + 800424c: 78db ldrb r3, [r3, #3] + 800424e: 059b lsls r3, r3, #22 + ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds) << RTC_ALRMAR_SU_Pos) | \ + 8004250: ea42 0403 orr.w r4, r2, r3 + ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << RTC_ALRMAR_DU_Pos) | \ + 8004254: 68bb ldr r3, [r7, #8] + 8004256: f893 3024 ldrb.w r3, [r3, #36] @ 0x24 + 800425a: 4618 mov r0, r3 + 800425c: f000 f9d8 bl 8004610 + 8004260: 4603 mov r3, r0 + 8004262: 061b lsls r3, r3, #24 + ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_ALRMAR_PM_Pos) | \ + 8004264: ea44 0203 orr.w r2, r4, r3 + ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \ + 8004268: 68bb ldr r3, [r7, #8] + 800426a: 6a1b ldr r3, [r3, #32] + ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << RTC_ALRMAR_DU_Pos) | \ + 800426c: 431a orrs r2, r3 + ((uint32_t)sAlarm->AlarmMask)); + 800426e: 68bb ldr r3, [r7, #8] + 8004270: 695b ldr r3, [r3, #20] + tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << RTC_ALRMAR_HU_Pos) | \ + 8004272: 4313 orrs r3, r2 + 8004274: 617b str r3, [r7, #20] + 8004276: e02c b.n 80042d2 + } + else /* Format BCD */ + { + if (sAlarm->AlarmMask != RTC_ALARMMASK_ALL) + 8004278: 68bb ldr r3, [r7, #8] + 800427a: 695b ldr r3, [r3, #20] + 800427c: f1b3 3f80 cmp.w r3, #2155905152 @ 0x80808080 + 8004280: d00d beq.n 800429e + { + if (sAlarm->AlarmMask != RTC_ALARMMASK_HOURS) + 8004282: 68bb ldr r3, [r7, #8] + 8004284: 695b ldr r3, [r3, #20] + 8004286: f5b3 0f00 cmp.w r3, #8388608 @ 0x800000 + 800428a: d008 beq.n 800429e + { + if (READ_BIT(RTC->CR, RTC_CR_FMT) != 0U) + 800428c: 4b4f ldr r3, [pc, #316] @ (80043cc ) + 800428e: 699b ldr r3, [r3, #24] + 8004290: f003 0340 and.w r3, r3, #64 @ 0x40 + 8004294: 2b00 cmp r3, #0 + 8004296: d102 bne.n 800429e + assert_param(IS_RTC_HOUR12(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours))); + assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat)); + } + else + { + sAlarm->AlarmTime.TimeFormat = 0x00U; + 8004298: 68bb ldr r3, [r7, #8] + 800429a: 2200 movs r2, #0 + 800429c: 70da strb r2, [r3, #3] + { + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay))); + } + } +#endif /* USE_FULL_ASSERT */ + tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << RTC_ALRMAR_HU_Pos) | \ + 800429e: 68bb ldr r3, [r7, #8] + 80042a0: 781b ldrb r3, [r3, #0] + 80042a2: 041a lsls r2, r3, #16 + ((uint32_t)(sAlarm->AlarmTime.Minutes) << RTC_ALRMAR_MNU_Pos) | \ + 80042a4: 68bb ldr r3, [r7, #8] + 80042a6: 785b ldrb r3, [r3, #1] + 80042a8: 021b lsls r3, r3, #8 + tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << RTC_ALRMAR_HU_Pos) | \ + 80042aa: 4313 orrs r3, r2 + ((uint32_t)(sAlarm->AlarmTime.Seconds) << RTC_ALRMAR_SU_Pos) | \ + 80042ac: 68ba ldr r2, [r7, #8] + 80042ae: 7892 ldrb r2, [r2, #2] + ((uint32_t)(sAlarm->AlarmTime.Minutes) << RTC_ALRMAR_MNU_Pos) | \ + 80042b0: 431a orrs r2, r3 + ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_ALRMAR_PM_Pos) | \ + 80042b2: 68bb ldr r3, [r7, #8] + 80042b4: 78db ldrb r3, [r3, #3] + 80042b6: 059b lsls r3, r3, #22 + ((uint32_t)(sAlarm->AlarmTime.Seconds) << RTC_ALRMAR_SU_Pos) | \ + 80042b8: 431a orrs r2, r3 + ((uint32_t)(sAlarm->AlarmDateWeekDay) << RTC_ALRMAR_DU_Pos) | \ + 80042ba: 68bb ldr r3, [r7, #8] + 80042bc: f893 3024 ldrb.w r3, [r3, #36] @ 0x24 + 80042c0: 061b lsls r3, r3, #24 + ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_ALRMAR_PM_Pos) | \ + 80042c2: 431a orrs r2, r3 + ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \ + 80042c4: 68bb ldr r3, [r7, #8] + 80042c6: 6a1b ldr r3, [r3, #32] + ((uint32_t)(sAlarm->AlarmDateWeekDay) << RTC_ALRMAR_DU_Pos) | \ + 80042c8: 431a orrs r2, r3 + ((uint32_t)sAlarm->AlarmMask)); + 80042ca: 68bb ldr r3, [r7, #8] + 80042cc: 695b ldr r3, [r3, #20] + tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << RTC_ALRMAR_HU_Pos) | \ + 80042ce: 4313 orrs r3, r2 + 80042d0: 617b str r3, [r7, #20] + + } + } + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + 80042d2: 4b3e ldr r3, [pc, #248] @ (80043cc ) + 80042d4: 22ca movs r2, #202 @ 0xca + 80042d6: 625a str r2, [r3, #36] @ 0x24 + 80042d8: 4b3c ldr r3, [pc, #240] @ (80043cc ) + 80042da: 2253 movs r2, #83 @ 0x53 + 80042dc: 625a str r2, [r3, #36] @ 0x24 + + /* Configure the Alarm register */ + if (sAlarm->Alarm == RTC_ALARM_A) + 80042de: 68bb ldr r3, [r7, #8] + 80042e0: 6a9b ldr r3, [r3, #40] @ 0x28 + 80042e2: f5b3 7f80 cmp.w r3, #256 @ 0x100 + 80042e6: d12c bne.n 8004342 + { + /* Disable the Alarm A interrupt */ + CLEAR_BIT(RTC->CR, RTC_CR_ALRAE | RTC_CR_ALRAIE); + 80042e8: 4b38 ldr r3, [pc, #224] @ (80043cc ) + 80042ea: 699b ldr r3, [r3, #24] + 80042ec: 4a37 ldr r2, [pc, #220] @ (80043cc ) + 80042ee: f423 5388 bic.w r3, r3, #4352 @ 0x1100 + 80042f2: 6193 str r3, [r2, #24] + /* Clear flag alarm A */ + WRITE_REG(RTC->SCR, RTC_SCR_CALRAF); + 80042f4: 4b35 ldr r3, [pc, #212] @ (80043cc ) + 80042f6: 2201 movs r2, #1 + 80042f8: 65da str r2, [r3, #92] @ 0x5c + + if (binaryMode == RTC_BINARY_ONLY) + 80042fa: 693b ldr r3, [r7, #16] + 80042fc: f5b3 7f80 cmp.w r3, #256 @ 0x100 + 8004300: d107 bne.n 8004312 + { + RTC->ALRMASSR = sAlarm->AlarmSubSecondMask | sAlarm->BinaryAutoClr; + 8004302: 68bb ldr r3, [r7, #8] + 8004304: 699a ldr r2, [r3, #24] + 8004306: 68bb ldr r3, [r7, #8] + 8004308: 69db ldr r3, [r3, #28] + 800430a: 4930 ldr r1, [pc, #192] @ (80043cc ) + 800430c: 4313 orrs r3, r2 + 800430e: 644b str r3, [r1, #68] @ 0x44 + 8004310: e006 b.n 8004320 + } + else + { + WRITE_REG(RTC->ALRMAR, tmpreg); + 8004312: 4a2e ldr r2, [pc, #184] @ (80043cc ) + 8004314: 697b ldr r3, [r7, #20] + 8004316: 6413 str r3, [r2, #64] @ 0x40 + WRITE_REG(RTC->ALRMASSR, sAlarm->AlarmSubSecondMask); + 8004318: 4a2c ldr r2, [pc, #176] @ (80043cc ) + 800431a: 68bb ldr r3, [r7, #8] + 800431c: 699b ldr r3, [r3, #24] + 800431e: 6453 str r3, [r2, #68] @ 0x44 + } + + WRITE_REG(RTC->ALRABINR, sAlarm->AlarmTime.SubSeconds); + 8004320: 4a2a ldr r2, [pc, #168] @ (80043cc ) + 8004322: 68bb ldr r3, [r7, #8] + 8004324: 685b ldr r3, [r3, #4] + 8004326: 6713 str r3, [r2, #112] @ 0x70 + + /* Store in the handle the Alarm A enabled */ + SET_BIT(hrtc->IsEnabled.RtcFeatures, RTC_MISR_ALRAMF); + 8004328: 68fb ldr r3, [r7, #12] + 800432a: 6b1b ldr r3, [r3, #48] @ 0x30 + 800432c: f043 0201 orr.w r2, r3, #1 + 8004330: 68fb ldr r3, [r7, #12] + 8004332: 631a str r2, [r3, #48] @ 0x30 + + /* Configure the Alarm interrupt */ + SET_BIT(RTC->CR, RTC_CR_ALRAE | RTC_CR_ALRAIE); + 8004334: 4b25 ldr r3, [pc, #148] @ (80043cc ) + 8004336: 699b ldr r3, [r3, #24] + 8004338: 4a24 ldr r2, [pc, #144] @ (80043cc ) + 800433a: f443 5388 orr.w r3, r3, #4352 @ 0x1100 + 800433e: 6193 str r3, [r2, #24] + 8004340: e02b b.n 800439a + } + else + { + /* Disable the Alarm B interrupt */ + CLEAR_BIT(RTC->CR, RTC_CR_ALRBE | RTC_CR_ALRBIE); + 8004342: 4b22 ldr r3, [pc, #136] @ (80043cc ) + 8004344: 699b ldr r3, [r3, #24] + 8004346: 4a21 ldr r2, [pc, #132] @ (80043cc ) + 8004348: f423 5308 bic.w r3, r3, #8704 @ 0x2200 + 800434c: 6193 str r3, [r2, #24] + /* Clear flag alarm B */ + WRITE_REG(RTC->SCR, RTC_SCR_CALRBF); + 800434e: 4b1f ldr r3, [pc, #124] @ (80043cc ) + 8004350: 2202 movs r2, #2 + 8004352: 65da str r2, [r3, #92] @ 0x5c + + if (binaryMode == RTC_BINARY_ONLY) + 8004354: 693b ldr r3, [r7, #16] + 8004356: f5b3 7f80 cmp.w r3, #256 @ 0x100 + 800435a: d107 bne.n 800436c + { + WRITE_REG(RTC->ALRMBSSR, sAlarm->AlarmSubSecondMask | sAlarm->BinaryAutoClr); + 800435c: 68bb ldr r3, [r7, #8] + 800435e: 699a ldr r2, [r3, #24] + 8004360: 68bb ldr r3, [r7, #8] + 8004362: 69db ldr r3, [r3, #28] + 8004364: 4919 ldr r1, [pc, #100] @ (80043cc ) + 8004366: 4313 orrs r3, r2 + 8004368: 64cb str r3, [r1, #76] @ 0x4c + 800436a: e006 b.n 800437a + } + else + { + WRITE_REG(RTC->ALRMBR, tmpreg); + 800436c: 4a17 ldr r2, [pc, #92] @ (80043cc ) + 800436e: 697b ldr r3, [r7, #20] + 8004370: 6493 str r3, [r2, #72] @ 0x48 + WRITE_REG(RTC->ALRMBSSR, sAlarm->AlarmSubSecondMask); + 8004372: 4a16 ldr r2, [pc, #88] @ (80043cc ) + 8004374: 68bb ldr r3, [r7, #8] + 8004376: 699b ldr r3, [r3, #24] + 8004378: 64d3 str r3, [r2, #76] @ 0x4c + } + + WRITE_REG(RTC->ALRBBINR, sAlarm->AlarmTime.SubSeconds); + 800437a: 4a14 ldr r2, [pc, #80] @ (80043cc ) + 800437c: 68bb ldr r3, [r7, #8] + 800437e: 685b ldr r3, [r3, #4] + 8004380: 6753 str r3, [r2, #116] @ 0x74 + + /* Store in the handle the Alarm B enabled */ + SET_BIT(hrtc->IsEnabled.RtcFeatures, RTC_MISR_ALRBMF); + 8004382: 68fb ldr r3, [r7, #12] + 8004384: 6b1b ldr r3, [r3, #48] @ 0x30 + 8004386: f043 0202 orr.w r2, r3, #2 + 800438a: 68fb ldr r3, [r7, #12] + 800438c: 631a str r2, [r3, #48] @ 0x30 + + /* Configure the Alarm interrupt */ + SET_BIT(RTC->CR, RTC_CR_ALRBE | RTC_CR_ALRBIE); + 800438e: 4b0f ldr r3, [pc, #60] @ (80043cc ) + 8004390: 699b ldr r3, [r3, #24] + 8004392: 4a0e ldr r2, [pc, #56] @ (80043cc ) + 8004394: f443 5308 orr.w r3, r3, #8704 @ 0x2200 + 8004398: 6193 str r3, [r2, #24] + } + + /* RTC Alarm Interrupt Configuration: EXTI configuration */ + __HAL_RTC_ALARM_EXTI_ENABLE_IT(); + 800439a: 4b0d ldr r3, [pc, #52] @ (80043d0 ) + 800439c: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 + 80043a0: 4a0b ldr r2, [pc, #44] @ (80043d0 ) + 80043a2: f443 3300 orr.w r3, r3, #131072 @ 0x20000 + 80043a6: f8c2 3080 str.w r3, [r2, #128] @ 0x80 + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + 80043aa: 4b08 ldr r3, [pc, #32] @ (80043cc ) + 80043ac: 22ff movs r2, #255 @ 0xff + 80043ae: 625a str r2, [r3, #36] @ 0x24 + + hrtc->State = HAL_RTC_STATE_READY; + 80043b0: 68fb ldr r3, [r7, #12] + 80043b2: 2201 movs r2, #1 + 80043b4: f883 202d strb.w r2, [r3, #45] @ 0x2d + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + 80043b8: 68fb ldr r3, [r7, #12] + 80043ba: 2200 movs r2, #0 + 80043bc: f883 202c strb.w r2, [r3, #44] @ 0x2c + + return HAL_OK; + 80043c0: 2300 movs r3, #0 +} + 80043c2: 4618 mov r0, r3 + 80043c4: 371c adds r7, #28 + 80043c6: 46bd mov sp, r7 + 80043c8: bd90 pop {r4, r7, pc} + 80043ca: bf00 nop + 80043cc: 40002800 .word 0x40002800 + 80043d0: 58000800 .word 0x58000800 + +080043d4 : + * @arg RTC_ALARM_A: AlarmA + * @arg RTC_ALARM_B: AlarmB + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm) +{ + 80043d4: b480 push {r7} + 80043d6: b083 sub sp, #12 + 80043d8: af00 add r7, sp, #0 + 80043da: 6078 str r0, [r7, #4] + 80043dc: 6039 str r1, [r7, #0] + /* Check the parameters */ + assert_param(IS_RTC_ALARM(Alarm)); + + /* Process Locked */ + __HAL_LOCK(hrtc); + 80043de: 687b ldr r3, [r7, #4] + 80043e0: f893 302c ldrb.w r3, [r3, #44] @ 0x2c + 80043e4: 2b01 cmp r3, #1 + 80043e6: d101 bne.n 80043ec + 80043e8: 2302 movs r3, #2 + 80043ea: e048 b.n 800447e + 80043ec: 687b ldr r3, [r7, #4] + 80043ee: 2201 movs r2, #1 + 80043f0: f883 202c strb.w r2, [r3, #44] @ 0x2c + + hrtc->State = HAL_RTC_STATE_BUSY; + 80043f4: 687b ldr r3, [r7, #4] + 80043f6: 2202 movs r2, #2 + 80043f8: f883 202d strb.w r2, [r3, #45] @ 0x2d + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + 80043fc: 4b22 ldr r3, [pc, #136] @ (8004488 ) + 80043fe: 22ca movs r2, #202 @ 0xca + 8004400: 625a str r2, [r3, #36] @ 0x24 + 8004402: 4b21 ldr r3, [pc, #132] @ (8004488 ) + 8004404: 2253 movs r2, #83 @ 0x53 + 8004406: 625a str r2, [r3, #36] @ 0x24 + + if (Alarm == RTC_ALARM_A) + 8004408: 683b ldr r3, [r7, #0] + 800440a: f5b3 7f80 cmp.w r3, #256 @ 0x100 + 800440e: d115 bne.n 800443c + { + /* AlarmA, In case of interrupt mode is used, the interrupt source must disabled */ + CLEAR_BIT(RTC->CR, RTC_CR_ALRAE | RTC_CR_ALRAIE); + 8004410: 4b1d ldr r3, [pc, #116] @ (8004488 ) + 8004412: 699b ldr r3, [r3, #24] + 8004414: 4a1c ldr r2, [pc, #112] @ (8004488 ) + 8004416: f423 5388 bic.w r3, r3, #4352 @ 0x1100 + 800441a: 6193 str r3, [r2, #24] + + /* AlarmA, Clear SSCLR */ + CLEAR_BIT(RTC->ALRMASSR, RTC_ALRMASSR_SSCLR); + 800441c: 4b1a ldr r3, [pc, #104] @ (8004488 ) + 800441e: 6c5b ldr r3, [r3, #68] @ 0x44 + 8004420: 4a19 ldr r2, [pc, #100] @ (8004488 ) + 8004422: f023 4300 bic.w r3, r3, #2147483648 @ 0x80000000 + 8004426: 6453 str r3, [r2, #68] @ 0x44 + + /* Store in the handle the Alarm A disabled */ + CLEAR_BIT(hrtc->IsEnabled.RtcFeatures, RTC_MISR_ALRAMF); + 8004428: 687b ldr r3, [r7, #4] + 800442a: 6b1b ldr r3, [r3, #48] @ 0x30 + 800442c: f023 0201 bic.w r2, r3, #1 + 8004430: 687b ldr r3, [r7, #4] + 8004432: 631a str r2, [r3, #48] @ 0x30 + + /* Clear AlarmA flag */ + WRITE_REG(RTC->SCR, RTC_SCR_CALRAF); + 8004434: 4b14 ldr r3, [pc, #80] @ (8004488 ) + 8004436: 2201 movs r2, #1 + 8004438: 65da str r2, [r3, #92] @ 0x5c + 800443a: e014 b.n 8004466 + } + else + { + /* AlarmB, In case of interrupt mode is used, the interrupt source must disabled */ + CLEAR_BIT(RTC->CR, RTC_CR_ALRBE | RTC_CR_ALRBIE); + 800443c: 4b12 ldr r3, [pc, #72] @ (8004488 ) + 800443e: 699b ldr r3, [r3, #24] + 8004440: 4a11 ldr r2, [pc, #68] @ (8004488 ) + 8004442: f423 5308 bic.w r3, r3, #8704 @ 0x2200 + 8004446: 6193 str r3, [r2, #24] + + /* AlarmB, Clear SSCLR */ + CLEAR_BIT(RTC->ALRMBSSR, RTC_ALRMBSSR_SSCLR); + 8004448: 4b0f ldr r3, [pc, #60] @ (8004488 ) + 800444a: 6cdb ldr r3, [r3, #76] @ 0x4c + 800444c: 4a0e ldr r2, [pc, #56] @ (8004488 ) + 800444e: f023 4300 bic.w r3, r3, #2147483648 @ 0x80000000 + 8004452: 64d3 str r3, [r2, #76] @ 0x4c + + /* Store in the handle the Alarm B disabled */ + CLEAR_BIT(hrtc->IsEnabled.RtcFeatures, RTC_MISR_ALRBMF); + 8004454: 687b ldr r3, [r7, #4] + 8004456: 6b1b ldr r3, [r3, #48] @ 0x30 + 8004458: f023 0202 bic.w r2, r3, #2 + 800445c: 687b ldr r3, [r7, #4] + 800445e: 631a str r2, [r3, #48] @ 0x30 + + /* Clear AlarmB flag */ + WRITE_REG(RTC->SCR, RTC_SCR_CALRBF); + 8004460: 4b09 ldr r3, [pc, #36] @ (8004488 ) + 8004462: 2202 movs r2, #2 + 8004464: 65da str r2, [r3, #92] @ 0x5c + } + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + 8004466: 4b08 ldr r3, [pc, #32] @ (8004488 ) + 8004468: 22ff movs r2, #255 @ 0xff + 800446a: 625a str r2, [r3, #36] @ 0x24 + + hrtc->State = HAL_RTC_STATE_READY; + 800446c: 687b ldr r3, [r7, #4] + 800446e: 2201 movs r2, #1 + 8004470: f883 202d strb.w r2, [r3, #45] @ 0x2d + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + 8004474: 687b ldr r3, [r7, #4] + 8004476: 2200 movs r2, #0 + 8004478: f883 202c strb.w r2, [r3, #44] @ 0x2c + + return HAL_OK; + 800447c: 2300 movs r3, #0 +} + 800447e: 4618 mov r0, r3 + 8004480: 370c adds r7, #12 + 8004482: 46bd mov sp, r7 + 8004484: bc80 pop {r7} + 8004486: 4770 bx lr + 8004488: 40002800 .word 0x40002800 + +0800448c : + * @brief Handle Alarm interrupt request. + * @param hrtc RTC handle + * @retval None + */ +void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc) +{ + 800448c: b580 push {r7, lr} + 800448e: b084 sub sp, #16 + 8004490: af00 add r7, sp, #0 + 8004492: 6078 str r0, [r7, #4] + uint32_t tmp = READ_REG(RTC->MISR) & READ_REG(hrtc->IsEnabled.RtcFeatures); + 8004494: 4b11 ldr r3, [pc, #68] @ (80044dc ) + 8004496: 6d5a ldr r2, [r3, #84] @ 0x54 + 8004498: 687b ldr r3, [r7, #4] + 800449a: 6b1b ldr r3, [r3, #48] @ 0x30 + 800449c: 4013 ands r3, r2 + 800449e: 60fb str r3, [r7, #12] + + if ((tmp & RTC_MISR_ALRAMF) != 0U) + 80044a0: 68fb ldr r3, [r7, #12] + 80044a2: f003 0301 and.w r3, r3, #1 + 80044a6: 2b00 cmp r3, #0 + 80044a8: d005 beq.n 80044b6 + { + /* Clear the AlarmA interrupt pending bit */ + WRITE_REG(RTC->SCR, RTC_SCR_CALRAF); + 80044aa: 4b0c ldr r3, [pc, #48] @ (80044dc ) + 80044ac: 2201 movs r2, #1 + 80044ae: 65da str r2, [r3, #92] @ 0x5c + +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + /* Call Compare Match registered Callback */ + hrtc->AlarmAEventCallback(hrtc); +#else + HAL_RTC_AlarmAEventCallback(hrtc); + 80044b0: 6878 ldr r0, [r7, #4] + 80044b2: f7fc fdf0 bl 8001096 +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ + } + + if ((tmp & RTC_MISR_ALRBMF) != 0U) + 80044b6: 68fb ldr r3, [r7, #12] + 80044b8: f003 0302 and.w r3, r3, #2 + 80044bc: 2b00 cmp r3, #0 + 80044be: d005 beq.n 80044cc + { + /* Clear the AlarmB interrupt pending bit */ + WRITE_REG(RTC->SCR, RTC_SCR_CALRBF); + 80044c0: 4b06 ldr r3, [pc, #24] @ (80044dc ) + 80044c2: 2202 movs r2, #2 + 80044c4: 65da str r2, [r3, #92] @ 0x5c + +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + /* Call Compare Match registered Callback */ + hrtc->AlarmBEventCallback(hrtc); +#else + HAL_RTCEx_AlarmBEventCallback(hrtc); + 80044c6: 6878 ldr r0, [r7, #4] + 80044c8: f000 f94a bl 8004760 +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ + } + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + 80044cc: 687b ldr r3, [r7, #4] + 80044ce: 2201 movs r2, #1 + 80044d0: f883 202d strb.w r2, [r3, #45] @ 0x2d +} + 80044d4: bf00 nop + 80044d6: 3710 adds r7, #16 + 80044d8: 46bd mov sp, r7 + 80044da: bd80 pop {r7, pc} + 80044dc: 40002800 .word 0x40002800 + +080044e0 : + * correctly copied into the RTC_TR and RTC_DR shadow registers. + * @param hrtc RTC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_WaitForSynchro(const RTC_HandleTypeDef *hrtc) +{ + 80044e0: b580 push {r7, lr} + 80044e2: b084 sub sp, #16 + 80044e4: af00 add r7, sp, #0 + 80044e6: 6078 str r0, [r7, #4] + uint32_t tickstart; + + UNUSED(hrtc); + /* Clear RSF flag */ + CLEAR_BIT(RTC->ICSR, RTC_ICSR_RSF); + 80044e8: 4b0f ldr r3, [pc, #60] @ (8004528 ) + 80044ea: 68db ldr r3, [r3, #12] + 80044ec: 4a0e ldr r2, [pc, #56] @ (8004528 ) + 80044ee: f023 0320 bic.w r3, r3, #32 + 80044f2: 60d3 str r3, [r2, #12] + + tickstart = HAL_GetTick(); + 80044f4: f7fc fba8 bl 8000c48 + 80044f8: 60f8 str r0, [r7, #12] + + /* Wait the registers to be synchronised */ + while (READ_BIT(RTC->ICSR, RTC_ICSR_RSF) == 0U) + 80044fa: e009 b.n 8004510 + { + if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) + 80044fc: f7fc fba4 bl 8000c48 + 8004500: 4602 mov r2, r0 + 8004502: 68fb ldr r3, [r7, #12] + 8004504: 1ad3 subs r3, r2, r3 + 8004506: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 + 800450a: d901 bls.n 8004510 + { + return HAL_TIMEOUT; + 800450c: 2303 movs r3, #3 + 800450e: e006 b.n 800451e + while (READ_BIT(RTC->ICSR, RTC_ICSR_RSF) == 0U) + 8004510: 4b05 ldr r3, [pc, #20] @ (8004528 ) + 8004512: 68db ldr r3, [r3, #12] + 8004514: f003 0320 and.w r3, r3, #32 + 8004518: 2b00 cmp r3, #0 + 800451a: d0ef beq.n 80044fc + } + } + + return HAL_OK; + 800451c: 2300 movs r3, #0 +} + 800451e: 4618 mov r0, r3 + 8004520: 3710 adds r7, #16 + 8004522: 46bd mov sp, r7 + 8004524: bd80 pop {r7, pc} + 8004526: bf00 nop + 8004528: 40002800 .word 0x40002800 + +0800452c : + * __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function. + * @param hrtc RTC handle + * @retval HAL status + */ +HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef *hrtc) +{ + 800452c: b580 push {r7, lr} + 800452e: b084 sub sp, #16 + 8004530: af00 add r7, sp, #0 + 8004532: 6078 str r0, [r7, #4] + uint32_t tickstart; + HAL_StatusTypeDef status = HAL_OK; + 8004534: 2300 movs r3, #0 + 8004536: 73fb strb r3, [r7, #15] + + UNUSED(hrtc); + /* Check if the Initialization mode is set */ + if (READ_BIT(RTC->ICSR, RTC_ICSR_INITF) == 0U) + 8004538: 4b15 ldr r3, [pc, #84] @ (8004590 ) + 800453a: 68db ldr r3, [r3, #12] + 800453c: f003 0340 and.w r3, r3, #64 @ 0x40 + 8004540: 2b00 cmp r3, #0 + 8004542: d120 bne.n 8004586 + { + /* Set the Initialization mode */ + SET_BIT(RTC->ICSR, RTC_ICSR_INIT); + 8004544: 4b12 ldr r3, [pc, #72] @ (8004590 ) + 8004546: 68db ldr r3, [r3, #12] + 8004548: 4a11 ldr r2, [pc, #68] @ (8004590 ) + 800454a: f043 0380 orr.w r3, r3, #128 @ 0x80 + 800454e: 60d3 str r3, [r2, #12] + + tickstart = HAL_GetTick(); + 8004550: f7fc fb7a bl 8000c48 + 8004554: 60b8 str r0, [r7, #8] + /* Wait till RTC is in INIT state and if Time out is reached exit */ + while ((READ_BIT(RTC->ICSR, RTC_ICSR_INITF) == 0U) && (status != HAL_TIMEOUT)) + 8004556: e00d b.n 8004574 + { + if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) + 8004558: f7fc fb76 bl 8000c48 + 800455c: 4602 mov r2, r0 + 800455e: 68bb ldr r3, [r7, #8] + 8004560: 1ad3 subs r3, r2, r3 + 8004562: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 + 8004566: d905 bls.n 8004574 + { + status = HAL_TIMEOUT; + 8004568: 2303 movs r3, #3 + 800456a: 73fb strb r3, [r7, #15] + hrtc->State = HAL_RTC_STATE_TIMEOUT; + 800456c: 687b ldr r3, [r7, #4] + 800456e: 2203 movs r2, #3 + 8004570: f883 202d strb.w r2, [r3, #45] @ 0x2d + while ((READ_BIT(RTC->ICSR, RTC_ICSR_INITF) == 0U) && (status != HAL_TIMEOUT)) + 8004574: 4b06 ldr r3, [pc, #24] @ (8004590 ) + 8004576: 68db ldr r3, [r3, #12] + 8004578: f003 0340 and.w r3, r3, #64 @ 0x40 + 800457c: 2b00 cmp r3, #0 + 800457e: d102 bne.n 8004586 + 8004580: 7bfb ldrb r3, [r7, #15] + 8004582: 2b03 cmp r3, #3 + 8004584: d1e8 bne.n 8004558 + } + } + } + + return status; + 8004586: 7bfb ldrb r3, [r7, #15] +} + 8004588: 4618 mov r0, r3 + 800458a: 3710 adds r7, #16 + 800458c: 46bd mov sp, r7 + 800458e: bd80 pop {r7, pc} + 8004590: 40002800 .word 0x40002800 + +08004594 : + * @brief Exit the RTC Initialization mode. + * @param hrtc RTC handle + * @retval HAL status + */ +HAL_StatusTypeDef RTC_ExitInitMode(RTC_HandleTypeDef *hrtc) +{ + 8004594: b580 push {r7, lr} + 8004596: b084 sub sp, #16 + 8004598: af00 add r7, sp, #0 + 800459a: 6078 str r0, [r7, #4] + HAL_StatusTypeDef status = HAL_OK; + 800459c: 2300 movs r3, #0 + 800459e: 73fb strb r3, [r7, #15] + + /* Exit Initialization mode */ + CLEAR_BIT(RTC->ICSR, RTC_ICSR_INIT); + 80045a0: 4b1a ldr r3, [pc, #104] @ (800460c ) + 80045a2: 68db ldr r3, [r3, #12] + 80045a4: 4a19 ldr r2, [pc, #100] @ (800460c ) + 80045a6: f023 0380 bic.w r3, r3, #128 @ 0x80 + 80045aa: 60d3 str r3, [r2, #12] + + /* If CR_BYPSHAD bit = 0, wait for synchro */ + if (READ_BIT(RTC->CR, RTC_CR_BYPSHAD) == 0U) + 80045ac: 4b17 ldr r3, [pc, #92] @ (800460c ) + 80045ae: 699b ldr r3, [r3, #24] + 80045b0: f003 0320 and.w r3, r3, #32 + 80045b4: 2b00 cmp r3, #0 + 80045b6: d10c bne.n 80045d2 + { + if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) + 80045b8: 6878 ldr r0, [r7, #4] + 80045ba: f7ff ff91 bl 80044e0 + 80045be: 4603 mov r3, r0 + 80045c0: 2b00 cmp r3, #0 + 80045c2: d01e beq.n 8004602 + { + hrtc->State = HAL_RTC_STATE_TIMEOUT; + 80045c4: 687b ldr r3, [r7, #4] + 80045c6: 2203 movs r2, #3 + 80045c8: f883 202d strb.w r2, [r3, #45] @ 0x2d + status = HAL_TIMEOUT; + 80045cc: 2303 movs r3, #3 + 80045ce: 73fb strb r3, [r7, #15] + 80045d0: e017 b.n 8004602 + } + } + else /* WA 2.9.6 Calendar initialization may fail in case of consecutive INIT mode entry. */ + { + /* Clear BYPSHAD bit */ + CLEAR_BIT(RTC->CR, RTC_CR_BYPSHAD); + 80045d2: 4b0e ldr r3, [pc, #56] @ (800460c ) + 80045d4: 699b ldr r3, [r3, #24] + 80045d6: 4a0d ldr r2, [pc, #52] @ (800460c ) + 80045d8: f023 0320 bic.w r3, r3, #32 + 80045dc: 6193 str r3, [r2, #24] + if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) + 80045de: 6878 ldr r0, [r7, #4] + 80045e0: f7ff ff7e bl 80044e0 + 80045e4: 4603 mov r3, r0 + 80045e6: 2b00 cmp r3, #0 + 80045e8: d005 beq.n 80045f6 + { + hrtc->State = HAL_RTC_STATE_TIMEOUT; + 80045ea: 687b ldr r3, [r7, #4] + 80045ec: 2203 movs r2, #3 + 80045ee: f883 202d strb.w r2, [r3, #45] @ 0x2d + status = HAL_TIMEOUT; + 80045f2: 2303 movs r3, #3 + 80045f4: 73fb strb r3, [r7, #15] + } + /* Restore BYPSHAD bit */ + SET_BIT(RTC->CR, RTC_CR_BYPSHAD); + 80045f6: 4b05 ldr r3, [pc, #20] @ (800460c ) + 80045f8: 699b ldr r3, [r3, #24] + 80045fa: 4a04 ldr r2, [pc, #16] @ (800460c ) + 80045fc: f043 0320 orr.w r3, r3, #32 + 8004600: 6193 str r3, [r2, #24] + } + + return status; + 8004602: 7bfb ldrb r3, [r7, #15] +} + 8004604: 4618 mov r0, r3 + 8004606: 3710 adds r7, #16 + 8004608: 46bd mov sp, r7 + 800460a: bd80 pop {r7, pc} + 800460c: 40002800 .word 0x40002800 + +08004610 : + * @brief Convert a 2 digit decimal to BCD format. + * @param Value Byte to be converted + * @retval Converted byte + */ +uint8_t RTC_ByteToBcd2(uint8_t Value) +{ + 8004610: b480 push {r7} + 8004612: b085 sub sp, #20 + 8004614: af00 add r7, sp, #0 + 8004616: 4603 mov r3, r0 + 8004618: 71fb strb r3, [r7, #7] + uint32_t bcdhigh = 0U; + 800461a: 2300 movs r3, #0 + 800461c: 60fb str r3, [r7, #12] + uint8_t tmp_Value = Value; + 800461e: 79fb ldrb r3, [r7, #7] + 8004620: 72fb strb r3, [r7, #11] + + while (tmp_Value >= 10U) + 8004622: e005 b.n 8004630 + { + bcdhigh++; + 8004624: 68fb ldr r3, [r7, #12] + 8004626: 3301 adds r3, #1 + 8004628: 60fb str r3, [r7, #12] + tmp_Value -= 10U; + 800462a: 7afb ldrb r3, [r7, #11] + 800462c: 3b0a subs r3, #10 + 800462e: 72fb strb r3, [r7, #11] + while (tmp_Value >= 10U) + 8004630: 7afb ldrb r3, [r7, #11] + 8004632: 2b09 cmp r3, #9 + 8004634: d8f6 bhi.n 8004624 + } + + return ((uint8_t)(bcdhigh << 4U) | tmp_Value); + 8004636: 68fb ldr r3, [r7, #12] + 8004638: b2db uxtb r3, r3 + 800463a: 011b lsls r3, r3, #4 + 800463c: b2da uxtb r2, r3 + 800463e: 7afb ldrb r3, [r7, #11] + 8004640: 4313 orrs r3, r2 + 8004642: b2db uxtb r3, r3 +} + 8004644: 4618 mov r0, r3 + 8004646: 3714 adds r7, #20 + 8004648: 46bd mov sp, r7 + 800464a: bc80 pop {r7} + 800464c: 4770 bx lr + ... + +08004650 : + * directly from the Calendar counter. + * @param hrtc RTC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef *hrtc) +{ + 8004650: b480 push {r7} + 8004652: b083 sub sp, #12 + 8004654: af00 add r7, sp, #0 + 8004656: 6078 str r0, [r7, #4] + /* Process Locked */ + __HAL_LOCK(hrtc); + 8004658: 687b ldr r3, [r7, #4] + 800465a: f893 302c ldrb.w r3, [r3, #44] @ 0x2c + 800465e: 2b01 cmp r3, #1 + 8004660: d101 bne.n 8004666 + 8004662: 2302 movs r3, #2 + 8004664: e01f b.n 80046a6 + 8004666: 687b ldr r3, [r7, #4] + 8004668: 2201 movs r2, #1 + 800466a: f883 202c strb.w r2, [r3, #44] @ 0x2c + + hrtc->State = HAL_RTC_STATE_BUSY; + 800466e: 687b ldr r3, [r7, #4] + 8004670: 2202 movs r2, #2 + 8004672: f883 202d strb.w r2, [r3, #45] @ 0x2d + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + 8004676: 4b0e ldr r3, [pc, #56] @ (80046b0 ) + 8004678: 22ca movs r2, #202 @ 0xca + 800467a: 625a str r2, [r3, #36] @ 0x24 + 800467c: 4b0c ldr r3, [pc, #48] @ (80046b0 ) + 800467e: 2253 movs r2, #83 @ 0x53 + 8004680: 625a str r2, [r3, #36] @ 0x24 + + /* Set the BYPSHAD bit */ + SET_BIT(RTC->CR, RTC_CR_BYPSHAD); + 8004682: 4b0b ldr r3, [pc, #44] @ (80046b0 ) + 8004684: 699b ldr r3, [r3, #24] + 8004686: 4a0a ldr r2, [pc, #40] @ (80046b0 ) + 8004688: f043 0320 orr.w r3, r3, #32 + 800468c: 6193 str r3, [r2, #24] + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + 800468e: 4b08 ldr r3, [pc, #32] @ (80046b0 ) + 8004690: 22ff movs r2, #255 @ 0xff + 8004692: 625a str r2, [r3, #36] @ 0x24 + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + 8004694: 687b ldr r3, [r7, #4] + 8004696: 2201 movs r2, #1 + 8004698: f883 202d strb.w r2, [r3, #45] @ 0x2d + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + 800469c: 687b ldr r3, [r7, #4] + 800469e: 2200 movs r2, #0 + 80046a0: f883 202c strb.w r2, [r3, #44] @ 0x2c + + return HAL_OK; + 80046a4: 2300 movs r3, #0 +} + 80046a6: 4618 mov r0, r3 + 80046a8: 370c adds r7, #12 + 80046aa: 46bd mov sp, r7 + 80046ac: bc80 pop {r7} + 80046ae: 4770 bx lr + 80046b0: 40002800 .word 0x40002800 + +080046b4 : + * @brief Set SSR Underflow detection with Interrupt. + * @param hrtc RTC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_SetSSRU_IT(RTC_HandleTypeDef *hrtc) +{ + 80046b4: b480 push {r7} + 80046b6: b083 sub sp, #12 + 80046b8: af00 add r7, sp, #0 + 80046ba: 6078 str r0, [r7, #4] + /* Process Locked */ + __HAL_LOCK(hrtc); + 80046bc: 687b ldr r3, [r7, #4] + 80046be: f893 302c ldrb.w r3, [r3, #44] @ 0x2c + 80046c2: 2b01 cmp r3, #1 + 80046c4: d101 bne.n 80046ca + 80046c6: 2302 movs r3, #2 + 80046c8: e027 b.n 800471a + 80046ca: 687b ldr r3, [r7, #4] + 80046cc: 2201 movs r2, #1 + 80046ce: f883 202c strb.w r2, [r3, #44] @ 0x2c + + hrtc->State = HAL_RTC_STATE_BUSY; + 80046d2: 687b ldr r3, [r7, #4] + 80046d4: 2202 movs r2, #2 + 80046d6: f883 202d strb.w r2, [r3, #45] @ 0x2d + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + 80046da: 4b12 ldr r3, [pc, #72] @ (8004724 ) + 80046dc: 22ca movs r2, #202 @ 0xca + 80046de: 625a str r2, [r3, #36] @ 0x24 + 80046e0: 4b10 ldr r3, [pc, #64] @ (8004724 ) + 80046e2: 2253 movs r2, #83 @ 0x53 + 80046e4: 625a str r2, [r3, #36] @ 0x24 + + /* Enable IT SSRU */ + __HAL_RTC_SSRU_ENABLE_IT(hrtc, RTC_IT_SSRU); + 80046e6: 4b0f ldr r3, [pc, #60] @ (8004724 ) + 80046e8: 699b ldr r3, [r3, #24] + 80046ea: 4a0e ldr r2, [pc, #56] @ (8004724 ) + 80046ec: f043 0380 orr.w r3, r3, #128 @ 0x80 + 80046f0: 6193 str r3, [r2, #24] + + /* RTC SSRU Interrupt Configuration: EXTI configuration */ + __HAL_RTC_SSRU_EXTI_ENABLE_IT(); + 80046f2: 4b0d ldr r3, [pc, #52] @ (8004728 ) + 80046f4: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 + 80046f8: 4a0b ldr r2, [pc, #44] @ (8004728 ) + 80046fa: f443 2380 orr.w r3, r3, #262144 @ 0x40000 + 80046fe: f8c2 3080 str.w r3, [r2, #128] @ 0x80 + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + 8004702: 4b08 ldr r3, [pc, #32] @ (8004724 ) + 8004704: 22ff movs r2, #255 @ 0xff + 8004706: 625a str r2, [r3, #36] @ 0x24 + + hrtc->State = HAL_RTC_STATE_READY; + 8004708: 687b ldr r3, [r7, #4] + 800470a: 2201 movs r2, #1 + 800470c: f883 202d strb.w r2, [r3, #45] @ 0x2d + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + 8004710: 687b ldr r3, [r7, #4] + 8004712: 2200 movs r2, #0 + 8004714: f883 202c strb.w r2, [r3, #44] @ 0x2c + + return HAL_OK; + 8004718: 2300 movs r3, #0 +} + 800471a: 4618 mov r0, r3 + 800471c: 370c adds r7, #12 + 800471e: 46bd mov sp, r7 + 8004720: bc80 pop {r7} + 8004722: 4770 bx lr + 8004724: 40002800 .word 0x40002800 + 8004728: 58000800 .word 0x58000800 + +0800472c : + * @brief Handle SSR underflow interrupt request. + * @param hrtc RTC handle + * @retval None + */ +void HAL_RTCEx_SSRUIRQHandler(RTC_HandleTypeDef *hrtc) +{ + 800472c: b580 push {r7, lr} + 800472e: b082 sub sp, #8 + 8004730: af00 add r7, sp, #0 + 8004732: 6078 str r0, [r7, #4] + if ((RTC->MISR & RTC_MISR_SSRUMF) != 0u) + 8004734: 4b09 ldr r3, [pc, #36] @ (800475c ) + 8004736: 6d5b ldr r3, [r3, #84] @ 0x54 + 8004738: f003 0340 and.w r3, r3, #64 @ 0x40 + 800473c: 2b00 cmp r3, #0 + 800473e: d005 beq.n 800474c + { + /* Immediately clear flags */ + RTC->SCR = RTC_SCR_CSSRUF; + 8004740: 4b06 ldr r3, [pc, #24] @ (800475c ) + 8004742: 2240 movs r2, #64 @ 0x40 + 8004744: 65da str r2, [r3, #92] @ 0x5c + /* SSRU callback */ +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + /* Call SSRUEvent registered Callback */ + hrtc->SSRUEventCallback(hrtc); +#else + HAL_RTCEx_SSRUEventCallback(hrtc); + 8004746: 6878 ldr r0, [r7, #4] + 8004748: f7fc fcaf bl 80010aa +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ + } + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + 800474c: 687b ldr r3, [r7, #4] + 800474e: 2201 movs r2, #1 + 8004750: f883 202d strb.w r2, [r3, #45] @ 0x2d +} + 8004754: bf00 nop + 8004756: 3708 adds r7, #8 + 8004758: 46bd mov sp, r7 + 800475a: bd80 pop {r7, pc} + 800475c: 40002800 .word 0x40002800 + +08004760 : + * @brief Alarm B callback. + * @param hrtc RTC handle + * @retval None + */ +__weak void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc) +{ + 8004760: b480 push {r7} + 8004762: b083 sub sp, #12 + 8004764: af00 add r7, sp, #0 + 8004766: 6078 str r0, [r7, #4] + UNUSED(hrtc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_RTCEx_AlarmBEventCallback could be implemented in the user file + */ +} + 8004768: bf00 nop + 800476a: 370c adds r7, #12 + 800476c: 46bd mov sp, r7 + 800476e: bc80 pop {r7} + 8004770: 4770 bx lr + ... + +08004774 : + * This parameter can be RTC_BKP_DRx where x can be from 0 to RTC_BACKUP_NB + * @param Data Data to be written in the specified Backup data register. + * @retval None + */ +void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data) +{ + 8004774: b480 push {r7} + 8004776: b087 sub sp, #28 + 8004778: af00 add r7, sp, #0 + 800477a: 60f8 str r0, [r7, #12] + 800477c: 60b9 str r1, [r7, #8] + 800477e: 607a str r2, [r7, #4] + + UNUSED(hrtc); + /* Check the parameters */ + assert_param(IS_RTC_BKP(BackupRegister)); + + tmp = (uint32_t) &(TAMP->BKP0R); + 8004780: 4b07 ldr r3, [pc, #28] @ (80047a0 ) + 8004782: 617b str r3, [r7, #20] + tmp += (BackupRegister * 4U); + 8004784: 68bb ldr r3, [r7, #8] + 8004786: 009b lsls r3, r3, #2 + 8004788: 697a ldr r2, [r7, #20] + 800478a: 4413 add r3, r2 + 800478c: 617b str r3, [r7, #20] + + /* Write the specified register */ + *(__IO uint32_t *)tmp = (uint32_t)Data; + 800478e: 697b ldr r3, [r7, #20] + 8004790: 687a ldr r2, [r7, #4] + 8004792: 601a str r2, [r3, #0] +} + 8004794: bf00 nop + 8004796: 371c adds r7, #28 + 8004798: 46bd mov sp, r7 + 800479a: bc80 pop {r7} + 800479c: 4770 bx lr + 800479e: bf00 nop + 80047a0: 4000b100 .word 0x4000b100 + +080047a4 : + * @param BackupRegister RTC Backup data Register number. + * This parameter can be RTC_BKP_DRx where x can be from 0 to RTC_BACKUP_NB + * @retval Read value + */ +uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister) +{ + 80047a4: b480 push {r7} + 80047a6: b085 sub sp, #20 + 80047a8: af00 add r7, sp, #0 + 80047aa: 6078 str r0, [r7, #4] + 80047ac: 6039 str r1, [r7, #0] + + UNUSED(hrtc); + /* Check the parameters */ + assert_param(IS_RTC_BKP(BackupRegister)); + + tmp = (uint32_t) &(TAMP->BKP0R); + 80047ae: 4b07 ldr r3, [pc, #28] @ (80047cc ) + 80047b0: 60fb str r3, [r7, #12] + tmp += (BackupRegister * 4U); + 80047b2: 683b ldr r3, [r7, #0] + 80047b4: 009b lsls r3, r3, #2 + 80047b6: 68fa ldr r2, [r7, #12] + 80047b8: 4413 add r3, r2 + 80047ba: 60fb str r3, [r7, #12] + + /* Read the specified register */ + return (*(__IO uint32_t *)tmp); + 80047bc: 68fb ldr r3, [r7, #12] + 80047be: 681b ldr r3, [r3, #0] +} + 80047c0: 4618 mov r0, r3 + 80047c2: 3714 adds r7, #20 + 80047c4: 46bd mov sp, r7 + 80047c6: bc80 pop {r7} + 80047c8: 4770 bx lr + 80047ca: bf00 nop + 80047cc: 4000b100 .word 0x4000b100 + +080047d0 : +{ + 80047d0: b480 push {r7} + 80047d2: b083 sub sp, #12 + 80047d4: af00 add r7, sp, #0 + 80047d6: 6078 str r0, [r7, #4] + MODIFY_REG(PWR->CR3, PWR_CR3_EWRFBUSY, RadioBusyTrigger); + 80047d8: 4b06 ldr r3, [pc, #24] @ (80047f4 ) + 80047da: 689b ldr r3, [r3, #8] + 80047dc: f423 6200 bic.w r2, r3, #2048 @ 0x800 + 80047e0: 4904 ldr r1, [pc, #16] @ (80047f4 ) + 80047e2: 687b ldr r3, [r7, #4] + 80047e4: 4313 orrs r3, r2 + 80047e6: 608b str r3, [r1, #8] +} + 80047e8: bf00 nop + 80047ea: 370c adds r7, #12 + 80047ec: 46bd mov sp, r7 + 80047ee: bc80 pop {r7} + 80047f0: 4770 bx lr + 80047f2: bf00 nop + 80047f4: 58000400 .word 0x58000400 + +080047f8 : +{ + 80047f8: b480 push {r7} + 80047fa: af00 add r7, sp, #0 + SET_BIT(PWR->SUBGHZSPICR, PWR_SUBGHZSPICR_NSS); + 80047fc: 4b05 ldr r3, [pc, #20] @ (8004814 ) + 80047fe: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 8004802: 4a04 ldr r2, [pc, #16] @ (8004814 ) + 8004804: f443 4300 orr.w r3, r3, #32768 @ 0x8000 + 8004808: f8c2 3090 str.w r3, [r2, #144] @ 0x90 +} + 800480c: bf00 nop + 800480e: 46bd mov sp, r7 + 8004810: bc80 pop {r7} + 8004812: 4770 bx lr + 8004814: 58000400 .word 0x58000400 + +08004818 : +{ + 8004818: b480 push {r7} + 800481a: af00 add r7, sp, #0 + CLEAR_BIT(PWR->SUBGHZSPICR, PWR_SUBGHZSPICR_NSS); + 800481c: 4b05 ldr r3, [pc, #20] @ (8004834 ) + 800481e: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 8004822: 4a04 ldr r2, [pc, #16] @ (8004834 ) + 8004824: f423 4300 bic.w r3, r3, #32768 @ 0x8000 + 8004828: f8c2 3090 str.w r3, [r2, #144] @ 0x90 +} + 800482c: bf00 nop + 800482e: 46bd mov sp, r7 + 8004830: bc80 pop {r7} + 8004832: 4770 bx lr + 8004834: 58000400 .word 0x58000400 + +08004838 : +{ + 8004838: b480 push {r7} + 800483a: af00 add r7, sp, #0 + WRITE_REG(PWR->SCR, PWR_SCR_CWRFBUSYF); + 800483c: 4b03 ldr r3, [pc, #12] @ (800484c ) + 800483e: f44f 6200 mov.w r2, #2048 @ 0x800 + 8004842: 619a str r2, [r3, #24] +} + 8004844: bf00 nop + 8004846: 46bd mov sp, r7 + 8004848: bc80 pop {r7} + 800484a: 4770 bx lr + 800484c: 58000400 .word 0x58000400 + +08004850 : +{ + 8004850: b480 push {r7} + 8004852: af00 add r7, sp, #0 + return ((READ_BIT(PWR->SR2, PWR_SR2_RFBUSYS) == (PWR_SR2_RFBUSYS)) ? 1UL : 0UL); + 8004854: 4b06 ldr r3, [pc, #24] @ (8004870 ) + 8004856: 695b ldr r3, [r3, #20] + 8004858: f003 0302 and.w r3, r3, #2 + 800485c: 2b02 cmp r3, #2 + 800485e: d101 bne.n 8004864 + 8004860: 2301 movs r3, #1 + 8004862: e000 b.n 8004866 + 8004864: 2300 movs r3, #0 +} + 8004866: 4618 mov r0, r3 + 8004868: 46bd mov sp, r7 + 800486a: bc80 pop {r7} + 800486c: 4770 bx lr + 800486e: bf00 nop + 8004870: 58000400 .word 0x58000400 + +08004874 : +{ + 8004874: b480 push {r7} + 8004876: af00 add r7, sp, #0 + return ((READ_BIT(PWR->SR2, PWR_SR2_RFBUSYMS) == (PWR_SR2_RFBUSYMS)) ? 1UL : 0UL); + 8004878: 4b06 ldr r3, [pc, #24] @ (8004894 ) + 800487a: 695b ldr r3, [r3, #20] + 800487c: f003 0304 and.w r3, r3, #4 + 8004880: 2b04 cmp r3, #4 + 8004882: d101 bne.n 8004888 + 8004884: 2301 movs r3, #1 + 8004886: e000 b.n 800488a + 8004888: 2300 movs r3, #0 +} + 800488a: 4618 mov r0, r3 + 800488c: 46bd mov sp, r7 + 800488e: bc80 pop {r7} + 8004890: 4770 bx lr + 8004892: bf00 nop + 8004894: 58000400 .word 0x58000400 + +08004898 : +{ + 8004898: b480 push {r7} + 800489a: af00 add r7, sp, #0 + CLEAR_BIT(RCC->CSR, RCC_CSR_RFRST); + 800489c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 80048a0: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 + 80048a4: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 80048a8: f423 4300 bic.w r3, r3, #32768 @ 0x8000 + 80048ac: f8c2 3094 str.w r3, [r2, #148] @ 0x94 +} + 80048b0: bf00 nop + 80048b2: 46bd mov sp, r7 + 80048b4: bc80 pop {r7} + 80048b6: 4770 bx lr + +080048b8 : +{ + 80048b8: b480 push {r7} + 80048ba: af00 add r7, sp, #0 + return ((READ_BIT(RCC->CSR, RCC_CSR_RFRSTF) == (RCC_CSR_RFRSTF)) ? 1UL : 0UL); + 80048bc: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 80048c0: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 + 80048c4: f403 4380 and.w r3, r3, #16384 @ 0x4000 + 80048c8: f5b3 4f80 cmp.w r3, #16384 @ 0x4000 + 80048cc: d101 bne.n 80048d2 + 80048ce: 2301 movs r3, #1 + 80048d0: e000 b.n 80048d4 + 80048d2: 2300 movs r3, #0 +} + 80048d4: 4618 mov r0, r3 + 80048d6: 46bd mov sp, r7 + 80048d8: bc80 pop {r7} + 80048da: 4770 bx lr + +080048dc : +{ + 80048dc: b480 push {r7} + 80048de: b083 sub sp, #12 + 80048e0: af00 add r7, sp, #0 + 80048e2: 6078 str r0, [r7, #4] + SET_BIT(EXTI->IMR2, ExtiLine); + 80048e4: 4b06 ldr r3, [pc, #24] @ (8004900 ) + 80048e6: f8d3 2090 ldr.w r2, [r3, #144] @ 0x90 + 80048ea: 4905 ldr r1, [pc, #20] @ (8004900 ) + 80048ec: 687b ldr r3, [r7, #4] + 80048ee: 4313 orrs r3, r2 + 80048f0: f8c1 3090 str.w r3, [r1, #144] @ 0x90 +} + 80048f4: bf00 nop + 80048f6: 370c adds r7, #12 + 80048f8: 46bd mov sp, r7 + 80048fa: bc80 pop {r7} + 80048fc: 4770 bx lr + 80048fe: bf00 nop + 8004900: 58000800 .word 0x58000800 + +08004904 : + * set the state to HAL_SUBGHZ_STATE_RESET_RF_READY with __HAL_SUBGHZ_RESET_HANDLE_STATE_RF_READY + * to avoid the reset of Radio peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SUBGHZ_Init(SUBGHZ_HandleTypeDef *hsubghz) +{ + 8004904: b580 push {r7, lr} + 8004906: b084 sub sp, #16 + 8004908: af00 add r7, sp, #0 + 800490a: 6078 str r0, [r7, #4] + HAL_StatusTypeDef status; + __IO uint32_t count; + HAL_SUBGHZ_StateTypeDef subghz_state; + + /* Check the hsubghz handle allocation */ + if (hsubghz == NULL) + 800490c: 687b ldr r3, [r7, #4] + 800490e: 2b00 cmp r3, #0 + 8004910: d103 bne.n 800491a + { + status = HAL_ERROR; + 8004912: 2301 movs r3, #1 + 8004914: 73fb strb r3, [r7, #15] + return status; + 8004916: 7bfb ldrb r3, [r7, #15] + 8004918: e052 b.n 80049c0 + } + else + { + status = HAL_OK; + 800491a: 2300 movs r3, #0 + 800491c: 73fb strb r3, [r7, #15] + } + + assert_param(IS_SUBGHZSPI_BAUDRATE_PRESCALER(hsubghz->Init.BaudratePrescaler)); + + subghz_state = hsubghz->State; + 800491e: 687b ldr r3, [r7, #4] + 8004920: 799b ldrb r3, [r3, #6] + 8004922: 73bb strb r3, [r7, #14] + if ((subghz_state == HAL_SUBGHZ_STATE_RESET) || + 8004924: 7bbb ldrb r3, [r7, #14] + 8004926: 2b00 cmp r3, #0 + 8004928: d002 beq.n 8004930 + 800492a: 7bbb ldrb r3, [r7, #14] + 800492c: 2b03 cmp r3, #3 + 800492e: d109 bne.n 8004944 + (subghz_state == HAL_SUBGHZ_STATE_RESET_RF_READY)) + { + /* Allocate lock resource and initialize it */ + hsubghz->Lock = HAL_UNLOCKED; + 8004930: 687b ldr r3, [r7, #4] + 8004932: 2200 movs r2, #0 + 8004934: 715a strb r2, [r3, #5] + + /* Init the low level hardware : GPIO, CLOCK, NVIC... */ + hsubghz->MspInitCallback(hsubghz); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC... */ + HAL_SUBGHZ_MspInit(hsubghz); + 8004936: 6878 ldr r0, [r7, #4] + 8004938: f7fc f8e6 bl 8000b08 +#if defined(CORE_CM0PLUS) + /* Enable EXTI 44 : Radio IRQ ITs for CPU2 */ + LL_C2_EXTI_EnableIT_32_63(LL_EXTI_LINE_44); +#else + /* Enable EXTI 44 : Radio IRQ ITs for CPU1 */ + LL_EXTI_EnableIT_32_63(LL_EXTI_LINE_44); + 800493c: f44f 5080 mov.w r0, #4096 @ 0x1000 + 8004940: f7ff ffcc bl 80048dc +#endif /* CORE_CM0PLUS */ + } + + if (subghz_state == HAL_SUBGHZ_STATE_RESET) + 8004944: 7bbb ldrb r3, [r7, #14] + 8004946: 2b00 cmp r3, #0 + 8004948: d126 bne.n 8004998 + { + /* Reinitialize Radio peripheral only if SUBGHZ is in full RESET state */ + hsubghz->State = HAL_SUBGHZ_STATE_BUSY; + 800494a: 687b ldr r3, [r7, #4] + 800494c: 2202 movs r2, #2 + 800494e: 719a strb r2, [r3, #6] + + /* De-asserts the reset signal of the Radio peripheral */ + LL_RCC_RF_DisableReset(); + 8004950: f7ff ffa2 bl 8004898 + + /* Verify that Radio in reset status flag is set */ + count = SUBGHZ_DEFAULT_TIMEOUT * SUBGHZ_DEFAULT_LOOP_TIME; + 8004954: 4b1c ldr r3, [pc, #112] @ (80049c8 ) + 8004956: 681a ldr r2, [r3, #0] + 8004958: 4613 mov r3, r2 + 800495a: 00db lsls r3, r3, #3 + 800495c: 1a9b subs r3, r3, r2 + 800495e: 009b lsls r3, r3, #2 + 8004960: 0cdb lsrs r3, r3, #19 + 8004962: 2264 movs r2, #100 @ 0x64 + 8004964: fb02 f303 mul.w r3, r2, r3 + 8004968: 60bb str r3, [r7, #8] + + do + { + if (count == 0U) + 800496a: 68bb ldr r3, [r7, #8] + 800496c: 2b00 cmp r3, #0 + 800496e: d105 bne.n 800497c + { + status = HAL_ERROR; + 8004970: 2301 movs r3, #1 + 8004972: 73fb strb r3, [r7, #15] + hsubghz->ErrorCode = HAL_SUBGHZ_ERROR_TIMEOUT; + 8004974: 687b ldr r3, [r7, #4] + 8004976: 2201 movs r2, #1 + 8004978: 609a str r2, [r3, #8] + break; + 800497a: e007 b.n 800498c + } + count--; + 800497c: 68bb ldr r3, [r7, #8] + 800497e: 3b01 subs r3, #1 + 8004980: 60bb str r3, [r7, #8] + } while (LL_RCC_IsRFUnderReset() != 0UL); + 8004982: f7ff ff99 bl 80048b8 + 8004986: 4603 mov r3, r0 + 8004988: 2b00 cmp r3, #0 + 800498a: d1ee bne.n 800496a + + /* Asserts the reset signal of the Radio peripheral */ + LL_PWR_UnselectSUBGHZSPI_NSS(); + 800498c: f7ff ff34 bl 80047f8 +#if defined(CORE_CM0PLUS) + /* Enable wakeup signal of the Radio peripheral */ + LL_C2_PWR_SetRadioBusyTrigger(LL_PWR_RADIO_BUSY_TRIGGER_WU_IT); +#else + /* Enable wakeup signal of the Radio peripheral */ + LL_PWR_SetRadioBusyTrigger(LL_PWR_RADIO_BUSY_TRIGGER_WU_IT); + 8004990: f44f 6000 mov.w r0, #2048 @ 0x800 + 8004994: f7ff ff1c bl 80047d0 +#endif /* CORE_CM0PLUS */ + } + + /* Clear Pending Flag */ + LL_PWR_ClearFlag_RFBUSY(); + 8004998: f7ff ff4e bl 8004838 + + if (status == HAL_OK) + 800499c: 7bfb ldrb r3, [r7, #15] + 800499e: 2b00 cmp r3, #0 + 80049a0: d10a bne.n 80049b8 + { + /* Initialize SUBGHZSPI Peripheral */ + SUBGHZSPI_Init(hsubghz->Init.BaudratePrescaler); + 80049a2: 687b ldr r3, [r7, #4] + 80049a4: 681b ldr r3, [r3, #0] + 80049a6: 4618 mov r0, r3 + 80049a8: f000 fac2 bl 8004f30 + + hsubghz->DeepSleep = SUBGHZ_DEEP_SLEEP_ENABLE; + 80049ac: 687b ldr r3, [r7, #4] + 80049ae: 2201 movs r2, #1 + 80049b0: 711a strb r2, [r3, #4] + hsubghz->ErrorCode = HAL_SUBGHZ_ERROR_NONE; + 80049b2: 687b ldr r3, [r7, #4] + 80049b4: 2200 movs r2, #0 + 80049b6: 609a str r2, [r3, #8] + } + + hsubghz->State = HAL_SUBGHZ_STATE_READY; + 80049b8: 687b ldr r3, [r7, #4] + 80049ba: 2201 movs r2, #1 + 80049bc: 719a strb r2, [r3, #6] + + return status; + 80049be: 7bfb ldrb r3, [r7, #15] +} + 80049c0: 4618 mov r0, r3 + 80049c2: 3710 adds r7, #16 + 80049c4: 46bd mov sp, r7 + 80049c6: bd80 pop {r7, pc} + 80049c8: 20000000 .word 0x20000000 + +080049cc : + */ +HAL_StatusTypeDef HAL_SUBGHZ_WriteRegisters(SUBGHZ_HandleTypeDef *hsubghz, + uint16_t Address, + uint8_t *pBuffer, + uint16_t Size) +{ + 80049cc: b580 push {r7, lr} + 80049ce: b086 sub sp, #24 + 80049d0: af00 add r7, sp, #0 + 80049d2: 60f8 str r0, [r7, #12] + 80049d4: 607a str r2, [r7, #4] + 80049d6: 461a mov r2, r3 + 80049d8: 460b mov r3, r1 + 80049da: 817b strh r3, [r7, #10] + 80049dc: 4613 mov r3, r2 + 80049de: 813b strh r3, [r7, #8] + HAL_StatusTypeDef status; + + if (hsubghz->State == HAL_SUBGHZ_STATE_READY) + 80049e0: 68fb ldr r3, [r7, #12] + 80049e2: 799b ldrb r3, [r3, #6] + 80049e4: b2db uxtb r3, r3 + 80049e6: 2b01 cmp r3, #1 + 80049e8: d14a bne.n 8004a80 + { + /* Process Locked */ + __HAL_LOCK(hsubghz); + 80049ea: 68fb ldr r3, [r7, #12] + 80049ec: 795b ldrb r3, [r3, #5] + 80049ee: 2b01 cmp r3, #1 + 80049f0: d101 bne.n 80049f6 + 80049f2: 2302 movs r3, #2 + 80049f4: e045 b.n 8004a82 + 80049f6: 68fb ldr r3, [r7, #12] + 80049f8: 2201 movs r2, #1 + 80049fa: 715a strb r2, [r3, #5] + + hsubghz->State = HAL_SUBGHZ_STATE_BUSY; + 80049fc: 68fb ldr r3, [r7, #12] + 80049fe: 2202 movs r2, #2 + 8004a00: 719a strb r2, [r3, #6] + + (void)SUBGHZ_CheckDeviceReady(hsubghz); + 8004a02: 68f8 ldr r0, [r7, #12] + 8004a04: f000 fb62 bl 80050cc + + /* NSS = 0 */ + LL_PWR_SelectSUBGHZSPI_NSS(); + 8004a08: f7ff ff06 bl 8004818 + + (void)SUBGHZSPI_Transmit(hsubghz, SUBGHZ_RADIO_WRITE_REGISTER); + 8004a0c: 210d movs r1, #13 + 8004a0e: 68f8 ldr r0, [r7, #12] + 8004a10: f000 faae bl 8004f70 + (void)SUBGHZSPI_Transmit(hsubghz, (uint8_t)((Address & 0xFF00U) >> 8U)); + 8004a14: 897b ldrh r3, [r7, #10] + 8004a16: 0a1b lsrs r3, r3, #8 + 8004a18: b29b uxth r3, r3 + 8004a1a: b2db uxtb r3, r3 + 8004a1c: 4619 mov r1, r3 + 8004a1e: 68f8 ldr r0, [r7, #12] + 8004a20: f000 faa6 bl 8004f70 + (void)SUBGHZSPI_Transmit(hsubghz, (uint8_t)(Address & 0x00FFU)); + 8004a24: 897b ldrh r3, [r7, #10] + 8004a26: b2db uxtb r3, r3 + 8004a28: 4619 mov r1, r3 + 8004a2a: 68f8 ldr r0, [r7, #12] + 8004a2c: f000 faa0 bl 8004f70 + + for (uint16_t i = 0U; i < Size; i++) + 8004a30: 2300 movs r3, #0 + 8004a32: 82bb strh r3, [r7, #20] + 8004a34: e00a b.n 8004a4c + { + (void)SUBGHZSPI_Transmit(hsubghz, pBuffer[i]); + 8004a36: 8abb ldrh r3, [r7, #20] + 8004a38: 687a ldr r2, [r7, #4] + 8004a3a: 4413 add r3, r2 + 8004a3c: 781b ldrb r3, [r3, #0] + 8004a3e: 4619 mov r1, r3 + 8004a40: 68f8 ldr r0, [r7, #12] + 8004a42: f000 fa95 bl 8004f70 + for (uint16_t i = 0U; i < Size; i++) + 8004a46: 8abb ldrh r3, [r7, #20] + 8004a48: 3301 adds r3, #1 + 8004a4a: 82bb strh r3, [r7, #20] + 8004a4c: 8aba ldrh r2, [r7, #20] + 8004a4e: 893b ldrh r3, [r7, #8] + 8004a50: 429a cmp r2, r3 + 8004a52: d3f0 bcc.n 8004a36 + } + + /* NSS = 1 */ + LL_PWR_UnselectSUBGHZSPI_NSS(); + 8004a54: f7ff fed0 bl 80047f8 + + (void)SUBGHZ_WaitOnBusy(hsubghz); + 8004a58: 68f8 ldr r0, [r7, #12] + 8004a5a: f000 fb57 bl 800510c + + if (hsubghz->ErrorCode != HAL_SUBGHZ_ERROR_NONE) + 8004a5e: 68fb ldr r3, [r7, #12] + 8004a60: 689b ldr r3, [r3, #8] + 8004a62: 2b00 cmp r3, #0 + 8004a64: d002 beq.n 8004a6c + { + status = HAL_ERROR; + 8004a66: 2301 movs r3, #1 + 8004a68: 75fb strb r3, [r7, #23] + 8004a6a: e001 b.n 8004a70 + } + else + { + status = HAL_OK; + 8004a6c: 2300 movs r3, #0 + 8004a6e: 75fb strb r3, [r7, #23] + } + + hsubghz->State = HAL_SUBGHZ_STATE_READY; + 8004a70: 68fb ldr r3, [r7, #12] + 8004a72: 2201 movs r2, #1 + 8004a74: 719a strb r2, [r3, #6] + + /* Process Unlocked */ + __HAL_UNLOCK(hsubghz); + 8004a76: 68fb ldr r3, [r7, #12] + 8004a78: 2200 movs r2, #0 + 8004a7a: 715a strb r2, [r3, #5] + + return status; + 8004a7c: 7dfb ldrb r3, [r7, #23] + 8004a7e: e000 b.n 8004a82 + } + else + { + return HAL_BUSY; + 8004a80: 2302 movs r3, #2 + } +} + 8004a82: 4618 mov r0, r3 + 8004a84: 3718 adds r7, #24 + 8004a86: 46bd mov sp, r7 + 8004a88: bd80 pop {r7, pc} + +08004a8a : + */ +HAL_StatusTypeDef HAL_SUBGHZ_ReadRegisters(SUBGHZ_HandleTypeDef *hsubghz, + uint16_t Address, + uint8_t *pBuffer, + uint16_t Size) +{ + 8004a8a: b580 push {r7, lr} + 8004a8c: b088 sub sp, #32 + 8004a8e: af00 add r7, sp, #0 + 8004a90: 60f8 str r0, [r7, #12] + 8004a92: 607a str r2, [r7, #4] + 8004a94: 461a mov r2, r3 + 8004a96: 460b mov r3, r1 + 8004a98: 817b strh r3, [r7, #10] + 8004a9a: 4613 mov r3, r2 + 8004a9c: 813b strh r3, [r7, #8] + HAL_StatusTypeDef status; + uint8_t *pData = pBuffer; + 8004a9e: 687b ldr r3, [r7, #4] + 8004aa0: 61bb str r3, [r7, #24] + + if (hsubghz->State == HAL_SUBGHZ_STATE_READY) + 8004aa2: 68fb ldr r3, [r7, #12] + 8004aa4: 799b ldrb r3, [r3, #6] + 8004aa6: b2db uxtb r3, r3 + 8004aa8: 2b01 cmp r3, #1 + 8004aaa: d14a bne.n 8004b42 + { + /* Process Locked */ + __HAL_LOCK(hsubghz); + 8004aac: 68fb ldr r3, [r7, #12] + 8004aae: 795b ldrb r3, [r3, #5] + 8004ab0: 2b01 cmp r3, #1 + 8004ab2: d101 bne.n 8004ab8 + 8004ab4: 2302 movs r3, #2 + 8004ab6: e045 b.n 8004b44 + 8004ab8: 68fb ldr r3, [r7, #12] + 8004aba: 2201 movs r2, #1 + 8004abc: 715a strb r2, [r3, #5] + + (void)SUBGHZ_CheckDeviceReady(hsubghz); + 8004abe: 68f8 ldr r0, [r7, #12] + 8004ac0: f000 fb04 bl 80050cc + + /* NSS = 0 */ + LL_PWR_SelectSUBGHZSPI_NSS(); + 8004ac4: f7ff fea8 bl 8004818 + + (void)SUBGHZSPI_Transmit(hsubghz, SUBGHZ_RADIO_READ_REGISTER); + 8004ac8: 211d movs r1, #29 + 8004aca: 68f8 ldr r0, [r7, #12] + 8004acc: f000 fa50 bl 8004f70 + (void)SUBGHZSPI_Transmit(hsubghz, (uint8_t)((Address & 0xFF00U) >> 8U)); + 8004ad0: 897b ldrh r3, [r7, #10] + 8004ad2: 0a1b lsrs r3, r3, #8 + 8004ad4: b29b uxth r3, r3 + 8004ad6: b2db uxtb r3, r3 + 8004ad8: 4619 mov r1, r3 + 8004ada: 68f8 ldr r0, [r7, #12] + 8004adc: f000 fa48 bl 8004f70 + (void)SUBGHZSPI_Transmit(hsubghz, (uint8_t)(Address & 0x00FFU)); + 8004ae0: 897b ldrh r3, [r7, #10] + 8004ae2: b2db uxtb r3, r3 + 8004ae4: 4619 mov r1, r3 + 8004ae6: 68f8 ldr r0, [r7, #12] + 8004ae8: f000 fa42 bl 8004f70 + (void)SUBGHZSPI_Transmit(hsubghz, 0U); + 8004aec: 2100 movs r1, #0 + 8004aee: 68f8 ldr r0, [r7, #12] + 8004af0: f000 fa3e bl 8004f70 + + for (uint16_t i = 0U; i < Size; i++) + 8004af4: 2300 movs r3, #0 + 8004af6: 82fb strh r3, [r7, #22] + 8004af8: e009 b.n 8004b0e + { + (void)SUBGHZSPI_Receive(hsubghz, (pData)); + 8004afa: 69b9 ldr r1, [r7, #24] + 8004afc: 68f8 ldr r0, [r7, #12] + 8004afe: f000 fa8d bl 800501c + pData++; + 8004b02: 69bb ldr r3, [r7, #24] + 8004b04: 3301 adds r3, #1 + 8004b06: 61bb str r3, [r7, #24] + for (uint16_t i = 0U; i < Size; i++) + 8004b08: 8afb ldrh r3, [r7, #22] + 8004b0a: 3301 adds r3, #1 + 8004b0c: 82fb strh r3, [r7, #22] + 8004b0e: 8afa ldrh r2, [r7, #22] + 8004b10: 893b ldrh r3, [r7, #8] + 8004b12: 429a cmp r2, r3 + 8004b14: d3f1 bcc.n 8004afa + } + + /* NSS = 1 */ + LL_PWR_UnselectSUBGHZSPI_NSS(); + 8004b16: f7ff fe6f bl 80047f8 + + (void)SUBGHZ_WaitOnBusy(hsubghz); + 8004b1a: 68f8 ldr r0, [r7, #12] + 8004b1c: f000 faf6 bl 800510c + + if (hsubghz->ErrorCode != HAL_SUBGHZ_ERROR_NONE) + 8004b20: 68fb ldr r3, [r7, #12] + 8004b22: 689b ldr r3, [r3, #8] + 8004b24: 2b00 cmp r3, #0 + 8004b26: d002 beq.n 8004b2e + { + status = HAL_ERROR; + 8004b28: 2301 movs r3, #1 + 8004b2a: 77fb strb r3, [r7, #31] + 8004b2c: e001 b.n 8004b32 + } + else + { + status = HAL_OK; + 8004b2e: 2300 movs r3, #0 + 8004b30: 77fb strb r3, [r7, #31] + } + + hsubghz->State = HAL_SUBGHZ_STATE_READY; + 8004b32: 68fb ldr r3, [r7, #12] + 8004b34: 2201 movs r2, #1 + 8004b36: 719a strb r2, [r3, #6] + + /* Process Unlocked */ + __HAL_UNLOCK(hsubghz); + 8004b38: 68fb ldr r3, [r7, #12] + 8004b3a: 2200 movs r2, #0 + 8004b3c: 715a strb r2, [r3, #5] + + return status; + 8004b3e: 7ffb ldrb r3, [r7, #31] + 8004b40: e000 b.n 8004b44 + } + else + { + return HAL_BUSY; + 8004b42: 2302 movs r3, #2 + } +} + 8004b44: 4618 mov r0, r3 + 8004b46: 3720 adds r7, #32 + 8004b48: 46bd mov sp, r7 + 8004b4a: bd80 pop {r7, pc} + +08004b4c : + */ +HAL_StatusTypeDef HAL_SUBGHZ_ExecSetCmd(SUBGHZ_HandleTypeDef *hsubghz, + SUBGHZ_RadioSetCmd_t Command, + uint8_t *pBuffer, + uint16_t Size) +{ + 8004b4c: b580 push {r7, lr} + 8004b4e: b086 sub sp, #24 + 8004b50: af00 add r7, sp, #0 + 8004b52: 60f8 str r0, [r7, #12] + 8004b54: 607a str r2, [r7, #4] + 8004b56: 461a mov r2, r3 + 8004b58: 460b mov r3, r1 + 8004b5a: 72fb strb r3, [r7, #11] + 8004b5c: 4613 mov r3, r2 + 8004b5e: 813b strh r3, [r7, #8] + HAL_StatusTypeDef status; + + /* LORA Modulation not available on STM32WLx4xx devices */ + assert_param(IS_SUBGHZ_MODULATION_SUPPORTED(Command, pBuffer[0U])); + + if (hsubghz->State == HAL_SUBGHZ_STATE_READY) + 8004b60: 68fb ldr r3, [r7, #12] + 8004b62: 799b ldrb r3, [r3, #6] + 8004b64: b2db uxtb r3, r3 + 8004b66: 2b01 cmp r3, #1 + 8004b68: d14a bne.n 8004c00 + { + /* Process Locked */ + __HAL_LOCK(hsubghz); + 8004b6a: 68fb ldr r3, [r7, #12] + 8004b6c: 795b ldrb r3, [r3, #5] + 8004b6e: 2b01 cmp r3, #1 + 8004b70: d101 bne.n 8004b76 + 8004b72: 2302 movs r3, #2 + 8004b74: e045 b.n 8004c02 + 8004b76: 68fb ldr r3, [r7, #12] + 8004b78: 2201 movs r2, #1 + 8004b7a: 715a strb r2, [r3, #5] + + /* Need to wakeup Radio if already in Sleep at startup */ + (void)SUBGHZ_CheckDeviceReady(hsubghz); + 8004b7c: 68f8 ldr r0, [r7, #12] + 8004b7e: f000 faa5 bl 80050cc + + if ((Command == RADIO_SET_SLEEP) || (Command == RADIO_SET_RXDUTYCYCLE)) + 8004b82: 7afb ldrb r3, [r7, #11] + 8004b84: 2b84 cmp r3, #132 @ 0x84 + 8004b86: d002 beq.n 8004b8e + 8004b88: 7afb ldrb r3, [r7, #11] + 8004b8a: 2b94 cmp r3, #148 @ 0x94 + 8004b8c: d103 bne.n 8004b96 + { + hsubghz->DeepSleep = SUBGHZ_DEEP_SLEEP_ENABLE; + 8004b8e: 68fb ldr r3, [r7, #12] + 8004b90: 2201 movs r2, #1 + 8004b92: 711a strb r2, [r3, #4] + 8004b94: e002 b.n 8004b9c + } + else + { + hsubghz->DeepSleep = SUBGHZ_DEEP_SLEEP_DISABLE; + 8004b96: 68fb ldr r3, [r7, #12] + 8004b98: 2200 movs r2, #0 + 8004b9a: 711a strb r2, [r3, #4] + } + + /* NSS = 0 */ + LL_PWR_SelectSUBGHZSPI_NSS(); + 8004b9c: f7ff fe3c bl 8004818 + + (void)SUBGHZSPI_Transmit(hsubghz, (uint8_t)Command); + 8004ba0: 7afb ldrb r3, [r7, #11] + 8004ba2: 4619 mov r1, r3 + 8004ba4: 68f8 ldr r0, [r7, #12] + 8004ba6: f000 f9e3 bl 8004f70 + + for (uint16_t i = 0U; i < Size; i++) + 8004baa: 2300 movs r3, #0 + 8004bac: 82bb strh r3, [r7, #20] + 8004bae: e00a b.n 8004bc6 + { + (void)SUBGHZSPI_Transmit(hsubghz, pBuffer[i]); + 8004bb0: 8abb ldrh r3, [r7, #20] + 8004bb2: 687a ldr r2, [r7, #4] + 8004bb4: 4413 add r3, r2 + 8004bb6: 781b ldrb r3, [r3, #0] + 8004bb8: 4619 mov r1, r3 + 8004bba: 68f8 ldr r0, [r7, #12] + 8004bbc: f000 f9d8 bl 8004f70 + for (uint16_t i = 0U; i < Size; i++) + 8004bc0: 8abb ldrh r3, [r7, #20] + 8004bc2: 3301 adds r3, #1 + 8004bc4: 82bb strh r3, [r7, #20] + 8004bc6: 8aba ldrh r2, [r7, #20] + 8004bc8: 893b ldrh r3, [r7, #8] + 8004bca: 429a cmp r2, r3 + 8004bcc: d3f0 bcc.n 8004bb0 + } + + /* NSS = 1 */ + LL_PWR_UnselectSUBGHZSPI_NSS(); + 8004bce: f7ff fe13 bl 80047f8 + + if (Command != RADIO_SET_SLEEP) + 8004bd2: 7afb ldrb r3, [r7, #11] + 8004bd4: 2b84 cmp r3, #132 @ 0x84 + 8004bd6: d002 beq.n 8004bde + { + (void)SUBGHZ_WaitOnBusy(hsubghz); + 8004bd8: 68f8 ldr r0, [r7, #12] + 8004bda: f000 fa97 bl 800510c + } + + if (hsubghz->ErrorCode != HAL_SUBGHZ_ERROR_NONE) + 8004bde: 68fb ldr r3, [r7, #12] + 8004be0: 689b ldr r3, [r3, #8] + 8004be2: 2b00 cmp r3, #0 + 8004be4: d002 beq.n 8004bec + { + status = HAL_ERROR; + 8004be6: 2301 movs r3, #1 + 8004be8: 75fb strb r3, [r7, #23] + 8004bea: e001 b.n 8004bf0 + } + else + { + status = HAL_OK; + 8004bec: 2300 movs r3, #0 + 8004bee: 75fb strb r3, [r7, #23] + } + + hsubghz->State = HAL_SUBGHZ_STATE_READY; + 8004bf0: 68fb ldr r3, [r7, #12] + 8004bf2: 2201 movs r2, #1 + 8004bf4: 719a strb r2, [r3, #6] + + /* Process Unlocked */ + __HAL_UNLOCK(hsubghz); + 8004bf6: 68fb ldr r3, [r7, #12] + 8004bf8: 2200 movs r2, #0 + 8004bfa: 715a strb r2, [r3, #5] + + return status; + 8004bfc: 7dfb ldrb r3, [r7, #23] + 8004bfe: e000 b.n 8004c02 + } + else + { + return HAL_BUSY; + 8004c00: 2302 movs r3, #2 + } +} + 8004c02: 4618 mov r0, r3 + 8004c04: 3718 adds r7, #24 + 8004c06: 46bd mov sp, r7 + 8004c08: bd80 pop {r7, pc} + +08004c0a : + */ +HAL_StatusTypeDef HAL_SUBGHZ_ExecGetCmd(SUBGHZ_HandleTypeDef *hsubghz, + SUBGHZ_RadioGetCmd_t Command, + uint8_t *pBuffer, + uint16_t Size) +{ + 8004c0a: b580 push {r7, lr} + 8004c0c: b088 sub sp, #32 + 8004c0e: af00 add r7, sp, #0 + 8004c10: 60f8 str r0, [r7, #12] + 8004c12: 607a str r2, [r7, #4] + 8004c14: 461a mov r2, r3 + 8004c16: 460b mov r3, r1 + 8004c18: 72fb strb r3, [r7, #11] + 8004c1a: 4613 mov r3, r2 + 8004c1c: 813b strh r3, [r7, #8] + HAL_StatusTypeDef status; + uint8_t *pData = pBuffer; + 8004c1e: 687b ldr r3, [r7, #4] + 8004c20: 61bb str r3, [r7, #24] + + if (hsubghz->State == HAL_SUBGHZ_STATE_READY) + 8004c22: 68fb ldr r3, [r7, #12] + 8004c24: 799b ldrb r3, [r3, #6] + 8004c26: b2db uxtb r3, r3 + 8004c28: 2b01 cmp r3, #1 + 8004c2a: d13d bne.n 8004ca8 + { + /* Process Locked */ + __HAL_LOCK(hsubghz); + 8004c2c: 68fb ldr r3, [r7, #12] + 8004c2e: 795b ldrb r3, [r3, #5] + 8004c30: 2b01 cmp r3, #1 + 8004c32: d101 bne.n 8004c38 + 8004c34: 2302 movs r3, #2 + 8004c36: e038 b.n 8004caa + 8004c38: 68fb ldr r3, [r7, #12] + 8004c3a: 2201 movs r2, #1 + 8004c3c: 715a strb r2, [r3, #5] + + (void)SUBGHZ_CheckDeviceReady(hsubghz); + 8004c3e: 68f8 ldr r0, [r7, #12] + 8004c40: f000 fa44 bl 80050cc + + /* NSS = 0 */ + LL_PWR_SelectSUBGHZSPI_NSS(); + 8004c44: f7ff fde8 bl 8004818 + + (void)SUBGHZSPI_Transmit(hsubghz, (uint8_t)Command); + 8004c48: 7afb ldrb r3, [r7, #11] + 8004c4a: 4619 mov r1, r3 + 8004c4c: 68f8 ldr r0, [r7, #12] + 8004c4e: f000 f98f bl 8004f70 + + /* Use to flush the Status (First byte) receive from SUBGHZ as not use */ + (void)SUBGHZSPI_Transmit(hsubghz, 0x00U); + 8004c52: 2100 movs r1, #0 + 8004c54: 68f8 ldr r0, [r7, #12] + 8004c56: f000 f98b bl 8004f70 + + for (uint16_t i = 0U; i < Size; i++) + 8004c5a: 2300 movs r3, #0 + 8004c5c: 82fb strh r3, [r7, #22] + 8004c5e: e009 b.n 8004c74 + { + (void)SUBGHZSPI_Receive(hsubghz, (pData)); + 8004c60: 69b9 ldr r1, [r7, #24] + 8004c62: 68f8 ldr r0, [r7, #12] + 8004c64: f000 f9da bl 800501c + pData++; + 8004c68: 69bb ldr r3, [r7, #24] + 8004c6a: 3301 adds r3, #1 + 8004c6c: 61bb str r3, [r7, #24] + for (uint16_t i = 0U; i < Size; i++) + 8004c6e: 8afb ldrh r3, [r7, #22] + 8004c70: 3301 adds r3, #1 + 8004c72: 82fb strh r3, [r7, #22] + 8004c74: 8afa ldrh r2, [r7, #22] + 8004c76: 893b ldrh r3, [r7, #8] + 8004c78: 429a cmp r2, r3 + 8004c7a: d3f1 bcc.n 8004c60 + } + + /* NSS = 1 */ + LL_PWR_UnselectSUBGHZSPI_NSS(); + 8004c7c: f7ff fdbc bl 80047f8 + + (void)SUBGHZ_WaitOnBusy(hsubghz); + 8004c80: 68f8 ldr r0, [r7, #12] + 8004c82: f000 fa43 bl 800510c + + if (hsubghz->ErrorCode != HAL_SUBGHZ_ERROR_NONE) + 8004c86: 68fb ldr r3, [r7, #12] + 8004c88: 689b ldr r3, [r3, #8] + 8004c8a: 2b00 cmp r3, #0 + 8004c8c: d002 beq.n 8004c94 + { + status = HAL_ERROR; + 8004c8e: 2301 movs r3, #1 + 8004c90: 77fb strb r3, [r7, #31] + 8004c92: e001 b.n 8004c98 + } + else + { + status = HAL_OK; + 8004c94: 2300 movs r3, #0 + 8004c96: 77fb strb r3, [r7, #31] + } + + hsubghz->State = HAL_SUBGHZ_STATE_READY; + 8004c98: 68fb ldr r3, [r7, #12] + 8004c9a: 2201 movs r2, #1 + 8004c9c: 719a strb r2, [r3, #6] + + /* Process Unlocked */ + __HAL_UNLOCK(hsubghz); + 8004c9e: 68fb ldr r3, [r7, #12] + 8004ca0: 2200 movs r2, #0 + 8004ca2: 715a strb r2, [r3, #5] + + return status; + 8004ca4: 7ffb ldrb r3, [r7, #31] + 8004ca6: e000 b.n 8004caa + } + else + { + return HAL_BUSY; + 8004ca8: 2302 movs r3, #2 + } +} + 8004caa: 4618 mov r0, r3 + 8004cac: 3720 adds r7, #32 + 8004cae: 46bd mov sp, r7 + 8004cb0: bd80 pop {r7, pc} + +08004cb2 : + */ +HAL_StatusTypeDef HAL_SUBGHZ_WriteBuffer(SUBGHZ_HandleTypeDef *hsubghz, + uint8_t Offset, + uint8_t *pBuffer, + uint16_t Size) +{ + 8004cb2: b580 push {r7, lr} + 8004cb4: b086 sub sp, #24 + 8004cb6: af00 add r7, sp, #0 + 8004cb8: 60f8 str r0, [r7, #12] + 8004cba: 607a str r2, [r7, #4] + 8004cbc: 461a mov r2, r3 + 8004cbe: 460b mov r3, r1 + 8004cc0: 72fb strb r3, [r7, #11] + 8004cc2: 4613 mov r3, r2 + 8004cc4: 813b strh r3, [r7, #8] + HAL_StatusTypeDef status; + + if (hsubghz->State == HAL_SUBGHZ_STATE_READY) + 8004cc6: 68fb ldr r3, [r7, #12] + 8004cc8: 799b ldrb r3, [r3, #6] + 8004cca: b2db uxtb r3, r3 + 8004ccc: 2b01 cmp r3, #1 + 8004cce: d13e bne.n 8004d4e + { + /* Process Locked */ + __HAL_LOCK(hsubghz); + 8004cd0: 68fb ldr r3, [r7, #12] + 8004cd2: 795b ldrb r3, [r3, #5] + 8004cd4: 2b01 cmp r3, #1 + 8004cd6: d101 bne.n 8004cdc + 8004cd8: 2302 movs r3, #2 + 8004cda: e039 b.n 8004d50 + 8004cdc: 68fb ldr r3, [r7, #12] + 8004cde: 2201 movs r2, #1 + 8004ce0: 715a strb r2, [r3, #5] + + (void)SUBGHZ_CheckDeviceReady(hsubghz); + 8004ce2: 68f8 ldr r0, [r7, #12] + 8004ce4: f000 f9f2 bl 80050cc + + /* NSS = 0 */ + LL_PWR_SelectSUBGHZSPI_NSS(); + 8004ce8: f7ff fd96 bl 8004818 + + (void)SUBGHZSPI_Transmit(hsubghz, SUBGHZ_RADIO_WRITE_BUFFER); + 8004cec: 210e movs r1, #14 + 8004cee: 68f8 ldr r0, [r7, #12] + 8004cf0: f000 f93e bl 8004f70 + (void)SUBGHZSPI_Transmit(hsubghz, Offset); + 8004cf4: 7afb ldrb r3, [r7, #11] + 8004cf6: 4619 mov r1, r3 + 8004cf8: 68f8 ldr r0, [r7, #12] + 8004cfa: f000 f939 bl 8004f70 + + for (uint16_t i = 0U; i < Size; i++) + 8004cfe: 2300 movs r3, #0 + 8004d00: 82bb strh r3, [r7, #20] + 8004d02: e00a b.n 8004d1a + { + (void)SUBGHZSPI_Transmit(hsubghz, pBuffer[i]); + 8004d04: 8abb ldrh r3, [r7, #20] + 8004d06: 687a ldr r2, [r7, #4] + 8004d08: 4413 add r3, r2 + 8004d0a: 781b ldrb r3, [r3, #0] + 8004d0c: 4619 mov r1, r3 + 8004d0e: 68f8 ldr r0, [r7, #12] + 8004d10: f000 f92e bl 8004f70 + for (uint16_t i = 0U; i < Size; i++) + 8004d14: 8abb ldrh r3, [r7, #20] + 8004d16: 3301 adds r3, #1 + 8004d18: 82bb strh r3, [r7, #20] + 8004d1a: 8aba ldrh r2, [r7, #20] + 8004d1c: 893b ldrh r3, [r7, #8] + 8004d1e: 429a cmp r2, r3 + 8004d20: d3f0 bcc.n 8004d04 + } + /* NSS = 1 */ + LL_PWR_UnselectSUBGHZSPI_NSS(); + 8004d22: f7ff fd69 bl 80047f8 + + (void)SUBGHZ_WaitOnBusy(hsubghz); + 8004d26: 68f8 ldr r0, [r7, #12] + 8004d28: f000 f9f0 bl 800510c + + if (hsubghz->ErrorCode != HAL_SUBGHZ_ERROR_NONE) + 8004d2c: 68fb ldr r3, [r7, #12] + 8004d2e: 689b ldr r3, [r3, #8] + 8004d30: 2b00 cmp r3, #0 + 8004d32: d002 beq.n 8004d3a + { + status = HAL_ERROR; + 8004d34: 2301 movs r3, #1 + 8004d36: 75fb strb r3, [r7, #23] + 8004d38: e001 b.n 8004d3e + } + else + { + status = HAL_OK; + 8004d3a: 2300 movs r3, #0 + 8004d3c: 75fb strb r3, [r7, #23] + } + + hsubghz->State = HAL_SUBGHZ_STATE_READY; + 8004d3e: 68fb ldr r3, [r7, #12] + 8004d40: 2201 movs r2, #1 + 8004d42: 719a strb r2, [r3, #6] + + /* Process Unlocked */ + __HAL_UNLOCK(hsubghz); + 8004d44: 68fb ldr r3, [r7, #12] + 8004d46: 2200 movs r2, #0 + 8004d48: 715a strb r2, [r3, #5] + + return status; + 8004d4a: 7dfb ldrb r3, [r7, #23] + 8004d4c: e000 b.n 8004d50 + } + else + { + return HAL_BUSY; + 8004d4e: 2302 movs r3, #2 + } +} + 8004d50: 4618 mov r0, r3 + 8004d52: 3718 adds r7, #24 + 8004d54: 46bd mov sp, r7 + 8004d56: bd80 pop {r7, pc} + +08004d58 : + */ +HAL_StatusTypeDef HAL_SUBGHZ_ReadBuffer(SUBGHZ_HandleTypeDef *hsubghz, + uint8_t Offset, + uint8_t *pBuffer, + uint16_t Size) +{ + 8004d58: b580 push {r7, lr} + 8004d5a: b088 sub sp, #32 + 8004d5c: af00 add r7, sp, #0 + 8004d5e: 60f8 str r0, [r7, #12] + 8004d60: 607a str r2, [r7, #4] + 8004d62: 461a mov r2, r3 + 8004d64: 460b mov r3, r1 + 8004d66: 72fb strb r3, [r7, #11] + 8004d68: 4613 mov r3, r2 + 8004d6a: 813b strh r3, [r7, #8] + HAL_StatusTypeDef status; + uint8_t *pData = pBuffer; + 8004d6c: 687b ldr r3, [r7, #4] + 8004d6e: 61bb str r3, [r7, #24] + + if (hsubghz->State == HAL_SUBGHZ_STATE_READY) + 8004d70: 68fb ldr r3, [r7, #12] + 8004d72: 799b ldrb r3, [r3, #6] + 8004d74: b2db uxtb r3, r3 + 8004d76: 2b01 cmp r3, #1 + 8004d78: d141 bne.n 8004dfe + { + /* Process Locked */ + __HAL_LOCK(hsubghz); + 8004d7a: 68fb ldr r3, [r7, #12] + 8004d7c: 795b ldrb r3, [r3, #5] + 8004d7e: 2b01 cmp r3, #1 + 8004d80: d101 bne.n 8004d86 + 8004d82: 2302 movs r3, #2 + 8004d84: e03c b.n 8004e00 + 8004d86: 68fb ldr r3, [r7, #12] + 8004d88: 2201 movs r2, #1 + 8004d8a: 715a strb r2, [r3, #5] + + (void)SUBGHZ_CheckDeviceReady(hsubghz); + 8004d8c: 68f8 ldr r0, [r7, #12] + 8004d8e: f000 f99d bl 80050cc + + /* NSS = 0 */ + LL_PWR_SelectSUBGHZSPI_NSS(); + 8004d92: f7ff fd41 bl 8004818 + + (void)SUBGHZSPI_Transmit(hsubghz, SUBGHZ_RADIO_READ_BUFFER); + 8004d96: 211e movs r1, #30 + 8004d98: 68f8 ldr r0, [r7, #12] + 8004d9a: f000 f8e9 bl 8004f70 + (void)SUBGHZSPI_Transmit(hsubghz, Offset); + 8004d9e: 7afb ldrb r3, [r7, #11] + 8004da0: 4619 mov r1, r3 + 8004da2: 68f8 ldr r0, [r7, #12] + 8004da4: f000 f8e4 bl 8004f70 + (void)SUBGHZSPI_Transmit(hsubghz, 0x00U); + 8004da8: 2100 movs r1, #0 + 8004daa: 68f8 ldr r0, [r7, #12] + 8004dac: f000 f8e0 bl 8004f70 + + for (uint16_t i = 0U; i < Size; i++) + 8004db0: 2300 movs r3, #0 + 8004db2: 82fb strh r3, [r7, #22] + 8004db4: e009 b.n 8004dca + { + (void)SUBGHZSPI_Receive(hsubghz, (pData)); + 8004db6: 69b9 ldr r1, [r7, #24] + 8004db8: 68f8 ldr r0, [r7, #12] + 8004dba: f000 f92f bl 800501c + pData++; + 8004dbe: 69bb ldr r3, [r7, #24] + 8004dc0: 3301 adds r3, #1 + 8004dc2: 61bb str r3, [r7, #24] + for (uint16_t i = 0U; i < Size; i++) + 8004dc4: 8afb ldrh r3, [r7, #22] + 8004dc6: 3301 adds r3, #1 + 8004dc8: 82fb strh r3, [r7, #22] + 8004dca: 8afa ldrh r2, [r7, #22] + 8004dcc: 893b ldrh r3, [r7, #8] + 8004dce: 429a cmp r2, r3 + 8004dd0: d3f1 bcc.n 8004db6 + } + + /* NSS = 1 */ + LL_PWR_UnselectSUBGHZSPI_NSS(); + 8004dd2: f7ff fd11 bl 80047f8 + + (void)SUBGHZ_WaitOnBusy(hsubghz); + 8004dd6: 68f8 ldr r0, [r7, #12] + 8004dd8: f000 f998 bl 800510c + + if (hsubghz->ErrorCode != HAL_SUBGHZ_ERROR_NONE) + 8004ddc: 68fb ldr r3, [r7, #12] + 8004dde: 689b ldr r3, [r3, #8] + 8004de0: 2b00 cmp r3, #0 + 8004de2: d002 beq.n 8004dea + { + status = HAL_ERROR; + 8004de4: 2301 movs r3, #1 + 8004de6: 77fb strb r3, [r7, #31] + 8004de8: e001 b.n 8004dee + } + else + { + status = HAL_OK; + 8004dea: 2300 movs r3, #0 + 8004dec: 77fb strb r3, [r7, #31] + } + + hsubghz->State = HAL_SUBGHZ_STATE_READY; + 8004dee: 68fb ldr r3, [r7, #12] + 8004df0: 2201 movs r2, #1 + 8004df2: 719a strb r2, [r3, #6] + + /* Process Unlocked */ + __HAL_UNLOCK(hsubghz); + 8004df4: 68fb ldr r3, [r7, #12] + 8004df6: 2200 movs r2, #0 + 8004df8: 715a strb r2, [r3, #5] + + return status; + 8004dfa: 7ffb ldrb r3, [r7, #31] + 8004dfc: e000 b.n 8004e00 + } + else + { + return HAL_BUSY; + 8004dfe: 2302 movs r3, #2 + } +} + 8004e00: 4618 mov r0, r3 + 8004e02: 3720 adds r7, #32 + 8004e04: 46bd mov sp, r7 + 8004e06: bd80 pop {r7, pc} + +08004e08 : + * @param hsubghz pointer to a SUBGHZ_HandleTypeDef structure that contains + * the configuration information for the specified SUBGHZ module. + * @retval None + */ +void HAL_SUBGHZ_IRQHandler(SUBGHZ_HandleTypeDef *hsubghz) +{ + 8004e08: b580 push {r7, lr} + 8004e0a: b084 sub sp, #16 + 8004e0c: af00 add r7, sp, #0 + 8004e0e: 6078 str r0, [r7, #4] + uint8_t tmpisr[2U] = {0U}; + 8004e10: 2300 movs r3, #0 + 8004e12: 81bb strh r3, [r7, #12] + uint16_t itsource; + + /* Retrieve Interrupts from SUBGHZ Irq Register */ + (void)HAL_SUBGHZ_ExecGetCmd(hsubghz, RADIO_GET_IRQSTATUS, tmpisr, 2U); + 8004e14: f107 020c add.w r2, r7, #12 + 8004e18: 2302 movs r3, #2 + 8004e1a: 2112 movs r1, #18 + 8004e1c: 6878 ldr r0, [r7, #4] + 8004e1e: f7ff fef4 bl 8004c0a + itsource = tmpisr[0U]; + 8004e22: 7b3b ldrb r3, [r7, #12] + 8004e24: 81fb strh r3, [r7, #14] + itsource = (itsource << 8U) | tmpisr[1U]; + 8004e26: f9b7 300e ldrsh.w r3, [r7, #14] + 8004e2a: 021b lsls r3, r3, #8 + 8004e2c: b21a sxth r2, r3 + 8004e2e: 7b7b ldrb r3, [r7, #13] + 8004e30: b21b sxth r3, r3 + 8004e32: 4313 orrs r3, r2 + 8004e34: b21b sxth r3, r3 + 8004e36: 81fb strh r3, [r7, #14] + + /* Clear SUBGHZ Irq Register */ + (void)HAL_SUBGHZ_ExecSetCmd(hsubghz, RADIO_CLR_IRQSTATUS, tmpisr, 2U); + 8004e38: f107 020c add.w r2, r7, #12 + 8004e3c: 2302 movs r3, #2 + 8004e3e: 2102 movs r1, #2 + 8004e40: 6878 ldr r0, [r7, #4] + 8004e42: f7ff fe83 bl 8004b4c + + /* Packet transmission completed Interrupt */ + if (SUBGHZ_CHECK_IT_SOURCE(itsource, SUBGHZ_IT_TX_CPLT) != RESET) + 8004e46: 89fb ldrh r3, [r7, #14] + 8004e48: f003 0301 and.w r3, r3, #1 + 8004e4c: 2b00 cmp r3, #0 + 8004e4e: d002 beq.n 8004e56 + { +#if (USE_HAL_SUBGHZ_REGISTER_CALLBACKS == 1U) + hsubghz->TxCpltCallback(hsubghz); +#else + HAL_SUBGHZ_TxCpltCallback(hsubghz); + 8004e50: 6878 ldr r0, [r7, #4] + 8004e52: f005 fdcd bl 800a9f0 +#endif /* USE_HAL_SUBGHZ_REGISTER_CALLBACKS */ + } + + /* Packet received Interrupt */ + if ((SUBGHZ_CHECK_IT_SOURCE(itsource, SUBGHZ_IT_RX_CPLT) != RESET)) + 8004e56: 89fb ldrh r3, [r7, #14] + 8004e58: 085b lsrs r3, r3, #1 + 8004e5a: f003 0301 and.w r3, r3, #1 + 8004e5e: 2b00 cmp r3, #0 + 8004e60: d00e beq.n 8004e80 + { + if (SUBGHZ_CHECK_IT_SOURCE(itsource, SUBGHZ_IT_CRC_ERROR) != RESET) + 8004e62: 89fb ldrh r3, [r7, #14] + 8004e64: 099b lsrs r3, r3, #6 + 8004e66: f003 0301 and.w r3, r3, #1 + 8004e6a: 2b00 cmp r3, #0 + 8004e6c: d005 beq.n 8004e7a + { + hsubghz->ErrorCode |= HAL_SUBGHZ_ERROR_CRC_MISMATCH; + 8004e6e: 687b ldr r3, [r7, #4] + 8004e70: 689b ldr r3, [r3, #8] + 8004e72: f043 0204 orr.w r2, r3, #4 + 8004e76: 687b ldr r3, [r7, #4] + 8004e78: 609a str r2, [r3, #8] + } +#if (USE_HAL_SUBGHZ_REGISTER_CALLBACKS == 1U) + hsubghz->RxCpltCallback(hsubghz); +#else + HAL_SUBGHZ_RxCpltCallback(hsubghz); + 8004e7a: 6878 ldr r0, [r7, #4] + 8004e7c: f005 fdc6 bl 800aa0c +#endif /* USE_HAL_SUBGHZ_REGISTER_CALLBACKS */ + } + + /* Preamble Detected Interrupt */ + if (SUBGHZ_CHECK_IT_SOURCE(itsource, SUBGHZ_IT_PREAMBLE_DETECTED) != RESET) + 8004e80: 89fb ldrh r3, [r7, #14] + 8004e82: 089b lsrs r3, r3, #2 + 8004e84: f003 0301 and.w r3, r3, #1 + 8004e88: 2b00 cmp r3, #0 + 8004e8a: d002 beq.n 8004e92 + { +#if (USE_HAL_SUBGHZ_REGISTER_CALLBACKS == 1U) + hsubghz->PreambleDetectedCallback(hsubghz); +#else + HAL_SUBGHZ_PreambleDetectedCallback(hsubghz); + 8004e8c: 6878 ldr r0, [r7, #4] + 8004e8e: f005 fe15 bl 800aabc +#endif /* USE_HAL_SUBGHZ_REGISTER_CALLBACKS */ + } + + /* Valid sync word detected Interrupt */ + if (SUBGHZ_CHECK_IT_SOURCE(itsource, SUBGHZ_IT_SYNCWORD_VALID) != RESET) + 8004e92: 89fb ldrh r3, [r7, #14] + 8004e94: 08db lsrs r3, r3, #3 + 8004e96: f003 0301 and.w r3, r3, #1 + 8004e9a: 2b00 cmp r3, #0 + 8004e9c: d002 beq.n 8004ea4 + { +#if (USE_HAL_SUBGHZ_REGISTER_CALLBACKS == 1U) + hsubghz->SyncWordValidCallback(hsubghz); +#else + HAL_SUBGHZ_SyncWordValidCallback(hsubghz); + 8004e9e: 6878 ldr r0, [r7, #4] + 8004ea0: f005 fe1a bl 800aad8 +#endif /* USE_HAL_SUBGHZ_REGISTER_CALLBACKS */ + } + + /* Valid LoRa header received Interrupt */ + if (SUBGHZ_CHECK_IT_SOURCE(itsource, SUBGHZ_IT_HEADER_VALID) != RESET) + 8004ea4: 89fb ldrh r3, [r7, #14] + 8004ea6: 091b lsrs r3, r3, #4 + 8004ea8: f003 0301 and.w r3, r3, #1 + 8004eac: 2b00 cmp r3, #0 + 8004eae: d002 beq.n 8004eb6 + { +#if (USE_HAL_SUBGHZ_REGISTER_CALLBACKS == 1U) + hsubghz->HeaderValidCallback(hsubghz); +#else + HAL_SUBGHZ_HeaderValidCallback(hsubghz); + 8004eb0: 6878 ldr r0, [r7, #4] + 8004eb2: f005 fe1f bl 800aaf4 +#endif /* USE_HAL_SUBGHZ_REGISTER_CALLBACKS */ + } + + /* LoRa header CRC error Interrupt */ + if (SUBGHZ_CHECK_IT_SOURCE(itsource, SUBGHZ_IT_HEADER_ERROR) != RESET) + 8004eb6: 89fb ldrh r3, [r7, #14] + 8004eb8: 095b lsrs r3, r3, #5 + 8004eba: f003 0301 and.w r3, r3, #1 + 8004ebe: 2b00 cmp r3, #0 + 8004ec0: d002 beq.n 8004ec8 + { +#if (USE_HAL_SUBGHZ_REGISTER_CALLBACKS == 1U) + hsubghz->HeaderErrorCallback(hsubghz); +#else + HAL_SUBGHZ_HeaderErrorCallback(hsubghz); + 8004ec2: 6878 ldr r0, [r7, #4] + 8004ec4: f005 fdec bl 800aaa0 +#endif /* USE_HAL_SUBGHZ_REGISTER_CALLBACKS */ + } + + /* Wrong CRC received Interrupt */ + if (SUBGHZ_CHECK_IT_SOURCE(itsource, SUBGHZ_IT_CRC_ERROR) != RESET) + 8004ec8: 89fb ldrh r3, [r7, #14] + 8004eca: 099b lsrs r3, r3, #6 + 8004ecc: f003 0301 and.w r3, r3, #1 + 8004ed0: 2b00 cmp r3, #0 + 8004ed2: d002 beq.n 8004eda + { +#if (USE_HAL_SUBGHZ_REGISTER_CALLBACKS == 1U) + hsubghz->CRCErrorCallback(hsubghz); +#else + HAL_SUBGHZ_CRCErrorCallback(hsubghz); + 8004ed4: 6878 ldr r0, [r7, #4] + 8004ed6: f005 fda7 bl 800aa28 +#endif /* USE_HAL_SUBGHZ_REGISTER_CALLBACKS */ + } + + /* Channel activity detection finished Interrupt */ + if (SUBGHZ_CHECK_IT_SOURCE(itsource, SUBGHZ_IT_CAD_DONE) != RESET) + 8004eda: 89fb ldrh r3, [r7, #14] + 8004edc: 09db lsrs r3, r3, #7 + 8004ede: f003 0301 and.w r3, r3, #1 + 8004ee2: 2b00 cmp r3, #0 + 8004ee4: d00e beq.n 8004f04 + { + hsubghz->CADStatusCallback(hsubghz, HAL_SUBGHZ_CAD_CLEAR); + } +#else + /* Channel activity Detected Interrupt */ + if (SUBGHZ_CHECK_IT_SOURCE(itsource, SUBGHZ_IT_CAD_ACTIVITY_DETECTED) != RESET) + 8004ee6: 89fb ldrh r3, [r7, #14] + 8004ee8: 0a1b lsrs r3, r3, #8 + 8004eea: f003 0301 and.w r3, r3, #1 + 8004eee: 2b00 cmp r3, #0 + 8004ef0: d004 beq.n 8004efc + { + HAL_SUBGHZ_CADStatusCallback(hsubghz, HAL_SUBGHZ_CAD_DETECTED); + 8004ef2: 2101 movs r1, #1 + 8004ef4: 6878 ldr r0, [r7, #4] + 8004ef6: f005 fda5 bl 800aa44 + 8004efa: e003 b.n 8004f04 + } + else + { + HAL_SUBGHZ_CADStatusCallback(hsubghz, HAL_SUBGHZ_CAD_CLEAR); + 8004efc: 2100 movs r1, #0 + 8004efe: 6878 ldr r0, [r7, #4] + 8004f00: f005 fda0 bl 800aa44 + } +#endif /* USE_HAL_SUBGHZ_REGISTER_CALLBACKS */ + } + + /* Rx or Tx Timeout Interrupt */ + if (SUBGHZ_CHECK_IT_SOURCE(itsource, SUBGHZ_IT_RX_TX_TIMEOUT) != RESET) + 8004f04: 89fb ldrh r3, [r7, #14] + 8004f06: 0a5b lsrs r3, r3, #9 + 8004f08: f003 0301 and.w r3, r3, #1 + 8004f0c: 2b00 cmp r3, #0 + 8004f0e: d002 beq.n 8004f16 + { +#if (USE_HAL_SUBGHZ_REGISTER_CALLBACKS == 1U) + hsubghz->RxTxTimeoutCallback(hsubghz); +#else + HAL_SUBGHZ_RxTxTimeoutCallback(hsubghz); + 8004f10: 6878 ldr r0, [r7, #4] + 8004f12: f005 fdb5 bl 800aa80 +#endif /* USE_HAL_SUBGHZ_REGISTER_CALLBACKS */ + } + + /* LR_FHSS Hop interrupt */ + if (SUBGHZ_CHECK_IT_SOURCE(itsource, SUBGHZ_IT_LR_FHSS_HOP) != RESET) + 8004f16: 89fb ldrh r3, [r7, #14] + 8004f18: 0b9b lsrs r3, r3, #14 + 8004f1a: f003 0301 and.w r3, r3, #1 + 8004f1e: 2b00 cmp r3, #0 + 8004f20: d002 beq.n 8004f28 + { +#if (USE_HAL_SUBGHZ_REGISTER_CALLBACKS == 1U) + hsubghz->LrFhssHopCallback(hsubghz); +#else + HAL_SUBGHZ_LrFhssHopCallback(hsubghz); + 8004f22: 6878 ldr r0, [r7, #4] + 8004f24: f005 fdf4 bl 800ab10 +#endif /* USE_HAL_SUBGHZ_REGISTER_CALLBACKS */ + } +} + 8004f28: bf00 nop + 8004f2a: 3710 adds r7, #16 + 8004f2c: 46bd mov sp, r7 + 8004f2e: bd80 pop {r7, pc} + +08004f30 : + * @brief Initializes the SUBGHZSPI peripheral + * @param BaudratePrescaler SPI Baudrate prescaler + * @retval None + */ +void SUBGHZSPI_Init(uint32_t BaudratePrescaler) +{ + 8004f30: b480 push {r7} + 8004f32: b083 sub sp, #12 + 8004f34: af00 add r7, sp, #0 + 8004f36: 6078 str r0, [r7, #4] + /* Check the parameters */ + assert_param(IS_SUBGHZ_ALL_INSTANCE(SUBGHZSPI)); + + /* Disable SUBGHZSPI Peripheral */ + CLEAR_BIT(SUBGHZSPI->CR1, SPI_CR1_SPE); + 8004f38: 4b0c ldr r3, [pc, #48] @ (8004f6c ) + 8004f3a: 681b ldr r3, [r3, #0] + 8004f3c: 4a0b ldr r2, [pc, #44] @ (8004f6c ) + 8004f3e: f023 0340 bic.w r3, r3, #64 @ 0x40 + 8004f42: 6013 str r3, [r2, #0] + * NSS management: Internal (Done with External bit inside PWR * + * Communication speed: BaudratePrescaler * + * First bit: MSB * + * CRC calculation: Disable * + *--------------------------------------------------------------------------*/ + WRITE_REG(SUBGHZSPI->CR1, (SPI_CR1_MSTR | SPI_CR1_SSI | BaudratePrescaler | SPI_CR1_SSM)); + 8004f44: 4a09 ldr r2, [pc, #36] @ (8004f6c ) + 8004f46: 687b ldr r3, [r7, #4] + 8004f48: f443 7341 orr.w r3, r3, #772 @ 0x304 + 8004f4c: 6013 str r3, [r2, #0] + * Data Size: 8bits * + * TI Mode: Disable * + * NSS Pulse: Disable * + * Rx FIFO Threshold: 8bits * + *--------------------------------------------------------------------------*/ + WRITE_REG(SUBGHZSPI->CR2, (SPI_CR2_FRXTH | SPI_CR2_DS_0 | SPI_CR2_DS_1 | SPI_CR2_DS_2)); + 8004f4e: 4b07 ldr r3, [pc, #28] @ (8004f6c ) + 8004f50: f44f 52b8 mov.w r2, #5888 @ 0x1700 + 8004f54: 605a str r2, [r3, #4] + + /* Enable SUBGHZSPI Peripheral */ + SET_BIT(SUBGHZSPI->CR1, SPI_CR1_SPE); + 8004f56: 4b05 ldr r3, [pc, #20] @ (8004f6c ) + 8004f58: 681b ldr r3, [r3, #0] + 8004f5a: 4a04 ldr r2, [pc, #16] @ (8004f6c ) + 8004f5c: f043 0340 orr.w r3, r3, #64 @ 0x40 + 8004f60: 6013 str r3, [r2, #0] +} + 8004f62: bf00 nop + 8004f64: 370c adds r7, #12 + 8004f66: 46bd mov sp, r7 + 8004f68: bc80 pop {r7} + 8004f6a: 4770 bx lr + 8004f6c: 58010000 .word 0x58010000 + +08004f70 : + * @param Data data to transmit + * @retval HAL status + */ +HAL_StatusTypeDef SUBGHZSPI_Transmit(SUBGHZ_HandleTypeDef *hsubghz, + uint8_t Data) +{ + 8004f70: b480 push {r7} + 8004f72: b087 sub sp, #28 + 8004f74: af00 add r7, sp, #0 + 8004f76: 6078 str r0, [r7, #4] + 8004f78: 460b mov r3, r1 + 8004f7a: 70fb strb r3, [r7, #3] + HAL_StatusTypeDef status = HAL_OK; + 8004f7c: 2300 movs r3, #0 + 8004f7e: 75fb strb r3, [r7, #23] + __IO uint32_t count; + + /* Handle Tx transmission from SUBGHZSPI peripheral to Radio ****************/ + /* Initialize Timeout */ + count = SUBGHZ_DEFAULT_TIMEOUT * SUBGHZ_DEFAULT_LOOP_TIME; + 8004f80: 4b23 ldr r3, [pc, #140] @ (8005010 ) + 8004f82: 681a ldr r2, [r3, #0] + 8004f84: 4613 mov r3, r2 + 8004f86: 00db lsls r3, r3, #3 + 8004f88: 1a9b subs r3, r3, r2 + 8004f8a: 009b lsls r3, r3, #2 + 8004f8c: 0cdb lsrs r3, r3, #19 + 8004f8e: 2264 movs r2, #100 @ 0x64 + 8004f90: fb02 f303 mul.w r3, r2, r3 + 8004f94: 60fb str r3, [r7, #12] + + /* Wait until TXE flag is set */ + do + { + if (count == 0U) + 8004f96: 68fb ldr r3, [r7, #12] + 8004f98: 2b00 cmp r3, #0 + 8004f9a: d105 bne.n 8004fa8 + { + status = HAL_ERROR; + 8004f9c: 2301 movs r3, #1 + 8004f9e: 75fb strb r3, [r7, #23] + hsubghz->ErrorCode = HAL_SUBGHZ_ERROR_TIMEOUT; + 8004fa0: 687b ldr r3, [r7, #4] + 8004fa2: 2201 movs r2, #1 + 8004fa4: 609a str r2, [r3, #8] + break; + 8004fa6: e008 b.n 8004fba + } + count--; + 8004fa8: 68fb ldr r3, [r7, #12] + 8004faa: 3b01 subs r3, #1 + 8004fac: 60fb str r3, [r7, #12] + } while (READ_BIT(SUBGHZSPI->SR, SPI_SR_TXE) != (SPI_SR_TXE)); + 8004fae: 4b19 ldr r3, [pc, #100] @ (8005014 ) + 8004fb0: 689b ldr r3, [r3, #8] + 8004fb2: f003 0302 and.w r3, r3, #2 + 8004fb6: 2b02 cmp r3, #2 + 8004fb8: d1ed bne.n 8004f96 + + /* Transmit Data*/ +#if defined (__GNUC__) + __IO uint8_t *spidr = ((__IO uint8_t *)&SUBGHZSPI->DR); + 8004fba: 4b17 ldr r3, [pc, #92] @ (8005018 ) + 8004fbc: 613b str r3, [r7, #16] + *spidr = Data; + 8004fbe: 693b ldr r3, [r7, #16] + 8004fc0: 78fa ldrb r2, [r7, #3] + 8004fc2: 701a strb r2, [r3, #0] + *((__IO uint8_t *)&SUBGHZSPI->DR) = Data; +#endif /* __GNUC__ */ + + /* Handle Rx transmission from SUBGHZSPI peripheral to Radio ****************/ + /* Initialize Timeout */ + count = SUBGHZ_DEFAULT_TIMEOUT * SUBGHZ_DEFAULT_LOOP_TIME; + 8004fc4: 4b12 ldr r3, [pc, #72] @ (8005010 ) + 8004fc6: 681a ldr r2, [r3, #0] + 8004fc8: 4613 mov r3, r2 + 8004fca: 00db lsls r3, r3, #3 + 8004fcc: 1a9b subs r3, r3, r2 + 8004fce: 009b lsls r3, r3, #2 + 8004fd0: 0cdb lsrs r3, r3, #19 + 8004fd2: 2264 movs r2, #100 @ 0x64 + 8004fd4: fb02 f303 mul.w r3, r2, r3 + 8004fd8: 60fb str r3, [r7, #12] + + /* Wait until RXNE flag is set */ + do + { + if (count == 0U) + 8004fda: 68fb ldr r3, [r7, #12] + 8004fdc: 2b00 cmp r3, #0 + 8004fde: d105 bne.n 8004fec + { + status = HAL_ERROR; + 8004fe0: 2301 movs r3, #1 + 8004fe2: 75fb strb r3, [r7, #23] + hsubghz->ErrorCode = HAL_SUBGHZ_ERROR_TIMEOUT; + 8004fe4: 687b ldr r3, [r7, #4] + 8004fe6: 2201 movs r2, #1 + 8004fe8: 609a str r2, [r3, #8] + break; + 8004fea: e008 b.n 8004ffe + } + count--; + 8004fec: 68fb ldr r3, [r7, #12] + 8004fee: 3b01 subs r3, #1 + 8004ff0: 60fb str r3, [r7, #12] + } while (READ_BIT(SUBGHZSPI->SR, SPI_SR_RXNE) != (SPI_SR_RXNE)); + 8004ff2: 4b08 ldr r3, [pc, #32] @ (8005014 ) + 8004ff4: 689b ldr r3, [r3, #8] + 8004ff6: f003 0301 and.w r3, r3, #1 + 8004ffa: 2b01 cmp r3, #1 + 8004ffc: d1ed bne.n 8004fda + + /* Flush Rx data */ + READ_REG(SUBGHZSPI->DR); + 8004ffe: 4b05 ldr r3, [pc, #20] @ (8005014 ) + 8005000: 68db ldr r3, [r3, #12] + + return status; + 8005002: 7dfb ldrb r3, [r7, #23] +} + 8005004: 4618 mov r0, r3 + 8005006: 371c adds r7, #28 + 8005008: 46bd mov sp, r7 + 800500a: bc80 pop {r7} + 800500c: 4770 bx lr + 800500e: bf00 nop + 8005010: 20000000 .word 0x20000000 + 8005014: 58010000 .word 0x58010000 + 8005018: 5801000c .word 0x5801000c + +0800501c : + * @param pData pointer on data to receive + * @retval HAL status + */ +HAL_StatusTypeDef SUBGHZSPI_Receive(SUBGHZ_HandleTypeDef *hsubghz, + uint8_t *pData) +{ + 800501c: b480 push {r7} + 800501e: b087 sub sp, #28 + 8005020: af00 add r7, sp, #0 + 8005022: 6078 str r0, [r7, #4] + 8005024: 6039 str r1, [r7, #0] + HAL_StatusTypeDef status = HAL_OK; + 8005026: 2300 movs r3, #0 + 8005028: 75fb strb r3, [r7, #23] + __IO uint32_t count; + + /* Handle Tx transmission from SUBGHZSPI peripheral to Radio ****************/ + /* Initialize Timeout */ + count = SUBGHZ_DEFAULT_TIMEOUT * SUBGHZ_DEFAULT_LOOP_TIME; + 800502a: 4b25 ldr r3, [pc, #148] @ (80050c0 ) + 800502c: 681a ldr r2, [r3, #0] + 800502e: 4613 mov r3, r2 + 8005030: 00db lsls r3, r3, #3 + 8005032: 1a9b subs r3, r3, r2 + 8005034: 009b lsls r3, r3, #2 + 8005036: 0cdb lsrs r3, r3, #19 + 8005038: 2264 movs r2, #100 @ 0x64 + 800503a: fb02 f303 mul.w r3, r2, r3 + 800503e: 60fb str r3, [r7, #12] + + /* Wait until TXE flag is set */ + do + { + if (count == 0U) + 8005040: 68fb ldr r3, [r7, #12] + 8005042: 2b00 cmp r3, #0 + 8005044: d105 bne.n 8005052 + { + status = HAL_ERROR; + 8005046: 2301 movs r3, #1 + 8005048: 75fb strb r3, [r7, #23] + hsubghz->ErrorCode = HAL_SUBGHZ_ERROR_TIMEOUT; + 800504a: 687b ldr r3, [r7, #4] + 800504c: 2201 movs r2, #1 + 800504e: 609a str r2, [r3, #8] + break; + 8005050: e008 b.n 8005064 + } + count--; + 8005052: 68fb ldr r3, [r7, #12] + 8005054: 3b01 subs r3, #1 + 8005056: 60fb str r3, [r7, #12] + } while (READ_BIT(SUBGHZSPI->SR, SPI_SR_TXE) != (SPI_SR_TXE)); + 8005058: 4b1a ldr r3, [pc, #104] @ (80050c4 ) + 800505a: 689b ldr r3, [r3, #8] + 800505c: f003 0302 and.w r3, r3, #2 + 8005060: 2b02 cmp r3, #2 + 8005062: d1ed bne.n 8005040 + + /* Transmit Data*/ +#if defined (__GNUC__) + __IO uint8_t *spidr = ((__IO uint8_t *)&SUBGHZSPI->DR); + 8005064: 4b18 ldr r3, [pc, #96] @ (80050c8 ) + 8005066: 613b str r3, [r7, #16] + *spidr = SUBGHZ_DUMMY_DATA; + 8005068: 693b ldr r3, [r7, #16] + 800506a: 22ff movs r2, #255 @ 0xff + 800506c: 701a strb r2, [r3, #0] + *((__IO uint8_t *)&SUBGHZSPI->DR) = SUBGHZ_DUMMY_DATA; +#endif /* __GNUC__ */ + + /* Handle Rx transmission from SUBGHZSPI peripheral to Radio ****************/ + /* Initialize Timeout */ + count = SUBGHZ_DEFAULT_TIMEOUT * SUBGHZ_DEFAULT_LOOP_TIME; + 800506e: 4b14 ldr r3, [pc, #80] @ (80050c0 ) + 8005070: 681a ldr r2, [r3, #0] + 8005072: 4613 mov r3, r2 + 8005074: 00db lsls r3, r3, #3 + 8005076: 1a9b subs r3, r3, r2 + 8005078: 009b lsls r3, r3, #2 + 800507a: 0cdb lsrs r3, r3, #19 + 800507c: 2264 movs r2, #100 @ 0x64 + 800507e: fb02 f303 mul.w r3, r2, r3 + 8005082: 60fb str r3, [r7, #12] + + /* Wait until RXNE flag is set */ + do + { + if (count == 0U) + 8005084: 68fb ldr r3, [r7, #12] + 8005086: 2b00 cmp r3, #0 + 8005088: d105 bne.n 8005096 + { + status = HAL_ERROR; + 800508a: 2301 movs r3, #1 + 800508c: 75fb strb r3, [r7, #23] + hsubghz->ErrorCode = HAL_SUBGHZ_ERROR_TIMEOUT; + 800508e: 687b ldr r3, [r7, #4] + 8005090: 2201 movs r2, #1 + 8005092: 609a str r2, [r3, #8] + break; + 8005094: e008 b.n 80050a8 + } + count--; + 8005096: 68fb ldr r3, [r7, #12] + 8005098: 3b01 subs r3, #1 + 800509a: 60fb str r3, [r7, #12] + } while (READ_BIT(SUBGHZSPI->SR, SPI_SR_RXNE) != (SPI_SR_RXNE)); + 800509c: 4b09 ldr r3, [pc, #36] @ (80050c4 ) + 800509e: 689b ldr r3, [r3, #8] + 80050a0: f003 0301 and.w r3, r3, #1 + 80050a4: 2b01 cmp r3, #1 + 80050a6: d1ed bne.n 8005084 + + /* Retrieve pData */ + *pData = (uint8_t)(READ_REG(SUBGHZSPI->DR)); + 80050a8: 4b06 ldr r3, [pc, #24] @ (80050c4 ) + 80050aa: 68db ldr r3, [r3, #12] + 80050ac: b2da uxtb r2, r3 + 80050ae: 683b ldr r3, [r7, #0] + 80050b0: 701a strb r2, [r3, #0] + + return status; + 80050b2: 7dfb ldrb r3, [r7, #23] +} + 80050b4: 4618 mov r0, r3 + 80050b6: 371c adds r7, #28 + 80050b8: 46bd mov sp, r7 + 80050ba: bc80 pop {r7} + 80050bc: 4770 bx lr + 80050be: bf00 nop + 80050c0: 20000000 .word 0x20000000 + 80050c4: 58010000 .word 0x58010000 + 80050c8: 5801000c .word 0x5801000c + +080050cc : + * @param hsubghz pointer to a SUBGHZ_HandleTypeDef structure that contains + * the handle information for SUBGHZ module. + * @retval HAL status + */ +HAL_StatusTypeDef SUBGHZ_CheckDeviceReady(SUBGHZ_HandleTypeDef *hsubghz) +{ + 80050cc: b580 push {r7, lr} + 80050ce: b084 sub sp, #16 + 80050d0: af00 add r7, sp, #0 + 80050d2: 6078 str r0, [r7, #4] + __IO uint32_t count; + + /* Wakeup radio in case of sleep mode: Select-Unselect radio */ + if (hsubghz->DeepSleep == SUBGHZ_DEEP_SLEEP_ENABLE) + 80050d4: 687b ldr r3, [r7, #4] + 80050d6: 791b ldrb r3, [r3, #4] + 80050d8: 2b01 cmp r3, #1 + 80050da: d10d bne.n 80050f8 + { + /* Initialize NSS switch Delay */ + count = SUBGHZ_NSS_LOOP_TIME; + 80050dc: 4b0a ldr r3, [pc, #40] @ (8005108 ) + 80050de: 681b ldr r3, [r3, #0] + 80050e0: 0c1b lsrs r3, r3, #16 + 80050e2: 60fb str r3, [r7, #12] + + /* NSS = 0; */ + LL_PWR_SelectSUBGHZSPI_NSS(); + 80050e4: f7ff fb98 bl 8004818 + + /* Wait Radio wakeup */ + do + { + count--; + 80050e8: 68fb ldr r3, [r7, #12] + 80050ea: 3b01 subs r3, #1 + 80050ec: 60fb str r3, [r7, #12] + } while (count != 0UL); + 80050ee: 68fb ldr r3, [r7, #12] + 80050f0: 2b00 cmp r3, #0 + 80050f2: d1f9 bne.n 80050e8 + + /* NSS = 1 */ + LL_PWR_UnselectSUBGHZSPI_NSS(); + 80050f4: f7ff fb80 bl 80047f8 + } + return (SUBGHZ_WaitOnBusy(hsubghz)); + 80050f8: 6878 ldr r0, [r7, #4] + 80050fa: f000 f807 bl 800510c + 80050fe: 4603 mov r3, r0 +} + 8005100: 4618 mov r0, r3 + 8005102: 3710 adds r7, #16 + 8005104: 46bd mov sp, r7 + 8005106: bd80 pop {r7, pc} + 8005108: 20000000 .word 0x20000000 + +0800510c : + * @param hsubghz pointer to a SUBGHZ_HandleTypeDef structure that contains + * the handle information for SUBGHZ module. + * @retval HAL status + */ +HAL_StatusTypeDef SUBGHZ_WaitOnBusy(SUBGHZ_HandleTypeDef *hsubghz) +{ + 800510c: b580 push {r7, lr} + 800510e: b086 sub sp, #24 + 8005110: af00 add r7, sp, #0 + 8005112: 6078 str r0, [r7, #4] + HAL_StatusTypeDef status; + __IO uint32_t count; + uint32_t mask; + + status = HAL_OK; + 8005114: 2300 movs r3, #0 + 8005116: 75fb strb r3, [r7, #23] + count = SUBGHZ_DEFAULT_TIMEOUT * SUBGHZ_RFBUSY_LOOP_TIME; + 8005118: 4b12 ldr r3, [pc, #72] @ (8005164 ) + 800511a: 681a ldr r2, [r3, #0] + 800511c: 4613 mov r3, r2 + 800511e: 005b lsls r3, r3, #1 + 8005120: 4413 add r3, r2 + 8005122: 00db lsls r3, r3, #3 + 8005124: 0d1b lsrs r3, r3, #20 + 8005126: 2264 movs r2, #100 @ 0x64 + 8005128: fb02 f303 mul.w r3, r2, r3 + 800512c: 60fb str r3, [r7, #12] + + /* Wait until Busy signal is set */ + do + { + mask = LL_PWR_IsActiveFlag_RFBUSYMS(); + 800512e: f7ff fba1 bl 8004874 + 8005132: 6138 str r0, [r7, #16] + + if (count == 0U) + 8005134: 68fb ldr r3, [r7, #12] + 8005136: 2b00 cmp r3, #0 + 8005138: d105 bne.n 8005146 + { + status = HAL_ERROR; + 800513a: 2301 movs r3, #1 + 800513c: 75fb strb r3, [r7, #23] + hsubghz->ErrorCode = HAL_SUBGHZ_ERROR_RF_BUSY; + 800513e: 687b ldr r3, [r7, #4] + 8005140: 2202 movs r2, #2 + 8005142: 609a str r2, [r3, #8] + break; + 8005144: e009 b.n 800515a + } + count--; + 8005146: 68fb ldr r3, [r7, #12] + 8005148: 3b01 subs r3, #1 + 800514a: 60fb str r3, [r7, #12] + } while ((LL_PWR_IsActiveFlag_RFBUSYS()& mask) == 1UL); + 800514c: f7ff fb80 bl 8004850 + 8005150: 4602 mov r2, r0 + 8005152: 693b ldr r3, [r7, #16] + 8005154: 4013 ands r3, r2 + 8005156: 2b01 cmp r3, #1 + 8005158: d0e9 beq.n 800512e + + return status; + 800515a: 7dfb ldrb r3, [r7, #23] +} + 800515c: 4618 mov r0, r3 + 800515e: 3718 adds r7, #24 + 8005160: 46bd mov sp, r7 + 8005162: bd80 pop {r7, pc} + 8005164: 20000000 .word 0x20000000 + +08005168 : +{ + 8005168: b480 push {r7} + 800516a: b083 sub sp, #12 + 800516c: af00 add r7, sp, #0 + 800516e: 6078 str r0, [r7, #4] + return (uint32_t)(READ_BIT(RCC->CCIPR, USARTx) | (USARTx << 16)); + 8005170: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8005174: f8d3 2088 ldr.w r2, [r3, #136] @ 0x88 + 8005178: 687b ldr r3, [r7, #4] + 800517a: 401a ands r2, r3 + 800517c: 687b ldr r3, [r7, #4] + 800517e: 041b lsls r3, r3, #16 + 8005180: 4313 orrs r3, r2 +} + 8005182: 4618 mov r0, r3 + 8005184: 370c adds r7, #12 + 8005186: 46bd mov sp, r7 + 8005188: bc80 pop {r7} + 800518a: 4770 bx lr + +0800518c : +{ + 800518c: b480 push {r7} + 800518e: b083 sub sp, #12 + 8005190: af00 add r7, sp, #0 + 8005192: 6078 str r0, [r7, #4] + return (uint32_t)(READ_BIT(RCC->CCIPR, LPUARTx)); + 8005194: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8005198: f8d3 2088 ldr.w r2, [r3, #136] @ 0x88 + 800519c: 687b ldr r3, [r7, #4] + 800519e: 4013 ands r3, r2 +} + 80051a0: 4618 mov r0, r3 + 80051a2: 370c adds r7, #12 + 80051a4: 46bd mov sp, r7 + 80051a6: bc80 pop {r7} + 80051a8: 4770 bx lr + +080051aa : + * parameters in the UART_InitTypeDef and initialize the associated handle. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) +{ + 80051aa: b580 push {r7, lr} + 80051ac: b082 sub sp, #8 + 80051ae: af00 add r7, sp, #0 + 80051b0: 6078 str r0, [r7, #4] + /* Check the UART handle allocation */ + if (huart == NULL) + 80051b2: 687b ldr r3, [r7, #4] + 80051b4: 2b00 cmp r3, #0 + 80051b6: d101 bne.n 80051bc + { + return HAL_ERROR; + 80051b8: 2301 movs r3, #1 + 80051ba: e042 b.n 8005242 + { + /* Check the parameters */ + assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance))); + } + + if (huart->gState == HAL_UART_STATE_RESET) + 80051bc: 687b ldr r3, [r7, #4] + 80051be: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 + 80051c2: 2b00 cmp r3, #0 + 80051c4: d106 bne.n 80051d4 + { + /* Allocate lock resource and initialize it */ + huart->Lock = HAL_UNLOCKED; + 80051c6: 687b ldr r3, [r7, #4] + 80051c8: 2200 movs r2, #0 + 80051ca: f883 2084 strb.w r2, [r3, #132] @ 0x84 + + /* Init the low level hardware */ + huart->MspInitCallback(huart); +#else + /* Init the low level hardware : GPIO, CLOCK */ + HAL_UART_MspInit(huart); + 80051ce: 6878 ldr r0, [r7, #4] + 80051d0: f7fc f8d0 bl 8001374 +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + + huart->gState = HAL_UART_STATE_BUSY; + 80051d4: 687b ldr r3, [r7, #4] + 80051d6: 2224 movs r2, #36 @ 0x24 + 80051d8: f8c3 2088 str.w r2, [r3, #136] @ 0x88 + + __HAL_UART_DISABLE(huart); + 80051dc: 687b ldr r3, [r7, #4] + 80051de: 681b ldr r3, [r3, #0] + 80051e0: 681a ldr r2, [r3, #0] + 80051e2: 687b ldr r3, [r7, #4] + 80051e4: 681b ldr r3, [r3, #0] + 80051e6: f022 0201 bic.w r2, r2, #1 + 80051ea: 601a str r2, [r3, #0] + + /* Perform advanced settings configuration */ + /* For some items, configuration requires to be done prior TE and RE bits are set */ + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) + 80051ec: 687b ldr r3, [r7, #4] + 80051ee: 6a9b ldr r3, [r3, #40] @ 0x28 + 80051f0: 2b00 cmp r3, #0 + 80051f2: d002 beq.n 80051fa + { + UART_AdvFeatureConfig(huart); + 80051f4: 6878 ldr r0, [r7, #4] + 80051f6: f001 f813 bl 8006220 + } + + /* Set the UART Communication parameters */ + if (UART_SetConfig(huart) == HAL_ERROR) + 80051fa: 6878 ldr r0, [r7, #4] + 80051fc: f000 fd9c bl 8005d38 + 8005200: 4603 mov r3, r0 + 8005202: 2b01 cmp r3, #1 + 8005204: d101 bne.n 800520a + { + return HAL_ERROR; + 8005206: 2301 movs r3, #1 + 8005208: e01b b.n 8005242 + } + + /* In asynchronous mode, the following bits must be kept cleared: + - LINEN and CLKEN bits in the USART_CR2 register, + - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ + CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + 800520a: 687b ldr r3, [r7, #4] + 800520c: 681b ldr r3, [r3, #0] + 800520e: 685a ldr r2, [r3, #4] + 8005210: 687b ldr r3, [r7, #4] + 8005212: 681b ldr r3, [r3, #0] + 8005214: f422 4290 bic.w r2, r2, #18432 @ 0x4800 + 8005218: 605a str r2, [r3, #4] + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); + 800521a: 687b ldr r3, [r7, #4] + 800521c: 681b ldr r3, [r3, #0] + 800521e: 689a ldr r2, [r3, #8] + 8005220: 687b ldr r3, [r7, #4] + 8005222: 681b ldr r3, [r3, #0] + 8005224: f022 022a bic.w r2, r2, #42 @ 0x2a + 8005228: 609a str r2, [r3, #8] + + __HAL_UART_ENABLE(huart); + 800522a: 687b ldr r3, [r7, #4] + 800522c: 681b ldr r3, [r3, #0] + 800522e: 681a ldr r2, [r3, #0] + 8005230: 687b ldr r3, [r7, #4] + 8005232: 681b ldr r3, [r3, #0] + 8005234: f042 0201 orr.w r2, r2, #1 + 8005238: 601a str r2, [r3, #0] + + /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ + return (UART_CheckIdleState(huart)); + 800523a: 6878 ldr r0, [r7, #4] + 800523c: f001 f891 bl 8006362 + 8005240: 4603 mov r3, r0 +} + 8005242: 4618 mov r0, r3 + 8005244: 3708 adds r7, #8 + 8005246: 46bd mov sp, r7 + 8005248: bd80 pop {r7, pc} + +0800524a : + * @param Size Amount of data elements (u8 or u16) to be sent. + * @param Timeout Timeout duration. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + 800524a: b580 push {r7, lr} + 800524c: b08a sub sp, #40 @ 0x28 + 800524e: af02 add r7, sp, #8 + 8005250: 60f8 str r0, [r7, #12] + 8005252: 60b9 str r1, [r7, #8] + 8005254: 603b str r3, [r7, #0] + 8005256: 4613 mov r3, r2 + 8005258: 80fb strh r3, [r7, #6] + const uint8_t *pdata8bits; + const uint16_t *pdata16bits; + uint32_t tickstart; + + /* Check that a Tx process is not already ongoing */ + if (huart->gState == HAL_UART_STATE_READY) + 800525a: 68fb ldr r3, [r7, #12] + 800525c: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 + 8005260: 2b20 cmp r3, #32 + 8005262: f040 8086 bne.w 8005372 + { + if ((pData == NULL) || (Size == 0U)) + 8005266: 68bb ldr r3, [r7, #8] + 8005268: 2b00 cmp r3, #0 + 800526a: d002 beq.n 8005272 + 800526c: 88fb ldrh r3, [r7, #6] + 800526e: 2b00 cmp r3, #0 + 8005270: d101 bne.n 8005276 + { + return HAL_ERROR; + 8005272: 2301 movs r3, #1 + 8005274: e07e b.n 8005374 + return HAL_ERROR; + } + } + +#endif /* CORE_CM0PLUS */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + 8005276: 68fb ldr r3, [r7, #12] + 8005278: 2200 movs r2, #0 + 800527a: f8c3 2090 str.w r2, [r3, #144] @ 0x90 + huart->gState = HAL_UART_STATE_BUSY_TX; + 800527e: 68fb ldr r3, [r7, #12] + 8005280: 2221 movs r2, #33 @ 0x21 + 8005282: f8c3 2088 str.w r2, [r3, #136] @ 0x88 + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + 8005286: f7fb fcdf bl 8000c48 + 800528a: 6178 str r0, [r7, #20] + + huart->TxXferSize = Size; + 800528c: 68fb ldr r3, [r7, #12] + 800528e: 88fa ldrh r2, [r7, #6] + 8005290: f8a3 2054 strh.w r2, [r3, #84] @ 0x54 + huart->TxXferCount = Size; + 8005294: 68fb ldr r3, [r7, #12] + 8005296: 88fa ldrh r2, [r7, #6] + 8005298: f8a3 2056 strh.w r2, [r3, #86] @ 0x56 + + /* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + 800529c: 68fb ldr r3, [r7, #12] + 800529e: 689b ldr r3, [r3, #8] + 80052a0: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 + 80052a4: d108 bne.n 80052b8 + 80052a6: 68fb ldr r3, [r7, #12] + 80052a8: 691b ldr r3, [r3, #16] + 80052aa: 2b00 cmp r3, #0 + 80052ac: d104 bne.n 80052b8 + { + pdata8bits = NULL; + 80052ae: 2300 movs r3, #0 + 80052b0: 61fb str r3, [r7, #28] + pdata16bits = (const uint16_t *) pData; + 80052b2: 68bb ldr r3, [r7, #8] + 80052b4: 61bb str r3, [r7, #24] + 80052b6: e003 b.n 80052c0 + } + else + { + pdata8bits = pData; + 80052b8: 68bb ldr r3, [r7, #8] + 80052ba: 61fb str r3, [r7, #28] + pdata16bits = NULL; + 80052bc: 2300 movs r3, #0 + 80052be: 61bb str r3, [r7, #24] + } + + while (huart->TxXferCount > 0U) + 80052c0: e03a b.n 8005338 + { + if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) + 80052c2: 683b ldr r3, [r7, #0] + 80052c4: 9300 str r3, [sp, #0] + 80052c6: 697b ldr r3, [r7, #20] + 80052c8: 2200 movs r2, #0 + 80052ca: 2180 movs r1, #128 @ 0x80 + 80052cc: 68f8 ldr r0, [r7, #12] + 80052ce: f001 f8f2 bl 80064b6 + 80052d2: 4603 mov r3, r0 + 80052d4: 2b00 cmp r3, #0 + 80052d6: d005 beq.n 80052e4 + { + + huart->gState = HAL_UART_STATE_READY; + 80052d8: 68fb ldr r3, [r7, #12] + 80052da: 2220 movs r2, #32 + 80052dc: f8c3 2088 str.w r2, [r3, #136] @ 0x88 + + return HAL_TIMEOUT; + 80052e0: 2303 movs r3, #3 + 80052e2: e047 b.n 8005374 + } + if (pdata8bits == NULL) + 80052e4: 69fb ldr r3, [r7, #28] + 80052e6: 2b00 cmp r3, #0 + 80052e8: d10b bne.n 8005302 + { + huart->Instance->TDR = (uint16_t)(*pdata16bits & 0x01FFU); + 80052ea: 69bb ldr r3, [r7, #24] + 80052ec: 881b ldrh r3, [r3, #0] + 80052ee: 461a mov r2, r3 + 80052f0: 68fb ldr r3, [r7, #12] + 80052f2: 681b ldr r3, [r3, #0] + 80052f4: f3c2 0208 ubfx r2, r2, #0, #9 + 80052f8: 629a str r2, [r3, #40] @ 0x28 + pdata16bits++; + 80052fa: 69bb ldr r3, [r7, #24] + 80052fc: 3302 adds r3, #2 + 80052fe: 61bb str r3, [r7, #24] + 8005300: e007 b.n 8005312 + } + else + { + huart->Instance->TDR = (uint8_t)(*pdata8bits & 0xFFU); + 8005302: 69fb ldr r3, [r7, #28] + 8005304: 781a ldrb r2, [r3, #0] + 8005306: 68fb ldr r3, [r7, #12] + 8005308: 681b ldr r3, [r3, #0] + 800530a: 629a str r2, [r3, #40] @ 0x28 + pdata8bits++; + 800530c: 69fb ldr r3, [r7, #28] + 800530e: 3301 adds r3, #1 + 8005310: 61fb str r3, [r7, #28] + } + if ((huart->gState & HAL_UART_STATE_BUSY_TX) == HAL_UART_STATE_BUSY_TX) + 8005312: 68fb ldr r3, [r7, #12] + 8005314: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 + 8005318: f003 0321 and.w r3, r3, #33 @ 0x21 + 800531c: 2b21 cmp r3, #33 @ 0x21 + 800531e: d109 bne.n 8005334 + { + huart->TxXferCount--; + 8005320: 68fb ldr r3, [r7, #12] + 8005322: f8b3 3056 ldrh.w r3, [r3, #86] @ 0x56 + 8005326: b29b uxth r3, r3 + 8005328: 3b01 subs r3, #1 + 800532a: b29a uxth r2, r3 + 800532c: 68fb ldr r3, [r7, #12] + 800532e: f8a3 2056 strh.w r2, [r3, #86] @ 0x56 + 8005332: e001 b.n 8005338 + } + else + { + /* Process was aborted during the transmission */ + return HAL_ERROR; + 8005334: 2301 movs r3, #1 + 8005336: e01d b.n 8005374 + while (huart->TxXferCount > 0U) + 8005338: 68fb ldr r3, [r7, #12] + 800533a: f8b3 3056 ldrh.w r3, [r3, #86] @ 0x56 + 800533e: b29b uxth r3, r3 + 8005340: 2b00 cmp r3, #0 + 8005342: d1be bne.n 80052c2 + } + } + + if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) + 8005344: 683b ldr r3, [r7, #0] + 8005346: 9300 str r3, [sp, #0] + 8005348: 697b ldr r3, [r7, #20] + 800534a: 2200 movs r2, #0 + 800534c: 2140 movs r1, #64 @ 0x40 + 800534e: 68f8 ldr r0, [r7, #12] + 8005350: f001 f8b1 bl 80064b6 + 8005354: 4603 mov r3, r0 + 8005356: 2b00 cmp r3, #0 + 8005358: d005 beq.n 8005366 + { + huart->gState = HAL_UART_STATE_READY; + 800535a: 68fb ldr r3, [r7, #12] + 800535c: 2220 movs r2, #32 + 800535e: f8c3 2088 str.w r2, [r3, #136] @ 0x88 + + return HAL_TIMEOUT; + 8005362: 2303 movs r3, #3 + 8005364: e006 b.n 8005374 + } + + /* At end of Tx process, restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + 8005366: 68fb ldr r3, [r7, #12] + 8005368: 2220 movs r2, #32 + 800536a: f8c3 2088 str.w r2, [r3, #136] @ 0x88 + + return HAL_OK; + 800536e: 2300 movs r3, #0 + 8005370: e000 b.n 8005374 + } + else + { + return HAL_BUSY; + 8005372: 2302 movs r3, #2 + } +} + 8005374: 4618 mov r0, r3 + 8005376: 3720 adds r7, #32 + 8005378: 46bd mov sp, r7 + 800537a: bd80 pop {r7, pc} + +0800537c : + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + 800537c: b580 push {r7, lr} + 800537e: b08a sub sp, #40 @ 0x28 + 8005380: af00 add r7, sp, #0 + 8005382: 60f8 str r0, [r7, #12] + 8005384: 60b9 str r1, [r7, #8] + 8005386: 4613 mov r3, r2 + 8005388: 80fb strh r3, [r7, #6] + /* Check that a Rx process is not already ongoing */ + if (huart->RxState == HAL_UART_STATE_READY) + 800538a: 68fb ldr r3, [r7, #12] + 800538c: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c + 8005390: 2b20 cmp r3, #32 + 8005392: d137 bne.n 8005404 + { + if ((pData == NULL) || (Size == 0U)) + 8005394: 68bb ldr r3, [r7, #8] + 8005396: 2b00 cmp r3, #0 + 8005398: d002 beq.n 80053a0 + 800539a: 88fb ldrh r3, [r7, #6] + 800539c: 2b00 cmp r3, #0 + 800539e: d101 bne.n 80053a4 + { + return HAL_ERROR; + 80053a0: 2301 movs r3, #1 + 80053a2: e030 b.n 8005406 + } + } + +#endif /* CORE_CM0PLUS */ + /* Set Reception type to Standard reception */ + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + 80053a4: 68fb ldr r3, [r7, #12] + 80053a6: 2200 movs r2, #0 + 80053a8: 66da str r2, [r3, #108] @ 0x6c + + if (!(IS_LPUART_INSTANCE(huart->Instance))) + 80053aa: 68fb ldr r3, [r7, #12] + 80053ac: 681b ldr r3, [r3, #0] + 80053ae: 4a18 ldr r2, [pc, #96] @ (8005410 ) + 80053b0: 4293 cmp r3, r2 + 80053b2: d01f beq.n 80053f4 + { + /* Check that USART RTOEN bit is set */ + if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) + 80053b4: 68fb ldr r3, [r7, #12] + 80053b6: 681b ldr r3, [r3, #0] + 80053b8: 685b ldr r3, [r3, #4] + 80053ba: f403 0300 and.w r3, r3, #8388608 @ 0x800000 + 80053be: 2b00 cmp r3, #0 + 80053c0: d018 beq.n 80053f4 + { + /* Enable the UART Receiver Timeout Interrupt */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RTOIE); + 80053c2: 68fb ldr r3, [r7, #12] + 80053c4: 681b ldr r3, [r3, #0] + 80053c6: 617b str r3, [r7, #20] + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 80053c8: 697b ldr r3, [r7, #20] + 80053ca: e853 3f00 ldrex r3, [r3] + 80053ce: 613b str r3, [r7, #16] + return(result); + 80053d0: 693b ldr r3, [r7, #16] + 80053d2: f043 6380 orr.w r3, r3, #67108864 @ 0x4000000 + 80053d6: 627b str r3, [r7, #36] @ 0x24 + 80053d8: 68fb ldr r3, [r7, #12] + 80053da: 681b ldr r3, [r3, #0] + 80053dc: 461a mov r2, r3 + 80053de: 6a7b ldr r3, [r7, #36] @ 0x24 + 80053e0: 623b str r3, [r7, #32] + 80053e2: 61fa str r2, [r7, #28] + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 80053e4: 69f9 ldr r1, [r7, #28] + 80053e6: 6a3a ldr r2, [r7, #32] + 80053e8: e841 2300 strex r3, r2, [r1] + 80053ec: 61bb str r3, [r7, #24] + return(result); + 80053ee: 69bb ldr r3, [r7, #24] + 80053f0: 2b00 cmp r3, #0 + 80053f2: d1e6 bne.n 80053c2 + } + } + + return (UART_Start_Receive_IT(huart, pData, Size)); + 80053f4: 88fb ldrh r3, [r7, #6] + 80053f6: 461a mov r2, r3 + 80053f8: 68b9 ldr r1, [r7, #8] + 80053fa: 68f8 ldr r0, [r7, #12] + 80053fc: f001 f8c8 bl 8006590 + 8005400: 4603 mov r3, r0 + 8005402: e000 b.n 8005406 + } + else + { + return HAL_BUSY; + 8005404: 2302 movs r3, #2 + } +} + 8005406: 4618 mov r0, r3 + 8005408: 3728 adds r7, #40 @ 0x28 + 800540a: 46bd mov sp, r7 + 800540c: bd80 pop {r7, pc} + 800540e: bf00 nop + 8005410: 40008000 .word 0x40008000 + +08005414 : + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be sent. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size) +{ + 8005414: b580 push {r7, lr} + 8005416: b08a sub sp, #40 @ 0x28 + 8005418: af00 add r7, sp, #0 + 800541a: 60f8 str r0, [r7, #12] + 800541c: 60b9 str r1, [r7, #8] + 800541e: 4613 mov r3, r2 + 8005420: 80fb strh r3, [r7, #6] + /* Check that a Tx process is not already ongoing */ + if (huart->gState == HAL_UART_STATE_READY) + 8005422: 68fb ldr r3, [r7, #12] + 8005424: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 + 8005428: 2b20 cmp r3, #32 + 800542a: d167 bne.n 80054fc + { + if ((pData == NULL) || (Size == 0U)) + 800542c: 68bb ldr r3, [r7, #8] + 800542e: 2b00 cmp r3, #0 + 8005430: d002 beq.n 8005438 + 8005432: 88fb ldrh r3, [r7, #6] + 8005434: 2b00 cmp r3, #0 + 8005436: d101 bne.n 800543c + { + return HAL_ERROR; + 8005438: 2301 movs r3, #1 + 800543a: e060 b.n 80054fe + return HAL_ERROR; + } + } + +#endif /* CORE_CM0PLUS */ + huart->pTxBuffPtr = pData; + 800543c: 68fb ldr r3, [r7, #12] + 800543e: 68ba ldr r2, [r7, #8] + 8005440: 651a str r2, [r3, #80] @ 0x50 + huart->TxXferSize = Size; + 8005442: 68fb ldr r3, [r7, #12] + 8005444: 88fa ldrh r2, [r7, #6] + 8005446: f8a3 2054 strh.w r2, [r3, #84] @ 0x54 + huart->TxXferCount = Size; + 800544a: 68fb ldr r3, [r7, #12] + 800544c: 88fa ldrh r2, [r7, #6] + 800544e: f8a3 2056 strh.w r2, [r3, #86] @ 0x56 + + huart->ErrorCode = HAL_UART_ERROR_NONE; + 8005452: 68fb ldr r3, [r7, #12] + 8005454: 2200 movs r2, #0 + 8005456: f8c3 2090 str.w r2, [r3, #144] @ 0x90 + huart->gState = HAL_UART_STATE_BUSY_TX; + 800545a: 68fb ldr r3, [r7, #12] + 800545c: 2221 movs r2, #33 @ 0x21 + 800545e: f8c3 2088 str.w r2, [r3, #136] @ 0x88 + + if (huart->hdmatx != NULL) + 8005462: 68fb ldr r3, [r7, #12] + 8005464: 6fdb ldr r3, [r3, #124] @ 0x7c + 8005466: 2b00 cmp r3, #0 + 8005468: d028 beq.n 80054bc + { + /* Set the UART DMA transfer complete callback */ + huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt; + 800546a: 68fb ldr r3, [r7, #12] + 800546c: 6fdb ldr r3, [r3, #124] @ 0x7c + 800546e: 4a26 ldr r2, [pc, #152] @ (8005508 ) + 8005470: 62da str r2, [r3, #44] @ 0x2c + + /* Set the UART DMA Half transfer complete callback */ + huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt; + 8005472: 68fb ldr r3, [r7, #12] + 8005474: 6fdb ldr r3, [r3, #124] @ 0x7c + 8005476: 4a25 ldr r2, [pc, #148] @ (800550c ) + 8005478: 631a str r2, [r3, #48] @ 0x30 + + /* Set the DMA error callback */ + huart->hdmatx->XferErrorCallback = UART_DMAError; + 800547a: 68fb ldr r3, [r7, #12] + 800547c: 6fdb ldr r3, [r3, #124] @ 0x7c + 800547e: 4a24 ldr r2, [pc, #144] @ (8005510 ) + 8005480: 635a str r2, [r3, #52] @ 0x34 + + /* Set the DMA abort callback */ + huart->hdmatx->XferAbortCallback = NULL; + 8005482: 68fb ldr r3, [r7, #12] + 8005484: 6fdb ldr r3, [r3, #124] @ 0x7c + 8005486: 2200 movs r2, #0 + 8005488: 639a str r2, [r3, #56] @ 0x38 + + /* Enable the UART transmit DMA channel */ + if (HAL_DMA_Start_IT(huart->hdmatx, (uint32_t)huart->pTxBuffPtr, (uint32_t)&huart->Instance->TDR, Size) != HAL_OK) + 800548a: 68fb ldr r3, [r7, #12] + 800548c: 6fd8 ldr r0, [r3, #124] @ 0x7c + 800548e: 68fb ldr r3, [r7, #12] + 8005490: 6d1b ldr r3, [r3, #80] @ 0x50 + 8005492: 4619 mov r1, r3 + 8005494: 68fb ldr r3, [r7, #12] + 8005496: 681b ldr r3, [r3, #0] + 8005498: 3328 adds r3, #40 @ 0x28 + 800549a: 461a mov r2, r3 + 800549c: 88fb ldrh r3, [r7, #6] + 800549e: f7fc fce3 bl 8001e68 + 80054a2: 4603 mov r3, r0 + 80054a4: 2b00 cmp r3, #0 + 80054a6: d009 beq.n 80054bc + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + 80054a8: 68fb ldr r3, [r7, #12] + 80054aa: 2210 movs r2, #16 + 80054ac: f8c3 2090 str.w r2, [r3, #144] @ 0x90 + + /* Restore huart->gState to ready */ + huart->gState = HAL_UART_STATE_READY; + 80054b0: 68fb ldr r3, [r7, #12] + 80054b2: 2220 movs r2, #32 + 80054b4: f8c3 2088 str.w r2, [r3, #136] @ 0x88 + + return HAL_ERROR; + 80054b8: 2301 movs r3, #1 + 80054ba: e020 b.n 80054fe + } + } + /* Clear the TC flag in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF); + 80054bc: 68fb ldr r3, [r7, #12] + 80054be: 681b ldr r3, [r3, #0] + 80054c0: 2240 movs r2, #64 @ 0x40 + 80054c2: 621a str r2, [r3, #32] + + /* Enable the DMA transfer for transmit request by setting the DMAT bit + in the UART CR3 register */ + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); + 80054c4: 68fb ldr r3, [r7, #12] + 80054c6: 681b ldr r3, [r3, #0] + 80054c8: 3308 adds r3, #8 + 80054ca: 617b str r3, [r7, #20] + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 80054cc: 697b ldr r3, [r7, #20] + 80054ce: e853 3f00 ldrex r3, [r3] + 80054d2: 613b str r3, [r7, #16] + return(result); + 80054d4: 693b ldr r3, [r7, #16] + 80054d6: f043 0380 orr.w r3, r3, #128 @ 0x80 + 80054da: 627b str r3, [r7, #36] @ 0x24 + 80054dc: 68fb ldr r3, [r7, #12] + 80054de: 681b ldr r3, [r3, #0] + 80054e0: 3308 adds r3, #8 + 80054e2: 6a7a ldr r2, [r7, #36] @ 0x24 + 80054e4: 623a str r2, [r7, #32] + 80054e6: 61fb str r3, [r7, #28] + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 80054e8: 69f9 ldr r1, [r7, #28] + 80054ea: 6a3a ldr r2, [r7, #32] + 80054ec: e841 2300 strex r3, r2, [r1] + 80054f0: 61bb str r3, [r7, #24] + return(result); + 80054f2: 69bb ldr r3, [r7, #24] + 80054f4: 2b00 cmp r3, #0 + 80054f6: d1e5 bne.n 80054c4 + + return HAL_OK; + 80054f8: 2300 movs r3, #0 + 80054fa: e000 b.n 80054fe + } + else + { + return HAL_BUSY; + 80054fc: 2302 movs r3, #2 + } +} + 80054fe: 4618 mov r0, r3 + 8005500: 3728 adds r7, #40 @ 0x28 + 8005502: 46bd mov sp, r7 + 8005504: bd80 pop {r7, pc} + 8005506: bf00 nop + 8005508: 0800691b .word 0x0800691b + 800550c: 080069ad .word 0x080069ad + 8005510: 080069c9 .word 0x080069c9 + +08005514 : + * - Set handle State to READY + * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart) +{ + 8005514: b580 push {r7, lr} + 8005516: b09a sub sp, #104 @ 0x68 + 8005518: af00 add r7, sp, #0 + 800551a: 6078 str r0, [r7, #4] + /* Disable PEIE, EIE, RXNEIE and RXFTIE interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE)); + 800551c: 687b ldr r3, [r7, #4] + 800551e: 681b ldr r3, [r3, #0] + 8005520: 64bb str r3, [r7, #72] @ 0x48 + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 8005522: 6cbb ldr r3, [r7, #72] @ 0x48 + 8005524: e853 3f00 ldrex r3, [r3] + 8005528: 647b str r3, [r7, #68] @ 0x44 + return(result); + 800552a: 6c7b ldr r3, [r7, #68] @ 0x44 + 800552c: f423 7390 bic.w r3, r3, #288 @ 0x120 + 8005530: 667b str r3, [r7, #100] @ 0x64 + 8005532: 687b ldr r3, [r7, #4] + 8005534: 681b ldr r3, [r3, #0] + 8005536: 461a mov r2, r3 + 8005538: 6e7b ldr r3, [r7, #100] @ 0x64 + 800553a: 657b str r3, [r7, #84] @ 0x54 + 800553c: 653a str r2, [r7, #80] @ 0x50 + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 800553e: 6d39 ldr r1, [r7, #80] @ 0x50 + 8005540: 6d7a ldr r2, [r7, #84] @ 0x54 + 8005542: e841 2300 strex r3, r2, [r1] + 8005546: 64fb str r3, [r7, #76] @ 0x4c + return(result); + 8005548: 6cfb ldr r3, [r7, #76] @ 0x4c + 800554a: 2b00 cmp r3, #0 + 800554c: d1e6 bne.n 800551c + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE); + 800554e: 687b ldr r3, [r7, #4] + 8005550: 681b ldr r3, [r3, #0] + 8005552: 3308 adds r3, #8 + 8005554: 637b str r3, [r7, #52] @ 0x34 + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 8005556: 6b7b ldr r3, [r7, #52] @ 0x34 + 8005558: e853 3f00 ldrex r3, [r3] + 800555c: 633b str r3, [r7, #48] @ 0x30 + return(result); + 800555e: 6b3b ldr r3, [r7, #48] @ 0x30 + 8005560: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 + 8005564: f023 0301 bic.w r3, r3, #1 + 8005568: 663b str r3, [r7, #96] @ 0x60 + 800556a: 687b ldr r3, [r7, #4] + 800556c: 681b ldr r3, [r3, #0] + 800556e: 3308 adds r3, #8 + 8005570: 6e3a ldr r2, [r7, #96] @ 0x60 + 8005572: 643a str r2, [r7, #64] @ 0x40 + 8005574: 63fb str r3, [r7, #60] @ 0x3c + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 8005576: 6bf9 ldr r1, [r7, #60] @ 0x3c + 8005578: 6c3a ldr r2, [r7, #64] @ 0x40 + 800557a: e841 2300 strex r3, r2, [r1] + 800557e: 63bb str r3, [r7, #56] @ 0x38 + return(result); + 8005580: 6bbb ldr r3, [r7, #56] @ 0x38 + 8005582: 2b00 cmp r3, #0 + 8005584: d1e3 bne.n 800554e + + /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + 8005586: 687b ldr r3, [r7, #4] + 8005588: 6edb ldr r3, [r3, #108] @ 0x6c + 800558a: 2b01 cmp r3, #1 + 800558c: d118 bne.n 80055c0 + { + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); + 800558e: 687b ldr r3, [r7, #4] + 8005590: 681b ldr r3, [r3, #0] + 8005592: 623b str r3, [r7, #32] + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 8005594: 6a3b ldr r3, [r7, #32] + 8005596: e853 3f00 ldrex r3, [r3] + 800559a: 61fb str r3, [r7, #28] + return(result); + 800559c: 69fb ldr r3, [r7, #28] + 800559e: f023 0310 bic.w r3, r3, #16 + 80055a2: 65fb str r3, [r7, #92] @ 0x5c + 80055a4: 687b ldr r3, [r7, #4] + 80055a6: 681b ldr r3, [r3, #0] + 80055a8: 461a mov r2, r3 + 80055aa: 6dfb ldr r3, [r7, #92] @ 0x5c + 80055ac: 62fb str r3, [r7, #44] @ 0x2c + 80055ae: 62ba str r2, [r7, #40] @ 0x28 + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 80055b0: 6ab9 ldr r1, [r7, #40] @ 0x28 + 80055b2: 6afa ldr r2, [r7, #44] @ 0x2c + 80055b4: e841 2300 strex r3, r2, [r1] + 80055b8: 627b str r3, [r7, #36] @ 0x24 + return(result); + 80055ba: 6a7b ldr r3, [r7, #36] @ 0x24 + 80055bc: 2b00 cmp r3, #0 + 80055be: d1e6 bne.n 800558e + } + + /* Abort the UART DMA Rx channel if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + 80055c0: 687b ldr r3, [r7, #4] + 80055c2: 681b ldr r3, [r3, #0] + 80055c4: 689b ldr r3, [r3, #8] + 80055c6: f003 0340 and.w r3, r3, #64 @ 0x40 + 80055ca: 2b40 cmp r3, #64 @ 0x40 + 80055cc: d13b bne.n 8005646 + { + /* Disable the UART DMA Rx request if enabled */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + 80055ce: 687b ldr r3, [r7, #4] + 80055d0: 681b ldr r3, [r3, #0] + 80055d2: 3308 adds r3, #8 + 80055d4: 60fb str r3, [r7, #12] + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 80055d6: 68fb ldr r3, [r7, #12] + 80055d8: e853 3f00 ldrex r3, [r3] + 80055dc: 60bb str r3, [r7, #8] + return(result); + 80055de: 68bb ldr r3, [r7, #8] + 80055e0: f023 0340 bic.w r3, r3, #64 @ 0x40 + 80055e4: 65bb str r3, [r7, #88] @ 0x58 + 80055e6: 687b ldr r3, [r7, #4] + 80055e8: 681b ldr r3, [r3, #0] + 80055ea: 3308 adds r3, #8 + 80055ec: 6dba ldr r2, [r7, #88] @ 0x58 + 80055ee: 61ba str r2, [r7, #24] + 80055f0: 617b str r3, [r7, #20] + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 80055f2: 6979 ldr r1, [r7, #20] + 80055f4: 69ba ldr r2, [r7, #24] + 80055f6: e841 2300 strex r3, r2, [r1] + 80055fa: 613b str r3, [r7, #16] + return(result); + 80055fc: 693b ldr r3, [r7, #16] + 80055fe: 2b00 cmp r3, #0 + 8005600: d1e5 bne.n 80055ce + + /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */ + if (huart->hdmarx != NULL) + 8005602: 687b ldr r3, [r7, #4] + 8005604: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 + 8005608: 2b00 cmp r3, #0 + 800560a: d01c beq.n 8005646 + { + /* Set the UART DMA Abort callback to Null. + No call back execution at end of DMA abort procedure */ + huart->hdmarx->XferAbortCallback = NULL; + 800560c: 687b ldr r3, [r7, #4] + 800560e: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 + 8005612: 2200 movs r2, #0 + 8005614: 639a str r2, [r3, #56] @ 0x38 + + if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK) + 8005616: 687b ldr r3, [r7, #4] + 8005618: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 + 800561c: 4618 mov r0, r3 + 800561e: f7fc fca1 bl 8001f64 + 8005622: 4603 mov r3, r0 + 8005624: 2b00 cmp r3, #0 + 8005626: d00e beq.n 8005646 + { + if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT) + 8005628: 687b ldr r3, [r7, #4] + 800562a: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 + 800562e: 4618 mov r0, r3 + 8005630: f7fc fe1c bl 800226c + 8005634: 4603 mov r3, r0 + 8005636: 2b20 cmp r3, #32 + 8005638: d105 bne.n 8005646 + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + 800563a: 687b ldr r3, [r7, #4] + 800563c: 2210 movs r2, #16 + 800563e: f8c3 2090 str.w r2, [r3, #144] @ 0x90 + + return HAL_TIMEOUT; + 8005642: 2303 movs r3, #3 + 8005644: e013 b.n 800566e + } + } + } + + /* Clear the Error flags in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); + 8005646: 687b ldr r3, [r7, #4] + 8005648: 681b ldr r3, [r3, #0] + 800564a: 220f movs r2, #15 + 800564c: 621a str r2, [r3, #32] + + /* Discard the received data */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + 800564e: 687b ldr r3, [r7, #4] + 8005650: 681b ldr r3, [r3, #0] + 8005652: 699a ldr r2, [r3, #24] + 8005654: 687b ldr r3, [r7, #4] + 8005656: 681b ldr r3, [r3, #0] + 8005658: f042 0208 orr.w r2, r2, #8 + 800565c: 619a str r2, [r3, #24] + + /* Restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + 800565e: 687b ldr r3, [r7, #4] + 8005660: 2220 movs r2, #32 + 8005662: f8c3 208c str.w r2, [r3, #140] @ 0x8c + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + 8005666: 687b ldr r3, [r7, #4] + 8005668: 2200 movs r2, #0 + 800566a: 66da str r2, [r3, #108] @ 0x6c + + return HAL_OK; + 800566c: 2300 movs r3, #0 +} + 800566e: 4618 mov r0, r3 + 8005670: 3768 adds r7, #104 @ 0x68 + 8005672: 46bd mov sp, r7 + 8005674: bd80 pop {r7, pc} + ... + +08005678 : + * @brief Handle UART interrupt request. + * @param huart UART handle. + * @retval None + */ +void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) +{ + 8005678: b580 push {r7, lr} + 800567a: b0ba sub sp, #232 @ 0xe8 + 800567c: af00 add r7, sp, #0 + 800567e: 6078 str r0, [r7, #4] + uint32_t isrflags = READ_REG(huart->Instance->ISR); + 8005680: 687b ldr r3, [r7, #4] + 8005682: 681b ldr r3, [r3, #0] + 8005684: 69db ldr r3, [r3, #28] + 8005686: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4 + uint32_t cr1its = READ_REG(huart->Instance->CR1); + 800568a: 687b ldr r3, [r7, #4] + 800568c: 681b ldr r3, [r3, #0] + 800568e: 681b ldr r3, [r3, #0] + 8005690: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0 + uint32_t cr3its = READ_REG(huart->Instance->CR3); + 8005694: 687b ldr r3, [r7, #4] + 8005696: 681b ldr r3, [r3, #0] + 8005698: 689b ldr r3, [r3, #8] + 800569a: f8c7 30dc str.w r3, [r7, #220] @ 0xdc + + uint32_t errorflags; + uint32_t errorcode; + + /* If no error occurs */ + errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF)); + 800569e: f8d7 20e4 ldr.w r2, [r7, #228] @ 0xe4 + 80056a2: f640 030f movw r3, #2063 @ 0x80f + 80056a6: 4013 ands r3, r2 + 80056a8: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8 + if (errorflags == 0U) + 80056ac: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8 + 80056b0: 2b00 cmp r3, #0 + 80056b2: d11b bne.n 80056ec + { + /* UART in mode Receiver ---------------------------------------------------*/ + if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U) + 80056b4: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 + 80056b8: f003 0320 and.w r3, r3, #32 + 80056bc: 2b00 cmp r3, #0 + 80056be: d015 beq.n 80056ec + && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) + 80056c0: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 + 80056c4: f003 0320 and.w r3, r3, #32 + 80056c8: 2b00 cmp r3, #0 + 80056ca: d105 bne.n 80056d8 + || ((cr3its & USART_CR3_RXFTIE) != 0U))) + 80056cc: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc + 80056d0: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 + 80056d4: 2b00 cmp r3, #0 + 80056d6: d009 beq.n 80056ec + { + if (huart->RxISR != NULL) + 80056d8: 687b ldr r3, [r7, #4] + 80056da: 6f5b ldr r3, [r3, #116] @ 0x74 + 80056dc: 2b00 cmp r3, #0 + 80056de: f000 8300 beq.w 8005ce2 + { + huart->RxISR(huart); + 80056e2: 687b ldr r3, [r7, #4] + 80056e4: 6f5b ldr r3, [r3, #116] @ 0x74 + 80056e6: 6878 ldr r0, [r7, #4] + 80056e8: 4798 blx r3 + } + return; + 80056ea: e2fa b.n 8005ce2 + } + } + + /* If some errors occur */ + if ((errorflags != 0U) + 80056ec: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8 + 80056f0: 2b00 cmp r3, #0 + 80056f2: f000 8123 beq.w 800593c + && ((((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U) + 80056f6: f8d7 20dc ldr.w r2, [r7, #220] @ 0xdc + 80056fa: 4b8d ldr r3, [pc, #564] @ (8005930 ) + 80056fc: 4013 ands r3, r2 + 80056fe: 2b00 cmp r3, #0 + 8005700: d106 bne.n 8005710 + || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE)) != 0U)))) + 8005702: f8d7 20e0 ldr.w r2, [r7, #224] @ 0xe0 + 8005706: 4b8b ldr r3, [pc, #556] @ (8005934 ) + 8005708: 4013 ands r3, r2 + 800570a: 2b00 cmp r3, #0 + 800570c: f000 8116 beq.w 800593c + { + /* UART parity error interrupt occurred -------------------------------------*/ + if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) + 8005710: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 + 8005714: f003 0301 and.w r3, r3, #1 + 8005718: 2b00 cmp r3, #0 + 800571a: d011 beq.n 8005740 + 800571c: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 + 8005720: f403 7380 and.w r3, r3, #256 @ 0x100 + 8005724: 2b00 cmp r3, #0 + 8005726: d00b beq.n 8005740 + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF); + 8005728: 687b ldr r3, [r7, #4] + 800572a: 681b ldr r3, [r3, #0] + 800572c: 2201 movs r2, #1 + 800572e: 621a str r2, [r3, #32] + + huart->ErrorCode |= HAL_UART_ERROR_PE; + 8005730: 687b ldr r3, [r7, #4] + 8005732: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 8005736: f043 0201 orr.w r2, r3, #1 + 800573a: 687b ldr r3, [r7, #4] + 800573c: f8c3 2090 str.w r2, [r3, #144] @ 0x90 + } + + /* UART frame error interrupt occurred --------------------------------------*/ + if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) + 8005740: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 + 8005744: f003 0302 and.w r3, r3, #2 + 8005748: 2b00 cmp r3, #0 + 800574a: d011 beq.n 8005770 + 800574c: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc + 8005750: f003 0301 and.w r3, r3, #1 + 8005754: 2b00 cmp r3, #0 + 8005756: d00b beq.n 8005770 + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF); + 8005758: 687b ldr r3, [r7, #4] + 800575a: 681b ldr r3, [r3, #0] + 800575c: 2202 movs r2, #2 + 800575e: 621a str r2, [r3, #32] + + huart->ErrorCode |= HAL_UART_ERROR_FE; + 8005760: 687b ldr r3, [r7, #4] + 8005762: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 8005766: f043 0204 orr.w r2, r3, #4 + 800576a: 687b ldr r3, [r7, #4] + 800576c: f8c3 2090 str.w r2, [r3, #144] @ 0x90 + } + + /* UART noise error interrupt occurred --------------------------------------*/ + if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) + 8005770: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 + 8005774: f003 0304 and.w r3, r3, #4 + 8005778: 2b00 cmp r3, #0 + 800577a: d011 beq.n 80057a0 + 800577c: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc + 8005780: f003 0301 and.w r3, r3, #1 + 8005784: 2b00 cmp r3, #0 + 8005786: d00b beq.n 80057a0 + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF); + 8005788: 687b ldr r3, [r7, #4] + 800578a: 681b ldr r3, [r3, #0] + 800578c: 2204 movs r2, #4 + 800578e: 621a str r2, [r3, #32] + + huart->ErrorCode |= HAL_UART_ERROR_NE; + 8005790: 687b ldr r3, [r7, #4] + 8005792: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 8005796: f043 0202 orr.w r2, r3, #2 + 800579a: 687b ldr r3, [r7, #4] + 800579c: f8c3 2090 str.w r2, [r3, #144] @ 0x90 + } + + /* UART Over-Run interrupt occurred -----------------------------------------*/ + if (((isrflags & USART_ISR_ORE) != 0U) + 80057a0: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 + 80057a4: f003 0308 and.w r3, r3, #8 + 80057a8: 2b00 cmp r3, #0 + 80057aa: d017 beq.n 80057dc + && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) || + 80057ac: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 + 80057b0: f003 0320 and.w r3, r3, #32 + 80057b4: 2b00 cmp r3, #0 + 80057b6: d105 bne.n 80057c4 + ((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U))) + 80057b8: f8d7 20dc ldr.w r2, [r7, #220] @ 0xdc + 80057bc: 4b5c ldr r3, [pc, #368] @ (8005930 ) + 80057be: 4013 ands r3, r2 + && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) || + 80057c0: 2b00 cmp r3, #0 + 80057c2: d00b beq.n 80057dc + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); + 80057c4: 687b ldr r3, [r7, #4] + 80057c6: 681b ldr r3, [r3, #0] + 80057c8: 2208 movs r2, #8 + 80057ca: 621a str r2, [r3, #32] + + huart->ErrorCode |= HAL_UART_ERROR_ORE; + 80057cc: 687b ldr r3, [r7, #4] + 80057ce: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 80057d2: f043 0208 orr.w r2, r3, #8 + 80057d6: 687b ldr r3, [r7, #4] + 80057d8: f8c3 2090 str.w r2, [r3, #144] @ 0x90 + } + + /* UART Receiver Timeout interrupt occurred ---------------------------------*/ + if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U)) + 80057dc: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 + 80057e0: f403 6300 and.w r3, r3, #2048 @ 0x800 + 80057e4: 2b00 cmp r3, #0 + 80057e6: d012 beq.n 800580e + 80057e8: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 + 80057ec: f003 6380 and.w r3, r3, #67108864 @ 0x4000000 + 80057f0: 2b00 cmp r3, #0 + 80057f2: d00c beq.n 800580e + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF); + 80057f4: 687b ldr r3, [r7, #4] + 80057f6: 681b ldr r3, [r3, #0] + 80057f8: f44f 6200 mov.w r2, #2048 @ 0x800 + 80057fc: 621a str r2, [r3, #32] + + huart->ErrorCode |= HAL_UART_ERROR_RTO; + 80057fe: 687b ldr r3, [r7, #4] + 8005800: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 8005804: f043 0220 orr.w r2, r3, #32 + 8005808: 687b ldr r3, [r7, #4] + 800580a: f8c3 2090 str.w r2, [r3, #144] @ 0x90 + } + + /* Call UART Error Call back function if need be ----------------------------*/ + if (huart->ErrorCode != HAL_UART_ERROR_NONE) + 800580e: 687b ldr r3, [r7, #4] + 8005810: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 8005814: 2b00 cmp r3, #0 + 8005816: f000 8266 beq.w 8005ce6 + { + /* UART in mode Receiver --------------------------------------------------*/ + if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U) + 800581a: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 + 800581e: f003 0320 and.w r3, r3, #32 + 8005822: 2b00 cmp r3, #0 + 8005824: d013 beq.n 800584e + && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) + 8005826: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 + 800582a: f003 0320 and.w r3, r3, #32 + 800582e: 2b00 cmp r3, #0 + 8005830: d105 bne.n 800583e + || ((cr3its & USART_CR3_RXFTIE) != 0U))) + 8005832: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc + 8005836: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 + 800583a: 2b00 cmp r3, #0 + 800583c: d007 beq.n 800584e + { + if (huart->RxISR != NULL) + 800583e: 687b ldr r3, [r7, #4] + 8005840: 6f5b ldr r3, [r3, #116] @ 0x74 + 8005842: 2b00 cmp r3, #0 + 8005844: d003 beq.n 800584e + { + huart->RxISR(huart); + 8005846: 687b ldr r3, [r7, #4] + 8005848: 6f5b ldr r3, [r3, #116] @ 0x74 + 800584a: 6878 ldr r0, [r7, #4] + 800584c: 4798 blx r3 + /* If Error is to be considered as blocking : + - Receiver Timeout error in Reception + - Overrun error in Reception + - any error occurs in DMA mode reception + */ + errorcode = huart->ErrorCode; + 800584e: 687b ldr r3, [r7, #4] + 8005850: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 8005854: f8c7 30d4 str.w r3, [r7, #212] @ 0xd4 + if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) || + 8005858: 687b ldr r3, [r7, #4] + 800585a: 681b ldr r3, [r3, #0] + 800585c: 689b ldr r3, [r3, #8] + 800585e: f003 0340 and.w r3, r3, #64 @ 0x40 + 8005862: 2b40 cmp r3, #64 @ 0x40 + 8005864: d005 beq.n 8005872 + ((errorcode & (HAL_UART_ERROR_RTO | HAL_UART_ERROR_ORE)) != 0U)) + 8005866: f8d7 30d4 ldr.w r3, [r7, #212] @ 0xd4 + 800586a: f003 0328 and.w r3, r3, #40 @ 0x28 + if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) || + 800586e: 2b00 cmp r3, #0 + 8005870: d054 beq.n 800591c + { + /* Blocking error : transfer is aborted + Set the UART state ready to be able to start again the process, + Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ + UART_EndRxTransfer(huart); + 8005872: 6878 ldr r0, [r7, #4] + 8005874: f000 ffec bl 8006850 + + /* Abort the UART DMA Rx channel if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + 8005878: 687b ldr r3, [r7, #4] + 800587a: 681b ldr r3, [r3, #0] + 800587c: 689b ldr r3, [r3, #8] + 800587e: f003 0340 and.w r3, r3, #64 @ 0x40 + 8005882: 2b40 cmp r3, #64 @ 0x40 + 8005884: d146 bne.n 8005914 + { + /* Disable the UART DMA Rx request if enabled */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + 8005886: 687b ldr r3, [r7, #4] + 8005888: 681b ldr r3, [r3, #0] + 800588a: 3308 adds r3, #8 + 800588c: f8c7 309c str.w r3, [r7, #156] @ 0x9c + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 8005890: f8d7 309c ldr.w r3, [r7, #156] @ 0x9c + 8005894: e853 3f00 ldrex r3, [r3] + 8005898: f8c7 3098 str.w r3, [r7, #152] @ 0x98 + return(result); + 800589c: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98 + 80058a0: f023 0340 bic.w r3, r3, #64 @ 0x40 + 80058a4: f8c7 30d0 str.w r3, [r7, #208] @ 0xd0 + 80058a8: 687b ldr r3, [r7, #4] + 80058aa: 681b ldr r3, [r3, #0] + 80058ac: 3308 adds r3, #8 + 80058ae: f8d7 20d0 ldr.w r2, [r7, #208] @ 0xd0 + 80058b2: f8c7 20a8 str.w r2, [r7, #168] @ 0xa8 + 80058b6: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4 + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 80058ba: f8d7 10a4 ldr.w r1, [r7, #164] @ 0xa4 + 80058be: f8d7 20a8 ldr.w r2, [r7, #168] @ 0xa8 + 80058c2: e841 2300 strex r3, r2, [r1] + 80058c6: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0 + return(result); + 80058ca: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0 + 80058ce: 2b00 cmp r3, #0 + 80058d0: d1d9 bne.n 8005886 + + /* Abort the UART DMA Rx channel */ + if (huart->hdmarx != NULL) + 80058d2: 687b ldr r3, [r7, #4] + 80058d4: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 + 80058d8: 2b00 cmp r3, #0 + 80058da: d017 beq.n 800590c + { + /* Set the UART DMA Abort callback : + will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */ + huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError; + 80058dc: 687b ldr r3, [r7, #4] + 80058de: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 + 80058e2: 4a15 ldr r2, [pc, #84] @ (8005938 ) + 80058e4: 639a str r2, [r3, #56] @ 0x38 + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) + 80058e6: 687b ldr r3, [r7, #4] + 80058e8: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 + 80058ec: 4618 mov r0, r3 + 80058ee: f7fc fb97 bl 8002020 + 80058f2: 4603 mov r3, r0 + 80058f4: 2b00 cmp r3, #0 + 80058f6: d019 beq.n 800592c + { + /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */ + huart->hdmarx->XferAbortCallback(huart->hdmarx); + 80058f8: 687b ldr r3, [r7, #4] + 80058fa: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 + 80058fe: 6b9b ldr r3, [r3, #56] @ 0x38 + 8005900: 687a ldr r2, [r7, #4] + 8005902: f8d2 2080 ldr.w r2, [r2, #128] @ 0x80 + 8005906: 4610 mov r0, r2 + 8005908: 4798 blx r3 + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + 800590a: e00f b.n 800592c +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); + 800590c: 6878 ldr r0, [r7, #4] + 800590e: f000 f9fe bl 8005d0e + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + 8005912: e00b b.n 800592c +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); + 8005914: 6878 ldr r0, [r7, #4] + 8005916: f000 f9fa bl 8005d0e + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + 800591a: e007 b.n 800592c +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); + 800591c: 6878 ldr r0, [r7, #4] + 800591e: f000 f9f6 bl 8005d0e +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + 8005922: 687b ldr r3, [r7, #4] + 8005924: 2200 movs r2, #0 + 8005926: f8c3 2090 str.w r2, [r3, #144] @ 0x90 + } + } + return; + 800592a: e1dc b.n 8005ce6 + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + 800592c: bf00 nop + return; + 800592e: e1da b.n 8005ce6 + 8005930: 10000001 .word 0x10000001 + 8005934: 04000120 .word 0x04000120 + 8005938: 08006a39 .word 0x08006a39 + + } /* End if some error occurs */ + + /* Check current reception Mode : + If Reception till IDLE event has been selected : */ + if ((huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + 800593c: 687b ldr r3, [r7, #4] + 800593e: 6edb ldr r3, [r3, #108] @ 0x6c + 8005940: 2b01 cmp r3, #1 + 8005942: f040 8170 bne.w 8005c26 + && ((isrflags & USART_ISR_IDLE) != 0U) + 8005946: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 + 800594a: f003 0310 and.w r3, r3, #16 + 800594e: 2b00 cmp r3, #0 + 8005950: f000 8169 beq.w 8005c26 + && ((cr1its & USART_ISR_IDLE) != 0U)) + 8005954: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 + 8005958: f003 0310 and.w r3, r3, #16 + 800595c: 2b00 cmp r3, #0 + 800595e: f000 8162 beq.w 8005c26 + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + 8005962: 687b ldr r3, [r7, #4] + 8005964: 681b ldr r3, [r3, #0] + 8005966: 2210 movs r2, #16 + 8005968: 621a str r2, [r3, #32] + + /* Check if DMA mode is enabled in UART */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + 800596a: 687b ldr r3, [r7, #4] + 800596c: 681b ldr r3, [r3, #0] + 800596e: 689b ldr r3, [r3, #8] + 8005970: f003 0340 and.w r3, r3, #64 @ 0x40 + 8005974: 2b40 cmp r3, #64 @ 0x40 + 8005976: f040 80d8 bne.w 8005b2a + { + /* DMA mode enabled */ + /* Check received length : If all expected data are received, do nothing, + (DMA cplt callback will be called). + Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ + uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx); + 800597a: 687b ldr r3, [r7, #4] + 800597c: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 + 8005980: 681b ldr r3, [r3, #0] + 8005982: 685b ldr r3, [r3, #4] + 8005984: f8a7 30be strh.w r3, [r7, #190] @ 0xbe + if ((nb_remaining_rx_data > 0U) + 8005988: f8b7 30be ldrh.w r3, [r7, #190] @ 0xbe + 800598c: 2b00 cmp r3, #0 + 800598e: f000 80af beq.w 8005af0 + && (nb_remaining_rx_data < huart->RxXferSize)) + 8005992: 687b ldr r3, [r7, #4] + 8005994: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c + 8005998: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe + 800599c: 429a cmp r2, r3 + 800599e: f080 80a7 bcs.w 8005af0 + { + /* Reception is not complete */ + huart->RxXferCount = nb_remaining_rx_data; + 80059a2: 687b ldr r3, [r7, #4] + 80059a4: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe + 80059a8: f8a3 205e strh.w r2, [r3, #94] @ 0x5e + + /* In Normal mode, end DMA xfer and HAL UART Rx process*/ + if (HAL_IS_BIT_CLR(huart->hdmarx->Instance->CCR, DMA_CCR_CIRC)) + 80059ac: 687b ldr r3, [r7, #4] + 80059ae: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 + 80059b2: 681b ldr r3, [r3, #0] + 80059b4: 681b ldr r3, [r3, #0] + 80059b6: f003 0320 and.w r3, r3, #32 + 80059ba: 2b00 cmp r3, #0 + 80059bc: f040 8087 bne.w 8005ace + { + /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); + 80059c0: 687b ldr r3, [r7, #4] + 80059c2: 681b ldr r3, [r3, #0] + 80059c4: f8c7 3088 str.w r3, [r7, #136] @ 0x88 + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 80059c8: f8d7 3088 ldr.w r3, [r7, #136] @ 0x88 + 80059cc: e853 3f00 ldrex r3, [r3] + 80059d0: f8c7 3084 str.w r3, [r7, #132] @ 0x84 + return(result); + 80059d4: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84 + 80059d8: f423 7380 bic.w r3, r3, #256 @ 0x100 + 80059dc: f8c7 30b8 str.w r3, [r7, #184] @ 0xb8 + 80059e0: 687b ldr r3, [r7, #4] + 80059e2: 681b ldr r3, [r3, #0] + 80059e4: 461a mov r2, r3 + 80059e6: f8d7 30b8 ldr.w r3, [r7, #184] @ 0xb8 + 80059ea: f8c7 3094 str.w r3, [r7, #148] @ 0x94 + 80059ee: f8c7 2090 str.w r2, [r7, #144] @ 0x90 + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 80059f2: f8d7 1090 ldr.w r1, [r7, #144] @ 0x90 + 80059f6: f8d7 2094 ldr.w r2, [r7, #148] @ 0x94 + 80059fa: e841 2300 strex r3, r2, [r1] + 80059fe: f8c7 308c str.w r3, [r7, #140] @ 0x8c + return(result); + 8005a02: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c + 8005a06: 2b00 cmp r3, #0 + 8005a08: d1da bne.n 80059c0 + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 8005a0a: 687b ldr r3, [r7, #4] + 8005a0c: 681b ldr r3, [r3, #0] + 8005a0e: 3308 adds r3, #8 + 8005a10: 677b str r3, [r7, #116] @ 0x74 + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 8005a12: 6f7b ldr r3, [r7, #116] @ 0x74 + 8005a14: e853 3f00 ldrex r3, [r3] + 8005a18: 673b str r3, [r7, #112] @ 0x70 + return(result); + 8005a1a: 6f3b ldr r3, [r7, #112] @ 0x70 + 8005a1c: f023 0301 bic.w r3, r3, #1 + 8005a20: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 + 8005a24: 687b ldr r3, [r7, #4] + 8005a26: 681b ldr r3, [r3, #0] + 8005a28: 3308 adds r3, #8 + 8005a2a: f8d7 20b4 ldr.w r2, [r7, #180] @ 0xb4 + 8005a2e: f8c7 2080 str.w r2, [r7, #128] @ 0x80 + 8005a32: 67fb str r3, [r7, #124] @ 0x7c + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 8005a34: 6ff9 ldr r1, [r7, #124] @ 0x7c + 8005a36: f8d7 2080 ldr.w r2, [r7, #128] @ 0x80 + 8005a3a: e841 2300 strex r3, r2, [r1] + 8005a3e: 67bb str r3, [r7, #120] @ 0x78 + return(result); + 8005a40: 6fbb ldr r3, [r7, #120] @ 0x78 + 8005a42: 2b00 cmp r3, #0 + 8005a44: d1e1 bne.n 8005a0a + + /* Disable the DMA transfer for the receiver request by resetting the DMAR bit + in the UART CR3 register */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + 8005a46: 687b ldr r3, [r7, #4] + 8005a48: 681b ldr r3, [r3, #0] + 8005a4a: 3308 adds r3, #8 + 8005a4c: 663b str r3, [r7, #96] @ 0x60 + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 8005a4e: 6e3b ldr r3, [r7, #96] @ 0x60 + 8005a50: e853 3f00 ldrex r3, [r3] + 8005a54: 65fb str r3, [r7, #92] @ 0x5c + return(result); + 8005a56: 6dfb ldr r3, [r7, #92] @ 0x5c + 8005a58: f023 0340 bic.w r3, r3, #64 @ 0x40 + 8005a5c: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 + 8005a60: 687b ldr r3, [r7, #4] + 8005a62: 681b ldr r3, [r3, #0] + 8005a64: 3308 adds r3, #8 + 8005a66: f8d7 20b0 ldr.w r2, [r7, #176] @ 0xb0 + 8005a6a: 66fa str r2, [r7, #108] @ 0x6c + 8005a6c: 66bb str r3, [r7, #104] @ 0x68 + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 8005a6e: 6eb9 ldr r1, [r7, #104] @ 0x68 + 8005a70: 6efa ldr r2, [r7, #108] @ 0x6c + 8005a72: e841 2300 strex r3, r2, [r1] + 8005a76: 667b str r3, [r7, #100] @ 0x64 + return(result); + 8005a78: 6e7b ldr r3, [r7, #100] @ 0x64 + 8005a7a: 2b00 cmp r3, #0 + 8005a7c: d1e3 bne.n 8005a46 + + /* At end of Rx process, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + 8005a7e: 687b ldr r3, [r7, #4] + 8005a80: 2220 movs r2, #32 + 8005a82: f8c3 208c str.w r2, [r3, #140] @ 0x8c + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + 8005a86: 687b ldr r3, [r7, #4] + 8005a88: 2200 movs r2, #0 + 8005a8a: 66da str r2, [r3, #108] @ 0x6c + + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + 8005a8c: 687b ldr r3, [r7, #4] + 8005a8e: 681b ldr r3, [r3, #0] + 8005a90: 64fb str r3, [r7, #76] @ 0x4c + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 8005a92: 6cfb ldr r3, [r7, #76] @ 0x4c + 8005a94: e853 3f00 ldrex r3, [r3] + 8005a98: 64bb str r3, [r7, #72] @ 0x48 + return(result); + 8005a9a: 6cbb ldr r3, [r7, #72] @ 0x48 + 8005a9c: f023 0310 bic.w r3, r3, #16 + 8005aa0: f8c7 30ac str.w r3, [r7, #172] @ 0xac + 8005aa4: 687b ldr r3, [r7, #4] + 8005aa6: 681b ldr r3, [r3, #0] + 8005aa8: 461a mov r2, r3 + 8005aaa: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac + 8005aae: 65bb str r3, [r7, #88] @ 0x58 + 8005ab0: 657a str r2, [r7, #84] @ 0x54 + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 8005ab2: 6d79 ldr r1, [r7, #84] @ 0x54 + 8005ab4: 6dba ldr r2, [r7, #88] @ 0x58 + 8005ab6: e841 2300 strex r3, r2, [r1] + 8005aba: 653b str r3, [r7, #80] @ 0x50 + return(result); + 8005abc: 6d3b ldr r3, [r7, #80] @ 0x50 + 8005abe: 2b00 cmp r3, #0 + 8005ac0: d1e4 bne.n 8005a8c + + /* Last bytes received, so no need as the abort is immediate */ + (void)HAL_DMA_Abort(huart->hdmarx); + 8005ac2: 687b ldr r3, [r7, #4] + 8005ac4: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 + 8005ac8: 4618 mov r0, r3 + 8005aca: f7fc fa4b bl 8001f64 + } + + /* Initialize type of RxEvent that correspond to RxEvent callback execution; + In this case, Rx Event type is Idle Event */ + huart->RxEventType = HAL_UART_RXEVENT_IDLE; + 8005ace: 687b ldr r3, [r7, #4] + 8005ad0: 2202 movs r2, #2 + 8005ad2: 671a str r2, [r3, #112] @ 0x70 +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); + 8005ad4: 687b ldr r3, [r7, #4] + 8005ad6: f8b3 205c ldrh.w r2, [r3, #92] @ 0x5c + 8005ada: 687b ldr r3, [r7, #4] + 8005adc: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e + 8005ae0: b29b uxth r3, r3 + 8005ae2: 1ad3 subs r3, r2, r3 + 8005ae4: b29b uxth r3, r3 + 8005ae6: 4619 mov r1, r3 + 8005ae8: 6878 ldr r0, [r7, #4] + 8005aea: f000 f919 bl 8005d20 + HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + } + } + return; + 8005aee: e0fc b.n 8005cea + if (nb_remaining_rx_data == huart->RxXferSize) + 8005af0: 687b ldr r3, [r7, #4] + 8005af2: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c + 8005af6: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe + 8005afa: 429a cmp r2, r3 + 8005afc: f040 80f5 bne.w 8005cea + if (HAL_IS_BIT_SET(huart->hdmarx->Instance->CCR, DMA_CCR_CIRC)) + 8005b00: 687b ldr r3, [r7, #4] + 8005b02: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 + 8005b06: 681b ldr r3, [r3, #0] + 8005b08: 681b ldr r3, [r3, #0] + 8005b0a: f003 0320 and.w r3, r3, #32 + 8005b0e: 2b20 cmp r3, #32 + 8005b10: f040 80eb bne.w 8005cea + huart->RxEventType = HAL_UART_RXEVENT_IDLE; + 8005b14: 687b ldr r3, [r7, #4] + 8005b16: 2202 movs r2, #2 + 8005b18: 671a str r2, [r3, #112] @ 0x70 + HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); + 8005b1a: 687b ldr r3, [r7, #4] + 8005b1c: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c + 8005b20: 4619 mov r1, r3 + 8005b22: 6878 ldr r0, [r7, #4] + 8005b24: f000 f8fc bl 8005d20 + return; + 8005b28: e0df b.n 8005cea + else + { + /* DMA mode not enabled */ + /* Check received length : If all expected data are received, do nothing. + Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ + uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount; + 8005b2a: 687b ldr r3, [r7, #4] + 8005b2c: f8b3 205c ldrh.w r2, [r3, #92] @ 0x5c + 8005b30: 687b ldr r3, [r7, #4] + 8005b32: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e + 8005b36: b29b uxth r3, r3 + 8005b38: 1ad3 subs r3, r2, r3 + 8005b3a: f8a7 30ce strh.w r3, [r7, #206] @ 0xce + if ((huart->RxXferCount > 0U) + 8005b3e: 687b ldr r3, [r7, #4] + 8005b40: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e + 8005b44: b29b uxth r3, r3 + 8005b46: 2b00 cmp r3, #0 + 8005b48: f000 80d1 beq.w 8005cee + && (nb_rx_data > 0U)) + 8005b4c: f8b7 30ce ldrh.w r3, [r7, #206] @ 0xce + 8005b50: 2b00 cmp r3, #0 + 8005b52: f000 80cc beq.w 8005cee + { + /* Disable the UART Parity Error Interrupt and RXNE interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); + 8005b56: 687b ldr r3, [r7, #4] + 8005b58: 681b ldr r3, [r3, #0] + 8005b5a: 63bb str r3, [r7, #56] @ 0x38 + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 8005b5c: 6bbb ldr r3, [r7, #56] @ 0x38 + 8005b5e: e853 3f00 ldrex r3, [r3] + 8005b62: 637b str r3, [r7, #52] @ 0x34 + return(result); + 8005b64: 6b7b ldr r3, [r7, #52] @ 0x34 + 8005b66: f423 7390 bic.w r3, r3, #288 @ 0x120 + 8005b6a: f8c7 30c8 str.w r3, [r7, #200] @ 0xc8 + 8005b6e: 687b ldr r3, [r7, #4] + 8005b70: 681b ldr r3, [r3, #0] + 8005b72: 461a mov r2, r3 + 8005b74: f8d7 30c8 ldr.w r3, [r7, #200] @ 0xc8 + 8005b78: 647b str r3, [r7, #68] @ 0x44 + 8005b7a: 643a str r2, [r7, #64] @ 0x40 + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 8005b7c: 6c39 ldr r1, [r7, #64] @ 0x40 + 8005b7e: 6c7a ldr r2, [r7, #68] @ 0x44 + 8005b80: e841 2300 strex r3, r2, [r1] + 8005b84: 63fb str r3, [r7, #60] @ 0x3c + return(result); + 8005b86: 6bfb ldr r3, [r7, #60] @ 0x3c + 8005b88: 2b00 cmp r3, #0 + 8005b8a: d1e4 bne.n 8005b56 + + /* Disable the UART Error Interrupt:(Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); + 8005b8c: 687b ldr r3, [r7, #4] + 8005b8e: 681b ldr r3, [r3, #0] + 8005b90: 3308 adds r3, #8 + 8005b92: 627b str r3, [r7, #36] @ 0x24 + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 8005b94: 6a7b ldr r3, [r7, #36] @ 0x24 + 8005b96: e853 3f00 ldrex r3, [r3] + 8005b9a: 623b str r3, [r7, #32] + return(result); + 8005b9c: 6a3b ldr r3, [r7, #32] + 8005b9e: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 + 8005ba2: f023 0301 bic.w r3, r3, #1 + 8005ba6: f8c7 30c4 str.w r3, [r7, #196] @ 0xc4 + 8005baa: 687b ldr r3, [r7, #4] + 8005bac: 681b ldr r3, [r3, #0] + 8005bae: 3308 adds r3, #8 + 8005bb0: f8d7 20c4 ldr.w r2, [r7, #196] @ 0xc4 + 8005bb4: 633a str r2, [r7, #48] @ 0x30 + 8005bb6: 62fb str r3, [r7, #44] @ 0x2c + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 8005bb8: 6af9 ldr r1, [r7, #44] @ 0x2c + 8005bba: 6b3a ldr r2, [r7, #48] @ 0x30 + 8005bbc: e841 2300 strex r3, r2, [r1] + 8005bc0: 62bb str r3, [r7, #40] @ 0x28 + return(result); + 8005bc2: 6abb ldr r3, [r7, #40] @ 0x28 + 8005bc4: 2b00 cmp r3, #0 + 8005bc6: d1e1 bne.n 8005b8c + + /* Rx process is completed, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + 8005bc8: 687b ldr r3, [r7, #4] + 8005bca: 2220 movs r2, #32 + 8005bcc: f8c3 208c str.w r2, [r3, #140] @ 0x8c + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + 8005bd0: 687b ldr r3, [r7, #4] + 8005bd2: 2200 movs r2, #0 + 8005bd4: 66da str r2, [r3, #108] @ 0x6c + + /* Clear RxISR function pointer */ + huart->RxISR = NULL; + 8005bd6: 687b ldr r3, [r7, #4] + 8005bd8: 2200 movs r2, #0 + 8005bda: 675a str r2, [r3, #116] @ 0x74 + + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + 8005bdc: 687b ldr r3, [r7, #4] + 8005bde: 681b ldr r3, [r3, #0] + 8005be0: 613b str r3, [r7, #16] + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 8005be2: 693b ldr r3, [r7, #16] + 8005be4: e853 3f00 ldrex r3, [r3] + 8005be8: 60fb str r3, [r7, #12] + return(result); + 8005bea: 68fb ldr r3, [r7, #12] + 8005bec: f023 0310 bic.w r3, r3, #16 + 8005bf0: f8c7 30c0 str.w r3, [r7, #192] @ 0xc0 + 8005bf4: 687b ldr r3, [r7, #4] + 8005bf6: 681b ldr r3, [r3, #0] + 8005bf8: 461a mov r2, r3 + 8005bfa: f8d7 30c0 ldr.w r3, [r7, #192] @ 0xc0 + 8005bfe: 61fb str r3, [r7, #28] + 8005c00: 61ba str r2, [r7, #24] + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 8005c02: 69b9 ldr r1, [r7, #24] + 8005c04: 69fa ldr r2, [r7, #28] + 8005c06: e841 2300 strex r3, r2, [r1] + 8005c0a: 617b str r3, [r7, #20] + return(result); + 8005c0c: 697b ldr r3, [r7, #20] + 8005c0e: 2b00 cmp r3, #0 + 8005c10: d1e4 bne.n 8005bdc + + /* Initialize type of RxEvent that correspond to RxEvent callback execution; + In this case, Rx Event type is Idle Event */ + huart->RxEventType = HAL_UART_RXEVENT_IDLE; + 8005c12: 687b ldr r3, [r7, #4] + 8005c14: 2202 movs r2, #2 + 8005c16: 671a str r2, [r3, #112] @ 0x70 +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx complete callback*/ + huart->RxEventCallback(huart, nb_rx_data); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, nb_rx_data); + 8005c18: f8b7 30ce ldrh.w r3, [r7, #206] @ 0xce + 8005c1c: 4619 mov r1, r3 + 8005c1e: 6878 ldr r0, [r7, #4] + 8005c20: f000 f87e bl 8005d20 +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + return; + 8005c24: e063 b.n 8005cee + } + } + + /* UART wakeup from Stop mode interrupt occurred ---------------------------*/ + if (((isrflags & USART_ISR_WUF) != 0U) && ((cr3its & USART_CR3_WUFIE) != 0U)) + 8005c26: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 + 8005c2a: f403 1380 and.w r3, r3, #1048576 @ 0x100000 + 8005c2e: 2b00 cmp r3, #0 + 8005c30: d00e beq.n 8005c50 + 8005c32: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc + 8005c36: f403 0380 and.w r3, r3, #4194304 @ 0x400000 + 8005c3a: 2b00 cmp r3, #0 + 8005c3c: d008 beq.n 8005c50 + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_WUF); + 8005c3e: 687b ldr r3, [r7, #4] + 8005c40: 681b ldr r3, [r3, #0] + 8005c42: f44f 1280 mov.w r2, #1048576 @ 0x100000 + 8005c46: 621a str r2, [r3, #32] +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Wakeup Callback */ + huart->WakeupCallback(huart); +#else + /* Call legacy weak Wakeup Callback */ + HAL_UARTEx_WakeupCallback(huart); + 8005c48: 6878 ldr r0, [r7, #4] + 8005c4a: f001 fc4f bl 80074ec +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + return; + 8005c4e: e051 b.n 8005cf4 + } + + /* UART in mode Transmitter ------------------------------------------------*/ + if (((isrflags & USART_ISR_TXE_TXFNF) != 0U) + 8005c50: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 + 8005c54: f003 0380 and.w r3, r3, #128 @ 0x80 + 8005c58: 2b00 cmp r3, #0 + 8005c5a: d014 beq.n 8005c86 + && (((cr1its & USART_CR1_TXEIE_TXFNFIE) != 0U) + 8005c5c: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 + 8005c60: f003 0380 and.w r3, r3, #128 @ 0x80 + 8005c64: 2b00 cmp r3, #0 + 8005c66: d105 bne.n 8005c74 + || ((cr3its & USART_CR3_TXFTIE) != 0U))) + 8005c68: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc + 8005c6c: f403 0300 and.w r3, r3, #8388608 @ 0x800000 + 8005c70: 2b00 cmp r3, #0 + 8005c72: d008 beq.n 8005c86 + { + if (huart->TxISR != NULL) + 8005c74: 687b ldr r3, [r7, #4] + 8005c76: 6f9b ldr r3, [r3, #120] @ 0x78 + 8005c78: 2b00 cmp r3, #0 + 8005c7a: d03a beq.n 8005cf2 + { + huart->TxISR(huart); + 8005c7c: 687b ldr r3, [r7, #4] + 8005c7e: 6f9b ldr r3, [r3, #120] @ 0x78 + 8005c80: 6878 ldr r0, [r7, #4] + 8005c82: 4798 blx r3 + } + return; + 8005c84: e035 b.n 8005cf2 + } + + /* UART in mode Transmitter (transmission end) -----------------------------*/ + if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U)) + 8005c86: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 + 8005c8a: f003 0340 and.w r3, r3, #64 @ 0x40 + 8005c8e: 2b00 cmp r3, #0 + 8005c90: d009 beq.n 8005ca6 + 8005c92: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 + 8005c96: f003 0340 and.w r3, r3, #64 @ 0x40 + 8005c9a: 2b00 cmp r3, #0 + 8005c9c: d003 beq.n 8005ca6 + { + UART_EndTransmit_IT(huart); + 8005c9e: 6878 ldr r0, [r7, #4] + 8005ca0: f000 fed8 bl 8006a54 + return; + 8005ca4: e026 b.n 8005cf4 + } + + /* UART TX Fifo Empty occurred ----------------------------------------------*/ + if (((isrflags & USART_ISR_TXFE) != 0U) && ((cr1its & USART_CR1_TXFEIE) != 0U)) + 8005ca6: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 + 8005caa: f403 0300 and.w r3, r3, #8388608 @ 0x800000 + 8005cae: 2b00 cmp r3, #0 + 8005cb0: d009 beq.n 8005cc6 + 8005cb2: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 + 8005cb6: f003 4380 and.w r3, r3, #1073741824 @ 0x40000000 + 8005cba: 2b00 cmp r3, #0 + 8005cbc: d003 beq.n 8005cc6 +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Tx Fifo Empty Callback */ + huart->TxFifoEmptyCallback(huart); +#else + /* Call legacy weak Tx Fifo Empty Callback */ + HAL_UARTEx_TxFifoEmptyCallback(huart); + 8005cbe: 6878 ldr r0, [r7, #4] + 8005cc0: f001 fc26 bl 8007510 +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + return; + 8005cc4: e016 b.n 8005cf4 + } + + /* UART RX Fifo Full occurred ----------------------------------------------*/ + if (((isrflags & USART_ISR_RXFF) != 0U) && ((cr1its & USART_CR1_RXFFIE) != 0U)) + 8005cc6: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 + 8005cca: f003 7380 and.w r3, r3, #16777216 @ 0x1000000 + 8005cce: 2b00 cmp r3, #0 + 8005cd0: d010 beq.n 8005cf4 + 8005cd2: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 + 8005cd6: 2b00 cmp r3, #0 + 8005cd8: da0c bge.n 8005cf4 +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Rx Fifo Full Callback */ + huart->RxFifoFullCallback(huart); +#else + /* Call legacy weak Rx Fifo Full Callback */ + HAL_UARTEx_RxFifoFullCallback(huart); + 8005cda: 6878 ldr r0, [r7, #4] + 8005cdc: f001 fc0f bl 80074fe +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + return; + 8005ce0: e008 b.n 8005cf4 + return; + 8005ce2: bf00 nop + 8005ce4: e006 b.n 8005cf4 + return; + 8005ce6: bf00 nop + 8005ce8: e004 b.n 8005cf4 + return; + 8005cea: bf00 nop + 8005cec: e002 b.n 8005cf4 + return; + 8005cee: bf00 nop + 8005cf0: e000 b.n 8005cf4 + return; + 8005cf2: bf00 nop + } +} + 8005cf4: 37e8 adds r7, #232 @ 0xe8 + 8005cf6: 46bd mov sp, r7 + 8005cf8: bd80 pop {r7, pc} + 8005cfa: bf00 nop + +08005cfc : + * @brief Tx Half Transfer completed callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart) +{ + 8005cfc: b480 push {r7} + 8005cfe: b083 sub sp, #12 + 8005d00: af00 add r7, sp, #0 + 8005d02: 6078 str r0, [r7, #4] + UNUSED(huart); + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_UART_TxHalfCpltCallback can be implemented in the user file. + */ +} + 8005d04: bf00 nop + 8005d06: 370c adds r7, #12 + 8005d08: 46bd mov sp, r7 + 8005d0a: bc80 pop {r7} + 8005d0c: 4770 bx lr + +08005d0e : + * @brief UART error callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) +{ + 8005d0e: b480 push {r7} + 8005d10: b083 sub sp, #12 + 8005d12: af00 add r7, sp, #0 + 8005d14: 6078 str r0, [r7, #4] + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_ErrorCallback can be implemented in the user file. + */ +} + 8005d16: bf00 nop + 8005d18: 370c adds r7, #12 + 8005d1a: 46bd mov sp, r7 + 8005d1c: bc80 pop {r7} + 8005d1e: 4770 bx lr + +08005d20 : + * @param Size Number of data available in application reception buffer (indicates a position in + * reception buffer until which, data are available) + * @retval None + */ +__weak void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size) +{ + 8005d20: b480 push {r7} + 8005d22: b083 sub sp, #12 + 8005d24: af00 add r7, sp, #0 + 8005d26: 6078 str r0, [r7, #4] + 8005d28: 460b mov r3, r1 + 8005d2a: 807b strh r3, [r7, #2] + UNUSED(Size); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UARTEx_RxEventCallback can be implemented in the user file. + */ +} + 8005d2c: bf00 nop + 8005d2e: 370c adds r7, #12 + 8005d30: 46bd mov sp, r7 + 8005d32: bc80 pop {r7} + 8005d34: 4770 bx lr + ... + +08005d38 : + * @brief Configure the UART peripheral. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) +{ + 8005d38: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr} + 8005d3c: b08c sub sp, #48 @ 0x30 + 8005d3e: af00 add r7, sp, #0 + 8005d40: 6178 str r0, [r7, #20] + uint32_t tmpreg; + uint16_t brrtemp; + UART_ClockSourceTypeDef clocksource; + uint32_t usartdiv; + HAL_StatusTypeDef ret = HAL_OK; + 8005d42: 2300 movs r3, #0 + 8005d44: f887 302a strb.w r3, [r7, #42] @ 0x2a + * the UART Word Length, Parity, Mode and oversampling: + * set the M bits according to huart->Init.WordLength value + * set PCE and PS bits according to huart->Init.Parity value + * set TE and RE bits according to huart->Init.Mode value + * set OVER8 bit according to huart->Init.OverSampling value */ + tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ; + 8005d48: 697b ldr r3, [r7, #20] + 8005d4a: 689a ldr r2, [r3, #8] + 8005d4c: 697b ldr r3, [r7, #20] + 8005d4e: 691b ldr r3, [r3, #16] + 8005d50: 431a orrs r2, r3 + 8005d52: 697b ldr r3, [r7, #20] + 8005d54: 695b ldr r3, [r3, #20] + 8005d56: 431a orrs r2, r3 + 8005d58: 697b ldr r3, [r7, #20] + 8005d5a: 69db ldr r3, [r3, #28] + 8005d5c: 4313 orrs r3, r2 + 8005d5e: 62fb str r3, [r7, #44] @ 0x2c + MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg); + 8005d60: 697b ldr r3, [r7, #20] + 8005d62: 681b ldr r3, [r3, #0] + 8005d64: 681a ldr r2, [r3, #0] + 8005d66: 4b94 ldr r3, [pc, #592] @ (8005fb8 ) + 8005d68: 4013 ands r3, r2 + 8005d6a: 697a ldr r2, [r7, #20] + 8005d6c: 6812 ldr r2, [r2, #0] + 8005d6e: 6af9 ldr r1, [r7, #44] @ 0x2c + 8005d70: 430b orrs r3, r1 + 8005d72: 6013 str r3, [r2, #0] + + /*-------------------------- USART CR2 Configuration -----------------------*/ + /* Configure the UART Stop Bits: Set STOP[13:12] bits according + * to huart->Init.StopBits value */ + MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); + 8005d74: 697b ldr r3, [r7, #20] + 8005d76: 681b ldr r3, [r3, #0] + 8005d78: 685b ldr r3, [r3, #4] + 8005d7a: f423 5140 bic.w r1, r3, #12288 @ 0x3000 + 8005d7e: 697b ldr r3, [r7, #20] + 8005d80: 68da ldr r2, [r3, #12] + 8005d82: 697b ldr r3, [r7, #20] + 8005d84: 681b ldr r3, [r3, #0] + 8005d86: 430a orrs r2, r1 + 8005d88: 605a str r2, [r3, #4] + /* Configure + * - UART HardWare Flow Control: set CTSE and RTSE bits according + * to huart->Init.HwFlowCtl value + * - one-bit sampling method versus three samples' majority rule according + * to huart->Init.OneBitSampling (not applicable to LPUART) */ + tmpreg = (uint32_t)huart->Init.HwFlowCtl; + 8005d8a: 697b ldr r3, [r7, #20] + 8005d8c: 699b ldr r3, [r3, #24] + 8005d8e: 62fb str r3, [r7, #44] @ 0x2c + + if (!(UART_INSTANCE_LOWPOWER(huart))) + 8005d90: 697b ldr r3, [r7, #20] + 8005d92: 681b ldr r3, [r3, #0] + 8005d94: 4a89 ldr r2, [pc, #548] @ (8005fbc ) + 8005d96: 4293 cmp r3, r2 + 8005d98: d004 beq.n 8005da4 + { + tmpreg |= huart->Init.OneBitSampling; + 8005d9a: 697b ldr r3, [r7, #20] + 8005d9c: 6a1b ldr r3, [r3, #32] + 8005d9e: 6afa ldr r2, [r7, #44] @ 0x2c + 8005da0: 4313 orrs r3, r2 + 8005da2: 62fb str r3, [r7, #44] @ 0x2c + } + MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg); + 8005da4: 697b ldr r3, [r7, #20] + 8005da6: 681b ldr r3, [r3, #0] + 8005da8: 689b ldr r3, [r3, #8] + 8005daa: f023 436e bic.w r3, r3, #3992977408 @ 0xee000000 + 8005dae: f423 6330 bic.w r3, r3, #2816 @ 0xb00 + 8005db2: 697a ldr r2, [r7, #20] + 8005db4: 6812 ldr r2, [r2, #0] + 8005db6: 6af9 ldr r1, [r7, #44] @ 0x2c + 8005db8: 430b orrs r3, r1 + 8005dba: 6093 str r3, [r2, #8] + + /*-------------------------- USART PRESC Configuration -----------------------*/ + /* Configure + * - UART Clock Prescaler : set PRESCALER according to huart->Init.ClockPrescaler value */ + MODIFY_REG(huart->Instance->PRESC, USART_PRESC_PRESCALER, huart->Init.ClockPrescaler); + 8005dbc: 697b ldr r3, [r7, #20] + 8005dbe: 681b ldr r3, [r3, #0] + 8005dc0: 6adb ldr r3, [r3, #44] @ 0x2c + 8005dc2: f023 010f bic.w r1, r3, #15 + 8005dc6: 697b ldr r3, [r7, #20] + 8005dc8: 6a5a ldr r2, [r3, #36] @ 0x24 + 8005dca: 697b ldr r3, [r7, #20] + 8005dcc: 681b ldr r3, [r3, #0] + 8005dce: 430a orrs r2, r1 + 8005dd0: 62da str r2, [r3, #44] @ 0x2c + + /*-------------------------- USART BRR Configuration -----------------------*/ + UART_GETCLOCKSOURCE(huart, clocksource); + 8005dd2: 697b ldr r3, [r7, #20] + 8005dd4: 681b ldr r3, [r3, #0] + 8005dd6: 4a7a ldr r2, [pc, #488] @ (8005fc0 ) + 8005dd8: 4293 cmp r3, r2 + 8005dda: d127 bne.n 8005e2c + 8005ddc: 2003 movs r0, #3 + 8005dde: f7ff f9c3 bl 8005168 + 8005de2: 4603 mov r3, r0 + 8005de4: f5a3 3340 sub.w r3, r3, #196608 @ 0x30000 + 8005de8: 2b03 cmp r3, #3 + 8005dea: d81b bhi.n 8005e24 + 8005dec: a201 add r2, pc, #4 @ (adr r2, 8005df4 ) + 8005dee: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 8005df2: bf00 nop + 8005df4: 08005e05 .word 0x08005e05 + 8005df8: 08005e15 .word 0x08005e15 + 8005dfc: 08005e0d .word 0x08005e0d + 8005e00: 08005e1d .word 0x08005e1d + 8005e04: 2301 movs r3, #1 + 8005e06: f887 302b strb.w r3, [r7, #43] @ 0x2b + 8005e0a: e080 b.n 8005f0e + 8005e0c: 2302 movs r3, #2 + 8005e0e: f887 302b strb.w r3, [r7, #43] @ 0x2b + 8005e12: e07c b.n 8005f0e + 8005e14: 2304 movs r3, #4 + 8005e16: f887 302b strb.w r3, [r7, #43] @ 0x2b + 8005e1a: e078 b.n 8005f0e + 8005e1c: 2308 movs r3, #8 + 8005e1e: f887 302b strb.w r3, [r7, #43] @ 0x2b + 8005e22: e074 b.n 8005f0e + 8005e24: 2310 movs r3, #16 + 8005e26: f887 302b strb.w r3, [r7, #43] @ 0x2b + 8005e2a: e070 b.n 8005f0e + 8005e2c: 697b ldr r3, [r7, #20] + 8005e2e: 681b ldr r3, [r3, #0] + 8005e30: 4a64 ldr r2, [pc, #400] @ (8005fc4 ) + 8005e32: 4293 cmp r3, r2 + 8005e34: d138 bne.n 8005ea8 + 8005e36: 200c movs r0, #12 + 8005e38: f7ff f996 bl 8005168 + 8005e3c: 4603 mov r3, r0 + 8005e3e: f5a3 2340 sub.w r3, r3, #786432 @ 0xc0000 + 8005e42: 2b0c cmp r3, #12 + 8005e44: d82c bhi.n 8005ea0 + 8005e46: a201 add r2, pc, #4 @ (adr r2, 8005e4c ) + 8005e48: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 8005e4c: 08005e81 .word 0x08005e81 + 8005e50: 08005ea1 .word 0x08005ea1 + 8005e54: 08005ea1 .word 0x08005ea1 + 8005e58: 08005ea1 .word 0x08005ea1 + 8005e5c: 08005e91 .word 0x08005e91 + 8005e60: 08005ea1 .word 0x08005ea1 + 8005e64: 08005ea1 .word 0x08005ea1 + 8005e68: 08005ea1 .word 0x08005ea1 + 8005e6c: 08005e89 .word 0x08005e89 + 8005e70: 08005ea1 .word 0x08005ea1 + 8005e74: 08005ea1 .word 0x08005ea1 + 8005e78: 08005ea1 .word 0x08005ea1 + 8005e7c: 08005e99 .word 0x08005e99 + 8005e80: 2300 movs r3, #0 + 8005e82: f887 302b strb.w r3, [r7, #43] @ 0x2b + 8005e86: e042 b.n 8005f0e + 8005e88: 2302 movs r3, #2 + 8005e8a: f887 302b strb.w r3, [r7, #43] @ 0x2b + 8005e8e: e03e b.n 8005f0e + 8005e90: 2304 movs r3, #4 + 8005e92: f887 302b strb.w r3, [r7, #43] @ 0x2b + 8005e96: e03a b.n 8005f0e + 8005e98: 2308 movs r3, #8 + 8005e9a: f887 302b strb.w r3, [r7, #43] @ 0x2b + 8005e9e: e036 b.n 8005f0e + 8005ea0: 2310 movs r3, #16 + 8005ea2: f887 302b strb.w r3, [r7, #43] @ 0x2b + 8005ea6: e032 b.n 8005f0e + 8005ea8: 697b ldr r3, [r7, #20] + 8005eaa: 681b ldr r3, [r3, #0] + 8005eac: 4a43 ldr r2, [pc, #268] @ (8005fbc ) + 8005eae: 4293 cmp r3, r2 + 8005eb0: d12a bne.n 8005f08 + 8005eb2: f44f 6040 mov.w r0, #3072 @ 0xc00 + 8005eb6: f7ff f969 bl 800518c + 8005eba: 4603 mov r3, r0 + 8005ebc: f5b3 6f40 cmp.w r3, #3072 @ 0xc00 + 8005ec0: d01a beq.n 8005ef8 + 8005ec2: f5b3 6f40 cmp.w r3, #3072 @ 0xc00 + 8005ec6: d81b bhi.n 8005f00 + 8005ec8: f5b3 6f00 cmp.w r3, #2048 @ 0x800 + 8005ecc: d00c beq.n 8005ee8 + 8005ece: f5b3 6f00 cmp.w r3, #2048 @ 0x800 + 8005ed2: d815 bhi.n 8005f00 + 8005ed4: 2b00 cmp r3, #0 + 8005ed6: d003 beq.n 8005ee0 + 8005ed8: f5b3 6f80 cmp.w r3, #1024 @ 0x400 + 8005edc: d008 beq.n 8005ef0 + 8005ede: e00f b.n 8005f00 + 8005ee0: 2300 movs r3, #0 + 8005ee2: f887 302b strb.w r3, [r7, #43] @ 0x2b + 8005ee6: e012 b.n 8005f0e + 8005ee8: 2302 movs r3, #2 + 8005eea: f887 302b strb.w r3, [r7, #43] @ 0x2b + 8005eee: e00e b.n 8005f0e + 8005ef0: 2304 movs r3, #4 + 8005ef2: f887 302b strb.w r3, [r7, #43] @ 0x2b + 8005ef6: e00a b.n 8005f0e + 8005ef8: 2308 movs r3, #8 + 8005efa: f887 302b strb.w r3, [r7, #43] @ 0x2b + 8005efe: e006 b.n 8005f0e + 8005f00: 2310 movs r3, #16 + 8005f02: f887 302b strb.w r3, [r7, #43] @ 0x2b + 8005f06: e002 b.n 8005f0e + 8005f08: 2310 movs r3, #16 + 8005f0a: f887 302b strb.w r3, [r7, #43] @ 0x2b + + /* Check LPUART instance */ + if (UART_INSTANCE_LOWPOWER(huart)) + 8005f0e: 697b ldr r3, [r7, #20] + 8005f10: 681b ldr r3, [r3, #0] + 8005f12: 4a2a ldr r2, [pc, #168] @ (8005fbc ) + 8005f14: 4293 cmp r3, r2 + 8005f16: f040 80a4 bne.w 8006062 + { + /* Retrieve frequency clock */ + switch (clocksource) + 8005f1a: f897 302b ldrb.w r3, [r7, #43] @ 0x2b + 8005f1e: 2b08 cmp r3, #8 + 8005f20: d823 bhi.n 8005f6a + 8005f22: a201 add r2, pc, #4 @ (adr r2, 8005f28 ) + 8005f24: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 8005f28: 08005f4d .word 0x08005f4d + 8005f2c: 08005f6b .word 0x08005f6b + 8005f30: 08005f55 .word 0x08005f55 + 8005f34: 08005f6b .word 0x08005f6b + 8005f38: 08005f5b .word 0x08005f5b + 8005f3c: 08005f6b .word 0x08005f6b + 8005f40: 08005f6b .word 0x08005f6b + 8005f44: 08005f6b .word 0x08005f6b + 8005f48: 08005f63 .word 0x08005f63 + { + case UART_CLOCKSOURCE_PCLK1: + pclk = HAL_RCC_GetPCLK1Freq(); + 8005f4c: f7fd fdc6 bl 8003adc + 8005f50: 6278 str r0, [r7, #36] @ 0x24 + break; + 8005f52: e010 b.n 8005f76 + case UART_CLOCKSOURCE_HSI: + pclk = (uint32_t) HSI_VALUE; + 8005f54: 4b1c ldr r3, [pc, #112] @ (8005fc8 ) + 8005f56: 627b str r3, [r7, #36] @ 0x24 + break; + 8005f58: e00d b.n 8005f76 + case UART_CLOCKSOURCE_SYSCLK: + pclk = HAL_RCC_GetSysClockFreq(); + 8005f5a: f7fd fd0b bl 8003974 + 8005f5e: 6278 str r0, [r7, #36] @ 0x24 + break; + 8005f60: e009 b.n 8005f76 + case UART_CLOCKSOURCE_LSE: + pclk = (uint32_t) LSE_VALUE; + 8005f62: f44f 4300 mov.w r3, #32768 @ 0x8000 + 8005f66: 627b str r3, [r7, #36] @ 0x24 + break; + 8005f68: e005 b.n 8005f76 + default: + pclk = 0U; + 8005f6a: 2300 movs r3, #0 + 8005f6c: 627b str r3, [r7, #36] @ 0x24 + ret = HAL_ERROR; + 8005f6e: 2301 movs r3, #1 + 8005f70: f887 302a strb.w r3, [r7, #42] @ 0x2a + break; + 8005f74: bf00 nop + } + + /* If proper clock source reported */ + if (pclk != 0U) + 8005f76: 6a7b ldr r3, [r7, #36] @ 0x24 + 8005f78: 2b00 cmp r3, #0 + 8005f7a: f000 8137 beq.w 80061ec + { + /* Compute clock after Prescaler */ + lpuart_ker_ck_pres = (pclk / UARTPrescTable[huart->Init.ClockPrescaler]); + 8005f7e: 697b ldr r3, [r7, #20] + 8005f80: 6a5b ldr r3, [r3, #36] @ 0x24 + 8005f82: 4a12 ldr r2, [pc, #72] @ (8005fcc ) + 8005f84: f832 3013 ldrh.w r3, [r2, r3, lsl #1] + 8005f88: 461a mov r2, r3 + 8005f8a: 6a7b ldr r3, [r7, #36] @ 0x24 + 8005f8c: fbb3 f3f2 udiv r3, r3, r2 + 8005f90: 61bb str r3, [r7, #24] + + /* Ensure that Frequency clock is in the range [3 * baudrate, 4096 * baudrate] */ + if ((lpuart_ker_ck_pres < (3U * huart->Init.BaudRate)) || + 8005f92: 697b ldr r3, [r7, #20] + 8005f94: 685a ldr r2, [r3, #4] + 8005f96: 4613 mov r3, r2 + 8005f98: 005b lsls r3, r3, #1 + 8005f9a: 4413 add r3, r2 + 8005f9c: 69ba ldr r2, [r7, #24] + 8005f9e: 429a cmp r2, r3 + 8005fa0: d305 bcc.n 8005fae + (lpuart_ker_ck_pres > (4096U * huart->Init.BaudRate))) + 8005fa2: 697b ldr r3, [r7, #20] + 8005fa4: 685b ldr r3, [r3, #4] + 8005fa6: 031b lsls r3, r3, #12 + if ((lpuart_ker_ck_pres < (3U * huart->Init.BaudRate)) || + 8005fa8: 69ba ldr r2, [r7, #24] + 8005faa: 429a cmp r2, r3 + 8005fac: d910 bls.n 8005fd0 + { + ret = HAL_ERROR; + 8005fae: 2301 movs r3, #1 + 8005fb0: f887 302a strb.w r3, [r7, #42] @ 0x2a + 8005fb4: e11a b.n 80061ec + 8005fb6: bf00 nop + 8005fb8: cfff69f3 .word 0xcfff69f3 + 8005fbc: 40008000 .word 0x40008000 + 8005fc0: 40013800 .word 0x40013800 + 8005fc4: 40004400 .word 0x40004400 + 8005fc8: 00f42400 .word 0x00f42400 + 8005fcc: 0800fb54 .word 0x0800fb54 + } + else + { + /* Check computed UsartDiv value is in allocated range + (it is forbidden to write values lower than 0x300 in the LPUART_BRR register) */ + usartdiv = (uint32_t)(UART_DIV_LPUART(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); + 8005fd0: 6a7b ldr r3, [r7, #36] @ 0x24 + 8005fd2: 2200 movs r2, #0 + 8005fd4: 60bb str r3, [r7, #8] + 8005fd6: 60fa str r2, [r7, #12] + 8005fd8: 697b ldr r3, [r7, #20] + 8005fda: 6a5b ldr r3, [r3, #36] @ 0x24 + 8005fdc: 4a8e ldr r2, [pc, #568] @ (8006218 ) + 8005fde: f832 3013 ldrh.w r3, [r2, r3, lsl #1] + 8005fe2: b29b uxth r3, r3 + 8005fe4: 2200 movs r2, #0 + 8005fe6: 603b str r3, [r7, #0] + 8005fe8: 607a str r2, [r7, #4] + 8005fea: e9d7 2300 ldrd r2, r3, [r7] + 8005fee: e9d7 0102 ldrd r0, r1, [r7, #8] + 8005ff2: f7fa f92d bl 8000250 <__aeabi_uldivmod> + 8005ff6: 4602 mov r2, r0 + 8005ff8: 460b mov r3, r1 + 8005ffa: 4610 mov r0, r2 + 8005ffc: 4619 mov r1, r3 + 8005ffe: f04f 0200 mov.w r2, #0 + 8006002: f04f 0300 mov.w r3, #0 + 8006006: 020b lsls r3, r1, #8 + 8006008: ea43 6310 orr.w r3, r3, r0, lsr #24 + 800600c: 0202 lsls r2, r0, #8 + 800600e: 6979 ldr r1, [r7, #20] + 8006010: 6849 ldr r1, [r1, #4] + 8006012: 0849 lsrs r1, r1, #1 + 8006014: 2000 movs r0, #0 + 8006016: 460c mov r4, r1 + 8006018: 4605 mov r5, r0 + 800601a: eb12 0804 adds.w r8, r2, r4 + 800601e: eb43 0905 adc.w r9, r3, r5 + 8006022: 697b ldr r3, [r7, #20] + 8006024: 685b ldr r3, [r3, #4] + 8006026: 2200 movs r2, #0 + 8006028: 469a mov sl, r3 + 800602a: 4693 mov fp, r2 + 800602c: 4652 mov r2, sl + 800602e: 465b mov r3, fp + 8006030: 4640 mov r0, r8 + 8006032: 4649 mov r1, r9 + 8006034: f7fa f90c bl 8000250 <__aeabi_uldivmod> + 8006038: 4602 mov r2, r0 + 800603a: 460b mov r3, r1 + 800603c: 4613 mov r3, r2 + 800603e: 623b str r3, [r7, #32] + if ((usartdiv >= LPUART_BRR_MIN) && (usartdiv <= LPUART_BRR_MAX)) + 8006040: 6a3b ldr r3, [r7, #32] + 8006042: f5b3 7f40 cmp.w r3, #768 @ 0x300 + 8006046: d308 bcc.n 800605a + 8006048: 6a3b ldr r3, [r7, #32] + 800604a: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 + 800604e: d204 bcs.n 800605a + { + huart->Instance->BRR = usartdiv; + 8006050: 697b ldr r3, [r7, #20] + 8006052: 681b ldr r3, [r3, #0] + 8006054: 6a3a ldr r2, [r7, #32] + 8006056: 60da str r2, [r3, #12] + 8006058: e0c8 b.n 80061ec + } + else + { + ret = HAL_ERROR; + 800605a: 2301 movs r3, #1 + 800605c: f887 302a strb.w r3, [r7, #42] @ 0x2a + 8006060: e0c4 b.n 80061ec + } /* if ( (lpuart_ker_ck_pres < (3 * huart->Init.BaudRate) ) || + (lpuart_ker_ck_pres > (4096 * huart->Init.BaudRate) )) */ + } /* if (pclk != 0) */ + } + /* Check UART Over Sampling to set Baud Rate Register */ + else if (huart->Init.OverSampling == UART_OVERSAMPLING_8) + 8006062: 697b ldr r3, [r7, #20] + 8006064: 69db ldr r3, [r3, #28] + 8006066: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 + 800606a: d167 bne.n 800613c + { + switch (clocksource) + 800606c: f897 302b ldrb.w r3, [r7, #43] @ 0x2b + 8006070: 2b08 cmp r3, #8 + 8006072: d828 bhi.n 80060c6 + 8006074: a201 add r2, pc, #4 @ (adr r2, 800607c ) + 8006076: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 800607a: bf00 nop + 800607c: 080060a1 .word 0x080060a1 + 8006080: 080060a9 .word 0x080060a9 + 8006084: 080060b1 .word 0x080060b1 + 8006088: 080060c7 .word 0x080060c7 + 800608c: 080060b7 .word 0x080060b7 + 8006090: 080060c7 .word 0x080060c7 + 8006094: 080060c7 .word 0x080060c7 + 8006098: 080060c7 .word 0x080060c7 + 800609c: 080060bf .word 0x080060bf + { + case UART_CLOCKSOURCE_PCLK1: + pclk = HAL_RCC_GetPCLK1Freq(); + 80060a0: f7fd fd1c bl 8003adc + 80060a4: 6278 str r0, [r7, #36] @ 0x24 + break; + 80060a6: e014 b.n 80060d2 + case UART_CLOCKSOURCE_PCLK2: + pclk = HAL_RCC_GetPCLK2Freq(); + 80060a8: f7fd fd2a bl 8003b00 + 80060ac: 6278 str r0, [r7, #36] @ 0x24 + break; + 80060ae: e010 b.n 80060d2 + case UART_CLOCKSOURCE_HSI: + pclk = (uint32_t) HSI_VALUE; + 80060b0: 4b5a ldr r3, [pc, #360] @ (800621c ) + 80060b2: 627b str r3, [r7, #36] @ 0x24 + break; + 80060b4: e00d b.n 80060d2 + case UART_CLOCKSOURCE_SYSCLK: + pclk = HAL_RCC_GetSysClockFreq(); + 80060b6: f7fd fc5d bl 8003974 + 80060ba: 6278 str r0, [r7, #36] @ 0x24 + break; + 80060bc: e009 b.n 80060d2 + case UART_CLOCKSOURCE_LSE: + pclk = (uint32_t) LSE_VALUE; + 80060be: f44f 4300 mov.w r3, #32768 @ 0x8000 + 80060c2: 627b str r3, [r7, #36] @ 0x24 + break; + 80060c4: e005 b.n 80060d2 + default: + pclk = 0U; + 80060c6: 2300 movs r3, #0 + 80060c8: 627b str r3, [r7, #36] @ 0x24 + ret = HAL_ERROR; + 80060ca: 2301 movs r3, #1 + 80060cc: f887 302a strb.w r3, [r7, #42] @ 0x2a + break; + 80060d0: bf00 nop + } + + /* USARTDIV must be greater than or equal to 0d16 */ + if (pclk != 0U) + 80060d2: 6a7b ldr r3, [r7, #36] @ 0x24 + 80060d4: 2b00 cmp r3, #0 + 80060d6: f000 8089 beq.w 80061ec + { + usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); + 80060da: 697b ldr r3, [r7, #20] + 80060dc: 6a5b ldr r3, [r3, #36] @ 0x24 + 80060de: 4a4e ldr r2, [pc, #312] @ (8006218 ) + 80060e0: f832 3013 ldrh.w r3, [r2, r3, lsl #1] + 80060e4: 461a mov r2, r3 + 80060e6: 6a7b ldr r3, [r7, #36] @ 0x24 + 80060e8: fbb3 f3f2 udiv r3, r3, r2 + 80060ec: 005a lsls r2, r3, #1 + 80060ee: 697b ldr r3, [r7, #20] + 80060f0: 685b ldr r3, [r3, #4] + 80060f2: 085b lsrs r3, r3, #1 + 80060f4: 441a add r2, r3 + 80060f6: 697b ldr r3, [r7, #20] + 80060f8: 685b ldr r3, [r3, #4] + 80060fa: fbb2 f3f3 udiv r3, r2, r3 + 80060fe: 623b str r3, [r7, #32] + if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) + 8006100: 6a3b ldr r3, [r7, #32] + 8006102: 2b0f cmp r3, #15 + 8006104: d916 bls.n 8006134 + 8006106: 6a3b ldr r3, [r7, #32] + 8006108: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 + 800610c: d212 bcs.n 8006134 + { + brrtemp = (uint16_t)(usartdiv & 0xFFF0U); + 800610e: 6a3b ldr r3, [r7, #32] + 8006110: b29b uxth r3, r3 + 8006112: f023 030f bic.w r3, r3, #15 + 8006116: 83fb strh r3, [r7, #30] + brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); + 8006118: 6a3b ldr r3, [r7, #32] + 800611a: 085b lsrs r3, r3, #1 + 800611c: b29b uxth r3, r3 + 800611e: f003 0307 and.w r3, r3, #7 + 8006122: b29a uxth r2, r3 + 8006124: 8bfb ldrh r3, [r7, #30] + 8006126: 4313 orrs r3, r2 + 8006128: 83fb strh r3, [r7, #30] + huart->Instance->BRR = brrtemp; + 800612a: 697b ldr r3, [r7, #20] + 800612c: 681b ldr r3, [r3, #0] + 800612e: 8bfa ldrh r2, [r7, #30] + 8006130: 60da str r2, [r3, #12] + 8006132: e05b b.n 80061ec + } + else + { + ret = HAL_ERROR; + 8006134: 2301 movs r3, #1 + 8006136: f887 302a strb.w r3, [r7, #42] @ 0x2a + 800613a: e057 b.n 80061ec + } + } + } + else + { + switch (clocksource) + 800613c: f897 302b ldrb.w r3, [r7, #43] @ 0x2b + 8006140: 2b08 cmp r3, #8 + 8006142: d828 bhi.n 8006196 + 8006144: a201 add r2, pc, #4 @ (adr r2, 800614c ) + 8006146: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 800614a: bf00 nop + 800614c: 08006171 .word 0x08006171 + 8006150: 08006179 .word 0x08006179 + 8006154: 08006181 .word 0x08006181 + 8006158: 08006197 .word 0x08006197 + 800615c: 08006187 .word 0x08006187 + 8006160: 08006197 .word 0x08006197 + 8006164: 08006197 .word 0x08006197 + 8006168: 08006197 .word 0x08006197 + 800616c: 0800618f .word 0x0800618f + { + case UART_CLOCKSOURCE_PCLK1: + pclk = HAL_RCC_GetPCLK1Freq(); + 8006170: f7fd fcb4 bl 8003adc + 8006174: 6278 str r0, [r7, #36] @ 0x24 + break; + 8006176: e014 b.n 80061a2 + case UART_CLOCKSOURCE_PCLK2: + pclk = HAL_RCC_GetPCLK2Freq(); + 8006178: f7fd fcc2 bl 8003b00 + 800617c: 6278 str r0, [r7, #36] @ 0x24 + break; + 800617e: e010 b.n 80061a2 + case UART_CLOCKSOURCE_HSI: + pclk = (uint32_t) HSI_VALUE; + 8006180: 4b26 ldr r3, [pc, #152] @ (800621c ) + 8006182: 627b str r3, [r7, #36] @ 0x24 + break; + 8006184: e00d b.n 80061a2 + case UART_CLOCKSOURCE_SYSCLK: + pclk = HAL_RCC_GetSysClockFreq(); + 8006186: f7fd fbf5 bl 8003974 + 800618a: 6278 str r0, [r7, #36] @ 0x24 + break; + 800618c: e009 b.n 80061a2 + case UART_CLOCKSOURCE_LSE: + pclk = (uint32_t) LSE_VALUE; + 800618e: f44f 4300 mov.w r3, #32768 @ 0x8000 + 8006192: 627b str r3, [r7, #36] @ 0x24 + break; + 8006194: e005 b.n 80061a2 + default: + pclk = 0U; + 8006196: 2300 movs r3, #0 + 8006198: 627b str r3, [r7, #36] @ 0x24 + ret = HAL_ERROR; + 800619a: 2301 movs r3, #1 + 800619c: f887 302a strb.w r3, [r7, #42] @ 0x2a + break; + 80061a0: bf00 nop + } + + if (pclk != 0U) + 80061a2: 6a7b ldr r3, [r7, #36] @ 0x24 + 80061a4: 2b00 cmp r3, #0 + 80061a6: d021 beq.n 80061ec + { + /* USARTDIV must be greater than or equal to 0d16 */ + usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); + 80061a8: 697b ldr r3, [r7, #20] + 80061aa: 6a5b ldr r3, [r3, #36] @ 0x24 + 80061ac: 4a1a ldr r2, [pc, #104] @ (8006218 ) + 80061ae: f832 3013 ldrh.w r3, [r2, r3, lsl #1] + 80061b2: 461a mov r2, r3 + 80061b4: 6a7b ldr r3, [r7, #36] @ 0x24 + 80061b6: fbb3 f2f2 udiv r2, r3, r2 + 80061ba: 697b ldr r3, [r7, #20] + 80061bc: 685b ldr r3, [r3, #4] + 80061be: 085b lsrs r3, r3, #1 + 80061c0: 441a add r2, r3 + 80061c2: 697b ldr r3, [r7, #20] + 80061c4: 685b ldr r3, [r3, #4] + 80061c6: fbb2 f3f3 udiv r3, r2, r3 + 80061ca: 623b str r3, [r7, #32] + if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) + 80061cc: 6a3b ldr r3, [r7, #32] + 80061ce: 2b0f cmp r3, #15 + 80061d0: d909 bls.n 80061e6 + 80061d2: 6a3b ldr r3, [r7, #32] + 80061d4: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 + 80061d8: d205 bcs.n 80061e6 + { + huart->Instance->BRR = (uint16_t)usartdiv; + 80061da: 6a3b ldr r3, [r7, #32] + 80061dc: b29a uxth r2, r3 + 80061de: 697b ldr r3, [r7, #20] + 80061e0: 681b ldr r3, [r3, #0] + 80061e2: 60da str r2, [r3, #12] + 80061e4: e002 b.n 80061ec + } + else + { + ret = HAL_ERROR; + 80061e6: 2301 movs r3, #1 + 80061e8: f887 302a strb.w r3, [r7, #42] @ 0x2a + } + } + } + + /* Initialize the number of data to process during RX/TX ISR execution */ + huart->NbTxDataToProcess = 1; + 80061ec: 697b ldr r3, [r7, #20] + 80061ee: 2201 movs r2, #1 + 80061f0: f8a3 206a strh.w r2, [r3, #106] @ 0x6a + huart->NbRxDataToProcess = 1; + 80061f4: 697b ldr r3, [r7, #20] + 80061f6: 2201 movs r2, #1 + 80061f8: f8a3 2068 strh.w r2, [r3, #104] @ 0x68 + + /* Clear ISR function pointers */ + huart->RxISR = NULL; + 80061fc: 697b ldr r3, [r7, #20] + 80061fe: 2200 movs r2, #0 + 8006200: 675a str r2, [r3, #116] @ 0x74 + huart->TxISR = NULL; + 8006202: 697b ldr r3, [r7, #20] + 8006204: 2200 movs r2, #0 + 8006206: 679a str r2, [r3, #120] @ 0x78 + + return ret; + 8006208: f897 302a ldrb.w r3, [r7, #42] @ 0x2a +} + 800620c: 4618 mov r0, r3 + 800620e: 3730 adds r7, #48 @ 0x30 + 8006210: 46bd mov sp, r7 + 8006212: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc} + 8006216: bf00 nop + 8006218: 0800fb54 .word 0x0800fb54 + 800621c: 00f42400 .word 0x00f42400 + +08006220 : + * @brief Configure the UART peripheral advanced features. + * @param huart UART handle. + * @retval None + */ +void UART_AdvFeatureConfig(UART_HandleTypeDef *huart) +{ + 8006220: b480 push {r7} + 8006222: b083 sub sp, #12 + 8006224: af00 add r7, sp, #0 + 8006226: 6078 str r0, [r7, #4] + /* Check whether the set of advanced features to configure is properly set */ + assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit)); + + /* if required, configure RX/TX pins swap */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT)) + 8006228: 687b ldr r3, [r7, #4] + 800622a: 6a9b ldr r3, [r3, #40] @ 0x28 + 800622c: f003 0308 and.w r3, r3, #8 + 8006230: 2b00 cmp r3, #0 + 8006232: d00a beq.n 800624a + { + assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap); + 8006234: 687b ldr r3, [r7, #4] + 8006236: 681b ldr r3, [r3, #0] + 8006238: 685b ldr r3, [r3, #4] + 800623a: f423 4100 bic.w r1, r3, #32768 @ 0x8000 + 800623e: 687b ldr r3, [r7, #4] + 8006240: 6b9a ldr r2, [r3, #56] @ 0x38 + 8006242: 687b ldr r3, [r7, #4] + 8006244: 681b ldr r3, [r3, #0] + 8006246: 430a orrs r2, r1 + 8006248: 605a str r2, [r3, #4] + } + + /* if required, configure TX pin active level inversion */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT)) + 800624a: 687b ldr r3, [r7, #4] + 800624c: 6a9b ldr r3, [r3, #40] @ 0x28 + 800624e: f003 0301 and.w r3, r3, #1 + 8006252: 2b00 cmp r3, #0 + 8006254: d00a beq.n 800626c + { + assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert); + 8006256: 687b ldr r3, [r7, #4] + 8006258: 681b ldr r3, [r3, #0] + 800625a: 685b ldr r3, [r3, #4] + 800625c: f423 3100 bic.w r1, r3, #131072 @ 0x20000 + 8006260: 687b ldr r3, [r7, #4] + 8006262: 6ada ldr r2, [r3, #44] @ 0x2c + 8006264: 687b ldr r3, [r7, #4] + 8006266: 681b ldr r3, [r3, #0] + 8006268: 430a orrs r2, r1 + 800626a: 605a str r2, [r3, #4] + } + + /* if required, configure RX pin active level inversion */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT)) + 800626c: 687b ldr r3, [r7, #4] + 800626e: 6a9b ldr r3, [r3, #40] @ 0x28 + 8006270: f003 0302 and.w r3, r3, #2 + 8006274: 2b00 cmp r3, #0 + 8006276: d00a beq.n 800628e + { + assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert); + 8006278: 687b ldr r3, [r7, #4] + 800627a: 681b ldr r3, [r3, #0] + 800627c: 685b ldr r3, [r3, #4] + 800627e: f423 3180 bic.w r1, r3, #65536 @ 0x10000 + 8006282: 687b ldr r3, [r7, #4] + 8006284: 6b1a ldr r2, [r3, #48] @ 0x30 + 8006286: 687b ldr r3, [r7, #4] + 8006288: 681b ldr r3, [r3, #0] + 800628a: 430a orrs r2, r1 + 800628c: 605a str r2, [r3, #4] + } + + /* if required, configure data inversion */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT)) + 800628e: 687b ldr r3, [r7, #4] + 8006290: 6a9b ldr r3, [r3, #40] @ 0x28 + 8006292: f003 0304 and.w r3, r3, #4 + 8006296: 2b00 cmp r3, #0 + 8006298: d00a beq.n 80062b0 + { + assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert); + 800629a: 687b ldr r3, [r7, #4] + 800629c: 681b ldr r3, [r3, #0] + 800629e: 685b ldr r3, [r3, #4] + 80062a0: f423 2180 bic.w r1, r3, #262144 @ 0x40000 + 80062a4: 687b ldr r3, [r7, #4] + 80062a6: 6b5a ldr r2, [r3, #52] @ 0x34 + 80062a8: 687b ldr r3, [r7, #4] + 80062aa: 681b ldr r3, [r3, #0] + 80062ac: 430a orrs r2, r1 + 80062ae: 605a str r2, [r3, #4] + } + + /* if required, configure RX overrun detection disabling */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT)) + 80062b0: 687b ldr r3, [r7, #4] + 80062b2: 6a9b ldr r3, [r3, #40] @ 0x28 + 80062b4: f003 0310 and.w r3, r3, #16 + 80062b8: 2b00 cmp r3, #0 + 80062ba: d00a beq.n 80062d2 + { + assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable)); + MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable); + 80062bc: 687b ldr r3, [r7, #4] + 80062be: 681b ldr r3, [r3, #0] + 80062c0: 689b ldr r3, [r3, #8] + 80062c2: f423 5180 bic.w r1, r3, #4096 @ 0x1000 + 80062c6: 687b ldr r3, [r7, #4] + 80062c8: 6bda ldr r2, [r3, #60] @ 0x3c + 80062ca: 687b ldr r3, [r7, #4] + 80062cc: 681b ldr r3, [r3, #0] + 80062ce: 430a orrs r2, r1 + 80062d0: 609a str r2, [r3, #8] + } + + /* if required, configure DMA disabling on reception error */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT)) + 80062d2: 687b ldr r3, [r7, #4] + 80062d4: 6a9b ldr r3, [r3, #40] @ 0x28 + 80062d6: f003 0320 and.w r3, r3, #32 + 80062da: 2b00 cmp r3, #0 + 80062dc: d00a beq.n 80062f4 + { + assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError)); + MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError); + 80062de: 687b ldr r3, [r7, #4] + 80062e0: 681b ldr r3, [r3, #0] + 80062e2: 689b ldr r3, [r3, #8] + 80062e4: f423 5100 bic.w r1, r3, #8192 @ 0x2000 + 80062e8: 687b ldr r3, [r7, #4] + 80062ea: 6c1a ldr r2, [r3, #64] @ 0x40 + 80062ec: 687b ldr r3, [r7, #4] + 80062ee: 681b ldr r3, [r3, #0] + 80062f0: 430a orrs r2, r1 + 80062f2: 609a str r2, [r3, #8] + } + + /* if required, configure auto Baud rate detection scheme */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT)) + 80062f4: 687b ldr r3, [r7, #4] + 80062f6: 6a9b ldr r3, [r3, #40] @ 0x28 + 80062f8: f003 0340 and.w r3, r3, #64 @ 0x40 + 80062fc: 2b00 cmp r3, #0 + 80062fe: d01a beq.n 8006336 + { + assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance)); + assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable); + 8006300: 687b ldr r3, [r7, #4] + 8006302: 681b ldr r3, [r3, #0] + 8006304: 685b ldr r3, [r3, #4] + 8006306: f423 1180 bic.w r1, r3, #1048576 @ 0x100000 + 800630a: 687b ldr r3, [r7, #4] + 800630c: 6c5a ldr r2, [r3, #68] @ 0x44 + 800630e: 687b ldr r3, [r7, #4] + 8006310: 681b ldr r3, [r3, #0] + 8006312: 430a orrs r2, r1 + 8006314: 605a str r2, [r3, #4] + /* set auto Baudrate detection parameters if detection is enabled */ + if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE) + 8006316: 687b ldr r3, [r7, #4] + 8006318: 6c5b ldr r3, [r3, #68] @ 0x44 + 800631a: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 + 800631e: d10a bne.n 8006336 + { + assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode); + 8006320: 687b ldr r3, [r7, #4] + 8006322: 681b ldr r3, [r3, #0] + 8006324: 685b ldr r3, [r3, #4] + 8006326: f423 01c0 bic.w r1, r3, #6291456 @ 0x600000 + 800632a: 687b ldr r3, [r7, #4] + 800632c: 6c9a ldr r2, [r3, #72] @ 0x48 + 800632e: 687b ldr r3, [r7, #4] + 8006330: 681b ldr r3, [r3, #0] + 8006332: 430a orrs r2, r1 + 8006334: 605a str r2, [r3, #4] + } + } + + /* if required, configure MSB first on communication line */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT)) + 8006336: 687b ldr r3, [r7, #4] + 8006338: 6a9b ldr r3, [r3, #40] @ 0x28 + 800633a: f003 0380 and.w r3, r3, #128 @ 0x80 + 800633e: 2b00 cmp r3, #0 + 8006340: d00a beq.n 8006358 + { + assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst); + 8006342: 687b ldr r3, [r7, #4] + 8006344: 681b ldr r3, [r3, #0] + 8006346: 685b ldr r3, [r3, #4] + 8006348: f423 2100 bic.w r1, r3, #524288 @ 0x80000 + 800634c: 687b ldr r3, [r7, #4] + 800634e: 6cda ldr r2, [r3, #76] @ 0x4c + 8006350: 687b ldr r3, [r7, #4] + 8006352: 681b ldr r3, [r3, #0] + 8006354: 430a orrs r2, r1 + 8006356: 605a str r2, [r3, #4] + } +} + 8006358: bf00 nop + 800635a: 370c adds r7, #12 + 800635c: 46bd mov sp, r7 + 800635e: bc80 pop {r7} + 8006360: 4770 bx lr + +08006362 : + * @brief Check the UART Idle State. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) +{ + 8006362: b580 push {r7, lr} + 8006364: b098 sub sp, #96 @ 0x60 + 8006366: af02 add r7, sp, #8 + 8006368: 6078 str r0, [r7, #4] + uint32_t tickstart; + + /* Initialize the UART ErrorCode */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + 800636a: 687b ldr r3, [r7, #4] + 800636c: 2200 movs r2, #0 + 800636e: f8c3 2090 str.w r2, [r3, #144] @ 0x90 + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + 8006372: f7fa fc69 bl 8000c48 + 8006376: 6578 str r0, [r7, #84] @ 0x54 + + /* Check if the Transmitter is enabled */ + if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) + 8006378: 687b ldr r3, [r7, #4] + 800637a: 681b ldr r3, [r3, #0] + 800637c: 681b ldr r3, [r3, #0] + 800637e: f003 0308 and.w r3, r3, #8 + 8006382: 2b08 cmp r3, #8 + 8006384: d12f bne.n 80063e6 + { + /* Wait until TEACK flag is set */ + if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) + 8006386: f06f 437e mvn.w r3, #4261412864 @ 0xfe000000 + 800638a: 9300 str r3, [sp, #0] + 800638c: 6d7b ldr r3, [r7, #84] @ 0x54 + 800638e: 2200 movs r2, #0 + 8006390: f44f 1100 mov.w r1, #2097152 @ 0x200000 + 8006394: 6878 ldr r0, [r7, #4] + 8006396: f000 f88e bl 80064b6 + 800639a: 4603 mov r3, r0 + 800639c: 2b00 cmp r3, #0 + 800639e: d022 beq.n 80063e6 + { + /* Disable TXE interrupt for the interrupt process */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE)); + 80063a0: 687b ldr r3, [r7, #4] + 80063a2: 681b ldr r3, [r3, #0] + 80063a4: 63bb str r3, [r7, #56] @ 0x38 + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 80063a6: 6bbb ldr r3, [r7, #56] @ 0x38 + 80063a8: e853 3f00 ldrex r3, [r3] + 80063ac: 637b str r3, [r7, #52] @ 0x34 + return(result); + 80063ae: 6b7b ldr r3, [r7, #52] @ 0x34 + 80063b0: f023 0380 bic.w r3, r3, #128 @ 0x80 + 80063b4: 653b str r3, [r7, #80] @ 0x50 + 80063b6: 687b ldr r3, [r7, #4] + 80063b8: 681b ldr r3, [r3, #0] + 80063ba: 461a mov r2, r3 + 80063bc: 6d3b ldr r3, [r7, #80] @ 0x50 + 80063be: 647b str r3, [r7, #68] @ 0x44 + 80063c0: 643a str r2, [r7, #64] @ 0x40 + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 80063c2: 6c39 ldr r1, [r7, #64] @ 0x40 + 80063c4: 6c7a ldr r2, [r7, #68] @ 0x44 + 80063c6: e841 2300 strex r3, r2, [r1] + 80063ca: 63fb str r3, [r7, #60] @ 0x3c + return(result); + 80063cc: 6bfb ldr r3, [r7, #60] @ 0x3c + 80063ce: 2b00 cmp r3, #0 + 80063d0: d1e6 bne.n 80063a0 + + huart->gState = HAL_UART_STATE_READY; + 80063d2: 687b ldr r3, [r7, #4] + 80063d4: 2220 movs r2, #32 + 80063d6: f8c3 2088 str.w r2, [r3, #136] @ 0x88 + + __HAL_UNLOCK(huart); + 80063da: 687b ldr r3, [r7, #4] + 80063dc: 2200 movs r2, #0 + 80063de: f883 2084 strb.w r2, [r3, #132] @ 0x84 + + /* Timeout occurred */ + return HAL_TIMEOUT; + 80063e2: 2303 movs r3, #3 + 80063e4: e063 b.n 80064ae + } + } + + /* Check if the Receiver is enabled */ + if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) + 80063e6: 687b ldr r3, [r7, #4] + 80063e8: 681b ldr r3, [r3, #0] + 80063ea: 681b ldr r3, [r3, #0] + 80063ec: f003 0304 and.w r3, r3, #4 + 80063f0: 2b04 cmp r3, #4 + 80063f2: d149 bne.n 8006488 + { + /* Wait until REACK flag is set */ + if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) + 80063f4: f06f 437e mvn.w r3, #4261412864 @ 0xfe000000 + 80063f8: 9300 str r3, [sp, #0] + 80063fa: 6d7b ldr r3, [r7, #84] @ 0x54 + 80063fc: 2200 movs r2, #0 + 80063fe: f44f 0180 mov.w r1, #4194304 @ 0x400000 + 8006402: 6878 ldr r0, [r7, #4] + 8006404: f000 f857 bl 80064b6 + 8006408: 4603 mov r3, r0 + 800640a: 2b00 cmp r3, #0 + 800640c: d03c beq.n 8006488 + { + /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) + interrupts for the interrupt process */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); + 800640e: 687b ldr r3, [r7, #4] + 8006410: 681b ldr r3, [r3, #0] + 8006412: 627b str r3, [r7, #36] @ 0x24 + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 8006414: 6a7b ldr r3, [r7, #36] @ 0x24 + 8006416: e853 3f00 ldrex r3, [r3] + 800641a: 623b str r3, [r7, #32] + return(result); + 800641c: 6a3b ldr r3, [r7, #32] + 800641e: f423 7390 bic.w r3, r3, #288 @ 0x120 + 8006422: 64fb str r3, [r7, #76] @ 0x4c + 8006424: 687b ldr r3, [r7, #4] + 8006426: 681b ldr r3, [r3, #0] + 8006428: 461a mov r2, r3 + 800642a: 6cfb ldr r3, [r7, #76] @ 0x4c + 800642c: 633b str r3, [r7, #48] @ 0x30 + 800642e: 62fa str r2, [r7, #44] @ 0x2c + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 8006430: 6af9 ldr r1, [r7, #44] @ 0x2c + 8006432: 6b3a ldr r2, [r7, #48] @ 0x30 + 8006434: e841 2300 strex r3, r2, [r1] + 8006438: 62bb str r3, [r7, #40] @ 0x28 + return(result); + 800643a: 6abb ldr r3, [r7, #40] @ 0x28 + 800643c: 2b00 cmp r3, #0 + 800643e: d1e6 bne.n 800640e + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 8006440: 687b ldr r3, [r7, #4] + 8006442: 681b ldr r3, [r3, #0] + 8006444: 3308 adds r3, #8 + 8006446: 613b str r3, [r7, #16] + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 8006448: 693b ldr r3, [r7, #16] + 800644a: e853 3f00 ldrex r3, [r3] + 800644e: 60fb str r3, [r7, #12] + return(result); + 8006450: 68fb ldr r3, [r7, #12] + 8006452: f023 0301 bic.w r3, r3, #1 + 8006456: 64bb str r3, [r7, #72] @ 0x48 + 8006458: 687b ldr r3, [r7, #4] + 800645a: 681b ldr r3, [r3, #0] + 800645c: 3308 adds r3, #8 + 800645e: 6cba ldr r2, [r7, #72] @ 0x48 + 8006460: 61fa str r2, [r7, #28] + 8006462: 61bb str r3, [r7, #24] + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 8006464: 69b9 ldr r1, [r7, #24] + 8006466: 69fa ldr r2, [r7, #28] + 8006468: e841 2300 strex r3, r2, [r1] + 800646c: 617b str r3, [r7, #20] + return(result); + 800646e: 697b ldr r3, [r7, #20] + 8006470: 2b00 cmp r3, #0 + 8006472: d1e5 bne.n 8006440 + + huart->RxState = HAL_UART_STATE_READY; + 8006474: 687b ldr r3, [r7, #4] + 8006476: 2220 movs r2, #32 + 8006478: f8c3 208c str.w r2, [r3, #140] @ 0x8c + + __HAL_UNLOCK(huart); + 800647c: 687b ldr r3, [r7, #4] + 800647e: 2200 movs r2, #0 + 8006480: f883 2084 strb.w r2, [r3, #132] @ 0x84 + + /* Timeout occurred */ + return HAL_TIMEOUT; + 8006484: 2303 movs r3, #3 + 8006486: e012 b.n 80064ae + } + } + + /* Initialize the UART State */ + huart->gState = HAL_UART_STATE_READY; + 8006488: 687b ldr r3, [r7, #4] + 800648a: 2220 movs r2, #32 + 800648c: f8c3 2088 str.w r2, [r3, #136] @ 0x88 + huart->RxState = HAL_UART_STATE_READY; + 8006490: 687b ldr r3, [r7, #4] + 8006492: 2220 movs r2, #32 + 8006494: f8c3 208c str.w r2, [r3, #140] @ 0x8c + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + 8006498: 687b ldr r3, [r7, #4] + 800649a: 2200 movs r2, #0 + 800649c: 66da str r2, [r3, #108] @ 0x6c + huart->RxEventType = HAL_UART_RXEVENT_TC; + 800649e: 687b ldr r3, [r7, #4] + 80064a0: 2200 movs r2, #0 + 80064a2: 671a str r2, [r3, #112] @ 0x70 + + __HAL_UNLOCK(huart); + 80064a4: 687b ldr r3, [r7, #4] + 80064a6: 2200 movs r2, #0 + 80064a8: f883 2084 strb.w r2, [r3, #132] @ 0x84 + + return HAL_OK; + 80064ac: 2300 movs r3, #0 +} + 80064ae: 4618 mov r0, r3 + 80064b0: 3758 adds r7, #88 @ 0x58 + 80064b2: 46bd mov sp, r7 + 80064b4: bd80 pop {r7, pc} + +080064b6 : + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, + uint32_t Tickstart, uint32_t Timeout) +{ + 80064b6: b580 push {r7, lr} + 80064b8: b084 sub sp, #16 + 80064ba: af00 add r7, sp, #0 + 80064bc: 60f8 str r0, [r7, #12] + 80064be: 60b9 str r1, [r7, #8] + 80064c0: 603b str r3, [r7, #0] + 80064c2: 4613 mov r3, r2 + 80064c4: 71fb strb r3, [r7, #7] + /* Wait until flag is set */ + while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) + 80064c6: e04f b.n 8006568 + { + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + 80064c8: 69bb ldr r3, [r7, #24] + 80064ca: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff + 80064ce: d04b beq.n 8006568 + { + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + 80064d0: f7fa fbba bl 8000c48 + 80064d4: 4602 mov r2, r0 + 80064d6: 683b ldr r3, [r7, #0] + 80064d8: 1ad3 subs r3, r2, r3 + 80064da: 69ba ldr r2, [r7, #24] + 80064dc: 429a cmp r2, r3 + 80064de: d302 bcc.n 80064e6 + 80064e0: 69bb ldr r3, [r7, #24] + 80064e2: 2b00 cmp r3, #0 + 80064e4: d101 bne.n 80064ea + { + + return HAL_TIMEOUT; + 80064e6: 2303 movs r3, #3 + 80064e8: e04e b.n 8006588 + } + + if ((READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) && (Flag != UART_FLAG_TXE) && (Flag != UART_FLAG_TC)) + 80064ea: 68fb ldr r3, [r7, #12] + 80064ec: 681b ldr r3, [r3, #0] + 80064ee: 681b ldr r3, [r3, #0] + 80064f0: f003 0304 and.w r3, r3, #4 + 80064f4: 2b00 cmp r3, #0 + 80064f6: d037 beq.n 8006568 + 80064f8: 68bb ldr r3, [r7, #8] + 80064fa: 2b80 cmp r3, #128 @ 0x80 + 80064fc: d034 beq.n 8006568 + 80064fe: 68bb ldr r3, [r7, #8] + 8006500: 2b40 cmp r3, #64 @ 0x40 + 8006502: d031 beq.n 8006568 + { + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET) + 8006504: 68fb ldr r3, [r7, #12] + 8006506: 681b ldr r3, [r3, #0] + 8006508: 69db ldr r3, [r3, #28] + 800650a: f003 0308 and.w r3, r3, #8 + 800650e: 2b08 cmp r3, #8 + 8006510: d110 bne.n 8006534 + { + /* Clear Overrun Error flag*/ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); + 8006512: 68fb ldr r3, [r7, #12] + 8006514: 681b ldr r3, [r3, #0] + 8006516: 2208 movs r2, #8 + 8006518: 621a str r2, [r3, #32] + + /* Blocking error : transfer is aborted + Set the UART state ready to be able to start again the process, + Disable Rx Interrupts if ongoing */ + UART_EndRxTransfer(huart); + 800651a: 68f8 ldr r0, [r7, #12] + 800651c: f000 f998 bl 8006850 + + huart->ErrorCode = HAL_UART_ERROR_ORE; + 8006520: 68fb ldr r3, [r7, #12] + 8006522: 2208 movs r2, #8 + 8006524: f8c3 2090 str.w r2, [r3, #144] @ 0x90 + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + 8006528: 68fb ldr r3, [r7, #12] + 800652a: 2200 movs r2, #0 + 800652c: f883 2084 strb.w r2, [r3, #132] @ 0x84 + + return HAL_ERROR; + 8006530: 2301 movs r3, #1 + 8006532: e029 b.n 8006588 + } + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET) + 8006534: 68fb ldr r3, [r7, #12] + 8006536: 681b ldr r3, [r3, #0] + 8006538: 69db ldr r3, [r3, #28] + 800653a: f403 6300 and.w r3, r3, #2048 @ 0x800 + 800653e: f5b3 6f00 cmp.w r3, #2048 @ 0x800 + 8006542: d111 bne.n 8006568 + { + /* Clear Receiver Timeout flag*/ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF); + 8006544: 68fb ldr r3, [r7, #12] + 8006546: 681b ldr r3, [r3, #0] + 8006548: f44f 6200 mov.w r2, #2048 @ 0x800 + 800654c: 621a str r2, [r3, #32] + + /* Blocking error : transfer is aborted + Set the UART state ready to be able to start again the process, + Disable Rx Interrupts if ongoing */ + UART_EndRxTransfer(huart); + 800654e: 68f8 ldr r0, [r7, #12] + 8006550: f000 f97e bl 8006850 + + huart->ErrorCode = HAL_UART_ERROR_RTO; + 8006554: 68fb ldr r3, [r7, #12] + 8006556: 2220 movs r2, #32 + 8006558: f8c3 2090 str.w r2, [r3, #144] @ 0x90 + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + 800655c: 68fb ldr r3, [r7, #12] + 800655e: 2200 movs r2, #0 + 8006560: f883 2084 strb.w r2, [r3, #132] @ 0x84 + + return HAL_TIMEOUT; + 8006564: 2303 movs r3, #3 + 8006566: e00f b.n 8006588 + while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) + 8006568: 68fb ldr r3, [r7, #12] + 800656a: 681b ldr r3, [r3, #0] + 800656c: 69da ldr r2, [r3, #28] + 800656e: 68bb ldr r3, [r7, #8] + 8006570: 4013 ands r3, r2 + 8006572: 68ba ldr r2, [r7, #8] + 8006574: 429a cmp r2, r3 + 8006576: bf0c ite eq + 8006578: 2301 moveq r3, #1 + 800657a: 2300 movne r3, #0 + 800657c: b2db uxtb r3, r3 + 800657e: 461a mov r2, r3 + 8006580: 79fb ldrb r3, [r7, #7] + 8006582: 429a cmp r2, r3 + 8006584: d0a0 beq.n 80064c8 + } + } + } + } + return HAL_OK; + 8006586: 2300 movs r3, #0 +} + 8006588: 4618 mov r0, r3 + 800658a: 3710 adds r7, #16 + 800658c: 46bd mov sp, r7 + 800658e: bd80 pop {r7, pc} + +08006590 : + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. + * @retval HAL status + */ +HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + 8006590: b480 push {r7} + 8006592: b0a3 sub sp, #140 @ 0x8c + 8006594: af00 add r7, sp, #0 + 8006596: 60f8 str r0, [r7, #12] + 8006598: 60b9 str r1, [r7, #8] + 800659a: 4613 mov r3, r2 + 800659c: 80fb strh r3, [r7, #6] + huart->pRxBuffPtr = pData; + 800659e: 68fb ldr r3, [r7, #12] + 80065a0: 68ba ldr r2, [r7, #8] + 80065a2: 659a str r2, [r3, #88] @ 0x58 + huart->RxXferSize = Size; + 80065a4: 68fb ldr r3, [r7, #12] + 80065a6: 88fa ldrh r2, [r7, #6] + 80065a8: f8a3 205c strh.w r2, [r3, #92] @ 0x5c + huart->RxXferCount = Size; + 80065ac: 68fb ldr r3, [r7, #12] + 80065ae: 88fa ldrh r2, [r7, #6] + 80065b0: f8a3 205e strh.w r2, [r3, #94] @ 0x5e + huart->RxISR = NULL; + 80065b4: 68fb ldr r3, [r7, #12] + 80065b6: 2200 movs r2, #0 + 80065b8: 675a str r2, [r3, #116] @ 0x74 + + /* Computation of UART mask to apply to RDR register */ + UART_MASK_COMPUTATION(huart); + 80065ba: 68fb ldr r3, [r7, #12] + 80065bc: 689b ldr r3, [r3, #8] + 80065be: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 + 80065c2: d10e bne.n 80065e2 + 80065c4: 68fb ldr r3, [r7, #12] + 80065c6: 691b ldr r3, [r3, #16] + 80065c8: 2b00 cmp r3, #0 + 80065ca: d105 bne.n 80065d8 + 80065cc: 68fb ldr r3, [r7, #12] + 80065ce: f240 12ff movw r2, #511 @ 0x1ff + 80065d2: f8a3 2060 strh.w r2, [r3, #96] @ 0x60 + 80065d6: e02d b.n 8006634 + 80065d8: 68fb ldr r3, [r7, #12] + 80065da: 22ff movs r2, #255 @ 0xff + 80065dc: f8a3 2060 strh.w r2, [r3, #96] @ 0x60 + 80065e0: e028 b.n 8006634 + 80065e2: 68fb ldr r3, [r7, #12] + 80065e4: 689b ldr r3, [r3, #8] + 80065e6: 2b00 cmp r3, #0 + 80065e8: d10d bne.n 8006606 + 80065ea: 68fb ldr r3, [r7, #12] + 80065ec: 691b ldr r3, [r3, #16] + 80065ee: 2b00 cmp r3, #0 + 80065f0: d104 bne.n 80065fc + 80065f2: 68fb ldr r3, [r7, #12] + 80065f4: 22ff movs r2, #255 @ 0xff + 80065f6: f8a3 2060 strh.w r2, [r3, #96] @ 0x60 + 80065fa: e01b b.n 8006634 + 80065fc: 68fb ldr r3, [r7, #12] + 80065fe: 227f movs r2, #127 @ 0x7f + 8006600: f8a3 2060 strh.w r2, [r3, #96] @ 0x60 + 8006604: e016 b.n 8006634 + 8006606: 68fb ldr r3, [r7, #12] + 8006608: 689b ldr r3, [r3, #8] + 800660a: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 + 800660e: d10d bne.n 800662c + 8006610: 68fb ldr r3, [r7, #12] + 8006612: 691b ldr r3, [r3, #16] + 8006614: 2b00 cmp r3, #0 + 8006616: d104 bne.n 8006622 + 8006618: 68fb ldr r3, [r7, #12] + 800661a: 227f movs r2, #127 @ 0x7f + 800661c: f8a3 2060 strh.w r2, [r3, #96] @ 0x60 + 8006620: e008 b.n 8006634 + 8006622: 68fb ldr r3, [r7, #12] + 8006624: 223f movs r2, #63 @ 0x3f + 8006626: f8a3 2060 strh.w r2, [r3, #96] @ 0x60 + 800662a: e003 b.n 8006634 + 800662c: 68fb ldr r3, [r7, #12] + 800662e: 2200 movs r2, #0 + 8006630: f8a3 2060 strh.w r2, [r3, #96] @ 0x60 + + huart->ErrorCode = HAL_UART_ERROR_NONE; + 8006634: 68fb ldr r3, [r7, #12] + 8006636: 2200 movs r2, #0 + 8006638: f8c3 2090 str.w r2, [r3, #144] @ 0x90 + huart->RxState = HAL_UART_STATE_BUSY_RX; + 800663c: 68fb ldr r3, [r7, #12] + 800663e: 2222 movs r2, #34 @ 0x22 + 8006640: f8c3 208c str.w r2, [r3, #140] @ 0x8c + + /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE); + 8006644: 68fb ldr r3, [r7, #12] + 8006646: 681b ldr r3, [r3, #0] + 8006648: 3308 adds r3, #8 + 800664a: 667b str r3, [r7, #100] @ 0x64 + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 800664c: 6e7b ldr r3, [r7, #100] @ 0x64 + 800664e: e853 3f00 ldrex r3, [r3] + 8006652: 663b str r3, [r7, #96] @ 0x60 + return(result); + 8006654: 6e3b ldr r3, [r7, #96] @ 0x60 + 8006656: f043 0301 orr.w r3, r3, #1 + 800665a: f8c7 3084 str.w r3, [r7, #132] @ 0x84 + 800665e: 68fb ldr r3, [r7, #12] + 8006660: 681b ldr r3, [r3, #0] + 8006662: 3308 adds r3, #8 + 8006664: f8d7 2084 ldr.w r2, [r7, #132] @ 0x84 + 8006668: 673a str r2, [r7, #112] @ 0x70 + 800666a: 66fb str r3, [r7, #108] @ 0x6c + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 800666c: 6ef9 ldr r1, [r7, #108] @ 0x6c + 800666e: 6f3a ldr r2, [r7, #112] @ 0x70 + 8006670: e841 2300 strex r3, r2, [r1] + 8006674: 66bb str r3, [r7, #104] @ 0x68 + return(result); + 8006676: 6ebb ldr r3, [r7, #104] @ 0x68 + 8006678: 2b00 cmp r3, #0 + 800667a: d1e3 bne.n 8006644 + + /* Configure Rx interrupt processing */ + if ((huart->FifoMode == UART_FIFOMODE_ENABLE) && (Size >= huart->NbRxDataToProcess)) + 800667c: 68fb ldr r3, [r7, #12] + 800667e: 6e5b ldr r3, [r3, #100] @ 0x64 + 8006680: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 + 8006684: d14f bne.n 8006726 + 8006686: 68fb ldr r3, [r7, #12] + 8006688: f8b3 3068 ldrh.w r3, [r3, #104] @ 0x68 + 800668c: 88fa ldrh r2, [r7, #6] + 800668e: 429a cmp r2, r3 + 8006690: d349 bcc.n 8006726 + { + /* Set the Rx ISR function pointer according to the data word length */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + 8006692: 68fb ldr r3, [r7, #12] + 8006694: 689b ldr r3, [r3, #8] + 8006696: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 + 800669a: d107 bne.n 80066ac + 800669c: 68fb ldr r3, [r7, #12] + 800669e: 691b ldr r3, [r3, #16] + 80066a0: 2b00 cmp r3, #0 + 80066a2: d103 bne.n 80066ac + { + huart->RxISR = UART_RxISR_16BIT_FIFOEN; + 80066a4: 68fb ldr r3, [r7, #12] + 80066a6: 4a46 ldr r2, [pc, #280] @ (80067c0 ) + 80066a8: 675a str r2, [r3, #116] @ 0x74 + 80066aa: e002 b.n 80066b2 + } + else + { + huart->RxISR = UART_RxISR_8BIT_FIFOEN; + 80066ac: 68fb ldr r3, [r7, #12] + 80066ae: 4a45 ldr r2, [pc, #276] @ (80067c4 ) + 80066b0: 675a str r2, [r3, #116] @ 0x74 + } + + /* Enable the UART Parity Error interrupt and RX FIFO Threshold interrupt */ + if (huart->Init.Parity != UART_PARITY_NONE) + 80066b2: 68fb ldr r3, [r7, #12] + 80066b4: 691b ldr r3, [r3, #16] + 80066b6: 2b00 cmp r3, #0 + 80066b8: d01a beq.n 80066f0 + { + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); + 80066ba: 68fb ldr r3, [r7, #12] + 80066bc: 681b ldr r3, [r3, #0] + 80066be: 653b str r3, [r7, #80] @ 0x50 + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 80066c0: 6d3b ldr r3, [r7, #80] @ 0x50 + 80066c2: e853 3f00 ldrex r3, [r3] + 80066c6: 64fb str r3, [r7, #76] @ 0x4c + return(result); + 80066c8: 6cfb ldr r3, [r7, #76] @ 0x4c + 80066ca: f443 7380 orr.w r3, r3, #256 @ 0x100 + 80066ce: f8c7 3080 str.w r3, [r7, #128] @ 0x80 + 80066d2: 68fb ldr r3, [r7, #12] + 80066d4: 681b ldr r3, [r3, #0] + 80066d6: 461a mov r2, r3 + 80066d8: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80 + 80066dc: 65fb str r3, [r7, #92] @ 0x5c + 80066de: 65ba str r2, [r7, #88] @ 0x58 + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 80066e0: 6db9 ldr r1, [r7, #88] @ 0x58 + 80066e2: 6dfa ldr r2, [r7, #92] @ 0x5c + 80066e4: e841 2300 strex r3, r2, [r1] + 80066e8: 657b str r3, [r7, #84] @ 0x54 + return(result); + 80066ea: 6d7b ldr r3, [r7, #84] @ 0x54 + 80066ec: 2b00 cmp r3, #0 + 80066ee: d1e4 bne.n 80066ba + } + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); + 80066f0: 68fb ldr r3, [r7, #12] + 80066f2: 681b ldr r3, [r3, #0] + 80066f4: 3308 adds r3, #8 + 80066f6: 63fb str r3, [r7, #60] @ 0x3c + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 80066f8: 6bfb ldr r3, [r7, #60] @ 0x3c + 80066fa: e853 3f00 ldrex r3, [r3] + 80066fe: 63bb str r3, [r7, #56] @ 0x38 + return(result); + 8006700: 6bbb ldr r3, [r7, #56] @ 0x38 + 8006702: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 + 8006706: 67fb str r3, [r7, #124] @ 0x7c + 8006708: 68fb ldr r3, [r7, #12] + 800670a: 681b ldr r3, [r3, #0] + 800670c: 3308 adds r3, #8 + 800670e: 6ffa ldr r2, [r7, #124] @ 0x7c + 8006710: 64ba str r2, [r7, #72] @ 0x48 + 8006712: 647b str r3, [r7, #68] @ 0x44 + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 8006714: 6c79 ldr r1, [r7, #68] @ 0x44 + 8006716: 6cba ldr r2, [r7, #72] @ 0x48 + 8006718: e841 2300 strex r3, r2, [r1] + 800671c: 643b str r3, [r7, #64] @ 0x40 + return(result); + 800671e: 6c3b ldr r3, [r7, #64] @ 0x40 + 8006720: 2b00 cmp r3, #0 + 8006722: d1e5 bne.n 80066f0 + 8006724: e046 b.n 80067b4 + } + else + { + /* Set the Rx ISR function pointer according to the data word length */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + 8006726: 68fb ldr r3, [r7, #12] + 8006728: 689b ldr r3, [r3, #8] + 800672a: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 + 800672e: d107 bne.n 8006740 + 8006730: 68fb ldr r3, [r7, #12] + 8006732: 691b ldr r3, [r3, #16] + 8006734: 2b00 cmp r3, #0 + 8006736: d103 bne.n 8006740 + { + huart->RxISR = UART_RxISR_16BIT; + 8006738: 68fb ldr r3, [r7, #12] + 800673a: 4a23 ldr r2, [pc, #140] @ (80067c8 ) + 800673c: 675a str r2, [r3, #116] @ 0x74 + 800673e: e002 b.n 8006746 + } + else + { + huart->RxISR = UART_RxISR_8BIT; + 8006740: 68fb ldr r3, [r7, #12] + 8006742: 4a22 ldr r2, [pc, #136] @ (80067cc ) + 8006744: 675a str r2, [r3, #116] @ 0x74 + } + + /* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */ + if (huart->Init.Parity != UART_PARITY_NONE) + 8006746: 68fb ldr r3, [r7, #12] + 8006748: 691b ldr r3, [r3, #16] + 800674a: 2b00 cmp r3, #0 + 800674c: d019 beq.n 8006782 + { + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE); + 800674e: 68fb ldr r3, [r7, #12] + 8006750: 681b ldr r3, [r3, #0] + 8006752: 62bb str r3, [r7, #40] @ 0x28 + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 8006754: 6abb ldr r3, [r7, #40] @ 0x28 + 8006756: e853 3f00 ldrex r3, [r3] + 800675a: 627b str r3, [r7, #36] @ 0x24 + return(result); + 800675c: 6a7b ldr r3, [r7, #36] @ 0x24 + 800675e: f443 7390 orr.w r3, r3, #288 @ 0x120 + 8006762: 677b str r3, [r7, #116] @ 0x74 + 8006764: 68fb ldr r3, [r7, #12] + 8006766: 681b ldr r3, [r3, #0] + 8006768: 461a mov r2, r3 + 800676a: 6f7b ldr r3, [r7, #116] @ 0x74 + 800676c: 637b str r3, [r7, #52] @ 0x34 + 800676e: 633a str r2, [r7, #48] @ 0x30 + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 8006770: 6b39 ldr r1, [r7, #48] @ 0x30 + 8006772: 6b7a ldr r2, [r7, #52] @ 0x34 + 8006774: e841 2300 strex r3, r2, [r1] + 8006778: 62fb str r3, [r7, #44] @ 0x2c + return(result); + 800677a: 6afb ldr r3, [r7, #44] @ 0x2c + 800677c: 2b00 cmp r3, #0 + 800677e: d1e6 bne.n 800674e + 8006780: e018 b.n 80067b4 + } + else + { + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); + 8006782: 68fb ldr r3, [r7, #12] + 8006784: 681b ldr r3, [r3, #0] + 8006786: 617b str r3, [r7, #20] + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 8006788: 697b ldr r3, [r7, #20] + 800678a: e853 3f00 ldrex r3, [r3] + 800678e: 613b str r3, [r7, #16] + return(result); + 8006790: 693b ldr r3, [r7, #16] + 8006792: f043 0320 orr.w r3, r3, #32 + 8006796: 67bb str r3, [r7, #120] @ 0x78 + 8006798: 68fb ldr r3, [r7, #12] + 800679a: 681b ldr r3, [r3, #0] + 800679c: 461a mov r2, r3 + 800679e: 6fbb ldr r3, [r7, #120] @ 0x78 + 80067a0: 623b str r3, [r7, #32] + 80067a2: 61fa str r2, [r7, #28] + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 80067a4: 69f9 ldr r1, [r7, #28] + 80067a6: 6a3a ldr r2, [r7, #32] + 80067a8: e841 2300 strex r3, r2, [r1] + 80067ac: 61bb str r3, [r7, #24] + return(result); + 80067ae: 69bb ldr r3, [r7, #24] + 80067b0: 2b00 cmp r3, #0 + 80067b2: d1e6 bne.n 8006782 + } + } + return HAL_OK; + 80067b4: 2300 movs r3, #0 +} + 80067b6: 4618 mov r0, r3 + 80067b8: 378c adds r7, #140 @ 0x8c + 80067ba: 46bd mov sp, r7 + 80067bc: bc80 pop {r7} + 80067be: 4770 bx lr + 80067c0: 08007181 .word 0x08007181 + 80067c4: 08006e1d .word 0x08006e1d + 80067c8: 08006c65 .word 0x08006c65 + 80067cc: 08006aad .word 0x08006aad + +080067d0 : + * @brief End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion). + * @param huart UART handle. + * @retval None + */ +static void UART_EndTxTransfer(UART_HandleTypeDef *huart) +{ + 80067d0: b480 push {r7} + 80067d2: b08f sub sp, #60 @ 0x3c + 80067d4: af00 add r7, sp, #0 + 80067d6: 6078 str r0, [r7, #4] + /* Disable TXEIE, TCIE, TXFT interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); + 80067d8: 687b ldr r3, [r7, #4] + 80067da: 681b ldr r3, [r3, #0] + 80067dc: 623b str r3, [r7, #32] + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 80067de: 6a3b ldr r3, [r7, #32] + 80067e0: e853 3f00 ldrex r3, [r3] + 80067e4: 61fb str r3, [r7, #28] + return(result); + 80067e6: 69fb ldr r3, [r7, #28] + 80067e8: f023 03c0 bic.w r3, r3, #192 @ 0xc0 + 80067ec: 637b str r3, [r7, #52] @ 0x34 + 80067ee: 687b ldr r3, [r7, #4] + 80067f0: 681b ldr r3, [r3, #0] + 80067f2: 461a mov r2, r3 + 80067f4: 6b7b ldr r3, [r7, #52] @ 0x34 + 80067f6: 62fb str r3, [r7, #44] @ 0x2c + 80067f8: 62ba str r2, [r7, #40] @ 0x28 + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 80067fa: 6ab9 ldr r1, [r7, #40] @ 0x28 + 80067fc: 6afa ldr r2, [r7, #44] @ 0x2c + 80067fe: e841 2300 strex r3, r2, [r1] + 8006802: 627b str r3, [r7, #36] @ 0x24 + return(result); + 8006804: 6a7b ldr r3, [r7, #36] @ 0x24 + 8006806: 2b00 cmp r3, #0 + 8006808: d1e6 bne.n 80067d8 + ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_TXFTIE)); + 800680a: 687b ldr r3, [r7, #4] + 800680c: 681b ldr r3, [r3, #0] + 800680e: 3308 adds r3, #8 + 8006810: 60fb str r3, [r7, #12] + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 8006812: 68fb ldr r3, [r7, #12] + 8006814: e853 3f00 ldrex r3, [r3] + 8006818: 60bb str r3, [r7, #8] + return(result); + 800681a: 68bb ldr r3, [r7, #8] + 800681c: f423 0300 bic.w r3, r3, #8388608 @ 0x800000 + 8006820: 633b str r3, [r7, #48] @ 0x30 + 8006822: 687b ldr r3, [r7, #4] + 8006824: 681b ldr r3, [r3, #0] + 8006826: 3308 adds r3, #8 + 8006828: 6b3a ldr r2, [r7, #48] @ 0x30 + 800682a: 61ba str r2, [r7, #24] + 800682c: 617b str r3, [r7, #20] + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 800682e: 6979 ldr r1, [r7, #20] + 8006830: 69ba ldr r2, [r7, #24] + 8006832: e841 2300 strex r3, r2, [r1] + 8006836: 613b str r3, [r7, #16] + return(result); + 8006838: 693b ldr r3, [r7, #16] + 800683a: 2b00 cmp r3, #0 + 800683c: d1e5 bne.n 800680a + + /* At end of Tx process, restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + 800683e: 687b ldr r3, [r7, #4] + 8006840: 2220 movs r2, #32 + 8006842: f8c3 2088 str.w r2, [r3, #136] @ 0x88 +} + 8006846: bf00 nop + 8006848: 373c adds r7, #60 @ 0x3c + 800684a: 46bd mov sp, r7 + 800684c: bc80 pop {r7} + 800684e: 4770 bx lr + +08006850 : + * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion). + * @param huart UART handle. + * @retval None + */ +static void UART_EndRxTransfer(UART_HandleTypeDef *huart) +{ + 8006850: b480 push {r7} + 8006852: b095 sub sp, #84 @ 0x54 + 8006854: af00 add r7, sp, #0 + 8006856: 6078 str r0, [r7, #4] + /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); + 8006858: 687b ldr r3, [r7, #4] + 800685a: 681b ldr r3, [r3, #0] + 800685c: 637b str r3, [r7, #52] @ 0x34 + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 800685e: 6b7b ldr r3, [r7, #52] @ 0x34 + 8006860: e853 3f00 ldrex r3, [r3] + 8006864: 633b str r3, [r7, #48] @ 0x30 + return(result); + 8006866: 6b3b ldr r3, [r7, #48] @ 0x30 + 8006868: f423 7390 bic.w r3, r3, #288 @ 0x120 + 800686c: 64fb str r3, [r7, #76] @ 0x4c + 800686e: 687b ldr r3, [r7, #4] + 8006870: 681b ldr r3, [r3, #0] + 8006872: 461a mov r2, r3 + 8006874: 6cfb ldr r3, [r7, #76] @ 0x4c + 8006876: 643b str r3, [r7, #64] @ 0x40 + 8006878: 63fa str r2, [r7, #60] @ 0x3c + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 800687a: 6bf9 ldr r1, [r7, #60] @ 0x3c + 800687c: 6c3a ldr r2, [r7, #64] @ 0x40 + 800687e: e841 2300 strex r3, r2, [r1] + 8006882: 63bb str r3, [r7, #56] @ 0x38 + return(result); + 8006884: 6bbb ldr r3, [r7, #56] @ 0x38 + 8006886: 2b00 cmp r3, #0 + 8006888: d1e6 bne.n 8006858 + ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); + 800688a: 687b ldr r3, [r7, #4] + 800688c: 681b ldr r3, [r3, #0] + 800688e: 3308 adds r3, #8 + 8006890: 623b str r3, [r7, #32] + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 8006892: 6a3b ldr r3, [r7, #32] + 8006894: e853 3f00 ldrex r3, [r3] + 8006898: 61fb str r3, [r7, #28] + return(result); + 800689a: 69fb ldr r3, [r7, #28] + 800689c: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 + 80068a0: f023 0301 bic.w r3, r3, #1 + 80068a4: 64bb str r3, [r7, #72] @ 0x48 + 80068a6: 687b ldr r3, [r7, #4] + 80068a8: 681b ldr r3, [r3, #0] + 80068aa: 3308 adds r3, #8 + 80068ac: 6cba ldr r2, [r7, #72] @ 0x48 + 80068ae: 62fa str r2, [r7, #44] @ 0x2c + 80068b0: 62bb str r3, [r7, #40] @ 0x28 + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 80068b2: 6ab9 ldr r1, [r7, #40] @ 0x28 + 80068b4: 6afa ldr r2, [r7, #44] @ 0x2c + 80068b6: e841 2300 strex r3, r2, [r1] + 80068ba: 627b str r3, [r7, #36] @ 0x24 + return(result); + 80068bc: 6a7b ldr r3, [r7, #36] @ 0x24 + 80068be: 2b00 cmp r3, #0 + 80068c0: d1e3 bne.n 800688a + + /* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + 80068c2: 687b ldr r3, [r7, #4] + 80068c4: 6edb ldr r3, [r3, #108] @ 0x6c + 80068c6: 2b01 cmp r3, #1 + 80068c8: d118 bne.n 80068fc + { + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + 80068ca: 687b ldr r3, [r7, #4] + 80068cc: 681b ldr r3, [r3, #0] + 80068ce: 60fb str r3, [r7, #12] + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 80068d0: 68fb ldr r3, [r7, #12] + 80068d2: e853 3f00 ldrex r3, [r3] + 80068d6: 60bb str r3, [r7, #8] + return(result); + 80068d8: 68bb ldr r3, [r7, #8] + 80068da: f023 0310 bic.w r3, r3, #16 + 80068de: 647b str r3, [r7, #68] @ 0x44 + 80068e0: 687b ldr r3, [r7, #4] + 80068e2: 681b ldr r3, [r3, #0] + 80068e4: 461a mov r2, r3 + 80068e6: 6c7b ldr r3, [r7, #68] @ 0x44 + 80068e8: 61bb str r3, [r7, #24] + 80068ea: 617a str r2, [r7, #20] + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 80068ec: 6979 ldr r1, [r7, #20] + 80068ee: 69ba ldr r2, [r7, #24] + 80068f0: e841 2300 strex r3, r2, [r1] + 80068f4: 613b str r3, [r7, #16] + return(result); + 80068f6: 693b ldr r3, [r7, #16] + 80068f8: 2b00 cmp r3, #0 + 80068fa: d1e6 bne.n 80068ca + } + + /* At end of Rx process, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + 80068fc: 687b ldr r3, [r7, #4] + 80068fe: 2220 movs r2, #32 + 8006900: f8c3 208c str.w r2, [r3, #140] @ 0x8c + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + 8006904: 687b ldr r3, [r7, #4] + 8006906: 2200 movs r2, #0 + 8006908: 66da str r2, [r3, #108] @ 0x6c + + /* Reset RxIsr function pointer */ + huart->RxISR = NULL; + 800690a: 687b ldr r3, [r7, #4] + 800690c: 2200 movs r2, #0 + 800690e: 675a str r2, [r3, #116] @ 0x74 +} + 8006910: bf00 nop + 8006912: 3754 adds r7, #84 @ 0x54 + 8006914: 46bd mov sp, r7 + 8006916: bc80 pop {r7} + 8006918: 4770 bx lr + +0800691a : + * @brief DMA UART transmit process complete callback. + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma) +{ + 800691a: b580 push {r7, lr} + 800691c: b090 sub sp, #64 @ 0x40 + 800691e: af00 add r7, sp, #0 + 8006920: 6078 str r0, [r7, #4] + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + 8006922: 687b ldr r3, [r7, #4] + 8006924: 6a9b ldr r3, [r3, #40] @ 0x28 + 8006926: 63fb str r3, [r7, #60] @ 0x3c + + /* DMA Normal mode */ + if (HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC)) + 8006928: 687b ldr r3, [r7, #4] + 800692a: 681b ldr r3, [r3, #0] + 800692c: 681b ldr r3, [r3, #0] + 800692e: f003 0320 and.w r3, r3, #32 + 8006932: 2b00 cmp r3, #0 + 8006934: d133 bne.n 800699e + { + /* Disable the DMA transfer for transmit request by resetting the DMAT bit + in the UART CR3 register */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + 8006936: 6bfb ldr r3, [r7, #60] @ 0x3c + 8006938: 681b ldr r3, [r3, #0] + 800693a: 3308 adds r3, #8 + 800693c: 627b str r3, [r7, #36] @ 0x24 + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 800693e: 6a7b ldr r3, [r7, #36] @ 0x24 + 8006940: e853 3f00 ldrex r3, [r3] + 8006944: 623b str r3, [r7, #32] + return(result); + 8006946: 6a3b ldr r3, [r7, #32] + 8006948: f023 0380 bic.w r3, r3, #128 @ 0x80 + 800694c: 63bb str r3, [r7, #56] @ 0x38 + 800694e: 6bfb ldr r3, [r7, #60] @ 0x3c + 8006950: 681b ldr r3, [r3, #0] + 8006952: 3308 adds r3, #8 + 8006954: 6bba ldr r2, [r7, #56] @ 0x38 + 8006956: 633a str r2, [r7, #48] @ 0x30 + 8006958: 62fb str r3, [r7, #44] @ 0x2c + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 800695a: 6af9 ldr r1, [r7, #44] @ 0x2c + 800695c: 6b3a ldr r2, [r7, #48] @ 0x30 + 800695e: e841 2300 strex r3, r2, [r1] + 8006962: 62bb str r3, [r7, #40] @ 0x28 + return(result); + 8006964: 6abb ldr r3, [r7, #40] @ 0x28 + 8006966: 2b00 cmp r3, #0 + 8006968: d1e5 bne.n 8006936 + + /* Enable the UART Transmit Complete Interrupt */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); + 800696a: 6bfb ldr r3, [r7, #60] @ 0x3c + 800696c: 681b ldr r3, [r3, #0] + 800696e: 613b str r3, [r7, #16] + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 8006970: 693b ldr r3, [r7, #16] + 8006972: e853 3f00 ldrex r3, [r3] + 8006976: 60fb str r3, [r7, #12] + return(result); + 8006978: 68fb ldr r3, [r7, #12] + 800697a: f043 0340 orr.w r3, r3, #64 @ 0x40 + 800697e: 637b str r3, [r7, #52] @ 0x34 + 8006980: 6bfb ldr r3, [r7, #60] @ 0x3c + 8006982: 681b ldr r3, [r3, #0] + 8006984: 461a mov r2, r3 + 8006986: 6b7b ldr r3, [r7, #52] @ 0x34 + 8006988: 61fb str r3, [r7, #28] + 800698a: 61ba str r2, [r7, #24] + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 800698c: 69b9 ldr r1, [r7, #24] + 800698e: 69fa ldr r2, [r7, #28] + 8006990: e841 2300 strex r3, r2, [r1] + 8006994: 617b str r3, [r7, #20] + return(result); + 8006996: 697b ldr r3, [r7, #20] + 8006998: 2b00 cmp r3, #0 + 800699a: d1e6 bne.n 800696a +#else + /*Call legacy weak Tx complete callback*/ + HAL_UART_TxCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } +} + 800699c: e002 b.n 80069a4 + HAL_UART_TxCpltCallback(huart); + 800699e: 6bf8 ldr r0, [r7, #60] @ 0x3c + 80069a0: f7fa fe5a bl 8001658 +} + 80069a4: bf00 nop + 80069a6: 3740 adds r7, #64 @ 0x40 + 80069a8: 46bd mov sp, r7 + 80069aa: bd80 pop {r7, pc} + +080069ac : + * @brief DMA UART transmit process half complete callback. + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma) +{ + 80069ac: b580 push {r7, lr} + 80069ae: b084 sub sp, #16 + 80069b0: af00 add r7, sp, #0 + 80069b2: 6078 str r0, [r7, #4] + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + 80069b4: 687b ldr r3, [r7, #4] + 80069b6: 6a9b ldr r3, [r3, #40] @ 0x28 + 80069b8: 60fb str r3, [r7, #12] +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Tx Half complete callback*/ + huart->TxHalfCpltCallback(huart); +#else + /*Call legacy weak Tx Half complete callback*/ + HAL_UART_TxHalfCpltCallback(huart); + 80069ba: 68f8 ldr r0, [r7, #12] + 80069bc: f7ff f99e bl 8005cfc +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + 80069c0: bf00 nop + 80069c2: 3710 adds r7, #16 + 80069c4: 46bd mov sp, r7 + 80069c6: bd80 pop {r7, pc} + +080069c8 : + * @brief DMA UART communication error callback. + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMAError(DMA_HandleTypeDef *hdma) +{ + 80069c8: b580 push {r7, lr} + 80069ca: b086 sub sp, #24 + 80069cc: af00 add r7, sp, #0 + 80069ce: 6078 str r0, [r7, #4] + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + 80069d0: 687b ldr r3, [r7, #4] + 80069d2: 6a9b ldr r3, [r3, #40] @ 0x28 + 80069d4: 617b str r3, [r7, #20] + + const HAL_UART_StateTypeDef gstate = huart->gState; + 80069d6: 697b ldr r3, [r7, #20] + 80069d8: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 + 80069dc: 613b str r3, [r7, #16] + const HAL_UART_StateTypeDef rxstate = huart->RxState; + 80069de: 697b ldr r3, [r7, #20] + 80069e0: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c + 80069e4: 60fb str r3, [r7, #12] + + /* Stop UART DMA Tx request if ongoing */ + if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) && + 80069e6: 697b ldr r3, [r7, #20] + 80069e8: 681b ldr r3, [r3, #0] + 80069ea: 689b ldr r3, [r3, #8] + 80069ec: f003 0380 and.w r3, r3, #128 @ 0x80 + 80069f0: 2b80 cmp r3, #128 @ 0x80 + 80069f2: d105 bne.n 8006a00 + 80069f4: 693b ldr r3, [r7, #16] + 80069f6: 2b21 cmp r3, #33 @ 0x21 + 80069f8: d102 bne.n 8006a00 + (gstate == HAL_UART_STATE_BUSY_TX)) + { + UART_EndTxTransfer(huart); + 80069fa: 6978 ldr r0, [r7, #20] + 80069fc: f7ff fee8 bl 80067d0 + } + + /* Stop UART DMA Rx request if ongoing */ + if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) && + 8006a00: 697b ldr r3, [r7, #20] + 8006a02: 681b ldr r3, [r3, #0] + 8006a04: 689b ldr r3, [r3, #8] + 8006a06: f003 0340 and.w r3, r3, #64 @ 0x40 + 8006a0a: 2b40 cmp r3, #64 @ 0x40 + 8006a0c: d105 bne.n 8006a1a + 8006a0e: 68fb ldr r3, [r7, #12] + 8006a10: 2b22 cmp r3, #34 @ 0x22 + 8006a12: d102 bne.n 8006a1a + (rxstate == HAL_UART_STATE_BUSY_RX)) + { + UART_EndRxTransfer(huart); + 8006a14: 6978 ldr r0, [r7, #20] + 8006a16: f7ff ff1b bl 8006850 + } + + huart->ErrorCode |= HAL_UART_ERROR_DMA; + 8006a1a: 697b ldr r3, [r7, #20] + 8006a1c: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 8006a20: f043 0210 orr.w r2, r3, #16 + 8006a24: 697b ldr r3, [r7, #20] + 8006a26: f8c3 2090 str.w r2, [r3, #144] @ 0x90 +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); + 8006a2a: 6978 ldr r0, [r7, #20] + 8006a2c: f7ff f96f bl 8005d0e +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + 8006a30: bf00 nop + 8006a32: 3718 adds r7, #24 + 8006a34: 46bd mov sp, r7 + 8006a36: bd80 pop {r7, pc} + +08006a38 : + * (To be called at end of DMA Abort procedure following error occurrence). + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma) +{ + 8006a38: b580 push {r7, lr} + 8006a3a: b084 sub sp, #16 + 8006a3c: af00 add r7, sp, #0 + 8006a3e: 6078 str r0, [r7, #4] + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + 8006a40: 687b ldr r3, [r7, #4] + 8006a42: 6a9b ldr r3, [r3, #40] @ 0x28 + 8006a44: 60fb str r3, [r7, #12] +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); + 8006a46: 68f8 ldr r0, [r7, #12] + 8006a48: f7ff f961 bl 8005d0e +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + 8006a4c: bf00 nop + 8006a4e: 3710 adds r7, #16 + 8006a50: 46bd mov sp, r7 + 8006a52: bd80 pop {r7, pc} + +08006a54 : + * @param huart pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval None + */ +static void UART_EndTransmit_IT(UART_HandleTypeDef *huart) +{ + 8006a54: b580 push {r7, lr} + 8006a56: b088 sub sp, #32 + 8006a58: af00 add r7, sp, #0 + 8006a5a: 6078 str r0, [r7, #4] + /* Disable the UART Transmit Complete Interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE); + 8006a5c: 687b ldr r3, [r7, #4] + 8006a5e: 681b ldr r3, [r3, #0] + 8006a60: 60fb str r3, [r7, #12] + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 8006a62: 68fb ldr r3, [r7, #12] + 8006a64: e853 3f00 ldrex r3, [r3] + 8006a68: 60bb str r3, [r7, #8] + return(result); + 8006a6a: 68bb ldr r3, [r7, #8] + 8006a6c: f023 0340 bic.w r3, r3, #64 @ 0x40 + 8006a70: 61fb str r3, [r7, #28] + 8006a72: 687b ldr r3, [r7, #4] + 8006a74: 681b ldr r3, [r3, #0] + 8006a76: 461a mov r2, r3 + 8006a78: 69fb ldr r3, [r7, #28] + 8006a7a: 61bb str r3, [r7, #24] + 8006a7c: 617a str r2, [r7, #20] + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 8006a7e: 6979 ldr r1, [r7, #20] + 8006a80: 69ba ldr r2, [r7, #24] + 8006a82: e841 2300 strex r3, r2, [r1] + 8006a86: 613b str r3, [r7, #16] + return(result); + 8006a88: 693b ldr r3, [r7, #16] + 8006a8a: 2b00 cmp r3, #0 + 8006a8c: d1e6 bne.n 8006a5c + + /* Tx process is ended, restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + 8006a8e: 687b ldr r3, [r7, #4] + 8006a90: 2220 movs r2, #32 + 8006a92: f8c3 2088 str.w r2, [r3, #136] @ 0x88 + + /* Cleat TxISR function pointer */ + huart->TxISR = NULL; + 8006a96: 687b ldr r3, [r7, #4] + 8006a98: 2200 movs r2, #0 + 8006a9a: 679a str r2, [r3, #120] @ 0x78 +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Tx complete callback*/ + huart->TxCpltCallback(huart); +#else + /*Call legacy weak Tx complete callback*/ + HAL_UART_TxCpltCallback(huart); + 8006a9c: 6878 ldr r0, [r7, #4] + 8006a9e: f7fa fddb bl 8001658 +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + 8006aa2: bf00 nop + 8006aa4: 3720 adds r7, #32 + 8006aa6: 46bd mov sp, r7 + 8006aa8: bd80 pop {r7, pc} + ... + +08006aac : + * @brief RX interrupt handler for 7 or 8 bits data word length . + * @param huart UART handle. + * @retval None + */ +static void UART_RxISR_8BIT(UART_HandleTypeDef *huart) +{ + 8006aac: b580 push {r7, lr} + 8006aae: b09c sub sp, #112 @ 0x70 + 8006ab0: af00 add r7, sp, #0 + 8006ab2: 6078 str r0, [r7, #4] + uint16_t uhMask = huart->Mask; + 8006ab4: 687b ldr r3, [r7, #4] + 8006ab6: f8b3 3060 ldrh.w r3, [r3, #96] @ 0x60 + 8006aba: f8a7 306e strh.w r3, [r7, #110] @ 0x6e + uint16_t uhdata; + + /* Check that a Rx process is ongoing */ + if (huart->RxState == HAL_UART_STATE_BUSY_RX) + 8006abe: 687b ldr r3, [r7, #4] + 8006ac0: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c + 8006ac4: 2b22 cmp r3, #34 @ 0x22 + 8006ac6: f040 80be bne.w 8006c46 + { + uhdata = (uint16_t) READ_REG(huart->Instance->RDR); + 8006aca: 687b ldr r3, [r7, #4] + 8006acc: 681b ldr r3, [r3, #0] + 8006ace: 6a5b ldr r3, [r3, #36] @ 0x24 + 8006ad0: f8a7 306c strh.w r3, [r7, #108] @ 0x6c + *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask); + 8006ad4: f8b7 306c ldrh.w r3, [r7, #108] @ 0x6c + 8006ad8: b2d9 uxtb r1, r3 + 8006ada: f8b7 306e ldrh.w r3, [r7, #110] @ 0x6e + 8006ade: b2da uxtb r2, r3 + 8006ae0: 687b ldr r3, [r7, #4] + 8006ae2: 6d9b ldr r3, [r3, #88] @ 0x58 + 8006ae4: 400a ands r2, r1 + 8006ae6: b2d2 uxtb r2, r2 + 8006ae8: 701a strb r2, [r3, #0] + huart->pRxBuffPtr++; + 8006aea: 687b ldr r3, [r7, #4] + 8006aec: 6d9b ldr r3, [r3, #88] @ 0x58 + 8006aee: 1c5a adds r2, r3, #1 + 8006af0: 687b ldr r3, [r7, #4] + 8006af2: 659a str r2, [r3, #88] @ 0x58 + huart->RxXferCount--; + 8006af4: 687b ldr r3, [r7, #4] + 8006af6: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e + 8006afa: b29b uxth r3, r3 + 8006afc: 3b01 subs r3, #1 + 8006afe: b29a uxth r2, r3 + 8006b00: 687b ldr r3, [r7, #4] + 8006b02: f8a3 205e strh.w r2, [r3, #94] @ 0x5e + + if (huart->RxXferCount == 0U) + 8006b06: 687b ldr r3, [r7, #4] + 8006b08: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e + 8006b0c: b29b uxth r3, r3 + 8006b0e: 2b00 cmp r3, #0 + 8006b10: f040 80a1 bne.w 8006c56 + { + /* Disable the UART Parity Error Interrupt and RXNE interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); + 8006b14: 687b ldr r3, [r7, #4] + 8006b16: 681b ldr r3, [r3, #0] + 8006b18: 64fb str r3, [r7, #76] @ 0x4c + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 8006b1a: 6cfb ldr r3, [r7, #76] @ 0x4c + 8006b1c: e853 3f00 ldrex r3, [r3] + 8006b20: 64bb str r3, [r7, #72] @ 0x48 + return(result); + 8006b22: 6cbb ldr r3, [r7, #72] @ 0x48 + 8006b24: f423 7390 bic.w r3, r3, #288 @ 0x120 + 8006b28: 66bb str r3, [r7, #104] @ 0x68 + 8006b2a: 687b ldr r3, [r7, #4] + 8006b2c: 681b ldr r3, [r3, #0] + 8006b2e: 461a mov r2, r3 + 8006b30: 6ebb ldr r3, [r7, #104] @ 0x68 + 8006b32: 65bb str r3, [r7, #88] @ 0x58 + 8006b34: 657a str r2, [r7, #84] @ 0x54 + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 8006b36: 6d79 ldr r1, [r7, #84] @ 0x54 + 8006b38: 6dba ldr r2, [r7, #88] @ 0x58 + 8006b3a: e841 2300 strex r3, r2, [r1] + 8006b3e: 653b str r3, [r7, #80] @ 0x50 + return(result); + 8006b40: 6d3b ldr r3, [r7, #80] @ 0x50 + 8006b42: 2b00 cmp r3, #0 + 8006b44: d1e6 bne.n 8006b14 + + /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 8006b46: 687b ldr r3, [r7, #4] + 8006b48: 681b ldr r3, [r3, #0] + 8006b4a: 3308 adds r3, #8 + 8006b4c: 63bb str r3, [r7, #56] @ 0x38 + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 8006b4e: 6bbb ldr r3, [r7, #56] @ 0x38 + 8006b50: e853 3f00 ldrex r3, [r3] + 8006b54: 637b str r3, [r7, #52] @ 0x34 + return(result); + 8006b56: 6b7b ldr r3, [r7, #52] @ 0x34 + 8006b58: f023 0301 bic.w r3, r3, #1 + 8006b5c: 667b str r3, [r7, #100] @ 0x64 + 8006b5e: 687b ldr r3, [r7, #4] + 8006b60: 681b ldr r3, [r3, #0] + 8006b62: 3308 adds r3, #8 + 8006b64: 6e7a ldr r2, [r7, #100] @ 0x64 + 8006b66: 647a str r2, [r7, #68] @ 0x44 + 8006b68: 643b str r3, [r7, #64] @ 0x40 + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 8006b6a: 6c39 ldr r1, [r7, #64] @ 0x40 + 8006b6c: 6c7a ldr r2, [r7, #68] @ 0x44 + 8006b6e: e841 2300 strex r3, r2, [r1] + 8006b72: 63fb str r3, [r7, #60] @ 0x3c + return(result); + 8006b74: 6bfb ldr r3, [r7, #60] @ 0x3c + 8006b76: 2b00 cmp r3, #0 + 8006b78: d1e5 bne.n 8006b46 + + /* Rx process is completed, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + 8006b7a: 687b ldr r3, [r7, #4] + 8006b7c: 2220 movs r2, #32 + 8006b7e: f8c3 208c str.w r2, [r3, #140] @ 0x8c + + /* Clear RxISR function pointer */ + huart->RxISR = NULL; + 8006b82: 687b ldr r3, [r7, #4] + 8006b84: 2200 movs r2, #0 + 8006b86: 675a str r2, [r3, #116] @ 0x74 + + /* Initialize type of RxEvent to Transfer Complete */ + huart->RxEventType = HAL_UART_RXEVENT_TC; + 8006b88: 687b ldr r3, [r7, #4] + 8006b8a: 2200 movs r2, #0 + 8006b8c: 671a str r2, [r3, #112] @ 0x70 + + if (!(IS_LPUART_INSTANCE(huart->Instance))) + 8006b8e: 687b ldr r3, [r7, #4] + 8006b90: 681b ldr r3, [r3, #0] + 8006b92: 4a33 ldr r2, [pc, #204] @ (8006c60 ) + 8006b94: 4293 cmp r3, r2 + 8006b96: d01f beq.n 8006bd8 + { + /* Check that USART RTOEN bit is set */ + if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) + 8006b98: 687b ldr r3, [r7, #4] + 8006b9a: 681b ldr r3, [r3, #0] + 8006b9c: 685b ldr r3, [r3, #4] + 8006b9e: f403 0300 and.w r3, r3, #8388608 @ 0x800000 + 8006ba2: 2b00 cmp r3, #0 + 8006ba4: d018 beq.n 8006bd8 + { + /* Enable the UART Receiver Timeout Interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); + 8006ba6: 687b ldr r3, [r7, #4] + 8006ba8: 681b ldr r3, [r3, #0] + 8006baa: 627b str r3, [r7, #36] @ 0x24 + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 8006bac: 6a7b ldr r3, [r7, #36] @ 0x24 + 8006bae: e853 3f00 ldrex r3, [r3] + 8006bb2: 623b str r3, [r7, #32] + return(result); + 8006bb4: 6a3b ldr r3, [r7, #32] + 8006bb6: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000 + 8006bba: 663b str r3, [r7, #96] @ 0x60 + 8006bbc: 687b ldr r3, [r7, #4] + 8006bbe: 681b ldr r3, [r3, #0] + 8006bc0: 461a mov r2, r3 + 8006bc2: 6e3b ldr r3, [r7, #96] @ 0x60 + 8006bc4: 633b str r3, [r7, #48] @ 0x30 + 8006bc6: 62fa str r2, [r7, #44] @ 0x2c + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 8006bc8: 6af9 ldr r1, [r7, #44] @ 0x2c + 8006bca: 6b3a ldr r2, [r7, #48] @ 0x30 + 8006bcc: e841 2300 strex r3, r2, [r1] + 8006bd0: 62bb str r3, [r7, #40] @ 0x28 + return(result); + 8006bd2: 6abb ldr r3, [r7, #40] @ 0x28 + 8006bd4: 2b00 cmp r3, #0 + 8006bd6: d1e6 bne.n 8006ba6 + } + } + + /* Check current reception Mode : + If Reception till IDLE event has been selected : */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + 8006bd8: 687b ldr r3, [r7, #4] + 8006bda: 6edb ldr r3, [r3, #108] @ 0x6c + 8006bdc: 2b01 cmp r3, #1 + 8006bde: d12e bne.n 8006c3e + { + /* Set reception type to Standard */ + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + 8006be0: 687b ldr r3, [r7, #4] + 8006be2: 2200 movs r2, #0 + 8006be4: 66da str r2, [r3, #108] @ 0x6c + + /* Disable IDLE interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + 8006be6: 687b ldr r3, [r7, #4] + 8006be8: 681b ldr r3, [r3, #0] + 8006bea: 613b str r3, [r7, #16] + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 8006bec: 693b ldr r3, [r7, #16] + 8006bee: e853 3f00 ldrex r3, [r3] + 8006bf2: 60fb str r3, [r7, #12] + return(result); + 8006bf4: 68fb ldr r3, [r7, #12] + 8006bf6: f023 0310 bic.w r3, r3, #16 + 8006bfa: 65fb str r3, [r7, #92] @ 0x5c + 8006bfc: 687b ldr r3, [r7, #4] + 8006bfe: 681b ldr r3, [r3, #0] + 8006c00: 461a mov r2, r3 + 8006c02: 6dfb ldr r3, [r7, #92] @ 0x5c + 8006c04: 61fb str r3, [r7, #28] + 8006c06: 61ba str r2, [r7, #24] + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 8006c08: 69b9 ldr r1, [r7, #24] + 8006c0a: 69fa ldr r2, [r7, #28] + 8006c0c: e841 2300 strex r3, r2, [r1] + 8006c10: 617b str r3, [r7, #20] + return(result); + 8006c12: 697b ldr r3, [r7, #20] + 8006c14: 2b00 cmp r3, #0 + 8006c16: d1e6 bne.n 8006be6 + + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) + 8006c18: 687b ldr r3, [r7, #4] + 8006c1a: 681b ldr r3, [r3, #0] + 8006c1c: 69db ldr r3, [r3, #28] + 8006c1e: f003 0310 and.w r3, r3, #16 + 8006c22: 2b10 cmp r3, #16 + 8006c24: d103 bne.n 8006c2e + { + /* Clear IDLE Flag */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + 8006c26: 687b ldr r3, [r7, #4] + 8006c28: 681b ldr r3, [r3, #0] + 8006c2a: 2210 movs r2, #16 + 8006c2c: 621a str r2, [r3, #32] +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, huart->RxXferSize); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); + 8006c2e: 687b ldr r3, [r7, #4] + 8006c30: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c + 8006c34: 4619 mov r1, r3 + 8006c36: 6878 ldr r0, [r7, #4] + 8006c38: f7ff f872 bl 8005d20 + else + { + /* Clear RXNE interrupt flag */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + } +} + 8006c3c: e00b b.n 8006c56 + HAL_UART_RxCpltCallback(huart); + 8006c3e: 6878 ldr r0, [r7, #4] + 8006c40: f7fa fd20 bl 8001684 +} + 8006c44: e007 b.n 8006c56 + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + 8006c46: 687b ldr r3, [r7, #4] + 8006c48: 681b ldr r3, [r3, #0] + 8006c4a: 699a ldr r2, [r3, #24] + 8006c4c: 687b ldr r3, [r7, #4] + 8006c4e: 681b ldr r3, [r3, #0] + 8006c50: f042 0208 orr.w r2, r2, #8 + 8006c54: 619a str r2, [r3, #24] +} + 8006c56: bf00 nop + 8006c58: 3770 adds r7, #112 @ 0x70 + 8006c5a: 46bd mov sp, r7 + 8006c5c: bd80 pop {r7, pc} + 8006c5e: bf00 nop + 8006c60: 40008000 .word 0x40008000 + +08006c64 : + * interruptions have been enabled by HAL_UART_Receive_IT() + * @param huart UART handle. + * @retval None + */ +static void UART_RxISR_16BIT(UART_HandleTypeDef *huart) +{ + 8006c64: b580 push {r7, lr} + 8006c66: b09c sub sp, #112 @ 0x70 + 8006c68: af00 add r7, sp, #0 + 8006c6a: 6078 str r0, [r7, #4] + uint16_t *tmp; + uint16_t uhMask = huart->Mask; + 8006c6c: 687b ldr r3, [r7, #4] + 8006c6e: f8b3 3060 ldrh.w r3, [r3, #96] @ 0x60 + 8006c72: f8a7 306e strh.w r3, [r7, #110] @ 0x6e + uint16_t uhdata; + + /* Check that a Rx process is ongoing */ + if (huart->RxState == HAL_UART_STATE_BUSY_RX) + 8006c76: 687b ldr r3, [r7, #4] + 8006c78: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c + 8006c7c: 2b22 cmp r3, #34 @ 0x22 + 8006c7e: f040 80be bne.w 8006dfe + { + uhdata = (uint16_t) READ_REG(huart->Instance->RDR); + 8006c82: 687b ldr r3, [r7, #4] + 8006c84: 681b ldr r3, [r3, #0] + 8006c86: 6a5b ldr r3, [r3, #36] @ 0x24 + 8006c88: f8a7 306c strh.w r3, [r7, #108] @ 0x6c + tmp = (uint16_t *) huart->pRxBuffPtr ; + 8006c8c: 687b ldr r3, [r7, #4] + 8006c8e: 6d9b ldr r3, [r3, #88] @ 0x58 + 8006c90: 66bb str r3, [r7, #104] @ 0x68 + *tmp = (uint16_t)(uhdata & uhMask); + 8006c92: f8b7 206c ldrh.w r2, [r7, #108] @ 0x6c + 8006c96: f8b7 306e ldrh.w r3, [r7, #110] @ 0x6e + 8006c9a: 4013 ands r3, r2 + 8006c9c: b29a uxth r2, r3 + 8006c9e: 6ebb ldr r3, [r7, #104] @ 0x68 + 8006ca0: 801a strh r2, [r3, #0] + huart->pRxBuffPtr += 2U; + 8006ca2: 687b ldr r3, [r7, #4] + 8006ca4: 6d9b ldr r3, [r3, #88] @ 0x58 + 8006ca6: 1c9a adds r2, r3, #2 + 8006ca8: 687b ldr r3, [r7, #4] + 8006caa: 659a str r2, [r3, #88] @ 0x58 + huart->RxXferCount--; + 8006cac: 687b ldr r3, [r7, #4] + 8006cae: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e + 8006cb2: b29b uxth r3, r3 + 8006cb4: 3b01 subs r3, #1 + 8006cb6: b29a uxth r2, r3 + 8006cb8: 687b ldr r3, [r7, #4] + 8006cba: f8a3 205e strh.w r2, [r3, #94] @ 0x5e + + if (huart->RxXferCount == 0U) + 8006cbe: 687b ldr r3, [r7, #4] + 8006cc0: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e + 8006cc4: b29b uxth r3, r3 + 8006cc6: 2b00 cmp r3, #0 + 8006cc8: f040 80a1 bne.w 8006e0e + { + /* Disable the UART Parity Error Interrupt and RXNE interrupt*/ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); + 8006ccc: 687b ldr r3, [r7, #4] + 8006cce: 681b ldr r3, [r3, #0] + 8006cd0: 64bb str r3, [r7, #72] @ 0x48 + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 8006cd2: 6cbb ldr r3, [r7, #72] @ 0x48 + 8006cd4: e853 3f00 ldrex r3, [r3] + 8006cd8: 647b str r3, [r7, #68] @ 0x44 + return(result); + 8006cda: 6c7b ldr r3, [r7, #68] @ 0x44 + 8006cdc: f423 7390 bic.w r3, r3, #288 @ 0x120 + 8006ce0: 667b str r3, [r7, #100] @ 0x64 + 8006ce2: 687b ldr r3, [r7, #4] + 8006ce4: 681b ldr r3, [r3, #0] + 8006ce6: 461a mov r2, r3 + 8006ce8: 6e7b ldr r3, [r7, #100] @ 0x64 + 8006cea: 657b str r3, [r7, #84] @ 0x54 + 8006cec: 653a str r2, [r7, #80] @ 0x50 + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 8006cee: 6d39 ldr r1, [r7, #80] @ 0x50 + 8006cf0: 6d7a ldr r2, [r7, #84] @ 0x54 + 8006cf2: e841 2300 strex r3, r2, [r1] + 8006cf6: 64fb str r3, [r7, #76] @ 0x4c + return(result); + 8006cf8: 6cfb ldr r3, [r7, #76] @ 0x4c + 8006cfa: 2b00 cmp r3, #0 + 8006cfc: d1e6 bne.n 8006ccc + + /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 8006cfe: 687b ldr r3, [r7, #4] + 8006d00: 681b ldr r3, [r3, #0] + 8006d02: 3308 adds r3, #8 + 8006d04: 637b str r3, [r7, #52] @ 0x34 + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 8006d06: 6b7b ldr r3, [r7, #52] @ 0x34 + 8006d08: e853 3f00 ldrex r3, [r3] + 8006d0c: 633b str r3, [r7, #48] @ 0x30 + return(result); + 8006d0e: 6b3b ldr r3, [r7, #48] @ 0x30 + 8006d10: f023 0301 bic.w r3, r3, #1 + 8006d14: 663b str r3, [r7, #96] @ 0x60 + 8006d16: 687b ldr r3, [r7, #4] + 8006d18: 681b ldr r3, [r3, #0] + 8006d1a: 3308 adds r3, #8 + 8006d1c: 6e3a ldr r2, [r7, #96] @ 0x60 + 8006d1e: 643a str r2, [r7, #64] @ 0x40 + 8006d20: 63fb str r3, [r7, #60] @ 0x3c + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 8006d22: 6bf9 ldr r1, [r7, #60] @ 0x3c + 8006d24: 6c3a ldr r2, [r7, #64] @ 0x40 + 8006d26: e841 2300 strex r3, r2, [r1] + 8006d2a: 63bb str r3, [r7, #56] @ 0x38 + return(result); + 8006d2c: 6bbb ldr r3, [r7, #56] @ 0x38 + 8006d2e: 2b00 cmp r3, #0 + 8006d30: d1e5 bne.n 8006cfe + + /* Rx process is completed, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + 8006d32: 687b ldr r3, [r7, #4] + 8006d34: 2220 movs r2, #32 + 8006d36: f8c3 208c str.w r2, [r3, #140] @ 0x8c + + /* Clear RxISR function pointer */ + huart->RxISR = NULL; + 8006d3a: 687b ldr r3, [r7, #4] + 8006d3c: 2200 movs r2, #0 + 8006d3e: 675a str r2, [r3, #116] @ 0x74 + + /* Initialize type of RxEvent to Transfer Complete */ + huart->RxEventType = HAL_UART_RXEVENT_TC; + 8006d40: 687b ldr r3, [r7, #4] + 8006d42: 2200 movs r2, #0 + 8006d44: 671a str r2, [r3, #112] @ 0x70 + + if (!(IS_LPUART_INSTANCE(huart->Instance))) + 8006d46: 687b ldr r3, [r7, #4] + 8006d48: 681b ldr r3, [r3, #0] + 8006d4a: 4a33 ldr r2, [pc, #204] @ (8006e18 ) + 8006d4c: 4293 cmp r3, r2 + 8006d4e: d01f beq.n 8006d90 + { + /* Check that USART RTOEN bit is set */ + if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) + 8006d50: 687b ldr r3, [r7, #4] + 8006d52: 681b ldr r3, [r3, #0] + 8006d54: 685b ldr r3, [r3, #4] + 8006d56: f403 0300 and.w r3, r3, #8388608 @ 0x800000 + 8006d5a: 2b00 cmp r3, #0 + 8006d5c: d018 beq.n 8006d90 + { + /* Enable the UART Receiver Timeout Interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); + 8006d5e: 687b ldr r3, [r7, #4] + 8006d60: 681b ldr r3, [r3, #0] + 8006d62: 623b str r3, [r7, #32] + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 8006d64: 6a3b ldr r3, [r7, #32] + 8006d66: e853 3f00 ldrex r3, [r3] + 8006d6a: 61fb str r3, [r7, #28] + return(result); + 8006d6c: 69fb ldr r3, [r7, #28] + 8006d6e: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000 + 8006d72: 65fb str r3, [r7, #92] @ 0x5c + 8006d74: 687b ldr r3, [r7, #4] + 8006d76: 681b ldr r3, [r3, #0] + 8006d78: 461a mov r2, r3 + 8006d7a: 6dfb ldr r3, [r7, #92] @ 0x5c + 8006d7c: 62fb str r3, [r7, #44] @ 0x2c + 8006d7e: 62ba str r2, [r7, #40] @ 0x28 + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 8006d80: 6ab9 ldr r1, [r7, #40] @ 0x28 + 8006d82: 6afa ldr r2, [r7, #44] @ 0x2c + 8006d84: e841 2300 strex r3, r2, [r1] + 8006d88: 627b str r3, [r7, #36] @ 0x24 + return(result); + 8006d8a: 6a7b ldr r3, [r7, #36] @ 0x24 + 8006d8c: 2b00 cmp r3, #0 + 8006d8e: d1e6 bne.n 8006d5e + } + } + + /* Check current reception Mode : + If Reception till IDLE event has been selected : */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + 8006d90: 687b ldr r3, [r7, #4] + 8006d92: 6edb ldr r3, [r3, #108] @ 0x6c + 8006d94: 2b01 cmp r3, #1 + 8006d96: d12e bne.n 8006df6 + { + /* Set reception type to Standard */ + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + 8006d98: 687b ldr r3, [r7, #4] + 8006d9a: 2200 movs r2, #0 + 8006d9c: 66da str r2, [r3, #108] @ 0x6c + + /* Disable IDLE interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + 8006d9e: 687b ldr r3, [r7, #4] + 8006da0: 681b ldr r3, [r3, #0] + 8006da2: 60fb str r3, [r7, #12] + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 8006da4: 68fb ldr r3, [r7, #12] + 8006da6: e853 3f00 ldrex r3, [r3] + 8006daa: 60bb str r3, [r7, #8] + return(result); + 8006dac: 68bb ldr r3, [r7, #8] + 8006dae: f023 0310 bic.w r3, r3, #16 + 8006db2: 65bb str r3, [r7, #88] @ 0x58 + 8006db4: 687b ldr r3, [r7, #4] + 8006db6: 681b ldr r3, [r3, #0] + 8006db8: 461a mov r2, r3 + 8006dba: 6dbb ldr r3, [r7, #88] @ 0x58 + 8006dbc: 61bb str r3, [r7, #24] + 8006dbe: 617a str r2, [r7, #20] + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 8006dc0: 6979 ldr r1, [r7, #20] + 8006dc2: 69ba ldr r2, [r7, #24] + 8006dc4: e841 2300 strex r3, r2, [r1] + 8006dc8: 613b str r3, [r7, #16] + return(result); + 8006dca: 693b ldr r3, [r7, #16] + 8006dcc: 2b00 cmp r3, #0 + 8006dce: d1e6 bne.n 8006d9e + + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) + 8006dd0: 687b ldr r3, [r7, #4] + 8006dd2: 681b ldr r3, [r3, #0] + 8006dd4: 69db ldr r3, [r3, #28] + 8006dd6: f003 0310 and.w r3, r3, #16 + 8006dda: 2b10 cmp r3, #16 + 8006ddc: d103 bne.n 8006de6 + { + /* Clear IDLE Flag */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + 8006dde: 687b ldr r3, [r7, #4] + 8006de0: 681b ldr r3, [r3, #0] + 8006de2: 2210 movs r2, #16 + 8006de4: 621a str r2, [r3, #32] +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, huart->RxXferSize); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); + 8006de6: 687b ldr r3, [r7, #4] + 8006de8: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c + 8006dec: 4619 mov r1, r3 + 8006dee: 6878 ldr r0, [r7, #4] + 8006df0: f7fe ff96 bl 8005d20 + else + { + /* Clear RXNE interrupt flag */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + } +} + 8006df4: e00b b.n 8006e0e + HAL_UART_RxCpltCallback(huart); + 8006df6: 6878 ldr r0, [r7, #4] + 8006df8: f7fa fc44 bl 8001684 +} + 8006dfc: e007 b.n 8006e0e + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + 8006dfe: 687b ldr r3, [r7, #4] + 8006e00: 681b ldr r3, [r3, #0] + 8006e02: 699a ldr r2, [r3, #24] + 8006e04: 687b ldr r3, [r7, #4] + 8006e06: 681b ldr r3, [r3, #0] + 8006e08: f042 0208 orr.w r2, r2, #8 + 8006e0c: 619a str r2, [r3, #24] +} + 8006e0e: bf00 nop + 8006e10: 3770 adds r7, #112 @ 0x70 + 8006e12: 46bd mov sp, r7 + 8006e14: bd80 pop {r7, pc} + 8006e16: bf00 nop + 8006e18: 40008000 .word 0x40008000 + +08006e1c : + * interruptions have been enabled by HAL_UART_Receive_IT() + * @param huart UART handle. + * @retval None + */ +static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) +{ + 8006e1c: b580 push {r7, lr} + 8006e1e: b0ac sub sp, #176 @ 0xb0 + 8006e20: af00 add r7, sp, #0 + 8006e22: 6078 str r0, [r7, #4] + uint16_t uhMask = huart->Mask; + 8006e24: 687b ldr r3, [r7, #4] + 8006e26: f8b3 3060 ldrh.w r3, [r3, #96] @ 0x60 + 8006e2a: f8a7 30aa strh.w r3, [r7, #170] @ 0xaa + uint16_t uhdata; + uint16_t nb_rx_data; + uint16_t rxdatacount; + uint32_t isrflags = READ_REG(huart->Instance->ISR); + 8006e2e: 687b ldr r3, [r7, #4] + 8006e30: 681b ldr r3, [r3, #0] + 8006e32: 69db ldr r3, [r3, #28] + 8006e34: f8c7 30ac str.w r3, [r7, #172] @ 0xac + uint32_t cr1its = READ_REG(huart->Instance->CR1); + 8006e38: 687b ldr r3, [r7, #4] + 8006e3a: 681b ldr r3, [r3, #0] + 8006e3c: 681b ldr r3, [r3, #0] + 8006e3e: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4 + uint32_t cr3its = READ_REG(huart->Instance->CR3); + 8006e42: 687b ldr r3, [r7, #4] + 8006e44: 681b ldr r3, [r3, #0] + 8006e46: 689b ldr r3, [r3, #8] + 8006e48: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0 + + /* Check that a Rx process is ongoing */ + if (huart->RxState == HAL_UART_STATE_BUSY_RX) + 8006e4c: 687b ldr r3, [r7, #4] + 8006e4e: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c + 8006e52: 2b22 cmp r3, #34 @ 0x22 + 8006e54: f040 8183 bne.w 800715e + { + nb_rx_data = huart->NbRxDataToProcess; + 8006e58: 687b ldr r3, [r7, #4] + 8006e5a: f8b3 3068 ldrh.w r3, [r3, #104] @ 0x68 + 8006e5e: f8a7 309e strh.w r3, [r7, #158] @ 0x9e + while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U)) + 8006e62: e126 b.n 80070b2 + { + uhdata = (uint16_t) READ_REG(huart->Instance->RDR); + 8006e64: 687b ldr r3, [r7, #4] + 8006e66: 681b ldr r3, [r3, #0] + 8006e68: 6a5b ldr r3, [r3, #36] @ 0x24 + 8006e6a: f8a7 309c strh.w r3, [r7, #156] @ 0x9c + *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask); + 8006e6e: f8b7 309c ldrh.w r3, [r7, #156] @ 0x9c + 8006e72: b2d9 uxtb r1, r3 + 8006e74: f8b7 30aa ldrh.w r3, [r7, #170] @ 0xaa + 8006e78: b2da uxtb r2, r3 + 8006e7a: 687b ldr r3, [r7, #4] + 8006e7c: 6d9b ldr r3, [r3, #88] @ 0x58 + 8006e7e: 400a ands r2, r1 + 8006e80: b2d2 uxtb r2, r2 + 8006e82: 701a strb r2, [r3, #0] + huart->pRxBuffPtr++; + 8006e84: 687b ldr r3, [r7, #4] + 8006e86: 6d9b ldr r3, [r3, #88] @ 0x58 + 8006e88: 1c5a adds r2, r3, #1 + 8006e8a: 687b ldr r3, [r7, #4] + 8006e8c: 659a str r2, [r3, #88] @ 0x58 + huart->RxXferCount--; + 8006e8e: 687b ldr r3, [r7, #4] + 8006e90: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e + 8006e94: b29b uxth r3, r3 + 8006e96: 3b01 subs r3, #1 + 8006e98: b29a uxth r2, r3 + 8006e9a: 687b ldr r3, [r7, #4] + 8006e9c: f8a3 205e strh.w r2, [r3, #94] @ 0x5e + isrflags = READ_REG(huart->Instance->ISR); + 8006ea0: 687b ldr r3, [r7, #4] + 8006ea2: 681b ldr r3, [r3, #0] + 8006ea4: 69db ldr r3, [r3, #28] + 8006ea6: f8c7 30ac str.w r3, [r7, #172] @ 0xac + + /* If some non blocking errors occurred */ + if ((isrflags & (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE)) != 0U) + 8006eaa: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac + 8006eae: f003 0307 and.w r3, r3, #7 + 8006eb2: 2b00 cmp r3, #0 + 8006eb4: d053 beq.n 8006f5e + { + /* UART parity error interrupt occurred -------------------------------------*/ + if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) + 8006eb6: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac + 8006eba: f003 0301 and.w r3, r3, #1 + 8006ebe: 2b00 cmp r3, #0 + 8006ec0: d011 beq.n 8006ee6 + 8006ec2: f8d7 30a4 ldr.w r3, [r7, #164] @ 0xa4 + 8006ec6: f403 7380 and.w r3, r3, #256 @ 0x100 + 8006eca: 2b00 cmp r3, #0 + 8006ecc: d00b beq.n 8006ee6 + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF); + 8006ece: 687b ldr r3, [r7, #4] + 8006ed0: 681b ldr r3, [r3, #0] + 8006ed2: 2201 movs r2, #1 + 8006ed4: 621a str r2, [r3, #32] + + huart->ErrorCode |= HAL_UART_ERROR_PE; + 8006ed6: 687b ldr r3, [r7, #4] + 8006ed8: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 8006edc: f043 0201 orr.w r2, r3, #1 + 8006ee0: 687b ldr r3, [r7, #4] + 8006ee2: f8c3 2090 str.w r2, [r3, #144] @ 0x90 + } + + /* UART frame error interrupt occurred --------------------------------------*/ + if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) + 8006ee6: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac + 8006eea: f003 0302 and.w r3, r3, #2 + 8006eee: 2b00 cmp r3, #0 + 8006ef0: d011 beq.n 8006f16 + 8006ef2: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0 + 8006ef6: f003 0301 and.w r3, r3, #1 + 8006efa: 2b00 cmp r3, #0 + 8006efc: d00b beq.n 8006f16 + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF); + 8006efe: 687b ldr r3, [r7, #4] + 8006f00: 681b ldr r3, [r3, #0] + 8006f02: 2202 movs r2, #2 + 8006f04: 621a str r2, [r3, #32] + + huart->ErrorCode |= HAL_UART_ERROR_FE; + 8006f06: 687b ldr r3, [r7, #4] + 8006f08: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 8006f0c: f043 0204 orr.w r2, r3, #4 + 8006f10: 687b ldr r3, [r7, #4] + 8006f12: f8c3 2090 str.w r2, [r3, #144] @ 0x90 + } + + /* UART noise error interrupt occurred --------------------------------------*/ + if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) + 8006f16: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac + 8006f1a: f003 0304 and.w r3, r3, #4 + 8006f1e: 2b00 cmp r3, #0 + 8006f20: d011 beq.n 8006f46 + 8006f22: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0 + 8006f26: f003 0301 and.w r3, r3, #1 + 8006f2a: 2b00 cmp r3, #0 + 8006f2c: d00b beq.n 8006f46 + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF); + 8006f2e: 687b ldr r3, [r7, #4] + 8006f30: 681b ldr r3, [r3, #0] + 8006f32: 2204 movs r2, #4 + 8006f34: 621a str r2, [r3, #32] + + huart->ErrorCode |= HAL_UART_ERROR_NE; + 8006f36: 687b ldr r3, [r7, #4] + 8006f38: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 8006f3c: f043 0202 orr.w r2, r3, #2 + 8006f40: 687b ldr r3, [r7, #4] + 8006f42: f8c3 2090 str.w r2, [r3, #144] @ 0x90 + } + + /* Call UART Error Call back function if need be ----------------------------*/ + if (huart->ErrorCode != HAL_UART_ERROR_NONE) + 8006f46: 687b ldr r3, [r7, #4] + 8006f48: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 8006f4c: 2b00 cmp r3, #0 + 8006f4e: d006 beq.n 8006f5e +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); + 8006f50: 6878 ldr r0, [r7, #4] + 8006f52: f7fe fedc bl 8005d0e +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + 8006f56: 687b ldr r3, [r7, #4] + 8006f58: 2200 movs r2, #0 + 8006f5a: f8c3 2090 str.w r2, [r3, #144] @ 0x90 + } + } + + if (huart->RxXferCount == 0U) + 8006f5e: 687b ldr r3, [r7, #4] + 8006f60: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e + 8006f64: b29b uxth r3, r3 + 8006f66: 2b00 cmp r3, #0 + 8006f68: f040 80a3 bne.w 80070b2 + { + /* Disable the UART Parity Error Interrupt and RXFT interrupt*/ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); + 8006f6c: 687b ldr r3, [r7, #4] + 8006f6e: 681b ldr r3, [r3, #0] + 8006f70: 673b str r3, [r7, #112] @ 0x70 + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 8006f72: 6f3b ldr r3, [r7, #112] @ 0x70 + 8006f74: e853 3f00 ldrex r3, [r3] + 8006f78: 66fb str r3, [r7, #108] @ 0x6c + return(result); + 8006f7a: 6efb ldr r3, [r7, #108] @ 0x6c + 8006f7c: f423 7380 bic.w r3, r3, #256 @ 0x100 + 8006f80: f8c7 3098 str.w r3, [r7, #152] @ 0x98 + 8006f84: 687b ldr r3, [r7, #4] + 8006f86: 681b ldr r3, [r3, #0] + 8006f88: 461a mov r2, r3 + 8006f8a: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98 + 8006f8e: 67fb str r3, [r7, #124] @ 0x7c + 8006f90: 67ba str r2, [r7, #120] @ 0x78 + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 8006f92: 6fb9 ldr r1, [r7, #120] @ 0x78 + 8006f94: 6ffa ldr r2, [r7, #124] @ 0x7c + 8006f96: e841 2300 strex r3, r2, [r1] + 8006f9a: 677b str r3, [r7, #116] @ 0x74 + return(result); + 8006f9c: 6f7b ldr r3, [r7, #116] @ 0x74 + 8006f9e: 2b00 cmp r3, #0 + 8006fa0: d1e4 bne.n 8006f6c + + /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) + and RX FIFO Threshold interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); + 8006fa2: 687b ldr r3, [r7, #4] + 8006fa4: 681b ldr r3, [r3, #0] + 8006fa6: 3308 adds r3, #8 + 8006fa8: 65fb str r3, [r7, #92] @ 0x5c + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 8006faa: 6dfb ldr r3, [r7, #92] @ 0x5c + 8006fac: e853 3f00 ldrex r3, [r3] + 8006fb0: 65bb str r3, [r7, #88] @ 0x58 + return(result); + 8006fb2: 6dbb ldr r3, [r7, #88] @ 0x58 + 8006fb4: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 + 8006fb8: f023 0301 bic.w r3, r3, #1 + 8006fbc: f8c7 3094 str.w r3, [r7, #148] @ 0x94 + 8006fc0: 687b ldr r3, [r7, #4] + 8006fc2: 681b ldr r3, [r3, #0] + 8006fc4: 3308 adds r3, #8 + 8006fc6: f8d7 2094 ldr.w r2, [r7, #148] @ 0x94 + 8006fca: 66ba str r2, [r7, #104] @ 0x68 + 8006fcc: 667b str r3, [r7, #100] @ 0x64 + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 8006fce: 6e79 ldr r1, [r7, #100] @ 0x64 + 8006fd0: 6eba ldr r2, [r7, #104] @ 0x68 + 8006fd2: e841 2300 strex r3, r2, [r1] + 8006fd6: 663b str r3, [r7, #96] @ 0x60 + return(result); + 8006fd8: 6e3b ldr r3, [r7, #96] @ 0x60 + 8006fda: 2b00 cmp r3, #0 + 8006fdc: d1e1 bne.n 8006fa2 + + /* Rx process is completed, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + 8006fde: 687b ldr r3, [r7, #4] + 8006fe0: 2220 movs r2, #32 + 8006fe2: f8c3 208c str.w r2, [r3, #140] @ 0x8c + + /* Clear RxISR function pointer */ + huart->RxISR = NULL; + 8006fe6: 687b ldr r3, [r7, #4] + 8006fe8: 2200 movs r2, #0 + 8006fea: 675a str r2, [r3, #116] @ 0x74 + + /* Initialize type of RxEvent to Transfer Complete */ + huart->RxEventType = HAL_UART_RXEVENT_TC; + 8006fec: 687b ldr r3, [r7, #4] + 8006fee: 2200 movs r2, #0 + 8006ff0: 671a str r2, [r3, #112] @ 0x70 + + if (!(IS_LPUART_INSTANCE(huart->Instance))) + 8006ff2: 687b ldr r3, [r7, #4] + 8006ff4: 681b ldr r3, [r3, #0] + 8006ff6: 4a60 ldr r2, [pc, #384] @ (8007178 ) + 8006ff8: 4293 cmp r3, r2 + 8006ffa: d021 beq.n 8007040 + { + /* Check that USART RTOEN bit is set */ + if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) + 8006ffc: 687b ldr r3, [r7, #4] + 8006ffe: 681b ldr r3, [r3, #0] + 8007000: 685b ldr r3, [r3, #4] + 8007002: f403 0300 and.w r3, r3, #8388608 @ 0x800000 + 8007006: 2b00 cmp r3, #0 + 8007008: d01a beq.n 8007040 + { + /* Enable the UART Receiver Timeout Interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); + 800700a: 687b ldr r3, [r7, #4] + 800700c: 681b ldr r3, [r3, #0] + 800700e: 64bb str r3, [r7, #72] @ 0x48 + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 8007010: 6cbb ldr r3, [r7, #72] @ 0x48 + 8007012: e853 3f00 ldrex r3, [r3] + 8007016: 647b str r3, [r7, #68] @ 0x44 + return(result); + 8007018: 6c7b ldr r3, [r7, #68] @ 0x44 + 800701a: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000 + 800701e: f8c7 3090 str.w r3, [r7, #144] @ 0x90 + 8007022: 687b ldr r3, [r7, #4] + 8007024: 681b ldr r3, [r3, #0] + 8007026: 461a mov r2, r3 + 8007028: f8d7 3090 ldr.w r3, [r7, #144] @ 0x90 + 800702c: 657b str r3, [r7, #84] @ 0x54 + 800702e: 653a str r2, [r7, #80] @ 0x50 + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 8007030: 6d39 ldr r1, [r7, #80] @ 0x50 + 8007032: 6d7a ldr r2, [r7, #84] @ 0x54 + 8007034: e841 2300 strex r3, r2, [r1] + 8007038: 64fb str r3, [r7, #76] @ 0x4c + return(result); + 800703a: 6cfb ldr r3, [r7, #76] @ 0x4c + 800703c: 2b00 cmp r3, #0 + 800703e: d1e4 bne.n 800700a + } + } + + /* Check current reception Mode : + If Reception till IDLE event has been selected : */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + 8007040: 687b ldr r3, [r7, #4] + 8007042: 6edb ldr r3, [r3, #108] @ 0x6c + 8007044: 2b01 cmp r3, #1 + 8007046: d130 bne.n 80070aa + { + /* Set reception type to Standard */ + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + 8007048: 687b ldr r3, [r7, #4] + 800704a: 2200 movs r2, #0 + 800704c: 66da str r2, [r3, #108] @ 0x6c + + /* Disable IDLE interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + 800704e: 687b ldr r3, [r7, #4] + 8007050: 681b ldr r3, [r3, #0] + 8007052: 637b str r3, [r7, #52] @ 0x34 + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 8007054: 6b7b ldr r3, [r7, #52] @ 0x34 + 8007056: e853 3f00 ldrex r3, [r3] + 800705a: 633b str r3, [r7, #48] @ 0x30 + return(result); + 800705c: 6b3b ldr r3, [r7, #48] @ 0x30 + 800705e: f023 0310 bic.w r3, r3, #16 + 8007062: f8c7 308c str.w r3, [r7, #140] @ 0x8c + 8007066: 687b ldr r3, [r7, #4] + 8007068: 681b ldr r3, [r3, #0] + 800706a: 461a mov r2, r3 + 800706c: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c + 8007070: 643b str r3, [r7, #64] @ 0x40 + 8007072: 63fa str r2, [r7, #60] @ 0x3c + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 8007074: 6bf9 ldr r1, [r7, #60] @ 0x3c + 8007076: 6c3a ldr r2, [r7, #64] @ 0x40 + 8007078: e841 2300 strex r3, r2, [r1] + 800707c: 63bb str r3, [r7, #56] @ 0x38 + return(result); + 800707e: 6bbb ldr r3, [r7, #56] @ 0x38 + 8007080: 2b00 cmp r3, #0 + 8007082: d1e4 bne.n 800704e + + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) + 8007084: 687b ldr r3, [r7, #4] + 8007086: 681b ldr r3, [r3, #0] + 8007088: 69db ldr r3, [r3, #28] + 800708a: f003 0310 and.w r3, r3, #16 + 800708e: 2b10 cmp r3, #16 + 8007090: d103 bne.n 800709a + { + /* Clear IDLE Flag */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + 8007092: 687b ldr r3, [r7, #4] + 8007094: 681b ldr r3, [r3, #0] + 8007096: 2210 movs r2, #16 + 8007098: 621a str r2, [r3, #32] +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, huart->RxXferSize); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); + 800709a: 687b ldr r3, [r7, #4] + 800709c: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c + 80070a0: 4619 mov r1, r3 + 80070a2: 6878 ldr r0, [r7, #4] + 80070a4: f7fe fe3c bl 8005d20 +#else + /*Call legacy weak Rx complete callback*/ + HAL_UART_RxCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + break; + 80070a8: e00e b.n 80070c8 + HAL_UART_RxCpltCallback(huart); + 80070aa: 6878 ldr r0, [r7, #4] + 80070ac: f7fa faea bl 8001684 + break; + 80070b0: e00a b.n 80070c8 + while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U)) + 80070b2: f8b7 309e ldrh.w r3, [r7, #158] @ 0x9e + 80070b6: 2b00 cmp r3, #0 + 80070b8: d006 beq.n 80070c8 + 80070ba: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac + 80070be: f003 0320 and.w r3, r3, #32 + 80070c2: 2b00 cmp r3, #0 + 80070c4: f47f aece bne.w 8006e64 + + /* When remaining number of bytes to receive is less than the RX FIFO + threshold, next incoming frames are processed as if FIFO mode was + disabled (i.e. one interrupt per received frame). + */ + rxdatacount = huart->RxXferCount; + 80070c8: 687b ldr r3, [r7, #4] + 80070ca: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e + 80070ce: f8a7 308a strh.w r3, [r7, #138] @ 0x8a + if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess)) + 80070d2: f8b7 308a ldrh.w r3, [r7, #138] @ 0x8a + 80070d6: 2b00 cmp r3, #0 + 80070d8: d049 beq.n 800716e + 80070da: 687b ldr r3, [r7, #4] + 80070dc: f8b3 3068 ldrh.w r3, [r3, #104] @ 0x68 + 80070e0: f8b7 208a ldrh.w r2, [r7, #138] @ 0x8a + 80070e4: 429a cmp r2, r3 + 80070e6: d242 bcs.n 800716e + { + /* Disable the UART RXFT interrupt*/ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); + 80070e8: 687b ldr r3, [r7, #4] + 80070ea: 681b ldr r3, [r3, #0] + 80070ec: 3308 adds r3, #8 + 80070ee: 623b str r3, [r7, #32] + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 80070f0: 6a3b ldr r3, [r7, #32] + 80070f2: e853 3f00 ldrex r3, [r3] + 80070f6: 61fb str r3, [r7, #28] + return(result); + 80070f8: 69fb ldr r3, [r7, #28] + 80070fa: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 + 80070fe: f8c7 3084 str.w r3, [r7, #132] @ 0x84 + 8007102: 687b ldr r3, [r7, #4] + 8007104: 681b ldr r3, [r3, #0] + 8007106: 3308 adds r3, #8 + 8007108: f8d7 2084 ldr.w r2, [r7, #132] @ 0x84 + 800710c: 62fa str r2, [r7, #44] @ 0x2c + 800710e: 62bb str r3, [r7, #40] @ 0x28 + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 8007110: 6ab9 ldr r1, [r7, #40] @ 0x28 + 8007112: 6afa ldr r2, [r7, #44] @ 0x2c + 8007114: e841 2300 strex r3, r2, [r1] + 8007118: 627b str r3, [r7, #36] @ 0x24 + return(result); + 800711a: 6a7b ldr r3, [r7, #36] @ 0x24 + 800711c: 2b00 cmp r3, #0 + 800711e: d1e3 bne.n 80070e8 + + /* Update the RxISR function pointer */ + huart->RxISR = UART_RxISR_8BIT; + 8007120: 687b ldr r3, [r7, #4] + 8007122: 4a16 ldr r2, [pc, #88] @ (800717c ) + 8007124: 675a str r2, [r3, #116] @ 0x74 + + /* Enable the UART Data Register Not Empty interrupt */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); + 8007126: 687b ldr r3, [r7, #4] + 8007128: 681b ldr r3, [r3, #0] + 800712a: 60fb str r3, [r7, #12] + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 800712c: 68fb ldr r3, [r7, #12] + 800712e: e853 3f00 ldrex r3, [r3] + 8007132: 60bb str r3, [r7, #8] + return(result); + 8007134: 68bb ldr r3, [r7, #8] + 8007136: f043 0320 orr.w r3, r3, #32 + 800713a: f8c7 3080 str.w r3, [r7, #128] @ 0x80 + 800713e: 687b ldr r3, [r7, #4] + 8007140: 681b ldr r3, [r3, #0] + 8007142: 461a mov r2, r3 + 8007144: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80 + 8007148: 61bb str r3, [r7, #24] + 800714a: 617a str r2, [r7, #20] + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 800714c: 6979 ldr r1, [r7, #20] + 800714e: 69ba ldr r2, [r7, #24] + 8007150: e841 2300 strex r3, r2, [r1] + 8007154: 613b str r3, [r7, #16] + return(result); + 8007156: 693b ldr r3, [r7, #16] + 8007158: 2b00 cmp r3, #0 + 800715a: d1e4 bne.n 8007126 + else + { + /* Clear RXNE interrupt flag */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + } +} + 800715c: e007 b.n 800716e + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + 800715e: 687b ldr r3, [r7, #4] + 8007160: 681b ldr r3, [r3, #0] + 8007162: 699a ldr r2, [r3, #24] + 8007164: 687b ldr r3, [r7, #4] + 8007166: 681b ldr r3, [r3, #0] + 8007168: f042 0208 orr.w r2, r2, #8 + 800716c: 619a str r2, [r3, #24] +} + 800716e: bf00 nop + 8007170: 37b0 adds r7, #176 @ 0xb0 + 8007172: 46bd mov sp, r7 + 8007174: bd80 pop {r7, pc} + 8007176: bf00 nop + 8007178: 40008000 .word 0x40008000 + 800717c: 08006aad .word 0x08006aad + +08007180 : + * interruptions have been enabled by HAL_UART_Receive_IT() + * @param huart UART handle. + * @retval None + */ +static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) +{ + 8007180: b580 push {r7, lr} + 8007182: b0ae sub sp, #184 @ 0xb8 + 8007184: af00 add r7, sp, #0 + 8007186: 6078 str r0, [r7, #4] + uint16_t *tmp; + uint16_t uhMask = huart->Mask; + 8007188: 687b ldr r3, [r7, #4] + 800718a: f8b3 3060 ldrh.w r3, [r3, #96] @ 0x60 + 800718e: f8a7 30b2 strh.w r3, [r7, #178] @ 0xb2 + uint16_t uhdata; + uint16_t nb_rx_data; + uint16_t rxdatacount; + uint32_t isrflags = READ_REG(huart->Instance->ISR); + 8007192: 687b ldr r3, [r7, #4] + 8007194: 681b ldr r3, [r3, #0] + 8007196: 69db ldr r3, [r3, #28] + 8007198: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 + uint32_t cr1its = READ_REG(huart->Instance->CR1); + 800719c: 687b ldr r3, [r7, #4] + 800719e: 681b ldr r3, [r3, #0] + 80071a0: 681b ldr r3, [r3, #0] + 80071a2: f8c7 30ac str.w r3, [r7, #172] @ 0xac + uint32_t cr3its = READ_REG(huart->Instance->CR3); + 80071a6: 687b ldr r3, [r7, #4] + 80071a8: 681b ldr r3, [r3, #0] + 80071aa: 689b ldr r3, [r3, #8] + 80071ac: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8 + + /* Check that a Rx process is ongoing */ + if (huart->RxState == HAL_UART_STATE_BUSY_RX) + 80071b0: 687b ldr r3, [r7, #4] + 80071b2: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c + 80071b6: 2b22 cmp r3, #34 @ 0x22 + 80071b8: f040 8187 bne.w 80074ca + { + nb_rx_data = huart->NbRxDataToProcess; + 80071bc: 687b ldr r3, [r7, #4] + 80071be: f8b3 3068 ldrh.w r3, [r3, #104] @ 0x68 + 80071c2: f8a7 30a6 strh.w r3, [r7, #166] @ 0xa6 + while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U)) + 80071c6: e12a b.n 800741e + { + uhdata = (uint16_t) READ_REG(huart->Instance->RDR); + 80071c8: 687b ldr r3, [r7, #4] + 80071ca: 681b ldr r3, [r3, #0] + 80071cc: 6a5b ldr r3, [r3, #36] @ 0x24 + 80071ce: f8a7 30a4 strh.w r3, [r7, #164] @ 0xa4 + tmp = (uint16_t *) huart->pRxBuffPtr ; + 80071d2: 687b ldr r3, [r7, #4] + 80071d4: 6d9b ldr r3, [r3, #88] @ 0x58 + 80071d6: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0 + *tmp = (uint16_t)(uhdata & uhMask); + 80071da: f8b7 20a4 ldrh.w r2, [r7, #164] @ 0xa4 + 80071de: f8b7 30b2 ldrh.w r3, [r7, #178] @ 0xb2 + 80071e2: 4013 ands r3, r2 + 80071e4: b29a uxth r2, r3 + 80071e6: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0 + 80071ea: 801a strh r2, [r3, #0] + huart->pRxBuffPtr += 2U; + 80071ec: 687b ldr r3, [r7, #4] + 80071ee: 6d9b ldr r3, [r3, #88] @ 0x58 + 80071f0: 1c9a adds r2, r3, #2 + 80071f2: 687b ldr r3, [r7, #4] + 80071f4: 659a str r2, [r3, #88] @ 0x58 + huart->RxXferCount--; + 80071f6: 687b ldr r3, [r7, #4] + 80071f8: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e + 80071fc: b29b uxth r3, r3 + 80071fe: 3b01 subs r3, #1 + 8007200: b29a uxth r2, r3 + 8007202: 687b ldr r3, [r7, #4] + 8007204: f8a3 205e strh.w r2, [r3, #94] @ 0x5e + isrflags = READ_REG(huart->Instance->ISR); + 8007208: 687b ldr r3, [r7, #4] + 800720a: 681b ldr r3, [r3, #0] + 800720c: 69db ldr r3, [r3, #28] + 800720e: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 + + /* If some non blocking errors occurred */ + if ((isrflags & (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE)) != 0U) + 8007212: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4 + 8007216: f003 0307 and.w r3, r3, #7 + 800721a: 2b00 cmp r3, #0 + 800721c: d053 beq.n 80072c6 + { + /* UART parity error interrupt occurred -------------------------------------*/ + if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) + 800721e: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4 + 8007222: f003 0301 and.w r3, r3, #1 + 8007226: 2b00 cmp r3, #0 + 8007228: d011 beq.n 800724e + 800722a: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac + 800722e: f403 7380 and.w r3, r3, #256 @ 0x100 + 8007232: 2b00 cmp r3, #0 + 8007234: d00b beq.n 800724e + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF); + 8007236: 687b ldr r3, [r7, #4] + 8007238: 681b ldr r3, [r3, #0] + 800723a: 2201 movs r2, #1 + 800723c: 621a str r2, [r3, #32] + + huart->ErrorCode |= HAL_UART_ERROR_PE; + 800723e: 687b ldr r3, [r7, #4] + 8007240: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 8007244: f043 0201 orr.w r2, r3, #1 + 8007248: 687b ldr r3, [r7, #4] + 800724a: f8c3 2090 str.w r2, [r3, #144] @ 0x90 + } + + /* UART frame error interrupt occurred --------------------------------------*/ + if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) + 800724e: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4 + 8007252: f003 0302 and.w r3, r3, #2 + 8007256: 2b00 cmp r3, #0 + 8007258: d011 beq.n 800727e + 800725a: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8 + 800725e: f003 0301 and.w r3, r3, #1 + 8007262: 2b00 cmp r3, #0 + 8007264: d00b beq.n 800727e + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF); + 8007266: 687b ldr r3, [r7, #4] + 8007268: 681b ldr r3, [r3, #0] + 800726a: 2202 movs r2, #2 + 800726c: 621a str r2, [r3, #32] + + huart->ErrorCode |= HAL_UART_ERROR_FE; + 800726e: 687b ldr r3, [r7, #4] + 8007270: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 8007274: f043 0204 orr.w r2, r3, #4 + 8007278: 687b ldr r3, [r7, #4] + 800727a: f8c3 2090 str.w r2, [r3, #144] @ 0x90 + } + + /* UART noise error interrupt occurred --------------------------------------*/ + if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) + 800727e: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4 + 8007282: f003 0304 and.w r3, r3, #4 + 8007286: 2b00 cmp r3, #0 + 8007288: d011 beq.n 80072ae + 800728a: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8 + 800728e: f003 0301 and.w r3, r3, #1 + 8007292: 2b00 cmp r3, #0 + 8007294: d00b beq.n 80072ae + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF); + 8007296: 687b ldr r3, [r7, #4] + 8007298: 681b ldr r3, [r3, #0] + 800729a: 2204 movs r2, #4 + 800729c: 621a str r2, [r3, #32] + + huart->ErrorCode |= HAL_UART_ERROR_NE; + 800729e: 687b ldr r3, [r7, #4] + 80072a0: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 80072a4: f043 0202 orr.w r2, r3, #2 + 80072a8: 687b ldr r3, [r7, #4] + 80072aa: f8c3 2090 str.w r2, [r3, #144] @ 0x90 + } + + /* Call UART Error Call back function if need be ----------------------------*/ + if (huart->ErrorCode != HAL_UART_ERROR_NONE) + 80072ae: 687b ldr r3, [r7, #4] + 80072b0: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 80072b4: 2b00 cmp r3, #0 + 80072b6: d006 beq.n 80072c6 +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); + 80072b8: 6878 ldr r0, [r7, #4] + 80072ba: f7fe fd28 bl 8005d0e +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + 80072be: 687b ldr r3, [r7, #4] + 80072c0: 2200 movs r2, #0 + 80072c2: f8c3 2090 str.w r2, [r3, #144] @ 0x90 + } + } + + if (huart->RxXferCount == 0U) + 80072c6: 687b ldr r3, [r7, #4] + 80072c8: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e + 80072cc: b29b uxth r3, r3 + 80072ce: 2b00 cmp r3, #0 + 80072d0: f040 80a5 bne.w 800741e + { + /* Disable the UART Parity Error Interrupt and RXFT interrupt*/ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); + 80072d4: 687b ldr r3, [r7, #4] + 80072d6: 681b ldr r3, [r3, #0] + 80072d8: 677b str r3, [r7, #116] @ 0x74 + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 80072da: 6f7b ldr r3, [r7, #116] @ 0x74 + 80072dc: e853 3f00 ldrex r3, [r3] + 80072e0: 673b str r3, [r7, #112] @ 0x70 + return(result); + 80072e2: 6f3b ldr r3, [r7, #112] @ 0x70 + 80072e4: f423 7380 bic.w r3, r3, #256 @ 0x100 + 80072e8: f8c7 309c str.w r3, [r7, #156] @ 0x9c + 80072ec: 687b ldr r3, [r7, #4] + 80072ee: 681b ldr r3, [r3, #0] + 80072f0: 461a mov r2, r3 + 80072f2: f8d7 309c ldr.w r3, [r7, #156] @ 0x9c + 80072f6: f8c7 3080 str.w r3, [r7, #128] @ 0x80 + 80072fa: 67fa str r2, [r7, #124] @ 0x7c + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 80072fc: 6ff9 ldr r1, [r7, #124] @ 0x7c + 80072fe: f8d7 2080 ldr.w r2, [r7, #128] @ 0x80 + 8007302: e841 2300 strex r3, r2, [r1] + 8007306: 67bb str r3, [r7, #120] @ 0x78 + return(result); + 8007308: 6fbb ldr r3, [r7, #120] @ 0x78 + 800730a: 2b00 cmp r3, #0 + 800730c: d1e2 bne.n 80072d4 + + /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) + and RX FIFO Threshold interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); + 800730e: 687b ldr r3, [r7, #4] + 8007310: 681b ldr r3, [r3, #0] + 8007312: 3308 adds r3, #8 + 8007314: 663b str r3, [r7, #96] @ 0x60 + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 8007316: 6e3b ldr r3, [r7, #96] @ 0x60 + 8007318: e853 3f00 ldrex r3, [r3] + 800731c: 65fb str r3, [r7, #92] @ 0x5c + return(result); + 800731e: 6dfb ldr r3, [r7, #92] @ 0x5c + 8007320: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 + 8007324: f023 0301 bic.w r3, r3, #1 + 8007328: f8c7 3098 str.w r3, [r7, #152] @ 0x98 + 800732c: 687b ldr r3, [r7, #4] + 800732e: 681b ldr r3, [r3, #0] + 8007330: 3308 adds r3, #8 + 8007332: f8d7 2098 ldr.w r2, [r7, #152] @ 0x98 + 8007336: 66fa str r2, [r7, #108] @ 0x6c + 8007338: 66bb str r3, [r7, #104] @ 0x68 + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 800733a: 6eb9 ldr r1, [r7, #104] @ 0x68 + 800733c: 6efa ldr r2, [r7, #108] @ 0x6c + 800733e: e841 2300 strex r3, r2, [r1] + 8007342: 667b str r3, [r7, #100] @ 0x64 + return(result); + 8007344: 6e7b ldr r3, [r7, #100] @ 0x64 + 8007346: 2b00 cmp r3, #0 + 8007348: d1e1 bne.n 800730e + + /* Rx process is completed, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + 800734a: 687b ldr r3, [r7, #4] + 800734c: 2220 movs r2, #32 + 800734e: f8c3 208c str.w r2, [r3, #140] @ 0x8c + + /* Clear RxISR function pointer */ + huart->RxISR = NULL; + 8007352: 687b ldr r3, [r7, #4] + 8007354: 2200 movs r2, #0 + 8007356: 675a str r2, [r3, #116] @ 0x74 + + /* Initialize type of RxEvent to Transfer Complete */ + huart->RxEventType = HAL_UART_RXEVENT_TC; + 8007358: 687b ldr r3, [r7, #4] + 800735a: 2200 movs r2, #0 + 800735c: 671a str r2, [r3, #112] @ 0x70 + + if (!(IS_LPUART_INSTANCE(huart->Instance))) + 800735e: 687b ldr r3, [r7, #4] + 8007360: 681b ldr r3, [r3, #0] + 8007362: 4a60 ldr r2, [pc, #384] @ (80074e4 ) + 8007364: 4293 cmp r3, r2 + 8007366: d021 beq.n 80073ac + { + /* Check that USART RTOEN bit is set */ + if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) + 8007368: 687b ldr r3, [r7, #4] + 800736a: 681b ldr r3, [r3, #0] + 800736c: 685b ldr r3, [r3, #4] + 800736e: f403 0300 and.w r3, r3, #8388608 @ 0x800000 + 8007372: 2b00 cmp r3, #0 + 8007374: d01a beq.n 80073ac + { + /* Enable the UART Receiver Timeout Interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); + 8007376: 687b ldr r3, [r7, #4] + 8007378: 681b ldr r3, [r3, #0] + 800737a: 64fb str r3, [r7, #76] @ 0x4c + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 800737c: 6cfb ldr r3, [r7, #76] @ 0x4c + 800737e: e853 3f00 ldrex r3, [r3] + 8007382: 64bb str r3, [r7, #72] @ 0x48 + return(result); + 8007384: 6cbb ldr r3, [r7, #72] @ 0x48 + 8007386: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000 + 800738a: f8c7 3094 str.w r3, [r7, #148] @ 0x94 + 800738e: 687b ldr r3, [r7, #4] + 8007390: 681b ldr r3, [r3, #0] + 8007392: 461a mov r2, r3 + 8007394: f8d7 3094 ldr.w r3, [r7, #148] @ 0x94 + 8007398: 65bb str r3, [r7, #88] @ 0x58 + 800739a: 657a str r2, [r7, #84] @ 0x54 + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 800739c: 6d79 ldr r1, [r7, #84] @ 0x54 + 800739e: 6dba ldr r2, [r7, #88] @ 0x58 + 80073a0: e841 2300 strex r3, r2, [r1] + 80073a4: 653b str r3, [r7, #80] @ 0x50 + return(result); + 80073a6: 6d3b ldr r3, [r7, #80] @ 0x50 + 80073a8: 2b00 cmp r3, #0 + 80073aa: d1e4 bne.n 8007376 + } + } + + /* Check current reception Mode : + If Reception till IDLE event has been selected : */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + 80073ac: 687b ldr r3, [r7, #4] + 80073ae: 6edb ldr r3, [r3, #108] @ 0x6c + 80073b0: 2b01 cmp r3, #1 + 80073b2: d130 bne.n 8007416 + { + /* Set reception type to Standard */ + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + 80073b4: 687b ldr r3, [r7, #4] + 80073b6: 2200 movs r2, #0 + 80073b8: 66da str r2, [r3, #108] @ 0x6c + + /* Disable IDLE interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + 80073ba: 687b ldr r3, [r7, #4] + 80073bc: 681b ldr r3, [r3, #0] + 80073be: 63bb str r3, [r7, #56] @ 0x38 + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 80073c0: 6bbb ldr r3, [r7, #56] @ 0x38 + 80073c2: e853 3f00 ldrex r3, [r3] + 80073c6: 637b str r3, [r7, #52] @ 0x34 + return(result); + 80073c8: 6b7b ldr r3, [r7, #52] @ 0x34 + 80073ca: f023 0310 bic.w r3, r3, #16 + 80073ce: f8c7 3090 str.w r3, [r7, #144] @ 0x90 + 80073d2: 687b ldr r3, [r7, #4] + 80073d4: 681b ldr r3, [r3, #0] + 80073d6: 461a mov r2, r3 + 80073d8: f8d7 3090 ldr.w r3, [r7, #144] @ 0x90 + 80073dc: 647b str r3, [r7, #68] @ 0x44 + 80073de: 643a str r2, [r7, #64] @ 0x40 + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 80073e0: 6c39 ldr r1, [r7, #64] @ 0x40 + 80073e2: 6c7a ldr r2, [r7, #68] @ 0x44 + 80073e4: e841 2300 strex r3, r2, [r1] + 80073e8: 63fb str r3, [r7, #60] @ 0x3c + return(result); + 80073ea: 6bfb ldr r3, [r7, #60] @ 0x3c + 80073ec: 2b00 cmp r3, #0 + 80073ee: d1e4 bne.n 80073ba + + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) + 80073f0: 687b ldr r3, [r7, #4] + 80073f2: 681b ldr r3, [r3, #0] + 80073f4: 69db ldr r3, [r3, #28] + 80073f6: f003 0310 and.w r3, r3, #16 + 80073fa: 2b10 cmp r3, #16 + 80073fc: d103 bne.n 8007406 + { + /* Clear IDLE Flag */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + 80073fe: 687b ldr r3, [r7, #4] + 8007400: 681b ldr r3, [r3, #0] + 8007402: 2210 movs r2, #16 + 8007404: 621a str r2, [r3, #32] +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, huart->RxXferSize); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); + 8007406: 687b ldr r3, [r7, #4] + 8007408: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c + 800740c: 4619 mov r1, r3 + 800740e: 6878 ldr r0, [r7, #4] + 8007410: f7fe fc86 bl 8005d20 +#else + /*Call legacy weak Rx complete callback*/ + HAL_UART_RxCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + break; + 8007414: e00e b.n 8007434 + HAL_UART_RxCpltCallback(huart); + 8007416: 6878 ldr r0, [r7, #4] + 8007418: f7fa f934 bl 8001684 + break; + 800741c: e00a b.n 8007434 + while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U)) + 800741e: f8b7 30a6 ldrh.w r3, [r7, #166] @ 0xa6 + 8007422: 2b00 cmp r3, #0 + 8007424: d006 beq.n 8007434 + 8007426: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4 + 800742a: f003 0320 and.w r3, r3, #32 + 800742e: 2b00 cmp r3, #0 + 8007430: f47f aeca bne.w 80071c8 + + /* When remaining number of bytes to receive is less than the RX FIFO + threshold, next incoming frames are processed as if FIFO mode was + disabled (i.e. one interrupt per received frame). + */ + rxdatacount = huart->RxXferCount; + 8007434: 687b ldr r3, [r7, #4] + 8007436: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e + 800743a: f8a7 308e strh.w r3, [r7, #142] @ 0x8e + if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess)) + 800743e: f8b7 308e ldrh.w r3, [r7, #142] @ 0x8e + 8007442: 2b00 cmp r3, #0 + 8007444: d049 beq.n 80074da + 8007446: 687b ldr r3, [r7, #4] + 8007448: f8b3 3068 ldrh.w r3, [r3, #104] @ 0x68 + 800744c: f8b7 208e ldrh.w r2, [r7, #142] @ 0x8e + 8007450: 429a cmp r2, r3 + 8007452: d242 bcs.n 80074da + { + /* Disable the UART RXFT interrupt*/ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); + 8007454: 687b ldr r3, [r7, #4] + 8007456: 681b ldr r3, [r3, #0] + 8007458: 3308 adds r3, #8 + 800745a: 627b str r3, [r7, #36] @ 0x24 + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 800745c: 6a7b ldr r3, [r7, #36] @ 0x24 + 800745e: e853 3f00 ldrex r3, [r3] + 8007462: 623b str r3, [r7, #32] + return(result); + 8007464: 6a3b ldr r3, [r7, #32] + 8007466: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 + 800746a: f8c7 3088 str.w r3, [r7, #136] @ 0x88 + 800746e: 687b ldr r3, [r7, #4] + 8007470: 681b ldr r3, [r3, #0] + 8007472: 3308 adds r3, #8 + 8007474: f8d7 2088 ldr.w r2, [r7, #136] @ 0x88 + 8007478: 633a str r2, [r7, #48] @ 0x30 + 800747a: 62fb str r3, [r7, #44] @ 0x2c + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 800747c: 6af9 ldr r1, [r7, #44] @ 0x2c + 800747e: 6b3a ldr r2, [r7, #48] @ 0x30 + 8007480: e841 2300 strex r3, r2, [r1] + 8007484: 62bb str r3, [r7, #40] @ 0x28 + return(result); + 8007486: 6abb ldr r3, [r7, #40] @ 0x28 + 8007488: 2b00 cmp r3, #0 + 800748a: d1e3 bne.n 8007454 + + /* Update the RxISR function pointer */ + huart->RxISR = UART_RxISR_16BIT; + 800748c: 687b ldr r3, [r7, #4] + 800748e: 4a16 ldr r2, [pc, #88] @ (80074e8 ) + 8007490: 675a str r2, [r3, #116] @ 0x74 + + /* Enable the UART Data Register Not Empty interrupt */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); + 8007492: 687b ldr r3, [r7, #4] + 8007494: 681b ldr r3, [r3, #0] + 8007496: 613b str r3, [r7, #16] + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 8007498: 693b ldr r3, [r7, #16] + 800749a: e853 3f00 ldrex r3, [r3] + 800749e: 60fb str r3, [r7, #12] + return(result); + 80074a0: 68fb ldr r3, [r7, #12] + 80074a2: f043 0320 orr.w r3, r3, #32 + 80074a6: f8c7 3084 str.w r3, [r7, #132] @ 0x84 + 80074aa: 687b ldr r3, [r7, #4] + 80074ac: 681b ldr r3, [r3, #0] + 80074ae: 461a mov r2, r3 + 80074b0: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84 + 80074b4: 61fb str r3, [r7, #28] + 80074b6: 61ba str r2, [r7, #24] + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 80074b8: 69b9 ldr r1, [r7, #24] + 80074ba: 69fa ldr r2, [r7, #28] + 80074bc: e841 2300 strex r3, r2, [r1] + 80074c0: 617b str r3, [r7, #20] + return(result); + 80074c2: 697b ldr r3, [r7, #20] + 80074c4: 2b00 cmp r3, #0 + 80074c6: d1e4 bne.n 8007492 + else + { + /* Clear RXNE interrupt flag */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + } +} + 80074c8: e007 b.n 80074da + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + 80074ca: 687b ldr r3, [r7, #4] + 80074cc: 681b ldr r3, [r3, #0] + 80074ce: 699a ldr r2, [r3, #24] + 80074d0: 687b ldr r3, [r7, #4] + 80074d2: 681b ldr r3, [r3, #0] + 80074d4: f042 0208 orr.w r2, r2, #8 + 80074d8: 619a str r2, [r3, #24] +} + 80074da: bf00 nop + 80074dc: 37b8 adds r7, #184 @ 0xb8 + 80074de: 46bd mov sp, r7 + 80074e0: bd80 pop {r7, pc} + 80074e2: bf00 nop + 80074e4: 40008000 .word 0x40008000 + 80074e8: 08006c65 .word 0x08006c65 + +080074ec : + * @brief UART wakeup from Stop mode callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart) +{ + 80074ec: b480 push {r7} + 80074ee: b083 sub sp, #12 + 80074f0: af00 add r7, sp, #0 + 80074f2: 6078 str r0, [r7, #4] + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UARTEx_WakeupCallback can be implemented in the user file. + */ +} + 80074f4: bf00 nop + 80074f6: 370c adds r7, #12 + 80074f8: 46bd mov sp, r7 + 80074fa: bc80 pop {r7} + 80074fc: 4770 bx lr + +080074fe : + * @brief UART RX Fifo full callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UARTEx_RxFifoFullCallback(UART_HandleTypeDef *huart) +{ + 80074fe: b480 push {r7} + 8007500: b083 sub sp, #12 + 8007502: af00 add r7, sp, #0 + 8007504: 6078 str r0, [r7, #4] + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UARTEx_RxFifoFullCallback can be implemented in the user file. + */ +} + 8007506: bf00 nop + 8007508: 370c adds r7, #12 + 800750a: 46bd mov sp, r7 + 800750c: bc80 pop {r7} + 800750e: 4770 bx lr + +08007510 : + * @brief UART TX Fifo empty callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart) +{ + 8007510: b480 push {r7} + 8007512: b083 sub sp, #12 + 8007514: af00 add r7, sp, #0 + 8007516: 6078 str r0, [r7, #4] + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UARTEx_TxFifoEmptyCallback can be implemented in the user file. + */ +} + 8007518: bf00 nop + 800751a: 370c adds r7, #12 + 800751c: 46bd mov sp, r7 + 800751e: bc80 pop {r7} + 8007520: 4770 bx lr + +08007522 : + * @arg @ref UART_WAKEUP_ON_STARTBIT + * @arg @ref UART_WAKEUP_ON_READDATA_NONEMPTY + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection) +{ + 8007522: b580 push {r7, lr} + 8007524: b088 sub sp, #32 + 8007526: af02 add r7, sp, #8 + 8007528: 60f8 str r0, [r7, #12] + 800752a: 1d3b adds r3, r7, #4 + 800752c: e883 0006 stmia.w r3, {r1, r2} + HAL_StatusTypeDef status = HAL_OK; + 8007530: 2300 movs r3, #0 + 8007532: 75fb strb r3, [r7, #23] + assert_param(IS_UART_WAKEUP_FROMSTOP_INSTANCE(huart->Instance)); + /* check the wake-up selection parameter */ + assert_param(IS_UART_WAKEUP_SELECTION(WakeUpSelection.WakeUpEvent)); + + /* Process Locked */ + __HAL_LOCK(huart); + 8007534: 68fb ldr r3, [r7, #12] + 8007536: f893 3084 ldrb.w r3, [r3, #132] @ 0x84 + 800753a: 2b01 cmp r3, #1 + 800753c: d101 bne.n 8007542 + 800753e: 2302 movs r3, #2 + 8007540: e046 b.n 80075d0 + 8007542: 68fb ldr r3, [r7, #12] + 8007544: 2201 movs r2, #1 + 8007546: f883 2084 strb.w r2, [r3, #132] @ 0x84 + + huart->gState = HAL_UART_STATE_BUSY; + 800754a: 68fb ldr r3, [r7, #12] + 800754c: 2224 movs r2, #36 @ 0x24 + 800754e: f8c3 2088 str.w r2, [r3, #136] @ 0x88 + + /* Disable the Peripheral */ + __HAL_UART_DISABLE(huart); + 8007552: 68fb ldr r3, [r7, #12] + 8007554: 681b ldr r3, [r3, #0] + 8007556: 681a ldr r2, [r3, #0] + 8007558: 68fb ldr r3, [r7, #12] + 800755a: 681b ldr r3, [r3, #0] + 800755c: f022 0201 bic.w r2, r2, #1 + 8007560: 601a str r2, [r3, #0] + + /* Set the wake-up selection scheme */ + MODIFY_REG(huart->Instance->CR3, USART_CR3_WUS, WakeUpSelection.WakeUpEvent); + 8007562: 68fb ldr r3, [r7, #12] + 8007564: 681b ldr r3, [r3, #0] + 8007566: 689b ldr r3, [r3, #8] + 8007568: f423 1140 bic.w r1, r3, #3145728 @ 0x300000 + 800756c: 687a ldr r2, [r7, #4] + 800756e: 68fb ldr r3, [r7, #12] + 8007570: 681b ldr r3, [r3, #0] + 8007572: 430a orrs r2, r1 + 8007574: 609a str r2, [r3, #8] + + if (WakeUpSelection.WakeUpEvent == UART_WAKEUP_ON_ADDRESS) + 8007576: 687b ldr r3, [r7, #4] + 8007578: 2b00 cmp r3, #0 + 800757a: d105 bne.n 8007588 + { + UARTEx_Wakeup_AddressConfig(huart, WakeUpSelection); + 800757c: 1d3b adds r3, r7, #4 + 800757e: e893 0006 ldmia.w r3, {r1, r2} + 8007582: 68f8 ldr r0, [r7, #12] + 8007584: f000 f911 bl 80077aa + } + + /* Enable the Peripheral */ + __HAL_UART_ENABLE(huart); + 8007588: 68fb ldr r3, [r7, #12] + 800758a: 681b ldr r3, [r3, #0] + 800758c: 681a ldr r2, [r3, #0] + 800758e: 68fb ldr r3, [r7, #12] + 8007590: 681b ldr r3, [r3, #0] + 8007592: f042 0201 orr.w r2, r2, #1 + 8007596: 601a str r2, [r3, #0] + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + 8007598: f7f9 fb56 bl 8000c48 + 800759c: 6138 str r0, [r7, #16] + + /* Wait until REACK flag is set */ + if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) + 800759e: f06f 437e mvn.w r3, #4261412864 @ 0xfe000000 + 80075a2: 9300 str r3, [sp, #0] + 80075a4: 693b ldr r3, [r7, #16] + 80075a6: 2200 movs r2, #0 + 80075a8: f44f 0180 mov.w r1, #4194304 @ 0x400000 + 80075ac: 68f8 ldr r0, [r7, #12] + 80075ae: f7fe ff82 bl 80064b6 + 80075b2: 4603 mov r3, r0 + 80075b4: 2b00 cmp r3, #0 + 80075b6: d002 beq.n 80075be + { + status = HAL_TIMEOUT; + 80075b8: 2303 movs r3, #3 + 80075ba: 75fb strb r3, [r7, #23] + 80075bc: e003 b.n 80075c6 + } + else + { + /* Initialize the UART State */ + huart->gState = HAL_UART_STATE_READY; + 80075be: 68fb ldr r3, [r7, #12] + 80075c0: 2220 movs r2, #32 + 80075c2: f8c3 2088 str.w r2, [r3, #136] @ 0x88 + } + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + 80075c6: 68fb ldr r3, [r7, #12] + 80075c8: 2200 movs r2, #0 + 80075ca: f883 2084 strb.w r2, [r3, #132] @ 0x84 + + return status; + 80075ce: 7dfb ldrb r3, [r7, #23] +} + 80075d0: 4618 mov r0, r3 + 80075d2: 3718 adds r7, #24 + 80075d4: 46bd mov sp, r7 + 80075d6: bd80 pop {r7, pc} + +080075d8 : + * @note The UART is able to wake up the MCU from Stop 1 mode as long as UART clock is HSI or LSE. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart) +{ + 80075d8: b480 push {r7} + 80075da: b089 sub sp, #36 @ 0x24 + 80075dc: af00 add r7, sp, #0 + 80075de: 6078 str r0, [r7, #4] + /* Process Locked */ + __HAL_LOCK(huart); + 80075e0: 687b ldr r3, [r7, #4] + 80075e2: f893 3084 ldrb.w r3, [r3, #132] @ 0x84 + 80075e6: 2b01 cmp r3, #1 + 80075e8: d101 bne.n 80075ee + 80075ea: 2302 movs r3, #2 + 80075ec: e021 b.n 8007632 + 80075ee: 687b ldr r3, [r7, #4] + 80075f0: 2201 movs r2, #1 + 80075f2: f883 2084 strb.w r2, [r3, #132] @ 0x84 + + /* Set UESM bit */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_UESM); + 80075f6: 687b ldr r3, [r7, #4] + 80075f8: 681b ldr r3, [r3, #0] + 80075fa: 60fb str r3, [r7, #12] + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 80075fc: 68fb ldr r3, [r7, #12] + 80075fe: e853 3f00 ldrex r3, [r3] + 8007602: 60bb str r3, [r7, #8] + return(result); + 8007604: 68bb ldr r3, [r7, #8] + 8007606: f043 0302 orr.w r3, r3, #2 + 800760a: 61fb str r3, [r7, #28] + 800760c: 687b ldr r3, [r7, #4] + 800760e: 681b ldr r3, [r3, #0] + 8007610: 461a mov r2, r3 + 8007612: 69fb ldr r3, [r7, #28] + 8007614: 61bb str r3, [r7, #24] + 8007616: 617a str r2, [r7, #20] + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 8007618: 6979 ldr r1, [r7, #20] + 800761a: 69ba ldr r2, [r7, #24] + 800761c: e841 2300 strex r3, r2, [r1] + 8007620: 613b str r3, [r7, #16] + return(result); + 8007622: 693b ldr r3, [r7, #16] + 8007624: 2b00 cmp r3, #0 + 8007626: d1e6 bne.n 80075f6 + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + 8007628: 687b ldr r3, [r7, #4] + 800762a: 2200 movs r2, #0 + 800762c: f883 2084 strb.w r2, [r3, #132] @ 0x84 + + return HAL_OK; + 8007630: 2300 movs r3, #0 +} + 8007632: 4618 mov r0, r3 + 8007634: 3724 adds r7, #36 @ 0x24 + 8007636: 46bd mov sp, r7 + 8007638: bc80 pop {r7} + 800763a: 4770 bx lr + +0800763c : + * @brief Enable the FIFO mode. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_EnableFifoMode(UART_HandleTypeDef *huart) +{ + 800763c: b580 push {r7, lr} + 800763e: b084 sub sp, #16 + 8007640: af00 add r7, sp, #0 + 8007642: 6078 str r0, [r7, #4] + + /* Check parameters */ + assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); + + /* Process Locked */ + __HAL_LOCK(huart); + 8007644: 687b ldr r3, [r7, #4] + 8007646: f893 3084 ldrb.w r3, [r3, #132] @ 0x84 + 800764a: 2b01 cmp r3, #1 + 800764c: d101 bne.n 8007652 + 800764e: 2302 movs r3, #2 + 8007650: e02b b.n 80076aa + 8007652: 687b ldr r3, [r7, #4] + 8007654: 2201 movs r2, #1 + 8007656: f883 2084 strb.w r2, [r3, #132] @ 0x84 + + huart->gState = HAL_UART_STATE_BUSY; + 800765a: 687b ldr r3, [r7, #4] + 800765c: 2224 movs r2, #36 @ 0x24 + 800765e: f8c3 2088 str.w r2, [r3, #136] @ 0x88 + + /* Save actual UART configuration */ + tmpcr1 = READ_REG(huart->Instance->CR1); + 8007662: 687b ldr r3, [r7, #4] + 8007664: 681b ldr r3, [r3, #0] + 8007666: 681b ldr r3, [r3, #0] + 8007668: 60fb str r3, [r7, #12] + + /* Disable UART */ + __HAL_UART_DISABLE(huart); + 800766a: 687b ldr r3, [r7, #4] + 800766c: 681b ldr r3, [r3, #0] + 800766e: 681a ldr r2, [r3, #0] + 8007670: 687b ldr r3, [r7, #4] + 8007672: 681b ldr r3, [r3, #0] + 8007674: f022 0201 bic.w r2, r2, #1 + 8007678: 601a str r2, [r3, #0] + + /* Enable FIFO mode */ + SET_BIT(tmpcr1, USART_CR1_FIFOEN); + 800767a: 68fb ldr r3, [r7, #12] + 800767c: f043 5300 orr.w r3, r3, #536870912 @ 0x20000000 + 8007680: 60fb str r3, [r7, #12] + huart->FifoMode = UART_FIFOMODE_ENABLE; + 8007682: 687b ldr r3, [r7, #4] + 8007684: f04f 5200 mov.w r2, #536870912 @ 0x20000000 + 8007688: 665a str r2, [r3, #100] @ 0x64 + + /* Restore UART configuration */ + WRITE_REG(huart->Instance->CR1, tmpcr1); + 800768a: 687b ldr r3, [r7, #4] + 800768c: 681b ldr r3, [r3, #0] + 800768e: 68fa ldr r2, [r7, #12] + 8007690: 601a str r2, [r3, #0] + + /* Determine the number of data to process during RX/TX ISR execution */ + UARTEx_SetNbDataToProcess(huart); + 8007692: 6878 ldr r0, [r7, #4] + 8007694: f000 f8ac bl 80077f0 + + huart->gState = HAL_UART_STATE_READY; + 8007698: 687b ldr r3, [r7, #4] + 800769a: 2220 movs r2, #32 + 800769c: f8c3 2088 str.w r2, [r3, #136] @ 0x88 + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + 80076a0: 687b ldr r3, [r7, #4] + 80076a2: 2200 movs r2, #0 + 80076a4: f883 2084 strb.w r2, [r3, #132] @ 0x84 + + return HAL_OK; + 80076a8: 2300 movs r3, #0 +} + 80076aa: 4618 mov r0, r3 + 80076ac: 3710 adds r7, #16 + 80076ae: 46bd mov sp, r7 + 80076b0: bd80 pop {r7, pc} + +080076b2 : + * @arg @ref UART_TXFIFO_THRESHOLD_7_8 + * @arg @ref UART_TXFIFO_THRESHOLD_8_8 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold) +{ + 80076b2: b580 push {r7, lr} + 80076b4: b084 sub sp, #16 + 80076b6: af00 add r7, sp, #0 + 80076b8: 6078 str r0, [r7, #4] + 80076ba: 6039 str r1, [r7, #0] + /* Check parameters */ + assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); + assert_param(IS_UART_TXFIFO_THRESHOLD(Threshold)); + + /* Process Locked */ + __HAL_LOCK(huart); + 80076bc: 687b ldr r3, [r7, #4] + 80076be: f893 3084 ldrb.w r3, [r3, #132] @ 0x84 + 80076c2: 2b01 cmp r3, #1 + 80076c4: d101 bne.n 80076ca + 80076c6: 2302 movs r3, #2 + 80076c8: e02d b.n 8007726 + 80076ca: 687b ldr r3, [r7, #4] + 80076cc: 2201 movs r2, #1 + 80076ce: f883 2084 strb.w r2, [r3, #132] @ 0x84 + + huart->gState = HAL_UART_STATE_BUSY; + 80076d2: 687b ldr r3, [r7, #4] + 80076d4: 2224 movs r2, #36 @ 0x24 + 80076d6: f8c3 2088 str.w r2, [r3, #136] @ 0x88 + + /* Save actual UART configuration */ + tmpcr1 = READ_REG(huart->Instance->CR1); + 80076da: 687b ldr r3, [r7, #4] + 80076dc: 681b ldr r3, [r3, #0] + 80076de: 681b ldr r3, [r3, #0] + 80076e0: 60fb str r3, [r7, #12] + + /* Disable UART */ + __HAL_UART_DISABLE(huart); + 80076e2: 687b ldr r3, [r7, #4] + 80076e4: 681b ldr r3, [r3, #0] + 80076e6: 681a ldr r2, [r3, #0] + 80076e8: 687b ldr r3, [r7, #4] + 80076ea: 681b ldr r3, [r3, #0] + 80076ec: f022 0201 bic.w r2, r2, #1 + 80076f0: 601a str r2, [r3, #0] + + /* Update TX threshold configuration */ + MODIFY_REG(huart->Instance->CR3, USART_CR3_TXFTCFG, Threshold); + 80076f2: 687b ldr r3, [r7, #4] + 80076f4: 681b ldr r3, [r3, #0] + 80076f6: 689b ldr r3, [r3, #8] + 80076f8: f023 4160 bic.w r1, r3, #3758096384 @ 0xe0000000 + 80076fc: 687b ldr r3, [r7, #4] + 80076fe: 681b ldr r3, [r3, #0] + 8007700: 683a ldr r2, [r7, #0] + 8007702: 430a orrs r2, r1 + 8007704: 609a str r2, [r3, #8] + + /* Determine the number of data to process during RX/TX ISR execution */ + UARTEx_SetNbDataToProcess(huart); + 8007706: 6878 ldr r0, [r7, #4] + 8007708: f000 f872 bl 80077f0 + + /* Restore UART configuration */ + WRITE_REG(huart->Instance->CR1, tmpcr1); + 800770c: 687b ldr r3, [r7, #4] + 800770e: 681b ldr r3, [r3, #0] + 8007710: 68fa ldr r2, [r7, #12] + 8007712: 601a str r2, [r3, #0] + + huart->gState = HAL_UART_STATE_READY; + 8007714: 687b ldr r3, [r7, #4] + 8007716: 2220 movs r2, #32 + 8007718: f8c3 2088 str.w r2, [r3, #136] @ 0x88 + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + 800771c: 687b ldr r3, [r7, #4] + 800771e: 2200 movs r2, #0 + 8007720: f883 2084 strb.w r2, [r3, #132] @ 0x84 + + return HAL_OK; + 8007724: 2300 movs r3, #0 +} + 8007726: 4618 mov r0, r3 + 8007728: 3710 adds r7, #16 + 800772a: 46bd mov sp, r7 + 800772c: bd80 pop {r7, pc} + +0800772e : + * @arg @ref UART_RXFIFO_THRESHOLD_7_8 + * @arg @ref UART_RXFIFO_THRESHOLD_8_8 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold) +{ + 800772e: b580 push {r7, lr} + 8007730: b084 sub sp, #16 + 8007732: af00 add r7, sp, #0 + 8007734: 6078 str r0, [r7, #4] + 8007736: 6039 str r1, [r7, #0] + /* Check the parameters */ + assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); + assert_param(IS_UART_RXFIFO_THRESHOLD(Threshold)); + + /* Process Locked */ + __HAL_LOCK(huart); + 8007738: 687b ldr r3, [r7, #4] + 800773a: f893 3084 ldrb.w r3, [r3, #132] @ 0x84 + 800773e: 2b01 cmp r3, #1 + 8007740: d101 bne.n 8007746 + 8007742: 2302 movs r3, #2 + 8007744: e02d b.n 80077a2 + 8007746: 687b ldr r3, [r7, #4] + 8007748: 2201 movs r2, #1 + 800774a: f883 2084 strb.w r2, [r3, #132] @ 0x84 + + huart->gState = HAL_UART_STATE_BUSY; + 800774e: 687b ldr r3, [r7, #4] + 8007750: 2224 movs r2, #36 @ 0x24 + 8007752: f8c3 2088 str.w r2, [r3, #136] @ 0x88 + + /* Save actual UART configuration */ + tmpcr1 = READ_REG(huart->Instance->CR1); + 8007756: 687b ldr r3, [r7, #4] + 8007758: 681b ldr r3, [r3, #0] + 800775a: 681b ldr r3, [r3, #0] + 800775c: 60fb str r3, [r7, #12] + + /* Disable UART */ + __HAL_UART_DISABLE(huart); + 800775e: 687b ldr r3, [r7, #4] + 8007760: 681b ldr r3, [r3, #0] + 8007762: 681a ldr r2, [r3, #0] + 8007764: 687b ldr r3, [r7, #4] + 8007766: 681b ldr r3, [r3, #0] + 8007768: f022 0201 bic.w r2, r2, #1 + 800776c: 601a str r2, [r3, #0] + + /* Update RX threshold configuration */ + MODIFY_REG(huart->Instance->CR3, USART_CR3_RXFTCFG, Threshold); + 800776e: 687b ldr r3, [r7, #4] + 8007770: 681b ldr r3, [r3, #0] + 8007772: 689b ldr r3, [r3, #8] + 8007774: f023 6160 bic.w r1, r3, #234881024 @ 0xe000000 + 8007778: 687b ldr r3, [r7, #4] + 800777a: 681b ldr r3, [r3, #0] + 800777c: 683a ldr r2, [r7, #0] + 800777e: 430a orrs r2, r1 + 8007780: 609a str r2, [r3, #8] + + /* Determine the number of data to process during RX/TX ISR execution */ + UARTEx_SetNbDataToProcess(huart); + 8007782: 6878 ldr r0, [r7, #4] + 8007784: f000 f834 bl 80077f0 + + /* Restore UART configuration */ + WRITE_REG(huart->Instance->CR1, tmpcr1); + 8007788: 687b ldr r3, [r7, #4] + 800778a: 681b ldr r3, [r3, #0] + 800778c: 68fa ldr r2, [r7, #12] + 800778e: 601a str r2, [r3, #0] + + huart->gState = HAL_UART_STATE_READY; + 8007790: 687b ldr r3, [r7, #4] + 8007792: 2220 movs r2, #32 + 8007794: f8c3 2088 str.w r2, [r3, #136] @ 0x88 + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + 8007798: 687b ldr r3, [r7, #4] + 800779a: 2200 movs r2, #0 + 800779c: f883 2084 strb.w r2, [r3, #132] @ 0x84 + + return HAL_OK; + 80077a0: 2300 movs r3, #0 +} + 80077a2: 4618 mov r0, r3 + 80077a4: 3710 adds r7, #16 + 80077a6: 46bd mov sp, r7 + 80077a8: bd80 pop {r7, pc} + +080077aa : + * @param huart UART handle. + * @param WakeUpSelection UART wake up from stop mode parameters. + * @retval None + */ +static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection) +{ + 80077aa: b480 push {r7} + 80077ac: b085 sub sp, #20 + 80077ae: af00 add r7, sp, #0 + 80077b0: 60f8 str r0, [r7, #12] + 80077b2: 1d3b adds r3, r7, #4 + 80077b4: e883 0006 stmia.w r3, {r1, r2} + assert_param(IS_UART_ADDRESSLENGTH_DETECT(WakeUpSelection.AddressLength)); + + /* Set the USART address length */ + MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, WakeUpSelection.AddressLength); + 80077b8: 68fb ldr r3, [r7, #12] + 80077ba: 681b ldr r3, [r3, #0] + 80077bc: 685b ldr r3, [r3, #4] + 80077be: f023 0210 bic.w r2, r3, #16 + 80077c2: 893b ldrh r3, [r7, #8] + 80077c4: 4619 mov r1, r3 + 80077c6: 68fb ldr r3, [r7, #12] + 80077c8: 681b ldr r3, [r3, #0] + 80077ca: 430a orrs r2, r1 + 80077cc: 605a str r2, [r3, #4] + + /* Set the USART address node */ + MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)WakeUpSelection.Address << UART_CR2_ADDRESS_LSB_POS)); + 80077ce: 68fb ldr r3, [r7, #12] + 80077d0: 681b ldr r3, [r3, #0] + 80077d2: 685b ldr r3, [r3, #4] + 80077d4: f023 417f bic.w r1, r3, #4278190080 @ 0xff000000 + 80077d8: 7abb ldrb r3, [r7, #10] + 80077da: 061a lsls r2, r3, #24 + 80077dc: 68fb ldr r3, [r7, #12] + 80077de: 681b ldr r3, [r3, #0] + 80077e0: 430a orrs r2, r1 + 80077e2: 605a str r2, [r3, #4] +} + 80077e4: bf00 nop + 80077e6: 3714 adds r7, #20 + 80077e8: 46bd mov sp, r7 + 80077ea: bc80 pop {r7} + 80077ec: 4770 bx lr + ... + +080077f0 : + * the UART configuration registers. + * @param huart UART handle. + * @retval None + */ +static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart) +{ + 80077f0: b480 push {r7} + 80077f2: b085 sub sp, #20 + 80077f4: af00 add r7, sp, #0 + 80077f6: 6078 str r0, [r7, #4] + uint8_t rx_fifo_threshold; + uint8_t tx_fifo_threshold; + static const uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U}; + static const uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U}; + + if (huart->FifoMode == UART_FIFOMODE_DISABLE) + 80077f8: 687b ldr r3, [r7, #4] + 80077fa: 6e5b ldr r3, [r3, #100] @ 0x64 + 80077fc: 2b00 cmp r3, #0 + 80077fe: d108 bne.n 8007812 + { + huart->NbTxDataToProcess = 1U; + 8007800: 687b ldr r3, [r7, #4] + 8007802: 2201 movs r2, #1 + 8007804: f8a3 206a strh.w r2, [r3, #106] @ 0x6a + huart->NbRxDataToProcess = 1U; + 8007808: 687b ldr r3, [r7, #4] + 800780a: 2201 movs r2, #1 + 800780c: f8a3 2068 strh.w r2, [r3, #104] @ 0x68 + huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / + (uint16_t)denominator[tx_fifo_threshold]; + huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / + (uint16_t)denominator[rx_fifo_threshold]; + } +} + 8007810: e031 b.n 8007876 + rx_fifo_depth = RX_FIFO_DEPTH; + 8007812: 2308 movs r3, #8 + 8007814: 73fb strb r3, [r7, #15] + tx_fifo_depth = TX_FIFO_DEPTH; + 8007816: 2308 movs r3, #8 + 8007818: 73bb strb r3, [r7, #14] + rx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos); + 800781a: 687b ldr r3, [r7, #4] + 800781c: 681b ldr r3, [r3, #0] + 800781e: 689b ldr r3, [r3, #8] + 8007820: 0e5b lsrs r3, r3, #25 + 8007822: b2db uxtb r3, r3 + 8007824: f003 0307 and.w r3, r3, #7 + 8007828: 737b strb r3, [r7, #13] + tx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos); + 800782a: 687b ldr r3, [r7, #4] + 800782c: 681b ldr r3, [r3, #0] + 800782e: 689b ldr r3, [r3, #8] + 8007830: 0f5b lsrs r3, r3, #29 + 8007832: b2db uxtb r3, r3 + 8007834: f003 0307 and.w r3, r3, #7 + 8007838: 733b strb r3, [r7, #12] + huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / + 800783a: 7bbb ldrb r3, [r7, #14] + 800783c: 7b3a ldrb r2, [r7, #12] + 800783e: 4910 ldr r1, [pc, #64] @ (8007880 ) + 8007840: 5c8a ldrb r2, [r1, r2] + 8007842: fb02 f303 mul.w r3, r2, r3 + (uint16_t)denominator[tx_fifo_threshold]; + 8007846: 7b3a ldrb r2, [r7, #12] + 8007848: 490e ldr r1, [pc, #56] @ (8007884 ) + 800784a: 5c8a ldrb r2, [r1, r2] + huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / + 800784c: fb93 f3f2 sdiv r3, r3, r2 + 8007850: b29a uxth r2, r3 + 8007852: 687b ldr r3, [r7, #4] + 8007854: f8a3 206a strh.w r2, [r3, #106] @ 0x6a + huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / + 8007858: 7bfb ldrb r3, [r7, #15] + 800785a: 7b7a ldrb r2, [r7, #13] + 800785c: 4908 ldr r1, [pc, #32] @ (8007880 ) + 800785e: 5c8a ldrb r2, [r1, r2] + 8007860: fb02 f303 mul.w r3, r2, r3 + (uint16_t)denominator[rx_fifo_threshold]; + 8007864: 7b7a ldrb r2, [r7, #13] + 8007866: 4907 ldr r1, [pc, #28] @ (8007884 ) + 8007868: 5c8a ldrb r2, [r1, r2] + huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / + 800786a: fb93 f3f2 sdiv r3, r3, r2 + 800786e: b29a uxth r2, r3 + 8007870: 687b ldr r3, [r7, #4] + 8007872: f8a3 2068 strh.w r2, [r3, #104] @ 0x68 +} + 8007876: bf00 nop + 8007878: 3714 adds r7, #20 + 800787a: 46bd mov sp, r7 + 800787c: bc80 pop {r7} + 800787e: 4770 bx lr + 8007880: 0800fb6c .word 0x0800fb6c + 8007884: 0800fb74 .word 0x0800fb74 + +08007888 : + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + 8007888: b480 push {r7} + 800788a: b083 sub sp, #12 + 800788c: af00 add r7, sp, #0 + 800788e: 6078 str r0, [r7, #4] + 8007890: 6039 str r1, [r7, #0] + WRITE_REG(GPIOx->BSRR, PinMask); + 8007892: 687b ldr r3, [r7, #4] + 8007894: 683a ldr r2, [r7, #0] + 8007896: 619a str r2, [r3, #24] +} + 8007898: bf00 nop + 800789a: 370c adds r7, #12 + 800789c: 46bd mov sp, r7 + 800789e: bc80 pop {r7} + 80078a0: 4770 bx lr + +080078a2 : + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void LL_GPIO_ResetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + 80078a2: b480 push {r7} + 80078a4: b083 sub sp, #12 + 80078a6: af00 add r7, sp, #0 + 80078a8: 6078 str r0, [r7, #4] + 80078aa: 6039 str r1, [r7, #0] + WRITE_REG(GPIOx->BRR, PinMask); + 80078ac: 687b ldr r3, [r7, #4] + 80078ae: 683a ldr r2, [r7, #0] + 80078b0: 629a str r2, [r3, #40] @ 0x28 +} + 80078b2: bf00 nop + 80078b4: 370c adds r7, #12 + 80078b6: 46bd mov sp, r7 + 80078b8: bc80 pop {r7} + 80078ba: 4770 bx lr + +080078bc : +TimerEvent_t RxTimeoutTimer; + +/* Private functions ---------------------------------------------------------*/ + +static void RadioInit( RadioEvents_t *events ) +{ + 80078bc: b580 push {r7, lr} + 80078be: b084 sub sp, #16 + 80078c0: af02 add r7, sp, #8 + 80078c2: 6078 str r0, [r7, #4] + RadioEvents = events; + 80078c4: 4a24 ldr r2, [pc, #144] @ (8007958 ) + 80078c6: 687b ldr r3, [r7, #4] + 80078c8: 6013 str r3, [r2, #0] + + SubgRf.RxContinuous = false; + 80078ca: 4b24 ldr r3, [pc, #144] @ (800795c ) + 80078cc: 2200 movs r2, #0 + 80078ce: 705a strb r2, [r3, #1] + SubgRf.TxTimeout = 0; + 80078d0: 4b22 ldr r3, [pc, #136] @ (800795c ) + 80078d2: 2200 movs r2, #0 + 80078d4: 605a str r2, [r3, #4] + SubgRf.RxTimeout = 0; + 80078d6: 4b21 ldr r3, [pc, #132] @ (800795c ) + 80078d8: 2200 movs r2, #0 + 80078da: 609a str r2, [r3, #8] + /*See STM32WL Errata: RadioSetRxDutyCycle*/ + SubgRf.RxDcPreambleDetectTimeout = 0; + 80078dc: 4b1f ldr r3, [pc, #124] @ (800795c ) + 80078de: 2200 movs r2, #0 + 80078e0: 659a str r2, [r3, #88] @ 0x58 +#if( RADIO_LR_FHSS_IS_ON == 1 ) + SubgRf.lr_fhss.is_lr_fhss_on = false; +#endif /* RADIO_LR_FHSS_IS_ON == 1 */ + SUBGRF_Init( RadioOnDioIrq ); + 80078e2: 481f ldr r0, [pc, #124] @ (8007960 ) + 80078e4: f001 fffa bl 80098dc + /*SubgRf.publicNetwork set to false*/ + SubgRf.PublicNetwork.Current = false; + 80078e8: 4b1c ldr r3, [pc, #112] @ (800795c ) + 80078ea: 2200 movs r2, #0 + 80078ec: 735a strb r2, [r3, #13] + SubgRf.PublicNetwork.Previous = false; + 80078ee: 4b1b ldr r3, [pc, #108] @ (800795c ) + 80078f0: 2200 movs r2, #0 + 80078f2: 731a strb r2, [r3, #12] + + RADIO_IRQ_PROCESS_INIT(); + + SUBGRF_SetRegulatorMode( ); + 80078f4: f002 fa90 bl 8009e18 + + SUBGRF_SetBufferBaseAddress( 0x00, 0x00 ); + 80078f8: 2100 movs r1, #0 + 80078fa: 2000 movs r0, #0 + 80078fc: f002 fe5c bl 800a5b8 + SUBGRF_SetTxParams( RFO_LP, 0, RADIO_RAMP_200_US ); + 8007900: 2204 movs r2, #4 + 8007902: 2100 movs r1, #0 + 8007904: 2001 movs r0, #1 + 8007906: f002 fc1f bl 800a148 + SUBGRF_SetDioIrqParams( IRQ_RADIO_ALL, IRQ_RADIO_ALL, IRQ_RADIO_NONE, IRQ_RADIO_NONE ); + 800790a: 2300 movs r3, #0 + 800790c: 2200 movs r2, #0 + 800790e: f64f 71ff movw r1, #65535 @ 0xffff + 8007912: f64f 70ff movw r0, #65535 @ 0xffff + 8007916: f002 fb4f bl 8009fb8 + + RadioSleep(); + 800791a: f000 fe9f bl 800865c + // Initialize driver timeout timers + TimerInit( &TxTimeoutTimer, RadioOnTxTimeoutIrq ); + 800791e: 2300 movs r3, #0 + 8007920: 9300 str r3, [sp, #0] + 8007922: 4b10 ldr r3, [pc, #64] @ (8007964 ) + 8007924: 2200 movs r2, #0 + 8007926: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff + 800792a: 480f ldr r0, [pc, #60] @ (8007968 ) + 800792c: f006 f8e0 bl 800daf0 + TimerInit( &RxTimeoutTimer, RadioOnRxTimeoutIrq ); + 8007930: 2300 movs r3, #0 + 8007932: 9300 str r3, [sp, #0] + 8007934: 4b0d ldr r3, [pc, #52] @ (800796c ) + 8007936: 2200 movs r2, #0 + 8007938: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff + 800793c: 480c ldr r0, [pc, #48] @ (8007970 ) + 800793e: f006 f8d7 bl 800daf0 + TimerStop( &TxTimeoutTimer ); + 8007942: 4809 ldr r0, [pc, #36] @ (8007968 ) + 8007944: f006 f978 bl 800dc38 + TimerStop( &RxTimeoutTimer ); + 8007948: 4809 ldr r0, [pc, #36] @ (8007970 ) + 800794a: f006 f975 bl 800dc38 +} + 800794e: bf00 nop + 8007950: 3708 adds r7, #8 + 8007952: 46bd mov sp, r7 + 8007954: bd80 pop {r7, pc} + 8007956: bf00 nop + 8007958: 200002fc .word 0x200002fc + 800795c: 20000300 .word 0x20000300 + 8007960: 08008a81 .word 0x08008a81 + 8007964: 080089f1 .word 0x080089f1 + 8007968: 2000035c .word 0x2000035c + 800796c: 08008a05 .word 0x08008a05 + 8007970: 20000374 .word 0x20000374 + +08007974 : + +static RadioState_t RadioGetStatus( void ) +{ + 8007974: b580 push {r7, lr} + 8007976: af00 add r7, sp, #0 + switch( SUBGRF_GetOperatingMode( ) ) + 8007978: f001 fff8 bl 800996c + 800797c: 4603 mov r3, r0 + 800797e: 2b07 cmp r3, #7 + 8007980: d00a beq.n 8007998 + 8007982: 2b07 cmp r3, #7 + 8007984: dc0a bgt.n 800799c + 8007986: 2b04 cmp r3, #4 + 8007988: d002 beq.n 8007990 + 800798a: 2b05 cmp r3, #5 + 800798c: d002 beq.n 8007994 + 800798e: e005 b.n 800799c + { + case MODE_TX: + return RF_TX_RUNNING; + 8007990: 2302 movs r3, #2 + 8007992: e004 b.n 800799e + case MODE_RX: + return RF_RX_RUNNING; + 8007994: 2301 movs r3, #1 + 8007996: e002 b.n 800799e + case MODE_CAD: + return RF_CAD; + 8007998: 2303 movs r3, #3 + 800799a: e000 b.n 800799e + default: + return RF_IDLE; + 800799c: 2300 movs r3, #0 + } +} + 800799e: 4618 mov r0, r3 + 80079a0: bd80 pop {r7, pc} + ... + +080079a4 : + +static void RadioSetModem( RadioModems_t modem ) +{ + 80079a4: b580 push {r7, lr} + 80079a6: b082 sub sp, #8 + 80079a8: af00 add r7, sp, #0 + 80079aa: 4603 mov r3, r0 + 80079ac: 71fb strb r3, [r7, #7] + SubgRf.Modem = modem; + 80079ae: 4a2a ldr r2, [pc, #168] @ (8007a58 ) + 80079b0: 79fb ldrb r3, [r7, #7] + 80079b2: 7013 strb r3, [r2, #0] + RFW_SetRadioModem( modem ); + 80079b4: 79fb ldrb r3, [r7, #7] + 80079b6: 4618 mov r0, r3 + 80079b8: f003 fd82 bl 800b4c0 + switch( modem ) + 80079bc: 79fb ldrb r3, [r7, #7] + 80079be: 2b05 cmp r3, #5 + 80079c0: d80e bhi.n 80079e0 + 80079c2: a201 add r2, pc, #4 @ (adr r2, 80079c8 ) + 80079c4: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 80079c8: 080079ef .word 0x080079ef + 80079cc: 080079fd .word 0x080079fd + 80079d0: 080079e1 .word 0x080079e1 + 80079d4: 08007a23 .word 0x08007a23 + 80079d8: 08007a31 .word 0x08007a31 + 80079dc: 08007a3f .word 0x08007a3f + { + default: + case MODEM_MSK: + SUBGRF_SetPacketType( PACKET_TYPE_GMSK ); + 80079e0: 2003 movs r0, #3 + 80079e2: f002 fb8b bl 800a0fc + // When switching to GFSK mode the LoRa SyncWord register value is reset + // Thus, we also reset the RadioPublicNetwork variable + SubgRf.PublicNetwork.Current = false; + 80079e6: 4b1c ldr r3, [pc, #112] @ (8007a58 ) + 80079e8: 2200 movs r2, #0 + 80079ea: 735a strb r2, [r3, #13] + break; + 80079ec: e02f b.n 8007a4e + case MODEM_FSK: + SUBGRF_SetPacketType( PACKET_TYPE_GFSK ); + 80079ee: 2000 movs r0, #0 + 80079f0: f002 fb84 bl 800a0fc + // When switching to GFSK mode the LoRa SyncWord register value is reset + // Thus, we also reset the RadioPublicNetwork variable + SubgRf.PublicNetwork.Current = false; + 80079f4: 4b18 ldr r3, [pc, #96] @ (8007a58 ) + 80079f6: 2200 movs r2, #0 + 80079f8: 735a strb r2, [r3, #13] + break; + 80079fa: e028 b.n 8007a4e + case MODEM_LORA: + SUBGRF_SetPacketType( PACKET_TYPE_LORA ); + 80079fc: 2001 movs r0, #1 + 80079fe: f002 fb7d bl 800a0fc + // Public/Private network register is reset when switching modems + if( SubgRf.PublicNetwork.Current != SubgRf.PublicNetwork.Previous ) + 8007a02: 4b15 ldr r3, [pc, #84] @ (8007a58 ) + 8007a04: 7b5a ldrb r2, [r3, #13] + 8007a06: 4b14 ldr r3, [pc, #80] @ (8007a58 ) + 8007a08: 7b1b ldrb r3, [r3, #12] + 8007a0a: 429a cmp r2, r3 + 8007a0c: d01e beq.n 8007a4c + { + SubgRf.PublicNetwork.Current = SubgRf.PublicNetwork.Previous; + 8007a0e: 4b12 ldr r3, [pc, #72] @ (8007a58 ) + 8007a10: 7b1a ldrb r2, [r3, #12] + 8007a12: 4b11 ldr r3, [pc, #68] @ (8007a58 ) + 8007a14: 735a strb r2, [r3, #13] + RadioSetPublicNetwork( SubgRf.PublicNetwork.Current ); + 8007a16: 4b10 ldr r3, [pc, #64] @ (8007a58 ) + 8007a18: 7b5b ldrb r3, [r3, #13] + 8007a1a: 4618 mov r0, r3 + 8007a1c: f000 ffb2 bl 8008984 + } + break; + 8007a20: e014 b.n 8007a4c + case MODEM_BPSK: + SUBGRF_SetPacketType( PACKET_TYPE_BPSK ); + 8007a22: 2002 movs r0, #2 + 8007a24: f002 fb6a bl 800a0fc + // When switching to BPSK mode the LoRa SyncWord register value is reset + // Thus, we also reset the RadioPublicNetwork variable + SubgRf.PublicNetwork.Current = false; + 8007a28: 4b0b ldr r3, [pc, #44] @ (8007a58 ) + 8007a2a: 2200 movs r2, #0 + 8007a2c: 735a strb r2, [r3, #13] + break; + 8007a2e: e00e b.n 8007a4e +#if (RADIO_SIGFOX_ENABLE == 1) + case MODEM_SIGFOX_TX: + SUBGRF_SetPacketType( PACKET_TYPE_BPSK ); + 8007a30: 2002 movs r0, #2 + 8007a32: f002 fb63 bl 800a0fc + // When switching to BPSK mode the LoRa SyncWord register value is reset + // Thus, we also reset the RadioPublicNetwork variable + SubgRf.PublicNetwork.Current = false; + 8007a36: 4b08 ldr r3, [pc, #32] @ (8007a58 ) + 8007a38: 2200 movs r2, #0 + 8007a3a: 735a strb r2, [r3, #13] + break; + 8007a3c: e007 b.n 8007a4e + case MODEM_SIGFOX_RX: + SUBGRF_SetPacketType( PACKET_TYPE_GFSK ); + 8007a3e: 2000 movs r0, #0 + 8007a40: f002 fb5c bl 800a0fc + // When switching to GFSK mode the LoRa SyncWord register value is reset + // Thus, we also reset the RadioPublicNetwork variable + SubgRf.PublicNetwork.Current = false; + 8007a44: 4b04 ldr r3, [pc, #16] @ (8007a58 ) + 8007a46: 2200 movs r2, #0 + 8007a48: 735a strb r2, [r3, #13] + break; + 8007a4a: e000 b.n 8007a4e + break; + 8007a4c: bf00 nop +#endif /*RADIO_SIGFOX_ENABLE == 1*/ + } +} + 8007a4e: bf00 nop + 8007a50: 3708 adds r7, #8 + 8007a52: 46bd mov sp, r7 + 8007a54: bd80 pop {r7, pc} + 8007a56: bf00 nop + 8007a58: 20000300 .word 0x20000300 + +08007a5c : + +static void RadioSetChannel( uint32_t freq ) +{ + 8007a5c: b580 push {r7, lr} + 8007a5e: b082 sub sp, #8 + 8007a60: af00 add r7, sp, #0 + 8007a62: 6078 str r0, [r7, #4] + SUBGRF_SetRfFrequency( freq ); + 8007a64: 6878 ldr r0, [r7, #4] + 8007a66: f002 fb03 bl 800a070 +} + 8007a6a: bf00 nop + 8007a6c: 3708 adds r7, #8 + 8007a6e: 46bd mov sp, r7 + 8007a70: bd80 pop {r7, pc} + +08007a72 : + +static bool RadioIsChannelFree( uint32_t freq, uint32_t rxBandwidth, int16_t rssiThresh, uint32_t maxCarrierSenseTime ) +{ + 8007a72: b580 push {r7, lr} + 8007a74: b090 sub sp, #64 @ 0x40 + 8007a76: af0a add r7, sp, #40 @ 0x28 + 8007a78: 60f8 str r0, [r7, #12] + 8007a7a: 60b9 str r1, [r7, #8] + 8007a7c: 603b str r3, [r7, #0] + 8007a7e: 4613 mov r3, r2 + 8007a80: 80fb strh r3, [r7, #6] + bool status = true; + 8007a82: 2301 movs r3, #1 + 8007a84: 75fb strb r3, [r7, #23] + int16_t rssi = 0; + 8007a86: 2300 movs r3, #0 + 8007a88: 82bb strh r3, [r7, #20] + uint32_t carrierSenseTime = 0; + 8007a8a: 2300 movs r3, #0 + 8007a8c: 613b str r3, [r7, #16] + + RadioStandby( ); + 8007a8e: f000 fdf8 bl 8008682 + + RadioSetModem( MODEM_FSK ); + 8007a92: 2000 movs r0, #0 + 8007a94: f7ff ff86 bl 80079a4 + + RadioSetChannel( freq ); + 8007a98: 68f8 ldr r0, [r7, #12] + 8007a9a: f7ff ffdf bl 8007a5c + + // Set Rx bandwidth. Other parameters are not used. + RadioSetRxConfig( MODEM_FSK, rxBandwidth, 600, 0, rxBandwidth, 3, 0, false, + 8007a9e: 2301 movs r3, #1 + 8007aa0: 9309 str r3, [sp, #36] @ 0x24 + 8007aa2: 2300 movs r3, #0 + 8007aa4: 9308 str r3, [sp, #32] + 8007aa6: 2300 movs r3, #0 + 8007aa8: 9307 str r3, [sp, #28] + 8007aaa: 2300 movs r3, #0 + 8007aac: 9306 str r3, [sp, #24] + 8007aae: 2300 movs r3, #0 + 8007ab0: 9305 str r3, [sp, #20] + 8007ab2: 2300 movs r3, #0 + 8007ab4: 9304 str r3, [sp, #16] + 8007ab6: 2300 movs r3, #0 + 8007ab8: 9303 str r3, [sp, #12] + 8007aba: 2300 movs r3, #0 + 8007abc: 9302 str r3, [sp, #8] + 8007abe: 2303 movs r3, #3 + 8007ac0: 9301 str r3, [sp, #4] + 8007ac2: 68bb ldr r3, [r7, #8] + 8007ac4: 9300 str r3, [sp, #0] + 8007ac6: 2300 movs r3, #0 + 8007ac8: f44f 7216 mov.w r2, #600 @ 0x258 + 8007acc: 68b9 ldr r1, [r7, #8] + 8007ace: 2000 movs r0, #0 + 8007ad0: f000 f83c bl 8007b4c + 0, false, 0, 0, false, true ); + RadioRx( 0 ); + 8007ad4: 2000 movs r0, #0 + 8007ad6: f000 fddb bl 8008690 + + RADIO_DELAY_MS( RadioGetWakeupTime( ) ); + 8007ada: f000 ff81 bl 80089e0 + 8007ade: 4603 mov r3, r0 + 8007ae0: 4618 mov r0, r3 + 8007ae2: f7f9 f8c5 bl 8000c70 + + carrierSenseTime = TimerGetCurrentTime( ); + 8007ae6: f006 f9c1 bl 800de6c + 8007aea: 6138 str r0, [r7, #16] + + // Perform carrier sense for maxCarrierSenseTime + while( TimerGetElapsedTime( carrierSenseTime ) < maxCarrierSenseTime ) + 8007aec: e00d b.n 8007b0a + { + rssi = RadioRssi( MODEM_FSK ); + 8007aee: 2000 movs r0, #0 + 8007af0: f000 fec8 bl 8008884 + 8007af4: 4603 mov r3, r0 + 8007af6: 82bb strh r3, [r7, #20] + + if( rssi > rssiThresh ) + 8007af8: f9b7 2014 ldrsh.w r2, [r7, #20] + 8007afc: f9b7 3006 ldrsh.w r3, [r7, #6] + 8007b00: 429a cmp r2, r3 + 8007b02: dd02 ble.n 8007b0a + { + status = false; + 8007b04: 2300 movs r3, #0 + 8007b06: 75fb strb r3, [r7, #23] + break; + 8007b08: e006 b.n 8007b18 + while( TimerGetElapsedTime( carrierSenseTime ) < maxCarrierSenseTime ) + 8007b0a: 6938 ldr r0, [r7, #16] + 8007b0c: f006 f9c0 bl 800de90 + 8007b10: 4602 mov r2, r0 + 8007b12: 683b ldr r3, [r7, #0] + 8007b14: 4293 cmp r3, r2 + 8007b16: d8ea bhi.n 8007aee + } + } + RadioStandby( ); + 8007b18: f000 fdb3 bl 8008682 + + return status; + 8007b1c: 7dfb ldrb r3, [r7, #23] +} + 8007b1e: 4618 mov r0, r3 + 8007b20: 3718 adds r7, #24 + 8007b22: 46bd mov sp, r7 + 8007b24: bd80 pop {r7, pc} + +08007b26 : + +static uint32_t RadioRandom( void ) +{ + 8007b26: b580 push {r7, lr} + 8007b28: b082 sub sp, #8 + 8007b2a: af00 add r7, sp, #0 + uint32_t rnd = 0; + 8007b2c: 2300 movs r3, #0 + 8007b2e: 607b str r3, [r7, #4] + + /* + * Radio setup for random number generation + */ + // Disable modem interrupts + SUBGRF_SetDioIrqParams( IRQ_RADIO_NONE, IRQ_RADIO_NONE, IRQ_RADIO_NONE, IRQ_RADIO_NONE ); + 8007b30: 2300 movs r3, #0 + 8007b32: 2200 movs r2, #0 + 8007b34: 2100 movs r1, #0 + 8007b36: 2000 movs r0, #0 + 8007b38: f002 fa3e bl 8009fb8 + + rnd = SUBGRF_GetRandom(); + 8007b3c: f001 ffe7 bl 8009b0e + 8007b40: 6078 str r0, [r7, #4] + + return rnd; + 8007b42: 687b ldr r3, [r7, #4] +} + 8007b44: 4618 mov r0, r3 + 8007b46: 3708 adds r7, #8 + 8007b48: 46bd mov sp, r7 + 8007b4a: bd80 pop {r7, pc} + +08007b4c : + uint32_t bandwidthAfc, uint16_t preambleLen, + uint16_t symbTimeout, bool fixLen, + uint8_t payloadLen, + bool crcOn, bool freqHopOn, uint8_t hopPeriod, + bool iqInverted, bool rxContinuous ) +{ + 8007b4c: b580 push {r7, lr} + 8007b4e: b08a sub sp, #40 @ 0x28 + 8007b50: af00 add r7, sp, #0 + 8007b52: 60b9 str r1, [r7, #8] + 8007b54: 607a str r2, [r7, #4] + 8007b56: 461a mov r2, r3 + 8007b58: 4603 mov r3, r0 + 8007b5a: 73fb strb r3, [r7, #15] + 8007b5c: 4613 mov r3, r2 + 8007b5e: 73bb strb r3, [r7, #14] +#if (RADIO_SIGFOX_ENABLE == 1) + uint8_t modReg; +#endif + SubgRf.RxContinuous = rxContinuous; + 8007b60: 4ab9 ldr r2, [pc, #740] @ (8007e48 ) + 8007b62: f897 3054 ldrb.w r3, [r7, #84] @ 0x54 + 8007b66: 7053 strb r3, [r2, #1] + RFW_DeInit(); + 8007b68: f003 fb40 bl 800b1ec + if( rxContinuous == true ) + 8007b6c: f897 3054 ldrb.w r3, [r7, #84] @ 0x54 + 8007b70: 2b00 cmp r3, #0 + 8007b72: d001 beq.n 8007b78 + { + symbTimeout = 0; + 8007b74: 2300 movs r3, #0 + 8007b76: 873b strh r3, [r7, #56] @ 0x38 + } + if( fixLen == true ) + 8007b78: f897 303c ldrb.w r3, [r7, #60] @ 0x3c + 8007b7c: 2b00 cmp r3, #0 + 8007b7e: d004 beq.n 8007b8a + { + MaxPayloadLength = payloadLen; + 8007b80: 4ab2 ldr r2, [pc, #712] @ (8007e4c ) + 8007b82: f897 3040 ldrb.w r3, [r7, #64] @ 0x40 + 8007b86: 7013 strb r3, [r2, #0] + 8007b88: e002 b.n 8007b90 + } + else + { + MaxPayloadLength = 0xFF; + 8007b8a: 4bb0 ldr r3, [pc, #704] @ (8007e4c ) + 8007b8c: 22ff movs r2, #255 @ 0xff + 8007b8e: 701a strb r2, [r3, #0] + } + + switch( modem ) + 8007b90: 7bfb ldrb r3, [r7, #15] + 8007b92: 2b05 cmp r3, #5 + 8007b94: d009 beq.n 8007baa + 8007b96: 2b05 cmp r3, #5 + 8007b98: f300 81d7 bgt.w 8007f4a + 8007b9c: 2b00 cmp r3, #0 + 8007b9e: f000 80bf beq.w 8007d20 + 8007ba2: 2b01 cmp r3, #1 + 8007ba4: f000 8124 beq.w 8007df0 + // Timeout Max, Timeout handled directly in SetRx function + SubgRf.RxTimeout = 0xFFFF; + + break; + default: + break; + 8007ba8: e1cf b.n 8007f4a + SUBGRF_SetStopRxTimerOnPreambleDetect( true ); + 8007baa: 2001 movs r0, #1 + 8007bac: f002 f8f6 bl 8009d9c + SubgRf.ModulationParams.PacketType = PACKET_TYPE_GFSK; + 8007bb0: 4ba5 ldr r3, [pc, #660] @ (8007e48 ) + 8007bb2: 2200 movs r2, #0 + 8007bb4: f883 2038 strb.w r2, [r3, #56] @ 0x38 + SubgRf.ModulationParams.Params.Gfsk.BitRate = datarate; + 8007bb8: 4aa3 ldr r2, [pc, #652] @ (8007e48 ) + 8007bba: 687b ldr r3, [r7, #4] + 8007bbc: 63d3 str r3, [r2, #60] @ 0x3c + SubgRf.ModulationParams.Params.Gfsk.ModulationShaping = MOD_SHAPING_G_BT_05; + 8007bbe: 4ba2 ldr r3, [pc, #648] @ (8007e48 ) + 8007bc0: 2209 movs r2, #9 + 8007bc2: f883 2044 strb.w r2, [r3, #68] @ 0x44 + SubgRf.ModulationParams.Params.Gfsk.Fdev = 800; + 8007bc6: 4ba0 ldr r3, [pc, #640] @ (8007e48 ) + 8007bc8: f44f 7248 mov.w r2, #800 @ 0x320 + 8007bcc: 641a str r2, [r3, #64] @ 0x40 + SubgRf.ModulationParams.Params.Gfsk.Bandwidth = SUBGRF_GetFskBandwidthRegValue( bandwidth ); + 8007bce: 68b8 ldr r0, [r7, #8] + 8007bd0: f002 ffd0 bl 800ab74 + 8007bd4: 4603 mov r3, r0 + 8007bd6: 461a mov r2, r3 + 8007bd8: 4b9b ldr r3, [pc, #620] @ (8007e48 ) + 8007bda: f883 2045 strb.w r2, [r3, #69] @ 0x45 + SubgRf.PacketParams.PacketType = PACKET_TYPE_GFSK; + 8007bde: 4b9a ldr r3, [pc, #616] @ (8007e48 ) + 8007be0: 2200 movs r2, #0 + 8007be2: 739a strb r2, [r3, #14] + SubgRf.PacketParams.Params.Gfsk.PreambleLength = ( preambleLen << 3 ); // convert byte into bit + 8007be4: 8ebb ldrh r3, [r7, #52] @ 0x34 + 8007be6: 00db lsls r3, r3, #3 + 8007be8: b29a uxth r2, r3 + 8007bea: 4b97 ldr r3, [pc, #604] @ (8007e48 ) + 8007bec: 821a strh r2, [r3, #16] + SubgRf.PacketParams.Params.Gfsk.PreambleMinDetect = RADIO_PREAMBLE_DETECTOR_OFF; + 8007bee: 4b96 ldr r3, [pc, #600] @ (8007e48 ) + 8007bf0: 2200 movs r2, #0 + 8007bf2: 749a strb r2, [r3, #18] + SubgRf.PacketParams.Params.Gfsk.SyncWordLength = 2 << 3; // convert byte into bit + 8007bf4: 4b94 ldr r3, [pc, #592] @ (8007e48 ) + 8007bf6: 2210 movs r2, #16 + 8007bf8: 74da strb r2, [r3, #19] + SubgRf.PacketParams.Params.Gfsk.AddrComp = RADIO_ADDRESSCOMP_FILT_OFF; + 8007bfa: 4b93 ldr r3, [pc, #588] @ (8007e48 ) + 8007bfc: 2200 movs r2, #0 + 8007bfe: 751a strb r2, [r3, #20] + SubgRf.PacketParams.Params.Gfsk.HeaderType = RADIO_PACKET_FIXED_LENGTH; + 8007c00: 4b91 ldr r3, [pc, #580] @ (8007e48 ) + 8007c02: 2200 movs r2, #0 + 8007c04: 755a strb r2, [r3, #21] + SubgRf.PacketParams.Params.Gfsk.PayloadLength = MaxPayloadLength; + 8007c06: 4b91 ldr r3, [pc, #580] @ (8007e4c ) + 8007c08: 781a ldrb r2, [r3, #0] + 8007c0a: 4b8f ldr r3, [pc, #572] @ (8007e48 ) + 8007c0c: 759a strb r2, [r3, #22] + SubgRf.PacketParams.Params.Gfsk.CrcLength = RADIO_CRC_OFF; + 8007c0e: 4b8e ldr r3, [pc, #568] @ (8007e48 ) + 8007c10: 2201 movs r2, #1 + 8007c12: 75da strb r2, [r3, #23] + SubgRf.PacketParams.Params.Gfsk.DcFree = RADIO_DC_FREE_OFF; + 8007c14: 4b8c ldr r3, [pc, #560] @ (8007e48 ) + 8007c16: 2200 movs r2, #0 + 8007c18: 761a strb r2, [r3, #24] + RadioSetModem( MODEM_SIGFOX_RX ); + 8007c1a: 2005 movs r0, #5 + 8007c1c: f7ff fec2 bl 80079a4 + SUBGRF_SetModulationParams( &SubgRf.ModulationParams ); + 8007c20: 488b ldr r0, [pc, #556] @ (8007e50 ) + 8007c22: f002 fb5f bl 800a2e4 + SUBGRF_SetPacketParams( &SubgRf.PacketParams ); + 8007c26: 488b ldr r0, [pc, #556] @ (8007e54 ) + 8007c28: f002 fc2a bl 800a480 + SUBGRF_SetSyncWord( ( uint8_t[] ){0xB2, 0x27, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 } ); + 8007c2c: 4a8a ldr r2, [pc, #552] @ (8007e58 ) + 8007c2e: f107 031c add.w r3, r7, #28 + 8007c32: e892 0003 ldmia.w r2, {r0, r1} + 8007c36: e883 0003 stmia.w r3, {r0, r1} + 8007c3a: f107 031c add.w r3, r7, #28 + 8007c3e: 4618 mov r0, r3 + 8007c40: f001 fee3 bl 8009a0a + SUBGRF_SetWhiteningSeed( 0x01FF ); + 8007c44: f240 10ff movw r0, #511 @ 0x1ff + 8007c48: f001 ff2e bl 8009aa8 + modReg= RadioRead(SUBGHZ_AGCGFORSTCFGR); + 8007c4c: f640 00b8 movw r0, #2232 @ 0x8b8 + 8007c50: f000 fe36 bl 80088c0 + 8007c54: 4603 mov r3, r0 + 8007c56: f887 3027 strb.w r3, [r7, #39] @ 0x27 + modReg&=RADIO_BIT_MASK(4); + 8007c5a: f897 3027 ldrb.w r3, [r7, #39] @ 0x27 + 8007c5e: f023 0310 bic.w r3, r3, #16 + 8007c62: f887 3027 strb.w r3, [r7, #39] @ 0x27 + RadioWrite(SUBGHZ_AGCGFORSTCFGR, modReg); + 8007c66: f897 3027 ldrb.w r3, [r7, #39] @ 0x27 + 8007c6a: 4619 mov r1, r3 + 8007c6c: f640 00b8 movw r0, #2232 @ 0x8b8 + 8007c70: f000 fe14 bl 800889c + RadioWrite(SUBGHZ_AGCGFORSTPOWTHR, 0x4 ); + 8007c74: 2104 movs r1, #4 + 8007c76: f640 00b9 movw r0, #2233 @ 0x8b9 + 8007c7a: f000 fe0f bl 800889c + modReg= RadioRead(SUBGHZ_AGCRSSICTL0R); + 8007c7e: f640 009b movw r0, #2203 @ 0x89b + 8007c82: f000 fe1d bl 80088c0 + 8007c86: 4603 mov r3, r0 + 8007c88: f887 3027 strb.w r3, [r7, #39] @ 0x27 + modReg&=( RADIO_BIT_MASK(2) & RADIO_BIT_MASK(3) & RADIO_BIT_MASK(4) ); + 8007c8c: f897 3027 ldrb.w r3, [r7, #39] @ 0x27 + 8007c90: f023 031c bic.w r3, r3, #28 + 8007c94: f887 3027 strb.w r3, [r7, #39] @ 0x27 + RadioWrite(SUBGHZ_AGCRSSICTL0R, (modReg| (0x1<<3) ) ); + 8007c98: f897 3027 ldrb.w r3, [r7, #39] @ 0x27 + 8007c9c: f043 0308 orr.w r3, r3, #8 + 8007ca0: b2db uxtb r3, r3 + 8007ca2: 4619 mov r1, r3 + 8007ca4: f640 009b movw r0, #2203 @ 0x89b + 8007ca8: f000 fdf8 bl 800889c + modReg= RadioRead(SUBGHZ_GAFCR); + 8007cac: f240 60d1 movw r0, #1745 @ 0x6d1 + 8007cb0: f000 fe06 bl 80088c0 + 8007cb4: 4603 mov r3, r0 + 8007cb6: f887 3027 strb.w r3, [r7, #39] @ 0x27 + modReg&=( RADIO_BIT_MASK(3) & RADIO_BIT_MASK(4) ); + 8007cba: f897 3027 ldrb.w r3, [r7, #39] @ 0x27 + 8007cbe: f023 0318 bic.w r3, r3, #24 + 8007cc2: f887 3027 strb.w r3, [r7, #39] @ 0x27 + RadioWrite(SUBGHZ_GAFCR, (modReg| (0x3<<3) )); + 8007cc6: f897 3027 ldrb.w r3, [r7, #39] @ 0x27 + 8007cca: f043 0318 orr.w r3, r3, #24 + 8007cce: b2db uxtb r3, r3 + 8007cd0: 4619 mov r1, r3 + 8007cd2: f240 60d1 movw r0, #1745 @ 0x6d1 + 8007cd6: f000 fde1 bl 800889c + modReg= RadioRead(SUBGHZ_GBSYNCR); + 8007cda: f240 60ac movw r0, #1708 @ 0x6ac + 8007cde: f000 fdef bl 80088c0 + 8007ce2: 4603 mov r3, r0 + 8007ce4: f887 3027 strb.w r3, [r7, #39] @ 0x27 + modReg&=( RADIO_BIT_MASK(4) & RADIO_BIT_MASK(5) & RADIO_BIT_MASK(6) ); + 8007ce8: f897 3027 ldrb.w r3, [r7, #39] @ 0x27 + 8007cec: f023 0370 bic.w r3, r3, #112 @ 0x70 + 8007cf0: f887 3027 strb.w r3, [r7, #39] @ 0x27 + RadioWrite(SUBGHZ_GBSYNCR, (modReg| (0x5<<4) )); + 8007cf4: f897 3027 ldrb.w r3, [r7, #39] @ 0x27 + 8007cf8: f043 0350 orr.w r3, r3, #80 @ 0x50 + 8007cfc: b2db uxtb r3, r3 + 8007cfe: 4619 mov r1, r3 + 8007d00: f240 60ac movw r0, #1708 @ 0x6ac + 8007d04: f000 fdca bl 800889c + SubgRf.RxTimeout = ( uint32_t )(( symbTimeout * 8 * 1000 ) /datarate); + 8007d08: 8f3b ldrh r3, [r7, #56] @ 0x38 + 8007d0a: f44f 52fa mov.w r2, #8000 @ 0x1f40 + 8007d0e: fb02 f303 mul.w r3, r2, r3 + 8007d12: 461a mov r2, r3 + 8007d14: 687b ldr r3, [r7, #4] + 8007d16: fbb2 f3f3 udiv r3, r2, r3 + 8007d1a: 4a4b ldr r2, [pc, #300] @ (8007e48 ) + 8007d1c: 6093 str r3, [r2, #8] + break; + 8007d1e: e115 b.n 8007f4c + SUBGRF_SetStopRxTimerOnPreambleDetect( false ); + 8007d20: 2000 movs r0, #0 + 8007d22: f002 f83b bl 8009d9c + SubgRf.ModulationParams.PacketType = PACKET_TYPE_GFSK; + 8007d26: 4b48 ldr r3, [pc, #288] @ (8007e48 ) + 8007d28: 2200 movs r2, #0 + 8007d2a: f883 2038 strb.w r2, [r3, #56] @ 0x38 + SubgRf.ModulationParams.Params.Gfsk.BitRate = datarate; + 8007d2e: 4a46 ldr r2, [pc, #280] @ (8007e48 ) + 8007d30: 687b ldr r3, [r7, #4] + 8007d32: 63d3 str r3, [r2, #60] @ 0x3c + SubgRf.ModulationParams.Params.Gfsk.ModulationShaping = MOD_SHAPING_G_BT_1; + 8007d34: 4b44 ldr r3, [pc, #272] @ (8007e48 ) + 8007d36: 220b movs r2, #11 + 8007d38: f883 2044 strb.w r2, [r3, #68] @ 0x44 + SubgRf.ModulationParams.Params.Gfsk.Bandwidth = SUBGRF_GetFskBandwidthRegValue( bandwidth ); + 8007d3c: 68b8 ldr r0, [r7, #8] + 8007d3e: f002 ff19 bl 800ab74 + 8007d42: 4603 mov r3, r0 + 8007d44: 461a mov r2, r3 + 8007d46: 4b40 ldr r3, [pc, #256] @ (8007e48 ) + 8007d48: f883 2045 strb.w r2, [r3, #69] @ 0x45 + SubgRf.PacketParams.PacketType = PACKET_TYPE_GFSK; + 8007d4c: 4b3e ldr r3, [pc, #248] @ (8007e48 ) + 8007d4e: 2200 movs r2, #0 + 8007d50: 739a strb r2, [r3, #14] + SubgRf.PacketParams.Params.Gfsk.PreambleLength = ( preambleLen << 3 ); // convert byte into bit + 8007d52: 8ebb ldrh r3, [r7, #52] @ 0x34 + 8007d54: 00db lsls r3, r3, #3 + 8007d56: b29a uxth r2, r3 + 8007d58: 4b3b ldr r3, [pc, #236] @ (8007e48 ) + 8007d5a: 821a strh r2, [r3, #16] + SubgRf.PacketParams.Params.Gfsk.PreambleMinDetect = RADIO_PREAMBLE_DETECTOR_08_BITS; + 8007d5c: 4b3a ldr r3, [pc, #232] @ (8007e48 ) + 8007d5e: 2204 movs r2, #4 + 8007d60: 749a strb r2, [r3, #18] + SubgRf.PacketParams.Params.Gfsk.SyncWordLength = 3 << 3; // convert byte into bit + 8007d62: 4b39 ldr r3, [pc, #228] @ (8007e48 ) + 8007d64: 2218 movs r2, #24 + 8007d66: 74da strb r2, [r3, #19] + SubgRf.PacketParams.Params.Gfsk.AddrComp = RADIO_ADDRESSCOMP_FILT_OFF; + 8007d68: 4b37 ldr r3, [pc, #220] @ (8007e48 ) + 8007d6a: 2200 movs r2, #0 + 8007d6c: 751a strb r2, [r3, #20] + SubgRf.PacketParams.Params.Gfsk.HeaderType = ( fixLen == true ) ? RADIO_PACKET_FIXED_LENGTH : RADIO_PACKET_VARIABLE_LENGTH; + 8007d6e: f897 303c ldrb.w r3, [r7, #60] @ 0x3c + 8007d72: f083 0301 eor.w r3, r3, #1 + 8007d76: b2db uxtb r3, r3 + 8007d78: 461a mov r2, r3 + 8007d7a: 4b33 ldr r3, [pc, #204] @ (8007e48 ) + 8007d7c: 755a strb r2, [r3, #21] + SubgRf.PacketParams.Params.Gfsk.PayloadLength = MaxPayloadLength; + 8007d7e: 4b33 ldr r3, [pc, #204] @ (8007e4c ) + 8007d80: 781a ldrb r2, [r3, #0] + 8007d82: 4b31 ldr r3, [pc, #196] @ (8007e48 ) + 8007d84: 759a strb r2, [r3, #22] + if( crcOn == true ) + 8007d86: f897 3044 ldrb.w r3, [r7, #68] @ 0x44 + 8007d8a: 2b00 cmp r3, #0 + 8007d8c: d003 beq.n 8007d96 + SubgRf.PacketParams.Params.Gfsk.CrcLength = RADIO_CRC_2_BYTES_CCIT; + 8007d8e: 4b2e ldr r3, [pc, #184] @ (8007e48 ) + 8007d90: 22f2 movs r2, #242 @ 0xf2 + 8007d92: 75da strb r2, [r3, #23] + 8007d94: e002 b.n 8007d9c + SubgRf.PacketParams.Params.Gfsk.CrcLength = RADIO_CRC_OFF; + 8007d96: 4b2c ldr r3, [pc, #176] @ (8007e48 ) + 8007d98: 2201 movs r2, #1 + 8007d9a: 75da strb r2, [r3, #23] + SubgRf.PacketParams.Params.Gfsk.DcFree = RADIO_DC_FREEWHITENING; + 8007d9c: 4b2a ldr r3, [pc, #168] @ (8007e48 ) + 8007d9e: 2201 movs r2, #1 + 8007da0: 761a strb r2, [r3, #24] + RadioStandby( ); + 8007da2: f000 fc6e bl 8008682 + RadioSetModem( MODEM_FSK ); + 8007da6: 2000 movs r0, #0 + 8007da8: f7ff fdfc bl 80079a4 + SUBGRF_SetModulationParams( &SubgRf.ModulationParams ); + 8007dac: 4828 ldr r0, [pc, #160] @ (8007e50 ) + 8007dae: f002 fa99 bl 800a2e4 + SUBGRF_SetPacketParams( &SubgRf.PacketParams ); + 8007db2: 4828 ldr r0, [pc, #160] @ (8007e54 ) + 8007db4: f002 fb64 bl 800a480 + SUBGRF_SetSyncWord( ( uint8_t[] ){ 0xC1, 0x94, 0xC1, 0x00, 0x00, 0x00, 0x00, 0x00 } ); + 8007db8: 4a28 ldr r2, [pc, #160] @ (8007e5c ) + 8007dba: f107 0314 add.w r3, r7, #20 + 8007dbe: e892 0003 ldmia.w r2, {r0, r1} + 8007dc2: e883 0003 stmia.w r3, {r0, r1} + 8007dc6: f107 0314 add.w r3, r7, #20 + 8007dca: 4618 mov r0, r3 + 8007dcc: f001 fe1d bl 8009a0a + SUBGRF_SetWhiteningSeed( 0x01FF ); + 8007dd0: f240 10ff movw r0, #511 @ 0x1ff + 8007dd4: f001 fe68 bl 8009aa8 + SubgRf.RxTimeout = ( uint32_t )(( symbTimeout * 8 * 1000 ) /datarate); + 8007dd8: 8f3b ldrh r3, [r7, #56] @ 0x38 + 8007dda: f44f 52fa mov.w r2, #8000 @ 0x1f40 + 8007dde: fb02 f303 mul.w r3, r2, r3 + 8007de2: 461a mov r2, r3 + 8007de4: 687b ldr r3, [r7, #4] + 8007de6: fbb2 f3f3 udiv r3, r2, r3 + 8007dea: 4a17 ldr r2, [pc, #92] @ (8007e48 ) + 8007dec: 6093 str r3, [r2, #8] + break; + 8007dee: e0ad b.n 8007f4c + SUBGRF_SetStopRxTimerOnPreambleDetect( false ); + 8007df0: 2000 movs r0, #0 + 8007df2: f001 ffd3 bl 8009d9c + SubgRf.ModulationParams.PacketType = PACKET_TYPE_LORA; + 8007df6: 4b14 ldr r3, [pc, #80] @ (8007e48 ) + 8007df8: 2201 movs r2, #1 + 8007dfa: f883 2038 strb.w r2, [r3, #56] @ 0x38 + SubgRf.ModulationParams.Params.LoRa.SpreadingFactor = ( RadioLoRaSpreadingFactors_t )datarate; + 8007dfe: 687b ldr r3, [r7, #4] + 8007e00: b2da uxtb r2, r3 + 8007e02: 4b11 ldr r3, [pc, #68] @ (8007e48 ) + 8007e04: f883 2050 strb.w r2, [r3, #80] @ 0x50 + SubgRf.ModulationParams.Params.LoRa.Bandwidth = Bandwidths[bandwidth]; + 8007e08: 4a15 ldr r2, [pc, #84] @ (8007e60 ) + 8007e0a: 68bb ldr r3, [r7, #8] + 8007e0c: 4413 add r3, r2 + 8007e0e: 781a ldrb r2, [r3, #0] + 8007e10: 4b0d ldr r3, [pc, #52] @ (8007e48 ) + 8007e12: f883 2051 strb.w r2, [r3, #81] @ 0x51 + SubgRf.ModulationParams.Params.LoRa.CodingRate = ( RadioLoRaCodingRates_t )coderate; + 8007e16: 4a0c ldr r2, [pc, #48] @ (8007e48 ) + 8007e18: 7bbb ldrb r3, [r7, #14] + 8007e1a: f882 3052 strb.w r3, [r2, #82] @ 0x52 + if( ( ( bandwidth == 0 ) && ( ( datarate == 11 ) || ( datarate == 12 ) ) ) || + 8007e1e: 68bb ldr r3, [r7, #8] + 8007e20: 2b00 cmp r3, #0 + 8007e22: d105 bne.n 8007e30 + 8007e24: 687b ldr r3, [r7, #4] + 8007e26: 2b0b cmp r3, #11 + 8007e28: d008 beq.n 8007e3c + 8007e2a: 687b ldr r3, [r7, #4] + 8007e2c: 2b0c cmp r3, #12 + 8007e2e: d005 beq.n 8007e3c + 8007e30: 68bb ldr r3, [r7, #8] + 8007e32: 2b01 cmp r3, #1 + 8007e34: d116 bne.n 8007e64 + ( ( bandwidth == 1 ) && ( datarate == 12 ) ) ) + 8007e36: 687b ldr r3, [r7, #4] + 8007e38: 2b0c cmp r3, #12 + 8007e3a: d113 bne.n 8007e64 + SubgRf.ModulationParams.Params.LoRa.LowDatarateOptimize = 0x01; + 8007e3c: 4b02 ldr r3, [pc, #8] @ (8007e48 ) + 8007e3e: 2201 movs r2, #1 + 8007e40: f883 2053 strb.w r2, [r3, #83] @ 0x53 + 8007e44: e012 b.n 8007e6c + 8007e46: bf00 nop + 8007e48: 20000300 .word 0x20000300 + 8007e4c: 20000008 .word 0x20000008 + 8007e50: 20000338 .word 0x20000338 + 8007e54: 2000030e .word 0x2000030e + 8007e58: 0800f0e8 .word 0x0800f0e8 + 8007e5c: 0800f0f0 .word 0x0800f0f0 + 8007e60: 0800fc08 .word 0x0800fc08 + SubgRf.ModulationParams.Params.LoRa.LowDatarateOptimize = 0x00; + 8007e64: 4b3b ldr r3, [pc, #236] @ (8007f54 ) + 8007e66: 2200 movs r2, #0 + 8007e68: f883 2053 strb.w r2, [r3, #83] @ 0x53 + SubgRf.PacketParams.PacketType = PACKET_TYPE_LORA; + 8007e6c: 4b39 ldr r3, [pc, #228] @ (8007f54 ) + 8007e6e: 2201 movs r2, #1 + 8007e70: 739a strb r2, [r3, #14] + if( ( SubgRf.ModulationParams.Params.LoRa.SpreadingFactor == LORA_SF5 ) || + 8007e72: 4b38 ldr r3, [pc, #224] @ (8007f54 ) + 8007e74: f893 3050 ldrb.w r3, [r3, #80] @ 0x50 + 8007e78: 2b05 cmp r3, #5 + 8007e7a: d004 beq.n 8007e86 + ( SubgRf.ModulationParams.Params.LoRa.SpreadingFactor == LORA_SF6 ) ) + 8007e7c: 4b35 ldr r3, [pc, #212] @ (8007f54 ) + 8007e7e: f893 3050 ldrb.w r3, [r3, #80] @ 0x50 + if( ( SubgRf.ModulationParams.Params.LoRa.SpreadingFactor == LORA_SF5 ) || + 8007e82: 2b06 cmp r3, #6 + 8007e84: d10a bne.n 8007e9c + if( preambleLen < 12 ) + 8007e86: 8ebb ldrh r3, [r7, #52] @ 0x34 + 8007e88: 2b0b cmp r3, #11 + 8007e8a: d803 bhi.n 8007e94 + SubgRf.PacketParams.Params.LoRa.PreambleLength = 12; + 8007e8c: 4b31 ldr r3, [pc, #196] @ (8007f54 ) + 8007e8e: 220c movs r2, #12 + 8007e90: 839a strh r2, [r3, #28] + if( preambleLen < 12 ) + 8007e92: e006 b.n 8007ea2 + SubgRf.PacketParams.Params.LoRa.PreambleLength = preambleLen; + 8007e94: 4a2f ldr r2, [pc, #188] @ (8007f54 ) + 8007e96: 8ebb ldrh r3, [r7, #52] @ 0x34 + 8007e98: 8393 strh r3, [r2, #28] + if( preambleLen < 12 ) + 8007e9a: e002 b.n 8007ea2 + SubgRf.PacketParams.Params.LoRa.PreambleLength = preambleLen; + 8007e9c: 4a2d ldr r2, [pc, #180] @ (8007f54 ) + 8007e9e: 8ebb ldrh r3, [r7, #52] @ 0x34 + 8007ea0: 8393 strh r3, [r2, #28] + SubgRf.PacketParams.Params.LoRa.HeaderType = ( RadioLoRaPacketLengthsMode_t )fixLen; + 8007ea2: f897 203c ldrb.w r2, [r7, #60] @ 0x3c + 8007ea6: 4b2b ldr r3, [pc, #172] @ (8007f54 ) + 8007ea8: 779a strb r2, [r3, #30] + SubgRf.PacketParams.Params.LoRa.PayloadLength = MaxPayloadLength; + 8007eaa: 4b2b ldr r3, [pc, #172] @ (8007f58 ) + 8007eac: 781a ldrb r2, [r3, #0] + 8007eae: 4b29 ldr r3, [pc, #164] @ (8007f54 ) + 8007eb0: 77da strb r2, [r3, #31] + SubgRf.PacketParams.Params.LoRa.CrcMode = ( RadioLoRaCrcModes_t )crcOn; + 8007eb2: f897 2044 ldrb.w r2, [r7, #68] @ 0x44 + 8007eb6: 4b27 ldr r3, [pc, #156] @ (8007f54 ) + 8007eb8: f883 2020 strb.w r2, [r3, #32] + SubgRf.PacketParams.Params.LoRa.InvertIQ = ( RadioLoRaIQModes_t )iqInverted; + 8007ebc: f897 2050 ldrb.w r2, [r7, #80] @ 0x50 + 8007ec0: 4b24 ldr r3, [pc, #144] @ (8007f54 ) + 8007ec2: f883 2021 strb.w r2, [r3, #33] @ 0x21 + RadioStandby( ); + 8007ec6: f000 fbdc bl 8008682 + RadioSetModem( MODEM_LORA ); + 8007eca: 2001 movs r0, #1 + 8007ecc: f7ff fd6a bl 80079a4 + SUBGRF_SetModulationParams( &SubgRf.ModulationParams ); + 8007ed0: 4822 ldr r0, [pc, #136] @ (8007f5c ) + 8007ed2: f002 fa07 bl 800a2e4 + SUBGRF_SetPacketParams( &SubgRf.PacketParams ); + 8007ed6: 4822 ldr r0, [pc, #136] @ (8007f60 ) + 8007ed8: f002 fad2 bl 800a480 + SUBGRF_SetLoRaSymbNumTimeout( symbTimeout ); + 8007edc: 8f3b ldrh r3, [r7, #56] @ 0x38 + 8007ede: b2db uxtb r3, r3 + 8007ee0: 4618 mov r0, r3 + 8007ee2: f001 ff6a bl 8009dba + SUBGRF_WriteRegister(SUBGHZ_AGCCFG,SUBGRF_ReadRegister(SUBGHZ_AGCCFG)&0x1); + 8007ee6: f640 00a3 movw r0, #2211 @ 0x8a3 + 8007eea: f002 fc31 bl 800a750 + 8007eee: 4603 mov r3, r0 + 8007ef0: f003 0301 and.w r3, r3, #1 + 8007ef4: b2db uxtb r3, r3 + 8007ef6: 4619 mov r1, r3 + 8007ef8: f640 00a3 movw r0, #2211 @ 0x8a3 + 8007efc: f002 fc06 bl 800a70c + if( SubgRf.PacketParams.Params.LoRa.InvertIQ == LORA_IQ_INVERTED ) + 8007f00: 4b14 ldr r3, [pc, #80] @ (8007f54 ) + 8007f02: f893 3021 ldrb.w r3, [r3, #33] @ 0x21 + 8007f06: 2b01 cmp r3, #1 + 8007f08: d10d bne.n 8007f26 + SUBGRF_WriteRegister( SUBGHZ_LIQPOLR, SUBGRF_ReadRegister( SUBGHZ_LIQPOLR ) & ~( 1 << 2 ) ); + 8007f0a: f240 7036 movw r0, #1846 @ 0x736 + 8007f0e: f002 fc1f bl 800a750 + 8007f12: 4603 mov r3, r0 + 8007f14: f023 0304 bic.w r3, r3, #4 + 8007f18: b2db uxtb r3, r3 + 8007f1a: 4619 mov r1, r3 + 8007f1c: f240 7036 movw r0, #1846 @ 0x736 + 8007f20: f002 fbf4 bl 800a70c + 8007f24: e00c b.n 8007f40 + SUBGRF_WriteRegister( SUBGHZ_LIQPOLR, SUBGRF_ReadRegister( SUBGHZ_LIQPOLR ) | ( 1 << 2 ) ); + 8007f26: f240 7036 movw r0, #1846 @ 0x736 + 8007f2a: f002 fc11 bl 800a750 + 8007f2e: 4603 mov r3, r0 + 8007f30: f043 0304 orr.w r3, r3, #4 + 8007f34: b2db uxtb r3, r3 + 8007f36: 4619 mov r1, r3 + 8007f38: f240 7036 movw r0, #1846 @ 0x736 + 8007f3c: f002 fbe6 bl 800a70c + SubgRf.RxTimeout = 0xFFFF; + 8007f40: 4b04 ldr r3, [pc, #16] @ (8007f54 ) + 8007f42: f64f 72ff movw r2, #65535 @ 0xffff + 8007f46: 609a str r2, [r3, #8] + break; + 8007f48: e000 b.n 8007f4c + break; + 8007f4a: bf00 nop + } +} + 8007f4c: bf00 nop + 8007f4e: 3728 adds r7, #40 @ 0x28 + 8007f50: 46bd mov sp, r7 + 8007f52: bd80 pop {r7, pc} + 8007f54: 20000300 .word 0x20000300 + 8007f58: 20000008 .word 0x20000008 + 8007f5c: 20000338 .word 0x20000338 + 8007f60: 2000030e .word 0x2000030e + +08007f64 : +static void RadioSetTxConfig( RadioModems_t modem, int8_t power, uint32_t fdev, + uint32_t bandwidth, uint32_t datarate, + uint8_t coderate, uint16_t preambleLen, + bool fixLen, bool crcOn, bool freqHopOn, + uint8_t hopPeriod, bool iqInverted, uint32_t timeout ) +{ + 8007f64: b580 push {r7, lr} + 8007f66: b086 sub sp, #24 + 8007f68: af00 add r7, sp, #0 + 8007f6a: 60ba str r2, [r7, #8] + 8007f6c: 607b str r3, [r7, #4] + 8007f6e: 4603 mov r3, r0 + 8007f70: 73fb strb r3, [r7, #15] + 8007f72: 460b mov r3, r1 + 8007f74: 73bb strb r3, [r7, #14] +#if( RADIO_LR_FHSS_IS_ON == 1 ) + /*disable LrFhss*/ + SubgRf.lr_fhss.is_lr_fhss_on = false; +#endif /* RADIO_LR_FHSS_IS_ON == 1 */ + RFW_DeInit(); + 8007f76: f003 f939 bl 800b1ec + switch( modem ) + 8007f7a: 7bfb ldrb r3, [r7, #15] + 8007f7c: 2b04 cmp r3, #4 + 8007f7e: f000 80c7 beq.w 8008110 + 8007f82: 2b04 cmp r3, #4 + 8007f84: f300 80d6 bgt.w 8008134 + 8007f88: 2b00 cmp r3, #0 + 8007f8a: d002 beq.n 8007f92 + 8007f8c: 2b01 cmp r3, #1 + 8007f8e: d059 beq.n 8008044 + SubgRf.ModulationParams.Params.Bpsk.ModulationShaping = MOD_SHAPING_DBPSK; + SUBGRF_SetModulationParams( &SubgRf.ModulationParams ); + break; +#endif /*RADIO_SIGFOX_ENABLE == 1*/ + default: + break; + 8007f90: e0d0 b.n 8008134 + SubgRf.ModulationParams.PacketType = PACKET_TYPE_GFSK; + 8007f92: 4b77 ldr r3, [pc, #476] @ (8008170 ) + 8007f94: 2200 movs r2, #0 + 8007f96: f883 2038 strb.w r2, [r3, #56] @ 0x38 + SubgRf.ModulationParams.Params.Gfsk.BitRate = datarate; + 8007f9a: 4a75 ldr r2, [pc, #468] @ (8008170 ) + 8007f9c: 6a3b ldr r3, [r7, #32] + 8007f9e: 63d3 str r3, [r2, #60] @ 0x3c + SubgRf.ModulationParams.Params.Gfsk.ModulationShaping = MOD_SHAPING_G_BT_1; + 8007fa0: 4b73 ldr r3, [pc, #460] @ (8008170 ) + 8007fa2: 220b movs r2, #11 + 8007fa4: f883 2044 strb.w r2, [r3, #68] @ 0x44 + SubgRf.ModulationParams.Params.Gfsk.Bandwidth = SUBGRF_GetFskBandwidthRegValue( bandwidth ); + 8007fa8: 6878 ldr r0, [r7, #4] + 8007faa: f002 fde3 bl 800ab74 + 8007fae: 4603 mov r3, r0 + 8007fb0: 461a mov r2, r3 + 8007fb2: 4b6f ldr r3, [pc, #444] @ (8008170 ) + 8007fb4: f883 2045 strb.w r2, [r3, #69] @ 0x45 + SubgRf.ModulationParams.Params.Gfsk.Fdev = fdev; + 8007fb8: 4a6d ldr r2, [pc, #436] @ (8008170 ) + 8007fba: 68bb ldr r3, [r7, #8] + 8007fbc: 6413 str r3, [r2, #64] @ 0x40 + SubgRf.PacketParams.PacketType = PACKET_TYPE_GFSK; + 8007fbe: 4b6c ldr r3, [pc, #432] @ (8008170 ) + 8007fc0: 2200 movs r2, #0 + 8007fc2: 739a strb r2, [r3, #14] + SubgRf.PacketParams.Params.Gfsk.PreambleLength = ( preambleLen << 3 ); // convert byte into bit + 8007fc4: 8d3b ldrh r3, [r7, #40] @ 0x28 + 8007fc6: 00db lsls r3, r3, #3 + 8007fc8: b29a uxth r2, r3 + 8007fca: 4b69 ldr r3, [pc, #420] @ (8008170 ) + 8007fcc: 821a strh r2, [r3, #16] + SubgRf.PacketParams.Params.Gfsk.PreambleMinDetect = RADIO_PREAMBLE_DETECTOR_08_BITS; + 8007fce: 4b68 ldr r3, [pc, #416] @ (8008170 ) + 8007fd0: 2204 movs r2, #4 + 8007fd2: 749a strb r2, [r3, #18] + SubgRf.PacketParams.Params.Gfsk.SyncWordLength = 3 << 3 ; // convert byte into bit + 8007fd4: 4b66 ldr r3, [pc, #408] @ (8008170 ) + 8007fd6: 2218 movs r2, #24 + 8007fd8: 74da strb r2, [r3, #19] + SubgRf.PacketParams.Params.Gfsk.AddrComp = RADIO_ADDRESSCOMP_FILT_OFF; + 8007fda: 4b65 ldr r3, [pc, #404] @ (8008170 ) + 8007fdc: 2200 movs r2, #0 + 8007fde: 751a strb r2, [r3, #20] + SubgRf.PacketParams.Params.Gfsk.HeaderType = ( fixLen == true ) ? RADIO_PACKET_FIXED_LENGTH : RADIO_PACKET_VARIABLE_LENGTH; + 8007fe0: f897 302c ldrb.w r3, [r7, #44] @ 0x2c + 8007fe4: f083 0301 eor.w r3, r3, #1 + 8007fe8: b2db uxtb r3, r3 + 8007fea: 461a mov r2, r3 + 8007fec: 4b60 ldr r3, [pc, #384] @ (8008170 ) + 8007fee: 755a strb r2, [r3, #21] + if( crcOn == true ) + 8007ff0: f897 3030 ldrb.w r3, [r7, #48] @ 0x30 + 8007ff4: 2b00 cmp r3, #0 + 8007ff6: d003 beq.n 8008000 + SubgRf.PacketParams.Params.Gfsk.CrcLength = RADIO_CRC_2_BYTES_CCIT; + 8007ff8: 4b5d ldr r3, [pc, #372] @ (8008170 ) + 8007ffa: 22f2 movs r2, #242 @ 0xf2 + 8007ffc: 75da strb r2, [r3, #23] + 8007ffe: e002 b.n 8008006 + SubgRf.PacketParams.Params.Gfsk.CrcLength = RADIO_CRC_OFF; + 8008000: 4b5b ldr r3, [pc, #364] @ (8008170 ) + 8008002: 2201 movs r2, #1 + 8008004: 75da strb r2, [r3, #23] + SubgRf.PacketParams.Params.Gfsk.DcFree = RADIO_DC_FREEWHITENING; + 8008006: 4b5a ldr r3, [pc, #360] @ (8008170 ) + 8008008: 2201 movs r2, #1 + 800800a: 761a strb r2, [r3, #24] + RadioStandby( ); + 800800c: f000 fb39 bl 8008682 + RadioSetModem( MODEM_FSK ); + 8008010: 2000 movs r0, #0 + 8008012: f7ff fcc7 bl 80079a4 + SUBGRF_SetModulationParams( &SubgRf.ModulationParams ); + 8008016: 4857 ldr r0, [pc, #348] @ (8008174 ) + 8008018: f002 f964 bl 800a2e4 + SUBGRF_SetPacketParams( &SubgRf.PacketParams ); + 800801c: 4856 ldr r0, [pc, #344] @ (8008178 ) + 800801e: f002 fa2f bl 800a480 + SUBGRF_SetSyncWord( ( uint8_t[] ){ 0xC1, 0x94, 0xC1, 0x00, 0x00, 0x00, 0x00, 0x00 } ); + 8008022: 4a56 ldr r2, [pc, #344] @ (800817c ) + 8008024: f107 0310 add.w r3, r7, #16 + 8008028: e892 0003 ldmia.w r2, {r0, r1} + 800802c: e883 0003 stmia.w r3, {r0, r1} + 8008030: f107 0310 add.w r3, r7, #16 + 8008034: 4618 mov r0, r3 + 8008036: f001 fce8 bl 8009a0a + SUBGRF_SetWhiteningSeed( 0x01FF ); + 800803a: f240 10ff movw r0, #511 @ 0x1ff + 800803e: f001 fd33 bl 8009aa8 + break; + 8008042: e078 b.n 8008136 + SubgRf.ModulationParams.PacketType = PACKET_TYPE_LORA; + 8008044: 4b4a ldr r3, [pc, #296] @ (8008170 ) + 8008046: 2201 movs r2, #1 + 8008048: f883 2038 strb.w r2, [r3, #56] @ 0x38 + SubgRf.ModulationParams.Params.LoRa.SpreadingFactor = ( RadioLoRaSpreadingFactors_t ) datarate; + 800804c: 6a3b ldr r3, [r7, #32] + 800804e: b2da uxtb r2, r3 + 8008050: 4b47 ldr r3, [pc, #284] @ (8008170 ) + 8008052: f883 2050 strb.w r2, [r3, #80] @ 0x50 + SubgRf.ModulationParams.Params.LoRa.Bandwidth = Bandwidths[bandwidth]; + 8008056: 4a4a ldr r2, [pc, #296] @ (8008180 ) + 8008058: 687b ldr r3, [r7, #4] + 800805a: 4413 add r3, r2 + 800805c: 781a ldrb r2, [r3, #0] + 800805e: 4b44 ldr r3, [pc, #272] @ (8008170 ) + 8008060: f883 2051 strb.w r2, [r3, #81] @ 0x51 + SubgRf.ModulationParams.Params.LoRa.CodingRate= ( RadioLoRaCodingRates_t )coderate; + 8008064: 4a42 ldr r2, [pc, #264] @ (8008170 ) + 8008066: f897 3024 ldrb.w r3, [r7, #36] @ 0x24 + 800806a: f882 3052 strb.w r3, [r2, #82] @ 0x52 + if( ( ( bandwidth == 0 ) && ( ( datarate == 11 ) || ( datarate == 12 ) ) ) || + 800806e: 687b ldr r3, [r7, #4] + 8008070: 2b00 cmp r3, #0 + 8008072: d105 bne.n 8008080 + 8008074: 6a3b ldr r3, [r7, #32] + 8008076: 2b0b cmp r3, #11 + 8008078: d008 beq.n 800808c + 800807a: 6a3b ldr r3, [r7, #32] + 800807c: 2b0c cmp r3, #12 + 800807e: d005 beq.n 800808c + 8008080: 687b ldr r3, [r7, #4] + 8008082: 2b01 cmp r3, #1 + 8008084: d107 bne.n 8008096 + ( ( bandwidth == 1 ) && ( datarate == 12 ) ) ) + 8008086: 6a3b ldr r3, [r7, #32] + 8008088: 2b0c cmp r3, #12 + 800808a: d104 bne.n 8008096 + SubgRf.ModulationParams.Params.LoRa.LowDatarateOptimize = 0x01; + 800808c: 4b38 ldr r3, [pc, #224] @ (8008170 ) + 800808e: 2201 movs r2, #1 + 8008090: f883 2053 strb.w r2, [r3, #83] @ 0x53 + 8008094: e003 b.n 800809e + SubgRf.ModulationParams.Params.LoRa.LowDatarateOptimize = 0x00; + 8008096: 4b36 ldr r3, [pc, #216] @ (8008170 ) + 8008098: 2200 movs r2, #0 + 800809a: f883 2053 strb.w r2, [r3, #83] @ 0x53 + SubgRf.PacketParams.PacketType = PACKET_TYPE_LORA; + 800809e: 4b34 ldr r3, [pc, #208] @ (8008170 ) + 80080a0: 2201 movs r2, #1 + 80080a2: 739a strb r2, [r3, #14] + if( ( SubgRf.ModulationParams.Params.LoRa.SpreadingFactor == LORA_SF5 ) || + 80080a4: 4b32 ldr r3, [pc, #200] @ (8008170 ) + 80080a6: f893 3050 ldrb.w r3, [r3, #80] @ 0x50 + 80080aa: 2b05 cmp r3, #5 + 80080ac: d004 beq.n 80080b8 + ( SubgRf.ModulationParams.Params.LoRa.SpreadingFactor == LORA_SF6 ) ) + 80080ae: 4b30 ldr r3, [pc, #192] @ (8008170 ) + 80080b0: f893 3050 ldrb.w r3, [r3, #80] @ 0x50 + if( ( SubgRf.ModulationParams.Params.LoRa.SpreadingFactor == LORA_SF5 ) || + 80080b4: 2b06 cmp r3, #6 + 80080b6: d10a bne.n 80080ce + if( preambleLen < 12 ) + 80080b8: 8d3b ldrh r3, [r7, #40] @ 0x28 + 80080ba: 2b0b cmp r3, #11 + 80080bc: d803 bhi.n 80080c6 + SubgRf.PacketParams.Params.LoRa.PreambleLength = 12; + 80080be: 4b2c ldr r3, [pc, #176] @ (8008170 ) + 80080c0: 220c movs r2, #12 + 80080c2: 839a strh r2, [r3, #28] + if( preambleLen < 12 ) + 80080c4: e006 b.n 80080d4 + SubgRf.PacketParams.Params.LoRa.PreambleLength = preambleLen; + 80080c6: 4a2a ldr r2, [pc, #168] @ (8008170 ) + 80080c8: 8d3b ldrh r3, [r7, #40] @ 0x28 + 80080ca: 8393 strh r3, [r2, #28] + if( preambleLen < 12 ) + 80080cc: e002 b.n 80080d4 + SubgRf.PacketParams.Params.LoRa.PreambleLength = preambleLen; + 80080ce: 4a28 ldr r2, [pc, #160] @ (8008170 ) + 80080d0: 8d3b ldrh r3, [r7, #40] @ 0x28 + 80080d2: 8393 strh r3, [r2, #28] + SubgRf.PacketParams.Params.LoRa.HeaderType = ( RadioLoRaPacketLengthsMode_t )fixLen; + 80080d4: f897 202c ldrb.w r2, [r7, #44] @ 0x2c + 80080d8: 4b25 ldr r3, [pc, #148] @ (8008170 ) + 80080da: 779a strb r2, [r3, #30] + SubgRf.PacketParams.Params.LoRa.PayloadLength = MaxPayloadLength; + 80080dc: 4b29 ldr r3, [pc, #164] @ (8008184 ) + 80080de: 781a ldrb r2, [r3, #0] + 80080e0: 4b23 ldr r3, [pc, #140] @ (8008170 ) + 80080e2: 77da strb r2, [r3, #31] + SubgRf.PacketParams.Params.LoRa.CrcMode = ( RadioLoRaCrcModes_t )crcOn; + 80080e4: f897 2030 ldrb.w r2, [r7, #48] @ 0x30 + 80080e8: 4b21 ldr r3, [pc, #132] @ (8008170 ) + 80080ea: f883 2020 strb.w r2, [r3, #32] + SubgRf.PacketParams.Params.LoRa.InvertIQ = ( RadioLoRaIQModes_t )iqInverted; + 80080ee: f897 203c ldrb.w r2, [r7, #60] @ 0x3c + 80080f2: 4b1f ldr r3, [pc, #124] @ (8008170 ) + 80080f4: f883 2021 strb.w r2, [r3, #33] @ 0x21 + RadioStandby( ); + 80080f8: f000 fac3 bl 8008682 + RadioSetModem( MODEM_LORA ); + 80080fc: 2001 movs r0, #1 + 80080fe: f7ff fc51 bl 80079a4 + SUBGRF_SetModulationParams( &SubgRf.ModulationParams ); + 8008102: 481c ldr r0, [pc, #112] @ (8008174 ) + 8008104: f002 f8ee bl 800a2e4 + SUBGRF_SetPacketParams( &SubgRf.PacketParams ); + 8008108: 481b ldr r0, [pc, #108] @ (8008178 ) + 800810a: f002 f9b9 bl 800a480 + break; + 800810e: e012 b.n 8008136 + RadioSetModem(MODEM_SIGFOX_TX); + 8008110: 2004 movs r0, #4 + 8008112: f7ff fc47 bl 80079a4 + SubgRf.ModulationParams.PacketType = PACKET_TYPE_BPSK; + 8008116: 4b16 ldr r3, [pc, #88] @ (8008170 ) + 8008118: 2202 movs r2, #2 + 800811a: f883 2038 strb.w r2, [r3, #56] @ 0x38 + SubgRf.ModulationParams.Params.Bpsk.BitRate = datarate; + 800811e: 4a14 ldr r2, [pc, #80] @ (8008170 ) + 8008120: 6a3b ldr r3, [r7, #32] + 8008122: 6493 str r3, [r2, #72] @ 0x48 + SubgRf.ModulationParams.Params.Bpsk.ModulationShaping = MOD_SHAPING_DBPSK; + 8008124: 4b12 ldr r3, [pc, #72] @ (8008170 ) + 8008126: 2216 movs r2, #22 + 8008128: f883 204c strb.w r2, [r3, #76] @ 0x4c + SUBGRF_SetModulationParams( &SubgRf.ModulationParams ); + 800812c: 4811 ldr r0, [pc, #68] @ (8008174 ) + 800812e: f002 f8d9 bl 800a2e4 + break; + 8008132: e000 b.n 8008136 + break; + 8008134: bf00 nop + } + + SubgRf.AntSwitchPaSelect = SUBGRF_SetRfTxPower( power ); + 8008136: f997 300e ldrsb.w r3, [r7, #14] + 800813a: 4618 mov r0, r3 + 800813c: f002 fc1c bl 800a978 + 8008140: 4603 mov r3, r0 + 8008142: 461a mov r2, r3 + 8008144: 4b0a ldr r3, [pc, #40] @ (8008170 ) + 8008146: f883 2056 strb.w r2, [r3, #86] @ 0x56 + /* WORKAROUND - Trimming the output voltage power_ldo to 3.3V */ + SUBGRF_WriteRegister(REG_DRV_CTRL, 0x7 << 1); + 800814a: 210e movs r1, #14 + 800814c: f640 101f movw r0, #2335 @ 0x91f + 8008150: f002 fadc bl 800a70c + RFW_SetAntSwitch( SubgRf.AntSwitchPaSelect ); + 8008154: 4b06 ldr r3, [pc, #24] @ (8008170 ) + 8008156: f893 3056 ldrb.w r3, [r3, #86] @ 0x56 + 800815a: 4618 mov r0, r3 + 800815c: f003 f866 bl 800b22c + SubgRf.TxTimeout = timeout; + 8008160: 4a03 ldr r2, [pc, #12] @ (8008170 ) + 8008162: 6c3b ldr r3, [r7, #64] @ 0x40 + 8008164: 6053 str r3, [r2, #4] +} + 8008166: bf00 nop + 8008168: 3718 adds r7, #24 + 800816a: 46bd mov sp, r7 + 800816c: bd80 pop {r7, pc} + 800816e: bf00 nop + 8008170: 20000300 .word 0x20000300 + 8008174: 20000338 .word 0x20000338 + 8008178: 2000030e .word 0x2000030e + 800817c: 0800f0f0 .word 0x0800f0f0 + 8008180: 0800fc08 .word 0x0800fc08 + 8008184: 20000008 .word 0x20000008 + +08008188 : + +static bool RadioCheckRfFrequency( uint32_t frequency ) +{ + 8008188: b480 push {r7} + 800818a: b083 sub sp, #12 + 800818c: af00 add r7, sp, #0 + 800818e: 6078 str r0, [r7, #4] + return true; + 8008190: 2301 movs r3, #1 +} + 8008192: 4618 mov r0, r3 + 8008194: 370c adds r7, #12 + 8008196: 46bd mov sp, r7 + 8008198: bc80 pop {r7} + 800819a: 4770 bx lr + +0800819c : + +static uint32_t RadioGetLoRaBandwidthInHz( RadioLoRaBandwidths_t bw ) +{ + 800819c: b480 push {r7} + 800819e: b085 sub sp, #20 + 80081a0: af00 add r7, sp, #0 + 80081a2: 4603 mov r3, r0 + 80081a4: 71fb strb r3, [r7, #7] + uint32_t bandwidthInHz = 0; + 80081a6: 2300 movs r3, #0 + 80081a8: 60fb str r3, [r7, #12] + + switch( bw ) + 80081aa: 79fb ldrb r3, [r7, #7] + 80081ac: 2b0a cmp r3, #10 + 80081ae: d83e bhi.n 800822e + 80081b0: a201 add r2, pc, #4 @ (adr r2, 80081b8 ) + 80081b2: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 80081b6: bf00 nop + 80081b8: 080081e5 .word 0x080081e5 + 80081bc: 080081f5 .word 0x080081f5 + 80081c0: 08008205 .word 0x08008205 + 80081c4: 08008215 .word 0x08008215 + 80081c8: 0800821d .word 0x0800821d + 80081cc: 08008223 .word 0x08008223 + 80081d0: 08008229 .word 0x08008229 + 80081d4: 0800822f .word 0x0800822f + 80081d8: 080081ed .word 0x080081ed + 80081dc: 080081fd .word 0x080081fd + 80081e0: 0800820d .word 0x0800820d + { + case LORA_BW_007: + bandwidthInHz = 7812UL; + 80081e4: f641 6384 movw r3, #7812 @ 0x1e84 + 80081e8: 60fb str r3, [r7, #12] + break; + 80081ea: e020 b.n 800822e + case LORA_BW_010: + bandwidthInHz = 10417UL; + 80081ec: f642 03b1 movw r3, #10417 @ 0x28b1 + 80081f0: 60fb str r3, [r7, #12] + break; + 80081f2: e01c b.n 800822e + case LORA_BW_015: + bandwidthInHz = 15625UL; + 80081f4: f643 5309 movw r3, #15625 @ 0x3d09 + 80081f8: 60fb str r3, [r7, #12] + break; + 80081fa: e018 b.n 800822e + case LORA_BW_020: + bandwidthInHz = 20833UL; + 80081fc: f245 1361 movw r3, #20833 @ 0x5161 + 8008200: 60fb str r3, [r7, #12] + break; + 8008202: e014 b.n 800822e + case LORA_BW_031: + bandwidthInHz = 31250UL; + 8008204: f647 2312 movw r3, #31250 @ 0x7a12 + 8008208: 60fb str r3, [r7, #12] + break; + 800820a: e010 b.n 800822e + case LORA_BW_041: + bandwidthInHz = 41667UL; + 800820c: f24a 23c3 movw r3, #41667 @ 0xa2c3 + 8008210: 60fb str r3, [r7, #12] + break; + 8008212: e00c b.n 800822e + case LORA_BW_062: + bandwidthInHz = 62500UL; + 8008214: f24f 4324 movw r3, #62500 @ 0xf424 + 8008218: 60fb str r3, [r7, #12] + break; + 800821a: e008 b.n 800822e + case LORA_BW_125: + bandwidthInHz = 125000UL; + 800821c: 4b07 ldr r3, [pc, #28] @ (800823c ) + 800821e: 60fb str r3, [r7, #12] + break; + 8008220: e005 b.n 800822e + case LORA_BW_250: + bandwidthInHz = 250000UL; + 8008222: 4b07 ldr r3, [pc, #28] @ (8008240 ) + 8008224: 60fb str r3, [r7, #12] + break; + 8008226: e002 b.n 800822e + case LORA_BW_500: + bandwidthInHz = 500000UL; + 8008228: 4b06 ldr r3, [pc, #24] @ (8008244 ) + 800822a: 60fb str r3, [r7, #12] + break; + 800822c: bf00 nop + } + + return bandwidthInHz; + 800822e: 68fb ldr r3, [r7, #12] +} + 8008230: 4618 mov r0, r3 + 8008232: 3714 adds r7, #20 + 8008234: 46bd mov sp, r7 + 8008236: bc80 pop {r7} + 8008238: 4770 bx lr + 800823a: bf00 nop + 800823c: 0001e848 .word 0x0001e848 + 8008240: 0003d090 .word 0x0003d090 + 8008244: 0007a120 .word 0x0007a120 + +08008248 : + +static uint32_t RadioGetGfskTimeOnAirNumerator( uint32_t datarate, uint8_t coderate, + uint16_t preambleLen, bool fixLen, uint8_t payloadLen, + bool crcOn ) +{ + 8008248: b480 push {r7} + 800824a: b083 sub sp, #12 + 800824c: af00 add r7, sp, #0 + 800824e: 6078 str r0, [r7, #4] + 8008250: 4608 mov r0, r1 + 8008252: 4611 mov r1, r2 + 8008254: 461a mov r2, r3 + 8008256: 4603 mov r3, r0 + 8008258: 70fb strb r3, [r7, #3] + 800825a: 460b mov r3, r1 + 800825c: 803b strh r3, [r7, #0] + 800825e: 4613 mov r3, r2 + 8008260: 70bb strb r3, [r7, #2] + return ( preambleLen << 3 ) + + 8008262: 883b ldrh r3, [r7, #0] + 8008264: 00db lsls r3, r3, #3 + ( ( fixLen == false ) ? 8 : 0 ) + 24 + + 8008266: 78ba ldrb r2, [r7, #2] + 8008268: f082 0201 eor.w r2, r2, #1 + 800826c: b2d2 uxtb r2, r2 + 800826e: 2a00 cmp r2, #0 + 8008270: d001 beq.n 8008276 + 8008272: 2208 movs r2, #8 + 8008274: e000 b.n 8008278 + 8008276: 2200 movs r2, #0 + return ( preambleLen << 3 ) + + 8008278: 4413 add r3, r2 + ( ( fixLen == false ) ? 8 : 0 ) + 24 + + 800827a: f103 0218 add.w r2, r3, #24 + ( ( payloadLen + ( ( crcOn == true ) ? 2 : 0 ) ) << 3 ); + 800827e: 7c3b ldrb r3, [r7, #16] + 8008280: 7d39 ldrb r1, [r7, #20] + 8008282: 2900 cmp r1, #0 + 8008284: d001 beq.n 800828a + 8008286: 2102 movs r1, #2 + 8008288: e000 b.n 800828c + 800828a: 2100 movs r1, #0 + 800828c: 440b add r3, r1 + 800828e: 00db lsls r3, r3, #3 + ( ( fixLen == false ) ? 8 : 0 ) + 24 + + 8008290: 4413 add r3, r2 +} + 8008292: 4618 mov r0, r3 + 8008294: 370c adds r7, #12 + 8008296: 46bd mov sp, r7 + 8008298: bc80 pop {r7} + 800829a: 4770 bx lr + +0800829c : + +static uint32_t RadioGetLoRaTimeOnAirNumerator( uint32_t bandwidth, + uint32_t datarate, uint8_t coderate, + uint16_t preambleLen, bool fixLen, uint8_t payloadLen, + bool crcOn ) +{ + 800829c: b480 push {r7} + 800829e: b08b sub sp, #44 @ 0x2c + 80082a0: af00 add r7, sp, #0 + 80082a2: 60f8 str r0, [r7, #12] + 80082a4: 60b9 str r1, [r7, #8] + 80082a6: 4611 mov r1, r2 + 80082a8: 461a mov r2, r3 + 80082aa: 460b mov r3, r1 + 80082ac: 71fb strb r3, [r7, #7] + 80082ae: 4613 mov r3, r2 + 80082b0: 80bb strh r3, [r7, #4] + int32_t crDenom = coderate + 4; + 80082b2: 79fb ldrb r3, [r7, #7] + 80082b4: 3304 adds r3, #4 + 80082b6: 617b str r3, [r7, #20] + bool lowDatareOptimize = false; + 80082b8: 2300 movs r3, #0 + 80082ba: f887 3027 strb.w r3, [r7, #39] @ 0x27 + + // Ensure that the preamble length is at least 12 symbols when using SF5 or SF6 + if( ( datarate == 5 ) || ( datarate == 6 ) ) + 80082be: 68bb ldr r3, [r7, #8] + 80082c0: 2b05 cmp r3, #5 + 80082c2: d002 beq.n 80082ca + 80082c4: 68bb ldr r3, [r7, #8] + 80082c6: 2b06 cmp r3, #6 + 80082c8: d104 bne.n 80082d4 + { + if( preambleLen < 12 ) + 80082ca: 88bb ldrh r3, [r7, #4] + 80082cc: 2b0b cmp r3, #11 + 80082ce: d801 bhi.n 80082d4 + { + preambleLen = 12; + 80082d0: 230c movs r3, #12 + 80082d2: 80bb strh r3, [r7, #4] + } + } + + if( ( ( bandwidth == 0 ) && ( ( datarate == 11 ) || ( datarate == 12 ) ) ) || + 80082d4: 68fb ldr r3, [r7, #12] + 80082d6: 2b00 cmp r3, #0 + 80082d8: d105 bne.n 80082e6 + 80082da: 68bb ldr r3, [r7, #8] + 80082dc: 2b0b cmp r3, #11 + 80082de: d008 beq.n 80082f2 + 80082e0: 68bb ldr r3, [r7, #8] + 80082e2: 2b0c cmp r3, #12 + 80082e4: d005 beq.n 80082f2 + 80082e6: 68fb ldr r3, [r7, #12] + 80082e8: 2b01 cmp r3, #1 + 80082ea: d105 bne.n 80082f8 + ( ( bandwidth == 1 ) && ( datarate == 12 ) ) ) + 80082ec: 68bb ldr r3, [r7, #8] + 80082ee: 2b0c cmp r3, #12 + 80082f0: d102 bne.n 80082f8 + { + lowDatareOptimize = true; + 80082f2: 2301 movs r3, #1 + 80082f4: f887 3027 strb.w r3, [r7, #39] @ 0x27 + } + + int32_t ceilDenominator; + int32_t ceilNumerator = ( payloadLen << 3 ) + + 80082f8: f897 3034 ldrb.w r3, [r7, #52] @ 0x34 + 80082fc: 00db lsls r3, r3, #3 + ( crcOn ? 16 : 0 ) - + 80082fe: f897 2038 ldrb.w r2, [r7, #56] @ 0x38 + 8008302: 2a00 cmp r2, #0 + 8008304: d001 beq.n 800830a + 8008306: 2210 movs r2, #16 + 8008308: e000 b.n 800830c + 800830a: 2200 movs r2, #0 + int32_t ceilNumerator = ( payloadLen << 3 ) + + 800830c: 4413 add r3, r2 + 800830e: 461a mov r2, r3 + ( 4 * datarate ) + + 8008310: 68bb ldr r3, [r7, #8] + 8008312: 009b lsls r3, r3, #2 + ( crcOn ? 16 : 0 ) - + 8008314: 1ad3 subs r3, r2, r3 + ( fixLen ? 0 : 20 ); + 8008316: f897 2030 ldrb.w r2, [r7, #48] @ 0x30 + 800831a: 2a00 cmp r2, #0 + 800831c: d001 beq.n 8008322 + 800831e: 2200 movs r2, #0 + 8008320: e000 b.n 8008324 + 8008322: 2214 movs r2, #20 + ( 4 * datarate ) + + 8008324: 4413 add r3, r2 + int32_t ceilNumerator = ( payloadLen << 3 ) + + 8008326: 61fb str r3, [r7, #28] + + if( datarate <= 6 ) + 8008328: 68bb ldr r3, [r7, #8] + 800832a: 2b06 cmp r3, #6 + 800832c: d803 bhi.n 8008336 + { + ceilDenominator = 4 * datarate; + 800832e: 68bb ldr r3, [r7, #8] + 8008330: 009b lsls r3, r3, #2 + 8008332: 623b str r3, [r7, #32] + 8008334: e00e b.n 8008354 + } + else + { + ceilNumerator += 8; + 8008336: 69fb ldr r3, [r7, #28] + 8008338: 3308 adds r3, #8 + 800833a: 61fb str r3, [r7, #28] + + if( lowDatareOptimize == true ) + 800833c: f897 3027 ldrb.w r3, [r7, #39] @ 0x27 + 8008340: 2b00 cmp r3, #0 + 8008342: d004 beq.n 800834e + { + ceilDenominator = 4 * ( datarate - 2 ); + 8008344: 68bb ldr r3, [r7, #8] + 8008346: 3b02 subs r3, #2 + 8008348: 009b lsls r3, r3, #2 + 800834a: 623b str r3, [r7, #32] + 800834c: e002 b.n 8008354 + } + else + { + ceilDenominator = 4 * datarate; + 800834e: 68bb ldr r3, [r7, #8] + 8008350: 009b lsls r3, r3, #2 + 8008352: 623b str r3, [r7, #32] + } + } + + if( ceilNumerator < 0 ) + 8008354: 69fb ldr r3, [r7, #28] + 8008356: 2b00 cmp r3, #0 + 8008358: da01 bge.n 800835e + { + ceilNumerator = 0; + 800835a: 2300 movs r3, #0 + 800835c: 61fb str r3, [r7, #28] + } + + // Perform integral ceil() + int32_t intermediate = + ( ( ceilNumerator + ceilDenominator - 1 ) / ceilDenominator ) * crDenom + preambleLen + 12; + 800835e: 69fa ldr r2, [r7, #28] + 8008360: 6a3b ldr r3, [r7, #32] + 8008362: 4413 add r3, r2 + 8008364: 1e5a subs r2, r3, #1 + 8008366: 6a3b ldr r3, [r7, #32] + 8008368: fb92 f3f3 sdiv r3, r2, r3 + 800836c: 697a ldr r2, [r7, #20] + 800836e: fb03 f202 mul.w r2, r3, r2 + 8008372: 88bb ldrh r3, [r7, #4] + 8008374: 4413 add r3, r2 + int32_t intermediate = + 8008376: 330c adds r3, #12 + 8008378: 61bb str r3, [r7, #24] + + if( datarate <= 6 ) + 800837a: 68bb ldr r3, [r7, #8] + 800837c: 2b06 cmp r3, #6 + 800837e: d802 bhi.n 8008386 + { + intermediate += 2; + 8008380: 69bb ldr r3, [r7, #24] + 8008382: 3302 adds r3, #2 + 8008384: 61bb str r3, [r7, #24] + } + + return ( uint32_t )( ( 4 * intermediate + 1 ) * ( 1 << ( datarate - 2 ) ) ); + 8008386: 69bb ldr r3, [r7, #24] + 8008388: 009b lsls r3, r3, #2 + 800838a: 1c5a adds r2, r3, #1 + 800838c: 68bb ldr r3, [r7, #8] + 800838e: 3b02 subs r3, #2 + 8008390: fa02 f303 lsl.w r3, r2, r3 +} + 8008394: 4618 mov r0, r3 + 8008396: 372c adds r7, #44 @ 0x2c + 8008398: 46bd mov sp, r7 + 800839a: bc80 pop {r7} + 800839c: 4770 bx lr + ... + +080083a0 : + +static uint32_t RadioTimeOnAir( RadioModems_t modem, uint32_t bandwidth, + uint32_t datarate, uint8_t coderate, + uint16_t preambleLen, bool fixLen, uint8_t payloadLen, + bool crcOn ) +{ + 80083a0: b580 push {r7, lr} + 80083a2: b08a sub sp, #40 @ 0x28 + 80083a4: af04 add r7, sp, #16 + 80083a6: 60b9 str r1, [r7, #8] + 80083a8: 607a str r2, [r7, #4] + 80083aa: 461a mov r2, r3 + 80083ac: 4603 mov r3, r0 + 80083ae: 73fb strb r3, [r7, #15] + 80083b0: 4613 mov r3, r2 + 80083b2: 73bb strb r3, [r7, #14] + uint32_t numerator = 0; + 80083b4: 2300 movs r3, #0 + 80083b6: 617b str r3, [r7, #20] + uint32_t denominator = 1; + 80083b8: 2301 movs r3, #1 + 80083ba: 613b str r3, [r7, #16] + + switch( modem ) + 80083bc: 7bfb ldrb r3, [r7, #15] + 80083be: 2b00 cmp r3, #0 + 80083c0: d002 beq.n 80083c8 + 80083c2: 2b01 cmp r3, #1 + 80083c4: d017 beq.n 80083f6 + fixLen, payloadLen, crcOn ); + denominator = RadioGetLoRaBandwidthInHz( Bandwidths[bandwidth] ); + } + break; + default: + break; + 80083c6: e035 b.n 8008434 + numerator = 1000U * RadioGetGfskTimeOnAirNumerator( datarate, coderate, + 80083c8: f897 0024 ldrb.w r0, [r7, #36] @ 0x24 + 80083cc: 8c3a ldrh r2, [r7, #32] + 80083ce: 7bb9 ldrb r1, [r7, #14] + 80083d0: f897 302c ldrb.w r3, [r7, #44] @ 0x2c + 80083d4: 9301 str r3, [sp, #4] + 80083d6: f897 3028 ldrb.w r3, [r7, #40] @ 0x28 + 80083da: 9300 str r3, [sp, #0] + 80083dc: 4603 mov r3, r0 + 80083de: 6878 ldr r0, [r7, #4] + 80083e0: f7ff ff32 bl 8008248 + 80083e4: 4603 mov r3, r0 + 80083e6: f44f 727a mov.w r2, #1000 @ 0x3e8 + 80083ea: fb02 f303 mul.w r3, r2, r3 + 80083ee: 617b str r3, [r7, #20] + denominator = datarate; + 80083f0: 687b ldr r3, [r7, #4] + 80083f2: 613b str r3, [r7, #16] + break; + 80083f4: e01e b.n 8008434 + numerator = 1000U * RadioGetLoRaTimeOnAirNumerator( bandwidth, datarate, + 80083f6: 8c39 ldrh r1, [r7, #32] + 80083f8: 7bba ldrb r2, [r7, #14] + 80083fa: f897 302c ldrb.w r3, [r7, #44] @ 0x2c + 80083fe: 9302 str r3, [sp, #8] + 8008400: f897 3028 ldrb.w r3, [r7, #40] @ 0x28 + 8008404: 9301 str r3, [sp, #4] + 8008406: f897 3024 ldrb.w r3, [r7, #36] @ 0x24 + 800840a: 9300 str r3, [sp, #0] + 800840c: 460b mov r3, r1 + 800840e: 6879 ldr r1, [r7, #4] + 8008410: 68b8 ldr r0, [r7, #8] + 8008412: f7ff ff43 bl 800829c + 8008416: 4603 mov r3, r0 + 8008418: f44f 727a mov.w r2, #1000 @ 0x3e8 + 800841c: fb02 f303 mul.w r3, r2, r3 + 8008420: 617b str r3, [r7, #20] + denominator = RadioGetLoRaBandwidthInHz( Bandwidths[bandwidth] ); + 8008422: 4a0a ldr r2, [pc, #40] @ (800844c ) + 8008424: 68bb ldr r3, [r7, #8] + 8008426: 4413 add r3, r2 + 8008428: 781b ldrb r3, [r3, #0] + 800842a: 4618 mov r0, r3 + 800842c: f7ff feb6 bl 800819c + 8008430: 6138 str r0, [r7, #16] + break; + 8008432: bf00 nop + } + // Perform integral ceil() + return DIVC( numerator, denominator ); + 8008434: 697a ldr r2, [r7, #20] + 8008436: 693b ldr r3, [r7, #16] + 8008438: 4413 add r3, r2 + 800843a: 1e5a subs r2, r3, #1 + 800843c: 693b ldr r3, [r7, #16] + 800843e: fbb2 f3f3 udiv r3, r2, r3 +} + 8008442: 4618 mov r0, r3 + 8008444: 3718 adds r7, #24 + 8008446: 46bd mov sp, r7 + 8008448: bd80 pop {r7, pc} + 800844a: bf00 nop + 800844c: 0800fc08 .word 0x0800fc08 + +08008450 : + +static radio_status_t RadioSend( uint8_t *buffer, uint8_t size ) +{ + 8008450: b580 push {r7, lr} + 8008452: b084 sub sp, #16 + 8008454: af00 add r7, sp, #0 + 8008456: 6078 str r0, [r7, #4] + 8008458: 460b mov r3, r1 + 800845a: 70fb strb r3, [r7, #3] + SUBGRF_SetDioIrqParams( IRQ_TX_DONE | IRQ_RX_TX_TIMEOUT | IRQ_TX_DBG, + 800845c: 2300 movs r3, #0 + 800845e: 2200 movs r2, #0 + 8008460: f240 2101 movw r1, #513 @ 0x201 + 8008464: f240 2001 movw r0, #513 @ 0x201 + 8008468: f001 fda6 bl 8009fb8 + IRQ_TX_DONE | IRQ_RX_TX_TIMEOUT | IRQ_TX_DBG, + IRQ_RADIO_NONE, + IRQ_RADIO_NONE ); + + /* Set DBG pin */ + DBG_GPIO_RADIO_TX( SET ); + 800846c: f44f 5100 mov.w r1, #8192 @ 0x2000 + 8008470: 4874 ldr r0, [pc, #464] @ (8008644 ) + 8008472: f7ff fa09 bl 8007888 + + /* Set RF switch */ + SUBGRF_SetSwitch( SubgRf.AntSwitchPaSelect, RFSWITCH_TX ); + 8008476: 4b74 ldr r3, [pc, #464] @ (8008648 ) + 8008478: f893 3056 ldrb.w r3, [r3, #86] @ 0x56 + 800847c: 2101 movs r1, #1 + 800847e: 4618 mov r0, r3 + 8008480: f002 fa52 bl 800a928 + /* WORKAROUND - Modulation Quality with 500 kHz LoRaTM Bandwidth*/ + /* RegTxModulation = @address 0x0889 */ + if( ( SubgRf.Modem == MODEM_LORA ) && ( SubgRf.ModulationParams.Params.LoRa.Bandwidth == LORA_BW_500 ) ) + 8008484: 4b70 ldr r3, [pc, #448] @ (8008648 ) + 8008486: 781b ldrb r3, [r3, #0] + 8008488: 2b01 cmp r3, #1 + 800848a: d112 bne.n 80084b2 + 800848c: 4b6e ldr r3, [pc, #440] @ (8008648 ) + 800848e: f893 3051 ldrb.w r3, [r3, #81] @ 0x51 + 8008492: 2b06 cmp r3, #6 + 8008494: d10d bne.n 80084b2 + { + SUBGRF_WriteRegister( SUBGHZ_SDCFG0R, SUBGRF_ReadRegister( SUBGHZ_SDCFG0R ) & ~( 1 << 2 ) ); + 8008496: f640 0089 movw r0, #2185 @ 0x889 + 800849a: f002 f959 bl 800a750 + 800849e: 4603 mov r3, r0 + 80084a0: f023 0304 bic.w r3, r3, #4 + 80084a4: b2db uxtb r3, r3 + 80084a6: 4619 mov r1, r3 + 80084a8: f640 0089 movw r0, #2185 @ 0x889 + 80084ac: f002 f92e bl 800a70c + 80084b0: e00c b.n 80084cc + } + else + { + SUBGRF_WriteRegister( SUBGHZ_SDCFG0R, SUBGRF_ReadRegister( SUBGHZ_SDCFG0R ) | ( 1 << 2 ) ); + 80084b2: f640 0089 movw r0, #2185 @ 0x889 + 80084b6: f002 f94b bl 800a750 + 80084ba: 4603 mov r3, r0 + 80084bc: f043 0304 orr.w r3, r3, #4 + 80084c0: b2db uxtb r3, r3 + 80084c2: 4619 mov r1, r3 + 80084c4: f640 0089 movw r0, #2185 @ 0x889 + 80084c8: f002 f920 bl 800a70c + } + else +#endif /* RADIO_LR_FHSS_IS_ON == 1 */ + { + /* WORKAROUND END */ + switch( SubgRf.Modem ) + 80084cc: 4b5e ldr r3, [pc, #376] @ (8008648 ) + 80084ce: 781b ldrb r3, [r3, #0] + 80084d0: 2b04 cmp r3, #4 + 80084d2: f200 80a7 bhi.w 8008624 + 80084d6: a201 add r2, pc, #4 @ (adr r2, 80084dc ) + 80084d8: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 80084dc: 0800850b .word 0x0800850b + 80084e0: 080084f1 .word 0x080084f1 + 80084e4: 0800850b .word 0x0800850b + 80084e8: 0800856d .word 0x0800856d + 80084ec: 0800858d .word 0x0800858d + { + case MODEM_LORA: + { + SubgRf.PacketParams.Params.LoRa.PayloadLength = size; + 80084f0: 4a55 ldr r2, [pc, #340] @ (8008648 ) + 80084f2: 78fb ldrb r3, [r7, #3] + 80084f4: 77d3 strb r3, [r2, #31] + SUBGRF_SetPacketParams( &SubgRf.PacketParams ); + 80084f6: 4855 ldr r0, [pc, #340] @ (800864c ) + 80084f8: f001 ffc2 bl 800a480 + SUBGRF_SendPayload( buffer, size, 0 ); + 80084fc: 78fb ldrb r3, [r7, #3] + 80084fe: 2200 movs r2, #0 + 8008500: 4619 mov r1, r3 + 8008502: 6878 ldr r0, [r7, #4] + 8008504: f001 fa6e bl 80099e4 + break; + 8008508: e08d b.n 8008626 + } + case MODEM_MSK: + case MODEM_FSK: + { + if ( 1UL == RFW_Is_Init( ) ) + 800850a: f002 fe7b bl 800b204 + 800850e: 4603 mov r3, r0 + 8008510: 2b01 cmp r3, #1 + 8008512: d11e bne.n 8008552 + { + uint8_t outsize; + if ( 0UL == RFW_TransmitInit( buffer,size, &outsize ) ) + 8008514: f107 020d add.w r2, r7, #13 + 8008518: 78fb ldrb r3, [r7, #3] + 800851a: 4619 mov r1, r3 + 800851c: 6878 ldr r0, [r7, #4] + 800851e: f002 fe95 bl 800b24c + 8008522: 4603 mov r3, r0 + 8008524: 2b00 cmp r3, #0 + 8008526: d10c bne.n 8008542 + { + SubgRf.PacketParams.Params.Gfsk.PayloadLength = outsize; + 8008528: 7b7a ldrb r2, [r7, #13] + 800852a: 4b47 ldr r3, [pc, #284] @ (8008648 ) + 800852c: 759a strb r2, [r3, #22] + SUBGRF_SetPacketParams( &SubgRf.PacketParams ); + 800852e: 4847 ldr r0, [pc, #284] @ (800864c ) + 8008530: f001 ffa6 bl 800a480 + SUBGRF_SendPayload( buffer, outsize, 0 ); + 8008534: 7b7b ldrb r3, [r7, #13] + 8008536: 2200 movs r2, #0 + 8008538: 4619 mov r1, r3 + 800853a: 6878 ldr r0, [r7, #4] + 800853c: f001 fa52 bl 80099e4 + { + SubgRf.PacketParams.Params.Gfsk.PayloadLength = size; + SUBGRF_SetPacketParams( &SubgRf.PacketParams ); + SUBGRF_SendPayload( buffer, size, 0 ); + } + break; + 8008540: e071 b.n 8008626 + MW_LOG( TS_ON, VLEVEL_M, "RadioSend Oversize\r\n" ); + 8008542: 4b43 ldr r3, [pc, #268] @ (8008650 ) + 8008544: 2201 movs r2, #1 + 8008546: 2100 movs r1, #0 + 8008548: 2002 movs r0, #2 + 800854a: f005 fd6d bl 800e028 + return RADIO_STATUS_ERROR; + 800854e: 2303 movs r3, #3 + 8008550: e073 b.n 800863a + SubgRf.PacketParams.Params.Gfsk.PayloadLength = size; + 8008552: 4a3d ldr r2, [pc, #244] @ (8008648 ) + 8008554: 78fb ldrb r3, [r7, #3] + 8008556: 7593 strb r3, [r2, #22] + SUBGRF_SetPacketParams( &SubgRf.PacketParams ); + 8008558: 483c ldr r0, [pc, #240] @ (800864c ) + 800855a: f001 ff91 bl 800a480 + SUBGRF_SendPayload( buffer, size, 0 ); + 800855e: 78fb ldrb r3, [r7, #3] + 8008560: 2200 movs r2, #0 + 8008562: 4619 mov r1, r3 + 8008564: 6878 ldr r0, [r7, #4] + 8008566: f001 fa3d bl 80099e4 + break; + 800856a: e05c b.n 8008626 + } + case MODEM_BPSK: + { + SubgRf.PacketParams.PacketType = PACKET_TYPE_BPSK; + 800856c: 4b36 ldr r3, [pc, #216] @ (8008648 ) + 800856e: 2202 movs r2, #2 + 8008570: 739a strb r2, [r3, #14] + SubgRf.PacketParams.Params.Bpsk.PayloadLength = size; + 8008572: 4a35 ldr r2, [pc, #212] @ (8008648 ) + 8008574: 78fb ldrb r3, [r7, #3] + 8008576: 7693 strb r3, [r2, #26] + SUBGRF_SetPacketParams( &SubgRf.PacketParams ); + 8008578: 4834 ldr r0, [pc, #208] @ (800864c ) + 800857a: f001 ff81 bl 800a480 + SUBGRF_SendPayload( buffer, size, 0 ); + 800857e: 78fb ldrb r3, [r7, #3] + 8008580: 2200 movs r2, #0 + 8008582: 4619 mov r1, r3 + 8008584: 6878 ldr r0, [r7, #4] + 8008586: f001 fa2d bl 80099e4 + break; + 800858a: e04c b.n 8008626 + case MODEM_SIGFOX_TX: + { + /* from bpsk to dbpsk */ + /* first 1 bit duplicated */ + /* RadioBuffer is 1 bytes more */ + payload_integration( RadioBuffer, buffer, size ); + 800858c: 78fb ldrb r3, [r7, #3] + 800858e: 461a mov r2, r3 + 8008590: 6879 ldr r1, [r7, #4] + 8008592: 4830 ldr r0, [pc, #192] @ (8008654 ) + 8008594: f000 fcfa bl 8008f8c + + SubgRf.PacketParams.PacketType = PACKET_TYPE_BPSK; + 8008598: 4b2b ldr r3, [pc, #172] @ (8008648 ) + 800859a: 2202 movs r2, #2 + 800859c: 739a strb r2, [r3, #14] + SubgRf.PacketParams.Params.Bpsk.PayloadLength = size + 1; + 800859e: 78fb ldrb r3, [r7, #3] + 80085a0: 3301 adds r3, #1 + 80085a2: b2da uxtb r2, r3 + 80085a4: 4b28 ldr r3, [pc, #160] @ (8008648 ) + 80085a6: 769a strb r2, [r3, #26] + SUBGRF_SetPacketParams( &SubgRf.PacketParams ); + 80085a8: 4828 ldr r0, [pc, #160] @ (800864c ) + 80085aa: f001 ff69 bl 800a480 + + RadioWrite( SUBGHZ_RAM_RAMPUPL, 0 ); // clean start-up LSB + 80085ae: 2100 movs r1, #0 + 80085b0: 20f1 movs r0, #241 @ 0xf1 + 80085b2: f000 f973 bl 800889c + RadioWrite( SUBGHZ_RAM_RAMPUPH, 0 ); // clean start-up MSB + 80085b6: 2100 movs r1, #0 + 80085b8: 20f0 movs r0, #240 @ 0xf0 + 80085ba: f000 f96f bl 800889c + if( SubgRf.ModulationParams.Params.Bpsk.BitRate == 100 ) + 80085be: 4b22 ldr r3, [pc, #136] @ (8008648 ) + 80085c0: 6c9b ldr r3, [r3, #72] @ 0x48 + 80085c2: 2b64 cmp r3, #100 @ 0x64 + 80085c4: d108 bne.n 80085d8 + { + RadioWrite( SUBGHZ_RAM_RAMPDNL, 0x70 ); // clean end of frame LSB + 80085c6: 2170 movs r1, #112 @ 0x70 + 80085c8: 20f3 movs r0, #243 @ 0xf3 + 80085ca: f000 f967 bl 800889c + RadioWrite( SUBGHZ_RAM_RAMPDNH, 0x1D ); // clean end of frame MSB + 80085ce: 211d movs r1, #29 + 80085d0: 20f2 movs r0, #242 @ 0xf2 + 80085d2: f000 f963 bl 800889c + 80085d6: e007 b.n 80085e8 + } + else // 600 bps + { + RadioWrite( SUBGHZ_RAM_RAMPDNL, 0xE1 ); // clean end of frame LSB + 80085d8: 21e1 movs r1, #225 @ 0xe1 + 80085da: 20f3 movs r0, #243 @ 0xf3 + 80085dc: f000 f95e bl 800889c + RadioWrite( SUBGHZ_RAM_RAMPDNH, 0x04 ); // clean end of frame MSB + 80085e0: 2104 movs r1, #4 + 80085e2: 20f2 movs r0, #242 @ 0xf2 + 80085e4: f000 f95a bl 800889c + } + + uint16_t bitNum = ( size * 8 ) + 2; + 80085e8: 78fb ldrb r3, [r7, #3] + 80085ea: b29b uxth r3, r3 + 80085ec: 00db lsls r3, r3, #3 + 80085ee: b29b uxth r3, r3 + 80085f0: 3302 adds r3, #2 + 80085f2: 81fb strh r3, [r7, #14] + RadioWrite( SUBGHZ_RAM_FRAMELIMH, ( bitNum >> 8 ) & 0x00FF ); // limit frame + 80085f4: 89fb ldrh r3, [r7, #14] + 80085f6: 0a1b lsrs r3, r3, #8 + 80085f8: b29b uxth r3, r3 + 80085fa: b2db uxtb r3, r3 + 80085fc: 4619 mov r1, r3 + 80085fe: 20f4 movs r0, #244 @ 0xf4 + 8008600: f000 f94c bl 800889c + RadioWrite( SUBGHZ_RAM_FRAMELIML, bitNum & 0x00FF ); // limit frame + 8008604: 89fb ldrh r3, [r7, #14] + 8008606: b2db uxtb r3, r3 + 8008608: 4619 mov r1, r3 + 800860a: 20f5 movs r0, #245 @ 0xf5 + 800860c: f000 f946 bl 800889c + SUBGRF_SendPayload( RadioBuffer, size + 1, 0xFFFFFF ); + 8008610: 78fb ldrb r3, [r7, #3] + 8008612: 3301 adds r3, #1 + 8008614: b2db uxtb r3, r3 + 8008616: f06f 427f mvn.w r2, #4278190080 @ 0xff000000 + 800861a: 4619 mov r1, r3 + 800861c: 480d ldr r0, [pc, #52] @ (8008654 ) + 800861e: f001 f9e1 bl 80099e4 + break; + 8008622: e000 b.n 8008626 + } +#endif /*RADIO_SIGFOX_ENABLE == 1*/ + default: + break; + 8008624: bf00 nop + } + + TimerSetValue( &TxTimeoutTimer, SubgRf.TxTimeout ); + 8008626: 4b08 ldr r3, [pc, #32] @ (8008648 ) + 8008628: 685b ldr r3, [r3, #4] + 800862a: 4619 mov r1, r3 + 800862c: 480a ldr r0, [pc, #40] @ (8008658 ) + 800862e: f005 fb73 bl 800dd18 + TimerStart( &TxTimeoutTimer ); + 8008632: 4809 ldr r0, [pc, #36] @ (8008658 ) + 8008634: f005 fa92 bl 800db5c + } + + return RADIO_STATUS_OK; + 8008638: 2300 movs r3, #0 +} + 800863a: 4618 mov r0, r3 + 800863c: 3710 adds r7, #16 + 800863e: 46bd mov sp, r7 + 8008640: bd80 pop {r7, pc} + 8008642: bf00 nop + 8008644: 48000400 .word 0x48000400 + 8008648: 20000300 .word 0x20000300 + 800864c: 2000030e .word 0x2000030e + 8008650: 0800f0f8 .word 0x0800f0f8 + 8008654: 200001fc .word 0x200001fc + 8008658: 2000035c .word 0x2000035c + +0800865c : + +static void RadioSleep( void ) +{ + 800865c: b580 push {r7, lr} + 800865e: b082 sub sp, #8 + 8008660: af00 add r7, sp, #0 + SleepParams_t params = { 0 }; + 8008662: 2300 movs r3, #0 + 8008664: 713b strb r3, [r7, #4] + + params.Fields.WarmStart = 1; + 8008666: 793b ldrb r3, [r7, #4] + 8008668: f043 0304 orr.w r3, r3, #4 + 800866c: 713b strb r3, [r7, #4] + SUBGRF_SetSleep( params ); + 800866e: 7938 ldrb r0, [r7, #4] + 8008670: f001 fa94 bl 8009b9c + + RADIO_DELAY_MS( 2 ); + 8008674: 2002 movs r0, #2 + 8008676: f7f8 fafb bl 8000c70 +} + 800867a: bf00 nop + 800867c: 3708 adds r7, #8 + 800867e: 46bd mov sp, r7 + 8008680: bd80 pop {r7, pc} + +08008682 : + +static void RadioStandby( void ) +{ + 8008682: b580 push {r7, lr} + 8008684: af00 add r7, sp, #0 + SUBGRF_SetStandby( STDBY_RC ); + 8008686: 2000 movs r0, #0 + 8008688: f001 fabc bl 8009c04 +} + 800868c: bf00 nop + 800868e: bd80 pop {r7, pc} + +08008690 : + +static void RadioRx( uint32_t timeout ) +{ + 8008690: b580 push {r7, lr} + 8008692: b082 sub sp, #8 + 8008694: af00 add r7, sp, #0 + 8008696: 6078 str r0, [r7, #4] + if( SubgRf.lr_fhss.is_lr_fhss_on == true ) + { + //return LORAMAC_RADIO_STATUS_ERROR; + } +#endif /* RADIO_LR_FHSS_IS_ON == 1 */ + if( 1UL == RFW_Is_Init( ) ) + 8008698: f002 fdb4 bl 800b204 + 800869c: 4603 mov r3, r0 + 800869e: 2b01 cmp r3, #1 + 80086a0: d102 bne.n 80086a8 + { + RFW_ReceiveInit( ); + 80086a2: f002 fe59 bl 800b358 + 80086a6: e007 b.n 80086b8 + } + else + { + SUBGRF_SetDioIrqParams( IRQ_RX_DONE | IRQ_RX_TX_TIMEOUT | IRQ_CRC_ERROR | IRQ_HEADER_ERROR | IRQ_RX_DBG, + 80086a8: 2300 movs r3, #0 + 80086aa: 2200 movs r2, #0 + 80086ac: f240 2162 movw r1, #610 @ 0x262 + 80086b0: f240 2062 movw r0, #610 @ 0x262 + 80086b4: f001 fc80 bl 8009fb8 + IRQ_RX_DONE | IRQ_RX_TX_TIMEOUT | IRQ_CRC_ERROR | IRQ_HEADER_ERROR | IRQ_RX_DBG, + IRQ_RADIO_NONE, + IRQ_RADIO_NONE ); + } + + if( timeout != 0 ) + 80086b8: 687b ldr r3, [r7, #4] + 80086ba: 2b00 cmp r3, #0 + 80086bc: d006 beq.n 80086cc + { + TimerSetValue( &RxTimeoutTimer, timeout ); + 80086be: 6879 ldr r1, [r7, #4] + 80086c0: 4813 ldr r0, [pc, #76] @ (8008710 ) + 80086c2: f005 fb29 bl 800dd18 + TimerStart( &RxTimeoutTimer ); + 80086c6: 4812 ldr r0, [pc, #72] @ (8008710 ) + 80086c8: f005 fa48 bl 800db5c + } + /* switch off RxDcPreambleDetect See STM32WL Errata: RadioSetRxDutyCycle*/ + SubgRf.RxDcPreambleDetectTimeout = 0; + 80086cc: 4b11 ldr r3, [pc, #68] @ (8008714 ) + 80086ce: 2200 movs r2, #0 + 80086d0: 659a str r2, [r3, #88] @ 0x58 + /* Set DBG pin */ + DBG_GPIO_RADIO_RX( SET ); + 80086d2: f44f 5180 mov.w r1, #4096 @ 0x1000 + 80086d6: 4810 ldr r0, [pc, #64] @ (8008718 ) + 80086d8: f7ff f8d6 bl 8007888 + /* RF switch configuration */ + SUBGRF_SetSwitch( SubgRf.AntSwitchPaSelect, RFSWITCH_RX ); + 80086dc: 4b0d ldr r3, [pc, #52] @ (8008714 ) + 80086de: f893 3056 ldrb.w r3, [r3, #86] @ 0x56 + 80086e2: 2100 movs r1, #0 + 80086e4: 4618 mov r0, r3 + 80086e6: f002 f91f bl 800a928 + + if( SubgRf.RxContinuous == true ) + 80086ea: 4b0a ldr r3, [pc, #40] @ (8008714 ) + 80086ec: 785b ldrb r3, [r3, #1] + 80086ee: 2b00 cmp r3, #0 + 80086f0: d004 beq.n 80086fc + { + SUBGRF_SetRx( 0xFFFFFF ); // Rx Continuous + 80086f2: f06f 407f mvn.w r0, #4278190080 @ 0xff000000 + 80086f6: f001 fac1 bl 8009c7c + } + else + { + SUBGRF_SetRx( SubgRf.RxTimeout << 6 ); + } +} + 80086fa: e005 b.n 8008708 + SUBGRF_SetRx( SubgRf.RxTimeout << 6 ); + 80086fc: 4b05 ldr r3, [pc, #20] @ (8008714 ) + 80086fe: 689b ldr r3, [r3, #8] + 8008700: 019b lsls r3, r3, #6 + 8008702: 4618 mov r0, r3 + 8008704: f001 faba bl 8009c7c +} + 8008708: bf00 nop + 800870a: 3708 adds r7, #8 + 800870c: 46bd mov sp, r7 + 800870e: bd80 pop {r7, pc} + 8008710: 20000374 .word 0x20000374 + 8008714: 20000300 .word 0x20000300 + 8008718: 48000400 .word 0x48000400 + +0800871c : + +static void RadioRxBoosted( uint32_t timeout ) +{ + 800871c: b580 push {r7, lr} + 800871e: b082 sub sp, #8 + 8008720: af00 add r7, sp, #0 + 8008722: 6078 str r0, [r7, #4] + if( SubgRf.lr_fhss.is_lr_fhss_on == true ) + { + //return LORAMAC_RADIO_STATUS_ERROR; + } +#endif /* RADIO_LR_FHSS_IS_ON == 1 */ + if( 1UL == RFW_Is_Init() ) + 8008724: f002 fd6e bl 800b204 + 8008728: 4603 mov r3, r0 + 800872a: 2b01 cmp r3, #1 + 800872c: d102 bne.n 8008734 + { + RFW_ReceiveInit(); + 800872e: f002 fe13 bl 800b358 + 8008732: e007 b.n 8008744 + } + else + { + SUBGRF_SetDioIrqParams( IRQ_RX_DONE | IRQ_RX_TX_TIMEOUT | IRQ_CRC_ERROR | IRQ_HEADER_ERROR | IRQ_RX_DBG, + 8008734: 2300 movs r3, #0 + 8008736: 2200 movs r2, #0 + 8008738: f240 2162 movw r1, #610 @ 0x262 + 800873c: f240 2062 movw r0, #610 @ 0x262 + 8008740: f001 fc3a bl 8009fb8 + IRQ_RX_DONE | IRQ_RX_TX_TIMEOUT | IRQ_CRC_ERROR | IRQ_HEADER_ERROR | IRQ_RX_DBG, + IRQ_RADIO_NONE, + IRQ_RADIO_NONE ); + } + if( timeout != 0 ) + 8008744: 687b ldr r3, [r7, #4] + 8008746: 2b00 cmp r3, #0 + 8008748: d006 beq.n 8008758 + { + TimerSetValue( &RxTimeoutTimer, timeout ); + 800874a: 6879 ldr r1, [r7, #4] + 800874c: 4813 ldr r0, [pc, #76] @ (800879c ) + 800874e: f005 fae3 bl 800dd18 + TimerStart( &RxTimeoutTimer ); + 8008752: 4812 ldr r0, [pc, #72] @ (800879c ) + 8008754: f005 fa02 bl 800db5c + } + /* switch off RxDcPreambleDetect See STM32WL Errata: RadioSetRxDutyCycle*/ + SubgRf.RxDcPreambleDetectTimeout = 0; + 8008758: 4b11 ldr r3, [pc, #68] @ (80087a0 ) + 800875a: 2200 movs r2, #0 + 800875c: 659a str r2, [r3, #88] @ 0x58 + /* Set DBG pin */ + DBG_GPIO_RADIO_RX( SET ); + 800875e: f44f 5180 mov.w r1, #4096 @ 0x1000 + 8008762: 4810 ldr r0, [pc, #64] @ (80087a4 ) + 8008764: f7ff f890 bl 8007888 + /* RF switch configuration */ + SUBGRF_SetSwitch( SubgRf.AntSwitchPaSelect, RFSWITCH_RX ); + 8008768: 4b0d ldr r3, [pc, #52] @ (80087a0 ) + 800876a: f893 3056 ldrb.w r3, [r3, #86] @ 0x56 + 800876e: 2100 movs r1, #0 + 8008770: 4618 mov r0, r3 + 8008772: f002 f8d9 bl 800a928 + + if( SubgRf.RxContinuous == true ) + 8008776: 4b0a ldr r3, [pc, #40] @ (80087a0 ) + 8008778: 785b ldrb r3, [r3, #1] + 800877a: 2b00 cmp r3, #0 + 800877c: d004 beq.n 8008788 + { + SUBGRF_SetRxBoosted( 0xFFFFFF ); // Rx Continuous + 800877e: f06f 407f mvn.w r0, #4278190080 @ 0xff000000 + 8008782: f001 fa9b bl 8009cbc + } + else + { + SUBGRF_SetRxBoosted( SubgRf.RxTimeout << 6 ); + } +} + 8008786: e005 b.n 8008794 + SUBGRF_SetRxBoosted( SubgRf.RxTimeout << 6 ); + 8008788: 4b05 ldr r3, [pc, #20] @ (80087a0 ) + 800878a: 689b ldr r3, [r3, #8] + 800878c: 019b lsls r3, r3, #6 + 800878e: 4618 mov r0, r3 + 8008790: f001 fa94 bl 8009cbc +} + 8008794: bf00 nop + 8008796: 3708 adds r7, #8 + 8008798: 46bd mov sp, r7 + 800879a: bd80 pop {r7, pc} + 800879c: 20000374 .word 0x20000374 + 80087a0: 20000300 .word 0x20000300 + 80087a4: 48000400 .word 0x48000400 + +080087a8 : + +static void RadioSetRxDutyCycle( uint32_t rxTime, uint32_t sleepTime ) +{ + 80087a8: b580 push {r7, lr} + 80087aa: b082 sub sp, #8 + 80087ac: af00 add r7, sp, #0 + 80087ae: 6078 str r0, [r7, #4] + 80087b0: 6039 str r1, [r7, #0] + /*See STM32WL Errata: RadioSetRxDutyCycle*/ + SubgRf.RxDcPreambleDetectTimeout = 2 * rxTime + sleepTime; + 80087b2: 687b ldr r3, [r7, #4] + 80087b4: 005a lsls r2, r3, #1 + 80087b6: 683b ldr r3, [r7, #0] + 80087b8: 4413 add r3, r2 + 80087ba: 4a0c ldr r2, [pc, #48] @ (80087ec ) + 80087bc: 6593 str r3, [r2, #88] @ 0x58 + /*Enable also the IRQ_PREAMBLE_DETECTED*/ + SUBGRF_SetDioIrqParams( IRQ_RADIO_ALL, IRQ_RADIO_ALL, IRQ_RADIO_NONE, IRQ_RADIO_NONE ); + 80087be: 2300 movs r3, #0 + 80087c0: 2200 movs r2, #0 + 80087c2: f64f 71ff movw r1, #65535 @ 0xffff + 80087c6: f64f 70ff movw r0, #65535 @ 0xffff + 80087ca: f001 fbf5 bl 8009fb8 + /* RF switch configuration */ + SUBGRF_SetSwitch( SubgRf.AntSwitchPaSelect, RFSWITCH_RX ); + 80087ce: 4b07 ldr r3, [pc, #28] @ (80087ec ) + 80087d0: f893 3056 ldrb.w r3, [r3, #86] @ 0x56 + 80087d4: 2100 movs r1, #0 + 80087d6: 4618 mov r0, r3 + 80087d8: f002 f8a6 bl 800a928 + /* Start Rx DutyCycle*/ + SUBGRF_SetRxDutyCycle( rxTime, sleepTime ); + 80087dc: 6839 ldr r1, [r7, #0] + 80087de: 6878 ldr r0, [r7, #4] + 80087e0: f001 fa90 bl 8009d04 +} + 80087e4: bf00 nop + 80087e6: 3708 adds r7, #8 + 80087e8: 46bd mov sp, r7 + 80087ea: bd80 pop {r7, pc} + 80087ec: 20000300 .word 0x20000300 + +080087f0 : + +static void RadioStartCad( void ) +{ + 80087f0: b580 push {r7, lr} + 80087f2: af00 add r7, sp, #0 + /* RF switch configuration */ + SUBGRF_SetSwitch( SubgRf.AntSwitchPaSelect, RFSWITCH_RX ); + 80087f4: 4b09 ldr r3, [pc, #36] @ (800881c ) + 80087f6: f893 3056 ldrb.w r3, [r3, #86] @ 0x56 + 80087fa: 2100 movs r1, #0 + 80087fc: 4618 mov r0, r3 + 80087fe: f002 f893 bl 800a928 + + SUBGRF_SetDioIrqParams( IRQ_CAD_CLEAR | IRQ_CAD_DETECTED, + 8008802: 2300 movs r3, #0 + 8008804: 2200 movs r2, #0 + 8008806: f44f 71c0 mov.w r1, #384 @ 0x180 + 800880a: f44f 70c0 mov.w r0, #384 @ 0x180 + 800880e: f001 fbd3 bl 8009fb8 + IRQ_CAD_CLEAR | IRQ_CAD_DETECTED, + IRQ_RADIO_NONE, + IRQ_RADIO_NONE ); + SUBGRF_SetCad( ); + 8008812: f001 faa3 bl 8009d5c +} + 8008816: bf00 nop + 8008818: bd80 pop {r7, pc} + 800881a: bf00 nop + 800881c: 20000300 .word 0x20000300 + +08008820 : + +static void RadioSetTxContinuousWave( uint32_t freq, int8_t power, uint16_t time ) +{ + 8008820: b580 push {r7, lr} + 8008822: b084 sub sp, #16 + 8008824: af00 add r7, sp, #0 + 8008826: 6078 str r0, [r7, #4] + 8008828: 460b mov r3, r1 + 800882a: 70fb strb r3, [r7, #3] + 800882c: 4613 mov r3, r2 + 800882e: 803b strh r3, [r7, #0] + if( SubgRf.lr_fhss.is_lr_fhss_on == true ) + { + //return LORAMAC_RADIO_STATUS_ERROR; + } +#endif /* RADIO_LR_FHSS_IS_ON == 1 */ + uint32_t timeout = ( uint32_t )time * 1000; + 8008830: 883b ldrh r3, [r7, #0] + 8008832: f44f 727a mov.w r2, #1000 @ 0x3e8 + 8008836: fb02 f303 mul.w r3, r2, r3 + 800883a: 60fb str r3, [r7, #12] + uint8_t antswitchpow; + + SUBGRF_SetRfFrequency( freq ); + 800883c: 6878 ldr r0, [r7, #4] + 800883e: f001 fc17 bl 800a070 + + antswitchpow = SUBGRF_SetRfTxPower( power ); + 8008842: f997 3003 ldrsb.w r3, [r7, #3] + 8008846: 4618 mov r0, r3 + 8008848: f002 f896 bl 800a978 + 800884c: 4603 mov r3, r0 + 800884e: 72fb strb r3, [r7, #11] + + /* WORKAROUND - Trimming the output voltage power_ldo to 3.3V */ + SUBGRF_WriteRegister(REG_DRV_CTRL, 0x7 << 1); + 8008850: 210e movs r1, #14 + 8008852: f640 101f movw r0, #2335 @ 0x91f + 8008856: f001 ff59 bl 800a70c + + /* Set RF switch */ + SUBGRF_SetSwitch( antswitchpow, RFSWITCH_TX ); + 800885a: 7afb ldrb r3, [r7, #11] + 800885c: 2101 movs r1, #1 + 800885e: 4618 mov r0, r3 + 8008860: f002 f862 bl 800a928 + + SUBGRF_SetTxContinuousWave( ); + 8008864: f001 fa88 bl 8009d78 + + TimerSetValue( &TxTimeoutTimer, timeout ); + 8008868: 68f9 ldr r1, [r7, #12] + 800886a: 4805 ldr r0, [pc, #20] @ (8008880 ) + 800886c: f005 fa54 bl 800dd18 + TimerStart( &TxTimeoutTimer ); + 8008870: 4803 ldr r0, [pc, #12] @ (8008880 ) + 8008872: f005 f973 bl 800db5c +} + 8008876: bf00 nop + 8008878: 3710 adds r7, #16 + 800887a: 46bd mov sp, r7 + 800887c: bd80 pop {r7, pc} + 800887e: bf00 nop + 8008880: 2000035c .word 0x2000035c + +08008884 : + +static int16_t RadioRssi( RadioModems_t modem ) +{ + 8008884: b580 push {r7, lr} + 8008886: b082 sub sp, #8 + 8008888: af00 add r7, sp, #0 + 800888a: 4603 mov r3, r0 + 800888c: 71fb strb r3, [r7, #7] + return SUBGRF_GetRssiInst( ); + 800888e: f001 feaa bl 800a5e6 + 8008892: 4603 mov r3, r0 +} + 8008894: 4618 mov r0, r3 + 8008896: 3708 adds r7, #8 + 8008898: 46bd mov sp, r7 + 800889a: bd80 pop {r7, pc} + +0800889c : + +static void RadioWrite( uint16_t addr, uint8_t data ) +{ + 800889c: b580 push {r7, lr} + 800889e: b082 sub sp, #8 + 80088a0: af00 add r7, sp, #0 + 80088a2: 4603 mov r3, r0 + 80088a4: 460a mov r2, r1 + 80088a6: 80fb strh r3, [r7, #6] + 80088a8: 4613 mov r3, r2 + 80088aa: 717b strb r3, [r7, #5] + SUBGRF_WriteRegister( addr, data ); + 80088ac: 797a ldrb r2, [r7, #5] + 80088ae: 88fb ldrh r3, [r7, #6] + 80088b0: 4611 mov r1, r2 + 80088b2: 4618 mov r0, r3 + 80088b4: f001 ff2a bl 800a70c +} + 80088b8: bf00 nop + 80088ba: 3708 adds r7, #8 + 80088bc: 46bd mov sp, r7 + 80088be: bd80 pop {r7, pc} + +080088c0 : + +static uint8_t RadioRead( uint16_t addr ) +{ + 80088c0: b580 push {r7, lr} + 80088c2: b082 sub sp, #8 + 80088c4: af00 add r7, sp, #0 + 80088c6: 4603 mov r3, r0 + 80088c8: 80fb strh r3, [r7, #6] + return SUBGRF_ReadRegister( addr ); + 80088ca: 88fb ldrh r3, [r7, #6] + 80088cc: 4618 mov r0, r3 + 80088ce: f001 ff3f bl 800a750 + 80088d2: 4603 mov r3, r0 +} + 80088d4: 4618 mov r0, r3 + 80088d6: 3708 adds r7, #8 + 80088d8: 46bd mov sp, r7 + 80088da: bd80 pop {r7, pc} + +080088dc : + +static void RadioWriteRegisters( uint16_t addr, uint8_t *buffer, uint8_t size ) +{ + 80088dc: b580 push {r7, lr} + 80088de: b082 sub sp, #8 + 80088e0: af00 add r7, sp, #0 + 80088e2: 4603 mov r3, r0 + 80088e4: 6039 str r1, [r7, #0] + 80088e6: 80fb strh r3, [r7, #6] + 80088e8: 4613 mov r3, r2 + 80088ea: 717b strb r3, [r7, #5] + SUBGRF_WriteRegisters( addr, buffer, size ); + 80088ec: 797b ldrb r3, [r7, #5] + 80088ee: b29a uxth r2, r3 + 80088f0: 88fb ldrh r3, [r7, #6] + 80088f2: 6839 ldr r1, [r7, #0] + 80088f4: 4618 mov r0, r3 + 80088f6: f001 ff4b bl 800a790 +} + 80088fa: bf00 nop + 80088fc: 3708 adds r7, #8 + 80088fe: 46bd mov sp, r7 + 8008900: bd80 pop {r7, pc} + +08008902 : + +static void RadioReadRegisters( uint16_t addr, uint8_t *buffer, uint8_t size ) +{ + 8008902: b580 push {r7, lr} + 8008904: b082 sub sp, #8 + 8008906: af00 add r7, sp, #0 + 8008908: 4603 mov r3, r0 + 800890a: 6039 str r1, [r7, #0] + 800890c: 80fb strh r3, [r7, #6] + 800890e: 4613 mov r3, r2 + 8008910: 717b strb r3, [r7, #5] + SUBGRF_ReadRegisters( addr, buffer, size ); + 8008912: 797b ldrb r3, [r7, #5] + 8008914: b29a uxth r2, r3 + 8008916: 88fb ldrh r3, [r7, #6] + 8008918: 6839 ldr r1, [r7, #0] + 800891a: 4618 mov r0, r3 + 800891c: f001 ff5a bl 800a7d4 +} + 8008920: bf00 nop + 8008922: 3708 adds r7, #8 + 8008924: 46bd mov sp, r7 + 8008926: bd80 pop {r7, pc} + +08008928 : + +static void RadioSetMaxPayloadLength( RadioModems_t modem, uint8_t max ) +{ + 8008928: b580 push {r7, lr} + 800892a: b082 sub sp, #8 + 800892c: af00 add r7, sp, #0 + 800892e: 4603 mov r3, r0 + 8008930: 460a mov r2, r1 + 8008932: 71fb strb r3, [r7, #7] + 8008934: 4613 mov r3, r2 + 8008936: 71bb strb r3, [r7, #6] + if( modem == MODEM_LORA ) + 8008938: 79fb ldrb r3, [r7, #7] + 800893a: 2b01 cmp r3, #1 + 800893c: d10a bne.n 8008954 + { + SubgRf.PacketParams.Params.LoRa.PayloadLength = MaxPayloadLength = max; + 800893e: 4a0e ldr r2, [pc, #56] @ (8008978 ) + 8008940: 79bb ldrb r3, [r7, #6] + 8008942: 7013 strb r3, [r2, #0] + 8008944: 4b0c ldr r3, [pc, #48] @ (8008978 ) + 8008946: 781a ldrb r2, [r3, #0] + 8008948: 4b0c ldr r3, [pc, #48] @ (800897c ) + 800894a: 77da strb r2, [r3, #31] + SUBGRF_SetPacketParams( &SubgRf.PacketParams ); + 800894c: 480c ldr r0, [pc, #48] @ (8008980 ) + 800894e: f001 fd97 bl 800a480 + { + SubgRf.PacketParams.Params.Gfsk.PayloadLength = MaxPayloadLength = max; + SUBGRF_SetPacketParams( &SubgRf.PacketParams ); + } + } +} + 8008952: e00d b.n 8008970 + if( SubgRf.PacketParams.Params.Gfsk.HeaderType == RADIO_PACKET_VARIABLE_LENGTH ) + 8008954: 4b09 ldr r3, [pc, #36] @ (800897c ) + 8008956: 7d5b ldrb r3, [r3, #21] + 8008958: 2b01 cmp r3, #1 + 800895a: d109 bne.n 8008970 + SubgRf.PacketParams.Params.Gfsk.PayloadLength = MaxPayloadLength = max; + 800895c: 4a06 ldr r2, [pc, #24] @ (8008978 ) + 800895e: 79bb ldrb r3, [r7, #6] + 8008960: 7013 strb r3, [r2, #0] + 8008962: 4b05 ldr r3, [pc, #20] @ (8008978 ) + 8008964: 781a ldrb r2, [r3, #0] + 8008966: 4b05 ldr r3, [pc, #20] @ (800897c ) + 8008968: 759a strb r2, [r3, #22] + SUBGRF_SetPacketParams( &SubgRf.PacketParams ); + 800896a: 4805 ldr r0, [pc, #20] @ (8008980 ) + 800896c: f001 fd88 bl 800a480 +} + 8008970: bf00 nop + 8008972: 3708 adds r7, #8 + 8008974: 46bd mov sp, r7 + 8008976: bd80 pop {r7, pc} + 8008978: 20000008 .word 0x20000008 + 800897c: 20000300 .word 0x20000300 + 8008980: 2000030e .word 0x2000030e + +08008984 : + +static void RadioSetPublicNetwork( bool enable ) +{ + 8008984: b580 push {r7, lr} + 8008986: b082 sub sp, #8 + 8008988: af00 add r7, sp, #0 + 800898a: 4603 mov r3, r0 + 800898c: 71fb strb r3, [r7, #7] + SubgRf.PublicNetwork.Current = SubgRf.PublicNetwork.Previous = enable; + 800898e: 4a13 ldr r2, [pc, #76] @ (80089dc ) + 8008990: 79fb ldrb r3, [r7, #7] + 8008992: 7313 strb r3, [r2, #12] + 8008994: 4b11 ldr r3, [pc, #68] @ (80089dc ) + 8008996: 7b1a ldrb r2, [r3, #12] + 8008998: 4b10 ldr r3, [pc, #64] @ (80089dc ) + 800899a: 735a strb r2, [r3, #13] + + RadioSetModem( MODEM_LORA ); + 800899c: 2001 movs r0, #1 + 800899e: f7ff f801 bl 80079a4 + if( enable == true ) + 80089a2: 79fb ldrb r3, [r7, #7] + 80089a4: 2b00 cmp r3, #0 + 80089a6: d00a beq.n 80089be + { + // Change LoRa modem SyncWord + SUBGRF_WriteRegister( REG_LR_SYNCWORD, ( LORA_MAC_PUBLIC_SYNCWORD >> 8 ) & 0xFF ); + 80089a8: 2134 movs r1, #52 @ 0x34 + 80089aa: f44f 60e8 mov.w r0, #1856 @ 0x740 + 80089ae: f001 fead bl 800a70c + SUBGRF_WriteRegister( REG_LR_SYNCWORD + 1, LORA_MAC_PUBLIC_SYNCWORD & 0xFF ); + 80089b2: 2144 movs r1, #68 @ 0x44 + 80089b4: f240 7041 movw r0, #1857 @ 0x741 + 80089b8: f001 fea8 bl 800a70c + { + // Change LoRa modem SyncWord + SUBGRF_WriteRegister( REG_LR_SYNCWORD, ( LORA_MAC_PRIVATE_SYNCWORD >> 8 ) & 0xFF ); + SUBGRF_WriteRegister( REG_LR_SYNCWORD + 1, LORA_MAC_PRIVATE_SYNCWORD & 0xFF ); + } +} + 80089bc: e009 b.n 80089d2 + SUBGRF_WriteRegister( REG_LR_SYNCWORD, ( LORA_MAC_PRIVATE_SYNCWORD >> 8 ) & 0xFF ); + 80089be: 2114 movs r1, #20 + 80089c0: f44f 60e8 mov.w r0, #1856 @ 0x740 + 80089c4: f001 fea2 bl 800a70c + SUBGRF_WriteRegister( REG_LR_SYNCWORD + 1, LORA_MAC_PRIVATE_SYNCWORD & 0xFF ); + 80089c8: 2124 movs r1, #36 @ 0x24 + 80089ca: f240 7041 movw r0, #1857 @ 0x741 + 80089ce: f001 fe9d bl 800a70c +} + 80089d2: bf00 nop + 80089d4: 3708 adds r7, #8 + 80089d6: 46bd mov sp, r7 + 80089d8: bd80 pop {r7, pc} + 80089da: bf00 nop + 80089dc: 20000300 .word 0x20000300 + +080089e0 : + +static uint32_t RadioGetWakeupTime( void ) +{ + 80089e0: b580 push {r7, lr} + 80089e2: af00 add r7, sp, #0 + return SUBGRF_GetRadioWakeUpTime() + RADIO_WAKEUP_TIME; + 80089e4: f001 fffc bl 800a9e0 + 80089e8: 4603 mov r3, r0 + 80089ea: 3303 adds r3, #3 +} + 80089ec: 4618 mov r0, r3 + 80089ee: bd80 pop {r7, pc} + +080089f0 : + +static void RadioOnTxTimeoutIrq( void *context ) +{ + 80089f0: b580 push {r7, lr} + 80089f2: b082 sub sp, #8 + 80089f4: af00 add r7, sp, #0 + 80089f6: 6078 str r0, [r7, #4] + RADIO_TX_TIMEOUT_PROCESS(); + 80089f8: f000 f80e bl 8008a18 +} + 80089fc: bf00 nop + 80089fe: 3708 adds r7, #8 + 8008a00: 46bd mov sp, r7 + 8008a02: bd80 pop {r7, pc} + +08008a04 : + +static void RadioOnRxTimeoutIrq( void *context ) +{ + 8008a04: b580 push {r7, lr} + 8008a06: b082 sub sp, #8 + 8008a08: af00 add r7, sp, #0 + 8008a0a: 6078 str r0, [r7, #4] + RADIO_RX_TIMEOUT_PROCESS(); + 8008a0c: f000 f81e bl 8008a4c +} + 8008a10: bf00 nop + 8008a12: 3708 adds r7, #8 + 8008a14: 46bd mov sp, r7 + 8008a16: bd80 pop {r7, pc} + +08008a18 : + +static void RadioOnTxTimeoutProcess( void ) +{ + 8008a18: b580 push {r7, lr} + 8008a1a: af00 add r7, sp, #0 + DBG_GPIO_RADIO_TX( RST ); + 8008a1c: f44f 5100 mov.w r1, #8192 @ 0x2000 + 8008a20: 4808 ldr r0, [pc, #32] @ (8008a44 ) + 8008a22: f7fe ff3e bl 80078a2 + + if( ( RadioEvents != NULL ) && ( RadioEvents->TxTimeout != NULL ) ) + 8008a26: 4b08 ldr r3, [pc, #32] @ (8008a48 ) + 8008a28: 681b ldr r3, [r3, #0] + 8008a2a: 2b00 cmp r3, #0 + 8008a2c: d008 beq.n 8008a40 + 8008a2e: 4b06 ldr r3, [pc, #24] @ (8008a48 ) + 8008a30: 681b ldr r3, [r3, #0] + 8008a32: 685b ldr r3, [r3, #4] + 8008a34: 2b00 cmp r3, #0 + 8008a36: d003 beq.n 8008a40 + { + RadioEvents->TxTimeout( ); + 8008a38: 4b03 ldr r3, [pc, #12] @ (8008a48 ) + 8008a3a: 681b ldr r3, [r3, #0] + 8008a3c: 685b ldr r3, [r3, #4] + 8008a3e: 4798 blx r3 + } +} + 8008a40: bf00 nop + 8008a42: bd80 pop {r7, pc} + 8008a44: 48000400 .word 0x48000400 + 8008a48: 200002fc .word 0x200002fc + +08008a4c : + +static void RadioOnRxTimeoutProcess( void ) +{ + 8008a4c: b580 push {r7, lr} + 8008a4e: af00 add r7, sp, #0 + DBG_GPIO_RADIO_RX( RST ); + 8008a50: f44f 5180 mov.w r1, #4096 @ 0x1000 + 8008a54: 4808 ldr r0, [pc, #32] @ (8008a78 ) + 8008a56: f7fe ff24 bl 80078a2 + + if( ( RadioEvents != NULL ) && ( RadioEvents->RxTimeout != NULL ) ) + 8008a5a: 4b08 ldr r3, [pc, #32] @ (8008a7c ) + 8008a5c: 681b ldr r3, [r3, #0] + 8008a5e: 2b00 cmp r3, #0 + 8008a60: d008 beq.n 8008a74 + 8008a62: 4b06 ldr r3, [pc, #24] @ (8008a7c ) + 8008a64: 681b ldr r3, [r3, #0] + 8008a66: 68db ldr r3, [r3, #12] + 8008a68: 2b00 cmp r3, #0 + 8008a6a: d003 beq.n 8008a74 + { + RadioEvents->RxTimeout( ); + 8008a6c: 4b03 ldr r3, [pc, #12] @ (8008a7c ) + 8008a6e: 681b ldr r3, [r3, #0] + 8008a70: 68db ldr r3, [r3, #12] + 8008a72: 4798 blx r3 + } +} + 8008a74: bf00 nop + 8008a76: bd80 pop {r7, pc} + 8008a78: 48000400 .word 0x48000400 + 8008a7c: 200002fc .word 0x200002fc + +08008a80 : + +static void RadioOnDioIrq( RadioIrqMasks_t radioIrq ) +{ + 8008a80: b580 push {r7, lr} + 8008a82: b082 sub sp, #8 + 8008a84: af00 add r7, sp, #0 + 8008a86: 4603 mov r3, r0 + 8008a88: 80fb strh r3, [r7, #6] + SubgRf.RadioIrq = radioIrq; + 8008a8a: 4a05 ldr r2, [pc, #20] @ (8008aa0 ) + 8008a8c: 88fb ldrh r3, [r7, #6] + 8008a8e: f8a2 3054 strh.w r3, [r2, #84] @ 0x54 + + RADIO_IRQ_PROCESS(); + 8008a92: f000 f807 bl 8008aa4 +} + 8008a96: bf00 nop + 8008a98: 3708 adds r7, #8 + 8008a9a: 46bd mov sp, r7 + 8008a9c: bd80 pop {r7, pc} + 8008a9e: bf00 nop + 8008aa0: 20000300 .word 0x20000300 + +08008aa4 : + +static void RadioIrqProcess( void ) +{ + 8008aa4: b5b0 push {r4, r5, r7, lr} + 8008aa6: b082 sub sp, #8 + 8008aa8: af00 add r7, sp, #0 + uint8_t size = 0; + 8008aaa: 2300 movs r3, #0 + 8008aac: 71fb strb r3, [r7, #7] + int32_t cfo = 0; + 8008aae: 2300 movs r3, #0 + 8008ab0: 603b str r3, [r7, #0] + + switch( SubgRf.RadioIrq ) + 8008ab2: 4bb2 ldr r3, [pc, #712] @ (8008d7c ) + 8008ab4: f8b3 3054 ldrh.w r3, [r3, #84] @ 0x54 + 8008ab8: f5b3 7f00 cmp.w r3, #512 @ 0x200 + 8008abc: f000 8117 beq.w 8008cee + 8008ac0: f5b3 7f00 cmp.w r3, #512 @ 0x200 + 8008ac4: f300 81fe bgt.w 8008ec4 + 8008ac8: f5b3 7f80 cmp.w r3, #256 @ 0x100 + 8008acc: f000 80fb beq.w 8008cc6 + 8008ad0: f5b3 7f80 cmp.w r3, #256 @ 0x100 + 8008ad4: f300 81f6 bgt.w 8008ec4 + 8008ad8: 2b80 cmp r3, #128 @ 0x80 + 8008ada: f000 80e0 beq.w 8008c9e + 8008ade: 2b80 cmp r3, #128 @ 0x80 + 8008ae0: f300 81f0 bgt.w 8008ec4 + 8008ae4: 2b20 cmp r3, #32 + 8008ae6: dc49 bgt.n 8008b7c + 8008ae8: 2b00 cmp r3, #0 + 8008aea: f340 81eb ble.w 8008ec4 + 8008aee: 3b01 subs r3, #1 + 8008af0: 2b1f cmp r3, #31 + 8008af2: f200 81e7 bhi.w 8008ec4 + 8008af6: a201 add r2, pc, #4 @ (adr r2, 8008afc ) + 8008af8: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 8008afc: 08008b85 .word 0x08008b85 + 8008b00: 08008bc9 .word 0x08008bc9 + 8008b04: 08008ec5 .word 0x08008ec5 + 8008b08: 08008da1 .word 0x08008da1 + 8008b0c: 08008ec5 .word 0x08008ec5 + 8008b10: 08008ec5 .word 0x08008ec5 + 8008b14: 08008ec5 .word 0x08008ec5 + 8008b18: 08008e1d .word 0x08008e1d + 8008b1c: 08008ec5 .word 0x08008ec5 + 8008b20: 08008ec5 .word 0x08008ec5 + 8008b24: 08008ec5 .word 0x08008ec5 + 8008b28: 08008ec5 .word 0x08008ec5 + 8008b2c: 08008ec5 .word 0x08008ec5 + 8008b30: 08008ec5 .word 0x08008ec5 + 8008b34: 08008ec5 .word 0x08008ec5 + 8008b38: 08008e39 .word 0x08008e39 + 8008b3c: 08008ec5 .word 0x08008ec5 + 8008b40: 08008ec5 .word 0x08008ec5 + 8008b44: 08008ec5 .word 0x08008ec5 + 8008b48: 08008ec5 .word 0x08008ec5 + 8008b4c: 08008ec5 .word 0x08008ec5 + 8008b50: 08008ec5 .word 0x08008ec5 + 8008b54: 08008ec5 .word 0x08008ec5 + 8008b58: 08008ec5 .word 0x08008ec5 + 8008b5c: 08008ec5 .word 0x08008ec5 + 8008b60: 08008ec5 .word 0x08008ec5 + 8008b64: 08008ec5 .word 0x08008ec5 + 8008b68: 08008ec5 .word 0x08008ec5 + 8008b6c: 08008ec5 .word 0x08008ec5 + 8008b70: 08008ec5 .word 0x08008ec5 + 8008b74: 08008ec5 .word 0x08008ec5 + 8008b78: 08008e47 .word 0x08008e47 + 8008b7c: 2b40 cmp r3, #64 @ 0x40 + 8008b7e: f000 8183 beq.w 8008e88 + MW_LOG( TS_ON, VLEVEL_M, "HOP\r\n" ); + break; + } +#endif /* RADIO_LR_FHSS_IS_ON == 1 */ + default: + break; + 8008b82: e19f b.n 8008ec4 + DBG_GPIO_RADIO_TX( RST ); + 8008b84: f44f 5100 mov.w r1, #8192 @ 0x2000 + 8008b88: 487d ldr r0, [pc, #500] @ (8008d80 ) + 8008b8a: f7fe fe8a bl 80078a2 + TimerStop( &TxTimeoutTimer ); + 8008b8e: 487d ldr r0, [pc, #500] @ (8008d84 ) + 8008b90: f005 f852 bl 800dc38 + SUBGRF_SetStandby( STDBY_RC ); + 8008b94: 2000 movs r0, #0 + 8008b96: f001 f835 bl 8009c04 + if( RFW_Is_LongPacketModeEnabled() == 1 ) + 8008b9a: f002 fb3d bl 800b218 + 8008b9e: 4603 mov r3, r0 + 8008ba0: 2b01 cmp r3, #1 + 8008ba2: d101 bne.n 8008ba8 + RFW_DeInit_TxLongPacket( ); + 8008ba4: f002 fbf4 bl 800b390 + if( ( RadioEvents != NULL ) && ( RadioEvents->TxDone != NULL ) ) + 8008ba8: 4b77 ldr r3, [pc, #476] @ (8008d88 ) + 8008baa: 681b ldr r3, [r3, #0] + 8008bac: 2b00 cmp r3, #0 + 8008bae: f000 818b beq.w 8008ec8 + 8008bb2: 4b75 ldr r3, [pc, #468] @ (8008d88 ) + 8008bb4: 681b ldr r3, [r3, #0] + 8008bb6: 681b ldr r3, [r3, #0] + 8008bb8: 2b00 cmp r3, #0 + 8008bba: f000 8185 beq.w 8008ec8 + RadioEvents->TxDone( ); + 8008bbe: 4b72 ldr r3, [pc, #456] @ (8008d88 ) + 8008bc0: 681b ldr r3, [r3, #0] + 8008bc2: 681b ldr r3, [r3, #0] + 8008bc4: 4798 blx r3 + break; + 8008bc6: e17f b.n 8008ec8 + DBG_GPIO_RADIO_RX( RST ); + 8008bc8: f44f 5180 mov.w r1, #4096 @ 0x1000 + 8008bcc: 486c ldr r0, [pc, #432] @ (8008d80 ) + 8008bce: f7fe fe68 bl 80078a2 + TimerStop( &RxTimeoutTimer ); + 8008bd2: 486e ldr r0, [pc, #440] @ (8008d8c ) + 8008bd4: f005 f830 bl 800dc38 + if( SubgRf.RxContinuous == false ) + 8008bd8: 4b68 ldr r3, [pc, #416] @ (8008d7c ) + 8008bda: 785b ldrb r3, [r3, #1] + 8008bdc: f083 0301 eor.w r3, r3, #1 + 8008be0: b2db uxtb r3, r3 + 8008be2: 2b00 cmp r3, #0 + 8008be4: d014 beq.n 8008c10 + SUBGRF_SetStandby( STDBY_RC ); + 8008be6: 2000 movs r0, #0 + 8008be8: f001 f80c bl 8009c04 + SUBGRF_WriteRegister( SUBGHZ_RTCCTLR, 0x00 ); + 8008bec: 2100 movs r1, #0 + 8008bee: f640 1002 movw r0, #2306 @ 0x902 + 8008bf2: f001 fd8b bl 800a70c + SUBGRF_WriteRegister( SUBGHZ_EVENTMASKR, SUBGRF_ReadRegister( SUBGHZ_EVENTMASKR ) | ( 1 << 1 ) ); + 8008bf6: f640 1044 movw r0, #2372 @ 0x944 + 8008bfa: f001 fda9 bl 800a750 + 8008bfe: 4603 mov r3, r0 + 8008c00: f043 0302 orr.w r3, r3, #2 + 8008c04: b2db uxtb r3, r3 + 8008c06: 4619 mov r1, r3 + 8008c08: f640 1044 movw r0, #2372 @ 0x944 + 8008c0c: f001 fd7e bl 800a70c + SUBGRF_GetPayload( RadioBuffer, &size, 255 ); + 8008c10: 1dfb adds r3, r7, #7 + 8008c12: 22ff movs r2, #255 @ 0xff + 8008c14: 4619 mov r1, r3 + 8008c16: 485e ldr r0, [pc, #376] @ (8008d90 ) + 8008c18: f000 fec2 bl 80099a0 + SUBGRF_GetPacketStatus( &( SubgRf.PacketStatus ) ); + 8008c1c: 485d ldr r0, [pc, #372] @ (8008d94 ) + 8008c1e: f001 fd23 bl 800a668 + if( ( RadioEvents != NULL ) && ( RadioEvents->RxDone != NULL ) ) + 8008c22: 4b59 ldr r3, [pc, #356] @ (8008d88 ) + 8008c24: 681b ldr r3, [r3, #0] + 8008c26: 2b00 cmp r3, #0 + 8008c28: f000 8150 beq.w 8008ecc + 8008c2c: 4b56 ldr r3, [pc, #344] @ (8008d88 ) + 8008c2e: 681b ldr r3, [r3, #0] + 8008c30: 689b ldr r3, [r3, #8] + 8008c32: 2b00 cmp r3, #0 + 8008c34: f000 814a beq.w 8008ecc + switch( SubgRf.PacketStatus.packetType ) + 8008c38: 4b50 ldr r3, [pc, #320] @ (8008d7c ) + 8008c3a: f893 3024 ldrb.w r3, [r3, #36] @ 0x24 + 8008c3e: 2b01 cmp r3, #1 + 8008c40: d10e bne.n 8008c60 + RadioEvents->RxDone( RadioBuffer, size, SubgRf.PacketStatus.Params.LoRa.RssiPkt, + 8008c42: 4b51 ldr r3, [pc, #324] @ (8008d88 ) + 8008c44: 681b ldr r3, [r3, #0] + 8008c46: 689c ldr r4, [r3, #8] + 8008c48: 79fb ldrb r3, [r7, #7] + 8008c4a: 4619 mov r1, r3 + 8008c4c: 4b4b ldr r3, [pc, #300] @ (8008d7c ) + 8008c4e: f993 3030 ldrsb.w r3, [r3, #48] @ 0x30 + 8008c52: 461a mov r2, r3 + 8008c54: 4b49 ldr r3, [pc, #292] @ (8008d7c ) + 8008c56: f993 3031 ldrsb.w r3, [r3, #49] @ 0x31 + 8008c5a: 484d ldr r0, [pc, #308] @ (8008d90 ) + 8008c5c: 47a0 blx r4 + break; + 8008c5e: e01d b.n 8008c9c + SUBGRF_GetCFO( SubgRf.ModulationParams.Params.Gfsk.BitRate, &cfo ); + 8008c60: 4b46 ldr r3, [pc, #280] @ (8008d7c ) + 8008c62: 6bdb ldr r3, [r3, #60] @ 0x3c + 8008c64: 463a mov r2, r7 + 8008c66: 4611 mov r1, r2 + 8008c68: 4618 mov r0, r3 + 8008c6a: f001 ffab bl 800abc4 + RadioEvents->RxDone( RadioBuffer, size, SubgRf.PacketStatus.Params.Gfsk.RssiAvg, ( int8_t ) DIVR( cfo, 1000 ) ); + 8008c6e: 4b46 ldr r3, [pc, #280] @ (8008d88 ) + 8008c70: 681b ldr r3, [r3, #0] + 8008c72: 689c ldr r4, [r3, #8] + 8008c74: 79fb ldrb r3, [r7, #7] + 8008c76: 4619 mov r1, r3 + 8008c78: 4b40 ldr r3, [pc, #256] @ (8008d7c ) + 8008c7a: f993 3029 ldrsb.w r3, [r3, #41] @ 0x29 + 8008c7e: 4618 mov r0, r3 + 8008c80: 683b ldr r3, [r7, #0] + 8008c82: f503 73fa add.w r3, r3, #500 @ 0x1f4 + 8008c86: 4a44 ldr r2, [pc, #272] @ (8008d98 ) + 8008c88: fb82 5203 smull r5, r2, r2, r3 + 8008c8c: 1192 asrs r2, r2, #6 + 8008c8e: 17db asrs r3, r3, #31 + 8008c90: 1ad3 subs r3, r2, r3 + 8008c92: b25b sxtb r3, r3 + 8008c94: 4602 mov r2, r0 + 8008c96: 483e ldr r0, [pc, #248] @ (8008d90 ) + 8008c98: 47a0 blx r4 + break; + 8008c9a: bf00 nop + break; + 8008c9c: e116 b.n 8008ecc + SUBGRF_SetStandby( STDBY_RC ); + 8008c9e: 2000 movs r0, #0 + 8008ca0: f000 ffb0 bl 8009c04 + if( ( RadioEvents != NULL ) && ( RadioEvents->CadDone != NULL ) ) + 8008ca4: 4b38 ldr r3, [pc, #224] @ (8008d88 ) + 8008ca6: 681b ldr r3, [r3, #0] + 8008ca8: 2b00 cmp r3, #0 + 8008caa: f000 8111 beq.w 8008ed0 + 8008cae: 4b36 ldr r3, [pc, #216] @ (8008d88 ) + 8008cb0: 681b ldr r3, [r3, #0] + 8008cb2: 699b ldr r3, [r3, #24] + 8008cb4: 2b00 cmp r3, #0 + 8008cb6: f000 810b beq.w 8008ed0 + RadioEvents->CadDone( false ); + 8008cba: 4b33 ldr r3, [pc, #204] @ (8008d88 ) + 8008cbc: 681b ldr r3, [r3, #0] + 8008cbe: 699b ldr r3, [r3, #24] + 8008cc0: 2000 movs r0, #0 + 8008cc2: 4798 blx r3 + break; + 8008cc4: e104 b.n 8008ed0 + SUBGRF_SetStandby( STDBY_RC ); + 8008cc6: 2000 movs r0, #0 + 8008cc8: f000 ff9c bl 8009c04 + if( ( RadioEvents != NULL ) && ( RadioEvents->CadDone != NULL ) ) + 8008ccc: 4b2e ldr r3, [pc, #184] @ (8008d88 ) + 8008cce: 681b ldr r3, [r3, #0] + 8008cd0: 2b00 cmp r3, #0 + 8008cd2: f000 80ff beq.w 8008ed4 + 8008cd6: 4b2c ldr r3, [pc, #176] @ (8008d88 ) + 8008cd8: 681b ldr r3, [r3, #0] + 8008cda: 699b ldr r3, [r3, #24] + 8008cdc: 2b00 cmp r3, #0 + 8008cde: f000 80f9 beq.w 8008ed4 + RadioEvents->CadDone( true ); + 8008ce2: 4b29 ldr r3, [pc, #164] @ (8008d88 ) + 8008ce4: 681b ldr r3, [r3, #0] + 8008ce6: 699b ldr r3, [r3, #24] + 8008ce8: 2001 movs r0, #1 + 8008cea: 4798 blx r3 + break; + 8008cec: e0f2 b.n 8008ed4 + MW_LOG( TS_ON, VLEVEL_M, "IRQ_RX_TX_TIMEOUT\r\n" ); + 8008cee: 4b2b ldr r3, [pc, #172] @ (8008d9c ) + 8008cf0: 2201 movs r2, #1 + 8008cf2: 2100 movs r1, #0 + 8008cf4: 2002 movs r0, #2 + 8008cf6: f005 f997 bl 800e028 + if( SUBGRF_GetOperatingMode( ) == MODE_TX ) + 8008cfa: f000 fe37 bl 800996c + 8008cfe: 4603 mov r3, r0 + 8008d00: 2b04 cmp r3, #4 + 8008d02: d11a bne.n 8008d3a + DBG_GPIO_RADIO_TX( RST ); + 8008d04: f44f 5100 mov.w r1, #8192 @ 0x2000 + 8008d08: 481d ldr r0, [pc, #116] @ (8008d80 ) + 8008d0a: f7fe fdca bl 80078a2 + TimerStop( &TxTimeoutTimer ); + 8008d0e: 481d ldr r0, [pc, #116] @ (8008d84 ) + 8008d10: f004 ff92 bl 800dc38 + SUBGRF_SetStandby( STDBY_RC ); + 8008d14: 2000 movs r0, #0 + 8008d16: f000 ff75 bl 8009c04 + if( ( RadioEvents != NULL ) && ( RadioEvents->TxTimeout != NULL ) ) + 8008d1a: 4b1b ldr r3, [pc, #108] @ (8008d88 ) + 8008d1c: 681b ldr r3, [r3, #0] + 8008d1e: 2b00 cmp r3, #0 + 8008d20: f000 80da beq.w 8008ed8 + 8008d24: 4b18 ldr r3, [pc, #96] @ (8008d88 ) + 8008d26: 681b ldr r3, [r3, #0] + 8008d28: 685b ldr r3, [r3, #4] + 8008d2a: 2b00 cmp r3, #0 + 8008d2c: f000 80d4 beq.w 8008ed8 + RadioEvents->TxTimeout( ); + 8008d30: 4b15 ldr r3, [pc, #84] @ (8008d88 ) + 8008d32: 681b ldr r3, [r3, #0] + 8008d34: 685b ldr r3, [r3, #4] + 8008d36: 4798 blx r3 + break; + 8008d38: e0ce b.n 8008ed8 + else if( SUBGRF_GetOperatingMode( ) == MODE_RX ) + 8008d3a: f000 fe17 bl 800996c + 8008d3e: 4603 mov r3, r0 + 8008d40: 2b05 cmp r3, #5 + 8008d42: f040 80c9 bne.w 8008ed8 + DBG_GPIO_RADIO_RX( RST ); + 8008d46: f44f 5180 mov.w r1, #4096 @ 0x1000 + 8008d4a: 480d ldr r0, [pc, #52] @ (8008d80 ) + 8008d4c: f7fe fda9 bl 80078a2 + TimerStop( &RxTimeoutTimer ); + 8008d50: 480e ldr r0, [pc, #56] @ (8008d8c ) + 8008d52: f004 ff71 bl 800dc38 + SUBGRF_SetStandby( STDBY_RC ); + 8008d56: 2000 movs r0, #0 + 8008d58: f000 ff54 bl 8009c04 + if( ( RadioEvents != NULL ) && ( RadioEvents->RxTimeout != NULL ) ) + 8008d5c: 4b0a ldr r3, [pc, #40] @ (8008d88 ) + 8008d5e: 681b ldr r3, [r3, #0] + 8008d60: 2b00 cmp r3, #0 + 8008d62: f000 80b9 beq.w 8008ed8 + 8008d66: 4b08 ldr r3, [pc, #32] @ (8008d88 ) + 8008d68: 681b ldr r3, [r3, #0] + 8008d6a: 68db ldr r3, [r3, #12] + 8008d6c: 2b00 cmp r3, #0 + 8008d6e: f000 80b3 beq.w 8008ed8 + RadioEvents->RxTimeout( ); + 8008d72: 4b05 ldr r3, [pc, #20] @ (8008d88 ) + 8008d74: 681b ldr r3, [r3, #0] + 8008d76: 68db ldr r3, [r3, #12] + 8008d78: 4798 blx r3 + break; + 8008d7a: e0ad b.n 8008ed8 + 8008d7c: 20000300 .word 0x20000300 + 8008d80: 48000400 .word 0x48000400 + 8008d84: 2000035c .word 0x2000035c + 8008d88: 200002fc .word 0x200002fc + 8008d8c: 20000374 .word 0x20000374 + 8008d90: 200001fc .word 0x200001fc + 8008d94: 20000324 .word 0x20000324 + 8008d98: 10624dd3 .word 0x10624dd3 + 8008d9c: 0800f110 .word 0x0800f110 + MW_LOG( TS_ON, VLEVEL_M, "PRE OK\r\n" ); + 8008da0: 4b54 ldr r3, [pc, #336] @ (8008ef4 ) + 8008da2: 2201 movs r2, #1 + 8008da4: 2100 movs r1, #0 + 8008da6: 2002 movs r0, #2 + 8008da8: f005 f93e bl 800e028 + if( SubgRf.RxDcPreambleDetectTimeout != 0 ) + 8008dac: 4b52 ldr r3, [pc, #328] @ (8008ef8 ) + 8008dae: 6d9b ldr r3, [r3, #88] @ 0x58 + 8008db0: 2b00 cmp r3, #0 + 8008db2: f000 8093 beq.w 8008edc + Radio.Write( SUBGHZ_RTCPRDR2, ( SubgRf.RxDcPreambleDetectTimeout >> 16 ) & 0xFF ); /*Update Radio RTC Period MSB*/ + 8008db6: 4a51 ldr r2, [pc, #324] @ (8008efc ) + 8008db8: 4b4f ldr r3, [pc, #316] @ (8008ef8 ) + 8008dba: 6d9b ldr r3, [r3, #88] @ 0x58 + 8008dbc: 0c1b lsrs r3, r3, #16 + 8008dbe: b2db uxtb r3, r3 + 8008dc0: 4619 mov r1, r3 + 8008dc2: f640 1003 movw r0, #2307 @ 0x903 + 8008dc6: 4790 blx r2 + Radio.Write( SUBGHZ_RTCPRDR1, ( SubgRf.RxDcPreambleDetectTimeout >> 8 ) & 0xFF ); /*Update Radio RTC Period MidByte*/ + 8008dc8: 4a4c ldr r2, [pc, #304] @ (8008efc ) + 8008dca: 4b4b ldr r3, [pc, #300] @ (8008ef8 ) + 8008dcc: 6d9b ldr r3, [r3, #88] @ 0x58 + 8008dce: 0a1b lsrs r3, r3, #8 + 8008dd0: b2db uxtb r3, r3 + 8008dd2: 4619 mov r1, r3 + 8008dd4: f640 1004 movw r0, #2308 @ 0x904 + 8008dd8: 4790 blx r2 + Radio.Write( SUBGHZ_RTCPRDR0, ( SubgRf.RxDcPreambleDetectTimeout ) & 0xFF ); /*Update Radio RTC Period lsb*/ + 8008dda: 4a48 ldr r2, [pc, #288] @ (8008efc ) + 8008ddc: 4b46 ldr r3, [pc, #280] @ (8008ef8 ) + 8008dde: 6d9b ldr r3, [r3, #88] @ 0x58 + 8008de0: b2db uxtb r3, r3 + 8008de2: 4619 mov r1, r3 + 8008de4: f640 1005 movw r0, #2309 @ 0x905 + 8008de8: 4790 blx r2 + Radio.Write( SUBGHZ_RTCCTLR, Radio.Read( SUBGHZ_RTCCTLR ) | 0x1 ); /*restart Radio RTC*/ + 8008dea: 4c44 ldr r4, [pc, #272] @ (8008efc ) + 8008dec: 4b44 ldr r3, [pc, #272] @ (8008f00 ) + 8008dee: f640 1002 movw r0, #2306 @ 0x902 + 8008df2: 4798 blx r3 + 8008df4: 4603 mov r3, r0 + 8008df6: f043 0301 orr.w r3, r3, #1 + 8008dfa: b2db uxtb r3, r3 + 8008dfc: 4619 mov r1, r3 + 8008dfe: f640 1002 movw r0, #2306 @ 0x902 + 8008e02: 47a0 blx r4 + SubgRf.RxDcPreambleDetectTimeout = 0; + 8008e04: 4b3c ldr r3, [pc, #240] @ (8008ef8 ) + 8008e06: 2200 movs r2, #0 + 8008e08: 659a str r2, [r3, #88] @ 0x58 + SUBGRF_SetDioIrqParams( IRQ_RX_DONE | IRQ_RX_TX_TIMEOUT | IRQ_CRC_ERROR | IRQ_HEADER_ERROR | IRQ_RX_DBG, + 8008e0a: 2300 movs r3, #0 + 8008e0c: 2200 movs r2, #0 + 8008e0e: f240 2162 movw r1, #610 @ 0x262 + 8008e12: f240 2062 movw r0, #610 @ 0x262 + 8008e16: f001 f8cf bl 8009fb8 + break; + 8008e1a: e05f b.n 8008edc + MW_LOG( TS_ON, VLEVEL_M, "SYNC OK\r\n" ); + 8008e1c: 4b39 ldr r3, [pc, #228] @ (8008f04 ) + 8008e1e: 2201 movs r2, #1 + 8008e20: 2100 movs r1, #0 + 8008e22: 2002 movs r0, #2 + 8008e24: f005 f900 bl 800e028 + if( 1UL == RFW_Is_Init( ) ) + 8008e28: f002 f9ec bl 800b204 + 8008e2c: 4603 mov r3, r0 + 8008e2e: 2b01 cmp r3, #1 + 8008e30: d156 bne.n 8008ee0 + RFW_ReceivePayload( ); + 8008e32: f002 fac9 bl 800b3c8 + break; + 8008e36: e053 b.n 8008ee0 + MW_LOG( TS_ON, VLEVEL_M, "HDR OK\r\n" ); + 8008e38: 4b33 ldr r3, [pc, #204] @ (8008f08 ) + 8008e3a: 2201 movs r2, #1 + 8008e3c: 2100 movs r1, #0 + 8008e3e: 2002 movs r0, #2 + 8008e40: f005 f8f2 bl 800e028 + break; + 8008e44: e051 b.n 8008eea + TimerStop( &RxTimeoutTimer ); + 8008e46: 4831 ldr r0, [pc, #196] @ (8008f0c ) + 8008e48: f004 fef6 bl 800dc38 + if( SubgRf.RxContinuous == false ) + 8008e4c: 4b2a ldr r3, [pc, #168] @ (8008ef8 ) + 8008e4e: 785b ldrb r3, [r3, #1] + 8008e50: f083 0301 eor.w r3, r3, #1 + 8008e54: b2db uxtb r3, r3 + 8008e56: 2b00 cmp r3, #0 + 8008e58: d002 beq.n 8008e60 + SUBGRF_SetStandby( STDBY_RC ); + 8008e5a: 2000 movs r0, #0 + 8008e5c: f000 fed2 bl 8009c04 + if( ( RadioEvents != NULL ) && ( RadioEvents->RxTimeout != NULL ) ) + 8008e60: 4b2b ldr r3, [pc, #172] @ (8008f10 ) + 8008e62: 681b ldr r3, [r3, #0] + 8008e64: 2b00 cmp r3, #0 + 8008e66: d03d beq.n 8008ee4 + 8008e68: 4b29 ldr r3, [pc, #164] @ (8008f10 ) + 8008e6a: 681b ldr r3, [r3, #0] + 8008e6c: 68db ldr r3, [r3, #12] + 8008e6e: 2b00 cmp r3, #0 + 8008e70: d038 beq.n 8008ee4 + RadioEvents->RxTimeout( ); + 8008e72: 4b27 ldr r3, [pc, #156] @ (8008f10 ) + 8008e74: 681b ldr r3, [r3, #0] + 8008e76: 68db ldr r3, [r3, #12] + 8008e78: 4798 blx r3 + MW_LOG( TS_ON, VLEVEL_M, "HDR KO\r\n" ); + 8008e7a: 4b26 ldr r3, [pc, #152] @ (8008f14 ) + 8008e7c: 2201 movs r2, #1 + 8008e7e: 2100 movs r1, #0 + 8008e80: 2002 movs r0, #2 + 8008e82: f005 f8d1 bl 800e028 + break; + 8008e86: e02d b.n 8008ee4 + MW_LOG( TS_ON, VLEVEL_M, "IRQ_CRC_ERROR\r\n" ); + 8008e88: 4b23 ldr r3, [pc, #140] @ (8008f18 ) + 8008e8a: 2201 movs r2, #1 + 8008e8c: 2100 movs r1, #0 + 8008e8e: 2002 movs r0, #2 + 8008e90: f005 f8ca bl 800e028 + if( SubgRf.RxContinuous == false ) + 8008e94: 4b18 ldr r3, [pc, #96] @ (8008ef8 ) + 8008e96: 785b ldrb r3, [r3, #1] + 8008e98: f083 0301 eor.w r3, r3, #1 + 8008e9c: b2db uxtb r3, r3 + 8008e9e: 2b00 cmp r3, #0 + 8008ea0: d002 beq.n 8008ea8 + SUBGRF_SetStandby( STDBY_RC ); + 8008ea2: 2000 movs r0, #0 + 8008ea4: f000 feae bl 8009c04 + if( ( RadioEvents != NULL ) && ( RadioEvents->RxError ) ) + 8008ea8: 4b19 ldr r3, [pc, #100] @ (8008f10 ) + 8008eaa: 681b ldr r3, [r3, #0] + 8008eac: 2b00 cmp r3, #0 + 8008eae: d01b beq.n 8008ee8 + 8008eb0: 4b17 ldr r3, [pc, #92] @ (8008f10 ) + 8008eb2: 681b ldr r3, [r3, #0] + 8008eb4: 691b ldr r3, [r3, #16] + 8008eb6: 2b00 cmp r3, #0 + 8008eb8: d016 beq.n 8008ee8 + RadioEvents->RxError( ); + 8008eba: 4b15 ldr r3, [pc, #84] @ (8008f10 ) + 8008ebc: 681b ldr r3, [r3, #0] + 8008ebe: 691b ldr r3, [r3, #16] + 8008ec0: 4798 blx r3 + break; + 8008ec2: e011 b.n 8008ee8 + break; + 8008ec4: bf00 nop + 8008ec6: e010 b.n 8008eea + break; + 8008ec8: bf00 nop + 8008eca: e00e b.n 8008eea + break; + 8008ecc: bf00 nop + 8008ece: e00c b.n 8008eea + break; + 8008ed0: bf00 nop + 8008ed2: e00a b.n 8008eea + break; + 8008ed4: bf00 nop + 8008ed6: e008 b.n 8008eea + break; + 8008ed8: bf00 nop + 8008eda: e006 b.n 8008eea + break; + 8008edc: bf00 nop + 8008ede: e004 b.n 8008eea + break; + 8008ee0: bf00 nop + 8008ee2: e002 b.n 8008eea + break; + 8008ee4: bf00 nop + 8008ee6: e000 b.n 8008eea + break; + 8008ee8: bf00 nop + } +} + 8008eea: bf00 nop + 8008eec: 3708 adds r7, #8 + 8008eee: 46bd mov sp, r7 + 8008ef0: bdb0 pop {r4, r5, r7, pc} + 8008ef2: bf00 nop + 8008ef4: 0800f124 .word 0x0800f124 + 8008ef8: 20000300 .word 0x20000300 + 8008efc: 0800889d .word 0x0800889d + 8008f00: 080088c1 .word 0x080088c1 + 8008f04: 0800f130 .word 0x0800f130 + 8008f08: 0800f13c .word 0x0800f13c + 8008f0c: 20000374 .word 0x20000374 + 8008f10: 200002fc .word 0x200002fc + 8008f14: 0800f148 .word 0x0800f148 + 8008f18: 0800f154 .word 0x0800f154 + +08008f1c : + +static void RadioTxPrbs( void ) +{ + 8008f1c: b580 push {r7, lr} + 8008f1e: af00 add r7, sp, #0 + SUBGRF_SetSwitch( SubgRf.AntSwitchPaSelect, RFSWITCH_TX ); + 8008f20: 4b09 ldr r3, [pc, #36] @ (8008f48 ) + 8008f22: f893 3056 ldrb.w r3, [r3, #86] @ 0x56 + 8008f26: 2101 movs r1, #1 + 8008f28: 4618 mov r0, r3 + 8008f2a: f001 fcfd bl 800a928 + Radio.Write( SUBGHZ_GPKTCTL1AR, 0x2d ); // sel mode prbs9 instead of preamble + 8008f2e: 4b07 ldr r3, [pc, #28] @ (8008f4c ) + 8008f30: 212d movs r1, #45 @ 0x2d + 8008f32: f44f 60d7 mov.w r0, #1720 @ 0x6b8 + 8008f36: 4798 blx r3 + SUBGRF_SetTxInfinitePreamble( ); + 8008f38: f000 ff27 bl 8009d8a + SUBGRF_SetTx( 0x0fffff ); + 8008f3c: 4804 ldr r0, [pc, #16] @ (8008f50 ) + 8008f3e: f000 fe7d bl 8009c3c +} + 8008f42: bf00 nop + 8008f44: bd80 pop {r7, pc} + 8008f46: bf00 nop + 8008f48: 20000300 .word 0x20000300 + 8008f4c: 0800889d .word 0x0800889d + 8008f50: 000fffff .word 0x000fffff + +08008f54 : + +static void RadioTxCw( int8_t power ) +{ + 8008f54: b580 push {r7, lr} + 8008f56: b084 sub sp, #16 + 8008f58: af00 add r7, sp, #0 + 8008f5a: 4603 mov r3, r0 + 8008f5c: 71fb strb r3, [r7, #7] + uint8_t paselect = SUBGRF_SetRfTxPower( power ); + 8008f5e: f997 3007 ldrsb.w r3, [r7, #7] + 8008f62: 4618 mov r0, r3 + 8008f64: f001 fd08 bl 800a978 + 8008f68: 4603 mov r3, r0 + 8008f6a: 73fb strb r3, [r7, #15] + /* WORKAROUND - Trimming the output voltage power_ldo to 3.3V */ + SUBGRF_WriteRegister(REG_DRV_CTRL, 0x7 << 1); + 8008f6c: 210e movs r1, #14 + 8008f6e: f640 101f movw r0, #2335 @ 0x91f + 8008f72: f001 fbcb bl 800a70c + SUBGRF_SetSwitch( paselect, RFSWITCH_TX ); + 8008f76: 7bfb ldrb r3, [r7, #15] + 8008f78: 2101 movs r1, #1 + 8008f7a: 4618 mov r0, r3 + 8008f7c: f001 fcd4 bl 800a928 + SUBGRF_SetTxContinuousWave( ); + 8008f80: f000 fefa bl 8009d78 +} + 8008f84: bf00 nop + 8008f86: 3710 adds r7, #16 + 8008f88: 46bd mov sp, r7 + 8008f8a: bd80 pop {r7, pc} + +08008f8c : + +#if (RADIO_SIGFOX_ENABLE == 1) +static void payload_integration( uint8_t *outBuffer, uint8_t *inBuffer, uint8_t size ) +{ + 8008f8c: b480 push {r7} + 8008f8e: b089 sub sp, #36 @ 0x24 + 8008f90: af00 add r7, sp, #0 + 8008f92: 60f8 str r0, [r7, #12] + 8008f94: 60b9 str r1, [r7, #8] + 8008f96: 4613 mov r3, r2 + 8008f98: 71fb strb r3, [r7, #7] + uint8_t prevInt = 0; + 8008f9a: 2300 movs r3, #0 + 8008f9c: 77fb strb r3, [r7, #31] + uint8_t currBit; + uint8_t index_bit; + uint8_t index_byte; + uint8_t index_bit_out; + uint8_t index_byte_out; + int32_t i = 0; + 8008f9e: 2300 movs r3, #0 + 8008fa0: 61bb str r3, [r7, #24] + + for( i = 0; i < size; i++ ) + 8008fa2: 2300 movs r3, #0 + 8008fa4: 61bb str r3, [r7, #24] + 8008fa6: e011 b.n 8008fcc + { + /* reverse all inputs */ + inBuffer[i] = ~inBuffer[i]; + 8008fa8: 69bb ldr r3, [r7, #24] + 8008faa: 68ba ldr r2, [r7, #8] + 8008fac: 4413 add r3, r2 + 8008fae: 781a ldrb r2, [r3, #0] + 8008fb0: 69bb ldr r3, [r7, #24] + 8008fb2: 68b9 ldr r1, [r7, #8] + 8008fb4: 440b add r3, r1 + 8008fb6: 43d2 mvns r2, r2 + 8008fb8: b2d2 uxtb r2, r2 + 8008fba: 701a strb r2, [r3, #0] + /* init outBuffer */ + outBuffer[i] = 0; + 8008fbc: 69bb ldr r3, [r7, #24] + 8008fbe: 68fa ldr r2, [r7, #12] + 8008fc0: 4413 add r3, r2 + 8008fc2: 2200 movs r2, #0 + 8008fc4: 701a strb r2, [r3, #0] + for( i = 0; i < size; i++ ) + 8008fc6: 69bb ldr r3, [r7, #24] + 8008fc8: 3301 adds r3, #1 + 8008fca: 61bb str r3, [r7, #24] + 8008fcc: 79fb ldrb r3, [r7, #7] + 8008fce: 69ba ldr r2, [r7, #24] + 8008fd0: 429a cmp r2, r3 + 8008fd2: dbe9 blt.n 8008fa8 + } + + for( i = 0; i < ( size * 8 ); i++ ) + 8008fd4: 2300 movs r3, #0 + 8008fd6: 61bb str r3, [r7, #24] + 8008fd8: e049 b.n 800906e + { + /* index to take bit in inBuffer */ + index_bit = 7 - ( i % 8 ); + 8008fda: 69bb ldr r3, [r7, #24] + 8008fdc: 425a negs r2, r3 + 8008fde: f003 0307 and.w r3, r3, #7 + 8008fe2: f002 0207 and.w r2, r2, #7 + 8008fe6: bf58 it pl + 8008fe8: 4253 negpl r3, r2 + 8008fea: b2db uxtb r3, r3 + 8008fec: f1c3 0307 rsb r3, r3, #7 + 8008ff0: 75fb strb r3, [r7, #23] + index_byte = i / 8; + 8008ff2: 69bb ldr r3, [r7, #24] + 8008ff4: 2b00 cmp r3, #0 + 8008ff6: da00 bge.n 8008ffa + 8008ff8: 3307 adds r3, #7 + 8008ffa: 10db asrs r3, r3, #3 + 8008ffc: 75bb strb r3, [r7, #22] + /* index to place bit in outBuffer is shifted 1 bit right */ + index_bit_out = 7 - ( ( i + 1 ) % 8 ); + 8008ffe: 69bb ldr r3, [r7, #24] + 8009000: 3301 adds r3, #1 + 8009002: 425a negs r2, r3 + 8009004: f003 0307 and.w r3, r3, #7 + 8009008: f002 0207 and.w r2, r2, #7 + 800900c: bf58 it pl + 800900e: 4253 negpl r3, r2 + 8009010: b2db uxtb r3, r3 + 8009012: f1c3 0307 rsb r3, r3, #7 + 8009016: 757b strb r3, [r7, #21] + index_byte_out = ( i + 1 ) / 8; + 8009018: 69bb ldr r3, [r7, #24] + 800901a: 3301 adds r3, #1 + 800901c: 2b00 cmp r3, #0 + 800901e: da00 bge.n 8009022 + 8009020: 3307 adds r3, #7 + 8009022: 10db asrs r3, r3, #3 + 8009024: 753b strb r3, [r7, #20] + /* extract current bit from input */ + currBit = ( inBuffer[index_byte] >> index_bit ) & 0x01; + 8009026: 7dbb ldrb r3, [r7, #22] + 8009028: 68ba ldr r2, [r7, #8] + 800902a: 4413 add r3, r2 + 800902c: 781b ldrb r3, [r3, #0] + 800902e: 461a mov r2, r3 + 8009030: 7dfb ldrb r3, [r7, #23] + 8009032: fa42 f303 asr.w r3, r2, r3 + 8009036: b2db uxtb r3, r3 + 8009038: f003 0301 and.w r3, r3, #1 + 800903c: 74fb strb r3, [r7, #19] + /* integration */ + prevInt ^= currBit; + 800903e: 7ffa ldrb r2, [r7, #31] + 8009040: 7cfb ldrb r3, [r7, #19] + 8009042: 4053 eors r3, r2 + 8009044: 77fb strb r3, [r7, #31] + /* write result integration in output */ + outBuffer[index_byte_out] |= ( prevInt << index_bit_out ); + 8009046: 7d3b ldrb r3, [r7, #20] + 8009048: 68fa ldr r2, [r7, #12] + 800904a: 4413 add r3, r2 + 800904c: 781b ldrb r3, [r3, #0] + 800904e: b25a sxtb r2, r3 + 8009050: 7ff9 ldrb r1, [r7, #31] + 8009052: 7d7b ldrb r3, [r7, #21] + 8009054: fa01 f303 lsl.w r3, r1, r3 + 8009058: b25b sxtb r3, r3 + 800905a: 4313 orrs r3, r2 + 800905c: b259 sxtb r1, r3 + 800905e: 7d3b ldrb r3, [r7, #20] + 8009060: 68fa ldr r2, [r7, #12] + 8009062: 4413 add r3, r2 + 8009064: b2ca uxtb r2, r1 + 8009066: 701a strb r2, [r3, #0] + for( i = 0; i < ( size * 8 ); i++ ) + 8009068: 69bb ldr r3, [r7, #24] + 800906a: 3301 adds r3, #1 + 800906c: 61bb str r3, [r7, #24] + 800906e: 79fb ldrb r3, [r7, #7] + 8009070: 00db lsls r3, r3, #3 + 8009072: 69ba ldr r2, [r7, #24] + 8009074: 429a cmp r2, r3 + 8009076: dbb0 blt.n 8008fda + } + + outBuffer[size] = ( prevInt << 7 ) | ( prevInt << 6 ) | ( ( ( !prevInt ) & 0x01 ) << 5 ) ; + 8009078: f997 301f ldrsb.w r3, [r7, #31] + 800907c: 01db lsls r3, r3, #7 + 800907e: b25a sxtb r2, r3 + 8009080: f997 301f ldrsb.w r3, [r7, #31] + 8009084: 019b lsls r3, r3, #6 + 8009086: b25b sxtb r3, r3 + 8009088: 4313 orrs r3, r2 + 800908a: b25b sxtb r3, r3 + 800908c: 7ffa ldrb r2, [r7, #31] + 800908e: 2a00 cmp r2, #0 + 8009090: d101 bne.n 8009096 + 8009092: 2220 movs r2, #32 + 8009094: e000 b.n 8009098 + 8009096: 2200 movs r2, #0 + 8009098: 4313 orrs r3, r2 + 800909a: b259 sxtb r1, r3 + 800909c: 79fb ldrb r3, [r7, #7] + 800909e: 68fa ldr r2, [r7, #12] + 80090a0: 4413 add r3, r2 + 80090a2: b2ca uxtb r2, r1 + 80090a4: 701a strb r2, [r3, #0] +} + 80090a6: bf00 nop + 80090a8: 3724 adds r7, #36 @ 0x24 + 80090aa: 46bd mov sp, r7 + 80090ac: bc80 pop {r7} + 80090ae: 4770 bx lr + +080090b0 : +#endif /*RADIO_SIGFOX_ENABLE == 1*/ + +static int32_t RadioSetRxGenericConfig( GenericModems_t modem, RxConfigGeneric_t *config, uint32_t rxContinuous, + uint32_t symbTimeout ) +{ + 80090b0: b580 push {r7, lr} + 80090b2: b08c sub sp, #48 @ 0x30 + 80090b4: af00 add r7, sp, #0 + 80090b6: 60b9 str r1, [r7, #8] + 80090b8: 607a str r2, [r7, #4] + 80090ba: 603b str r3, [r7, #0] + 80090bc: 4603 mov r3, r0 + 80090be: 73fb strb r3, [r7, #15] +#if (RADIO_GENERIC_CONFIG_ENABLE == 1) + int32_t status = 0; + 80090c0: 2300 movs r3, #0 + 80090c2: 62bb str r3, [r7, #40] @ 0x28 + uint8_t syncword[8] = {0}; + 80090c4: f107 0320 add.w r3, r7, #32 + 80090c8: 2200 movs r2, #0 + 80090ca: 601a str r2, [r3, #0] + 80090cc: 605a str r2, [r3, #4] + uint8_t MaxPayloadLength; + + RFW_DeInit( ); /* switch Off FwPacketDecoding by default */ + 80090ce: f002 f88d bl 800b1ec + + if( rxContinuous != 0 ) + 80090d2: 687b ldr r3, [r7, #4] + 80090d4: 2b00 cmp r3, #0 + 80090d6: d001 beq.n 80090dc + { + symbTimeout = 0; + 80090d8: 2300 movs r3, #0 + 80090da: 603b str r3, [r7, #0] + } + SubgRf.RxContinuous = ( rxContinuous == 0 ) ? false : true; + 80090dc: 687b ldr r3, [r7, #4] + 80090de: 2b00 cmp r3, #0 + 80090e0: bf14 ite ne + 80090e2: 2301 movne r3, #1 + 80090e4: 2300 moveq r3, #0 + 80090e6: b2da uxtb r2, r3 + 80090e8: 4ba3 ldr r3, [pc, #652] @ (8009378 ) + 80090ea: 705a strb r2, [r3, #1] + + switch( modem ) + 80090ec: 7bfb ldrb r3, [r7, #15] + 80090ee: 2b00 cmp r3, #0 + 80090f0: d003 beq.n 80090fa + 80090f2: 2b01 cmp r3, #1 + 80090f4: f000 80dc beq.w 80092b0 + + // Timeout Max, Timeout handled directly in SetRx function + SubgRf.RxTimeout = 0xFFFF; + break; + default: + break; + 80090f8: e195 b.n 8009426 + if( ( config->fsk.BitRate == 0 ) || ( config->fsk.PreambleLen == 0 ) ) + 80090fa: 68bb ldr r3, [r7, #8] + 80090fc: 689b ldr r3, [r3, #8] + 80090fe: 2b00 cmp r3, #0 + 8009100: d003 beq.n 800910a + 8009102: 68bb ldr r3, [r7, #8] + 8009104: 68db ldr r3, [r3, #12] + 8009106: 2b00 cmp r3, #0 + 8009108: d102 bne.n 8009110 + return -1; + 800910a: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff + 800910e: e18b b.n 8009428 + if( config->fsk.SyncWordLength > 8 ) + 8009110: 68bb ldr r3, [r7, #8] + 8009112: 7f9b ldrb r3, [r3, #30] + 8009114: 2b08 cmp r3, #8 + 8009116: d902 bls.n 800911e + return -1; + 8009118: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff + 800911c: e184 b.n 8009428 + RADIO_MEMCPY8( syncword, config->fsk.SyncWord, config->fsk.SyncWordLength ); + 800911e: 68bb ldr r3, [r7, #8] + 8009120: 6919 ldr r1, [r3, #16] + 8009122: 68bb ldr r3, [r7, #8] + 8009124: 7f9b ldrb r3, [r3, #30] + 8009126: 461a mov r2, r3 + 8009128: f107 0320 add.w r3, r7, #32 + 800912c: 4618 mov r0, r3 + 800912e: f004 f87d bl 800d22c + SUBGRF_SetStopRxTimerOnPreambleDetect( ( config->fsk.StopTimerOnPreambleDetect == 0 ) ? false : true ); + 8009132: 68bb ldr r3, [r7, #8] + 8009134: 681b ldr r3, [r3, #0] + 8009136: 2b00 cmp r3, #0 + 8009138: bf14 ite ne + 800913a: 2301 movne r3, #1 + 800913c: 2300 moveq r3, #0 + 800913e: b2db uxtb r3, r3 + 8009140: 4618 mov r0, r3 + 8009142: f000 fe2b bl 8009d9c + SubgRf.ModulationParams.PacketType = PACKET_TYPE_GFSK; + 8009146: 4b8c ldr r3, [pc, #560] @ (8009378 ) + 8009148: 2200 movs r2, #0 + 800914a: f883 2038 strb.w r2, [r3, #56] @ 0x38 + SubgRf.ModulationParams.Params.Gfsk.BitRate = config->fsk.BitRate; + 800914e: 68bb ldr r3, [r7, #8] + 8009150: 689b ldr r3, [r3, #8] + 8009152: 4a89 ldr r2, [pc, #548] @ (8009378 ) + 8009154: 63d3 str r3, [r2, #60] @ 0x3c + SubgRf.ModulationParams.Params.Gfsk.ModulationShaping = ( RadioModShapings_t ) config->fsk.ModulationShaping; + 8009156: 68bb ldr r3, [r7, #8] + 8009158: f893 2020 ldrb.w r2, [r3, #32] + 800915c: 4b86 ldr r3, [pc, #536] @ (8009378 ) + 800915e: f883 2044 strb.w r2, [r3, #68] @ 0x44 + SubgRf.ModulationParams.Params.Gfsk.Bandwidth = SUBGRF_GetFskBandwidthRegValue( config->fsk.Bandwidth ); + 8009162: 68bb ldr r3, [r7, #8] + 8009164: 685b ldr r3, [r3, #4] + 8009166: 4618 mov r0, r3 + 8009168: f001 fd04 bl 800ab74 + 800916c: 4603 mov r3, r0 + 800916e: 461a mov r2, r3 + 8009170: 4b81 ldr r3, [pc, #516] @ (8009378 ) + 8009172: f883 2045 strb.w r2, [r3, #69] @ 0x45 + SubgRf.PacketParams.PacketType = PACKET_TYPE_GFSK; + 8009176: 4b80 ldr r3, [pc, #512] @ (8009378 ) + 8009178: 2200 movs r2, #0 + 800917a: 739a strb r2, [r3, #14] + SubgRf.PacketParams.Params.Gfsk.PreambleLength = ( config->fsk.PreambleLen ) << 3 ; // convert byte into bit + 800917c: 68bb ldr r3, [r7, #8] + 800917e: 68db ldr r3, [r3, #12] + 8009180: b29b uxth r3, r3 + 8009182: 00db lsls r3, r3, #3 + 8009184: b29a uxth r2, r3 + 8009186: 4b7c ldr r3, [pc, #496] @ (8009378 ) + 8009188: 821a strh r2, [r3, #16] + SubgRf.PacketParams.Params.Gfsk.PreambleMinDetect = ( RadioPreambleDetection_t ) config->fsk.PreambleMinDetect; + 800918a: 68bb ldr r3, [r7, #8] + 800918c: 7fda ldrb r2, [r3, #31] + 800918e: 4b7a ldr r3, [pc, #488] @ (8009378 ) + 8009190: 749a strb r2, [r3, #18] + SubgRf.PacketParams.Params.Gfsk.SyncWordLength = ( config->fsk.SyncWordLength ) << 3; // convert byte into bit + 8009192: 68bb ldr r3, [r7, #8] + 8009194: 7f9b ldrb r3, [r3, #30] + 8009196: 00db lsls r3, r3, #3 + 8009198: b2da uxtb r2, r3 + 800919a: 4b77 ldr r3, [pc, #476] @ (8009378 ) + 800919c: 74da strb r2, [r3, #19] + SubgRf.PacketParams.Params.Gfsk.AddrComp = ( RadioAddressComp_t ) config->fsk.AddrComp; + 800919e: 68bb ldr r3, [r7, #8] + 80091a0: f893 2021 ldrb.w r2, [r3, #33] @ 0x21 + 80091a4: 4b74 ldr r3, [pc, #464] @ (8009378 ) + 80091a6: 751a strb r2, [r3, #20] + if( config->fsk.LengthMode == RADIO_FSK_PACKET_FIXED_LENGTH ) + 80091a8: 68bb ldr r3, [r7, #8] + 80091aa: f893 3022 ldrb.w r3, [r3, #34] @ 0x22 + 80091ae: 2b00 cmp r3, #0 + 80091b0: d105 bne.n 80091be + SubgRf.PacketParams.Params.Gfsk.PayloadLength = config->fsk.MaxPayloadLength; + 80091b2: 68bb ldr r3, [r7, #8] + 80091b4: 695b ldr r3, [r3, #20] + 80091b6: b2da uxtb r2, r3 + 80091b8: 4b6f ldr r3, [pc, #444] @ (8009378 ) + 80091ba: 759a strb r2, [r3, #22] + 80091bc: e00b b.n 80091d6 + else if( config->fsk.LengthMode == RADIO_FSK_PACKET_2BYTES_LENGTH ) + 80091be: 68bb ldr r3, [r7, #8] + 80091c0: f893 3022 ldrb.w r3, [r3, #34] @ 0x22 + 80091c4: 2b02 cmp r3, #2 + 80091c6: d103 bne.n 80091d0 + SubgRf.PacketParams.Params.Gfsk.PayloadLength = 0xFF; + 80091c8: 4b6b ldr r3, [pc, #428] @ (8009378 ) + 80091ca: 22ff movs r2, #255 @ 0xff + 80091cc: 759a strb r2, [r3, #22] + 80091ce: e002 b.n 80091d6 + SubgRf.PacketParams.Params.Gfsk.PayloadLength = 0xFF; + 80091d0: 4b69 ldr r3, [pc, #420] @ (8009378 ) + 80091d2: 22ff movs r2, #255 @ 0xff + 80091d4: 759a strb r2, [r3, #22] + if( ( config->fsk.Whitening == RADIO_FSK_DC_IBM_WHITENING ) + 80091d6: 68bb ldr r3, [r7, #8] + 80091d8: f893 3024 ldrb.w r3, [r3, #36] @ 0x24 + 80091dc: 2b02 cmp r3, #2 + 80091de: d004 beq.n 80091ea + || ( config->fsk.LengthMode == RADIO_FSK_PACKET_2BYTES_LENGTH ) ) + 80091e0: 68bb ldr r3, [r7, #8] + 80091e2: f893 3022 ldrb.w r3, [r3, #34] @ 0x22 + 80091e6: 2b02 cmp r3, #2 + 80091e8: d12d bne.n 8009246 + if( ( config->fsk.CrcLength != RADIO_FSK_CRC_2_BYTES_IBM ) && ( config->fsk.CrcLength != RADIO_FSK_CRC_2_BYTES_CCIT ) + 80091ea: 68bb ldr r3, [r7, #8] + 80091ec: f893 3023 ldrb.w r3, [r3, #35] @ 0x23 + 80091f0: 2bf1 cmp r3, #241 @ 0xf1 + 80091f2: d00c beq.n 800920e + 80091f4: 68bb ldr r3, [r7, #8] + 80091f6: f893 3023 ldrb.w r3, [r3, #35] @ 0x23 + 80091fa: 2bf2 cmp r3, #242 @ 0xf2 + 80091fc: d007 beq.n 800920e + && ( config->fsk.CrcLength != RADIO_FSK_CRC_OFF ) ) + 80091fe: 68bb ldr r3, [r7, #8] + 8009200: f893 3023 ldrb.w r3, [r3, #35] @ 0x23 + 8009204: 2b01 cmp r3, #1 + 8009206: d002 beq.n 800920e + return -1; + 8009208: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff + 800920c: e10c b.n 8009428 + ConfigGeneric.rtx = CONFIG_RX; + 800920e: 2300 movs r3, #0 + 8009210: 773b strb r3, [r7, #28] + ConfigGeneric.RxConfig = config; + 8009212: 68bb ldr r3, [r7, #8] + 8009214: 61bb str r3, [r7, #24] + if( 0UL != RFW_Init( &ConfigGeneric, RadioEvents, &RxTimeoutTimer ) ) + 8009216: 4b59 ldr r3, [pc, #356] @ (800937c ) + 8009218: 6819 ldr r1, [r3, #0] + 800921a: f107 0314 add.w r3, r7, #20 + 800921e: 4a58 ldr r2, [pc, #352] @ (8009380 ) + 8009220: 4618 mov r0, r3 + 8009222: f001 ff49 bl 800b0b8 + 8009226: 4603 mov r3, r0 + 8009228: 2b00 cmp r3, #0 + 800922a: d002 beq.n 8009232 + return -1; + 800922c: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff + 8009230: e0fa b.n 8009428 + SubgRf.PacketParams.Params.Gfsk.DcFree = ( RadioDcFree_t ) RADIO_FSK_DC_FREE_OFF; + 8009232: 4b51 ldr r3, [pc, #324] @ (8009378 ) + 8009234: 2200 movs r2, #0 + 8009236: 761a strb r2, [r3, #24] + SubgRf.PacketParams.Params.Gfsk.CrcLength = ( RadioCrcTypes_t ) RADIO_CRC_OFF; + 8009238: 4b4f ldr r3, [pc, #316] @ (8009378 ) + 800923a: 2201 movs r2, #1 + 800923c: 75da strb r2, [r3, #23] + SubgRf.PacketParams.Params.Gfsk.HeaderType = ( RadioPacketLengthModes_t ) RADIO_PACKET_FIXED_LENGTH; + 800923e: 4b4e ldr r3, [pc, #312] @ (8009378 ) + 8009240: 2200 movs r2, #0 + 8009242: 755a strb r2, [r3, #21] + { + 8009244: e00e b.n 8009264 + SubgRf.PacketParams.Params.Gfsk.CrcLength = ( RadioCrcTypes_t ) config->fsk.CrcLength; + 8009246: 68bb ldr r3, [r7, #8] + 8009248: f893 2023 ldrb.w r2, [r3, #35] @ 0x23 + 800924c: 4b4a ldr r3, [pc, #296] @ (8009378 ) + 800924e: 75da strb r2, [r3, #23] + SubgRf.PacketParams.Params.Gfsk.DcFree = ( RadioDcFree_t ) config->fsk.Whitening; + 8009250: 68bb ldr r3, [r7, #8] + 8009252: f893 2024 ldrb.w r2, [r3, #36] @ 0x24 + 8009256: 4b48 ldr r3, [pc, #288] @ (8009378 ) + 8009258: 761a strb r2, [r3, #24] + SubgRf.PacketParams.Params.Gfsk.HeaderType = ( RadioPacketLengthModes_t ) config->fsk.LengthMode; + 800925a: 68bb ldr r3, [r7, #8] + 800925c: f893 2022 ldrb.w r2, [r3, #34] @ 0x22 + 8009260: 4b45 ldr r3, [pc, #276] @ (8009378 ) + 8009262: 755a strb r2, [r3, #21] + RadioStandby( ); + 8009264: f7ff fa0d bl 8008682 + RadioSetModem( MODEM_FSK ); + 8009268: 2000 movs r0, #0 + 800926a: f7fe fb9b bl 80079a4 + SUBGRF_SetModulationParams( &SubgRf.ModulationParams ); + 800926e: 4845 ldr r0, [pc, #276] @ (8009384 ) + 8009270: f001 f838 bl 800a2e4 + SUBGRF_SetPacketParams( &SubgRf.PacketParams ); + 8009274: 4844 ldr r0, [pc, #272] @ (8009388 ) + 8009276: f001 f903 bl 800a480 + SUBGRF_SetSyncWord( syncword ); + 800927a: f107 0320 add.w r3, r7, #32 + 800927e: 4618 mov r0, r3 + 8009280: f000 fbc3 bl 8009a0a + SUBGRF_SetWhiteningSeed( config->fsk.whiteSeed ); + 8009284: 68bb ldr r3, [r7, #8] + 8009286: 8b9b ldrh r3, [r3, #28] + 8009288: 4618 mov r0, r3 + 800928a: f000 fc0d bl 8009aa8 + SUBGRF_SetCrcPolynomial( config->fsk.CrcPolynomial ); + 800928e: 68bb ldr r3, [r7, #8] + 8009290: 8b1b ldrh r3, [r3, #24] + 8009292: 4618 mov r0, r3 + 8009294: f000 fbe8 bl 8009a68 + SubgRf.RxTimeout = ( uint32_t )( ( symbTimeout * 1000 * 8 ) / config->fsk.BitRate ); + 8009298: 683b ldr r3, [r7, #0] + 800929a: f44f 52fa mov.w r2, #8000 @ 0x1f40 + 800929e: fb03 f202 mul.w r2, r3, r2 + 80092a2: 68bb ldr r3, [r7, #8] + 80092a4: 689b ldr r3, [r3, #8] + 80092a6: fbb2 f3f3 udiv r3, r2, r3 + 80092aa: 4a33 ldr r2, [pc, #204] @ (8009378 ) + 80092ac: 6093 str r3, [r2, #8] + break; + 80092ae: e0ba b.n 8009426 + if( config->lora.PreambleLen == 0 ) + 80092b0: 68bb ldr r3, [r7, #8] + 80092b2: 8e1b ldrh r3, [r3, #48] @ 0x30 + 80092b4: 2b00 cmp r3, #0 + 80092b6: d102 bne.n 80092be + return -1; + 80092b8: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff + 80092bc: e0b4 b.n 8009428 + if( config->lora.LengthMode == RADIO_LORA_PACKET_FIXED_LENGTH ) + 80092be: 68bb ldr r3, [r7, #8] + 80092c0: f893 3032 ldrb.w r3, [r3, #50] @ 0x32 + 80092c4: 2b01 cmp r3, #1 + 80092c6: d105 bne.n 80092d4 + MaxPayloadLength = config->lora.MaxPayloadLength; + 80092c8: 68bb ldr r3, [r7, #8] + 80092ca: f893 3033 ldrb.w r3, [r3, #51] @ 0x33 + 80092ce: f887 302f strb.w r3, [r7, #47] @ 0x2f + 80092d2: e002 b.n 80092da + MaxPayloadLength = 0xFF; + 80092d4: 23ff movs r3, #255 @ 0xff + 80092d6: f887 302f strb.w r3, [r7, #47] @ 0x2f + SUBGRF_SetStopRxTimerOnPreambleDetect( ( config->lora.StopTimerOnPreambleDetect == 0 ) ? false : true ); + 80092da: 68bb ldr r3, [r7, #8] + 80092dc: 6a9b ldr r3, [r3, #40] @ 0x28 + 80092de: 2b00 cmp r3, #0 + 80092e0: bf14 ite ne + 80092e2: 2301 movne r3, #1 + 80092e4: 2300 moveq r3, #0 + 80092e6: b2db uxtb r3, r3 + 80092e8: 4618 mov r0, r3 + 80092ea: f000 fd57 bl 8009d9c + SUBGRF_SetLoRaSymbNumTimeout( symbTimeout ); + 80092ee: 683b ldr r3, [r7, #0] + 80092f0: b2db uxtb r3, r3 + 80092f2: 4618 mov r0, r3 + 80092f4: f000 fd61 bl 8009dba + SubgRf.ModulationParams.PacketType = PACKET_TYPE_LORA; + 80092f8: 4b1f ldr r3, [pc, #124] @ (8009378 ) + 80092fa: 2201 movs r2, #1 + 80092fc: f883 2038 strb.w r2, [r3, #56] @ 0x38 + SubgRf.ModulationParams.Params.LoRa.SpreadingFactor = ( RadioLoRaSpreadingFactors_t ) config->lora.SpreadingFactor; + 8009300: 68bb ldr r3, [r7, #8] + 8009302: f893 202c ldrb.w r2, [r3, #44] @ 0x2c + 8009306: 4b1c ldr r3, [pc, #112] @ (8009378 ) + 8009308: f883 2050 strb.w r2, [r3, #80] @ 0x50 + SubgRf.ModulationParams.Params.LoRa.Bandwidth = ( RadioLoRaBandwidths_t ) config->lora.Bandwidth; + 800930c: 68bb ldr r3, [r7, #8] + 800930e: f893 202d ldrb.w r2, [r3, #45] @ 0x2d + 8009312: 4b19 ldr r3, [pc, #100] @ (8009378 ) + 8009314: f883 2051 strb.w r2, [r3, #81] @ 0x51 + SubgRf.ModulationParams.Params.LoRa.CodingRate = ( RadioLoRaCodingRates_t ) config->lora.Coderate; + 8009318: 68bb ldr r3, [r7, #8] + 800931a: f893 202e ldrb.w r2, [r3, #46] @ 0x2e + 800931e: 4b16 ldr r3, [pc, #88] @ (8009378 ) + 8009320: f883 2052 strb.w r2, [r3, #82] @ 0x52 + switch( config->lora.LowDatarateOptimize ) + 8009324: 68bb ldr r3, [r7, #8] + 8009326: f893 302f ldrb.w r3, [r3, #47] @ 0x2f + 800932a: 2b02 cmp r3, #2 + 800932c: d010 beq.n 8009350 + 800932e: 2b02 cmp r3, #2 + 8009330: dc2c bgt.n 800938c + 8009332: 2b00 cmp r3, #0 + 8009334: d002 beq.n 800933c + 8009336: 2b01 cmp r3, #1 + 8009338: d005 beq.n 8009346 + break; + 800933a: e027 b.n 800938c + SubgRf.ModulationParams.Params.LoRa.LowDatarateOptimize = 0; + 800933c: 4b0e ldr r3, [pc, #56] @ (8009378 ) + 800933e: 2200 movs r2, #0 + 8009340: f883 2053 strb.w r2, [r3, #83] @ 0x53 + break; + 8009344: e023 b.n 800938e + SubgRf.ModulationParams.Params.LoRa.LowDatarateOptimize = 1; + 8009346: 4b0c ldr r3, [pc, #48] @ (8009378 ) + 8009348: 2201 movs r2, #1 + 800934a: f883 2053 strb.w r2, [r3, #83] @ 0x53 + break; + 800934e: e01e b.n 800938e + if( ( config->lora.SpreadingFactor == RADIO_LORA_SF11 ) || ( config->lora.SpreadingFactor == RADIO_LORA_SF12 ) ) + 8009350: 68bb ldr r3, [r7, #8] + 8009352: f893 302c ldrb.w r3, [r3, #44] @ 0x2c + 8009356: 2b0b cmp r3, #11 + 8009358: d004 beq.n 8009364 + 800935a: 68bb ldr r3, [r7, #8] + 800935c: f893 302c ldrb.w r3, [r3, #44] @ 0x2c + 8009360: 2b0c cmp r3, #12 + 8009362: d104 bne.n 800936e + SubgRf.ModulationParams.Params.LoRa.LowDatarateOptimize = 1; + 8009364: 4b04 ldr r3, [pc, #16] @ (8009378 ) + 8009366: 2201 movs r2, #1 + 8009368: f883 2053 strb.w r2, [r3, #83] @ 0x53 + break; + 800936c: e00f b.n 800938e + SubgRf.ModulationParams.Params.LoRa.LowDatarateOptimize = 0; + 800936e: 4b02 ldr r3, [pc, #8] @ (8009378 ) + 8009370: 2200 movs r2, #0 + 8009372: f883 2053 strb.w r2, [r3, #83] @ 0x53 + break; + 8009376: e00a b.n 800938e + 8009378: 20000300 .word 0x20000300 + 800937c: 200002fc .word 0x200002fc + 8009380: 20000374 .word 0x20000374 + 8009384: 20000338 .word 0x20000338 + 8009388: 2000030e .word 0x2000030e + break; + 800938c: bf00 nop + SubgRf.PacketParams.PacketType = PACKET_TYPE_LORA; + 800938e: 4b28 ldr r3, [pc, #160] @ (8009430 ) + 8009390: 2201 movs r2, #1 + 8009392: 739a strb r2, [r3, #14] + SubgRf.PacketParams.Params.LoRa.PreambleLength = config->lora.PreambleLen; + 8009394: 68bb ldr r3, [r7, #8] + 8009396: 8e1a ldrh r2, [r3, #48] @ 0x30 + 8009398: 4b25 ldr r3, [pc, #148] @ (8009430 ) + 800939a: 839a strh r2, [r3, #28] + SubgRf.PacketParams.Params.LoRa.HeaderType = ( RadioLoRaPacketLengthsMode_t ) config->lora.LengthMode; + 800939c: 68bb ldr r3, [r7, #8] + 800939e: f893 2032 ldrb.w r2, [r3, #50] @ 0x32 + 80093a2: 4b23 ldr r3, [pc, #140] @ (8009430 ) + 80093a4: 779a strb r2, [r3, #30] + SubgRf.PacketParams.Params.LoRa.PayloadLength = MaxPayloadLength; + 80093a6: 4a22 ldr r2, [pc, #136] @ (8009430 ) + 80093a8: f897 302f ldrb.w r3, [r7, #47] @ 0x2f + 80093ac: 77d3 strb r3, [r2, #31] + SubgRf.PacketParams.Params.LoRa.CrcMode = ( RadioLoRaCrcModes_t ) config->lora.CrcMode; + 80093ae: 68bb ldr r3, [r7, #8] + 80093b0: f893 2034 ldrb.w r2, [r3, #52] @ 0x34 + 80093b4: 4b1e ldr r3, [pc, #120] @ (8009430 ) + 80093b6: f883 2020 strb.w r2, [r3, #32] + SubgRf.PacketParams.Params.LoRa.InvertIQ = ( RadioLoRaIQModes_t ) config->lora.IqInverted; + 80093ba: 68bb ldr r3, [r7, #8] + 80093bc: f893 2035 ldrb.w r2, [r3, #53] @ 0x35 + 80093c0: 4b1b ldr r3, [pc, #108] @ (8009430 ) + 80093c2: f883 2021 strb.w r2, [r3, #33] @ 0x21 + RadioStandby( ); + 80093c6: f7ff f95c bl 8008682 + RadioSetModem( MODEM_LORA ); + 80093ca: 2001 movs r0, #1 + 80093cc: f7fe faea bl 80079a4 + SUBGRF_SetModulationParams( &SubgRf.ModulationParams ); + 80093d0: 4818 ldr r0, [pc, #96] @ (8009434 ) + 80093d2: f000 ff87 bl 800a2e4 + SUBGRF_SetPacketParams( &SubgRf.PacketParams ); + 80093d6: 4818 ldr r0, [pc, #96] @ (8009438 ) + 80093d8: f001 f852 bl 800a480 + if( SubgRf.PacketParams.Params.LoRa.InvertIQ == LORA_IQ_INVERTED ) + 80093dc: 4b14 ldr r3, [pc, #80] @ (8009430 ) + 80093de: f893 3021 ldrb.w r3, [r3, #33] @ 0x21 + 80093e2: 2b01 cmp r3, #1 + 80093e4: d10d bne.n 8009402 + SUBGRF_WriteRegister( SUBGHZ_LIQPOLR, SUBGRF_ReadRegister( SUBGHZ_LIQPOLR ) & ~( 1 << 2 ) ); + 80093e6: f240 7036 movw r0, #1846 @ 0x736 + 80093ea: f001 f9b1 bl 800a750 + 80093ee: 4603 mov r3, r0 + 80093f0: f023 0304 bic.w r3, r3, #4 + 80093f4: b2db uxtb r3, r3 + 80093f6: 4619 mov r1, r3 + 80093f8: f240 7036 movw r0, #1846 @ 0x736 + 80093fc: f001 f986 bl 800a70c + 8009400: e00c b.n 800941c + SUBGRF_WriteRegister( SUBGHZ_LIQPOLR, SUBGRF_ReadRegister( SUBGHZ_LIQPOLR ) | ( 1 << 2 ) ); + 8009402: f240 7036 movw r0, #1846 @ 0x736 + 8009406: f001 f9a3 bl 800a750 + 800940a: 4603 mov r3, r0 + 800940c: f043 0304 orr.w r3, r3, #4 + 8009410: b2db uxtb r3, r3 + 8009412: 4619 mov r1, r3 + 8009414: f240 7036 movw r0, #1846 @ 0x736 + 8009418: f001 f978 bl 800a70c + SubgRf.RxTimeout = 0xFFFF; + 800941c: 4b04 ldr r3, [pc, #16] @ (8009430 ) + 800941e: f64f 72ff movw r2, #65535 @ 0xffff + 8009422: 609a str r2, [r3, #8] + break; + 8009424: bf00 nop + } + return status; + 8009426: 6abb ldr r3, [r7, #40] @ 0x28 +#else /* RADIO_GENERIC_CONFIG_ENABLE == 1*/ + return -1; +#endif /* RADIO_GENERIC_CONFIG_ENABLE == 0*/ +} + 8009428: 4618 mov r0, r3 + 800942a: 3730 adds r7, #48 @ 0x30 + 800942c: 46bd mov sp, r7 + 800942e: bd80 pop {r7, pc} + 8009430: 20000300 .word 0x20000300 + 8009434: 20000338 .word 0x20000338 + 8009438: 2000030e .word 0x2000030e + +0800943c : + +static int32_t RadioSetTxGenericConfig( GenericModems_t modem, TxConfigGeneric_t *config, int8_t power, + uint32_t timeout ) +{ + 800943c: b580 push {r7, lr} + 800943e: b08e sub sp, #56 @ 0x38 + 8009440: af00 add r7, sp, #0 + 8009442: 60b9 str r1, [r7, #8] + 8009444: 607b str r3, [r7, #4] + 8009446: 4603 mov r3, r0 + 8009448: 73fb strb r3, [r7, #15] + 800944a: 4613 mov r3, r2 + 800944c: 73bb strb r3, [r7, #14] +#if( RADIO_LR_FHSS_IS_ON == 1 ) + /*disable LrFhss*/ + SubgRf.lr_fhss.is_lr_fhss_on = false; +#endif /* RADIO_LR_FHSS_IS_ON == 1 */ +#if (RADIO_GENERIC_CONFIG_ENABLE == 1) + uint8_t syncword[8] = {0}; + 800944e: f107 032c add.w r3, r7, #44 @ 0x2c + 8009452: 2200 movs r2, #0 + 8009454: 601a str r2, [r3, #0] + 8009456: 605a str r2, [r3, #4] + RadioModems_t radio_modem; + RFW_DeInit( ); /* switch Off FwPacketDecoding by default */ + 8009458: f001 fec8 bl 800b1ec + switch( modem ) + 800945c: 7bfb ldrb r3, [r7, #15] + 800945e: 2b03 cmp r3, #3 + 8009460: f200 8205 bhi.w 800986e + 8009464: a201 add r2, pc, #4 @ (adr r2, 800946c ) + 8009466: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 800946a: bf00 nop + 800946c: 080095f1 .word 0x080095f1 + 8009470: 08009739 .word 0x08009739 + 8009474: 08009831 .word 0x08009831 + 8009478: 0800947d .word 0x0800947d + { + case GENERIC_MSK: + if( config->msk.SyncWordLength > 8 ) + 800947c: 68bb ldr r3, [r7, #8] + 800947e: 7c9b ldrb r3, [r3, #18] + 8009480: 2b08 cmp r3, #8 + 8009482: d902 bls.n 800948a + { + return -1; + 8009484: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff + 8009488: e206 b.n 8009898 + } + else + { + RADIO_MEMCPY8( syncword, config->msk.SyncWord, config->msk.SyncWordLength ); + 800948a: 68bb ldr r3, [r7, #8] + 800948c: 6899 ldr r1, [r3, #8] + 800948e: 68bb ldr r3, [r7, #8] + 8009490: 7c9b ldrb r3, [r3, #18] + 8009492: 461a mov r2, r3 + 8009494: f107 032c add.w r3, r7, #44 @ 0x2c + 8009498: 4618 mov r0, r3 + 800949a: f003 fec7 bl 800d22c + } + if( ( config->msk.BitRate == 0 ) ) + 800949e: 68bb ldr r3, [r7, #8] + 80094a0: 681b ldr r3, [r3, #0] + 80094a2: 2b00 cmp r3, #0 + 80094a4: d102 bne.n 80094ac + { + return -1; + 80094a6: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff + 80094aa: e1f5 b.n 8009898 + } + else if( config->msk.BitRate <= 10000 ) + 80094ac: 68bb ldr r3, [r7, #8] + 80094ae: 681b ldr r3, [r3, #0] + 80094b0: f242 7210 movw r2, #10000 @ 0x2710 + 80094b4: 4293 cmp r3, r2 + 80094b6: d813 bhi.n 80094e0 + { + /*max msk modulator datarate is 10kbps*/ + radio_modem = MODEM_MSK; + 80094b8: 2302 movs r3, #2 + 80094ba: f887 3037 strb.w r3, [r7, #55] @ 0x37 + SubgRf.PacketParams.PacketType = PACKET_TYPE_GMSK; + 80094be: 4b99 ldr r3, [pc, #612] @ (8009724 ) + 80094c0: 2203 movs r2, #3 + 80094c2: 739a strb r2, [r3, #14] + SubgRf.ModulationParams.PacketType = PACKET_TYPE_GMSK; + 80094c4: 4b97 ldr r3, [pc, #604] @ (8009724 ) + 80094c6: 2203 movs r2, #3 + 80094c8: f883 2038 strb.w r2, [r3, #56] @ 0x38 + SubgRf.ModulationParams.Params.Gfsk.BitRate = config->msk.BitRate; + 80094cc: 68bb ldr r3, [r7, #8] + 80094ce: 681b ldr r3, [r3, #0] + 80094d0: 4a94 ldr r2, [pc, #592] @ (8009724 ) + 80094d2: 63d3 str r3, [r2, #60] @ 0x3c + SubgRf.ModulationParams.Params.Gfsk.ModulationShaping = ( RadioModShapings_t ) config->msk.ModulationShaping; + 80094d4: 68bb ldr r3, [r7, #8] + 80094d6: 7cda ldrb r2, [r3, #19] + 80094d8: 4b92 ldr r3, [pc, #584] @ (8009724 ) + 80094da: f883 2044 strb.w r2, [r3, #68] @ 0x44 + 80094de: e017 b.n 8009510 + } + else + { + radio_modem = MODEM_FSK; + 80094e0: 2300 movs r3, #0 + 80094e2: f887 3037 strb.w r3, [r7, #55] @ 0x37 + SubgRf.PacketParams.PacketType = PACKET_TYPE_GFSK; + 80094e6: 4b8f ldr r3, [pc, #572] @ (8009724 ) + 80094e8: 2200 movs r2, #0 + 80094ea: 739a strb r2, [r3, #14] + SubgRf.ModulationParams.PacketType = PACKET_TYPE_GFSK; + 80094ec: 4b8d ldr r3, [pc, #564] @ (8009724 ) + 80094ee: 2200 movs r2, #0 + 80094f0: f883 2038 strb.w r2, [r3, #56] @ 0x38 + SubgRf.ModulationParams.Params.Gfsk.BitRate = config->msk.BitRate; + 80094f4: 68bb ldr r3, [r7, #8] + 80094f6: 681b ldr r3, [r3, #0] + 80094f8: 4a8a ldr r2, [pc, #552] @ (8009724 ) + 80094fa: 63d3 str r3, [r2, #60] @ 0x3c + SubgRf.ModulationParams.Params.Gfsk.ModulationShaping = ( RadioModShapings_t ) config->msk.ModulationShaping; + 80094fc: 68bb ldr r3, [r7, #8] + 80094fe: 7cda ldrb r2, [r3, #19] + 8009500: 4b88 ldr r3, [pc, #544] @ (8009724 ) + 8009502: f883 2044 strb.w r2, [r3, #68] @ 0x44 + /*do msk with gfsk modulator*/ + SubgRf.ModulationParams.Params.Gfsk.Fdev = config->msk.BitRate / 4; + 8009506: 68bb ldr r3, [r7, #8] + 8009508: 681b ldr r3, [r3, #0] + 800950a: 089b lsrs r3, r3, #2 + 800950c: 4a85 ldr r2, [pc, #532] @ (8009724 ) + 800950e: 6413 str r3, [r2, #64] @ 0x40 + } + + SubgRf.PacketParams.Params.Gfsk.PreambleLength = ( config->msk.PreambleLen ) << 3; // convert byte into bit + 8009510: 68bb ldr r3, [r7, #8] + 8009512: 685b ldr r3, [r3, #4] + 8009514: b29b uxth r3, r3 + 8009516: 00db lsls r3, r3, #3 + 8009518: b29a uxth r2, r3 + 800951a: 4b82 ldr r3, [pc, #520] @ (8009724 ) + 800951c: 821a strh r2, [r3, #16] + SubgRf.PacketParams.Params.Gfsk.PreambleMinDetect = RADIO_PREAMBLE_DETECTOR_08_BITS; // don't care in tx + 800951e: 4b81 ldr r3, [pc, #516] @ (8009724 ) + 8009520: 2204 movs r2, #4 + 8009522: 749a strb r2, [r3, #18] + SubgRf.PacketParams.Params.Gfsk.SyncWordLength = ( config->msk.SyncWordLength ) << 3; // convert byte into bit + 8009524: 68bb ldr r3, [r7, #8] + 8009526: 7c9b ldrb r3, [r3, #18] + 8009528: 00db lsls r3, r3, #3 + 800952a: b2da uxtb r2, r3 + 800952c: 4b7d ldr r3, [pc, #500] @ (8009724 ) + 800952e: 74da strb r2, [r3, #19] + SubgRf.PacketParams.Params.Gfsk.AddrComp = RADIO_ADDRESSCOMP_FILT_OFF; // don't care in tx + 8009530: 4b7c ldr r3, [pc, #496] @ (8009724 ) + 8009532: 2200 movs r2, #0 + 8009534: 751a strb r2, [r3, #20] + + if( ( config->msk.Whitening == RADIO_FSK_DC_IBM_WHITENING ) + 8009536: 68bb ldr r3, [r7, #8] + 8009538: 7d9b ldrb r3, [r3, #22] + 800953a: 2b02 cmp r3, #2 + 800953c: d003 beq.n 8009546 + || ( config->msk.HeaderType == RADIO_FSK_PACKET_2BYTES_LENGTH ) ) + 800953e: 68bb ldr r3, [r7, #8] + 8009540: 7d1b ldrb r3, [r3, #20] + 8009542: 2b02 cmp r3, #2 + 8009544: d12b bne.n 800959e + { + /* Supports only RADIO_FSK_CRC_2_BYTES_IBM or RADIO_FSK_CRC_2_BYTES_CCIT */ + if( ( config->msk.CrcLength != RADIO_FSK_CRC_2_BYTES_IBM ) && ( config->msk.CrcLength != RADIO_FSK_CRC_2_BYTES_CCIT ) + 8009546: 68bb ldr r3, [r7, #8] + 8009548: 7d5b ldrb r3, [r3, #21] + 800954a: 2bf1 cmp r3, #241 @ 0xf1 + 800954c: d00a beq.n 8009564 + 800954e: 68bb ldr r3, [r7, #8] + 8009550: 7d5b ldrb r3, [r3, #21] + 8009552: 2bf2 cmp r3, #242 @ 0xf2 + 8009554: d006 beq.n 8009564 + && ( config->msk.CrcLength != RADIO_FSK_CRC_OFF ) ) + 8009556: 68bb ldr r3, [r7, #8] + 8009558: 7d5b ldrb r3, [r3, #21] + 800955a: 2b01 cmp r3, #1 + 800955c: d002 beq.n 8009564 + { + return -1; + 800955e: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff + 8009562: e199 b.n 8009898 + } + ConfigGeneric_t ConfigGeneric; + /*msk and fsk are union, no need for copy as fsk/msk struct are on same address*/ + ConfigGeneric.TxConfig = config; + 8009564: 68bb ldr r3, [r7, #8] + 8009566: 623b str r3, [r7, #32] + ConfigGeneric.rtx = CONFIG_TX; + 8009568: 2301 movs r3, #1 + 800956a: f887 3028 strb.w r3, [r7, #40] @ 0x28 + if( 0UL != RFW_Init( &ConfigGeneric, RadioEvents, &TxTimeoutTimer ) ) + 800956e: 4b6e ldr r3, [pc, #440] @ (8009728 ) + 8009570: 6819 ldr r1, [r3, #0] + 8009572: f107 0320 add.w r3, r7, #32 + 8009576: 4a6d ldr r2, [pc, #436] @ (800972c ) + 8009578: 4618 mov r0, r3 + 800957a: f001 fd9d bl 800b0b8 + 800957e: 4603 mov r3, r0 + 8009580: 2b00 cmp r3, #0 + 8009582: d002 beq.n 800958a + { + return -1; + 8009584: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff + 8009588: e186 b.n 8009898 + } + /* whitening off, will be processed by FW, switch off built-in radio whitening */ + SubgRf.PacketParams.Params.Gfsk.DcFree = ( RadioDcFree_t ) RADIO_FSK_DC_FREE_OFF; + 800958a: 4b66 ldr r3, [pc, #408] @ (8009724 ) + 800958c: 2200 movs r2, #0 + 800958e: 761a strb r2, [r3, #24] + /* Crc processed by FW, switch off built-in radio Crc */ + SubgRf.PacketParams.Params.Gfsk.CrcLength = ( RadioCrcTypes_t ) RADIO_CRC_OFF; + 8009590: 4b64 ldr r3, [pc, #400] @ (8009724 ) + 8009592: 2201 movs r2, #1 + 8009594: 75da strb r2, [r3, #23] + /* length contained in Tx, but will be processed by FW after de-whitening */ + SubgRf.PacketParams.Params.Gfsk.HeaderType = ( RadioPacketLengthModes_t ) RADIO_PACKET_FIXED_LENGTH; + 8009596: 4b63 ldr r3, [pc, #396] @ (8009724 ) + 8009598: 2200 movs r2, #0 + 800959a: 755a strb r2, [r3, #21] + { + 800959c: e00b b.n 80095b6 + } + else + { + SubgRf.PacketParams.Params.Gfsk.CrcLength = ( RadioCrcTypes_t ) config->msk.CrcLength; + 800959e: 68bb ldr r3, [r7, #8] + 80095a0: 7d5a ldrb r2, [r3, #21] + 80095a2: 4b60 ldr r3, [pc, #384] @ (8009724 ) + 80095a4: 75da strb r2, [r3, #23] + SubgRf.PacketParams.Params.Gfsk.DcFree = ( RadioDcFree_t ) config->msk.Whitening; + 80095a6: 68bb ldr r3, [r7, #8] + 80095a8: 7d9a ldrb r2, [r3, #22] + 80095aa: 4b5e ldr r3, [pc, #376] @ (8009724 ) + 80095ac: 761a strb r2, [r3, #24] + SubgRf.PacketParams.Params.Gfsk.HeaderType = ( RadioPacketLengthModes_t ) config->msk.HeaderType; + 80095ae: 68bb ldr r3, [r7, #8] + 80095b0: 7d1a ldrb r2, [r3, #20] + 80095b2: 4b5c ldr r3, [pc, #368] @ (8009724 ) + 80095b4: 755a strb r2, [r3, #21] + } + + RadioStandby( ); + 80095b6: f7ff f864 bl 8008682 + RadioSetModem( radio_modem ); + 80095ba: f897 3037 ldrb.w r3, [r7, #55] @ 0x37 + 80095be: 4618 mov r0, r3 + 80095c0: f7fe f9f0 bl 80079a4 + + SUBGRF_SetModulationParams( &SubgRf.ModulationParams ); + 80095c4: 485a ldr r0, [pc, #360] @ (8009730 ) + 80095c6: f000 fe8d bl 800a2e4 + SUBGRF_SetPacketParams( &SubgRf.PacketParams ); + 80095ca: 485a ldr r0, [pc, #360] @ (8009734 ) + 80095cc: f000 ff58 bl 800a480 + SUBGRF_SetSyncWord( syncword ); + 80095d0: f107 032c add.w r3, r7, #44 @ 0x2c + 80095d4: 4618 mov r0, r3 + 80095d6: f000 fa18 bl 8009a0a + SUBGRF_SetWhiteningSeed( config->msk.whiteSeed ); + 80095da: 68bb ldr r3, [r7, #8] + 80095dc: 8a1b ldrh r3, [r3, #16] + 80095de: 4618 mov r0, r3 + 80095e0: f000 fa62 bl 8009aa8 + SUBGRF_SetCrcPolynomial( config->msk.CrcPolynomial ); + 80095e4: 68bb ldr r3, [r7, #8] + 80095e6: 899b ldrh r3, [r3, #12] + 80095e8: 4618 mov r0, r3 + 80095ea: f000 fa3d bl 8009a68 + break; + 80095ee: e13f b.n 8009870 + case GENERIC_FSK: + if( config->fsk.BitRate == 0 ) + 80095f0: 68bb ldr r3, [r7, #8] + 80095f2: 681b ldr r3, [r3, #0] + 80095f4: 2b00 cmp r3, #0 + 80095f6: d102 bne.n 80095fe + { + return -1; + 80095f8: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff + 80095fc: e14c b.n 8009898 + } + if( config->fsk.SyncWordLength > 8 ) + 80095fe: 68bb ldr r3, [r7, #8] + 8009600: 7c9b ldrb r3, [r3, #18] + 8009602: 2b08 cmp r3, #8 + 8009604: d902 bls.n 800960c + { + return -1; + 8009606: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff + 800960a: e145 b.n 8009898 + } + else + { + RADIO_MEMCPY8( syncword, config->fsk.SyncWord, config->fsk.SyncWordLength ); + 800960c: 68bb ldr r3, [r7, #8] + 800960e: 6899 ldr r1, [r3, #8] + 8009610: 68bb ldr r3, [r7, #8] + 8009612: 7c9b ldrb r3, [r3, #18] + 8009614: 461a mov r2, r3 + 8009616: f107 032c add.w r3, r7, #44 @ 0x2c + 800961a: 4618 mov r0, r3 + 800961c: f003 fe06 bl 800d22c + } + SubgRf.ModulationParams.PacketType = PACKET_TYPE_GFSK; + 8009620: 4b40 ldr r3, [pc, #256] @ (8009724 ) + 8009622: 2200 movs r2, #0 + 8009624: f883 2038 strb.w r2, [r3, #56] @ 0x38 + SubgRf.ModulationParams.Params.Gfsk.BitRate = config->fsk.BitRate; + 8009628: 68bb ldr r3, [r7, #8] + 800962a: 681b ldr r3, [r3, #0] + 800962c: 4a3d ldr r2, [pc, #244] @ (8009724 ) + 800962e: 63d3 str r3, [r2, #60] @ 0x3c + SubgRf.ModulationParams.Params.Gfsk.ModulationShaping = ( RadioModShapings_t ) config->fsk.ModulationShaping; + 8009630: 68bb ldr r3, [r7, #8] + 8009632: 7cda ldrb r2, [r3, #19] + 8009634: 4b3b ldr r3, [pc, #236] @ (8009724 ) + 8009636: f883 2044 strb.w r2, [r3, #68] @ 0x44 + SubgRf.ModulationParams.Params.Gfsk.Fdev = config->fsk.FrequencyDeviation; + 800963a: 68bb ldr r3, [r7, #8] + 800963c: 699b ldr r3, [r3, #24] + 800963e: 4a39 ldr r2, [pc, #228] @ (8009724 ) + 8009640: 6413 str r3, [r2, #64] @ 0x40 + + SubgRf.PacketParams.PacketType = PACKET_TYPE_GFSK; + 8009642: 4b38 ldr r3, [pc, #224] @ (8009724 ) + 8009644: 2200 movs r2, #0 + 8009646: 739a strb r2, [r3, #14] + SubgRf.PacketParams.Params.Gfsk.PreambleLength = ( config->fsk.PreambleLen ) << 3; // convert byte into bit + 8009648: 68bb ldr r3, [r7, #8] + 800964a: 685b ldr r3, [r3, #4] + 800964c: b29b uxth r3, r3 + 800964e: 00db lsls r3, r3, #3 + 8009650: b29a uxth r2, r3 + 8009652: 4b34 ldr r3, [pc, #208] @ (8009724 ) + 8009654: 821a strh r2, [r3, #16] + SubgRf.PacketParams.Params.Gfsk.PreambleMinDetect = RADIO_PREAMBLE_DETECTOR_08_BITS; // don't care in tx + 8009656: 4b33 ldr r3, [pc, #204] @ (8009724 ) + 8009658: 2204 movs r2, #4 + 800965a: 749a strb r2, [r3, #18] + SubgRf.PacketParams.Params.Gfsk.SyncWordLength = ( config->fsk.SyncWordLength ) << 3; // convert byte into bit + 800965c: 68bb ldr r3, [r7, #8] + 800965e: 7c9b ldrb r3, [r3, #18] + 8009660: 00db lsls r3, r3, #3 + 8009662: b2da uxtb r2, r3 + 8009664: 4b2f ldr r3, [pc, #188] @ (8009724 ) + 8009666: 74da strb r2, [r3, #19] + SubgRf.PacketParams.Params.Gfsk.AddrComp = RADIO_ADDRESSCOMP_FILT_OFF; // don't care in tx + 8009668: 4b2e ldr r3, [pc, #184] @ (8009724 ) + 800966a: 2200 movs r2, #0 + 800966c: 751a strb r2, [r3, #20] + + if( ( config->fsk.Whitening == RADIO_FSK_DC_IBM_WHITENING ) + 800966e: 68bb ldr r3, [r7, #8] + 8009670: 7d9b ldrb r3, [r3, #22] + 8009672: 2b02 cmp r3, #2 + 8009674: d003 beq.n 800967e + || ( config->fsk.HeaderType == RADIO_FSK_PACKET_2BYTES_LENGTH ) ) + 8009676: 68bb ldr r3, [r7, #8] + 8009678: 7d1b ldrb r3, [r3, #20] + 800967a: 2b02 cmp r3, #2 + 800967c: d12a bne.n 80096d4 + { + /* Supports only RADIO_FSK_CRC_2_BYTES_IBM or RADIO_FSK_CRC_2_BYTES_CCIT */ + if( ( config->fsk.CrcLength != RADIO_FSK_CRC_2_BYTES_IBM ) && ( config->fsk.CrcLength != RADIO_FSK_CRC_2_BYTES_CCIT ) + 800967e: 68bb ldr r3, [r7, #8] + 8009680: 7d5b ldrb r3, [r3, #21] + 8009682: 2bf1 cmp r3, #241 @ 0xf1 + 8009684: d00a beq.n 800969c + 8009686: 68bb ldr r3, [r7, #8] + 8009688: 7d5b ldrb r3, [r3, #21] + 800968a: 2bf2 cmp r3, #242 @ 0xf2 + 800968c: d006 beq.n 800969c + && ( config->fsk.CrcLength != RADIO_FSK_CRC_OFF ) ) + 800968e: 68bb ldr r3, [r7, #8] + 8009690: 7d5b ldrb r3, [r3, #21] + 8009692: 2b01 cmp r3, #1 + 8009694: d002 beq.n 800969c + { + return -1; + 8009696: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff + 800969a: e0fd b.n 8009898 + } + ConfigGeneric_t ConfigGeneric; + ConfigGeneric.rtx = CONFIG_TX; + 800969c: 2301 movs r3, #1 + 800969e: 773b strb r3, [r7, #28] + ConfigGeneric.TxConfig = config; + 80096a0: 68bb ldr r3, [r7, #8] + 80096a2: 617b str r3, [r7, #20] + if( 0UL != RFW_Init( &ConfigGeneric, RadioEvents, &TxTimeoutTimer ) ) + 80096a4: 4b20 ldr r3, [pc, #128] @ (8009728 ) + 80096a6: 6819 ldr r1, [r3, #0] + 80096a8: f107 0314 add.w r3, r7, #20 + 80096ac: 4a1f ldr r2, [pc, #124] @ (800972c ) + 80096ae: 4618 mov r0, r3 + 80096b0: f001 fd02 bl 800b0b8 + 80096b4: 4603 mov r3, r0 + 80096b6: 2b00 cmp r3, #0 + 80096b8: d002 beq.n 80096c0 + { + return -1; + 80096ba: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff + 80096be: e0eb b.n 8009898 + } + /* whitening off, will be processed by FW, switch off built-in radio whitening */ + SubgRf.PacketParams.Params.Gfsk.DcFree = ( RadioDcFree_t ) RADIO_FSK_DC_FREE_OFF; + 80096c0: 4b18 ldr r3, [pc, #96] @ (8009724 ) + 80096c2: 2200 movs r2, #0 + 80096c4: 761a strb r2, [r3, #24] + /* Crc processed by FW, switch off built-in radio Crc */ + SubgRf.PacketParams.Params.Gfsk.CrcLength = ( RadioCrcTypes_t ) RADIO_CRC_OFF; + 80096c6: 4b17 ldr r3, [pc, #92] @ (8009724 ) + 80096c8: 2201 movs r2, #1 + 80096ca: 75da strb r2, [r3, #23] + /* length contained in Tx, but will be processed by FW after de-whitening */ + SubgRf.PacketParams.Params.Gfsk.HeaderType = ( RadioPacketLengthModes_t ) RADIO_PACKET_FIXED_LENGTH; + 80096cc: 4b15 ldr r3, [pc, #84] @ (8009724 ) + 80096ce: 2200 movs r2, #0 + 80096d0: 755a strb r2, [r3, #21] + { + 80096d2: e00b b.n 80096ec + } + else + { + SubgRf.PacketParams.Params.Gfsk.CrcLength = ( RadioCrcTypes_t ) config->fsk.CrcLength; + 80096d4: 68bb ldr r3, [r7, #8] + 80096d6: 7d5a ldrb r2, [r3, #21] + 80096d8: 4b12 ldr r3, [pc, #72] @ (8009724 ) + 80096da: 75da strb r2, [r3, #23] + SubgRf.PacketParams.Params.Gfsk.DcFree = ( RadioDcFree_t ) config->fsk.Whitening; + 80096dc: 68bb ldr r3, [r7, #8] + 80096de: 7d9a ldrb r2, [r3, #22] + 80096e0: 4b10 ldr r3, [pc, #64] @ (8009724 ) + 80096e2: 761a strb r2, [r3, #24] + SubgRf.PacketParams.Params.Gfsk.HeaderType = ( RadioPacketLengthModes_t ) config->fsk.HeaderType; + 80096e4: 68bb ldr r3, [r7, #8] + 80096e6: 7d1a ldrb r2, [r3, #20] + 80096e8: 4b0e ldr r3, [pc, #56] @ (8009724 ) + 80096ea: 755a strb r2, [r3, #21] + } + + RadioStandby( ); + 80096ec: f7fe ffc9 bl 8008682 + RadioSetModem( MODEM_FSK ); + 80096f0: 2000 movs r0, #0 + 80096f2: f7fe f957 bl 80079a4 + SUBGRF_SetModulationParams( &SubgRf.ModulationParams ); + 80096f6: 480e ldr r0, [pc, #56] @ (8009730 ) + 80096f8: f000 fdf4 bl 800a2e4 + SUBGRF_SetPacketParams( &SubgRf.PacketParams ); + 80096fc: 480d ldr r0, [pc, #52] @ (8009734 ) + 80096fe: f000 febf bl 800a480 + SUBGRF_SetSyncWord( syncword ); + 8009702: f107 032c add.w r3, r7, #44 @ 0x2c + 8009706: 4618 mov r0, r3 + 8009708: f000 f97f bl 8009a0a + SUBGRF_SetWhiteningSeed( config->fsk.whiteSeed ); + 800970c: 68bb ldr r3, [r7, #8] + 800970e: 8a1b ldrh r3, [r3, #16] + 8009710: 4618 mov r0, r3 + 8009712: f000 f9c9 bl 8009aa8 + SUBGRF_SetCrcPolynomial( config->fsk.CrcPolynomial ); + 8009716: 68bb ldr r3, [r7, #8] + 8009718: 899b ldrh r3, [r3, #12] + 800971a: 4618 mov r0, r3 + 800971c: f000 f9a4 bl 8009a68 + break; + 8009720: e0a6 b.n 8009870 + 8009722: bf00 nop + 8009724: 20000300 .word 0x20000300 + 8009728: 200002fc .word 0x200002fc + 800972c: 2000035c .word 0x2000035c + 8009730: 20000338 .word 0x20000338 + 8009734: 2000030e .word 0x2000030e + case GENERIC_LORA: + SubgRf.ModulationParams.PacketType = PACKET_TYPE_LORA; + 8009738: 4b59 ldr r3, [pc, #356] @ (80098a0 ) + 800973a: 2201 movs r2, #1 + 800973c: f883 2038 strb.w r2, [r3, #56] @ 0x38 + SubgRf.ModulationParams.Params.LoRa.SpreadingFactor = ( RadioLoRaSpreadingFactors_t ) config->lora.SpreadingFactor; + 8009740: 68bb ldr r3, [r7, #8] + 8009742: 781a ldrb r2, [r3, #0] + 8009744: 4b56 ldr r3, [pc, #344] @ (80098a0 ) + 8009746: f883 2050 strb.w r2, [r3, #80] @ 0x50 + SubgRf.ModulationParams.Params.LoRa.Bandwidth = ( RadioLoRaBandwidths_t ) config->lora.Bandwidth; + 800974a: 68bb ldr r3, [r7, #8] + 800974c: 785a ldrb r2, [r3, #1] + 800974e: 4b54 ldr r3, [pc, #336] @ (80098a0 ) + 8009750: f883 2051 strb.w r2, [r3, #81] @ 0x51 + SubgRf.ModulationParams.Params.LoRa.CodingRate = ( RadioLoRaCodingRates_t ) config->lora.Coderate; + 8009754: 68bb ldr r3, [r7, #8] + 8009756: 789a ldrb r2, [r3, #2] + 8009758: 4b51 ldr r3, [pc, #324] @ (80098a0 ) + 800975a: f883 2052 strb.w r2, [r3, #82] @ 0x52 + switch( config->lora.LowDatarateOptimize ) + 800975e: 68bb ldr r3, [r7, #8] + 8009760: 78db ldrb r3, [r3, #3] + 8009762: 2b02 cmp r3, #2 + 8009764: d010 beq.n 8009788 + 8009766: 2b02 cmp r3, #2 + 8009768: dc20 bgt.n 80097ac + 800976a: 2b00 cmp r3, #0 + 800976c: d002 beq.n 8009774 + 800976e: 2b01 cmp r3, #1 + 8009770: d005 beq.n 800977e + { + SubgRf.ModulationParams.Params.LoRa.LowDatarateOptimize = 0; + } + break; + default: + break; + 8009772: e01b b.n 80097ac + SubgRf.ModulationParams.Params.LoRa.LowDatarateOptimize = 0; + 8009774: 4b4a ldr r3, [pc, #296] @ (80098a0 ) + 8009776: 2200 movs r2, #0 + 8009778: f883 2053 strb.w r2, [r3, #83] @ 0x53 + break; + 800977c: e017 b.n 80097ae + SubgRf.ModulationParams.Params.LoRa.LowDatarateOptimize = 1; + 800977e: 4b48 ldr r3, [pc, #288] @ (80098a0 ) + 8009780: 2201 movs r2, #1 + 8009782: f883 2053 strb.w r2, [r3, #83] @ 0x53 + break; + 8009786: e012 b.n 80097ae + if( ( config->lora.SpreadingFactor == RADIO_LORA_SF11 ) || ( config->lora.SpreadingFactor == RADIO_LORA_SF12 ) ) + 8009788: 68bb ldr r3, [r7, #8] + 800978a: 781b ldrb r3, [r3, #0] + 800978c: 2b0b cmp r3, #11 + 800978e: d003 beq.n 8009798 + 8009790: 68bb ldr r3, [r7, #8] + 8009792: 781b ldrb r3, [r3, #0] + 8009794: 2b0c cmp r3, #12 + 8009796: d104 bne.n 80097a2 + SubgRf.ModulationParams.Params.LoRa.LowDatarateOptimize = 1; + 8009798: 4b41 ldr r3, [pc, #260] @ (80098a0 ) + 800979a: 2201 movs r2, #1 + 800979c: f883 2053 strb.w r2, [r3, #83] @ 0x53 + break; + 80097a0: e005 b.n 80097ae + SubgRf.ModulationParams.Params.LoRa.LowDatarateOptimize = 0; + 80097a2: 4b3f ldr r3, [pc, #252] @ (80098a0 ) + 80097a4: 2200 movs r2, #0 + 80097a6: f883 2053 strb.w r2, [r3, #83] @ 0x53 + break; + 80097aa: e000 b.n 80097ae + break; + 80097ac: bf00 nop + } + + SubgRf.PacketParams.PacketType = PACKET_TYPE_LORA; + 80097ae: 4b3c ldr r3, [pc, #240] @ (80098a0 ) + 80097b0: 2201 movs r2, #1 + 80097b2: 739a strb r2, [r3, #14] + SubgRf.PacketParams.Params.LoRa.PreambleLength = config->lora.PreambleLen; + 80097b4: 68bb ldr r3, [r7, #8] + 80097b6: 889a ldrh r2, [r3, #4] + 80097b8: 4b39 ldr r3, [pc, #228] @ (80098a0 ) + 80097ba: 839a strh r2, [r3, #28] + SubgRf.PacketParams.Params.LoRa.HeaderType = ( RadioLoRaPacketLengthsMode_t ) config->lora.LengthMode; + 80097bc: 68bb ldr r3, [r7, #8] + 80097be: 799a ldrb r2, [r3, #6] + 80097c0: 4b37 ldr r3, [pc, #220] @ (80098a0 ) + 80097c2: 779a strb r2, [r3, #30] + SubgRf.PacketParams.Params.LoRa.CrcMode = ( RadioLoRaCrcModes_t ) config->lora.CrcMode; + 80097c4: 68bb ldr r3, [r7, #8] + 80097c6: 79da ldrb r2, [r3, #7] + 80097c8: 4b35 ldr r3, [pc, #212] @ (80098a0 ) + 80097ca: f883 2020 strb.w r2, [r3, #32] + SubgRf.PacketParams.Params.LoRa.InvertIQ = ( RadioLoRaIQModes_t ) config->lora.IqInverted; + 80097ce: 68bb ldr r3, [r7, #8] + 80097d0: 7a1a ldrb r2, [r3, #8] + 80097d2: 4b33 ldr r3, [pc, #204] @ (80098a0 ) + 80097d4: f883 2021 strb.w r2, [r3, #33] @ 0x21 + + RadioStandby( ); + 80097d8: f7fe ff53 bl 8008682 + RadioSetModem( MODEM_LORA ); + 80097dc: 2001 movs r0, #1 + 80097de: f7fe f8e1 bl 80079a4 + SUBGRF_SetModulationParams( &SubgRf.ModulationParams ); + 80097e2: 4830 ldr r0, [pc, #192] @ (80098a4 ) + 80097e4: f000 fd7e bl 800a2e4 + SUBGRF_SetPacketParams( &SubgRf.PacketParams ); + 80097e8: 482f ldr r0, [pc, #188] @ (80098a8 ) + 80097ea: f000 fe49 bl 800a480 + + /* WORKAROUND - Modulation Quality with 500 kHz LoRa Bandwidth, see STM32WL Erratasheet */ + if( SubgRf.ModulationParams.Params.LoRa.Bandwidth == LORA_BW_500 ) + 80097ee: 4b2c ldr r3, [pc, #176] @ (80098a0 ) + 80097f0: f893 3051 ldrb.w r3, [r3, #81] @ 0x51 + 80097f4: 2b06 cmp r3, #6 + 80097f6: d10d bne.n 8009814 + { + // RegTxModulation = @address 0x0889 + SUBGRF_WriteRegister( SUBGHZ_SDCFG0R, SUBGRF_ReadRegister( SUBGHZ_SDCFG0R ) & ~( 1 << 2 ) ); + 80097f8: f640 0089 movw r0, #2185 @ 0x889 + 80097fc: f000 ffa8 bl 800a750 + 8009800: 4603 mov r3, r0 + 8009802: f023 0304 bic.w r3, r3, #4 + 8009806: b2db uxtb r3, r3 + 8009808: 4619 mov r1, r3 + 800980a: f640 0089 movw r0, #2185 @ 0x889 + 800980e: f000 ff7d bl 800a70c + { + // RegTxModulation = @address 0x0889 + SUBGRF_WriteRegister( SUBGHZ_SDCFG0R, SUBGRF_ReadRegister( SUBGHZ_SDCFG0R ) | ( 1 << 2 ) ); + } + /* WORKAROUND END */ + break; + 8009812: e02d b.n 8009870 + SUBGRF_WriteRegister( SUBGHZ_SDCFG0R, SUBGRF_ReadRegister( SUBGHZ_SDCFG0R ) | ( 1 << 2 ) ); + 8009814: f640 0089 movw r0, #2185 @ 0x889 + 8009818: f000 ff9a bl 800a750 + 800981c: 4603 mov r3, r0 + 800981e: f043 0304 orr.w r3, r3, #4 + 8009822: b2db uxtb r3, r3 + 8009824: 4619 mov r1, r3 + 8009826: f640 0089 movw r0, #2185 @ 0x889 + 800982a: f000 ff6f bl 800a70c + break; + 800982e: e01f b.n 8009870 + case GENERIC_BPSK: + if( ( config->bpsk.BitRate == 0 ) || ( config->bpsk.BitRate > 1000 ) ) + 8009830: 68bb ldr r3, [r7, #8] + 8009832: 681b ldr r3, [r3, #0] + 8009834: 2b00 cmp r3, #0 + 8009836: d004 beq.n 8009842 + 8009838: 68bb ldr r3, [r7, #8] + 800983a: 681b ldr r3, [r3, #0] + 800983c: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 + 8009840: d902 bls.n 8009848 + { + return -1; + 8009842: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff + 8009846: e027 b.n 8009898 + } + RadioSetModem( MODEM_BPSK ); + 8009848: 2003 movs r0, #3 + 800984a: f7fe f8ab bl 80079a4 + SubgRf.ModulationParams.PacketType = PACKET_TYPE_BPSK; + 800984e: 4b14 ldr r3, [pc, #80] @ (80098a0 ) + 8009850: 2202 movs r2, #2 + 8009852: f883 2038 strb.w r2, [r3, #56] @ 0x38 + SubgRf.ModulationParams.Params.Bpsk.BitRate = config->bpsk.BitRate; + 8009856: 68bb ldr r3, [r7, #8] + 8009858: 681b ldr r3, [r3, #0] + 800985a: 4a11 ldr r2, [pc, #68] @ (80098a0 ) + 800985c: 6493 str r3, [r2, #72] @ 0x48 + SubgRf.ModulationParams.Params.Bpsk.ModulationShaping = MOD_SHAPING_DBPSK; + 800985e: 4b10 ldr r3, [pc, #64] @ (80098a0 ) + 8009860: 2216 movs r2, #22 + 8009862: f883 204c strb.w r2, [r3, #76] @ 0x4c + SUBGRF_SetModulationParams( &SubgRf.ModulationParams ); + 8009866: 480f ldr r0, [pc, #60] @ (80098a4 ) + 8009868: f000 fd3c bl 800a2e4 + break; + 800986c: e000 b.n 8009870 + default: + break; + 800986e: bf00 nop + } + + SubgRf.AntSwitchPaSelect = SUBGRF_SetRfTxPower( power ); + 8009870: f997 300e ldrsb.w r3, [r7, #14] + 8009874: 4618 mov r0, r3 + 8009876: f001 f87f bl 800a978 + 800987a: 4603 mov r3, r0 + 800987c: 461a mov r2, r3 + 800987e: 4b08 ldr r3, [pc, #32] @ (80098a0 ) + 8009880: f883 2056 strb.w r2, [r3, #86] @ 0x56 + RFW_SetAntSwitch( SubgRf.AntSwitchPaSelect ); + 8009884: 4b06 ldr r3, [pc, #24] @ (80098a0 ) + 8009886: f893 3056 ldrb.w r3, [r3, #86] @ 0x56 + 800988a: 4618 mov r0, r3 + 800988c: f001 fcce bl 800b22c + SubgRf.TxTimeout = timeout; + 8009890: 4a03 ldr r2, [pc, #12] @ (80098a0 ) + 8009892: 687b ldr r3, [r7, #4] + 8009894: 6053 str r3, [r2, #4] + return 0; + 8009896: 2300 movs r3, #0 +#else /* RADIO_GENERIC_CONFIG_ENABLE == 1*/ + return -1; +#endif /* RADIO_GENERIC_CONFIG_ENABLE == 0*/ +} + 8009898: 4618 mov r0, r3 + 800989a: 3738 adds r7, #56 @ 0x38 + 800989c: 46bd mov sp, r7 + 800989e: bd80 pop {r7, pc} + 80098a0: 20000300 .word 0x20000300 + 80098a4: 20000338 .word 0x20000338 + 80098a8: 2000030e .word 0x2000030e + +080098ac : + return ( prbs31_val - 1 ) % ( max ); +} +#endif /* RADIO_LR_FHSS_IS_ON == 1 */ + +static radio_status_t RadioLrFhssSetCfg( const radio_lr_fhss_cfg_params_t *cfg_params ) +{ + 80098ac: b480 push {r7} + 80098ae: b085 sub sp, #20 + 80098b0: af00 add r7, sp, #0 + 80098b2: 6078 str r0, [r7, #4] + radio_status_t status = RADIO_STATUS_UNSUPPORTED_FEATURE; + 80098b4: 2301 movs r3, #1 + 80098b6: 73fb strb r3, [r7, #15] + { + return status; + } + SubgRf.lr_fhss.is_lr_fhss_on = true; +#endif /* RADIO_LR_FHSS_IS_ON == 1 */ + return status; + 80098b8: 7bfb ldrb r3, [r7, #15] +} + 80098ba: 4618 mov r0, r3 + 80098bc: 3714 adds r7, #20 + 80098be: 46bd mov sp, r7 + 80098c0: bc80 pop {r7} + 80098c2: 4770 bx lr + +080098c4 : + +static radio_status_t RadioLrFhssGetTimeOnAirInMs( const radio_lr_fhss_time_on_air_params_t *params, + uint32_t *time_on_air_in_ms ) +{ + 80098c4: b480 push {r7} + 80098c6: b083 sub sp, #12 + 80098c8: af00 add r7, sp, #0 + 80098ca: 6078 str r0, [r7, #4] + 80098cc: 6039 str r1, [r7, #0] + *time_on_air_in_ms = lr_fhss_get_time_on_air_in_ms( ¶ms->radio_lr_fhss_params.lr_fhss_params, + params->pld_len_in_bytes ); + + return RADIO_STATUS_OK; +#else + return RADIO_STATUS_UNSUPPORTED_FEATURE; + 80098ce: 2301 movs r3, #1 +#endif /* RADIO_LR_FHSS_IS_ON */ + 80098d0: 4618 mov r0, r3 + 80098d2: 370c adds r7, #12 + 80098d4: 46bd mov sp, r7 + 80098d6: bc80 pop {r7} + 80098d8: 4770 bx lr + ... + +080098dc : + */ +static DioIrqHandler RadioOnDioIrqCb; + +/* Exported functions ---------------------------------------------------------*/ +void SUBGRF_Init( DioIrqHandler dioIrq ) +{ + 80098dc: b580 push {r7, lr} + 80098de: b084 sub sp, #16 + 80098e0: af00 add r7, sp, #0 + 80098e2: 6078 str r0, [r7, #4] + if ( dioIrq != NULL) + 80098e4: 687b ldr r3, [r7, #4] + 80098e6: 2b00 cmp r3, #0 + 80098e8: d002 beq.n 80098f0 + { + RadioOnDioIrqCb = dioIrq; + 80098ea: 4a1d ldr r2, [pc, #116] @ (8009960 ) + 80098ec: 687b ldr r3, [r7, #4] + 80098ee: 6013 str r3, [r2, #0] + } + + RADIO_INIT(); + 80098f0: f7f7 f8f8 bl 8000ae4 + + /* set default SMPS current drive to default*/ + Radio_SMPS_Set(SMPS_DRIVE_SETTING_DEFAULT); + 80098f4: 2002 movs r0, #2 + 80098f6: f001 f91b bl 800ab30 + + ImageCalibrated = false; + 80098fa: 4b1a ldr r3, [pc, #104] @ (8009964 ) + 80098fc: 2200 movs r2, #0 + 80098fe: 701a strb r2, [r3, #0] + + SUBGRF_SetStandby( STDBY_RC ); + 8009900: 2000 movs r0, #0 + 8009902: f000 f97f bl 8009c04 + + // Initialize TCXO control + if (1U == RBI_IsTCXO() ) + 8009906: f003 fbcf bl 800d0a8 + 800990a: 4603 mov r3, r0 + 800990c: 2b01 cmp r3, #1 + 800990e: d10e bne.n 800992e + { + SUBGRF_SetTcxoMode( TCXO_CTRL_VOLTAGE, RF_WAKEUP_TIME << 6 );// 100 ms + 8009910: 2140 movs r1, #64 @ 0x40 + 8009912: 2001 movs r0, #1 + 8009914: f000 fb8a bl 800a02c + SUBGRF_WriteRegister( REG_XTA_TRIM, 0x00 ); + 8009918: 2100 movs r1, #0 + 800991a: f640 1011 movw r0, #2321 @ 0x911 + 800991e: f000 fef5 bl 800a70c + + /*enable calibration for cut1.1 and later*/ + CalibrationParams_t calibParam; + calibParam.Value = 0x7F; + 8009922: 237f movs r3, #127 @ 0x7f + 8009924: 733b strb r3, [r7, #12] + SUBGRF_Calibrate( calibParam ); + 8009926: 7b38 ldrb r0, [r7, #12] + 8009928: f000 fa8d bl 8009e46 + 800992c: e009 b.n 8009942 + } + else + { + SUBGRF_WriteRegister( REG_XTA_TRIM, XTAL_DEFAULT_CAP_VALUE ); + 800992e: 2120 movs r1, #32 + 8009930: f640 1011 movw r0, #2321 @ 0x911 + 8009934: f000 feea bl 800a70c + SUBGRF_WriteRegister( REG_XTB_TRIM, XTAL_DEFAULT_CAP_VALUE ); + 8009938: 2120 movs r1, #32 + 800993a: f640 1012 movw r0, #2322 @ 0x912 + 800993e: f000 fee5 bl 800a70c + } + + /* WORKAROUND - Trimming the output voltage power_ldo to 3.3V */ + SUBGRF_WriteRegister(REG_DRV_CTRL, 0x7 << 1); + 8009942: 210e movs r1, #14 + 8009944: f640 101f movw r0, #2335 @ 0x91f + 8009948: f000 fee0 bl 800a70c + + /* Init RF Switch */ + RBI_Init(); + 800994c: f003 fb90 bl 800d070 + + OperatingMode = MODE_STDBY_RC; + 8009950: 4b05 ldr r3, [pc, #20] @ (8009968 ) + 8009952: 2201 movs r2, #1 + 8009954: 701a strb r2, [r3, #0] +} + 8009956: bf00 nop + 8009958: 3710 adds r7, #16 + 800995a: 46bd mov sp, r7 + 800995c: bd80 pop {r7, pc} + 800995e: bf00 nop + 8009960: 20000398 .word 0x20000398 + 8009964: 20000394 .word 0x20000394 + 8009968: 2000038c .word 0x2000038c + +0800996c : + +RadioOperatingModes_t SUBGRF_GetOperatingMode( void ) +{ + 800996c: b480 push {r7} + 800996e: af00 add r7, sp, #0 + return OperatingMode; + 8009970: 4b02 ldr r3, [pc, #8] @ (800997c ) + 8009972: 781b ldrb r3, [r3, #0] +} + 8009974: 4618 mov r0, r3 + 8009976: 46bd mov sp, r7 + 8009978: bc80 pop {r7} + 800997a: 4770 bx lr + 800997c: 2000038c .word 0x2000038c + +08009980 : + +void SUBGRF_SetPayload( uint8_t *payload, uint8_t size ) +{ + 8009980: b580 push {r7, lr} + 8009982: b082 sub sp, #8 + 8009984: af00 add r7, sp, #0 + 8009986: 6078 str r0, [r7, #4] + 8009988: 460b mov r3, r1 + 800998a: 70fb strb r3, [r7, #3] + SUBGRF_WriteBuffer( 0x00, payload, size ); + 800998c: 78fb ldrb r3, [r7, #3] + 800998e: 461a mov r2, r3 + 8009990: 6879 ldr r1, [r7, #4] + 8009992: 2000 movs r0, #0 + 8009994: f000 ff40 bl 800a818 +} + 8009998: bf00 nop + 800999a: 3708 adds r7, #8 + 800999c: 46bd mov sp, r7 + 800999e: bd80 pop {r7, pc} + +080099a0 : + +uint8_t SUBGRF_GetPayload( uint8_t *buffer, uint8_t *size, uint8_t maxSize ) +{ + 80099a0: b580 push {r7, lr} + 80099a2: b086 sub sp, #24 + 80099a4: af00 add r7, sp, #0 + 80099a6: 60f8 str r0, [r7, #12] + 80099a8: 60b9 str r1, [r7, #8] + 80099aa: 4613 mov r3, r2 + 80099ac: 71fb strb r3, [r7, #7] + uint8_t offset = 0; + 80099ae: 2300 movs r3, #0 + 80099b0: 75fb strb r3, [r7, #23] + + SUBGRF_GetRxBufferStatus( size, &offset ); + 80099b2: f107 0317 add.w r3, r7, #23 + 80099b6: 4619 mov r1, r3 + 80099b8: 68b8 ldr r0, [r7, #8] + 80099ba: f000 fe29 bl 800a610 + if( *size > maxSize ) + 80099be: 68bb ldr r3, [r7, #8] + 80099c0: 781b ldrb r3, [r3, #0] + 80099c2: 79fa ldrb r2, [r7, #7] + 80099c4: 429a cmp r2, r3 + 80099c6: d201 bcs.n 80099cc + { + return 1; + 80099c8: 2301 movs r3, #1 + 80099ca: e007 b.n 80099dc + } + SUBGRF_ReadBuffer( offset, buffer, *size ); + 80099cc: 7df8 ldrb r0, [r7, #23] + 80099ce: 68bb ldr r3, [r7, #8] + 80099d0: 781b ldrb r3, [r3, #0] + 80099d2: 461a mov r2, r3 + 80099d4: 68f9 ldr r1, [r7, #12] + 80099d6: f000 ff41 bl 800a85c + + return 0; + 80099da: 2300 movs r3, #0 +} + 80099dc: 4618 mov r0, r3 + 80099de: 3718 adds r7, #24 + 80099e0: 46bd mov sp, r7 + 80099e2: bd80 pop {r7, pc} + +080099e4 : + +void SUBGRF_SendPayload( uint8_t *payload, uint8_t size, uint32_t timeout) +{ + 80099e4: b580 push {r7, lr} + 80099e6: b084 sub sp, #16 + 80099e8: af00 add r7, sp, #0 + 80099ea: 60f8 str r0, [r7, #12] + 80099ec: 460b mov r3, r1 + 80099ee: 607a str r2, [r7, #4] + 80099f0: 72fb strb r3, [r7, #11] + SUBGRF_SetPayload( payload, size ); + 80099f2: 7afb ldrb r3, [r7, #11] + 80099f4: 4619 mov r1, r3 + 80099f6: 68f8 ldr r0, [r7, #12] + 80099f8: f7ff ffc2 bl 8009980 + SUBGRF_SetTx( timeout ); + 80099fc: 6878 ldr r0, [r7, #4] + 80099fe: f000 f91d bl 8009c3c +} + 8009a02: bf00 nop + 8009a04: 3710 adds r7, #16 + 8009a06: 46bd mov sp, r7 + 8009a08: bd80 pop {r7, pc} + +08009a0a : + +uint8_t SUBGRF_SetSyncWord( uint8_t *syncWord ) +{ + 8009a0a: b580 push {r7, lr} + 8009a0c: b082 sub sp, #8 + 8009a0e: af00 add r7, sp, #0 + 8009a10: 6078 str r0, [r7, #4] + SUBGRF_WriteRegisters( REG_LR_SYNCWORDBASEADDRESS, syncWord, 8 ); + 8009a12: 2208 movs r2, #8 + 8009a14: 6879 ldr r1, [r7, #4] + 8009a16: f44f 60d8 mov.w r0, #1728 @ 0x6c0 + 8009a1a: f000 feb9 bl 800a790 + return 0; + 8009a1e: 2300 movs r3, #0 +} + 8009a20: 4618 mov r0, r3 + 8009a22: 3708 adds r7, #8 + 8009a24: 46bd mov sp, r7 + 8009a26: bd80 pop {r7, pc} + +08009a28 : + +void SUBGRF_SetCrcSeed( uint16_t seed ) +{ + 8009a28: b580 push {r7, lr} + 8009a2a: b084 sub sp, #16 + 8009a2c: af00 add r7, sp, #0 + 8009a2e: 4603 mov r3, r0 + 8009a30: 80fb strh r3, [r7, #6] + uint8_t buf[2]; + + buf[0] = ( uint8_t )( ( seed >> 8 ) & 0xFF ); + 8009a32: 88fb ldrh r3, [r7, #6] + 8009a34: 0a1b lsrs r3, r3, #8 + 8009a36: b29b uxth r3, r3 + 8009a38: b2db uxtb r3, r3 + 8009a3a: 733b strb r3, [r7, #12] + buf[1] = ( uint8_t )( seed & 0xFF ); + 8009a3c: 88fb ldrh r3, [r7, #6] + 8009a3e: b2db uxtb r3, r3 + 8009a40: 737b strb r3, [r7, #13] + + switch( SUBGRF_GetPacketType( ) ) + 8009a42: f000 fb77 bl 800a134 + 8009a46: 4603 mov r3, r0 + 8009a48: 2b00 cmp r3, #0 + 8009a4a: d108 bne.n 8009a5e + { + case PACKET_TYPE_GFSK: + SUBGRF_WriteRegisters( REG_LR_CRCSEEDBASEADDR, buf, 2 ); + 8009a4c: f107 030c add.w r3, r7, #12 + 8009a50: 2202 movs r2, #2 + 8009a52: 4619 mov r1, r3 + 8009a54: f240 60bc movw r0, #1724 @ 0x6bc + 8009a58: f000 fe9a bl 800a790 + break; + 8009a5c: e000 b.n 8009a60 + + default: + break; + 8009a5e: bf00 nop + } +} + 8009a60: bf00 nop + 8009a62: 3710 adds r7, #16 + 8009a64: 46bd mov sp, r7 + 8009a66: bd80 pop {r7, pc} + +08009a68 : + +void SUBGRF_SetCrcPolynomial( uint16_t polynomial ) +{ + 8009a68: b580 push {r7, lr} + 8009a6a: b084 sub sp, #16 + 8009a6c: af00 add r7, sp, #0 + 8009a6e: 4603 mov r3, r0 + 8009a70: 80fb strh r3, [r7, #6] + uint8_t buf[2]; + + buf[0] = ( uint8_t )( ( polynomial >> 8 ) & 0xFF ); + 8009a72: 88fb ldrh r3, [r7, #6] + 8009a74: 0a1b lsrs r3, r3, #8 + 8009a76: b29b uxth r3, r3 + 8009a78: b2db uxtb r3, r3 + 8009a7a: 733b strb r3, [r7, #12] + buf[1] = ( uint8_t )( polynomial & 0xFF ); + 8009a7c: 88fb ldrh r3, [r7, #6] + 8009a7e: b2db uxtb r3, r3 + 8009a80: 737b strb r3, [r7, #13] + + switch( SUBGRF_GetPacketType( ) ) + 8009a82: f000 fb57 bl 800a134 + 8009a86: 4603 mov r3, r0 + 8009a88: 2b00 cmp r3, #0 + 8009a8a: d108 bne.n 8009a9e + { + case PACKET_TYPE_GFSK: + SUBGRF_WriteRegisters( REG_LR_CRCPOLYBASEADDR, buf, 2 ); + 8009a8c: f107 030c add.w r3, r7, #12 + 8009a90: 2202 movs r2, #2 + 8009a92: 4619 mov r1, r3 + 8009a94: f240 60be movw r0, #1726 @ 0x6be + 8009a98: f000 fe7a bl 800a790 + break; + 8009a9c: e000 b.n 8009aa0 + + default: + break; + 8009a9e: bf00 nop + } +} + 8009aa0: bf00 nop + 8009aa2: 3710 adds r7, #16 + 8009aa4: 46bd mov sp, r7 + 8009aa6: bd80 pop {r7, pc} + +08009aa8 : + +void SUBGRF_SetWhiteningSeed( uint16_t seed ) +{ + 8009aa8: b580 push {r7, lr} + 8009aaa: b084 sub sp, #16 + 8009aac: af00 add r7, sp, #0 + 8009aae: 4603 mov r3, r0 + 8009ab0: 80fb strh r3, [r7, #6] + uint8_t regValue = 0; + 8009ab2: 2300 movs r3, #0 + 8009ab4: 73fb strb r3, [r7, #15] + + switch( SUBGRF_GetPacketType( ) ) + 8009ab6: f000 fb3d bl 800a134 + 8009aba: 4603 mov r3, r0 + 8009abc: 2b00 cmp r3, #0 + 8009abe: d121 bne.n 8009b04 + { + case PACKET_TYPE_GFSK: + regValue = SUBGRF_ReadRegister( REG_LR_WHITSEEDBASEADDR_MSB ) & 0xFE; + 8009ac0: f44f 60d7 mov.w r0, #1720 @ 0x6b8 + 8009ac4: f000 fe44 bl 800a750 + 8009ac8: 4603 mov r3, r0 + 8009aca: f023 0301 bic.w r3, r3, #1 + 8009ace: 73fb strb r3, [r7, #15] + regValue = ( ( seed >> 8 ) & 0x01 ) | regValue; + 8009ad0: 88fb ldrh r3, [r7, #6] + 8009ad2: 0a1b lsrs r3, r3, #8 + 8009ad4: b29b uxth r3, r3 + 8009ad6: b25b sxtb r3, r3 + 8009ad8: f003 0301 and.w r3, r3, #1 + 8009adc: b25a sxtb r2, r3 + 8009ade: f997 300f ldrsb.w r3, [r7, #15] + 8009ae2: 4313 orrs r3, r2 + 8009ae4: b25b sxtb r3, r3 + 8009ae6: 73fb strb r3, [r7, #15] + SUBGRF_WriteRegister( REG_LR_WHITSEEDBASEADDR_MSB, regValue ); // only 1 bit. + 8009ae8: 7bfb ldrb r3, [r7, #15] + 8009aea: 4619 mov r1, r3 + 8009aec: f44f 60d7 mov.w r0, #1720 @ 0x6b8 + 8009af0: f000 fe0c bl 800a70c + SUBGRF_WriteRegister( REG_LR_WHITSEEDBASEADDR_LSB, (uint8_t)seed ); + 8009af4: 88fb ldrh r3, [r7, #6] + 8009af6: b2db uxtb r3, r3 + 8009af8: 4619 mov r1, r3 + 8009afa: f240 60b9 movw r0, #1721 @ 0x6b9 + 8009afe: f000 fe05 bl 800a70c + break; + 8009b02: e000 b.n 8009b06 + + default: + break; + 8009b04: bf00 nop + } +} + 8009b06: bf00 nop + 8009b08: 3710 adds r7, #16 + 8009b0a: 46bd mov sp, r7 + 8009b0c: bd80 pop {r7, pc} + +08009b0e : + +uint32_t SUBGRF_GetRandom( void ) +{ + 8009b0e: b580 push {r7, lr} + 8009b10: b082 sub sp, #8 + 8009b12: af00 add r7, sp, #0 + uint32_t number = 0; + 8009b14: 2300 movs r3, #0 + 8009b16: 603b str r3, [r7, #0] + uint8_t regAnaLna = 0; + 8009b18: 2300 movs r3, #0 + 8009b1a: 71fb strb r3, [r7, #7] + uint8_t regAnaMixer = 0; + 8009b1c: 2300 movs r3, #0 + 8009b1e: 71bb strb r3, [r7, #6] + + regAnaLna = SUBGRF_ReadRegister( REG_ANA_LNA ); + 8009b20: f640 00e2 movw r0, #2274 @ 0x8e2 + 8009b24: f000 fe14 bl 800a750 + 8009b28: 4603 mov r3, r0 + 8009b2a: 71fb strb r3, [r7, #7] + SUBGRF_WriteRegister( REG_ANA_LNA, regAnaLna & ~( 1 << 0 ) ); + 8009b2c: 79fb ldrb r3, [r7, #7] + 8009b2e: f023 0301 bic.w r3, r3, #1 + 8009b32: b2db uxtb r3, r3 + 8009b34: 4619 mov r1, r3 + 8009b36: f640 00e2 movw r0, #2274 @ 0x8e2 + 8009b3a: f000 fde7 bl 800a70c + + regAnaMixer = SUBGRF_ReadRegister( REG_ANA_MIXER ); + 8009b3e: f640 00e5 movw r0, #2277 @ 0x8e5 + 8009b42: f000 fe05 bl 800a750 + 8009b46: 4603 mov r3, r0 + 8009b48: 71bb strb r3, [r7, #6] + SUBGRF_WriteRegister( REG_ANA_MIXER, regAnaMixer & ~( 1 << 7 ) ); + 8009b4a: 79bb ldrb r3, [r7, #6] + 8009b4c: f003 037f and.w r3, r3, #127 @ 0x7f + 8009b50: b2db uxtb r3, r3 + 8009b52: 4619 mov r1, r3 + 8009b54: f640 00e5 movw r0, #2277 @ 0x8e5 + 8009b58: f000 fdd8 bl 800a70c + + // Set radio in continuous reception + SUBGRF_SetRx( 0xFFFFFF ); // Rx Continuous + 8009b5c: f06f 407f mvn.w r0, #4278190080 @ 0xff000000 + 8009b60: f000 f88c bl 8009c7c + + SUBGRF_ReadRegisters( RANDOM_NUMBER_GENERATORBASEADDR, ( uint8_t* )&number, 4 ); + 8009b64: 463b mov r3, r7 + 8009b66: 2204 movs r2, #4 + 8009b68: 4619 mov r1, r3 + 8009b6a: f640 0019 movw r0, #2073 @ 0x819 + 8009b6e: f000 fe31 bl 800a7d4 + + SUBGRF_SetStandby( STDBY_RC ); + 8009b72: 2000 movs r0, #0 + 8009b74: f000 f846 bl 8009c04 + + SUBGRF_WriteRegister( REG_ANA_LNA, regAnaLna ); + 8009b78: 79fb ldrb r3, [r7, #7] + 8009b7a: 4619 mov r1, r3 + 8009b7c: f640 00e2 movw r0, #2274 @ 0x8e2 + 8009b80: f000 fdc4 bl 800a70c + SUBGRF_WriteRegister( REG_ANA_MIXER, regAnaMixer ); + 8009b84: 79bb ldrb r3, [r7, #6] + 8009b86: 4619 mov r1, r3 + 8009b88: f640 00e5 movw r0, #2277 @ 0x8e5 + 8009b8c: f000 fdbe bl 800a70c + + return number; + 8009b90: 683b ldr r3, [r7, #0] +} + 8009b92: 4618 mov r0, r3 + 8009b94: 3708 adds r7, #8 + 8009b96: 46bd mov sp, r7 + 8009b98: bd80 pop {r7, pc} + ... + +08009b9c : + +void SUBGRF_SetSleep( SleepParams_t sleepConfig ) +{ + 8009b9c: b580 push {r7, lr} + 8009b9e: b084 sub sp, #16 + 8009ba0: af00 add r7, sp, #0 + 8009ba2: 7138 strb r0, [r7, #4] + /* switch the antenna OFF by SW */ + RBI_ConfigRFSwitch(RBI_SWITCH_OFF); + 8009ba4: 2000 movs r0, #0 + 8009ba6: f003 fa6a bl 800d07e + + Radio_SMPS_Set(SMPS_DRIVE_SETTING_DEFAULT); + 8009baa: 2002 movs r0, #2 + 8009bac: f000 ffc0 bl 800ab30 + + uint8_t value = ( ( ( uint8_t )sleepConfig.Fields.WarmStart << 2 ) | + 8009bb0: 793b ldrb r3, [r7, #4] + 8009bb2: f3c3 0380 ubfx r3, r3, #2, #1 + 8009bb6: b2db uxtb r3, r3 + 8009bb8: b25b sxtb r3, r3 + 8009bba: 009b lsls r3, r3, #2 + 8009bbc: b25a sxtb r2, r3 + ( ( uint8_t )sleepConfig.Fields.Reset << 1 ) | + 8009bbe: 793b ldrb r3, [r7, #4] + 8009bc0: f3c3 0340 ubfx r3, r3, #1, #1 + 8009bc4: b2db uxtb r3, r3 + uint8_t value = ( ( ( uint8_t )sleepConfig.Fields.WarmStart << 2 ) | + 8009bc6: b25b sxtb r3, r3 + 8009bc8: 005b lsls r3, r3, #1 + 8009bca: b25b sxtb r3, r3 + 8009bcc: 4313 orrs r3, r2 + 8009bce: b25a sxtb r2, r3 + ( ( uint8_t )sleepConfig.Fields.WakeUpRTC ) ); + 8009bd0: 793b ldrb r3, [r7, #4] + 8009bd2: f3c3 0300 ubfx r3, r3, #0, #1 + 8009bd6: b2db uxtb r3, r3 + 8009bd8: b25b sxtb r3, r3 + ( ( uint8_t )sleepConfig.Fields.Reset << 1 ) | + 8009bda: 4313 orrs r3, r2 + 8009bdc: b25b sxtb r3, r3 + 8009bde: b2db uxtb r3, r3 + uint8_t value = ( ( ( uint8_t )sleepConfig.Fields.WarmStart << 2 ) | + 8009be0: 73fb strb r3, [r7, #15] + SUBGRF_WriteCommand( RADIO_SET_SLEEP, &value, 1 ); + 8009be2: f107 030f add.w r3, r7, #15 + 8009be6: 2201 movs r2, #1 + 8009be8: 4619 mov r1, r3 + 8009bea: 2084 movs r0, #132 @ 0x84 + 8009bec: f000 fe58 bl 800a8a0 + OperatingMode = MODE_SLEEP; + 8009bf0: 4b03 ldr r3, [pc, #12] @ (8009c00 ) + 8009bf2: 2200 movs r2, #0 + 8009bf4: 701a strb r2, [r3, #0] +} + 8009bf6: bf00 nop + 8009bf8: 3710 adds r7, #16 + 8009bfa: 46bd mov sp, r7 + 8009bfc: bd80 pop {r7, pc} + 8009bfe: bf00 nop + 8009c00: 2000038c .word 0x2000038c + +08009c04 : + +void SUBGRF_SetStandby( RadioStandbyModes_t standbyConfig ) +{ + 8009c04: b580 push {r7, lr} + 8009c06: b082 sub sp, #8 + 8009c08: af00 add r7, sp, #0 + 8009c0a: 4603 mov r3, r0 + 8009c0c: 71fb strb r3, [r7, #7] + SUBGRF_WriteCommand( RADIO_SET_STANDBY, ( uint8_t* )&standbyConfig, 1 ); + 8009c0e: 1dfb adds r3, r7, #7 + 8009c10: 2201 movs r2, #1 + 8009c12: 4619 mov r1, r3 + 8009c14: 2080 movs r0, #128 @ 0x80 + 8009c16: f000 fe43 bl 800a8a0 + if( standbyConfig == STDBY_RC ) + 8009c1a: 79fb ldrb r3, [r7, #7] + 8009c1c: 2b00 cmp r3, #0 + 8009c1e: d103 bne.n 8009c28 + { + OperatingMode = MODE_STDBY_RC; + 8009c20: 4b05 ldr r3, [pc, #20] @ (8009c38 ) + 8009c22: 2201 movs r2, #1 + 8009c24: 701a strb r2, [r3, #0] + } + else + { + OperatingMode = MODE_STDBY_XOSC; + } +} + 8009c26: e002 b.n 8009c2e + OperatingMode = MODE_STDBY_XOSC; + 8009c28: 4b03 ldr r3, [pc, #12] @ (8009c38 ) + 8009c2a: 2202 movs r2, #2 + 8009c2c: 701a strb r2, [r3, #0] +} + 8009c2e: bf00 nop + 8009c30: 3708 adds r7, #8 + 8009c32: 46bd mov sp, r7 + 8009c34: bd80 pop {r7, pc} + 8009c36: bf00 nop + 8009c38: 2000038c .word 0x2000038c + +08009c3c : + SUBGRF_WriteCommand( RADIO_SET_FS, 0, 0 ); + OperatingMode = MODE_FS; +} + +void SUBGRF_SetTx( uint32_t timeout ) +{ + 8009c3c: b580 push {r7, lr} + 8009c3e: b084 sub sp, #16 + 8009c40: af00 add r7, sp, #0 + 8009c42: 6078 str r0, [r7, #4] + uint8_t buf[3]; + + OperatingMode = MODE_TX; + 8009c44: 4b0c ldr r3, [pc, #48] @ (8009c78 ) + 8009c46: 2204 movs r2, #4 + 8009c48: 701a strb r2, [r3, #0] + + buf[0] = ( uint8_t )( ( timeout >> 16 ) & 0xFF ); + 8009c4a: 687b ldr r3, [r7, #4] + 8009c4c: 0c1b lsrs r3, r3, #16 + 8009c4e: b2db uxtb r3, r3 + 8009c50: 733b strb r3, [r7, #12] + buf[1] = ( uint8_t )( ( timeout >> 8 ) & 0xFF ); + 8009c52: 687b ldr r3, [r7, #4] + 8009c54: 0a1b lsrs r3, r3, #8 + 8009c56: b2db uxtb r3, r3 + 8009c58: 737b strb r3, [r7, #13] + buf[2] = ( uint8_t )( timeout & 0xFF ); + 8009c5a: 687b ldr r3, [r7, #4] + 8009c5c: b2db uxtb r3, r3 + 8009c5e: 73bb strb r3, [r7, #14] + SUBGRF_WriteCommand( RADIO_SET_TX, buf, 3 ); + 8009c60: f107 030c add.w r3, r7, #12 + 8009c64: 2203 movs r2, #3 + 8009c66: 4619 mov r1, r3 + 8009c68: 2083 movs r0, #131 @ 0x83 + 8009c6a: f000 fe19 bl 800a8a0 +} + 8009c6e: bf00 nop + 8009c70: 3710 adds r7, #16 + 8009c72: 46bd mov sp, r7 + 8009c74: bd80 pop {r7, pc} + 8009c76: bf00 nop + 8009c78: 2000038c .word 0x2000038c + +08009c7c : + +void SUBGRF_SetRx( uint32_t timeout ) +{ + 8009c7c: b580 push {r7, lr} + 8009c7e: b084 sub sp, #16 + 8009c80: af00 add r7, sp, #0 + 8009c82: 6078 str r0, [r7, #4] + uint8_t buf[3]; + + OperatingMode = MODE_RX; + 8009c84: 4b0c ldr r3, [pc, #48] @ (8009cb8 ) + 8009c86: 2205 movs r2, #5 + 8009c88: 701a strb r2, [r3, #0] + + buf[0] = ( uint8_t )( ( timeout >> 16 ) & 0xFF ); + 8009c8a: 687b ldr r3, [r7, #4] + 8009c8c: 0c1b lsrs r3, r3, #16 + 8009c8e: b2db uxtb r3, r3 + 8009c90: 733b strb r3, [r7, #12] + buf[1] = ( uint8_t )( ( timeout >> 8 ) & 0xFF ); + 8009c92: 687b ldr r3, [r7, #4] + 8009c94: 0a1b lsrs r3, r3, #8 + 8009c96: b2db uxtb r3, r3 + 8009c98: 737b strb r3, [r7, #13] + buf[2] = ( uint8_t )( timeout & 0xFF ); + 8009c9a: 687b ldr r3, [r7, #4] + 8009c9c: b2db uxtb r3, r3 + 8009c9e: 73bb strb r3, [r7, #14] + SUBGRF_WriteCommand( RADIO_SET_RX, buf, 3 ); + 8009ca0: f107 030c add.w r3, r7, #12 + 8009ca4: 2203 movs r2, #3 + 8009ca6: 4619 mov r1, r3 + 8009ca8: 2082 movs r0, #130 @ 0x82 + 8009caa: f000 fdf9 bl 800a8a0 +} + 8009cae: bf00 nop + 8009cb0: 3710 adds r7, #16 + 8009cb2: 46bd mov sp, r7 + 8009cb4: bd80 pop {r7, pc} + 8009cb6: bf00 nop + 8009cb8: 2000038c .word 0x2000038c + +08009cbc : + +void SUBGRF_SetRxBoosted( uint32_t timeout ) +{ + 8009cbc: b580 push {r7, lr} + 8009cbe: b084 sub sp, #16 + 8009cc0: af00 add r7, sp, #0 + 8009cc2: 6078 str r0, [r7, #4] + uint8_t buf[3]; + + OperatingMode = MODE_RX; + 8009cc4: 4b0e ldr r3, [pc, #56] @ (8009d00 ) + 8009cc6: 2205 movs r2, #5 + 8009cc8: 701a strb r2, [r3, #0] + + SUBGRF_WriteRegister( REG_RX_GAIN, 0x97 ); // max LNA gain, increase current by ~2mA for around ~3dB in sensitivity + 8009cca: 2197 movs r1, #151 @ 0x97 + 8009ccc: f640 00ac movw r0, #2220 @ 0x8ac + 8009cd0: f000 fd1c bl 800a70c + + buf[0] = ( uint8_t )( ( timeout >> 16 ) & 0xFF ); + 8009cd4: 687b ldr r3, [r7, #4] + 8009cd6: 0c1b lsrs r3, r3, #16 + 8009cd8: b2db uxtb r3, r3 + 8009cda: 733b strb r3, [r7, #12] + buf[1] = ( uint8_t )( ( timeout >> 8 ) & 0xFF ); + 8009cdc: 687b ldr r3, [r7, #4] + 8009cde: 0a1b lsrs r3, r3, #8 + 8009ce0: b2db uxtb r3, r3 + 8009ce2: 737b strb r3, [r7, #13] + buf[2] = ( uint8_t )( timeout & 0xFF ); + 8009ce4: 687b ldr r3, [r7, #4] + 8009ce6: b2db uxtb r3, r3 + 8009ce8: 73bb strb r3, [r7, #14] + SUBGRF_WriteCommand( RADIO_SET_RX, buf, 3 ); + 8009cea: f107 030c add.w r3, r7, #12 + 8009cee: 2203 movs r2, #3 + 8009cf0: 4619 mov r1, r3 + 8009cf2: 2082 movs r0, #130 @ 0x82 + 8009cf4: f000 fdd4 bl 800a8a0 +} + 8009cf8: bf00 nop + 8009cfa: 3710 adds r7, #16 + 8009cfc: 46bd mov sp, r7 + 8009cfe: bd80 pop {r7, pc} + 8009d00: 2000038c .word 0x2000038c + +08009d04 : + +void SUBGRF_SetRxDutyCycle( uint32_t rxTime, uint32_t sleepTime ) +{ + 8009d04: b580 push {r7, lr} + 8009d06: b084 sub sp, #16 + 8009d08: af00 add r7, sp, #0 + 8009d0a: 6078 str r0, [r7, #4] + 8009d0c: 6039 str r1, [r7, #0] + uint8_t buf[6]; + + buf[0] = ( uint8_t )( ( rxTime >> 16 ) & 0xFF ); + 8009d0e: 687b ldr r3, [r7, #4] + 8009d10: 0c1b lsrs r3, r3, #16 + 8009d12: b2db uxtb r3, r3 + 8009d14: 723b strb r3, [r7, #8] + buf[1] = ( uint8_t )( ( rxTime >> 8 ) & 0xFF ); + 8009d16: 687b ldr r3, [r7, #4] + 8009d18: 0a1b lsrs r3, r3, #8 + 8009d1a: b2db uxtb r3, r3 + 8009d1c: 727b strb r3, [r7, #9] + buf[2] = ( uint8_t )( rxTime & 0xFF ); + 8009d1e: 687b ldr r3, [r7, #4] + 8009d20: b2db uxtb r3, r3 + 8009d22: 72bb strb r3, [r7, #10] + buf[3] = ( uint8_t )( ( sleepTime >> 16 ) & 0xFF ); + 8009d24: 683b ldr r3, [r7, #0] + 8009d26: 0c1b lsrs r3, r3, #16 + 8009d28: b2db uxtb r3, r3 + 8009d2a: 72fb strb r3, [r7, #11] + buf[4] = ( uint8_t )( ( sleepTime >> 8 ) & 0xFF ); + 8009d2c: 683b ldr r3, [r7, #0] + 8009d2e: 0a1b lsrs r3, r3, #8 + 8009d30: b2db uxtb r3, r3 + 8009d32: 733b strb r3, [r7, #12] + buf[5] = ( uint8_t )( sleepTime & 0xFF ); + 8009d34: 683b ldr r3, [r7, #0] + 8009d36: b2db uxtb r3, r3 + 8009d38: 737b strb r3, [r7, #13] + SUBGRF_WriteCommand( RADIO_SET_RXDUTYCYCLE, buf, 6 ); + 8009d3a: f107 0308 add.w r3, r7, #8 + 8009d3e: 2206 movs r2, #6 + 8009d40: 4619 mov r1, r3 + 8009d42: 2094 movs r0, #148 @ 0x94 + 8009d44: f000 fdac bl 800a8a0 + OperatingMode = MODE_RX_DC; + 8009d48: 4b03 ldr r3, [pc, #12] @ (8009d58 ) + 8009d4a: 2206 movs r2, #6 + 8009d4c: 701a strb r2, [r3, #0] +} + 8009d4e: bf00 nop + 8009d50: 3710 adds r7, #16 + 8009d52: 46bd mov sp, r7 + 8009d54: bd80 pop {r7, pc} + 8009d56: bf00 nop + 8009d58: 2000038c .word 0x2000038c + +08009d5c : + +void SUBGRF_SetCad( void ) +{ + 8009d5c: b580 push {r7, lr} + 8009d5e: af00 add r7, sp, #0 + SUBGRF_WriteCommand( RADIO_SET_CAD, 0, 0 ); + 8009d60: 2200 movs r2, #0 + 8009d62: 2100 movs r1, #0 + 8009d64: 20c5 movs r0, #197 @ 0xc5 + 8009d66: f000 fd9b bl 800a8a0 + OperatingMode = MODE_CAD; + 8009d6a: 4b02 ldr r3, [pc, #8] @ (8009d74 ) + 8009d6c: 2207 movs r2, #7 + 8009d6e: 701a strb r2, [r3, #0] +} + 8009d70: bf00 nop + 8009d72: bd80 pop {r7, pc} + 8009d74: 2000038c .word 0x2000038c + +08009d78 : + +void SUBGRF_SetTxContinuousWave( void ) +{ + 8009d78: b580 push {r7, lr} + 8009d7a: af00 add r7, sp, #0 + SUBGRF_WriteCommand( RADIO_SET_TXCONTINUOUSWAVE, 0, 0 ); + 8009d7c: 2200 movs r2, #0 + 8009d7e: 2100 movs r1, #0 + 8009d80: 20d1 movs r0, #209 @ 0xd1 + 8009d82: f000 fd8d bl 800a8a0 +} + 8009d86: bf00 nop + 8009d88: bd80 pop {r7, pc} + +08009d8a : + +void SUBGRF_SetTxInfinitePreamble( void ) +{ + 8009d8a: b580 push {r7, lr} + 8009d8c: af00 add r7, sp, #0 + SUBGRF_WriteCommand( RADIO_SET_TXCONTINUOUSPREAMBLE, 0, 0 ); + 8009d8e: 2200 movs r2, #0 + 8009d90: 2100 movs r1, #0 + 8009d92: 20d2 movs r0, #210 @ 0xd2 + 8009d94: f000 fd84 bl 800a8a0 +} + 8009d98: bf00 nop + 8009d9a: bd80 pop {r7, pc} + +08009d9c : + +void SUBGRF_SetStopRxTimerOnPreambleDetect( bool enable ) +{ + 8009d9c: b580 push {r7, lr} + 8009d9e: b082 sub sp, #8 + 8009da0: af00 add r7, sp, #0 + 8009da2: 4603 mov r3, r0 + 8009da4: 71fb strb r3, [r7, #7] + SUBGRF_WriteCommand( RADIO_SET_STOPRXTIMERONPREAMBLE, ( uint8_t* )&enable, 1 ); + 8009da6: 1dfb adds r3, r7, #7 + 8009da8: 2201 movs r2, #1 + 8009daa: 4619 mov r1, r3 + 8009dac: 209f movs r0, #159 @ 0x9f + 8009dae: f000 fd77 bl 800a8a0 +} + 8009db2: bf00 nop + 8009db4: 3708 adds r7, #8 + 8009db6: 46bd mov sp, r7 + 8009db8: bd80 pop {r7, pc} + +08009dba : + +void SUBGRF_SetLoRaSymbNumTimeout( uint8_t symbNum ) +{ + 8009dba: b580 push {r7, lr} + 8009dbc: b084 sub sp, #16 + 8009dbe: af00 add r7, sp, #0 + 8009dc0: 4603 mov r3, r0 + 8009dc2: 71fb strb r3, [r7, #7] + SUBGRF_WriteCommand( RADIO_SET_LORASYMBTIMEOUT, &symbNum, 1 ); + 8009dc4: 1dfb adds r3, r7, #7 + 8009dc6: 2201 movs r2, #1 + 8009dc8: 4619 mov r1, r3 + 8009dca: 20a0 movs r0, #160 @ 0xa0 + 8009dcc: f000 fd68 bl 800a8a0 + + if( symbNum >= 64 ) + 8009dd0: 79fb ldrb r3, [r7, #7] + 8009dd2: 2b3f cmp r3, #63 @ 0x3f + 8009dd4: d91c bls.n 8009e10 + { + uint8_t mant = symbNum >> 1; + 8009dd6: 79fb ldrb r3, [r7, #7] + 8009dd8: 085b lsrs r3, r3, #1 + 8009dda: 73fb strb r3, [r7, #15] + uint8_t exp = 0; + 8009ddc: 2300 movs r3, #0 + 8009dde: 73bb strb r3, [r7, #14] + uint8_t reg = 0; + 8009de0: 2300 movs r3, #0 + 8009de2: 737b strb r3, [r7, #13] + + while( mant > 31 ) + 8009de4: e005 b.n 8009df2 + { + mant >>= 2; + 8009de6: 7bfb ldrb r3, [r7, #15] + 8009de8: 089b lsrs r3, r3, #2 + 8009dea: 73fb strb r3, [r7, #15] + exp++; + 8009dec: 7bbb ldrb r3, [r7, #14] + 8009dee: 3301 adds r3, #1 + 8009df0: 73bb strb r3, [r7, #14] + while( mant > 31 ) + 8009df2: 7bfb ldrb r3, [r7, #15] + 8009df4: 2b1f cmp r3, #31 + 8009df6: d8f6 bhi.n 8009de6 + } + + reg = exp + ( mant << 3 ); + 8009df8: 7bfb ldrb r3, [r7, #15] + 8009dfa: 00db lsls r3, r3, #3 + 8009dfc: b2da uxtb r2, r3 + 8009dfe: 7bbb ldrb r3, [r7, #14] + 8009e00: 4413 add r3, r2 + 8009e02: 737b strb r3, [r7, #13] + SUBGRF_WriteRegister( REG_LR_SYNCH_TIMEOUT, reg ); + 8009e04: 7b7b ldrb r3, [r7, #13] + 8009e06: 4619 mov r1, r3 + 8009e08: f240 7006 movw r0, #1798 @ 0x706 + 8009e0c: f000 fc7e bl 800a70c + } +} + 8009e10: bf00 nop + 8009e12: 3710 adds r7, #16 + 8009e14: 46bd mov sp, r7 + 8009e16: bd80 pop {r7, pc} + +08009e18 : + +void SUBGRF_SetRegulatorMode( void ) +{ + 8009e18: b580 push {r7, lr} + 8009e1a: b082 sub sp, #8 + 8009e1c: af00 add r7, sp, #0 + RadioRegulatorMode_t mode; + + if ( ( 1UL == RBI_IsDCDC() ) && ( 1UL == DCDC_ENABLE ) ) + 8009e1e: f003 f94a bl 800d0b6 + 8009e22: 4603 mov r3, r0 + 8009e24: 2b01 cmp r3, #1 + 8009e26: d102 bne.n 8009e2e + { + mode = USE_DCDC ; + 8009e28: 2301 movs r3, #1 + 8009e2a: 71fb strb r3, [r7, #7] + 8009e2c: e001 b.n 8009e32 + } + else + { + mode = USE_LDO ; + 8009e2e: 2300 movs r3, #0 + 8009e30: 71fb strb r3, [r7, #7] + } + SUBGRF_WriteCommand( RADIO_SET_REGULATORMODE, ( uint8_t* )&mode, 1 ); + 8009e32: 1dfb adds r3, r7, #7 + 8009e34: 2201 movs r2, #1 + 8009e36: 4619 mov r1, r3 + 8009e38: 2096 movs r0, #150 @ 0x96 + 8009e3a: f000 fd31 bl 800a8a0 +} + 8009e3e: bf00 nop + 8009e40: 3708 adds r7, #8 + 8009e42: 46bd mov sp, r7 + 8009e44: bd80 pop {r7, pc} + +08009e46 : + +void SUBGRF_Calibrate( CalibrationParams_t calibParam ) +{ + 8009e46: b580 push {r7, lr} + 8009e48: b084 sub sp, #16 + 8009e4a: af00 add r7, sp, #0 + 8009e4c: 7138 strb r0, [r7, #4] + uint8_t value = ( ( ( uint8_t )calibParam.Fields.ImgEnable << 6 ) | + 8009e4e: 793b ldrb r3, [r7, #4] + 8009e50: f3c3 1380 ubfx r3, r3, #6, #1 + 8009e54: b2db uxtb r3, r3 + 8009e56: b25b sxtb r3, r3 + 8009e58: 019b lsls r3, r3, #6 + 8009e5a: b25a sxtb r2, r3 + ( ( uint8_t )calibParam.Fields.ADCBulkPEnable << 5 ) | + 8009e5c: 793b ldrb r3, [r7, #4] + 8009e5e: f3c3 1340 ubfx r3, r3, #5, #1 + 8009e62: b2db uxtb r3, r3 + uint8_t value = ( ( ( uint8_t )calibParam.Fields.ImgEnable << 6 ) | + 8009e64: b25b sxtb r3, r3 + 8009e66: 015b lsls r3, r3, #5 + 8009e68: b25b sxtb r3, r3 + 8009e6a: 4313 orrs r3, r2 + 8009e6c: b25a sxtb r2, r3 + ( ( uint8_t )calibParam.Fields.ADCBulkNEnable << 4 ) | + 8009e6e: 793b ldrb r3, [r7, #4] + 8009e70: f3c3 1300 ubfx r3, r3, #4, #1 + 8009e74: b2db uxtb r3, r3 + ( ( uint8_t )calibParam.Fields.ADCBulkPEnable << 5 ) | + 8009e76: b25b sxtb r3, r3 + 8009e78: 011b lsls r3, r3, #4 + 8009e7a: b25b sxtb r3, r3 + 8009e7c: 4313 orrs r3, r2 + 8009e7e: b25a sxtb r2, r3 + ( ( uint8_t )calibParam.Fields.ADCPulseEnable << 3 ) | + 8009e80: 793b ldrb r3, [r7, #4] + 8009e82: f3c3 03c0 ubfx r3, r3, #3, #1 + 8009e86: b2db uxtb r3, r3 + ( ( uint8_t )calibParam.Fields.ADCBulkNEnable << 4 ) | + 8009e88: b25b sxtb r3, r3 + 8009e8a: 00db lsls r3, r3, #3 + 8009e8c: b25b sxtb r3, r3 + 8009e8e: 4313 orrs r3, r2 + 8009e90: b25a sxtb r2, r3 + ( ( uint8_t )calibParam.Fields.PLLEnable << 2 ) | + 8009e92: 793b ldrb r3, [r7, #4] + 8009e94: f3c3 0380 ubfx r3, r3, #2, #1 + 8009e98: b2db uxtb r3, r3 + ( ( uint8_t )calibParam.Fields.ADCPulseEnable << 3 ) | + 8009e9a: b25b sxtb r3, r3 + 8009e9c: 009b lsls r3, r3, #2 + 8009e9e: b25b sxtb r3, r3 + 8009ea0: 4313 orrs r3, r2 + 8009ea2: b25a sxtb r2, r3 + ( ( uint8_t )calibParam.Fields.RC13MEnable << 1 ) | + 8009ea4: 793b ldrb r3, [r7, #4] + 8009ea6: f3c3 0340 ubfx r3, r3, #1, #1 + 8009eaa: b2db uxtb r3, r3 + ( ( uint8_t )calibParam.Fields.PLLEnable << 2 ) | + 8009eac: b25b sxtb r3, r3 + 8009eae: 005b lsls r3, r3, #1 + 8009eb0: b25b sxtb r3, r3 + 8009eb2: 4313 orrs r3, r2 + 8009eb4: b25a sxtb r2, r3 + ( ( uint8_t )calibParam.Fields.RC64KEnable ) ); + 8009eb6: 793b ldrb r3, [r7, #4] + 8009eb8: f3c3 0300 ubfx r3, r3, #0, #1 + 8009ebc: b2db uxtb r3, r3 + 8009ebe: b25b sxtb r3, r3 + ( ( uint8_t )calibParam.Fields.RC13MEnable << 1 ) | + 8009ec0: 4313 orrs r3, r2 + 8009ec2: b25b sxtb r3, r3 + 8009ec4: b2db uxtb r3, r3 + uint8_t value = ( ( ( uint8_t )calibParam.Fields.ImgEnable << 6 ) | + 8009ec6: 73fb strb r3, [r7, #15] + + SUBGRF_WriteCommand( RADIO_CALIBRATE, &value, 1 ); + 8009ec8: f107 030f add.w r3, r7, #15 + 8009ecc: 2201 movs r2, #1 + 8009ece: 4619 mov r1, r3 + 8009ed0: 2089 movs r0, #137 @ 0x89 + 8009ed2: f000 fce5 bl 800a8a0 +} + 8009ed6: bf00 nop + 8009ed8: 3710 adds r7, #16 + 8009eda: 46bd mov sp, r7 + 8009edc: bd80 pop {r7, pc} + ... + +08009ee0 : + +void SUBGRF_CalibrateImage( uint32_t freq ) +{ + 8009ee0: b580 push {r7, lr} + 8009ee2: b084 sub sp, #16 + 8009ee4: af00 add r7, sp, #0 + 8009ee6: 6078 str r0, [r7, #4] + uint8_t calFreq[2]; + + if( freq > 900000000 ) + 8009ee8: 687b ldr r3, [r7, #4] + 8009eea: 4a1d ldr r2, [pc, #116] @ (8009f60 ) + 8009eec: 4293 cmp r3, r2 + 8009eee: d904 bls.n 8009efa + { + calFreq[0] = 0xE1; + 8009ef0: 23e1 movs r3, #225 @ 0xe1 + 8009ef2: 733b strb r3, [r7, #12] + calFreq[1] = 0xE9; + 8009ef4: 23e9 movs r3, #233 @ 0xe9 + 8009ef6: 737b strb r3, [r7, #13] + 8009ef8: e027 b.n 8009f4a + } + else if( freq > 850000000 ) + 8009efa: 687b ldr r3, [r7, #4] + 8009efc: 4a19 ldr r2, [pc, #100] @ (8009f64 ) + 8009efe: 4293 cmp r3, r2 + 8009f00: d904 bls.n 8009f0c + { + calFreq[0] = 0xD7; + 8009f02: 23d7 movs r3, #215 @ 0xd7 + 8009f04: 733b strb r3, [r7, #12] + calFreq[1] = 0xDB; + 8009f06: 23db movs r3, #219 @ 0xdb + 8009f08: 737b strb r3, [r7, #13] + 8009f0a: e01e b.n 8009f4a + } + else if( freq > 770000000 ) + 8009f0c: 687b ldr r3, [r7, #4] + 8009f0e: 4a16 ldr r2, [pc, #88] @ (8009f68 ) + 8009f10: 4293 cmp r3, r2 + 8009f12: d904 bls.n 8009f1e + { + calFreq[0] = 0xC1; + 8009f14: 23c1 movs r3, #193 @ 0xc1 + 8009f16: 733b strb r3, [r7, #12] + calFreq[1] = 0xC5; + 8009f18: 23c5 movs r3, #197 @ 0xc5 + 8009f1a: 737b strb r3, [r7, #13] + 8009f1c: e015 b.n 8009f4a + } + else if( freq > 460000000 ) + 8009f1e: 687b ldr r3, [r7, #4] + 8009f20: 4a12 ldr r2, [pc, #72] @ (8009f6c ) + 8009f22: 4293 cmp r3, r2 + 8009f24: d904 bls.n 8009f30 + { + calFreq[0] = 0x75; + 8009f26: 2375 movs r3, #117 @ 0x75 + 8009f28: 733b strb r3, [r7, #12] + calFreq[1] = 0x81; + 8009f2a: 2381 movs r3, #129 @ 0x81 + 8009f2c: 737b strb r3, [r7, #13] + 8009f2e: e00c b.n 8009f4a + } + else if( freq > 425000000 ) + 8009f30: 687b ldr r3, [r7, #4] + 8009f32: 4a0f ldr r2, [pc, #60] @ (8009f70 ) + 8009f34: 4293 cmp r3, r2 + 8009f36: d904 bls.n 8009f42 + { + calFreq[0] = 0x6B; + 8009f38: 236b movs r3, #107 @ 0x6b + 8009f3a: 733b strb r3, [r7, #12] + calFreq[1] = 0x6F; + 8009f3c: 236f movs r3, #111 @ 0x6f + 8009f3e: 737b strb r3, [r7, #13] + 8009f40: e003 b.n 8009f4a + } + else /* freq <= 425000000*/ + { + /* [ 156MHz - 171MHz ] */ + calFreq[0] = 0x29; + 8009f42: 2329 movs r3, #41 @ 0x29 + 8009f44: 733b strb r3, [r7, #12] + calFreq[1] = 0x2B ; + 8009f46: 232b movs r3, #43 @ 0x2b + 8009f48: 737b strb r3, [r7, #13] + } + SUBGRF_WriteCommand( RADIO_CALIBRATEIMAGE, calFreq, 2 ); + 8009f4a: f107 030c add.w r3, r7, #12 + 8009f4e: 2202 movs r2, #2 + 8009f50: 4619 mov r1, r3 + 8009f52: 2098 movs r0, #152 @ 0x98 + 8009f54: f000 fca4 bl 800a8a0 +} + 8009f58: bf00 nop + 8009f5a: 3710 adds r7, #16 + 8009f5c: 46bd mov sp, r7 + 8009f5e: bd80 pop {r7, pc} + 8009f60: 35a4e900 .word 0x35a4e900 + 8009f64: 32a9f880 .word 0x32a9f880 + 8009f68: 2de54480 .word 0x2de54480 + 8009f6c: 1b6b0b00 .word 0x1b6b0b00 + 8009f70: 1954fc40 .word 0x1954fc40 + +08009f74 : + +void SUBGRF_SetPaConfig( uint8_t paDutyCycle, uint8_t hpMax, uint8_t deviceSel, uint8_t paLut ) +{ + 8009f74: b590 push {r4, r7, lr} + 8009f76: b085 sub sp, #20 + 8009f78: af00 add r7, sp, #0 + 8009f7a: 4604 mov r4, r0 + 8009f7c: 4608 mov r0, r1 + 8009f7e: 4611 mov r1, r2 + 8009f80: 461a mov r2, r3 + 8009f82: 4623 mov r3, r4 + 8009f84: 71fb strb r3, [r7, #7] + 8009f86: 4603 mov r3, r0 + 8009f88: 71bb strb r3, [r7, #6] + 8009f8a: 460b mov r3, r1 + 8009f8c: 717b strb r3, [r7, #5] + 8009f8e: 4613 mov r3, r2 + 8009f90: 713b strb r3, [r7, #4] + uint8_t buf[4]; + + buf[0] = paDutyCycle; + 8009f92: 79fb ldrb r3, [r7, #7] + 8009f94: 733b strb r3, [r7, #12] + buf[1] = hpMax; + 8009f96: 79bb ldrb r3, [r7, #6] + 8009f98: 737b strb r3, [r7, #13] + buf[2] = deviceSel; + 8009f9a: 797b ldrb r3, [r7, #5] + 8009f9c: 73bb strb r3, [r7, #14] + buf[3] = paLut; + 8009f9e: 793b ldrb r3, [r7, #4] + 8009fa0: 73fb strb r3, [r7, #15] + SUBGRF_WriteCommand( RADIO_SET_PACONFIG, buf, 4 ); + 8009fa2: f107 030c add.w r3, r7, #12 + 8009fa6: 2204 movs r2, #4 + 8009fa8: 4619 mov r1, r3 + 8009faa: 2095 movs r0, #149 @ 0x95 + 8009fac: f000 fc78 bl 800a8a0 +} + 8009fb0: bf00 nop + 8009fb2: 3714 adds r7, #20 + 8009fb4: 46bd mov sp, r7 + 8009fb6: bd90 pop {r4, r7, pc} + +08009fb8 : +{ + SUBGRF_WriteCommand( RADIO_SET_TXFALLBACKMODE, &fallbackMode, 1 ); +} + +void SUBGRF_SetDioIrqParams( uint16_t irqMask, uint16_t dio1Mask, uint16_t dio2Mask, uint16_t dio3Mask ) +{ + 8009fb8: b590 push {r4, r7, lr} + 8009fba: b085 sub sp, #20 + 8009fbc: af00 add r7, sp, #0 + 8009fbe: 4604 mov r4, r0 + 8009fc0: 4608 mov r0, r1 + 8009fc2: 4611 mov r1, r2 + 8009fc4: 461a mov r2, r3 + 8009fc6: 4623 mov r3, r4 + 8009fc8: 80fb strh r3, [r7, #6] + 8009fca: 4603 mov r3, r0 + 8009fcc: 80bb strh r3, [r7, #4] + 8009fce: 460b mov r3, r1 + 8009fd0: 807b strh r3, [r7, #2] + 8009fd2: 4613 mov r3, r2 + 8009fd4: 803b strh r3, [r7, #0] + uint8_t buf[8]; + + buf[0] = ( uint8_t )( ( irqMask >> 8 ) & 0x00FF ); + 8009fd6: 88fb ldrh r3, [r7, #6] + 8009fd8: 0a1b lsrs r3, r3, #8 + 8009fda: b29b uxth r3, r3 + 8009fdc: b2db uxtb r3, r3 + 8009fde: 723b strb r3, [r7, #8] + buf[1] = ( uint8_t )( irqMask & 0x00FF ); + 8009fe0: 88fb ldrh r3, [r7, #6] + 8009fe2: b2db uxtb r3, r3 + 8009fe4: 727b strb r3, [r7, #9] + buf[2] = ( uint8_t )( ( dio1Mask >> 8 ) & 0x00FF ); + 8009fe6: 88bb ldrh r3, [r7, #4] + 8009fe8: 0a1b lsrs r3, r3, #8 + 8009fea: b29b uxth r3, r3 + 8009fec: b2db uxtb r3, r3 + 8009fee: 72bb strb r3, [r7, #10] + buf[3] = ( uint8_t )( dio1Mask & 0x00FF ); + 8009ff0: 88bb ldrh r3, [r7, #4] + 8009ff2: b2db uxtb r3, r3 + 8009ff4: 72fb strb r3, [r7, #11] + buf[4] = ( uint8_t )( ( dio2Mask >> 8 ) & 0x00FF ); + 8009ff6: 887b ldrh r3, [r7, #2] + 8009ff8: 0a1b lsrs r3, r3, #8 + 8009ffa: b29b uxth r3, r3 + 8009ffc: b2db uxtb r3, r3 + 8009ffe: 733b strb r3, [r7, #12] + buf[5] = ( uint8_t )( dio2Mask & 0x00FF ); + 800a000: 887b ldrh r3, [r7, #2] + 800a002: b2db uxtb r3, r3 + 800a004: 737b strb r3, [r7, #13] + buf[6] = ( uint8_t )( ( dio3Mask >> 8 ) & 0x00FF ); + 800a006: 883b ldrh r3, [r7, #0] + 800a008: 0a1b lsrs r3, r3, #8 + 800a00a: b29b uxth r3, r3 + 800a00c: b2db uxtb r3, r3 + 800a00e: 73bb strb r3, [r7, #14] + buf[7] = ( uint8_t )( dio3Mask & 0x00FF ); + 800a010: 883b ldrh r3, [r7, #0] + 800a012: b2db uxtb r3, r3 + 800a014: 73fb strb r3, [r7, #15] + SUBGRF_WriteCommand( RADIO_CFG_DIOIRQ, buf, 8 ); + 800a016: f107 0308 add.w r3, r7, #8 + 800a01a: 2208 movs r2, #8 + 800a01c: 4619 mov r1, r3 + 800a01e: 2008 movs r0, #8 + 800a020: f000 fc3e bl 800a8a0 +} + 800a024: bf00 nop + 800a026: 3714 adds r7, #20 + 800a028: 46bd mov sp, r7 + 800a02a: bd90 pop {r4, r7, pc} + +0800a02c : + SUBGRF_ReadCommand( RADIO_GET_IRQSTATUS, irqStatus, 2 ); + return ( irqStatus[0] << 8 ) | irqStatus[1]; +} + +void SUBGRF_SetTcxoMode (RadioTcxoCtrlVoltage_t tcxoVoltage, uint32_t timeout ) +{ + 800a02c: b580 push {r7, lr} + 800a02e: b084 sub sp, #16 + 800a030: af00 add r7, sp, #0 + 800a032: 4603 mov r3, r0 + 800a034: 6039 str r1, [r7, #0] + 800a036: 71fb strb r3, [r7, #7] + uint8_t buf[4]; + + buf[0] = tcxoVoltage & 0x07; + 800a038: 79fb ldrb r3, [r7, #7] + 800a03a: f003 0307 and.w r3, r3, #7 + 800a03e: b2db uxtb r3, r3 + 800a040: 733b strb r3, [r7, #12] + buf[1] = ( uint8_t )( ( timeout >> 16 ) & 0xFF ); + 800a042: 683b ldr r3, [r7, #0] + 800a044: 0c1b lsrs r3, r3, #16 + 800a046: b2db uxtb r3, r3 + 800a048: 737b strb r3, [r7, #13] + buf[2] = ( uint8_t )( ( timeout >> 8 ) & 0xFF ); + 800a04a: 683b ldr r3, [r7, #0] + 800a04c: 0a1b lsrs r3, r3, #8 + 800a04e: b2db uxtb r3, r3 + 800a050: 73bb strb r3, [r7, #14] + buf[3] = ( uint8_t )( timeout & 0xFF ); + 800a052: 683b ldr r3, [r7, #0] + 800a054: b2db uxtb r3, r3 + 800a056: 73fb strb r3, [r7, #15] + + SUBGRF_WriteCommand( RADIO_SET_TCXOMODE, buf, 4 ); + 800a058: f107 030c add.w r3, r7, #12 + 800a05c: 2204 movs r2, #4 + 800a05e: 4619 mov r1, r3 + 800a060: 2097 movs r0, #151 @ 0x97 + 800a062: f000 fc1d bl 800a8a0 +} + 800a066: bf00 nop + 800a068: 3710 adds r7, #16 + 800a06a: 46bd mov sp, r7 + 800a06c: bd80 pop {r7, pc} + ... + +0800a070 : + +void SUBGRF_SetRfFrequency( uint32_t frequency ) +{ + 800a070: e92d 43b0 stmdb sp!, {r4, r5, r7, r8, r9, lr} + 800a074: b084 sub sp, #16 + 800a076: af00 add r7, sp, #0 + 800a078: 6078 str r0, [r7, #4] + uint8_t buf[4]; + uint32_t chan = 0; + 800a07a: 2300 movs r3, #0 + 800a07c: 60fb str r3, [r7, #12] + + if( ImageCalibrated == false ) + 800a07e: 4b1d ldr r3, [pc, #116] @ (800a0f4 ) + 800a080: 781b ldrb r3, [r3, #0] + 800a082: f083 0301 eor.w r3, r3, #1 + 800a086: b2db uxtb r3, r3 + 800a088: 2b00 cmp r3, #0 + 800a08a: d005 beq.n 800a098 + { + SUBGRF_CalibrateImage( frequency ); + 800a08c: 6878 ldr r0, [r7, #4] + 800a08e: f7ff ff27 bl 8009ee0 + ImageCalibrated = true; + 800a092: 4b18 ldr r3, [pc, #96] @ (800a0f4 ) + 800a094: 2201 movs r2, #1 + 800a096: 701a strb r2, [r3, #0] + } + SX_FREQ_TO_CHANNEL(chan, frequency); + 800a098: 687b ldr r3, [r7, #4] + 800a09a: 2200 movs r2, #0 + 800a09c: 461c mov r4, r3 + 800a09e: 4615 mov r5, r2 + 800a0a0: ea4f 19d4 mov.w r9, r4, lsr #7 + 800a0a4: ea4f 6844 mov.w r8, r4, lsl #25 + 800a0a8: 4a13 ldr r2, [pc, #76] @ (800a0f8 ) + 800a0aa: f04f 0300 mov.w r3, #0 + 800a0ae: 4640 mov r0, r8 + 800a0b0: 4649 mov r1, r9 + 800a0b2: f7f6 f8cd bl 8000250 <__aeabi_uldivmod> + 800a0b6: 4602 mov r2, r0 + 800a0b8: 460b mov r3, r1 + 800a0ba: 4613 mov r3, r2 + 800a0bc: 60fb str r3, [r7, #12] + buf[0] = ( uint8_t )( ( chan >> 24 ) & 0xFF ); + 800a0be: 68fb ldr r3, [r7, #12] + 800a0c0: 0e1b lsrs r3, r3, #24 + 800a0c2: b2db uxtb r3, r3 + 800a0c4: 723b strb r3, [r7, #8] + buf[1] = ( uint8_t )( ( chan >> 16 ) & 0xFF ); + 800a0c6: 68fb ldr r3, [r7, #12] + 800a0c8: 0c1b lsrs r3, r3, #16 + 800a0ca: b2db uxtb r3, r3 + 800a0cc: 727b strb r3, [r7, #9] + buf[2] = ( uint8_t )( ( chan >> 8 ) & 0xFF ); + 800a0ce: 68fb ldr r3, [r7, #12] + 800a0d0: 0a1b lsrs r3, r3, #8 + 800a0d2: b2db uxtb r3, r3 + 800a0d4: 72bb strb r3, [r7, #10] + buf[3] = ( uint8_t )( chan & 0xFF ); + 800a0d6: 68fb ldr r3, [r7, #12] + 800a0d8: b2db uxtb r3, r3 + 800a0da: 72fb strb r3, [r7, #11] + SUBGRF_WriteCommand( RADIO_SET_RFFREQUENCY, buf, 4 ); + 800a0dc: f107 0308 add.w r3, r7, #8 + 800a0e0: 2204 movs r2, #4 + 800a0e2: 4619 mov r1, r3 + 800a0e4: 2086 movs r0, #134 @ 0x86 + 800a0e6: f000 fbdb bl 800a8a0 +} + 800a0ea: bf00 nop + 800a0ec: 3710 adds r7, #16 + 800a0ee: 46bd mov sp, r7 + 800a0f0: e8bd 83b0 ldmia.w sp!, {r4, r5, r7, r8, r9, pc} + 800a0f4: 20000394 .word 0x20000394 + 800a0f8: 01e84800 .word 0x01e84800 + +0800a0fc : + +void SUBGRF_SetPacketType( RadioPacketTypes_t packetType ) +{ + 800a0fc: b580 push {r7, lr} + 800a0fe: b082 sub sp, #8 + 800a100: af00 add r7, sp, #0 + 800a102: 4603 mov r3, r0 + 800a104: 71fb strb r3, [r7, #7] + // Save packet type internally to avoid questioning the radio + PacketType = packetType; + 800a106: 79fa ldrb r2, [r7, #7] + 800a108: 4b09 ldr r3, [pc, #36] @ (800a130 ) + 800a10a: 701a strb r2, [r3, #0] + + if( packetType == PACKET_TYPE_GFSK ) + 800a10c: 79fb ldrb r3, [r7, #7] + 800a10e: 2b00 cmp r3, #0 + 800a110: d104 bne.n 800a11c + { + SUBGRF_WriteRegister( REG_BIT_SYNC, 0x00 ); + 800a112: 2100 movs r1, #0 + 800a114: f240 60ac movw r0, #1708 @ 0x6ac + 800a118: f000 faf8 bl 800a70c + } + SUBGRF_WriteCommand( RADIO_SET_PACKETTYPE, ( uint8_t* )&packetType, 1 ); + 800a11c: 1dfb adds r3, r7, #7 + 800a11e: 2201 movs r2, #1 + 800a120: 4619 mov r1, r3 + 800a122: 208a movs r0, #138 @ 0x8a + 800a124: f000 fbbc bl 800a8a0 +} + 800a128: bf00 nop + 800a12a: 3708 adds r7, #8 + 800a12c: 46bd mov sp, r7 + 800a12e: bd80 pop {r7, pc} + 800a130: 2000038d .word 0x2000038d + +0800a134 : + +RadioPacketTypes_t SUBGRF_GetPacketType( void ) +{ + 800a134: b480 push {r7} + 800a136: af00 add r7, sp, #0 + return PacketType; + 800a138: 4b02 ldr r3, [pc, #8] @ (800a144 ) + 800a13a: 781b ldrb r3, [r3, #0] +} + 800a13c: 4618 mov r0, r3 + 800a13e: 46bd mov sp, r7 + 800a140: bc80 pop {r7} + 800a142: 4770 bx lr + 800a144: 2000038d .word 0x2000038d + +0800a148 : + +void SUBGRF_SetTxParams( uint8_t paSelect, int8_t power, RadioRampTimes_t rampTime ) +{ + 800a148: b580 push {r7, lr} + 800a14a: b084 sub sp, #16 + 800a14c: af00 add r7, sp, #0 + 800a14e: 4603 mov r3, r0 + 800a150: 71fb strb r3, [r7, #7] + 800a152: 460b mov r3, r1 + 800a154: 71bb strb r3, [r7, #6] + 800a156: 4613 mov r3, r2 + 800a158: 717b strb r3, [r7, #5] + uint8_t buf[2]; + int32_t max_power; + + if (paSelect == RFO_LP) + 800a15a: 79fb ldrb r3, [r7, #7] + 800a15c: 2b01 cmp r3, #1 + 800a15e: d149 bne.n 800a1f4 + { + max_power = RBI_GetRFOMaxPowerConfig(RBI_RFO_LP_MAXPOWER); + 800a160: 2000 movs r0, #0 + 800a162: f002 ffaf bl 800d0c4 + 800a166: 60f8 str r0, [r7, #12] + if (power > max_power) + 800a168: f997 3006 ldrsb.w r3, [r7, #6] + 800a16c: 68fa ldr r2, [r7, #12] + 800a16e: 429a cmp r2, r3 + 800a170: da01 bge.n 800a176 + { + power = max_power; + 800a172: 68fb ldr r3, [r7, #12] + 800a174: 71bb strb r3, [r7, #6] + } + if (max_power == 14) + 800a176: 68fb ldr r3, [r7, #12] + 800a178: 2b0e cmp r3, #14 + 800a17a: d10e bne.n 800a19a + { + SUBGRF_SetPaConfig(0x04, 0x00, 0x01, 0x01); + 800a17c: 2301 movs r3, #1 + 800a17e: 2201 movs r2, #1 + 800a180: 2100 movs r1, #0 + 800a182: 2004 movs r0, #4 + 800a184: f7ff fef6 bl 8009f74 + power = 0x0E - (max_power - power); + 800a188: 79ba ldrb r2, [r7, #6] + 800a18a: 68fb ldr r3, [r7, #12] + 800a18c: b2db uxtb r3, r3 + 800a18e: 1ad3 subs r3, r2, r3 + 800a190: b2db uxtb r3, r3 + 800a192: 330e adds r3, #14 + 800a194: b2db uxtb r3, r3 + 800a196: 71bb strb r3, [r7, #6] + 800a198: e01f b.n 800a1da + } + else if (max_power == 10) + 800a19a: 68fb ldr r3, [r7, #12] + 800a19c: 2b0a cmp r3, #10 + 800a19e: d10e bne.n 800a1be + { + SUBGRF_SetPaConfig(0x01, 0x00, 0x01, 0x01); + 800a1a0: 2301 movs r3, #1 + 800a1a2: 2201 movs r2, #1 + 800a1a4: 2100 movs r1, #0 + 800a1a6: 2001 movs r0, #1 + 800a1a8: f7ff fee4 bl 8009f74 + power = 0x0D - (max_power - power); + 800a1ac: 79ba ldrb r2, [r7, #6] + 800a1ae: 68fb ldr r3, [r7, #12] + 800a1b0: b2db uxtb r3, r3 + 800a1b2: 1ad3 subs r3, r2, r3 + 800a1b4: b2db uxtb r3, r3 + 800a1b6: 330d adds r3, #13 + 800a1b8: b2db uxtb r3, r3 + 800a1ba: 71bb strb r3, [r7, #6] + 800a1bc: e00d b.n 800a1da + } + else /*default 15dBm*/ + { + SUBGRF_SetPaConfig(0x07, 0x00, 0x01, 0x01); + 800a1be: 2301 movs r3, #1 + 800a1c0: 2201 movs r2, #1 + 800a1c2: 2100 movs r1, #0 + 800a1c4: 2007 movs r0, #7 + 800a1c6: f7ff fed5 bl 8009f74 + power = 0x0E - (max_power - power); + 800a1ca: 79ba ldrb r2, [r7, #6] + 800a1cc: 68fb ldr r3, [r7, #12] + 800a1ce: b2db uxtb r3, r3 + 800a1d0: 1ad3 subs r3, r2, r3 + 800a1d2: b2db uxtb r3, r3 + 800a1d4: 330e adds r3, #14 + 800a1d6: b2db uxtb r3, r3 + 800a1d8: 71bb strb r3, [r7, #6] + } + if (power < -17) + 800a1da: f997 3006 ldrsb.w r3, [r7, #6] + 800a1de: f113 0f11 cmn.w r3, #17 + 800a1e2: da01 bge.n 800a1e8 + { + power = -17; + 800a1e4: 23ef movs r3, #239 @ 0xef + 800a1e6: 71bb strb r3, [r7, #6] + } + SUBGRF_WriteRegister(REG_OCP, 0x18); /* current max is 80 mA for the whole device*/ + 800a1e8: 2118 movs r1, #24 + 800a1ea: f640 00e7 movw r0, #2279 @ 0x8e7 + 800a1ee: f000 fa8d bl 800a70c + 800a1f2: e067 b.n 800a2c4 + } + else /* rfo_hp*/ + { + /* WORKAROUND - Better Resistance of the RFO High Power Tx to Antenna Mismatch, see STM32WL Erratasheet*/ + SUBGRF_WriteRegister(REG_TX_CLAMP, SUBGRF_ReadRegister(REG_TX_CLAMP) | (0x0F << 1)); + 800a1f4: f640 00d8 movw r0, #2264 @ 0x8d8 + 800a1f8: f000 faaa bl 800a750 + 800a1fc: 4603 mov r3, r0 + 800a1fe: f043 031e orr.w r3, r3, #30 + 800a202: b2db uxtb r3, r3 + 800a204: 4619 mov r1, r3 + 800a206: f640 00d8 movw r0, #2264 @ 0x8d8 + 800a20a: f000 fa7f bl 800a70c + /* WORKAROUND END*/ + max_power = RBI_GetRFOMaxPowerConfig(RBI_RFO_HP_MAXPOWER); + 800a20e: 2001 movs r0, #1 + 800a210: f002 ff58 bl 800d0c4 + 800a214: 60f8 str r0, [r7, #12] + if (power > max_power) + 800a216: f997 3006 ldrsb.w r3, [r7, #6] + 800a21a: 68fa ldr r2, [r7, #12] + 800a21c: 429a cmp r2, r3 + 800a21e: da01 bge.n 800a224 + { + power = max_power; + 800a220: 68fb ldr r3, [r7, #12] + 800a222: 71bb strb r3, [r7, #6] + } + if (max_power == 20) + 800a224: 68fb ldr r3, [r7, #12] + 800a226: 2b14 cmp r3, #20 + 800a228: d10e bne.n 800a248 + { + SUBGRF_SetPaConfig(0x03, 0x05, 0x00, 0x01); + 800a22a: 2301 movs r3, #1 + 800a22c: 2200 movs r2, #0 + 800a22e: 2105 movs r1, #5 + 800a230: 2003 movs r0, #3 + 800a232: f7ff fe9f bl 8009f74 + power = 0x16 - (max_power - power); + 800a236: 79ba ldrb r2, [r7, #6] + 800a238: 68fb ldr r3, [r7, #12] + 800a23a: b2db uxtb r3, r3 + 800a23c: 1ad3 subs r3, r2, r3 + 800a23e: b2db uxtb r3, r3 + 800a240: 3316 adds r3, #22 + 800a242: b2db uxtb r3, r3 + 800a244: 71bb strb r3, [r7, #6] + 800a246: e031 b.n 800a2ac + } + else if (max_power == 17) + 800a248: 68fb ldr r3, [r7, #12] + 800a24a: 2b11 cmp r3, #17 + 800a24c: d10e bne.n 800a26c + { + SUBGRF_SetPaConfig(0x02, 0x03, 0x00, 0x01); + 800a24e: 2301 movs r3, #1 + 800a250: 2200 movs r2, #0 + 800a252: 2103 movs r1, #3 + 800a254: 2002 movs r0, #2 + 800a256: f7ff fe8d bl 8009f74 + power = 0x16 - (max_power - power); + 800a25a: 79ba ldrb r2, [r7, #6] + 800a25c: 68fb ldr r3, [r7, #12] + 800a25e: b2db uxtb r3, r3 + 800a260: 1ad3 subs r3, r2, r3 + 800a262: b2db uxtb r3, r3 + 800a264: 3316 adds r3, #22 + 800a266: b2db uxtb r3, r3 + 800a268: 71bb strb r3, [r7, #6] + 800a26a: e01f b.n 800a2ac + } + else if (max_power == 14) + 800a26c: 68fb ldr r3, [r7, #12] + 800a26e: 2b0e cmp r3, #14 + 800a270: d10e bne.n 800a290 + { + SUBGRF_SetPaConfig(0x02, 0x02, 0x00, 0x01); + 800a272: 2301 movs r3, #1 + 800a274: 2200 movs r2, #0 + 800a276: 2102 movs r1, #2 + 800a278: 2002 movs r0, #2 + 800a27a: f7ff fe7b bl 8009f74 + power = 0x0E - (max_power - power); + 800a27e: 79ba ldrb r2, [r7, #6] + 800a280: 68fb ldr r3, [r7, #12] + 800a282: b2db uxtb r3, r3 + 800a284: 1ad3 subs r3, r2, r3 + 800a286: b2db uxtb r3, r3 + 800a288: 330e adds r3, #14 + 800a28a: b2db uxtb r3, r3 + 800a28c: 71bb strb r3, [r7, #6] + 800a28e: e00d b.n 800a2ac + } + else /*22dBm*/ + { + SUBGRF_SetPaConfig(0x04, 0x07, 0x00, 0x01); + 800a290: 2301 movs r3, #1 + 800a292: 2200 movs r2, #0 + 800a294: 2107 movs r1, #7 + 800a296: 2004 movs r0, #4 + 800a298: f7ff fe6c bl 8009f74 + power = 0x16 - (max_power - power); + 800a29c: 79ba ldrb r2, [r7, #6] + 800a29e: 68fb ldr r3, [r7, #12] + 800a2a0: b2db uxtb r3, r3 + 800a2a2: 1ad3 subs r3, r2, r3 + 800a2a4: b2db uxtb r3, r3 + 800a2a6: 3316 adds r3, #22 + 800a2a8: b2db uxtb r3, r3 + 800a2aa: 71bb strb r3, [r7, #6] + } + if (power < -9) + 800a2ac: f997 3006 ldrsb.w r3, [r7, #6] + 800a2b0: f113 0f09 cmn.w r3, #9 + 800a2b4: da01 bge.n 800a2ba + { + power = -9; + 800a2b6: 23f7 movs r3, #247 @ 0xf7 + 800a2b8: 71bb strb r3, [r7, #6] + } + SUBGRF_WriteRegister(REG_OCP, 0x38); /*current max 160mA for the whole device*/ + 800a2ba: 2138 movs r1, #56 @ 0x38 + 800a2bc: f640 00e7 movw r0, #2279 @ 0x8e7 + 800a2c0: f000 fa24 bl 800a70c + } + buf[0] = power; + 800a2c4: 79bb ldrb r3, [r7, #6] + 800a2c6: 723b strb r3, [r7, #8] + buf[1] = (uint8_t)rampTime; + 800a2c8: 797b ldrb r3, [r7, #5] + 800a2ca: 727b strb r3, [r7, #9] + SUBGRF_WriteCommand(RADIO_SET_TXPARAMS, buf, 2); + 800a2cc: f107 0308 add.w r3, r7, #8 + 800a2d0: 2202 movs r2, #2 + 800a2d2: 4619 mov r1, r3 + 800a2d4: 208e movs r0, #142 @ 0x8e + 800a2d6: f000 fae3 bl 800a8a0 +} + 800a2da: bf00 nop + 800a2dc: 3710 adds r7, #16 + 800a2de: 46bd mov sp, r7 + 800a2e0: bd80 pop {r7, pc} + ... + +0800a2e4 : + +void SUBGRF_SetModulationParams( ModulationParams_t *modulationParams ) +{ + 800a2e4: e92d 43b0 stmdb sp!, {r4, r5, r7, r8, r9, lr} + 800a2e8: b086 sub sp, #24 + 800a2ea: af00 add r7, sp, #0 + 800a2ec: 6078 str r0, [r7, #4] + uint8_t n; + uint32_t tempVal = 0; + 800a2ee: 2300 movs r3, #0 + 800a2f0: 617b str r3, [r7, #20] + uint8_t buf[8] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; + 800a2f2: f107 0308 add.w r3, r7, #8 + 800a2f6: 2200 movs r2, #0 + 800a2f8: 601a str r2, [r3, #0] + 800a2fa: 605a str r2, [r3, #4] + + // Check if required configuration corresponds to the stored packet type + // If not, silently update radio packet type + if( PacketType != modulationParams->PacketType ) + 800a2fc: 687b ldr r3, [r7, #4] + 800a2fe: 781a ldrb r2, [r3, #0] + 800a300: 4b5c ldr r3, [pc, #368] @ (800a474 ) + 800a302: 781b ldrb r3, [r3, #0] + 800a304: 429a cmp r2, r3 + 800a306: d004 beq.n 800a312 + { + SUBGRF_SetPacketType( modulationParams->PacketType ); + 800a308: 687b ldr r3, [r7, #4] + 800a30a: 781b ldrb r3, [r3, #0] + 800a30c: 4618 mov r0, r3 + 800a30e: f7ff fef5 bl 800a0fc + } + + switch( modulationParams->PacketType ) + 800a312: 687b ldr r3, [r7, #4] + 800a314: 781b ldrb r3, [r3, #0] + 800a316: 2b03 cmp r3, #3 + 800a318: f200 80a5 bhi.w 800a466 + 800a31c: a201 add r2, pc, #4 @ (adr r2, 800a324 ) + 800a31e: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 800a322: bf00 nop + 800a324: 0800a335 .word 0x0800a335 + 800a328: 0800a3f5 .word 0x0800a3f5 + 800a32c: 0800a3b7 .word 0x0800a3b7 + 800a330: 0800a423 .word 0x0800a423 + { + case PACKET_TYPE_GFSK: + n = 8; + 800a334: 2308 movs r3, #8 + 800a336: 74fb strb r3, [r7, #19] + tempVal = ( uint32_t )(( 32 * XTAL_FREQ ) / modulationParams->Params.Gfsk.BitRate ); + 800a338: 687b ldr r3, [r7, #4] + 800a33a: 685b ldr r3, [r3, #4] + 800a33c: 4a4e ldr r2, [pc, #312] @ (800a478 ) + 800a33e: fbb2 f3f3 udiv r3, r2, r3 + 800a342: 617b str r3, [r7, #20] + buf[0] = ( tempVal >> 16 ) & 0xFF; + 800a344: 697b ldr r3, [r7, #20] + 800a346: 0c1b lsrs r3, r3, #16 + 800a348: b2db uxtb r3, r3 + 800a34a: 723b strb r3, [r7, #8] + buf[1] = ( tempVal >> 8 ) & 0xFF; + 800a34c: 697b ldr r3, [r7, #20] + 800a34e: 0a1b lsrs r3, r3, #8 + 800a350: b2db uxtb r3, r3 + 800a352: 727b strb r3, [r7, #9] + buf[2] = tempVal & 0xFF; + 800a354: 697b ldr r3, [r7, #20] + 800a356: b2db uxtb r3, r3 + 800a358: 72bb strb r3, [r7, #10] + buf[3] = modulationParams->Params.Gfsk.ModulationShaping; + 800a35a: 687b ldr r3, [r7, #4] + 800a35c: 7b1b ldrb r3, [r3, #12] + 800a35e: 72fb strb r3, [r7, #11] + buf[4] = modulationParams->Params.Gfsk.Bandwidth; + 800a360: 687b ldr r3, [r7, #4] + 800a362: 7b5b ldrb r3, [r3, #13] + 800a364: 733b strb r3, [r7, #12] + SX_FREQ_TO_CHANNEL(tempVal, modulationParams->Params.Gfsk.Fdev); + 800a366: 687b ldr r3, [r7, #4] + 800a368: 689b ldr r3, [r3, #8] + 800a36a: 2200 movs r2, #0 + 800a36c: 461c mov r4, r3 + 800a36e: 4615 mov r5, r2 + 800a370: ea4f 19d4 mov.w r9, r4, lsr #7 + 800a374: ea4f 6844 mov.w r8, r4, lsl #25 + 800a378: 4a40 ldr r2, [pc, #256] @ (800a47c ) + 800a37a: f04f 0300 mov.w r3, #0 + 800a37e: 4640 mov r0, r8 + 800a380: 4649 mov r1, r9 + 800a382: f7f5 ff65 bl 8000250 <__aeabi_uldivmod> + 800a386: 4602 mov r2, r0 + 800a388: 460b mov r3, r1 + 800a38a: 4613 mov r3, r2 + 800a38c: 617b str r3, [r7, #20] + buf[5] = ( tempVal >> 16 ) & 0xFF; + 800a38e: 697b ldr r3, [r7, #20] + 800a390: 0c1b lsrs r3, r3, #16 + 800a392: b2db uxtb r3, r3 + 800a394: 737b strb r3, [r7, #13] + buf[6] = ( tempVal >> 8 ) & 0xFF; + 800a396: 697b ldr r3, [r7, #20] + 800a398: 0a1b lsrs r3, r3, #8 + 800a39a: b2db uxtb r3, r3 + 800a39c: 73bb strb r3, [r7, #14] + buf[7] = ( tempVal& 0xFF ); + 800a39e: 697b ldr r3, [r7, #20] + 800a3a0: b2db uxtb r3, r3 + 800a3a2: 73fb strb r3, [r7, #15] + SUBGRF_WriteCommand( RADIO_SET_MODULATIONPARAMS, buf, n ); + 800a3a4: 7cfb ldrb r3, [r7, #19] + 800a3a6: b29a uxth r2, r3 + 800a3a8: f107 0308 add.w r3, r7, #8 + 800a3ac: 4619 mov r1, r3 + 800a3ae: 208b movs r0, #139 @ 0x8b + 800a3b0: f000 fa76 bl 800a8a0 + break; + 800a3b4: e058 b.n 800a468 + case PACKET_TYPE_BPSK: + n = 4; + 800a3b6: 2304 movs r3, #4 + 800a3b8: 74fb strb r3, [r7, #19] + tempVal = ( uint32_t ) (( 32 * XTAL_FREQ) / modulationParams->Params.Bpsk.BitRate ); + 800a3ba: 687b ldr r3, [r7, #4] + 800a3bc: 691b ldr r3, [r3, #16] + 800a3be: 4a2e ldr r2, [pc, #184] @ (800a478 ) + 800a3c0: fbb2 f3f3 udiv r3, r2, r3 + 800a3c4: 617b str r3, [r7, #20] + buf[0] = ( tempVal >> 16 ) & 0xFF; + 800a3c6: 697b ldr r3, [r7, #20] + 800a3c8: 0c1b lsrs r3, r3, #16 + 800a3ca: b2db uxtb r3, r3 + 800a3cc: 723b strb r3, [r7, #8] + buf[1] = ( tempVal >> 8 ) & 0xFF; + 800a3ce: 697b ldr r3, [r7, #20] + 800a3d0: 0a1b lsrs r3, r3, #8 + 800a3d2: b2db uxtb r3, r3 + 800a3d4: 727b strb r3, [r7, #9] + buf[2] = tempVal & 0xFF; + 800a3d6: 697b ldr r3, [r7, #20] + 800a3d8: b2db uxtb r3, r3 + 800a3da: 72bb strb r3, [r7, #10] + buf[3] = modulationParams->Params.Bpsk.ModulationShaping; + 800a3dc: 687b ldr r3, [r7, #4] + 800a3de: 7d1b ldrb r3, [r3, #20] + 800a3e0: 72fb strb r3, [r7, #11] + SUBGRF_WriteCommand( RADIO_SET_MODULATIONPARAMS, buf, n ); + 800a3e2: 7cfb ldrb r3, [r7, #19] + 800a3e4: b29a uxth r2, r3 + 800a3e6: f107 0308 add.w r3, r7, #8 + 800a3ea: 4619 mov r1, r3 + 800a3ec: 208b movs r0, #139 @ 0x8b + 800a3ee: f000 fa57 bl 800a8a0 + break; + 800a3f2: e039 b.n 800a468 + case PACKET_TYPE_LORA: + n = 4; + 800a3f4: 2304 movs r3, #4 + 800a3f6: 74fb strb r3, [r7, #19] + buf[0] = modulationParams->Params.LoRa.SpreadingFactor; + 800a3f8: 687b ldr r3, [r7, #4] + 800a3fa: 7e1b ldrb r3, [r3, #24] + 800a3fc: 723b strb r3, [r7, #8] + buf[1] = modulationParams->Params.LoRa.Bandwidth; + 800a3fe: 687b ldr r3, [r7, #4] + 800a400: 7e5b ldrb r3, [r3, #25] + 800a402: 727b strb r3, [r7, #9] + buf[2] = modulationParams->Params.LoRa.CodingRate; + 800a404: 687b ldr r3, [r7, #4] + 800a406: 7e9b ldrb r3, [r3, #26] + 800a408: 72bb strb r3, [r7, #10] + buf[3] = modulationParams->Params.LoRa.LowDatarateOptimize; + 800a40a: 687b ldr r3, [r7, #4] + 800a40c: 7edb ldrb r3, [r3, #27] + 800a40e: 72fb strb r3, [r7, #11] + + SUBGRF_WriteCommand( RADIO_SET_MODULATIONPARAMS, buf, n ); + 800a410: 7cfb ldrb r3, [r7, #19] + 800a412: b29a uxth r2, r3 + 800a414: f107 0308 add.w r3, r7, #8 + 800a418: 4619 mov r1, r3 + 800a41a: 208b movs r0, #139 @ 0x8b + 800a41c: f000 fa40 bl 800a8a0 + + break; + 800a420: e022 b.n 800a468 + case PACKET_TYPE_GMSK: + n = 5; + 800a422: 2305 movs r3, #5 + 800a424: 74fb strb r3, [r7, #19] + tempVal = ( uint32_t )(( 32 *XTAL_FREQ) / modulationParams->Params.Gfsk.BitRate ); + 800a426: 687b ldr r3, [r7, #4] + 800a428: 685b ldr r3, [r3, #4] + 800a42a: 4a13 ldr r2, [pc, #76] @ (800a478 ) + 800a42c: fbb2 f3f3 udiv r3, r2, r3 + 800a430: 617b str r3, [r7, #20] + buf[0] = ( tempVal >> 16 ) & 0xFF; + 800a432: 697b ldr r3, [r7, #20] + 800a434: 0c1b lsrs r3, r3, #16 + 800a436: b2db uxtb r3, r3 + 800a438: 723b strb r3, [r7, #8] + buf[1] = ( tempVal >> 8 ) & 0xFF; + 800a43a: 697b ldr r3, [r7, #20] + 800a43c: 0a1b lsrs r3, r3, #8 + 800a43e: b2db uxtb r3, r3 + 800a440: 727b strb r3, [r7, #9] + buf[2] = tempVal & 0xFF; + 800a442: 697b ldr r3, [r7, #20] + 800a444: b2db uxtb r3, r3 + 800a446: 72bb strb r3, [r7, #10] + buf[3] = modulationParams->Params.Gfsk.ModulationShaping; + 800a448: 687b ldr r3, [r7, #4] + 800a44a: 7b1b ldrb r3, [r3, #12] + 800a44c: 72fb strb r3, [r7, #11] + buf[4] = modulationParams->Params.Gfsk.Bandwidth; + 800a44e: 687b ldr r3, [r7, #4] + 800a450: 7b5b ldrb r3, [r3, #13] + 800a452: 733b strb r3, [r7, #12] + SUBGRF_WriteCommand( RADIO_SET_MODULATIONPARAMS, buf, n ); + 800a454: 7cfb ldrb r3, [r7, #19] + 800a456: b29a uxth r2, r3 + 800a458: f107 0308 add.w r3, r7, #8 + 800a45c: 4619 mov r1, r3 + 800a45e: 208b movs r0, #139 @ 0x8b + 800a460: f000 fa1e bl 800a8a0 + break; + 800a464: e000 b.n 800a468 + default: + case PACKET_TYPE_NONE: + break; + 800a466: bf00 nop + } +} + 800a468: bf00 nop + 800a46a: 3718 adds r7, #24 + 800a46c: 46bd mov sp, r7 + 800a46e: e8bd 83b0 ldmia.w sp!, {r4, r5, r7, r8, r9, pc} + 800a472: bf00 nop + 800a474: 2000038d .word 0x2000038d + 800a478: 3d090000 .word 0x3d090000 + 800a47c: 01e84800 .word 0x01e84800 + +0800a480 : + +void SUBGRF_SetPacketParams( PacketParams_t *packetParams ) +{ + 800a480: b580 push {r7, lr} + 800a482: b086 sub sp, #24 + 800a484: af00 add r7, sp, #0 + 800a486: 6078 str r0, [r7, #4] + uint8_t n; + uint8_t crcVal = 0; + 800a488: 2300 movs r3, #0 + 800a48a: 75bb strb r3, [r7, #22] + uint8_t buf[9] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; + 800a48c: f107 030c add.w r3, r7, #12 + 800a490: 2200 movs r2, #0 + 800a492: 601a str r2, [r3, #0] + 800a494: 605a str r2, [r3, #4] + 800a496: 721a strb r2, [r3, #8] + + // Check if required configuration corresponds to the stored packet type + // If not, silently update radio packet type + if( PacketType != packetParams->PacketType ) + 800a498: 687b ldr r3, [r7, #4] + 800a49a: 781a ldrb r2, [r3, #0] + 800a49c: 4b44 ldr r3, [pc, #272] @ (800a5b0 ) + 800a49e: 781b ldrb r3, [r3, #0] + 800a4a0: 429a cmp r2, r3 + 800a4a2: d004 beq.n 800a4ae + { + SUBGRF_SetPacketType( packetParams->PacketType ); + 800a4a4: 687b ldr r3, [r7, #4] + 800a4a6: 781b ldrb r3, [r3, #0] + 800a4a8: 4618 mov r0, r3 + 800a4aa: f7ff fe27 bl 800a0fc + } + + switch( packetParams->PacketType ) + 800a4ae: 687b ldr r3, [r7, #4] + 800a4b0: 781b ldrb r3, [r3, #0] + 800a4b2: 2b03 cmp r3, #3 + 800a4b4: d878 bhi.n 800a5a8 + 800a4b6: a201 add r2, pc, #4 @ (adr r2, 800a4bc ) + 800a4b8: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 800a4bc: 0800a4cd .word 0x0800a4cd + 800a4c0: 0800a55d .word 0x0800a55d + 800a4c4: 0800a551 .word 0x0800a551 + 800a4c8: 0800a4cd .word 0x0800a4cd + { + case PACKET_TYPE_GMSK: + case PACKET_TYPE_GFSK: + if( packetParams->Params.Gfsk.CrcLength == RADIO_CRC_2_BYTES_IBM ) + 800a4cc: 687b ldr r3, [r7, #4] + 800a4ce: 7a5b ldrb r3, [r3, #9] + 800a4d0: 2bf1 cmp r3, #241 @ 0xf1 + 800a4d2: d10a bne.n 800a4ea + { + SUBGRF_SetCrcSeed( CRC_IBM_SEED ); + 800a4d4: f64f 70ff movw r0, #65535 @ 0xffff + 800a4d8: f7ff faa6 bl 8009a28 + SUBGRF_SetCrcPolynomial( CRC_POLYNOMIAL_IBM ); + 800a4dc: f248 0005 movw r0, #32773 @ 0x8005 + 800a4e0: f7ff fac2 bl 8009a68 + crcVal = RADIO_CRC_2_BYTES; + 800a4e4: 2302 movs r3, #2 + 800a4e6: 75bb strb r3, [r7, #22] + 800a4e8: e011 b.n 800a50e + } + else if( packetParams->Params.Gfsk.CrcLength == RADIO_CRC_2_BYTES_CCIT ) + 800a4ea: 687b ldr r3, [r7, #4] + 800a4ec: 7a5b ldrb r3, [r3, #9] + 800a4ee: 2bf2 cmp r3, #242 @ 0xf2 + 800a4f0: d10a bne.n 800a508 + { + SUBGRF_SetCrcSeed( CRC_CCITT_SEED ); + 800a4f2: f641 500f movw r0, #7439 @ 0x1d0f + 800a4f6: f7ff fa97 bl 8009a28 + SUBGRF_SetCrcPolynomial( CRC_POLYNOMIAL_CCITT ); + 800a4fa: f241 0021 movw r0, #4129 @ 0x1021 + 800a4fe: f7ff fab3 bl 8009a68 + crcVal = RADIO_CRC_2_BYTES_INV; + 800a502: 2306 movs r3, #6 + 800a504: 75bb strb r3, [r7, #22] + 800a506: e002 b.n 800a50e + } + else + { + crcVal = packetParams->Params.Gfsk.CrcLength; + 800a508: 687b ldr r3, [r7, #4] + 800a50a: 7a5b ldrb r3, [r3, #9] + 800a50c: 75bb strb r3, [r7, #22] + } + n = 9; + 800a50e: 2309 movs r3, #9 + 800a510: 75fb strb r3, [r7, #23] + buf[0] = ( packetParams->Params.Gfsk.PreambleLength >> 8 ) & 0xFF; + 800a512: 687b ldr r3, [r7, #4] + 800a514: 885b ldrh r3, [r3, #2] + 800a516: 0a1b lsrs r3, r3, #8 + 800a518: b29b uxth r3, r3 + 800a51a: b2db uxtb r3, r3 + 800a51c: 733b strb r3, [r7, #12] + buf[1] = packetParams->Params.Gfsk.PreambleLength; + 800a51e: 687b ldr r3, [r7, #4] + 800a520: 885b ldrh r3, [r3, #2] + 800a522: b2db uxtb r3, r3 + 800a524: 737b strb r3, [r7, #13] + buf[2] = packetParams->Params.Gfsk.PreambleMinDetect; + 800a526: 687b ldr r3, [r7, #4] + 800a528: 791b ldrb r3, [r3, #4] + 800a52a: 73bb strb r3, [r7, #14] + buf[3] = ( packetParams->Params.Gfsk.SyncWordLength /*<< 3*/ ); // convert from byte to bit + 800a52c: 687b ldr r3, [r7, #4] + 800a52e: 795b ldrb r3, [r3, #5] + 800a530: 73fb strb r3, [r7, #15] + buf[4] = packetParams->Params.Gfsk.AddrComp; + 800a532: 687b ldr r3, [r7, #4] + 800a534: 799b ldrb r3, [r3, #6] + 800a536: 743b strb r3, [r7, #16] + buf[5] = packetParams->Params.Gfsk.HeaderType; + 800a538: 687b ldr r3, [r7, #4] + 800a53a: 79db ldrb r3, [r3, #7] + 800a53c: 747b strb r3, [r7, #17] + buf[6] = packetParams->Params.Gfsk.PayloadLength; + 800a53e: 687b ldr r3, [r7, #4] + 800a540: 7a1b ldrb r3, [r3, #8] + 800a542: 74bb strb r3, [r7, #18] + buf[7] = crcVal; + 800a544: 7dbb ldrb r3, [r7, #22] + 800a546: 74fb strb r3, [r7, #19] + buf[8] = packetParams->Params.Gfsk.DcFree; + 800a548: 687b ldr r3, [r7, #4] + 800a54a: 7a9b ldrb r3, [r3, #10] + 800a54c: 753b strb r3, [r7, #20] + break; + 800a54e: e022 b.n 800a596 + case PACKET_TYPE_BPSK: + n = 1; + 800a550: 2301 movs r3, #1 + 800a552: 75fb strb r3, [r7, #23] + buf[0] = packetParams->Params.Bpsk.PayloadLength; + 800a554: 687b ldr r3, [r7, #4] + 800a556: 7b1b ldrb r3, [r3, #12] + 800a558: 733b strb r3, [r7, #12] + break; + 800a55a: e01c b.n 800a596 + case PACKET_TYPE_LORA: + n = 6; + 800a55c: 2306 movs r3, #6 + 800a55e: 75fb strb r3, [r7, #23] + buf[0] = ( packetParams->Params.LoRa.PreambleLength >> 8 ) & 0xFF; + 800a560: 687b ldr r3, [r7, #4] + 800a562: 89db ldrh r3, [r3, #14] + 800a564: 0a1b lsrs r3, r3, #8 + 800a566: b29b uxth r3, r3 + 800a568: b2db uxtb r3, r3 + 800a56a: 733b strb r3, [r7, #12] + buf[1] = packetParams->Params.LoRa.PreambleLength; + 800a56c: 687b ldr r3, [r7, #4] + 800a56e: 89db ldrh r3, [r3, #14] + 800a570: b2db uxtb r3, r3 + 800a572: 737b strb r3, [r7, #13] + buf[2] = LoRaHeaderType = packetParams->Params.LoRa.HeaderType; + 800a574: 687b ldr r3, [r7, #4] + 800a576: 7c1a ldrb r2, [r3, #16] + 800a578: 4b0e ldr r3, [pc, #56] @ (800a5b4 ) + 800a57a: 4611 mov r1, r2 + 800a57c: 7019 strb r1, [r3, #0] + 800a57e: 4613 mov r3, r2 + 800a580: 73bb strb r3, [r7, #14] + buf[3] = packetParams->Params.LoRa.PayloadLength; + 800a582: 687b ldr r3, [r7, #4] + 800a584: 7c5b ldrb r3, [r3, #17] + 800a586: 73fb strb r3, [r7, #15] + buf[4] = packetParams->Params.LoRa.CrcMode; + 800a588: 687b ldr r3, [r7, #4] + 800a58a: 7c9b ldrb r3, [r3, #18] + 800a58c: 743b strb r3, [r7, #16] + buf[5] = packetParams->Params.LoRa.InvertIQ; + 800a58e: 687b ldr r3, [r7, #4] + 800a590: 7cdb ldrb r3, [r3, #19] + 800a592: 747b strb r3, [r7, #17] + break; + 800a594: bf00 nop + default: + case PACKET_TYPE_NONE: + return; + } + SUBGRF_WriteCommand( RADIO_SET_PACKETPARAMS, buf, n ); + 800a596: 7dfb ldrb r3, [r7, #23] + 800a598: b29a uxth r2, r3 + 800a59a: f107 030c add.w r3, r7, #12 + 800a59e: 4619 mov r1, r3 + 800a5a0: 208c movs r0, #140 @ 0x8c + 800a5a2: f000 f97d bl 800a8a0 + 800a5a6: e000 b.n 800a5aa + return; + 800a5a8: bf00 nop +} + 800a5aa: 3718 adds r7, #24 + 800a5ac: 46bd mov sp, r7 + 800a5ae: bd80 pop {r7, pc} + 800a5b0: 2000038d .word 0x2000038d + 800a5b4: 2000038e .word 0x2000038e + +0800a5b8 : + SUBGRF_WriteCommand( RADIO_SET_CADPARAMS, buf, 7 ); + OperatingMode = MODE_CAD; +} + +void SUBGRF_SetBufferBaseAddress( uint8_t txBaseAddress, uint8_t rxBaseAddress ) +{ + 800a5b8: b580 push {r7, lr} + 800a5ba: b084 sub sp, #16 + 800a5bc: af00 add r7, sp, #0 + 800a5be: 4603 mov r3, r0 + 800a5c0: 460a mov r2, r1 + 800a5c2: 71fb strb r3, [r7, #7] + 800a5c4: 4613 mov r3, r2 + 800a5c6: 71bb strb r3, [r7, #6] + uint8_t buf[2]; + + buf[0] = txBaseAddress; + 800a5c8: 79fb ldrb r3, [r7, #7] + 800a5ca: 733b strb r3, [r7, #12] + buf[1] = rxBaseAddress; + 800a5cc: 79bb ldrb r3, [r7, #6] + 800a5ce: 737b strb r3, [r7, #13] + SUBGRF_WriteCommand( RADIO_SET_BUFFERBASEADDRESS, buf, 2 ); + 800a5d0: f107 030c add.w r3, r7, #12 + 800a5d4: 2202 movs r2, #2 + 800a5d6: 4619 mov r1, r3 + 800a5d8: 208f movs r0, #143 @ 0x8f + 800a5da: f000 f961 bl 800a8a0 +} + 800a5de: bf00 nop + 800a5e0: 3710 adds r7, #16 + 800a5e2: 46bd mov sp, r7 + 800a5e4: bd80 pop {r7, pc} + +0800a5e6 : + status.Fields.ChipMode = ( stat & ( 0x07 << 4 ) ) >> 4; + return status; +} + +int8_t SUBGRF_GetRssiInst( void ) +{ + 800a5e6: b580 push {r7, lr} + 800a5e8: b082 sub sp, #8 + 800a5ea: af00 add r7, sp, #0 + uint8_t buf[1]; + int8_t rssi = 0; + 800a5ec: 2300 movs r3, #0 + 800a5ee: 71fb strb r3, [r7, #7] + + SUBGRF_ReadCommand( RADIO_GET_RSSIINST, buf, 1 ); + 800a5f0: 1d3b adds r3, r7, #4 + 800a5f2: 2201 movs r2, #1 + 800a5f4: 4619 mov r1, r3 + 800a5f6: 2015 movs r0, #21 + 800a5f8: f000 f974 bl 800a8e4 + rssi = -buf[0] >> 1; + 800a5fc: 793b ldrb r3, [r7, #4] + 800a5fe: 425b negs r3, r3 + 800a600: 105b asrs r3, r3, #1 + 800a602: 71fb strb r3, [r7, #7] + return rssi; + 800a604: f997 3007 ldrsb.w r3, [r7, #7] +} + 800a608: 4618 mov r0, r3 + 800a60a: 3708 adds r7, #8 + 800a60c: 46bd mov sp, r7 + 800a60e: bd80 pop {r7, pc} + +0800a610 : + +void SUBGRF_GetRxBufferStatus( uint8_t *payloadLength, uint8_t *rxStartBufferPointer ) +{ + 800a610: b580 push {r7, lr} + 800a612: b084 sub sp, #16 + 800a614: af00 add r7, sp, #0 + 800a616: 6078 str r0, [r7, #4] + 800a618: 6039 str r1, [r7, #0] + uint8_t status[2]; + + SUBGRF_ReadCommand( RADIO_GET_RXBUFFERSTATUS, status, 2 ); + 800a61a: f107 030c add.w r3, r7, #12 + 800a61e: 2202 movs r2, #2 + 800a620: 4619 mov r1, r3 + 800a622: 2013 movs r0, #19 + 800a624: f000 f95e bl 800a8e4 + + // In case of LORA fixed header, the payloadLength is obtained by reading + // the register REG_LR_PAYLOADLENGTH + if( ( SUBGRF_GetPacketType( ) == PACKET_TYPE_LORA ) && ( LoRaHeaderType == LORA_PACKET_FIXED_LENGTH ) ) + 800a628: f7ff fd84 bl 800a134 + 800a62c: 4603 mov r3, r0 + 800a62e: 2b01 cmp r3, #1 + 800a630: d10d bne.n 800a64e + 800a632: 4b0c ldr r3, [pc, #48] @ (800a664 ) + 800a634: 781b ldrb r3, [r3, #0] + 800a636: b2db uxtb r3, r3 + 800a638: 2b01 cmp r3, #1 + 800a63a: d108 bne.n 800a64e + { + *payloadLength = SUBGRF_ReadRegister( REG_LR_PAYLOADLENGTH ); + 800a63c: f240 7002 movw r0, #1794 @ 0x702 + 800a640: f000 f886 bl 800a750 + 800a644: 4603 mov r3, r0 + 800a646: 461a mov r2, r3 + 800a648: 687b ldr r3, [r7, #4] + 800a64a: 701a strb r2, [r3, #0] + 800a64c: e002 b.n 800a654 + } + else + { + *payloadLength = status[0]; + 800a64e: 7b3a ldrb r2, [r7, #12] + 800a650: 687b ldr r3, [r7, #4] + 800a652: 701a strb r2, [r3, #0] + } + *rxStartBufferPointer = status[1]; + 800a654: 7b7a ldrb r2, [r7, #13] + 800a656: 683b ldr r3, [r7, #0] + 800a658: 701a strb r2, [r3, #0] +} + 800a65a: bf00 nop + 800a65c: 3710 adds r7, #16 + 800a65e: 46bd mov sp, r7 + 800a660: bd80 pop {r7, pc} + 800a662: bf00 nop + 800a664: 2000038e .word 0x2000038e + +0800a668 : + +void SUBGRF_GetPacketStatus( PacketStatus_t *pktStatus ) +{ + 800a668: b580 push {r7, lr} + 800a66a: b084 sub sp, #16 + 800a66c: af00 add r7, sp, #0 + 800a66e: 6078 str r0, [r7, #4] + uint8_t status[3]; + + SUBGRF_ReadCommand( RADIO_GET_PACKETSTATUS, status, 3 ); + 800a670: f107 030c add.w r3, r7, #12 + 800a674: 2203 movs r2, #3 + 800a676: 4619 mov r1, r3 + 800a678: 2014 movs r0, #20 + 800a67a: f000 f933 bl 800a8e4 + + pktStatus->packetType = SUBGRF_GetPacketType( ); + 800a67e: f7ff fd59 bl 800a134 + 800a682: 4603 mov r3, r0 + 800a684: 461a mov r2, r3 + 800a686: 687b ldr r3, [r7, #4] + 800a688: 701a strb r2, [r3, #0] + switch( pktStatus->packetType ) + 800a68a: 687b ldr r3, [r7, #4] + 800a68c: 781b ldrb r3, [r3, #0] + 800a68e: 2b00 cmp r3, #0 + 800a690: d002 beq.n 800a698 + 800a692: 2b01 cmp r3, #1 + 800a694: d013 beq.n 800a6be + 800a696: e02a b.n 800a6ee + { + case PACKET_TYPE_GFSK: + pktStatus->Params.Gfsk.RxStatus = status[0]; + 800a698: 7b3a ldrb r2, [r7, #12] + 800a69a: 687b ldr r3, [r7, #4] + 800a69c: 711a strb r2, [r3, #4] + pktStatus->Params.Gfsk.RssiSync = -status[1] >> 1; + 800a69e: 7b7b ldrb r3, [r7, #13] + 800a6a0: 425b negs r3, r3 + 800a6a2: 105b asrs r3, r3, #1 + 800a6a4: b25a sxtb r2, r3 + 800a6a6: 687b ldr r3, [r7, #4] + 800a6a8: 719a strb r2, [r3, #6] + pktStatus->Params.Gfsk.RssiAvg = -status[2] >> 1; + 800a6aa: 7bbb ldrb r3, [r7, #14] + 800a6ac: 425b negs r3, r3 + 800a6ae: 105b asrs r3, r3, #1 + 800a6b0: b25a sxtb r2, r3 + 800a6b2: 687b ldr r3, [r7, #4] + 800a6b4: 715a strb r2, [r3, #5] + pktStatus->Params.Gfsk.FreqError = 0; + 800a6b6: 687b ldr r3, [r7, #4] + 800a6b8: 2200 movs r2, #0 + 800a6ba: 609a str r2, [r3, #8] + break; + 800a6bc: e020 b.n 800a700 + + case PACKET_TYPE_LORA: + pktStatus->Params.LoRa.RssiPkt = -status[0] >> 1; + 800a6be: 7b3b ldrb r3, [r7, #12] + 800a6c0: 425b negs r3, r3 + 800a6c2: 105b asrs r3, r3, #1 + 800a6c4: b25a sxtb r2, r3 + 800a6c6: 687b ldr r3, [r7, #4] + 800a6c8: 731a strb r2, [r3, #12] + // Returns SNR value [dB] rounded to the nearest integer value + pktStatus->Params.LoRa.SnrPkt = ( ( ( int8_t )status[1] ) + 2 ) >> 2; + 800a6ca: 7b7b ldrb r3, [r7, #13] + 800a6cc: b25b sxtb r3, r3 + 800a6ce: 3302 adds r3, #2 + 800a6d0: 109b asrs r3, r3, #2 + 800a6d2: b25a sxtb r2, r3 + 800a6d4: 687b ldr r3, [r7, #4] + 800a6d6: 735a strb r2, [r3, #13] + pktStatus->Params.LoRa.SignalRssiPkt = -status[2] >> 1; + 800a6d8: 7bbb ldrb r3, [r7, #14] + 800a6da: 425b negs r3, r3 + 800a6dc: 105b asrs r3, r3, #1 + 800a6de: b25a sxtb r2, r3 + 800a6e0: 687b ldr r3, [r7, #4] + 800a6e2: 739a strb r2, [r3, #14] + pktStatus->Params.LoRa.FreqError = FrequencyError; + 800a6e4: 4b08 ldr r3, [pc, #32] @ (800a708 ) + 800a6e6: 681a ldr r2, [r3, #0] + 800a6e8: 687b ldr r3, [r7, #4] + 800a6ea: 611a str r2, [r3, #16] + break; + 800a6ec: e008 b.n 800a700 + + default: + case PACKET_TYPE_NONE: + // In that specific case, we set everything in the pktStatus to zeros + // and reset the packet type accordingly + RADIO_MEMSET8( pktStatus, 0, sizeof( PacketStatus_t ) ); + 800a6ee: 2214 movs r2, #20 + 800a6f0: 2100 movs r1, #0 + 800a6f2: 6878 ldr r0, [r7, #4] + 800a6f4: f002 fdb9 bl 800d26a + pktStatus->packetType = PACKET_TYPE_NONE; + 800a6f8: 687b ldr r3, [r7, #4] + 800a6fa: 220f movs r2, #15 + 800a6fc: 701a strb r2, [r3, #0] + break; + 800a6fe: bf00 nop + } +} + 800a700: bf00 nop + 800a702: 3710 adds r7, #16 + 800a704: 46bd mov sp, r7 + 800a706: bd80 pop {r7, pc} + 800a708: 20000390 .word 0x20000390 + +0800a70c : + buf[1] = ( uint8_t )( ( uint16_t )irq & 0x00FF ); + SUBGRF_WriteCommand( RADIO_CLR_IRQSTATUS, buf, 2 ); +} + +void SUBGRF_WriteRegister( uint16_t addr, uint8_t data ) +{ + 800a70c: b580 push {r7, lr} + 800a70e: b086 sub sp, #24 + 800a710: af00 add r7, sp, #0 + 800a712: 4603 mov r3, r0 + 800a714: 460a mov r2, r1 + 800a716: 80fb strh r3, [r7, #6] + 800a718: 4613 mov r3, r2 + 800a71a: 717b strb r3, [r7, #5] + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 800a71c: f3ef 8310 mrs r3, PRIMASK + 800a720: 60fb str r3, [r7, #12] + return(result); + 800a722: 68fb ldr r3, [r7, #12] + CRITICAL_SECTION_BEGIN(); + 800a724: 617b str r3, [r7, #20] + __ASM volatile ("cpsid i" : : : "memory"); + 800a726: b672 cpsid i +} + 800a728: bf00 nop + HAL_SUBGHZ_WriteRegisters( &hsubghz, addr, (uint8_t*)&data, 1 ); + 800a72a: 1d7a adds r2, r7, #5 + 800a72c: 88f9 ldrh r1, [r7, #6] + 800a72e: 2301 movs r3, #1 + 800a730: 4806 ldr r0, [pc, #24] @ (800a74c ) + 800a732: f7fa f94b bl 80049cc + 800a736: 697b ldr r3, [r7, #20] + 800a738: 613b str r3, [r7, #16] + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 800a73a: 693b ldr r3, [r7, #16] + 800a73c: f383 8810 msr PRIMASK, r3 +} + 800a740: bf00 nop + CRITICAL_SECTION_END(); +} + 800a742: bf00 nop + 800a744: 3718 adds r7, #24 + 800a746: 46bd mov sp, r7 + 800a748: bd80 pop {r7, pc} + 800a74a: bf00 nop + 800a74c: 200000e0 .word 0x200000e0 + +0800a750 : + +uint8_t SUBGRF_ReadRegister( uint16_t addr ) +{ + 800a750: b580 push {r7, lr} + 800a752: b086 sub sp, #24 + 800a754: af00 add r7, sp, #0 + 800a756: 4603 mov r3, r0 + 800a758: 80fb strh r3, [r7, #6] + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 800a75a: f3ef 8310 mrs r3, PRIMASK + 800a75e: 60fb str r3, [r7, #12] + return(result); + 800a760: 68fb ldr r3, [r7, #12] + uint8_t data; + CRITICAL_SECTION_BEGIN(); + 800a762: 617b str r3, [r7, #20] + __ASM volatile ("cpsid i" : : : "memory"); + 800a764: b672 cpsid i +} + 800a766: bf00 nop + HAL_SUBGHZ_ReadRegisters( &hsubghz, addr, &data, 1 ); + 800a768: f107 020b add.w r2, r7, #11 + 800a76c: 88f9 ldrh r1, [r7, #6] + 800a76e: 2301 movs r3, #1 + 800a770: 4806 ldr r0, [pc, #24] @ (800a78c ) + 800a772: f7fa f98a bl 8004a8a + 800a776: 697b ldr r3, [r7, #20] + 800a778: 613b str r3, [r7, #16] + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 800a77a: 693b ldr r3, [r7, #16] + 800a77c: f383 8810 msr PRIMASK, r3 +} + 800a780: bf00 nop + CRITICAL_SECTION_END(); + return data; + 800a782: 7afb ldrb r3, [r7, #11] +} + 800a784: 4618 mov r0, r3 + 800a786: 3718 adds r7, #24 + 800a788: 46bd mov sp, r7 + 800a78a: bd80 pop {r7, pc} + 800a78c: 200000e0 .word 0x200000e0 + +0800a790 : + +void SUBGRF_WriteRegisters( uint16_t address, uint8_t *buffer, uint16_t size ) +{ + 800a790: b580 push {r7, lr} + 800a792: b086 sub sp, #24 + 800a794: af00 add r7, sp, #0 + 800a796: 4603 mov r3, r0 + 800a798: 6039 str r1, [r7, #0] + 800a79a: 80fb strh r3, [r7, #6] + 800a79c: 4613 mov r3, r2 + 800a79e: 80bb strh r3, [r7, #4] + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 800a7a0: f3ef 8310 mrs r3, PRIMASK + 800a7a4: 60fb str r3, [r7, #12] + return(result); + 800a7a6: 68fb ldr r3, [r7, #12] + CRITICAL_SECTION_BEGIN(); + 800a7a8: 617b str r3, [r7, #20] + __ASM volatile ("cpsid i" : : : "memory"); + 800a7aa: b672 cpsid i +} + 800a7ac: bf00 nop + HAL_SUBGHZ_WriteRegisters( &hsubghz, address, buffer, size ); + 800a7ae: 88bb ldrh r3, [r7, #4] + 800a7b0: 88f9 ldrh r1, [r7, #6] + 800a7b2: 683a ldr r2, [r7, #0] + 800a7b4: 4806 ldr r0, [pc, #24] @ (800a7d0 ) + 800a7b6: f7fa f909 bl 80049cc + 800a7ba: 697b ldr r3, [r7, #20] + 800a7bc: 613b str r3, [r7, #16] + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 800a7be: 693b ldr r3, [r7, #16] + 800a7c0: f383 8810 msr PRIMASK, r3 +} + 800a7c4: bf00 nop + CRITICAL_SECTION_END(); +} + 800a7c6: bf00 nop + 800a7c8: 3718 adds r7, #24 + 800a7ca: 46bd mov sp, r7 + 800a7cc: bd80 pop {r7, pc} + 800a7ce: bf00 nop + 800a7d0: 200000e0 .word 0x200000e0 + +0800a7d4 : + +void SUBGRF_ReadRegisters( uint16_t address, uint8_t *buffer, uint16_t size ) +{ + 800a7d4: b580 push {r7, lr} + 800a7d6: b086 sub sp, #24 + 800a7d8: af00 add r7, sp, #0 + 800a7da: 4603 mov r3, r0 + 800a7dc: 6039 str r1, [r7, #0] + 800a7de: 80fb strh r3, [r7, #6] + 800a7e0: 4613 mov r3, r2 + 800a7e2: 80bb strh r3, [r7, #4] + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 800a7e4: f3ef 8310 mrs r3, PRIMASK + 800a7e8: 60fb str r3, [r7, #12] + return(result); + 800a7ea: 68fb ldr r3, [r7, #12] + CRITICAL_SECTION_BEGIN(); + 800a7ec: 617b str r3, [r7, #20] + __ASM volatile ("cpsid i" : : : "memory"); + 800a7ee: b672 cpsid i +} + 800a7f0: bf00 nop + HAL_SUBGHZ_ReadRegisters( &hsubghz, address, buffer, size ); + 800a7f2: 88bb ldrh r3, [r7, #4] + 800a7f4: 88f9 ldrh r1, [r7, #6] + 800a7f6: 683a ldr r2, [r7, #0] + 800a7f8: 4806 ldr r0, [pc, #24] @ (800a814 ) + 800a7fa: f7fa f946 bl 8004a8a + 800a7fe: 697b ldr r3, [r7, #20] + 800a800: 613b str r3, [r7, #16] + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 800a802: 693b ldr r3, [r7, #16] + 800a804: f383 8810 msr PRIMASK, r3 +} + 800a808: bf00 nop + CRITICAL_SECTION_END(); +} + 800a80a: bf00 nop + 800a80c: 3718 adds r7, #24 + 800a80e: 46bd mov sp, r7 + 800a810: bd80 pop {r7, pc} + 800a812: bf00 nop + 800a814: 200000e0 .word 0x200000e0 + +0800a818 : + +void SUBGRF_WriteBuffer( uint8_t offset, uint8_t *buffer, uint8_t size ) +{ + 800a818: b580 push {r7, lr} + 800a81a: b086 sub sp, #24 + 800a81c: af00 add r7, sp, #0 + 800a81e: 4603 mov r3, r0 + 800a820: 6039 str r1, [r7, #0] + 800a822: 71fb strb r3, [r7, #7] + 800a824: 4613 mov r3, r2 + 800a826: 71bb strb r3, [r7, #6] + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 800a828: f3ef 8310 mrs r3, PRIMASK + 800a82c: 60fb str r3, [r7, #12] + return(result); + 800a82e: 68fb ldr r3, [r7, #12] + CRITICAL_SECTION_BEGIN(); + 800a830: 617b str r3, [r7, #20] + __ASM volatile ("cpsid i" : : : "memory"); + 800a832: b672 cpsid i +} + 800a834: bf00 nop + HAL_SUBGHZ_WriteBuffer( &hsubghz, offset, buffer, size ); + 800a836: 79bb ldrb r3, [r7, #6] + 800a838: b29b uxth r3, r3 + 800a83a: 79f9 ldrb r1, [r7, #7] + 800a83c: 683a ldr r2, [r7, #0] + 800a83e: 4806 ldr r0, [pc, #24] @ (800a858 ) + 800a840: f7fa fa37 bl 8004cb2 + 800a844: 697b ldr r3, [r7, #20] + 800a846: 613b str r3, [r7, #16] + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 800a848: 693b ldr r3, [r7, #16] + 800a84a: f383 8810 msr PRIMASK, r3 +} + 800a84e: bf00 nop + CRITICAL_SECTION_END(); +} + 800a850: bf00 nop + 800a852: 3718 adds r7, #24 + 800a854: 46bd mov sp, r7 + 800a856: bd80 pop {r7, pc} + 800a858: 200000e0 .word 0x200000e0 + +0800a85c : + +void SUBGRF_ReadBuffer( uint8_t offset, uint8_t *buffer, uint8_t size ) +{ + 800a85c: b580 push {r7, lr} + 800a85e: b086 sub sp, #24 + 800a860: af00 add r7, sp, #0 + 800a862: 4603 mov r3, r0 + 800a864: 6039 str r1, [r7, #0] + 800a866: 71fb strb r3, [r7, #7] + 800a868: 4613 mov r3, r2 + 800a86a: 71bb strb r3, [r7, #6] + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 800a86c: f3ef 8310 mrs r3, PRIMASK + 800a870: 60fb str r3, [r7, #12] + return(result); + 800a872: 68fb ldr r3, [r7, #12] + CRITICAL_SECTION_BEGIN(); + 800a874: 617b str r3, [r7, #20] + __ASM volatile ("cpsid i" : : : "memory"); + 800a876: b672 cpsid i +} + 800a878: bf00 nop + HAL_SUBGHZ_ReadBuffer( &hsubghz, offset, buffer, size ); + 800a87a: 79bb ldrb r3, [r7, #6] + 800a87c: b29b uxth r3, r3 + 800a87e: 79f9 ldrb r1, [r7, #7] + 800a880: 683a ldr r2, [r7, #0] + 800a882: 4806 ldr r0, [pc, #24] @ (800a89c ) + 800a884: f7fa fa68 bl 8004d58 + 800a888: 697b ldr r3, [r7, #20] + 800a88a: 613b str r3, [r7, #16] + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 800a88c: 693b ldr r3, [r7, #16] + 800a88e: f383 8810 msr PRIMASK, r3 +} + 800a892: bf00 nop + CRITICAL_SECTION_END(); +} + 800a894: bf00 nop + 800a896: 3718 adds r7, #24 + 800a898: 46bd mov sp, r7 + 800a89a: bd80 pop {r7, pc} + 800a89c: 200000e0 .word 0x200000e0 + +0800a8a0 : + +void SUBGRF_WriteCommand( SUBGHZ_RadioSetCmd_t Command, uint8_t *pBuffer, + uint16_t Size ) +{ + 800a8a0: b580 push {r7, lr} + 800a8a2: b086 sub sp, #24 + 800a8a4: af00 add r7, sp, #0 + 800a8a6: 4603 mov r3, r0 + 800a8a8: 6039 str r1, [r7, #0] + 800a8aa: 71fb strb r3, [r7, #7] + 800a8ac: 4613 mov r3, r2 + 800a8ae: 80bb strh r3, [r7, #4] + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 800a8b0: f3ef 8310 mrs r3, PRIMASK + 800a8b4: 60fb str r3, [r7, #12] + return(result); + 800a8b6: 68fb ldr r3, [r7, #12] + CRITICAL_SECTION_BEGIN(); + 800a8b8: 617b str r3, [r7, #20] + __ASM volatile ("cpsid i" : : : "memory"); + 800a8ba: b672 cpsid i +} + 800a8bc: bf00 nop + HAL_SUBGHZ_ExecSetCmd( &hsubghz, Command, pBuffer, Size ); + 800a8be: 88bb ldrh r3, [r7, #4] + 800a8c0: 79f9 ldrb r1, [r7, #7] + 800a8c2: 683a ldr r2, [r7, #0] + 800a8c4: 4806 ldr r0, [pc, #24] @ (800a8e0 ) + 800a8c6: f7fa f941 bl 8004b4c + 800a8ca: 697b ldr r3, [r7, #20] + 800a8cc: 613b str r3, [r7, #16] + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 800a8ce: 693b ldr r3, [r7, #16] + 800a8d0: f383 8810 msr PRIMASK, r3 +} + 800a8d4: bf00 nop + CRITICAL_SECTION_END(); +} + 800a8d6: bf00 nop + 800a8d8: 3718 adds r7, #24 + 800a8da: 46bd mov sp, r7 + 800a8dc: bd80 pop {r7, pc} + 800a8de: bf00 nop + 800a8e0: 200000e0 .word 0x200000e0 + +0800a8e4 : + +void SUBGRF_ReadCommand( SUBGHZ_RadioGetCmd_t Command, uint8_t *pBuffer, + uint16_t Size ) +{ + 800a8e4: b580 push {r7, lr} + 800a8e6: b086 sub sp, #24 + 800a8e8: af00 add r7, sp, #0 + 800a8ea: 4603 mov r3, r0 + 800a8ec: 6039 str r1, [r7, #0] + 800a8ee: 71fb strb r3, [r7, #7] + 800a8f0: 4613 mov r3, r2 + 800a8f2: 80bb strh r3, [r7, #4] + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 800a8f4: f3ef 8310 mrs r3, PRIMASK + 800a8f8: 60fb str r3, [r7, #12] + return(result); + 800a8fa: 68fb ldr r3, [r7, #12] + CRITICAL_SECTION_BEGIN(); + 800a8fc: 617b str r3, [r7, #20] + __ASM volatile ("cpsid i" : : : "memory"); + 800a8fe: b672 cpsid i +} + 800a900: bf00 nop + HAL_SUBGHZ_ExecGetCmd( &hsubghz, Command, pBuffer, Size ); + 800a902: 88bb ldrh r3, [r7, #4] + 800a904: 79f9 ldrb r1, [r7, #7] + 800a906: 683a ldr r2, [r7, #0] + 800a908: 4806 ldr r0, [pc, #24] @ (800a924 ) + 800a90a: f7fa f97e bl 8004c0a + 800a90e: 697b ldr r3, [r7, #20] + 800a910: 613b str r3, [r7, #16] + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 800a912: 693b ldr r3, [r7, #16] + 800a914: f383 8810 msr PRIMASK, r3 +} + 800a918: bf00 nop + CRITICAL_SECTION_END(); +} + 800a91a: bf00 nop + 800a91c: 3718 adds r7, #24 + 800a91e: 46bd mov sp, r7 + 800a920: bd80 pop {r7, pc} + 800a922: bf00 nop + 800a924: 200000e0 .word 0x200000e0 + +0800a928 : + +void SUBGRF_SetSwitch( uint8_t paSelect, RFState_t rxtx ) +{ + 800a928: b580 push {r7, lr} + 800a92a: b084 sub sp, #16 + 800a92c: af00 add r7, sp, #0 + 800a92e: 4603 mov r3, r0 + 800a930: 460a mov r2, r1 + 800a932: 71fb strb r3, [r7, #7] + 800a934: 4613 mov r3, r2 + 800a936: 71bb strb r3, [r7, #6] + RBI_Switch_TypeDef state = RBI_SWITCH_RX; + 800a938: 2301 movs r3, #1 + 800a93a: 73fb strb r3, [r7, #15] + + if (rxtx == RFSWITCH_TX) + 800a93c: 79bb ldrb r3, [r7, #6] + 800a93e: 2b01 cmp r3, #1 + 800a940: d10d bne.n 800a95e + { + if (paSelect == RFO_LP) + 800a942: 79fb ldrb r3, [r7, #7] + 800a944: 2b01 cmp r3, #1 + 800a946: d104 bne.n 800a952 + { + state = RBI_SWITCH_RFO_LP; + 800a948: 2302 movs r3, #2 + 800a94a: 73fb strb r3, [r7, #15] + Radio_SMPS_Set(SMPS_DRIVE_SETTING_MAX); + 800a94c: 2004 movs r0, #4 + 800a94e: f000 f8ef bl 800ab30 + } + if (paSelect == RFO_HP) + 800a952: 79fb ldrb r3, [r7, #7] + 800a954: 2b02 cmp r3, #2 + 800a956: d107 bne.n 800a968 + { + state = RBI_SWITCH_RFO_HP; + 800a958: 2303 movs r3, #3 + 800a95a: 73fb strb r3, [r7, #15] + 800a95c: e004 b.n 800a968 + } + } + else + { + if (rxtx == RFSWITCH_RX) + 800a95e: 79bb ldrb r3, [r7, #6] + 800a960: 2b00 cmp r3, #0 + 800a962: d101 bne.n 800a968 + { + state = RBI_SWITCH_RX; + 800a964: 2301 movs r3, #1 + 800a966: 73fb strb r3, [r7, #15] + } + } + RBI_ConfigRFSwitch(state); + 800a968: 7bfb ldrb r3, [r7, #15] + 800a96a: 4618 mov r0, r3 + 800a96c: f002 fb87 bl 800d07e +} + 800a970: bf00 nop + 800a972: 3710 adds r7, #16 + 800a974: 46bd mov sp, r7 + 800a976: bd80 pop {r7, pc} + +0800a978 : + +uint8_t SUBGRF_SetRfTxPower( int8_t power ) +{ + 800a978: b580 push {r7, lr} + 800a97a: b084 sub sp, #16 + 800a97c: af00 add r7, sp, #0 + 800a97e: 4603 mov r3, r0 + 800a980: 71fb strb r3, [r7, #7] + uint8_t paSelect= RFO_LP; + 800a982: 2301 movs r3, #1 + 800a984: 73fb strb r3, [r7, #15] + + int32_t TxConfig = RBI_GetTxConfig(); + 800a986: f002 fb88 bl 800d09a + 800a98a: 60b8 str r0, [r7, #8] + + switch (TxConfig) + 800a98c: 68bb ldr r3, [r7, #8] + 800a98e: 2b02 cmp r3, #2 + 800a990: d016 beq.n 800a9c0 + 800a992: 68bb ldr r3, [r7, #8] + 800a994: 2b02 cmp r3, #2 + 800a996: dc16 bgt.n 800a9c6 + 800a998: 68bb ldr r3, [r7, #8] + 800a99a: 2b00 cmp r3, #0 + 800a99c: d003 beq.n 800a9a6 + 800a99e: 68bb ldr r3, [r7, #8] + 800a9a0: 2b01 cmp r3, #1 + 800a9a2: d00a beq.n 800a9ba + { + paSelect = RFO_HP; + break; + } + default: + break; + 800a9a4: e00f b.n 800a9c6 + if (power > 15) + 800a9a6: f997 3007 ldrsb.w r3, [r7, #7] + 800a9aa: 2b0f cmp r3, #15 + 800a9ac: dd02 ble.n 800a9b4 + paSelect = RFO_HP; + 800a9ae: 2302 movs r3, #2 + 800a9b0: 73fb strb r3, [r7, #15] + break; + 800a9b2: e009 b.n 800a9c8 + paSelect = RFO_LP; + 800a9b4: 2301 movs r3, #1 + 800a9b6: 73fb strb r3, [r7, #15] + break; + 800a9b8: e006 b.n 800a9c8 + paSelect = RFO_LP; + 800a9ba: 2301 movs r3, #1 + 800a9bc: 73fb strb r3, [r7, #15] + break; + 800a9be: e003 b.n 800a9c8 + paSelect = RFO_HP; + 800a9c0: 2302 movs r3, #2 + 800a9c2: 73fb strb r3, [r7, #15] + break; + 800a9c4: e000 b.n 800a9c8 + break; + 800a9c6: bf00 nop + } + + SUBGRF_SetTxParams( paSelect, power, RADIO_RAMP_40_US ); + 800a9c8: f997 1007 ldrsb.w r1, [r7, #7] + 800a9cc: 7bfb ldrb r3, [r7, #15] + 800a9ce: 2202 movs r2, #2 + 800a9d0: 4618 mov r0, r3 + 800a9d2: f7ff fbb9 bl 800a148 + + return paSelect; + 800a9d6: 7bfb ldrb r3, [r7, #15] +} + 800a9d8: 4618 mov r0, r3 + 800a9da: 3710 adds r7, #16 + 800a9dc: 46bd mov sp, r7 + 800a9de: bd80 pop {r7, pc} + +0800a9e0 : + +uint32_t SUBGRF_GetRadioWakeUpTime( void ) +{ + 800a9e0: b480 push {r7} + 800a9e2: af00 add r7, sp, #0 + return RF_WAKEUP_TIME; + 800a9e4: 2301 movs r3, #1 +} + 800a9e6: 4618 mov r0, r3 + 800a9e8: 46bd mov sp, r7 + 800a9ea: bc80 pop {r7} + 800a9ec: 4770 bx lr + ... + +0800a9f0 : + +/* HAL_SUBGHz Callbacks definitions */ +void HAL_SUBGHZ_TxCpltCallback(SUBGHZ_HandleTypeDef *hsubghz) +{ + 800a9f0: b580 push {r7, lr} + 800a9f2: b082 sub sp, #8 + 800a9f4: af00 add r7, sp, #0 + 800a9f6: 6078 str r0, [r7, #4] + RadioOnDioIrqCb( IRQ_TX_DONE ); + 800a9f8: 4b03 ldr r3, [pc, #12] @ (800aa08 ) + 800a9fa: 681b ldr r3, [r3, #0] + 800a9fc: 2001 movs r0, #1 + 800a9fe: 4798 blx r3 +} + 800aa00: bf00 nop + 800aa02: 3708 adds r7, #8 + 800aa04: 46bd mov sp, r7 + 800aa06: bd80 pop {r7, pc} + 800aa08: 20000398 .word 0x20000398 + +0800aa0c : + +void HAL_SUBGHZ_RxCpltCallback(SUBGHZ_HandleTypeDef *hsubghz) +{ + 800aa0c: b580 push {r7, lr} + 800aa0e: b082 sub sp, #8 + 800aa10: af00 add r7, sp, #0 + 800aa12: 6078 str r0, [r7, #4] + RadioOnDioIrqCb( IRQ_RX_DONE ); + 800aa14: 4b03 ldr r3, [pc, #12] @ (800aa24 ) + 800aa16: 681b ldr r3, [r3, #0] + 800aa18: 2002 movs r0, #2 + 800aa1a: 4798 blx r3 +} + 800aa1c: bf00 nop + 800aa1e: 3708 adds r7, #8 + 800aa20: 46bd mov sp, r7 + 800aa22: bd80 pop {r7, pc} + 800aa24: 20000398 .word 0x20000398 + +0800aa28 : + +void HAL_SUBGHZ_CRCErrorCallback (SUBGHZ_HandleTypeDef *hsubghz) +{ + 800aa28: b580 push {r7, lr} + 800aa2a: b082 sub sp, #8 + 800aa2c: af00 add r7, sp, #0 + 800aa2e: 6078 str r0, [r7, #4] + RadioOnDioIrqCb( IRQ_CRC_ERROR); + 800aa30: 4b03 ldr r3, [pc, #12] @ (800aa40 ) + 800aa32: 681b ldr r3, [r3, #0] + 800aa34: 2040 movs r0, #64 @ 0x40 + 800aa36: 4798 blx r3 +} + 800aa38: bf00 nop + 800aa3a: 3708 adds r7, #8 + 800aa3c: 46bd mov sp, r7 + 800aa3e: bd80 pop {r7, pc} + 800aa40: 20000398 .word 0x20000398 + +0800aa44 : + +void HAL_SUBGHZ_CADStatusCallback(SUBGHZ_HandleTypeDef *hsubghz, HAL_SUBGHZ_CadStatusTypeDef cadstatus) +{ + 800aa44: b580 push {r7, lr} + 800aa46: b082 sub sp, #8 + 800aa48: af00 add r7, sp, #0 + 800aa4a: 6078 str r0, [r7, #4] + 800aa4c: 460b mov r3, r1 + 800aa4e: 70fb strb r3, [r7, #3] + switch (cadstatus) + 800aa50: 78fb ldrb r3, [r7, #3] + 800aa52: 2b00 cmp r3, #0 + 800aa54: d002 beq.n 800aa5c + 800aa56: 2b01 cmp r3, #1 + 800aa58: d005 beq.n 800aa66 + break; + case HAL_SUBGHZ_CAD_DETECTED: + RadioOnDioIrqCb( IRQ_CAD_DETECTED); + break; + default: + break; + 800aa5a: e00a b.n 800aa72 + RadioOnDioIrqCb( IRQ_CAD_CLEAR); + 800aa5c: 4b07 ldr r3, [pc, #28] @ (800aa7c ) + 800aa5e: 681b ldr r3, [r3, #0] + 800aa60: 2080 movs r0, #128 @ 0x80 + 800aa62: 4798 blx r3 + break; + 800aa64: e005 b.n 800aa72 + RadioOnDioIrqCb( IRQ_CAD_DETECTED); + 800aa66: 4b05 ldr r3, [pc, #20] @ (800aa7c ) + 800aa68: 681b ldr r3, [r3, #0] + 800aa6a: f44f 7080 mov.w r0, #256 @ 0x100 + 800aa6e: 4798 blx r3 + break; + 800aa70: bf00 nop + } +} + 800aa72: bf00 nop + 800aa74: 3708 adds r7, #8 + 800aa76: 46bd mov sp, r7 + 800aa78: bd80 pop {r7, pc} + 800aa7a: bf00 nop + 800aa7c: 20000398 .word 0x20000398 + +0800aa80 : + +void HAL_SUBGHZ_RxTxTimeoutCallback(SUBGHZ_HandleTypeDef *hsubghz) +{ + 800aa80: b580 push {r7, lr} + 800aa82: b082 sub sp, #8 + 800aa84: af00 add r7, sp, #0 + 800aa86: 6078 str r0, [r7, #4] + RadioOnDioIrqCb( IRQ_RX_TX_TIMEOUT ); + 800aa88: 4b04 ldr r3, [pc, #16] @ (800aa9c ) + 800aa8a: 681b ldr r3, [r3, #0] + 800aa8c: f44f 7000 mov.w r0, #512 @ 0x200 + 800aa90: 4798 blx r3 +} + 800aa92: bf00 nop + 800aa94: 3708 adds r7, #8 + 800aa96: 46bd mov sp, r7 + 800aa98: bd80 pop {r7, pc} + 800aa9a: bf00 nop + 800aa9c: 20000398 .word 0x20000398 + +0800aaa0 : + +void HAL_SUBGHZ_HeaderErrorCallback(SUBGHZ_HandleTypeDef *hsubghz) +{ + 800aaa0: b580 push {r7, lr} + 800aaa2: b082 sub sp, #8 + 800aaa4: af00 add r7, sp, #0 + 800aaa6: 6078 str r0, [r7, #4] + RadioOnDioIrqCb( IRQ_HEADER_ERROR ); + 800aaa8: 4b03 ldr r3, [pc, #12] @ (800aab8 ) + 800aaaa: 681b ldr r3, [r3, #0] + 800aaac: 2020 movs r0, #32 + 800aaae: 4798 blx r3 +} + 800aab0: bf00 nop + 800aab2: 3708 adds r7, #8 + 800aab4: 46bd mov sp, r7 + 800aab6: bd80 pop {r7, pc} + 800aab8: 20000398 .word 0x20000398 + +0800aabc : + +void HAL_SUBGHZ_PreambleDetectedCallback(SUBGHZ_HandleTypeDef *hsubghz) +{ + 800aabc: b580 push {r7, lr} + 800aabe: b082 sub sp, #8 + 800aac0: af00 add r7, sp, #0 + 800aac2: 6078 str r0, [r7, #4] + RadioOnDioIrqCb( IRQ_PREAMBLE_DETECTED ); + 800aac4: 4b03 ldr r3, [pc, #12] @ (800aad4 ) + 800aac6: 681b ldr r3, [r3, #0] + 800aac8: 2004 movs r0, #4 + 800aaca: 4798 blx r3 +} + 800aacc: bf00 nop + 800aace: 3708 adds r7, #8 + 800aad0: 46bd mov sp, r7 + 800aad2: bd80 pop {r7, pc} + 800aad4: 20000398 .word 0x20000398 + +0800aad8 : + +void HAL_SUBGHZ_SyncWordValidCallback(SUBGHZ_HandleTypeDef *hsubghz) +{ + 800aad8: b580 push {r7, lr} + 800aada: b082 sub sp, #8 + 800aadc: af00 add r7, sp, #0 + 800aade: 6078 str r0, [r7, #4] + RadioOnDioIrqCb( IRQ_SYNCWORD_VALID ); + 800aae0: 4b03 ldr r3, [pc, #12] @ (800aaf0 ) + 800aae2: 681b ldr r3, [r3, #0] + 800aae4: 2008 movs r0, #8 + 800aae6: 4798 blx r3 +} + 800aae8: bf00 nop + 800aaea: 3708 adds r7, #8 + 800aaec: 46bd mov sp, r7 + 800aaee: bd80 pop {r7, pc} + 800aaf0: 20000398 .word 0x20000398 + +0800aaf4 : + +void HAL_SUBGHZ_HeaderValidCallback(SUBGHZ_HandleTypeDef *hsubghz) +{ + 800aaf4: b580 push {r7, lr} + 800aaf6: b082 sub sp, #8 + 800aaf8: af00 add r7, sp, #0 + 800aafa: 6078 str r0, [r7, #4] + RadioOnDioIrqCb( IRQ_HEADER_VALID ); + 800aafc: 4b03 ldr r3, [pc, #12] @ (800ab0c ) + 800aafe: 681b ldr r3, [r3, #0] + 800ab00: 2010 movs r0, #16 + 800ab02: 4798 blx r3 +} + 800ab04: bf00 nop + 800ab06: 3708 adds r7, #8 + 800ab08: 46bd mov sp, r7 + 800ab0a: bd80 pop {r7, pc} + 800ab0c: 20000398 .word 0x20000398 + +0800ab10 : + +void HAL_SUBGHZ_LrFhssHopCallback(SUBGHZ_HandleTypeDef *hsubghz) +{ + 800ab10: b580 push {r7, lr} + 800ab12: b082 sub sp, #8 + 800ab14: af00 add r7, sp, #0 + 800ab16: 6078 str r0, [r7, #4] + RadioOnDioIrqCb( IRQ_LR_FHSS_HOP ); + 800ab18: 4b04 ldr r3, [pc, #16] @ (800ab2c ) + 800ab1a: 681b ldr r3, [r3, #0] + 800ab1c: f44f 4080 mov.w r0, #16384 @ 0x4000 + 800ab20: 4798 blx r3 +} + 800ab22: bf00 nop + 800ab24: 3708 adds r7, #8 + 800ab26: 46bd mov sp, r7 + 800ab28: bd80 pop {r7, pc} + 800ab2a: bf00 nop + 800ab2c: 20000398 .word 0x20000398 + +0800ab30 : + +static void Radio_SMPS_Set(uint8_t level) +{ + 800ab30: b580 push {r7, lr} + 800ab32: b084 sub sp, #16 + 800ab34: af00 add r7, sp, #0 + 800ab36: 4603 mov r3, r0 + 800ab38: 71fb strb r3, [r7, #7] + if ( 1U == RBI_IsDCDC() ) + 800ab3a: f002 fabc bl 800d0b6 + 800ab3e: 4603 mov r3, r0 + 800ab40: 2b01 cmp r3, #1 + 800ab42: d112 bne.n 800ab6a + { + uint8_t modReg; + modReg= SUBGRF_ReadRegister(SUBGHZ_SMPSC2R); + 800ab44: f640 1023 movw r0, #2339 @ 0x923 + 800ab48: f7ff fe02 bl 800a750 + 800ab4c: 4603 mov r3, r0 + 800ab4e: 73fb strb r3, [r7, #15] + modReg&= (~SMPS_DRV_MASK); + 800ab50: 7bfb ldrb r3, [r7, #15] + 800ab52: f023 0306 bic.w r3, r3, #6 + 800ab56: 73fb strb r3, [r7, #15] + SUBGRF_WriteRegister(SUBGHZ_SMPSC2R, modReg | level); + 800ab58: 7bfa ldrb r2, [r7, #15] + 800ab5a: 79fb ldrb r3, [r7, #7] + 800ab5c: 4313 orrs r3, r2 + 800ab5e: b2db uxtb r3, r3 + 800ab60: 4619 mov r1, r3 + 800ab62: f640 1023 movw r0, #2339 @ 0x923 + 800ab66: f7ff fdd1 bl 800a70c + } +} + 800ab6a: bf00 nop + 800ab6c: 3710 adds r7, #16 + 800ab6e: 46bd mov sp, r7 + 800ab70: bd80 pop {r7, pc} + ... + +0800ab74 : + +uint8_t SUBGRF_GetFskBandwidthRegValue( uint32_t bandwidth ) +{ + 800ab74: b480 push {r7} + 800ab76: b085 sub sp, #20 + 800ab78: af00 add r7, sp, #0 + 800ab7a: 6078 str r0, [r7, #4] + uint8_t i; + + if( bandwidth == 0 ) + 800ab7c: 687b ldr r3, [r7, #4] + 800ab7e: 2b00 cmp r3, #0 + 800ab80: d101 bne.n 800ab86 + { + return( 0x1F ); + 800ab82: 231f movs r3, #31 + 800ab84: e017 b.n 800abb6 + } + + for( i = 0; i < ( sizeof( FskBandwidths ) / sizeof( FskBandwidth_t ) ); i++ ) + 800ab86: 2300 movs r3, #0 + 800ab88: 73fb strb r3, [r7, #15] + 800ab8a: e00f b.n 800abac + { + if ( bandwidth < FskBandwidths[i].bandwidth ) + 800ab8c: 7bfb ldrb r3, [r7, #15] + 800ab8e: 4a0c ldr r2, [pc, #48] @ (800abc0 ) + 800ab90: f852 3033 ldr.w r3, [r2, r3, lsl #3] + 800ab94: 687a ldr r2, [r7, #4] + 800ab96: 429a cmp r2, r3 + 800ab98: d205 bcs.n 800aba6 + { + return FskBandwidths[i].RegValue; + 800ab9a: 7bfb ldrb r3, [r7, #15] + 800ab9c: 4a08 ldr r2, [pc, #32] @ (800abc0 ) + 800ab9e: 00db lsls r3, r3, #3 + 800aba0: 4413 add r3, r2 + 800aba2: 791b ldrb r3, [r3, #4] + 800aba4: e007 b.n 800abb6 + for( i = 0; i < ( sizeof( FskBandwidths ) / sizeof( FskBandwidth_t ) ); i++ ) + 800aba6: 7bfb ldrb r3, [r7, #15] + 800aba8: 3301 adds r3, #1 + 800abaa: 73fb strb r3, [r7, #15] + 800abac: 7bfb ldrb r3, [r7, #15] + 800abae: 2b15 cmp r3, #21 + 800abb0: d9ec bls.n 800ab8c + } + } + // ERROR: Value not found + while( 1 ); + 800abb2: bf00 nop + 800abb4: e7fd b.n 800abb2 +} + 800abb6: 4618 mov r0, r3 + 800abb8: 3714 adds r7, #20 + 800abba: 46bd mov sp, r7 + 800abbc: bc80 pop {r7} + 800abbe: 4770 bx lr + 800abc0: 0800fc0c .word 0x0800fc0c + +0800abc4 : +void SUBGRF_GetCFO( uint32_t bitRate, int32_t *cfo) +{ + 800abc4: b580 push {r7, lr} + 800abc6: b08a sub sp, #40 @ 0x28 + 800abc8: af00 add r7, sp, #0 + 800abca: 6078 str r0, [r7, #4] + 800abcc: 6039 str r1, [r7, #0] + uint8_t BwMant[] = {4, 8, 10, 12}; + 800abce: 4b35 ldr r3, [pc, #212] @ (800aca4 ) + 800abd0: 60fb str r3, [r7, #12] + /* read demod bandwidth: mant bit4:3, exp bits 2:0 */ + uint8_t reg = (SUBGRF_ReadRegister( SUBGHZ_BWSELR )); + 800abd2: f640 0007 movw r0, #2055 @ 0x807 + 800abd6: f7ff fdbb bl 800a750 + 800abda: 4603 mov r3, r0 + 800abdc: 77fb strb r3, [r7, #31] + uint8_t bandwidth_mant = BwMant[( reg >> 3 ) & 0x3]; + 800abde: 7ffb ldrb r3, [r7, #31] + 800abe0: 08db lsrs r3, r3, #3 + 800abe2: b2db uxtb r3, r3 + 800abe4: f003 0303 and.w r3, r3, #3 + 800abe8: 3328 adds r3, #40 @ 0x28 + 800abea: 443b add r3, r7 + 800abec: f813 3c1c ldrb.w r3, [r3, #-28] + 800abf0: 77bb strb r3, [r7, #30] + uint8_t bandwidth_exp = reg & 0x7; + 800abf2: 7ffb ldrb r3, [r7, #31] + 800abf4: f003 0307 and.w r3, r3, #7 + 800abf8: 777b strb r3, [r7, #29] + uint32_t cf_fs = XTAL_FREQ / ( bandwidth_mant * ( 1 << ( bandwidth_exp + 1 ))); + 800abfa: 7fba ldrb r2, [r7, #30] + 800abfc: 7f7b ldrb r3, [r7, #29] + 800abfe: 3301 adds r3, #1 + 800ac00: fa02 f303 lsl.w r3, r2, r3 + 800ac04: 461a mov r2, r3 + 800ac06: 4b28 ldr r3, [pc, #160] @ (800aca8 ) + 800ac08: fbb3 f3f2 udiv r3, r3, r2 + 800ac0c: 61bb str r3, [r7, #24] + uint32_t cf_osr = cf_fs / bitRate; + 800ac0e: 69ba ldr r2, [r7, #24] + 800ac10: 687b ldr r3, [r7, #4] + 800ac12: fbb2 f3f3 udiv r3, r2, r3 + 800ac16: 617b str r3, [r7, #20] + uint8_t interp = 1; + 800ac18: 2301 movs r3, #1 + 800ac1a: f887 3027 strb.w r3, [r7, #39] @ 0x27 + /* calculate demod interpolation factor */ + if (cf_osr * interp < 8) + 800ac1e: f897 3027 ldrb.w r3, [r7, #39] @ 0x27 + 800ac22: 697a ldr r2, [r7, #20] + 800ac24: fb02 f303 mul.w r3, r2, r3 + 800ac28: 2b07 cmp r3, #7 + 800ac2a: d802 bhi.n 800ac32 + { + interp = 2; + 800ac2c: 2302 movs r3, #2 + 800ac2e: f887 3027 strb.w r3, [r7, #39] @ 0x27 + } + if (cf_osr * interp < 4) + 800ac32: f897 3027 ldrb.w r3, [r7, #39] @ 0x27 + 800ac36: 697a ldr r2, [r7, #20] + 800ac38: fb02 f303 mul.w r3, r2, r3 + 800ac3c: 2b03 cmp r3, #3 + 800ac3e: d802 bhi.n 800ac46 + { + interp = 4; + 800ac40: 2304 movs r3, #4 + 800ac42: f887 3027 strb.w r3, [r7, #39] @ 0x27 + } + /* calculate demod sampling frequency */ + uint32_t fs = cf_fs* interp; + 800ac46: f897 2027 ldrb.w r2, [r7, #39] @ 0x27 + 800ac4a: 69bb ldr r3, [r7, #24] + 800ac4c: fb02 f303 mul.w r3, r2, r3 + 800ac50: 613b str r3, [r7, #16] + /* get the cfo registers */ + int32_t cfo_bin = ( SUBGRF_ReadRegister( SUBGHZ_GCFORH ) & 0xF ) << 8; + 800ac52: f44f 60d6 mov.w r0, #1712 @ 0x6b0 + 800ac56: f7ff fd7b bl 800a750 + 800ac5a: 4603 mov r3, r0 + 800ac5c: 021b lsls r3, r3, #8 + 800ac5e: f403 6370 and.w r3, r3, #3840 @ 0xf00 + 800ac62: 623b str r3, [r7, #32] + cfo_bin |= SUBGRF_ReadRegister( SUBGHZ_GCFORL ); + 800ac64: f240 60b1 movw r0, #1713 @ 0x6b1 + 800ac68: f7ff fd72 bl 800a750 + 800ac6c: 4603 mov r3, r0 + 800ac6e: 461a mov r2, r3 + 800ac70: 6a3b ldr r3, [r7, #32] + 800ac72: 4313 orrs r3, r2 + 800ac74: 623b str r3, [r7, #32] + /* negate if 12 bits sign bit is 1 */ + if (( cfo_bin & 0x800 ) == 0x800 ) + 800ac76: 6a3b ldr r3, [r7, #32] + 800ac78: f403 6300 and.w r3, r3, #2048 @ 0x800 + 800ac7c: 2b00 cmp r3, #0 + 800ac7e: d005 beq.n 800ac8c + { + cfo_bin |= 0xFFFFF000; + 800ac80: 6a3b ldr r3, [r7, #32] + 800ac82: ea6f 5303 mvn.w r3, r3, lsl #20 + 800ac86: ea6f 5313 mvn.w r3, r3, lsr #20 + 800ac8a: 623b str r3, [r7, #32] + } + /* calculate cfo in Hz */ + /* shift by 5 first to not saturate, cfo_bin on 12bits */ + *cfo = ((int32_t)( cfo_bin * ( fs >> 5 ))) >> ( 12 - 5 ); + 800ac8c: 693b ldr r3, [r7, #16] + 800ac8e: 095b lsrs r3, r3, #5 + 800ac90: 6a3a ldr r2, [r7, #32] + 800ac92: fb02 f303 mul.w r3, r2, r3 + 800ac96: 11da asrs r2, r3, #7 + 800ac98: 683b ldr r3, [r7, #0] + 800ac9a: 601a str r2, [r3, #0] +} + 800ac9c: bf00 nop + 800ac9e: 3728 adds r7, #40 @ 0x28 + 800aca0: 46bd mov sp, r7 + 800aca2: bd80 pop {r7, pc} + 800aca4: 0c0a0804 .word 0x0c0a0804 + 800aca8: 01e84800 .word 0x01e84800 + +0800acac : +{ + 800acac: b480 push {r7} + 800acae: af00 add r7, sp, #0 + return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos); + 800acb0: 4b03 ldr r3, [pc, #12] @ (800acc0 ) + 800acb2: 681b ldr r3, [r3, #0] + 800acb4: 0c1b lsrs r3, r3, #16 + 800acb6: b29b uxth r3, r3 +} + 800acb8: 4618 mov r0, r3 + 800acba: 46bd mov sp, r7 + 800acbc: bc80 pop {r7} + 800acbe: 4770 bx lr + 800acc0: e0042000 .word 0xe0042000 + +0800acc4 : +{ + 800acc4: b480 push {r7} + 800acc6: b083 sub sp, #12 + 800acc8: af00 add r7, sp, #0 + 800acca: 6078 str r0, [r7, #4] + 800accc: 6039 str r1, [r7, #0] + WRITE_REG(GPIOx->BSRR, PinMask); + 800acce: 687b ldr r3, [r7, #4] + 800acd0: 683a ldr r2, [r7, #0] + 800acd2: 619a str r2, [r3, #24] +} + 800acd4: bf00 nop + 800acd6: 370c adds r7, #12 + 800acd8: 46bd mov sp, r7 + 800acda: bc80 pop {r7} + 800acdc: 4770 bx lr + +0800acde : +{ + 800acde: b480 push {r7} + 800ace0: b083 sub sp, #12 + 800ace2: af00 add r7, sp, #0 + 800ace4: 6078 str r0, [r7, #4] + 800ace6: 6039 str r1, [r7, #0] + WRITE_REG(GPIOx->BRR, PinMask); + 800ace8: 687b ldr r3, [r7, #4] + 800acea: 683a ldr r2, [r7, #0] + 800acec: 629a str r2, [r3, #40] @ 0x28 +} + 800acee: bf00 nop + 800acf0: 370c adds r7, #12 + 800acf2: 46bd mov sp, r7 + 800acf4: bc80 pop {r7} + 800acf6: 4770 bx lr + +0800acf8 : +#endif /* RFW_ENABLE == 1 */ + +/* Exported functions --------------------------------------------------------*/ +int32_t RFW_TransmitLongPacket( uint16_t payload_size, uint32_t timeout, + void ( *TxLongPacketGetNextChunkCb )( uint8_t **buffer, uint8_t buffer_size ) ) +{ + 800acf8: b580 push {r7, lr} + 800acfa: b08e sub sp, #56 @ 0x38 + 800acfc: af02 add r7, sp, #8 + 800acfe: 4603 mov r3, r0 + 800ad00: 60b9 str r1, [r7, #8] + 800ad02: 607a str r2, [r7, #4] + 800ad04: 81fb strh r3, [r7, #14] + int32_t status = 0; + 800ad06: 2300 movs r3, #0 + 800ad08: 62fb str r3, [r7, #44] @ 0x2c +#if (RFW_LONGPACKET_ENABLE == 1 ) + uint32_t total_size = payload_size + RFWPacket.Init.PayloadLengthFieldSize + RFWPacket.Init.CrcFieldSize; + 800ad0a: 89fb ldrh r3, [r7, #14] + 800ad0c: 4ab0 ldr r2, [pc, #704] @ (800afd0 ) + 800ad0e: 7852 ldrb r2, [r2, #1] + 800ad10: 4413 add r3, r2 + 800ad12: 4aaf ldr r2, [pc, #700] @ (800afd0 ) + 800ad14: 78d2 ldrb r2, [r2, #3] + 800ad16: 4413 add r3, r2 + 800ad18: 627b str r3, [r7, #36] @ 0x24 + + RFW_MW_LOG( TS_ON, VLEVEL_M, "RevID=%04X\r\n", LL_DBGMCU_GetRevisionID() ); + 800ad1a: f7ff ffc7 bl 800acac + 800ad1e: 4603 mov r3, r0 + 800ad20: 9300 str r3, [sp, #0] + 800ad22: 4bac ldr r3, [pc, #688] @ (800afd4 ) + 800ad24: 2201 movs r2, #1 + 800ad26: 2100 movs r1, #0 + 800ad28: 2002 movs r0, #2 + 800ad2a: f003 f97d bl 800e028 + + if( ( TxLongPacketGetNextChunkCb == NULL ) || + 800ad2e: 687b ldr r3, [r7, #4] + 800ad30: 2b00 cmp r3, #0 + 800ad32: d012 beq.n 800ad5a + ( payload_size > ( 1 << ( 8 * RFWPacket.Init.PayloadLengthFieldSize ) ) - 1 ) || /*check that size fits inside the packetLengthField*/ + 800ad34: 4ba6 ldr r3, [pc, #664] @ (800afd0 ) + 800ad36: 785b ldrb r3, [r3, #1] + 800ad38: 00db lsls r3, r3, #3 + 800ad3a: 2201 movs r2, #1 + 800ad3c: 409a lsls r2, r3 + 800ad3e: 89fb ldrh r3, [r7, #14] + if( ( TxLongPacketGetNextChunkCb == NULL ) || + 800ad40: 429a cmp r2, r3 + 800ad42: dd0a ble.n 800ad5a + ( RFWPacket.Init.Enable == 0 ) || /* Can only be used when after RadioSetTxGenericConfig*/ + 800ad44: 4ba2 ldr r3, [pc, #648] @ (800afd0 ) + 800ad46: 781b ldrb r3, [r3, #0] + ( payload_size > ( 1 << ( 8 * RFWPacket.Init.PayloadLengthFieldSize ) ) - 1 ) || /*check that size fits inside the packetLengthField*/ + 800ad48: 2b00 cmp r3, #0 + 800ad4a: d006 beq.n 800ad5a + ( LL_DBGMCU_GetRevisionID() < 0x1003 ) ) /* Only available from stm32wl revision Y*/ + 800ad4c: f7ff ffae bl 800acac + 800ad50: 4603 mov r3, r0 + ( RFWPacket.Init.Enable == 0 ) || /* Can only be used when after RadioSetTxGenericConfig*/ + 800ad52: f241 0202 movw r2, #4098 @ 0x1002 + 800ad56: 4293 cmp r3, r2 + 800ad58: d803 bhi.n 800ad62 + { + status = -1; + 800ad5a: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff + 800ad5e: 62fb str r3, [r7, #44] @ 0x2c + 800ad60: e130 b.n 800afc4 + } + else + { + /*chunk buffer pointer fed by the application*/ + uint8_t *app_chunk_buffer_ptr = NULL; + 800ad62: 2300 movs r3, #0 + 800ad64: 61bb str r3, [r7, #24] + uint8_t chunk_size; + uint8_t crc_size; + /*timeout for next chunk*/ + uint32_t chunk_timeout; + /*Records call back*/ + RFWPacket.TxLongPacketGetNextChunkCb = TxLongPacketGetNextChunkCb; + 800ad66: 4a9a ldr r2, [pc, #616] @ (800afd0 ) + 800ad68: 687b ldr r3, [r7, #4] + 800ad6a: 6413 str r3, [r2, #64] @ 0x40 + + /* Radio IRQ is set to DIO1 by default */ + SUBGRF_SetDioIrqParams( IRQ_TX_DONE | IRQ_RX_TX_TIMEOUT, + 800ad6c: 2300 movs r3, #0 + 800ad6e: 2200 movs r2, #0 + 800ad70: f240 2101 movw r1, #513 @ 0x201 + 800ad74: f240 2001 movw r0, #513 @ 0x201 + 800ad78: f7ff f91e bl 8009fb8 + IRQ_TX_DONE | IRQ_RX_TX_TIMEOUT, + IRQ_RADIO_NONE, + IRQ_RADIO_NONE ); + + /* Set DBG pin */ + DBG_GPIO_RADIO_TX( SET ); + 800ad7c: f44f 5100 mov.w r1, #8192 @ 0x2000 + 800ad80: 4895 ldr r0, [pc, #596] @ (800afd8 ) + 800ad82: f7ff ff9f bl 800acc4 + /* Set RF switch */ + SUBGRF_SetSwitch( RFWPacket.AntSwitchPaSelect, RFSWITCH_TX ); + 800ad86: 4b92 ldr r3, [pc, #584] @ (800afd0 ) + 800ad88: f893 3044 ldrb.w r3, [r3, #68] @ 0x44 + 800ad8c: 2101 movs r1, #1 + 800ad8e: 4618 mov r0, r3 + 800ad90: f7ff fdca bl 800a928 + + switch( RFWPacket.Init.Modem ) + 800ad94: 4b8e ldr r3, [pc, #568] @ (800afd0 ) + 800ad96: 7b9b ldrb r3, [r3, #14] + 800ad98: 2b04 cmp r3, #4 + 800ad9a: f200 8110 bhi.w 800afbe + 800ad9e: a201 add r2, pc, #4 @ (adr r2, 800ada4 ) + 800ada0: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 800ada4: 0800adb9 .word 0x0800adb9 + 800ada8: 0800afa7 .word 0x0800afa7 + 800adac: 0800adb9 .word 0x0800adb9 + 800adb0: 0800afaf .word 0x0800afaf + 800adb4: 0800afb7 .word 0x0800afb7 + { + case MODEM_FSK: + case MODEM_MSK: + { + if( RFWPacket.Init.Enable == 1 ) + 800adb8: 4b85 ldr r3, [pc, #532] @ (800afd0 ) + 800adba: 781b ldrb r3, [r3, #0] + 800adbc: 2b01 cmp r3, #1 + 800adbe: f040 80ee bne.w 800af9e + { + /*crc will be calculated on the fly along with packet chunk transmission*/ + uint8_t crc_result[2]; + /*init radio buffer offset*/ + RFWPacket.RadioBufferOffset = 0; + 800adc2: 4b83 ldr r3, [pc, #524] @ (800afd0 ) + 800adc4: 2200 movs r2, #0 + 800adc6: f883 2036 strb.w r2, [r3, #54] @ 0x36 + /*long packet mode enable*/ + RFWPacket.LongPacketModeEnable = 1; + 800adca: 4b81 ldr r3, [pc, #516] @ (800afd0 ) + 800adcc: 2201 movs r2, #1 + 800adce: 769a strb r2, [r3, #26] + /*Remaining bytes to transmit*/ + RFWPacket.LongPacketRemainingBytes = total_size; + 800add0: 6a7b ldr r3, [r7, #36] @ 0x24 + 800add2: b29a uxth r2, r3 + 800add4: 4b7e ldr r3, [pc, #504] @ (800afd0 ) + 800add6: 869a strh r2, [r3, #52] @ 0x34 + /*Records total payload bytes to transmit*/ + RFWPacket.PayloadLength = total_size; + 800add8: 6a7b ldr r3, [r7, #36] @ 0x24 + 800adda: b29a uxth r2, r3 + 800addc: 4b7c ldr r3, [pc, #496] @ (800afd0 ) + 800adde: 831a strh r2, [r3, #24] + if( total_size > RADIO_BUF_SIZE ) + 800ade0: 6a7b ldr r3, [r7, #36] @ 0x24 + 800ade2: 2bff cmp r3, #255 @ 0xff + 800ade4: d919 bls.n 800ae1a + { + /*cut in chunk*/ + if( total_size < RADIO_BUF_SIZE + RFWPacket.Init.CrcFieldSize ) + 800ade6: 4b7a ldr r3, [pc, #488] @ (800afd0 ) + 800ade8: 78db ldrb r3, [r3, #3] + 800adea: 33ff adds r3, #255 @ 0xff + 800adec: 461a mov r2, r3 + 800adee: 6a7b ldr r3, [r7, #36] @ 0x24 + 800adf0: 4293 cmp r3, r2 + 800adf2: d209 bcs.n 800ae08 + { + /*reduce chunk so that crc is treated in the next chunk*/ + chunk_size = RADIO_BUF_SIZE - RFWPacket.Init.PayloadLengthFieldSize - RFWPacket.Init.CrcFieldSize; + 800adf4: 4b76 ldr r3, [pc, #472] @ (800afd0 ) + 800adf6: 785b ldrb r3, [r3, #1] + 800adf8: 43db mvns r3, r3 + 800adfa: b2da uxtb r2, r3 + 800adfc: 4b74 ldr r3, [pc, #464] @ (800afd0 ) + 800adfe: 78db ldrb r3, [r3, #3] + 800ae00: 1ad3 subs r3, r2, r3 + 800ae02: f887 302b strb.w r3, [r7, #43] @ 0x2b + 800ae06: e004 b.n 800ae12 + } + else + { + chunk_size = RADIO_BUF_SIZE - RFWPacket.Init.PayloadLengthFieldSize; + 800ae08: 4b71 ldr r3, [pc, #452] @ (800afd0 ) + 800ae0a: 785b ldrb r3, [r3, #1] + 800ae0c: 43db mvns r3, r3 + 800ae0e: f887 302b strb.w r3, [r7, #43] @ 0x2b + } + /*Set crc size for the crc calculation: no crc here because it is not the end of the packet*/ + crc_size = 0; + 800ae12: 2300 movs r3, #0 + 800ae14: f887 302a strb.w r3, [r7, #42] @ 0x2a + 800ae18: e006 b.n 800ae28 + } + else + { + chunk_size = payload_size; + 800ae1a: 89fb ldrh r3, [r7, #14] + 800ae1c: f887 302b strb.w r3, [r7, #43] @ 0x2b + /*Set crc size for the crc calculation*/ + crc_size = RFWPacket.Init.CrcFieldSize; + 800ae20: 4b6b ldr r3, [pc, #428] @ (800afd0 ) + 800ae22: 78db ldrb r3, [r3, #3] + 800ae24: f887 302a strb.w r3, [r7, #42] @ 0x2a + } + /* Prepend payload size before Payload*/ + if( RFWPacket.Init.PayloadLengthFieldSize == 1 ) + 800ae28: 4b69 ldr r3, [pc, #420] @ (800afd0 ) + 800ae2a: 785b ldrb r3, [r3, #1] + 800ae2c: 2b01 cmp r3, #1 + 800ae2e: d104 bne.n 800ae3a + { + ChunkBuffer[0] = payload_size; + 800ae30: 89fb ldrh r3, [r7, #14] + 800ae32: b2da uxtb r2, r3 + 800ae34: 4b69 ldr r3, [pc, #420] @ (800afdc ) + 800ae36: 701a strb r2, [r3, #0] + 800ae38: e009 b.n 800ae4e + } + else + { + ChunkBuffer[0] = ( uint8_t )( ( payload_size ) >> 8 ); + 800ae3a: 89fb ldrh r3, [r7, #14] + 800ae3c: 0a1b lsrs r3, r3, #8 + 800ae3e: b29b uxth r3, r3 + 800ae40: b2da uxtb r2, r3 + 800ae42: 4b66 ldr r3, [pc, #408] @ (800afdc ) + 800ae44: 701a strb r2, [r3, #0] + ChunkBuffer[1] = ( uint8_t )( ( payload_size ) & 0xFF ); + 800ae46: 89fb ldrh r3, [r7, #14] + 800ae48: b2da uxtb r2, r3 + 800ae4a: 4b64 ldr r3, [pc, #400] @ (800afdc ) + 800ae4c: 705a strb r2, [r3, #1] + } + /* Get Tx chunk from app*/ + TxLongPacketGetNextChunkCb( &app_chunk_buffer_ptr, chunk_size ); + 800ae4e: f897 102b ldrb.w r1, [r7, #43] @ 0x2b + 800ae52: f107 0218 add.w r2, r7, #24 + 800ae56: 687b ldr r3, [r7, #4] + 800ae58: 4610 mov r0, r2 + 800ae5a: 4798 blx r3 + + /* Copy first chunk in ChunkBuffer Buffer*/ + RADIO_MEMCPY8( &ChunkBuffer[RFWPacket.Init.PayloadLengthFieldSize], app_chunk_buffer_ptr, chunk_size ); + 800ae5c: 4b5c ldr r3, [pc, #368] @ (800afd0 ) + 800ae5e: 785b ldrb r3, [r3, #1] + 800ae60: 461a mov r2, r3 + 800ae62: 4b5e ldr r3, [pc, #376] @ (800afdc ) + 800ae64: 4413 add r3, r2 + 800ae66: 69b9 ldr r1, [r7, #24] + 800ae68: f897 202b ldrb.w r2, [r7, #43] @ 0x2b + 800ae6c: b292 uxth r2, r2 + 800ae6e: 4618 mov r0, r3 + 800ae70: f002 f9dc bl 800d22c + + if( RFWPacket.Init.CrcEnable == 1 ) + 800ae74: 4b56 ldr r3, [pc, #344] @ (800afd0 ) + 800ae76: 789b ldrb r3, [r3, #2] + 800ae78: 2b01 cmp r3, #1 + 800ae7a: d11f bne.n 800aebc + { + /* Set the state of the Crc to crc_seed*/ + RFW_CrcSetState( &RFWPacket ); + 800ae7c: 4854 ldr r0, [pc, #336] @ (800afd0 ) + 800ae7e: f000 fc57 bl 800b730 + /* Run the crc calculation on payload length and payload*/ + RFW_CrcRun( &RFWPacket, ChunkBuffer, RFWPacket.Init.PayloadLengthFieldSize + chunk_size, crc_result ); + 800ae82: 4b53 ldr r3, [pc, #332] @ (800afd0 ) + 800ae84: 785b ldrb r3, [r3, #1] + 800ae86: 461a mov r2, r3 + 800ae88: f897 302b ldrb.w r3, [r7, #43] @ 0x2b + 800ae8c: 4413 add r3, r2 + 800ae8e: 461a mov r2, r3 + 800ae90: f107 0314 add.w r3, r7, #20 + 800ae94: 4951 ldr r1, [pc, #324] @ (800afdc ) + 800ae96: 484e ldr r0, [pc, #312] @ (800afd0 ) + 800ae98: f000 fc9f bl 800b7da + /* Append the crc result after the payload if total_size<= RADIO_BUF_SIZE*/ + RADIO_MEMCPY8( &ChunkBuffer[RFWPacket.Init.PayloadLengthFieldSize + chunk_size], crc_result, crc_size ); + 800ae9c: 4b4c ldr r3, [pc, #304] @ (800afd0 ) + 800ae9e: 785b ldrb r3, [r3, #1] + 800aea0: 461a mov r2, r3 + 800aea2: f897 302b ldrb.w r3, [r7, #43] @ 0x2b + 800aea6: 4413 add r3, r2 + 800aea8: 4a4c ldr r2, [pc, #304] @ (800afdc ) + 800aeaa: 4413 add r3, r2 + 800aeac: f897 202a ldrb.w r2, [r7, #42] @ 0x2a + 800aeb0: b292 uxth r2, r2 + 800aeb2: f107 0114 add.w r1, r7, #20 + 800aeb6: 4618 mov r0, r3 + 800aeb8: f002 f9b8 bl 800d22c + } + /* Init whitening at beginning of the packet*/ + RFW_WhiteSetState( &RFWPacket ); + 800aebc: 4844 ldr r0, [pc, #272] @ (800afd0 ) + 800aebe: f000 fc0f bl 800b6e0 + /* Run the whitening calculation on payload length, payload and crc if crc fits inside 1st chunk*/ + RFW_WhiteRun( &RFWPacket, &ChunkBuffer[0], RFWPacket.Init.PayloadLengthFieldSize + chunk_size + crc_size ); + 800aec2: 4b43 ldr r3, [pc, #268] @ (800afd0 ) + 800aec4: 785b ldrb r3, [r3, #1] + 800aec6: 461a mov r2, r3 + 800aec8: f897 302b ldrb.w r3, [r7, #43] @ 0x2b + 800aecc: 441a add r2, r3 + 800aece: f897 302a ldrb.w r3, [r7, #42] @ 0x2a + 800aed2: 4413 add r3, r2 + 800aed4: 461a mov r2, r3 + 800aed6: 4941 ldr r1, [pc, #260] @ (800afdc ) + 800aed8: 483d ldr r0, [pc, #244] @ (800afd0 ) + 800aeda: f000 fc36 bl 800b74a + /* Configure the Transmitter to send all*/ + /* Init radio buffer */ + SUBGRF_WriteRegister( SUBGHZ_GRTXPLDLEN, RFWPacket.Init.PayloadLengthFieldSize + chunk_size + crc_size ); + 800aede: 4b3c ldr r3, [pc, #240] @ (800afd0 ) + 800aee0: 785a ldrb r2, [r3, #1] + 800aee2: f897 302b ldrb.w r3, [r7, #43] @ 0x2b + 800aee6: 4413 add r3, r2 + 800aee8: b2da uxtb r2, r3 + 800aeea: f897 302a ldrb.w r3, [r7, #42] @ 0x2a + 800aeee: 4413 add r3, r2 + 800aef0: b2db uxtb r3, r3 + 800aef2: 4619 mov r1, r3 + 800aef4: f240 60bb movw r0, #1723 @ 0x6bb + 800aef8: f7ff fc08 bl 800a70c + SUBGRF_WriteRegister( SUBGHZ_TXADRPTR, 0 ); + 800aefc: 2100 movs r1, #0 + 800aefe: f640 0002 movw r0, #2050 @ 0x802 + 800af02: f7ff fc03 bl 800a70c + /* Send*/ + SUBGRF_SendPayload( ChunkBuffer, RFWPacket.Init.PayloadLengthFieldSize + chunk_size + crc_size, 0 ); + 800af06: 4b32 ldr r3, [pc, #200] @ (800afd0 ) + 800af08: 785a ldrb r2, [r3, #1] + 800af0a: f897 302b ldrb.w r3, [r7, #43] @ 0x2b + 800af0e: 4413 add r3, r2 + 800af10: b2da uxtb r2, r3 + 800af12: f897 302a ldrb.w r3, [r7, #42] @ 0x2a + 800af16: 4413 add r3, r2 + 800af18: b2db uxtb r3, r3 + 800af1a: 2200 movs r2, #0 + 800af1c: 4619 mov r1, r3 + 800af1e: 482f ldr r0, [pc, #188] @ (800afdc ) + 800af20: f7fe fd60 bl 80099e4 + if( total_size > RADIO_BUF_SIZE ) + 800af24: 6a7b ldr r3, [r7, #36] @ 0x24 + 800af26: 2bff cmp r3, #255 @ 0xff + 800af28: d94b bls.n 800afc2 + { + /*in case total size is greater than RADIO_BUF_SIZE, need to program a timer to get next chunk*/ + /*RFWPacket.LongPacketRemainingBytes-= RFWPacket.Init.PayloadLengthFieldSize+ chunk_size+ crc_size;*/ + /*Initialize Timer to get new chunk and update radio ptr*/ + chunk_timeout = ( LONGPACKET_CHUNK_LENGTH_BYTES * 8 * 1000 ) / RFWPacket.BitRate; + 800af2a: 4b29 ldr r3, [pc, #164] @ (800afd0 ) + 800af2c: 6c9b ldr r3, [r3, #72] @ 0x48 + 800af2e: f44f 227a mov.w r2, #1024000 @ 0xfa000 + 800af32: fbb2 f3f3 udiv r3, r2, r3 + 800af36: 623b str r3, [r7, #32] + RFW_MW_LOG( TS_ON, VLEVEL_M, "Timeout=%d,\r\n", chunk_timeout ); + 800af38: 6a3b ldr r3, [r7, #32] + 800af3a: 9300 str r3, [sp, #0] + 800af3c: 4b28 ldr r3, [pc, #160] @ (800afe0 ) + 800af3e: 2201 movs r2, #1 + 800af40: 2100 movs r1, #0 + 800af42: 2002 movs r0, #2 + 800af44: f003 f870 bl 800e028 + TimerInit( &RFWPacket.Timer, RFW_TransmitLongPacket_NewTxChunkTimerEvent ); + 800af48: 2300 movs r3, #0 + 800af4a: 9300 str r3, [sp, #0] + 800af4c: 4b25 ldr r3, [pc, #148] @ (800afe4 ) + 800af4e: 2200 movs r2, #0 + 800af50: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff + 800af54: 4824 ldr r0, [pc, #144] @ (800afe8 ) + 800af56: f002 fdcb bl 800daf0 + TimerSetValue( &RFWPacket.Timer, chunk_timeout ); + 800af5a: 6a39 ldr r1, [r7, #32] + 800af5c: 4822 ldr r0, [pc, #136] @ (800afe8 ) + 800af5e: f002 fedb bl 800dd18 + TimerStart( &RFWPacket.Timer ); + 800af62: 4821 ldr r0, [pc, #132] @ (800afe8 ) + 800af64: f002 fdfa bl 800db5c + /*Write bit infinite_sequence = 1, required for long packet*/ + uint8_t reg = SUBGRF_ReadRegister( SUBGHZ_GPKTCTL1AR ); + 800af68: f44f 60d7 mov.w r0, #1720 @ 0x6b8 + 800af6c: f7ff fbf0 bl 800a750 + 800af70: 4603 mov r3, r0 + 800af72: 77fb strb r3, [r7, #31] + SUBGRF_WriteRegister( SUBGHZ_GPKTCTL1AR, reg | 0x02 ); + 800af74: 7ffb ldrb r3, [r7, #31] + 800af76: f043 0302 orr.w r3, r3, #2 + 800af7a: b2db uxtb r3, r3 + 800af7c: 4619 mov r1, r3 + 800af7e: f44f 60d7 mov.w r0, #1720 @ 0x6b8 + 800af82: f7ff fbc3 bl 800a70c + + TimerSetValue( RFWPacket.RxTimeoutTimer, timeout ); + 800af86: 4b12 ldr r3, [pc, #72] @ (800afd0 ) + 800af88: 6cdb ldr r3, [r3, #76] @ 0x4c + 800af8a: 68b9 ldr r1, [r7, #8] + 800af8c: 4618 mov r0, r3 + 800af8e: f002 fec3 bl 800dd18 + TimerStart( RFWPacket.RxTimeoutTimer ); + 800af92: 4b0f ldr r3, [pc, #60] @ (800afd0 ) + 800af94: 6cdb ldr r3, [r3, #76] @ 0x4c + 800af96: 4618 mov r0, r3 + 800af98: f002 fde0 bl 800db5c + else + { + /* error*/ + status = -1; + } + break; + 800af9c: e011 b.n 800afc2 + status = -1; + 800af9e: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff + 800afa2: 62fb str r3, [r7, #44] @ 0x2c + break; + 800afa4: e00d b.n 800afc2 + } + case MODEM_LORA: + { + /* not supported by the radio Ip*/ + status = -2; + 800afa6: f06f 0301 mvn.w r3, #1 + 800afaa: 62fb str r3, [r7, #44] @ 0x2c + break; + 800afac: e00a b.n 800afc4 + } + case MODEM_BPSK: + { + /* not supported by the FW*/ + status = -2; + 800afae: f06f 0301 mvn.w r3, #1 + 800afb2: 62fb str r3, [r7, #44] @ 0x2c + break; + 800afb4: e006 b.n 800afc4 + } + case MODEM_SIGFOX_TX: + { + /* not supported by the FW*/ + status = -2; + 800afb6: f06f 0301 mvn.w r3, #1 + 800afba: 62fb str r3, [r7, #44] @ 0x2c + break; + 800afbc: e002 b.n 800afc4 + } + default: + break; + 800afbe: bf00 nop + 800afc0: e000 b.n 800afc4 + break; + 800afc2: bf00 nop + } + } +#else + status = -1; +#endif /* RFW_LONGPACKET_ENABLE == 1 */ + return status; + 800afc4: 6afb ldr r3, [r7, #44] @ 0x2c +} + 800afc6: 4618 mov r0, r3 + 800afc8: 3730 adds r7, #48 @ 0x30 + 800afca: 46bd mov sp, r7 + 800afcc: bd80 pop {r7, pc} + 800afce: bf00 nop + 800afd0: 2000039c .word 0x2000039c + 800afd4: 0800f164 .word 0x0800f164 + 800afd8: 48000400 .word 0x48000400 + 800afdc: 200003f0 .word 0x200003f0 + 800afe0: 0800f174 .word 0x0800f174 + 800afe4: 0800b4e1 .word 0x0800b4e1 + 800afe8: 200003b8 .word 0x200003b8 + +0800afec : + +int32_t RFW_ReceiveLongPacket( uint8_t boosted_mode, uint32_t timeout, + void ( *RxLongPacketStoreChunkCb )( uint8_t *buffer, uint8_t chunk_size ) ) +{ + 800afec: b580 push {r7, lr} + 800afee: b086 sub sp, #24 + 800aff0: af00 add r7, sp, #0 + 800aff2: 4603 mov r3, r0 + 800aff4: 60b9 str r1, [r7, #8] + 800aff6: 607a str r2, [r7, #4] + 800aff8: 73fb strb r3, [r7, #15] + int32_t status = 0; + 800affa: 2300 movs r3, #0 + 800affc: 617b str r3, [r7, #20] +#if (RFW_LONGPACKET_ENABLE == 1 ) + if( ( RxLongPacketStoreChunkCb == NULL ) || + 800affe: 687b ldr r3, [r7, #4] + 800b000: 2b00 cmp r3, #0 + 800b002: d003 beq.n 800b00c + ( RFWPacket.Init.Enable == 0 ) ) /* Can only be used when after RadioSetRxGenericConfig*/ + 800b004: 4b2a ldr r3, [pc, #168] @ (800b0b0 ) + 800b006: 781b ldrb r3, [r3, #0] + if( ( RxLongPacketStoreChunkCb == NULL ) || + 800b008: 2b00 cmp r3, #0 + 800b00a: d103 bne.n 800b014 + { + status = -1; + 800b00c: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff + 800b010: 617b str r3, [r7, #20] + 800b012: e047 b.n 800b0a4 + } + else + { + /*Records call back*/ + RFWPacket.RxLongPacketStoreChunkCb = RxLongPacketStoreChunkCb; + 800b014: 4a26 ldr r2, [pc, #152] @ (800b0b0 ) + 800b016: 687b ldr r3, [r7, #4] + 800b018: 63d3 str r3, [r2, #60] @ 0x3c + SUBGRF_SetDioIrqParams( IRQ_SYNCWORD_VALID | IRQ_RX_TX_TIMEOUT, + 800b01a: 2300 movs r3, #0 + 800b01c: 2200 movs r2, #0 + 800b01e: f44f 7102 mov.w r1, #520 @ 0x208 + 800b022: f44f 7002 mov.w r0, #520 @ 0x208 + 800b026: f7fe ffc7 bl 8009fb8 + IRQ_SYNCWORD_VALID | IRQ_RX_TX_TIMEOUT, + IRQ_RADIO_NONE, + IRQ_RADIO_NONE ); + SUBGRF_SetSwitch( RFWPacket.AntSwitchPaSelect, RFSWITCH_RX ); + 800b02a: 4b21 ldr r3, [pc, #132] @ (800b0b0 ) + 800b02c: f893 3044 ldrb.w r3, [r3, #68] @ 0x44 + 800b030: 2100 movs r1, #0 + 800b032: 4618 mov r0, r3 + 800b034: f7ff fc78 bl 800a928 + /*init radio buffer offset*/ + RFWPacket.RadioBufferOffset = 0; + 800b038: 4b1d ldr r3, [pc, #116] @ (800b0b0 ) + 800b03a: 2200 movs r2, #0 + 800b03c: f883 2036 strb.w r2, [r3, #54] @ 0x36 + /* Init whitening at beginning of the packet*/ + RFW_WhiteSetState( &RFWPacket ); + 800b040: 481b ldr r0, [pc, #108] @ (800b0b0 ) + 800b042: f000 fb4d bl 800b6e0 + /* Set the state of the Crc to crc_seed*/ + RFW_CrcSetState( &RFWPacket ); + 800b046: 481a ldr r0, [pc, #104] @ (800b0b0 ) + 800b048: f000 fb72 bl 800b730 + /* Init radio buffer */ + SUBGRF_WriteRegister( SUBGHZ_GRTXPLDLEN, 255 ); + 800b04c: 21ff movs r1, #255 @ 0xff + 800b04e: f240 60bb movw r0, #1723 @ 0x6bb + 800b052: f7ff fb5b bl 800a70c + SUBGRF_WriteRegister( SUBGHZ_RXADRPTR, 0 ); + 800b056: 2100 movs r1, #0 + 800b058: f640 0003 movw r0, #2051 @ 0x803 + 800b05c: f7ff fb56 bl 800a70c + /*enable long packet*/ + RFWPacket.LongPacketModeEnable = 1; + 800b060: 4b13 ldr r3, [pc, #76] @ (800b0b0 ) + 800b062: 2201 movs r2, #1 + 800b064: 769a strb r2, [r3, #26] + + if( timeout != 0 ) + 800b066: 68bb ldr r3, [r7, #8] + 800b068: 2b00 cmp r3, #0 + 800b06a: d00a beq.n 800b082 + { + TimerSetValue( RFWPacket.RxTimeoutTimer, timeout ); + 800b06c: 4b10 ldr r3, [pc, #64] @ (800b0b0 ) + 800b06e: 6cdb ldr r3, [r3, #76] @ 0x4c + 800b070: 68b9 ldr r1, [r7, #8] + 800b072: 4618 mov r0, r3 + 800b074: f002 fe50 bl 800dd18 + TimerStart( RFWPacket.RxTimeoutTimer ); + 800b078: 4b0d ldr r3, [pc, #52] @ (800b0b0 ) + 800b07a: 6cdb ldr r3, [r3, #76] @ 0x4c + 800b07c: 4618 mov r0, r3 + 800b07e: f002 fd6d bl 800db5c + } + DBG_GPIO_RADIO_RX( SET ); + 800b082: f44f 5180 mov.w r1, #4096 @ 0x1000 + 800b086: 480b ldr r0, [pc, #44] @ (800b0b4 ) + 800b088: f7ff fe1c bl 800acc4 + if( boosted_mode == 1 ) + 800b08c: 7bfb ldrb r3, [r7, #15] + 800b08e: 2b01 cmp r3, #1 + 800b090: d104 bne.n 800b09c + { + SUBGRF_SetRxBoosted( 0xFFFFFF ); /* Rx Continuous */ + 800b092: f06f 407f mvn.w r0, #4278190080 @ 0xff000000 + 800b096: f7fe fe11 bl 8009cbc + 800b09a: e003 b.n 800b0a4 + } + else + { + SUBGRF_SetRx( 0xFFFFFF ); /* Rx Continuous */ + 800b09c: f06f 407f mvn.w r0, #4278190080 @ 0xff000000 + 800b0a0: f7fe fdec bl 8009c7c + } + } +#else + status = -1; +#endif /* RFW_LONGPACKET_ENABLE == 1 */ + return status; + 800b0a4: 697b ldr r3, [r7, #20] +} + 800b0a6: 4618 mov r0, r3 + 800b0a8: 3718 adds r7, #24 + 800b0aa: 46bd mov sp, r7 + 800b0ac: bd80 pop {r7, pc} + 800b0ae: bf00 nop + 800b0b0: 2000039c .word 0x2000039c + 800b0b4: 48000400 .word 0x48000400 + +0800b0b8 : + +int32_t RFW_Init( ConfigGeneric_t *config, RadioEvents_t *RadioEvents, TimerEvent_t *TimeoutTimerEvent ) +{ + 800b0b8: b580 push {r7, lr} + 800b0ba: b08a sub sp, #40 @ 0x28 + 800b0bc: af02 add r7, sp, #8 + 800b0be: 60f8 str r0, [r7, #12] + 800b0c0: 60b9 str r1, [r7, #8] + 800b0c2: 607a str r2, [r7, #4] +#if (RFW_ENABLE == 1 ) + RADIO_FSK_PacketLengthModes_t HeaderType; + uint32_t RxMaxPayloadLength = 0; + 800b0c4: 2300 movs r3, #0 + 800b0c6: 61bb str r3, [r7, #24] + RADIO_FSK_CrcTypes_t CrcLength; + uint16_t whiteSeed; + uint16_t CrcPolynomial; + uint16_t CrcSeed; + if( config->rtx == CONFIG_TX ) + 800b0c8: 68fb ldr r3, [r7, #12] + 800b0ca: 7a1b ldrb r3, [r3, #8] + 800b0cc: 2b01 cmp r3, #1 + 800b0ce: d11c bne.n 800b10a + { + HeaderType = config->TxConfig->fsk.HeaderType; + 800b0d0: 68fb ldr r3, [r7, #12] + 800b0d2: 681b ldr r3, [r3, #0] + 800b0d4: 7d1b ldrb r3, [r3, #20] + 800b0d6: 77fb strb r3, [r7, #31] + CrcLength = config->TxConfig->fsk.CrcLength; + 800b0d8: 68fb ldr r3, [r7, #12] + 800b0da: 681b ldr r3, [r3, #0] + 800b0dc: 7d5b ldrb r3, [r3, #21] + 800b0de: 75fb strb r3, [r7, #23] + whiteSeed = config->TxConfig->fsk.whiteSeed; + 800b0e0: 68fb ldr r3, [r7, #12] + 800b0e2: 681b ldr r3, [r3, #0] + 800b0e4: 8a1b ldrh r3, [r3, #16] + 800b0e6: 82bb strh r3, [r7, #20] + CrcPolynomial = config->TxConfig->fsk.CrcPolynomial; + 800b0e8: 68fb ldr r3, [r7, #12] + 800b0ea: 681b ldr r3, [r3, #0] + 800b0ec: 899b ldrh r3, [r3, #12] + 800b0ee: 827b strh r3, [r7, #18] + CrcSeed = config->TxConfig->fsk.CrcSeed; + 800b0f0: 68fb ldr r3, [r7, #12] + 800b0f2: 681b ldr r3, [r3, #0] + 800b0f4: 89db ldrh r3, [r3, #14] + 800b0f6: 823b strh r3, [r7, #16] + RFWPacket.BitRate = config->TxConfig->fsk.BitRate; + 800b0f8: 68fb ldr r3, [r7, #12] + 800b0fa: 681b ldr r3, [r3, #0] + 800b0fc: 681b ldr r3, [r3, #0] + 800b0fe: 4a38 ldr r2, [pc, #224] @ (800b1e0 ) + 800b100: 6493 str r3, [r2, #72] @ 0x48 + RFWPacket.TxTimeoutTimer = TimeoutTimerEvent; + 800b102: 4a37 ldr r2, [pc, #220] @ (800b1e0 ) + 800b104: 687b ldr r3, [r7, #4] + 800b106: 6513 str r3, [r2, #80] @ 0x50 + 800b108: e021 b.n 800b14e + } + else + { + HeaderType = config->RxConfig->fsk.LengthMode; + 800b10a: 68fb ldr r3, [r7, #12] + 800b10c: 685b ldr r3, [r3, #4] + 800b10e: f893 3022 ldrb.w r3, [r3, #34] @ 0x22 + 800b112: 77fb strb r3, [r7, #31] + CrcLength = config->RxConfig->fsk.CrcLength; + 800b114: 68fb ldr r3, [r7, #12] + 800b116: 685b ldr r3, [r3, #4] + 800b118: f893 3023 ldrb.w r3, [r3, #35] @ 0x23 + 800b11c: 75fb strb r3, [r7, #23] + RxMaxPayloadLength = config->RxConfig->fsk.MaxPayloadLength; + 800b11e: 68fb ldr r3, [r7, #12] + 800b120: 685b ldr r3, [r3, #4] + 800b122: 695b ldr r3, [r3, #20] + 800b124: 61bb str r3, [r7, #24] + whiteSeed = config->RxConfig->fsk.whiteSeed; + 800b126: 68fb ldr r3, [r7, #12] + 800b128: 685b ldr r3, [r3, #4] + 800b12a: 8b9b ldrh r3, [r3, #28] + 800b12c: 82bb strh r3, [r7, #20] + CrcPolynomial = config->RxConfig->fsk.CrcPolynomial; + 800b12e: 68fb ldr r3, [r7, #12] + 800b130: 685b ldr r3, [r3, #4] + 800b132: 8b1b ldrh r3, [r3, #24] + 800b134: 827b strh r3, [r7, #18] + CrcSeed = config->RxConfig->fsk.CrcSeed; + 800b136: 68fb ldr r3, [r7, #12] + 800b138: 685b ldr r3, [r3, #4] + 800b13a: 8b5b ldrh r3, [r3, #26] + 800b13c: 823b strh r3, [r7, #16] + RFWPacket.BitRate = config->RxConfig->fsk.BitRate; + 800b13e: 68fb ldr r3, [r7, #12] + 800b140: 685b ldr r3, [r3, #4] + 800b142: 689b ldr r3, [r3, #8] + 800b144: 4a26 ldr r2, [pc, #152] @ (800b1e0 ) + 800b146: 6493 str r3, [r2, #72] @ 0x48 + RFWPacket.RxTimeoutTimer = TimeoutTimerEvent; + 800b148: 4a25 ldr r2, [pc, #148] @ (800b1e0 ) + 800b14a: 687b ldr r3, [r7, #4] + 800b14c: 64d3 str r3, [r2, #76] @ 0x4c + } + if( ( RadioEvents != NULL ) && ( RadioEvents->RxError ) ) + 800b14e: 68bb ldr r3, [r7, #8] + 800b150: 2b00 cmp r3, #0 + 800b152: d00a beq.n 800b16a + 800b154: 68bb ldr r3, [r7, #8] + 800b156: 691b ldr r3, [r3, #16] + 800b158: 2b00 cmp r3, #0 + 800b15a: d006 beq.n 800b16a + { + RFWPacket.Init.RadioEvents = RadioEvents; + 800b15c: 4a20 ldr r2, [pc, #128] @ (800b1e0 ) + 800b15e: 68bb ldr r3, [r7, #8] + 800b160: 6113 str r3, [r2, #16] + } + else + { + return -1; + } + if( HeaderType == RADIO_FSK_PACKET_2BYTES_LENGTH ) + 800b162: 7ffb ldrb r3, [r7, #31] + 800b164: 2b02 cmp r3, #2 + 800b166: d003 beq.n 800b170 + 800b168: e006 b.n 800b178 + return -1; + 800b16a: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff + 800b16e: e032 b.n 800b1d6 + { +#if (RFW_LONGPACKET_ENABLE == 1 ) + RFWPacket.Init.PayloadLengthFieldSize = 2; + 800b170: 4b1b ldr r3, [pc, #108] @ (800b1e0 ) + 800b172: 2202 movs r2, #2 + 800b174: 705a strb r2, [r3, #1] + 800b176: e002 b.n 800b17e + return -1; +#endif /* RFW_LONGPACKET_ENABLE == 1 */ + } + else + { + RFWPacket.Init.PayloadLengthFieldSize = 1; + 800b178: 4b19 ldr r3, [pc, #100] @ (800b1e0 ) + 800b17a: 2201 movs r2, #1 + 800b17c: 705a strb r2, [r3, #1] + } + /*record, used to reject packet in length decoded at sync time out greater than LongPacketMaxRxLength*/ + RFWPacket.Init.LongPacketMaxRxLength = RxMaxPayloadLength; + 800b17e: 69bb ldr r3, [r7, #24] + 800b180: b29a uxth r2, r3 + 800b182: 4b17 ldr r3, [pc, #92] @ (800b1e0 ) + 800b184: 819a strh r2, [r3, #12] + if( CrcLength == RADIO_FSK_CRC_OFF ) + 800b186: 7dfb ldrb r3, [r7, #23] + 800b188: 2b01 cmp r3, #1 + 800b18a: d106 bne.n 800b19a + { + RFWPacket.Init.CrcEnable = 0; + 800b18c: 4b14 ldr r3, [pc, #80] @ (800b1e0 ) + 800b18e: 2200 movs r2, #0 + 800b190: 709a strb r2, [r3, #2] + RFWPacket.Init.CrcFieldSize = 0; + 800b192: 4b13 ldr r3, [pc, #76] @ (800b1e0 ) + 800b194: 2200 movs r2, #0 + 800b196: 70da strb r2, [r3, #3] + 800b198: e005 b.n 800b1a6 + } + else + { + RFWPacket.Init.CrcEnable = 1; + 800b19a: 4b11 ldr r3, [pc, #68] @ (800b1e0 ) + 800b19c: 2201 movs r2, #1 + 800b19e: 709a strb r2, [r3, #2] + RFWPacket.Init.CrcFieldSize = 2; + 800b1a0: 4b0f ldr r3, [pc, #60] @ (800b1e0 ) + 800b1a2: 2202 movs r2, #2 + 800b1a4: 70da strb r2, [r3, #3] + } + /*Macro can be used to init interrupt behaviour*/ + RFW_IT_INIT(); + /*Initialise whitening Seed*/ + RFW_WhiteInitState( &RFWPacket.Init, whiteSeed ); + 800b1a6: 8abb ldrh r3, [r7, #20] + 800b1a8: 4619 mov r1, r3 + 800b1aa: 480d ldr r0, [pc, #52] @ (800b1e0 ) + 800b1ac: f000 fa8a bl 800b6c4 + /*Initialise Crc Seed*/ + RFW_CrcInitState( &RFWPacket.Init, CrcPolynomial, CrcSeed, CrcLength ); + 800b1b0: 7dfb ldrb r3, [r7, #23] + 800b1b2: 8a3a ldrh r2, [r7, #16] + 800b1b4: 8a79 ldrh r1, [r7, #18] + 800b1b6: 480a ldr r0, [pc, #40] @ (800b1e0 ) + 800b1b8: f000 fa9f bl 800b6fa + /*Enable the RFWPacket decoding*/ + RFWPacket.Init.Enable = 1; + 800b1bc: 4b08 ldr r3, [pc, #32] @ (800b1e0 ) + 800b1be: 2201 movs r2, #1 + 800b1c0: 701a strb r2, [r3, #0] + /* Initialize Timer for end of fixed packet, started at sync*/ + TimerInit( &RFWPacket.Timer, RFW_GetPayloadTimerEvent ); + 800b1c2: 2300 movs r3, #0 + 800b1c4: 9300 str r3, [sp, #0] + 800b1c6: 4b07 ldr r3, [pc, #28] @ (800b1e4 ) + 800b1c8: 2200 movs r2, #0 + 800b1ca: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff + 800b1ce: 4806 ldr r0, [pc, #24] @ (800b1e8 ) + 800b1d0: f002 fc8e bl 800daf0 + return 0; + 800b1d4: 2300 movs r3, #0 +#else + return -1; +#endif /* RFW_ENABLE == 1 */ +} + 800b1d6: 4618 mov r0, r3 + 800b1d8: 3720 adds r7, #32 + 800b1da: 46bd mov sp, r7 + 800b1dc: bd80 pop {r7, pc} + 800b1de: bf00 nop + 800b1e0: 2000039c .word 0x2000039c + 800b1e4: 0800b9f5 .word 0x0800b9f5 + 800b1e8: 200003b8 .word 0x200003b8 + +0800b1ec : + +void RFW_DeInit( void ) +{ + 800b1ec: b480 push {r7} + 800b1ee: af00 add r7, sp, #0 +#if (RFW_ENABLE == 1 ) + RFWPacket.Init.Enable = 0; /*Disable the RFWPacket decoding*/ + 800b1f0: 4b03 ldr r3, [pc, #12] @ (800b200 ) + 800b1f2: 2200 movs r2, #0 + 800b1f4: 701a strb r2, [r3, #0] +#endif /* RFW_ENABLE == 1 */ +} + 800b1f6: bf00 nop + 800b1f8: 46bd mov sp, r7 + 800b1fa: bc80 pop {r7} + 800b1fc: 4770 bx lr + 800b1fe: bf00 nop + 800b200: 2000039c .word 0x2000039c + +0800b204 : + +uint8_t RFW_Is_Init( void ) +{ + 800b204: b480 push {r7} + 800b206: af00 add r7, sp, #0 +#if (RFW_ENABLE == 1 ) + return RFWPacket.Init.Enable; + 800b208: 4b02 ldr r3, [pc, #8] @ (800b214 ) + 800b20a: 781b ldrb r3, [r3, #0] +#else + return 0; +#endif /* RFW_ENABLE == 1 */ +} + 800b20c: 4618 mov r0, r3 + 800b20e: 46bd mov sp, r7 + 800b210: bc80 pop {r7} + 800b212: 4770 bx lr + 800b214: 2000039c .word 0x2000039c + +0800b218 : + +uint8_t RFW_Is_LongPacketModeEnabled( void ) +{ + 800b218: b480 push {r7} + 800b21a: af00 add r7, sp, #0 +#if (RFW_ENABLE == 1 ) + return RFWPacket.LongPacketModeEnable; + 800b21c: 4b02 ldr r3, [pc, #8] @ (800b228 ) + 800b21e: 7e9b ldrb r3, [r3, #26] +#else + return 0; +#endif /* RFW_ENABLE == 1 */ +} + 800b220: 4618 mov r0, r3 + 800b222: 46bd mov sp, r7 + 800b224: bc80 pop {r7} + 800b226: 4770 bx lr + 800b228: 2000039c .word 0x2000039c + +0800b22c : + +void RFW_SetAntSwitch( uint8_t AntSwitch ) +{ + 800b22c: b480 push {r7} + 800b22e: b083 sub sp, #12 + 800b230: af00 add r7, sp, #0 + 800b232: 4603 mov r3, r0 + 800b234: 71fb strb r3, [r7, #7] +#if (RFW_ENABLE == 1 ) + RFWPacket.AntSwitchPaSelect = AntSwitch; + 800b236: 4a04 ldr r2, [pc, #16] @ (800b248 ) + 800b238: 79fb ldrb r3, [r7, #7] + 800b23a: f882 3044 strb.w r3, [r2, #68] @ 0x44 +#endif /* RFW_ENABLE == 1 */ +} + 800b23e: bf00 nop + 800b240: 370c adds r7, #12 + 800b242: 46bd mov sp, r7 + 800b244: bc80 pop {r7} + 800b246: 4770 bx lr + 800b248: 2000039c .word 0x2000039c + +0800b24c : + +int32_t RFW_TransmitInit( uint8_t *inOutBuffer, uint8_t size, uint8_t *outSize ) +{ + 800b24c: b580 push {r7, lr} + 800b24e: b086 sub sp, #24 + 800b250: af00 add r7, sp, #0 + 800b252: 60f8 str r0, [r7, #12] + 800b254: 460b mov r3, r1 + 800b256: 607a str r2, [r7, #4] + 800b258: 72fb strb r3, [r7, #11] + int32_t status = -1; + 800b25a: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff + 800b25e: 617b str r3, [r7, #20] +#if (RFW_ENABLE == 1 ) + uint8_t crc_result[2]; + if( size + RFWPacket.Init.PayloadLengthFieldSize + RFWPacket.Init.CrcFieldSize > RADIO_BUF_SIZE ) + 800b260: 7afb ldrb r3, [r7, #11] + 800b262: 4a3a ldr r2, [pc, #232] @ (800b34c ) + 800b264: 7852 ldrb r2, [r2, #1] + 800b266: 4413 add r3, r2 + 800b268: 4a38 ldr r2, [pc, #224] @ (800b34c ) + 800b26a: 78d2 ldrb r2, [r2, #3] + 800b26c: 4413 add r3, r2 + 800b26e: 2bff cmp r3, #255 @ 0xff + 800b270: dd09 ble.n 800b286 + { + RFW_MW_LOG( TS_ON, VLEVEL_M, "RadioSend Oversize\r\n" ); + 800b272: 4b37 ldr r3, [pc, #220] @ (800b350 ) + 800b274: 2201 movs r2, #1 + 800b276: 2100 movs r1, #0 + 800b278: 2002 movs r0, #2 + 800b27a: f002 fed5 bl 800e028 + status = -1; + 800b27e: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff + 800b282: 617b str r3, [r7, #20] + 800b284: e05d b.n 800b342 + } + else + { + /* Copy tx buffer in payload*/ + RADIO_MEMCPY8( &ChunkBuffer[RFWPacket.Init.PayloadLengthFieldSize], inOutBuffer, size ); + 800b286: 4b31 ldr r3, [pc, #196] @ (800b34c ) + 800b288: 785b ldrb r3, [r3, #1] + 800b28a: 461a mov r2, r3 + 800b28c: 4b31 ldr r3, [pc, #196] @ (800b354 ) + 800b28e: 4413 add r3, r2 + 800b290: 7afa ldrb r2, [r7, #11] + 800b292: b292 uxth r2, r2 + 800b294: 68f9 ldr r1, [r7, #12] + 800b296: 4618 mov r0, r3 + 800b298: f001 ffc8 bl 800d22c + /* Calculate the crc on */ + /* Payload Size without the packet length field nor the CRC */ + /* Prepend payload size before Payload*/ + if( RFWPacket.Init.PayloadLengthFieldSize == 1 ) + 800b29c: 4b2b ldr r3, [pc, #172] @ (800b34c ) + 800b29e: 785b ldrb r3, [r3, #1] + 800b2a0: 2b01 cmp r3, #1 + 800b2a2: d103 bne.n 800b2ac + { + ChunkBuffer[0] = size; + 800b2a4: 4a2b ldr r2, [pc, #172] @ (800b354 ) + 800b2a6: 7afb ldrb r3, [r7, #11] + 800b2a8: 7013 strb r3, [r2, #0] + 800b2aa: e005 b.n 800b2b8 + } + else + { + ChunkBuffer[0] = 0; + 800b2ac: 4b29 ldr r3, [pc, #164] @ (800b354 ) + 800b2ae: 2200 movs r2, #0 + 800b2b0: 701a strb r2, [r3, #0] + ChunkBuffer[1] = size; + 800b2b2: 4a28 ldr r2, [pc, #160] @ (800b354 ) + 800b2b4: 7afb ldrb r3, [r7, #11] + 800b2b6: 7053 strb r3, [r2, #1] + } + if( RFWPacket.Init.CrcEnable == 1 ) + 800b2b8: 4b24 ldr r3, [pc, #144] @ (800b34c ) + 800b2ba: 789b ldrb r3, [r3, #2] + 800b2bc: 2b01 cmp r3, #1 + 800b2be: d11a bne.n 800b2f6 + { + /* Set the state of the Crc to crc_seed*/ + RFW_CrcSetState( &RFWPacket ); + 800b2c0: 4822 ldr r0, [pc, #136] @ (800b34c ) + 800b2c2: f000 fa35 bl 800b730 + /*Run the crc calculation on payload length and payload*/ + RFW_CrcRun( &RFWPacket, &ChunkBuffer[0], size + RFWPacket.Init.PayloadLengthFieldSize, crc_result ); + 800b2c6: 7afb ldrb r3, [r7, #11] + 800b2c8: 4a20 ldr r2, [pc, #128] @ (800b34c ) + 800b2ca: 7852 ldrb r2, [r2, #1] + 800b2cc: 4413 add r3, r2 + 800b2ce: 461a mov r2, r3 + 800b2d0: f107 0310 add.w r3, r7, #16 + 800b2d4: 491f ldr r1, [pc, #124] @ (800b354 ) + 800b2d6: 481d ldr r0, [pc, #116] @ (800b34c ) + 800b2d8: f000 fa7f bl 800b7da + /*append the crc result after the payload*/ + RADIO_MEMCPY8( &ChunkBuffer[size + RFWPacket.Init.PayloadLengthFieldSize], crc_result, RFWPacket.Init.CrcFieldSize ); + 800b2dc: 7afb ldrb r3, [r7, #11] + 800b2de: 4a1b ldr r2, [pc, #108] @ (800b34c ) + 800b2e0: 7852 ldrb r2, [r2, #1] + 800b2e2: 4413 add r3, r2 + 800b2e4: 4a1b ldr r2, [pc, #108] @ (800b354 ) + 800b2e6: 4413 add r3, r2 + 800b2e8: 4a18 ldr r2, [pc, #96] @ (800b34c ) + 800b2ea: 78d2 ldrb r2, [r2, #3] + 800b2ec: f107 0110 add.w r1, r7, #16 + 800b2f0: 4618 mov r0, r3 + 800b2f2: f001 ff9b bl 800d22c + } + /*init whitening at beginning of the packet*/ + RFW_WhiteSetState( &RFWPacket ); + 800b2f6: 4815 ldr r0, [pc, #84] @ (800b34c ) + 800b2f8: f000 f9f2 bl 800b6e0 + /*Run the whitening calculation on payload length, payload and crc*/ + RFW_WhiteRun( &RFWPacket, &ChunkBuffer[0], size + RFWPacket.Init.PayloadLengthFieldSize + RFWPacket.Init.CrcFieldSize ); + 800b2fc: 7afb ldrb r3, [r7, #11] + 800b2fe: 4a13 ldr r2, [pc, #76] @ (800b34c ) + 800b300: 7852 ldrb r2, [r2, #1] + 800b302: 4413 add r3, r2 + 800b304: 4a11 ldr r2, [pc, #68] @ (800b34c ) + 800b306: 78d2 ldrb r2, [r2, #3] + 800b308: 4413 add r3, r2 + 800b30a: 461a mov r2, r3 + 800b30c: 4911 ldr r1, [pc, #68] @ (800b354 ) + 800b30e: 480f ldr r0, [pc, #60] @ (800b34c ) + 800b310: f000 fa1b bl 800b74a + /*Configure the Transmitter to send all*/ + *outSize = ( uint8_t ) size + RFWPacket.Init.PayloadLengthFieldSize + RFWPacket.Init.CrcFieldSize; + 800b314: 4b0d ldr r3, [pc, #52] @ (800b34c ) + 800b316: 785a ldrb r2, [r3, #1] + 800b318: 7afb ldrb r3, [r7, #11] + 800b31a: 4413 add r3, r2 + 800b31c: b2da uxtb r2, r3 + 800b31e: 4b0b ldr r3, [pc, #44] @ (800b34c ) + 800b320: 78db ldrb r3, [r3, #3] + 800b322: 4413 add r3, r2 + 800b324: b2da uxtb r2, r3 + 800b326: 687b ldr r3, [r7, #4] + 800b328: 701a strb r2, [r3, #0] + /*copy result*/ + RADIO_MEMCPY8( inOutBuffer, ChunkBuffer, *outSize ); + 800b32a: 687b ldr r3, [r7, #4] + 800b32c: 781b ldrb r3, [r3, #0] + 800b32e: 461a mov r2, r3 + 800b330: 4908 ldr r1, [pc, #32] @ (800b354 ) + 800b332: 68f8 ldr r0, [r7, #12] + 800b334: f001 ff7a bl 800d22c + + RFWPacket.LongPacketModeEnable = 0; + 800b338: 4b04 ldr r3, [pc, #16] @ (800b34c ) + 800b33a: 2200 movs r2, #0 + 800b33c: 769a strb r2, [r3, #26] + + status = 0; + 800b33e: 2300 movs r3, #0 + 800b340: 617b str r3, [r7, #20] + } +#endif /* RFW_ENABLE == 1 */ + return status; + 800b342: 697b ldr r3, [r7, #20] +} + 800b344: 4618 mov r0, r3 + 800b346: 3718 adds r7, #24 + 800b348: 46bd mov sp, r7 + 800b34a: bd80 pop {r7, pc} + 800b34c: 2000039c .word 0x2000039c + 800b350: 0800f184 .word 0x0800f184 + 800b354: 200003f0 .word 0x200003f0 + +0800b358 : + +int32_t RFW_ReceiveInit( void ) +{ + 800b358: b580 push {r7, lr} + 800b35a: af00 add r7, sp, #0 +#if (RFW_ENABLE == 1 ) + /* Radio IRQ is set to DIO1 by default */ + SUBGRF_SetDioIrqParams( IRQ_RADIO_ALL & ( ~IRQ_RX_DONE ), /* IRQ_RX_DONE | IRQ_RX_TX_TIMEOUT, */ + 800b35c: 2300 movs r3, #0 + 800b35e: 2200 movs r2, #0 + 800b360: f64f 71fd movw r1, #65533 @ 0xfffd + 800b364: f64f 70fd movw r0, #65533 @ 0xfffd + 800b368: f7fe fe26 bl 8009fb8 + IRQ_RADIO_ALL & ( ~IRQ_RX_DONE ), /* IRQ_RX_DONE | IRQ_RX_TX_TIMEOUT, */ + IRQ_RADIO_NONE, + IRQ_RADIO_NONE ); + + /*init whitening at beginning of the packet*/ + RFW_WhiteSetState( &RFWPacket ); + 800b36c: 4807 ldr r0, [pc, #28] @ (800b38c ) + 800b36e: f000 f9b7 bl 800b6e0 + /* Set the state of the Crc to crc_seed*/ + RFW_CrcSetState( &RFWPacket ); + 800b372: 4806 ldr r0, [pc, #24] @ (800b38c ) + 800b374: f000 f9dc bl 800b730 + + RFWPacket.RxPayloadOffset = 0; + 800b378: 4b04 ldr r3, [pc, #16] @ (800b38c ) + 800b37a: 2200 movs r2, #0 + 800b37c: 871a strh r2, [r3, #56] @ 0x38 + + RFWPacket.LongPacketModeEnable = 0; + 800b37e: 4b03 ldr r3, [pc, #12] @ (800b38c ) + 800b380: 2200 movs r2, #0 + 800b382: 769a strb r2, [r3, #26] + return 0; + 800b384: 2300 movs r3, #0 +#else + return -1; +#endif /* RFW_ENABLE == 1 */ +} + 800b386: 4618 mov r0, r3 + 800b388: bd80 pop {r7, pc} + 800b38a: bf00 nop + 800b38c: 2000039c .word 0x2000039c + +0800b390 : + +void RFW_DeInit_TxLongPacket( void ) +{ + 800b390: b580 push {r7, lr} + 800b392: b082 sub sp, #8 + 800b394: af00 add r7, sp, #0 +#if (RFW_LONGPACKET_ENABLE == 1 ) + /*long packet WA*/ + uint8_t reg = SUBGRF_ReadRegister( SUBGHZ_GPKTCTL1AR ); + 800b396: f44f 60d7 mov.w r0, #1720 @ 0x6b8 + 800b39a: f7ff f9d9 bl 800a750 + 800b39e: 4603 mov r3, r0 + 800b3a0: 71fb strb r3, [r7, #7] + SUBGRF_WriteRegister( SUBGHZ_GPKTCTL1AR, reg & ~0x02 ); /* clear infinite_sequence bit */ + 800b3a2: 79fb ldrb r3, [r7, #7] + 800b3a4: f023 0302 bic.w r3, r3, #2 + 800b3a8: b2db uxtb r3, r3 + 800b3aa: 4619 mov r1, r3 + 800b3ac: f44f 60d7 mov.w r0, #1720 @ 0x6b8 + 800b3b0: f7ff f9ac bl 800a70c + SUBGRF_WriteRegister( SUBGHZ_GRTXPLDLEN, 0xFF ); /* RxTxPldLen: reset to 0xFF */ + 800b3b4: 21ff movs r1, #255 @ 0xff + 800b3b6: f240 60bb movw r0, #1723 @ 0x6bb + 800b3ba: f7ff f9a7 bl 800a70c +#endif /* RFW_LONGPACKET_ENABLE == 1 */ +} + 800b3be: bf00 nop + 800b3c0: 3708 adds r7, #8 + 800b3c2: 46bd mov sp, r7 + 800b3c4: bd80 pop {r7, pc} + ... + +0800b3c8 : + +void RFW_ReceivePayload( void ) +{ + 800b3c8: b580 push {r7, lr} + 800b3ca: b086 sub sp, #24 + 800b3cc: af02 add r7, sp, #8 +#if (RFW_ENABLE == 1 ) + uint16_t PayloadLength = 0; + 800b3ce: 2300 movs r3, #0 + 800b3d0: 80fb strh r3, [r7, #6] + if( RFW_GetPacketLength( &PayloadLength ) == 0 ) + 800b3d2: 1dbb adds r3, r7, #6 + 800b3d4: 4618 mov r0, r3 + 800b3d6: f000 fab7 bl 800b948 + 800b3da: 4603 mov r3, r0 + 800b3dc: 2b00 cmp r3, #0 + 800b3de: d15e bne.n 800b49e + { + uint32_t timeout; + uint32_t packet_length = PayloadLength + RFWPacket.Init.CrcFieldSize; + 800b3e0: 88fb ldrh r3, [r7, #6] + 800b3e2: 461a mov r2, r3 + 800b3e4: 4b33 ldr r3, [pc, #204] @ (800b4b4 ) + 800b3e6: 78db ldrb r3, [r3, #3] + 800b3e8: 4413 add r3, r2 + 800b3ea: 60bb str r3, [r7, #8] + /*record payload length*/ + RFWPacket.PayloadLength = PayloadLength; + 800b3ec: 88fa ldrh r2, [r7, #6] + 800b3ee: 4b31 ldr r3, [pc, #196] @ (800b4b4 ) + 800b3f0: 831a strh r2, [r3, #24] + /*record remaining payload length*/ + RFWPacket.LongPacketRemainingBytes = ( uint16_t ) packet_length; + 800b3f2: 68bb ldr r3, [r7, #8] + 800b3f4: b29a uxth r2, r3 + 800b3f6: 4b2f ldr r3, [pc, #188] @ (800b4b4 ) + 800b3f8: 869a strh r2, [r3, #52] @ 0x34 + /*record rx buffer offset*/ + RFWPacket.RadioBufferOffset = RFWPacket.Init.PayloadLengthFieldSize; + 800b3fa: 4b2e ldr r3, [pc, #184] @ (800b4b4 ) + 800b3fc: 785a ldrb r2, [r3, #1] + 800b3fe: 4b2d ldr r3, [pc, #180] @ (800b4b4 ) + 800b400: f883 2036 strb.w r2, [r3, #54] @ 0x36 + /*if decoded PayloadLength is longer than LongPacketMaxRxLength, reject packet*/ + if( PayloadLength > RFWPacket.Init.LongPacketMaxRxLength ) + 800b404: 4b2b ldr r3, [pc, #172] @ (800b4b4 ) + 800b406: 899a ldrh r2, [r3, #12] + 800b408: 88fb ldrh r3, [r7, #6] + 800b40a: 429a cmp r2, r3 + 800b40c: d207 bcs.n 800b41e + { + SUBGRF_SetStandby( STDBY_RC ); + 800b40e: 2000 movs r0, #0 + 800b410: f7fe fbf8 bl 8009c04 + RFWPacket.Init.RadioEvents->RxError( ); + 800b414: 4b27 ldr r3, [pc, #156] @ (800b4b4 ) + 800b416: 691b ldr r3, [r3, #16] + 800b418: 691b ldr r3, [r3, #16] + 800b41a: 4798 blx r3 + 800b41c: e046 b.n 800b4ac + return; + } + if( packet_length < LONGPACKET_CHUNK_LENGTH_BYTES ) + 800b41e: 68bb ldr r3, [r7, #8] + 800b420: 2b7f cmp r3, #127 @ 0x7f + 800b422: d817 bhi.n 800b454 + { + /* all in one chunks*/ + /* calculate time to end of packet*/ + timeout = DIVC( ( packet_length ) * 8 * 1000, RFWPacket.BitRate ) + 2; + 800b424: 68bb ldr r3, [r7, #8] + 800b426: f44f 52fa mov.w r2, #8000 @ 0x1f40 + 800b42a: fb03 f202 mul.w r2, r3, r2 + 800b42e: 4b21 ldr r3, [pc, #132] @ (800b4b4 ) + 800b430: 6c9b ldr r3, [r3, #72] @ 0x48 + 800b432: 4413 add r3, r2 + 800b434: 1e5a subs r2, r3, #1 + 800b436: 4b1f ldr r3, [pc, #124] @ (800b4b4 ) + 800b438: 6c9b ldr r3, [r3, #72] @ 0x48 + 800b43a: fbb2 f3f3 udiv r3, r2, r3 + 800b43e: 3302 adds r3, #2 + 800b440: 60fb str r3, [r7, #12] + /**/ + /* start timer at the end of the packet*/ + RFW_MW_LOG( TS_ON, VLEVEL_M, "end packet in %dms\r\n", timeout ); + 800b442: 68fb ldr r3, [r7, #12] + 800b444: 9300 str r3, [sp, #0] + 800b446: 4b1c ldr r3, [pc, #112] @ (800b4b8 ) + 800b448: 2201 movs r2, #1 + 800b44a: 2100 movs r1, #0 + 800b44c: 2002 movs r0, #2 + 800b44e: f002 fdeb bl 800e028 + 800b452: e01c b.n 800b48e + + } + else if( packet_length < ( 3 * LONGPACKET_CHUNK_LENGTH_BYTES / 2 ) ) + 800b454: 68bb ldr r3, [r7, #8] + 800b456: 2bbf cmp r3, #191 @ 0xbf + 800b458: d80f bhi.n 800b47a + { + /* packet contained in 2 chunks*/ + /* make sure that crc not cut in chunk*/ + timeout = DIVR( ( packet_length * 8 * 1000 ) / 2, RFWPacket.BitRate ); + 800b45a: 68bb ldr r3, [r7, #8] + 800b45c: f44f 52fa mov.w r2, #8000 @ 0x1f40 + 800b460: fb02 f303 mul.w r3, r2, r3 + 800b464: 085a lsrs r2, r3, #1 + 800b466: 4b13 ldr r3, [pc, #76] @ (800b4b4 ) + 800b468: 6c9b ldr r3, [r3, #72] @ 0x48 + 800b46a: 085b lsrs r3, r3, #1 + 800b46c: 441a add r2, r3 + 800b46e: 4b11 ldr r3, [pc, #68] @ (800b4b4 ) + 800b470: 6c9b ldr r3, [r3, #72] @ 0x48 + 800b472: fbb2 f3f3 udiv r3, r2, r3 + 800b476: 60fb str r3, [r7, #12] + 800b478: e009 b.n 800b48e + } + else + { + /* packet contained in multiple chunk*/ + /* program radio timer for first chunk*/ + timeout = DIVR( LONGPACKET_CHUNK_LENGTH_BYTES * 8 * 1000, RFWPacket.BitRate ); + 800b47a: 4b0e ldr r3, [pc, #56] @ (800b4b4 ) + 800b47c: 6c9b ldr r3, [r3, #72] @ 0x48 + 800b47e: 085b lsrs r3, r3, #1 + 800b480: f503 227a add.w r2, r3, #1024000 @ 0xfa000 + 800b484: 4b0b ldr r3, [pc, #44] @ (800b4b4 ) + 800b486: 6c9b ldr r3, [r3, #72] @ 0x48 + 800b488: fbb2 f3f3 udiv r3, r2, r3 + 800b48c: 60fb str r3, [r7, #12] + } + TimerSetValue( &RFWPacket.Timer, timeout ); + 800b48e: 68f9 ldr r1, [r7, #12] + 800b490: 480a ldr r0, [pc, #40] @ (800b4bc ) + 800b492: f002 fc41 bl 800dd18 + TimerStart( &RFWPacket.Timer ); + 800b496: 4809 ldr r0, [pc, #36] @ (800b4bc ) + 800b498: f002 fb60 bl 800db5c + 800b49c: e006 b.n 800b4ac + } + else + { + /*timeout*/ + SUBGRF_SetStandby( STDBY_RC ); + 800b49e: 2000 movs r0, #0 + 800b4a0: f7fe fbb0 bl 8009c04 + RFWPacket.Init.RadioEvents->RxTimeout( ); + 800b4a4: 4b03 ldr r3, [pc, #12] @ (800b4b4 ) + 800b4a6: 691b ldr r3, [r3, #16] + 800b4a8: 68db ldr r3, [r3, #12] + 800b4aa: 4798 blx r3 + } +#endif /* RFW_ENABLE == 1 */ +} + 800b4ac: 3710 adds r7, #16 + 800b4ae: 46bd mov sp, r7 + 800b4b0: bd80 pop {r7, pc} + 800b4b2: bf00 nop + 800b4b4: 2000039c .word 0x2000039c + 800b4b8: 0800f19c .word 0x0800f19c + 800b4bc: 200003b8 .word 0x200003b8 + +0800b4c0 : + +void RFW_SetRadioModem( RadioModems_t Modem ) +{ + 800b4c0: b480 push {r7} + 800b4c2: b083 sub sp, #12 + 800b4c4: af00 add r7, sp, #0 + 800b4c6: 4603 mov r3, r0 + 800b4c8: 71fb strb r3, [r7, #7] +#if (RFW_ENABLE == 1 ) + RFWPacket.Init.Modem = Modem; + 800b4ca: 4a04 ldr r2, [pc, #16] @ (800b4dc ) + 800b4cc: 79fb ldrb r3, [r7, #7] + 800b4ce: 7393 strb r3, [r2, #14] +#endif /* RFW_ENABLE == 1 */ +} + 800b4d0: bf00 nop + 800b4d2: 370c adds r7, #12 + 800b4d4: 46bd mov sp, r7 + 800b4d6: bc80 pop {r7} + 800b4d8: 4770 bx lr + 800b4da: bf00 nop + 800b4dc: 2000039c .word 0x2000039c + +0800b4e0 : + +/* Private Functions Definition -----------------------------------------------*/ +#if (RFW_LONGPACKET_ENABLE == 1 ) +static void RFW_TransmitLongPacket_NewTxChunkTimerEvent( void *param ) +{ + 800b4e0: b580 push {r7, lr} + 800b4e2: b082 sub sp, #8 + 800b4e4: af00 add r7, sp, #0 + 800b4e6: 6078 str r0, [r7, #4] + RFW_TRANSMIT_LONGPACKET_TX_CHUNK_PROCESS(); + 800b4e8: f000 f804 bl 800b4f4 +} + 800b4ec: bf00 nop + 800b4ee: 3708 adds r7, #8 + 800b4f0: 46bd mov sp, r7 + 800b4f2: bd80 pop {r7, pc} + +0800b4f4 : + +static void RFW_TransmitLongPacket_TxChunkProcess( void ) +{ + 800b4f4: b590 push {r4, r7, lr} + 800b4f6: b08d sub sp, #52 @ 0x34 + 800b4f8: af06 add r7, sp, #24 + uint8_t *app_chunk_buffer_ptr = NULL; + 800b4fa: 2300 movs r3, #0 + 800b4fc: 60bb str r3, [r7, #8] + uint8_t chunk_size = 0; + 800b4fe: 2300 movs r3, #0 + 800b500: 75fb strb r3, [r7, #23] + uint8_t crc_result[2] = {0}; + 800b502: 2300 movs r3, #0 + 800b504: 80bb strh r3, [r7, #4] + uint8_t crc_size; + uint32_t timeout;/*timeout for next chunk*/ + /*records how much has been sent*/ + uint8_t read_ptr = SUBGRF_ReadRegister( SUBGHZ_TXADRPTR ); /*radio has transmitted up to read_ptr*/ + 800b506: f640 0002 movw r0, #2050 @ 0x802 + 800b50a: f7ff f921 bl 800a750 + 800b50e: 4603 mov r3, r0 + 800b510: 757b strb r3, [r7, #21] + uint8_t write_ptr = SUBGRF_ReadRegister( SUBGHZ_GRTXPLDLEN ); /*from read_ptr to write_ptr still to be transmitted*/ + 800b512: f240 60bb movw r0, #1723 @ 0x6bb + 800b516: f7ff f91b bl 800a750 + 800b51a: 4603 mov r3, r0 + 800b51c: 753b strb r3, [r7, #20] + /*calculates how much bytes were sent since previous radio loading*/ + uint8_t bytes_sent = read_ptr - RFWPacket.RadioBufferOffset; + 800b51e: 4b64 ldr r3, [pc, #400] @ (800b6b0 ) + 800b520: f893 3036 ldrb.w r3, [r3, #54] @ 0x36 + 800b524: 7d7a ldrb r2, [r7, #21] + 800b526: 1ad3 subs r3, r2, r3 + 800b528: 74fb strb r3, [r7, #19] + /*bytes already loaded in the radio to send*/ + uint8_t bytes_loaded = write_ptr - read_ptr; + 800b52a: 7d3a ldrb r2, [r7, #20] + 800b52c: 7d7b ldrb r3, [r7, #21] + 800b52e: 1ad3 subs r3, r2, r3 + 800b530: 74bb strb r3, [r7, #18] + + /* Update offset tx, intentional wrap around*/ + RFWPacket.RadioBufferOffset += bytes_sent; + 800b532: 4b5f ldr r3, [pc, #380] @ (800b6b0 ) + 800b534: f893 2036 ldrb.w r2, [r3, #54] @ 0x36 + 800b538: 7cfb ldrb r3, [r7, #19] + 800b53a: 4413 add r3, r2 + 800b53c: b2da uxtb r2, r3 + 800b53e: 4b5c ldr r3, [pc, #368] @ (800b6b0 ) + 800b540: f883 2036 strb.w r2, [r3, #54] @ 0x36 + /*record payload remaining bytes to send*/ + RFWPacket.LongPacketRemainingBytes -= bytes_sent; + 800b544: 4b5a ldr r3, [pc, #360] @ (800b6b0 ) + 800b546: 8e9a ldrh r2, [r3, #52] @ 0x34 + 800b548: 7cfb ldrb r3, [r7, #19] + 800b54a: b29b uxth r3, r3 + 800b54c: 1ad3 subs r3, r2, r3 + 800b54e: b29a uxth r2, r3 + 800b550: 4b57 ldr r3, [pc, #348] @ (800b6b0 ) + 800b552: 869a strh r2, [r3, #52] @ 0x34 + RFW_MW_LOG( TS_ON, VLEVEL_M, "read_ptr=%d, write_ptr=%d, bytes_sent=%d, bytes_loaded=%d,remaining to send=%d\r\n", + 800b554: 7d7b ldrb r3, [r7, #21] + 800b556: 7d3a ldrb r2, [r7, #20] + 800b558: 7cf9 ldrb r1, [r7, #19] + 800b55a: 7cb8 ldrb r0, [r7, #18] + 800b55c: 4c54 ldr r4, [pc, #336] @ (800b6b0 ) + 800b55e: 8ea4 ldrh r4, [r4, #52] @ 0x34 + 800b560: 9404 str r4, [sp, #16] + 800b562: 9003 str r0, [sp, #12] + 800b564: 9102 str r1, [sp, #8] + 800b566: 9201 str r2, [sp, #4] + 800b568: 9300 str r3, [sp, #0] + 800b56a: 4b52 ldr r3, [pc, #328] @ (800b6b4 ) + 800b56c: 2201 movs r2, #1 + 800b56e: 2100 movs r1, #0 + 800b570: 2002 movs r0, #2 + 800b572: f002 fd59 bl 800e028 + read_ptr, write_ptr, bytes_sent, bytes_loaded, RFWPacket.LongPacketRemainingBytes ); + if( RFWPacket.LongPacketRemainingBytes > 256 ) + 800b576: 4b4e ldr r3, [pc, #312] @ (800b6b0 ) + 800b578: 8e9b ldrh r3, [r3, #52] @ 0x34 + 800b57a: f5b3 7f80 cmp.w r3, #256 @ 0x100 + 800b57e: d929 bls.n 800b5d4 + { + /*get next chunk */ + /*make sure that at least full CrcFieldSize will be loaded for the last chunk*/ + if( RFWPacket.LongPacketRemainingBytes > 256 + RFWPacket.Init.CrcFieldSize ) + 800b580: 4b4b ldr r3, [pc, #300] @ (800b6b0 ) + 800b582: 8e9b ldrh r3, [r3, #52] @ 0x34 + 800b584: 461a mov r2, r3 + 800b586: 4b4a ldr r3, [pc, #296] @ (800b6b0 ) + 800b588: 78db ldrb r3, [r3, #3] + 800b58a: f503 7380 add.w r3, r3, #256 @ 0x100 + 800b58e: 429a cmp r2, r3 + 800b590: dd02 ble.n 800b598 + { + chunk_size = bytes_sent; + 800b592: 7cfb ldrb r3, [r7, #19] + 800b594: 75fb strb r3, [r7, #23] + 800b596: e004 b.n 800b5a2 + } + else + { + chunk_size = bytes_sent - RFWPacket.Init.CrcFieldSize; + 800b598: 4b45 ldr r3, [pc, #276] @ (800b6b0 ) + 800b59a: 78db ldrb r3, [r3, #3] + 800b59c: 7cfa ldrb r2, [r7, #19] + 800b59e: 1ad3 subs r3, r2, r3 + 800b5a0: 75fb strb r3, [r7, #23] + } + /*no crc since it is not the last chunk*/ + crc_size = 0; + 800b5a2: 2300 movs r3, #0 + 800b5a4: 75bb strb r3, [r7, #22] + /*calculate timeout for next chunk*/ + timeout = DIVR( chunk_size * 8 * 1000, RFWPacket.BitRate ); + 800b5a6: 7dfb ldrb r3, [r7, #23] + 800b5a8: f44f 52fa mov.w r2, #8000 @ 0x1f40 + 800b5ac: fb02 f303 mul.w r3, r2, r3 + 800b5b0: 461a mov r2, r3 + 800b5b2: 4b3f ldr r3, [pc, #252] @ (800b6b0 ) + 800b5b4: 6c9b ldr r3, [r3, #72] @ 0x48 + 800b5b6: 085b lsrs r3, r3, #1 + 800b5b8: 441a add r2, r3 + 800b5ba: 4b3d ldr r3, [pc, #244] @ (800b6b0 ) + 800b5bc: 6c9b ldr r3, [r3, #72] @ 0x48 + 800b5be: fbb2 f3f3 udiv r3, r2, r3 + 800b5c2: 60fb str r3, [r7, #12] + + TimerSetValue( &RFWPacket.Timer, timeout ); + 800b5c4: 68f9 ldr r1, [r7, #12] + 800b5c6: 483c ldr r0, [pc, #240] @ (800b6b8 ) + 800b5c8: f002 fba6 bl 800dd18 + TimerStart( &RFWPacket.Timer ); + 800b5cc: 483a ldr r0, [pc, #232] @ (800b6b8 ) + 800b5ce: f002 fac5 bl 800db5c + 800b5d2: e015 b.n 800b600 + } + else + { + /*last chunk to send*/ + + if( RFWPacket.LongPacketRemainingBytes > bytes_loaded ) + 800b5d4: 4b36 ldr r3, [pc, #216] @ (800b6b0 ) + 800b5d6: 8e9a ldrh r2, [r3, #52] @ 0x34 + 800b5d8: 7cbb ldrb r3, [r7, #18] + 800b5da: b29b uxth r3, r3 + 800b5dc: 429a cmp r2, r3 + 800b5de: d906 bls.n 800b5ee + { + chunk_size = RFWPacket.LongPacketRemainingBytes - bytes_loaded; + 800b5e0: 4b33 ldr r3, [pc, #204] @ (800b6b0 ) + 800b5e2: 8e9b ldrh r3, [r3, #52] @ 0x34 + 800b5e4: b2da uxtb r2, r3 + 800b5e6: 7cbb ldrb r3, [r7, #18] + 800b5e8: 1ad3 subs r3, r2, r3 + 800b5ea: 75fb strb r3, [r7, #23] + 800b5ec: e002 b.n 800b5f4 + } + else/* nothing to load anymore*/ + { + chunk_size = RFWPacket.Init.CrcFieldSize; + 800b5ee: 4b30 ldr r3, [pc, #192] @ (800b6b0 ) + 800b5f0: 78db ldrb r3, [r3, #3] + 800b5f2: 75fb strb r3, [r7, #23] + } + /* crc, since it is the last chunk*/ + crc_size = RFWPacket.Init.CrcFieldSize; + 800b5f4: 4b2e ldr r3, [pc, #184] @ (800b6b0 ) + 800b5f6: 78db ldrb r3, [r3, #3] + 800b5f8: 75bb strb r3, [r7, #22] + /*no more bytes to send*/ + RFWPacket.LongPacketRemainingBytes = 0; + 800b5fa: 4b2d ldr r3, [pc, #180] @ (800b6b0 ) + 800b5fc: 2200 movs r2, #0 + 800b5fe: 869a strh r2, [r3, #52] @ 0x34 + /*no need to program another timer, Tx done will complete the Tx process*/ + } + /*get new chunk from the app*/ + RFWPacket.TxLongPacketGetNextChunkCb( &app_chunk_buffer_ptr, chunk_size - crc_size ); + 800b600: 4b2b ldr r3, [pc, #172] @ (800b6b0 ) + 800b602: 6c1b ldr r3, [r3, #64] @ 0x40 + 800b604: 7df9 ldrb r1, [r7, #23] + 800b606: 7dba ldrb r2, [r7, #22] + 800b608: 1a8a subs r2, r1, r2 + 800b60a: b2d1 uxtb r1, r2 + 800b60c: f107 0208 add.w r2, r7, #8 + 800b610: 4610 mov r0, r2 + 800b612: 4798 blx r3 + /* Copy app_chunk_buffer_ptr in ChunkBuffer Buffer*/ + RADIO_MEMCPY8( ChunkBuffer, app_chunk_buffer_ptr, chunk_size - crc_size ); + 800b614: 68b9 ldr r1, [r7, #8] + 800b616: 7dfb ldrb r3, [r7, #23] + 800b618: b29a uxth r2, r3 + 800b61a: 7dbb ldrb r3, [r7, #22] + 800b61c: b29b uxth r3, r3 + 800b61e: 1ad3 subs r3, r2, r3 + 800b620: b29b uxth r3, r3 + 800b622: 461a mov r2, r3 + 800b624: 4825 ldr r0, [pc, #148] @ (800b6bc ) + 800b626: f001 fe01 bl 800d22c + if( RFWPacket.Init.CrcEnable == 1 ) + 800b62a: 4b21 ldr r3, [pc, #132] @ (800b6b0 ) + 800b62c: 789b ldrb r3, [r3, #2] + 800b62e: 2b01 cmp r3, #1 + 800b630: d113 bne.n 800b65a + { + /* Run the crc calculation on payload length and payload*/ + RFW_CrcRun( &RFWPacket, ChunkBuffer, chunk_size - crc_size, crc_result ); + 800b632: 7dfa ldrb r2, [r7, #23] + 800b634: 7dbb ldrb r3, [r7, #22] + 800b636: 1ad3 subs r3, r2, r3 + 800b638: 461a mov r2, r3 + 800b63a: 1d3b adds r3, r7, #4 + 800b63c: 491f ldr r1, [pc, #124] @ (800b6bc ) + 800b63e: 481c ldr r0, [pc, #112] @ (800b6b0 ) + 800b640: f000 f8cb bl 800b7da + /* Append the crc result after the payload (if last chunk)*/ + RADIO_MEMCPY8( &ChunkBuffer[chunk_size - crc_size], crc_result, crc_size ); + 800b644: 7dfa ldrb r2, [r7, #23] + 800b646: 7dbb ldrb r3, [r7, #22] + 800b648: 1ad3 subs r3, r2, r3 + 800b64a: 4a1c ldr r2, [pc, #112] @ (800b6bc ) + 800b64c: 4413 add r3, r2 + 800b64e: 7dba ldrb r2, [r7, #22] + 800b650: b292 uxth r2, r2 + 800b652: 1d39 adds r1, r7, #4 + 800b654: 4618 mov r0, r3 + 800b656: f001 fde9 bl 800d22c + } + /* Run the whitening calculation on payload length, payload and crc*/ + RFW_WhiteRun( &RFWPacket, ChunkBuffer, chunk_size ); + 800b65a: 7dfb ldrb r3, [r7, #23] + 800b65c: 461a mov r2, r3 + 800b65e: 4917 ldr r1, [pc, #92] @ (800b6bc ) + 800b660: 4813 ldr r0, [pc, #76] @ (800b6b0 ) + 800b662: f000 f872 bl 800b74a + /*write next chunk*/ + SUBGRF_WriteBuffer( write_ptr, ChunkBuffer, chunk_size ); + 800b666: 7dfa ldrb r2, [r7, #23] + 800b668: 7d3b ldrb r3, [r7, #20] + 800b66a: 4914 ldr r1, [pc, #80] @ (800b6bc ) + 800b66c: 4618 mov r0, r3 + 800b66e: f7ff f8d3 bl 800a818 + + /*update end ptr*/ + SUBGRF_WriteRegister( SUBGHZ_GRTXPLDLEN, ( uint8_t )( chunk_size + write_ptr ) ); + 800b672: 7dfa ldrb r2, [r7, #23] + 800b674: 7d3b ldrb r3, [r7, #20] + 800b676: 4413 add r3, r2 + 800b678: b2db uxtb r3, r3 + 800b67a: 4619 mov r1, r3 + 800b67c: f240 60bb movw r0, #1723 @ 0x6bb + 800b680: f7ff f844 bl 800a70c + + RFW_MW_LOG( TS_ON, VLEVEL_M, "next chunk size=%d, new write ptr=%d\n\r", chunk_size + crc_size, + 800b684: 7dfa ldrb r2, [r7, #23] + 800b686: 7dbb ldrb r3, [r7, #22] + 800b688: 4413 add r3, r2 + 800b68a: 7df9 ldrb r1, [r7, #23] + 800b68c: 7dba ldrb r2, [r7, #22] + 800b68e: 440a add r2, r1 + 800b690: b2d1 uxtb r1, r2 + 800b692: 7d3a ldrb r2, [r7, #20] + 800b694: 440a add r2, r1 + 800b696: b2d2 uxtb r2, r2 + 800b698: 9201 str r2, [sp, #4] + 800b69a: 9300 str r3, [sp, #0] + 800b69c: 4b08 ldr r3, [pc, #32] @ (800b6c0 ) + 800b69e: 2201 movs r2, #1 + 800b6a0: 2100 movs r1, #0 + 800b6a2: 2002 movs r0, #2 + 800b6a4: f002 fcc0 bl 800e028 + ( uint8_t )( chunk_size + crc_size + write_ptr ) ); +} + 800b6a8: bf00 nop + 800b6aa: 371c adds r7, #28 + 800b6ac: 46bd mov sp, r7 + 800b6ae: bd90 pop {r4, r7, pc} + 800b6b0: 2000039c .word 0x2000039c + 800b6b4: 0800f1b4 .word 0x0800f1b4 + 800b6b8: 200003b8 .word 0x200003b8 + 800b6bc: 200003f0 .word 0x200003f0 + 800b6c0: 0800f208 .word 0x0800f208 + +0800b6c4 : +#endif /* RFW_LONGPACKET_ENABLE == 1 */ + +#if (RFW_ENABLE == 1 ) +static void RFW_WhiteInitState( RFwInit_t *Init, uint16_t WhiteSeed ) +{ + 800b6c4: b480 push {r7} + 800b6c6: b083 sub sp, #12 + 800b6c8: af00 add r7, sp, #0 + 800b6ca: 6078 str r0, [r7, #4] + 800b6cc: 460b mov r3, r1 + 800b6ce: 807b strh r3, [r7, #2] + Init->WhiteSeed = WhiteSeed; + 800b6d0: 687b ldr r3, [r7, #4] + 800b6d2: 887a ldrh r2, [r7, #2] + 800b6d4: 815a strh r2, [r3, #10] +} + 800b6d6: bf00 nop + 800b6d8: 370c adds r7, #12 + 800b6da: 46bd mov sp, r7 + 800b6dc: bc80 pop {r7} + 800b6de: 4770 bx lr + +0800b6e0 : + +static void RFW_WhiteSetState( RadioFw_t *RFWPacket ) +{ + 800b6e0: b480 push {r7} + 800b6e2: b083 sub sp, #12 + 800b6e4: af00 add r7, sp, #0 + 800b6e6: 6078 str r0, [r7, #4] + RFWPacket->WhiteLfsrState = RFWPacket->Init.WhiteSeed; + 800b6e8: 687b ldr r3, [r7, #4] + 800b6ea: 895a ldrh r2, [r3, #10] + 800b6ec: 687b ldr r3, [r7, #4] + 800b6ee: 82da strh r2, [r3, #22] +} + 800b6f0: bf00 nop + 800b6f2: 370c adds r7, #12 + 800b6f4: 46bd mov sp, r7 + 800b6f6: bc80 pop {r7} + 800b6f8: 4770 bx lr + +0800b6fa : + +static void RFW_CrcInitState( RFwInit_t *Init, const uint16_t CrcPolynomial, const uint16_t CrcSeed, + const RADIO_FSK_CrcTypes_t CrcType ) +{ + 800b6fa: b480 push {r7} + 800b6fc: b085 sub sp, #20 + 800b6fe: af00 add r7, sp, #0 + 800b700: 60f8 str r0, [r7, #12] + 800b702: 4608 mov r0, r1 + 800b704: 4611 mov r1, r2 + 800b706: 461a mov r2, r3 + 800b708: 4603 mov r3, r0 + 800b70a: 817b strh r3, [r7, #10] + 800b70c: 460b mov r3, r1 + 800b70e: 813b strh r3, [r7, #8] + 800b710: 4613 mov r3, r2 + 800b712: 71fb strb r3, [r7, #7] + Init->CrcPolynomial = CrcPolynomial; + 800b714: 68fb ldr r3, [r7, #12] + 800b716: 897a ldrh r2, [r7, #10] + 800b718: 809a strh r2, [r3, #4] + Init->CrcSeed = CrcSeed; + 800b71a: 68fb ldr r3, [r7, #12] + 800b71c: 893a ldrh r2, [r7, #8] + 800b71e: 80da strh r2, [r3, #6] + Init->CrcType = CrcType; + 800b720: 68fb ldr r3, [r7, #12] + 800b722: 79fa ldrb r2, [r7, #7] + 800b724: 721a strb r2, [r3, #8] +} + 800b726: bf00 nop + 800b728: 3714 adds r7, #20 + 800b72a: 46bd mov sp, r7 + 800b72c: bc80 pop {r7} + 800b72e: 4770 bx lr + +0800b730 : + +static void RFW_CrcSetState( RadioFw_t *RFWPacket ) +{ + 800b730: b480 push {r7} + 800b732: b083 sub sp, #12 + 800b734: af00 add r7, sp, #0 + 800b736: 6078 str r0, [r7, #4] + RFWPacket->CrcLfsrState = RFWPacket->Init.CrcSeed; + 800b738: 687b ldr r3, [r7, #4] + 800b73a: 88da ldrh r2, [r3, #6] + 800b73c: 687b ldr r3, [r7, #4] + 800b73e: 829a strh r2, [r3, #20] +} + 800b740: bf00 nop + 800b742: 370c adds r7, #12 + 800b744: 46bd mov sp, r7 + 800b746: bc80 pop {r7} + 800b748: 4770 bx lr + +0800b74a : + +static void RFW_WhiteRun( RadioFw_t *RFWPacket, uint8_t *Payload, uint32_t Size ) +{ + 800b74a: b480 push {r7} + 800b74c: b089 sub sp, #36 @ 0x24 + 800b74e: af00 add r7, sp, #0 + 800b750: 60f8 str r0, [r7, #12] + 800b752: 60b9 str r1, [r7, #8] + 800b754: 607a str r2, [r7, #4] + /*run the whitening algo on Size bytes*/ + uint16_t ibmwhite_state = RFWPacket->WhiteLfsrState; + 800b756: 68fb ldr r3, [r7, #12] + 800b758: 8adb ldrh r3, [r3, #22] + 800b75a: 83fb strh r3, [r7, #30] + for( int32_t i = 0; i < Size; i++ ) + 800b75c: 2300 movs r3, #0 + 800b75e: 61bb str r3, [r7, #24] + 800b760: e02f b.n 800b7c2 + { + Payload[i] ^= ibmwhite_state & 0xFF; + 800b762: 69bb ldr r3, [r7, #24] + 800b764: 68ba ldr r2, [r7, #8] + 800b766: 4413 add r3, r2 + 800b768: 781b ldrb r3, [r3, #0] + 800b76a: b25a sxtb r2, r3 + 800b76c: 8bfb ldrh r3, [r7, #30] + 800b76e: b25b sxtb r3, r3 + 800b770: 4053 eors r3, r2 + 800b772: b259 sxtb r1, r3 + 800b774: 69bb ldr r3, [r7, #24] + 800b776: 68ba ldr r2, [r7, #8] + 800b778: 4413 add r3, r2 + 800b77a: b2ca uxtb r2, r1 + 800b77c: 701a strb r2, [r3, #0] + for( int32_t j = 0; j < 8; j++ ) + 800b77e: 2300 movs r3, #0 + 800b780: 617b str r3, [r7, #20] + 800b782: e018 b.n 800b7b6 + { + uint8_t msb = ( ( ibmwhite_state >> 5 ) & 0x1 ) ^ ( ( ibmwhite_state >> 0 ) & 0x1 ); + 800b784: 8bfb ldrh r3, [r7, #30] + 800b786: 095b lsrs r3, r3, #5 + 800b788: b29b uxth r3, r3 + 800b78a: b2da uxtb r2, r3 + 800b78c: 8bfb ldrh r3, [r7, #30] + 800b78e: b2db uxtb r3, r3 + 800b790: 4053 eors r3, r2 + 800b792: b2db uxtb r3, r3 + 800b794: f003 0301 and.w r3, r3, #1 + 800b798: 74fb strb r3, [r7, #19] + ibmwhite_state = ( ( msb << 8 ) | ( ibmwhite_state >> 1 ) ); + 800b79a: 7cfb ldrb r3, [r7, #19] + 800b79c: b21b sxth r3, r3 + 800b79e: 021b lsls r3, r3, #8 + 800b7a0: b21a sxth r2, r3 + 800b7a2: 8bfb ldrh r3, [r7, #30] + 800b7a4: 085b lsrs r3, r3, #1 + 800b7a6: b29b uxth r3, r3 + 800b7a8: b21b sxth r3, r3 + 800b7aa: 4313 orrs r3, r2 + 800b7ac: b21b sxth r3, r3 + 800b7ae: 83fb strh r3, [r7, #30] + for( int32_t j = 0; j < 8; j++ ) + 800b7b0: 697b ldr r3, [r7, #20] + 800b7b2: 3301 adds r3, #1 + 800b7b4: 617b str r3, [r7, #20] + 800b7b6: 697b ldr r3, [r7, #20] + 800b7b8: 2b07 cmp r3, #7 + 800b7ba: dde3 ble.n 800b784 + for( int32_t i = 0; i < Size; i++ ) + 800b7bc: 69bb ldr r3, [r7, #24] + 800b7be: 3301 adds r3, #1 + 800b7c0: 61bb str r3, [r7, #24] + 800b7c2: 69bb ldr r3, [r7, #24] + 800b7c4: 687a ldr r2, [r7, #4] + 800b7c6: 429a cmp r2, r3 + 800b7c8: d8cb bhi.n 800b762 + } + } + RFWPacket->WhiteLfsrState = ibmwhite_state; + 800b7ca: 68fb ldr r3, [r7, #12] + 800b7cc: 8bfa ldrh r2, [r7, #30] + 800b7ce: 82da strh r2, [r3, #22] +} + 800b7d0: bf00 nop + 800b7d2: 3724 adds r7, #36 @ 0x24 + 800b7d4: 46bd mov sp, r7 + 800b7d6: bc80 pop {r7} + 800b7d8: 4770 bx lr + +0800b7da : + +static int32_t RFW_CrcRun( RadioFw_t *const RFWPacket, const uint8_t *Payload, const uint32_t Size, + uint8_t CrcResult[2] ) +{ + 800b7da: b580 push {r7, lr} + 800b7dc: b088 sub sp, #32 + 800b7de: af00 add r7, sp, #0 + 800b7e0: 60f8 str r0, [r7, #12] + 800b7e2: 60b9 str r1, [r7, #8] + 800b7e4: 607a str r2, [r7, #4] + 800b7e6: 603b str r3, [r7, #0] + int32_t status = 0; + 800b7e8: 2300 movs r3, #0 + 800b7ea: 617b str r3, [r7, #20] + int32_t i = 0; + 800b7ec: 2300 movs r3, #0 + 800b7ee: 61fb str r3, [r7, #28] + uint16_t polynomial = RFWPacket->Init.CrcPolynomial; + 800b7f0: 68fb ldr r3, [r7, #12] + 800b7f2: 889b ldrh r3, [r3, #4] + 800b7f4: 827b strh r3, [r7, #18] + /* Restore state from previous chunk*/ + uint16_t crc = RFWPacket->CrcLfsrState; + 800b7f6: 68fb ldr r3, [r7, #12] + 800b7f8: 8a9b ldrh r3, [r3, #20] + 800b7fa: 837b strh r3, [r7, #26] + for( i = 0; i < Size; i++ ) + 800b7fc: 2300 movs r3, #0 + 800b7fe: 61fb str r3, [r7, #28] + 800b800: e00d b.n 800b81e + { + crc = RFW_CrcRun1Byte( crc, Payload[i], polynomial ); + 800b802: 69fb ldr r3, [r7, #28] + 800b804: 68ba ldr r2, [r7, #8] + 800b806: 4413 add r3, r2 + 800b808: 7819 ldrb r1, [r3, #0] + 800b80a: 8a7a ldrh r2, [r7, #18] + 800b80c: 8b7b ldrh r3, [r7, #26] + 800b80e: 4618 mov r0, r3 + 800b810: f000 f82f bl 800b872 + 800b814: 4603 mov r3, r0 + 800b816: 837b strh r3, [r7, #26] + for( i = 0; i < Size; i++ ) + 800b818: 69fb ldr r3, [r7, #28] + 800b81a: 3301 adds r3, #1 + 800b81c: 61fb str r3, [r7, #28] + 800b81e: 69fb ldr r3, [r7, #28] + 800b820: 687a ldr r2, [r7, #4] + 800b822: 429a cmp r2, r3 + 800b824: d8ed bhi.n 800b802 + } + /*Save state for next chunk*/ + RFWPacket->CrcLfsrState = crc; + 800b826: 68fb ldr r3, [r7, #12] + 800b828: 8b7a ldrh r2, [r7, #26] + 800b82a: 829a strh r2, [r3, #20] + + if( RFWPacket->Init.CrcType == RADIO_FSK_CRC_2_BYTES_IBM ) + 800b82c: 68fb ldr r3, [r7, #12] + 800b82e: 7a1b ldrb r3, [r3, #8] + 800b830: 2bf1 cmp r3, #241 @ 0xf1 + 800b832: d10b bne.n 800b84c + { + CrcResult[1] = crc & 0xFF; + 800b834: 683b ldr r3, [r7, #0] + 800b836: 3301 adds r3, #1 + 800b838: 8b7a ldrh r2, [r7, #26] + 800b83a: b2d2 uxtb r2, r2 + 800b83c: 701a strb r2, [r3, #0] + CrcResult[0] = crc >> 8; + 800b83e: 8b7b ldrh r3, [r7, #26] + 800b840: 0a1b lsrs r3, r3, #8 + 800b842: b29b uxth r3, r3 + 800b844: b2da uxtb r2, r3 + 800b846: 683b ldr r3, [r7, #0] + 800b848: 701a strb r2, [r3, #0] + 800b84a: e00d b.n 800b868 + } + else + { + crc = ~crc ; + 800b84c: 8b7b ldrh r3, [r7, #26] + 800b84e: 43db mvns r3, r3 + 800b850: 837b strh r3, [r7, #26] + CrcResult[1] = crc & 0xFF; + 800b852: 683b ldr r3, [r7, #0] + 800b854: 3301 adds r3, #1 + 800b856: 8b7a ldrh r2, [r7, #26] + 800b858: b2d2 uxtb r2, r2 + 800b85a: 701a strb r2, [r3, #0] + CrcResult[0] = crc >> 8; + 800b85c: 8b7b ldrh r3, [r7, #26] + 800b85e: 0a1b lsrs r3, r3, #8 + 800b860: b29b uxth r3, r3 + 800b862: b2da uxtb r2, r3 + 800b864: 683b ldr r3, [r7, #0] + 800b866: 701a strb r2, [r3, #0] + } + return status; + 800b868: 697b ldr r3, [r7, #20] +} + 800b86a: 4618 mov r0, r3 + 800b86c: 3720 adds r7, #32 + 800b86e: 46bd mov sp, r7 + 800b870: bd80 pop {r7, pc} + +0800b872 : + +uint16_t RFW_CrcRun1Byte( uint16_t Crc, uint8_t DataByte, uint16_t Polynomial ) +{ + 800b872: b480 push {r7} + 800b874: b085 sub sp, #20 + 800b876: af00 add r7, sp, #0 + 800b878: 4603 mov r3, r0 + 800b87a: 80fb strh r3, [r7, #6] + 800b87c: 460b mov r3, r1 + 800b87e: 717b strb r3, [r7, #5] + 800b880: 4613 mov r3, r2 + 800b882: 807b strh r3, [r7, #2] + uint8_t i; + for( i = 0; i < 8; i++ ) + 800b884: 2300 movs r3, #0 + 800b886: 73fb strb r3, [r7, #15] + 800b888: e018 b.n 800b8bc + { + if( ( ( ( Crc & 0x8000 ) >> 8 ) ^ ( DataByte & 0x80 ) ) != 0 ) + 800b88a: 88fb ldrh r3, [r7, #6] + 800b88c: 121a asrs r2, r3, #8 + 800b88e: 797b ldrb r3, [r7, #5] + 800b890: 4053 eors r3, r2 + 800b892: f003 0380 and.w r3, r3, #128 @ 0x80 + 800b896: 2b00 cmp r3, #0 + 800b898: d007 beq.n 800b8aa + { + Crc <<= 1; + 800b89a: 88fb ldrh r3, [r7, #6] + 800b89c: 005b lsls r3, r3, #1 + 800b89e: 80fb strh r3, [r7, #6] + Crc ^= Polynomial; + 800b8a0: 88fa ldrh r2, [r7, #6] + 800b8a2: 887b ldrh r3, [r7, #2] + 800b8a4: 4053 eors r3, r2 + 800b8a6: 80fb strh r3, [r7, #6] + 800b8a8: e002 b.n 800b8b0 + } + else + { + Crc <<= 1; + 800b8aa: 88fb ldrh r3, [r7, #6] + 800b8ac: 005b lsls r3, r3, #1 + 800b8ae: 80fb strh r3, [r7, #6] + } + DataByte <<= 1; + 800b8b0: 797b ldrb r3, [r7, #5] + 800b8b2: 005b lsls r3, r3, #1 + 800b8b4: 717b strb r3, [r7, #5] + for( i = 0; i < 8; i++ ) + 800b8b6: 7bfb ldrb r3, [r7, #15] + 800b8b8: 3301 adds r3, #1 + 800b8ba: 73fb strb r3, [r7, #15] + 800b8bc: 7bfb ldrb r3, [r7, #15] + 800b8be: 2b07 cmp r3, #7 + 800b8c0: d9e3 bls.n 800b88a + } + return Crc; + 800b8c2: 88fb ldrh r3, [r7, #6] +} + 800b8c4: 4618 mov r0, r3 + 800b8c6: 3714 adds r7, #20 + 800b8c8: 46bd mov sp, r7 + 800b8ca: bc80 pop {r7} + 800b8cc: 4770 bx lr + ... + +0800b8d0 : + +static int32_t RFW_PollRxBytes( uint32_t bytes ) +{ + 800b8d0: b580 push {r7, lr} + 800b8d2: b086 sub sp, #24 + 800b8d4: af00 add r7, sp, #0 + 800b8d6: 6078 str r0, [r7, #4] + uint32_t now = TimerGetCurrentTime( ); + 800b8d8: f002 fac8 bl 800de6c + 800b8dc: 6138 str r0, [r7, #16] + uint8_t reg_buff_ptr_ref = SUBGRF_ReadRegister( SUBGHZ_RXADRPTR ); + 800b8de: f640 0003 movw r0, #2051 @ 0x803 + 800b8e2: f7fe ff35 bl 800a750 + 800b8e6: 4603 mov r3, r0 + 800b8e8: 73fb strb r3, [r7, #15] + uint8_t reg_buff_ptr = reg_buff_ptr_ref; + 800b8ea: 7bfb ldrb r3, [r7, #15] + 800b8ec: 75fb strb r3, [r7, #23] + uint32_t timeout = DIVC( bytes * 8 * 1000, RFWPacket.BitRate ); + 800b8ee: 687b ldr r3, [r7, #4] + 800b8f0: f44f 52fa mov.w r2, #8000 @ 0x1f40 + 800b8f4: fb03 f202 mul.w r2, r3, r2 + 800b8f8: 4b12 ldr r3, [pc, #72] @ (800b944 ) + 800b8fa: 6c9b ldr r3, [r3, #72] @ 0x48 + 800b8fc: 4413 add r3, r2 + 800b8fe: 1e5a subs r2, r3, #1 + 800b900: 4b10 ldr r3, [pc, #64] @ (800b944 ) + 800b902: 6c9b ldr r3, [r3, #72] @ 0x48 + 800b904: fbb2 f3f3 udiv r3, r2, r3 + 800b908: 60bb str r3, [r7, #8] + /* Wait that packet length is received */ + while( ( reg_buff_ptr - reg_buff_ptr_ref ) < bytes ) + 800b90a: e00f b.n 800b92c + { + /*reading rx address pointer*/ + reg_buff_ptr = SUBGRF_ReadRegister( SUBGHZ_RXADRPTR ); + 800b90c: f640 0003 movw r0, #2051 @ 0x803 + 800b910: f7fe ff1e bl 800a750 + 800b914: 4603 mov r3, r0 + 800b916: 75fb strb r3, [r7, #23] + if( TimerGetElapsedTime( now ) > timeout ) + 800b918: 6938 ldr r0, [r7, #16] + 800b91a: f002 fab9 bl 800de90 + 800b91e: 4602 mov r2, r0 + 800b920: 68bb ldr r3, [r7, #8] + 800b922: 4293 cmp r3, r2 + 800b924: d202 bcs.n 800b92c + { + /*timeout*/ + return -1; + 800b926: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff + 800b92a: e007 b.n 800b93c + while( ( reg_buff_ptr - reg_buff_ptr_ref ) < bytes ) + 800b92c: 7dfa ldrb r2, [r7, #23] + 800b92e: 7bfb ldrb r3, [r7, #15] + 800b930: 1ad3 subs r3, r2, r3 + 800b932: 461a mov r2, r3 + 800b934: 687b ldr r3, [r7, #4] + 800b936: 4293 cmp r3, r2 + 800b938: d8e8 bhi.n 800b90c + } + } + return 0; + 800b93a: 2300 movs r3, #0 +} + 800b93c: 4618 mov r0, r3 + 800b93e: 3718 adds r7, #24 + 800b940: 46bd mov sp, r7 + 800b942: bd80 pop {r7, pc} + 800b944: 2000039c .word 0x2000039c + +0800b948 : + +static int32_t RFW_GetPacketLength( uint16_t *PayloadLength ) +{ + 800b948: b580 push {r7, lr} + 800b94a: b086 sub sp, #24 + 800b94c: af02 add r7, sp, #8 + 800b94e: 6078 str r0, [r7, #4] + if( 0UL != RFW_PollRxBytes( RFWPacket.Init.PayloadLengthFieldSize ) ) + 800b950: 4b25 ldr r3, [pc, #148] @ (800b9e8 ) + 800b952: 785b ldrb r3, [r3, #1] + 800b954: 4618 mov r0, r3 + 800b956: f7ff ffbb bl 800b8d0 + 800b95a: 4603 mov r3, r0 + 800b95c: 2b00 cmp r3, #0 + 800b95e: d002 beq.n 800b966 + { + return -1; + 800b960: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff + 800b964: e03b b.n 800b9de + } + /* Get buffer from Radio*/ + SUBGRF_ReadBuffer( 0, ChunkBuffer, RFWPacket.Init.PayloadLengthFieldSize ); + 800b966: 4b20 ldr r3, [pc, #128] @ (800b9e8 ) + 800b968: 785b ldrb r3, [r3, #1] + 800b96a: 461a mov r2, r3 + 800b96c: 491f ldr r1, [pc, #124] @ (800b9ec ) + 800b96e: 2000 movs r0, #0 + 800b970: f7fe ff74 bl 800a85c + /* De-whiten packet length*/ + RFW_WhiteRun( &RFWPacket, ChunkBuffer, RFWPacket.Init.PayloadLengthFieldSize ); + 800b974: 4b1c ldr r3, [pc, #112] @ (800b9e8 ) + 800b976: 785b ldrb r3, [r3, #1] + 800b978: 461a mov r2, r3 + 800b97a: 491c ldr r1, [pc, #112] @ (800b9ec ) + 800b97c: 481a ldr r0, [pc, #104] @ (800b9e8 ) + 800b97e: f7ff fee4 bl 800b74a + /*do crc 1st calculation packetLengthField and store intermediate result */ + if( RFWPacket.Init.CrcEnable == 1 ) + 800b982: 4b19 ldr r3, [pc, #100] @ (800b9e8 ) + 800b984: 789b ldrb r3, [r3, #2] + 800b986: 2b01 cmp r3, #1 + 800b988: d108 bne.n 800b99c + { + /*run Crc algo on payloadLengthField*/ + uint8_t crc_dummy[2]; + RFW_CrcRun( &RFWPacket, ChunkBuffer, RFWPacket.Init.PayloadLengthFieldSize, crc_dummy ); + 800b98a: 4b17 ldr r3, [pc, #92] @ (800b9e8 ) + 800b98c: 785b ldrb r3, [r3, #1] + 800b98e: 461a mov r2, r3 + 800b990: f107 030c add.w r3, r7, #12 + 800b994: 4915 ldr r1, [pc, #84] @ (800b9ec ) + 800b996: 4814 ldr r0, [pc, #80] @ (800b9e8 ) + 800b998: f7ff ff1f bl 800b7da + } + if( RFWPacket.Init.PayloadLengthFieldSize == 1 ) + 800b99c: 4b12 ldr r3, [pc, #72] @ (800b9e8 ) + 800b99e: 785b ldrb r3, [r3, #1] + 800b9a0: 2b01 cmp r3, #1 + 800b9a2: d105 bne.n 800b9b0 + { + *PayloadLength = ( uint16_t ) ChunkBuffer[0]; + 800b9a4: 4b11 ldr r3, [pc, #68] @ (800b9ec ) + 800b9a6: 781b ldrb r3, [r3, #0] + 800b9a8: 461a mov r2, r3 + 800b9aa: 687b ldr r3, [r7, #4] + 800b9ac: 801a strh r2, [r3, #0] + 800b9ae: e00c b.n 800b9ca + } + else + { + /*packet length is 2 bytes*/ + *PayloadLength = ( ( ( uint16_t ) ChunkBuffer[0] ) << 8 ) | ChunkBuffer[1]; + 800b9b0: 4b0e ldr r3, [pc, #56] @ (800b9ec ) + 800b9b2: 781b ldrb r3, [r3, #0] + 800b9b4: b21b sxth r3, r3 + 800b9b6: 021b lsls r3, r3, #8 + 800b9b8: b21a sxth r2, r3 + 800b9ba: 4b0c ldr r3, [pc, #48] @ (800b9ec ) + 800b9bc: 785b ldrb r3, [r3, #1] + 800b9be: b21b sxth r3, r3 + 800b9c0: 4313 orrs r3, r2 + 800b9c2: b21b sxth r3, r3 + 800b9c4: b29a uxth r2, r3 + 800b9c6: 687b ldr r3, [r7, #4] + 800b9c8: 801a strh r2, [r3, #0] + } + RFW_MW_LOG( TS_ON, VLEVEL_M, "PayloadLength=%d,\r\n", *PayloadLength ); + 800b9ca: 687b ldr r3, [r7, #4] + 800b9cc: 881b ldrh r3, [r3, #0] + 800b9ce: 9300 str r3, [sp, #0] + 800b9d0: 4b07 ldr r3, [pc, #28] @ (800b9f0 ) + 800b9d2: 2201 movs r2, #1 + 800b9d4: 2100 movs r1, #0 + 800b9d6: 2002 movs r0, #2 + 800b9d8: f002 fb26 bl 800e028 + return 0; + 800b9dc: 2300 movs r3, #0 +} + 800b9de: 4618 mov r0, r3 + 800b9e0: 3710 adds r7, #16 + 800b9e2: 46bd mov sp, r7 + 800b9e4: bd80 pop {r7, pc} + 800b9e6: bf00 nop + 800b9e8: 2000039c .word 0x2000039c + 800b9ec: 200003f0 .word 0x200003f0 + 800b9f0: 0800f230 .word 0x0800f230 + +0800b9f4 : + +static void RFW_GetPayloadTimerEvent( void *context ) +{ + 800b9f4: b580 push {r7, lr} + 800b9f6: b082 sub sp, #8 + 800b9f8: af00 add r7, sp, #0 + 800b9fa: 6078 str r0, [r7, #4] + RFW_GET_PAYLOAD_PROCESS(); + 800b9fc: f000 f804 bl 800ba08 +} + 800ba00: bf00 nop + 800ba02: 3708 adds r7, #8 + 800ba04: 46bd mov sp, r7 + 800ba06: bd80 pop {r7, pc} + +0800ba08 : + +static void RFW_GetPayloadProcess( void ) +{ + 800ba08: b580 push {r7, lr} + 800ba0a: b086 sub sp, #24 + 800ba0c: af04 add r7, sp, #16 + /*long packet mode*/ + uint8_t read_ptr = SUBGRF_ReadRegister( SUBGHZ_RXADRPTR ); + 800ba0e: f640 0003 movw r0, #2051 @ 0x803 + 800ba12: f7fe fe9d bl 800a750 + 800ba16: 4603 mov r3, r0 + 800ba18: 70fb strb r3, [r7, #3] + uint8_t size = read_ptr - RFWPacket.RadioBufferOffset; + 800ba1a: 4b83 ldr r3, [pc, #524] @ (800bc28 ) + 800ba1c: f893 3036 ldrb.w r3, [r3, #54] @ 0x36 + 800ba20: 78fa ldrb r2, [r7, #3] + 800ba22: 1ad3 subs r3, r2, r3 + 800ba24: 70bb strb r3, [r7, #2] + uint32_t Timeout; + /*check remaining size*/ + if( RFWPacket.LongPacketRemainingBytes > size ) + 800ba26: 4b80 ldr r3, [pc, #512] @ (800bc28 ) + 800ba28: 8e9a ldrh r2, [r3, #52] @ 0x34 + 800ba2a: 78bb ldrb r3, [r7, #2] + 800ba2c: b29b uxth r3, r3 + 800ba2e: 429a cmp r2, r3 + 800ba30: f240 80cd bls.w 800bbce + { + /* update LongPacketRemainingBytes*/ + RFWPacket.LongPacketRemainingBytes -= size; + 800ba34: 4b7c ldr r3, [pc, #496] @ (800bc28 ) + 800ba36: 8e9a ldrh r2, [r3, #52] @ 0x34 + 800ba38: 78bb ldrb r3, [r7, #2] + 800ba3a: b29b uxth r3, r3 + 800ba3c: 1ad3 subs r3, r2, r3 + 800ba3e: b29a uxth r2, r3 + 800ba40: 4b79 ldr r3, [pc, #484] @ (800bc28 ) + 800ba42: 869a strh r2, [r3, #52] @ 0x34 + /*intermediate chunk*/ + RFW_MW_LOG( TS_ON, VLEVEL_M, "RxTxPldLen=0x%02X,\r\n", SUBGRF_ReadRegister( SUBGHZ_GRTXPLDLEN ) ); + 800ba44: f240 60bb movw r0, #1723 @ 0x6bb + 800ba48: f7fe fe82 bl 800a750 + 800ba4c: 4603 mov r3, r0 + 800ba4e: 9300 str r3, [sp, #0] + 800ba50: 4b76 ldr r3, [pc, #472] @ (800bc2c ) + 800ba52: 2201 movs r2, #1 + 800ba54: 2100 movs r1, #0 + 800ba56: 2002 movs r0, #2 + 800ba58: f002 fae6 bl 800e028 + RFW_MW_LOG( TS_ON, VLEVEL_M, "RxAddrPtr=0x%02X,\r\n", read_ptr ); + 800ba5c: 78fb ldrb r3, [r7, #3] + 800ba5e: 9300 str r3, [sp, #0] + 800ba60: 4b73 ldr r3, [pc, #460] @ (800bc30 ) + 800ba62: 2201 movs r2, #1 + 800ba64: 2100 movs r1, #0 + 800ba66: 2002 movs r0, #2 + 800ba68: f002 fade bl 800e028 + RFW_MW_LOG( TS_ON, VLEVEL_M, "offset= %d, size=%d, remaining=%d,\r\n", RFWPacket.RadioBufferOffset, size, + 800ba6c: 4b6e ldr r3, [pc, #440] @ (800bc28 ) + 800ba6e: f893 3036 ldrb.w r3, [r3, #54] @ 0x36 + 800ba72: 4619 mov r1, r3 + 800ba74: 78bb ldrb r3, [r7, #2] + 800ba76: 4a6c ldr r2, [pc, #432] @ (800bc28 ) + 800ba78: 8e92 ldrh r2, [r2, #52] @ 0x34 + 800ba7a: 9202 str r2, [sp, #8] + 800ba7c: 9301 str r3, [sp, #4] + 800ba7e: 9100 str r1, [sp, #0] + 800ba80: 4b6c ldr r3, [pc, #432] @ (800bc34 ) + 800ba82: 2201 movs r2, #1 + 800ba84: 2100 movs r1, #0 + 800ba86: 2002 movs r0, #2 + 800ba88: f002 face bl 800e028 + RFWPacket.LongPacketRemainingBytes ); + /*update pld length so that not reached*/ + SUBGRF_WriteRegister( SUBGHZ_GRTXPLDLEN, read_ptr - 1 ); + 800ba8c: 78fb ldrb r3, [r7, #3] + 800ba8e: 3b01 subs r3, #1 + 800ba90: b2db uxtb r3, r3 + 800ba92: 4619 mov r1, r3 + 800ba94: f240 60bb movw r0, #1723 @ 0x6bb + 800ba98: f7fe fe38 bl 800a70c + /* read data from radio*/ + SUBGRF_ReadBuffer( RFWPacket.RadioBufferOffset, ChunkBuffer, size ); + 800ba9c: 4b62 ldr r3, [pc, #392] @ (800bc28 ) + 800ba9e: f893 3036 ldrb.w r3, [r3, #54] @ 0x36 + 800baa2: 78ba ldrb r2, [r7, #2] + 800baa4: 4964 ldr r1, [pc, #400] @ (800bc38 ) + 800baa6: 4618 mov r0, r3 + 800baa8: f7fe fed8 bl 800a85c + /* update buffer Offset, with intentional wrap around*/ + RFWPacket.RadioBufferOffset += size; + 800baac: 4b5e ldr r3, [pc, #376] @ (800bc28 ) + 800baae: f893 2036 ldrb.w r2, [r3, #54] @ 0x36 + 800bab2: 78bb ldrb r3, [r7, #2] + 800bab4: 4413 add r3, r2 + 800bab6: b2da uxtb r2, r3 + 800bab8: 4b5b ldr r3, [pc, #364] @ (800bc28 ) + 800baba: f883 2036 strb.w r2, [r3, #54] @ 0x36 + /*Run the de-whitening on current chunk*/ + RFW_WhiteRun( &RFWPacket, ChunkBuffer, size ); + 800babe: 78bb ldrb r3, [r7, #2] + 800bac0: 461a mov r2, r3 + 800bac2: 495d ldr r1, [pc, #372] @ (800bc38 ) + 800bac4: 4858 ldr r0, [pc, #352] @ (800bc28 ) + 800bac6: f7ff fe40 bl 800b74a + if( RFWPacket.Init.CrcEnable == 1 ) + 800baca: 4b57 ldr r3, [pc, #348] @ (800bc28 ) + 800bacc: 789b ldrb r3, [r3, #2] + 800bace: 2b01 cmp r3, #1 + 800bad0: d105 bne.n 800bade + { + /*run Crc algo on partial chunk*/ + uint8_t crc_dummy[2]; + RFW_CrcRun( &RFWPacket, ChunkBuffer, size, crc_dummy ); + 800bad2: 78ba ldrb r2, [r7, #2] + 800bad4: 463b mov r3, r7 + 800bad6: 4958 ldr r1, [pc, #352] @ (800bc38 ) + 800bad8: 4853 ldr r0, [pc, #332] @ (800bc28 ) + 800bada: f7ff fe7e bl 800b7da + } + + if( RFWPacket.LongPacketModeEnable == 1 ) + 800bade: 4b52 ldr r3, [pc, #328] @ (800bc28 ) + 800bae0: 7e9b ldrb r3, [r3, #26] + 800bae2: 2b01 cmp r3, #1 + 800bae4: d106 bne.n 800baf4 + { + /*report rx data chunk to application*/ + RFWPacket.RxLongPacketStoreChunkCb( ChunkBuffer, size ); + 800bae6: 4b50 ldr r3, [pc, #320] @ (800bc28 ) + 800bae8: 6bdb ldr r3, [r3, #60] @ 0x3c + 800baea: 78ba ldrb r2, [r7, #2] + 800baec: 4611 mov r1, r2 + 800baee: 4852 ldr r0, [pc, #328] @ (800bc38 ) + 800baf0: 4798 blx r3 + 800baf2: e02b b.n 800bb4c + } + else + { + if( RFWPacket.RxPayloadOffset += size < RADIO_BUF_SIZE ) + 800baf4: 4b4c ldr r3, [pc, #304] @ (800bc28 ) + 800baf6: 8f1b ldrh r3, [r3, #56] @ 0x38 + 800baf8: 78ba ldrb r2, [r7, #2] + 800bafa: 2aff cmp r2, #255 @ 0xff + 800bafc: bf14 ite ne + 800bafe: 2201 movne r2, #1 + 800bb00: 2200 moveq r2, #0 + 800bb02: b2d2 uxtb r2, r2 + 800bb04: 4413 add r3, r2 + 800bb06: b29a uxth r2, r3 + 800bb08: 4b47 ldr r3, [pc, #284] @ (800bc28 ) + 800bb0a: 871a strh r2, [r3, #56] @ 0x38 + 800bb0c: 4b46 ldr r3, [pc, #280] @ (800bc28 ) + 800bb0e: 8f1b ldrh r3, [r3, #56] @ 0x38 + 800bb10: 2b00 cmp r3, #0 + 800bb12: d013 beq.n 800bb3c + { + RADIO_MEMCPY8( &RxBuffer[RFWPacket.RxPayloadOffset], ChunkBuffer, size ); + 800bb14: 4b44 ldr r3, [pc, #272] @ (800bc28 ) + 800bb16: 8f1b ldrh r3, [r3, #56] @ 0x38 + 800bb18: 461a mov r2, r3 + 800bb1a: 4b48 ldr r3, [pc, #288] @ (800bc3c ) + 800bb1c: 4413 add r3, r2 + 800bb1e: 78ba ldrb r2, [r7, #2] + 800bb20: b292 uxth r2, r2 + 800bb22: 4945 ldr r1, [pc, #276] @ (800bc38 ) + 800bb24: 4618 mov r0, r3 + 800bb26: f001 fb81 bl 800d22c + RFWPacket.RxPayloadOffset += size; + 800bb2a: 4b3f ldr r3, [pc, #252] @ (800bc28 ) + 800bb2c: 8f1a ldrh r2, [r3, #56] @ 0x38 + 800bb2e: 78bb ldrb r3, [r7, #2] + 800bb30: b29b uxth r3, r3 + 800bb32: 4413 add r3, r2 + 800bb34: b29a uxth r2, r3 + 800bb36: 4b3c ldr r3, [pc, #240] @ (800bc28 ) + 800bb38: 871a strh r2, [r3, #56] @ 0x38 + 800bb3a: e007 b.n 800bb4c + } + else + { + /*stop the radio*/ + SUBGRF_SetStandby( STDBY_RC ); + 800bb3c: 2000 movs r0, #0 + 800bb3e: f7fe f861 bl 8009c04 + /*report CRC error*/ + RFWPacket.Init.RadioEvents->RxError( ); + 800bb42: 4b39 ldr r3, [pc, #228] @ (800bc28 ) + 800bb44: 691b ldr r3, [r3, #16] + 800bb46: 691b ldr r3, [r3, #16] + 800bb48: 4798 blx r3 + return; + 800bb4a: e069 b.n 800bc20 + } + } + /*calculate next timer timeout*/ + if( RFWPacket.LongPacketRemainingBytes < LONGPACKET_CHUNK_LENGTH_BYTES ) + 800bb4c: 4b36 ldr r3, [pc, #216] @ (800bc28 ) + 800bb4e: 8e9b ldrh r3, [r3, #52] @ 0x34 + 800bb50: 2b7f cmp r3, #127 @ 0x7f + 800bb52: d812 bhi.n 800bb7a + { + /*for the next and last chunk DIVC +1 to make sure crc is received.*/ + Timeout = DIVC( ( RFWPacket.LongPacketRemainingBytes ) * 8 * 1000, RFWPacket.BitRate ) + 2; + 800bb54: 4b34 ldr r3, [pc, #208] @ (800bc28 ) + 800bb56: 8e9b ldrh r3, [r3, #52] @ 0x34 + 800bb58: 461a mov r2, r3 + 800bb5a: f44f 53fa mov.w r3, #8000 @ 0x1f40 + 800bb5e: fb02 f303 mul.w r3, r2, r3 + 800bb62: 461a mov r2, r3 + 800bb64: 4b30 ldr r3, [pc, #192] @ (800bc28 ) + 800bb66: 6c9b ldr r3, [r3, #72] @ 0x48 + 800bb68: 4413 add r3, r2 + 800bb6a: 1e5a subs r2, r3, #1 + 800bb6c: 4b2e ldr r3, [pc, #184] @ (800bc28 ) + 800bb6e: 6c9b ldr r3, [r3, #72] @ 0x48 + 800bb70: fbb2 f3f3 udiv r3, r2, r3 + 800bb74: 3302 adds r3, #2 + 800bb76: 607b str r3, [r7, #4] + 800bb78: e021 b.n 800bbbe + } + else if( RFWPacket.LongPacketRemainingBytes < ( 3 * LONGPACKET_CHUNK_LENGTH_BYTES ) / 2 ) + 800bb7a: 4b2b ldr r3, [pc, #172] @ (800bc28 ) + 800bb7c: 8e9b ldrh r3, [r3, #52] @ 0x34 + 800bb7e: 2bbf cmp r3, #191 @ 0xbf + 800bb80: d813 bhi.n 800bbaa + { + /*this is to make sure that last chunk will always be greater than LONGPACKET_CHUNK_LENGTH_BYTES/2 */ + Timeout = DIVR( ( RFWPacket.LongPacketRemainingBytes / 2 ) * 8 * 1000, RFWPacket.BitRate ); + 800bb82: 4b29 ldr r3, [pc, #164] @ (800bc28 ) + 800bb84: 8e9b ldrh r3, [r3, #52] @ 0x34 + 800bb86: 085b lsrs r3, r3, #1 + 800bb88: b29b uxth r3, r3 + 800bb8a: 461a mov r2, r3 + 800bb8c: f44f 53fa mov.w r3, #8000 @ 0x1f40 + 800bb90: fb02 f303 mul.w r3, r2, r3 + 800bb94: 461a mov r2, r3 + 800bb96: 4b24 ldr r3, [pc, #144] @ (800bc28 ) + 800bb98: 6c9b ldr r3, [r3, #72] @ 0x48 + 800bb9a: 085b lsrs r3, r3, #1 + 800bb9c: 441a add r2, r3 + 800bb9e: 4b22 ldr r3, [pc, #136] @ (800bc28 ) + 800bba0: 6c9b ldr r3, [r3, #72] @ 0x48 + 800bba2: fbb2 f3f3 udiv r3, r2, r3 + 800bba6: 607b str r3, [r7, #4] + 800bba8: e009 b.n 800bbbe + } + else + { + /*size value is close to LONGPACKET_CHUNK_LENGTH_BYTES with +/- errors compensated in closed loop here*/ + Timeout = DIVR( ( LONGPACKET_CHUNK_LENGTH_BYTES ) * 8 * 1000, RFWPacket.BitRate ); + 800bbaa: 4b1f ldr r3, [pc, #124] @ (800bc28 ) + 800bbac: 6c9b ldr r3, [r3, #72] @ 0x48 + 800bbae: 085b lsrs r3, r3, #1 + 800bbb0: f503 227a add.w r2, r3, #1024000 @ 0xfa000 + 800bbb4: 4b1c ldr r3, [pc, #112] @ (800bc28 ) + 800bbb6: 6c9b ldr r3, [r3, #72] @ 0x48 + 800bbb8: fbb2 f3f3 udiv r3, r2, r3 + 800bbbc: 607b str r3, [r7, #4] + } + TimerSetValue( &RFWPacket.Timer, Timeout ); + 800bbbe: 6879 ldr r1, [r7, #4] + 800bbc0: 481f ldr r0, [pc, #124] @ (800bc40 ) + 800bbc2: f002 f8a9 bl 800dd18 + TimerStart( &RFWPacket.Timer ); + 800bbc6: 481e ldr r0, [pc, #120] @ (800bc40 ) + 800bbc8: f001 ffc8 bl 800db5c + 800bbcc: e028 b.n 800bc20 + } + else + { + if( RFWPacket.LongPacketRemainingBytes < RFWPacket.Init.CrcFieldSize ) + 800bbce: 4b16 ldr r3, [pc, #88] @ (800bc28 ) + 800bbd0: 8e9b ldrh r3, [r3, #52] @ 0x34 + 800bbd2: 4a15 ldr r2, [pc, #84] @ (800bc28 ) + 800bbd4: 78d2 ldrb r2, [r2, #3] + 800bbd6: 4293 cmp r3, r2 + 800bbd8: d204 bcs.n 800bbe4 + { + /* force LongPacketRemainingBytes to CrcFieldSize: this should never happen*/ + RFWPacket.LongPacketRemainingBytes = RFWPacket.Init.CrcFieldSize; + 800bbda: 4b13 ldr r3, [pc, #76] @ (800bc28 ) + 800bbdc: 78db ldrb r3, [r3, #3] + 800bbde: 461a mov r2, r3 + 800bbe0: 4b11 ldr r3, [pc, #68] @ (800bc28 ) + 800bbe2: 869a strh r2, [r3, #52] @ 0x34 + } + /*last chunk*/ + RFW_MW_LOG( TS_ON, VLEVEL_M, "LastChunk. offset= %d, size=%d, remaining=%d,\r\n", RFWPacket.RadioBufferOffset, size, + 800bbe4: 4b10 ldr r3, [pc, #64] @ (800bc28 ) + 800bbe6: f893 3036 ldrb.w r3, [r3, #54] @ 0x36 + 800bbea: 4619 mov r1, r3 + 800bbec: 78bb ldrb r3, [r7, #2] + 800bbee: 4a0e ldr r2, [pc, #56] @ (800bc28 ) + 800bbf0: 8e92 ldrh r2, [r2, #52] @ 0x34 + 800bbf2: 9202 str r2, [sp, #8] + 800bbf4: 9301 str r3, [sp, #4] + 800bbf6: 9100 str r1, [sp, #0] + 800bbf8: 4b12 ldr r3, [pc, #72] @ (800bc44 ) + 800bbfa: 2201 movs r2, #1 + 800bbfc: 2100 movs r1, #0 + 800bbfe: 2002 movs r0, #2 + 800bc00: f002 fa12 bl 800e028 + RFWPacket.LongPacketRemainingBytes ); + size = RFWPacket.LongPacketRemainingBytes; + 800bc04: 4b08 ldr r3, [pc, #32] @ (800bc28 ) + 800bc06: 8e9b ldrh r3, [r3, #52] @ 0x34 + 800bc08: 70bb strb r3, [r7, #2] + /* update LongPacketRemainingBytes*/ + RFWPacket.LongPacketRemainingBytes = 0; + 800bc0a: 4b07 ldr r3, [pc, #28] @ (800bc28 ) + 800bc0c: 2200 movs r2, #0 + 800bc0e: 869a strh r2, [r3, #52] @ 0x34 + /*Process last chunk*/ + RFW_GetPayload( RFWPacket.RadioBufferOffset, size ); + 800bc10: 4b05 ldr r3, [pc, #20] @ (800bc28 ) + 800bc12: f893 3036 ldrb.w r3, [r3, #54] @ 0x36 + 800bc16: 78ba ldrb r2, [r7, #2] + 800bc18: 4611 mov r1, r2 + 800bc1a: 4618 mov r0, r3 + 800bc1c: f000 f814 bl 800bc48 + } +} + 800bc20: 3708 adds r7, #8 + 800bc22: 46bd mov sp, r7 + 800bc24: bd80 pop {r7, pc} + 800bc26: bf00 nop + 800bc28: 2000039c .word 0x2000039c + 800bc2c: 0800f244 .word 0x0800f244 + 800bc30: 0800f25c .word 0x0800f25c + 800bc34: 0800f270 .word 0x0800f270 + 800bc38: 200003f0 .word 0x200003f0 + 800bc3c: 200004f0 .word 0x200004f0 + 800bc40: 200003b8 .word 0x200003b8 + 800bc44: 0800f298 .word 0x0800f298 + +0800bc48 : + +static void RFW_GetPayload( uint8_t Offset, uint8_t Length ) +{ + 800bc48: b5b0 push {r4, r5, r7, lr} + 800bc4a: b088 sub sp, #32 + 800bc4c: af04 add r7, sp, #16 + 800bc4e: 4603 mov r3, r0 + 800bc50: 460a mov r2, r1 + 800bc52: 71fb strb r3, [r7, #7] + 800bc54: 4613 mov r3, r2 + 800bc56: 71bb strb r3, [r7, #6] + uint8_t crc_result[2]; + /*stop the radio*/ + SUBGRF_SetStandby( STDBY_RC ); + 800bc58: 2000 movs r0, #0 + 800bc5a: f7fd ffd3 bl 8009c04 + /*read data buffer*/ + SUBGRF_ReadBuffer( Offset, ChunkBuffer, Length ); + 800bc5e: 79ba ldrb r2, [r7, #6] + 800bc60: 79fb ldrb r3, [r7, #7] + 800bc62: 495a ldr r1, [pc, #360] @ (800bdcc ) + 800bc64: 4618 mov r0, r3 + 800bc66: f7fe fdf9 bl 800a85c + /*Run the de-whitening on all packet*/ + RFW_WhiteRun( &RFWPacket, ChunkBuffer, Length ); + 800bc6a: 79bb ldrb r3, [r7, #6] + 800bc6c: 461a mov r2, r3 + 800bc6e: 4957 ldr r1, [pc, #348] @ (800bdcc ) + 800bc70: 4857 ldr r0, [pc, #348] @ (800bdd0 ) + 800bc72: f7ff fd6a bl 800b74a + if( RFWPacket.Init.CrcEnable == 1 ) + 800bc76: 4b56 ldr r3, [pc, #344] @ (800bdd0 ) + 800bc78: 789b ldrb r3, [r3, #2] + 800bc7a: 2b01 cmp r3, #1 + 800bc7c: d10a bne.n 800bc94 + { + RFW_CrcRun( &RFWPacket, ChunkBuffer, Length - RFWPacket.Init.CrcFieldSize, crc_result ); + 800bc7e: 79bb ldrb r3, [r7, #6] + 800bc80: 4a53 ldr r2, [pc, #332] @ (800bdd0 ) + 800bc82: 78d2 ldrb r2, [r2, #3] + 800bc84: 1a9b subs r3, r3, r2 + 800bc86: 461a mov r2, r3 + 800bc88: f107 030c add.w r3, r7, #12 + 800bc8c: 494f ldr r1, [pc, #316] @ (800bdcc ) + 800bc8e: 4850 ldr r0, [pc, #320] @ (800bdd0 ) + 800bc90: f7ff fda3 bl 800b7da + } + if( RFWPacket.LongPacketModeEnable == 1 ) + 800bc94: 4b4e ldr r3, [pc, #312] @ (800bdd0 ) + 800bc96: 7e9b ldrb r3, [r3, #26] + 800bc98: 2b01 cmp r3, #1 + 800bc9a: d10a bne.n 800bcb2 + { + /*report rx data chunk to application*/ + + RFWPacket.RxLongPacketStoreChunkCb( ChunkBuffer, Length - RFWPacket.Init.CrcFieldSize ); + 800bc9c: 4b4c ldr r3, [pc, #304] @ (800bdd0 ) + 800bc9e: 6bdb ldr r3, [r3, #60] @ 0x3c + 800bca0: 4a4b ldr r2, [pc, #300] @ (800bdd0 ) + 800bca2: 78d2 ldrb r2, [r2, #3] + 800bca4: 79b9 ldrb r1, [r7, #6] + 800bca6: 1a8a subs r2, r1, r2 + 800bca8: b2d2 uxtb r2, r2 + 800bcaa: 4611 mov r1, r2 + 800bcac: 4847 ldr r0, [pc, #284] @ (800bdcc ) + 800bcae: 4798 blx r3 + 800bcb0: e02a b.n 800bd08 + } + else + { + if( RFWPacket.RxPayloadOffset + Length - RFWPacket.Init.CrcFieldSize < RADIO_BUF_SIZE ) + 800bcb2: 4b47 ldr r3, [pc, #284] @ (800bdd0 ) + 800bcb4: 8f1b ldrh r3, [r3, #56] @ 0x38 + 800bcb6: 461a mov r2, r3 + 800bcb8: 79bb ldrb r3, [r7, #6] + 800bcba: 4413 add r3, r2 + 800bcbc: 4a44 ldr r2, [pc, #272] @ (800bdd0 ) + 800bcbe: 78d2 ldrb r2, [r2, #3] + 800bcc0: 1a9b subs r3, r3, r2 + 800bcc2: 2bfe cmp r3, #254 @ 0xfe + 800bcc4: dc1b bgt.n 800bcfe + { + RADIO_MEMCPY8( &RxBuffer[RFWPacket.RxPayloadOffset], ChunkBuffer, Length - RFWPacket.Init.CrcFieldSize ); + 800bcc6: 4b42 ldr r3, [pc, #264] @ (800bdd0 ) + 800bcc8: 8f1b ldrh r3, [r3, #56] @ 0x38 + 800bcca: 461a mov r2, r3 + 800bccc: 4b41 ldr r3, [pc, #260] @ (800bdd4 ) + 800bcce: 18d0 adds r0, r2, r3 + 800bcd0: 79bb ldrb r3, [r7, #6] + 800bcd2: b29b uxth r3, r3 + 800bcd4: 4a3e ldr r2, [pc, #248] @ (800bdd0 ) + 800bcd6: 78d2 ldrb r2, [r2, #3] + 800bcd8: 1a9b subs r3, r3, r2 + 800bcda: b29b uxth r3, r3 + 800bcdc: 461a mov r2, r3 + 800bcde: 493b ldr r1, [pc, #236] @ (800bdcc ) + 800bce0: f001 faa4 bl 800d22c + RFWPacket.RxPayloadOffset += Length - RFWPacket.Init.CrcFieldSize; + 800bce4: 4b3a ldr r3, [pc, #232] @ (800bdd0 ) + 800bce6: 8f1a ldrh r2, [r3, #56] @ 0x38 + 800bce8: 79bb ldrb r3, [r7, #6] + 800bcea: b29b uxth r3, r3 + 800bcec: 4938 ldr r1, [pc, #224] @ (800bdd0 ) + 800bcee: 78c9 ldrb r1, [r1, #3] + 800bcf0: 1a5b subs r3, r3, r1 + 800bcf2: b29b uxth r3, r3 + 800bcf4: 4413 add r3, r2 + 800bcf6: b29a uxth r2, r3 + 800bcf8: 4b35 ldr r3, [pc, #212] @ (800bdd0 ) + 800bcfa: 871a strh r2, [r3, #56] @ 0x38 + 800bcfc: e004 b.n 800bd08 + } + else + { + /*report CRC error*/ + RFWPacket.Init.RadioEvents->RxError( ); + 800bcfe: 4b34 ldr r3, [pc, #208] @ (800bdd0 ) + 800bd00: 691b ldr r3, [r3, #16] + 800bd02: 691b ldr r3, [r3, #16] + 800bd04: 4798 blx r3 + 800bd06: e05d b.n 800bdc4 + return; + } + } + TimerStop( RFWPacket.RxTimeoutTimer ); + 800bd08: 4b31 ldr r3, [pc, #196] @ (800bdd0 ) + 800bd0a: 6cdb ldr r3, [r3, #76] @ 0x4c + 800bd0c: 4618 mov r0, r3 + 800bd0e: f001 ff93 bl 800dc38 + /* CRC check*/ + RFW_MW_LOG( TS_ON, VLEVEL_M, "crc_result= 0x%02X%02X, crc_payload=0x%02X%02X\r\n", crc_result[0], crc_result[1], + 800bd12: 7b3b ldrb r3, [r7, #12] + 800bd14: 4619 mov r1, r3 + 800bd16: 7b7b ldrb r3, [r7, #13] + 800bd18: 4618 mov r0, r3 + 800bd1a: 79bb ldrb r3, [r7, #6] + 800bd1c: 3b02 subs r3, #2 + 800bd1e: 4a2b ldr r2, [pc, #172] @ (800bdcc ) + 800bd20: 5cd3 ldrb r3, [r2, r3] + 800bd22: 461c mov r4, r3 + 800bd24: 79bb ldrb r3, [r7, #6] + 800bd26: 3b01 subs r3, #1 + 800bd28: 4a28 ldr r2, [pc, #160] @ (800bdcc ) + 800bd2a: 5cd3 ldrb r3, [r2, r3] + 800bd2c: 9303 str r3, [sp, #12] + 800bd2e: 9402 str r4, [sp, #8] + 800bd30: 9001 str r0, [sp, #4] + 800bd32: 9100 str r1, [sp, #0] + 800bd34: 4b28 ldr r3, [pc, #160] @ (800bdd8 ) + 800bd36: 2201 movs r2, #1 + 800bd38: 2100 movs r1, #0 + 800bd3a: 2002 movs r0, #2 + 800bd3c: f002 f974 bl 800e028 + ChunkBuffer[Length - 2], ChunkBuffer[Length - 1] ); + if( ( ( crc_result[0] == ChunkBuffer[Length - 2] ) && + 800bd40: 7b3a ldrb r2, [r7, #12] + 800bd42: 79bb ldrb r3, [r7, #6] + 800bd44: 3b02 subs r3, #2 + 800bd46: 4921 ldr r1, [pc, #132] @ (800bdcc ) + 800bd48: 5ccb ldrb r3, [r1, r3] + 800bd4a: 429a cmp r2, r3 + 800bd4c: d106 bne.n 800bd5c + ( crc_result[1] == ChunkBuffer[Length - 1] ) ) || + 800bd4e: 7b7a ldrb r2, [r7, #13] + 800bd50: 79bb ldrb r3, [r7, #6] + 800bd52: 3b01 subs r3, #1 + 800bd54: 491d ldr r1, [pc, #116] @ (800bdcc ) + 800bd56: 5ccb ldrb r3, [r1, r3] + if( ( ( crc_result[0] == ChunkBuffer[Length - 2] ) && + 800bd58: 429a cmp r2, r3 + 800bd5a: d003 beq.n 800bd64 + ( RFWPacket.Init.CrcEnable == 0 ) ) + 800bd5c: 4b1c ldr r3, [pc, #112] @ (800bdd0 ) + 800bd5e: 789b ldrb r3, [r3, #2] + ( crc_result[1] == ChunkBuffer[Length - 1] ) ) || + 800bd60: 2b00 cmp r3, #0 + 800bd62: d126 bne.n 800bdb2 + { + /*read Rssi sampled at Sync*/ + uint8_t rssi_sync = SUBGRF_ReadRegister( 0x06CA ); + 800bd64: f240 60ca movw r0, #1738 @ 0x6ca + 800bd68: f7fe fcf2 bl 800a750 + 800bd6c: 4603 mov r3, r0 + 800bd6e: 73fb strb r3, [r7, #15] + /* Get Carrier Frequency Offset*/ + int32_t cfo; + SUBGRF_GetCFO( RFWPacket.BitRate, &cfo ); + 800bd70: 4b17 ldr r3, [pc, #92] @ (800bdd0 ) + 800bd72: 6c9b ldr r3, [r3, #72] @ 0x48 + 800bd74: f107 0208 add.w r2, r7, #8 + 800bd78: 4611 mov r1, r2 + 800bd7a: 4618 mov r0, r3 + 800bd7c: f7fe ff22 bl 800abc4 + /*ChunkBuffer[1] to remove packet Length*/ + RFWPacket.Init.RadioEvents->RxDone( RxBuffer, + 800bd80: 4b13 ldr r3, [pc, #76] @ (800bdd0 ) + 800bd82: 691b ldr r3, [r3, #16] + 800bd84: 689c ldr r4, [r3, #8] + 800bd86: 4b12 ldr r3, [pc, #72] @ (800bdd0 ) + 800bd88: 8f19 ldrh r1, [r3, #56] @ 0x38 + 800bd8a: 7bfb ldrb r3, [r7, #15] + 800bd8c: 085b lsrs r3, r3, #1 + 800bd8e: b2db uxtb r3, r3 + 800bd90: 425b negs r3, r3 + 800bd92: b29b uxth r3, r3 + 800bd94: b218 sxth r0, r3 + RFWPacket.RxPayloadOffset, + -( rssi_sync >> 1 ), + ( int8_t ) DIVR( cfo, 1000 ) ); + 800bd96: 68bb ldr r3, [r7, #8] + 800bd98: f503 73fa add.w r3, r3, #500 @ 0x1f4 + 800bd9c: 4a0f ldr r2, [pc, #60] @ (800bddc ) + 800bd9e: fb82 5203 smull r5, r2, r2, r3 + 800bda2: 1192 asrs r2, r2, #6 + 800bda4: 17db asrs r3, r3, #31 + 800bda6: 1ad3 subs r3, r2, r3 + RFWPacket.Init.RadioEvents->RxDone( RxBuffer, + 800bda8: b25b sxtb r3, r3 + 800bdaa: 4602 mov r2, r0 + 800bdac: 4809 ldr r0, [pc, #36] @ (800bdd4 ) + 800bdae: 47a0 blx r4 + { + 800bdb0: e003 b.n 800bdba + } + else + { + /*report CRC error*/ + RFWPacket.Init.RadioEvents->RxError( ); + 800bdb2: 4b07 ldr r3, [pc, #28] @ (800bdd0 ) + 800bdb4: 691b ldr r3, [r3, #16] + 800bdb6: 691b ldr r3, [r3, #16] + 800bdb8: 4798 blx r3 + } + DBG_GPIO_RADIO_RX( RST ); + 800bdba: f44f 5180 mov.w r1, #4096 @ 0x1000 + 800bdbe: 4808 ldr r0, [pc, #32] @ (800bde0 ) + 800bdc0: f7fe ff8d bl 800acde +} + 800bdc4: 3710 adds r7, #16 + 800bdc6: 46bd mov sp, r7 + 800bdc8: bdb0 pop {r4, r5, r7, pc} + 800bdca: bf00 nop + 800bdcc: 200003f0 .word 0x200003f0 + 800bdd0: 2000039c .word 0x2000039c + 800bdd4: 200004f0 .word 0x200004f0 + 800bdd8: 0800f2c8 .word 0x0800f2c8 + 800bddc: 10624dd3 .word 0x10624dd3 + 800bde0: 48000400 .word 0x48000400 + +0800bde4 : +#include "subghz_phy_app.h" +#include "sys_app.h" +#include "stm32_seq.h" + +void MX_SubGHz_Phy_Init(void) +{ + 800bde4: b580 push {r7, lr} + 800bde6: af00 add r7, sp, #0 + SystemApp_Init(); + 800bde8: f7f4 feb4 bl 8000b54 + SubghzApp_Init(); + 800bdec: f000 f80c bl 800be08 +} + 800bdf0: bf00 nop + 800bdf2: bd80 pop {r7, pc} + +0800bdf4 : + +void MX_SubGHz_Phy_Process(void) +{ + 800bdf4: b580 push {r7, lr} + 800bdf6: af00 add r7, sp, #0 + SubghzApp_Process(); + 800bdf8: f000 f846 bl 800be88 + UTIL_SEQ_Run(UTIL_SEQ_DEFAULT); + 800bdfc: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff + 800be00: f001 fd26 bl 800d850 +} + 800be04: bf00 nop + 800be06: bd80 pop {r7, pc} + +0800be08 : +static void App_ReconfigureUart(uint32_t baudrate); +static uint8_t App_ParseHexSyncWord(const char *text, uint8_t out[3]); +static char *App_SkipSpaces(char *s); + +void SubghzApp_Init(void) +{ + 800be08: b580 push {r7, lr} + 800be0a: af00 add r7, sp, #0 + RadioEvents.TxDone = OnTxDone; + 800be0c: 4b13 ldr r3, [pc, #76] @ (800be5c ) + 800be0e: 4a14 ldr r2, [pc, #80] @ (800be60 ) + 800be10: 601a str r2, [r3, #0] + RadioEvents.RxDone = OnRxDone; + 800be12: 4b12 ldr r3, [pc, #72] @ (800be5c ) + 800be14: 4a13 ldr r2, [pc, #76] @ (800be64 ) + 800be16: 609a str r2, [r3, #8] + RadioEvents.TxTimeout = OnTxTimeout; + 800be18: 4b10 ldr r3, [pc, #64] @ (800be5c ) + 800be1a: 4a13 ldr r2, [pc, #76] @ (800be68 ) + 800be1c: 605a str r2, [r3, #4] + RadioEvents.RxTimeout = OnRxTimeout; + 800be1e: 4b0f ldr r3, [pc, #60] @ (800be5c ) + 800be20: 4a12 ldr r2, [pc, #72] @ (800be6c ) + 800be22: 60da str r2, [r3, #12] + RadioEvents.RxError = OnRxError; + 800be24: 4b0d ldr r3, [pc, #52] @ (800be5c ) + 800be26: 4a12 ldr r2, [pc, #72] @ (800be70 ) + 800be28: 611a str r2, [r3, #16] + + Radio.Init(&RadioEvents); + 800be2a: 4b12 ldr r3, [pc, #72] @ (800be74 ) + 800be2c: 681b ldr r3, [r3, #0] + 800be2e: 480b ldr r0, [pc, #44] @ (800be5c ) + 800be30: 4798 blx r3 + App_RadioApplyConfig(); + 800be32: f000 f97d bl 800c130 + App_RadioEnterRx(); + 800be36: f000 fa2f bl 800c298 + + g_uart_last_data_tick = HAL_GetTick(); + 800be3a: f7f4 ff05 bl 8000c48 + 800be3e: 4603 mov r3, r0 + 800be40: 4a0d ldr r2, [pc, #52] @ (800be78 ) + 800be42: 6013 str r3, [r2, #0] + (void)vcom_ReceiveInit(UartRxByteCallback); + 800be44: 480d ldr r0, [pc, #52] @ (800be7c ) + 800be46: f7f5 fbb1 bl 80015ac + + App_Printf("\r\nSTM32WL UART<->SUBGHZ bridge started\r\n"); + 800be4a: 480d ldr r0, [pc, #52] @ (800be80 ) + 800be4c: f000 ff98 bl 800cd80 + App_Printf("DATA mode, escape sequence: silence 800 ms + +++ + silence 800 ms\r\n"); + 800be50: 480c ldr r0, [pc, #48] @ (800be84 ) + 800be52: f000 ff95 bl 800cd80 +} + 800be56: bf00 nop + 800be58: bd80 pop {r7, pc} + 800be5a: bf00 nop + 800be5c: 200005f0 .word 0x200005f0 + 800be60: 0800cfad .word 0x0800cfad + 800be64: 0800cfc5 .word 0x0800cfc5 + 800be68: 0800d029 .word 0x0800d029 + 800be6c: 0800d041 .word 0x0800d041 + 800be70: 0800d059 .word 0x0800d059 + 800be74: 0800fb7c .word 0x0800fb7c + 800be78: 20000b50 .word 0x20000b50 + 800be7c: 0800c4e5 .word 0x0800c4e5 + 800be80: 0800f2fc .word 0x0800f2fc + 800be84: 0800f328 .word 0x0800f328 + +0800be88 : + +void SubghzApp_Process(void) +{ + 800be88: b580 push {r7, lr} + 800be8a: af00 add r7, sp, #0 + App_ProcessEscape(); + 800be8c: f000 f8c6 bl 800c01c + App_ProcessUartPacketizer(); + 800be90: f000 f898 bl 800bfc4 + App_ProcessRadioEvents(); + 800be94: f000 f804 bl 800bea0 + App_StartNextTxIfPossible(); + 800be98: f000 f910 bl 800c0bc +} + 800be9c: bf00 nop + 800be9e: bd80 pop {r7, pc} + +0800bea0 : + +static void App_ProcessRadioEvents(void) +{ + 800bea0: b580 push {r7, lr} + 800bea2: af00 add r7, sp, #0 + if (g_radio_tx_done != 0U) + 800bea4: 4b38 ldr r3, [pc, #224] @ (800bf88 ) + 800bea6: 781b ldrb r3, [r3, #0] + 800bea8: b2db uxtb r3, r3 + 800beaa: 2b00 cmp r3, #0 + 800beac: d00f beq.n 800bece + { + g_radio_tx_done = 0U; + 800beae: 4b36 ldr r3, [pc, #216] @ (800bf88 ) + 800beb0: 2200 movs r2, #0 + 800beb2: 701a strb r2, [r3, #0] + g_radio_busy = 0U; + 800beb4: 4b35 ldr r3, [pc, #212] @ (800bf8c ) + 800beb6: 2200 movs r2, #0 + 800beb8: 701a strb r2, [r3, #0] + g_stat_uart_packets_tx++; + 800beba: 4b35 ldr r3, [pc, #212] @ (800bf90 ) + 800bebc: 681b ldr r3, [r3, #0] + 800bebe: 3301 adds r3, #1 + 800bec0: 4a33 ldr r2, [pc, #204] @ (800bf90 ) + 800bec2: 6013 str r3, [r2, #0] + App_QueuePop(); + 800bec4: f000 faf0 bl 800c4a8 + g_radio_needs_rx_restart = 1U; + 800bec8: 4b32 ldr r3, [pc, #200] @ (800bf94 ) + 800beca: 2201 movs r2, #1 + 800becc: 701a strb r2, [r3, #0] + } + + if (g_radio_tx_timeout != 0U) + 800bece: 4b32 ldr r3, [pc, #200] @ (800bf98 ) + 800bed0: 781b ldrb r3, [r3, #0] + 800bed2: b2db uxtb r3, r3 + 800bed4: 2b00 cmp r3, #0 + 800bed6: d00d beq.n 800bef4 + { + g_radio_tx_timeout = 0U; + 800bed8: 4b2f ldr r3, [pc, #188] @ (800bf98 ) + 800beda: 2200 movs r2, #0 + 800bedc: 701a strb r2, [r3, #0] + g_radio_busy = 0U; + 800bede: 4b2b ldr r3, [pc, #172] @ (800bf8c ) + 800bee0: 2200 movs r2, #0 + 800bee2: 701a strb r2, [r3, #0] + App_QueuePop(); + 800bee4: f000 fae0 bl 800c4a8 + App_Printf("\r\n[WARN] radio tx timeout\r\n"); + 800bee8: 482c ldr r0, [pc, #176] @ (800bf9c ) + 800beea: f000 ff49 bl 800cd80 + g_radio_needs_rx_restart = 1U; + 800beee: 4b29 ldr r3, [pc, #164] @ (800bf94 ) + 800bef0: 2201 movs r2, #1 + 800bef2: 701a strb r2, [r3, #0] + } + + if (g_radio_rx_done != 0U) + 800bef4: 4b2a ldr r3, [pc, #168] @ (800bfa0 ) + 800bef6: 781b ldrb r3, [r3, #0] + 800bef8: b2db uxtb r3, r3 + 800befa: 2b00 cmp r3, #0 + 800befc: d01c beq.n 800bf38 + { + g_radio_rx_done = 0U; + 800befe: 4b28 ldr r3, [pc, #160] @ (800bfa0 ) + 800bf00: 2200 movs r2, #0 + 800bf02: 701a strb r2, [r3, #0] + g_stat_radio_packets_rx++; + 800bf04: 4b27 ldr r3, [pc, #156] @ (800bfa4 ) + 800bf06: 681b ldr r3, [r3, #0] + 800bf08: 3301 adds r3, #1 + 800bf0a: 4a26 ldr r2, [pc, #152] @ (800bfa4 ) + 800bf0c: 6013 str r3, [r2, #0] + g_stat_radio_bytes_rx += g_rx_payload_len; + 800bf0e: 4b26 ldr r3, [pc, #152] @ (800bfa8 ) + 800bf10: 881b ldrh r3, [r3, #0] + 800bf12: 461a mov r2, r3 + 800bf14: 4b25 ldr r3, [pc, #148] @ (800bfac ) + 800bf16: 681b ldr r3, [r3, #0] + 800bf18: 4413 add r3, r2 + 800bf1a: 4a24 ldr r2, [pc, #144] @ (800bfac ) + 800bf1c: 6013 str r3, [r2, #0] + + if (g_mode == APP_MODE_DATA) + 800bf1e: 4b24 ldr r3, [pc, #144] @ (800bfb0 ) + 800bf20: 781b ldrb r3, [r3, #0] + 800bf22: 2b00 cmp r3, #0 + 800bf24: d105 bne.n 800bf32 + { + App_Write(g_rx_payload, g_rx_payload_len); + 800bf26: 4b20 ldr r3, [pc, #128] @ (800bfa8 ) + 800bf28: 881b ldrh r3, [r3, #0] + 800bf2a: 4619 mov r1, r3 + 800bf2c: 4821 ldr r0, [pc, #132] @ (800bfb4 ) + 800bf2e: f000 ff53 bl 800cdd8 + } + + g_radio_needs_rx_restart = 1U; + 800bf32: 4b18 ldr r3, [pc, #96] @ (800bf94 ) + 800bf34: 2201 movs r2, #1 + 800bf36: 701a strb r2, [r3, #0] + } + + if ((g_radio_rx_timeout != 0U) || (g_radio_rx_error != 0U)) + 800bf38: 4b1f ldr r3, [pc, #124] @ (800bfb8 ) + 800bf3a: 781b ldrb r3, [r3, #0] + 800bf3c: b2db uxtb r3, r3 + 800bf3e: 2b00 cmp r3, #0 + 800bf40: d104 bne.n 800bf4c + 800bf42: 4b1e ldr r3, [pc, #120] @ (800bfbc ) + 800bf44: 781b ldrb r3, [r3, #0] + 800bf46: b2db uxtb r3, r3 + 800bf48: 2b00 cmp r3, #0 + 800bf4a: d008 beq.n 800bf5e + { + g_radio_rx_timeout = 0U; + 800bf4c: 4b1a ldr r3, [pc, #104] @ (800bfb8 ) + 800bf4e: 2200 movs r2, #0 + 800bf50: 701a strb r2, [r3, #0] + g_radio_rx_error = 0U; + 800bf52: 4b1a ldr r3, [pc, #104] @ (800bfbc ) + 800bf54: 2200 movs r2, #0 + 800bf56: 701a strb r2, [r3, #0] + g_radio_needs_rx_restart = 1U; + 800bf58: 4b0e ldr r3, [pc, #56] @ (800bf94 ) + 800bf5a: 2201 movs r2, #1 + 800bf5c: 701a strb r2, [r3, #0] + } + + if ((g_radio_needs_rx_restart != 0U) && (g_radio_busy == 0U) && (g_tx_q_count == 0U)) + 800bf5e: 4b0d ldr r3, [pc, #52] @ (800bf94 ) + 800bf60: 781b ldrb r3, [r3, #0] + 800bf62: b2db uxtb r3, r3 + 800bf64: 2b00 cmp r3, #0 + 800bf66: d00d beq.n 800bf84 + 800bf68: 4b08 ldr r3, [pc, #32] @ (800bf8c ) + 800bf6a: 781b ldrb r3, [r3, #0] + 800bf6c: b2db uxtb r3, r3 + 800bf6e: 2b00 cmp r3, #0 + 800bf70: d108 bne.n 800bf84 + 800bf72: 4b13 ldr r3, [pc, #76] @ (800bfc0 ) + 800bf74: 781b ldrb r3, [r3, #0] + 800bf76: 2b00 cmp r3, #0 + 800bf78: d104 bne.n 800bf84 + { + g_radio_needs_rx_restart = 0U; + 800bf7a: 4b06 ldr r3, [pc, #24] @ (800bf94 ) + 800bf7c: 2200 movs r2, #0 + 800bf7e: 701a strb r2, [r3, #0] + App_RadioEnterRx(); + 800bf80: f000 f98a bl 800c298 + } +} + 800bf84: bf00 nop + 800bf86: bd80 pop {r7, pc} + 800bf88: 2000060c .word 0x2000060c + 800bf8c: 20000615 .word 0x20000615 + 800bf90: 20000bcc .word 0x20000bcc + 800bf94: 20000616 .word 0x20000616 + 800bf98: 2000060d .word 0x2000060d + 800bf9c: 0800f36c .word 0x0800f36c + 800bfa0: 2000060e .word 0x2000060e + 800bfa4: 20000bd4 .word 0x20000bd4 + 800bfa8: 200006f4 .word 0x200006f4 + 800bfac: 20000bd8 .word 0x20000bd8 + 800bfb0: 20000b64 .word 0x20000b64 + 800bfb4: 20000618 .word 0x20000618 + 800bfb8: 2000060f .word 0x2000060f + 800bfbc: 20000610 .word 0x20000610 + 800bfc0: 20000a6e .word 0x20000a6e + +0800bfc4 : + +static void App_ProcessUartPacketizer(void) +{ + 800bfc4: b580 push {r7, lr} + 800bfc6: b082 sub sp, #8 + 800bfc8: af00 add r7, sp, #0 + uint32_t now = HAL_GetTick(); + 800bfca: f7f4 fe3d bl 8000c48 + 800bfce: 6078 str r0, [r7, #4] + + if (g_mode != APP_MODE_DATA) + 800bfd0: 4b0d ldr r3, [pc, #52] @ (800c008 ) + 800bfd2: 781b ldrb r3, [r3, #0] + 800bfd4: 2b00 cmp r3, #0 + 800bfd6: d112 bne.n 800bffe + { + return; + } + + if ((g_uart_build_len > 0U) && + 800bfd8: 4b0c ldr r3, [pc, #48] @ (800c00c ) + 800bfda: 881b ldrh r3, [r3, #0] + 800bfdc: 2b00 cmp r3, #0 + 800bfde: d00f beq.n 800c000 + ((now - g_uart_last_data_tick) >= g_cfg.uart_packet_timeout_ms) && + 800bfe0: 4b0b ldr r3, [pc, #44] @ (800c010 ) + 800bfe2: 681b ldr r3, [r3, #0] + 800bfe4: 687a ldr r2, [r7, #4] + 800bfe6: 1ad3 subs r3, r2, r3 + 800bfe8: 4a0a ldr r2, [pc, #40] @ (800c014 ) + 800bfea: 8b52 ldrh r2, [r2, #26] + if ((g_uart_build_len > 0U) && + 800bfec: 4293 cmp r3, r2 + 800bfee: d307 bcc.n 800c000 + (g_escape.active == 0U)) + 800bff0: 4b09 ldr r3, [pc, #36] @ (800c018 ) + 800bff2: 781b ldrb r3, [r3, #0] + ((now - g_uart_last_data_tick) >= g_cfg.uart_packet_timeout_ms) && + 800bff4: 2b00 cmp r3, #0 + 800bff6: d103 bne.n 800c000 + { + App_DataModeFlushBuilder(); + 800bff8: f000 f9f0 bl 800c3dc + 800bffc: e000 b.n 800c000 + return; + 800bffe: bf00 nop + } +} + 800c000: 3708 adds r7, #8 + 800c002: 46bd mov sp, r7 + 800c004: bd80 pop {r7, pc} + 800c006: bf00 nop + 800c008: 20000b64 .word 0x20000b64 + 800c00c: 20000b4c .word 0x20000b4c + 800c010: 20000b50 .word 0x20000b50 + 800c014: 2000000c .word 0x2000000c + 800c018: 20000b54 .word 0x20000b54 + +0800c01c : + +static void App_ProcessEscape(void) +{ + 800c01c: b580 push {r7, lr} + 800c01e: b082 sub sp, #8 + 800c020: af00 add r7, sp, #0 + uint32_t now = HAL_GetTick(); + 800c022: f7f4 fe11 bl 8000c48 + 800c026: 6038 str r0, [r7, #0] + uint8_t i; + + if ((g_mode != APP_MODE_DATA) || (g_escape.active == 0U)) + 800c028: 4b22 ldr r3, [pc, #136] @ (800c0b4 ) + 800c02a: 781b ldrb r3, [r3, #0] + 800c02c: 2b00 cmp r3, #0 + 800c02e: d13c bne.n 800c0aa + 800c030: 4b21 ldr r3, [pc, #132] @ (800c0b8 ) + 800c032: 781b ldrb r3, [r3, #0] + 800c034: 2b00 cmp r3, #0 + 800c036: d038 beq.n 800c0aa + { + return; + } + + if ((g_escape.count == 3U) && ((now - g_escape.last_tick) >= CONFIG_ESCAPE_GUARD_MS)) + 800c038: 4b1f ldr r3, [pc, #124] @ (800c0b8 ) + 800c03a: 785b ldrb r3, [r3, #1] + 800c03c: 2b03 cmp r3, #3 + 800c03e: d10f bne.n 800c060 + 800c040: 4b1d ldr r3, [pc, #116] @ (800c0b8 ) + 800c042: 68db ldr r3, [r3, #12] + 800c044: 683a ldr r2, [r7, #0] + 800c046: 1ad3 subs r3, r2, r3 + 800c048: f5b3 7f48 cmp.w r3, #800 @ 0x320 + 800c04c: d308 bcc.n 800c060 + { + g_escape.active = 0U; + 800c04e: 4b1a ldr r3, [pc, #104] @ (800c0b8 ) + 800c050: 2200 movs r2, #0 + 800c052: 701a strb r2, [r3, #0] + g_escape.count = 0U; + 800c054: 4b18 ldr r3, [pc, #96] @ (800c0b8 ) + 800c056: 2200 movs r2, #0 + 800c058: 705a strb r2, [r3, #1] + App_EnterConfigMode(); + 800c05a: f000 f929 bl 800c2b0 + return; + 800c05e: e025 b.n 800c0ac + } + + if ((g_escape.count < 3U) && ((now - g_escape.last_tick) >= CONFIG_ESCAPE_GUARD_MS)) + 800c060: 4b15 ldr r3, [pc, #84] @ (800c0b8 ) + 800c062: 785b ldrb r3, [r3, #1] + 800c064: 2b02 cmp r3, #2 + 800c066: d821 bhi.n 800c0ac + 800c068: 4b13 ldr r3, [pc, #76] @ (800c0b8 ) + 800c06a: 68db ldr r3, [r3, #12] + 800c06c: 683a ldr r2, [r7, #0] + 800c06e: 1ad3 subs r3, r2, r3 + 800c070: f5b3 7f48 cmp.w r3, #800 @ 0x320 + 800c074: d31a bcc.n 800c0ac + { + for (i = 0U; i < g_escape.count; i++) + 800c076: 2300 movs r3, #0 + 800c078: 71fb strb r3, [r7, #7] + 800c07a: e00a b.n 800c092 + { + App_DataModeFeedByte(g_escape.bytes[i], now); + 800c07c: 79fb ldrb r3, [r7, #7] + 800c07e: 4a0e ldr r2, [pc, #56] @ (800c0b8 ) + 800c080: 4413 add r3, r2 + 800c082: 789b ldrb r3, [r3, #2] + 800c084: 6839 ldr r1, [r7, #0] + 800c086: 4618 mov r0, r3 + 800c088: f000 f966 bl 800c358 + for (i = 0U; i < g_escape.count; i++) + 800c08c: 79fb ldrb r3, [r7, #7] + 800c08e: 3301 adds r3, #1 + 800c090: 71fb strb r3, [r7, #7] + 800c092: 4b09 ldr r3, [pc, #36] @ (800c0b8 ) + 800c094: 785b ldrb r3, [r3, #1] + 800c096: 79fa ldrb r2, [r7, #7] + 800c098: 429a cmp r2, r3 + 800c09a: d3ef bcc.n 800c07c + } + g_escape.active = 0U; + 800c09c: 4b06 ldr r3, [pc, #24] @ (800c0b8 ) + 800c09e: 2200 movs r2, #0 + 800c0a0: 701a strb r2, [r3, #0] + g_escape.count = 0U; + 800c0a2: 4b05 ldr r3, [pc, #20] @ (800c0b8 ) + 800c0a4: 2200 movs r2, #0 + 800c0a6: 705a strb r2, [r3, #1] + 800c0a8: e000 b.n 800c0ac + return; + 800c0aa: bf00 nop + } +} + 800c0ac: 3708 adds r7, #8 + 800c0ae: 46bd mov sp, r7 + 800c0b0: bd80 pop {r7, pc} + 800c0b2: bf00 nop + 800c0b4: 20000b64 .word 0x20000b64 + 800c0b8: 20000b54 .word 0x20000b54 + +0800c0bc : + +static void App_StartNextTxIfPossible(void) +{ + 800c0bc: b598 push {r3, r4, r7, lr} + 800c0be: af00 add r7, sp, #0 + if ((g_mode != APP_MODE_DATA) || (g_radio_busy != 0U) || (g_tx_q_count == 0U)) + 800c0c0: 4b15 ldr r3, [pc, #84] @ (800c118 ) + 800c0c2: 781b ldrb r3, [r3, #0] + 800c0c4: 2b00 cmp r3, #0 + 800c0c6: d124 bne.n 800c112 + 800c0c8: 4b14 ldr r3, [pc, #80] @ (800c11c ) + 800c0ca: 781b ldrb r3, [r3, #0] + 800c0cc: b2db uxtb r3, r3 + 800c0ce: 2b00 cmp r3, #0 + 800c0d0: d11f bne.n 800c112 + 800c0d2: 4b13 ldr r3, [pc, #76] @ (800c120 ) + 800c0d4: 781b ldrb r3, [r3, #0] + 800c0d6: 2b00 cmp r3, #0 + 800c0d8: d01b beq.n 800c112 + { + return; + } + + App_RadioConfigureTx(); + 800c0da: f000 f891 bl 800c200 + g_radio_busy = 1U; + 800c0de: 4b0f ldr r3, [pc, #60] @ (800c11c ) + 800c0e0: 2201 movs r2, #1 + 800c0e2: 701a strb r2, [r3, #0] + (void)Radio.Send(g_tx_queue[g_tx_q_head].data, g_tx_queue[g_tx_q_head].len); + 800c0e4: 4b0f ldr r3, [pc, #60] @ (800c124 ) + 800c0e6: 6a9b ldr r3, [r3, #40] @ 0x28 + 800c0e8: 4a0f ldr r2, [pc, #60] @ (800c128 ) + 800c0ea: 7812 ldrb r2, [r2, #0] + 800c0ec: 4611 mov r1, r2 + 800c0ee: 22dd movs r2, #221 @ 0xdd + 800c0f0: fb01 f202 mul.w r2, r1, r2 + 800c0f4: 490d ldr r1, [pc, #52] @ (800c12c ) + 800c0f6: 1850 adds r0, r2, r1 + 800c0f8: 4a0b ldr r2, [pc, #44] @ (800c128 ) + 800c0fa: 7812 ldrb r2, [r2, #0] + 800c0fc: 4614 mov r4, r2 + 800c0fe: 490b ldr r1, [pc, #44] @ (800c12c ) + 800c100: 22dd movs r2, #221 @ 0xdd + 800c102: fb04 f202 mul.w r2, r4, r2 + 800c106: 440a add r2, r1 + 800c108: 32dc adds r2, #220 @ 0xdc + 800c10a: 7812 ldrb r2, [r2, #0] + 800c10c: 4611 mov r1, r2 + 800c10e: 4798 blx r3 + 800c110: e000 b.n 800c114 + return; + 800c112: bf00 nop +} + 800c114: bd98 pop {r3, r4, r7, pc} + 800c116: bf00 nop + 800c118: 20000b64 .word 0x20000b64 + 800c11c: 20000615 .word 0x20000615 + 800c120: 20000a6e .word 0x20000a6e + 800c124: 0800fb7c .word 0x0800fb7c + 800c128: 20000a6c .word 0x20000a6c + 800c12c: 200006f8 .word 0x200006f8 + +0800c130 : + +static void App_RadioApplyConfig(void) +{ + 800c130: b580 push {r7, lr} + 800c132: af00 add r7, sp, #0 + Radio.SetChannel(g_cfg.rf_frequency); + 800c134: 4b05 ldr r3, [pc, #20] @ (800c14c ) + 800c136: 68db ldr r3, [r3, #12] + 800c138: 4a05 ldr r2, [pc, #20] @ (800c150 ) + 800c13a: 6812 ldr r2, [r2, #0] + 800c13c: 4610 mov r0, r2 + 800c13e: 4798 blx r3 + g_radio_needs_rx_restart = 1U; + 800c140: 4b04 ldr r3, [pc, #16] @ (800c154 ) + 800c142: 2201 movs r2, #1 + 800c144: 701a strb r2, [r3, #0] +} + 800c146: bf00 nop + 800c148: bd80 pop {r7, pc} + 800c14a: bf00 nop + 800c14c: 0800fb7c .word 0x0800fb7c + 800c150: 2000000c .word 0x2000000c + 800c154: 20000616 .word 0x20000616 + +0800c158 : + +static void App_RadioConfigureRx(void) +{ + 800c158: b590 push {r4, r7, lr} + 800c15a: b08f sub sp, #60 @ 0x3c + 800c15c: af00 add r7, sp, #0 + RxConfigGeneric_t rx = {0}; + 800c15e: 463b mov r3, r7 + 800c160: 2238 movs r2, #56 @ 0x38 + 800c162: 2100 movs r1, #0 + 800c164: 4618 mov r0, r3 + 800c166: f002 fb0f bl 800e788 + + Radio.SetChannel(g_cfg.rf_frequency); + 800c16a: 4b22 ldr r3, [pc, #136] @ (800c1f4 ) + 800c16c: 68db ldr r3, [r3, #12] + 800c16e: 4a22 ldr r2, [pc, #136] @ (800c1f8 ) + 800c170: 6812 ldr r2, [r2, #0] + 800c172: 4610 mov r0, r2 + 800c174: 4798 blx r3 + + rx.fsk.ModulationShaping = RADIO_FSK_MOD_SHAPING_G_BT_05; + 800c176: 2309 movs r3, #9 + 800c178: f887 3020 strb.w r3, [r7, #32] + rx.fsk.Bandwidth = g_cfg.fsk_bandwidth; + 800c17c: 4b1e ldr r3, [pc, #120] @ (800c1f8 ) + 800c17e: 68db ldr r3, [r3, #12] + 800c180: 607b str r3, [r7, #4] + rx.fsk.BitRate = g_cfg.fsk_bitrate; + 800c182: 4b1d ldr r3, [pc, #116] @ (800c1f8 ) + 800c184: 689b ldr r3, [r3, #8] + 800c186: 60bb str r3, [r7, #8] + rx.fsk.PreambleLen = g_cfg.fsk_preamble_len; + 800c188: 4b1b ldr r3, [pc, #108] @ (800c1f8 ) + 800c18a: 8a9b ldrh r3, [r3, #20] + 800c18c: 60fb str r3, [r7, #12] + rx.fsk.SyncWordLength = RADIO_SYNCWORD_LEN; + 800c18e: 2303 movs r3, #3 + 800c190: 77bb strb r3, [r7, #30] + rx.fsk.PreambleMinDetect = RADIO_FSK_PREAMBLE_DETECTOR_08_BITS; + 800c192: 2304 movs r3, #4 + 800c194: 77fb strb r3, [r7, #31] + rx.fsk.SyncWord = g_cfg.syncword; + 800c196: 4b19 ldr r3, [pc, #100] @ (800c1fc ) + 800c198: 613b str r3, [r7, #16] + rx.fsk.whiteSeed = RADIO_WHITENING_SEED; + 800c19a: f240 13ff movw r3, #511 @ 0x1ff + 800c19e: 83bb strh r3, [r7, #28] + rx.fsk.LengthMode = RADIO_FSK_PACKET_VARIABLE_LENGTH; + 800c1a0: 2301 movs r3, #1 + 800c1a2: f887 3022 strb.w r3, [r7, #34] @ 0x22 + rx.fsk.CrcLength = RADIO_FSK_CRC_2_BYTES_IBM; + 800c1a6: 23f1 movs r3, #241 @ 0xf1 + 800c1a8: f887 3023 strb.w r3, [r7, #35] @ 0x23 + rx.fsk.CrcPolynomial = RADIO_CRC_POLY; + 800c1ac: f248 0305 movw r3, #32773 @ 0x8005 + 800c1b0: 833b strh r3, [r7, #24] + rx.fsk.CrcSeed = RADIO_CRC_SEED; + 800c1b2: f64f 73ff movw r3, #65535 @ 0xffff + 800c1b6: 837b strh r3, [r7, #26] + rx.fsk.Whitening = RADIO_FSK_DC_FREEWHITENING; + 800c1b8: 2301 movs r3, #1 + 800c1ba: f887 3024 strb.w r3, [r7, #36] @ 0x24 + rx.fsk.MaxPayloadLength = RADIO_MAX_PAYLOAD_SIZE; + 800c1be: 23dc movs r3, #220 @ 0xdc + 800c1c0: 617b str r3, [r7, #20] + rx.fsk.StopTimerOnPreambleDetect = 0; + 800c1c2: 2300 movs r3, #0 + 800c1c4: 603b str r3, [r7, #0] + rx.fsk.AddrComp = RADIO_FSK_ADDRESSCOMP_FILT_OFF; + 800c1c6: 2300 movs r3, #0 + 800c1c8: f887 3021 strb.w r3, [r7, #33] @ 0x21 + + Radio.Standby(); + 800c1cc: 4b09 ldr r3, [pc, #36] @ (800c1f4 ) + 800c1ce: 6b1b ldr r3, [r3, #48] @ 0x30 + 800c1d0: 4798 blx r3 + if (0UL != Radio.RadioSetRxGenericConfig(GENERIC_FSK, &rx, RX_CONTINUOUS_ON, 0U)) + 800c1d2: 4b08 ldr r3, [pc, #32] @ (800c1f4 ) + 800c1d4: 6f5c ldr r4, [r3, #116] @ 0x74 + 800c1d6: 4639 mov r1, r7 + 800c1d8: 2300 movs r3, #0 + 800c1da: 2201 movs r2, #1 + 800c1dc: 2000 movs r0, #0 + 800c1de: 47a0 blx r4 + 800c1e0: 4603 mov r3, r0 + 800c1e2: 2b00 cmp r3, #0 + 800c1e4: d001 beq.n 800c1ea + { + Error_Handler(); + 800c1e6: f7f4 faf3 bl 80007d0 + } +} + 800c1ea: bf00 nop + 800c1ec: 373c adds r7, #60 @ 0x3c + 800c1ee: 46bd mov sp, r7 + 800c1f0: bd90 pop {r4, r7, pc} + 800c1f2: bf00 nop + 800c1f4: 0800fb7c .word 0x0800fb7c + 800c1f8: 2000000c .word 0x2000000c + 800c1fc: 20000022 .word 0x20000022 + +0800c200 : + +static void App_RadioConfigureTx(void) +{ + 800c200: b590 push {r4, r7, lr} + 800c202: b089 sub sp, #36 @ 0x24 + 800c204: af00 add r7, sp, #0 + TxConfigGeneric_t tx = {0}; + 800c206: 1d3b adds r3, r7, #4 + 800c208: 2200 movs r2, #0 + 800c20a: 601a str r2, [r3, #0] + 800c20c: 605a str r2, [r3, #4] + 800c20e: 609a str r2, [r3, #8] + 800c210: 60da str r2, [r3, #12] + 800c212: 611a str r2, [r3, #16] + 800c214: 615a str r2, [r3, #20] + 800c216: 619a str r2, [r3, #24] + + Radio.SetChannel(g_cfg.rf_frequency); + 800c218: 4b1c ldr r3, [pc, #112] @ (800c28c ) + 800c21a: 68db ldr r3, [r3, #12] + 800c21c: 4a1c ldr r2, [pc, #112] @ (800c290 ) + 800c21e: 6812 ldr r2, [r2, #0] + 800c220: 4610 mov r0, r2 + 800c222: 4798 blx r3 + + tx.fsk.ModulationShaping = RADIO_FSK_MOD_SHAPING_G_BT_05; + 800c224: 2309 movs r3, #9 + 800c226: 75fb strb r3, [r7, #23] + tx.fsk.FrequencyDeviation = g_cfg.fsk_fdev; + 800c228: 4b19 ldr r3, [pc, #100] @ (800c290 ) + 800c22a: 691b ldr r3, [r3, #16] + 800c22c: 61fb str r3, [r7, #28] + tx.fsk.BitRate = g_cfg.fsk_bitrate; + 800c22e: 4b18 ldr r3, [pc, #96] @ (800c290 ) + 800c230: 689b ldr r3, [r3, #8] + 800c232: 607b str r3, [r7, #4] + tx.fsk.PreambleLen = g_cfg.fsk_preamble_len; + 800c234: 4b16 ldr r3, [pc, #88] @ (800c290 ) + 800c236: 8a9b ldrh r3, [r3, #20] + 800c238: 60bb str r3, [r7, #8] + tx.fsk.SyncWordLength = RADIO_SYNCWORD_LEN; + 800c23a: 2303 movs r3, #3 + 800c23c: 75bb strb r3, [r7, #22] + tx.fsk.SyncWord = g_cfg.syncword; + 800c23e: 4b15 ldr r3, [pc, #84] @ (800c294 ) + 800c240: 60fb str r3, [r7, #12] + tx.fsk.whiteSeed = RADIO_WHITENING_SEED; + 800c242: f240 13ff movw r3, #511 @ 0x1ff + 800c246: 82bb strh r3, [r7, #20] + tx.fsk.HeaderType = RADIO_FSK_PACKET_VARIABLE_LENGTH; + 800c248: 2301 movs r3, #1 + 800c24a: 763b strb r3, [r7, #24] + tx.fsk.CrcLength = RADIO_FSK_CRC_2_BYTES_IBM; + 800c24c: 23f1 movs r3, #241 @ 0xf1 + 800c24e: 767b strb r3, [r7, #25] + tx.fsk.CrcPolynomial = RADIO_CRC_POLY; + 800c250: f248 0305 movw r3, #32773 @ 0x8005 + 800c254: 823b strh r3, [r7, #16] + tx.fsk.CrcSeed = RADIO_CRC_SEED; + 800c256: f64f 73ff movw r3, #65535 @ 0xffff + 800c25a: 827b strh r3, [r7, #18] + tx.fsk.Whitening = RADIO_FSK_DC_FREEWHITENING; + 800c25c: 2301 movs r3, #1 + 800c25e: 76bb strb r3, [r7, #26] + + Radio.Standby(); + 800c260: 4b0a ldr r3, [pc, #40] @ (800c28c ) + 800c262: 6b1b ldr r3, [r3, #48] @ 0x30 + 800c264: 4798 blx r3 + if (0UL != Radio.RadioSetTxGenericConfig(GENERIC_FSK, &tx, g_cfg.tx_power, TX_TIMEOUT_VALUE_MS)) + 800c266: 4b09 ldr r3, [pc, #36] @ (800c28c ) + 800c268: 6f9c ldr r4, [r3, #120] @ 0x78 + 800c26a: 4b09 ldr r3, [pc, #36] @ (800c290 ) + 800c26c: f993 2004 ldrsb.w r2, [r3, #4] + 800c270: 1d39 adds r1, r7, #4 + 800c272: f640 33b8 movw r3, #3000 @ 0xbb8 + 800c276: 2000 movs r0, #0 + 800c278: 47a0 blx r4 + 800c27a: 4603 mov r3, r0 + 800c27c: 2b00 cmp r3, #0 + 800c27e: d001 beq.n 800c284 + { + Error_Handler(); + 800c280: f7f4 faa6 bl 80007d0 + } +} + 800c284: bf00 nop + 800c286: 3724 adds r7, #36 @ 0x24 + 800c288: 46bd mov sp, r7 + 800c28a: bd90 pop {r4, r7, pc} + 800c28c: 0800fb7c .word 0x0800fb7c + 800c290: 2000000c .word 0x2000000c + 800c294: 20000022 .word 0x20000022 + +0800c298 : + +static void App_RadioEnterRx(void) +{ + 800c298: b580 push {r7, lr} + 800c29a: af00 add r7, sp, #0 + App_RadioConfigureRx(); + 800c29c: f7ff ff5c bl 800c158 + Radio.Rx(RX_TIMEOUT_VALUE_MS); + 800c2a0: 4b02 ldr r3, [pc, #8] @ (800c2ac ) + 800c2a2: 6b5b ldr r3, [r3, #52] @ 0x34 + 800c2a4: 2000 movs r0, #0 + 800c2a6: 4798 blx r3 +} + 800c2a8: bf00 nop + 800c2aa: bd80 pop {r7, pc} + 800c2ac: 0800fb7c .word 0x0800fb7c + +0800c2b0 : + +static void App_EnterConfigMode(void) +{ + 800c2b0: b580 push {r7, lr} + 800c2b2: af00 add r7, sp, #0 + App_ResetDataPath(); + 800c2b4: f000 f82e bl 800c314 + g_mode = APP_MODE_CONFIG; + 800c2b8: 4b06 ldr r3, [pc, #24] @ (800c2d4 ) + 800c2ba: 2201 movs r2, #1 + 800c2bc: 701a strb r2, [r3, #0] + App_Printf("\r\n\r\n[CONFIG MODE]\r\n"); + 800c2be: 4806 ldr r0, [pc, #24] @ (800c2d8 ) + 800c2c0: f000 fd5e bl 800cd80 + App_Printf("type 'help' for commands\r\n"); + 800c2c4: 4805 ldr r0, [pc, #20] @ (800c2dc ) + 800c2c6: f000 fd5b bl 800cd80 + App_PrintConfigPrompt(); + 800c2ca: f000 fc45 bl 800cb58 +} + 800c2ce: bf00 nop + 800c2d0: bd80 pop {r7, pc} + 800c2d2: bf00 nop + 800c2d4: 20000b64 .word 0x20000b64 + 800c2d8: 0800f388 .word 0x0800f388 + 800c2dc: 0800f39c .word 0x0800f39c + +0800c2e0 : + +static void App_ExitConfigMode(void) +{ + 800c2e0: b580 push {r7, lr} + 800c2e2: af00 add r7, sp, #0 + g_cfg_line_len = 0U; + 800c2e4: 4b07 ldr r3, [pc, #28] @ (800c304 ) + 800c2e6: 2200 movs r2, #0 + 800c2e8: 801a strh r2, [r3, #0] + App_ResetDataPath(); + 800c2ea: f000 f813 bl 800c314 + g_mode = APP_MODE_DATA; + 800c2ee: 4b06 ldr r3, [pc, #24] @ (800c308 ) + 800c2f0: 2200 movs r2, #0 + 800c2f2: 701a strb r2, [r3, #0] + App_Printf("\r\n[DATA MODE]\r\n"); + 800c2f4: 4805 ldr r0, [pc, #20] @ (800c30c ) + 800c2f6: f000 fd43 bl 800cd80 + g_radio_needs_rx_restart = 1U; + 800c2fa: 4b05 ldr r3, [pc, #20] @ (800c310 ) + 800c2fc: 2201 movs r2, #1 + 800c2fe: 701a strb r2, [r3, #0] +} + 800c300: bf00 nop + 800c302: bd80 pop {r7, pc} + 800c304: 20000bc8 .word 0x20000bc8 + 800c308: 20000b64 .word 0x20000b64 + 800c30c: 0800f3b8 .word 0x0800f3b8 + 800c310: 20000616 .word 0x20000616 + +0800c314 : + +static void App_ResetDataPath(void) +{ + 800c314: b480 push {r7} + 800c316: af00 add r7, sp, #0 + g_uart_build_len = 0U; + 800c318: 4b0a ldr r3, [pc, #40] @ (800c344 ) + 800c31a: 2200 movs r2, #0 + 800c31c: 801a strh r2, [r3, #0] + g_escape.active = 0U; + 800c31e: 4b0a ldr r3, [pc, #40] @ (800c348 ) + 800c320: 2200 movs r2, #0 + 800c322: 701a strb r2, [r3, #0] + g_escape.count = 0U; + 800c324: 4b08 ldr r3, [pc, #32] @ (800c348 ) + 800c326: 2200 movs r2, #0 + 800c328: 705a strb r2, [r3, #1] + g_tx_q_head = 0U; + 800c32a: 4b08 ldr r3, [pc, #32] @ (800c34c ) + 800c32c: 2200 movs r2, #0 + 800c32e: 701a strb r2, [r3, #0] + g_tx_q_tail = 0U; + 800c330: 4b07 ldr r3, [pc, #28] @ (800c350 ) + 800c332: 2200 movs r2, #0 + 800c334: 701a strb r2, [r3, #0] + g_tx_q_count = 0U; + 800c336: 4b07 ldr r3, [pc, #28] @ (800c354 ) + 800c338: 2200 movs r2, #0 + 800c33a: 701a strb r2, [r3, #0] +} + 800c33c: bf00 nop + 800c33e: 46bd mov sp, r7 + 800c340: bc80 pop {r7} + 800c342: 4770 bx lr + 800c344: 20000b4c .word 0x20000b4c + 800c348: 20000b54 .word 0x20000b54 + 800c34c: 20000a6c .word 0x20000a6c + 800c350: 20000a6d .word 0x20000a6d + 800c354: 20000a6e .word 0x20000a6e + +0800c358 : + +static void App_DataModeFeedByte(uint8_t ch, uint32_t now) +{ + 800c358: b580 push {r7, lr} + 800c35a: b082 sub sp, #8 + 800c35c: af00 add r7, sp, #0 + 800c35e: 4603 mov r3, r0 + 800c360: 6039 str r1, [r7, #0] + 800c362: 71fb strb r3, [r7, #7] + if (g_uart_build_len < UART_DATA_BUFFER_SIZE) + 800c364: 4b19 ldr r3, [pc, #100] @ (800c3cc ) + 800c366: 881b ldrh r3, [r3, #0] + 800c368: 2bdb cmp r3, #219 @ 0xdb + 800c36a: d812 bhi.n 800c392 + { + g_uart_build_buf[g_uart_build_len++] = ch; + 800c36c: 4b17 ldr r3, [pc, #92] @ (800c3cc ) + 800c36e: 881b ldrh r3, [r3, #0] + 800c370: 1c5a adds r2, r3, #1 + 800c372: b291 uxth r1, r2 + 800c374: 4a15 ldr r2, [pc, #84] @ (800c3cc ) + 800c376: 8011 strh r1, [r2, #0] + 800c378: 4619 mov r1, r3 + 800c37a: 4a15 ldr r2, [pc, #84] @ (800c3d0 ) + 800c37c: 79fb ldrb r3, [r7, #7] + 800c37e: 5453 strb r3, [r2, r1] + g_uart_last_data_tick = now; + 800c380: 4a14 ldr r2, [pc, #80] @ (800c3d4 ) + 800c382: 683b ldr r3, [r7, #0] + 800c384: 6013 str r3, [r2, #0] + g_stat_uart_bytes_tx++; + 800c386: 4b14 ldr r3, [pc, #80] @ (800c3d8 ) + 800c388: 681b ldr r3, [r3, #0] + 800c38a: 3301 adds r3, #1 + 800c38c: 4a12 ldr r2, [pc, #72] @ (800c3d8 ) + 800c38e: 6013 str r3, [r2, #0] + g_uart_build_buf[g_uart_build_len++] = ch; + g_uart_last_data_tick = now; + g_stat_uart_bytes_tx++; + } + } +} + 800c390: e017 b.n 800c3c2 + App_DataModeFlushBuilder(); + 800c392: f000 f823 bl 800c3dc + if (g_uart_build_len < UART_DATA_BUFFER_SIZE) + 800c396: 4b0d ldr r3, [pc, #52] @ (800c3cc ) + 800c398: 881b ldrh r3, [r3, #0] + 800c39a: 2bdb cmp r3, #219 @ 0xdb + 800c39c: d811 bhi.n 800c3c2 + g_uart_build_buf[g_uart_build_len++] = ch; + 800c39e: 4b0b ldr r3, [pc, #44] @ (800c3cc ) + 800c3a0: 881b ldrh r3, [r3, #0] + 800c3a2: 1c5a adds r2, r3, #1 + 800c3a4: b291 uxth r1, r2 + 800c3a6: 4a09 ldr r2, [pc, #36] @ (800c3cc ) + 800c3a8: 8011 strh r1, [r2, #0] + 800c3aa: 4619 mov r1, r3 + 800c3ac: 4a08 ldr r2, [pc, #32] @ (800c3d0 ) + 800c3ae: 79fb ldrb r3, [r7, #7] + 800c3b0: 5453 strb r3, [r2, r1] + g_uart_last_data_tick = now; + 800c3b2: 4a08 ldr r2, [pc, #32] @ (800c3d4 ) + 800c3b4: 683b ldr r3, [r7, #0] + 800c3b6: 6013 str r3, [r2, #0] + g_stat_uart_bytes_tx++; + 800c3b8: 4b07 ldr r3, [pc, #28] @ (800c3d8 ) + 800c3ba: 681b ldr r3, [r3, #0] + 800c3bc: 3301 adds r3, #1 + 800c3be: 4a06 ldr r2, [pc, #24] @ (800c3d8 ) + 800c3c0: 6013 str r3, [r2, #0] +} + 800c3c2: bf00 nop + 800c3c4: 3708 adds r7, #8 + 800c3c6: 46bd mov sp, r7 + 800c3c8: bd80 pop {r7, pc} + 800c3ca: bf00 nop + 800c3cc: 20000b4c .word 0x20000b4c + 800c3d0: 20000a70 .word 0x20000a70 + 800c3d4: 20000b50 .word 0x20000b50 + 800c3d8: 20000bd0 .word 0x20000bd0 + +0800c3dc : + +static void App_DataModeFlushBuilder(void) +{ + 800c3dc: b580 push {r7, lr} + 800c3de: af00 add r7, sp, #0 + if (g_uart_build_len == 0U) + 800c3e0: 4b0b ldr r3, [pc, #44] @ (800c410 ) + 800c3e2: 881b ldrh r3, [r3, #0] + 800c3e4: 2b00 cmp r3, #0 + 800c3e6: d011 beq.n 800c40c + { + return; + } + + if (App_QueuePush(g_uart_build_buf, g_uart_build_len) == 0U) + 800c3e8: 4b09 ldr r3, [pc, #36] @ (800c410 ) + 800c3ea: 881b ldrh r3, [r3, #0] + 800c3ec: 4619 mov r1, r3 + 800c3ee: 4809 ldr r0, [pc, #36] @ (800c414 ) + 800c3f0: f000 f814 bl 800c41c + 800c3f4: 4603 mov r3, r0 + 800c3f6: 2b00 cmp r3, #0 + 800c3f8: d104 bne.n 800c404 + { + g_stat_queue_overflow++; + 800c3fa: 4b07 ldr r3, [pc, #28] @ (800c418 ) + 800c3fc: 681b ldr r3, [r3, #0] + 800c3fe: 3301 adds r3, #1 + 800c400: 4a05 ldr r2, [pc, #20] @ (800c418 ) + 800c402: 6013 str r3, [r2, #0] + } + g_uart_build_len = 0U; + 800c404: 4b02 ldr r3, [pc, #8] @ (800c410 ) + 800c406: 2200 movs r2, #0 + 800c408: 801a strh r2, [r3, #0] + 800c40a: e000 b.n 800c40e + return; + 800c40c: bf00 nop +} + 800c40e: bd80 pop {r7, pc} + 800c410: 20000b4c .word 0x20000b4c + 800c414: 20000a70 .word 0x20000a70 + 800c418: 20000bdc .word 0x20000bdc + +0800c41c : + +static uint8_t App_QueuePush(const uint8_t *data, uint16_t len) +{ + 800c41c: b580 push {r7, lr} + 800c41e: b082 sub sp, #8 + 800c420: af00 add r7, sp, #0 + 800c422: 6078 str r0, [r7, #4] + 800c424: 460b mov r3, r1 + 800c426: 807b strh r3, [r7, #2] + if ((len == 0U) || (len > RADIO_MAX_PAYLOAD_SIZE) || (g_tx_q_count >= TX_QUEUE_DEPTH)) + 800c428: 887b ldrh r3, [r7, #2] + 800c42a: 2b00 cmp r3, #0 + 800c42c: d006 beq.n 800c43c + 800c42e: 887b ldrh r3, [r7, #2] + 800c430: 2bdc cmp r3, #220 @ 0xdc + 800c432: d803 bhi.n 800c43c + 800c434: 4b19 ldr r3, [pc, #100] @ (800c49c ) + 800c436: 781b ldrb r3, [r3, #0] + 800c438: 2b03 cmp r3, #3 + 800c43a: d901 bls.n 800c440 + { + return 0U; + 800c43c: 2300 movs r3, #0 + 800c43e: e029 b.n 800c494 + } + + memcpy(g_tx_queue[g_tx_q_tail].data, data, len); + 800c440: 4b17 ldr r3, [pc, #92] @ (800c4a0 ) + 800c442: 781b ldrb r3, [r3, #0] + 800c444: 461a mov r2, r3 + 800c446: 23dd movs r3, #221 @ 0xdd + 800c448: fb02 f303 mul.w r3, r2, r3 + 800c44c: 4a15 ldr r2, [pc, #84] @ (800c4a4 ) + 800c44e: 4413 add r3, r2 + 800c450: 887a ldrh r2, [r7, #2] + 800c452: 6879 ldr r1, [r7, #4] + 800c454: 4618 mov r0, r3 + 800c456: f002 f9dd bl 800e814 + g_tx_queue[g_tx_q_tail].len = (uint8_t)len; + 800c45a: 4b11 ldr r3, [pc, #68] @ (800c4a0 ) + 800c45c: 781b ldrb r3, [r3, #0] + 800c45e: 4618 mov r0, r3 + 800c460: 887b ldrh r3, [r7, #2] + 800c462: b2d9 uxtb r1, r3 + 800c464: 4a0f ldr r2, [pc, #60] @ (800c4a4 ) + 800c466: 23dd movs r3, #221 @ 0xdd + 800c468: fb00 f303 mul.w r3, r0, r3 + 800c46c: 4413 add r3, r2 + 800c46e: 33dc adds r3, #220 @ 0xdc + 800c470: 460a mov r2, r1 + 800c472: 701a strb r2, [r3, #0] + g_tx_q_tail = (uint8_t)((g_tx_q_tail + 1U) % TX_QUEUE_DEPTH); + 800c474: 4b0a ldr r3, [pc, #40] @ (800c4a0 ) + 800c476: 781b ldrb r3, [r3, #0] + 800c478: 3301 adds r3, #1 + 800c47a: b2db uxtb r3, r3 + 800c47c: f003 0303 and.w r3, r3, #3 + 800c480: b2da uxtb r2, r3 + 800c482: 4b07 ldr r3, [pc, #28] @ (800c4a0 ) + 800c484: 701a strb r2, [r3, #0] + g_tx_q_count++; + 800c486: 4b05 ldr r3, [pc, #20] @ (800c49c ) + 800c488: 781b ldrb r3, [r3, #0] + 800c48a: 3301 adds r3, #1 + 800c48c: b2da uxtb r2, r3 + 800c48e: 4b03 ldr r3, [pc, #12] @ (800c49c ) + 800c490: 701a strb r2, [r3, #0] + return 1U; + 800c492: 2301 movs r3, #1 +} + 800c494: 4618 mov r0, r3 + 800c496: 3708 adds r7, #8 + 800c498: 46bd mov sp, r7 + 800c49a: bd80 pop {r7, pc} + 800c49c: 20000a6e .word 0x20000a6e + 800c4a0: 20000a6d .word 0x20000a6d + 800c4a4: 200006f8 .word 0x200006f8 + +0800c4a8 : + +static void App_QueuePop(void) +{ + 800c4a8: b480 push {r7} + 800c4aa: af00 add r7, sp, #0 + if (g_tx_q_count == 0U) + 800c4ac: 4b0b ldr r3, [pc, #44] @ (800c4dc ) + 800c4ae: 781b ldrb r3, [r3, #0] + 800c4b0: 2b00 cmp r3, #0 + 800c4b2: d00f beq.n 800c4d4 + { + return; + } + + g_tx_q_head = (uint8_t)((g_tx_q_head + 1U) % TX_QUEUE_DEPTH); + 800c4b4: 4b0a ldr r3, [pc, #40] @ (800c4e0 ) + 800c4b6: 781b ldrb r3, [r3, #0] + 800c4b8: 3301 adds r3, #1 + 800c4ba: b2db uxtb r3, r3 + 800c4bc: f003 0303 and.w r3, r3, #3 + 800c4c0: b2da uxtb r2, r3 + 800c4c2: 4b07 ldr r3, [pc, #28] @ (800c4e0 ) + 800c4c4: 701a strb r2, [r3, #0] + g_tx_q_count--; + 800c4c6: 4b05 ldr r3, [pc, #20] @ (800c4dc ) + 800c4c8: 781b ldrb r3, [r3, #0] + 800c4ca: 3b01 subs r3, #1 + 800c4cc: b2da uxtb r2, r3 + 800c4ce: 4b03 ldr r3, [pc, #12] @ (800c4dc ) + 800c4d0: 701a strb r2, [r3, #0] + 800c4d2: e000 b.n 800c4d6 + return; + 800c4d4: bf00 nop +} + 800c4d6: 46bd mov sp, r7 + 800c4d8: bc80 pop {r7} + 800c4da: 4770 bx lr + 800c4dc: 20000a6e .word 0x20000a6e + 800c4e0: 20000a6c .word 0x20000a6c + +0800c4e4 : + +static void UartRxByteCallback(uint8_t *rxChar, uint16_t size, uint8_t error) +{ + 800c4e4: b580 push {r7, lr} + 800c4e6: b084 sub sp, #16 + 800c4e8: af00 add r7, sp, #0 + 800c4ea: 6078 str r0, [r7, #4] + 800c4ec: 460b mov r3, r1 + 800c4ee: 807b strh r3, [r7, #2] + 800c4f0: 4613 mov r3, r2 + 800c4f2: 707b strb r3, [r7, #1] + uint8_t ch; + uint32_t now; + uint8_t i; + + if ((error != 0U) || (size == 0U) || (rxChar == NULL)) + 800c4f4: 787b ldrb r3, [r7, #1] + 800c4f6: 2b00 cmp r3, #0 + 800c4f8: f040 808a bne.w 800c610 + 800c4fc: 887b ldrh r3, [r7, #2] + 800c4fe: 2b00 cmp r3, #0 + 800c500: f000 8086 beq.w 800c610 + 800c504: 687b ldr r3, [r7, #4] + 800c506: 2b00 cmp r3, #0 + 800c508: f000 8082 beq.w 800c610 + { + return; + } + + ch = rxChar[0]; + 800c50c: 687b ldr r3, [r7, #4] + 800c50e: 781b ldrb r3, [r3, #0] + 800c510: 73bb strb r3, [r7, #14] + now = HAL_GetTick(); + 800c512: f7f4 fb99 bl 8000c48 + 800c516: 60b8 str r0, [r7, #8] + + if (g_mode == APP_MODE_CONFIG) + 800c518: 4b3f ldr r3, [pc, #252] @ (800c618 ) + 800c51a: 781b ldrb r3, [r3, #0] + 800c51c: 2b01 cmp r3, #1 + 800c51e: d104 bne.n 800c52a + { + App_ConfigFeedByte(ch); + 800c520: 7bbb ldrb r3, [r7, #14] + 800c522: 4618 mov r0, r3 + 800c524: f000 f87e bl 800c624 + return; + 800c528: e073 b.n 800c612 + } + + if (g_escape.active == 0U) + 800c52a: 4b3c ldr r3, [pc, #240] @ (800c61c ) + 800c52c: 781b ldrb r3, [r3, #0] + 800c52e: 2b00 cmp r3, #0 + 800c530: d11f bne.n 800c572 + { + if (((now - g_uart_last_data_tick) >= CONFIG_ESCAPE_GUARD_MS) && (ch == '+')) + 800c532: 4b3b ldr r3, [pc, #236] @ (800c620 ) + 800c534: 681b ldr r3, [r3, #0] + 800c536: 68ba ldr r2, [r7, #8] + 800c538: 1ad3 subs r3, r2, r3 + 800c53a: f5b3 7f48 cmp.w r3, #800 @ 0x320 + 800c53e: d312 bcc.n 800c566 + 800c540: 7bbb ldrb r3, [r7, #14] + 800c542: 2b2b cmp r3, #43 @ 0x2b + 800c544: d10f bne.n 800c566 + { + g_escape.active = 1U; + 800c546: 4b35 ldr r3, [pc, #212] @ (800c61c ) + 800c548: 2201 movs r2, #1 + 800c54a: 701a strb r2, [r3, #0] + g_escape.count = 1U; + 800c54c: 4b33 ldr r3, [pc, #204] @ (800c61c ) + 800c54e: 2201 movs r2, #1 + 800c550: 705a strb r2, [r3, #1] + g_escape.bytes[0] = ch; + 800c552: 4a32 ldr r2, [pc, #200] @ (800c61c ) + 800c554: 7bbb ldrb r3, [r7, #14] + 800c556: 7093 strb r3, [r2, #2] + g_escape.start_tick = now; + 800c558: 4a30 ldr r2, [pc, #192] @ (800c61c ) + 800c55a: 68bb ldr r3, [r7, #8] + 800c55c: 6093 str r3, [r2, #8] + g_escape.last_tick = now; + 800c55e: 4a2f ldr r2, [pc, #188] @ (800c61c ) + 800c560: 68bb ldr r3, [r7, #8] + 800c562: 60d3 str r3, [r2, #12] + return; + 800c564: e055 b.n 800c612 + } + + App_DataModeFeedByte(ch, now); + 800c566: 7bbb ldrb r3, [r7, #14] + 800c568: 68b9 ldr r1, [r7, #8] + 800c56a: 4618 mov r0, r3 + 800c56c: f7ff fef4 bl 800c358 + return; + 800c570: e04f b.n 800c612 + } + + if ((ch == '+') && (g_escape.count < 3U)) + 800c572: 7bbb ldrb r3, [r7, #14] + 800c574: 2b2b cmp r3, #43 @ 0x2b + 800c576: d112 bne.n 800c59e + 800c578: 4b28 ldr r3, [pc, #160] @ (800c61c ) + 800c57a: 785b ldrb r3, [r3, #1] + 800c57c: 2b02 cmp r3, #2 + 800c57e: d80e bhi.n 800c59e + { + g_escape.bytes[g_escape.count++] = ch; + 800c580: 4b26 ldr r3, [pc, #152] @ (800c61c ) + 800c582: 785b ldrb r3, [r3, #1] + 800c584: 1c5a adds r2, r3, #1 + 800c586: b2d1 uxtb r1, r2 + 800c588: 4a24 ldr r2, [pc, #144] @ (800c61c ) + 800c58a: 7051 strb r1, [r2, #1] + 800c58c: 461a mov r2, r3 + 800c58e: 4b23 ldr r3, [pc, #140] @ (800c61c ) + 800c590: 4413 add r3, r2 + 800c592: 7bba ldrb r2, [r7, #14] + 800c594: 709a strb r2, [r3, #2] + g_escape.last_tick = now; + 800c596: 4a21 ldr r2, [pc, #132] @ (800c61c ) + 800c598: 68bb ldr r3, [r7, #8] + 800c59a: 60d3 str r3, [r2, #12] + return; + 800c59c: e039 b.n 800c612 + } + + for (i = 0U; i < g_escape.count; i++) + 800c59e: 2300 movs r3, #0 + 800c5a0: 73fb strb r3, [r7, #15] + 800c5a2: e00a b.n 800c5ba + { + App_DataModeFeedByte(g_escape.bytes[i], now); + 800c5a4: 7bfb ldrb r3, [r7, #15] + 800c5a6: 4a1d ldr r2, [pc, #116] @ (800c61c ) + 800c5a8: 4413 add r3, r2 + 800c5aa: 789b ldrb r3, [r3, #2] + 800c5ac: 68b9 ldr r1, [r7, #8] + 800c5ae: 4618 mov r0, r3 + 800c5b0: f7ff fed2 bl 800c358 + for (i = 0U; i < g_escape.count; i++) + 800c5b4: 7bfb ldrb r3, [r7, #15] + 800c5b6: 3301 adds r3, #1 + 800c5b8: 73fb strb r3, [r7, #15] + 800c5ba: 4b18 ldr r3, [pc, #96] @ (800c61c ) + 800c5bc: 785b ldrb r3, [r3, #1] + 800c5be: 7bfa ldrb r2, [r7, #15] + 800c5c0: 429a cmp r2, r3 + 800c5c2: d3ef bcc.n 800c5a4 + } + g_escape.active = 0U; + 800c5c4: 4b15 ldr r3, [pc, #84] @ (800c61c ) + 800c5c6: 2200 movs r2, #0 + 800c5c8: 701a strb r2, [r3, #0] + g_escape.count = 0U; + 800c5ca: 4b14 ldr r3, [pc, #80] @ (800c61c ) + 800c5cc: 2200 movs r2, #0 + 800c5ce: 705a strb r2, [r3, #1] + + if (((now - g_uart_last_data_tick) >= CONFIG_ESCAPE_GUARD_MS) && (ch == '+')) + 800c5d0: 4b13 ldr r3, [pc, #76] @ (800c620 ) + 800c5d2: 681b ldr r3, [r3, #0] + 800c5d4: 68ba ldr r2, [r7, #8] + 800c5d6: 1ad3 subs r3, r2, r3 + 800c5d8: f5b3 7f48 cmp.w r3, #800 @ 0x320 + 800c5dc: d312 bcc.n 800c604 + 800c5de: 7bbb ldrb r3, [r7, #14] + 800c5e0: 2b2b cmp r3, #43 @ 0x2b + 800c5e2: d10f bne.n 800c604 + { + g_escape.active = 1U; + 800c5e4: 4b0d ldr r3, [pc, #52] @ (800c61c ) + 800c5e6: 2201 movs r2, #1 + 800c5e8: 701a strb r2, [r3, #0] + g_escape.count = 1U; + 800c5ea: 4b0c ldr r3, [pc, #48] @ (800c61c ) + 800c5ec: 2201 movs r2, #1 + 800c5ee: 705a strb r2, [r3, #1] + g_escape.bytes[0] = ch; + 800c5f0: 4a0a ldr r2, [pc, #40] @ (800c61c ) + 800c5f2: 7bbb ldrb r3, [r7, #14] + 800c5f4: 7093 strb r3, [r2, #2] + g_escape.start_tick = now; + 800c5f6: 4a09 ldr r2, [pc, #36] @ (800c61c ) + 800c5f8: 68bb ldr r3, [r7, #8] + 800c5fa: 6093 str r3, [r2, #8] + g_escape.last_tick = now; + 800c5fc: 4a07 ldr r2, [pc, #28] @ (800c61c ) + 800c5fe: 68bb ldr r3, [r7, #8] + 800c600: 60d3 str r3, [r2, #12] + return; + 800c602: e006 b.n 800c612 + } + + App_DataModeFeedByte(ch, now); + 800c604: 7bbb ldrb r3, [r7, #14] + 800c606: 68b9 ldr r1, [r7, #8] + 800c608: 4618 mov r0, r3 + 800c60a: f7ff fea5 bl 800c358 + 800c60e: e000 b.n 800c612 + return; + 800c610: bf00 nop +} + 800c612: 3710 adds r7, #16 + 800c614: 46bd mov sp, r7 + 800c616: bd80 pop {r7, pc} + 800c618: 20000b64 .word 0x20000b64 + 800c61c: 20000b54 .word 0x20000b54 + 800c620: 20000b50 .word 0x20000b50 + +0800c624 : + +static void App_ConfigFeedByte(uint8_t ch) +{ + 800c624: b580 push {r7, lr} + 800c626: b082 sub sp, #8 + 800c628: af00 add r7, sp, #0 + 800c62a: 4603 mov r3, r0 + 800c62c: 71fb strb r3, [r7, #7] + if ((ch == '\r') || (ch == '\n')) + 800c62e: 79fb ldrb r3, [r7, #7] + 800c630: 2b0d cmp r3, #13 + 800c632: d002 beq.n 800c63a + 800c634: 79fb ldrb r3, [r7, #7] + 800c636: 2b0a cmp r3, #10 + 800c638: d115 bne.n 800c666 + { + if (g_cfg_line_len > 0U) + 800c63a: 4b26 ldr r3, [pc, #152] @ (800c6d4 ) + 800c63c: 881b ldrh r3, [r3, #0] + 800c63e: 2b00 cmp r3, #0 + 800c640: d00e beq.n 800c660 + { + g_cfg_line[g_cfg_line_len] = '\0'; + 800c642: 4b24 ldr r3, [pc, #144] @ (800c6d4 ) + 800c644: 881b ldrh r3, [r3, #0] + 800c646: 461a mov r2, r3 + 800c648: 4b23 ldr r3, [pc, #140] @ (800c6d8 ) + 800c64a: 2100 movs r1, #0 + 800c64c: 5499 strb r1, [r3, r2] + App_Printf("\r\n"); + 800c64e: 4823 ldr r0, [pc, #140] @ (800c6dc ) + 800c650: f000 fb96 bl 800cd80 + App_ConfigExecuteLine(g_cfg_line); + 800c654: 4820 ldr r0, [pc, #128] @ (800c6d8 ) + 800c656: f000 f847 bl 800c6e8 + g_cfg_line_len = 0U; + 800c65a: 4b1e ldr r3, [pc, #120] @ (800c6d4 ) + 800c65c: 2200 movs r2, #0 + 800c65e: 801a strh r2, [r3, #0] + } + App_PrintConfigPrompt(); + 800c660: f000 fa7a bl 800cb58 + return; + 800c664: e032 b.n 800c6cc + } + + if ((ch == 0x08U) || (ch == 0x7FU)) + 800c666: 79fb ldrb r3, [r7, #7] + 800c668: 2b08 cmp r3, #8 + 800c66a: d002 beq.n 800c672 + 800c66c: 79fb ldrb r3, [r7, #7] + 800c66e: 2b7f cmp r3, #127 @ 0x7f + 800c670: d10e bne.n 800c690 + { + if (g_cfg_line_len > 0U) + 800c672: 4b18 ldr r3, [pc, #96] @ (800c6d4 ) + 800c674: 881b ldrh r3, [r3, #0] + 800c676: 2b00 cmp r3, #0 + 800c678: d027 beq.n 800c6ca + { + g_cfg_line_len--; + 800c67a: 4b16 ldr r3, [pc, #88] @ (800c6d4 ) + 800c67c: 881b ldrh r3, [r3, #0] + 800c67e: 3b01 subs r3, #1 + 800c680: b29a uxth r2, r3 + 800c682: 4b14 ldr r3, [pc, #80] @ (800c6d4 ) + 800c684: 801a strh r2, [r3, #0] + App_Write((const uint8_t *)"\b \b", 3U); + 800c686: 2103 movs r1, #3 + 800c688: 4815 ldr r0, [pc, #84] @ (800c6e0 ) + 800c68a: f000 fba5 bl 800cdd8 + } + return; + 800c68e: e01c b.n 800c6ca + } + + if ((isprint(ch) != 0) && (g_cfg_line_len < (CONFIG_LINE_SIZE - 1U))) + 800c690: 79fb ldrb r3, [r7, #7] + 800c692: 3301 adds r3, #1 + 800c694: 4a13 ldr r2, [pc, #76] @ (800c6e4 ) + 800c696: 4413 add r3, r2 + 800c698: 781b ldrb r3, [r3, #0] + 800c69a: f003 0397 and.w r3, r3, #151 @ 0x97 + 800c69e: 2b00 cmp r3, #0 + 800c6a0: d014 beq.n 800c6cc + 800c6a2: 4b0c ldr r3, [pc, #48] @ (800c6d4 ) + 800c6a4: 881b ldrh r3, [r3, #0] + 800c6a6: 2b5e cmp r3, #94 @ 0x5e + 800c6a8: d810 bhi.n 800c6cc + { + g_cfg_line[g_cfg_line_len++] = (char)ch; + 800c6aa: 4b0a ldr r3, [pc, #40] @ (800c6d4 ) + 800c6ac: 881b ldrh r3, [r3, #0] + 800c6ae: 1c5a adds r2, r3, #1 + 800c6b0: b291 uxth r1, r2 + 800c6b2: 4a08 ldr r2, [pc, #32] @ (800c6d4 ) + 800c6b4: 8011 strh r1, [r2, #0] + 800c6b6: 461a mov r2, r3 + 800c6b8: 79f9 ldrb r1, [r7, #7] + 800c6ba: 4b07 ldr r3, [pc, #28] @ (800c6d8 ) + 800c6bc: 5499 strb r1, [r3, r2] + App_Write(&ch, 1U); + 800c6be: 1dfb adds r3, r7, #7 + 800c6c0: 2101 movs r1, #1 + 800c6c2: 4618 mov r0, r3 + 800c6c4: f000 fb88 bl 800cdd8 + 800c6c8: e000 b.n 800c6cc + return; + 800c6ca: bf00 nop + } +} + 800c6cc: 3708 adds r7, #8 + 800c6ce: 46bd mov sp, r7 + 800c6d0: bd80 pop {r7, pc} + 800c6d2: bf00 nop + 800c6d4: 20000bc8 .word 0x20000bc8 + 800c6d8: 20000b68 .word 0x20000b68 + 800c6dc: 0800f3c8 .word 0x0800f3c8 + 800c6e0: 0800f3cc .word 0x0800f3cc + 800c6e4: 0800fccc .word 0x0800fccc + +0800c6e8 : + +static void App_ConfigExecuteLine(char *line) +{ + 800c6e8: b580 push {r7, lr} + 800c6ea: b086 sub sp, #24 + 800c6ec: af00 add r7, sp, #0 + 800c6ee: 6078 str r0, [r7, #4] + char *arg; + uint32_t u32; + uint8_t sync[3]; + + line = App_SkipSpaces(line); + 800c6f0: 6878 ldr r0, [r7, #4] + 800c6f2: f000 fc39 bl 800cf68 + 800c6f6: 6078 str r0, [r7, #4] + if (*line == '\0') + 800c6f8: 687b ldr r3, [r7, #4] + 800c6fa: 781b ldrb r3, [r3, #0] + 800c6fc: 2b00 cmp r3, #0 + 800c6fe: f000 8210 beq.w 800cb22 + { + return; + } + + if ((strcmp(line, "help") == 0) || (strcmp(line, "?") == 0)) + 800c702: 49a4 ldr r1, [pc, #656] @ (800c994 ) + 800c704: 6878 ldr r0, [r7, #4] + 800c706: f7f3 fd3b bl 8000180 + 800c70a: 4603 mov r3, r0 + 800c70c: 2b00 cmp r3, #0 + 800c70e: d006 beq.n 800c71e + 800c710: 49a1 ldr r1, [pc, #644] @ (800c998 ) + 800c712: 6878 ldr r0, [r7, #4] + 800c714: f7f3 fd34 bl 8000180 + 800c718: 4603 mov r3, r0 + 800c71a: 2b00 cmp r3, #0 + 800c71c: d102 bne.n 800c724 + { + App_PrintHelp(); + 800c71e: f000 fa2b bl 800cb78 + return; + 800c722: e1ff b.n 800cb24 + } + + if ((strcmp(line, "show") == 0) || (strcmp(line, "status") == 0)) + 800c724: 499d ldr r1, [pc, #628] @ (800c99c ) + 800c726: 6878 ldr r0, [r7, #4] + 800c728: f7f3 fd2a bl 8000180 + 800c72c: 4603 mov r3, r0 + 800c72e: 2b00 cmp r3, #0 + 800c730: d006 beq.n 800c740 + 800c732: 499b ldr r1, [pc, #620] @ (800c9a0 ) + 800c734: 6878 ldr r0, [r7, #4] + 800c736: f7f3 fd23 bl 8000180 + 800c73a: 4603 mov r3, r0 + 800c73c: 2b00 cmp r3, #0 + 800c73e: d102 bne.n 800c746 + { + App_PrintStatus(); + 800c740: f000 fa64 bl 800cc0c + return; + 800c744: e1ee b.n 800cb24 + } + + if (strcmp(line, "exit") == 0) + 800c746: 4997 ldr r1, [pc, #604] @ (800c9a4 ) + 800c748: 6878 ldr r0, [r7, #4] + 800c74a: f7f3 fd19 bl 8000180 + 800c74e: 4603 mov r3, r0 + 800c750: 2b00 cmp r3, #0 + 800c752: d102 bne.n 800c75a + { + App_ExitConfigMode(); + 800c754: f7ff fdc4 bl 800c2e0 + return; + 800c758: e1e4 b.n 800cb24 + } + + if (strcmp(line, "defaults") == 0) + 800c75a: 4993 ldr r1, [pc, #588] @ (800c9a8 ) + 800c75c: 6878 ldr r0, [r7, #4] + 800c75e: f7f3 fd0f bl 8000180 + 800c762: 4603 mov r3, r0 + 800c764: 2b00 cmp r3, #0 + 800c766: d126 bne.n 800c7b6 + { + g_cfg.rf_frequency = RF_FREQUENCY_DEFAULT; + 800c768: 4b90 ldr r3, [pc, #576] @ (800c9ac ) + 800c76a: 4a91 ldr r2, [pc, #580] @ (800c9b0 ) + 800c76c: 601a str r2, [r3, #0] + g_cfg.tx_power = TX_OUTPUT_POWER_DEFAULT; + 800c76e: 4b8f ldr r3, [pc, #572] @ (800c9ac ) + 800c770: 220e movs r2, #14 + 800c772: 711a strb r2, [r3, #4] + g_cfg.fsk_bitrate = FSK_DATARATE_DEFAULT; + 800c774: 4b8d ldr r3, [pc, #564] @ (800c9ac ) + 800c776: f24c 3250 movw r2, #50000 @ 0xc350 + 800c77a: 609a str r2, [r3, #8] + g_cfg.fsk_bandwidth = FSK_BANDWIDTH_DEFAULT; + 800c77c: 4b8b ldr r3, [pc, #556] @ (800c9ac ) + 800c77e: f24c 3250 movw r2, #50000 @ 0xc350 + 800c782: 60da str r2, [r3, #12] + g_cfg.fsk_fdev = FSK_FDEV_DEFAULT; + 800c784: 4b89 ldr r3, [pc, #548] @ (800c9ac ) + 800c786: f246 12a8 movw r2, #25000 @ 0x61a8 + 800c78a: 611a str r2, [r3, #16] + g_cfg.fsk_preamble_len = FSK_PREAMBLE_LENGTH_DEFAULT; + 800c78c: 4b87 ldr r3, [pc, #540] @ (800c9ac ) + 800c78e: 2204 movs r2, #4 + 800c790: 829a strh r2, [r3, #20] + g_cfg.syncword[0] = 0xC1U; + 800c792: 4b86 ldr r3, [pc, #536] @ (800c9ac ) + 800c794: 22c1 movs r2, #193 @ 0xc1 + 800c796: 759a strb r2, [r3, #22] + g_cfg.syncword[1] = 0x94U; + 800c798: 4b84 ldr r3, [pc, #528] @ (800c9ac ) + 800c79a: 2294 movs r2, #148 @ 0x94 + 800c79c: 75da strb r2, [r3, #23] + g_cfg.syncword[2] = 0xC1U; + 800c79e: 4b83 ldr r3, [pc, #524] @ (800c9ac ) + 800c7a0: 22c1 movs r2, #193 @ 0xc1 + 800c7a2: 761a strb r2, [r3, #24] + g_cfg.uart_packet_timeout_ms = DEFAULT_UART_PACKET_TIMEOUT_MS; + 800c7a4: 4b81 ldr r3, [pc, #516] @ (800c9ac ) + 800c7a6: 2214 movs r2, #20 + 800c7a8: 835a strh r2, [r3, #26] + App_RadioApplyConfig(); + 800c7aa: f7ff fcc1 bl 800c130 + App_Printf("defaults restored\r\n"); + 800c7ae: 4881 ldr r0, [pc, #516] @ (800c9b4 ) + 800c7b0: f000 fae6 bl 800cd80 + return; + 800c7b4: e1b6 b.n 800cb24 + } + + if (strncmp(line, "freq ", 5) == 0) + 800c7b6: 2205 movs r2, #5 + 800c7b8: 497f ldr r1, [pc, #508] @ (800c9b8 ) + 800c7ba: 6878 ldr r0, [r7, #4] + 800c7bc: f001 ffec bl 800e798 + 800c7c0: 4603 mov r3, r0 + 800c7c2: 2b00 cmp r3, #0 + 800c7c4: d11f bne.n 800c806 + { + u32 = strtoul(&line[5], NULL, 10); + 800c7c6: 687b ldr r3, [r7, #4] + 800c7c8: 3305 adds r3, #5 + 800c7ca: 220a movs r2, #10 + 800c7cc: 2100 movs r1, #0 + 800c7ce: 4618 mov r0, r3 + 800c7d0: f001 ff94 bl 800e6fc + 800c7d4: 6138 str r0, [r7, #16] + if (u32 < 150000000UL || u32 > 960000000UL) + 800c7d6: 693b ldr r3, [r7, #16] + 800c7d8: 4a78 ldr r2, [pc, #480] @ (800c9bc ) + 800c7da: 4293 cmp r3, r2 + 800c7dc: d903 bls.n 800c7e6 + 800c7de: 693b ldr r3, [r7, #16] + 800c7e0: 4a77 ldr r2, [pc, #476] @ (800c9c0 ) + 800c7e2: 4293 cmp r3, r2 + 800c7e4: d903 bls.n 800c7ee + { + App_Printf("bad frequency\r\n"); + 800c7e6: 4877 ldr r0, [pc, #476] @ (800c9c4 ) + 800c7e8: f000 faca bl 800cd80 + return; + 800c7ec: e19a b.n 800cb24 + } + g_cfg.rf_frequency = u32; + 800c7ee: 4a6f ldr r2, [pc, #444] @ (800c9ac ) + 800c7f0: 693b ldr r3, [r7, #16] + 800c7f2: 6013 str r3, [r2, #0] + App_RadioApplyConfig(); + 800c7f4: f7ff fc9c bl 800c130 + App_Printf("freq=%lu\r\n", (unsigned long)g_cfg.rf_frequency); + 800c7f8: 4b6c ldr r3, [pc, #432] @ (800c9ac ) + 800c7fa: 681b ldr r3, [r3, #0] + 800c7fc: 4619 mov r1, r3 + 800c7fe: 4872 ldr r0, [pc, #456] @ (800c9c8 ) + 800c800: f000 fabe bl 800cd80 + return; + 800c804: e18e b.n 800cb24 + } + + if (strncmp(line, "power ", 6) == 0) + 800c806: 2206 movs r2, #6 + 800c808: 4970 ldr r1, [pc, #448] @ (800c9cc ) + 800c80a: 6878 ldr r0, [r7, #4] + 800c80c: f001 ffc4 bl 800e798 + 800c810: 4603 mov r3, r0 + 800c812: 2b00 cmp r3, #0 + 800c814: d120 bne.n 800c858 + { + long pwr = strtol(&line[6], NULL, 10); + 800c816: 687b ldr r3, [r7, #4] + 800c818: 3306 adds r3, #6 + 800c81a: 220a movs r2, #10 + 800c81c: 2100 movs r1, #0 + 800c81e: 4618 mov r0, r3 + 800c820: f001 fef4 bl 800e60c + 800c824: 60f8 str r0, [r7, #12] + if ((pwr < -9L) || (pwr > 22L)) + 800c826: 68fb ldr r3, [r7, #12] + 800c828: f113 0f09 cmn.w r3, #9 + 800c82c: db02 blt.n 800c834 + 800c82e: 68fb ldr r3, [r7, #12] + 800c830: 2b16 cmp r3, #22 + 800c832: dd03 ble.n 800c83c + { + App_Printf("bad power\r\n"); + 800c834: 4866 ldr r0, [pc, #408] @ (800c9d0 ) + 800c836: f000 faa3 bl 800cd80 + return; + 800c83a: e173 b.n 800cb24 + } + g_cfg.tx_power = (int8_t)pwr; + 800c83c: 68fb ldr r3, [r7, #12] + 800c83e: b25a sxtb r2, r3 + 800c840: 4b5a ldr r3, [pc, #360] @ (800c9ac ) + 800c842: 711a strb r2, [r3, #4] + App_RadioApplyConfig(); + 800c844: f7ff fc74 bl 800c130 + App_Printf("power=%d\r\n", g_cfg.tx_power); + 800c848: 4b58 ldr r3, [pc, #352] @ (800c9ac ) + 800c84a: f993 3004 ldrsb.w r3, [r3, #4] + 800c84e: 4619 mov r1, r3 + 800c850: 4860 ldr r0, [pc, #384] @ (800c9d4 ) + 800c852: f000 fa95 bl 800cd80 + return; + 800c856: e165 b.n 800cb24 + } + + if (strncmp(line, "bitrate ", 8) == 0) + 800c858: 2208 movs r2, #8 + 800c85a: 495f ldr r1, [pc, #380] @ (800c9d8 ) + 800c85c: 6878 ldr r0, [r7, #4] + 800c85e: f001 ff9b bl 800e798 + 800c862: 4603 mov r3, r0 + 800c864: 2b00 cmp r3, #0 + 800c866: d11f bne.n 800c8a8 + { + u32 = strtoul(&line[8], NULL, 10); + 800c868: 687b ldr r3, [r7, #4] + 800c86a: 3308 adds r3, #8 + 800c86c: 220a movs r2, #10 + 800c86e: 2100 movs r1, #0 + 800c870: 4618 mov r0, r3 + 800c872: f001 ff43 bl 800e6fc + 800c876: 6138 str r0, [r7, #16] + if ((u32 < 600UL) || (u32 > 300000UL)) + 800c878: 693b ldr r3, [r7, #16] + 800c87a: f5b3 7f16 cmp.w r3, #600 @ 0x258 + 800c87e: d303 bcc.n 800c888 + 800c880: 693b ldr r3, [r7, #16] + 800c882: 4a56 ldr r2, [pc, #344] @ (800c9dc ) + 800c884: 4293 cmp r3, r2 + 800c886: d903 bls.n 800c890 + { + App_Printf("bad bitrate\r\n"); + 800c888: 4855 ldr r0, [pc, #340] @ (800c9e0 ) + 800c88a: f000 fa79 bl 800cd80 + return; + 800c88e: e149 b.n 800cb24 + } + g_cfg.fsk_bitrate = u32; + 800c890: 4a46 ldr r2, [pc, #280] @ (800c9ac ) + 800c892: 693b ldr r3, [r7, #16] + 800c894: 6093 str r3, [r2, #8] + App_RadioApplyConfig(); + 800c896: f7ff fc4b bl 800c130 + App_Printf("bitrate=%lu\r\n", (unsigned long)g_cfg.fsk_bitrate); + 800c89a: 4b44 ldr r3, [pc, #272] @ (800c9ac ) + 800c89c: 689b ldr r3, [r3, #8] + 800c89e: 4619 mov r1, r3 + 800c8a0: 4850 ldr r0, [pc, #320] @ (800c9e4 ) + 800c8a2: f000 fa6d bl 800cd80 + return; + 800c8a6: e13d b.n 800cb24 + } + + if (strncmp(line, "bandwidth ", 10) == 0) + 800c8a8: 220a movs r2, #10 + 800c8aa: 494f ldr r1, [pc, #316] @ (800c9e8 ) + 800c8ac: 6878 ldr r0, [r7, #4] + 800c8ae: f001 ff73 bl 800e798 + 800c8b2: 4603 mov r3, r0 + 800c8b4: 2b00 cmp r3, #0 + 800c8b6: d120 bne.n 800c8fa + { + u32 = strtoul(&line[10], NULL, 10); + 800c8b8: 687b ldr r3, [r7, #4] + 800c8ba: 330a adds r3, #10 + 800c8bc: 220a movs r2, #10 + 800c8be: 2100 movs r1, #0 + 800c8c0: 4618 mov r0, r3 + 800c8c2: f001 ff1b bl 800e6fc + 800c8c6: 6138 str r0, [r7, #16] + if ((u32 < 2600UL) || (u32 > 250000UL)) + 800c8c8: 693b ldr r3, [r7, #16] + 800c8ca: f640 2227 movw r2, #2599 @ 0xa27 + 800c8ce: 4293 cmp r3, r2 + 800c8d0: d903 bls.n 800c8da + 800c8d2: 693b ldr r3, [r7, #16] + 800c8d4: 4a45 ldr r2, [pc, #276] @ (800c9ec ) + 800c8d6: 4293 cmp r3, r2 + 800c8d8: d903 bls.n 800c8e2 + { + App_Printf("bad bandwidth\r\n"); + 800c8da: 4845 ldr r0, [pc, #276] @ (800c9f0 ) + 800c8dc: f000 fa50 bl 800cd80 + return; + 800c8e0: e120 b.n 800cb24 + } + g_cfg.fsk_bandwidth = u32; + 800c8e2: 4a32 ldr r2, [pc, #200] @ (800c9ac ) + 800c8e4: 693b ldr r3, [r7, #16] + 800c8e6: 60d3 str r3, [r2, #12] + App_RadioApplyConfig(); + 800c8e8: f7ff fc22 bl 800c130 + App_Printf("bandwidth=%lu\r\n", (unsigned long)g_cfg.fsk_bandwidth); + 800c8ec: 4b2f ldr r3, [pc, #188] @ (800c9ac ) + 800c8ee: 68db ldr r3, [r3, #12] + 800c8f0: 4619 mov r1, r3 + 800c8f2: 4840 ldr r0, [pc, #256] @ (800c9f4 ) + 800c8f4: f000 fa44 bl 800cd80 + return; + 800c8f8: e114 b.n 800cb24 + } + + if (strncmp(line, "fdev ", 5) == 0) + 800c8fa: 2205 movs r2, #5 + 800c8fc: 493e ldr r1, [pc, #248] @ (800c9f8 ) + 800c8fe: 6878 ldr r0, [r7, #4] + 800c900: f001 ff4a bl 800e798 + 800c904: 4603 mov r3, r0 + 800c906: 2b00 cmp r3, #0 + 800c908: d11b bne.n 800c942 + { + u32 = strtoul(&line[5], NULL, 10); + 800c90a: 687b ldr r3, [r7, #4] + 800c90c: 3305 adds r3, #5 + 800c90e: 220a movs r2, #10 + 800c910: 2100 movs r1, #0 + 800c912: 4618 mov r0, r3 + 800c914: f001 fef2 bl 800e6fc + 800c918: 6138 str r0, [r7, #16] + if (u32 > 200000UL) + 800c91a: 693b ldr r3, [r7, #16] + 800c91c: 4a37 ldr r2, [pc, #220] @ (800c9fc ) + 800c91e: 4293 cmp r3, r2 + 800c920: d903 bls.n 800c92a + { + App_Printf("bad fdev\r\n"); + 800c922: 4837 ldr r0, [pc, #220] @ (800ca00 ) + 800c924: f000 fa2c bl 800cd80 + return; + 800c928: e0fc b.n 800cb24 + } + g_cfg.fsk_fdev = u32; + 800c92a: 4a20 ldr r2, [pc, #128] @ (800c9ac ) + 800c92c: 693b ldr r3, [r7, #16] + 800c92e: 6113 str r3, [r2, #16] + App_RadioApplyConfig(); + 800c930: f7ff fbfe bl 800c130 + App_Printf("fdev=%lu\r\n", (unsigned long)g_cfg.fsk_fdev); + 800c934: 4b1d ldr r3, [pc, #116] @ (800c9ac ) + 800c936: 691b ldr r3, [r3, #16] + 800c938: 4619 mov r1, r3 + 800c93a: 4832 ldr r0, [pc, #200] @ (800ca04 ) + 800c93c: f000 fa20 bl 800cd80 + return; + 800c940: e0f0 b.n 800cb24 + } + + if (strncmp(line, "preamble ", 9) == 0) + 800c942: 2209 movs r2, #9 + 800c944: 4930 ldr r1, [pc, #192] @ (800ca08 ) + 800c946: 6878 ldr r0, [r7, #4] + 800c948: f001 ff26 bl 800e798 + 800c94c: 4603 mov r3, r0 + 800c94e: 2b00 cmp r3, #0 + 800c950: d160 bne.n 800ca14 + { + u32 = strtoul(&line[9], NULL, 10); + 800c952: 687b ldr r3, [r7, #4] + 800c954: 3309 adds r3, #9 + 800c956: 220a movs r2, #10 + 800c958: 2100 movs r1, #0 + 800c95a: 4618 mov r0, r3 + 800c95c: f001 fece bl 800e6fc + 800c960: 6138 str r0, [r7, #16] + if ((u32 < 2UL) || (u32 > 65535UL)) + 800c962: 693b ldr r3, [r7, #16] + 800c964: 2b01 cmp r3, #1 + 800c966: d903 bls.n 800c970 + 800c968: 693b ldr r3, [r7, #16] + 800c96a: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 + 800c96e: d303 bcc.n 800c978 + { + App_Printf("bad preamble\r\n"); + 800c970: 4826 ldr r0, [pc, #152] @ (800ca0c ) + 800c972: f000 fa05 bl 800cd80 + return; + 800c976: e0d5 b.n 800cb24 + } + g_cfg.fsk_preamble_len = (uint16_t)u32; + 800c978: 693b ldr r3, [r7, #16] + 800c97a: b29a uxth r2, r3 + 800c97c: 4b0b ldr r3, [pc, #44] @ (800c9ac ) + 800c97e: 829a strh r2, [r3, #20] + App_RadioApplyConfig(); + 800c980: f7ff fbd6 bl 800c130 + App_Printf("preamble=%u\r\n", g_cfg.fsk_preamble_len); + 800c984: 4b09 ldr r3, [pc, #36] @ (800c9ac ) + 800c986: 8a9b ldrh r3, [r3, #20] + 800c988: 4619 mov r1, r3 + 800c98a: 4821 ldr r0, [pc, #132] @ (800ca10 ) + 800c98c: f000 f9f8 bl 800cd80 + return; + 800c990: e0c8 b.n 800cb24 + 800c992: bf00 nop + 800c994: 0800f3d0 .word 0x0800f3d0 + 800c998: 0800f3d8 .word 0x0800f3d8 + 800c99c: 0800f3dc .word 0x0800f3dc + 800c9a0: 0800f3e4 .word 0x0800f3e4 + 800c9a4: 0800f3ec .word 0x0800f3ec + 800c9a8: 0800f3f4 .word 0x0800f3f4 + 800c9ac: 2000000c .word 0x2000000c + 800c9b0: 19d094e0 .word 0x19d094e0 + 800c9b4: 0800f400 .word 0x0800f400 + 800c9b8: 0800f414 .word 0x0800f414 + 800c9bc: 08f0d17f .word 0x08f0d17f + 800c9c0: 39387000 .word 0x39387000 + 800c9c4: 0800f41c .word 0x0800f41c + 800c9c8: 0800f42c .word 0x0800f42c + 800c9cc: 0800f438 .word 0x0800f438 + 800c9d0: 0800f440 .word 0x0800f440 + 800c9d4: 0800f44c .word 0x0800f44c + 800c9d8: 0800f458 .word 0x0800f458 + 800c9dc: 000493e0 .word 0x000493e0 + 800c9e0: 0800f464 .word 0x0800f464 + 800c9e4: 0800f474 .word 0x0800f474 + 800c9e8: 0800f484 .word 0x0800f484 + 800c9ec: 0003d090 .word 0x0003d090 + 800c9f0: 0800f490 .word 0x0800f490 + 800c9f4: 0800f4a0 .word 0x0800f4a0 + 800c9f8: 0800f4b0 .word 0x0800f4b0 + 800c9fc: 00030d40 .word 0x00030d40 + 800ca00: 0800f4b8 .word 0x0800f4b8 + 800ca04: 0800f4c4 .word 0x0800f4c4 + 800ca08: 0800f4d0 .word 0x0800f4d0 + 800ca0c: 0800f4dc .word 0x0800f4dc + 800ca10: 0800f4ec .word 0x0800f4ec + } + + if (strncmp(line, "timeout ", 8) == 0) + 800ca14: 2208 movs r2, #8 + 800ca16: 4945 ldr r1, [pc, #276] @ (800cb2c ) + 800ca18: 6878 ldr r0, [r7, #4] + 800ca1a: f001 febd bl 800e798 + 800ca1e: 4603 mov r3, r0 + 800ca20: 2b00 cmp r3, #0 + 800ca22: d11d bne.n 800ca60 + { + u32 = strtoul(&line[8], NULL, 10); + 800ca24: 687b ldr r3, [r7, #4] + 800ca26: 3308 adds r3, #8 + 800ca28: 220a movs r2, #10 + 800ca2a: 2100 movs r1, #0 + 800ca2c: 4618 mov r0, r3 + 800ca2e: f001 fe65 bl 800e6fc + 800ca32: 6138 str r0, [r7, #16] + if ((u32 < 1UL) || (u32 > 1000UL)) + 800ca34: 693b ldr r3, [r7, #16] + 800ca36: 2b00 cmp r3, #0 + 800ca38: d003 beq.n 800ca42 + 800ca3a: 693b ldr r3, [r7, #16] + 800ca3c: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 + 800ca40: d903 bls.n 800ca4a + { + App_Printf("bad timeout\r\n"); + 800ca42: 483b ldr r0, [pc, #236] @ (800cb30 ) + 800ca44: f000 f99c bl 800cd80 + return; + 800ca48: e06c b.n 800cb24 + } + g_cfg.uart_packet_timeout_ms = (uint16_t)u32; + 800ca4a: 693b ldr r3, [r7, #16] + 800ca4c: b29a uxth r2, r3 + 800ca4e: 4b39 ldr r3, [pc, #228] @ (800cb34 ) + 800ca50: 835a strh r2, [r3, #26] + App_Printf("timeout=%u\r\n", g_cfg.uart_packet_timeout_ms); + 800ca52: 4b38 ldr r3, [pc, #224] @ (800cb34 ) + 800ca54: 8b5b ldrh r3, [r3, #26] + 800ca56: 4619 mov r1, r3 + 800ca58: 4837 ldr r0, [pc, #220] @ (800cb38 ) + 800ca5a: f000 f991 bl 800cd80 + return; + 800ca5e: e061 b.n 800cb24 + } + + if (strncmp(line, "uart ", 5) == 0) + 800ca60: 2205 movs r2, #5 + 800ca62: 4936 ldr r1, [pc, #216] @ (800cb3c ) + 800ca64: 6878 ldr r0, [r7, #4] + 800ca66: f001 fe97 bl 800e798 + 800ca6a: 4603 mov r3, r0 + 800ca6c: 2b00 cmp r3, #0 + 800ca6e: d122 bne.n 800cab6 + { + u32 = strtoul(&line[5], NULL, 10); + 800ca70: 687b ldr r3, [r7, #4] + 800ca72: 3305 adds r3, #5 + 800ca74: 220a movs r2, #10 + 800ca76: 2100 movs r1, #0 + 800ca78: 4618 mov r0, r3 + 800ca7a: f001 fe3f bl 800e6fc + 800ca7e: 6138 str r0, [r7, #16] + if ((u32 < 1200UL) || (u32 > 921600UL)) + 800ca80: 693b ldr r3, [r7, #16] + 800ca82: f5b3 6f96 cmp.w r3, #1200 @ 0x4b0 + 800ca86: d303 bcc.n 800ca90 + 800ca88: 693b ldr r3, [r7, #16] + 800ca8a: f5b3 2f61 cmp.w r3, #921600 @ 0xe1000 + 800ca8e: d903 bls.n 800ca98 + { + App_Printf("bad uart baudrate\r\n"); + 800ca90: 482b ldr r0, [pc, #172] @ (800cb40 ) + 800ca92: f000 f975 bl 800cd80 + return; + 800ca96: e045 b.n 800cb24 + } + g_cfg.uart_baudrate = u32; + 800ca98: 4a26 ldr r2, [pc, #152] @ (800cb34 ) + 800ca9a: 693b ldr r3, [r7, #16] + 800ca9c: 61d3 str r3, [r2, #28] + App_Printf("switching uart to %lu baud\r\n", (unsigned long)g_cfg.uart_baudrate); + 800ca9e: 4b25 ldr r3, [pc, #148] @ (800cb34 ) + 800caa0: 69db ldr r3, [r3, #28] + 800caa2: 4619 mov r1, r3 + 800caa4: 4827 ldr r0, [pc, #156] @ (800cb44 ) + 800caa6: f000 f96b bl 800cd80 + App_ReconfigureUart(g_cfg.uart_baudrate); + 800caaa: 4b22 ldr r3, [pc, #136] @ (800cb34 ) + 800caac: 69db ldr r3, [r3, #28] + 800caae: 4618 mov r0, r3 + 800cab0: f000 f9ac bl 800ce0c + return; + 800cab4: e036 b.n 800cb24 + } + + if (strncmp(line, "sync ", 5) == 0) + 800cab6: 2205 movs r2, #5 + 800cab8: 4923 ldr r1, [pc, #140] @ (800cb48 ) + 800caba: 6878 ldr r0, [r7, #4] + 800cabc: f001 fe6c bl 800e798 + 800cac0: 4603 mov r3, r0 + 800cac2: 2b00 cmp r3, #0 + 800cac4: d128 bne.n 800cb18 + { + arg = App_SkipSpaces(&line[5]); + 800cac6: 687b ldr r3, [r7, #4] + 800cac8: 3305 adds r3, #5 + 800caca: 4618 mov r0, r3 + 800cacc: f000 fa4c bl 800cf68 + 800cad0: 6178 str r0, [r7, #20] + if (App_ParseHexSyncWord(arg, sync) == 0U) + 800cad2: f107 0308 add.w r3, r7, #8 + 800cad6: 4619 mov r1, r3 + 800cad8: 6978 ldr r0, [r7, #20] + 800cada: f000 f9cf bl 800ce7c + 800cade: 4603 mov r3, r0 + 800cae0: 2b00 cmp r3, #0 + 800cae2: d103 bne.n 800caec + { + App_Printf("bad sync, use 6 hex chars, e.g. C194C1\r\n"); + 800cae4: 4819 ldr r0, [pc, #100] @ (800cb4c ) + 800cae6: f000 f94b bl 800cd80 + return; + 800caea: e01b b.n 800cb24 + } + memcpy(g_cfg.syncword, sync, sizeof(sync)); + 800caec: 4b11 ldr r3, [pc, #68] @ (800cb34 ) + 800caee: 3316 adds r3, #22 + 800caf0: f107 0208 add.w r2, r7, #8 + 800caf4: 8811 ldrh r1, [r2, #0] + 800caf6: 7892 ldrb r2, [r2, #2] + 800caf8: 8019 strh r1, [r3, #0] + 800cafa: 709a strb r2, [r3, #2] + App_RadioApplyConfig(); + 800cafc: f7ff fb18 bl 800c130 + App_Printf("sync=%02X%02X%02X\r\n", g_cfg.syncword[0], g_cfg.syncword[1], g_cfg.syncword[2]); + 800cb00: 4b0c ldr r3, [pc, #48] @ (800cb34 ) + 800cb02: 7d9b ldrb r3, [r3, #22] + 800cb04: 4619 mov r1, r3 + 800cb06: 4b0b ldr r3, [pc, #44] @ (800cb34 ) + 800cb08: 7ddb ldrb r3, [r3, #23] + 800cb0a: 461a mov r2, r3 + 800cb0c: 4b09 ldr r3, [pc, #36] @ (800cb34 ) + 800cb0e: 7e1b ldrb r3, [r3, #24] + 800cb10: 480f ldr r0, [pc, #60] @ (800cb50 ) + 800cb12: f000 f935 bl 800cd80 + return; + 800cb16: e005 b.n 800cb24 + } + + App_Printf("unknown command: %s\r\n", line); + 800cb18: 6879 ldr r1, [r7, #4] + 800cb1a: 480e ldr r0, [pc, #56] @ (800cb54 ) + 800cb1c: f000 f930 bl 800cd80 + 800cb20: e000 b.n 800cb24 + return; + 800cb22: bf00 nop +} + 800cb24: 3718 adds r7, #24 + 800cb26: 46bd mov sp, r7 + 800cb28: bd80 pop {r7, pc} + 800cb2a: bf00 nop + 800cb2c: 0800f4fc .word 0x0800f4fc + 800cb30: 0800f508 .word 0x0800f508 + 800cb34: 2000000c .word 0x2000000c + 800cb38: 0800f518 .word 0x0800f518 + 800cb3c: 0800f528 .word 0x0800f528 + 800cb40: 0800f530 .word 0x0800f530 + 800cb44: 0800f544 .word 0x0800f544 + 800cb48: 0800f564 .word 0x0800f564 + 800cb4c: 0800f56c .word 0x0800f56c + 800cb50: 0800f598 .word 0x0800f598 + 800cb54: 0800f5ac .word 0x0800f5ac + +0800cb58 : + +static void App_PrintConfigPrompt(void) +{ + 800cb58: b580 push {r7, lr} + 800cb5a: af00 add r7, sp, #0 + if (g_mode == APP_MODE_CONFIG) + 800cb5c: 4b04 ldr r3, [pc, #16] @ (800cb70 ) + 800cb5e: 781b ldrb r3, [r3, #0] + 800cb60: 2b01 cmp r3, #1 + 800cb62: d102 bne.n 800cb6a + { + App_Printf("cfg> "); + 800cb64: 4803 ldr r0, [pc, #12] @ (800cb74 ) + 800cb66: f000 f90b bl 800cd80 + } +} + 800cb6a: bf00 nop + 800cb6c: bd80 pop {r7, pc} + 800cb6e: bf00 nop + 800cb70: 20000b64 .word 0x20000b64 + 800cb74: 0800f5c4 .word 0x0800f5c4 + +0800cb78 : + +static void App_PrintHelp(void) +{ + 800cb78: b580 push {r7, lr} + 800cb7a: af00 add r7, sp, #0 + App_Printf("commands:\r\n"); + 800cb7c: 4815 ldr r0, [pc, #84] @ (800cbd4 ) + 800cb7e: f000 f8ff bl 800cd80 + App_Printf(" help - this help\r\n"); + 800cb82: 4815 ldr r0, [pc, #84] @ (800cbd8 ) + 800cb84: f000 f8fc bl 800cd80 + App_Printf(" show - current config and counters\r\n"); + 800cb88: 4814 ldr r0, [pc, #80] @ (800cbdc ) + 800cb8a: f000 f8f9 bl 800cd80 + App_Printf(" freq - rf frequency\r\n"); + 800cb8e: 4814 ldr r0, [pc, #80] @ (800cbe0 ) + 800cb90: f000 f8f6 bl 800cd80 + App_Printf(" power - tx power (-9..22)\r\n"); + 800cb94: 4813 ldr r0, [pc, #76] @ (800cbe4 ) + 800cb96: f000 f8f3 bl 800cd80 + App_Printf(" bitrate - fsk bitrate\r\n"); + 800cb9a: 4813 ldr r0, [pc, #76] @ (800cbe8 ) + 800cb9c: f000 f8f0 bl 800cd80 + App_Printf(" bandwidth - fsk rx bandwidth\r\n"); + 800cba0: 4812 ldr r0, [pc, #72] @ (800cbec ) + 800cba2: f000 f8ed bl 800cd80 + App_Printf(" fdev - fsk frequency deviation\r\n"); + 800cba6: 4812 ldr r0, [pc, #72] @ (800cbf0 ) + 800cba8: f000 f8ea bl 800cd80 + App_Printf(" preamble - fsk preamble length\r\n"); + 800cbac: 4811 ldr r0, [pc, #68] @ (800cbf4 ) + 800cbae: f000 f8e7 bl 800cd80 + App_Printf(" sync - 3-byte syncword, example C194C1\r\n"); + 800cbb2: 4811 ldr r0, [pc, #68] @ (800cbf8 ) + 800cbb4: f000 f8e4 bl 800cd80 + App_Printf(" timeout - uart silence before rf packet send\r\n"); + 800cbb8: 4810 ldr r0, [pc, #64] @ (800cbfc ) + 800cbba: f000 f8e1 bl 800cd80 + App_Printf(" uart - change uart baudrate immediately\r\n"); + 800cbbe: 4810 ldr r0, [pc, #64] @ (800cc00 ) + 800cbc0: f000 f8de bl 800cd80 + App_Printf(" defaults - restore default config\r\n"); + 800cbc4: 480f ldr r0, [pc, #60] @ (800cc04 ) + 800cbc6: f000 f8db bl 800cd80 + App_Printf(" exit - return to transparent bridge mode\r\n"); + 800cbca: 480f ldr r0, [pc, #60] @ (800cc08 ) + 800cbcc: f000 f8d8 bl 800cd80 +} + 800cbd0: bf00 nop + 800cbd2: bd80 pop {r7, pc} + 800cbd4: 0800f5cc .word 0x0800f5cc + 800cbd8: 0800f5d8 .word 0x0800f5d8 + 800cbdc: 0800f600 .word 0x0800f600 + 800cbe0: 0800f638 .word 0x0800f638 + 800cbe4: 0800f660 .word 0x0800f660 + 800cbe8: 0800f690 .word 0x0800f690 + 800cbec: 0800f6b8 .word 0x0800f6b8 + 800cbf0: 0800f6e4 .word 0x0800f6e4 + 800cbf4: 0800f718 .word 0x0800f718 + 800cbf8: 0800f748 .word 0x0800f748 + 800cbfc: 0800f784 .word 0x0800f784 + 800cc00: 0800f7c4 .word 0x0800f7c4 + 800cc04: 0800f800 .word 0x0800f800 + 800cc08: 0800f834 .word 0x0800f834 + +0800cc0c : + +static void App_PrintStatus(void) +{ + 800cc0c: b580 push {r7, lr} + 800cc0e: af00 add r7, sp, #0 + App_Printf("mode=%s\r\n", (g_mode == APP_MODE_CONFIG) ? "config" : "data"); + 800cc10: 4b3d ldr r3, [pc, #244] @ (800cd08 ) + 800cc12: 781b ldrb r3, [r3, #0] + 800cc14: 2b01 cmp r3, #1 + 800cc16: d101 bne.n 800cc1c + 800cc18: 4b3c ldr r3, [pc, #240] @ (800cd0c ) + 800cc1a: e000 b.n 800cc1e + 800cc1c: 4b3c ldr r3, [pc, #240] @ (800cd10 ) + 800cc1e: 4619 mov r1, r3 + 800cc20: 483c ldr r0, [pc, #240] @ (800cd14 ) + 800cc22: f000 f8ad bl 800cd80 + App_Printf("freq=%lu Hz\r\n", (unsigned long)g_cfg.rf_frequency); + 800cc26: 4b3c ldr r3, [pc, #240] @ (800cd18 ) + 800cc28: 681b ldr r3, [r3, #0] + 800cc2a: 4619 mov r1, r3 + 800cc2c: 483b ldr r0, [pc, #236] @ (800cd1c ) + 800cc2e: f000 f8a7 bl 800cd80 + App_Printf("power=%d dBm\r\n", g_cfg.tx_power); + 800cc32: 4b39 ldr r3, [pc, #228] @ (800cd18 ) + 800cc34: f993 3004 ldrsb.w r3, [r3, #4] + 800cc38: 4619 mov r1, r3 + 800cc3a: 4839 ldr r0, [pc, #228] @ (800cd20 ) + 800cc3c: f000 f8a0 bl 800cd80 + App_Printf("bitrate=%lu bps\r\n", (unsigned long)g_cfg.fsk_bitrate); + 800cc40: 4b35 ldr r3, [pc, #212] @ (800cd18 ) + 800cc42: 689b ldr r3, [r3, #8] + 800cc44: 4619 mov r1, r3 + 800cc46: 4837 ldr r0, [pc, #220] @ (800cd24 ) + 800cc48: f000 f89a bl 800cd80 + App_Printf("bandwidth=%lu Hz\r\n", (unsigned long)g_cfg.fsk_bandwidth); + 800cc4c: 4b32 ldr r3, [pc, #200] @ (800cd18 ) + 800cc4e: 68db ldr r3, [r3, #12] + 800cc50: 4619 mov r1, r3 + 800cc52: 4835 ldr r0, [pc, #212] @ (800cd28 ) + 800cc54: f000 f894 bl 800cd80 + App_Printf("fdev=%lu Hz\r\n", (unsigned long)g_cfg.fsk_fdev); + 800cc58: 4b2f ldr r3, [pc, #188] @ (800cd18 ) + 800cc5a: 691b ldr r3, [r3, #16] + 800cc5c: 4619 mov r1, r3 + 800cc5e: 4833 ldr r0, [pc, #204] @ (800cd2c ) + 800cc60: f000 f88e bl 800cd80 + App_Printf("preamble=%u bytes\r\n", g_cfg.fsk_preamble_len); + 800cc64: 4b2c ldr r3, [pc, #176] @ (800cd18 ) + 800cc66: 8a9b ldrh r3, [r3, #20] + 800cc68: 4619 mov r1, r3 + 800cc6a: 4831 ldr r0, [pc, #196] @ (800cd30 ) + 800cc6c: f000 f888 bl 800cd80 + App_Printf("sync=%02X%02X%02X\r\n", g_cfg.syncword[0], g_cfg.syncword[1], g_cfg.syncword[2]); + 800cc70: 4b29 ldr r3, [pc, #164] @ (800cd18 ) + 800cc72: 7d9b ldrb r3, [r3, #22] + 800cc74: 4619 mov r1, r3 + 800cc76: 4b28 ldr r3, [pc, #160] @ (800cd18 ) + 800cc78: 7ddb ldrb r3, [r3, #23] + 800cc7a: 461a mov r2, r3 + 800cc7c: 4b26 ldr r3, [pc, #152] @ (800cd18 ) + 800cc7e: 7e1b ldrb r3, [r3, #24] + 800cc80: 482c ldr r0, [pc, #176] @ (800cd34 ) + 800cc82: f000 f87d bl 800cd80 + App_Printf("uart_baud=%lu\r\n", (unsigned long)g_cfg.uart_baudrate); + 800cc86: 4b24 ldr r3, [pc, #144] @ (800cd18 ) + 800cc88: 69db ldr r3, [r3, #28] + 800cc8a: 4619 mov r1, r3 + 800cc8c: 482a ldr r0, [pc, #168] @ (800cd38 ) + 800cc8e: f000 f877 bl 800cd80 + App_Printf("uart_pkt_timeout=%u ms\r\n", g_cfg.uart_packet_timeout_ms); + 800cc92: 4b21 ldr r3, [pc, #132] @ (800cd18 ) + 800cc94: 8b5b ldrh r3, [r3, #26] + 800cc96: 4619 mov r1, r3 + 800cc98: 4828 ldr r0, [pc, #160] @ (800cd3c ) + 800cc9a: f000 f871 bl 800cd80 + App_Printf("tx_queue=%u/%u\r\n", g_tx_q_count, TX_QUEUE_DEPTH); + 800cc9e: 4b28 ldr r3, [pc, #160] @ (800cd40 ) + 800cca0: 781b ldrb r3, [r3, #0] + 800cca2: 2204 movs r2, #4 + 800cca4: 4619 mov r1, r3 + 800cca6: 4827 ldr r0, [pc, #156] @ (800cd44 ) + 800cca8: f000 f86a bl 800cd80 + App_Printf("last_rx_rssi=%d dBm\r\n", (int)g_last_rx_rssi); + 800ccac: 4b26 ldr r3, [pc, #152] @ (800cd48 ) + 800ccae: 881b ldrh r3, [r3, #0] + 800ccb0: b21b sxth r3, r3 + 800ccb2: 4619 mov r1, r3 + 800ccb4: 4825 ldr r0, [pc, #148] @ (800cd4c ) + 800ccb6: f000 f863 bl 800cd80 + App_Printf("last_rx_cfo=%d\r\n", (int)g_last_rx_cfo); + 800ccba: 4b25 ldr r3, [pc, #148] @ (800cd50 ) + 800ccbc: 781b ldrb r3, [r3, #0] + 800ccbe: b25b sxtb r3, r3 + 800ccc0: 4619 mov r1, r3 + 800ccc2: 4824 ldr r0, [pc, #144] @ (800cd54 ) + 800ccc4: f000 f85c bl 800cd80 + App_Printf("stat_uart_packets_tx=%lu\r\n", (unsigned long)g_stat_uart_packets_tx); + 800ccc8: 4b23 ldr r3, [pc, #140] @ (800cd58 ) + 800ccca: 681b ldr r3, [r3, #0] + 800cccc: 4619 mov r1, r3 + 800ccce: 4823 ldr r0, [pc, #140] @ (800cd5c ) + 800ccd0: f000 f856 bl 800cd80 + App_Printf("stat_uart_bytes_tx=%lu\r\n", (unsigned long)g_stat_uart_bytes_tx); + 800ccd4: 4b22 ldr r3, [pc, #136] @ (800cd60 ) + 800ccd6: 681b ldr r3, [r3, #0] + 800ccd8: 4619 mov r1, r3 + 800ccda: 4822 ldr r0, [pc, #136] @ (800cd64 ) + 800ccdc: f000 f850 bl 800cd80 + App_Printf("stat_radio_packets_rx=%lu\r\n", (unsigned long)g_stat_radio_packets_rx); + 800cce0: 4b21 ldr r3, [pc, #132] @ (800cd68 ) + 800cce2: 681b ldr r3, [r3, #0] + 800cce4: 4619 mov r1, r3 + 800cce6: 4821 ldr r0, [pc, #132] @ (800cd6c ) + 800cce8: f000 f84a bl 800cd80 + App_Printf("stat_radio_bytes_rx=%lu\r\n", (unsigned long)g_stat_radio_bytes_rx); + 800ccec: 4b20 ldr r3, [pc, #128] @ (800cd70 ) + 800ccee: 681b ldr r3, [r3, #0] + 800ccf0: 4619 mov r1, r3 + 800ccf2: 4820 ldr r0, [pc, #128] @ (800cd74 ) + 800ccf4: f000 f844 bl 800cd80 + App_Printf("stat_queue_overflow=%lu\r\n", (unsigned long)g_stat_queue_overflow); + 800ccf8: 4b1f ldr r3, [pc, #124] @ (800cd78 ) + 800ccfa: 681b ldr r3, [r3, #0] + 800ccfc: 4619 mov r1, r3 + 800ccfe: 481f ldr r0, [pc, #124] @ (800cd7c ) + 800cd00: f000 f83e bl 800cd80 +} + 800cd04: bf00 nop + 800cd06: bd80 pop {r7, pc} + 800cd08: 20000b64 .word 0x20000b64 + 800cd0c: 0800f874 .word 0x0800f874 + 800cd10: 0800f87c .word 0x0800f87c + 800cd14: 0800f884 .word 0x0800f884 + 800cd18: 2000000c .word 0x2000000c + 800cd1c: 0800f890 .word 0x0800f890 + 800cd20: 0800f8a0 .word 0x0800f8a0 + 800cd24: 0800f8b0 .word 0x0800f8b0 + 800cd28: 0800f8c4 .word 0x0800f8c4 + 800cd2c: 0800f8d8 .word 0x0800f8d8 + 800cd30: 0800f8e8 .word 0x0800f8e8 + 800cd34: 0800f598 .word 0x0800f598 + 800cd38: 0800f8fc .word 0x0800f8fc + 800cd3c: 0800f90c .word 0x0800f90c + 800cd40: 20000a6e .word 0x20000a6e + 800cd44: 0800f928 .word 0x0800f928 + 800cd48: 20000612 .word 0x20000612 + 800cd4c: 0800f93c .word 0x0800f93c + 800cd50: 20000614 .word 0x20000614 + 800cd54: 0800f954 .word 0x0800f954 + 800cd58: 20000bcc .word 0x20000bcc + 800cd5c: 0800f968 .word 0x0800f968 + 800cd60: 20000bd0 .word 0x20000bd0 + 800cd64: 0800f984 .word 0x0800f984 + 800cd68: 20000bd4 .word 0x20000bd4 + 800cd6c: 0800f9a0 .word 0x0800f9a0 + 800cd70: 20000bd8 .word 0x20000bd8 + 800cd74: 0800f9bc .word 0x0800f9bc + 800cd78: 20000bdc .word 0x20000bdc + 800cd7c: 0800f9d8 .word 0x0800f9d8 + +0800cd80 : + +static void App_Printf(const char *fmt, ...) +{ + 800cd80: b40f push {r0, r1, r2, r3} + 800cd82: b580 push {r7, lr} + 800cd84: b0b2 sub sp, #200 @ 0xc8 + 800cd86: af00 add r7, sp, #0 + char buffer[192]; + va_list ap; + int len; + + va_start(ap, fmt); + 800cd88: f107 03d4 add.w r3, r7, #212 @ 0xd4 + 800cd8c: 603b str r3, [r7, #0] + len = vsnprintf(buffer, sizeof(buffer), fmt, ap); + 800cd8e: 1d38 adds r0, r7, #4 + 800cd90: 683b ldr r3, [r7, #0] + 800cd92: f8d7 20d0 ldr.w r2, [r7, #208] @ 0xd0 + 800cd96: 21c0 movs r1, #192 @ 0xc0 + 800cd98: f001 fce8 bl 800e76c + 800cd9c: f8c7 00c4 str.w r0, [r7, #196] @ 0xc4 + va_end(ap); + + if (len <= 0) + 800cda0: f8d7 30c4 ldr.w r3, [r7, #196] @ 0xc4 + 800cda4: 2b00 cmp r3, #0 + 800cda6: dd0f ble.n 800cdc8 + { + return; + } + + if ((size_t)len >= sizeof(buffer)) + 800cda8: f8d7 30c4 ldr.w r3, [r7, #196] @ 0xc4 + 800cdac: 2bbf cmp r3, #191 @ 0xbf + 800cdae: d902 bls.n 800cdb6 + { + len = (int)(sizeof(buffer) - 1U); + 800cdb0: 23bf movs r3, #191 @ 0xbf + 800cdb2: f8c7 30c4 str.w r3, [r7, #196] @ 0xc4 + } + + App_Write((const uint8_t *)buffer, (uint16_t)len); + 800cdb6: f8d7 30c4 ldr.w r3, [r7, #196] @ 0xc4 + 800cdba: b29a uxth r2, r3 + 800cdbc: 1d3b adds r3, r7, #4 + 800cdbe: 4611 mov r1, r2 + 800cdc0: 4618 mov r0, r3 + 800cdc2: f000 f809 bl 800cdd8 + 800cdc6: e000 b.n 800cdca + return; + 800cdc8: bf00 nop +} + 800cdca: 37c8 adds r7, #200 @ 0xc8 + 800cdcc: 46bd mov sp, r7 + 800cdce: e8bd 4080 ldmia.w sp!, {r7, lr} + 800cdd2: b004 add sp, #16 + 800cdd4: 4770 bx lr + ... + +0800cdd8 : + +static void App_Write(const uint8_t *data, uint16_t len) +{ + 800cdd8: b580 push {r7, lr} + 800cdda: b082 sub sp, #8 + 800cddc: af00 add r7, sp, #0 + 800cdde: 6078 str r0, [r7, #4] + 800cde0: 460b mov r3, r1 + 800cde2: 807b strh r3, [r7, #2] + if ((data == NULL) || (len == 0U)) + 800cde4: 687b ldr r3, [r7, #4] + 800cde6: 2b00 cmp r3, #0 + 800cde8: d00a beq.n 800ce00 + 800cdea: 887b ldrh r3, [r7, #2] + 800cdec: 2b00 cmp r3, #0 + 800cdee: d007 beq.n 800ce00 + { + return; + } + + (void)HAL_UART_Transmit(&huart2, (uint8_t *)data, len, 1000U); + 800cdf0: 887a ldrh r2, [r7, #2] + 800cdf2: f44f 737a mov.w r3, #1000 @ 0x3e8 + 800cdf6: 6879 ldr r1, [r7, #4] + 800cdf8: 4803 ldr r0, [pc, #12] @ (800ce08 ) + 800cdfa: f7f8 fa26 bl 800524a + 800cdfe: e000 b.n 800ce02 + return; + 800ce00: bf00 nop +} + 800ce02: 3708 adds r7, #8 + 800ce04: 46bd mov sp, r7 + 800ce06: bd80 pop {r7, pc} + 800ce08: 200000fc .word 0x200000fc + +0800ce0c : + +static void App_ReconfigureUart(uint32_t baudrate) +{ + 800ce0c: b580 push {r7, lr} + 800ce0e: b082 sub sp, #8 + 800ce10: af00 add r7, sp, #0 + 800ce12: 6078 str r0, [r7, #4] + huart2.Init.BaudRate = baudrate; + 800ce14: 4a17 ldr r2, [pc, #92] @ (800ce74 ) + 800ce16: 687b ldr r3, [r7, #4] + 800ce18: 6053 str r3, [r2, #4] + + (void)HAL_UART_AbortReceive(&huart2); + 800ce1a: 4816 ldr r0, [pc, #88] @ (800ce74 ) + 800ce1c: f7f8 fb7a bl 8005514 + + if (HAL_UART_Init(&huart2) != HAL_OK) + 800ce20: 4814 ldr r0, [pc, #80] @ (800ce74 ) + 800ce22: f7f8 f9c2 bl 80051aa + 800ce26: 4603 mov r3, r0 + 800ce28: 2b00 cmp r3, #0 + 800ce2a: d001 beq.n 800ce30 + { + Error_Handler(); + 800ce2c: f7f3 fcd0 bl 80007d0 + } + if (HAL_UARTEx_SetTxFifoThreshold(&huart2, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK) + 800ce30: 2100 movs r1, #0 + 800ce32: 4810 ldr r0, [pc, #64] @ (800ce74 ) + 800ce34: f7fa fc3d bl 80076b2 + 800ce38: 4603 mov r3, r0 + 800ce3a: 2b00 cmp r3, #0 + 800ce3c: d001 beq.n 800ce42 + { + Error_Handler(); + 800ce3e: f7f3 fcc7 bl 80007d0 + } + if (HAL_UARTEx_SetRxFifoThreshold(&huart2, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK) + 800ce42: 2100 movs r1, #0 + 800ce44: 480b ldr r0, [pc, #44] @ (800ce74 ) + 800ce46: f7fa fc72 bl 800772e + 800ce4a: 4603 mov r3, r0 + 800ce4c: 2b00 cmp r3, #0 + 800ce4e: d001 beq.n 800ce54 + { + Error_Handler(); + 800ce50: f7f3 fcbe bl 80007d0 + } + if (HAL_UARTEx_EnableFifoMode(&huart2) != HAL_OK) + 800ce54: 4807 ldr r0, [pc, #28] @ (800ce74 ) + 800ce56: f7fa fbf1 bl 800763c + 800ce5a: 4603 mov r3, r0 + 800ce5c: 2b00 cmp r3, #0 + 800ce5e: d001 beq.n 800ce64 + { + Error_Handler(); + 800ce60: f7f3 fcb6 bl 80007d0 + } + + (void)vcom_ReceiveInit(UartRxByteCallback); + 800ce64: 4804 ldr r0, [pc, #16] @ (800ce78 ) + 800ce66: f7f4 fba1 bl 80015ac +} + 800ce6a: bf00 nop + 800ce6c: 3708 adds r7, #8 + 800ce6e: 46bd mov sp, r7 + 800ce70: bd80 pop {r7, pc} + 800ce72: bf00 nop + 800ce74: 200000fc .word 0x200000fc + 800ce78: 0800c4e5 .word 0x0800c4e5 + +0800ce7c : + +static uint8_t App_ParseHexSyncWord(const char *text, uint8_t out[3]) +{ + 800ce7c: b580 push {r7, lr} + 800ce7e: b088 sub sp, #32 + 800ce80: af00 add r7, sp, #0 + 800ce82: 6078 str r0, [r7, #4] + 800ce84: 6039 str r1, [r7, #0] + char buf[7]; + char *endptr; + unsigned long value; + size_t i; + size_t n = 0U; + 800ce86: 2300 movs r3, #0 + 800ce88: 61bb str r3, [r7, #24] + + if ((text == NULL) || (out == NULL)) + 800ce8a: 687b ldr r3, [r7, #4] + 800ce8c: 2b00 cmp r3, #0 + 800ce8e: d002 beq.n 800ce96 + 800ce90: 683b ldr r3, [r7, #0] + 800ce92: 2b00 cmp r3, #0 + 800ce94: d117 bne.n 800cec6 + { + return 0U; + 800ce96: 2300 movs r3, #0 + 800ce98: e05f b.n 800cf5a + } + + while ((*text != '\0') && (n < 6U)) + { + if (isxdigit((unsigned char)*text) != 0) + 800ce9a: 687b ldr r3, [r7, #4] + 800ce9c: 781b ldrb r3, [r3, #0] + 800ce9e: 3301 adds r3, #1 + 800cea0: 4a30 ldr r2, [pc, #192] @ (800cf64 ) + 800cea2: 4413 add r3, r2 + 800cea4: 781b ldrb r3, [r3, #0] + 800cea6: f003 0344 and.w r3, r3, #68 @ 0x44 + 800ceaa: 2b00 cmp r3, #0 + 800ceac: d008 beq.n 800cec0 + { + buf[n++] = *text; + 800ceae: 69bb ldr r3, [r7, #24] + 800ceb0: 1c5a adds r2, r3, #1 + 800ceb2: 61ba str r2, [r7, #24] + 800ceb4: 687a ldr r2, [r7, #4] + 800ceb6: 7812 ldrb r2, [r2, #0] + 800ceb8: 3320 adds r3, #32 + 800ceba: 443b add r3, r7 + 800cebc: f803 2c14 strb.w r2, [r3, #-20] + } + text++; + 800cec0: 687b ldr r3, [r7, #4] + 800cec2: 3301 adds r3, #1 + 800cec4: 607b str r3, [r7, #4] + while ((*text != '\0') && (n < 6U)) + 800cec6: 687b ldr r3, [r7, #4] + 800cec8: 781b ldrb r3, [r3, #0] + 800ceca: 2b00 cmp r3, #0 + 800cecc: d002 beq.n 800ced4 + 800cece: 69bb ldr r3, [r7, #24] + 800ced0: 2b05 cmp r3, #5 + 800ced2: d9e2 bls.n 800ce9a + } + + if (n != 6U) + 800ced4: 69bb ldr r3, [r7, #24] + 800ced6: 2b06 cmp r3, #6 + 800ced8: d001 beq.n 800cede + { + return 0U; + 800ceda: 2300 movs r3, #0 + 800cedc: e03d b.n 800cf5a + } + + for (i = 0U; i < n; i++) + 800cede: 2300 movs r3, #0 + 800cee0: 61fb str r3, [r7, #28] + 800cee2: e011 b.n 800cf08 + { + if (isxdigit((unsigned char)buf[i]) == 0) + 800cee4: f107 020c add.w r2, r7, #12 + 800cee8: 69fb ldr r3, [r7, #28] + 800ceea: 4413 add r3, r2 + 800ceec: 781b ldrb r3, [r3, #0] + 800ceee: 3301 adds r3, #1 + 800cef0: 4a1c ldr r2, [pc, #112] @ (800cf64 ) + 800cef2: 4413 add r3, r2 + 800cef4: 781b ldrb r3, [r3, #0] + 800cef6: f003 0344 and.w r3, r3, #68 @ 0x44 + 800cefa: 2b00 cmp r3, #0 + 800cefc: d101 bne.n 800cf02 + { + return 0U; + 800cefe: 2300 movs r3, #0 + 800cf00: e02b b.n 800cf5a + for (i = 0U; i < n; i++) + 800cf02: 69fb ldr r3, [r7, #28] + 800cf04: 3301 adds r3, #1 + 800cf06: 61fb str r3, [r7, #28] + 800cf08: 69fa ldr r2, [r7, #28] + 800cf0a: 69bb ldr r3, [r7, #24] + 800cf0c: 429a cmp r2, r3 + 800cf0e: d3e9 bcc.n 800cee4 + } + } + + buf[6] = '\0'; + 800cf10: 2300 movs r3, #0 + 800cf12: 74bb strb r3, [r7, #18] + value = strtoul(buf, &endptr, 16); + 800cf14: f107 0108 add.w r1, r7, #8 + 800cf18: f107 030c add.w r3, r7, #12 + 800cf1c: 2210 movs r2, #16 + 800cf1e: 4618 mov r0, r3 + 800cf20: f001 fbec bl 800e6fc + 800cf24: 6178 str r0, [r7, #20] + if ((endptr == NULL) || (*endptr != '\0')) + 800cf26: 68bb ldr r3, [r7, #8] + 800cf28: 2b00 cmp r3, #0 + 800cf2a: d003 beq.n 800cf34 + 800cf2c: 68bb ldr r3, [r7, #8] + 800cf2e: 781b ldrb r3, [r3, #0] + 800cf30: 2b00 cmp r3, #0 + 800cf32: d001 beq.n 800cf38 + { + return 0U; + 800cf34: 2300 movs r3, #0 + 800cf36: e010 b.n 800cf5a + } + + out[0] = (uint8_t)((value >> 16) & 0xFFU); + 800cf38: 697b ldr r3, [r7, #20] + 800cf3a: 0c1b lsrs r3, r3, #16 + 800cf3c: b2da uxtb r2, r3 + 800cf3e: 683b ldr r3, [r7, #0] + 800cf40: 701a strb r2, [r3, #0] + out[1] = (uint8_t)((value >> 8) & 0xFFU); + 800cf42: 697b ldr r3, [r7, #20] + 800cf44: 0a1a lsrs r2, r3, #8 + 800cf46: 683b ldr r3, [r7, #0] + 800cf48: 3301 adds r3, #1 + 800cf4a: b2d2 uxtb r2, r2 + 800cf4c: 701a strb r2, [r3, #0] + out[2] = (uint8_t)(value & 0xFFU); + 800cf4e: 683b ldr r3, [r7, #0] + 800cf50: 3302 adds r3, #2 + 800cf52: 697a ldr r2, [r7, #20] + 800cf54: b2d2 uxtb r2, r2 + 800cf56: 701a strb r2, [r3, #0] + return 1U; + 800cf58: 2301 movs r3, #1 +} + 800cf5a: 4618 mov r0, r3 + 800cf5c: 3720 adds r7, #32 + 800cf5e: 46bd mov sp, r7 + 800cf60: bd80 pop {r7, pc} + 800cf62: bf00 nop + 800cf64: 0800fccc .word 0x0800fccc + +0800cf68 : + +static char *App_SkipSpaces(char *s) +{ + 800cf68: b480 push {r7} + 800cf6a: b083 sub sp, #12 + 800cf6c: af00 add r7, sp, #0 + 800cf6e: 6078 str r0, [r7, #4] + while ((s != NULL) && (*s != '\0') && isspace((unsigned char)*s)) + 800cf70: e002 b.n 800cf78 + { + s++; + 800cf72: 687b ldr r3, [r7, #4] + 800cf74: 3301 adds r3, #1 + 800cf76: 607b str r3, [r7, #4] + while ((s != NULL) && (*s != '\0') && isspace((unsigned char)*s)) + 800cf78: 687b ldr r3, [r7, #4] + 800cf7a: 2b00 cmp r3, #0 + 800cf7c: d00d beq.n 800cf9a + 800cf7e: 687b ldr r3, [r7, #4] + 800cf80: 781b ldrb r3, [r3, #0] + 800cf82: 2b00 cmp r3, #0 + 800cf84: d009 beq.n 800cf9a + 800cf86: 687b ldr r3, [r7, #4] + 800cf88: 781b ldrb r3, [r3, #0] + 800cf8a: 3301 adds r3, #1 + 800cf8c: 4a06 ldr r2, [pc, #24] @ (800cfa8 ) + 800cf8e: 4413 add r3, r2 + 800cf90: 781b ldrb r3, [r3, #0] + 800cf92: f003 0308 and.w r3, r3, #8 + 800cf96: 2b00 cmp r3, #0 + 800cf98: d1eb bne.n 800cf72 + } + return s; + 800cf9a: 687b ldr r3, [r7, #4] +} + 800cf9c: 4618 mov r0, r3 + 800cf9e: 370c adds r7, #12 + 800cfa0: 46bd mov sp, r7 + 800cfa2: bc80 pop {r7} + 800cfa4: 4770 bx lr + 800cfa6: bf00 nop + 800cfa8: 0800fccc .word 0x0800fccc + +0800cfac : + +static void OnTxDone(void) +{ + 800cfac: b480 push {r7} + 800cfae: af00 add r7, sp, #0 + g_radio_tx_done = 1U; + 800cfb0: 4b03 ldr r3, [pc, #12] @ (800cfc0 ) + 800cfb2: 2201 movs r2, #1 + 800cfb4: 701a strb r2, [r3, #0] +} + 800cfb6: bf00 nop + 800cfb8: 46bd mov sp, r7 + 800cfba: bc80 pop {r7} + 800cfbc: 4770 bx lr + 800cfbe: bf00 nop + 800cfc0: 2000060c .word 0x2000060c + +0800cfc4 : + +static void OnRxDone(uint8_t *payload, uint16_t size, int16_t rssi, int8_t cfo) +{ + 800cfc4: b580 push {r7, lr} + 800cfc6: b084 sub sp, #16 + 800cfc8: af00 add r7, sp, #0 + 800cfca: 60f8 str r0, [r7, #12] + 800cfcc: 4608 mov r0, r1 + 800cfce: 4611 mov r1, r2 + 800cfd0: 461a mov r2, r3 + 800cfd2: 4603 mov r3, r0 + 800cfd4: 817b strh r3, [r7, #10] + 800cfd6: 460b mov r3, r1 + 800cfd8: 813b strh r3, [r7, #8] + 800cfda: 4613 mov r3, r2 + 800cfdc: 71fb strb r3, [r7, #7] + g_last_rx_rssi = rssi; + 800cfde: 4a0d ldr r2, [pc, #52] @ (800d014 ) + 800cfe0: 893b ldrh r3, [r7, #8] + 800cfe2: 8013 strh r3, [r2, #0] + g_last_rx_cfo = cfo; + 800cfe4: 4a0c ldr r2, [pc, #48] @ (800d018 ) + 800cfe6: 79fb ldrb r3, [r7, #7] + 800cfe8: 7013 strb r3, [r2, #0] + + if (size > RADIO_MAX_PAYLOAD_SIZE) + 800cfea: 897b ldrh r3, [r7, #10] + 800cfec: 2bdc cmp r3, #220 @ 0xdc + 800cfee: d901 bls.n 800cff4 + { + size = RADIO_MAX_PAYLOAD_SIZE; + 800cff0: 23dc movs r3, #220 @ 0xdc + 800cff2: 817b strh r3, [r7, #10] + } + + memcpy(g_rx_payload, payload, size); + 800cff4: 897b ldrh r3, [r7, #10] + 800cff6: 461a mov r2, r3 + 800cff8: 68f9 ldr r1, [r7, #12] + 800cffa: 4808 ldr r0, [pc, #32] @ (800d01c ) + 800cffc: f001 fc0a bl 800e814 + g_rx_payload_len = size; + 800d000: 4a07 ldr r2, [pc, #28] @ (800d020 ) + 800d002: 897b ldrh r3, [r7, #10] + 800d004: 8013 strh r3, [r2, #0] + g_radio_rx_done = 1U; + 800d006: 4b07 ldr r3, [pc, #28] @ (800d024 ) + 800d008: 2201 movs r2, #1 + 800d00a: 701a strb r2, [r3, #0] +} + 800d00c: bf00 nop + 800d00e: 3710 adds r7, #16 + 800d010: 46bd mov sp, r7 + 800d012: bd80 pop {r7, pc} + 800d014: 20000612 .word 0x20000612 + 800d018: 20000614 .word 0x20000614 + 800d01c: 20000618 .word 0x20000618 + 800d020: 200006f4 .word 0x200006f4 + 800d024: 2000060e .word 0x2000060e + +0800d028 : + +static void OnTxTimeout(void) +{ + 800d028: b480 push {r7} + 800d02a: af00 add r7, sp, #0 + g_radio_tx_timeout = 1U; + 800d02c: 4b03 ldr r3, [pc, #12] @ (800d03c ) + 800d02e: 2201 movs r2, #1 + 800d030: 701a strb r2, [r3, #0] +} + 800d032: bf00 nop + 800d034: 46bd mov sp, r7 + 800d036: bc80 pop {r7} + 800d038: 4770 bx lr + 800d03a: bf00 nop + 800d03c: 2000060d .word 0x2000060d + +0800d040 : + +static void OnRxTimeout(void) +{ + 800d040: b480 push {r7} + 800d042: af00 add r7, sp, #0 + g_radio_rx_timeout = 1U; + 800d044: 4b03 ldr r3, [pc, #12] @ (800d054 ) + 800d046: 2201 movs r2, #1 + 800d048: 701a strb r2, [r3, #0] +} + 800d04a: bf00 nop + 800d04c: 46bd mov sp, r7 + 800d04e: bc80 pop {r7} + 800d050: 4770 bx lr + 800d052: bf00 nop + 800d054: 2000060f .word 0x2000060f + +0800d058 : + +static void OnRxError(void) +{ + 800d058: b480 push {r7} + 800d05a: af00 add r7, sp, #0 + g_radio_rx_error = 1U; + 800d05c: 4b03 ldr r3, [pc, #12] @ (800d06c ) + 800d05e: 2201 movs r2, #1 + 800d060: 701a strb r2, [r3, #0] +} + 800d062: bf00 nop + 800d064: 46bd mov sp, r7 + 800d066: bc80 pop {r7} + 800d068: 4770 bx lr + 800d06a: bf00 nop + 800d06c: 20000610 .word 0x20000610 + +0800d070 : + +/* USER CODE END PFP */ + +/* Exported functions --------------------------------------------------------*/ +int32_t RBI_Init(void) +{ + 800d070: b580 push {r7, lr} + 800d072: af00 add r7, sp, #0 + * 1/ For User boards, the BSP/STM32WLxx_Nucleo/ directory can be copied and replaced in the project. The copy must then be updated depending: + * on board RF switch configuration (pin control, number of port etc) + * on TCXO configuration + * on DC/DC configuration + * on maximum output power that the board can deliver*/ + return BSP_RADIO_Init(); + 800d074: f7f4 fb70 bl 8001758 + 800d078: 4603 mov r3, r0 + /* USER CODE BEGIN RBI_Init_2 */ +#warning user to provide its board code or to call his board driver functions + /* USER CODE END RBI_Init_2 */ + return retcode; +#endif /* USE_BSP_DRIVER */ +} + 800d07a: 4618 mov r0, r3 + 800d07c: bd80 pop {r7, pc} + +0800d07e : + return retcode; +#endif /* USE_BSP_DRIVER */ +} + +int32_t RBI_ConfigRFSwitch(RBI_Switch_TypeDef Config) +{ + 800d07e: b580 push {r7, lr} + 800d080: b082 sub sp, #8 + 800d082: af00 add r7, sp, #0 + 800d084: 4603 mov r3, r0 + 800d086: 71fb strb r3, [r7, #7] + * 1/ For User boards, the BSP/STM32WLxx_Nucleo/ directory can be copied and replaced in the project. The copy must then be updated depending: + * on board RF switch configuration (pin control, number of port etc) + * on TCXO configuration + * on DC/DC configuration + * on maximum output power that the board can deliver*/ + return BSP_RADIO_ConfigRFSwitch((BSP_RADIO_Switch_TypeDef) Config); + 800d088: 79fb ldrb r3, [r7, #7] + 800d08a: 4618 mov r0, r3 + 800d08c: f7f4 fba2 bl 80017d4 + 800d090: 4603 mov r3, r0 + /* USER CODE BEGIN RBI_ConfigRFSwitch_2 */ +#warning user to provide its board code or to call his board driver functions + /* USER CODE END RBI_ConfigRFSwitch_2 */ + return retcode; +#endif /* USE_BSP_DRIVER */ +} + 800d092: 4618 mov r0, r3 + 800d094: 3708 adds r7, #8 + 800d096: 46bd mov sp, r7 + 800d098: bd80 pop {r7, pc} + +0800d09a : + +int32_t RBI_GetTxConfig(void) +{ + 800d09a: b580 push {r7, lr} + 800d09c: af00 add r7, sp, #0 + * 1/ For User boards, the BSP/STM32WLxx_Nucleo/ directory can be copied and replaced in the project. The copy must then be updated depending: + * on board RF switch configuration (pin control, number of port etc) + * on TCXO configuration + * on DC/DC configuration + * on maximum output power that the board can deliver*/ + return BSP_RADIO_GetTxConfig(); + 800d09e: f7f4 fbf5 bl 800188c + 800d0a2: 4603 mov r3, r0 + /* USER CODE BEGIN RBI_GetTxConfig_2 */ +#warning user to provide its board code or to call his board driver functions + /* USER CODE END RBI_GetTxConfig_2 */ + return retcode; +#endif /* USE_BSP_DRIVER */ +} + 800d0a4: 4618 mov r0, r3 + 800d0a6: bd80 pop {r7, pc} + +0800d0a8 : + +int32_t RBI_IsTCXO(void) +{ + 800d0a8: b580 push {r7, lr} + 800d0aa: af00 add r7, sp, #0 + * 1/ For User boards, the BSP/STM32WLxx_Nucleo/ directory can be copied and replaced in the project. The copy must then be updated depending: + * on board RF switch configuration (pin control, number of port etc) + * on TCXO configuration + * on DC/DC configuration + * on maximum output power that the board can deliver*/ + return BSP_RADIO_IsTCXO(); + 800d0ac: f7f4 fbf5 bl 800189a + 800d0b0: 4603 mov r3, r0 + /* USER CODE BEGIN RBI_IsTCXO_2 */ +#warning user to provide its board code or to call his board driver functions + /* USER CODE END RBI_IsTCXO_2 */ + return retcode; +#endif /* USE_BSP_DRIVER */ +} + 800d0b2: 4618 mov r0, r3 + 800d0b4: bd80 pop {r7, pc} + +0800d0b6 : + +int32_t RBI_IsDCDC(void) +{ + 800d0b6: b580 push {r7, lr} + 800d0b8: af00 add r7, sp, #0 + * 1/ For User boards, the BSP/STM32WLxx_Nucleo/ directory can be copied and replaced in the project. The copy must then be updated depending: + * on board RF switch configuration (pin control, number of port etc) + * on TCXO configuration + * on DC/DC configuration + * on maximum output power that the board can deliver*/ + return BSP_RADIO_IsDCDC(); + 800d0ba: f7f4 fbf5 bl 80018a8 + 800d0be: 4603 mov r3, r0 + /* USER CODE BEGIN RBI_IsDCDC_2 */ +#warning user to provide its board code or to call his board driver functions + /* USER CODE END RBI_IsDCDC_2 */ + return retcode; +#endif /* USE_BSP_DRIVER */ +} + 800d0c0: 4618 mov r0, r3 + 800d0c2: bd80 pop {r7, pc} + +0800d0c4 : + +int32_t RBI_GetRFOMaxPowerConfig(RBI_RFOMaxPowerConfig_TypeDef Config) +{ + 800d0c4: b580 push {r7, lr} + 800d0c6: b082 sub sp, #8 + 800d0c8: af00 add r7, sp, #0 + 800d0ca: 4603 mov r3, r0 + 800d0cc: 71fb strb r3, [r7, #7] + * 1/ For User boards, the BSP/STM32WLxx_Nucleo/ directory can be copied and replaced in the project. The copy must then be updated depending: + * on board RF switch configuration (pin control, number of port etc) + * on TCXO configuration + * on DC/DC configuration + * on maximum output power that the board can deliver*/ + return BSP_RADIO_GetRFOMaxPowerConfig((BSP_RADIO_RFOMaxPowerConfig_TypeDef) Config); + 800d0ce: 79fb ldrb r3, [r7, #7] + 800d0d0: 4618 mov r0, r3 + 800d0d2: f7f4 fbf0 bl 80018b6 + 800d0d6: 4603 mov r3, r0 + ret = 22; /*dBm*/ + } + /* USER CODE END RBI_GetRFOMaxPowerConfig_2 */ + return ret; +#endif /* USE_BSP_DRIVER */ +} + 800d0d8: 4618 mov r0, r3 + 800d0da: 3708 adds r7, #8 + 800d0dc: 46bd mov sp, r7 + 800d0de: bd80 pop {r7, pc} + +0800d0e0 : + +/** @addtogroup TINY_LPM_Exported_function + * @{ + */ +void UTIL_LPM_Init( void ) +{ + 800d0e0: b480 push {r7} + 800d0e2: af00 add r7, sp, #0 + StopModeDisable = UTIL_LPM_NO_BIT_SET; + 800d0e4: 4b04 ldr r3, [pc, #16] @ (800d0f8 ) + 800d0e6: 2200 movs r2, #0 + 800d0e8: 601a str r2, [r3, #0] + OffModeDisable = UTIL_LPM_NO_BIT_SET; + 800d0ea: 4b04 ldr r3, [pc, #16] @ (800d0fc ) + 800d0ec: 2200 movs r2, #0 + 800d0ee: 601a str r2, [r3, #0] + UTIL_LPM_INIT_CRITICAL_SECTION( ); +} + 800d0f0: bf00 nop + 800d0f2: 46bd mov sp, r7 + 800d0f4: bc80 pop {r7} + 800d0f6: 4770 bx lr + 800d0f8: 20000be0 .word 0x20000be0 + 800d0fc: 20000be4 .word 0x20000be4 + +0800d100 : +void UTIL_LPM_DeInit( void ) +{ +} + +void UTIL_LPM_SetStopMode( UTIL_LPM_bm_t lpm_id_bm, UTIL_LPM_State_t state ) +{ + 800d100: b480 push {r7} + 800d102: b087 sub sp, #28 + 800d104: af00 add r7, sp, #0 + 800d106: 6078 str r0, [r7, #4] + 800d108: 460b mov r3, r1 + 800d10a: 70fb strb r3, [r7, #3] + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 800d10c: f3ef 8310 mrs r3, PRIMASK + 800d110: 613b str r3, [r7, #16] + return(result); + 800d112: 693b ldr r3, [r7, #16] + UTIL_LPM_ENTER_CRITICAL_SECTION( ); + 800d114: 617b str r3, [r7, #20] + __ASM volatile ("cpsid i" : : : "memory"); + 800d116: b672 cpsid i +} + 800d118: bf00 nop + + switch( state ) + 800d11a: 78fb ldrb r3, [r7, #3] + 800d11c: 2b00 cmp r3, #0 + 800d11e: d008 beq.n 800d132 + 800d120: 2b01 cmp r3, #1 + 800d122: d10e bne.n 800d142 + { + case UTIL_LPM_DISABLE: + { + StopModeDisable |= lpm_id_bm; + 800d124: 4b0d ldr r3, [pc, #52] @ (800d15c ) + 800d126: 681a ldr r2, [r3, #0] + 800d128: 687b ldr r3, [r7, #4] + 800d12a: 4313 orrs r3, r2 + 800d12c: 4a0b ldr r2, [pc, #44] @ (800d15c ) + 800d12e: 6013 str r3, [r2, #0] + break; + 800d130: e008 b.n 800d144 + } + case UTIL_LPM_ENABLE: + { + StopModeDisable &= ( ~lpm_id_bm ); + 800d132: 687b ldr r3, [r7, #4] + 800d134: 43da mvns r2, r3 + 800d136: 4b09 ldr r3, [pc, #36] @ (800d15c ) + 800d138: 681b ldr r3, [r3, #0] + 800d13a: 4013 ands r3, r2 + 800d13c: 4a07 ldr r2, [pc, #28] @ (800d15c ) + 800d13e: 6013 str r3, [r2, #0] + break; + 800d140: e000 b.n 800d144 + } + default : + { + break; + 800d142: bf00 nop + 800d144: 697b ldr r3, [r7, #20] + 800d146: 60fb str r3, [r7, #12] + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 800d148: 68fb ldr r3, [r7, #12] + 800d14a: f383 8810 msr PRIMASK, r3 +} + 800d14e: bf00 nop + } + } + + UTIL_LPM_EXIT_CRITICAL_SECTION( ); +} + 800d150: bf00 nop + 800d152: 371c adds r7, #28 + 800d154: 46bd mov sp, r7 + 800d156: bc80 pop {r7} + 800d158: 4770 bx lr + 800d15a: bf00 nop + 800d15c: 20000be0 .word 0x20000be0 + +0800d160 : + +void UTIL_LPM_SetOffMode( UTIL_LPM_bm_t lpm_id_bm, UTIL_LPM_State_t state ) +{ + 800d160: b480 push {r7} + 800d162: b087 sub sp, #28 + 800d164: af00 add r7, sp, #0 + 800d166: 6078 str r0, [r7, #4] + 800d168: 460b mov r3, r1 + 800d16a: 70fb strb r3, [r7, #3] + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 800d16c: f3ef 8310 mrs r3, PRIMASK + 800d170: 613b str r3, [r7, #16] + return(result); + 800d172: 693b ldr r3, [r7, #16] + UTIL_LPM_ENTER_CRITICAL_SECTION( ); + 800d174: 617b str r3, [r7, #20] + __ASM volatile ("cpsid i" : : : "memory"); + 800d176: b672 cpsid i +} + 800d178: bf00 nop + + switch(state) + 800d17a: 78fb ldrb r3, [r7, #3] + 800d17c: 2b00 cmp r3, #0 + 800d17e: d008 beq.n 800d192 + 800d180: 2b01 cmp r3, #1 + 800d182: d10e bne.n 800d1a2 + { + case UTIL_LPM_DISABLE: + { + OffModeDisable |= lpm_id_bm; + 800d184: 4b0d ldr r3, [pc, #52] @ (800d1bc ) + 800d186: 681a ldr r2, [r3, #0] + 800d188: 687b ldr r3, [r7, #4] + 800d18a: 4313 orrs r3, r2 + 800d18c: 4a0b ldr r2, [pc, #44] @ (800d1bc ) + 800d18e: 6013 str r3, [r2, #0] + break; + 800d190: e008 b.n 800d1a4 + } + case UTIL_LPM_ENABLE: + { + OffModeDisable &= ( ~lpm_id_bm ); + 800d192: 687b ldr r3, [r7, #4] + 800d194: 43da mvns r2, r3 + 800d196: 4b09 ldr r3, [pc, #36] @ (800d1bc ) + 800d198: 681b ldr r3, [r3, #0] + 800d19a: 4013 ands r3, r2 + 800d19c: 4a07 ldr r2, [pc, #28] @ (800d1bc ) + 800d19e: 6013 str r3, [r2, #0] + break; + 800d1a0: e000 b.n 800d1a4 + } + default : + { + break; + 800d1a2: bf00 nop + 800d1a4: 697b ldr r3, [r7, #20] + 800d1a6: 60fb str r3, [r7, #12] + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 800d1a8: 68fb ldr r3, [r7, #12] + 800d1aa: f383 8810 msr PRIMASK, r3 +} + 800d1ae: bf00 nop + } + } + + UTIL_LPM_EXIT_CRITICAL_SECTION( ); +} + 800d1b0: bf00 nop + 800d1b2: 371c adds r7, #28 + 800d1b4: 46bd mov sp, r7 + 800d1b6: bc80 pop {r7} + 800d1b8: 4770 bx lr + 800d1ba: bf00 nop + 800d1bc: 20000be4 .word 0x20000be4 + +0800d1c0 : + + return mode_selected; +} + +void UTIL_LPM_EnterLowPower( void ) +{ + 800d1c0: b580 push {r7, lr} + 800d1c2: b084 sub sp, #16 + 800d1c4: af00 add r7, sp, #0 + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 800d1c6: f3ef 8310 mrs r3, PRIMASK + 800d1ca: 60bb str r3, [r7, #8] + return(result); + 800d1cc: 68bb ldr r3, [r7, #8] + UTIL_LPM_ENTER_CRITICAL_SECTION_ELP( ); + 800d1ce: 60fb str r3, [r7, #12] + __ASM volatile ("cpsid i" : : : "memory"); + 800d1d0: b672 cpsid i +} + 800d1d2: bf00 nop + + if( StopModeDisable != UTIL_LPM_NO_BIT_SET ) + 800d1d4: 4b12 ldr r3, [pc, #72] @ (800d220 ) + 800d1d6: 681b ldr r3, [r3, #0] + 800d1d8: 2b00 cmp r3, #0 + 800d1da: d006 beq.n 800d1ea + { + /** + * At least one user disallows Stop Mode + * SLEEP mode is required + */ + UTIL_PowerDriver.EnterSleepMode( ); + 800d1dc: 4b11 ldr r3, [pc, #68] @ (800d224 ) + 800d1de: 681b ldr r3, [r3, #0] + 800d1e0: 4798 blx r3 + UTIL_PowerDriver.ExitSleepMode( ); + 800d1e2: 4b10 ldr r3, [pc, #64] @ (800d224 ) + 800d1e4: 685b ldr r3, [r3, #4] + 800d1e6: 4798 blx r3 + 800d1e8: e010 b.n 800d20c + } + else + { + if( OffModeDisable != UTIL_LPM_NO_BIT_SET ) + 800d1ea: 4b0f ldr r3, [pc, #60] @ (800d228 ) + 800d1ec: 681b ldr r3, [r3, #0] + 800d1ee: 2b00 cmp r3, #0 + 800d1f0: d006 beq.n 800d200 + { + /** + * At least one user disallows Off Mode + * STOP mode is required + */ + UTIL_PowerDriver.EnterStopMode( ); + 800d1f2: 4b0c ldr r3, [pc, #48] @ (800d224 ) + 800d1f4: 689b ldr r3, [r3, #8] + 800d1f6: 4798 blx r3 + UTIL_PowerDriver.ExitStopMode( ); + 800d1f8: 4b0a ldr r3, [pc, #40] @ (800d224 ) + 800d1fa: 68db ldr r3, [r3, #12] + 800d1fc: 4798 blx r3 + 800d1fe: e005 b.n 800d20c + else + { + /** + * OFF mode is required + */ + UTIL_PowerDriver.EnterOffMode( ); + 800d200: 4b08 ldr r3, [pc, #32] @ (800d224 ) + 800d202: 691b ldr r3, [r3, #16] + 800d204: 4798 blx r3 + UTIL_PowerDriver.ExitOffMode( ); + 800d206: 4b07 ldr r3, [pc, #28] @ (800d224 ) + 800d208: 695b ldr r3, [r3, #20] + 800d20a: 4798 blx r3 + 800d20c: 68fb ldr r3, [r7, #12] + 800d20e: 607b str r3, [r7, #4] + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 800d210: 687b ldr r3, [r7, #4] + 800d212: f383 8810 msr PRIMASK, r3 +} + 800d216: bf00 nop + } + } + + UTIL_LPM_EXIT_CRITICAL_SECTION_ELP( ); +} + 800d218: bf00 nop + 800d21a: 3710 adds r7, #16 + 800d21c: 46bd mov sp, r7 + 800d21e: bd80 pop {r7, pc} + 800d220: 20000be0 .word 0x20000be0 + 800d224: 0800fa4c .word 0x0800fa4c + 800d228: 20000be4 .word 0x20000be4 + +0800d22c : +/* Global variables ----------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Functions Definition ------------------------------------------------------*/ + +void UTIL_MEM_cpy_8( void *dst, const void *src, uint16_t size ) +{ + 800d22c: b480 push {r7} + 800d22e: b087 sub sp, #28 + 800d230: af00 add r7, sp, #0 + 800d232: 60f8 str r0, [r7, #12] + 800d234: 60b9 str r1, [r7, #8] + 800d236: 4613 mov r3, r2 + 800d238: 80fb strh r3, [r7, #6] + uint8_t* dst8= (uint8_t *) dst; + 800d23a: 68fb ldr r3, [r7, #12] + 800d23c: 617b str r3, [r7, #20] + uint8_t* src8= (uint8_t *) src; + 800d23e: 68bb ldr r3, [r7, #8] + 800d240: 613b str r3, [r7, #16] + + while( size-- ) + 800d242: e007 b.n 800d254 + { + *dst8++ = *src8++; + 800d244: 693a ldr r2, [r7, #16] + 800d246: 1c53 adds r3, r2, #1 + 800d248: 613b str r3, [r7, #16] + 800d24a: 697b ldr r3, [r7, #20] + 800d24c: 1c59 adds r1, r3, #1 + 800d24e: 6179 str r1, [r7, #20] + 800d250: 7812 ldrb r2, [r2, #0] + 800d252: 701a strb r2, [r3, #0] + while( size-- ) + 800d254: 88fb ldrh r3, [r7, #6] + 800d256: 1e5a subs r2, r3, #1 + 800d258: 80fa strh r2, [r7, #6] + 800d25a: 2b00 cmp r3, #0 + 800d25c: d1f2 bne.n 800d244 + } +} + 800d25e: bf00 nop + 800d260: bf00 nop + 800d262: 371c adds r7, #28 + 800d264: 46bd mov sp, r7 + 800d266: bc80 pop {r7} + 800d268: 4770 bx lr + +0800d26a : + *dst8-- = *src8++; + } +} + +void UTIL_MEM_set_8( void *dst, uint8_t value, uint16_t size ) +{ + 800d26a: b480 push {r7} + 800d26c: b085 sub sp, #20 + 800d26e: af00 add r7, sp, #0 + 800d270: 6078 str r0, [r7, #4] + 800d272: 460b mov r3, r1 + 800d274: 70fb strb r3, [r7, #3] + 800d276: 4613 mov r3, r2 + 800d278: 803b strh r3, [r7, #0] + uint8_t* dst8= (uint8_t *) dst; + 800d27a: 687b ldr r3, [r7, #4] + 800d27c: 60fb str r3, [r7, #12] + while( size-- ) + 800d27e: e004 b.n 800d28a + { + *dst8++ = value; + 800d280: 68fb ldr r3, [r7, #12] + 800d282: 1c5a adds r2, r3, #1 + 800d284: 60fa str r2, [r7, #12] + 800d286: 78fa ldrb r2, [r7, #3] + 800d288: 701a strb r2, [r3, #0] + while( size-- ) + 800d28a: 883b ldrh r3, [r7, #0] + 800d28c: 1e5a subs r2, r3, #1 + 800d28e: 803a strh r2, [r7, #0] + 800d290: 2b00 cmp r3, #0 + 800d292: d1f5 bne.n 800d280 + } +} + 800d294: bf00 nop + 800d296: bf00 nop + 800d298: 3714 adds r7, #20 + 800d29a: 46bd mov sp, r7 + 800d29c: bc80 pop {r7} + 800d29e: 4770 bx lr + +0800d2a0 : + * @addtogroup SYSTIME_exported_function + * @{ + */ + +SysTime_t SysTimeAdd( SysTime_t a, SysTime_t b ) +{ + 800d2a0: b082 sub sp, #8 + 800d2a2: b480 push {r7} + 800d2a4: b087 sub sp, #28 + 800d2a6: af00 add r7, sp, #0 + 800d2a8: 60f8 str r0, [r7, #12] + 800d2aa: 1d38 adds r0, r7, #4 + 800d2ac: e880 0006 stmia.w r0, {r1, r2} + 800d2b0: 627b str r3, [r7, #36] @ 0x24 + SysTime_t c = { .Seconds = 0, .SubSeconds = 0 }; + 800d2b2: 2300 movs r3, #0 + 800d2b4: 613b str r3, [r7, #16] + 800d2b6: 2300 movs r3, #0 + 800d2b8: 82bb strh r3, [r7, #20] + + c.Seconds = a.Seconds + b.Seconds; + 800d2ba: 687a ldr r2, [r7, #4] + 800d2bc: 6a7b ldr r3, [r7, #36] @ 0x24 + 800d2be: 4413 add r3, r2 + 800d2c0: 613b str r3, [r7, #16] + c.SubSeconds = a.SubSeconds + b.SubSeconds; + 800d2c2: f9b7 3008 ldrsh.w r3, [r7, #8] + 800d2c6: b29a uxth r2, r3 + 800d2c8: f9b7 3028 ldrsh.w r3, [r7, #40] @ 0x28 + 800d2cc: b29b uxth r3, r3 + 800d2ce: 4413 add r3, r2 + 800d2d0: b29b uxth r3, r3 + 800d2d2: b21b sxth r3, r3 + 800d2d4: 82bb strh r3, [r7, #20] + if( c.SubSeconds >= 1000 ) + 800d2d6: f9b7 3014 ldrsh.w r3, [r7, #20] + 800d2da: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 + 800d2de: db0a blt.n 800d2f6 + { + c.Seconds++; + 800d2e0: 693b ldr r3, [r7, #16] + 800d2e2: 3301 adds r3, #1 + 800d2e4: 613b str r3, [r7, #16] + c.SubSeconds -= 1000; + 800d2e6: f9b7 3014 ldrsh.w r3, [r7, #20] + 800d2ea: b29b uxth r3, r3 + 800d2ec: f5a3 737a sub.w r3, r3, #1000 @ 0x3e8 + 800d2f0: b29b uxth r3, r3 + 800d2f2: b21b sxth r3, r3 + 800d2f4: 82bb strh r3, [r7, #20] + } + return c; + 800d2f6: 68fb ldr r3, [r7, #12] + 800d2f8: 461a mov r2, r3 + 800d2fa: f107 0310 add.w r3, r7, #16 + 800d2fe: e893 0003 ldmia.w r3, {r0, r1} + 800d302: e882 0003 stmia.w r2, {r0, r1} +} + 800d306: 68f8 ldr r0, [r7, #12] + 800d308: 371c adds r7, #28 + 800d30a: 46bd mov sp, r7 + 800d30c: bc80 pop {r7} + 800d30e: b002 add sp, #8 + 800d310: 4770 bx lr + ... + +0800d314 : + UTIL_SYSTIMDriver.BKUPWrite_Seconds( DeltaTime.Seconds ); + UTIL_SYSTIMDriver.BKUPWrite_SubSeconds( ( uint32_t ) DeltaTime.SubSeconds ); +} + +SysTime_t SysTimeGet( void ) +{ + 800d314: b580 push {r7, lr} + 800d316: b08a sub sp, #40 @ 0x28 + 800d318: af02 add r7, sp, #8 + 800d31a: 6078 str r0, [r7, #4] + SysTime_t calendarTime = { .Seconds = 0, .SubSeconds = 0 }; + 800d31c: 2300 movs r3, #0 + 800d31e: 61bb str r3, [r7, #24] + 800d320: 2300 movs r3, #0 + 800d322: 83bb strh r3, [r7, #28] + SysTime_t sysTime = { .Seconds = 0, .SubSeconds = 0 }; + 800d324: 2300 movs r3, #0 + 800d326: 613b str r3, [r7, #16] + 800d328: 2300 movs r3, #0 + 800d32a: 82bb strh r3, [r7, #20] + SysTime_t DeltaTime; + + calendarTime.Seconds = UTIL_SYSTIMDriver.GetCalendarTime( ( uint16_t* )&calendarTime.SubSeconds ); + 800d32c: 4b14 ldr r3, [pc, #80] @ (800d380 ) + 800d32e: 691b ldr r3, [r3, #16] + 800d330: f107 0218 add.w r2, r7, #24 + 800d334: 3204 adds r2, #4 + 800d336: 4610 mov r0, r2 + 800d338: 4798 blx r3 + 800d33a: 4603 mov r3, r0 + 800d33c: 61bb str r3, [r7, #24] + + DeltaTime.SubSeconds = (int16_t)UTIL_SYSTIMDriver.BKUPRead_SubSeconds(); + 800d33e: 4b10 ldr r3, [pc, #64] @ (800d380 ) + 800d340: 68db ldr r3, [r3, #12] + 800d342: 4798 blx r3 + 800d344: 4603 mov r3, r0 + 800d346: b21b sxth r3, r3 + 800d348: 81bb strh r3, [r7, #12] + DeltaTime.Seconds = UTIL_SYSTIMDriver.BKUPRead_Seconds(); + 800d34a: 4b0d ldr r3, [pc, #52] @ (800d380 ) + 800d34c: 685b ldr r3, [r3, #4] + 800d34e: 4798 blx r3 + 800d350: 4603 mov r3, r0 + 800d352: 60bb str r3, [r7, #8] + + sysTime = SysTimeAdd( DeltaTime, calendarTime ); + 800d354: f107 0010 add.w r0, r7, #16 + 800d358: 69fb ldr r3, [r7, #28] + 800d35a: 9300 str r3, [sp, #0] + 800d35c: 69bb ldr r3, [r7, #24] + 800d35e: f107 0208 add.w r2, r7, #8 + 800d362: ca06 ldmia r2, {r1, r2} + 800d364: f7ff ff9c bl 800d2a0 + + return sysTime; + 800d368: 687b ldr r3, [r7, #4] + 800d36a: 461a mov r2, r3 + 800d36c: f107 0310 add.w r3, r7, #16 + 800d370: e893 0003 ldmia.w r3, {r0, r1} + 800d374: e882 0003 stmia.w r2, {r0, r1} +} + 800d378: 6878 ldr r0, [r7, #4] + 800d37a: 3720 adds r7, #32 + 800d37c: 46bd mov sp, r7 + 800d37e: bd80 pop {r7, pc} + 800d380: 0800fb30 .word 0x0800fb30 + +0800d384 : + return sc - s; +} +#endif + +static int ee_skip_atoi(const char **s) +{ + 800d384: b480 push {r7} + 800d386: b085 sub sp, #20 + 800d388: af00 add r7, sp, #0 + 800d38a: 6078 str r0, [r7, #4] + int i = 0; + 800d38c: 2300 movs r3, #0 + 800d38e: 60fb str r3, [r7, #12] + while (is_digit(**s)) i = i*10 + *((*s)++) - '0'; + 800d390: e00e b.n 800d3b0 + 800d392: 68fa ldr r2, [r7, #12] + 800d394: 4613 mov r3, r2 + 800d396: 009b lsls r3, r3, #2 + 800d398: 4413 add r3, r2 + 800d39a: 005b lsls r3, r3, #1 + 800d39c: 4618 mov r0, r3 + 800d39e: 687b ldr r3, [r7, #4] + 800d3a0: 681b ldr r3, [r3, #0] + 800d3a2: 1c59 adds r1, r3, #1 + 800d3a4: 687a ldr r2, [r7, #4] + 800d3a6: 6011 str r1, [r2, #0] + 800d3a8: 781b ldrb r3, [r3, #0] + 800d3aa: 4403 add r3, r0 + 800d3ac: 3b30 subs r3, #48 @ 0x30 + 800d3ae: 60fb str r3, [r7, #12] + 800d3b0: 687b ldr r3, [r7, #4] + 800d3b2: 681b ldr r3, [r3, #0] + 800d3b4: 781b ldrb r3, [r3, #0] + 800d3b6: 2b2f cmp r3, #47 @ 0x2f + 800d3b8: d904 bls.n 800d3c4 + 800d3ba: 687b ldr r3, [r7, #4] + 800d3bc: 681b ldr r3, [r3, #0] + 800d3be: 781b ldrb r3, [r3, #0] + 800d3c0: 2b39 cmp r3, #57 @ 0x39 + 800d3c2: d9e6 bls.n 800d392 + return i; + 800d3c4: 68fb ldr r3, [r7, #12] +} + 800d3c6: 4618 mov r0, r3 + 800d3c8: 3714 adds r7, #20 + 800d3ca: 46bd mov sp, r7 + 800d3cc: bc80 pop {r7} + 800d3ce: 4770 bx lr + +0800d3d0 : + +#define ASSIGN_STR(_c) do { *str++ = (_c); max_size--; if (max_size == 0) return str; } while (0) + +static char *ee_number(char *str, int max_size, long num, int base, int size, int precision, int type) +{ + 800d3d0: b480 push {r7} + 800d3d2: b099 sub sp, #100 @ 0x64 + 800d3d4: af00 add r7, sp, #0 + 800d3d6: 60f8 str r0, [r7, #12] + 800d3d8: 60b9 str r1, [r7, #8] + 800d3da: 607a str r2, [r7, #4] + 800d3dc: 603b str r3, [r7, #0] + char c; + char sign, tmp[66]; + char *dig = lower_digits; + 800d3de: 4b71 ldr r3, [pc, #452] @ (800d5a4 ) + 800d3e0: 681b ldr r3, [r3, #0] + 800d3e2: 65bb str r3, [r7, #88] @ 0x58 + int i; + + if (type & UPPERCASE) dig = upper_digits; + 800d3e4: 6f3b ldr r3, [r7, #112] @ 0x70 + 800d3e6: f003 0340 and.w r3, r3, #64 @ 0x40 + 800d3ea: 2b00 cmp r3, #0 + 800d3ec: d002 beq.n 800d3f4 + 800d3ee: 4b6e ldr r3, [pc, #440] @ (800d5a8 ) + 800d3f0: 681b ldr r3, [r3, #0] + 800d3f2: 65bb str r3, [r7, #88] @ 0x58 +#ifdef TINY_PRINTF +#else + if (type & LEFT) type &= ~ZEROPAD; +#endif + if (base < 2 || base > 36) return 0; + 800d3f4: 683b ldr r3, [r7, #0] + 800d3f6: 2b01 cmp r3, #1 + 800d3f8: dd02 ble.n 800d400 + 800d3fa: 683b ldr r3, [r7, #0] + 800d3fc: 2b24 cmp r3, #36 @ 0x24 + 800d3fe: dd01 ble.n 800d404 + 800d400: 2300 movs r3, #0 + 800d402: e0ca b.n 800d59a + + c = (type & ZEROPAD) ? '0' : ' '; + 800d404: 6f3b ldr r3, [r7, #112] @ 0x70 + 800d406: f003 0301 and.w r3, r3, #1 + 800d40a: 2b00 cmp r3, #0 + 800d40c: d001 beq.n 800d412 + 800d40e: 2330 movs r3, #48 @ 0x30 + 800d410: e000 b.n 800d414 + 800d412: 2320 movs r3, #32 + 800d414: f887 3053 strb.w r3, [r7, #83] @ 0x53 + sign = 0; + 800d418: 2300 movs r3, #0 + 800d41a: f887 305f strb.w r3, [r7, #95] @ 0x5f + if (type & SIGN) + 800d41e: 6f3b ldr r3, [r7, #112] @ 0x70 + 800d420: f003 0302 and.w r3, r3, #2 + 800d424: 2b00 cmp r3, #0 + 800d426: d00b beq.n 800d440 + { + if (num < 0) + 800d428: 687b ldr r3, [r7, #4] + 800d42a: 2b00 cmp r3, #0 + 800d42c: da08 bge.n 800d440 + { + sign = '-'; + 800d42e: 232d movs r3, #45 @ 0x2d + 800d430: f887 305f strb.w r3, [r7, #95] @ 0x5f + num = -num; + 800d434: 687b ldr r3, [r7, #4] + 800d436: 425b negs r3, r3 + 800d438: 607b str r3, [r7, #4] + size--; + 800d43a: 6ebb ldr r3, [r7, #104] @ 0x68 + 800d43c: 3b01 subs r3, #1 + 800d43e: 66bb str r3, [r7, #104] @ 0x68 + else if (base == 8) + size--; + } +#endif + + i = 0; + 800d440: 2300 movs r3, #0 + 800d442: 657b str r3, [r7, #84] @ 0x54 + + if (num == 0) + 800d444: 687b ldr r3, [r7, #4] + 800d446: 2b00 cmp r3, #0 + 800d448: d11e bne.n 800d488 + tmp[i++] = '0'; + 800d44a: 6d7b ldr r3, [r7, #84] @ 0x54 + 800d44c: 1c5a adds r2, r3, #1 + 800d44e: 657a str r2, [r7, #84] @ 0x54 + 800d450: 3360 adds r3, #96 @ 0x60 + 800d452: 443b add r3, r7 + 800d454: 2230 movs r2, #48 @ 0x30 + 800d456: f803 2c50 strb.w r2, [r3, #-80] + 800d45a: e018 b.n 800d48e + else + { + while (num != 0) + { + tmp[i++] = dig[((unsigned long) num) % (unsigned) base]; + 800d45c: 687b ldr r3, [r7, #4] + 800d45e: 683a ldr r2, [r7, #0] + 800d460: fbb3 f1f2 udiv r1, r3, r2 + 800d464: fb01 f202 mul.w r2, r1, r2 + 800d468: 1a9b subs r3, r3, r2 + 800d46a: 6dba ldr r2, [r7, #88] @ 0x58 + 800d46c: 441a add r2, r3 + 800d46e: 6d7b ldr r3, [r7, #84] @ 0x54 + 800d470: 1c59 adds r1, r3, #1 + 800d472: 6579 str r1, [r7, #84] @ 0x54 + 800d474: 7812 ldrb r2, [r2, #0] + 800d476: 3360 adds r3, #96 @ 0x60 + 800d478: 443b add r3, r7 + 800d47a: f803 2c50 strb.w r2, [r3, #-80] + num = ((unsigned long) num) / (unsigned) base; + 800d47e: 687a ldr r2, [r7, #4] + 800d480: 683b ldr r3, [r7, #0] + 800d482: fbb2 f3f3 udiv r3, r2, r3 + 800d486: 607b str r3, [r7, #4] + while (num != 0) + 800d488: 687b ldr r3, [r7, #4] + 800d48a: 2b00 cmp r3, #0 + 800d48c: d1e6 bne.n 800d45c + } + } + + if (i > precision) precision = i; + 800d48e: 6d7a ldr r2, [r7, #84] @ 0x54 + 800d490: 6efb ldr r3, [r7, #108] @ 0x6c + 800d492: 429a cmp r2, r3 + 800d494: dd01 ble.n 800d49a + 800d496: 6d7b ldr r3, [r7, #84] @ 0x54 + 800d498: 66fb str r3, [r7, #108] @ 0x6c + size -= precision; + 800d49a: 6eba ldr r2, [r7, #104] @ 0x68 + 800d49c: 6efb ldr r3, [r7, #108] @ 0x6c + 800d49e: 1ad3 subs r3, r2, r3 + 800d4a0: 66bb str r3, [r7, #104] @ 0x68 + if (!(type & (ZEROPAD /* TINY option | LEFT */))) while (size-- > 0) ASSIGN_STR(' '); + 800d4a2: 6f3b ldr r3, [r7, #112] @ 0x70 + 800d4a4: f003 0301 and.w r3, r3, #1 + 800d4a8: 2b00 cmp r3, #0 + 800d4aa: d112 bne.n 800d4d2 + 800d4ac: e00c b.n 800d4c8 + 800d4ae: 68fb ldr r3, [r7, #12] + 800d4b0: 1c5a adds r2, r3, #1 + 800d4b2: 60fa str r2, [r7, #12] + 800d4b4: 2220 movs r2, #32 + 800d4b6: 701a strb r2, [r3, #0] + 800d4b8: 68bb ldr r3, [r7, #8] + 800d4ba: 3b01 subs r3, #1 + 800d4bc: 60bb str r3, [r7, #8] + 800d4be: 68bb ldr r3, [r7, #8] + 800d4c0: 2b00 cmp r3, #0 + 800d4c2: d101 bne.n 800d4c8 + 800d4c4: 68fb ldr r3, [r7, #12] + 800d4c6: e068 b.n 800d59a + 800d4c8: 6ebb ldr r3, [r7, #104] @ 0x68 + 800d4ca: 1e5a subs r2, r3, #1 + 800d4cc: 66ba str r2, [r7, #104] @ 0x68 + 800d4ce: 2b00 cmp r3, #0 + 800d4d0: dced bgt.n 800d4ae + if (sign) ASSIGN_STR(sign); + 800d4d2: f897 305f ldrb.w r3, [r7, #95] @ 0x5f + 800d4d6: 2b00 cmp r3, #0 + 800d4d8: d01b beq.n 800d512 + 800d4da: 68fb ldr r3, [r7, #12] + 800d4dc: 1c5a adds r2, r3, #1 + 800d4de: 60fa str r2, [r7, #12] + 800d4e0: f897 205f ldrb.w r2, [r7, #95] @ 0x5f + 800d4e4: 701a strb r2, [r3, #0] + 800d4e6: 68bb ldr r3, [r7, #8] + 800d4e8: 3b01 subs r3, #1 + 800d4ea: 60bb str r3, [r7, #8] + 800d4ec: 68bb ldr r3, [r7, #8] + 800d4ee: 2b00 cmp r3, #0 + 800d4f0: d10f bne.n 800d512 + 800d4f2: 68fb ldr r3, [r7, #12] + 800d4f4: e051 b.n 800d59a + } + } +#endif + +#ifdef TINY_PRINTF + while (size-- > 0) ASSIGN_STR(c); + 800d4f6: 68fb ldr r3, [r7, #12] + 800d4f8: 1c5a adds r2, r3, #1 + 800d4fa: 60fa str r2, [r7, #12] + 800d4fc: f897 2053 ldrb.w r2, [r7, #83] @ 0x53 + 800d500: 701a strb r2, [r3, #0] + 800d502: 68bb ldr r3, [r7, #8] + 800d504: 3b01 subs r3, #1 + 800d506: 60bb str r3, [r7, #8] + 800d508: 68bb ldr r3, [r7, #8] + 800d50a: 2b00 cmp r3, #0 + 800d50c: d101 bne.n 800d512 + 800d50e: 68fb ldr r3, [r7, #12] + 800d510: e043 b.n 800d59a + 800d512: 6ebb ldr r3, [r7, #104] @ 0x68 + 800d514: 1e5a subs r2, r3, #1 + 800d516: 66ba str r2, [r7, #104] @ 0x68 + 800d518: 2b00 cmp r3, #0 + 800d51a: dcec bgt.n 800d4f6 +#else + if (!(type & LEFT)) while (size-- > 0) ASSIGN_STR(c); +#endif + while (i < precision--) ASSIGN_STR('0'); + 800d51c: e00c b.n 800d538 + 800d51e: 68fb ldr r3, [r7, #12] + 800d520: 1c5a adds r2, r3, #1 + 800d522: 60fa str r2, [r7, #12] + 800d524: 2230 movs r2, #48 @ 0x30 + 800d526: 701a strb r2, [r3, #0] + 800d528: 68bb ldr r3, [r7, #8] + 800d52a: 3b01 subs r3, #1 + 800d52c: 60bb str r3, [r7, #8] + 800d52e: 68bb ldr r3, [r7, #8] + 800d530: 2b00 cmp r3, #0 + 800d532: d101 bne.n 800d538 + 800d534: 68fb ldr r3, [r7, #12] + 800d536: e030 b.n 800d59a + 800d538: 6efb ldr r3, [r7, #108] @ 0x6c + 800d53a: 1e5a subs r2, r3, #1 + 800d53c: 66fa str r2, [r7, #108] @ 0x6c + 800d53e: 6d7a ldr r2, [r7, #84] @ 0x54 + 800d540: 429a cmp r2, r3 + 800d542: dbec blt.n 800d51e + while (i-- > 0) ASSIGN_STR(tmp[i]); + 800d544: e010 b.n 800d568 + 800d546: 68fb ldr r3, [r7, #12] + 800d548: 1c5a adds r2, r3, #1 + 800d54a: 60fa str r2, [r7, #12] + 800d54c: f107 0110 add.w r1, r7, #16 + 800d550: 6d7a ldr r2, [r7, #84] @ 0x54 + 800d552: 440a add r2, r1 + 800d554: 7812 ldrb r2, [r2, #0] + 800d556: 701a strb r2, [r3, #0] + 800d558: 68bb ldr r3, [r7, #8] + 800d55a: 3b01 subs r3, #1 + 800d55c: 60bb str r3, [r7, #8] + 800d55e: 68bb ldr r3, [r7, #8] + 800d560: 2b00 cmp r3, #0 + 800d562: d101 bne.n 800d568 + 800d564: 68fb ldr r3, [r7, #12] + 800d566: e018 b.n 800d59a + 800d568: 6d7b ldr r3, [r7, #84] @ 0x54 + 800d56a: 1e5a subs r2, r3, #1 + 800d56c: 657a str r2, [r7, #84] @ 0x54 + 800d56e: 2b00 cmp r3, #0 + 800d570: dce9 bgt.n 800d546 + while (size-- > 0) ASSIGN_STR(' '); + 800d572: e00c b.n 800d58e + 800d574: 68fb ldr r3, [r7, #12] + 800d576: 1c5a adds r2, r3, #1 + 800d578: 60fa str r2, [r7, #12] + 800d57a: 2220 movs r2, #32 + 800d57c: 701a strb r2, [r3, #0] + 800d57e: 68bb ldr r3, [r7, #8] + 800d580: 3b01 subs r3, #1 + 800d582: 60bb str r3, [r7, #8] + 800d584: 68bb ldr r3, [r7, #8] + 800d586: 2b00 cmp r3, #0 + 800d588: d101 bne.n 800d58e + 800d58a: 68fb ldr r3, [r7, #12] + 800d58c: e005 b.n 800d59a + 800d58e: 6ebb ldr r3, [r7, #104] @ 0x68 + 800d590: 1e5a subs r2, r3, #1 + 800d592: 66ba str r2, [r7, #104] @ 0x68 + 800d594: 2b00 cmp r3, #0 + 800d596: dced bgt.n 800d574 + + return str; + 800d598: 68fb ldr r3, [r7, #12] +} + 800d59a: 4618 mov r0, r3 + 800d59c: 3764 adds r7, #100 @ 0x64 + 800d59e: 46bd mov sp, r7 + 800d5a0: bc80 pop {r7} + 800d5a2: 4770 bx lr + 800d5a4: 2000002c .word 0x2000002c + 800d5a8: 20000030 .word 0x20000030 + +0800d5ac : + +#define CHECK_STR_SIZE(_buf, _str, _size) \ + if ((((_str) - (_buf)) >= ((_size)-1))) { break; } + +int tiny_vsnprintf_like(char *buf, const int size, const char *fmt, va_list args) +{ + 800d5ac: b580 push {r7, lr} + 800d5ae: b092 sub sp, #72 @ 0x48 + 800d5b0: af04 add r7, sp, #16 + 800d5b2: 60f8 str r0, [r7, #12] + 800d5b4: 60b9 str r1, [r7, #8] + 800d5b6: 607a str r2, [r7, #4] + 800d5b8: 603b str r3, [r7, #0] + + int field_width; // Width of output field + int precision; // Min. # of digits for integers; max number of chars for from string + int qualifier; // 'h', 'l', or 'L' for integer fields + + if (size <= 0) + 800d5ba: 68bb ldr r3, [r7, #8] + 800d5bc: 2b00 cmp r3, #0 + 800d5be: dc01 bgt.n 800d5c4 + { + return 0; + 800d5c0: 2300 movs r3, #0 + 800d5c2: e13e b.n 800d842 + } + + for (str = buf; *fmt || ((str - buf) >= size-1); fmt++) + 800d5c4: 68fb ldr r3, [r7, #12] + 800d5c6: 62fb str r3, [r7, #44] @ 0x2c + 800d5c8: e128 b.n 800d81c + { + CHECK_STR_SIZE(buf, str, size); + 800d5ca: 6afa ldr r2, [r7, #44] @ 0x2c + 800d5cc: 68fb ldr r3, [r7, #12] + 800d5ce: 1ad2 subs r2, r2, r3 + 800d5d0: 68bb ldr r3, [r7, #8] + 800d5d2: 3b01 subs r3, #1 + 800d5d4: 429a cmp r2, r3 + 800d5d6: f280 812e bge.w 800d836 + + if (*fmt != '%') + 800d5da: 687b ldr r3, [r7, #4] + 800d5dc: 781b ldrb r3, [r3, #0] + 800d5de: 2b25 cmp r3, #37 @ 0x25 + 800d5e0: d006 beq.n 800d5f0 + { + *str++ = *fmt; + 800d5e2: 687a ldr r2, [r7, #4] + 800d5e4: 6afb ldr r3, [r7, #44] @ 0x2c + 800d5e6: 1c59 adds r1, r3, #1 + 800d5e8: 62f9 str r1, [r7, #44] @ 0x2c + 800d5ea: 7812 ldrb r2, [r2, #0] + 800d5ec: 701a strb r2, [r3, #0] + continue; + 800d5ee: e112 b.n 800d816 + } + + // Process flags + flags = 0; + 800d5f0: 2300 movs r3, #0 + 800d5f2: 623b str r3, [r7, #32] +#ifdef TINY_PRINTF + /* Support %0, but not %-, %+, %space and %# */ + fmt++; + 800d5f4: 687b ldr r3, [r7, #4] + 800d5f6: 3301 adds r3, #1 + 800d5f8: 607b str r3, [r7, #4] + if (*fmt == '0') + 800d5fa: 687b ldr r3, [r7, #4] + 800d5fc: 781b ldrb r3, [r3, #0] + 800d5fe: 2b30 cmp r3, #48 @ 0x30 + 800d600: d103 bne.n 800d60a + { + flags |= ZEROPAD; + 800d602: 6a3b ldr r3, [r7, #32] + 800d604: f043 0301 orr.w r3, r3, #1 + 800d608: 623b str r3, [r7, #32] + case '0': flags |= ZEROPAD; goto repeat; + } +#endif + + // Get field width + field_width = -1; + 800d60a: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff + 800d60e: 61fb str r3, [r7, #28] + if (is_digit(*fmt)) + 800d610: 687b ldr r3, [r7, #4] + 800d612: 781b ldrb r3, [r3, #0] + 800d614: 2b2f cmp r3, #47 @ 0x2f + 800d616: d908 bls.n 800d62a + 800d618: 687b ldr r3, [r7, #4] + 800d61a: 781b ldrb r3, [r3, #0] + 800d61c: 2b39 cmp r3, #57 @ 0x39 + 800d61e: d804 bhi.n 800d62a + field_width = ee_skip_atoi(&fmt); + 800d620: 1d3b adds r3, r7, #4 + 800d622: 4618 mov r0, r3 + 800d624: f7ff feae bl 800d384 + 800d628: 61f8 str r0, [r7, #28] + } + } +#endif + + // Get the precision + precision = -1; + 800d62a: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff + 800d62e: 61bb str r3, [r7, #24] + if (precision < 0) precision = 0; + } +#endif + + // Get the conversion qualifier + qualifier = -1; + 800d630: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff + 800d634: 617b str r3, [r7, #20] + fmt++; + } +#endif + + // Default base + base = 10; + 800d636: 230a movs r3, #10 + 800d638: 633b str r3, [r7, #48] @ 0x30 + + switch (*fmt) + 800d63a: 687b ldr r3, [r7, #4] + 800d63c: 781b ldrb r3, [r3, #0] + 800d63e: 3b58 subs r3, #88 @ 0x58 + 800d640: 2b20 cmp r3, #32 + 800d642: f200 8094 bhi.w 800d76e + 800d646: a201 add r2, pc, #4 @ (adr r2, 800d64c ) + 800d648: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 800d64c: 0800d757 .word 0x0800d757 + 800d650: 0800d76f .word 0x0800d76f + 800d654: 0800d76f .word 0x0800d76f + 800d658: 0800d76f .word 0x0800d76f + 800d65c: 0800d76f .word 0x0800d76f + 800d660: 0800d76f .word 0x0800d76f + 800d664: 0800d76f .word 0x0800d76f + 800d668: 0800d76f .word 0x0800d76f + 800d66c: 0800d76f .word 0x0800d76f + 800d670: 0800d76f .word 0x0800d76f + 800d674: 0800d76f .word 0x0800d76f + 800d678: 0800d6db .word 0x0800d6db + 800d67c: 0800d765 .word 0x0800d765 + 800d680: 0800d76f .word 0x0800d76f + 800d684: 0800d76f .word 0x0800d76f + 800d688: 0800d76f .word 0x0800d76f + 800d68c: 0800d76f .word 0x0800d76f + 800d690: 0800d765 .word 0x0800d765 + 800d694: 0800d76f .word 0x0800d76f + 800d698: 0800d76f .word 0x0800d76f + 800d69c: 0800d76f .word 0x0800d76f + 800d6a0: 0800d76f .word 0x0800d76f + 800d6a4: 0800d76f .word 0x0800d76f + 800d6a8: 0800d76f .word 0x0800d76f + 800d6ac: 0800d76f .word 0x0800d76f + 800d6b0: 0800d76f .word 0x0800d76f + 800d6b4: 0800d76f .word 0x0800d76f + 800d6b8: 0800d6fb .word 0x0800d6fb + 800d6bc: 0800d76f .word 0x0800d76f + 800d6c0: 0800d7bb .word 0x0800d7bb + 800d6c4: 0800d76f .word 0x0800d76f + 800d6c8: 0800d76f .word 0x0800d76f + 800d6cc: 0800d75f .word 0x0800d75f + case 'c': +#ifdef TINY_PRINTF +#else + if (!(flags & LEFT)) +#endif + while (--field_width > 0) *str++ = ' '; + 800d6d0: 6afb ldr r3, [r7, #44] @ 0x2c + 800d6d2: 1c5a adds r2, r3, #1 + 800d6d4: 62fa str r2, [r7, #44] @ 0x2c + 800d6d6: 2220 movs r2, #32 + 800d6d8: 701a strb r2, [r3, #0] + 800d6da: 69fb ldr r3, [r7, #28] + 800d6dc: 3b01 subs r3, #1 + 800d6de: 61fb str r3, [r7, #28] + 800d6e0: 69fb ldr r3, [r7, #28] + 800d6e2: 2b00 cmp r3, #0 + 800d6e4: dcf4 bgt.n 800d6d0 + *str++ = (unsigned char) va_arg(args, int); + 800d6e6: 683b ldr r3, [r7, #0] + 800d6e8: 1d1a adds r2, r3, #4 + 800d6ea: 603a str r2, [r7, #0] + 800d6ec: 6819 ldr r1, [r3, #0] + 800d6ee: 6afb ldr r3, [r7, #44] @ 0x2c + 800d6f0: 1c5a adds r2, r3, #1 + 800d6f2: 62fa str r2, [r7, #44] @ 0x2c + 800d6f4: b2ca uxtb r2, r1 + 800d6f6: 701a strb r2, [r3, #0] +#ifdef TINY_PRINTF +#else + while (--field_width > 0) *str++ = ' '; +#endif + continue; + 800d6f8: e08d b.n 800d816 + + case 's': + s = va_arg(args, char *); + 800d6fa: 683b ldr r3, [r7, #0] + 800d6fc: 1d1a adds r2, r3, #4 + 800d6fe: 603a str r2, [r7, #0] + 800d700: 681b ldr r3, [r3, #0] + 800d702: 627b str r3, [r7, #36] @ 0x24 + if (!s) s = ""; + 800d704: 6a7b ldr r3, [r7, #36] @ 0x24 + 800d706: 2b00 cmp r3, #0 + 800d708: d101 bne.n 800d70e + 800d70a: 4b50 ldr r3, [pc, #320] @ (800d84c ) + 800d70c: 627b str r3, [r7, #36] @ 0x24 +#ifdef TINY_PRINTF + len = strlen(s); + 800d70e: 6a78 ldr r0, [r7, #36] @ 0x24 + 800d710: f7f2 fd40 bl 8000194 + 800d714: 4603 mov r3, r0 + 800d716: 613b str r3, [r7, #16] +#else + len = strnlen(s, precision); + if (!(flags & LEFT)) +#endif + while (len < field_width--) *str++ = ' '; + 800d718: e004 b.n 800d724 + 800d71a: 6afb ldr r3, [r7, #44] @ 0x2c + 800d71c: 1c5a adds r2, r3, #1 + 800d71e: 62fa str r2, [r7, #44] @ 0x2c + 800d720: 2220 movs r2, #32 + 800d722: 701a strb r2, [r3, #0] + 800d724: 69fb ldr r3, [r7, #28] + 800d726: 1e5a subs r2, r3, #1 + 800d728: 61fa str r2, [r7, #28] + 800d72a: 693a ldr r2, [r7, #16] + 800d72c: 429a cmp r2, r3 + 800d72e: dbf4 blt.n 800d71a + for (i = 0; i < len; ++i) *str++ = *s++; + 800d730: 2300 movs r3, #0 + 800d732: 62bb str r3, [r7, #40] @ 0x28 + 800d734: e00a b.n 800d74c + 800d736: 6a7a ldr r2, [r7, #36] @ 0x24 + 800d738: 1c53 adds r3, r2, #1 + 800d73a: 627b str r3, [r7, #36] @ 0x24 + 800d73c: 6afb ldr r3, [r7, #44] @ 0x2c + 800d73e: 1c59 adds r1, r3, #1 + 800d740: 62f9 str r1, [r7, #44] @ 0x2c + 800d742: 7812 ldrb r2, [r2, #0] + 800d744: 701a strb r2, [r3, #0] + 800d746: 6abb ldr r3, [r7, #40] @ 0x28 + 800d748: 3301 adds r3, #1 + 800d74a: 62bb str r3, [r7, #40] @ 0x28 + 800d74c: 6aba ldr r2, [r7, #40] @ 0x28 + 800d74e: 693b ldr r3, [r7, #16] + 800d750: 429a cmp r2, r3 + 800d752: dbf0 blt.n 800d736 +#ifdef TINY_PRINTF +#else + while (len < field_width--) *str++ = ' '; +#endif + continue; + 800d754: e05f b.n 800d816 + base = 8; + break; +#endif + + case 'X': + flags |= UPPERCASE; + 800d756: 6a3b ldr r3, [r7, #32] + 800d758: f043 0340 orr.w r3, r3, #64 @ 0x40 + 800d75c: 623b str r3, [r7, #32] + + case 'x': + base = 16; + 800d75e: 2310 movs r3, #16 + 800d760: 633b str r3, [r7, #48] @ 0x30 + break; + 800d762: e02b b.n 800d7bc + + case 'd': + case 'i': + flags |= SIGN; + 800d764: 6a3b ldr r3, [r7, #32] + 800d766: f043 0302 orr.w r3, r3, #2 + 800d76a: 623b str r3, [r7, #32] + + case 'u': + break; + 800d76c: e025 b.n 800d7ba + continue; + +#endif + + default: + if (*fmt != '%') *str++ = '%'; + 800d76e: 687b ldr r3, [r7, #4] + 800d770: 781b ldrb r3, [r3, #0] + 800d772: 2b25 cmp r3, #37 @ 0x25 + 800d774: d004 beq.n 800d780 + 800d776: 6afb ldr r3, [r7, #44] @ 0x2c + 800d778: 1c5a adds r2, r3, #1 + 800d77a: 62fa str r2, [r7, #44] @ 0x2c + 800d77c: 2225 movs r2, #37 @ 0x25 + 800d77e: 701a strb r2, [r3, #0] + CHECK_STR_SIZE(buf, str, size); + 800d780: 6afa ldr r2, [r7, #44] @ 0x2c + 800d782: 68fb ldr r3, [r7, #12] + 800d784: 1ad2 subs r2, r2, r3 + 800d786: 68bb ldr r3, [r7, #8] + 800d788: 3b01 subs r3, #1 + 800d78a: 429a cmp r2, r3 + 800d78c: da16 bge.n 800d7bc + if (*fmt) + 800d78e: 687b ldr r3, [r7, #4] + 800d790: 781b ldrb r3, [r3, #0] + 800d792: 2b00 cmp r3, #0 + 800d794: d006 beq.n 800d7a4 + *str++ = *fmt; + 800d796: 687a ldr r2, [r7, #4] + 800d798: 6afb ldr r3, [r7, #44] @ 0x2c + 800d79a: 1c59 adds r1, r3, #1 + 800d79c: 62f9 str r1, [r7, #44] @ 0x2c + 800d79e: 7812 ldrb r2, [r2, #0] + 800d7a0: 701a strb r2, [r3, #0] + 800d7a2: e002 b.n 800d7aa + else + --fmt; + 800d7a4: 687b ldr r3, [r7, #4] + 800d7a6: 3b01 subs r3, #1 + 800d7a8: 607b str r3, [r7, #4] + CHECK_STR_SIZE(buf, str, size); + 800d7aa: 6afa ldr r2, [r7, #44] @ 0x2c + 800d7ac: 68fb ldr r3, [r7, #12] + 800d7ae: 1ad2 subs r2, r2, r3 + 800d7b0: 68bb ldr r3, [r7, #8] + 800d7b2: 3b01 subs r3, #1 + 800d7b4: 429a cmp r2, r3 + 800d7b6: db2d blt.n 800d814 + 800d7b8: e000 b.n 800d7bc + break; + 800d7ba: bf00 nop + continue; + } + + if (qualifier == 'l') + 800d7bc: 697b ldr r3, [r7, #20] + 800d7be: 2b6c cmp r3, #108 @ 0x6c + 800d7c0: d105 bne.n 800d7ce + num = va_arg(args, unsigned long); + 800d7c2: 683b ldr r3, [r7, #0] + 800d7c4: 1d1a adds r2, r3, #4 + 800d7c6: 603a str r2, [r7, #0] + 800d7c8: 681b ldr r3, [r3, #0] + 800d7ca: 637b str r3, [r7, #52] @ 0x34 + 800d7cc: e00f b.n 800d7ee + else if (flags & SIGN) + 800d7ce: 6a3b ldr r3, [r7, #32] + 800d7d0: f003 0302 and.w r3, r3, #2 + 800d7d4: 2b00 cmp r3, #0 + 800d7d6: d005 beq.n 800d7e4 + num = va_arg(args, int); + 800d7d8: 683b ldr r3, [r7, #0] + 800d7da: 1d1a adds r2, r3, #4 + 800d7dc: 603a str r2, [r7, #0] + 800d7de: 681b ldr r3, [r3, #0] + 800d7e0: 637b str r3, [r7, #52] @ 0x34 + 800d7e2: e004 b.n 800d7ee + else + num = va_arg(args, unsigned int); + 800d7e4: 683b ldr r3, [r7, #0] + 800d7e6: 1d1a adds r2, r3, #4 + 800d7e8: 603a str r2, [r7, #0] + 800d7ea: 681b ldr r3, [r3, #0] + 800d7ec: 637b str r3, [r7, #52] @ 0x34 + + str = ee_number(str, ((size - 1) - (str - buf)), num, base, field_width, precision, flags); + 800d7ee: 68bb ldr r3, [r7, #8] + 800d7f0: 1e5a subs r2, r3, #1 + 800d7f2: 6af9 ldr r1, [r7, #44] @ 0x2c + 800d7f4: 68fb ldr r3, [r7, #12] + 800d7f6: 1acb subs r3, r1, r3 + 800d7f8: 1ad1 subs r1, r2, r3 + 800d7fa: 6b7a ldr r2, [r7, #52] @ 0x34 + 800d7fc: 6a3b ldr r3, [r7, #32] + 800d7fe: 9302 str r3, [sp, #8] + 800d800: 69bb ldr r3, [r7, #24] + 800d802: 9301 str r3, [sp, #4] + 800d804: 69fb ldr r3, [r7, #28] + 800d806: 9300 str r3, [sp, #0] + 800d808: 6b3b ldr r3, [r7, #48] @ 0x30 + 800d80a: 6af8 ldr r0, [r7, #44] @ 0x2c + 800d80c: f7ff fde0 bl 800d3d0 + 800d810: 62f8 str r0, [r7, #44] @ 0x2c + 800d812: e000 b.n 800d816 + continue; + 800d814: bf00 nop + for (str = buf; *fmt || ((str - buf) >= size-1); fmt++) + 800d816: 687b ldr r3, [r7, #4] + 800d818: 3301 adds r3, #1 + 800d81a: 607b str r3, [r7, #4] + 800d81c: 687b ldr r3, [r7, #4] + 800d81e: 781b ldrb r3, [r3, #0] + 800d820: 2b00 cmp r3, #0 + 800d822: f47f aed2 bne.w 800d5ca + 800d826: 6afa ldr r2, [r7, #44] @ 0x2c + 800d828: 68fb ldr r3, [r7, #12] + 800d82a: 1ad2 subs r2, r2, r3 + 800d82c: 68bb ldr r3, [r7, #8] + 800d82e: 3b01 subs r3, #1 + 800d830: 429a cmp r2, r3 + 800d832: f6bf aeca bge.w 800d5ca + } + + *str = '\0'; + 800d836: 6afb ldr r3, [r7, #44] @ 0x2c + 800d838: 2200 movs r2, #0 + 800d83a: 701a strb r2, [r3, #0] + return str - buf; + 800d83c: 6afa ldr r2, [r7, #44] @ 0x2c + 800d83e: 68fb ldr r3, [r7, #12] + 800d840: 1ad3 subs r3, r2, r3 +} + 800d842: 4618 mov r0, r3 + 800d844: 3738 adds r7, #56 @ 0x38 + 800d846: 46bd mov sp, r7 + 800d848: bd80 pop {r7, pc} + 800d84a: bf00 nop + 800d84c: 0800fa44 .word 0x0800fa44 + +0800d850 : + * That is the reason why many variables that are used only in that function are declared static. + * Note: These variables could have been declared static in the function. + * + */ +void UTIL_SEQ_Run( UTIL_SEQ_bm_t Mask_bm ) +{ + 800d850: b580 push {r7, lr} + 800d852: b090 sub sp, #64 @ 0x40 + 800d854: af00 add r7, sp, #0 + 800d856: 6078 str r0, [r7, #4] + /* + * When this function is nested, the mask to be applied cannot be larger than the first call + * The mask is always getting smaller and smaller + * A copy is made of the mask set by UTIL_SEQ_Run() in case it is called again in the task + */ + super_mask_backup = SuperMask; + 800d858: 4b73 ldr r3, [pc, #460] @ (800da28 ) + 800d85a: 681b ldr r3, [r3, #0] + 800d85c: 62bb str r3, [r7, #40] @ 0x28 + SuperMask &= Mask_bm; + 800d85e: 4b72 ldr r3, [pc, #456] @ (800da28 ) + 800d860: 681a ldr r2, [r3, #0] + 800d862: 687b ldr r3, [r7, #4] + 800d864: 4013 ands r3, r2 + 800d866: 4a70 ldr r2, [pc, #448] @ (800da28 ) + 800d868: 6013 str r3, [r2, #0] + * TaskMask that comes from UTIL_SEQ_PauseTask() / UTIL_SEQ_ResumeTask + * SuperMask that comes from UTIL_SEQ_Run + * If the waited event is there, exit from UTIL_SEQ_Run() to return to the + * waiting task + */ + local_taskset = TaskSet; + 800d86a: 4b70 ldr r3, [pc, #448] @ (800da2c ) + 800d86c: 681b ldr r3, [r3, #0] + 800d86e: 63bb str r3, [r7, #56] @ 0x38 + local_evtset = EvtSet; + 800d870: 4b6f ldr r3, [pc, #444] @ (800da30 ) + 800d872: 681b ldr r3, [r3, #0] + 800d874: 637b str r3, [r7, #52] @ 0x34 + local_taskmask = TaskMask; + 800d876: 4b6f ldr r3, [pc, #444] @ (800da34 ) + 800d878: 681b ldr r3, [r3, #0] + 800d87a: 633b str r3, [r7, #48] @ 0x30 + local_evtwaited = EvtWaited; + 800d87c: 4b6e ldr r3, [pc, #440] @ (800da38 ) + 800d87e: 681b ldr r3, [r3, #0] + 800d880: 62fb str r3, [r7, #44] @ 0x2c + while(((local_taskset & local_taskmask & SuperMask) != 0U) && ((local_evtset & local_evtwaited)==0U)) + 800d882: e08d b.n 800d9a0 + { + counter = 0U; + 800d884: 2300 movs r3, #0 + 800d886: 63fb str r3, [r7, #60] @ 0x3c + /* + * When a flag is set, the associated bit is set in TaskPrio[counter].priority mask depending + * on the priority parameter given from UTIL_SEQ_SetTask() + * The while loop is looking for a flag set from the highest priority maskr to the lower + */ + while((TaskPrio[counter].priority & local_taskmask & SuperMask)== 0U) + 800d888: e002 b.n 800d890 + { + counter++; + 800d88a: 6bfb ldr r3, [r7, #60] @ 0x3c + 800d88c: 3301 adds r3, #1 + 800d88e: 63fb str r3, [r7, #60] @ 0x3c + while((TaskPrio[counter].priority & local_taskmask & SuperMask)== 0U) + 800d890: 4a6a ldr r2, [pc, #424] @ (800da3c ) + 800d892: 6bfb ldr r3, [r7, #60] @ 0x3c + 800d894: f852 2033 ldr.w r2, [r2, r3, lsl #3] + 800d898: 6b3b ldr r3, [r7, #48] @ 0x30 + 800d89a: 401a ands r2, r3 + 800d89c: 4b62 ldr r3, [pc, #392] @ (800da28 ) + 800d89e: 681b ldr r3, [r3, #0] + 800d8a0: 4013 ands r3, r2 + 800d8a2: 2b00 cmp r3, #0 + 800d8a4: d0f1 beq.n 800d88a + } + + current_task_set = TaskPrio[counter].priority & local_taskmask & SuperMask; + 800d8a6: 4a65 ldr r2, [pc, #404] @ (800da3c ) + 800d8a8: 6bfb ldr r3, [r7, #60] @ 0x3c + 800d8aa: f852 2033 ldr.w r2, [r2, r3, lsl #3] + 800d8ae: 6b3b ldr r3, [r7, #48] @ 0x30 + 800d8b0: 401a ands r2, r3 + 800d8b2: 4b5d ldr r3, [pc, #372] @ (800da28 ) + 800d8b4: 681b ldr r3, [r3, #0] + 800d8b6: 4013 ands r3, r2 + 800d8b8: 627b str r3, [r7, #36] @ 0x24 + * so that the second one can be executed. + * Note that the first flag is not removed from the list of pending task but just masked by the round_robin mask + * + * In the check below, the round_robin mask is reinitialize in case all pending tasks haven been executed at least once + */ + if ((TaskPrio[counter].round_robin & current_task_set) == 0U) + 800d8ba: 4a60 ldr r2, [pc, #384] @ (800da3c ) + 800d8bc: 6bfb ldr r3, [r7, #60] @ 0x3c + 800d8be: 00db lsls r3, r3, #3 + 800d8c0: 4413 add r3, r2 + 800d8c2: 685a ldr r2, [r3, #4] + 800d8c4: 6a7b ldr r3, [r7, #36] @ 0x24 + 800d8c6: 4013 ands r3, r2 + 800d8c8: 2b00 cmp r3, #0 + 800d8ca: d106 bne.n 800d8da + { + TaskPrio[counter].round_robin = UTIL_SEQ_ALL_BIT_SET; + 800d8cc: 4a5b ldr r2, [pc, #364] @ (800da3c ) + 800d8ce: 6bfb ldr r3, [r7, #60] @ 0x3c + 800d8d0: 00db lsls r3, r3, #3 + 800d8d2: 4413 add r3, r2 + 800d8d4: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff + 800d8d8: 605a str r2, [r3, #4] + /* + * Read the flag index of the task to be executed + * Once the index is read, the associated task will be executed even though a higher priority stack is requested + * before task execution. + */ + CurrentTaskIdx = (SEQ_BitPosition(current_task_set & TaskPrio[counter].round_robin)); + 800d8da: 4a58 ldr r2, [pc, #352] @ (800da3c ) + 800d8dc: 6bfb ldr r3, [r7, #60] @ 0x3c + 800d8de: 00db lsls r3, r3, #3 + 800d8e0: 4413 add r3, r2 + 800d8e2: 685a ldr r2, [r3, #4] + 800d8e4: 6a7b ldr r3, [r7, #36] @ 0x24 + 800d8e6: 4013 ands r3, r2 + 800d8e8: 4618 mov r0, r3 + 800d8ea: f000 f8b9 bl 800da60 + 800d8ee: 4603 mov r3, r0 + 800d8f0: 461a mov r2, r3 + 800d8f2: 4b53 ldr r3, [pc, #332] @ (800da40 ) + 800d8f4: 601a str r2, [r3, #0] + + /* + * remove from the roun_robin mask the task that has been selected to be executed + */ + TaskPrio[counter].round_robin &= ~(1U << CurrentTaskIdx); + 800d8f6: 4a51 ldr r2, [pc, #324] @ (800da3c ) + 800d8f8: 6bfb ldr r3, [r7, #60] @ 0x3c + 800d8fa: 00db lsls r3, r3, #3 + 800d8fc: 4413 add r3, r2 + 800d8fe: 685a ldr r2, [r3, #4] + 800d900: 4b4f ldr r3, [pc, #316] @ (800da40 ) + 800d902: 681b ldr r3, [r3, #0] + 800d904: 2101 movs r1, #1 + 800d906: fa01 f303 lsl.w r3, r1, r3 + 800d90a: 43db mvns r3, r3 + 800d90c: 401a ands r2, r3 + 800d90e: 494b ldr r1, [pc, #300] @ (800da3c ) + 800d910: 6bfb ldr r3, [r7, #60] @ 0x3c + 800d912: 00db lsls r3, r3, #3 + 800d914: 440b add r3, r1 + 800d916: 605a str r2, [r3, #4] + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 800d918: f3ef 8310 mrs r3, PRIMASK + 800d91c: 61bb str r3, [r7, #24] + return(result); + 800d91e: 69bb ldr r3, [r7, #24] + + UTIL_SEQ_ENTER_CRITICAL_SECTION( ); + 800d920: 623b str r3, [r7, #32] + __ASM volatile ("cpsid i" : : : "memory"); + 800d922: b672 cpsid i +} + 800d924: bf00 nop + /* remove from the list or pending task the one that has been selected to be executed */ + TaskSet &= ~(1U << CurrentTaskIdx); + 800d926: 4b46 ldr r3, [pc, #280] @ (800da40 ) + 800d928: 681b ldr r3, [r3, #0] + 800d92a: 2201 movs r2, #1 + 800d92c: fa02 f303 lsl.w r3, r2, r3 + 800d930: 43da mvns r2, r3 + 800d932: 4b3e ldr r3, [pc, #248] @ (800da2c ) + 800d934: 681b ldr r3, [r3, #0] + 800d936: 4013 ands r3, r2 + 800d938: 4a3c ldr r2, [pc, #240] @ (800da2c ) + 800d93a: 6013 str r3, [r2, #0] + /* remove from all priority mask the task that has been selected to be executed */ + for (counter = UTIL_SEQ_CONF_PRIO_NBR; counter != 0U; counter--) + 800d93c: 2301 movs r3, #1 + 800d93e: 63fb str r3, [r7, #60] @ 0x3c + 800d940: e013 b.n 800d96a + { + TaskPrio[counter - 1U].priority &= ~(1U << CurrentTaskIdx); + 800d942: 6bfb ldr r3, [r7, #60] @ 0x3c + 800d944: 3b01 subs r3, #1 + 800d946: 4a3d ldr r2, [pc, #244] @ (800da3c ) + 800d948: f852 1033 ldr.w r1, [r2, r3, lsl #3] + 800d94c: 4b3c ldr r3, [pc, #240] @ (800da40 ) + 800d94e: 681b ldr r3, [r3, #0] + 800d950: 2201 movs r2, #1 + 800d952: fa02 f303 lsl.w r3, r2, r3 + 800d956: 43da mvns r2, r3 + 800d958: 6bfb ldr r3, [r7, #60] @ 0x3c + 800d95a: 3b01 subs r3, #1 + 800d95c: 400a ands r2, r1 + 800d95e: 4937 ldr r1, [pc, #220] @ (800da3c ) + 800d960: f841 2033 str.w r2, [r1, r3, lsl #3] + for (counter = UTIL_SEQ_CONF_PRIO_NBR; counter != 0U; counter--) + 800d964: 6bfb ldr r3, [r7, #60] @ 0x3c + 800d966: 3b01 subs r3, #1 + 800d968: 63fb str r3, [r7, #60] @ 0x3c + 800d96a: 6bfb ldr r3, [r7, #60] @ 0x3c + 800d96c: 2b00 cmp r3, #0 + 800d96e: d1e8 bne.n 800d942 + 800d970: 6a3b ldr r3, [r7, #32] + 800d972: 617b str r3, [r7, #20] + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 800d974: 697b ldr r3, [r7, #20] + 800d976: f383 8810 msr PRIMASK, r3 +} + 800d97a: bf00 nop + } + UTIL_SEQ_EXIT_CRITICAL_SECTION( ); + + /* Execute the task */ + TaskCb[CurrentTaskIdx]( ); + 800d97c: 4b30 ldr r3, [pc, #192] @ (800da40 ) + 800d97e: 681b ldr r3, [r3, #0] + 800d980: 4a30 ldr r2, [pc, #192] @ (800da44 ) + 800d982: f852 3023 ldr.w r3, [r2, r3, lsl #2] + 800d986: 4798 blx r3 + + local_taskset = TaskSet; + 800d988: 4b28 ldr r3, [pc, #160] @ (800da2c ) + 800d98a: 681b ldr r3, [r3, #0] + 800d98c: 63bb str r3, [r7, #56] @ 0x38 + local_evtset = EvtSet; + 800d98e: 4b28 ldr r3, [pc, #160] @ (800da30 ) + 800d990: 681b ldr r3, [r3, #0] + 800d992: 637b str r3, [r7, #52] @ 0x34 + local_taskmask = TaskMask; + 800d994: 4b27 ldr r3, [pc, #156] @ (800da34 ) + 800d996: 681b ldr r3, [r3, #0] + 800d998: 633b str r3, [r7, #48] @ 0x30 + local_evtwaited = EvtWaited; + 800d99a: 4b27 ldr r3, [pc, #156] @ (800da38 ) + 800d99c: 681b ldr r3, [r3, #0] + 800d99e: 62fb str r3, [r7, #44] @ 0x2c + while(((local_taskset & local_taskmask & SuperMask) != 0U) && ((local_evtset & local_evtwaited)==0U)) + 800d9a0: 6bba ldr r2, [r7, #56] @ 0x38 + 800d9a2: 6b3b ldr r3, [r7, #48] @ 0x30 + 800d9a4: 401a ands r2, r3 + 800d9a6: 4b20 ldr r3, [pc, #128] @ (800da28 ) + 800d9a8: 681b ldr r3, [r3, #0] + 800d9aa: 4013 ands r3, r2 + 800d9ac: 2b00 cmp r3, #0 + 800d9ae: d005 beq.n 800d9bc + 800d9b0: 6b7a ldr r2, [r7, #52] @ 0x34 + 800d9b2: 6afb ldr r3, [r7, #44] @ 0x2c + 800d9b4: 4013 ands r3, r2 + 800d9b6: 2b00 cmp r3, #0 + 800d9b8: f43f af64 beq.w 800d884 + } + + /* the set of CurrentTaskIdx to no task running allows to call WaitEvt in the Pre/Post ilde context */ + CurrentTaskIdx = UTIL_SEQ_NOTASKRUNNING; + 800d9bc: 4b20 ldr r3, [pc, #128] @ (800da40 ) + 800d9be: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff + 800d9c2: 601a str r2, [r3, #0] + UTIL_SEQ_PreIdle( ); + 800d9c4: f000 f840 bl 800da48 + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 800d9c8: f3ef 8310 mrs r3, PRIMASK + 800d9cc: 613b str r3, [r7, #16] + return(result); + 800d9ce: 693b ldr r3, [r7, #16] + + UTIL_SEQ_ENTER_CRITICAL_SECTION_IDLE( ); + 800d9d0: 61fb str r3, [r7, #28] + __ASM volatile ("cpsid i" : : : "memory"); + 800d9d2: b672 cpsid i +} + 800d9d4: bf00 nop + local_taskset = TaskSet; + 800d9d6: 4b15 ldr r3, [pc, #84] @ (800da2c ) + 800d9d8: 681b ldr r3, [r3, #0] + 800d9da: 63bb str r3, [r7, #56] @ 0x38 + local_evtset = EvtSet; + 800d9dc: 4b14 ldr r3, [pc, #80] @ (800da30 ) + 800d9de: 681b ldr r3, [r3, #0] + 800d9e0: 637b str r3, [r7, #52] @ 0x34 + local_taskmask = TaskMask; + 800d9e2: 4b14 ldr r3, [pc, #80] @ (800da34 ) + 800d9e4: 681b ldr r3, [r3, #0] + 800d9e6: 633b str r3, [r7, #48] @ 0x30 + if ((local_taskset & local_taskmask & SuperMask) == 0U) + 800d9e8: 6bba ldr r2, [r7, #56] @ 0x38 + 800d9ea: 6b3b ldr r3, [r7, #48] @ 0x30 + 800d9ec: 401a ands r2, r3 + 800d9ee: 4b0e ldr r3, [pc, #56] @ (800da28 ) + 800d9f0: 681b ldr r3, [r3, #0] + 800d9f2: 4013 ands r3, r2 + 800d9f4: 2b00 cmp r3, #0 + 800d9f6: d107 bne.n 800da08 + { + if ((local_evtset & EvtWaited)== 0U) + 800d9f8: 4b0f ldr r3, [pc, #60] @ (800da38 ) + 800d9fa: 681a ldr r2, [r3, #0] + 800d9fc: 6b7b ldr r3, [r7, #52] @ 0x34 + 800d9fe: 4013 ands r3, r2 + 800da00: 2b00 cmp r3, #0 + 800da02: d101 bne.n 800da08 + { + UTIL_SEQ_Idle( ); + 800da04: f7f3 f8ca bl 8000b9c + 800da08: 69fb ldr r3, [r7, #28] + 800da0a: 60fb str r3, [r7, #12] + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 800da0c: 68fb ldr r3, [r7, #12] + 800da0e: f383 8810 msr PRIMASK, r3 +} + 800da12: bf00 nop + } + } + UTIL_SEQ_EXIT_CRITICAL_SECTION_IDLE( ); + + UTIL_SEQ_PostIdle( ); + 800da14: f000 f81e bl 800da54 + + /* restore the mask from UTIL_SEQ_Run() */ + SuperMask = super_mask_backup; + 800da18: 4a03 ldr r2, [pc, #12] @ (800da28 ) + 800da1a: 6abb ldr r3, [r7, #40] @ 0x28 + 800da1c: 6013 str r3, [r2, #0] + + return; + 800da1e: bf00 nop +} + 800da20: 3740 adds r7, #64 @ 0x40 + 800da22: 46bd mov sp, r7 + 800da24: bd80 pop {r7, pc} + 800da26: bf00 nop + 800da28: 20000038 .word 0x20000038 + 800da2c: 20000be8 .word 0x20000be8 + 800da30: 20000bec .word 0x20000bec + 800da34: 20000034 .word 0x20000034 + 800da38: 20000bf0 .word 0x20000bf0 + 800da3c: 20000bfc .word 0x20000bfc + 800da40: 20000bf4 .word 0x20000bf4 + 800da44: 20000bf8 .word 0x20000bf8 + +0800da48 : +{ + return; +} + +__WEAK void UTIL_SEQ_PreIdle( void ) +{ + 800da48: b480 push {r7} + 800da4a: af00 add r7, sp, #0 + /* + * Unless specified by the application, there is nothing to be done + */ + return; + 800da4c: bf00 nop +} + 800da4e: 46bd mov sp, r7 + 800da50: bc80 pop {r7} + 800da52: 4770 bx lr + +0800da54 : + +__WEAK void UTIL_SEQ_PostIdle( void ) +{ + 800da54: b480 push {r7} + 800da56: af00 add r7, sp, #0 + /* + * Unless specified by the application, there is nothing to be done + */ + return; + 800da58: bf00 nop +} + 800da5a: 46bd mov sp, r7 + 800da5c: bc80 pop {r7} + 800da5e: 4770 bx lr + +0800da60 : + * @brief return the position of the first bit set to 1 + * @param Value 32 bit value + * @retval bit position + */ +uint8_t SEQ_BitPosition(uint32_t Value) +{ + 800da60: b480 push {r7} + 800da62: b085 sub sp, #20 + 800da64: af00 add r7, sp, #0 + 800da66: 6078 str r0, [r7, #4] +uint8_t n = 0U; + 800da68: 2300 movs r3, #0 + 800da6a: 73fb strb r3, [r7, #15] +uint32_t lvalue = Value; + 800da6c: 687b ldr r3, [r7, #4] + 800da6e: 60bb str r3, [r7, #8] + + if ((lvalue & 0xFFFF0000U) == 0U) { n = 16U; lvalue <<= 16U; } + 800da70: 68bb ldr r3, [r7, #8] + 800da72: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 + 800da76: d204 bcs.n 800da82 + 800da78: 2310 movs r3, #16 + 800da7a: 73fb strb r3, [r7, #15] + 800da7c: 68bb ldr r3, [r7, #8] + 800da7e: 041b lsls r3, r3, #16 + 800da80: 60bb str r3, [r7, #8] + if ((lvalue & 0xFF000000U) == 0U) { n += 8U; lvalue <<= 8U; } + 800da82: 68bb ldr r3, [r7, #8] + 800da84: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000 + 800da88: d205 bcs.n 800da96 + 800da8a: 7bfb ldrb r3, [r7, #15] + 800da8c: 3308 adds r3, #8 + 800da8e: 73fb strb r3, [r7, #15] + 800da90: 68bb ldr r3, [r7, #8] + 800da92: 021b lsls r3, r3, #8 + 800da94: 60bb str r3, [r7, #8] + if ((lvalue & 0xF0000000U) == 0U) { n += 4U; lvalue <<= 4U; } + 800da96: 68bb ldr r3, [r7, #8] + 800da98: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 + 800da9c: d205 bcs.n 800daaa + 800da9e: 7bfb ldrb r3, [r7, #15] + 800daa0: 3304 adds r3, #4 + 800daa2: 73fb strb r3, [r7, #15] + 800daa4: 68bb ldr r3, [r7, #8] + 800daa6: 011b lsls r3, r3, #4 + 800daa8: 60bb str r3, [r7, #8] + + n += SEQ_clz_table_4bit[lvalue >> (32-4)]; + 800daaa: 68bb ldr r3, [r7, #8] + 800daac: 0f1b lsrs r3, r3, #28 + 800daae: 4a07 ldr r2, [pc, #28] @ (800dacc ) + 800dab0: 5cd2 ldrb r2, [r2, r3] + 800dab2: 7bfb ldrb r3, [r7, #15] + 800dab4: 4413 add r3, r2 + 800dab6: 73fb strb r3, [r7, #15] + + return (uint8_t)(31U-n); + 800dab8: 7bfb ldrb r3, [r7, #15] + 800daba: f1c3 031f rsb r3, r3, #31 + 800dabe: b2db uxtb r3, r3 +} + 800dac0: 4618 mov r0, r3 + 800dac2: 3714 adds r7, #20 + 800dac4: 46bd mov sp, r7 + 800dac6: bc80 pop {r7} + 800dac8: 4770 bx lr + 800daca: bf00 nop + 800dacc: 0800fcbc .word 0x0800fcbc + +0800dad0 : + * @addtogroup TIMER_SERVER_exported_function + * @{ + */ + +UTIL_TIMER_Status_t UTIL_TIMER_Init(void) +{ + 800dad0: b580 push {r7, lr} + 800dad2: af00 add r7, sp, #0 + UTIL_TIMER_INIT_CRITICAL_SECTION(); + TimerListHead = NULL; + 800dad4: 4b04 ldr r3, [pc, #16] @ (800dae8 ) + 800dad6: 2200 movs r2, #0 + 800dad8: 601a str r2, [r3, #0] + return UTIL_TimerDriver.InitTimer(); + 800dada: 4b04 ldr r3, [pc, #16] @ (800daec ) + 800dadc: 681b ldr r3, [r3, #0] + 800dade: 4798 blx r3 + 800dae0: 4603 mov r3, r0 +} + 800dae2: 4618 mov r0, r3 + 800dae4: bd80 pop {r7, pc} + 800dae6: bf00 nop + 800dae8: 20000c04 .word 0x20000c04 + 800daec: 0800fb04 .word 0x0800fb04 + +0800daf0 : +{ + return UTIL_TimerDriver.DeInitTimer(); +} + +UTIL_TIMER_Status_t UTIL_TIMER_Create( UTIL_TIMER_Object_t *TimerObject, uint32_t PeriodValue, UTIL_TIMER_Mode_t Mode, void ( *Callback )( void *), void *Argument) +{ + 800daf0: b580 push {r7, lr} + 800daf2: b084 sub sp, #16 + 800daf4: af00 add r7, sp, #0 + 800daf6: 60f8 str r0, [r7, #12] + 800daf8: 60b9 str r1, [r7, #8] + 800dafa: 603b str r3, [r7, #0] + 800dafc: 4613 mov r3, r2 + 800dafe: 71fb strb r3, [r7, #7] + if((TimerObject != NULL) && (Callback != NULL)) + 800db00: 68fb ldr r3, [r7, #12] + 800db02: 2b00 cmp r3, #0 + 800db04: d023 beq.n 800db4e + 800db06: 683b ldr r3, [r7, #0] + 800db08: 2b00 cmp r3, #0 + 800db0a: d020 beq.n 800db4e + { + TimerObject->Timestamp = 0U; + 800db0c: 68fb ldr r3, [r7, #12] + 800db0e: 2200 movs r2, #0 + 800db10: 601a str r2, [r3, #0] + TimerObject->ReloadValue = UTIL_TimerDriver.ms2Tick(PeriodValue); + 800db12: 4b11 ldr r3, [pc, #68] @ (800db58 ) + 800db14: 6a5b ldr r3, [r3, #36] @ 0x24 + 800db16: 68b8 ldr r0, [r7, #8] + 800db18: 4798 blx r3 + 800db1a: 4602 mov r2, r0 + 800db1c: 68fb ldr r3, [r7, #12] + 800db1e: 605a str r2, [r3, #4] + TimerObject->IsPending = 0U; + 800db20: 68fb ldr r3, [r7, #12] + 800db22: 2200 movs r2, #0 + 800db24: 721a strb r2, [r3, #8] + TimerObject->IsRunning = 0U; + 800db26: 68fb ldr r3, [r7, #12] + 800db28: 2200 movs r2, #0 + 800db2a: 725a strb r2, [r3, #9] + TimerObject->IsReloadStopped = 0U; + 800db2c: 68fb ldr r3, [r7, #12] + 800db2e: 2200 movs r2, #0 + 800db30: 729a strb r2, [r3, #10] + TimerObject->Callback = Callback; + 800db32: 68fb ldr r3, [r7, #12] + 800db34: 683a ldr r2, [r7, #0] + 800db36: 60da str r2, [r3, #12] + TimerObject->argument = Argument; + 800db38: 68fb ldr r3, [r7, #12] + 800db3a: 69ba ldr r2, [r7, #24] + 800db3c: 611a str r2, [r3, #16] + TimerObject->Mode = Mode; + 800db3e: 68fb ldr r3, [r7, #12] + 800db40: 79fa ldrb r2, [r7, #7] + 800db42: 72da strb r2, [r3, #11] + TimerObject->Next = NULL; + 800db44: 68fb ldr r3, [r7, #12] + 800db46: 2200 movs r2, #0 + 800db48: 615a str r2, [r3, #20] + return UTIL_TIMER_OK; + 800db4a: 2300 movs r3, #0 + 800db4c: e000 b.n 800db50 + } + else + { + return UTIL_TIMER_INVALID_PARAM; + 800db4e: 2301 movs r3, #1 + } +} + 800db50: 4618 mov r0, r3 + 800db52: 3710 adds r7, #16 + 800db54: 46bd mov sp, r7 + 800db56: bd80 pop {r7, pc} + 800db58: 0800fb04 .word 0x0800fb04 + +0800db5c : + +UTIL_TIMER_Status_t UTIL_TIMER_Start( UTIL_TIMER_Object_t *TimerObject) +{ + 800db5c: b580 push {r7, lr} + 800db5e: b08a sub sp, #40 @ 0x28 + 800db60: af00 add r7, sp, #0 + 800db62: 6078 str r0, [r7, #4] + UTIL_TIMER_Status_t ret = UTIL_TIMER_OK; + 800db64: 2300 movs r3, #0 + 800db66: f887 3027 strb.w r3, [r7, #39] @ 0x27 + uint32_t elapsedTime; + uint32_t minValue; + uint32_t ticks; + + if(( TimerObject != NULL ) && ( TimerExists( TimerObject ) == false ) && (TimerObject->IsRunning == 0U)) + 800db6a: 687b ldr r3, [r7, #4] + 800db6c: 2b00 cmp r3, #0 + 800db6e: d056 beq.n 800dc1e + 800db70: 6878 ldr r0, [r7, #4] + 800db72: f000 f9a9 bl 800dec8 + 800db76: 4603 mov r3, r0 + 800db78: f083 0301 eor.w r3, r3, #1 + 800db7c: b2db uxtb r3, r3 + 800db7e: 2b00 cmp r3, #0 + 800db80: d04d beq.n 800dc1e + 800db82: 687b ldr r3, [r7, #4] + 800db84: 7a5b ldrb r3, [r3, #9] + 800db86: 2b00 cmp r3, #0 + 800db88: d149 bne.n 800dc1e + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 800db8a: f3ef 8310 mrs r3, PRIMASK + 800db8e: 613b str r3, [r7, #16] + return(result); + 800db90: 693b ldr r3, [r7, #16] + { + UTIL_TIMER_ENTER_CRITICAL_SECTION(); + 800db92: 61fb str r3, [r7, #28] + __ASM volatile ("cpsid i" : : : "memory"); + 800db94: b672 cpsid i +} + 800db96: bf00 nop + ticks = TimerObject->ReloadValue; + 800db98: 687b ldr r3, [r7, #4] + 800db9a: 685b ldr r3, [r3, #4] + 800db9c: 623b str r3, [r7, #32] + minValue = UTIL_TimerDriver.GetMinimumTimeout( ); + 800db9e: 4b24 ldr r3, [pc, #144] @ (800dc30 ) + 800dba0: 6a1b ldr r3, [r3, #32] + 800dba2: 4798 blx r3 + 800dba4: 61b8 str r0, [r7, #24] + + if( ticks < minValue ) + 800dba6: 6a3a ldr r2, [r7, #32] + 800dba8: 69bb ldr r3, [r7, #24] + 800dbaa: 429a cmp r2, r3 + 800dbac: d201 bcs.n 800dbb2 + { + ticks = minValue; + 800dbae: 69bb ldr r3, [r7, #24] + 800dbb0: 623b str r3, [r7, #32] + } + + TimerObject->Timestamp = ticks; + 800dbb2: 687b ldr r3, [r7, #4] + 800dbb4: 6a3a ldr r2, [r7, #32] + 800dbb6: 601a str r2, [r3, #0] + TimerObject->IsPending = 0U; + 800dbb8: 687b ldr r3, [r7, #4] + 800dbba: 2200 movs r2, #0 + 800dbbc: 721a strb r2, [r3, #8] + TimerObject->IsRunning = 1U; + 800dbbe: 687b ldr r3, [r7, #4] + 800dbc0: 2201 movs r2, #1 + 800dbc2: 725a strb r2, [r3, #9] + TimerObject->IsReloadStopped = 0U; + 800dbc4: 687b ldr r3, [r7, #4] + 800dbc6: 2200 movs r2, #0 + 800dbc8: 729a strb r2, [r3, #10] + if( TimerListHead == NULL ) + 800dbca: 4b1a ldr r3, [pc, #104] @ (800dc34 ) + 800dbcc: 681b ldr r3, [r3, #0] + 800dbce: 2b00 cmp r3, #0 + 800dbd0: d106 bne.n 800dbe0 + { + UTIL_TimerDriver.SetTimerContext(); + 800dbd2: 4b17 ldr r3, [pc, #92] @ (800dc30 ) + 800dbd4: 691b ldr r3, [r3, #16] + 800dbd6: 4798 blx r3 + TimerInsertNewHeadTimer( TimerObject ); /* insert a timeout at now+obj->Timestamp */ + 800dbd8: 6878 ldr r0, [r7, #4] + 800dbda: f000 f9eb bl 800dfb4 + 800dbde: e017 b.n 800dc10 + } + else + { + elapsedTime = UTIL_TimerDriver.GetTimerElapsedTime( ); + 800dbe0: 4b13 ldr r3, [pc, #76] @ (800dc30 ) + 800dbe2: 699b ldr r3, [r3, #24] + 800dbe4: 4798 blx r3 + 800dbe6: 6178 str r0, [r7, #20] + TimerObject->Timestamp += elapsedTime; + 800dbe8: 687b ldr r3, [r7, #4] + 800dbea: 681a ldr r2, [r3, #0] + 800dbec: 697b ldr r3, [r7, #20] + 800dbee: 441a add r2, r3 + 800dbf0: 687b ldr r3, [r7, #4] + 800dbf2: 601a str r2, [r3, #0] + + if( TimerObject->Timestamp < TimerListHead->Timestamp ) + 800dbf4: 687b ldr r3, [r7, #4] + 800dbf6: 681a ldr r2, [r3, #0] + 800dbf8: 4b0e ldr r3, [pc, #56] @ (800dc34 ) + 800dbfa: 681b ldr r3, [r3, #0] + 800dbfc: 681b ldr r3, [r3, #0] + 800dbfe: 429a cmp r2, r3 + 800dc00: d203 bcs.n 800dc0a + { + TimerInsertNewHeadTimer( TimerObject); + 800dc02: 6878 ldr r0, [r7, #4] + 800dc04: f000 f9d6 bl 800dfb4 + 800dc08: e002 b.n 800dc10 + } + else + { + TimerInsertTimer( TimerObject); + 800dc0a: 6878 ldr r0, [r7, #4] + 800dc0c: f000 f9a2 bl 800df54 + 800dc10: 69fb ldr r3, [r7, #28] + 800dc12: 60fb str r3, [r7, #12] + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 800dc14: 68fb ldr r3, [r7, #12] + 800dc16: f383 8810 msr PRIMASK, r3 +} + 800dc1a: bf00 nop + { + 800dc1c: e002 b.n 800dc24 + } + UTIL_TIMER_EXIT_CRITICAL_SECTION(); + } + else + { + ret = UTIL_TIMER_INVALID_PARAM; + 800dc1e: 2301 movs r3, #1 + 800dc20: f887 3027 strb.w r3, [r7, #39] @ 0x27 + } + return ret; + 800dc24: f897 3027 ldrb.w r3, [r7, #39] @ 0x27 +} + 800dc28: 4618 mov r0, r3 + 800dc2a: 3728 adds r7, #40 @ 0x28 + 800dc2c: 46bd mov sp, r7 + 800dc2e: bd80 pop {r7, pc} + 800dc30: 0800fb04 .word 0x0800fb04 + 800dc34: 20000c04 .word 0x20000c04 + +0800dc38 : + } + return ret; +} + +UTIL_TIMER_Status_t UTIL_TIMER_Stop( UTIL_TIMER_Object_t *TimerObject ) +{ + 800dc38: b580 push {r7, lr} + 800dc3a: b088 sub sp, #32 + 800dc3c: af00 add r7, sp, #0 + 800dc3e: 6078 str r0, [r7, #4] + UTIL_TIMER_Status_t ret = UTIL_TIMER_OK; + 800dc40: 2300 movs r3, #0 + 800dc42: 77fb strb r3, [r7, #31] + + if (NULL != TimerObject) + 800dc44: 687b ldr r3, [r7, #4] + 800dc46: 2b00 cmp r3, #0 + 800dc48: d05b beq.n 800dd02 + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 800dc4a: f3ef 8310 mrs r3, PRIMASK + 800dc4e: 60fb str r3, [r7, #12] + return(result); + 800dc50: 68fb ldr r3, [r7, #12] + { + UTIL_TIMER_ENTER_CRITICAL_SECTION(); + 800dc52: 613b str r3, [r7, #16] + __ASM volatile ("cpsid i" : : : "memory"); + 800dc54: b672 cpsid i +} + 800dc56: bf00 nop + UTIL_TIMER_Object_t* prev = TimerListHead; + 800dc58: 4b2d ldr r3, [pc, #180] @ (800dd10 ) + 800dc5a: 681b ldr r3, [r3, #0] + 800dc5c: 61bb str r3, [r7, #24] + UTIL_TIMER_Object_t* cur = TimerListHead; + 800dc5e: 4b2c ldr r3, [pc, #176] @ (800dd10 ) + 800dc60: 681b ldr r3, [r3, #0] + 800dc62: 617b str r3, [r7, #20] + TimerObject->IsReloadStopped = 1U; + 800dc64: 687b ldr r3, [r7, #4] + 800dc66: 2201 movs r2, #1 + 800dc68: 729a strb r2, [r3, #10] + + /* List is empty or the Obj to stop does not exist */ + if(NULL != TimerListHead) + 800dc6a: 4b29 ldr r3, [pc, #164] @ (800dd10 ) + 800dc6c: 681b ldr r3, [r3, #0] + 800dc6e: 2b00 cmp r3, #0 + 800dc70: d041 beq.n 800dcf6 + { + TimerObject->IsRunning = 0U; + 800dc72: 687b ldr r3, [r7, #4] + 800dc74: 2200 movs r2, #0 + 800dc76: 725a strb r2, [r3, #9] + + if( TimerListHead == TimerObject ) /* Stop the Head */ + 800dc78: 4b25 ldr r3, [pc, #148] @ (800dd10 ) + 800dc7a: 681b ldr r3, [r3, #0] + 800dc7c: 687a ldr r2, [r7, #4] + 800dc7e: 429a cmp r2, r3 + 800dc80: d134 bne.n 800dcec + { + TimerListHead->IsPending = 0; + 800dc82: 4b23 ldr r3, [pc, #140] @ (800dd10 ) + 800dc84: 681b ldr r3, [r3, #0] + 800dc86: 2200 movs r2, #0 + 800dc88: 721a strb r2, [r3, #8] + if( TimerListHead->Next != NULL ) + 800dc8a: 4b21 ldr r3, [pc, #132] @ (800dd10 ) + 800dc8c: 681b ldr r3, [r3, #0] + 800dc8e: 695b ldr r3, [r3, #20] + 800dc90: 2b00 cmp r3, #0 + 800dc92: d00a beq.n 800dcaa + { + TimerListHead = TimerListHead->Next; + 800dc94: 4b1e ldr r3, [pc, #120] @ (800dd10 ) + 800dc96: 681b ldr r3, [r3, #0] + 800dc98: 695b ldr r3, [r3, #20] + 800dc9a: 4a1d ldr r2, [pc, #116] @ (800dd10 ) + 800dc9c: 6013 str r3, [r2, #0] + TimerSetTimeout( TimerListHead ); + 800dc9e: 4b1c ldr r3, [pc, #112] @ (800dd10 ) + 800dca0: 681b ldr r3, [r3, #0] + 800dca2: 4618 mov r0, r3 + 800dca4: f000 f92c bl 800df00 + 800dca8: e023 b.n 800dcf2 + } + else + { + UTIL_TimerDriver.StopTimerEvt( ); + 800dcaa: 4b1a ldr r3, [pc, #104] @ (800dd14 ) + 800dcac: 68db ldr r3, [r3, #12] + 800dcae: 4798 blx r3 + TimerListHead = NULL; + 800dcb0: 4b17 ldr r3, [pc, #92] @ (800dd10 ) + 800dcb2: 2200 movs r2, #0 + 800dcb4: 601a str r2, [r3, #0] + 800dcb6: e01c b.n 800dcf2 + } + else /* Stop an object within the list */ + { + while( cur != NULL ) + { + if( cur == TimerObject ) + 800dcb8: 697a ldr r2, [r7, #20] + 800dcba: 687b ldr r3, [r7, #4] + 800dcbc: 429a cmp r2, r3 + 800dcbe: d110 bne.n 800dce2 + { + if( cur->Next != NULL ) + 800dcc0: 697b ldr r3, [r7, #20] + 800dcc2: 695b ldr r3, [r3, #20] + 800dcc4: 2b00 cmp r3, #0 + 800dcc6: d006 beq.n 800dcd6 + { + cur = cur->Next; + 800dcc8: 697b ldr r3, [r7, #20] + 800dcca: 695b ldr r3, [r3, #20] + 800dccc: 617b str r3, [r7, #20] + prev->Next = cur; + 800dcce: 69bb ldr r3, [r7, #24] + 800dcd0: 697a ldr r2, [r7, #20] + 800dcd2: 615a str r2, [r3, #20] + else + { + cur = NULL; + prev->Next = cur; + } + break; + 800dcd4: e00d b.n 800dcf2 + cur = NULL; + 800dcd6: 2300 movs r3, #0 + 800dcd8: 617b str r3, [r7, #20] + prev->Next = cur; + 800dcda: 69bb ldr r3, [r7, #24] + 800dcdc: 697a ldr r2, [r7, #20] + 800dcde: 615a str r2, [r3, #20] + break; + 800dce0: e007 b.n 800dcf2 + } + else + { + prev = cur; + 800dce2: 697b ldr r3, [r7, #20] + 800dce4: 61bb str r3, [r7, #24] + cur = cur->Next; + 800dce6: 697b ldr r3, [r7, #20] + 800dce8: 695b ldr r3, [r3, #20] + 800dcea: 617b str r3, [r7, #20] + while( cur != NULL ) + 800dcec: 697b ldr r3, [r7, #20] + 800dcee: 2b00 cmp r3, #0 + 800dcf0: d1e2 bne.n 800dcb8 + } + } + } + ret = UTIL_TIMER_OK; + 800dcf2: 2300 movs r3, #0 + 800dcf4: 77fb strb r3, [r7, #31] + 800dcf6: 693b ldr r3, [r7, #16] + 800dcf8: 60bb str r3, [r7, #8] + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 800dcfa: 68bb ldr r3, [r7, #8] + 800dcfc: f383 8810 msr PRIMASK, r3 +} + 800dd00: e001 b.n 800dd06 + } + UTIL_TIMER_EXIT_CRITICAL_SECTION(); + } + else + { + ret = UTIL_TIMER_INVALID_PARAM; + 800dd02: 2301 movs r3, #1 + 800dd04: 77fb strb r3, [r7, #31] + } + return ret; + 800dd06: 7ffb ldrb r3, [r7, #31] +} + 800dd08: 4618 mov r0, r3 + 800dd0a: 3720 adds r7, #32 + 800dd0c: 46bd mov sp, r7 + 800dd0e: bd80 pop {r7, pc} + 800dd10: 20000c04 .word 0x20000c04 + 800dd14: 0800fb04 .word 0x0800fb04 + +0800dd18 : + +UTIL_TIMER_Status_t UTIL_TIMER_SetPeriod(UTIL_TIMER_Object_t *TimerObject, uint32_t NewPeriodValue) +{ + 800dd18: b580 push {r7, lr} + 800dd1a: b084 sub sp, #16 + 800dd1c: af00 add r7, sp, #0 + 800dd1e: 6078 str r0, [r7, #4] + 800dd20: 6039 str r1, [r7, #0] + UTIL_TIMER_Status_t ret = UTIL_TIMER_OK; + 800dd22: 2300 movs r3, #0 + 800dd24: 73fb strb r3, [r7, #15] + + if(NULL == TimerObject) + 800dd26: 687b ldr r3, [r7, #4] + 800dd28: 2b00 cmp r3, #0 + 800dd2a: d102 bne.n 800dd32 + { + ret = UTIL_TIMER_INVALID_PARAM; + 800dd2c: 2301 movs r3, #1 + 800dd2e: 73fb strb r3, [r7, #15] + 800dd30: e014 b.n 800dd5c + } + else + { + TimerObject->ReloadValue = UTIL_TimerDriver.ms2Tick(NewPeriodValue); + 800dd32: 4b0d ldr r3, [pc, #52] @ (800dd68 ) + 800dd34: 6a5b ldr r3, [r3, #36] @ 0x24 + 800dd36: 6838 ldr r0, [r7, #0] + 800dd38: 4798 blx r3 + 800dd3a: 4602 mov r2, r0 + 800dd3c: 687b ldr r3, [r7, #4] + 800dd3e: 605a str r2, [r3, #4] + if(TimerExists(TimerObject)) + 800dd40: 6878 ldr r0, [r7, #4] + 800dd42: f000 f8c1 bl 800dec8 + 800dd46: 4603 mov r3, r0 + 800dd48: 2b00 cmp r3, #0 + 800dd4a: d007 beq.n 800dd5c + { + (void)UTIL_TIMER_Stop(TimerObject); + 800dd4c: 6878 ldr r0, [r7, #4] + 800dd4e: f7ff ff73 bl 800dc38 + ret = UTIL_TIMER_Start(TimerObject); + 800dd52: 6878 ldr r0, [r7, #4] + 800dd54: f7ff ff02 bl 800db5c + 800dd58: 4603 mov r3, r0 + 800dd5a: 73fb strb r3, [r7, #15] + } + } + return ret; + 800dd5c: 7bfb ldrb r3, [r7, #15] +} + 800dd5e: 4618 mov r0, r3 + 800dd60: 3710 adds r7, #16 + 800dd62: 46bd mov sp, r7 + 800dd64: bd80 pop {r7, pc} + 800dd66: bf00 nop + 800dd68: 0800fb04 .word 0x0800fb04 + +0800dd6c : + } + return NextTimer; +} + +void UTIL_TIMER_IRQ_Handler( void ) +{ + 800dd6c: b590 push {r4, r7, lr} + 800dd6e: b089 sub sp, #36 @ 0x24 + 800dd70: af00 add r7, sp, #0 + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 800dd72: f3ef 8310 mrs r3, PRIMASK + 800dd76: 60bb str r3, [r7, #8] + return(result); + 800dd78: 68bb ldr r3, [r7, #8] + UTIL_TIMER_Object_t* cur; + uint32_t old, now, DeltaContext; + + UTIL_TIMER_ENTER_CRITICAL_SECTION(); + 800dd7a: 61bb str r3, [r7, #24] + __ASM volatile ("cpsid i" : : : "memory"); + 800dd7c: b672 cpsid i +} + 800dd7e: bf00 nop + + old = UTIL_TimerDriver.GetTimerContext( ); + 800dd80: 4b38 ldr r3, [pc, #224] @ (800de64 ) + 800dd82: 695b ldr r3, [r3, #20] + 800dd84: 4798 blx r3 + 800dd86: 6178 str r0, [r7, #20] + now = UTIL_TimerDriver.SetTimerContext( ); + 800dd88: 4b36 ldr r3, [pc, #216] @ (800de64 ) + 800dd8a: 691b ldr r3, [r3, #16] + 800dd8c: 4798 blx r3 + 800dd8e: 6138 str r0, [r7, #16] + + DeltaContext = now - old; /*intentional wrap around */ + 800dd90: 693a ldr r2, [r7, #16] + 800dd92: 697b ldr r3, [r7, #20] + 800dd94: 1ad3 subs r3, r2, r3 + 800dd96: 60fb str r3, [r7, #12] + + /* update timeStamp based upon new Time Reference*/ + /* because delta context should never exceed 2^32*/ + if ( TimerListHead != NULL ) + 800dd98: 4b33 ldr r3, [pc, #204] @ (800de68 ) + 800dd9a: 681b ldr r3, [r3, #0] + 800dd9c: 2b00 cmp r3, #0 + 800dd9e: d037 beq.n 800de10 + { + cur = TimerListHead; + 800dda0: 4b31 ldr r3, [pc, #196] @ (800de68 ) + 800dda2: 681b ldr r3, [r3, #0] + 800dda4: 61fb str r3, [r7, #28] + do { + if (cur->Timestamp > DeltaContext) + 800dda6: 69fb ldr r3, [r7, #28] + 800dda8: 681b ldr r3, [r3, #0] + 800ddaa: 68fa ldr r2, [r7, #12] + 800ddac: 429a cmp r2, r3 + 800ddae: d206 bcs.n 800ddbe + { + cur->Timestamp -= DeltaContext; + 800ddb0: 69fb ldr r3, [r7, #28] + 800ddb2: 681a ldr r2, [r3, #0] + 800ddb4: 68fb ldr r3, [r7, #12] + 800ddb6: 1ad2 subs r2, r2, r3 + 800ddb8: 69fb ldr r3, [r7, #28] + 800ddba: 601a str r2, [r3, #0] + 800ddbc: e002 b.n 800ddc4 + } + else + { + cur->Timestamp = 0; + 800ddbe: 69fb ldr r3, [r7, #28] + 800ddc0: 2200 movs r2, #0 + 800ddc2: 601a str r2, [r3, #0] + } + cur = cur->Next; + 800ddc4: 69fb ldr r3, [r7, #28] + 800ddc6: 695b ldr r3, [r3, #20] + 800ddc8: 61fb str r3, [r7, #28] + } while(cur != NULL); + 800ddca: 69fb ldr r3, [r7, #28] + 800ddcc: 2b00 cmp r3, #0 + 800ddce: d1ea bne.n 800dda6 + } + + /* Execute expired timer and update the list */ + while ((TimerListHead != NULL) && ((TimerListHead->Timestamp == 0U) || (TimerListHead->Timestamp < UTIL_TimerDriver.GetTimerElapsedTime( )))) + 800ddd0: e01e b.n 800de10 + { + cur = TimerListHead; + 800ddd2: 4b25 ldr r3, [pc, #148] @ (800de68 ) + 800ddd4: 681b ldr r3, [r3, #0] + 800ddd6: 61fb str r3, [r7, #28] + TimerListHead = TimerListHead->Next; + 800ddd8: 4b23 ldr r3, [pc, #140] @ (800de68 ) + 800ddda: 681b ldr r3, [r3, #0] + 800dddc: 695b ldr r3, [r3, #20] + 800ddde: 4a22 ldr r2, [pc, #136] @ (800de68 ) + 800dde0: 6013 str r3, [r2, #0] + cur->IsPending = 0; + 800dde2: 69fb ldr r3, [r7, #28] + 800dde4: 2200 movs r2, #0 + 800dde6: 721a strb r2, [r3, #8] + cur->IsRunning = 0; + 800dde8: 69fb ldr r3, [r7, #28] + 800ddea: 2200 movs r2, #0 + 800ddec: 725a strb r2, [r3, #9] + cur->Callback(cur->argument); + 800ddee: 69fb ldr r3, [r7, #28] + 800ddf0: 68db ldr r3, [r3, #12] + 800ddf2: 69fa ldr r2, [r7, #28] + 800ddf4: 6912 ldr r2, [r2, #16] + 800ddf6: 4610 mov r0, r2 + 800ddf8: 4798 blx r3 + if(( cur->Mode == UTIL_TIMER_PERIODIC) && (cur->IsReloadStopped == 0U)) + 800ddfa: 69fb ldr r3, [r7, #28] + 800ddfc: 7adb ldrb r3, [r3, #11] + 800ddfe: 2b01 cmp r3, #1 + 800de00: d106 bne.n 800de10 + 800de02: 69fb ldr r3, [r7, #28] + 800de04: 7a9b ldrb r3, [r3, #10] + 800de06: 2b00 cmp r3, #0 + 800de08: d102 bne.n 800de10 + { + (void)UTIL_TIMER_Start(cur); + 800de0a: 69f8 ldr r0, [r7, #28] + 800de0c: f7ff fea6 bl 800db5c + while ((TimerListHead != NULL) && ((TimerListHead->Timestamp == 0U) || (TimerListHead->Timestamp < UTIL_TimerDriver.GetTimerElapsedTime( )))) + 800de10: 4b15 ldr r3, [pc, #84] @ (800de68 ) + 800de12: 681b ldr r3, [r3, #0] + 800de14: 2b00 cmp r3, #0 + 800de16: d00d beq.n 800de34 + 800de18: 4b13 ldr r3, [pc, #76] @ (800de68 ) + 800de1a: 681b ldr r3, [r3, #0] + 800de1c: 681b ldr r3, [r3, #0] + 800de1e: 2b00 cmp r3, #0 + 800de20: d0d7 beq.n 800ddd2 + 800de22: 4b11 ldr r3, [pc, #68] @ (800de68 ) + 800de24: 681b ldr r3, [r3, #0] + 800de26: 681c ldr r4, [r3, #0] + 800de28: 4b0e ldr r3, [pc, #56] @ (800de64 ) + 800de2a: 699b ldr r3, [r3, #24] + 800de2c: 4798 blx r3 + 800de2e: 4603 mov r3, r0 + 800de30: 429c cmp r4, r3 + 800de32: d3ce bcc.n 800ddd2 + } + } + + /* start the next TimerListHead if it exists and it is not pending*/ + if(( TimerListHead != NULL ) && (TimerListHead->IsPending == 0U)) + 800de34: 4b0c ldr r3, [pc, #48] @ (800de68 ) + 800de36: 681b ldr r3, [r3, #0] + 800de38: 2b00 cmp r3, #0 + 800de3a: d009 beq.n 800de50 + 800de3c: 4b0a ldr r3, [pc, #40] @ (800de68 ) + 800de3e: 681b ldr r3, [r3, #0] + 800de40: 7a1b ldrb r3, [r3, #8] + 800de42: 2b00 cmp r3, #0 + 800de44: d104 bne.n 800de50 + { + TimerSetTimeout( TimerListHead ); + 800de46: 4b08 ldr r3, [pc, #32] @ (800de68 ) + 800de48: 681b ldr r3, [r3, #0] + 800de4a: 4618 mov r0, r3 + 800de4c: f000 f858 bl 800df00 + 800de50: 69bb ldr r3, [r7, #24] + 800de52: 607b str r3, [r7, #4] + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 800de54: 687b ldr r3, [r7, #4] + 800de56: f383 8810 msr PRIMASK, r3 +} + 800de5a: bf00 nop + } + UTIL_TIMER_EXIT_CRITICAL_SECTION(); +} + 800de5c: bf00 nop + 800de5e: 3724 adds r7, #36 @ 0x24 + 800de60: 46bd mov sp, r7 + 800de62: bd90 pop {r4, r7, pc} + 800de64: 0800fb04 .word 0x0800fb04 + 800de68: 20000c04 .word 0x20000c04 + +0800de6c : + +UTIL_TIMER_Time_t UTIL_TIMER_GetCurrentTime(void) +{ + 800de6c: b580 push {r7, lr} + 800de6e: b082 sub sp, #8 + 800de70: af00 add r7, sp, #0 + uint32_t now = UTIL_TimerDriver.GetTimerValue( ); + 800de72: 4b06 ldr r3, [pc, #24] @ (800de8c ) + 800de74: 69db ldr r3, [r3, #28] + 800de76: 4798 blx r3 + 800de78: 6078 str r0, [r7, #4] + return UTIL_TimerDriver.Tick2ms(now); + 800de7a: 4b04 ldr r3, [pc, #16] @ (800de8c ) + 800de7c: 6a9b ldr r3, [r3, #40] @ 0x28 + 800de7e: 6878 ldr r0, [r7, #4] + 800de80: 4798 blx r3 + 800de82: 4603 mov r3, r0 +} + 800de84: 4618 mov r0, r3 + 800de86: 3708 adds r7, #8 + 800de88: 46bd mov sp, r7 + 800de8a: bd80 pop {r7, pc} + 800de8c: 0800fb04 .word 0x0800fb04 + +0800de90 : + +UTIL_TIMER_Time_t UTIL_TIMER_GetElapsedTime(UTIL_TIMER_Time_t past ) +{ + 800de90: b580 push {r7, lr} + 800de92: b084 sub sp, #16 + 800de94: af00 add r7, sp, #0 + 800de96: 6078 str r0, [r7, #4] + uint32_t nowInTicks = UTIL_TimerDriver.GetTimerValue( ); + 800de98: 4b0a ldr r3, [pc, #40] @ (800dec4 ) + 800de9a: 69db ldr r3, [r3, #28] + 800de9c: 4798 blx r3 + 800de9e: 60f8 str r0, [r7, #12] + uint32_t pastInTicks = UTIL_TimerDriver.ms2Tick( past ); + 800dea0: 4b08 ldr r3, [pc, #32] @ (800dec4 ) + 800dea2: 6a5b ldr r3, [r3, #36] @ 0x24 + 800dea4: 6878 ldr r0, [r7, #4] + 800dea6: 4798 blx r3 + 800dea8: 60b8 str r0, [r7, #8] + /* intentional wrap around. Works Ok if tick duation below 1ms */ + return UTIL_TimerDriver.Tick2ms( nowInTicks- pastInTicks ); + 800deaa: 4b06 ldr r3, [pc, #24] @ (800dec4 ) + 800deac: 6a9b ldr r3, [r3, #40] @ 0x28 + 800deae: 68f9 ldr r1, [r7, #12] + 800deb0: 68ba ldr r2, [r7, #8] + 800deb2: 1a8a subs r2, r1, r2 + 800deb4: 4610 mov r0, r2 + 800deb6: 4798 blx r3 + 800deb8: 4603 mov r3, r0 +} + 800deba: 4618 mov r0, r3 + 800debc: 3710 adds r7, #16 + 800debe: 46bd mov sp, r7 + 800dec0: bd80 pop {r7, pc} + 800dec2: bf00 nop + 800dec4: 0800fb04 .word 0x0800fb04 + +0800dec8 : + * + * @param TimerObject Structure containing the timer object parameters + * @retval 1 (the object is already in the list) or 0 + */ +bool TimerExists( UTIL_TIMER_Object_t *TimerObject ) +{ + 800dec8: b480 push {r7} + 800deca: b085 sub sp, #20 + 800decc: af00 add r7, sp, #0 + 800dece: 6078 str r0, [r7, #4] + UTIL_TIMER_Object_t* cur = TimerListHead; + 800ded0: 4b0a ldr r3, [pc, #40] @ (800defc ) + 800ded2: 681b ldr r3, [r3, #0] + 800ded4: 60fb str r3, [r7, #12] + + while( cur != NULL ) + 800ded6: e008 b.n 800deea + { + if( cur == TimerObject ) + 800ded8: 68fa ldr r2, [r7, #12] + 800deda: 687b ldr r3, [r7, #4] + 800dedc: 429a cmp r2, r3 + 800dede: d101 bne.n 800dee4 + { + return true; + 800dee0: 2301 movs r3, #1 + 800dee2: e006 b.n 800def2 + } + cur = cur->Next; + 800dee4: 68fb ldr r3, [r7, #12] + 800dee6: 695b ldr r3, [r3, #20] + 800dee8: 60fb str r3, [r7, #12] + while( cur != NULL ) + 800deea: 68fb ldr r3, [r7, #12] + 800deec: 2b00 cmp r3, #0 + 800deee: d1f3 bne.n 800ded8 + } + return false; + 800def0: 2300 movs r3, #0 +} + 800def2: 4618 mov r0, r3 + 800def4: 3714 adds r7, #20 + 800def6: 46bd mov sp, r7 + 800def8: bc80 pop {r7} + 800defa: 4770 bx lr + 800defc: 20000c04 .word 0x20000c04 + +0800df00 : + * @brief Sets a timeout with the duration "timestamp" + * + * @param TimerObject Structure containing the timer object parameters + */ +void TimerSetTimeout( UTIL_TIMER_Object_t *TimerObject ) +{ + 800df00: b590 push {r4, r7, lr} + 800df02: b085 sub sp, #20 + 800df04: af00 add r7, sp, #0 + 800df06: 6078 str r0, [r7, #4] + uint32_t minTicks= UTIL_TimerDriver.GetMinimumTimeout( ); + 800df08: 4b11 ldr r3, [pc, #68] @ (800df50 ) + 800df0a: 6a1b ldr r3, [r3, #32] + 800df0c: 4798 blx r3 + 800df0e: 60f8 str r0, [r7, #12] + TimerObject->IsPending = 1; + 800df10: 687b ldr r3, [r7, #4] + 800df12: 2201 movs r2, #1 + 800df14: 721a strb r2, [r3, #8] + + /* In case deadline too soon */ + if(TimerObject->Timestamp < (UTIL_TimerDriver.GetTimerElapsedTime( ) + minTicks) ) + 800df16: 687b ldr r3, [r7, #4] + 800df18: 681c ldr r4, [r3, #0] + 800df1a: 4b0d ldr r3, [pc, #52] @ (800df50 ) + 800df1c: 699b ldr r3, [r3, #24] + 800df1e: 4798 blx r3 + 800df20: 4602 mov r2, r0 + 800df22: 68fb ldr r3, [r7, #12] + 800df24: 4413 add r3, r2 + 800df26: 429c cmp r4, r3 + 800df28: d207 bcs.n 800df3a + { + TimerObject->Timestamp = UTIL_TimerDriver.GetTimerElapsedTime( ) + minTicks; + 800df2a: 4b09 ldr r3, [pc, #36] @ (800df50 ) + 800df2c: 699b ldr r3, [r3, #24] + 800df2e: 4798 blx r3 + 800df30: 4602 mov r2, r0 + 800df32: 68fb ldr r3, [r7, #12] + 800df34: 441a add r2, r3 + 800df36: 687b ldr r3, [r7, #4] + 800df38: 601a str r2, [r3, #0] + } + UTIL_TimerDriver.StartTimerEvt( TimerObject->Timestamp ); + 800df3a: 4b05 ldr r3, [pc, #20] @ (800df50 ) + 800df3c: 689b ldr r3, [r3, #8] + 800df3e: 687a ldr r2, [r7, #4] + 800df40: 6812 ldr r2, [r2, #0] + 800df42: 4610 mov r0, r2 + 800df44: 4798 blx r3 +} + 800df46: bf00 nop + 800df48: 3714 adds r7, #20 + 800df4a: 46bd mov sp, r7 + 800df4c: bd90 pop {r4, r7, pc} + 800df4e: bf00 nop + 800df50: 0800fb04 .word 0x0800fb04 + +0800df54 : + * next timer to expire. + * + * @param TimerObject Structure containing the timer object parameters + */ +void TimerInsertTimer( UTIL_TIMER_Object_t *TimerObject) +{ + 800df54: b480 push {r7} + 800df56: b085 sub sp, #20 + 800df58: af00 add r7, sp, #0 + 800df5a: 6078 str r0, [r7, #4] + UTIL_TIMER_Object_t* cur = TimerListHead; + 800df5c: 4b14 ldr r3, [pc, #80] @ (800dfb0 ) + 800df5e: 681b ldr r3, [r3, #0] + 800df60: 60fb str r3, [r7, #12] + UTIL_TIMER_Object_t* next = TimerListHead->Next; + 800df62: 4b13 ldr r3, [pc, #76] @ (800dfb0 ) + 800df64: 681b ldr r3, [r3, #0] + 800df66: 695b ldr r3, [r3, #20] + 800df68: 60bb str r3, [r7, #8] + + while (cur->Next != NULL ) + 800df6a: e012 b.n 800df92 + { + if( TimerObject->Timestamp > next->Timestamp ) + 800df6c: 687b ldr r3, [r7, #4] + 800df6e: 681a ldr r2, [r3, #0] + 800df70: 68bb ldr r3, [r7, #8] + 800df72: 681b ldr r3, [r3, #0] + 800df74: 429a cmp r2, r3 + 800df76: d905 bls.n 800df84 + { + cur = next; + 800df78: 68bb ldr r3, [r7, #8] + 800df7a: 60fb str r3, [r7, #12] + next = next->Next; + 800df7c: 68bb ldr r3, [r7, #8] + 800df7e: 695b ldr r3, [r3, #20] + 800df80: 60bb str r3, [r7, #8] + 800df82: e006 b.n 800df92 + } + else + { + cur->Next = TimerObject; + 800df84: 68fb ldr r3, [r7, #12] + 800df86: 687a ldr r2, [r7, #4] + 800df88: 615a str r2, [r3, #20] + TimerObject->Next = next; + 800df8a: 687b ldr r3, [r7, #4] + 800df8c: 68ba ldr r2, [r7, #8] + 800df8e: 615a str r2, [r3, #20] + return; + 800df90: e009 b.n 800dfa6 + while (cur->Next != NULL ) + 800df92: 68fb ldr r3, [r7, #12] + 800df94: 695b ldr r3, [r3, #20] + 800df96: 2b00 cmp r3, #0 + 800df98: d1e8 bne.n 800df6c + + } + } + cur->Next = TimerObject; + 800df9a: 68fb ldr r3, [r7, #12] + 800df9c: 687a ldr r2, [r7, #4] + 800df9e: 615a str r2, [r3, #20] + TimerObject->Next = NULL; + 800dfa0: 687b ldr r3, [r7, #4] + 800dfa2: 2200 movs r2, #0 + 800dfa4: 615a str r2, [r3, #20] +} + 800dfa6: 3714 adds r7, #20 + 800dfa8: 46bd mov sp, r7 + 800dfaa: bc80 pop {r7} + 800dfac: 4770 bx lr + 800dfae: bf00 nop + 800dfb0: 20000c04 .word 0x20000c04 + +0800dfb4 : + * + * @remark The list is automatically sorted. The list head always contains the + * next timer to expire. + */ +void TimerInsertNewHeadTimer( UTIL_TIMER_Object_t *TimerObject ) +{ + 800dfb4: b580 push {r7, lr} + 800dfb6: b084 sub sp, #16 + 800dfb8: af00 add r7, sp, #0 + 800dfba: 6078 str r0, [r7, #4] + UTIL_TIMER_Object_t* cur = TimerListHead; + 800dfbc: 4b0b ldr r3, [pc, #44] @ (800dfec ) + 800dfbe: 681b ldr r3, [r3, #0] + 800dfc0: 60fb str r3, [r7, #12] + + if( cur != NULL ) + 800dfc2: 68fb ldr r3, [r7, #12] + 800dfc4: 2b00 cmp r3, #0 + 800dfc6: d002 beq.n 800dfce + { + cur->IsPending = 0; + 800dfc8: 68fb ldr r3, [r7, #12] + 800dfca: 2200 movs r2, #0 + 800dfcc: 721a strb r2, [r3, #8] + } + + TimerObject->Next = cur; + 800dfce: 687b ldr r3, [r7, #4] + 800dfd0: 68fa ldr r2, [r7, #12] + 800dfd2: 615a str r2, [r3, #20] + TimerListHead = TimerObject; + 800dfd4: 4a05 ldr r2, [pc, #20] @ (800dfec ) + 800dfd6: 687b ldr r3, [r7, #4] + 800dfd8: 6013 str r3, [r2, #0] + TimerSetTimeout( TimerListHead ); + 800dfda: 4b04 ldr r3, [pc, #16] @ (800dfec ) + 800dfdc: 681b ldr r3, [r3, #0] + 800dfde: 4618 mov r0, r3 + 800dfe0: f7ff ff8e bl 800df00 +} + 800dfe4: bf00 nop + 800dfe6: 3710 adds r7, #16 + 800dfe8: 46bd mov sp, r7 + 800dfea: bd80 pop {r7, pc} + 800dfec: 20000c04 .word 0x20000c04 + +0800dff0 : + +/** @addtogroup ADV_TRACE_exported_function + * @{ + */ +UTIL_ADV_TRACE_Status_t UTIL_ADV_TRACE_Init(void) +{ + 800dff0: b580 push {r7, lr} + 800dff2: af00 add r7, sp, #0 + /* initialize the Ptr for Read/Write */ + (void)UTIL_ADV_TRACE_MEMSET8(&ADV_TRACE_Ctx, 0x0, sizeof(ADV_TRACE_Context)); + 800dff4: 2218 movs r2, #24 + 800dff6: 2100 movs r1, #0 + 800dff8: 4807 ldr r0, [pc, #28] @ (800e018 ) + 800dffa: f7ff f936 bl 800d26a + (void)UTIL_ADV_TRACE_MEMSET8(&ADV_TRACE_Buffer, 0x0, sizeof(ADV_TRACE_Buffer)); + 800dffe: f44f 7200 mov.w r2, #512 @ 0x200 + 800e002: 2100 movs r1, #0 + 800e004: 4805 ldr r0, [pc, #20] @ (800e01c ) + 800e006: f7ff f930 bl 800d26a +#endif + /* Allocate Lock resource */ + UTIL_ADV_TRACE_INIT_CRITICAL_SECTION(); + + /* Initialize the Low Level interface */ + return UTIL_TraceDriver.Init(TRACE_TxCpltCallback); + 800e00a: 4b05 ldr r3, [pc, #20] @ (800e020 ) + 800e00c: 681b ldr r3, [r3, #0] + 800e00e: 4805 ldr r0, [pc, #20] @ (800e024 ) + 800e010: 4798 blx r3 + 800e012: 4603 mov r3, r0 +} + 800e014: 4618 mov r0, r3 + 800e016: bd80 pop {r7, pc} + 800e018: 20000c08 .word 0x20000c08 + 800e01c: 20000c20 .word 0x20000c20 + 800e020: 0800fb44 .word 0x0800fb44 + 800e024: 0800e26d .word 0x0800e26d + +0800e028 : + return UTIL_TraceDriver.StartRx(UserCallback); +} + +#if defined(UTIL_ADV_TRACE_CONDITIONNAL) +UTIL_ADV_TRACE_Status_t UTIL_ADV_TRACE_COND_FSend(uint32_t VerboseLevel, uint32_t Region, uint32_t TimeStampState, const char *strFormat, ...) +{ + 800e028: b408 push {r3} + 800e02a: b580 push {r7, lr} + 800e02c: b08d sub sp, #52 @ 0x34 + 800e02e: af00 add r7, sp, #0 + 800e030: 60f8 str r0, [r7, #12] + 800e032: 60b9 str r1, [r7, #8] + 800e034: 607a str r2, [r7, #4] + va_list vaArgs; +#if defined(UTIL_ADV_TRACE_UNCHUNK_MODE) + uint8_t buf[UTIL_ADV_TRACE_TMP_MAX_TIMESTMAP_SIZE]; + uint16_t timestamp_size = 0u; + 800e036: 2300 movs r3, #0 + 800e038: 82fb strh r3, [r7, #22] + uint16_t writepos; + uint16_t idx; +#else + uint8_t buf[UTIL_ADV_TRACE_TMP_BUF_SIZE+UTIL_ADV_TRACE_TMP_MAX_TIMESTMAP_SIZE]; +#endif + uint16_t buff_size = 0u; + 800e03a: 2300 movs r3, #0 + 800e03c: 85bb strh r3, [r7, #44] @ 0x2c + + /* check verbose level */ + if(!(ADV_TRACE_Ctx.CurrentVerboseLevel >= VerboseLevel)) + 800e03e: 4b37 ldr r3, [pc, #220] @ (800e11c ) + 800e040: 7a1b ldrb r3, [r3, #8] + 800e042: 461a mov r2, r3 + 800e044: 68fb ldr r3, [r7, #12] + 800e046: 4293 cmp r3, r2 + 800e048: d902 bls.n 800e050 + { + return UTIL_ADV_TRACE_GIVEUP; + 800e04a: f06f 0304 mvn.w r3, #4 + 800e04e: e05e b.n 800e10e + } + + if((Region & ADV_TRACE_Ctx.RegionMask) != Region) + 800e050: 4b32 ldr r3, [pc, #200] @ (800e11c ) + 800e052: 68da ldr r2, [r3, #12] + 800e054: 68bb ldr r3, [r7, #8] + 800e056: 4013 ands r3, r2 + 800e058: 68ba ldr r2, [r7, #8] + 800e05a: 429a cmp r2, r3 + 800e05c: d002 beq.n 800e064 + { + return UTIL_ADV_TRACE_REGIONMASKED; + 800e05e: f06f 0305 mvn.w r3, #5 + 800e062: e054 b.n 800e10e + } + +#if defined(UTIL_ADV_TRACE_UNCHUNK_MODE) + if((ADV_TRACE_Ctx.timestamp_func != NULL) && (TimeStampState != 0u)) + 800e064: 4b2d ldr r3, [pc, #180] @ (800e11c ) + 800e066: 685b ldr r3, [r3, #4] + 800e068: 2b00 cmp r3, #0 + 800e06a: d00a beq.n 800e082 + 800e06c: 687b ldr r3, [r7, #4] + 800e06e: 2b00 cmp r3, #0 + 800e070: d007 beq.n 800e082 + { + ADV_TRACE_Ctx.timestamp_func(buf,×tamp_size); + 800e072: 4b2a ldr r3, [pc, #168] @ (800e11c ) + 800e074: 685b ldr r3, [r3, #4] + 800e076: f107 0116 add.w r1, r7, #22 + 800e07a: f107 0218 add.w r2, r7, #24 + 800e07e: 4610 mov r0, r2 + 800e080: 4798 blx r3 + } + + va_start( vaArgs, strFormat); + 800e082: f107 0340 add.w r3, r7, #64 @ 0x40 + 800e086: 62bb str r3, [r7, #40] @ 0x28 + buff_size =(uint16_t)UTIL_ADV_TRACE_VSNPRINTF((char *)sztmp,UTIL_ADV_TRACE_TMP_BUF_SIZE, strFormat, vaArgs); + 800e088: 6abb ldr r3, [r7, #40] @ 0x28 + 800e08a: 6bfa ldr r2, [r7, #60] @ 0x3c + 800e08c: f44f 7180 mov.w r1, #256 @ 0x100 + 800e090: 4823 ldr r0, [pc, #140] @ (800e120 ) + 800e092: f7ff fa8b bl 800d5ac + 800e096: 4603 mov r3, r0 + 800e098: 85bb strh r3, [r7, #44] @ 0x2c + + TRACE_Lock(); + 800e09a: f000 f9f1 bl 800e480 + + /* if allocation is ok, write data into the buffer */ + if (TRACE_AllocateBufer((buff_size+timestamp_size),&writepos) != -1) + 800e09e: 8afa ldrh r2, [r7, #22] + 800e0a0: 8dbb ldrh r3, [r7, #44] @ 0x2c + 800e0a2: 4413 add r3, r2 + 800e0a4: b29b uxth r3, r3 + 800e0a6: f107 0214 add.w r2, r7, #20 + 800e0aa: 4611 mov r1, r2 + 800e0ac: 4618 mov r0, r3 + 800e0ae: f000 f969 bl 800e384 + 800e0b2: 4603 mov r3, r0 + 800e0b4: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff + 800e0b8: d025 beq.n 800e106 + } + UTIL_ADV_TRACE_EXIT_CRITICAL_SECTION(); +#endif + + /* copy the timestamp */ + for (idx = 0u; idx < timestamp_size; idx++) + 800e0ba: 2300 movs r3, #0 + 800e0bc: 85fb strh r3, [r7, #46] @ 0x2e + 800e0be: e00e b.n 800e0de + { + ADV_TRACE_Buffer[writepos] = buf[idx]; + 800e0c0: 8dfb ldrh r3, [r7, #46] @ 0x2e + 800e0c2: 8aba ldrh r2, [r7, #20] + 800e0c4: 3330 adds r3, #48 @ 0x30 + 800e0c6: 443b add r3, r7 + 800e0c8: f813 1c18 ldrb.w r1, [r3, #-24] + 800e0cc: 4b15 ldr r3, [pc, #84] @ (800e124 ) + 800e0ce: 5499 strb r1, [r3, r2] + writepos = writepos + 1u; + 800e0d0: 8abb ldrh r3, [r7, #20] + 800e0d2: 3301 adds r3, #1 + 800e0d4: b29b uxth r3, r3 + 800e0d6: 82bb strh r3, [r7, #20] + for (idx = 0u; idx < timestamp_size; idx++) + 800e0d8: 8dfb ldrh r3, [r7, #46] @ 0x2e + 800e0da: 3301 adds r3, #1 + 800e0dc: 85fb strh r3, [r7, #46] @ 0x2e + 800e0de: 8afb ldrh r3, [r7, #22] + 800e0e0: 8dfa ldrh r2, [r7, #46] @ 0x2e + 800e0e2: 429a cmp r2, r3 + 800e0e4: d3ec bcc.n 800e0c0 + } + + /* copy the data */ + (void)UTIL_ADV_TRACE_VSNPRINTF((char *)(&ADV_TRACE_Buffer[writepos]), UTIL_ADV_TRACE_TMP_BUF_SIZE, strFormat, vaArgs); + 800e0e6: 8abb ldrh r3, [r7, #20] + 800e0e8: 461a mov r2, r3 + 800e0ea: 4b0e ldr r3, [pc, #56] @ (800e124 ) + 800e0ec: 18d0 adds r0, r2, r3 + 800e0ee: 6abb ldr r3, [r7, #40] @ 0x28 + 800e0f0: 6bfa ldr r2, [r7, #60] @ 0x3c + 800e0f2: f44f 7180 mov.w r1, #256 @ 0x100 + 800e0f6: f7ff fa59 bl 800d5ac + va_end(vaArgs); + + TRACE_UnLock(); + 800e0fa: f000 f9df bl 800e4bc + + return TRACE_Send(); + 800e0fe: f000 f831 bl 800e164 + 800e102: 4603 mov r3, r0 + 800e104: e003 b.n 800e10e + } + + va_end(vaArgs); + TRACE_UnLock(); + 800e106: f000 f9d9 bl 800e4bc + ADV_TRACE_Ctx.OverRunStatus = TRACE_OVERRUN_INDICATION; + } + UTIL_ADV_TRACE_EXIT_CRITICAL_SECTION(); +#endif + + return UTIL_ADV_TRACE_MEM_FULL; + 800e10a: f06f 0302 mvn.w r3, #2 + buff_size += (uint16_t) UTIL_ADV_TRACE_VSNPRINTF((char* )(buf + buff_size), UTIL_ADV_TRACE_TMP_BUF_SIZE, strFormat, vaArgs); + va_end(vaArgs); + + return UTIL_ADV_TRACE_Send(buf, buff_size); +#endif +} + 800e10e: 4618 mov r0, r3 + 800e110: 3734 adds r7, #52 @ 0x34 + 800e112: 46bd mov sp, r7 + 800e114: e8bd 4080 ldmia.w sp!, {r7, lr} + 800e118: b001 add sp, #4 + 800e11a: 4770 bx lr + 800e11c: 20000c08 .word 0x20000c08 + 800e120: 20000e20 .word 0x20000e20 + 800e124: 20000c20 .word 0x20000c20 + +0800e128 : +} +#endif + +#if defined(UTIL_ADV_TRACE_CONDITIONNAL) +void UTIL_ADV_TRACE_RegisterTimeStampFunction(cb_timestamp *cb) +{ + 800e128: b480 push {r7} + 800e12a: b083 sub sp, #12 + 800e12c: af00 add r7, sp, #0 + 800e12e: 6078 str r0, [r7, #4] + ADV_TRACE_Ctx.timestamp_func = *cb; + 800e130: 4a03 ldr r2, [pc, #12] @ (800e140 ) + 800e132: 687b ldr r3, [r7, #4] + 800e134: 6053 str r3, [r2, #4] +} + 800e136: bf00 nop + 800e138: 370c adds r7, #12 + 800e13a: 46bd mov sp, r7 + 800e13c: bc80 pop {r7} + 800e13e: 4770 bx lr + 800e140: 20000c08 .word 0x20000c08 + +0800e144 : + +void UTIL_ADV_TRACE_SetVerboseLevel(uint8_t Level) +{ + 800e144: b480 push {r7} + 800e146: b083 sub sp, #12 + 800e148: af00 add r7, sp, #0 + 800e14a: 4603 mov r3, r0 + 800e14c: 71fb strb r3, [r7, #7] + ADV_TRACE_Ctx.CurrentVerboseLevel = Level; + 800e14e: 4a04 ldr r2, [pc, #16] @ (800e160 ) + 800e150: 79fb ldrb r3, [r7, #7] + 800e152: 7213 strb r3, [r2, #8] +} + 800e154: bf00 nop + 800e156: 370c adds r7, #12 + 800e158: 46bd mov sp, r7 + 800e15a: bc80 pop {r7} + 800e15c: 4770 bx lr + 800e15e: bf00 nop + 800e160: 20000c08 .word 0x20000c08 + +0800e164 : +/** + * @brief send the data of the trace to low layer + * @retval Status based on @ref UTIL_ADV_TRACE_Status_t + */ +static UTIL_ADV_TRACE_Status_t TRACE_Send(void) +{ + 800e164: b580 push {r7, lr} + 800e166: b088 sub sp, #32 + 800e168: af00 add r7, sp, #0 + UTIL_ADV_TRACE_Status_t ret = UTIL_ADV_TRACE_OK; + 800e16a: 2300 movs r3, #0 + 800e16c: 77fb strb r3, [r7, #31] + uint8_t *ptr = NULL; + 800e16e: 2300 movs r3, #0 + 800e170: 61bb str r3, [r7, #24] + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 800e172: f3ef 8310 mrs r3, PRIMASK + 800e176: 613b str r3, [r7, #16] + return(result); + 800e178: 693b ldr r3, [r7, #16] + + UTIL_ADV_TRACE_ENTER_CRITICAL_SECTION(); + 800e17a: 617b str r3, [r7, #20] + __ASM volatile ("cpsid i" : : : "memory"); + 800e17c: b672 cpsid i +} + 800e17e: bf00 nop + + if(TRACE_IsLocked() == 0u) + 800e180: f000 f9ba bl 800e4f8 + 800e184: 4603 mov r3, r0 + 800e186: 2b00 cmp r3, #0 + 800e188: d15d bne.n 800e246 + { + TRACE_Lock(); + 800e18a: f000 f979 bl 800e480 + + if(ADV_TRACE_Ctx.TraceRdPtr != ADV_TRACE_Ctx.TraceWrPtr) + 800e18e: 4b34 ldr r3, [pc, #208] @ (800e260 ) + 800e190: 8a1a ldrh r2, [r3, #16] + 800e192: 4b33 ldr r3, [pc, #204] @ (800e260 ) + 800e194: 8a5b ldrh r3, [r3, #18] + 800e196: 429a cmp r2, r3 + 800e198: d04d beq.n 800e236 + { +#ifdef UTIL_ADV_TRACE_UNCHUNK_MODE + if(TRACE_UNCHUNK_DETECTED == ADV_TRACE_Ctx.unchunk_status) + 800e19a: 4b31 ldr r3, [pc, #196] @ (800e260 ) + 800e19c: 789b ldrb r3, [r3, #2] + 800e19e: 2b01 cmp r3, #1 + 800e1a0: d117 bne.n 800e1d2 + { + ADV_TRACE_Ctx.TraceSentSize = (uint16_t) (ADV_TRACE_Ctx.unchunk_enabled - ADV_TRACE_Ctx.TraceRdPtr); + 800e1a2: 4b2f ldr r3, [pc, #188] @ (800e260 ) + 800e1a4: 881a ldrh r2, [r3, #0] + 800e1a6: 4b2e ldr r3, [pc, #184] @ (800e260 ) + 800e1a8: 8a1b ldrh r3, [r3, #16] + 800e1aa: 1ad3 subs r3, r2, r3 + 800e1ac: b29a uxth r2, r3 + 800e1ae: 4b2c ldr r3, [pc, #176] @ (800e260 ) + 800e1b0: 829a strh r2, [r3, #20] + ADV_TRACE_Ctx.unchunk_status = TRACE_UNCHUNK_TRANSFER; + 800e1b2: 4b2b ldr r3, [pc, #172] @ (800e260 ) + 800e1b4: 2202 movs r2, #2 + 800e1b6: 709a strb r2, [r3, #2] + ADV_TRACE_Ctx.unchunk_enabled = 0; + 800e1b8: 4b29 ldr r3, [pc, #164] @ (800e260 ) + 800e1ba: 2200 movs r2, #0 + 800e1bc: 801a strh r2, [r3, #0] + + UTIL_ADV_TRACE_DEBUG("\nTRACE_TxCpltCallback::unchunk start(%d,%d)\n", ADV_TRACE_Ctx.unchunk_enabled, ADV_TRACE_Ctx.TraceRdPtr); + + if(0u == ADV_TRACE_Ctx.TraceSentSize) + 800e1be: 4b28 ldr r3, [pc, #160] @ (800e260 ) + 800e1c0: 8a9b ldrh r3, [r3, #20] + 800e1c2: 2b00 cmp r3, #0 + 800e1c4: d105 bne.n 800e1d2 + { + ADV_TRACE_Ctx.unchunk_status = TRACE_UNCHUNK_NONE; + 800e1c6: 4b26 ldr r3, [pc, #152] @ (800e260 ) + 800e1c8: 2200 movs r2, #0 + 800e1ca: 709a strb r2, [r3, #2] + ADV_TRACE_Ctx.TraceRdPtr = 0; + 800e1cc: 4b24 ldr r3, [pc, #144] @ (800e260 ) + 800e1ce: 2200 movs r2, #0 + 800e1d0: 821a strh r2, [r3, #16] + } + } + + if(TRACE_UNCHUNK_NONE == ADV_TRACE_Ctx.unchunk_status) + 800e1d2: 4b23 ldr r3, [pc, #140] @ (800e260 ) + 800e1d4: 789b ldrb r3, [r3, #2] + 800e1d6: 2b00 cmp r3, #0 + 800e1d8: d115 bne.n 800e206 + { +#endif + if(ADV_TRACE_Ctx.TraceWrPtr > ADV_TRACE_Ctx.TraceRdPtr) + 800e1da: 4b21 ldr r3, [pc, #132] @ (800e260 ) + 800e1dc: 8a5a ldrh r2, [r3, #18] + 800e1de: 4b20 ldr r3, [pc, #128] @ (800e260 ) + 800e1e0: 8a1b ldrh r3, [r3, #16] + 800e1e2: 429a cmp r2, r3 + 800e1e4: d908 bls.n 800e1f8 + { + ADV_TRACE_Ctx.TraceSentSize = ADV_TRACE_Ctx.TraceWrPtr - ADV_TRACE_Ctx.TraceRdPtr; + 800e1e6: 4b1e ldr r3, [pc, #120] @ (800e260 ) + 800e1e8: 8a5a ldrh r2, [r3, #18] + 800e1ea: 4b1d ldr r3, [pc, #116] @ (800e260 ) + 800e1ec: 8a1b ldrh r3, [r3, #16] + 800e1ee: 1ad3 subs r3, r2, r3 + 800e1f0: b29a uxth r2, r3 + 800e1f2: 4b1b ldr r3, [pc, #108] @ (800e260 ) + 800e1f4: 829a strh r2, [r3, #20] + 800e1f6: e006 b.n 800e206 + } + else /* TraceRdPtr > TraceWrPtr */ + { + ADV_TRACE_Ctx.TraceSentSize = UTIL_ADV_TRACE_FIFO_SIZE - ADV_TRACE_Ctx.TraceRdPtr; + 800e1f8: 4b19 ldr r3, [pc, #100] @ (800e260 ) + 800e1fa: 8a1b ldrh r3, [r3, #16] + 800e1fc: f5c3 7300 rsb r3, r3, #512 @ 0x200 + 800e200: b29a uxth r2, r3 + 800e202: 4b17 ldr r3, [pc, #92] @ (800e260 ) + 800e204: 829a strh r2, [r3, #20] + + } +#ifdef UTIL_ADV_TRACE_UNCHUNK_MODE + } +#endif + ptr = &ADV_TRACE_Buffer[ADV_TRACE_Ctx.TraceRdPtr]; + 800e206: 4b16 ldr r3, [pc, #88] @ (800e260 ) + 800e208: 8a1b ldrh r3, [r3, #16] + 800e20a: 461a mov r2, r3 + 800e20c: 4b15 ldr r3, [pc, #84] @ (800e264 ) + 800e20e: 4413 add r3, r2 + 800e210: 61bb str r3, [r7, #24] + 800e212: 697b ldr r3, [r7, #20] + 800e214: 60fb str r3, [r7, #12] + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 800e216: 68fb ldr r3, [r7, #12] + 800e218: f383 8810 msr PRIMASK, r3 +} + 800e21c: bf00 nop + + UTIL_ADV_TRACE_EXIT_CRITICAL_SECTION(); + UTIL_ADV_TRACE_PreSendHook(); + 800e21e: f7f2 fce3 bl 8000be8 + + UTIL_ADV_TRACE_DEBUG("\n--TRACE_Send(%d-%d)--\n", ADV_TRACE_Ctx.TraceRdPtr, ADV_TRACE_Ctx.TraceSentSize); + ret = UTIL_TraceDriver.Send(ptr, ADV_TRACE_Ctx.TraceSentSize); + 800e222: 4b11 ldr r3, [pc, #68] @ (800e268 ) + 800e224: 68db ldr r3, [r3, #12] + 800e226: 4a0e ldr r2, [pc, #56] @ (800e260 ) + 800e228: 8a92 ldrh r2, [r2, #20] + 800e22a: 4611 mov r1, r2 + 800e22c: 69b8 ldr r0, [r7, #24] + 800e22e: 4798 blx r3 + 800e230: 4603 mov r3, r0 + 800e232: 77fb strb r3, [r7, #31] + 800e234: e00d b.n 800e252 + } + else + { + TRACE_UnLock(); + 800e236: f000 f941 bl 800e4bc + 800e23a: 697b ldr r3, [r7, #20] + 800e23c: 60bb str r3, [r7, #8] + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 800e23e: 68bb ldr r3, [r7, #8] + 800e240: f383 8810 msr PRIMASK, r3 +} + 800e244: e005 b.n 800e252 + 800e246: 697b ldr r3, [r7, #20] + 800e248: 607b str r3, [r7, #4] + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 800e24a: 687b ldr r3, [r7, #4] + 800e24c: f383 8810 msr PRIMASK, r3 +} + 800e250: bf00 nop + else + { + UTIL_ADV_TRACE_EXIT_CRITICAL_SECTION(); + } + + return ret; + 800e252: f997 301f ldrsb.w r3, [r7, #31] +} + 800e256: 4618 mov r0, r3 + 800e258: 3720 adds r7, #32 + 800e25a: 46bd mov sp, r7 + 800e25c: bd80 pop {r7, pc} + 800e25e: bf00 nop + 800e260: 20000c08 .word 0x20000c08 + 800e264: 20000c20 .word 0x20000c20 + 800e268: 0800fb44 .word 0x0800fb44 + +0800e26c : + * @brief Tx callback called by the low layer level to inform a transfer complete + * @param Ptr pointer not used only for HAL compatibility + * @retval none + */ +static void TRACE_TxCpltCallback(void *Ptr) +{ + 800e26c: b580 push {r7, lr} + 800e26e: b088 sub sp, #32 + 800e270: af00 add r7, sp, #0 + 800e272: 6078 str r0, [r7, #4] + uint8_t *ptr = NULL; + 800e274: 2300 movs r3, #0 + 800e276: 61fb str r3, [r7, #28] + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 800e278: f3ef 8310 mrs r3, PRIMASK + 800e27c: 617b str r3, [r7, #20] + return(result); + 800e27e: 697b ldr r3, [r7, #20] + UTIL_ADV_TRACE_ENTER_CRITICAL_SECTION(); + 800e280: 61bb str r3, [r7, #24] + __ASM volatile ("cpsid i" : : : "memory"); + 800e282: b672 cpsid i +} + 800e284: bf00 nop + ADV_TRACE_Ctx.TraceSentSize = 0u; + } +#endif + +#if defined(UTIL_ADV_TRACE_UNCHUNK_MODE) + if(TRACE_UNCHUNK_TRANSFER == ADV_TRACE_Ctx.unchunk_status) + 800e286: 4b3c ldr r3, [pc, #240] @ (800e378 ) + 800e288: 789b ldrb r3, [r3, #2] + 800e28a: 2b02 cmp r3, #2 + 800e28c: d106 bne.n 800e29c + { + ADV_TRACE_Ctx.unchunk_status = TRACE_UNCHUNK_NONE; + 800e28e: 4b3a ldr r3, [pc, #232] @ (800e378 ) + 800e290: 2200 movs r2, #0 + 800e292: 709a strb r2, [r3, #2] + ADV_TRACE_Ctx.TraceRdPtr = 0; + 800e294: 4b38 ldr r3, [pc, #224] @ (800e378 ) + 800e296: 2200 movs r2, #0 + 800e298: 821a strh r2, [r3, #16] + 800e29a: e00a b.n 800e2b2 + UTIL_ADV_TRACE_DEBUG("\nTRACE_TxCpltCallback::unchunk complete\n"); + } + else + { + ADV_TRACE_Ctx.TraceRdPtr = (ADV_TRACE_Ctx.TraceRdPtr + ADV_TRACE_Ctx.TraceSentSize) % UTIL_ADV_TRACE_FIFO_SIZE; + 800e29c: 4b36 ldr r3, [pc, #216] @ (800e378 ) + 800e29e: 8a1a ldrh r2, [r3, #16] + 800e2a0: 4b35 ldr r3, [pc, #212] @ (800e378 ) + 800e2a2: 8a9b ldrh r3, [r3, #20] + 800e2a4: 4413 add r3, r2 + 800e2a6: b29b uxth r3, r3 + 800e2a8: f3c3 0308 ubfx r3, r3, #0, #9 + 800e2ac: b29a uxth r2, r3 + 800e2ae: 4b32 ldr r3, [pc, #200] @ (800e378 ) + 800e2b0: 821a strh r2, [r3, #16] + UTIL_TraceDriver.Send(ptr, ADV_TRACE_Ctx.TraceSentSize); + return; + } +#endif + + if((ADV_TRACE_Ctx.TraceRdPtr != ADV_TRACE_Ctx.TraceWrPtr) && (1u == ADV_TRACE_Ctx.TraceLock)) + 800e2b2: 4b31 ldr r3, [pc, #196] @ (800e378 ) + 800e2b4: 8a1a ldrh r2, [r3, #16] + 800e2b6: 4b30 ldr r3, [pc, #192] @ (800e378 ) + 800e2b8: 8a5b ldrh r3, [r3, #18] + 800e2ba: 429a cmp r2, r3 + 800e2bc: d04d beq.n 800e35a + 800e2be: 4b2e ldr r3, [pc, #184] @ (800e378 ) + 800e2c0: 8adb ldrh r3, [r3, #22] + 800e2c2: 2b01 cmp r3, #1 + 800e2c4: d149 bne.n 800e35a + { +#ifdef UTIL_ADV_TRACE_UNCHUNK_MODE + if(TRACE_UNCHUNK_DETECTED == ADV_TRACE_Ctx.unchunk_status) + 800e2c6: 4b2c ldr r3, [pc, #176] @ (800e378 ) + 800e2c8: 789b ldrb r3, [r3, #2] + 800e2ca: 2b01 cmp r3, #1 + 800e2cc: d117 bne.n 800e2fe + { + ADV_TRACE_Ctx.TraceSentSize = ADV_TRACE_Ctx.unchunk_enabled - ADV_TRACE_Ctx.TraceRdPtr; + 800e2ce: 4b2a ldr r3, [pc, #168] @ (800e378 ) + 800e2d0: 881a ldrh r2, [r3, #0] + 800e2d2: 4b29 ldr r3, [pc, #164] @ (800e378 ) + 800e2d4: 8a1b ldrh r3, [r3, #16] + 800e2d6: 1ad3 subs r3, r2, r3 + 800e2d8: b29a uxth r2, r3 + 800e2da: 4b27 ldr r3, [pc, #156] @ (800e378 ) + 800e2dc: 829a strh r2, [r3, #20] + ADV_TRACE_Ctx.unchunk_status = TRACE_UNCHUNK_TRANSFER; + 800e2de: 4b26 ldr r3, [pc, #152] @ (800e378 ) + 800e2e0: 2202 movs r2, #2 + 800e2e2: 709a strb r2, [r3, #2] + ADV_TRACE_Ctx.unchunk_enabled = 0; + 800e2e4: 4b24 ldr r3, [pc, #144] @ (800e378 ) + 800e2e6: 2200 movs r2, #0 + 800e2e8: 801a strh r2, [r3, #0] + + UTIL_ADV_TRACE_DEBUG("\nTRACE_TxCpltCallback::unchunk start(%d,%d)\n", ADV_TRACE_Ctx.unchunk_enabled, ADV_TRACE_Ctx.TraceRdPtr); + + if(0u == ADV_TRACE_Ctx.TraceSentSize) + 800e2ea: 4b23 ldr r3, [pc, #140] @ (800e378 ) + 800e2ec: 8a9b ldrh r3, [r3, #20] + 800e2ee: 2b00 cmp r3, #0 + 800e2f0: d105 bne.n 800e2fe + { + /* this case occurs when an ongoing write aligned the Rd position with chunk position */ + /* in that case the unchunk is forgot */ + ADV_TRACE_Ctx.unchunk_status = TRACE_UNCHUNK_NONE; + 800e2f2: 4b21 ldr r3, [pc, #132] @ (800e378 ) + 800e2f4: 2200 movs r2, #0 + 800e2f6: 709a strb r2, [r3, #2] + ADV_TRACE_Ctx.TraceRdPtr = 0; + 800e2f8: 4b1f ldr r3, [pc, #124] @ (800e378 ) + 800e2fa: 2200 movs r2, #0 + 800e2fc: 821a strh r2, [r3, #16] + } + } + + if(TRACE_UNCHUNK_NONE == ADV_TRACE_Ctx.unchunk_status) + 800e2fe: 4b1e ldr r3, [pc, #120] @ (800e378 ) + 800e300: 789b ldrb r3, [r3, #2] + 800e302: 2b00 cmp r3, #0 + 800e304: d115 bne.n 800e332 + { +#endif + if(ADV_TRACE_Ctx.TraceWrPtr > ADV_TRACE_Ctx.TraceRdPtr) + 800e306: 4b1c ldr r3, [pc, #112] @ (800e378 ) + 800e308: 8a5a ldrh r2, [r3, #18] + 800e30a: 4b1b ldr r3, [pc, #108] @ (800e378 ) + 800e30c: 8a1b ldrh r3, [r3, #16] + 800e30e: 429a cmp r2, r3 + 800e310: d908 bls.n 800e324 + { + ADV_TRACE_Ctx.TraceSentSize = ADV_TRACE_Ctx.TraceWrPtr - ADV_TRACE_Ctx.TraceRdPtr; + 800e312: 4b19 ldr r3, [pc, #100] @ (800e378 ) + 800e314: 8a5a ldrh r2, [r3, #18] + 800e316: 4b18 ldr r3, [pc, #96] @ (800e378 ) + 800e318: 8a1b ldrh r3, [r3, #16] + 800e31a: 1ad3 subs r3, r2, r3 + 800e31c: b29a uxth r2, r3 + 800e31e: 4b16 ldr r3, [pc, #88] @ (800e378 ) + 800e320: 829a strh r2, [r3, #20] + 800e322: e006 b.n 800e332 + } + else /* TraceRdPtr > TraceWrPtr */ + { + ADV_TRACE_Ctx.TraceSentSize = UTIL_ADV_TRACE_FIFO_SIZE - ADV_TRACE_Ctx.TraceRdPtr; + 800e324: 4b14 ldr r3, [pc, #80] @ (800e378 ) + 800e326: 8a1b ldrh r3, [r3, #16] + 800e328: f5c3 7300 rsb r3, r3, #512 @ 0x200 + 800e32c: b29a uxth r2, r3 + 800e32e: 4b12 ldr r3, [pc, #72] @ (800e378 ) + 800e330: 829a strh r2, [r3, #20] + } +#ifdef UTIL_ADV_TRACE_UNCHUNK_MODE + } +#endif + ptr = &ADV_TRACE_Buffer[ADV_TRACE_Ctx.TraceRdPtr]; + 800e332: 4b11 ldr r3, [pc, #68] @ (800e378 ) + 800e334: 8a1b ldrh r3, [r3, #16] + 800e336: 461a mov r2, r3 + 800e338: 4b10 ldr r3, [pc, #64] @ (800e37c ) + 800e33a: 4413 add r3, r2 + 800e33c: 61fb str r3, [r7, #28] + 800e33e: 69bb ldr r3, [r7, #24] + 800e340: 613b str r3, [r7, #16] + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 800e342: 693b ldr r3, [r7, #16] + 800e344: f383 8810 msr PRIMASK, r3 +} + 800e348: bf00 nop + UTIL_ADV_TRACE_EXIT_CRITICAL_SECTION(); + UTIL_ADV_TRACE_DEBUG("\n--TRACE_Send(%d-%d)--\n", ADV_TRACE_Ctx.TraceRdPtr, ADV_TRACE_Ctx.TraceSentSize); + UTIL_TraceDriver.Send(ptr, ADV_TRACE_Ctx.TraceSentSize); + 800e34a: 4b0d ldr r3, [pc, #52] @ (800e380 ) + 800e34c: 68db ldr r3, [r3, #12] + 800e34e: 4a0a ldr r2, [pc, #40] @ (800e378 ) + 800e350: 8a92 ldrh r2, [r2, #20] + 800e352: 4611 mov r1, r2 + 800e354: 69f8 ldr r0, [r7, #28] + 800e356: 4798 blx r3 + 800e358: e00a b.n 800e370 + 800e35a: 69bb ldr r3, [r7, #24] + 800e35c: 60fb str r3, [r7, #12] + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 800e35e: 68fb ldr r3, [r7, #12] + 800e360: f383 8810 msr PRIMASK, r3 +} + 800e364: bf00 nop + } + else + { + UTIL_ADV_TRACE_EXIT_CRITICAL_SECTION(); + UTIL_ADV_TRACE_PostSendHook(); + 800e366: f7f2 fc47 bl 8000bf8 + TRACE_UnLock(); + 800e36a: f000 f8a7 bl 800e4bc + } +} + 800e36e: bf00 nop + 800e370: bf00 nop + 800e372: 3720 adds r7, #32 + 800e374: 46bd mov sp, r7 + 800e376: bd80 pop {r7, pc} + 800e378: 20000c08 .word 0x20000c08 + 800e37c: 20000c20 .word 0x20000c20 + 800e380: 0800fb44 .word 0x0800fb44 + +0800e384 : + * @param Size to allocate within fifo + * @param Pos position within the fifo + * @retval write position inside the buffer is -1 no space available. + */ +static int16_t TRACE_AllocateBufer(uint16_t Size, uint16_t *Pos) +{ + 800e384: b480 push {r7} + 800e386: b087 sub sp, #28 + 800e388: af00 add r7, sp, #0 + 800e38a: 4603 mov r3, r0 + 800e38c: 6039 str r1, [r7, #0] + 800e38e: 80fb strh r3, [r7, #6] + uint16_t freesize; + int16_t ret = -1; + 800e390: f64f 73ff movw r3, #65535 @ 0xffff + 800e394: 82bb strh r3, [r7, #20] + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 800e396: f3ef 8310 mrs r3, PRIMASK + 800e39a: 60fb str r3, [r7, #12] + return(result); + 800e39c: 68fb ldr r3, [r7, #12] + + UTIL_ADV_TRACE_ENTER_CRITICAL_SECTION(); + 800e39e: 613b str r3, [r7, #16] + __ASM volatile ("cpsid i" : : : "memory"); + 800e3a0: b672 cpsid i +} + 800e3a2: bf00 nop + + if(ADV_TRACE_Ctx.TraceWrPtr == ADV_TRACE_Ctx.TraceRdPtr) + 800e3a4: 4b35 ldr r3, [pc, #212] @ (800e47c ) + 800e3a6: 8a5a ldrh r2, [r3, #18] + 800e3a8: 4b34 ldr r3, [pc, #208] @ (800e47c ) + 800e3aa: 8a1b ldrh r3, [r3, #16] + 800e3ac: 429a cmp r2, r3 + 800e3ae: d11b bne.n 800e3e8 + { +#ifdef UTIL_ADV_TRACE_UNCHUNK_MODE + freesize = (uint16_t)(UTIL_ADV_TRACE_FIFO_SIZE - ADV_TRACE_Ctx.TraceWrPtr); + 800e3b0: 4b32 ldr r3, [pc, #200] @ (800e47c ) + 800e3b2: 8a5b ldrh r3, [r3, #18] + 800e3b4: f5c3 7300 rsb r3, r3, #512 @ 0x200 + 800e3b8: 82fb strh r3, [r7, #22] + if((Size >= freesize) && (ADV_TRACE_Ctx.TraceRdPtr > Size)) + 800e3ba: 88fa ldrh r2, [r7, #6] + 800e3bc: 8afb ldrh r3, [r7, #22] + 800e3be: 429a cmp r2, r3 + 800e3c0: d33a bcc.n 800e438 + 800e3c2: 4b2e ldr r3, [pc, #184] @ (800e47c ) + 800e3c4: 8a1b ldrh r3, [r3, #16] + 800e3c6: 88fa ldrh r2, [r7, #6] + 800e3c8: 429a cmp r2, r3 + 800e3ca: d235 bcs.n 800e438 + { + ADV_TRACE_Ctx.unchunk_status = TRACE_UNCHUNK_DETECTED; + 800e3cc: 4b2b ldr r3, [pc, #172] @ (800e47c ) + 800e3ce: 2201 movs r2, #1 + 800e3d0: 709a strb r2, [r3, #2] + ADV_TRACE_Ctx.unchunk_enabled = ADV_TRACE_Ctx.TraceWrPtr; + 800e3d2: 4b2a ldr r3, [pc, #168] @ (800e47c ) + 800e3d4: 8a5a ldrh r2, [r3, #18] + 800e3d6: 4b29 ldr r3, [pc, #164] @ (800e47c ) + 800e3d8: 801a strh r2, [r3, #0] + freesize = ADV_TRACE_Ctx.TraceRdPtr; + 800e3da: 4b28 ldr r3, [pc, #160] @ (800e47c ) + 800e3dc: 8a1b ldrh r3, [r3, #16] + 800e3de: 82fb strh r3, [r7, #22] + ADV_TRACE_Ctx.TraceWrPtr = 0; + 800e3e0: 4b26 ldr r3, [pc, #152] @ (800e47c ) + 800e3e2: 2200 movs r2, #0 + 800e3e4: 825a strh r2, [r3, #18] + 800e3e6: e027 b.n 800e438 +#endif + } + else + { +#ifdef UTIL_ADV_TRACE_UNCHUNK_MODE + if (ADV_TRACE_Ctx.TraceWrPtr > ADV_TRACE_Ctx.TraceRdPtr) + 800e3e8: 4b24 ldr r3, [pc, #144] @ (800e47c ) + 800e3ea: 8a5a ldrh r2, [r3, #18] + 800e3ec: 4b23 ldr r3, [pc, #140] @ (800e47c ) + 800e3ee: 8a1b ldrh r3, [r3, #16] + 800e3f0: 429a cmp r2, r3 + 800e3f2: d91b bls.n 800e42c + { + freesize = (uint16_t)(UTIL_ADV_TRACE_FIFO_SIZE - ADV_TRACE_Ctx.TraceWrPtr); + 800e3f4: 4b21 ldr r3, [pc, #132] @ (800e47c ) + 800e3f6: 8a5b ldrh r3, [r3, #18] + 800e3f8: f5c3 7300 rsb r3, r3, #512 @ 0x200 + 800e3fc: 82fb strh r3, [r7, #22] + if((Size >= freesize) && (ADV_TRACE_Ctx.TraceRdPtr > Size)) + 800e3fe: 88fa ldrh r2, [r7, #6] + 800e400: 8afb ldrh r3, [r7, #22] + 800e402: 429a cmp r2, r3 + 800e404: d318 bcc.n 800e438 + 800e406: 4b1d ldr r3, [pc, #116] @ (800e47c ) + 800e408: 8a1b ldrh r3, [r3, #16] + 800e40a: 88fa ldrh r2, [r7, #6] + 800e40c: 429a cmp r2, r3 + 800e40e: d213 bcs.n 800e438 + { + ADV_TRACE_Ctx.unchunk_status = TRACE_UNCHUNK_DETECTED; + 800e410: 4b1a ldr r3, [pc, #104] @ (800e47c ) + 800e412: 2201 movs r2, #1 + 800e414: 709a strb r2, [r3, #2] + ADV_TRACE_Ctx.unchunk_enabled = ADV_TRACE_Ctx.TraceWrPtr; + 800e416: 4b19 ldr r3, [pc, #100] @ (800e47c ) + 800e418: 8a5a ldrh r2, [r3, #18] + 800e41a: 4b18 ldr r3, [pc, #96] @ (800e47c ) + 800e41c: 801a strh r2, [r3, #0] + freesize = ADV_TRACE_Ctx.TraceRdPtr; + 800e41e: 4b17 ldr r3, [pc, #92] @ (800e47c ) + 800e420: 8a1b ldrh r3, [r3, #16] + 800e422: 82fb strh r3, [r7, #22] + ADV_TRACE_Ctx.TraceWrPtr = 0; + 800e424: 4b15 ldr r3, [pc, #84] @ (800e47c ) + 800e426: 2200 movs r2, #0 + 800e428: 825a strh r2, [r3, #18] + 800e42a: e005 b.n 800e438 + } + } + else + { + freesize = (uint16_t)(ADV_TRACE_Ctx.TraceRdPtr - ADV_TRACE_Ctx.TraceWrPtr); + 800e42c: 4b13 ldr r3, [pc, #76] @ (800e47c ) + 800e42e: 8a1a ldrh r2, [r3, #16] + 800e430: 4b12 ldr r3, [pc, #72] @ (800e47c ) + 800e432: 8a5b ldrh r3, [r3, #18] + 800e434: 1ad3 subs r3, r2, r3 + 800e436: 82fb strh r3, [r7, #22] + freesize = ADV_TRACE_Ctx.TraceRdPtr - ADV_TRACE_Ctx.TraceWrPtr; + } +#endif + } + + if(freesize > Size) + 800e438: 8afa ldrh r2, [r7, #22] + 800e43a: 88fb ldrh r3, [r7, #6] + 800e43c: 429a cmp r2, r3 + 800e43e: d90f bls.n 800e460 + { + *Pos = ADV_TRACE_Ctx.TraceWrPtr; + 800e440: 4b0e ldr r3, [pc, #56] @ (800e47c ) + 800e442: 8a5a ldrh r2, [r3, #18] + 800e444: 683b ldr r3, [r7, #0] + 800e446: 801a strh r2, [r3, #0] + ADV_TRACE_Ctx.TraceWrPtr = (ADV_TRACE_Ctx.TraceWrPtr + Size) % UTIL_ADV_TRACE_FIFO_SIZE; + 800e448: 4b0c ldr r3, [pc, #48] @ (800e47c ) + 800e44a: 8a5a ldrh r2, [r3, #18] + 800e44c: 88fb ldrh r3, [r7, #6] + 800e44e: 4413 add r3, r2 + 800e450: b29b uxth r3, r3 + 800e452: f3c3 0308 ubfx r3, r3, #0, #9 + 800e456: b29a uxth r2, r3 + 800e458: 4b08 ldr r3, [pc, #32] @ (800e47c ) + 800e45a: 825a strh r2, [r3, #18] + ret = 0; + 800e45c: 2300 movs r3, #0 + 800e45e: 82bb strh r3, [r7, #20] + 800e460: 693b ldr r3, [r7, #16] + 800e462: 60bb str r3, [r7, #8] + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 800e464: 68bb ldr r3, [r7, #8] + 800e466: f383 8810 msr PRIMASK, r3 +} + 800e46a: bf00 nop + } + } +#endif + + UTIL_ADV_TRACE_EXIT_CRITICAL_SECTION(); + return ret; + 800e46c: f9b7 3014 ldrsh.w r3, [r7, #20] +} + 800e470: 4618 mov r0, r3 + 800e472: 371c adds r7, #28 + 800e474: 46bd mov sp, r7 + 800e476: bc80 pop {r7} + 800e478: 4770 bx lr + 800e47a: bf00 nop + 800e47c: 20000c08 .word 0x20000c08 + +0800e480 : +/** + * @brief Lock the trace buffer. + * @retval None. + */ +static void TRACE_Lock(void) +{ + 800e480: b480 push {r7} + 800e482: b085 sub sp, #20 + 800e484: af00 add r7, sp, #0 + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 800e486: f3ef 8310 mrs r3, PRIMASK + 800e48a: 607b str r3, [r7, #4] + return(result); + 800e48c: 687b ldr r3, [r7, #4] + UTIL_ADV_TRACE_ENTER_CRITICAL_SECTION(); + 800e48e: 60fb str r3, [r7, #12] + __ASM volatile ("cpsid i" : : : "memory"); + 800e490: b672 cpsid i +} + 800e492: bf00 nop + ADV_TRACE_Ctx.TraceLock++; + 800e494: 4b08 ldr r3, [pc, #32] @ (800e4b8 ) + 800e496: 8adb ldrh r3, [r3, #22] + 800e498: 3301 adds r3, #1 + 800e49a: b29a uxth r2, r3 + 800e49c: 4b06 ldr r3, [pc, #24] @ (800e4b8 ) + 800e49e: 82da strh r2, [r3, #22] + 800e4a0: 68fb ldr r3, [r7, #12] + 800e4a2: 60bb str r3, [r7, #8] + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 800e4a4: 68bb ldr r3, [r7, #8] + 800e4a6: f383 8810 msr PRIMASK, r3 +} + 800e4aa: bf00 nop + UTIL_ADV_TRACE_EXIT_CRITICAL_SECTION(); +} + 800e4ac: bf00 nop + 800e4ae: 3714 adds r7, #20 + 800e4b0: 46bd mov sp, r7 + 800e4b2: bc80 pop {r7} + 800e4b4: 4770 bx lr + 800e4b6: bf00 nop + 800e4b8: 20000c08 .word 0x20000c08 + +0800e4bc : +/** + * @brief UnLock the trace buffer. + * @retval None. + */ +static void TRACE_UnLock(void) +{ + 800e4bc: b480 push {r7} + 800e4be: b085 sub sp, #20 + 800e4c0: af00 add r7, sp, #0 + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 800e4c2: f3ef 8310 mrs r3, PRIMASK + 800e4c6: 607b str r3, [r7, #4] + return(result); + 800e4c8: 687b ldr r3, [r7, #4] + UTIL_ADV_TRACE_ENTER_CRITICAL_SECTION(); + 800e4ca: 60fb str r3, [r7, #12] + __ASM volatile ("cpsid i" : : : "memory"); + 800e4cc: b672 cpsid i +} + 800e4ce: bf00 nop + ADV_TRACE_Ctx.TraceLock--; + 800e4d0: 4b08 ldr r3, [pc, #32] @ (800e4f4 ) + 800e4d2: 8adb ldrh r3, [r3, #22] + 800e4d4: 3b01 subs r3, #1 + 800e4d6: b29a uxth r2, r3 + 800e4d8: 4b06 ldr r3, [pc, #24] @ (800e4f4 ) + 800e4da: 82da strh r2, [r3, #22] + 800e4dc: 68fb ldr r3, [r7, #12] + 800e4de: 60bb str r3, [r7, #8] + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 800e4e0: 68bb ldr r3, [r7, #8] + 800e4e2: f383 8810 msr PRIMASK, r3 +} + 800e4e6: bf00 nop + UTIL_ADV_TRACE_EXIT_CRITICAL_SECTION(); +} + 800e4e8: bf00 nop + 800e4ea: 3714 adds r7, #20 + 800e4ec: 46bd mov sp, r7 + 800e4ee: bc80 pop {r7} + 800e4f0: 4770 bx lr + 800e4f2: bf00 nop + 800e4f4: 20000c08 .word 0x20000c08 + +0800e4f8 : +/** + * @brief UnLock the trace buffer. + * @retval None. + */ +static uint32_t TRACE_IsLocked(void) +{ + 800e4f8: b480 push {r7} + 800e4fa: af00 add r7, sp, #0 + return (ADV_TRACE_Ctx.TraceLock == 0u? 0u: 1u); + 800e4fc: 4b05 ldr r3, [pc, #20] @ (800e514 ) + 800e4fe: 8adb ldrh r3, [r3, #22] + 800e500: 2b00 cmp r3, #0 + 800e502: bf14 ite ne + 800e504: 2301 movne r3, #1 + 800e506: 2300 moveq r3, #0 + 800e508: b2db uxtb r3, r3 +} + 800e50a: 4618 mov r0, r3 + 800e50c: 46bd mov sp, r7 + 800e50e: bc80 pop {r7} + 800e510: 4770 bx lr + 800e512: bf00 nop + 800e514: 20000c08 .word 0x20000c08 + +0800e518 <_strtol_l.isra.0>: + 800e518: 2b24 cmp r3, #36 @ 0x24 + 800e51a: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} + 800e51e: 4686 mov lr, r0 + 800e520: 4690 mov r8, r2 + 800e522: d801 bhi.n 800e528 <_strtol_l.isra.0+0x10> + 800e524: 2b01 cmp r3, #1 + 800e526: d106 bne.n 800e536 <_strtol_l.isra.0+0x1e> + 800e528: f000 f948 bl 800e7bc <__errno> + 800e52c: 2316 movs r3, #22 + 800e52e: 6003 str r3, [r0, #0] + 800e530: 2000 movs r0, #0 + 800e532: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} + 800e536: 4834 ldr r0, [pc, #208] @ (800e608 <_strtol_l.isra.0+0xf0>) + 800e538: 460d mov r5, r1 + 800e53a: 462a mov r2, r5 + 800e53c: f815 4b01 ldrb.w r4, [r5], #1 + 800e540: 5d06 ldrb r6, [r0, r4] + 800e542: f016 0608 ands.w r6, r6, #8 + 800e546: d1f8 bne.n 800e53a <_strtol_l.isra.0+0x22> + 800e548: 2c2d cmp r4, #45 @ 0x2d + 800e54a: d110 bne.n 800e56e <_strtol_l.isra.0+0x56> + 800e54c: 782c ldrb r4, [r5, #0] + 800e54e: 2601 movs r6, #1 + 800e550: 1c95 adds r5, r2, #2 + 800e552: f033 0210 bics.w r2, r3, #16 + 800e556: d115 bne.n 800e584 <_strtol_l.isra.0+0x6c> + 800e558: 2c30 cmp r4, #48 @ 0x30 + 800e55a: d10d bne.n 800e578 <_strtol_l.isra.0+0x60> + 800e55c: 782a ldrb r2, [r5, #0] + 800e55e: f002 02df and.w r2, r2, #223 @ 0xdf + 800e562: 2a58 cmp r2, #88 @ 0x58 + 800e564: d108 bne.n 800e578 <_strtol_l.isra.0+0x60> + 800e566: 786c ldrb r4, [r5, #1] + 800e568: 3502 adds r5, #2 + 800e56a: 2310 movs r3, #16 + 800e56c: e00a b.n 800e584 <_strtol_l.isra.0+0x6c> + 800e56e: 2c2b cmp r4, #43 @ 0x2b + 800e570: bf04 itt eq + 800e572: 782c ldrbeq r4, [r5, #0] + 800e574: 1c95 addeq r5, r2, #2 + 800e576: e7ec b.n 800e552 <_strtol_l.isra.0+0x3a> + 800e578: 2b00 cmp r3, #0 + 800e57a: d1f6 bne.n 800e56a <_strtol_l.isra.0+0x52> + 800e57c: 2c30 cmp r4, #48 @ 0x30 + 800e57e: bf14 ite ne + 800e580: 230a movne r3, #10 + 800e582: 2308 moveq r3, #8 + 800e584: f106 4c00 add.w ip, r6, #2147483648 @ 0x80000000 + 800e588: f10c 3cff add.w ip, ip, #4294967295 @ 0xffffffff + 800e58c: 2200 movs r2, #0 + 800e58e: fbbc f9f3 udiv r9, ip, r3 + 800e592: 4610 mov r0, r2 + 800e594: fb03 ca19 mls sl, r3, r9, ip + 800e598: f1a4 0730 sub.w r7, r4, #48 @ 0x30 + 800e59c: 2f09 cmp r7, #9 + 800e59e: d80f bhi.n 800e5c0 <_strtol_l.isra.0+0xa8> + 800e5a0: 463c mov r4, r7 + 800e5a2: 42a3 cmp r3, r4 + 800e5a4: dd1b ble.n 800e5de <_strtol_l.isra.0+0xc6> + 800e5a6: 1c57 adds r7, r2, #1 + 800e5a8: d007 beq.n 800e5ba <_strtol_l.isra.0+0xa2> + 800e5aa: 4581 cmp r9, r0 + 800e5ac: d314 bcc.n 800e5d8 <_strtol_l.isra.0+0xc0> + 800e5ae: d101 bne.n 800e5b4 <_strtol_l.isra.0+0x9c> + 800e5b0: 45a2 cmp sl, r4 + 800e5b2: db11 blt.n 800e5d8 <_strtol_l.isra.0+0xc0> + 800e5b4: fb00 4003 mla r0, r0, r3, r4 + 800e5b8: 2201 movs r2, #1 + 800e5ba: f815 4b01 ldrb.w r4, [r5], #1 + 800e5be: e7eb b.n 800e598 <_strtol_l.isra.0+0x80> + 800e5c0: f1a4 0741 sub.w r7, r4, #65 @ 0x41 + 800e5c4: 2f19 cmp r7, #25 + 800e5c6: d801 bhi.n 800e5cc <_strtol_l.isra.0+0xb4> + 800e5c8: 3c37 subs r4, #55 @ 0x37 + 800e5ca: e7ea b.n 800e5a2 <_strtol_l.isra.0+0x8a> + 800e5cc: f1a4 0761 sub.w r7, r4, #97 @ 0x61 + 800e5d0: 2f19 cmp r7, #25 + 800e5d2: d804 bhi.n 800e5de <_strtol_l.isra.0+0xc6> + 800e5d4: 3c57 subs r4, #87 @ 0x57 + 800e5d6: e7e4 b.n 800e5a2 <_strtol_l.isra.0+0x8a> + 800e5d8: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff + 800e5dc: e7ed b.n 800e5ba <_strtol_l.isra.0+0xa2> + 800e5de: 1c53 adds r3, r2, #1 + 800e5e0: d108 bne.n 800e5f4 <_strtol_l.isra.0+0xdc> + 800e5e2: 2322 movs r3, #34 @ 0x22 + 800e5e4: f8ce 3000 str.w r3, [lr] + 800e5e8: 4660 mov r0, ip + 800e5ea: f1b8 0f00 cmp.w r8, #0 + 800e5ee: d0a0 beq.n 800e532 <_strtol_l.isra.0+0x1a> + 800e5f0: 1e69 subs r1, r5, #1 + 800e5f2: e006 b.n 800e602 <_strtol_l.isra.0+0xea> + 800e5f4: b106 cbz r6, 800e5f8 <_strtol_l.isra.0+0xe0> + 800e5f6: 4240 negs r0, r0 + 800e5f8: f1b8 0f00 cmp.w r8, #0 + 800e5fc: d099 beq.n 800e532 <_strtol_l.isra.0+0x1a> + 800e5fe: 2a00 cmp r2, #0 + 800e600: d1f6 bne.n 800e5f0 <_strtol_l.isra.0+0xd8> + 800e602: f8c8 1000 str.w r1, [r8] + 800e606: e794 b.n 800e532 <_strtol_l.isra.0+0x1a> + 800e608: 0800fccd .word 0x0800fccd + +0800e60c : + 800e60c: 4613 mov r3, r2 + 800e60e: 460a mov r2, r1 + 800e610: 4601 mov r1, r0 + 800e612: 4802 ldr r0, [pc, #8] @ (800e61c ) + 800e614: 6800 ldr r0, [r0, #0] + 800e616: f7ff bf7f b.w 800e518 <_strtol_l.isra.0> + 800e61a: bf00 nop + 800e61c: 2000003c .word 0x2000003c + +0800e620 <_strtoul_l.isra.0>: + 800e620: e92d 43f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, lr} + 800e624: 4e34 ldr r6, [pc, #208] @ (800e6f8 <_strtoul_l.isra.0+0xd8>) + 800e626: 4686 mov lr, r0 + 800e628: 460d mov r5, r1 + 800e62a: 4628 mov r0, r5 + 800e62c: f815 4b01 ldrb.w r4, [r5], #1 + 800e630: 5d37 ldrb r7, [r6, r4] + 800e632: f017 0708 ands.w r7, r7, #8 + 800e636: d1f8 bne.n 800e62a <_strtoul_l.isra.0+0xa> + 800e638: 2c2d cmp r4, #45 @ 0x2d + 800e63a: d110 bne.n 800e65e <_strtoul_l.isra.0+0x3e> + 800e63c: 782c ldrb r4, [r5, #0] + 800e63e: 2701 movs r7, #1 + 800e640: 1c85 adds r5, r0, #2 + 800e642: f033 0010 bics.w r0, r3, #16 + 800e646: d115 bne.n 800e674 <_strtoul_l.isra.0+0x54> + 800e648: 2c30 cmp r4, #48 @ 0x30 + 800e64a: d10d bne.n 800e668 <_strtoul_l.isra.0+0x48> + 800e64c: 7828 ldrb r0, [r5, #0] + 800e64e: f000 00df and.w r0, r0, #223 @ 0xdf + 800e652: 2858 cmp r0, #88 @ 0x58 + 800e654: d108 bne.n 800e668 <_strtoul_l.isra.0+0x48> + 800e656: 786c ldrb r4, [r5, #1] + 800e658: 3502 adds r5, #2 + 800e65a: 2310 movs r3, #16 + 800e65c: e00a b.n 800e674 <_strtoul_l.isra.0+0x54> + 800e65e: 2c2b cmp r4, #43 @ 0x2b + 800e660: bf04 itt eq + 800e662: 782c ldrbeq r4, [r5, #0] + 800e664: 1c85 addeq r5, r0, #2 + 800e666: e7ec b.n 800e642 <_strtoul_l.isra.0+0x22> + 800e668: 2b00 cmp r3, #0 + 800e66a: d1f6 bne.n 800e65a <_strtoul_l.isra.0+0x3a> + 800e66c: 2c30 cmp r4, #48 @ 0x30 + 800e66e: bf14 ite ne + 800e670: 230a movne r3, #10 + 800e672: 2308 moveq r3, #8 + 800e674: f04f 38ff mov.w r8, #4294967295 @ 0xffffffff + 800e678: 2600 movs r6, #0 + 800e67a: fbb8 f8f3 udiv r8, r8, r3 + 800e67e: fb03 f908 mul.w r9, r3, r8 + 800e682: ea6f 0909 mvn.w r9, r9 + 800e686: 4630 mov r0, r6 + 800e688: f1a4 0c30 sub.w ip, r4, #48 @ 0x30 + 800e68c: f1bc 0f09 cmp.w ip, #9 + 800e690: d810 bhi.n 800e6b4 <_strtoul_l.isra.0+0x94> + 800e692: 4664 mov r4, ip + 800e694: 42a3 cmp r3, r4 + 800e696: dd1e ble.n 800e6d6 <_strtoul_l.isra.0+0xb6> + 800e698: f1b6 3fff cmp.w r6, #4294967295 @ 0xffffffff + 800e69c: d007 beq.n 800e6ae <_strtoul_l.isra.0+0x8e> + 800e69e: 4580 cmp r8, r0 + 800e6a0: d316 bcc.n 800e6d0 <_strtoul_l.isra.0+0xb0> + 800e6a2: d101 bne.n 800e6a8 <_strtoul_l.isra.0+0x88> + 800e6a4: 45a1 cmp r9, r4 + 800e6a6: db13 blt.n 800e6d0 <_strtoul_l.isra.0+0xb0> + 800e6a8: fb00 4003 mla r0, r0, r3, r4 + 800e6ac: 2601 movs r6, #1 + 800e6ae: f815 4b01 ldrb.w r4, [r5], #1 + 800e6b2: e7e9 b.n 800e688 <_strtoul_l.isra.0+0x68> + 800e6b4: f1a4 0c41 sub.w ip, r4, #65 @ 0x41 + 800e6b8: f1bc 0f19 cmp.w ip, #25 + 800e6bc: d801 bhi.n 800e6c2 <_strtoul_l.isra.0+0xa2> + 800e6be: 3c37 subs r4, #55 @ 0x37 + 800e6c0: e7e8 b.n 800e694 <_strtoul_l.isra.0+0x74> + 800e6c2: f1a4 0c61 sub.w ip, r4, #97 @ 0x61 + 800e6c6: f1bc 0f19 cmp.w ip, #25 + 800e6ca: d804 bhi.n 800e6d6 <_strtoul_l.isra.0+0xb6> + 800e6cc: 3c57 subs r4, #87 @ 0x57 + 800e6ce: e7e1 b.n 800e694 <_strtoul_l.isra.0+0x74> + 800e6d0: f04f 36ff mov.w r6, #4294967295 @ 0xffffffff + 800e6d4: e7eb b.n 800e6ae <_strtoul_l.isra.0+0x8e> + 800e6d6: 1c73 adds r3, r6, #1 + 800e6d8: d106 bne.n 800e6e8 <_strtoul_l.isra.0+0xc8> + 800e6da: 2322 movs r3, #34 @ 0x22 + 800e6dc: f8ce 3000 str.w r3, [lr] + 800e6e0: 4630 mov r0, r6 + 800e6e2: b932 cbnz r2, 800e6f2 <_strtoul_l.isra.0+0xd2> + 800e6e4: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} + 800e6e8: b107 cbz r7, 800e6ec <_strtoul_l.isra.0+0xcc> + 800e6ea: 4240 negs r0, r0 + 800e6ec: 2a00 cmp r2, #0 + 800e6ee: d0f9 beq.n 800e6e4 <_strtoul_l.isra.0+0xc4> + 800e6f0: b106 cbz r6, 800e6f4 <_strtoul_l.isra.0+0xd4> + 800e6f2: 1e69 subs r1, r5, #1 + 800e6f4: 6011 str r1, [r2, #0] + 800e6f6: e7f5 b.n 800e6e4 <_strtoul_l.isra.0+0xc4> + 800e6f8: 0800fccd .word 0x0800fccd + +0800e6fc : + 800e6fc: 4613 mov r3, r2 + 800e6fe: 460a mov r2, r1 + 800e700: 4601 mov r1, r0 + 800e702: 4802 ldr r0, [pc, #8] @ (800e70c ) + 800e704: 6800 ldr r0, [r0, #0] + 800e706: f7ff bf8b b.w 800e620 <_strtoul_l.isra.0> + 800e70a: bf00 nop + 800e70c: 2000003c .word 0x2000003c + +0800e710 <_vsniprintf_r>: + 800e710: b530 push {r4, r5, lr} + 800e712: 4614 mov r4, r2 + 800e714: 2c00 cmp r4, #0 + 800e716: b09b sub sp, #108 @ 0x6c + 800e718: 4605 mov r5, r0 + 800e71a: 461a mov r2, r3 + 800e71c: da05 bge.n 800e72a <_vsniprintf_r+0x1a> + 800e71e: 238b movs r3, #139 @ 0x8b + 800e720: 6003 str r3, [r0, #0] + 800e722: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff + 800e726: b01b add sp, #108 @ 0x6c + 800e728: bd30 pop {r4, r5, pc} + 800e72a: f44f 7302 mov.w r3, #520 @ 0x208 + 800e72e: f8ad 300c strh.w r3, [sp, #12] + 800e732: f04f 0300 mov.w r3, #0 + 800e736: 9319 str r3, [sp, #100] @ 0x64 + 800e738: bf14 ite ne + 800e73a: f104 33ff addne.w r3, r4, #4294967295 @ 0xffffffff + 800e73e: 4623 moveq r3, r4 + 800e740: 9302 str r3, [sp, #8] + 800e742: 9305 str r3, [sp, #20] + 800e744: f64f 73ff movw r3, #65535 @ 0xffff + 800e748: 9100 str r1, [sp, #0] + 800e74a: 9104 str r1, [sp, #16] + 800e74c: f8ad 300e strh.w r3, [sp, #14] + 800e750: 4669 mov r1, sp + 800e752: 9b1e ldr r3, [sp, #120] @ 0x78 + 800e754: f000 f9c0 bl 800ead8 <_svfiprintf_r> + 800e758: 1c43 adds r3, r0, #1 + 800e75a: bfbc itt lt + 800e75c: 238b movlt r3, #139 @ 0x8b + 800e75e: 602b strlt r3, [r5, #0] + 800e760: 2c00 cmp r4, #0 + 800e762: d0e0 beq.n 800e726 <_vsniprintf_r+0x16> + 800e764: 9b00 ldr r3, [sp, #0] + 800e766: 2200 movs r2, #0 + 800e768: 701a strb r2, [r3, #0] + 800e76a: e7dc b.n 800e726 <_vsniprintf_r+0x16> + +0800e76c : + 800e76c: b507 push {r0, r1, r2, lr} + 800e76e: 9300 str r3, [sp, #0] + 800e770: 4613 mov r3, r2 + 800e772: 460a mov r2, r1 + 800e774: 4601 mov r1, r0 + 800e776: 4803 ldr r0, [pc, #12] @ (800e784 ) + 800e778: 6800 ldr r0, [r0, #0] + 800e77a: f7ff ffc9 bl 800e710 <_vsniprintf_r> + 800e77e: b003 add sp, #12 + 800e780: f85d fb04 ldr.w pc, [sp], #4 + 800e784: 2000003c .word 0x2000003c + +0800e788 : + 800e788: 4402 add r2, r0 + 800e78a: 4603 mov r3, r0 + 800e78c: 4293 cmp r3, r2 + 800e78e: d100 bne.n 800e792 + 800e790: 4770 bx lr + 800e792: f803 1b01 strb.w r1, [r3], #1 + 800e796: e7f9 b.n 800e78c + +0800e798 : + 800e798: b510 push {r4, lr} + 800e79a: b16a cbz r2, 800e7b8 + 800e79c: 3901 subs r1, #1 + 800e79e: 1884 adds r4, r0, r2 + 800e7a0: f810 2b01 ldrb.w r2, [r0], #1 + 800e7a4: f811 3f01 ldrb.w r3, [r1, #1]! + 800e7a8: 429a cmp r2, r3 + 800e7aa: d103 bne.n 800e7b4 + 800e7ac: 42a0 cmp r0, r4 + 800e7ae: d001 beq.n 800e7b4 + 800e7b0: 2a00 cmp r2, #0 + 800e7b2: d1f5 bne.n 800e7a0 + 800e7b4: 1ad0 subs r0, r2, r3 + 800e7b6: bd10 pop {r4, pc} + 800e7b8: 4610 mov r0, r2 + 800e7ba: e7fc b.n 800e7b6 + +0800e7bc <__errno>: + 800e7bc: 4b01 ldr r3, [pc, #4] @ (800e7c4 <__errno+0x8>) + 800e7be: 6818 ldr r0, [r3, #0] + 800e7c0: 4770 bx lr + 800e7c2: bf00 nop + 800e7c4: 2000003c .word 0x2000003c + +0800e7c8 <__libc_init_array>: + 800e7c8: b570 push {r4, r5, r6, lr} + 800e7ca: 4d0d ldr r5, [pc, #52] @ (800e800 <__libc_init_array+0x38>) + 800e7cc: 4c0d ldr r4, [pc, #52] @ (800e804 <__libc_init_array+0x3c>) + 800e7ce: 1b64 subs r4, r4, r5 + 800e7d0: 10a4 asrs r4, r4, #2 + 800e7d2: 2600 movs r6, #0 + 800e7d4: 42a6 cmp r6, r4 + 800e7d6: d109 bne.n 800e7ec <__libc_init_array+0x24> + 800e7d8: 4d0b ldr r5, [pc, #44] @ (800e808 <__libc_init_array+0x40>) + 800e7da: 4c0c ldr r4, [pc, #48] @ (800e80c <__libc_init_array+0x44>) + 800e7dc: f000 fc64 bl 800f0a8 <_init> + 800e7e0: 1b64 subs r4, r4, r5 + 800e7e2: 10a4 asrs r4, r4, #2 + 800e7e4: 2600 movs r6, #0 + 800e7e6: 42a6 cmp r6, r4 + 800e7e8: d105 bne.n 800e7f6 <__libc_init_array+0x2e> + 800e7ea: bd70 pop {r4, r5, r6, pc} + 800e7ec: f855 3b04 ldr.w r3, [r5], #4 + 800e7f0: 4798 blx r3 + 800e7f2: 3601 adds r6, #1 + 800e7f4: e7ee b.n 800e7d4 <__libc_init_array+0xc> + 800e7f6: f855 3b04 ldr.w r3, [r5], #4 + 800e7fa: 4798 blx r3 + 800e7fc: 3601 adds r6, #1 + 800e7fe: e7f2 b.n 800e7e6 <__libc_init_array+0x1e> + 800e800: 0800fe08 .word 0x0800fe08 + 800e804: 0800fe08 .word 0x0800fe08 + 800e808: 0800fe08 .word 0x0800fe08 + 800e80c: 0800fe0c .word 0x0800fe0c + +0800e810 <__retarget_lock_acquire_recursive>: + 800e810: 4770 bx lr + +0800e812 <__retarget_lock_release_recursive>: + 800e812: 4770 bx lr + +0800e814 : + 800e814: 440a add r2, r1 + 800e816: 4291 cmp r1, r2 + 800e818: f100 33ff add.w r3, r0, #4294967295 @ 0xffffffff + 800e81c: d100 bne.n 800e820 + 800e81e: 4770 bx lr + 800e820: b510 push {r4, lr} + 800e822: f811 4b01 ldrb.w r4, [r1], #1 + 800e826: f803 4f01 strb.w r4, [r3, #1]! + 800e82a: 4291 cmp r1, r2 + 800e82c: d1f9 bne.n 800e822 + 800e82e: bd10 pop {r4, pc} + +0800e830 <_free_r>: + 800e830: b538 push {r3, r4, r5, lr} + 800e832: 4605 mov r5, r0 + 800e834: 2900 cmp r1, #0 + 800e836: d041 beq.n 800e8bc <_free_r+0x8c> + 800e838: f851 3c04 ldr.w r3, [r1, #-4] + 800e83c: 1f0c subs r4, r1, #4 + 800e83e: 2b00 cmp r3, #0 + 800e840: bfb8 it lt + 800e842: 18e4 addlt r4, r4, r3 + 800e844: f000 f8e0 bl 800ea08 <__malloc_lock> + 800e848: 4a1d ldr r2, [pc, #116] @ (800e8c0 <_free_r+0x90>) + 800e84a: 6813 ldr r3, [r2, #0] + 800e84c: b933 cbnz r3, 800e85c <_free_r+0x2c> + 800e84e: 6063 str r3, [r4, #4] + 800e850: 6014 str r4, [r2, #0] + 800e852: 4628 mov r0, r5 + 800e854: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} + 800e858: f000 b8dc b.w 800ea14 <__malloc_unlock> + 800e85c: 42a3 cmp r3, r4 + 800e85e: d908 bls.n 800e872 <_free_r+0x42> + 800e860: 6820 ldr r0, [r4, #0] + 800e862: 1821 adds r1, r4, r0 + 800e864: 428b cmp r3, r1 + 800e866: bf01 itttt eq + 800e868: 6819 ldreq r1, [r3, #0] + 800e86a: 685b ldreq r3, [r3, #4] + 800e86c: 1809 addeq r1, r1, r0 + 800e86e: 6021 streq r1, [r4, #0] + 800e870: e7ed b.n 800e84e <_free_r+0x1e> + 800e872: 461a mov r2, r3 + 800e874: 685b ldr r3, [r3, #4] + 800e876: b10b cbz r3, 800e87c <_free_r+0x4c> + 800e878: 42a3 cmp r3, r4 + 800e87a: d9fa bls.n 800e872 <_free_r+0x42> + 800e87c: 6811 ldr r1, [r2, #0] + 800e87e: 1850 adds r0, r2, r1 + 800e880: 42a0 cmp r0, r4 + 800e882: d10b bne.n 800e89c <_free_r+0x6c> + 800e884: 6820 ldr r0, [r4, #0] + 800e886: 4401 add r1, r0 + 800e888: 1850 adds r0, r2, r1 + 800e88a: 4283 cmp r3, r0 + 800e88c: 6011 str r1, [r2, #0] + 800e88e: d1e0 bne.n 800e852 <_free_r+0x22> + 800e890: 6818 ldr r0, [r3, #0] + 800e892: 685b ldr r3, [r3, #4] + 800e894: 6053 str r3, [r2, #4] + 800e896: 4408 add r0, r1 + 800e898: 6010 str r0, [r2, #0] + 800e89a: e7da b.n 800e852 <_free_r+0x22> + 800e89c: d902 bls.n 800e8a4 <_free_r+0x74> + 800e89e: 230c movs r3, #12 + 800e8a0: 602b str r3, [r5, #0] + 800e8a2: e7d6 b.n 800e852 <_free_r+0x22> + 800e8a4: 6820 ldr r0, [r4, #0] + 800e8a6: 1821 adds r1, r4, r0 + 800e8a8: 428b cmp r3, r1 + 800e8aa: bf04 itt eq + 800e8ac: 6819 ldreq r1, [r3, #0] + 800e8ae: 685b ldreq r3, [r3, #4] + 800e8b0: 6063 str r3, [r4, #4] + 800e8b2: bf04 itt eq + 800e8b4: 1809 addeq r1, r1, r0 + 800e8b6: 6021 streq r1, [r4, #0] + 800e8b8: 6054 str r4, [r2, #4] + 800e8ba: e7ca b.n 800e852 <_free_r+0x22> + 800e8bc: bd38 pop {r3, r4, r5, pc} + 800e8be: bf00 nop + 800e8c0: 20001064 .word 0x20001064 + +0800e8c4 : + 800e8c4: b570 push {r4, r5, r6, lr} + 800e8c6: 4e0f ldr r6, [pc, #60] @ (800e904 ) + 800e8c8: 460c mov r4, r1 + 800e8ca: 6831 ldr r1, [r6, #0] + 800e8cc: 4605 mov r5, r0 + 800e8ce: b911 cbnz r1, 800e8d6 + 800e8d0: f000 fba4 bl 800f01c <_sbrk_r> + 800e8d4: 6030 str r0, [r6, #0] + 800e8d6: 4621 mov r1, r4 + 800e8d8: 4628 mov r0, r5 + 800e8da: f000 fb9f bl 800f01c <_sbrk_r> + 800e8de: 1c43 adds r3, r0, #1 + 800e8e0: d103 bne.n 800e8ea + 800e8e2: f04f 34ff mov.w r4, #4294967295 @ 0xffffffff + 800e8e6: 4620 mov r0, r4 + 800e8e8: bd70 pop {r4, r5, r6, pc} + 800e8ea: 1cc4 adds r4, r0, #3 + 800e8ec: f024 0403 bic.w r4, r4, #3 + 800e8f0: 42a0 cmp r0, r4 + 800e8f2: d0f8 beq.n 800e8e6 + 800e8f4: 1a21 subs r1, r4, r0 + 800e8f6: 4628 mov r0, r5 + 800e8f8: f000 fb90 bl 800f01c <_sbrk_r> + 800e8fc: 3001 adds r0, #1 + 800e8fe: d1f2 bne.n 800e8e6 + 800e900: e7ef b.n 800e8e2 + 800e902: bf00 nop + 800e904: 20001060 .word 0x20001060 + +0800e908 <_malloc_r>: + 800e908: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} + 800e90c: 1ccd adds r5, r1, #3 + 800e90e: f025 0503 bic.w r5, r5, #3 + 800e912: 3508 adds r5, #8 + 800e914: 2d0c cmp r5, #12 + 800e916: bf38 it cc + 800e918: 250c movcc r5, #12 + 800e91a: 2d00 cmp r5, #0 + 800e91c: 4606 mov r6, r0 + 800e91e: db01 blt.n 800e924 <_malloc_r+0x1c> + 800e920: 42a9 cmp r1, r5 + 800e922: d904 bls.n 800e92e <_malloc_r+0x26> + 800e924: 230c movs r3, #12 + 800e926: 6033 str r3, [r6, #0] + 800e928: 2000 movs r0, #0 + 800e92a: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} + 800e92e: f8df 80d4 ldr.w r8, [pc, #212] @ 800ea04 <_malloc_r+0xfc> + 800e932: f000 f869 bl 800ea08 <__malloc_lock> + 800e936: f8d8 3000 ldr.w r3, [r8] + 800e93a: 461c mov r4, r3 + 800e93c: bb44 cbnz r4, 800e990 <_malloc_r+0x88> + 800e93e: 4629 mov r1, r5 + 800e940: 4630 mov r0, r6 + 800e942: f7ff ffbf bl 800e8c4 + 800e946: 1c43 adds r3, r0, #1 + 800e948: 4604 mov r4, r0 + 800e94a: d158 bne.n 800e9fe <_malloc_r+0xf6> + 800e94c: f8d8 4000 ldr.w r4, [r8] + 800e950: 4627 mov r7, r4 + 800e952: 2f00 cmp r7, #0 + 800e954: d143 bne.n 800e9de <_malloc_r+0xd6> + 800e956: 2c00 cmp r4, #0 + 800e958: d04b beq.n 800e9f2 <_malloc_r+0xea> + 800e95a: 6823 ldr r3, [r4, #0] + 800e95c: 4639 mov r1, r7 + 800e95e: 4630 mov r0, r6 + 800e960: eb04 0903 add.w r9, r4, r3 + 800e964: f000 fb5a bl 800f01c <_sbrk_r> + 800e968: 4581 cmp r9, r0 + 800e96a: d142 bne.n 800e9f2 <_malloc_r+0xea> + 800e96c: 6821 ldr r1, [r4, #0] + 800e96e: 1a6d subs r5, r5, r1 + 800e970: 4629 mov r1, r5 + 800e972: 4630 mov r0, r6 + 800e974: f7ff ffa6 bl 800e8c4 + 800e978: 3001 adds r0, #1 + 800e97a: d03a beq.n 800e9f2 <_malloc_r+0xea> + 800e97c: 6823 ldr r3, [r4, #0] + 800e97e: 442b add r3, r5 + 800e980: 6023 str r3, [r4, #0] + 800e982: f8d8 3000 ldr.w r3, [r8] + 800e986: 685a ldr r2, [r3, #4] + 800e988: bb62 cbnz r2, 800e9e4 <_malloc_r+0xdc> + 800e98a: f8c8 7000 str.w r7, [r8] + 800e98e: e00f b.n 800e9b0 <_malloc_r+0xa8> + 800e990: 6822 ldr r2, [r4, #0] + 800e992: 1b52 subs r2, r2, r5 + 800e994: d420 bmi.n 800e9d8 <_malloc_r+0xd0> + 800e996: 2a0b cmp r2, #11 + 800e998: d917 bls.n 800e9ca <_malloc_r+0xc2> + 800e99a: 1961 adds r1, r4, r5 + 800e99c: 42a3 cmp r3, r4 + 800e99e: 6025 str r5, [r4, #0] + 800e9a0: bf18 it ne + 800e9a2: 6059 strne r1, [r3, #4] + 800e9a4: 6863 ldr r3, [r4, #4] + 800e9a6: bf08 it eq + 800e9a8: f8c8 1000 streq.w r1, [r8] + 800e9ac: 5162 str r2, [r4, r5] + 800e9ae: 604b str r3, [r1, #4] + 800e9b0: 4630 mov r0, r6 + 800e9b2: f000 f82f bl 800ea14 <__malloc_unlock> + 800e9b6: f104 000b add.w r0, r4, #11 + 800e9ba: 1d23 adds r3, r4, #4 + 800e9bc: f020 0007 bic.w r0, r0, #7 + 800e9c0: 1ac2 subs r2, r0, r3 + 800e9c2: bf1c itt ne + 800e9c4: 1a1b subne r3, r3, r0 + 800e9c6: 50a3 strne r3, [r4, r2] + 800e9c8: e7af b.n 800e92a <_malloc_r+0x22> + 800e9ca: 6862 ldr r2, [r4, #4] + 800e9cc: 42a3 cmp r3, r4 + 800e9ce: bf0c ite eq + 800e9d0: f8c8 2000 streq.w r2, [r8] + 800e9d4: 605a strne r2, [r3, #4] + 800e9d6: e7eb b.n 800e9b0 <_malloc_r+0xa8> + 800e9d8: 4623 mov r3, r4 + 800e9da: 6864 ldr r4, [r4, #4] + 800e9dc: e7ae b.n 800e93c <_malloc_r+0x34> + 800e9de: 463c mov r4, r7 + 800e9e0: 687f ldr r7, [r7, #4] + 800e9e2: e7b6 b.n 800e952 <_malloc_r+0x4a> + 800e9e4: 461a mov r2, r3 + 800e9e6: 685b ldr r3, [r3, #4] + 800e9e8: 42a3 cmp r3, r4 + 800e9ea: d1fb bne.n 800e9e4 <_malloc_r+0xdc> + 800e9ec: 2300 movs r3, #0 + 800e9ee: 6053 str r3, [r2, #4] + 800e9f0: e7de b.n 800e9b0 <_malloc_r+0xa8> + 800e9f2: 230c movs r3, #12 + 800e9f4: 6033 str r3, [r6, #0] + 800e9f6: 4630 mov r0, r6 + 800e9f8: f000 f80c bl 800ea14 <__malloc_unlock> + 800e9fc: e794 b.n 800e928 <_malloc_r+0x20> + 800e9fe: 6005 str r5, [r0, #0] + 800ea00: e7d6 b.n 800e9b0 <_malloc_r+0xa8> + 800ea02: bf00 nop + 800ea04: 20001064 .word 0x20001064 + +0800ea08 <__malloc_lock>: + 800ea08: 4801 ldr r0, [pc, #4] @ (800ea10 <__malloc_lock+0x8>) + 800ea0a: f7ff bf01 b.w 800e810 <__retarget_lock_acquire_recursive> + 800ea0e: bf00 nop + 800ea10: 2000105c .word 0x2000105c + +0800ea14 <__malloc_unlock>: + 800ea14: 4801 ldr r0, [pc, #4] @ (800ea1c <__malloc_unlock+0x8>) + 800ea16: f7ff befc b.w 800e812 <__retarget_lock_release_recursive> + 800ea1a: bf00 nop + 800ea1c: 2000105c .word 0x2000105c + +0800ea20 <__ssputs_r>: + 800ea20: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} + 800ea24: 688e ldr r6, [r1, #8] + 800ea26: 461f mov r7, r3 + 800ea28: 42be cmp r6, r7 + 800ea2a: 680b ldr r3, [r1, #0] + 800ea2c: 4682 mov sl, r0 + 800ea2e: 460c mov r4, r1 + 800ea30: 4690 mov r8, r2 + 800ea32: d82d bhi.n 800ea90 <__ssputs_r+0x70> + 800ea34: f9b1 200c ldrsh.w r2, [r1, #12] + 800ea38: f412 6f90 tst.w r2, #1152 @ 0x480 + 800ea3c: d026 beq.n 800ea8c <__ssputs_r+0x6c> + 800ea3e: 6965 ldr r5, [r4, #20] + 800ea40: 6909 ldr r1, [r1, #16] + 800ea42: eb05 0545 add.w r5, r5, r5, lsl #1 + 800ea46: eba3 0901 sub.w r9, r3, r1 + 800ea4a: eb05 75d5 add.w r5, r5, r5, lsr #31 + 800ea4e: 1c7b adds r3, r7, #1 + 800ea50: 444b add r3, r9 + 800ea52: 106d asrs r5, r5, #1 + 800ea54: 429d cmp r5, r3 + 800ea56: bf38 it cc + 800ea58: 461d movcc r5, r3 + 800ea5a: 0553 lsls r3, r2, #21 + 800ea5c: d527 bpl.n 800eaae <__ssputs_r+0x8e> + 800ea5e: 4629 mov r1, r5 + 800ea60: f7ff ff52 bl 800e908 <_malloc_r> + 800ea64: 4606 mov r6, r0 + 800ea66: b360 cbz r0, 800eac2 <__ssputs_r+0xa2> + 800ea68: 6921 ldr r1, [r4, #16] + 800ea6a: 464a mov r2, r9 + 800ea6c: f7ff fed2 bl 800e814 + 800ea70: 89a3 ldrh r3, [r4, #12] + 800ea72: f423 6390 bic.w r3, r3, #1152 @ 0x480 + 800ea76: f043 0380 orr.w r3, r3, #128 @ 0x80 + 800ea7a: 81a3 strh r3, [r4, #12] + 800ea7c: 6126 str r6, [r4, #16] + 800ea7e: 6165 str r5, [r4, #20] + 800ea80: 444e add r6, r9 + 800ea82: eba5 0509 sub.w r5, r5, r9 + 800ea86: 6026 str r6, [r4, #0] + 800ea88: 60a5 str r5, [r4, #8] + 800ea8a: 463e mov r6, r7 + 800ea8c: 42be cmp r6, r7 + 800ea8e: d900 bls.n 800ea92 <__ssputs_r+0x72> + 800ea90: 463e mov r6, r7 + 800ea92: 6820 ldr r0, [r4, #0] + 800ea94: 4632 mov r2, r6 + 800ea96: 4641 mov r1, r8 + 800ea98: f000 faa6 bl 800efe8 + 800ea9c: 68a3 ldr r3, [r4, #8] + 800ea9e: 1b9b subs r3, r3, r6 + 800eaa0: 60a3 str r3, [r4, #8] + 800eaa2: 6823 ldr r3, [r4, #0] + 800eaa4: 4433 add r3, r6 + 800eaa6: 6023 str r3, [r4, #0] + 800eaa8: 2000 movs r0, #0 + 800eaaa: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} + 800eaae: 462a mov r2, r5 + 800eab0: f000 fac4 bl 800f03c <_realloc_r> + 800eab4: 4606 mov r6, r0 + 800eab6: 2800 cmp r0, #0 + 800eab8: d1e0 bne.n 800ea7c <__ssputs_r+0x5c> + 800eaba: 6921 ldr r1, [r4, #16] + 800eabc: 4650 mov r0, sl + 800eabe: f7ff feb7 bl 800e830 <_free_r> + 800eac2: 230c movs r3, #12 + 800eac4: f8ca 3000 str.w r3, [sl] + 800eac8: 89a3 ldrh r3, [r4, #12] + 800eaca: f043 0340 orr.w r3, r3, #64 @ 0x40 + 800eace: 81a3 strh r3, [r4, #12] + 800ead0: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff + 800ead4: e7e9 b.n 800eaaa <__ssputs_r+0x8a> + ... + +0800ead8 <_svfiprintf_r>: + 800ead8: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + 800eadc: 4698 mov r8, r3 + 800eade: 898b ldrh r3, [r1, #12] + 800eae0: 061b lsls r3, r3, #24 + 800eae2: b09d sub sp, #116 @ 0x74 + 800eae4: 4607 mov r7, r0 + 800eae6: 460d mov r5, r1 + 800eae8: 4614 mov r4, r2 + 800eaea: d510 bpl.n 800eb0e <_svfiprintf_r+0x36> + 800eaec: 690b ldr r3, [r1, #16] + 800eaee: b973 cbnz r3, 800eb0e <_svfiprintf_r+0x36> + 800eaf0: 2140 movs r1, #64 @ 0x40 + 800eaf2: f7ff ff09 bl 800e908 <_malloc_r> + 800eaf6: 6028 str r0, [r5, #0] + 800eaf8: 6128 str r0, [r5, #16] + 800eafa: b930 cbnz r0, 800eb0a <_svfiprintf_r+0x32> + 800eafc: 230c movs r3, #12 + 800eafe: 603b str r3, [r7, #0] + 800eb00: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff + 800eb04: b01d add sp, #116 @ 0x74 + 800eb06: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + 800eb0a: 2340 movs r3, #64 @ 0x40 + 800eb0c: 616b str r3, [r5, #20] + 800eb0e: 2300 movs r3, #0 + 800eb10: 9309 str r3, [sp, #36] @ 0x24 + 800eb12: 2320 movs r3, #32 + 800eb14: f88d 3029 strb.w r3, [sp, #41] @ 0x29 + 800eb18: f8cd 800c str.w r8, [sp, #12] + 800eb1c: 2330 movs r3, #48 @ 0x30 + 800eb1e: f8df 819c ldr.w r8, [pc, #412] @ 800ecbc <_svfiprintf_r+0x1e4> + 800eb22: f88d 302a strb.w r3, [sp, #42] @ 0x2a + 800eb26: f04f 0901 mov.w r9, #1 + 800eb2a: 4623 mov r3, r4 + 800eb2c: 469a mov sl, r3 + 800eb2e: f813 2b01 ldrb.w r2, [r3], #1 + 800eb32: b10a cbz r2, 800eb38 <_svfiprintf_r+0x60> + 800eb34: 2a25 cmp r2, #37 @ 0x25 + 800eb36: d1f9 bne.n 800eb2c <_svfiprintf_r+0x54> + 800eb38: ebba 0b04 subs.w fp, sl, r4 + 800eb3c: d00b beq.n 800eb56 <_svfiprintf_r+0x7e> + 800eb3e: 465b mov r3, fp + 800eb40: 4622 mov r2, r4 + 800eb42: 4629 mov r1, r5 + 800eb44: 4638 mov r0, r7 + 800eb46: f7ff ff6b bl 800ea20 <__ssputs_r> + 800eb4a: 3001 adds r0, #1 + 800eb4c: f000 80a7 beq.w 800ec9e <_svfiprintf_r+0x1c6> + 800eb50: 9a09 ldr r2, [sp, #36] @ 0x24 + 800eb52: 445a add r2, fp + 800eb54: 9209 str r2, [sp, #36] @ 0x24 + 800eb56: f89a 3000 ldrb.w r3, [sl] + 800eb5a: 2b00 cmp r3, #0 + 800eb5c: f000 809f beq.w 800ec9e <_svfiprintf_r+0x1c6> + 800eb60: 2300 movs r3, #0 + 800eb62: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff + 800eb66: e9cd 2305 strd r2, r3, [sp, #20] + 800eb6a: f10a 0a01 add.w sl, sl, #1 + 800eb6e: 9304 str r3, [sp, #16] + 800eb70: 9307 str r3, [sp, #28] + 800eb72: f88d 3053 strb.w r3, [sp, #83] @ 0x53 + 800eb76: 931a str r3, [sp, #104] @ 0x68 + 800eb78: 4654 mov r4, sl + 800eb7a: 2205 movs r2, #5 + 800eb7c: f814 1b01 ldrb.w r1, [r4], #1 + 800eb80: 484e ldr r0, [pc, #312] @ (800ecbc <_svfiprintf_r+0x1e4>) + 800eb82: f7f1 fb15 bl 80001b0 + 800eb86: 9a04 ldr r2, [sp, #16] + 800eb88: b9d8 cbnz r0, 800ebc2 <_svfiprintf_r+0xea> + 800eb8a: 06d0 lsls r0, r2, #27 + 800eb8c: bf44 itt mi + 800eb8e: 2320 movmi r3, #32 + 800eb90: f88d 3053 strbmi.w r3, [sp, #83] @ 0x53 + 800eb94: 0711 lsls r1, r2, #28 + 800eb96: bf44 itt mi + 800eb98: 232b movmi r3, #43 @ 0x2b + 800eb9a: f88d 3053 strbmi.w r3, [sp, #83] @ 0x53 + 800eb9e: f89a 3000 ldrb.w r3, [sl] + 800eba2: 2b2a cmp r3, #42 @ 0x2a + 800eba4: d015 beq.n 800ebd2 <_svfiprintf_r+0xfa> + 800eba6: 9a07 ldr r2, [sp, #28] + 800eba8: 4654 mov r4, sl + 800ebaa: 2000 movs r0, #0 + 800ebac: f04f 0c0a mov.w ip, #10 + 800ebb0: 4621 mov r1, r4 + 800ebb2: f811 3b01 ldrb.w r3, [r1], #1 + 800ebb6: 3b30 subs r3, #48 @ 0x30 + 800ebb8: 2b09 cmp r3, #9 + 800ebba: d94b bls.n 800ec54 <_svfiprintf_r+0x17c> + 800ebbc: b1b0 cbz r0, 800ebec <_svfiprintf_r+0x114> + 800ebbe: 9207 str r2, [sp, #28] + 800ebc0: e014 b.n 800ebec <_svfiprintf_r+0x114> + 800ebc2: eba0 0308 sub.w r3, r0, r8 + 800ebc6: fa09 f303 lsl.w r3, r9, r3 + 800ebca: 4313 orrs r3, r2 + 800ebcc: 9304 str r3, [sp, #16] + 800ebce: 46a2 mov sl, r4 + 800ebd0: e7d2 b.n 800eb78 <_svfiprintf_r+0xa0> + 800ebd2: 9b03 ldr r3, [sp, #12] + 800ebd4: 1d19 adds r1, r3, #4 + 800ebd6: 681b ldr r3, [r3, #0] + 800ebd8: 9103 str r1, [sp, #12] + 800ebda: 2b00 cmp r3, #0 + 800ebdc: bfbb ittet lt + 800ebde: 425b neglt r3, r3 + 800ebe0: f042 0202 orrlt.w r2, r2, #2 + 800ebe4: 9307 strge r3, [sp, #28] + 800ebe6: 9307 strlt r3, [sp, #28] + 800ebe8: bfb8 it lt + 800ebea: 9204 strlt r2, [sp, #16] + 800ebec: 7823 ldrb r3, [r4, #0] + 800ebee: 2b2e cmp r3, #46 @ 0x2e + 800ebf0: d10a bne.n 800ec08 <_svfiprintf_r+0x130> + 800ebf2: 7863 ldrb r3, [r4, #1] + 800ebf4: 2b2a cmp r3, #42 @ 0x2a + 800ebf6: d132 bne.n 800ec5e <_svfiprintf_r+0x186> + 800ebf8: 9b03 ldr r3, [sp, #12] + 800ebfa: 1d1a adds r2, r3, #4 + 800ebfc: 681b ldr r3, [r3, #0] + 800ebfe: 9203 str r2, [sp, #12] + 800ec00: ea43 73e3 orr.w r3, r3, r3, asr #31 + 800ec04: 3402 adds r4, #2 + 800ec06: 9305 str r3, [sp, #20] + 800ec08: f8df a0b4 ldr.w sl, [pc, #180] @ 800ecc0 <_svfiprintf_r+0x1e8> + 800ec0c: 7821 ldrb r1, [r4, #0] + 800ec0e: 2203 movs r2, #3 + 800ec10: 4650 mov r0, sl + 800ec12: f7f1 facd bl 80001b0 + 800ec16: b138 cbz r0, 800ec28 <_svfiprintf_r+0x150> + 800ec18: 9b04 ldr r3, [sp, #16] + 800ec1a: eba0 000a sub.w r0, r0, sl + 800ec1e: 2240 movs r2, #64 @ 0x40 + 800ec20: 4082 lsls r2, r0 + 800ec22: 4313 orrs r3, r2 + 800ec24: 3401 adds r4, #1 + 800ec26: 9304 str r3, [sp, #16] + 800ec28: f814 1b01 ldrb.w r1, [r4], #1 + 800ec2c: 4825 ldr r0, [pc, #148] @ (800ecc4 <_svfiprintf_r+0x1ec>) + 800ec2e: f88d 1028 strb.w r1, [sp, #40] @ 0x28 + 800ec32: 2206 movs r2, #6 + 800ec34: f7f1 fabc bl 80001b0 + 800ec38: 2800 cmp r0, #0 + 800ec3a: d036 beq.n 800ecaa <_svfiprintf_r+0x1d2> + 800ec3c: 4b22 ldr r3, [pc, #136] @ (800ecc8 <_svfiprintf_r+0x1f0>) + 800ec3e: bb1b cbnz r3, 800ec88 <_svfiprintf_r+0x1b0> + 800ec40: 9b03 ldr r3, [sp, #12] + 800ec42: 3307 adds r3, #7 + 800ec44: f023 0307 bic.w r3, r3, #7 + 800ec48: 3308 adds r3, #8 + 800ec4a: 9303 str r3, [sp, #12] + 800ec4c: 9b09 ldr r3, [sp, #36] @ 0x24 + 800ec4e: 4433 add r3, r6 + 800ec50: 9309 str r3, [sp, #36] @ 0x24 + 800ec52: e76a b.n 800eb2a <_svfiprintf_r+0x52> + 800ec54: fb0c 3202 mla r2, ip, r2, r3 + 800ec58: 460c mov r4, r1 + 800ec5a: 2001 movs r0, #1 + 800ec5c: e7a8 b.n 800ebb0 <_svfiprintf_r+0xd8> + 800ec5e: 2300 movs r3, #0 + 800ec60: 3401 adds r4, #1 + 800ec62: 9305 str r3, [sp, #20] + 800ec64: 4619 mov r1, r3 + 800ec66: f04f 0c0a mov.w ip, #10 + 800ec6a: 4620 mov r0, r4 + 800ec6c: f810 2b01 ldrb.w r2, [r0], #1 + 800ec70: 3a30 subs r2, #48 @ 0x30 + 800ec72: 2a09 cmp r2, #9 + 800ec74: d903 bls.n 800ec7e <_svfiprintf_r+0x1a6> + 800ec76: 2b00 cmp r3, #0 + 800ec78: d0c6 beq.n 800ec08 <_svfiprintf_r+0x130> + 800ec7a: 9105 str r1, [sp, #20] + 800ec7c: e7c4 b.n 800ec08 <_svfiprintf_r+0x130> + 800ec7e: fb0c 2101 mla r1, ip, r1, r2 + 800ec82: 4604 mov r4, r0 + 800ec84: 2301 movs r3, #1 + 800ec86: e7f0 b.n 800ec6a <_svfiprintf_r+0x192> + 800ec88: ab03 add r3, sp, #12 + 800ec8a: 9300 str r3, [sp, #0] + 800ec8c: 462a mov r2, r5 + 800ec8e: 4b0f ldr r3, [pc, #60] @ (800eccc <_svfiprintf_r+0x1f4>) + 800ec90: a904 add r1, sp, #16 + 800ec92: 4638 mov r0, r7 + 800ec94: f3af 8000 nop.w + 800ec98: 1c42 adds r2, r0, #1 + 800ec9a: 4606 mov r6, r0 + 800ec9c: d1d6 bne.n 800ec4c <_svfiprintf_r+0x174> + 800ec9e: 89ab ldrh r3, [r5, #12] + 800eca0: 065b lsls r3, r3, #25 + 800eca2: f53f af2d bmi.w 800eb00 <_svfiprintf_r+0x28> + 800eca6: 9809 ldr r0, [sp, #36] @ 0x24 + 800eca8: e72c b.n 800eb04 <_svfiprintf_r+0x2c> + 800ecaa: ab03 add r3, sp, #12 + 800ecac: 9300 str r3, [sp, #0] + 800ecae: 462a mov r2, r5 + 800ecb0: 4b06 ldr r3, [pc, #24] @ (800eccc <_svfiprintf_r+0x1f4>) + 800ecb2: a904 add r1, sp, #16 + 800ecb4: 4638 mov r0, r7 + 800ecb6: f000 f879 bl 800edac <_printf_i> + 800ecba: e7ed b.n 800ec98 <_svfiprintf_r+0x1c0> + 800ecbc: 0800fdcd .word 0x0800fdcd + 800ecc0: 0800fdd3 .word 0x0800fdd3 + 800ecc4: 0800fdd7 .word 0x0800fdd7 + 800ecc8: 00000000 .word 0x00000000 + 800eccc: 0800ea21 .word 0x0800ea21 + +0800ecd0 <_printf_common>: + 800ecd0: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} + 800ecd4: 4616 mov r6, r2 + 800ecd6: 4698 mov r8, r3 + 800ecd8: 688a ldr r2, [r1, #8] + 800ecda: 690b ldr r3, [r1, #16] + 800ecdc: f8dd 9020 ldr.w r9, [sp, #32] + 800ece0: 4293 cmp r3, r2 + 800ece2: bfb8 it lt + 800ece4: 4613 movlt r3, r2 + 800ece6: 6033 str r3, [r6, #0] + 800ece8: f891 2043 ldrb.w r2, [r1, #67] @ 0x43 + 800ecec: 4607 mov r7, r0 + 800ecee: 460c mov r4, r1 + 800ecf0: b10a cbz r2, 800ecf6 <_printf_common+0x26> + 800ecf2: 3301 adds r3, #1 + 800ecf4: 6033 str r3, [r6, #0] + 800ecf6: 6823 ldr r3, [r4, #0] + 800ecf8: 0699 lsls r1, r3, #26 + 800ecfa: bf42 ittt mi + 800ecfc: 6833 ldrmi r3, [r6, #0] + 800ecfe: 3302 addmi r3, #2 + 800ed00: 6033 strmi r3, [r6, #0] + 800ed02: 6825 ldr r5, [r4, #0] + 800ed04: f015 0506 ands.w r5, r5, #6 + 800ed08: d106 bne.n 800ed18 <_printf_common+0x48> + 800ed0a: f104 0a19 add.w sl, r4, #25 + 800ed0e: 68e3 ldr r3, [r4, #12] + 800ed10: 6832 ldr r2, [r6, #0] + 800ed12: 1a9b subs r3, r3, r2 + 800ed14: 42ab cmp r3, r5 + 800ed16: dc26 bgt.n 800ed66 <_printf_common+0x96> + 800ed18: f894 3043 ldrb.w r3, [r4, #67] @ 0x43 + 800ed1c: 6822 ldr r2, [r4, #0] + 800ed1e: 3b00 subs r3, #0 + 800ed20: bf18 it ne + 800ed22: 2301 movne r3, #1 + 800ed24: 0692 lsls r2, r2, #26 + 800ed26: d42b bmi.n 800ed80 <_printf_common+0xb0> + 800ed28: f104 0243 add.w r2, r4, #67 @ 0x43 + 800ed2c: 4641 mov r1, r8 + 800ed2e: 4638 mov r0, r7 + 800ed30: 47c8 blx r9 + 800ed32: 3001 adds r0, #1 + 800ed34: d01e beq.n 800ed74 <_printf_common+0xa4> + 800ed36: 6823 ldr r3, [r4, #0] + 800ed38: 6922 ldr r2, [r4, #16] + 800ed3a: f003 0306 and.w r3, r3, #6 + 800ed3e: 2b04 cmp r3, #4 + 800ed40: bf02 ittt eq + 800ed42: 68e5 ldreq r5, [r4, #12] + 800ed44: 6833 ldreq r3, [r6, #0] + 800ed46: 1aed subeq r5, r5, r3 + 800ed48: 68a3 ldr r3, [r4, #8] + 800ed4a: bf0c ite eq + 800ed4c: ea25 75e5 biceq.w r5, r5, r5, asr #31 + 800ed50: 2500 movne r5, #0 + 800ed52: 4293 cmp r3, r2 + 800ed54: bfc4 itt gt + 800ed56: 1a9b subgt r3, r3, r2 + 800ed58: 18ed addgt r5, r5, r3 + 800ed5a: 2600 movs r6, #0 + 800ed5c: 341a adds r4, #26 + 800ed5e: 42b5 cmp r5, r6 + 800ed60: d11a bne.n 800ed98 <_printf_common+0xc8> + 800ed62: 2000 movs r0, #0 + 800ed64: e008 b.n 800ed78 <_printf_common+0xa8> + 800ed66: 2301 movs r3, #1 + 800ed68: 4652 mov r2, sl + 800ed6a: 4641 mov r1, r8 + 800ed6c: 4638 mov r0, r7 + 800ed6e: 47c8 blx r9 + 800ed70: 3001 adds r0, #1 + 800ed72: d103 bne.n 800ed7c <_printf_common+0xac> + 800ed74: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff + 800ed78: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} + 800ed7c: 3501 adds r5, #1 + 800ed7e: e7c6 b.n 800ed0e <_printf_common+0x3e> + 800ed80: 18e1 adds r1, r4, r3 + 800ed82: 1c5a adds r2, r3, #1 + 800ed84: 2030 movs r0, #48 @ 0x30 + 800ed86: f881 0043 strb.w r0, [r1, #67] @ 0x43 + 800ed8a: 4422 add r2, r4 + 800ed8c: f894 1045 ldrb.w r1, [r4, #69] @ 0x45 + 800ed90: f882 1043 strb.w r1, [r2, #67] @ 0x43 + 800ed94: 3302 adds r3, #2 + 800ed96: e7c7 b.n 800ed28 <_printf_common+0x58> + 800ed98: 2301 movs r3, #1 + 800ed9a: 4622 mov r2, r4 + 800ed9c: 4641 mov r1, r8 + 800ed9e: 4638 mov r0, r7 + 800eda0: 47c8 blx r9 + 800eda2: 3001 adds r0, #1 + 800eda4: d0e6 beq.n 800ed74 <_printf_common+0xa4> + 800eda6: 3601 adds r6, #1 + 800eda8: e7d9 b.n 800ed5e <_printf_common+0x8e> + ... + +0800edac <_printf_i>: + 800edac: e92d 47ff stmdb sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, lr} + 800edb0: 7e0f ldrb r7, [r1, #24] + 800edb2: 9e0c ldr r6, [sp, #48] @ 0x30 + 800edb4: 2f78 cmp r7, #120 @ 0x78 + 800edb6: 4691 mov r9, r2 + 800edb8: 4680 mov r8, r0 + 800edba: 460c mov r4, r1 + 800edbc: 469a mov sl, r3 + 800edbe: f101 0243 add.w r2, r1, #67 @ 0x43 + 800edc2: d807 bhi.n 800edd4 <_printf_i+0x28> + 800edc4: 2f62 cmp r7, #98 @ 0x62 + 800edc6: d80a bhi.n 800edde <_printf_i+0x32> + 800edc8: 2f00 cmp r7, #0 + 800edca: f000 80d1 beq.w 800ef70 <_printf_i+0x1c4> + 800edce: 2f58 cmp r7, #88 @ 0x58 + 800edd0: f000 80b8 beq.w 800ef44 <_printf_i+0x198> + 800edd4: f104 0642 add.w r6, r4, #66 @ 0x42 + 800edd8: f884 7042 strb.w r7, [r4, #66] @ 0x42 + 800eddc: e03a b.n 800ee54 <_printf_i+0xa8> + 800edde: f1a7 0363 sub.w r3, r7, #99 @ 0x63 + 800ede2: 2b15 cmp r3, #21 + 800ede4: d8f6 bhi.n 800edd4 <_printf_i+0x28> + 800ede6: a101 add r1, pc, #4 @ (adr r1, 800edec <_printf_i+0x40>) + 800ede8: f851 f023 ldr.w pc, [r1, r3, lsl #2] + 800edec: 0800ee45 .word 0x0800ee45 + 800edf0: 0800ee59 .word 0x0800ee59 + 800edf4: 0800edd5 .word 0x0800edd5 + 800edf8: 0800edd5 .word 0x0800edd5 + 800edfc: 0800edd5 .word 0x0800edd5 + 800ee00: 0800edd5 .word 0x0800edd5 + 800ee04: 0800ee59 .word 0x0800ee59 + 800ee08: 0800edd5 .word 0x0800edd5 + 800ee0c: 0800edd5 .word 0x0800edd5 + 800ee10: 0800edd5 .word 0x0800edd5 + 800ee14: 0800edd5 .word 0x0800edd5 + 800ee18: 0800ef57 .word 0x0800ef57 + 800ee1c: 0800ee83 .word 0x0800ee83 + 800ee20: 0800ef11 .word 0x0800ef11 + 800ee24: 0800edd5 .word 0x0800edd5 + 800ee28: 0800edd5 .word 0x0800edd5 + 800ee2c: 0800ef79 .word 0x0800ef79 + 800ee30: 0800edd5 .word 0x0800edd5 + 800ee34: 0800ee83 .word 0x0800ee83 + 800ee38: 0800edd5 .word 0x0800edd5 + 800ee3c: 0800edd5 .word 0x0800edd5 + 800ee40: 0800ef19 .word 0x0800ef19 + 800ee44: 6833 ldr r3, [r6, #0] + 800ee46: 1d1a adds r2, r3, #4 + 800ee48: 681b ldr r3, [r3, #0] + 800ee4a: 6032 str r2, [r6, #0] + 800ee4c: f104 0642 add.w r6, r4, #66 @ 0x42 + 800ee50: f884 3042 strb.w r3, [r4, #66] @ 0x42 + 800ee54: 2301 movs r3, #1 + 800ee56: e09c b.n 800ef92 <_printf_i+0x1e6> + 800ee58: 6833 ldr r3, [r6, #0] + 800ee5a: 6820 ldr r0, [r4, #0] + 800ee5c: 1d19 adds r1, r3, #4 + 800ee5e: 6031 str r1, [r6, #0] + 800ee60: 0606 lsls r6, r0, #24 + 800ee62: d501 bpl.n 800ee68 <_printf_i+0xbc> + 800ee64: 681d ldr r5, [r3, #0] + 800ee66: e003 b.n 800ee70 <_printf_i+0xc4> + 800ee68: 0645 lsls r5, r0, #25 + 800ee6a: d5fb bpl.n 800ee64 <_printf_i+0xb8> + 800ee6c: f9b3 5000 ldrsh.w r5, [r3] + 800ee70: 2d00 cmp r5, #0 + 800ee72: da03 bge.n 800ee7c <_printf_i+0xd0> + 800ee74: 232d movs r3, #45 @ 0x2d + 800ee76: 426d negs r5, r5 + 800ee78: f884 3043 strb.w r3, [r4, #67] @ 0x43 + 800ee7c: 4858 ldr r0, [pc, #352] @ (800efe0 <_printf_i+0x234>) + 800ee7e: 230a movs r3, #10 + 800ee80: e011 b.n 800eea6 <_printf_i+0xfa> + 800ee82: 6821 ldr r1, [r4, #0] + 800ee84: 6833 ldr r3, [r6, #0] + 800ee86: 0608 lsls r0, r1, #24 + 800ee88: f853 5b04 ldr.w r5, [r3], #4 + 800ee8c: d402 bmi.n 800ee94 <_printf_i+0xe8> + 800ee8e: 0649 lsls r1, r1, #25 + 800ee90: bf48 it mi + 800ee92: b2ad uxthmi r5, r5 + 800ee94: 2f6f cmp r7, #111 @ 0x6f + 800ee96: 4852 ldr r0, [pc, #328] @ (800efe0 <_printf_i+0x234>) + 800ee98: 6033 str r3, [r6, #0] + 800ee9a: bf14 ite ne + 800ee9c: 230a movne r3, #10 + 800ee9e: 2308 moveq r3, #8 + 800eea0: 2100 movs r1, #0 + 800eea2: f884 1043 strb.w r1, [r4, #67] @ 0x43 + 800eea6: 6866 ldr r6, [r4, #4] + 800eea8: 60a6 str r6, [r4, #8] + 800eeaa: 2e00 cmp r6, #0 + 800eeac: db05 blt.n 800eeba <_printf_i+0x10e> + 800eeae: 6821 ldr r1, [r4, #0] + 800eeb0: 432e orrs r6, r5 + 800eeb2: f021 0104 bic.w r1, r1, #4 + 800eeb6: 6021 str r1, [r4, #0] + 800eeb8: d04b beq.n 800ef52 <_printf_i+0x1a6> + 800eeba: 4616 mov r6, r2 + 800eebc: fbb5 f1f3 udiv r1, r5, r3 + 800eec0: fb03 5711 mls r7, r3, r1, r5 + 800eec4: 5dc7 ldrb r7, [r0, r7] + 800eec6: f806 7d01 strb.w r7, [r6, #-1]! + 800eeca: 462f mov r7, r5 + 800eecc: 42bb cmp r3, r7 + 800eece: 460d mov r5, r1 + 800eed0: d9f4 bls.n 800eebc <_printf_i+0x110> + 800eed2: 2b08 cmp r3, #8 + 800eed4: d10b bne.n 800eeee <_printf_i+0x142> + 800eed6: 6823 ldr r3, [r4, #0] + 800eed8: 07df lsls r7, r3, #31 + 800eeda: d508 bpl.n 800eeee <_printf_i+0x142> + 800eedc: 6923 ldr r3, [r4, #16] + 800eede: 6861 ldr r1, [r4, #4] + 800eee0: 4299 cmp r1, r3 + 800eee2: bfde ittt le + 800eee4: 2330 movle r3, #48 @ 0x30 + 800eee6: f806 3c01 strble.w r3, [r6, #-1] + 800eeea: f106 36ff addle.w r6, r6, #4294967295 @ 0xffffffff + 800eeee: 1b92 subs r2, r2, r6 + 800eef0: 6122 str r2, [r4, #16] + 800eef2: f8cd a000 str.w sl, [sp] + 800eef6: 464b mov r3, r9 + 800eef8: aa03 add r2, sp, #12 + 800eefa: 4621 mov r1, r4 + 800eefc: 4640 mov r0, r8 + 800eefe: f7ff fee7 bl 800ecd0 <_printf_common> + 800ef02: 3001 adds r0, #1 + 800ef04: d14a bne.n 800ef9c <_printf_i+0x1f0> + 800ef06: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff + 800ef0a: b004 add sp, #16 + 800ef0c: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} + 800ef10: 6823 ldr r3, [r4, #0] + 800ef12: f043 0320 orr.w r3, r3, #32 + 800ef16: 6023 str r3, [r4, #0] + 800ef18: 4832 ldr r0, [pc, #200] @ (800efe4 <_printf_i+0x238>) + 800ef1a: 2778 movs r7, #120 @ 0x78 + 800ef1c: f884 7045 strb.w r7, [r4, #69] @ 0x45 + 800ef20: 6823 ldr r3, [r4, #0] + 800ef22: 6831 ldr r1, [r6, #0] + 800ef24: 061f lsls r7, r3, #24 + 800ef26: f851 5b04 ldr.w r5, [r1], #4 + 800ef2a: d402 bmi.n 800ef32 <_printf_i+0x186> + 800ef2c: 065f lsls r7, r3, #25 + 800ef2e: bf48 it mi + 800ef30: b2ad uxthmi r5, r5 + 800ef32: 6031 str r1, [r6, #0] + 800ef34: 07d9 lsls r1, r3, #31 + 800ef36: bf44 itt mi + 800ef38: f043 0320 orrmi.w r3, r3, #32 + 800ef3c: 6023 strmi r3, [r4, #0] + 800ef3e: b11d cbz r5, 800ef48 <_printf_i+0x19c> + 800ef40: 2310 movs r3, #16 + 800ef42: e7ad b.n 800eea0 <_printf_i+0xf4> + 800ef44: 4826 ldr r0, [pc, #152] @ (800efe0 <_printf_i+0x234>) + 800ef46: e7e9 b.n 800ef1c <_printf_i+0x170> + 800ef48: 6823 ldr r3, [r4, #0] + 800ef4a: f023 0320 bic.w r3, r3, #32 + 800ef4e: 6023 str r3, [r4, #0] + 800ef50: e7f6 b.n 800ef40 <_printf_i+0x194> + 800ef52: 4616 mov r6, r2 + 800ef54: e7bd b.n 800eed2 <_printf_i+0x126> + 800ef56: 6833 ldr r3, [r6, #0] + 800ef58: 6825 ldr r5, [r4, #0] + 800ef5a: 6961 ldr r1, [r4, #20] + 800ef5c: 1d18 adds r0, r3, #4 + 800ef5e: 6030 str r0, [r6, #0] + 800ef60: 062e lsls r6, r5, #24 + 800ef62: 681b ldr r3, [r3, #0] + 800ef64: d501 bpl.n 800ef6a <_printf_i+0x1be> + 800ef66: 6019 str r1, [r3, #0] + 800ef68: e002 b.n 800ef70 <_printf_i+0x1c4> + 800ef6a: 0668 lsls r0, r5, #25 + 800ef6c: d5fb bpl.n 800ef66 <_printf_i+0x1ba> + 800ef6e: 8019 strh r1, [r3, #0] + 800ef70: 2300 movs r3, #0 + 800ef72: 6123 str r3, [r4, #16] + 800ef74: 4616 mov r6, r2 + 800ef76: e7bc b.n 800eef2 <_printf_i+0x146> + 800ef78: 6833 ldr r3, [r6, #0] + 800ef7a: 1d1a adds r2, r3, #4 + 800ef7c: 6032 str r2, [r6, #0] + 800ef7e: 681e ldr r6, [r3, #0] + 800ef80: 6862 ldr r2, [r4, #4] + 800ef82: 2100 movs r1, #0 + 800ef84: 4630 mov r0, r6 + 800ef86: f7f1 f913 bl 80001b0 + 800ef8a: b108 cbz r0, 800ef90 <_printf_i+0x1e4> + 800ef8c: 1b80 subs r0, r0, r6 + 800ef8e: 6060 str r0, [r4, #4] + 800ef90: 6863 ldr r3, [r4, #4] + 800ef92: 6123 str r3, [r4, #16] + 800ef94: 2300 movs r3, #0 + 800ef96: f884 3043 strb.w r3, [r4, #67] @ 0x43 + 800ef9a: e7aa b.n 800eef2 <_printf_i+0x146> + 800ef9c: 6923 ldr r3, [r4, #16] + 800ef9e: 4632 mov r2, r6 + 800efa0: 4649 mov r1, r9 + 800efa2: 4640 mov r0, r8 + 800efa4: 47d0 blx sl + 800efa6: 3001 adds r0, #1 + 800efa8: d0ad beq.n 800ef06 <_printf_i+0x15a> + 800efaa: 6823 ldr r3, [r4, #0] + 800efac: 079b lsls r3, r3, #30 + 800efae: d413 bmi.n 800efd8 <_printf_i+0x22c> + 800efb0: 68e0 ldr r0, [r4, #12] + 800efb2: 9b03 ldr r3, [sp, #12] + 800efb4: 4298 cmp r0, r3 + 800efb6: bfb8 it lt + 800efb8: 4618 movlt r0, r3 + 800efba: e7a6 b.n 800ef0a <_printf_i+0x15e> + 800efbc: 2301 movs r3, #1 + 800efbe: 4632 mov r2, r6 + 800efc0: 4649 mov r1, r9 + 800efc2: 4640 mov r0, r8 + 800efc4: 47d0 blx sl + 800efc6: 3001 adds r0, #1 + 800efc8: d09d beq.n 800ef06 <_printf_i+0x15a> + 800efca: 3501 adds r5, #1 + 800efcc: 68e3 ldr r3, [r4, #12] + 800efce: 9903 ldr r1, [sp, #12] + 800efd0: 1a5b subs r3, r3, r1 + 800efd2: 42ab cmp r3, r5 + 800efd4: dcf2 bgt.n 800efbc <_printf_i+0x210> + 800efd6: e7eb b.n 800efb0 <_printf_i+0x204> + 800efd8: 2500 movs r5, #0 + 800efda: f104 0619 add.w r6, r4, #25 + 800efde: e7f5 b.n 800efcc <_printf_i+0x220> + 800efe0: 0800fdde .word 0x0800fdde + 800efe4: 0800fdef .word 0x0800fdef + +0800efe8 : + 800efe8: 4288 cmp r0, r1 + 800efea: b510 push {r4, lr} + 800efec: eb01 0402 add.w r4, r1, r2 + 800eff0: d902 bls.n 800eff8 + 800eff2: 4284 cmp r4, r0 + 800eff4: 4623 mov r3, r4 + 800eff6: d807 bhi.n 800f008 + 800eff8: 1e43 subs r3, r0, #1 + 800effa: 42a1 cmp r1, r4 + 800effc: d008 beq.n 800f010 + 800effe: f811 2b01 ldrb.w r2, [r1], #1 + 800f002: f803 2f01 strb.w r2, [r3, #1]! + 800f006: e7f8 b.n 800effa + 800f008: 4402 add r2, r0 + 800f00a: 4601 mov r1, r0 + 800f00c: 428a cmp r2, r1 + 800f00e: d100 bne.n 800f012 + 800f010: bd10 pop {r4, pc} + 800f012: f813 4d01 ldrb.w r4, [r3, #-1]! + 800f016: f802 4d01 strb.w r4, [r2, #-1]! + 800f01a: e7f7 b.n 800f00c + +0800f01c <_sbrk_r>: + 800f01c: b538 push {r3, r4, r5, lr} + 800f01e: 4d06 ldr r5, [pc, #24] @ (800f038 <_sbrk_r+0x1c>) + 800f020: 2300 movs r3, #0 + 800f022: 4604 mov r4, r0 + 800f024: 4608 mov r0, r1 + 800f026: 602b str r3, [r5, #0] + 800f028: f7f1 fe9c bl 8000d64 <_sbrk> + 800f02c: 1c43 adds r3, r0, #1 + 800f02e: d102 bne.n 800f036 <_sbrk_r+0x1a> + 800f030: 682b ldr r3, [r5, #0] + 800f032: b103 cbz r3, 800f036 <_sbrk_r+0x1a> + 800f034: 6023 str r3, [r4, #0] + 800f036: bd38 pop {r3, r4, r5, pc} + 800f038: 20001058 .word 0x20001058 + +0800f03c <_realloc_r>: + 800f03c: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} + 800f040: 4607 mov r7, r0 + 800f042: 4614 mov r4, r2 + 800f044: 460d mov r5, r1 + 800f046: b921 cbnz r1, 800f052 <_realloc_r+0x16> + 800f048: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} + 800f04c: 4611 mov r1, r2 + 800f04e: f7ff bc5b b.w 800e908 <_malloc_r> + 800f052: b92a cbnz r2, 800f060 <_realloc_r+0x24> + 800f054: f7ff fbec bl 800e830 <_free_r> + 800f058: 4625 mov r5, r4 + 800f05a: 4628 mov r0, r5 + 800f05c: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} + 800f060: f000 f81a bl 800f098 <_malloc_usable_size_r> + 800f064: 4284 cmp r4, r0 + 800f066: 4606 mov r6, r0 + 800f068: d802 bhi.n 800f070 <_realloc_r+0x34> + 800f06a: ebb4 0f50 cmp.w r4, r0, lsr #1 + 800f06e: d8f4 bhi.n 800f05a <_realloc_r+0x1e> + 800f070: 4621 mov r1, r4 + 800f072: 4638 mov r0, r7 + 800f074: f7ff fc48 bl 800e908 <_malloc_r> + 800f078: 4680 mov r8, r0 + 800f07a: b908 cbnz r0, 800f080 <_realloc_r+0x44> + 800f07c: 4645 mov r5, r8 + 800f07e: e7ec b.n 800f05a <_realloc_r+0x1e> + 800f080: 42b4 cmp r4, r6 + 800f082: 4622 mov r2, r4 + 800f084: 4629 mov r1, r5 + 800f086: bf28 it cs + 800f088: 4632 movcs r2, r6 + 800f08a: f7ff fbc3 bl 800e814 + 800f08e: 4629 mov r1, r5 + 800f090: 4638 mov r0, r7 + 800f092: f7ff fbcd bl 800e830 <_free_r> + 800f096: e7f1 b.n 800f07c <_realloc_r+0x40> + +0800f098 <_malloc_usable_size_r>: + 800f098: f851 3c04 ldr.w r3, [r1, #-4] + 800f09c: 1f18 subs r0, r3, #4 + 800f09e: 2b00 cmp r3, #0 + 800f0a0: bfbc itt lt + 800f0a2: 580b ldrlt r3, [r1, r0] + 800f0a4: 18c0 addlt r0, r0, r3 + 800f0a6: 4770 bx lr + +0800f0a8 <_init>: + 800f0a8: b5f8 push {r3, r4, r5, r6, r7, lr} + 800f0aa: bf00 nop + 800f0ac: bcf8 pop {r3, r4, r5, r6, r7} + 800f0ae: bc08 pop {r3} + 800f0b0: 469e mov lr, r3 + 800f0b2: 4770 bx lr + +0800f0b4 <_fini>: + 800f0b4: b5f8 push {r3, r4, r5, r6, r7, lr} + 800f0b6: bf00 nop + 800f0b8: bcf8 pop {r3, r4, r5, r6, r7} + 800f0ba: bc08 pop {r3} + 800f0bc: 469e mov lr, r3 + 800f0be: 4770 bx lr diff --git a/Debug/SubGHz_Phy_Per_My_Test.map b/Debug/SubGHz_Phy_Per_My_Test.map new file mode 100644 index 0000000..8af47e0 --- /dev/null +++ b/Debug/SubGHz_Phy_Per_My_Test.map @@ -0,0 +1,9745 @@ +Archive member included to satisfy reference by file (symbol) + +/opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(libc_a-exit.o) + /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/crt0.o (exit) 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/opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(libc_a-memmove.o) + .bss 0x00000000 0x0 /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(libc_a-memmove.o) + .text 0x00000000 0x0 /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(libc_a-sbrkr.o) + .data 0x00000000 0x0 /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(libc_a-sbrkr.o) + .bss 0x00000000 0x0 /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(libc_a-sbrkr.o) + .data 0x00000000 0x0 /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(libc_a-memchr.o) + .bss 0x00000000 0x0 /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(libc_a-memchr.o) + .ARM.extab 0x00000000 0x0 /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(libc_a-memchr.o) + .eh_frame 0x00000000 0x50 /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(libc_a-memchr.o) + .text 0x00000000 0x0 /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(libc_a-reallocr.o) + .data 0x00000000 0x0 /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(libc_a-reallocr.o) + .bss 0x00000000 0x0 /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(libc_a-reallocr.o) + .text 0x00000000 0x0 /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(libc_a-msizer.o) + .data 0x00000000 0x0 /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(libc_a-msizer.o) + .bss 0x00000000 0x0 /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(libc_a-msizer.o) + .data 0x00000000 0x0 /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m/nofp/libgcc.a(_aeabi_uldivmod.o) + .bss 0x00000000 0x0 /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m/nofp/libgcc.a(_aeabi_uldivmod.o) + .data 0x00000000 0x0 /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m/nofp/libgcc.a(_udivmoddi4.o) + .bss 0x00000000 0x0 /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m/nofp/libgcc.a(_udivmoddi4.o) + .ARM.extab 0x00000000 0x0 /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m/nofp/libgcc.a(_udivmoddi4.o) + .data 0x00000000 0x0 /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m/nofp/libgcc.a(_dvmd_tls.o) + .bss 0x00000000 0x0 /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m/nofp/libgcc.a(_dvmd_tls.o) + .text 0x00000000 0x0 /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m/nofp/crtend.o + .data 0x00000000 0x0 /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m/nofp/crtend.o + .bss 0x00000000 0x0 /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m/nofp/crtend.o + .rodata 0x00000000 0x24 /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m/nofp/crtend.o + .eh_frame 0x00000000 0x4 /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m/nofp/crtend.o + .ARM.attributes + 0x00000000 0x2e /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m/nofp/crtend.o + .text 0x00000000 0x0 /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m/nofp/crtn.o + .data 0x00000000 0x0 /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m/nofp/crtn.o + .bss 0x00000000 0x0 /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m/nofp/crtn.o + +Memory Configuration + +Name Origin Length Attributes +RAM 0x20000000 0x00010000 xrw +RAM2 0x10000000 0x00008000 xrw +FLASH 0x08000000 0x00040000 xr +*default* 0x00000000 0xffffffff + +Linker script and memory map + +LOAD /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m/nofp/crti.o +LOAD /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m/nofp/crtbegin.o +LOAD /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/crt0.o +LOAD ./Core/Src/dma.o +LOAD ./Core/Src/gpio.o +LOAD ./Core/Src/main.o +LOAD ./Core/Src/rtc.o +LOAD ./Core/Src/stm32_lpm_if.o +LOAD ./Core/Src/stm32wlxx_hal_msp.o +LOAD ./Core/Src/stm32wlxx_it.o +LOAD ./Core/Src/subghz.o +LOAD ./Core/Src/sys_app.o +LOAD ./Core/Src/sys_debug.o +LOAD ./Core/Src/syscalls.o +LOAD ./Core/Src/sysmem.o +LOAD ./Core/Src/system_stm32wlxx.o +LOAD ./Core/Src/timer_if.o +LOAD ./Core/Src/usart.o +LOAD ./Core/Src/usart_if.o +LOAD ./Core/Startup/startup_stm32wl55jcix.o +LOAD ./Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo.o +LOAD ./Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo_radio.o +LOAD ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.o +LOAD ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.o +LOAD ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.o +LOAD ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma_ex.o +LOAD ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_exti.o +LOAD ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash.o +LOAD ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.o +LOAD ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_gpio.o +LOAD ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.o +LOAD ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.o +LOAD ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.o +LOAD ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.o +LOAD ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.o +LOAD ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.o +LOAD ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.o +LOAD ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.o +LOAD ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.o +LOAD ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.o +LOAD ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o +LOAD ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o +LOAD ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.o +LOAD ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/wl_lr_fhss.o +LOAD ./SubGHz_Phy/App/app_subghz_phy.o +LOAD ./SubGHz_Phy/App/subghz_phy_app.o +LOAD ./SubGHz_Phy/Target/radio_board_if.o +LOAD ./Utilities/lpm/tiny_lpm/stm32_lpm.o +LOAD ./Utilities/misc/stm32_mem.o +LOAD ./Utilities/misc/stm32_systime.o +LOAD ./Utilities/misc/stm32_tiny_sscanf.o +LOAD ./Utilities/misc/stm32_tiny_vsnprintf.o +LOAD ./Utilities/sequencer/stm32_seq.o +LOAD ./Utilities/timer/stm32_timer.o +LOAD ./Utilities/trace/adv_trace/stm32_adv_trace.o +START GROUP +LOAD /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a +LOAD /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libm.a +END GROUP +START GROUP +LOAD /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m/nofp/libgcc.a +LOAD /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a +END GROUP +START GROUP +LOAD /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m/nofp/libgcc.a +LOAD /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a +LOAD /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libnosys.a +END GROUP +START GROUP +LOAD /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m/nofp/libgcc.a +LOAD /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a +LOAD /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libnosys.a +END GROUP +LOAD /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m/nofp/crtend.o +LOAD /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m/nofp/crtn.o + 0x20010000 _estack = (ORIGIN (RAM) + LENGTH (RAM)) + 0x00000200 _Min_Heap_Size = 0x200 + 0x00000800 _Min_Stack_Size = 0x800 + +.isr_vector 0x08000000 0x138 + 0x08000000 . = ALIGN (0x4) + *(.isr_vector) + .isr_vector 0x08000000 0x138 ./Core/Startup/startup_stm32wl55jcix.o + 0x08000000 g_pfnVectors + 0x08000138 . = ALIGN (0x4) + +.text 0x08000140 0xef80 + 0x08000140 . = ALIGN (0x4) + *(.text) + .text 0x08000140 0x40 /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m/nofp/crtbegin.o + .text 0x08000180 0x14 /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(libc_a-strcmp.o) + 0x08000180 strcmp + .text 0x08000194 0x10 /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(libc_a-strlen.o) + 0x08000194 strlen + *fill* 0x080001a4 0xc + .text 0x080001b0 0xa0 /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(libc_a-memchr.o) + 0x080001b0 memchr + .text 0x08000250 0x30 /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m/nofp/libgcc.a(_aeabi_uldivmod.o) + 0x08000250 __aeabi_uldivmod + .text 0x08000280 0x2f8 /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m/nofp/libgcc.a(_udivmoddi4.o) + 0x08000280 __udivmoddi4 + .text 0x08000578 0x4 /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m/nofp/libgcc.a(_dvmd_tls.o) + 0x08000578 __aeabi_ldiv0 + 0x08000578 __aeabi_idiv0 + *(.text*) + .text.LL_AHB1_GRP1_EnableClock + 0x0800057c 0x30 ./Core/Src/dma.o + .text.MX_DMA_Init + 0x080005ac 0x24 ./Core/Src/dma.o + 0x080005ac MX_DMA_Init + .text.LL_AHB2_GRP1_EnableClock + 0x080005d0 0x30 ./Core/Src/gpio.o + .text.MX_GPIO_Init + 0x08000600 0xdc ./Core/Src/gpio.o + 0x08000600 MX_GPIO_Init + .text.LL_RCC_LSE_SetDriveCapability + 0x080006dc 0x2a ./Core/Src/main.o + .text.main 0x08000706 0x1a ./Core/Src/main.o + 0x08000706 main + .text.SystemClock_Config + 0x08000720 0xb0 ./Core/Src/main.o + 0x08000720 SystemClock_Config + .text.Error_Handler + 0x080007d0 0xc ./Core/Src/main.o + 0x080007d0 Error_Handler + .text.LL_RCC_EnableRTC + 0x080007dc 0x20 ./Core/Src/rtc.o + .text.LL_APB1_GRP1_EnableClock + 0x080007fc 0x30 ./Core/Src/rtc.o + .text.MX_RTC_Init + 0x0800082c 0xa4 ./Core/Src/rtc.o + 0x0800082c MX_RTC_Init + .text.HAL_RTC_MspInit + 0x080008d0 0x78 ./Core/Src/rtc.o + 0x080008d0 HAL_RTC_MspInit + .text.LL_PWR_ClearFlag_C1STOP_C1STB + 0x08000948 0x18 ./Core/Src/stm32_lpm_if.o + .text.PWR_EnterOffMode + 0x08000960 0xc ./Core/Src/stm32_lpm_if.o + 0x08000960 PWR_EnterOffMode + .text.PWR_ExitOffMode + 0x0800096c 0xc ./Core/Src/stm32_lpm_if.o + 0x0800096c PWR_ExitOffMode + .text.PWR_EnterStopMode + 0x08000978 0x16 ./Core/Src/stm32_lpm_if.o + 0x08000978 PWR_EnterStopMode + .text.PWR_ExitStopMode + 0x0800098e 0x10 ./Core/Src/stm32_lpm_if.o + 0x0800098e PWR_ExitStopMode + .text.PWR_EnterSleepMode + 0x0800099e 0x14 ./Core/Src/stm32_lpm_if.o + 0x0800099e PWR_EnterSleepMode + .text.PWR_ExitSleepMode + 0x080009b2 0xc ./Core/Src/stm32_lpm_if.o + 0x080009b2 PWR_ExitSleepMode + .text.HAL_MspInit + 0x080009be 0xc ./Core/Src/stm32wlxx_hal_msp.o + 0x080009be HAL_MspInit + .text.NMI_Handler + 0x080009ca 0x8 ./Core/Src/stm32wlxx_it.o + 0x080009ca NMI_Handler + .text.HardFault_Handler + 0x080009d2 0x8 ./Core/Src/stm32wlxx_it.o + 0x080009d2 HardFault_Handler + .text.MemManage_Handler + 0x080009da 0x8 ./Core/Src/stm32wlxx_it.o + 0x080009da MemManage_Handler + .text.BusFault_Handler + 0x080009e2 0x8 ./Core/Src/stm32wlxx_it.o + 0x080009e2 BusFault_Handler + .text.UsageFault_Handler + 0x080009ea 0x8 ./Core/Src/stm32wlxx_it.o + 0x080009ea UsageFault_Handler + .text.SVC_Handler + 0x080009f2 0xc ./Core/Src/stm32wlxx_it.o + 0x080009f2 SVC_Handler + .text.DebugMon_Handler + 0x080009fe 0xc ./Core/Src/stm32wlxx_it.o + 0x080009fe DebugMon_Handler + .text.PendSV_Handler + 0x08000a0a 0xc ./Core/Src/stm32wlxx_it.o + 0x08000a0a PendSV_Handler + .text.SysTick_Handler + 0x08000a16 0xc ./Core/Src/stm32wlxx_it.o + 0x08000a16 SysTick_Handler + *fill* 0x08000a22 0x2 + .text.TAMP_STAMP_LSECSS_SSRU_IRQHandler + 0x08000a24 0x14 ./Core/Src/stm32wlxx_it.o + 0x08000a24 TAMP_STAMP_LSECSS_SSRU_IRQHandler + .text.EXTI0_IRQHandler + 0x08000a38 0xe ./Core/Src/stm32wlxx_it.o + 0x08000a38 EXTI0_IRQHandler + .text.EXTI1_IRQHandler + 0x08000a46 0xe ./Core/Src/stm32wlxx_it.o + 0x08000a46 EXTI1_IRQHandler + .text.DMA1_Channel5_IRQHandler + 0x08000a54 0x14 ./Core/Src/stm32wlxx_it.o + 0x08000a54 DMA1_Channel5_IRQHandler + .text.EXTI9_5_IRQHandler + 0x08000a68 0xe ./Core/Src/stm32wlxx_it.o + 0x08000a68 EXTI9_5_IRQHandler + *fill* 0x08000a76 0x2 + .text.USART2_IRQHandler + 0x08000a78 0x14 ./Core/Src/stm32wlxx_it.o + 0x08000a78 USART2_IRQHandler + .text.RTC_Alarm_IRQHandler + 0x08000a8c 0x14 ./Core/Src/stm32wlxx_it.o + 0x08000a8c RTC_Alarm_IRQHandler + .text.SUBGHZ_Radio_IRQHandler + 0x08000aa0 0x14 ./Core/Src/stm32wlxx_it.o + 0x08000aa0 SUBGHZ_Radio_IRQHandler + .text.LL_APB3_GRP1_EnableClock + 0x08000ab4 0x30 ./Core/Src/subghz.o + .text.MX_SUBGHZ_Init + 0x08000ae4 0x24 ./Core/Src/subghz.o + 0x08000ae4 MX_SUBGHZ_Init + .text.HAL_SUBGHZ_MspInit + 0x08000b08 0x26 ./Core/Src/subghz.o + 0x08000b08 HAL_SUBGHZ_MspInit + .text.LL_RCC_SetClkAfterWakeFromStop + 0x08000b2e 0x26 ./Core/Src/sys_app.o + .text.SystemApp_Init + 0x08000b54 0x48 ./Core/Src/sys_app.o + 0x08000b54 SystemApp_Init + .text.UTIL_SEQ_Idle + 0x08000b9c 0xc ./Core/Src/sys_app.o + 0x08000b9c UTIL_SEQ_Idle + .text.TimestampNow + 0x08000ba8 0x40 ./Core/Src/sys_app.o + .text.UTIL_ADV_TRACE_PreSendHook + 0x08000be8 0x10 ./Core/Src/sys_app.o + 0x08000be8 UTIL_ADV_TRACE_PreSendHook + .text.UTIL_ADV_TRACE_PostSendHook + 0x08000bf8 0x10 ./Core/Src/sys_app.o + 0x08000bf8 UTIL_ADV_TRACE_PostSendHook + .text.tiny_snprintf_like + 0x08000c08 0x2c ./Core/Src/sys_app.o + .text.HAL_InitTick + 0x08000c34 0x14 ./Core/Src/sys_app.o + 0x08000c34 HAL_InitTick + .text.HAL_GetTick + 0x08000c48 0x28 ./Core/Src/sys_app.o + 0x08000c48 HAL_GetTick + .text.HAL_Delay + 0x08000c70 0x18 ./Core/Src/sys_app.o + 0x08000c70 HAL_Delay + .text.LL_AHB2_GRP1_EnableClock + 0x08000c88 0x30 ./Core/Src/sys_debug.o + .text.LL_EXTI_EnableIT_32_63 + 0x08000cb8 0x28 ./Core/Src/sys_debug.o + .text.DBG_Init + 0x08000ce0 0x84 ./Core/Src/sys_debug.o + 0x08000ce0 DBG_Init + .text._sbrk 0x08000d64 0x6c ./Core/Src/sysmem.o + 0x08000d64 _sbrk + .text.SystemInit + 0x08000dd0 0xc ./Core/Src/system_stm32wlxx.o + 0x08000dd0 SystemInit + .text.LL_RTC_TIME_GetSubSecond + 0x08000ddc 0x16 ./Core/Src/timer_if.o + *fill* 0x08000df2 0x2 + .text.TIMER_IF_Init + 0x08000df4 0x64 ./Core/Src/timer_if.o + 0x08000df4 TIMER_IF_Init + .text.TIMER_IF_StartTimer + 0x08000e58 0x70 ./Core/Src/timer_if.o + 0x08000e58 TIMER_IF_StartTimer + .text.TIMER_IF_StopTimer + 0x08000ec8 0x34 ./Core/Src/timer_if.o + 0x08000ec8 TIMER_IF_StopTimer + .text.TIMER_IF_SetTimerContext + 0x08000efc 0x1c ./Core/Src/timer_if.o + 0x08000efc TIMER_IF_SetTimerContext + .text.TIMER_IF_GetTimerContext + 0x08000f18 0x14 ./Core/Src/timer_if.o + 0x08000f18 TIMER_IF_GetTimerContext + .text.TIMER_IF_GetTimerElapsedTime + 0x08000f2c 0x28 ./Core/Src/timer_if.o + 0x08000f2c TIMER_IF_GetTimerElapsedTime + .text.TIMER_IF_GetTimerValue + 0x08000f54 0x28 ./Core/Src/timer_if.o + 0x08000f54 TIMER_IF_GetTimerValue + .text.TIMER_IF_GetMinimumTimeout + 0x08000f7c 0x1a ./Core/Src/timer_if.o + 0x08000f7c TIMER_IF_GetMinimumTimeout + .text.TIMER_IF_Convert_ms2Tick + 0x08000f96 0x3a ./Core/Src/timer_if.o + 0x08000f96 TIMER_IF_Convert_ms2Tick + .text.TIMER_IF_Convert_Tick2ms + 0x08000fd0 0x92 ./Core/Src/timer_if.o + 0x08000fd0 TIMER_IF_Convert_Tick2ms + .text.TIMER_IF_DelayMs + 0x08001062 0x34 ./Core/Src/timer_if.o + 0x08001062 TIMER_IF_DelayMs + .text.HAL_RTC_AlarmAEventCallback + 0x08001096 0x14 ./Core/Src/timer_if.o + 0x08001096 HAL_RTC_AlarmAEventCallback + .text.HAL_RTCEx_SSRUEventCallback + 0x080010aa 0x20 ./Core/Src/timer_if.o + 0x080010aa HAL_RTCEx_SSRUEventCallback + .text.TIMER_IF_GetTime + 0x080010ca 0x8e ./Core/Src/timer_if.o + 0x080010ca TIMER_IF_GetTime + .text.TIMER_IF_BkUp_Write_Seconds + 0x08001158 0x20 ./Core/Src/timer_if.o + 0x08001158 TIMER_IF_BkUp_Write_Seconds + .text.TIMER_IF_BkUp_Write_SubSeconds + 0x08001178 0x20 ./Core/Src/timer_if.o + 0x08001178 TIMER_IF_BkUp_Write_SubSeconds + .text.TIMER_IF_BkUp_Read_Seconds + 0x08001198 0x24 ./Core/Src/timer_if.o + 0x08001198 TIMER_IF_BkUp_Read_Seconds + .text.TIMER_IF_BkUp_Read_SubSeconds + 0x080011bc 0x24 ./Core/Src/timer_if.o + 0x080011bc TIMER_IF_BkUp_Read_SubSeconds + .text.TIMER_IF_BkUp_Write_MSBticks + 0x080011e0 0x20 ./Core/Src/timer_if.o + .text.TIMER_IF_BkUp_Read_MSBticks + 0x08001200 0x20 ./Core/Src/timer_if.o + .text.GetTimerTicks + 0x08001220 0x38 ./Core/Src/timer_if.o + .text.LL_AHB2_GRP1_EnableClock + 0x08001258 0x30 ./Core/Src/usart.o + .text.LL_APB1_GRP1_EnableClock + 0x08001288 0x30 ./Core/Src/usart.o + .text.LL_APB1_GRP1_DisableClock + 0x080012b8 0x24 ./Core/Src/usart.o + .text.MX_USART2_UART_Init + 0x080012dc 0x98 ./Core/Src/usart.o + 0x080012dc MX_USART2_UART_Init + .text.HAL_UART_MspInit + 0x08001374 0x108 ./Core/Src/usart.o + 0x08001374 HAL_UART_MspInit + .text.HAL_UART_MspDeInit + 0x0800147c 0x40 ./Core/Src/usart.o + 0x0800147c HAL_UART_MspDeInit + .text.LL_APB1_GRP1_ForceReset + 0x080014bc 0x22 ./Core/Src/usart_if.o + .text.LL_APB1_GRP1_ReleaseReset + 0x080014de 0x24 ./Core/Src/usart_if.o + *fill* 0x08001502 0x2 + .text.LL_EXTI_EnableIT_0_31 + 0x08001504 0x28 ./Core/Src/usart_if.o + .text.vcom_Init + 0x0800152c 0x2c ./Core/Src/usart_if.o + 0x0800152c vcom_Init + .text.vcom_DeInit + 0x08001558 0x2c ./Core/Src/usart_if.o + 0x08001558 vcom_DeInit + .text.vcom_Trace_DMA + 0x08001584 0x28 ./Core/Src/usart_if.o + 0x08001584 vcom_Trace_DMA + .text.vcom_ReceiveInit + 0x080015ac 0x7c ./Core/Src/usart_if.o + 0x080015ac vcom_ReceiveInit + .text.vcom_Resume + 0x08001628 0x30 ./Core/Src/usart_if.o + 0x08001628 vcom_Resume + .text.HAL_UART_TxCpltCallback + 0x08001658 0x2c ./Core/Src/usart_if.o + 0x08001658 HAL_UART_TxCpltCallback + .text.HAL_UART_RxCpltCallback + 0x08001684 0x50 ./Core/Src/usart_if.o + 0x08001684 HAL_UART_RxCpltCallback + .text.Reset_Handler + 0x080016d4 0x50 ./Core/Startup/startup_stm32wl55jcix.o + 0x080016d4 Reset_Handler + .text.Default_Handler + 0x08001724 0x2 ./Core/Startup/startup_stm32wl55jcix.o + 0x08001724 EXTI2_IRQHandler + 0x08001724 TIM1_CC_IRQHandler + 0x08001724 EXTI3_IRQHandler + 0x08001724 LPTIM2_IRQHandler + 0x08001724 I2C3_ER_IRQHandler + 0x08001724 LPTIM3_IRQHandler + 0x08001724 I2C2_EV_IRQHandler + 0x08001724 SPI1_IRQHandler + 0x08001724 DMA2_Channel2_IRQHandler + 0x08001724 DMA1_Channel4_IRQHandler + 0x08001724 PKA_IRQHandler + 0x08001724 TIM17_IRQHandler + 0x08001724 DMA1_Channel7_IRQHandler + 0x08001724 SUBGHZSPI_IRQHandler + 0x08001724 IPCC_C1_TX_IRQHandler + 0x08001724 DMA2_Channel1_IRQHandler + 0x08001724 I2C1_EV_IRQHandler + 0x08001724 DMAMUX1_OVR_IRQHandler + 0x08001724 DMA1_Channel6_IRQHandler + 0x08001724 TIM16_IRQHandler + 0x08001724 DMA2_Channel4_IRQHandler + 0x08001724 RCC_IRQHandler + 0x08001724 TIM1_TRG_COM_IRQHandler + 0x08001724 DMA1_Channel1_IRQHandler + 0x08001724 Default_Handler + 0x08001724 DMA2_Channel7_IRQHandler + 0x08001724 EXTI15_10_IRQHandler + 0x08001724 IPCC_C1_RX_IRQHandler + 0x08001724 ADC_IRQHandler + 0x08001724 C2SEV_PWR_C2H_IRQHandler + 0x08001724 I2C3_EV_IRQHandler + 0x08001724 RTC_WKUP_IRQHandler + 0x08001724 PVD_PVM_IRQHandler + 0x08001724 SPI2_IRQHandler + 0x08001724 DMA2_Channel5_IRQHandler + 0x08001724 EXTI4_IRQHandler + 0x08001724 RNG_IRQHandler + 0x08001724 DMA1_Channel3_IRQHandler + 0x08001724 COMP_IRQHandler + 0x08001724 HSEM_IRQHandler + 0x08001724 TIM1_UP_IRQHandler + 0x08001724 WWDG_IRQHandler + 0x08001724 LPUART1_IRQHandler + 0x08001724 DMA2_Channel6_IRQHandler + 0x08001724 TIM2_IRQHandler + 0x08001724 TIM1_BRK_IRQHandler + 0x08001724 DAC_IRQHandler + 0x08001724 AES_IRQHandler + 0x08001724 I2C2_ER_IRQHandler + 0x08001724 DMA1_Channel2_IRQHandler + 0x08001724 FLASH_IRQHandler + 0x08001724 USART1_IRQHandler + 0x08001724 I2C1_ER_IRQHandler + 0x08001724 LPTIM1_IRQHandler + 0x08001724 DMA2_Channel3_IRQHandler + .text.LL_AHB2_GRP1_EnableClock + 0x08001726 0x30 ./Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo_radio.o + *fill* 0x08001756 0x2 + .text.BSP_RADIO_Init + 0x08001758 0x7c ./Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo_radio.o + 0x08001758 BSP_RADIO_Init + .text.BSP_RADIO_ConfigRFSwitch + 0x080017d4 0xb8 ./Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo_radio.o + 0x080017d4 BSP_RADIO_ConfigRFSwitch + .text.BSP_RADIO_GetTxConfig + 0x0800188c 0xe ./Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo_radio.o + 0x0800188c BSP_RADIO_GetTxConfig + .text.BSP_RADIO_IsTCXO + 0x0800189a 0xe ./Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo_radio.o + 0x0800189a BSP_RADIO_IsTCXO + .text.BSP_RADIO_IsDCDC + 0x080018a8 0xe ./Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo_radio.o + 0x080018a8 BSP_RADIO_IsDCDC + .text.BSP_RADIO_GetRFOMaxPowerConfig + 0x080018b6 0x26 ./Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo_radio.o + 0x080018b6 BSP_RADIO_GetRFOMaxPowerConfig + .text.LL_DBGMCU_EnableDBGSleepMode + 0x080018dc 0x1c ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.o + .text.LL_DBGMCU_EnableDBGStopMode + 0x080018f8 0x1c ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.o + .text.LL_DBGMCU_EnableDBGStandbyMode + 0x08001914 0x1c ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.o + .text.HAL_Init + 0x08001930 0x40 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.o + 0x08001930 HAL_Init + .text.HAL_SuspendTick + 0x08001970 0x1c ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.o + 0x08001970 HAL_SuspendTick + .text.HAL_ResumeTick + 0x0800198c 0x1c ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.o + 0x0800198c HAL_ResumeTick + .text.HAL_DBGMCU_EnableDBGSleepMode + 0x080019a8 0xc ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.o + 0x080019a8 HAL_DBGMCU_EnableDBGSleepMode + .text.HAL_DBGMCU_EnableDBGStopMode + 0x080019b4 0xc ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.o + 0x080019b4 HAL_DBGMCU_EnableDBGStopMode + .text.HAL_DBGMCU_EnableDBGStandbyMode + 0x080019c0 0xc ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.o + 0x080019c0 HAL_DBGMCU_EnableDBGStandbyMode + .text.__NVIC_SetPriorityGrouping + 0x080019cc 0x48 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.o + .text.__NVIC_GetPriorityGrouping + 0x08001a14 0x1c ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.o + .text.__NVIC_EnableIRQ + 0x08001a30 0x38 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.o + .text.__NVIC_DisableIRQ + 0x08001a68 0x48 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.o + .text.__NVIC_SetPriority + 0x08001ab0 0x54 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.o + .text.NVIC_EncodePriority + 0x08001b04 0x64 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.o + .text.HAL_NVIC_SetPriorityGrouping + 0x08001b68 0x16 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.o + 0x08001b68 HAL_NVIC_SetPriorityGrouping + .text.HAL_NVIC_SetPriority + 0x08001b7e 0x34 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.o + 0x08001b7e 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.text.SUBGHZSPI_Transmit + 0x08004f70 0xac ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.o + 0x08004f70 SUBGHZSPI_Transmit + .text.SUBGHZSPI_Receive + 0x0800501c 0xb0 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.o + 0x0800501c SUBGHZSPI_Receive + .text.SUBGHZ_CheckDeviceReady + 0x080050cc 0x40 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.o + 0x080050cc SUBGHZ_CheckDeviceReady + .text.SUBGHZ_WaitOnBusy + 0x0800510c 0x5c ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.o + 0x0800510c SUBGHZ_WaitOnBusy + .text.LL_RCC_GetUSARTClockSource + 0x08005168 0x24 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.o + .text.LL_RCC_GetLPUARTClockSource + 0x0800518c 0x1e ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.o + .text.HAL_UART_Init + 0x080051aa 0xa0 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.o + 0x080051aa HAL_UART_Init + .text.HAL_UART_Transmit + 0x0800524a 0x132 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.o + 0x0800524a HAL_UART_Transmit + .text.HAL_UART_Receive_IT + 0x0800537c 0x98 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.o + 0x0800537c HAL_UART_Receive_IT + .text.HAL_UART_Transmit_DMA + 0x08005414 0x100 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.o + 0x08005414 HAL_UART_Transmit_DMA + .text.HAL_UART_AbortReceive + 0x08005514 0x162 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.o + 0x08005514 HAL_UART_AbortReceive + *fill* 0x08005676 0x2 + .text.HAL_UART_IRQHandler + 0x08005678 0x684 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.o + 0x08005678 HAL_UART_IRQHandler + .text.HAL_UART_TxHalfCpltCallback + 0x08005cfc 0x12 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.o + 0x08005cfc HAL_UART_TxHalfCpltCallback + .text.HAL_UART_ErrorCallback + 0x08005d0e 0x12 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.o + 0x08005d0e HAL_UART_ErrorCallback + .text.HAL_UARTEx_RxEventCallback + 0x08005d20 0x16 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.o + 0x08005d20 HAL_UARTEx_RxEventCallback + *fill* 0x08005d36 0x2 + .text.UART_SetConfig + 0x08005d38 0x4e8 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.o + 0x08005d38 UART_SetConfig + .text.UART_AdvFeatureConfig + 0x08006220 0x142 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.o + 0x08006220 UART_AdvFeatureConfig + .text.UART_CheckIdleState + 0x08006362 0x154 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.o + 0x08006362 UART_CheckIdleState + .text.UART_WaitOnFlagUntilTimeout + 0x080064b6 0xda ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.o + 0x080064b6 UART_WaitOnFlagUntilTimeout + .text.UART_Start_Receive_IT + 0x08006590 0x240 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.o + 0x08006590 UART_Start_Receive_IT + .text.UART_EndTxTransfer + 0x080067d0 0x80 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.o + .text.UART_EndRxTransfer + 0x08006850 0xca ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.o + .text.UART_DMATransmitCplt + 0x0800691a 0x92 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.o + .text.UART_DMATxHalfCplt + 0x080069ac 0x1c ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.o + .text.UART_DMAError + 0x080069c8 0x70 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.o + .text.UART_DMAAbortOnError + 0x08006a38 0x1c ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.o + .text.UART_EndTransmit_IT + 0x08006a54 0x56 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.o + *fill* 0x08006aaa 0x2 + .text.UART_RxISR_8BIT + 0x08006aac 0x1b8 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.o + .text.UART_RxISR_16BIT + 0x08006c64 0x1b8 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.o + .text.UART_RxISR_8BIT_FIFOEN + 0x08006e1c 0x364 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.o + .text.UART_RxISR_16BIT_FIFOEN + 0x08007180 0x36c ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.o + .text.HAL_UARTEx_WakeupCallback + 0x080074ec 0x12 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.o + 0x080074ec HAL_UARTEx_WakeupCallback + .text.HAL_UARTEx_RxFifoFullCallback + 0x080074fe 0x12 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.o + 0x080074fe HAL_UARTEx_RxFifoFullCallback + .text.HAL_UARTEx_TxFifoEmptyCallback + 0x08007510 0x12 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.o + 0x08007510 HAL_UARTEx_TxFifoEmptyCallback + .text.HAL_UARTEx_StopModeWakeUpSourceConfig + 0x08007522 0xb6 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.o + 0x08007522 HAL_UARTEx_StopModeWakeUpSourceConfig + .text.HAL_UARTEx_EnableStopMode + 0x080075d8 0x64 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.o + 0x080075d8 HAL_UARTEx_EnableStopMode + .text.HAL_UARTEx_EnableFifoMode + 0x0800763c 0x76 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.o + 0x0800763c HAL_UARTEx_EnableFifoMode + .text.HAL_UARTEx_SetTxFifoThreshold + 0x080076b2 0x7c ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.o + 0x080076b2 HAL_UARTEx_SetTxFifoThreshold + .text.HAL_UARTEx_SetRxFifoThreshold + 0x0800772e 0x7c ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.o + 0x0800772e HAL_UARTEx_SetRxFifoThreshold + .text.UARTEx_Wakeup_AddressConfig + 0x080077aa 0x44 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.o + *fill* 0x080077ee 0x2 + .text.UARTEx_SetNbDataToProcess + 0x080077f0 0x98 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.o + .text.LL_GPIO_SetOutputPin + 0x08007888 0x1a ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + .text.LL_GPIO_ResetOutputPin + 0x080078a2 0x1a ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + .text.RadioInit + 0x080078bc 0xb8 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + .text.RadioGetStatus + 0x08007974 0x2e ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + *fill* 0x080079a2 0x2 + .text.RadioSetModem + 0x080079a4 0xb8 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + .text.RadioSetChannel + 0x08007a5c 0x16 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + .text.RadioIsChannelFree + 0x08007a72 0xb4 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + .text.RadioRandom + 0x08007b26 0x26 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + .text.RadioSetRxConfig + 0x08007b4c 0x418 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + .text.RadioSetTxConfig + 0x08007f64 0x224 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + .text.RadioCheckRfFrequency + 0x08008188 0x14 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + .text.RadioGetLoRaBandwidthInHz + 0x0800819c 0xac ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + .text.RadioGetGfskTimeOnAirNumerator + 0x08008248 0x54 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + .text.RadioGetLoRaTimeOnAirNumerator + 0x0800829c 0x102 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + *fill* 0x0800839e 0x2 + .text.RadioTimeOnAir + 0x080083a0 0xb0 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + .text.RadioSend + 0x08008450 0x20c ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + .text.RadioSleep + 0x0800865c 0x26 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + .text.RadioStandby + 0x08008682 0xe ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + .text.RadioRx 0x08008690 0x8c ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + .text.RadioRxBoosted + 0x0800871c 0x8c ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + .text.RadioSetRxDutyCycle + 0x080087a8 0x48 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + .text.RadioStartCad + 0x080087f0 0x30 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + .text.RadioSetTxContinuousWave + 0x08008820 0x64 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + .text.RadioRssi + 0x08008884 0x18 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + .text.RadioWrite + 0x0800889c 0x24 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + .text.RadioRead + 0x080088c0 0x1c ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + .text.RadioWriteRegisters + 0x080088dc 0x26 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + .text.RadioReadRegisters + 0x08008902 0x26 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + .text.RadioSetMaxPayloadLength + 0x08008928 0x5c ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + .text.RadioSetPublicNetwork + 0x08008984 0x5c ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + .text.RadioGetWakeupTime + 0x080089e0 0x10 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + .text.RadioOnTxTimeoutIrq + 0x080089f0 0x14 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + .text.RadioOnRxTimeoutIrq + 0x08008a04 0x14 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + .text.RadioOnTxTimeoutProcess + 0x08008a18 0x34 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + .text.RadioOnRxTimeoutProcess + 0x08008a4c 0x34 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + .text.RadioOnDioIrq + 0x08008a80 0x24 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + .text.RadioIrqProcess + 0x08008aa4 0x478 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + .text.RadioTxPrbs + 0x08008f1c 0x38 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + .text.RadioTxCw + 0x08008f54 0x38 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + .text.payload_integration + 0x08008f8c 0x124 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + .text.RadioSetRxGenericConfig + 0x080090b0 0x38c ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + .text.RadioSetTxGenericConfig + 0x0800943c 0x470 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + .text.RadioLrFhssSetCfg + 0x080098ac 0x18 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + .text.RadioLrFhssGetTimeOnAirInMs + 0x080098c4 0x16 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + *fill* 0x080098da 0x2 + .text.SUBGRF_Init + 0x080098dc 0x90 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x080098dc SUBGRF_Init + .text.SUBGRF_GetOperatingMode + 0x0800996c 0x14 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x0800996c SUBGRF_GetOperatingMode + .text.SUBGRF_SetPayload + 0x08009980 0x20 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x08009980 SUBGRF_SetPayload + .text.SUBGRF_GetPayload + 0x080099a0 0x44 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x080099a0 SUBGRF_GetPayload + .text.SUBGRF_SendPayload + 0x080099e4 0x26 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x080099e4 SUBGRF_SendPayload + .text.SUBGRF_SetSyncWord + 0x08009a0a 0x1e ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x08009a0a SUBGRF_SetSyncWord + .text.SUBGRF_SetCrcSeed + 0x08009a28 0x40 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x08009a28 SUBGRF_SetCrcSeed + .text.SUBGRF_SetCrcPolynomial + 0x08009a68 0x40 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x08009a68 SUBGRF_SetCrcPolynomial + .text.SUBGRF_SetWhiteningSeed + 0x08009aa8 0x66 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x08009aa8 SUBGRF_SetWhiteningSeed + .text.SUBGRF_GetRandom + 0x08009b0e 0x8c ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x08009b0e SUBGRF_GetRandom + *fill* 0x08009b9a 0x2 + .text.SUBGRF_SetSleep + 0x08009b9c 0x68 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x08009b9c SUBGRF_SetSleep + .text.SUBGRF_SetStandby + 0x08009c04 0x38 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x08009c04 SUBGRF_SetStandby + .text.SUBGRF_SetTx + 0x08009c3c 0x40 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x08009c3c SUBGRF_SetTx + .text.SUBGRF_SetRx + 0x08009c7c 0x40 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x08009c7c SUBGRF_SetRx + .text.SUBGRF_SetRxBoosted + 0x08009cbc 0x48 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x08009cbc SUBGRF_SetRxBoosted + .text.SUBGRF_SetRxDutyCycle + 0x08009d04 0x58 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x08009d04 SUBGRF_SetRxDutyCycle + .text.SUBGRF_SetCad + 0x08009d5c 0x1c ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x08009d5c SUBGRF_SetCad + .text.SUBGRF_SetTxContinuousWave + 0x08009d78 0x12 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x08009d78 SUBGRF_SetTxContinuousWave + .text.SUBGRF_SetTxInfinitePreamble + 0x08009d8a 0x12 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x08009d8a SUBGRF_SetTxInfinitePreamble + .text.SUBGRF_SetStopRxTimerOnPreambleDetect + 0x08009d9c 0x1e ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x08009d9c SUBGRF_SetStopRxTimerOnPreambleDetect + .text.SUBGRF_SetLoRaSymbNumTimeout + 0x08009dba 0x5e ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x08009dba SUBGRF_SetLoRaSymbNumTimeout + .text.SUBGRF_SetRegulatorMode + 0x08009e18 0x2e ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x08009e18 SUBGRF_SetRegulatorMode + .text.SUBGRF_Calibrate + 0x08009e46 0x98 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x08009e46 SUBGRF_Calibrate + *fill* 0x08009ede 0x2 + .text.SUBGRF_CalibrateImage + 0x08009ee0 0x94 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x08009ee0 SUBGRF_CalibrateImage + .text.SUBGRF_SetPaConfig + 0x08009f74 0x44 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x08009f74 SUBGRF_SetPaConfig + .text.SUBGRF_SetDioIrqParams + 0x08009fb8 0x74 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x08009fb8 SUBGRF_SetDioIrqParams + .text.SUBGRF_SetTcxoMode + 0x0800a02c 0x42 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x0800a02c SUBGRF_SetTcxoMode + *fill* 0x0800a06e 0x2 + .text.SUBGRF_SetRfFrequency + 0x0800a070 0x8c ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x0800a070 SUBGRF_SetRfFrequency + .text.SUBGRF_SetPacketType + 0x0800a0fc 0x38 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x0800a0fc SUBGRF_SetPacketType + .text.SUBGRF_GetPacketType + 0x0800a134 0x14 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x0800a134 SUBGRF_GetPacketType + .text.SUBGRF_SetTxParams + 0x0800a148 0x19a ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x0800a148 SUBGRF_SetTxParams + *fill* 0x0800a2e2 0x2 + .text.SUBGRF_SetModulationParams + 0x0800a2e4 0x19c ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x0800a2e4 SUBGRF_SetModulationParams + .text.SUBGRF_SetPacketParams + 0x0800a480 0x138 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x0800a480 SUBGRF_SetPacketParams + .text.SUBGRF_SetBufferBaseAddress + 0x0800a5b8 0x2e ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x0800a5b8 SUBGRF_SetBufferBaseAddress + .text.SUBGRF_GetRssiInst + 0x0800a5e6 0x2a ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x0800a5e6 SUBGRF_GetRssiInst + .text.SUBGRF_GetRxBufferStatus + 0x0800a610 0x58 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x0800a610 SUBGRF_GetRxBufferStatus + .text.SUBGRF_GetPacketStatus + 0x0800a668 0xa4 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x0800a668 SUBGRF_GetPacketStatus + .text.SUBGRF_WriteRegister + 0x0800a70c 0x44 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x0800a70c SUBGRF_WriteRegister + .text.SUBGRF_ReadRegister + 0x0800a750 0x40 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x0800a750 SUBGRF_ReadRegister + .text.SUBGRF_WriteRegisters + 0x0800a790 0x44 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x0800a790 SUBGRF_WriteRegisters + .text.SUBGRF_ReadRegisters + 0x0800a7d4 0x44 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x0800a7d4 SUBGRF_ReadRegisters + .text.SUBGRF_WriteBuffer + 0x0800a818 0x44 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x0800a818 SUBGRF_WriteBuffer + .text.SUBGRF_ReadBuffer + 0x0800a85c 0x44 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x0800a85c SUBGRF_ReadBuffer + .text.SUBGRF_WriteCommand + 0x0800a8a0 0x44 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x0800a8a0 SUBGRF_WriteCommand + .text.SUBGRF_ReadCommand + 0x0800a8e4 0x44 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x0800a8e4 SUBGRF_ReadCommand + .text.SUBGRF_SetSwitch + 0x0800a928 0x50 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x0800a928 SUBGRF_SetSwitch + .text.SUBGRF_SetRfTxPower + 0x0800a978 0x68 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x0800a978 SUBGRF_SetRfTxPower + .text.SUBGRF_GetRadioWakeUpTime + 0x0800a9e0 0xe ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x0800a9e0 SUBGRF_GetRadioWakeUpTime + *fill* 0x0800a9ee 0x2 + .text.HAL_SUBGHZ_TxCpltCallback + 0x0800a9f0 0x1c ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x0800a9f0 HAL_SUBGHZ_TxCpltCallback + .text.HAL_SUBGHZ_RxCpltCallback + 0x0800aa0c 0x1c ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x0800aa0c HAL_SUBGHZ_RxCpltCallback + .text.HAL_SUBGHZ_CRCErrorCallback + 0x0800aa28 0x1c ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x0800aa28 HAL_SUBGHZ_CRCErrorCallback + .text.HAL_SUBGHZ_CADStatusCallback + 0x0800aa44 0x3c ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x0800aa44 HAL_SUBGHZ_CADStatusCallback + .text.HAL_SUBGHZ_RxTxTimeoutCallback + 0x0800aa80 0x20 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x0800aa80 HAL_SUBGHZ_RxTxTimeoutCallback + .text.HAL_SUBGHZ_HeaderErrorCallback + 0x0800aaa0 0x1c ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x0800aaa0 HAL_SUBGHZ_HeaderErrorCallback + .text.HAL_SUBGHZ_PreambleDetectedCallback + 0x0800aabc 0x1c ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x0800aabc HAL_SUBGHZ_PreambleDetectedCallback + .text.HAL_SUBGHZ_SyncWordValidCallback + 0x0800aad8 0x1c ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x0800aad8 HAL_SUBGHZ_SyncWordValidCallback + .text.HAL_SUBGHZ_HeaderValidCallback + 0x0800aaf4 0x1c ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x0800aaf4 HAL_SUBGHZ_HeaderValidCallback + .text.HAL_SUBGHZ_LrFhssHopCallback + 0x0800ab10 0x20 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x0800ab10 HAL_SUBGHZ_LrFhssHopCallback + .text.Radio_SMPS_Set + 0x0800ab30 0x42 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + *fill* 0x0800ab72 0x2 + .text.SUBGRF_GetFskBandwidthRegValue + 0x0800ab74 0x50 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x0800ab74 SUBGRF_GetFskBandwidthRegValue + .text.SUBGRF_GetCFO + 0x0800abc4 0xe8 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x0800abc4 SUBGRF_GetCFO + .text.LL_DBGMCU_GetRevisionID + 0x0800acac 0x18 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.o + .text.LL_GPIO_SetOutputPin + 0x0800acc4 0x1a ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.o + .text.LL_GPIO_ResetOutputPin + 0x0800acde 0x1a ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.o + .text.RFW_TransmitLongPacket + 0x0800acf8 0x2f4 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.o + 0x0800acf8 RFW_TransmitLongPacket + .text.RFW_ReceiveLongPacket + 0x0800afec 0xcc ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.o + 0x0800afec RFW_ReceiveLongPacket + .text.RFW_Init + 0x0800b0b8 0x134 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.o + 0x0800b0b8 RFW_Init + .text.RFW_DeInit + 0x0800b1ec 0x18 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.o + 0x0800b1ec RFW_DeInit + .text.RFW_Is_Init + 0x0800b204 0x14 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.o + 0x0800b204 RFW_Is_Init + .text.RFW_Is_LongPacketModeEnabled + 0x0800b218 0x14 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.o + 0x0800b218 RFW_Is_LongPacketModeEnabled + .text.RFW_SetAntSwitch + 0x0800b22c 0x20 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.o + 0x0800b22c RFW_SetAntSwitch + .text.RFW_TransmitInit + 0x0800b24c 0x10c ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.o + 0x0800b24c RFW_TransmitInit + .text.RFW_ReceiveInit + 0x0800b358 0x38 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.o + 0x0800b358 RFW_ReceiveInit + .text.RFW_DeInit_TxLongPacket + 0x0800b390 0x36 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.o + 0x0800b390 RFW_DeInit_TxLongPacket + *fill* 0x0800b3c6 0x2 + .text.RFW_ReceivePayload + 0x0800b3c8 0xf8 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.o + 0x0800b3c8 RFW_ReceivePayload + .text.RFW_SetRadioModem + 0x0800b4c0 0x20 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.o + 0x0800b4c0 RFW_SetRadioModem + .text.RFW_TransmitLongPacket_NewTxChunkTimerEvent + 0x0800b4e0 0x14 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.o + .text.RFW_TransmitLongPacket_TxChunkProcess + 0x0800b4f4 0x1d0 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.o + .text.RFW_WhiteInitState + 0x0800b6c4 0x1c ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.o + .text.RFW_WhiteSetState + 0x0800b6e0 0x1a ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.o + .text.RFW_CrcInitState + 0x0800b6fa 0x36 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.o + .text.RFW_CrcSetState + 0x0800b730 0x1a ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.o + .text.RFW_WhiteRun + 0x0800b74a 0x90 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.o + .text.RFW_CrcRun + 0x0800b7da 0x98 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.o + .text.RFW_CrcRun1Byte + 0x0800b872 0x5c ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.o + 0x0800b872 RFW_CrcRun1Byte + *fill* 0x0800b8ce 0x2 + .text.RFW_PollRxBytes + 0x0800b8d0 0x78 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.o + .text.RFW_GetPacketLength + 0x0800b948 0xac ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.o + .text.RFW_GetPayloadTimerEvent + 0x0800b9f4 0x14 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.o + .text.RFW_GetPayloadProcess + 0x0800ba08 0x240 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.o + .text.RFW_GetPayload + 0x0800bc48 0x19c ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.o + .text.MX_SubGHz_Phy_Init + 0x0800bde4 0x10 ./SubGHz_Phy/App/app_subghz_phy.o + 0x0800bde4 MX_SubGHz_Phy_Init + .text.MX_SubGHz_Phy_Process + 0x0800bdf4 0x14 ./SubGHz_Phy/App/app_subghz_phy.o + 0x0800bdf4 MX_SubGHz_Phy_Process + .text.SubghzApp_Init + 0x0800be08 0x80 ./SubGHz_Phy/App/subghz_phy_app.o + 0x0800be08 SubghzApp_Init + .text.SubghzApp_Process + 0x0800be88 0x18 ./SubGHz_Phy/App/subghz_phy_app.o + 0x0800be88 SubghzApp_Process + .text.App_ProcessRadioEvents + 0x0800bea0 0x124 ./SubGHz_Phy/App/subghz_phy_app.o + .text.App_ProcessUartPacketizer + 0x0800bfc4 0x58 ./SubGHz_Phy/App/subghz_phy_app.o + .text.App_ProcessEscape + 0x0800c01c 0xa0 ./SubGHz_Phy/App/subghz_phy_app.o + .text.App_StartNextTxIfPossible + 0x0800c0bc 0x74 ./SubGHz_Phy/App/subghz_phy_app.o + .text.App_RadioApplyConfig + 0x0800c130 0x28 ./SubGHz_Phy/App/subghz_phy_app.o + .text.App_RadioConfigureRx + 0x0800c158 0xa8 ./SubGHz_Phy/App/subghz_phy_app.o + .text.App_RadioConfigureTx + 0x0800c200 0x98 ./SubGHz_Phy/App/subghz_phy_app.o + .text.App_RadioEnterRx + 0x0800c298 0x18 ./SubGHz_Phy/App/subghz_phy_app.o + .text.App_EnterConfigMode + 0x0800c2b0 0x30 ./SubGHz_Phy/App/subghz_phy_app.o + .text.App_ExitConfigMode + 0x0800c2e0 0x34 ./SubGHz_Phy/App/subghz_phy_app.o + .text.App_ResetDataPath + 0x0800c314 0x44 ./SubGHz_Phy/App/subghz_phy_app.o + .text.App_DataModeFeedByte + 0x0800c358 0x84 ./SubGHz_Phy/App/subghz_phy_app.o + .text.App_DataModeFlushBuilder + 0x0800c3dc 0x40 ./SubGHz_Phy/App/subghz_phy_app.o + .text.App_QueuePush + 0x0800c41c 0x8c ./SubGHz_Phy/App/subghz_phy_app.o + .text.App_QueuePop + 0x0800c4a8 0x3c ./SubGHz_Phy/App/subghz_phy_app.o + .text.UartRxByteCallback + 0x0800c4e4 0x140 ./SubGHz_Phy/App/subghz_phy_app.o + .text.App_ConfigFeedByte + 0x0800c624 0xc4 ./SubGHz_Phy/App/subghz_phy_app.o + .text.App_ConfigExecuteLine + 0x0800c6e8 0x470 ./SubGHz_Phy/App/subghz_phy_app.o + .text.App_PrintConfigPrompt + 0x0800cb58 0x20 ./SubGHz_Phy/App/subghz_phy_app.o + .text.App_PrintHelp + 0x0800cb78 0x94 ./SubGHz_Phy/App/subghz_phy_app.o + .text.App_PrintStatus + 0x0800cc0c 0x174 ./SubGHz_Phy/App/subghz_phy_app.o + .text.App_Printf + 0x0800cd80 0x56 ./SubGHz_Phy/App/subghz_phy_app.o + *fill* 0x0800cdd6 0x2 + .text.App_Write + 0x0800cdd8 0x34 ./SubGHz_Phy/App/subghz_phy_app.o + .text.App_ReconfigureUart + 0x0800ce0c 0x70 ./SubGHz_Phy/App/subghz_phy_app.o + .text.App_ParseHexSyncWord + 0x0800ce7c 0xec ./SubGHz_Phy/App/subghz_phy_app.o + .text.App_SkipSpaces + 0x0800cf68 0x44 ./SubGHz_Phy/App/subghz_phy_app.o + .text.OnTxDone + 0x0800cfac 0x18 ./SubGHz_Phy/App/subghz_phy_app.o + .text.OnRxDone + 0x0800cfc4 0x64 ./SubGHz_Phy/App/subghz_phy_app.o + .text.OnTxTimeout + 0x0800d028 0x18 ./SubGHz_Phy/App/subghz_phy_app.o + .text.OnRxTimeout + 0x0800d040 0x18 ./SubGHz_Phy/App/subghz_phy_app.o + .text.OnRxError + 0x0800d058 0x18 ./SubGHz_Phy/App/subghz_phy_app.o + .text.RBI_Init + 0x0800d070 0xe ./SubGHz_Phy/Target/radio_board_if.o + 0x0800d070 RBI_Init + .text.RBI_ConfigRFSwitch + 0x0800d07e 0x1c ./SubGHz_Phy/Target/radio_board_if.o + 0x0800d07e RBI_ConfigRFSwitch + .text.RBI_GetTxConfig + 0x0800d09a 0xe ./SubGHz_Phy/Target/radio_board_if.o + 0x0800d09a RBI_GetTxConfig + .text.RBI_IsTCXO + 0x0800d0a8 0xe ./SubGHz_Phy/Target/radio_board_if.o + 0x0800d0a8 RBI_IsTCXO + .text.RBI_IsDCDC + 0x0800d0b6 0xe ./SubGHz_Phy/Target/radio_board_if.o + 0x0800d0b6 RBI_IsDCDC + .text.RBI_GetRFOMaxPowerConfig + 0x0800d0c4 0x1c ./SubGHz_Phy/Target/radio_board_if.o + 0x0800d0c4 RBI_GetRFOMaxPowerConfig + .text.UTIL_LPM_Init + 0x0800d0e0 0x20 ./Utilities/lpm/tiny_lpm/stm32_lpm.o + 0x0800d0e0 UTIL_LPM_Init + .text.UTIL_LPM_SetStopMode + 0x0800d100 0x60 ./Utilities/lpm/tiny_lpm/stm32_lpm.o + 0x0800d100 UTIL_LPM_SetStopMode + .text.UTIL_LPM_SetOffMode + 0x0800d160 0x60 ./Utilities/lpm/tiny_lpm/stm32_lpm.o + 0x0800d160 UTIL_LPM_SetOffMode + .text.UTIL_LPM_EnterLowPower + 0x0800d1c0 0x6c ./Utilities/lpm/tiny_lpm/stm32_lpm.o + 0x0800d1c0 UTIL_LPM_EnterLowPower + .text.UTIL_MEM_cpy_8 + 0x0800d22c 0x3e ./Utilities/misc/stm32_mem.o + 0x0800d22c UTIL_MEM_cpy_8 + .text.UTIL_MEM_set_8 + 0x0800d26a 0x36 ./Utilities/misc/stm32_mem.o + 0x0800d26a UTIL_MEM_set_8 + .text.SysTimeAdd + 0x0800d2a0 0x72 ./Utilities/misc/stm32_systime.o + 0x0800d2a0 SysTimeAdd + *fill* 0x0800d312 0x2 + .text.SysTimeGet + 0x0800d314 0x70 ./Utilities/misc/stm32_systime.o + 0x0800d314 SysTimeGet + .text.ee_skip_atoi + 0x0800d384 0x4c ./Utilities/misc/stm32_tiny_vsnprintf.o + .text.ee_number + 0x0800d3d0 0x1dc ./Utilities/misc/stm32_tiny_vsnprintf.o + .text.tiny_vsnprintf_like + 0x0800d5ac 0x2a4 ./Utilities/misc/stm32_tiny_vsnprintf.o + 0x0800d5ac tiny_vsnprintf_like + .text.UTIL_SEQ_Run + 0x0800d850 0x1f8 ./Utilities/sequencer/stm32_seq.o + 0x0800d850 UTIL_SEQ_Run + .text.UTIL_SEQ_PreIdle + 0x0800da48 0xc ./Utilities/sequencer/stm32_seq.o + 0x0800da48 UTIL_SEQ_PreIdle + .text.UTIL_SEQ_PostIdle + 0x0800da54 0xc ./Utilities/sequencer/stm32_seq.o + 0x0800da54 UTIL_SEQ_PostIdle + .text.SEQ_BitPosition + 0x0800da60 0x70 ./Utilities/sequencer/stm32_seq.o + 0x0800da60 SEQ_BitPosition + .text.UTIL_TIMER_Init + 0x0800dad0 0x20 ./Utilities/timer/stm32_timer.o + 0x0800dad0 UTIL_TIMER_Init + .text.UTIL_TIMER_Create + 0x0800daf0 0x6c ./Utilities/timer/stm32_timer.o + 0x0800daf0 UTIL_TIMER_Create + .text.UTIL_TIMER_Start + 0x0800db5c 0xdc ./Utilities/timer/stm32_timer.o + 0x0800db5c UTIL_TIMER_Start + .text.UTIL_TIMER_Stop + 0x0800dc38 0xe0 ./Utilities/timer/stm32_timer.o + 0x0800dc38 UTIL_TIMER_Stop + .text.UTIL_TIMER_SetPeriod + 0x0800dd18 0x54 ./Utilities/timer/stm32_timer.o + 0x0800dd18 UTIL_TIMER_SetPeriod + .text.UTIL_TIMER_IRQ_Handler + 0x0800dd6c 0x100 ./Utilities/timer/stm32_timer.o + 0x0800dd6c UTIL_TIMER_IRQ_Handler + .text.UTIL_TIMER_GetCurrentTime + 0x0800de6c 0x24 ./Utilities/timer/stm32_timer.o + 0x0800de6c UTIL_TIMER_GetCurrentTime + .text.UTIL_TIMER_GetElapsedTime + 0x0800de90 0x38 ./Utilities/timer/stm32_timer.o + 0x0800de90 UTIL_TIMER_GetElapsedTime + .text.TimerExists + 0x0800dec8 0x38 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./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + 0x0800fc08 Bandwidths + *fill* 0x0800fc0b 0x1 + .rodata.FskBandwidths + 0x0800fc0c 0xb0 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + .rodata.SEQ_clz_table_4bit + 0x0800fcbc 0x10 ./Utilities/sequencer/stm32_seq.o + 0x0800fcbc SEQ_clz_table_4bit + .rodata._ctype_ + 0x0800fccc 0x101 /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(libc_a-ctype_.o) + 0x0800fccc _ctype_ + .rodata._svfprintf_r.str1.1 + 0x0800fdcd 0x33 /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(libc_a-nano-svfprintf.o) + 0x11 (size before relaxing) + .rodata._printf_i.str1.1 + 0x0800fe00 0x0 /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(libc_a-nano-vfprintf_i.o) + 0x22 (size before relaxing) + 0x0800fe00 . = ALIGN (0x4) + +.ARM.extab 0x0800fe00 0x0 + 0x0800fe00 . = ALIGN (0x4) + *(.ARM.extab* .gnu.linkonce.armextab.*) + 0x0800fe00 . = ALIGN (0x4) + +.ARM 0x0800fe00 0x8 + 0x0800fe00 . = ALIGN (0x4) + 0x0800fe00 __exidx_start = . + *(.ARM.exidx*) + .ARM.exidx 0x0800fe00 0x8 /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(libc_a-strcmp.o) + .ARM.exidx 0x0800fe08 0x0 /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(libc_a-strlen.o) + 0x8 (size before relaxing) + .ARM.exidx 0x0800fe08 0x0 /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(libc_a-memchr.o) + 0x8 (size before relaxing) + .ARM.exidx 0x0800fe08 0x0 /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m/nofp/libgcc.a(_udivmoddi4.o) + 0x8 (size before relaxing) + 0x0800fe08 __exidx_end = . + 0x0800fe08 . = ALIGN (0x4) + +.preinit_array 0x0800fe08 0x0 + 0x0800fe08 . = ALIGN (0x4) + 0x0800fe08 PROVIDE (__preinit_array_start = .) + *(.preinit_array*) + 0x0800fe08 PROVIDE (__preinit_array_end = .) + 0x0800fe08 . = ALIGN (0x4) + +.init_array 0x0800fe08 0x4 + 0x0800fe08 . = ALIGN (0x4) + 0x0800fe08 PROVIDE (__init_array_start = .) + *(SORT_BY_NAME(.init_array.*)) + *(.init_array*) + .init_array 0x0800fe08 0x4 /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m/nofp/crtbegin.o + 0x0800fe0c PROVIDE (__init_array_end = .) + 0x0800fe0c . = ALIGN (0x4) + +.fini_array 0x0800fe0c 0x4 + 0x0800fe0c . = ALIGN (0x4) + [!provide] PROVIDE (__fini_array_start = .) + *(SORT_BY_NAME(.fini_array.*)) + *(.fini_array*) + .fini_array 0x0800fe0c 0x4 /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m/nofp/crtbegin.o + [!provide] PROVIDE (__fini_array_end = .) + 0x0800fe10 . = ALIGN (0x4) + 0x0800fe10 _sidata = LOADADDR (.data) + +.rel.dyn 0x0800fe10 0x0 + .rel.iplt 0x0800fe10 0x0 /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m/nofp/crtbegin.o + +.data 0x20000000 0x8c load address 0x0800fe10 + 0x20000000 . = ALIGN (0x4) + 0x20000000 _sdata = . + *(.data) + *(.data*) + .data.SystemCoreClock + 0x20000000 0x4 ./Core/Src/system_stm32wlxx.o + 0x20000000 SystemCoreClock + .data.uwTickPrio + 0x20000004 0x4 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.o + 0x20000004 uwTickPrio + .data.MaxPayloadLength + 0x20000008 0x1 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + *fill* 0x20000009 0x3 + .data.g_cfg 0x2000000c 0x20 ./SubGHz_Phy/App/subghz_phy_app.o + .data.lower_digits + 0x2000002c 0x4 ./Utilities/misc/stm32_tiny_vsnprintf.o + .data.upper_digits + 0x20000030 0x4 ./Utilities/misc/stm32_tiny_vsnprintf.o + .data.TaskMask + 0x20000034 0x4 ./Utilities/sequencer/stm32_seq.o + .data.SuperMask + 0x20000038 0x4 ./Utilities/sequencer/stm32_seq.o + .data._impure_ptr + 0x2000003c 0x4 /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(libc_a-impure.o) + 0x2000003c _impure_ptr + .data._impure_data + 0x20000040 0x4c /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(libc_a-impure.o) + 0x20000040 _impure_data + *(.RamFunc) + *(.RamFunc*) + 0x2000008c . = ALIGN (0x4) + 0x2000008c _edata = . + +.igot.plt 0x2000008c 0x0 load address 0x0800fe9c + .igot.plt 0x2000008c 0x0 /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m/nofp/crtbegin.o + 0x2000008c . = ALIGN (0x4) + +.bss 0x2000008c 0xfdc load address 0x0800fe9c + 0x2000008c _sbss = . + 0x2000008c __bss_start__ = _sbss + *(.bss) + .bss 0x2000008c 0x1c /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m/nofp/crtbegin.o + *(.bss*) + .bss.hrtc 0x200000a8 0x38 ./Core/Src/rtc.o + 0x200000a8 hrtc + .bss.hsubghz 0x200000e0 0xc ./Core/Src/subghz.o + 0x200000e0 hsubghz + .bss.SYS_TimerInitialisedFlag + 0x200000ec 0x1 ./Core/Src/sys_app.o + *fill* 0x200000ed 0x3 + .bss.__sbrk_heap_end + 0x200000f0 0x4 ./Core/Src/sysmem.o + .bss.RTC_Initialized + 0x200000f4 0x1 ./Core/Src/timer_if.o + *fill* 0x200000f5 0x3 + .bss.RtcTimerContext + 0x200000f8 0x4 ./Core/Src/timer_if.o + .bss.huart2 0x200000fc 0x94 ./Core/Src/usart.o + 0x200000fc huart2 + .bss.hdma_usart2_tx + 0x20000190 0x60 ./Core/Src/usart.o + 0x20000190 hdma_usart2_tx + .bss.charRx 0x200001f0 0x1 ./Core/Src/usart_if.o + 0x200001f0 charRx + *fill* 0x200001f1 0x3 + .bss.TxCpltCallback + 0x200001f4 0x4 ./Core/Src/usart_if.o + .bss.RxCpltCallback + 0x200001f8 0x4 ./Core/Src/usart_if.o + .bss.RadioBuffer + 0x200001fc 0xff ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + *fill* 0x200002fb 0x1 + .bss.RadioEvents + 0x200002fc 0x4 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + .bss.SubgRf 0x20000300 0x5c ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + 0x20000300 SubgRf + .bss.TxTimeoutTimer + 0x2000035c 0x18 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + 0x2000035c TxTimeoutTimer + .bss.RxTimeoutTimer + 0x20000374 0x18 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + 0x20000374 RxTimeoutTimer + .bss.OperatingMode + 0x2000038c 0x1 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + .bss.PacketType + 0x2000038d 0x1 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + .bss.LoRaHeaderType + 0x2000038e 0x1 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + *fill* 0x2000038f 0x1 + .bss.FrequencyError + 0x20000390 0x4 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x20000390 FrequencyError + .bss.ImageCalibrated + 0x20000394 0x1 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + *fill* 0x20000395 0x3 + .bss.RadioOnDioIrqCb + 0x20000398 0x4 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + .bss.RFWPacket + 0x2000039c 0x54 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.o + .bss.ChunkBuffer + 0x200003f0 0xff ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.o + *fill* 0x200004ef 0x1 + .bss.RxBuffer 0x200004f0 0xff ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.o + *fill* 0x200005ef 0x1 + .bss.RadioEvents + 0x200005f0 0x1c ./SubGHz_Phy/App/subghz_phy_app.o + .bss.g_radio_tx_done + 0x2000060c 0x1 ./SubGHz_Phy/App/subghz_phy_app.o + .bss.g_radio_tx_timeout + 0x2000060d 0x1 ./SubGHz_Phy/App/subghz_phy_app.o + .bss.g_radio_rx_done + 0x2000060e 0x1 ./SubGHz_Phy/App/subghz_phy_app.o + .bss.g_radio_rx_timeout + 0x2000060f 0x1 ./SubGHz_Phy/App/subghz_phy_app.o + .bss.g_radio_rx_error + 0x20000610 0x1 ./SubGHz_Phy/App/subghz_phy_app.o + *fill* 0x20000611 0x1 + .bss.g_last_rx_rssi + 0x20000612 0x2 ./SubGHz_Phy/App/subghz_phy_app.o + .bss.g_last_rx_cfo + 0x20000614 0x1 ./SubGHz_Phy/App/subghz_phy_app.o + .bss.g_radio_busy + 0x20000615 0x1 ./SubGHz_Phy/App/subghz_phy_app.o + .bss.g_radio_needs_rx_restart + 0x20000616 0x1 ./SubGHz_Phy/App/subghz_phy_app.o + *fill* 0x20000617 0x1 + .bss.g_rx_payload + 0x20000618 0xdc ./SubGHz_Phy/App/subghz_phy_app.o + .bss.g_rx_payload_len + 0x200006f4 0x2 ./SubGHz_Phy/App/subghz_phy_app.o + *fill* 0x200006f6 0x2 + .bss.g_tx_queue + 0x200006f8 0x374 ./SubGHz_Phy/App/subghz_phy_app.o + .bss.g_tx_q_head + 0x20000a6c 0x1 ./SubGHz_Phy/App/subghz_phy_app.o + .bss.g_tx_q_tail + 0x20000a6d 0x1 ./SubGHz_Phy/App/subghz_phy_app.o + .bss.g_tx_q_count + 0x20000a6e 0x1 ./SubGHz_Phy/App/subghz_phy_app.o + *fill* 0x20000a6f 0x1 + .bss.g_uart_build_buf + 0x20000a70 0xdc ./SubGHz_Phy/App/subghz_phy_app.o + .bss.g_uart_build_len + 0x20000b4c 0x2 ./SubGHz_Phy/App/subghz_phy_app.o + *fill* 0x20000b4e 0x2 + .bss.g_uart_last_data_tick + 0x20000b50 0x4 ./SubGHz_Phy/App/subghz_phy_app.o + .bss.g_escape 0x20000b54 0x10 ./SubGHz_Phy/App/subghz_phy_app.o + .bss.g_mode 0x20000b64 0x1 ./SubGHz_Phy/App/subghz_phy_app.o + *fill* 0x20000b65 0x3 + .bss.g_cfg_line + 0x20000b68 0x60 ./SubGHz_Phy/App/subghz_phy_app.o + .bss.g_cfg_line_len + 0x20000bc8 0x2 ./SubGHz_Phy/App/subghz_phy_app.o + *fill* 0x20000bca 0x2 + .bss.g_stat_uart_packets_tx + 0x20000bcc 0x4 ./SubGHz_Phy/App/subghz_phy_app.o + .bss.g_stat_uart_bytes_tx + 0x20000bd0 0x4 ./SubGHz_Phy/App/subghz_phy_app.o + .bss.g_stat_radio_packets_rx + 0x20000bd4 0x4 ./SubGHz_Phy/App/subghz_phy_app.o + .bss.g_stat_radio_bytes_rx + 0x20000bd8 0x4 ./SubGHz_Phy/App/subghz_phy_app.o + .bss.g_stat_queue_overflow + 0x20000bdc 0x4 ./SubGHz_Phy/App/subghz_phy_app.o + .bss.StopModeDisable + 0x20000be0 0x4 ./Utilities/lpm/tiny_lpm/stm32_lpm.o + .bss.OffModeDisable + 0x20000be4 0x4 ./Utilities/lpm/tiny_lpm/stm32_lpm.o + .bss.TaskSet 0x20000be8 0x4 ./Utilities/sequencer/stm32_seq.o + .bss.EvtSet 0x20000bec 0x4 ./Utilities/sequencer/stm32_seq.o + .bss.EvtWaited + 0x20000bf0 0x4 ./Utilities/sequencer/stm32_seq.o + .bss.CurrentTaskIdx + 0x20000bf4 0x4 ./Utilities/sequencer/stm32_seq.o + .bss.TaskCb 0x20000bf8 0x4 ./Utilities/sequencer/stm32_seq.o + .bss.TaskPrio 0x20000bfc 0x8 ./Utilities/sequencer/stm32_seq.o + .bss.TimerListHead + 0x20000c04 0x4 ./Utilities/timer/stm32_timer.o + .bss.ADV_TRACE_Ctx + 0x20000c08 0x18 ./Utilities/trace/adv_trace/stm32_adv_trace.o + .bss.ADV_TRACE_Buffer + 0x20000c20 0x200 ./Utilities/trace/adv_trace/stm32_adv_trace.o + .bss.sztmp 0x20000e20 0x100 ./Utilities/trace/adv_trace/stm32_adv_trace.o + .bss.__sf 0x20000f20 0x138 /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(libc_a-findfp.o) + 0x20000f20 __sf + .bss.errno 0x20001058 0x4 /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(libc_a-reent.o) + 0x20001058 errno + .bss.__lock___malloc_recursive_mutex + 0x2000105c 0x1 /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(libc_a-lock.o) + 0x2000105c __lock___malloc_recursive_mutex + *fill* 0x2000105d 0x3 + .bss.__malloc_sbrk_start + 0x20001060 0x4 /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(libc_a-mallocr.o) + 0x20001060 __malloc_sbrk_start + .bss.__malloc_free_list + 0x20001064 0x4 /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(libc_a-mallocr.o) + 0x20001064 __malloc_free_list + *(COMMON) + 0x20001068 . = ALIGN (0x4) + 0x20001068 _ebss = . + 0x20001068 __bss_end__ = _ebss + +._user_heap_stack + 0x20001068 0xa00 load address 0x0800fe9c + 0x20001068 . = ALIGN (0x8) + [!provide] PROVIDE (end = .) + 0x20001068 PROVIDE (_end = .) + 0x20001268 . = (. + _Min_Heap_Size) + *fill* 0x20001068 0x200 + 0x20001a68 . = (. + _Min_Stack_Size) + *fill* 0x20001268 0x800 + 0x20001a68 . = ALIGN (0x8) + +/DISCARD/ + libc.a(*) + libm.a(*) + libgcc.a(*) + +.ARM.attributes + 0x00000000 0x2a + *(.ARM.attributes) + .ARM.attributes + 0x00000000 0x1e /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m/nofp/crti.o + .ARM.attributes + 0x0000001e 0x2e /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m/nofp/crtbegin.o + .ARM.attributes + 0x0000004c 0x2e ./Core/Src/dma.o + .ARM.attributes + 0x0000007a 0x2e ./Core/Src/gpio.o + .ARM.attributes + 0x000000a8 0x2e ./Core/Src/main.o + .ARM.attributes + 0x000000d6 0x2e ./Core/Src/rtc.o + .ARM.attributes + 0x00000104 0x2e ./Core/Src/stm32_lpm_if.o + .ARM.attributes + 0x00000132 0x2e ./Core/Src/stm32wlxx_hal_msp.o + .ARM.attributes + 0x00000160 0x2e ./Core/Src/stm32wlxx_it.o + .ARM.attributes + 0x0000018e 0x2e ./Core/Src/subghz.o + .ARM.attributes + 0x000001bc 0x2e ./Core/Src/sys_app.o + .ARM.attributes + 0x000001ea 0x2e ./Core/Src/sys_debug.o + .ARM.attributes + 0x00000218 0x2e ./Core/Src/sysmem.o + .ARM.attributes + 0x00000246 0x2e ./Core/Src/system_stm32wlxx.o + .ARM.attributes + 0x00000274 0x2e ./Core/Src/timer_if.o + .ARM.attributes + 0x000002a2 0x2e ./Core/Src/usart.o + .ARM.attributes + 0x000002d0 0x2e ./Core/Src/usart_if.o + .ARM.attributes + 0x000002fe 0x21 ./Core/Startup/startup_stm32wl55jcix.o + .ARM.attributes + 0x0000031f 0x2e ./Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo_radio.o + .ARM.attributes + 0x0000034d 0x2e ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.o + .ARM.attributes + 0x0000037b 0x2e ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.o + .ARM.attributes + 0x000003a9 0x2e ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.o + .ARM.attributes + 0x000003d7 0x2e ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_gpio.o + .ARM.attributes + 0x00000405 0x2e ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.o + .ARM.attributes + 0x00000433 0x2e ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.o + .ARM.attributes + 0x00000461 0x2e ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.o + .ARM.attributes + 0x0000048f 0x2e ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.o + .ARM.attributes + 0x000004bd 0x2e ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.o + .ARM.attributes + 0x000004eb 0x2e ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.o + .ARM.attributes + 0x00000519 0x2e ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.o + .ARM.attributes + 0x00000547 0x2e ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.o + .ARM.attributes + 0x00000575 0x2e ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.o + .ARM.attributes + 0x000005a3 0x2e ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + .ARM.attributes + 0x000005d1 0x2e ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + .ARM.attributes + 0x000005ff 0x2e ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.o + .ARM.attributes + 0x0000062d 0x2e ./SubGHz_Phy/App/app_subghz_phy.o + .ARM.attributes + 0x0000065b 0x2e ./SubGHz_Phy/App/subghz_phy_app.o + .ARM.attributes + 0x00000689 0x2e ./SubGHz_Phy/Target/radio_board_if.o + .ARM.attributes + 0x000006b7 0x2e ./Utilities/lpm/tiny_lpm/stm32_lpm.o + .ARM.attributes + 0x000006e5 0x2e ./Utilities/misc/stm32_mem.o + .ARM.attributes + 0x00000713 0x2e ./Utilities/misc/stm32_systime.o + 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/opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(libc_a-ctype_.o) + .ARM.attributes + 0x00000883 0x2e /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(libc_a-findfp.o) + .ARM.attributes + 0x000008b1 0x2e /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(libc_a-vsnprintf.o) + .ARM.attributes + 0x000008df 0x2e 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/opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m/nofp/libgcc.a(_udivmoddi4.o) + .ARM.attributes + 0x00000c88 0x1e /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m/nofp/libgcc.a(_dvmd_tls.o) + .ARM.attributes + 0x00000ca6 0x1e /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m/nofp/crtn.o +OUTPUT(SubGHz_Phy_Per_My_Test.elf elf32-littlearm) +LOAD linker stubs +LOAD /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc.a +LOAD /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libm.a +LOAD /opt/st/stm32cubeide_2.0.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m/nofp/libgcc.a + +.debug_info 0x00000000 0x24226 + .debug_info 0x00000000 0x642 ./Core/Src/dma.o + .debug_info 0x00000642 0x7cf ./Core/Src/gpio.o + .debug_info 0x00000e11 0x8a2 ./Core/Src/main.o + .debug_info 0x000016b3 0xc77 ./Core/Src/rtc.o + .debug_info 0x0000232a 0x35c ./Core/Src/stm32_lpm_if.o + .debug_info 0x00002686 0xce ./Core/Src/stm32wlxx_hal_msp.o + .debug_info 0x00002754 0xd06 ./Core/Src/stm32wlxx_it.o + .debug_info 0x0000345a 0x7f8 ./Core/Src/subghz.o + .debug_info 0x00003c52 0x841 ./Core/Src/sys_app.o + .debug_info 0x00004493 0x794 ./Core/Src/sys_debug.o + .debug_info 0x00004c27 0x168 ./Core/Src/sysmem.o + .debug_info 0x00004d8f 0x515 ./Core/Src/system_stm32wlxx.o + .debug_info 0x000052a4 0xbc3 ./Core/Src/timer_if.o + .debug_info 0x00005e67 0x1144 ./Core/Src/usart.o + .debug_info 0x00006fab 0x130f ./Core/Src/usart_if.o + .debug_info 0x000082ba 0x30 ./Core/Startup/startup_stm32wl55jcix.o + .debug_info 0x000082ea 0x70c ./Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo_radio.o + .debug_info 0x000089f6 0x116a ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.o + .debug_info 0x00009b60 0xd39 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.o + .debug_info 0x0000a899 0x91b ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.o + .debug_info 0x0000b1b4 0x717 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_gpio.o + .debug_info 0x0000b8cb 0x8ed ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.o + .debug_info 0x0000c1b8 0xdec ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.o + .debug_info 0x0000cfa4 0x13f4 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.o + .debug_info 0x0000e398 0xf21 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.o + .debug_info 0x0000f2b9 0xefa ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.o + .debug_info 0x000101b3 0x14a6 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.o + .debug_info 0x00011659 0x1397 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.o + .debug_info 0x000129f0 0x4a46 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.o + .debug_info 0x00017436 0x1003 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.o + .debug_info 0x00018439 0x2e4f ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + .debug_info 0x0001b288 0x22ae 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0000000..443e7e1 --- /dev/null +++ b/Debug/Utilities/lpm/tiny_lpm/stm32_lpm.cyclo @@ -0,0 +1,6 @@ +../Utilities/lpm/tiny_lpm/stm32_lpm.c:121:6:UTIL_LPM_Init 1 +../Utilities/lpm/tiny_lpm/stm32_lpm.c:128:6:UTIL_LPM_DeInit 1 +../Utilities/lpm/tiny_lpm/stm32_lpm.c:132:6:UTIL_LPM_SetStopMode 3 +../Utilities/lpm/tiny_lpm/stm32_lpm.c:157:6:UTIL_LPM_SetOffMode 3 +../Utilities/lpm/tiny_lpm/stm32_lpm.c:182:17:UTIL_LPM_GetMode 3 +../Utilities/lpm/tiny_lpm/stm32_lpm.c:215:6:UTIL_LPM_EnterLowPower 3 diff --git a/Debug/Utilities/lpm/tiny_lpm/stm32_lpm.d b/Debug/Utilities/lpm/tiny_lpm/stm32_lpm.d new file mode 100644 index 0000000..31852d7 --- /dev/null +++ b/Debug/Utilities/lpm/tiny_lpm/stm32_lpm.d @@ -0,0 +1,12 @@ +Utilities/lpm/tiny_lpm/stm32_lpm.o: ../Utilities/lpm/tiny_lpm/stm32_lpm.c \ + ../Utilities/lpm/tiny_lpm/stm32_lpm.h ../Core/Inc/utilities_conf.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h ../Utilities/misc/stm32_mem.h \ + ../Utilities/misc/stm32_tiny_vsnprintf.h ../Core/Inc/utilities_def.h +../Utilities/lpm/tiny_lpm/stm32_lpm.h: +../Core/Inc/utilities_conf.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Utilities/misc/stm32_mem.h: +../Utilities/misc/stm32_tiny_vsnprintf.h: +../Core/Inc/utilities_def.h: diff --git a/Debug/Utilities/lpm/tiny_lpm/stm32_lpm.o b/Debug/Utilities/lpm/tiny_lpm/stm32_lpm.o new file mode 100644 index 0000000..1fdfd38 Binary files /dev/null and b/Debug/Utilities/lpm/tiny_lpm/stm32_lpm.o differ diff --git a/Debug/Utilities/lpm/tiny_lpm/stm32_lpm.su b/Debug/Utilities/lpm/tiny_lpm/stm32_lpm.su new file mode 100644 index 0000000..22578f4 --- /dev/null +++ b/Debug/Utilities/lpm/tiny_lpm/stm32_lpm.su @@ -0,0 +1,6 @@ +../Utilities/lpm/tiny_lpm/stm32_lpm.c:121:6:UTIL_LPM_Init 4 static +../Utilities/lpm/tiny_lpm/stm32_lpm.c:128:6:UTIL_LPM_DeInit 4 static +../Utilities/lpm/tiny_lpm/stm32_lpm.c:132:6:UTIL_LPM_SetStopMode 32 static,ignoring_inline_asm +../Utilities/lpm/tiny_lpm/stm32_lpm.c:157:6:UTIL_LPM_SetOffMode 32 static,ignoring_inline_asm +../Utilities/lpm/tiny_lpm/stm32_lpm.c:182:17:UTIL_LPM_GetMode 24 static,ignoring_inline_asm +../Utilities/lpm/tiny_lpm/stm32_lpm.c:215:6:UTIL_LPM_EnterLowPower 24 static,ignoring_inline_asm diff --git a/Debug/Utilities/lpm/tiny_lpm/subdir.mk b/Debug/Utilities/lpm/tiny_lpm/subdir.mk new file mode 100644 index 0000000..5e95660 --- /dev/null +++ b/Debug/Utilities/lpm/tiny_lpm/subdir.mk @@ -0,0 +1,27 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (13.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Utilities/lpm/tiny_lpm/stm32_lpm.c + +OBJS += \ +./Utilities/lpm/tiny_lpm/stm32_lpm.o + +C_DEPS += \ +./Utilities/lpm/tiny_lpm/stm32_lpm.d + + +# Each subdirectory must supply rules for building sources it contributes +Utilities/lpm/tiny_lpm/%.o Utilities/lpm/tiny_lpm/%.su Utilities/lpm/tiny_lpm/%.cyclo: ../Utilities/lpm/tiny_lpm/%.c Utilities/lpm/tiny_lpm/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WL55xx -c -I../Core/Inc -I../SubGHz_Phy/App -I../SubGHz_Phy/Target -I../Utilities/trace/adv_trace -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Utilities/misc -I../Utilities/sequencer -I../Utilities/timer -I../Utilities/lpm/tiny_lpm -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Middlewares/Third_Party/SubGHz_Phy -I../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver -I../Drivers/CMSIS/Include -I../Drivers/BSP/STM32WLxx_Nucleo -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Utilities-2f-lpm-2f-tiny_lpm + +clean-Utilities-2f-lpm-2f-tiny_lpm: + -$(RM) ./Utilities/lpm/tiny_lpm/stm32_lpm.cyclo ./Utilities/lpm/tiny_lpm/stm32_lpm.d ./Utilities/lpm/tiny_lpm/stm32_lpm.o ./Utilities/lpm/tiny_lpm/stm32_lpm.su + +.PHONY: clean-Utilities-2f-lpm-2f-tiny_lpm + diff --git a/Debug/Utilities/misc/stm32_mem.cyclo b/Debug/Utilities/misc/stm32_mem.cyclo new file mode 100644 index 0000000..5de88d4 --- /dev/null +++ b/Debug/Utilities/misc/stm32_mem.cyclo @@ -0,0 +1,3 @@ +../Utilities/misc/stm32_mem.c:31:6:UTIL_MEM_cpy_8 2 +../Utilities/misc/stm32_mem.c:42:6:UTIL_MEM_cpyr_8 2 +../Utilities/misc/stm32_mem.c:54:6:UTIL_MEM_set_8 2 diff --git a/Debug/Utilities/misc/stm32_mem.d b/Debug/Utilities/misc/stm32_mem.d new file mode 100644 index 0000000..aa500c7 --- /dev/null +++ b/Debug/Utilities/misc/stm32_mem.d @@ -0,0 +1,12 @@ +Utilities/misc/stm32_mem.o: ../Utilities/misc/stm32_mem.c \ + ../Utilities/misc/stm32_mem.h ../Core/Inc/utilities_conf.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h ../Utilities/misc/stm32_mem.h \ + ../Utilities/misc/stm32_tiny_vsnprintf.h ../Core/Inc/utilities_def.h +../Utilities/misc/stm32_mem.h: +../Core/Inc/utilities_conf.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Utilities/misc/stm32_mem.h: +../Utilities/misc/stm32_tiny_vsnprintf.h: +../Core/Inc/utilities_def.h: diff --git a/Debug/Utilities/misc/stm32_mem.o b/Debug/Utilities/misc/stm32_mem.o new file mode 100644 index 0000000..ea33661 Binary files /dev/null and b/Debug/Utilities/misc/stm32_mem.o differ diff --git a/Debug/Utilities/misc/stm32_mem.su b/Debug/Utilities/misc/stm32_mem.su new file mode 100644 index 0000000..90d582e --- /dev/null +++ b/Debug/Utilities/misc/stm32_mem.su @@ -0,0 +1,3 @@ +../Utilities/misc/stm32_mem.c:31:6:UTIL_MEM_cpy_8 32 static +../Utilities/misc/stm32_mem.c:42:6:UTIL_MEM_cpyr_8 32 static +../Utilities/misc/stm32_mem.c:54:6:UTIL_MEM_set_8 24 static diff --git a/Debug/Utilities/misc/stm32_systime.cyclo b/Debug/Utilities/misc/stm32_systime.cyclo new file mode 100644 index 0000000..b43fd35 --- /dev/null +++ b/Debug/Utilities/misc/stm32_systime.cyclo @@ -0,0 +1,13 @@ +../Utilities/misc/stm32_systime.c:199:11:SysTimeAdd 2 +../Utilities/misc/stm32_systime.c:213:11:SysTimeSub 2 +../Utilities/misc/stm32_systime.c:227:6:SysTimeSet 1 +../Utilities/misc/stm32_systime.c:242:11:SysTimeGet 1 +../Utilities/misc/stm32_systime.c:259:11:SysTimeGetMcuTime 1 +../Utilities/misc/stm32_systime.c:268:10:SysTimeToMs 1 +../Utilities/misc/stm32_systime.c:278:11:SysTimeFromMs 1 +../Utilities/misc/stm32_systime.c:289:10:SysTimeMkTime 1 +../Utilities/misc/stm32_systime.c:318:6:SysTimeLocalTime 1 +../Utilities/misc/stm32_systime.c:381:17:CalendarGetMonth 6 +../Utilities/misc/stm32_systime.c:418:13:CalendarDiv86400 3 +../Utilities/misc/stm32_systime.c:444:17:CalendarDiv61 3 +../Utilities/misc/stm32_systime.c:466:13:CalendarDiv60 3 diff --git a/Debug/Utilities/misc/stm32_systime.d b/Debug/Utilities/misc/stm32_systime.d new file mode 100644 index 0000000..b6045b2 --- /dev/null +++ b/Debug/Utilities/misc/stm32_systime.d @@ -0,0 +1,3 @@ +Utilities/misc/stm32_systime.o: ../Utilities/misc/stm32_systime.c \ + ../Utilities/misc/stm32_systime.h +../Utilities/misc/stm32_systime.h: diff --git a/Debug/Utilities/misc/stm32_systime.o b/Debug/Utilities/misc/stm32_systime.o new file mode 100644 index 0000000..5ad731b Binary files /dev/null and b/Debug/Utilities/misc/stm32_systime.o differ diff --git a/Debug/Utilities/misc/stm32_systime.su b/Debug/Utilities/misc/stm32_systime.su new file mode 100644 index 0000000..03ceef9 --- /dev/null +++ b/Debug/Utilities/misc/stm32_systime.su @@ -0,0 +1,13 @@ +../Utilities/misc/stm32_systime.c:199:11:SysTimeAdd 32 static +../Utilities/misc/stm32_systime.c:213:11:SysTimeSub 32 static +../Utilities/misc/stm32_systime.c:227:6:SysTimeSet 40 static +../Utilities/misc/stm32_systime.c:242:11:SysTimeGet 48 static +../Utilities/misc/stm32_systime.c:259:11:SysTimeGetMcuTime 24 static +../Utilities/misc/stm32_systime.c:268:10:SysTimeToMs 40 static +../Utilities/misc/stm32_systime.c:278:11:SysTimeFromMs 48 static +../Utilities/misc/stm32_systime.c:289:10:SysTimeMkTime 48 static +../Utilities/misc/stm32_systime.c:318:6:SysTimeLocalTime 64 static +../Utilities/misc/stm32_systime.c:381:17:CalendarGetMonth 24 static +../Utilities/misc/stm32_systime.c:418:13:CalendarDiv86400 32 static +../Utilities/misc/stm32_systime.c:444:17:CalendarDiv61 24 static +../Utilities/misc/stm32_systime.c:466:13:CalendarDiv60 32 static diff --git a/Debug/Utilities/misc/stm32_tiny_sscanf.cyclo b/Debug/Utilities/misc/stm32_tiny_sscanf.cyclo new file mode 100644 index 0000000..1de6a73 --- /dev/null +++ b/Debug/Utilities/misc/stm32_tiny_sscanf.cyclo @@ -0,0 +1,2 @@ +../Utilities/misc/stm32_tiny_sscanf.c:152:1:tiny_vfscanf 39 +../Utilities/misc/stm32_tiny_sscanf.c:983:1:tiny_sscanf 1 diff --git a/Debug/Utilities/misc/stm32_tiny_sscanf.d b/Debug/Utilities/misc/stm32_tiny_sscanf.d new file mode 100644 index 0000000..fcb8a55 --- /dev/null +++ b/Debug/Utilities/misc/stm32_tiny_sscanf.d @@ -0,0 +1,3 @@ +Utilities/misc/stm32_tiny_sscanf.o: ../Utilities/misc/stm32_tiny_sscanf.c \ + ../Utilities/misc/stm32_tiny_sscanf.h +../Utilities/misc/stm32_tiny_sscanf.h: diff --git a/Debug/Utilities/misc/stm32_tiny_sscanf.o b/Debug/Utilities/misc/stm32_tiny_sscanf.o new file mode 100644 index 0000000..cc34a3d Binary files /dev/null and b/Debug/Utilities/misc/stm32_tiny_sscanf.o differ diff --git a/Debug/Utilities/misc/stm32_tiny_sscanf.su b/Debug/Utilities/misc/stm32_tiny_sscanf.su new file mode 100644 index 0000000..7b09c51 --- /dev/null +++ b/Debug/Utilities/misc/stm32_tiny_sscanf.su @@ -0,0 +1,2 @@ +../Utilities/misc/stm32_tiny_sscanf.c:152:1:tiny_vfscanf 720 static +../Utilities/misc/stm32_tiny_sscanf.c:983:1:tiny_sscanf 28 static diff --git a/Debug/Utilities/misc/stm32_tiny_vsnprintf.cyclo b/Debug/Utilities/misc/stm32_tiny_vsnprintf.cyclo new file mode 100644 index 0000000..8234188 --- /dev/null +++ b/Debug/Utilities/misc/stm32_tiny_vsnprintf.cyclo @@ -0,0 +1,3 @@ +../Utilities/misc/stm32_tiny_vsnprintf.c:91:12:ee_skip_atoi 3 +../Utilities/misc/stm32_tiny_vsnprintf.c:100:14:ee_number 23 +../Utilities/misc/stm32_tiny_vsnprintf.c:485:5:tiny_vsnprintf_like 25 diff --git a/Debug/Utilities/misc/stm32_tiny_vsnprintf.d b/Debug/Utilities/misc/stm32_tiny_vsnprintf.d new file mode 100644 index 0000000..68bbb5b --- /dev/null +++ b/Debug/Utilities/misc/stm32_tiny_vsnprintf.d @@ -0,0 +1,4 @@ +Utilities/misc/stm32_tiny_vsnprintf.o: \ + ../Utilities/misc/stm32_tiny_vsnprintf.c \ + ../Utilities/misc/stm32_tiny_vsnprintf.h +../Utilities/misc/stm32_tiny_vsnprintf.h: diff --git a/Debug/Utilities/misc/stm32_tiny_vsnprintf.o b/Debug/Utilities/misc/stm32_tiny_vsnprintf.o new file mode 100644 index 0000000..1b32cff Binary files /dev/null and b/Debug/Utilities/misc/stm32_tiny_vsnprintf.o differ diff --git a/Debug/Utilities/misc/stm32_tiny_vsnprintf.su b/Debug/Utilities/misc/stm32_tiny_vsnprintf.su new file mode 100644 index 0000000..dcaa3ff --- /dev/null +++ b/Debug/Utilities/misc/stm32_tiny_vsnprintf.su @@ -0,0 +1,3 @@ +../Utilities/misc/stm32_tiny_vsnprintf.c:91:12:ee_skip_atoi 24 static +../Utilities/misc/stm32_tiny_vsnprintf.c:100:14:ee_number 104 static +../Utilities/misc/stm32_tiny_vsnprintf.c:485:5:tiny_vsnprintf_like 80 static diff --git a/Debug/Utilities/misc/subdir.mk b/Debug/Utilities/misc/subdir.mk new file mode 100644 index 0000000..4a1947e --- /dev/null +++ b/Debug/Utilities/misc/subdir.mk @@ -0,0 +1,36 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (13.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Utilities/misc/stm32_mem.c \ +../Utilities/misc/stm32_systime.c \ +../Utilities/misc/stm32_tiny_sscanf.c \ +../Utilities/misc/stm32_tiny_vsnprintf.c + +OBJS += \ +./Utilities/misc/stm32_mem.o \ +./Utilities/misc/stm32_systime.o \ +./Utilities/misc/stm32_tiny_sscanf.o \ +./Utilities/misc/stm32_tiny_vsnprintf.o + +C_DEPS += \ +./Utilities/misc/stm32_mem.d \ +./Utilities/misc/stm32_systime.d \ +./Utilities/misc/stm32_tiny_sscanf.d \ +./Utilities/misc/stm32_tiny_vsnprintf.d + + +# Each subdirectory must supply rules for building sources it contributes +Utilities/misc/%.o Utilities/misc/%.su Utilities/misc/%.cyclo: ../Utilities/misc/%.c Utilities/misc/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WL55xx -c -I../Core/Inc -I../SubGHz_Phy/App -I../SubGHz_Phy/Target -I../Utilities/trace/adv_trace -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Utilities/misc -I../Utilities/sequencer -I../Utilities/timer -I../Utilities/lpm/tiny_lpm -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Middlewares/Third_Party/SubGHz_Phy -I../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver -I../Drivers/CMSIS/Include -I../Drivers/BSP/STM32WLxx_Nucleo -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Utilities-2f-misc + +clean-Utilities-2f-misc: + -$(RM) ./Utilities/misc/stm32_mem.cyclo ./Utilities/misc/stm32_mem.d ./Utilities/misc/stm32_mem.o ./Utilities/misc/stm32_mem.su ./Utilities/misc/stm32_systime.cyclo ./Utilities/misc/stm32_systime.d ./Utilities/misc/stm32_systime.o ./Utilities/misc/stm32_systime.su ./Utilities/misc/stm32_tiny_sscanf.cyclo ./Utilities/misc/stm32_tiny_sscanf.d ./Utilities/misc/stm32_tiny_sscanf.o ./Utilities/misc/stm32_tiny_sscanf.su ./Utilities/misc/stm32_tiny_vsnprintf.cyclo ./Utilities/misc/stm32_tiny_vsnprintf.d ./Utilities/misc/stm32_tiny_vsnprintf.o ./Utilities/misc/stm32_tiny_vsnprintf.su + +.PHONY: clean-Utilities-2f-misc + diff --git a/Debug/Utilities/sequencer/stm32_seq.cyclo b/Debug/Utilities/sequencer/stm32_seq.cyclo new file mode 100644 index 0000000..7c0fa9b --- /dev/null +++ b/Debug/Utilities/sequencer/stm32_seq.cyclo @@ -0,0 +1,18 @@ +../Utilities/sequencer/stm32_seq.c:180:6:UTIL_SEQ_Init 2 +../Utilities/sequencer/stm32_seq.c:197:6:UTIL_SEQ_DeInit 1 +../Utilities/sequencer/stm32_seq.c:207:6:UTIL_SEQ_Run 8 +../Utilities/sequencer/stm32_seq.c:323:6:UTIL_SEQ_RegTask 1 +../Utilities/sequencer/stm32_seq.c:335:6:UTIL_SEQ_SetTask 1 +../Utilities/sequencer/stm32_seq.c:347:10:UTIL_SEQ_IsSchedulableTask 2 +../Utilities/sequencer/stm32_seq.c:361:6:UTIL_SEQ_PauseTask 1 +../Utilities/sequencer/stm32_seq.c:372:10:UTIL_SEQ_IsPauseTask 1 +../Utilities/sequencer/stm32_seq.c:383:6:UTIL_SEQ_ResumeTask 1 +../Utilities/sequencer/stm32_seq.c:394:6:UTIL_SEQ_SetEvt 1 +../Utilities/sequencer/stm32_seq.c:405:6:UTIL_SEQ_ClrEvt 1 +../Utilities/sequencer/stm32_seq.c:416:6:UTIL_SEQ_WaitEvt 3 +../Utilities/sequencer/stm32_seq.c:469:15:UTIL_SEQ_IsEvtPend 1 +../Utilities/sequencer/stm32_seq.c:475:13:UTIL_SEQ_EvtIdle 1 +../Utilities/sequencer/stm32_seq.c:482:13:UTIL_SEQ_Idle 1 +../Utilities/sequencer/stm32_seq.c:487:13:UTIL_SEQ_PreIdle 1 +../Utilities/sequencer/stm32_seq.c:495:13:UTIL_SEQ_PostIdle 1 +../Utilities/sequencer/stm32_seq.c:518:9:SEQ_BitPosition 4 diff --git a/Debug/Utilities/sequencer/stm32_seq.d b/Debug/Utilities/sequencer/stm32_seq.d new file mode 100644 index 0000000..a960a74 --- /dev/null +++ b/Debug/Utilities/sequencer/stm32_seq.d @@ -0,0 +1,12 @@ +Utilities/sequencer/stm32_seq.o: ../Utilities/sequencer/stm32_seq.c \ + ../Utilities/sequencer/stm32_seq.h ../Core/Inc/utilities_conf.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h ../Utilities/misc/stm32_mem.h \ + ../Utilities/misc/stm32_tiny_vsnprintf.h ../Core/Inc/utilities_def.h +../Utilities/sequencer/stm32_seq.h: +../Core/Inc/utilities_conf.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Utilities/misc/stm32_mem.h: +../Utilities/misc/stm32_tiny_vsnprintf.h: +../Core/Inc/utilities_def.h: diff --git a/Debug/Utilities/sequencer/stm32_seq.o b/Debug/Utilities/sequencer/stm32_seq.o new file mode 100644 index 0000000..cec5d37 Binary files /dev/null and b/Debug/Utilities/sequencer/stm32_seq.o differ diff --git a/Debug/Utilities/sequencer/stm32_seq.su b/Debug/Utilities/sequencer/stm32_seq.su new file mode 100644 index 0000000..04dcb9e --- /dev/null +++ b/Debug/Utilities/sequencer/stm32_seq.su @@ -0,0 +1,18 @@ +../Utilities/sequencer/stm32_seq.c:180:6:UTIL_SEQ_Init 16 static +../Utilities/sequencer/stm32_seq.c:197:6:UTIL_SEQ_DeInit 4 static +../Utilities/sequencer/stm32_seq.c:207:6:UTIL_SEQ_Run 72 static,ignoring_inline_asm +../Utilities/sequencer/stm32_seq.c:323:6:UTIL_SEQ_RegTask 40 static,ignoring_inline_asm +../Utilities/sequencer/stm32_seq.c:335:6:UTIL_SEQ_SetTask 32 static,ignoring_inline_asm +../Utilities/sequencer/stm32_seq.c:347:10:UTIL_SEQ_IsSchedulableTask 40 static,ignoring_inline_asm +../Utilities/sequencer/stm32_seq.c:361:6:UTIL_SEQ_PauseTask 32 static,ignoring_inline_asm +../Utilities/sequencer/stm32_seq.c:372:10:UTIL_SEQ_IsPauseTask 32 static,ignoring_inline_asm +../Utilities/sequencer/stm32_seq.c:383:6:UTIL_SEQ_ResumeTask 32 static,ignoring_inline_asm +../Utilities/sequencer/stm32_seq.c:394:6:UTIL_SEQ_SetEvt 32 static,ignoring_inline_asm +../Utilities/sequencer/stm32_seq.c:405:6:UTIL_SEQ_ClrEvt 32 static,ignoring_inline_asm +../Utilities/sequencer/stm32_seq.c:416:6:UTIL_SEQ_WaitEvt 40 static,ignoring_inline_asm +../Utilities/sequencer/stm32_seq.c:469:15:UTIL_SEQ_IsEvtPend 16 static +../Utilities/sequencer/stm32_seq.c:475:13:UTIL_SEQ_EvtIdle 16 static +../Utilities/sequencer/stm32_seq.c:482:13:UTIL_SEQ_Idle 4 static +../Utilities/sequencer/stm32_seq.c:487:13:UTIL_SEQ_PreIdle 4 static +../Utilities/sequencer/stm32_seq.c:495:13:UTIL_SEQ_PostIdle 4 static +../Utilities/sequencer/stm32_seq.c:518:9:SEQ_BitPosition 24 static diff --git a/Debug/Utilities/sequencer/subdir.mk b/Debug/Utilities/sequencer/subdir.mk new file mode 100644 index 0000000..aa905f2 --- /dev/null +++ b/Debug/Utilities/sequencer/subdir.mk @@ -0,0 +1,27 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (13.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Utilities/sequencer/stm32_seq.c + +OBJS += \ +./Utilities/sequencer/stm32_seq.o + +C_DEPS += \ +./Utilities/sequencer/stm32_seq.d + + +# Each subdirectory must supply rules for building sources it contributes +Utilities/sequencer/%.o Utilities/sequencer/%.su Utilities/sequencer/%.cyclo: ../Utilities/sequencer/%.c Utilities/sequencer/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WL55xx -c -I../Core/Inc -I../SubGHz_Phy/App -I../SubGHz_Phy/Target -I../Utilities/trace/adv_trace -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Utilities/misc -I../Utilities/sequencer -I../Utilities/timer -I../Utilities/lpm/tiny_lpm -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Middlewares/Third_Party/SubGHz_Phy -I../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver -I../Drivers/CMSIS/Include -I../Drivers/BSP/STM32WLxx_Nucleo -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Utilities-2f-sequencer + +clean-Utilities-2f-sequencer: + -$(RM) ./Utilities/sequencer/stm32_seq.cyclo ./Utilities/sequencer/stm32_seq.d ./Utilities/sequencer/stm32_seq.o ./Utilities/sequencer/stm32_seq.su + +.PHONY: clean-Utilities-2f-sequencer + diff --git a/Debug/Utilities/timer/stm32_timer.cyclo b/Debug/Utilities/timer/stm32_timer.cyclo new file mode 100644 index 0000000..bcd3371 --- /dev/null +++ b/Debug/Utilities/timer/stm32_timer.cyclo @@ -0,0 +1,19 @@ +../Utilities/timer/stm32_timer.c:116:21:UTIL_TIMER_Init 1 +../Utilities/timer/stm32_timer.c:123:21:UTIL_TIMER_DeInit 1 +../Utilities/timer/stm32_timer.c:128:21:UTIL_TIMER_Create 3 +../Utilities/timer/stm32_timer.c:149:21:UTIL_TIMER_Start 7 +../Utilities/timer/stm32_timer.c:199:21:UTIL_TIMER_StartWithPeriod 3 +../Utilities/timer/stm32_timer.c:219:21:UTIL_TIMER_Stop 8 +../Utilities/timer/stm32_timer.c:285:21:UTIL_TIMER_SetPeriod 3 +../Utilities/timer/stm32_timer.c:305:21:UTIL_TIMER_SetReloadMode 2 +../Utilities/timer/stm32_timer.c:320:21:UTIL_TIMER_GetRemainingTime 3 +../Utilities/timer/stm32_timer.c:342:10:UTIL_TIMER_IsRunning 2 +../Utilities/timer/stm32_timer.c:354:10:UTIL_TIMER_GetFirstRemainingTime 2 +../Utilities/timer/stm32_timer.c:365:6:UTIL_TIMER_IRQ_Handler 11 +../Utilities/timer/stm32_timer.c:417:19:UTIL_TIMER_GetCurrentTime 1 +../Utilities/timer/stm32_timer.c:423:19:UTIL_TIMER_GetElapsedTime 1 +../Utilities/timer/stm32_timer.c:431:22:UTIL_TIMER_GetTimerList 1 +../Utilities/timer/stm32_timer.c:453:6:TimerExists 3 +../Utilities/timer/stm32_timer.c:473:6:TimerSetTimeout 2 +../Utilities/timer/stm32_timer.c:494:6:TimerInsertTimer 3 +../Utilities/timer/stm32_timer.c:526:6:TimerInsertNewHeadTimer 2 diff --git a/Debug/Utilities/timer/stm32_timer.d b/Debug/Utilities/timer/stm32_timer.d new file mode 100644 index 0000000..4bd6c91 --- /dev/null +++ b/Debug/Utilities/timer/stm32_timer.d @@ -0,0 +1,13 @@ +Utilities/timer/stm32_timer.o: ../Utilities/timer/stm32_timer.c \ + ../Utilities/timer/stm32_timer.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h ../Core/Inc/utilities_conf.h \ + ../Utilities/misc/stm32_mem.h ../Utilities/misc/stm32_tiny_vsnprintf.h \ + ../Core/Inc/utilities_def.h +../Utilities/timer/stm32_timer.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Core/Inc/utilities_conf.h: +../Utilities/misc/stm32_mem.h: +../Utilities/misc/stm32_tiny_vsnprintf.h: +../Core/Inc/utilities_def.h: diff --git a/Debug/Utilities/timer/stm32_timer.o b/Debug/Utilities/timer/stm32_timer.o new file mode 100644 index 0000000..4e9efd7 Binary files /dev/null and b/Debug/Utilities/timer/stm32_timer.o differ diff --git a/Debug/Utilities/timer/stm32_timer.su b/Debug/Utilities/timer/stm32_timer.su new file mode 100644 index 0000000..c69a001 --- /dev/null +++ b/Debug/Utilities/timer/stm32_timer.su @@ -0,0 +1,19 @@ +../Utilities/timer/stm32_timer.c:116:21:UTIL_TIMER_Init 8 static +../Utilities/timer/stm32_timer.c:123:21:UTIL_TIMER_DeInit 8 static +../Utilities/timer/stm32_timer.c:128:21:UTIL_TIMER_Create 24 static +../Utilities/timer/stm32_timer.c:149:21:UTIL_TIMER_Start 48 static,ignoring_inline_asm +../Utilities/timer/stm32_timer.c:199:21:UTIL_TIMER_StartWithPeriod 24 static +../Utilities/timer/stm32_timer.c:219:21:UTIL_TIMER_Stop 40 static,ignoring_inline_asm +../Utilities/timer/stm32_timer.c:285:21:UTIL_TIMER_SetPeriod 24 static +../Utilities/timer/stm32_timer.c:305:21:UTIL_TIMER_SetReloadMode 24 static +../Utilities/timer/stm32_timer.c:320:21:UTIL_TIMER_GetRemainingTime 24 static +../Utilities/timer/stm32_timer.c:342:10:UTIL_TIMER_IsRunning 16 static +../Utilities/timer/stm32_timer.c:354:10:UTIL_TIMER_GetFirstRemainingTime 16 static +../Utilities/timer/stm32_timer.c:365:6:UTIL_TIMER_IRQ_Handler 48 static,ignoring_inline_asm +../Utilities/timer/stm32_timer.c:417:19:UTIL_TIMER_GetCurrentTime 16 static +../Utilities/timer/stm32_timer.c:423:19:UTIL_TIMER_GetElapsedTime 24 static +../Utilities/timer/stm32_timer.c:431:22:UTIL_TIMER_GetTimerList 4 static +../Utilities/timer/stm32_timer.c:453:6:TimerExists 24 static +../Utilities/timer/stm32_timer.c:473:6:TimerSetTimeout 32 static +../Utilities/timer/stm32_timer.c:494:6:TimerInsertTimer 24 static +../Utilities/timer/stm32_timer.c:526:6:TimerInsertNewHeadTimer 24 static diff --git a/Debug/Utilities/timer/subdir.mk b/Debug/Utilities/timer/subdir.mk new file mode 100644 index 0000000..a1b8ba5 --- /dev/null +++ b/Debug/Utilities/timer/subdir.mk @@ -0,0 +1,27 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (13.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Utilities/timer/stm32_timer.c + +OBJS += \ +./Utilities/timer/stm32_timer.o + +C_DEPS += \ +./Utilities/timer/stm32_timer.d + + +# Each subdirectory must supply rules for building sources it contributes +Utilities/timer/%.o Utilities/timer/%.su Utilities/timer/%.cyclo: ../Utilities/timer/%.c Utilities/timer/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WL55xx -c -I../Core/Inc -I../SubGHz_Phy/App -I../SubGHz_Phy/Target -I../Utilities/trace/adv_trace -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Utilities/misc -I../Utilities/sequencer -I../Utilities/timer -I../Utilities/lpm/tiny_lpm -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Middlewares/Third_Party/SubGHz_Phy -I../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver -I../Drivers/CMSIS/Include -I../Drivers/BSP/STM32WLxx_Nucleo -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Utilities-2f-timer + +clean-Utilities-2f-timer: + -$(RM) ./Utilities/timer/stm32_timer.cyclo ./Utilities/timer/stm32_timer.d ./Utilities/timer/stm32_timer.o ./Utilities/timer/stm32_timer.su + +.PHONY: clean-Utilities-2f-timer + diff --git a/Debug/Utilities/trace/adv_trace/stm32_adv_trace.cyclo b/Debug/Utilities/trace/adv_trace/stm32_adv_trace.cyclo new file mode 100644 index 0000000..64319a0 --- /dev/null +++ b/Debug/Utilities/trace/adv_trace/stm32_adv_trace.cyclo @@ -0,0 +1,26 @@ +../Utilities/trace/adv_trace/stm32_adv_trace.c:165:25:UTIL_ADV_TRACE_Init 1 +../Utilities/trace/adv_trace/stm32_adv_trace.c:181:25:UTIL_ADV_TRACE_DeInit 1 +../Utilities/trace/adv_trace/stm32_adv_trace.c:187:9:UTIL_ADV_TRACE_IsBufferEmpty 2 +../Utilities/trace/adv_trace/stm32_adv_trace.c:195:25:UTIL_ADV_TRACE_StartRxProcess 1 +../Utilities/trace/adv_trace/stm32_adv_trace.c:202:25:UTIL_ADV_TRACE_COND_FSend 7 +../Utilities/trace/adv_trace/stm32_adv_trace.c:295:25:UTIL_ADV_TRACE_FSend 1 +../Utilities/trace/adv_trace/stm32_adv_trace.c:308:25:UTIL_ADV_TRACE_COND_ZCSend_Allocation 7 +../Utilities/trace/adv_trace/stm32_adv_trace.c:356:25:UTIL_ADV_TRACE_COND_ZCSend_Finalize 1 +../Utilities/trace/adv_trace/stm32_adv_trace.c:362:25:UTIL_ADV_TRACE_ZCSend_Allocation 2 +../Utilities/trace/adv_trace/stm32_adv_trace.c:386:25:UTIL_ADV_TRACE_ZCSend_Finalize 1 +../Utilities/trace/adv_trace/stm32_adv_trace.c:393:25:UTIL_ADV_TRACE_COND_Send 8 +../Utilities/trace/adv_trace/stm32_adv_trace.c:448:25:UTIL_ADV_TRACE_Send 3 +../Utilities/trace/adv_trace/stm32_adv_trace.c:486:6:UTIL_ADV_TRACE_RegisterTimeStampFunction 1 +../Utilities/trace/adv_trace/stm32_adv_trace.c:491:6:UTIL_ADV_TRACE_SetVerboseLevel 1 +../Utilities/trace/adv_trace/stm32_adv_trace.c:496:9:UTIL_ADV_TRACE_GetVerboseLevel 1 +../Utilities/trace/adv_trace/stm32_adv_trace.c:501:6:UTIL_ADV_TRACE_SetRegion 1 +../Utilities/trace/adv_trace/stm32_adv_trace.c:506:10:UTIL_ADV_TRACE_GetRegion 1 +../Utilities/trace/adv_trace/stm32_adv_trace.c:511:6:UTIL_ADV_TRACE_ResetRegion 1 +../Utilities/trace/adv_trace/stm32_adv_trace.c:517:13:UTIL_ADV_TRACE_PreSendHook 1 +../Utilities/trace/adv_trace/stm32_adv_trace.c:521:13:UTIL_ADV_TRACE_PostSendHook 1 +../Utilities/trace/adv_trace/stm32_adv_trace.c:537:32:TRACE_Send 7 +../Utilities/trace/adv_trace/stm32_adv_trace.c:608:13:TRACE_TxCpltCallback 8 +../Utilities/trace/adv_trace/stm32_adv_trace.c:703:16:TRACE_AllocateBufer 8 +../Utilities/trace/adv_trace/stm32_adv_trace.c:794:13:TRACE_Lock 1 +../Utilities/trace/adv_trace/stm32_adv_trace.c:805:13:TRACE_UnLock 1 +../Utilities/trace/adv_trace/stm32_adv_trace.c:816:17:TRACE_IsLocked 1 diff --git a/Debug/Utilities/trace/adv_trace/stm32_adv_trace.d b/Debug/Utilities/trace/adv_trace/stm32_adv_trace.d new file mode 100644 index 0000000..4114487 --- /dev/null +++ b/Debug/Utilities/trace/adv_trace/stm32_adv_trace.d @@ -0,0 +1,13 @@ +Utilities/trace/adv_trace/stm32_adv_trace.o: \ + ../Utilities/trace/adv_trace/stm32_adv_trace.c \ + ../Utilities/trace/adv_trace/stm32_adv_trace.h \ + ../Core/Inc/utilities_conf.h ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h ../Utilities/misc/stm32_mem.h \ + ../Utilities/misc/stm32_tiny_vsnprintf.h ../Core/Inc/utilities_def.h +../Utilities/trace/adv_trace/stm32_adv_trace.h: +../Core/Inc/utilities_conf.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Utilities/misc/stm32_mem.h: +../Utilities/misc/stm32_tiny_vsnprintf.h: +../Core/Inc/utilities_def.h: diff --git a/Debug/Utilities/trace/adv_trace/stm32_adv_trace.o b/Debug/Utilities/trace/adv_trace/stm32_adv_trace.o new file mode 100644 index 0000000..4f36994 Binary files /dev/null and b/Debug/Utilities/trace/adv_trace/stm32_adv_trace.o differ diff --git a/Debug/Utilities/trace/adv_trace/stm32_adv_trace.su b/Debug/Utilities/trace/adv_trace/stm32_adv_trace.su new file mode 100644 index 0000000..697208d --- /dev/null +++ b/Debug/Utilities/trace/adv_trace/stm32_adv_trace.su @@ -0,0 +1,26 @@ +../Utilities/trace/adv_trace/stm32_adv_trace.c:165:25:UTIL_ADV_TRACE_Init 8 static +../Utilities/trace/adv_trace/stm32_adv_trace.c:181:25:UTIL_ADV_TRACE_DeInit 8 static +../Utilities/trace/adv_trace/stm32_adv_trace.c:187:9:UTIL_ADV_TRACE_IsBufferEmpty 4 static +../Utilities/trace/adv_trace/stm32_adv_trace.c:195:25:UTIL_ADV_TRACE_StartRxProcess 16 static +../Utilities/trace/adv_trace/stm32_adv_trace.c:202:25:UTIL_ADV_TRACE_COND_FSend 60 static +../Utilities/trace/adv_trace/stm32_adv_trace.c:295:25:UTIL_ADV_TRACE_FSend 272 static +../Utilities/trace/adv_trace/stm32_adv_trace.c:308:25:UTIL_ADV_TRACE_COND_ZCSend_Allocation 56 static +../Utilities/trace/adv_trace/stm32_adv_trace.c:356:25:UTIL_ADV_TRACE_COND_ZCSend_Finalize 8 static +../Utilities/trace/adv_trace/stm32_adv_trace.c:362:25:UTIL_ADV_TRACE_ZCSend_Allocation 32 static +../Utilities/trace/adv_trace/stm32_adv_trace.c:386:25:UTIL_ADV_TRACE_ZCSend_Finalize 8 static +../Utilities/trace/adv_trace/stm32_adv_trace.c:393:25:UTIL_ADV_TRACE_COND_Send 56 static +../Utilities/trace/adv_trace/stm32_adv_trace.c:448:25:UTIL_ADV_TRACE_Send 32 static +../Utilities/trace/adv_trace/stm32_adv_trace.c:486:6:UTIL_ADV_TRACE_RegisterTimeStampFunction 16 static +../Utilities/trace/adv_trace/stm32_adv_trace.c:491:6:UTIL_ADV_TRACE_SetVerboseLevel 16 static +../Utilities/trace/adv_trace/stm32_adv_trace.c:496:9:UTIL_ADV_TRACE_GetVerboseLevel 4 static +../Utilities/trace/adv_trace/stm32_adv_trace.c:501:6:UTIL_ADV_TRACE_SetRegion 16 static +../Utilities/trace/adv_trace/stm32_adv_trace.c:506:10:UTIL_ADV_TRACE_GetRegion 4 static +../Utilities/trace/adv_trace/stm32_adv_trace.c:511:6:UTIL_ADV_TRACE_ResetRegion 16 static +../Utilities/trace/adv_trace/stm32_adv_trace.c:517:13:UTIL_ADV_TRACE_PreSendHook 4 static +../Utilities/trace/adv_trace/stm32_adv_trace.c:521:13:UTIL_ADV_TRACE_PostSendHook 4 static +../Utilities/trace/adv_trace/stm32_adv_trace.c:537:32:TRACE_Send 40 static,ignoring_inline_asm +../Utilities/trace/adv_trace/stm32_adv_trace.c:608:13:TRACE_TxCpltCallback 40 static,ignoring_inline_asm +../Utilities/trace/adv_trace/stm32_adv_trace.c:703:16:TRACE_AllocateBufer 32 static,ignoring_inline_asm +../Utilities/trace/adv_trace/stm32_adv_trace.c:794:13:TRACE_Lock 24 static,ignoring_inline_asm +../Utilities/trace/adv_trace/stm32_adv_trace.c:805:13:TRACE_UnLock 24 static,ignoring_inline_asm +../Utilities/trace/adv_trace/stm32_adv_trace.c:816:17:TRACE_IsLocked 4 static diff --git a/Debug/Utilities/trace/adv_trace/subdir.mk b/Debug/Utilities/trace/adv_trace/subdir.mk new file mode 100644 index 0000000..9e1414f --- /dev/null +++ b/Debug/Utilities/trace/adv_trace/subdir.mk @@ -0,0 +1,27 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (13.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Utilities/trace/adv_trace/stm32_adv_trace.c + +OBJS += \ +./Utilities/trace/adv_trace/stm32_adv_trace.o + +C_DEPS += \ +./Utilities/trace/adv_trace/stm32_adv_trace.d + + +# Each subdirectory must supply rules for building sources it contributes +Utilities/trace/adv_trace/%.o Utilities/trace/adv_trace/%.su Utilities/trace/adv_trace/%.cyclo: ../Utilities/trace/adv_trace/%.c Utilities/trace/adv_trace/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WL55xx -c -I../Core/Inc -I../SubGHz_Phy/App -I../SubGHz_Phy/Target -I../Utilities/trace/adv_trace -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Utilities/misc -I../Utilities/sequencer -I../Utilities/timer -I../Utilities/lpm/tiny_lpm -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Middlewares/Third_Party/SubGHz_Phy -I../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver -I../Drivers/CMSIS/Include -I../Drivers/BSP/STM32WLxx_Nucleo -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Utilities-2f-trace-2f-adv_trace + +clean-Utilities-2f-trace-2f-adv_trace: + -$(RM) ./Utilities/trace/adv_trace/stm32_adv_trace.cyclo ./Utilities/trace/adv_trace/stm32_adv_trace.d ./Utilities/trace/adv_trace/stm32_adv_trace.o ./Utilities/trace/adv_trace/stm32_adv_trace.su + +.PHONY: clean-Utilities-2f-trace-2f-adv_trace + diff --git a/Debug/makefile b/Debug/makefile new file mode 100644 index 0000000..6a392ff --- /dev/null +++ b/Debug/makefile @@ -0,0 +1,103 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (13.3.rel1) +################################################################################ + +-include ../makefile.init + +RM := rm -rf + +# All of the sources participating in the build are defined here +-include sources.mk +-include Utilities/trace/adv_trace/subdir.mk +-include Utilities/timer/subdir.mk +-include Utilities/sequencer/subdir.mk +-include Utilities/misc/subdir.mk +-include Utilities/lpm/tiny_lpm/subdir.mk +-include SubGHz_Phy/Target/subdir.mk +-include SubGHz_Phy/App/subdir.mk +-include Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/subdir.mk +-include Drivers/STM32WLxx_HAL_Driver/Src/subdir.mk +-include Drivers/BSP/STM32WLxx_Nucleo/subdir.mk +-include Core/Startup/subdir.mk +-include Core/Src/subdir.mk +-include objects.mk + +ifneq ($(MAKECMDGOALS),clean) +ifneq ($(strip $(S_DEPS)),) +-include $(S_DEPS) +endif +ifneq ($(strip $(S_UPPER_DEPS)),) +-include $(S_UPPER_DEPS) +endif +ifneq ($(strip $(C_DEPS)),) +-include $(C_DEPS) +endif +endif + +-include ../makefile.defs + +OPTIONAL_TOOL_DEPS := \ +$(wildcard ../makefile.defs) \ +$(wildcard ../makefile.init) \ +$(wildcard ../makefile.targets) \ + + +BUILD_ARTIFACT_NAME := SubGHz_Phy_Per_My_Test +BUILD_ARTIFACT_EXTENSION := elf +BUILD_ARTIFACT_PREFIX := +BUILD_ARTIFACT := $(BUILD_ARTIFACT_PREFIX)$(BUILD_ARTIFACT_NAME)$(if $(BUILD_ARTIFACT_EXTENSION),.$(BUILD_ARTIFACT_EXTENSION),) + +# Add inputs and outputs from these tool invocations to the build variables +EXECUTABLES += \ +SubGHz_Phy_Per_My_Test.elf \ + +MAP_FILES += \ +SubGHz_Phy_Per_My_Test.map \ + +SIZE_OUTPUT += \ +default.size.stdout \ + +OBJDUMP_LIST += \ +SubGHz_Phy_Per_My_Test.list \ + + +# All Target +all: main-build + +# Main-build Target +main-build: SubGHz_Phy_Per_My_Test.elf secondary-outputs + +# Tool invocations +SubGHz_Phy_Per_My_Test.elf SubGHz_Phy_Per_My_Test.map: $(OBJS) $(USER_OBJS) /soft/stm32/projects/SubGHz_Phy_Per_My_Test/STM32WL55JCIX_FLASH.ld makefile objects.list $(OPTIONAL_TOOL_DEPS) + arm-none-eabi-gcc -o "SubGHz_Phy_Per_My_Test.elf" @"objects.list" $(USER_OBJS) $(LIBS) -mcpu=cortex-m4 -T"/soft/stm32/projects/SubGHz_Phy_Per_My_Test/STM32WL55JCIX_FLASH.ld" --specs=nosys.specs -Wl,-Map="SubGHz_Phy_Per_My_Test.map" -Wl,--gc-sections -static --specs=nano.specs -mfloat-abi=soft -mthumb -Wl,--start-group -lc -lm -Wl,--end-group + @echo 'Finished building target: $@' + @echo ' ' + +default.size.stdout: $(EXECUTABLES) makefile objects.list $(OPTIONAL_TOOL_DEPS) + arm-none-eabi-size $(EXECUTABLES) + @echo 'Finished building: $@' + @echo ' ' + +SubGHz_Phy_Per_My_Test.list: $(EXECUTABLES) makefile objects.list $(OPTIONAL_TOOL_DEPS) + arm-none-eabi-objdump -h -S $(EXECUTABLES) > "SubGHz_Phy_Per_My_Test.list" + @echo 'Finished building: $@' + @echo ' ' + +# Other Targets +clean: + -$(RM) SubGHz_Phy_Per_My_Test.elf SubGHz_Phy_Per_My_Test.list SubGHz_Phy_Per_My_Test.map default.size.stdout + -@echo ' ' + +secondary-outputs: $(SIZE_OUTPUT) $(OBJDUMP_LIST) + +fail-specified-linker-script-missing: + @echo 'Error: Cannot find the specified linker script. Check the linker settings in the build configuration.' + @exit 2 + +warn-no-linker-script-specified: + @echo 'Warning: No linker script specified. Check the linker settings in the build configuration.' + +.PHONY: all clean dependents main-build fail-specified-linker-script-missing warn-no-linker-script-specified + +-include ../makefile.targets diff --git a/Debug/objects.list b/Debug/objects.list new file mode 100644 index 0000000..e16abe2 --- /dev/null +++ b/Debug/objects.list @@ -0,0 +1,52 @@ +"./Core/Src/dma.o" +"./Core/Src/gpio.o" +"./Core/Src/main.o" +"./Core/Src/rtc.o" +"./Core/Src/stm32_lpm_if.o" +"./Core/Src/stm32wlxx_hal_msp.o" +"./Core/Src/stm32wlxx_it.o" +"./Core/Src/subghz.o" +"./Core/Src/sys_app.o" +"./Core/Src/sys_debug.o" +"./Core/Src/syscalls.o" +"./Core/Src/sysmem.o" +"./Core/Src/system_stm32wlxx.o" +"./Core/Src/timer_if.o" +"./Core/Src/usart.o" +"./Core/Src/usart_if.o" +"./Core/Startup/startup_stm32wl55jcix.o" +"./Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo.o" +"./Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo_radio.o" +"./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.o" +"./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.o" +"./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.o" +"./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma_ex.o" +"./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_exti.o" +"./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash.o" +"./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.o" +"./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_gpio.o" +"./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.o" +"./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.o" +"./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.o" +"./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.o" +"./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.o" +"./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.o" +"./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.o" +"./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.o" +"./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.o" +"./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.o" +"./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o" +"./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o" +"./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.o" +"./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/wl_lr_fhss.o" +"./SubGHz_Phy/App/app_subghz_phy.o" +"./SubGHz_Phy/App/subghz_phy_app.o" +"./SubGHz_Phy/Target/radio_board_if.o" +"./Utilities/lpm/tiny_lpm/stm32_lpm.o" +"./Utilities/misc/stm32_mem.o" +"./Utilities/misc/stm32_systime.o" +"./Utilities/misc/stm32_tiny_sscanf.o" +"./Utilities/misc/stm32_tiny_vsnprintf.o" +"./Utilities/sequencer/stm32_seq.o" +"./Utilities/timer/stm32_timer.o" +"./Utilities/trace/adv_trace/stm32_adv_trace.o" diff --git a/Debug/objects.mk b/Debug/objects.mk new file mode 100644 index 0000000..b471e98 --- /dev/null +++ b/Debug/objects.mk @@ -0,0 +1,9 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (13.3.rel1) +################################################################################ + +USER_OBJS := + +LIBS := + diff --git a/Debug/sources.mk b/Debug/sources.mk new file mode 100644 index 0000000..ca5795d --- /dev/null +++ b/Debug/sources.mk @@ -0,0 +1,37 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (13.3.rel1) +################################################################################ + +ELF_SRCS := +OBJ_SRCS := +S_SRCS := +C_SRCS := +S_UPPER_SRCS := +O_SRCS := +CYCLO_FILES := +SIZE_OUTPUT := +OBJDUMP_LIST := +SU_FILES := +EXECUTABLES := +OBJS := +MAP_FILES := +S_DEPS := +S_UPPER_DEPS := +C_DEPS := + +# Every subdirectory with source files must be described here +SUBDIRS := \ +Core/Src \ +Core/Startup \ +Drivers/BSP/STM32WLxx_Nucleo \ +Drivers/STM32WLxx_HAL_Driver/Src \ +Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver \ +SubGHz_Phy/App \ +SubGHz_Phy/Target \ +Utilities/lpm/tiny_lpm \ +Utilities/misc \ +Utilities/sequencer \ +Utilities/timer \ +Utilities/trace/adv_trace \ + diff --git a/Drivers/BSP/STM32WLxx_Nucleo/LICENSE.txt b/Drivers/BSP/STM32WLxx_Nucleo/LICENSE.txt new file mode 100644 index 0000000..3edc4d1 --- /dev/null +++ b/Drivers/BSP/STM32WLxx_Nucleo/LICENSE.txt @@ -0,0 +1,6 @@ +This software component is provided to you as part of a software package and +applicable license terms are in the Package_license file. If you received this +software component outside of a package or without applicable license terms, +the terms of the BSD-3-Clause license shall apply. +You may obtain a copy of the BSD-3-Clause at: +https://opensource.org/licenses/BSD-3-Clause diff --git a/Drivers/BSP/STM32WLxx_Nucleo/Release_Notes.html b/Drivers/BSP/STM32WLxx_Nucleo/Release_Notes.html new file mode 100644 index 0000000..c687e28 --- /dev/null +++ b/Drivers/BSP/STM32WLxx_Nucleo/Release_Notes.html @@ -0,0 +1,183 @@ + + + + + + + Release Notes for STM32WLxx_Nucleo + + + + + +
+
+
+

Release Notes for

+

STM32WLxx_Nucleo

+

Copyright © 2020 STMicroelectronics
+

+ +
+

Purpose

+

This driver provides a set of functions to manage:

+
    +
  • RF Switches, LEDs and push-button available on STM32WLxx_Nucleo Kit +from STMicroelectronics
    • +
+
+
+

Update History

+
+ + +
+

Main Changes

+

Maintenance Release

+

Contents

+
    +
  • fix build error with NUCLEO-WL55JC1 and NUCLEO-WL55JC2 boards using +Keil IDE
    • +
+

Known Limitations

+

None

+

Dependencies

+

None

+

Notes

+

stm32wlxx_nucleo_conf_template.h file must be copied in user +application as stm32wlxx_nucleo_conf.h with optional configuration +update

+
+
+
+ + +
+

Main Changes

+

Maintenance Release

+

Contents

+
    +
  • printf() implementation change to be compliant with IAR EWARM +V9.20.1
    • +
+

Known Limitations

+

None

+

Dependencies

+

None

+

Notes

+

stm32wlxx_nucleo_conf_template.h file must be copied in user +application as stm32wlxx_nucleo_conf.h with optional configuration +update

+
+
+
+ + +
+

Main Changes

+

Maintenance Release

+

Contents

+
    +
  • All source files and templates: update disclaimer to add reference +to the new license agreement
    • +
  • Add README.md file
    • +
  • Rename BSP_BUTTON_SWx_IT_PRIORITY constant to +BSP_BUTTON_USER_IT_PRIORITY
    • +
  • Add new interface BSP_RADIO_GetRFOMaxPowerConfig to get the RFO Max +Power configuration
    • +
+

Known Limitations

+

None

+

Dependencies

+

None

+

Notes

+

stm32wlxx_nucleo_conf_template.h file must be copied in user +application as stm32wlxx_nucleo_conf.h with optional configuration +update

+
+
+
+ + +
+

Main Changes

+

Maintenance Release

+

Contents

+
    +
  • Move some radio definitions (TCXO, DSDC) from +stm32wlxx_nucleo_conf.h to stm32wlxx_nucleo_radio.h
    • +
  • Add 2 interfaces to check BSP_RADIO_IsTCXO and BSP_RADIO_IsDCDC +definitions
    • +
  • Remove radio API BSP_RADIO_GetWakeUpTime from +stm32wlxx_nucleo_radio.c
    • +
+

Known Limitations

+

None

+

Dependencies

+

None

+

Notes

+

stm32wlxx_nucleo_conf_template.h file must be copied in user +application as stm32wlxx_nucleo_conf.h with optional configuration +update

+
+
+
+ + +
+

Main Changes

+

First Official Release

+

Contents

+

First official release of board drivers for NUCLEO-WL55JC +board (MB1389 C-01) in line with STM32Cube BSP drivers +development guidelines (UM2298 - revision 2)

+

Known Limitations

+

None

+

Dependencies

+

None

+

Notes

+

stm32wlxx_nucleo_conf_template.h file must be copied in user +application as stm32wlxx_nucleo_conf.h with optional configuration +update

+
+
+
+
+
+
+
+

For complete documentation on STM32WLxx, visit: www.st.com/stm32wl

+

This release note uses up to date web standards and, for this +reason, should not be opened with Internet Explorer but preferably with +popular browsers such as Google Chrome, Mozilla Firefox, Opera or +Microsoft Edge.

+
+

Info

+
+
+
+ + diff --git a/Drivers/BSP/STM32WLxx_Nucleo/STM32WLxx_Nucleo_BSP_User_Manual.chm b/Drivers/BSP/STM32WLxx_Nucleo/STM32WLxx_Nucleo_BSP_User_Manual.chm new file mode 100644 index 0000000..2efed49 Binary files /dev/null and b/Drivers/BSP/STM32WLxx_Nucleo/STM32WLxx_Nucleo_BSP_User_Manual.chm differ diff --git a/Drivers/BSP/STM32WLxx_Nucleo/_htmresc/Add button.svg b/Drivers/BSP/STM32WLxx_Nucleo/_htmresc/Add button.svg new file mode 100644 index 0000000..c211545 --- /dev/null +++ b/Drivers/BSP/STM32WLxx_Nucleo/_htmresc/Add button.svg @@ -0,0 +1,2 @@ + + diff --git a/Drivers/BSP/STM32WLxx_Nucleo/_htmresc/Update.svg b/Drivers/BSP/STM32WLxx_Nucleo/_htmresc/Update.svg new file mode 100644 index 0000000..f88381f --- /dev/null +++ b/Drivers/BSP/STM32WLxx_Nucleo/_htmresc/Update.svg @@ -0,0 +1,2 @@ + + diff --git a/Drivers/BSP/STM32WLxx_Nucleo/_htmresc/favicon.png b/Drivers/BSP/STM32WLxx_Nucleo/_htmresc/favicon.png new file mode 100644 index 0000000..06713ee Binary files /dev/null and b/Drivers/BSP/STM32WLxx_Nucleo/_htmresc/favicon.png differ diff --git a/Drivers/BSP/STM32WLxx_Nucleo/_htmresc/mini-st_2020.css b/Drivers/BSP/STM32WLxx_Nucleo/_htmresc/mini-st_2020.css new file mode 100644 index 0000000..986f4d4 --- /dev/null +++ b/Drivers/BSP/STM32WLxx_Nucleo/_htmresc/mini-st_2020.css @@ -0,0 +1,1711 @@ +@charset "UTF-8"; +/* + Flavor name: Custom (mini-custom) + Generated online - https://minicss.org/flavors + mini.css version: v3.0.1 +*/ +/* + Browsers resets and base typography. +*/ +/* Core module CSS variable definitions */ +:root { + --fore-color: #03234b; + --secondary-fore-color: #03234b; + --back-color: #ffffff; + --secondary-back-color: #ffffff; + --blockquote-color: #e6007e; + --pre-color: #e6007e; + --border-color: #3cb4e6; + --secondary-border-color: #3cb4e6; + --heading-ratio: 1.2; + --universal-margin: 0.5rem; + --universal-padding: 0.25rem; + --universal-border-radius: 0.075rem; + --background-margin: 1.5%; + --a-link-color: #3cb4e6; + --a-visited-color: #8c0078; } + +html { + font-size: 13.5px; } + +a, b, del, em, i, ins, q, span, strong, u { + font-size: 1em; } + +html, * { + font-family: -apple-system, BlinkMacSystemFont, Helvetica, arial, sans-serif; + line-height: 1.25; + -webkit-text-size-adjust: 100%; } + +* { + font-size: 1rem; } + +body { + margin: 0; + color: var(--fore-color); + @background: var(--back-color); + background: var(--back-color) linear-gradient(#ffd200, #ffd200) repeat-y left top; + background-size: var(--background-margin); + } + +details { + display: block; } + +summary { + display: list-item; } + +abbr[title] { + border-bottom: none; + text-decoration: underline dotted; } + +input { + overflow: visible; } + +img { + max-width: 100%; + height: auto; } + +h1, h2, h3, h4, h5, h6 { + line-height: 1.25; + margin: calc(1.5 * var(--universal-margin)) var(--universal-margin); + font-weight: 400; } + h1 small, h2 small, h3 small, h4 small, h5 small, h6 small { + color: var(--secondary-fore-color); + display: block; + margin-top: -0.25rem; } + +h1 { + font-size: calc(1rem * var(--heading-ratio) * var(--heading-ratio) * var(--heading-ratio)); } + +h2 { + font-size: calc(1rem * var(--heading-ratio) * var(--heading-ratio) ); + border-style: none none solid none ; + border-width: thin; + border-color: var(--border-color); } +h3 { + font-size: calc(1rem * var(--heading-ratio) ); } + +h4 { + font-size: calc(1rem * var(--heading-ratio)); } + +h5 { + font-size: 1rem; } + +h6 { + font-size: calc(1rem / var(--heading-ratio)); } + +p { + margin: var(--universal-margin); } + +ol, ul { + margin: var(--universal-margin); + padding-left: calc(3 * var(--universal-margin)); } + +b, strong { + font-weight: 700; } + +hr { + box-sizing: content-box; + border: 0; + line-height: 1.25em; + margin: var(--universal-margin); + height: 0.0714285714rem; + background: linear-gradient(to right, transparent, var(--border-color) 20%, var(--border-color) 80%, transparent); } + +blockquote { + display: block; + position: relative; + font-style: italic; + color: var(--secondary-fore-color); + margin: var(--universal-margin); + padding: calc(3 * var(--universal-padding)); + border: 0.0714285714rem solid var(--secondary-border-color); + border-left: 0.3rem solid var(--blockquote-color); + border-radius: 0 var(--universal-border-radius) var(--universal-border-radius) 0; } + blockquote:before { + position: absolute; + top: calc(0rem - var(--universal-padding)); + left: 0; + font-family: sans-serif; + font-size: 2rem; + font-weight: 800; + content: "\201c"; + color: var(--blockquote-color); } + blockquote[cite]:after { + font-style: normal; + font-size: 0.75em; + font-weight: 700; + content: "\a— " attr(cite); + white-space: pre; } + +code, kbd, pre, samp { + font-family: Menlo, Consolas, monospace; + font-size: 0.85em; } + +code { + background: var(--secondary-back-color); + border-radius: var(--universal-border-radius); + padding: calc(var(--universal-padding) / 4) calc(var(--universal-padding) / 2); } + +kbd { + background: var(--fore-color); + color: var(--back-color); + border-radius: var(--universal-border-radius); + padding: calc(var(--universal-padding) / 4) calc(var(--universal-padding) / 2); } + +pre { + overflow: auto; + background: var(--secondary-back-color); + padding: calc(1.5 * var(--universal-padding)); + margin: var(--universal-margin); + border: 0.0714285714rem solid var(--secondary-border-color); + border-left: 0.2857142857rem solid var(--pre-color); + border-radius: 0 var(--universal-border-radius) var(--universal-border-radius) 0; } + +sup, sub, code, kbd { + line-height: 0; + position: relative; + vertical-align: baseline; } + +small, sup, sub, figcaption { + font-size: 0.75em; } + +sup { + top: -0.5em; } + +sub { + bottom: -0.25em; } + +figure { + margin: var(--universal-margin); } + +figcaption { + color: var(--secondary-fore-color); } + +a { + text-decoration: none; } + a:link { + color: var(--a-link-color); } + a:visited { + color: var(--a-visited-color); } + a:hover, a:focus { + text-decoration: underline; } + +/* + Definitions for the grid system, cards and containers. +*/ +.container { + margin: 0 auto; + padding: 0 calc(1.5 * var(--universal-padding)); } + +.row { + box-sizing: border-box; + display: flex; + flex: 0 1 auto; + flex-flow: row wrap; + margin: 0 0 0 var(--background-margin); } + +.col-sm, +[class^='col-sm-'], +[class^='col-sm-offset-'], +.row[class*='cols-sm-'] > * { + box-sizing: border-box; + flex: 0 0 auto; + padding: 0 calc(var(--universal-padding) / 2); } + +.col-sm, +.row.cols-sm > * { + max-width: 100%; + flex-grow: 1; + flex-basis: 0; } + +.col-sm-1, +.row.cols-sm-1 > * { + max-width: 8.3333333333%; + flex-basis: 8.3333333333%; } + +.col-sm-offset-0 { + margin-left: 0; } + +.col-sm-2, +.row.cols-sm-2 > * { + max-width: 16.6666666667%; + flex-basis: 16.6666666667%; } + +.col-sm-offset-1 { + margin-left: 8.3333333333%; } + +.col-sm-3, +.row.cols-sm-3 > * { + max-width: 25%; + flex-basis: 25%; } + +.col-sm-offset-2 { + margin-left: 16.6666666667%; } + +.col-sm-4, +.row.cols-sm-4 > * { + max-width: 33.3333333333%; + flex-basis: 33.3333333333%; } + +.col-sm-offset-3 { + margin-left: 25%; } + +.col-sm-5, +.row.cols-sm-5 > * { + max-width: 41.6666666667%; + flex-basis: 41.6666666667%; } + +.col-sm-offset-4 { + margin-left: 33.3333333333%; } + +.col-sm-6, +.row.cols-sm-6 > * { + max-width: 50%; + flex-basis: 50%; } + +.col-sm-offset-5 { + margin-left: 41.6666666667%; } + +.col-sm-7, +.row.cols-sm-7 > * { + max-width: 58.3333333333%; + flex-basis: 58.3333333333%; } + +.col-sm-offset-6 { + margin-left: 50%; } + +.col-sm-8, +.row.cols-sm-8 > * { + max-width: 66.6666666667%; + flex-basis: 66.6666666667%; } + +.col-sm-offset-7 { + margin-left: 58.3333333333%; } + +.col-sm-9, +.row.cols-sm-9 > * { + max-width: 75%; + flex-basis: 75%; } + +.col-sm-offset-8 { + margin-left: 66.6666666667%; } + +.col-sm-10, +.row.cols-sm-10 > * { + max-width: 83.3333333333%; + flex-basis: 83.3333333333%; } + +.col-sm-offset-9 { + margin-left: 75%; } + +.col-sm-11, +.row.cols-sm-11 > * { + max-width: 91.6666666667%; + flex-basis: 91.6666666667%; } + +.col-sm-offset-10 { + margin-left: 83.3333333333%; } + +.col-sm-12, +.row.cols-sm-12 > * { + max-width: 100%; + flex-basis: 100%; } + +.col-sm-offset-11 { + margin-left: 91.6666666667%; } + +.col-sm-normal { + order: initial; } + +.col-sm-first { + order: -999; } + +.col-sm-last { + order: 999; } + +@media screen and (min-width: 500px) { + .col-md, + [class^='col-md-'], + [class^='col-md-offset-'], + .row[class*='cols-md-'] > * { + box-sizing: border-box; + flex: 0 0 auto; + padding: 0 calc(var(--universal-padding) / 2); } + + .col-md, + .row.cols-md > * { + max-width: 100%; + flex-grow: 1; + flex-basis: 0; } + + .col-md-1, + .row.cols-md-1 > * { + max-width: 8.3333333333%; + flex-basis: 8.3333333333%; } + + .col-md-offset-0 { + margin-left: 0; } + + .col-md-2, + .row.cols-md-2 > * { + max-width: 16.6666666667%; + flex-basis: 16.6666666667%; } + + .col-md-offset-1 { + margin-left: 8.3333333333%; } + + .col-md-3, + .row.cols-md-3 > * { + max-width: 25%; + flex-basis: 25%; } + + .col-md-offset-2 { + margin-left: 16.6666666667%; } + + .col-md-4, + .row.cols-md-4 > * { + max-width: 33.3333333333%; + flex-basis: 33.3333333333%; } + + .col-md-offset-3 { + margin-left: 25%; } + + .col-md-5, + .row.cols-md-5 > * { + max-width: 41.6666666667%; + flex-basis: 41.6666666667%; } + + .col-md-offset-4 { + margin-left: 33.3333333333%; } + + .col-md-6, + .row.cols-md-6 > * { + max-width: 50%; + flex-basis: 50%; } + + .col-md-offset-5 { + margin-left: 41.6666666667%; } + + .col-md-7, + .row.cols-md-7 > * { + max-width: 58.3333333333%; + flex-basis: 58.3333333333%; } + + .col-md-offset-6 { + margin-left: 50%; } + + .col-md-8, + .row.cols-md-8 > * { + max-width: 66.6666666667%; + flex-basis: 66.6666666667%; } + + .col-md-offset-7 { + margin-left: 58.3333333333%; } + + .col-md-9, + .row.cols-md-9 > * { + max-width: 75%; + flex-basis: 75%; } + + .col-md-offset-8 { + margin-left: 66.6666666667%; } + + .col-md-10, + .row.cols-md-10 > * { + max-width: 83.3333333333%; + flex-basis: 83.3333333333%; } + + .col-md-offset-9 { + margin-left: 75%; } + + .col-md-11, + .row.cols-md-11 > * { + max-width: 91.6666666667%; + flex-basis: 91.6666666667%; } + + .col-md-offset-10 { + margin-left: 83.3333333333%; } + + .col-md-12, + .row.cols-md-12 > * { + max-width: 100%; + flex-basis: 100%; } + + .col-md-offset-11 { + margin-left: 91.6666666667%; } + + .col-md-normal { + order: initial; } + + .col-md-first { + order: -999; } + + .col-md-last { + order: 999; } } +@media screen and (min-width: 1280px) { + .col-lg, + [class^='col-lg-'], + [class^='col-lg-offset-'], + .row[class*='cols-lg-'] > * { + box-sizing: border-box; + flex: 0 0 auto; + padding: 0 calc(var(--universal-padding) / 2); } + + .col-lg, + .row.cols-lg > * { + max-width: 100%; + flex-grow: 1; + flex-basis: 0; } + + .col-lg-1, + .row.cols-lg-1 > * { + max-width: 8.3333333333%; + flex-basis: 8.3333333333%; } + + .col-lg-offset-0 { + margin-left: 0; } + + .col-lg-2, + .row.cols-lg-2 > * { + max-width: 16.6666666667%; + flex-basis: 16.6666666667%; } + + .col-lg-offset-1 { + margin-left: 8.3333333333%; } + + .col-lg-3, + .row.cols-lg-3 > * { + max-width: 25%; + flex-basis: 25%; } + + .col-lg-offset-2 { + margin-left: 16.6666666667%; } + + .col-lg-4, + .row.cols-lg-4 > * { + max-width: 33.3333333333%; + flex-basis: 33.3333333333%; } + + .col-lg-offset-3 { + margin-left: 25%; } + + .col-lg-5, + .row.cols-lg-5 > * { + max-width: 41.6666666667%; + flex-basis: 41.6666666667%; } + + .col-lg-offset-4 { + margin-left: 33.3333333333%; } + + .col-lg-6, + .row.cols-lg-6 > * { + max-width: 50%; + flex-basis: 50%; } + + .col-lg-offset-5 { + margin-left: 41.6666666667%; } + + .col-lg-7, + .row.cols-lg-7 > * { + max-width: 58.3333333333%; + flex-basis: 58.3333333333%; } + + .col-lg-offset-6 { + margin-left: 50%; } + + .col-lg-8, + .row.cols-lg-8 > * { + max-width: 66.6666666667%; + flex-basis: 66.6666666667%; } + + .col-lg-offset-7 { + margin-left: 58.3333333333%; } + + .col-lg-9, + .row.cols-lg-9 > * { + max-width: 75%; + flex-basis: 75%; } + + .col-lg-offset-8 { + margin-left: 66.6666666667%; } + + .col-lg-10, + .row.cols-lg-10 > * { + max-width: 83.3333333333%; + flex-basis: 83.3333333333%; } + + .col-lg-offset-9 { + margin-left: 75%; } + + .col-lg-11, + .row.cols-lg-11 > * { + max-width: 91.6666666667%; + flex-basis: 91.6666666667%; } + + .col-lg-offset-10 { + margin-left: 83.3333333333%; } + + .col-lg-12, + .row.cols-lg-12 > * { + max-width: 100%; + flex-basis: 100%; } + + .col-lg-offset-11 { + margin-left: 91.6666666667%; } + + .col-lg-normal { + order: initial; } + + .col-lg-first { + order: -999; } + + .col-lg-last { + order: 999; } } +/* Card component CSS variable definitions */ +:root { + --card-back-color: #3cb4e6; + --card-fore-color: #03234b; + --card-border-color: #03234b; } + +.card { + display: flex; + flex-direction: column; + justify-content: space-between; + align-self: center; + position: relative; + width: 100%; + background: var(--card-back-color); + color: var(--card-fore-color); + border: 0.0714285714rem solid var(--card-border-color); + border-radius: var(--universal-border-radius); + margin: var(--universal-margin); + overflow: hidden; } + @media screen and (min-width: 320px) { + .card { + max-width: 320px; } } + .card > .sectione { + background: var(--card-back-color); + color: var(--card-fore-color); + box-sizing: border-box; + margin: 0; + border: 0; + border-radius: 0; + border-bottom: 0.0714285714rem solid var(--card-border-color); + padding: var(--universal-padding); + width: 100%; } + .card > .sectione.media { + height: 200px; + padding: 0; + -o-object-fit: cover; + object-fit: cover; } + .card > .sectione:last-child { + border-bottom: 0; } + +/* + Custom elements for card elements. +*/ +@media screen and (min-width: 240px) { + .card.small { + max-width: 240px; } } +@media screen and (min-width: 480px) { + .card.large { + max-width: 480px; } } +.card.fluid { + max-width: 100%; + width: auto; } + +.card.warning { + --card-back-color: #e5b8b7; + --card-fore-color: #3b234b; + --card-border-color: #8c0078; } + +.card.error { + --card-back-color: #464650; + --card-fore-color: #ffffff; + --card-border-color: #8c0078; } + +.card > .sectione.dark { + --card-back-color: #3b234b; + --card-fore-color: #ffffff; } + +.card > .sectione.double-padded { + padding: calc(1.5 * var(--universal-padding)); } + +/* + Definitions for forms and input elements. +*/ +/* Input_control module CSS variable definitions */ +:root { + --form-back-color: #ffe97f; + --form-fore-color: #03234b; + --form-border-color: #3cb4e6; + --input-back-color: #ffffff; + --input-fore-color: #03234b; + --input-border-color: #3cb4e6; + --input-focus-color: #0288d1; + --input-invalid-color: #d32f2f; + --button-back-color: #e2e2e2; + --button-hover-back-color: #dcdcdc; + --button-fore-color: #212121; + --button-border-color: transparent; + --button-hover-border-color: transparent; + --button-group-border-color: rgba(124, 124, 124, 0.54); } + +form { + background: var(--form-back-color); + color: var(--form-fore-color); + border: 0.0714285714rem solid var(--form-border-color); + border-radius: var(--universal-border-radius); + margin: var(--universal-margin); + padding: calc(2 * var(--universal-padding)) var(--universal-padding); } + +fieldset { + border: 0.0714285714rem solid var(--form-border-color); + border-radius: var(--universal-border-radius); + margin: calc(var(--universal-margin) / 4); + padding: var(--universal-padding); } + +legend { + box-sizing: border-box; + display: table; + max-width: 100%; + white-space: normal; + font-weight: 500; + padding: calc(var(--universal-padding) / 2); } + +label { + padding: calc(var(--universal-padding) / 2) var(--universal-padding); } + +.input-group { + display: inline-block; } + .input-group.fluid { + display: flex; + align-items: center; + justify-content: center; } + .input-group.fluid > input { + max-width: 100%; + flex-grow: 1; + flex-basis: 0px; } + @media screen and (max-width: 499px) { + .input-group.fluid { + align-items: stretch; + flex-direction: column; } } + .input-group.vertical { + display: flex; + align-items: stretch; + flex-direction: column; } + .input-group.vertical > input { + max-width: 100%; + flex-grow: 1; + flex-basis: 0px; } + +[type="number"]::-webkit-inner-spin-button, [type="number"]::-webkit-outer-spin-button { + height: auto; } + +[type="search"] { + -webkit-appearance: textfield; + outline-offset: -2px; } + +[type="search"]::-webkit-search-cancel-button, +[type="search"]::-webkit-search-decoration { + -webkit-appearance: none; } + +input:not([type]), [type="text"], [type="email"], [type="number"], [type="search"], +[type="password"], [type="url"], [type="tel"], [type="checkbox"], [type="radio"], textarea, select { + box-sizing: border-box; + background: var(--input-back-color); + color: var(--input-fore-color); + border: 0.0714285714rem solid var(--input-border-color); + border-radius: var(--universal-border-radius); + margin: calc(var(--universal-margin) / 2); + padding: var(--universal-padding) calc(1.5 * var(--universal-padding)); } + +input:not([type="button"]):not([type="submit"]):not([type="reset"]):hover, input:not([type="button"]):not([type="submit"]):not([type="reset"]):focus, textarea:hover, textarea:focus, select:hover, select:focus { + border-color: var(--input-focus-color); + box-shadow: none; } +input:not([type="button"]):not([type="submit"]):not([type="reset"]):invalid, input:not([type="button"]):not([type="submit"]):not([type="reset"]):focus:invalid, textarea:invalid, textarea:focus:invalid, select:invalid, select:focus:invalid { + border-color: var(--input-invalid-color); + box-shadow: none; } +input:not([type="button"]):not([type="submit"]):not([type="reset"])[readonly], textarea[readonly], select[readonly] { + background: var(--secondary-back-color); } + +select { + max-width: 100%; } + +option { + overflow: hidden; + text-overflow: ellipsis; } + +[type="checkbox"], [type="radio"] { + -webkit-appearance: none; + -moz-appearance: none; + appearance: none; + position: relative; + height: calc(1rem + var(--universal-padding) / 2); + width: calc(1rem + var(--universal-padding) / 2); + vertical-align: text-bottom; + padding: 0; + flex-basis: calc(1rem + var(--universal-padding) / 2) !important; + flex-grow: 0 !important; } + [type="checkbox"]:checked:before, [type="radio"]:checked:before { + position: absolute; } + +[type="checkbox"]:checked:before { + content: '\2713'; + font-family: sans-serif; + font-size: calc(1rem + var(--universal-padding) / 2); + top: calc(0rem - var(--universal-padding)); + left: calc(var(--universal-padding) / 4); } + +[type="radio"] { + border-radius: 100%; } + [type="radio"]:checked:before { + border-radius: 100%; + content: ''; + top: calc(0.0714285714rem + var(--universal-padding) / 2); + left: calc(0.0714285714rem + var(--universal-padding) / 2); + background: var(--input-fore-color); + width: 0.5rem; + height: 0.5rem; } + +:placeholder-shown { + color: var(--input-fore-color); } + +::-ms-placeholder { + color: var(--input-fore-color); + opacity: 0.54; } + +button::-moz-focus-inner, [type="button"]::-moz-focus-inner, [type="reset"]::-moz-focus-inner, [type="submit"]::-moz-focus-inner { + border-style: none; + padding: 0; } + +button, html [type="button"], [type="reset"], [type="submit"] { + -webkit-appearance: button; } + +button { + overflow: visible; + text-transform: none; } + +button, [type="button"], [type="submit"], [type="reset"], +a.button, label.button, .button, +a[role="button"], label[role="button"], [role="button"] { + display: inline-block; + background: var(--button-back-color); + color: var(--button-fore-color); + border: 0.0714285714rem solid var(--button-border-color); + border-radius: var(--universal-border-radius); + padding: var(--universal-padding) calc(1.5 * var(--universal-padding)); + margin: var(--universal-margin); + text-decoration: none; + cursor: pointer; + transition: background 0.3s; } + button:hover, button:focus, [type="button"]:hover, [type="button"]:focus, [type="submit"]:hover, [type="submit"]:focus, [type="reset"]:hover, [type="reset"]:focus, + a.button:hover, + a.button:focus, label.button:hover, label.button:focus, .button:hover, .button:focus, + a[role="button"]:hover, + a[role="button"]:focus, label[role="button"]:hover, label[role="button"]:focus, [role="button"]:hover, [role="button"]:focus { + background: var(--button-hover-back-color); + border-color: var(--button-hover-border-color); } + +input:disabled, input[disabled], textarea:disabled, textarea[disabled], select:disabled, select[disabled], button:disabled, button[disabled], .button:disabled, .button[disabled], [role="button"]:disabled, [role="button"][disabled] { + cursor: not-allowed; + opacity: 0.75; } + +.button-group { + display: flex; + border: 0.0714285714rem solid var(--button-group-border-color); + border-radius: var(--universal-border-radius); + margin: var(--universal-margin); } + .button-group > button, .button-group [type="button"], .button-group > [type="submit"], .button-group > [type="reset"], .button-group > .button, .button-group > [role="button"] { + margin: 0; + max-width: 100%; + flex: 1 1 auto; + text-align: center; + border: 0; + border-radius: 0; + box-shadow: none; } + .button-group > :not(:first-child) { + border-left: 0.0714285714rem solid var(--button-group-border-color); } + @media screen and (max-width: 499px) { + .button-group { + flex-direction: column; } + .button-group > :not(:first-child) { + border: 0; + border-top: 0.0714285714rem solid var(--button-group-border-color); } } + +/* + Custom elements for forms and input elements. +*/ +button.primary, [type="button"].primary, [type="submit"].primary, [type="reset"].primary, .button.primary, [role="button"].primary { + --button-back-color: #1976d2; + --button-fore-color: #f8f8f8; } + button.primary:hover, button.primary:focus, [type="button"].primary:hover, [type="button"].primary:focus, [type="submit"].primary:hover, [type="submit"].primary:focus, [type="reset"].primary:hover, [type="reset"].primary:focus, .button.primary:hover, .button.primary:focus, [role="button"].primary:hover, [role="button"].primary:focus { + --button-hover-back-color: #1565c0; } + +button.secondary, [type="button"].secondary, [type="submit"].secondary, [type="reset"].secondary, .button.secondary, [role="button"].secondary { + --button-back-color: #d32f2f; + --button-fore-color: #f8f8f8; } + button.secondary:hover, button.secondary:focus, [type="button"].secondary:hover, [type="button"].secondary:focus, [type="submit"].secondary:hover, [type="submit"].secondary:focus, [type="reset"].secondary:hover, [type="reset"].secondary:focus, .button.secondary:hover, .button.secondary:focus, [role="button"].secondary:hover, [role="button"].secondary:focus { + --button-hover-back-color: #c62828; } + +button.tertiary, [type="button"].tertiary, [type="submit"].tertiary, [type="reset"].tertiary, .button.tertiary, [role="button"].tertiary { + --button-back-color: #308732; + --button-fore-color: #f8f8f8; } + button.tertiary:hover, button.tertiary:focus, [type="button"].tertiary:hover, [type="button"].tertiary:focus, [type="submit"].tertiary:hover, [type="submit"].tertiary:focus, [type="reset"].tertiary:hover, [type="reset"].tertiary:focus, .button.tertiary:hover, .button.tertiary:focus, [role="button"].tertiary:hover, [role="button"].tertiary:focus { + --button-hover-back-color: #277529; } + +button.inverse, [type="button"].inverse, [type="submit"].inverse, [type="reset"].inverse, .button.inverse, [role="button"].inverse { + --button-back-color: #212121; + --button-fore-color: #f8f8f8; } + button.inverse:hover, button.inverse:focus, [type="button"].inverse:hover, [type="button"].inverse:focus, [type="submit"].inverse:hover, [type="submit"].inverse:focus, [type="reset"].inverse:hover, [type="reset"].inverse:focus, .button.inverse:hover, .button.inverse:focus, [role="button"].inverse:hover, [role="button"].inverse:focus { + --button-hover-back-color: #111; } + +button.small, [type="button"].small, [type="submit"].small, [type="reset"].small, .button.small, [role="button"].small { + padding: calc(0.5 * var(--universal-padding)) calc(0.75 * var(--universal-padding)); + margin: var(--universal-margin); } + +button.large, [type="button"].large, [type="submit"].large, [type="reset"].large, .button.large, [role="button"].large { + padding: calc(1.5 * var(--universal-padding)) calc(2 * var(--universal-padding)); + margin: var(--universal-margin); } + +/* + Definitions for navigation elements. +*/ +/* Navigation module CSS variable definitions */ +:root { + --header-back-color: #03234b; + --header-hover-back-color: #ffd200; + --header-fore-color: #ffffff; + --header-border-color: #3cb4e6; + --nav-back-color: #ffffff; + --nav-hover-back-color: #ffe97f; + --nav-fore-color: #e6007e; + --nav-border-color: #3cb4e6; + --nav-link-color: #3cb4e6; + --footer-fore-color: #ffffff; + --footer-back-color: #03234b; + --footer-border-color: #3cb4e6; + --footer-link-color: #3cb4e6; + --drawer-back-color: #ffffff; + --drawer-hover-back-color: #ffe97f; + --drawer-border-color: #3cb4e6; + --drawer-close-color: #e6007e; } + +header { + height: 2.75rem; + background: var(--header-back-color); + color: var(--header-fore-color); + border-bottom: 0.0714285714rem solid var(--header-border-color); + padding: calc(var(--universal-padding) / 4) 0; + white-space: nowrap; + overflow-x: auto; + overflow-y: hidden; } + header.row { + box-sizing: content-box; } + header .logo { + color: var(--header-fore-color); + font-size: 1.75rem; + padding: var(--universal-padding) calc(2 * var(--universal-padding)); + text-decoration: none; } + header button, header [type="button"], header .button, header [role="button"] { + box-sizing: border-box; + position: relative; + top: calc(0rem - var(--universal-padding) / 4); + height: calc(3.1875rem + var(--universal-padding) / 2); + background: var(--header-back-color); + line-height: calc(3.1875rem - var(--universal-padding) * 1.5); + text-align: center; + color: var(--header-fore-color); + border: 0; + border-radius: 0; + margin: 0; + text-transform: uppercase; } + header button:hover, header button:focus, header [type="button"]:hover, header [type="button"]:focus, header .button:hover, header .button:focus, header [role="button"]:hover, header [role="button"]:focus { + background: var(--header-hover-back-color); } + +nav { + background: var(--nav-back-color); + color: var(--nav-fore-color); + border: 0.0714285714rem solid var(--nav-border-color); + border-radius: var(--universal-border-radius); + margin: var(--universal-margin); } + nav * { + padding: var(--universal-padding) calc(1.5 * var(--universal-padding)); } + nav a, nav a:visited { + display: block; + color: var(--nav-link-color); + border-radius: var(--universal-border-radius); + transition: background 0.3s; } + nav a:hover, nav a:focus, nav a:visited:hover, nav a:visited:focus { + text-decoration: none; + background: var(--nav-hover-back-color); } + nav .sublink-1 { + position: relative; + margin-left: calc(2 * var(--universal-padding)); } + nav .sublink-1:before { + position: absolute; + left: calc(var(--universal-padding) - 1 * var(--universal-padding)); + top: -0.0714285714rem; + content: ''; + height: 100%; + border: 0.0714285714rem solid var(--nav-border-color); + border-left: 0; } + nav .sublink-2 { + position: relative; + margin-left: calc(4 * var(--universal-padding)); } + nav .sublink-2:before { + position: absolute; + left: calc(var(--universal-padding) - 3 * var(--universal-padding)); + top: -0.0714285714rem; + content: ''; + height: 100%; + border: 0.0714285714rem solid var(--nav-border-color); + border-left: 0; } + +footer { + background: var(--footer-back-color); + color: var(--footer-fore-color); + border-top: 0.0714285714rem solid var(--footer-border-color); + padding: calc(2 * var(--universal-padding)) var(--universal-padding); + font-size: 0.875rem; } + footer a, footer a:visited { + color: var(--footer-link-color); } + +header.sticky { + position: -webkit-sticky; + position: sticky; + z-index: 1101; + top: 0; } + +footer.sticky { + position: -webkit-sticky; + position: sticky; + z-index: 1101; + bottom: 0; } + +.drawer-toggle:before { + display: inline-block; + position: relative; + vertical-align: bottom; + content: '\00a0\2261\00a0'; + font-family: sans-serif; + font-size: 1.5em; } +@media screen and (min-width: 500px) { + .drawer-toggle:not(.persistent) { + display: none; } } + +[type="checkbox"].drawer { + height: 1px; + width: 1px; + margin: -1px; + overflow: hidden; + position: absolute; + clip: rect(0 0 0 0); + -webkit-clip-path: inset(100%); + clip-path: inset(100%); } + [type="checkbox"].drawer + * { + display: block; + box-sizing: border-box; + position: fixed; + top: 0; + width: 320px; + height: 100vh; + overflow-y: auto; + background: var(--drawer-back-color); + border: 0.0714285714rem solid var(--drawer-border-color); + border-radius: 0; + margin: 0; + z-index: 1110; + right: -320px; + transition: right 0.3s; } + [type="checkbox"].drawer + * .drawer-close { + position: absolute; + top: var(--universal-margin); + right: var(--universal-margin); + z-index: 1111; + width: 2rem; + height: 2rem; + border-radius: var(--universal-border-radius); + padding: var(--universal-padding); + margin: 0; + cursor: pointer; + transition: background 0.3s; } + [type="checkbox"].drawer + * .drawer-close:before { + display: block; + content: '\00D7'; + color: var(--drawer-close-color); + position: relative; + font-family: sans-serif; + font-size: 2rem; + line-height: 1; + text-align: center; } + [type="checkbox"].drawer + * .drawer-close:hover, [type="checkbox"].drawer + * .drawer-close:focus { + background: var(--drawer-hover-back-color); } + @media screen and (max-width: 320px) { + [type="checkbox"].drawer + * { + width: 100%; } } + [type="checkbox"].drawer:checked + * { + right: 0; } + @media screen and (min-width: 500px) { + [type="checkbox"].drawer:not(.persistent) + * { + position: static; + height: 100%; + z-index: 1100; } + [type="checkbox"].drawer:not(.persistent) + * .drawer-close { + display: none; } } + +/* + Definitions for the responsive table component. +*/ +/* Table module CSS variable definitions. */ +:root { + --table-border-color: #03234b; + --table-border-separator-color: #03234b; + --table-head-back-color: #03234b; + --table-head-fore-color: #ffffff; + --table-body-back-color: #ffffff; + --table-body-fore-color: #03234b; + --table-body-alt-back-color: #f4f4f4; } + +table { + border-collapse: separate; + border-spacing: 0; + margin: 0; + display: flex; + flex: 0 1 auto; + flex-flow: row wrap; + padding: var(--universal-padding); + padding-top: 0; } + table caption { + font-size: 1rem; + margin: calc(2 * var(--universal-margin)) 0; + max-width: 100%; + flex: 0 0 100%; } + table thead, table tbody { + display: flex; + flex-flow: row wrap; + border: 0.0714285714rem solid var(--table-border-color); } + table thead { + z-index: 999; + border-radius: var(--universal-border-radius) var(--universal-border-radius) 0 0; + border-bottom: 0.0714285714rem solid var(--table-border-separator-color); } + table tbody { + border-top: 0; + margin-top: calc(0 - var(--universal-margin)); + border-radius: 0 0 var(--universal-border-radius) var(--universal-border-radius); } + table tr { + display: flex; + padding: 0; } + table th, table td { + padding: calc(0.5 * var(--universal-padding)); + font-size: 0.9rem; } + table th { + text-align: left; + background: var(--table-head-back-color); + color: var(--table-head-fore-color); } + table td { + background: var(--table-body-back-color); + color: var(--table-body-fore-color); + border-top: 0.0714285714rem solid var(--table-border-color); } + +table:not(.horizontal) { + overflow: auto; + max-height: 100%; } + table:not(.horizontal) thead, table:not(.horizontal) tbody { + max-width: 100%; + flex: 0 0 100%; } + table:not(.horizontal) tr { + flex-flow: row wrap; + flex: 0 0 100%; } + table:not(.horizontal) th, table:not(.horizontal) td { + flex: 1 0 0%; + overflow: hidden; + text-overflow: ellipsis; } + table:not(.horizontal) thead { + position: sticky; + top: 0; } + table:not(.horizontal) tbody tr:first-child td { + border-top: 0; } + +table.horizontal { + border: 0; } + table.horizontal thead, table.horizontal tbody { + border: 0; + flex: .2 0 0; + flex-flow: row nowrap; } + table.horizontal tbody { + overflow: auto; + justify-content: space-between; + flex: .8 0 0; + margin-left: 0; + padding-bottom: calc(var(--universal-padding) / 4); } + table.horizontal tr { + flex-direction: column; + flex: 1 0 auto; } + table.horizontal th, table.horizontal td { + width: auto; + border: 0; + border-bottom: 0.0714285714rem solid var(--table-border-color); } + table.horizontal th:not(:first-child), table.horizontal td:not(:first-child) { + border-top: 0; } + table.horizontal th { + text-align: right; + border-left: 0.0714285714rem solid var(--table-border-color); + border-right: 0.0714285714rem solid var(--table-border-separator-color); } + table.horizontal thead tr:first-child { + padding-left: 0; } + table.horizontal th:first-child, table.horizontal td:first-child { + border-top: 0.0714285714rem solid var(--table-border-color); } + table.horizontal tbody tr:last-child td { + border-right: 0.0714285714rem solid var(--table-border-color); } + table.horizontal tbody tr:last-child td:first-child { + border-top-right-radius: 0.25rem; } + table.horizontal tbody tr:last-child td:last-child { + border-bottom-right-radius: 0.25rem; } + table.horizontal thead tr:first-child th:first-child { + border-top-left-radius: 0.25rem; } + table.horizontal thead tr:first-child th:last-child { + border-bottom-left-radius: 0.25rem; } + +@media screen and (max-width: 499px) { + table, table.horizontal { + border-collapse: collapse; + border: 0; + width: 100%; + display: table; } + table thead, table th, table.horizontal thead, table.horizontal th { + border: 0; + height: 1px; + width: 1px; + margin: -1px; + overflow: hidden; + padding: 0; + position: absolute; + clip: rect(0 0 0 0); + -webkit-clip-path: inset(100%); + clip-path: inset(100%); } + table tbody, table.horizontal tbody { + border: 0; + display: table-row-group; } + table tr, table.horizontal tr { + display: block; + border: 0.0714285714rem solid var(--table-border-color); + border-radius: var(--universal-border-radius); + background: #ffffff; + padding: var(--universal-padding); + margin: var(--universal-margin); + margin-bottom: calc(1 * var(--universal-margin)); } + table th, table td, table.horizontal th, table.horizontal td { + width: auto; } + table td, table.horizontal td { + display: block; + border: 0; + text-align: right; } + table td:before, table.horizontal td:before { + content: attr(data-label); + float: left; + font-weight: 600; } + table th:first-child, table td:first-child, table.horizontal th:first-child, table.horizontal td:first-child { + border-top: 0; } + table tbody tr:last-child td, table.horizontal tbody tr:last-child td { + border-right: 0; } } +table tr:nth-of-type(2n) > td { + background: var(--table-body-alt-back-color); } + +@media screen and (max-width: 500px) { + table tr:nth-of-type(2n) { + background: var(--table-body-alt-back-color); } } +:root { + --table-body-hover-back-color: #90caf9; } + +table.hoverable tr:hover, table.hoverable tr:hover > td, table.hoverable tr:focus, table.hoverable tr:focus > td { + background: var(--table-body-hover-back-color); } + +@media screen and (max-width: 500px) { + table.hoverable tr:hover, table.hoverable tr:hover > td, table.hoverable tr:focus, table.hoverable tr:focus > td { + background: var(--table-body-hover-back-color); } } +/* + Definitions for contextual background elements, toasts and tooltips. +*/ +/* Contextual module CSS variable definitions */ +:root { + --mark-back-color: #3cb4e6; + --mark-fore-color: #ffffff; } + +mark { + background: var(--mark-back-color); + color: var(--mark-fore-color); + font-size: 0.95em; + line-height: 1em; + border-radius: var(--universal-border-radius); + padding: calc(var(--universal-padding) / 4) var(--universal-padding); } + mark.inline-block { + display: inline-block; + font-size: 1em; + line-height: 1.4; + padding: calc(var(--universal-padding) / 2) var(--universal-padding); } + +:root { + --toast-back-color: #424242; + --toast-fore-color: #fafafa; } + +.toast { + position: fixed; + bottom: calc(var(--universal-margin) * 3); + left: 50%; + transform: translate(-50%, -50%); + z-index: 1111; + color: var(--toast-fore-color); + background: var(--toast-back-color); + border-radius: calc(var(--universal-border-radius) * 16); + padding: var(--universal-padding) calc(var(--universal-padding) * 3); } + +:root { + --tooltip-back-color: #212121; + --tooltip-fore-color: #fafafa; } + +.tooltip { + position: relative; + display: inline-block; } + .tooltip:before, .tooltip:after { + position: absolute; + opacity: 0; + clip: rect(0 0 0 0); + -webkit-clip-path: inset(100%); + clip-path: inset(100%); + transition: all 0.3s; + z-index: 1010; + left: 50%; } + .tooltip:not(.bottom):before, .tooltip:not(.bottom):after { + bottom: 75%; } + .tooltip.bottom:before, .tooltip.bottom:after { + top: 75%; } + .tooltip:hover:before, .tooltip:hover:after, .tooltip:focus:before, .tooltip:focus:after { + opacity: 1; + clip: auto; + -webkit-clip-path: inset(0%); + clip-path: inset(0%); } + .tooltip:before { + content: ''; + background: transparent; + border: var(--universal-margin) solid transparent; + left: calc(50% - var(--universal-margin)); } + .tooltip:not(.bottom):before { + border-top-color: #212121; } + .tooltip.bottom:before { + border-bottom-color: #212121; } + .tooltip:after { + content: attr(aria-label); + color: var(--tooltip-fore-color); + background: var(--tooltip-back-color); + border-radius: var(--universal-border-radius); + padding: var(--universal-padding); + white-space: nowrap; + transform: translateX(-50%); } + .tooltip:not(.bottom):after { + margin-bottom: calc(2 * var(--universal-margin)); } + .tooltip.bottom:after { + margin-top: calc(2 * var(--universal-margin)); } + +:root { + --modal-overlay-color: rgba(0, 0, 0, 0.45); + --modal-close-color: #e6007e; + --modal-close-hover-color: #ffe97f; } + +[type="checkbox"].modal { + height: 1px; + width: 1px; + margin: -1px; + overflow: hidden; + position: absolute; + clip: rect(0 0 0 0); + -webkit-clip-path: inset(100%); + clip-path: inset(100%); } + [type="checkbox"].modal + div { + position: fixed; + top: 0; + left: 0; + display: none; + width: 100vw; + height: 100vh; + background: var(--modal-overlay-color); } + [type="checkbox"].modal + div .card { + margin: 0 auto; + max-height: 50vh; + overflow: auto; } + [type="checkbox"].modal + div .card .modal-close { + position: absolute; + top: 0; + right: 0; + width: 1.75rem; + height: 1.75rem; + border-radius: var(--universal-border-radius); + padding: var(--universal-padding); + margin: 0; + cursor: pointer; + transition: background 0.3s; } + [type="checkbox"].modal + div .card .modal-close:before { + display: block; + content: '\00D7'; + color: var(--modal-close-color); + position: relative; + font-family: sans-serif; + font-size: 1.75rem; + line-height: 1; + text-align: center; } + [type="checkbox"].modal + div .card .modal-close:hover, [type="checkbox"].modal + div .card .modal-close:focus { + background: var(--modal-close-hover-color); } + [type="checkbox"].modal:checked + div { + display: flex; + flex: 0 1 auto; + z-index: 1200; } + [type="checkbox"].modal:checked + div .card .modal-close { + z-index: 1211; } + +:root { + --collapse-label-back-color: #03234b; + --collapse-label-fore-color: #ffffff; + --collapse-label-hover-back-color: #3cb4e6; + --collapse-selected-label-back-color: #3cb4e6; + --collapse-border-color: var(--collapse-label-back-color); + --collapse-selected-border-color: #ceecf8; + --collapse-content-back-color: #ffffff; + --collapse-selected-label-border-color: #3cb4e6; } + +.collapse { + width: calc(100% - 2 * var(--universal-margin)); + opacity: 1; + display: flex; + flex-direction: column; + margin: var(--universal-margin); + border-radius: var(--universal-border-radius); } + .collapse > [type="radio"], .collapse > [type="checkbox"] { + height: 1px; + width: 1px; + margin: -1px; + overflow: hidden; + position: absolute; + clip: rect(0 0 0 0); + -webkit-clip-path: inset(100%); + clip-path: inset(100%); } + .collapse > label { + flex-grow: 1; + display: inline-block; + height: 1.25rem; + cursor: pointer; + transition: background 0.2s; + color: var(--collapse-label-fore-color); + background: var(--collapse-label-back-color); + border: 0.0714285714rem solid var(--collapse-selected-border-color); + padding: calc(1.25 * var(--universal-padding)); } + .collapse > label:hover, .collapse > label:focus { + background: var(--collapse-label-hover-back-color); } + .collapse > label + div { + flex-basis: auto; + height: 1px; + width: 1px; + margin: -1px; + overflow: hidden; + position: absolute; + clip: rect(0 0 0 0); + -webkit-clip-path: inset(100%); + clip-path: inset(100%); + transition: max-height 0.3s; + max-height: 1px; } + .collapse > :checked + label { + background: var(--collapse-selected-label-back-color); + border-color: var(--collapse-selected-label-border-color); } + .collapse > :checked + label + div { + box-sizing: border-box; + position: relative; + width: 100%; + height: auto; + overflow: auto; + margin: 0; + background: var(--collapse-content-back-color); + border: 0.0714285714rem solid var(--collapse-selected-border-color); + border-top: 0; + padding: var(--universal-padding); + clip: auto; + -webkit-clip-path: inset(0%); + clip-path: inset(0%); + max-height: 100%; } + .collapse > label:not(:first-of-type) { + border-top: 0; } + .collapse > label:first-of-type { + border-radius: var(--universal-border-radius) var(--universal-border-radius) 0 0; } + .collapse > label:last-of-type:not(:first-of-type) { + border-radius: 0 0 var(--universal-border-radius) var(--universal-border-radius); } + .collapse > label:last-of-type:first-of-type { + border-radius: var(--universal-border-radius); } + .collapse > :checked:last-of-type:not(:first-of-type) + label { + border-radius: 0; } + .collapse > :checked:last-of-type + label + div { + border-radius: 0 0 var(--universal-border-radius) var(--universal-border-radius); } + +/* + Custom elements for contextual background elements, toasts and tooltips. +*/ +mark.tertiary { + --mark-back-color: #3cb4e6; } + +mark.tag { + padding: calc(var(--universal-padding)/2) var(--universal-padding); + border-radius: 1em; } + +/* + Definitions for progress elements and spinners. +*/ +/* Progress module CSS variable definitions */ +:root { + --progress-back-color: #3cb4e6; + --progress-fore-color: #555; } + +progress { + display: block; + vertical-align: baseline; + -webkit-appearance: none; + -moz-appearance: none; + appearance: none; + height: 0.75rem; + width: calc(100% - 2 * var(--universal-margin)); + margin: var(--universal-margin); + border: 0; + border-radius: calc(2 * var(--universal-border-radius)); + background: var(--progress-back-color); + color: var(--progress-fore-color); } + progress::-webkit-progress-value { + background: var(--progress-fore-color); + border-top-left-radius: calc(2 * var(--universal-border-radius)); + border-bottom-left-radius: calc(2 * var(--universal-border-radius)); } + progress::-webkit-progress-bar { + background: var(--progress-back-color); } + progress::-moz-progress-bar { + background: var(--progress-fore-color); + border-top-left-radius: calc(2 * var(--universal-border-radius)); + border-bottom-left-radius: calc(2 * var(--universal-border-radius)); } + progress[value="1000"]::-webkit-progress-value { + border-radius: calc(2 * var(--universal-border-radius)); } + progress[value="1000"]::-moz-progress-bar { + border-radius: calc(2 * var(--universal-border-radius)); } + progress.inline { + display: inline-block; + vertical-align: middle; + width: 60%; } + +:root { + --spinner-back-color: #ddd; + --spinner-fore-color: #555; } + +@keyframes spinner-donut-anim { + 0% { + transform: rotate(0deg); } + 100% { + transform: rotate(360deg); } } +.spinner { + display: inline-block; + margin: var(--universal-margin); + border: 0.25rem solid var(--spinner-back-color); + border-left: 0.25rem solid var(--spinner-fore-color); + border-radius: 50%; + width: 1.25rem; + height: 1.25rem; + animation: spinner-donut-anim 1.2s linear infinite; } + +/* + Custom elements for progress bars and spinners. +*/ +progress.primary { + --progress-fore-color: #1976d2; } + +progress.secondary { + --progress-fore-color: #d32f2f; } + +progress.tertiary { + --progress-fore-color: #308732; } + +.spinner.primary { + --spinner-fore-color: #1976d2; } + +.spinner.secondary { + --spinner-fore-color: #d32f2f; } + +.spinner.tertiary { + --spinner-fore-color: #308732; } + +/* + Definitions for icons - powered by Feather (https://feathericons.com/). +*/ +span[class^='icon-'] { + display: inline-block; + height: 1em; + width: 1em; + vertical-align: -0.125em; + background-size: contain; + margin: 0 calc(var(--universal-margin) / 4); } + span[class^='icon-'].secondary { + -webkit-filter: invert(25%); + filter: invert(25%); } + span[class^='icon-'].inverse { + -webkit-filter: invert(100%); + filter: invert(100%); } + +span.icon-alert { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='8' x2='12' y2='12'%3E%3C/line%3E%3Cline x1='12' y1='16' x2='12' y2='16'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-bookmark { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M19 21l-7-5-7 5V5a2 2 0 0 1 2-2h10a2 2 0 0 1 2 2z'%3E%3C/path%3E%3C/svg%3E"); } +span.icon-calendar { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='3' y='4' width='18' height='18' rx='2' ry='2'%3E%3C/rect%3E%3Cline x1='16' y1='2' x2='16' y2='6'%3E%3C/line%3E%3Cline x1='8' y1='2' x2='8' y2='6'%3E%3C/line%3E%3Cline x1='3' y1='10' x2='21' y2='10'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-credit { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='1' y='4' width='22' height='16' rx='2' ry='2'%3E%3C/rect%3E%3Cline x1='1' y1='10' x2='23' y2='10'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-edit { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M20 14.66V20a2 2 0 0 1-2 2H4a2 2 0 0 1-2-2V6a2 2 0 0 1 2-2h5.34'%3E%3C/path%3E%3Cpolygon points='18 2 22 6 12 16 8 16 8 12 18 2'%3E%3C/polygon%3E%3C/svg%3E"); } +span.icon-link { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M18 13v6a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2V8a2 2 0 0 1 2-2h6'%3E%3C/path%3E%3Cpolyline points='15 3 21 3 21 9'%3E%3C/polyline%3E%3Cline x1='10' y1='14' x2='21' y2='3'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-help { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M9.09 9a3 3 0 0 1 5.83 1c0 2-3 3-3 3'%3E%3C/path%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='17' x2='12' y2='17'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-home { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M3 9l9-7 9 7v11a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2z'%3E%3C/path%3E%3Cpolyline points='9 22 9 12 15 12 15 22'%3E%3C/polyline%3E%3C/svg%3E"); } +span.icon-info { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='16' x2='12' y2='12'%3E%3C/line%3E%3Cline x1='12' y1='8' x2='12' y2='8'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-lock { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='3' y='11' width='18' height='11' rx='2' ry='2'%3E%3C/rect%3E%3Cpath d='M7 11V7a5 5 0 0 1 10 0v4'%3E%3C/path%3E%3C/svg%3E"); } +span.icon-mail { + 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.hidden-md { + display: none !important; } } +@media screen and (min-width: 1280px) { + .hidden-lg { + display: none !important; } } +@media screen and (max-width: 499px) { + .visually-hidden-sm { + position: absolute !important; + width: 1px !important; + height: 1px !important; + margin: -1px !important; + border: 0 !important; + padding: 0 !important; + clip: rect(0 0 0 0) !important; + -webkit-clip-path: inset(100%) !important; + clip-path: inset(100%) !important; + overflow: hidden !important; } } +@media screen and (min-width: 500px) and (max-width: 1279px) { + .visually-hidden-md { + position: absolute !important; + width: 1px !important; + height: 1px !important; + margin: -1px !important; + border: 0 !important; + padding: 0 !important; + clip: rect(0 0 0 0) !important; + -webkit-clip-path: inset(100%) !important; + clip-path: inset(100%) !important; + overflow: hidden !important; } } +@media screen and (min-width: 1280px) { + .visually-hidden-lg { + position: absolute !important; + width: 1px !important; + height: 1px !important; + margin: -1px !important; + border: 0 !important; + padding: 0 !important; + clip: rect(0 0 0 0) !important; + -webkit-clip-path: inset(100%) !important; + clip-path: inset(100%) !important; + overflow: hidden !important; } } + +/*# sourceMappingURL=mini-custom.css.map */ + +img[alt="ST logo"] { display: block; margin: auto; width: 75%; max-width: 250px; min-width: 71px; } +img[alt="Cube logo"] { float: right; width: 30%; max-width: 10rem; min-width: 8rem; padding-right: 1rem;} + +.figure { + display: block; + margin-left: auto; + margin-right: auto; + text-align: center; +} \ No newline at end of file diff --git a/Drivers/BSP/STM32WLxx_Nucleo/_htmresc/st_logo_2020.png b/Drivers/BSP/STM32WLxx_Nucleo/_htmresc/st_logo_2020.png new file mode 100644 index 0000000..d6cebb5 Binary files /dev/null and b/Drivers/BSP/STM32WLxx_Nucleo/_htmresc/st_logo_2020.png differ diff --git a/Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo.c b/Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo.c new file mode 100644 index 0000000..9fe68e0 --- /dev/null +++ b/Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo.c @@ -0,0 +1,715 @@ +/** + ****************************************************************************** + * @file stm32wlxx_nucleo.c + * @author MCD Application Team + * @brief This file provides set of firmware functions to manage: + * - LEDs and push-buttons available on STM32WLXX-Nucleo + * Kit from STMicroelectronics + ****************************************************************************** + * @attention + * + * Copyright (c) 2020-2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wlxx_nucleo.h" + +#if defined(__ICCARM__) +#include +#endif /* __ICCARM__ */ + +/** @addtogroup BSP + * @{ + */ + +/** @addtogroup STM32WLXX_NUCLEO + * @{ + */ + +/** @addtogroup STM32WLXX_NUCLEO_LOW_LEVEL + * @brief This file provides set of firmware functions to manage LEDs and push-buttons + * on STM32WLXX-Nucleo Kit from STMicroelectronics. + * @{ + */ + + +/** @defgroup STM32WLXX_NUCLEO_LOW_LEVEL_Exported_Variables LOW LEVEL Exported Variables + * @{ + */ +EXTI_HandleTypeDef hpb_exti[BUTTONn]; +#if (USE_BSP_COM_FEATURE > 0) +UART_HandleTypeDef hcom_uart[COMn]; +#endif /* (USE_BSP_COM_FEATURE > 0) */ +/** + * @} + */ + +/** @defgroup STM32WLXX_NUCLEO_LOW_LEVEL_Private_Defines LOW LEVEL Private Defines + * @{ + */ +#if (USE_COM_LOG == 1) +/** + * @brief Redirect console output to COM + */ +#if defined(__ICCARM__) +/* New definition from EWARM V9, compatible with EWARM8 */ +int iar_fputc(int ch); +#define PUTCHAR_PROTOTYPE int iar_fputc(int ch) +#elif defined (__CC_ARM) || defined(__ARMCC_VERSION) +/* ARM Compiler 5/6 */ +#define PUTCHAR_PROTOTYPE int fputc(int ch, FILE *f) +#elif defined(__GNUC__) +#define PUTCHAR_PROTOTYPE int __io_putchar(int ch) +#endif /* __ICCARM__ */ + +#endif /* USE_COM_LOG */ + +/** + * @} + */ + +/** @defgroup STM32WLXX_NUCLEO_LOW_LEVEL_Private_TypesDefinitions LOW LEVEL Private Typedef + * @{ + */ +typedef void (* BSP_EXTI_LineCallback) (void); +/** + * @} + */ + +/** @defgroup STM32WLXX_NUCLEO_LOW_LEVEL_Private_Variables LOW LEVEL Private Variables + * @{ + */ +static GPIO_TypeDef* LED_PORT[LEDn] = {LED1_GPIO_PORT, LED2_GPIO_PORT, LED3_GPIO_PORT}; + +static const uint16_t LED_PIN[LEDn] = {LED1_PIN, LED2_PIN, LED3_PIN}; + +static GPIO_TypeDef* BUTTON_PORT[BUTTONn] = {BUTTON_SW1_GPIO_PORT, BUTTON_SW2_GPIO_PORT, BUTTON_SW3_GPIO_PORT}; + +static const uint16_t BUTTON_PIN[BUTTONn] = {BUTTON_SW1_PIN, BUTTON_SW2_PIN, BUTTON_SW3_PIN}; + +static const IRQn_Type BUTTON_IRQn[BUTTONn] = {BUTTON_SW1_EXTI_IRQn, BUTTON_SW2_EXTI_IRQn, BUTTON_SW3_EXTI_IRQn}; + +#if (USE_BSP_COM_FEATURE > 0) +static USART_TypeDef* COM_USART[COMn] = {COM1_UART}; + +#if (USE_COM_LOG > 0) +static COM_TypeDef COM_ActiveLogPort = COM1; +#endif + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +static uint32_t IsComMspCbValid[COMn] = {0}; +#endif +#endif /* (USE_BSP_COM_FEATURE > 0) */ +/** + * @} + */ + +/** @defgroup STM32WLXX_NUCLEO_LOW_LEVEL_Private_Functions LOW LEVEL Private Functions + * @{ + */ +static void BUTTON_SW1_EXTI_Callback(void); +static void BUTTON_SW2_EXTI_Callback(void); +static void BUTTON_SW3_EXTI_Callback(void); +#if (USE_BSP_COM_FEATURE > 0) +static void COM1_MspInit(UART_HandleTypeDef *huart); +static void COM1_MspDeInit(UART_HandleTypeDef *huart); +#endif /* (USE_BSP_COM_FEATURE > 0) */ +/** + * @} + */ + + +/** @addtogroup STM32WLXX_NUCLEO_LOW_LEVEL_Exported_Functions + * @{ + */ + +/** + * @brief This method returns the STM32WLXX NUCLEO BSP Driver revision + * @retval version: 0xXYZR (8bits for each decimal, R for RC) + */ +uint32_t BSP_GetVersion(void) +{ + return (int32_t)__STM32WLXX_NUCLEO_BSP_VERSION; +} + +/** @addtogroup STM32WLXX_NUCLEO_LOW_LEVEL_LED_Functions + * @{ + */ + +/** + * @brief Configures LED GPIO. + * @param Led: LED to be configured. + * This parameter can be one of the following values: + * @arg LED1 + * @arg LED2 + * @arg LED3 + * @retval BSP status + */ +int32_t BSP_LED_Init(Led_TypeDef Led) +{ + GPIO_InitTypeDef gpio_init_structure = {0}; + + /* Enable the GPIO_LED Clock */ + LEDx_GPIO_CLK_ENABLE(Led); + + /* Configure the GPIO_LED pin */ + gpio_init_structure.Pin = LED_PIN[Led]; + gpio_init_structure.Mode = GPIO_MODE_OUTPUT_PP; + gpio_init_structure.Pull = GPIO_NOPULL; + gpio_init_structure.Speed = GPIO_SPEED_FREQ_HIGH; + + HAL_GPIO_Init(LED_PORT[Led], &gpio_init_structure); + HAL_GPIO_WritePin(LED_PORT[Led], LED_PIN[Led], GPIO_PIN_RESET); + + return BSP_ERROR_NONE; +} + +/** + * @brief DeInit LEDs. + * @param Led: LED to be de-init. + * This parameter can be one of the following values: + * @arg LED1 + * @arg LED2 + * @arg LED3 + * @note Led DeInit does not disable the GPIO clock nor disable the Mfx + * @retval BSP status + */ +int32_t BSP_LED_DeInit(Led_TypeDef Led) +{ + /* Turn off LED */ + HAL_GPIO_WritePin(LED_PORT[Led], LED_PIN[Led], GPIO_PIN_RESET); + + /* DeInit the GPIO_LED pin */ + HAL_GPIO_DeInit(LED_PORT[Led], LED_PIN[Led]); + + return BSP_ERROR_NONE; +} + +/** + * @brief Turns selected LED On. + * @param Led: Specifies the Led to be set on. + * This parameter can be one of the following values: + * @arg LED1 + * @arg LED2 + * @arg LED3 + * @retval BSP status + */ +int32_t BSP_LED_On(Led_TypeDef Led) +{ + HAL_GPIO_WritePin(LED_PORT[Led], LED_PIN[Led], GPIO_PIN_SET); + + return BSP_ERROR_NONE; +} + +/** + * @brief Turns selected LED Off. + * @param Led: Specifies the Led to be set off. + * This parameter can be one of the following values: + * @arg LED1 + * @arg LED2 + * @arg LED3 + * @retval BSP status + */ +int32_t BSP_LED_Off(Led_TypeDef Led) +{ + HAL_GPIO_WritePin(LED_PORT[Led], LED_PIN[Led], GPIO_PIN_RESET); + + return BSP_ERROR_NONE; +} + +/** + * @brief Toggles the selected LED. + * @param Led: Specifies the Led to be toggled. + * This parameter can be one of the following values: + * @arg LED1 + * @arg LED2 + * @arg LED3 + * @retval BSP status + */ +int32_t BSP_LED_Toggle(Led_TypeDef Led) +{ + HAL_GPIO_TogglePin(LED_PORT[Led], LED_PIN[Led]); + + return BSP_ERROR_NONE; +} + +/** + * @brief Get the status of the selected LED. + * @param Led Specifies the Led to get its state. + * This parameter can be one of following parameters: + * @arg LED1 + * @arg LED2 + * @arg LED3 + * @retval LED status + */ +int32_t BSP_LED_GetState(Led_TypeDef Led) +{ + return (int32_t)HAL_GPIO_ReadPin(LED_PORT[Led], LED_PIN[Led]); +} + +/** + * @} + */ + +/** @addtogroup STM32WLXX_NUCLEO_LOW_LEVEL_BUTTON_Functions + * @{ + */ + +/** + * @brief Configures Button GPIO and EXTI Line. + * @param Button: Specifies the Button to be configured. + * This parameter can be one of following parameters: + * @arg BUTTON_SW1 + * @arg BUTTON_SW2 + * @arg BUTTON_SW3 + * @param ButtonMode: Specifies Button mode. + * This parameter can be one of following parameters: + * @arg BUTTON_MODE_GPIO: Button will be used as simple IO + * @arg BUTTON_MODE_EXTI: Button will be connected to EXTI line with interrupt + * generation capability + * @retval BSP status + */ +int32_t BSP_PB_Init(Button_TypeDef Button, ButtonMode_TypeDef ButtonMode) +{ + GPIO_InitTypeDef gpio_init_structure = {0}; + static BSP_EXTI_LineCallback button_callback[BUTTONn] = {BUTTON_SW1_EXTI_Callback, BUTTON_SW2_EXTI_Callback, BUTTON_SW3_EXTI_Callback}; + static uint32_t button_interrupt_priority[BUTTONn] = {BSP_BUTTON_USER_IT_PRIORITY, BSP_BUTTON_USER_IT_PRIORITY, BSP_BUTTON_USER_IT_PRIORITY}; + static const uint32_t button_exti_line[BUTTONn] = {BUTTON_SW1_EXTI_LINE, BUTTON_SW2_EXTI_LINE, BUTTON_SW3_EXTI_LINE}; + + /* Enable the BUTTON Clock */ + BUTTONx_GPIO_CLK_ENABLE(Button); + + gpio_init_structure.Pin = BUTTON_PIN[Button]; + gpio_init_structure.Pull = GPIO_PULLUP; + gpio_init_structure.Speed = GPIO_SPEED_FREQ_HIGH; + + if(ButtonMode == BUTTON_MODE_GPIO) + { + /* Configure Button pin as input */ + gpio_init_structure.Mode = GPIO_MODE_INPUT; + HAL_GPIO_Init(BUTTON_PORT[Button], &gpio_init_structure); + } + else /* (ButtonMode == BUTTON_MODE_EXTI) */ + { + /* Configure Button pin as input with External interrupt */ + gpio_init_structure.Mode = GPIO_MODE_IT_FALLING; + + HAL_GPIO_Init(BUTTON_PORT[Button], &gpio_init_structure); + + (void)HAL_EXTI_GetHandle(&hpb_exti[Button], button_exti_line[Button]); + (void)HAL_EXTI_RegisterCallback(&hpb_exti[Button], HAL_EXTI_COMMON_CB_ID, button_callback[Button]); + + /* Enable and set Button EXTI Interrupt to the lowest priority */ + HAL_NVIC_SetPriority((BUTTON_IRQn[Button]), button_interrupt_priority[Button], 0x00); + HAL_NVIC_EnableIRQ((BUTTON_IRQn[Button])); + } + + return BSP_ERROR_NONE; +} + +/** + * @brief Push Button DeInit. + * @param Button: Button to be configured + * This parameter can be one of following parameters: + * @arg BUTTON_SW1 + * @arg BUTTON_SW2 + * @arg BUTTON_SW3 + * @note PB DeInit does not disable the GPIO clock + * @retval BSP status + */ +int32_t BSP_PB_DeInit(Button_TypeDef Button) +{ + HAL_NVIC_DisableIRQ((BUTTON_IRQn[Button])); + HAL_GPIO_DeInit(BUTTON_PORT[Button], BUTTON_PIN[Button]); + + return BSP_ERROR_NONE; +} + +/** + * @brief Returns the selected Button state. + * @param Button: Specifies the Button to be checked. + * This parameter can be one of following parameters: + * @arg BUTTON_SW1 + * @arg BUTTON_SW2 + * @arg BUTTON_SW3 + * @retval The Button GPIO pin value. + */ +int32_t BSP_PB_GetState(Button_TypeDef Button) +{ + return (int32_t)HAL_GPIO_ReadPin(BUTTON_PORT[Button], BUTTON_PIN[Button]); +} + +/** + * @brief This function handles Push-Button interrupt requests. + * @param Button Specifies the pin connected EXTI line + * @retval None + */ +void BSP_PB_IRQHandler(Button_TypeDef Button) +{ + HAL_EXTI_IRQHandler(&hpb_exti[Button]); +} + +/** + * @brief BSP Push Button callback + * @param Button: Specifies the Button to be checked. + * This parameter can be one of following parameters: + * @arg BUTTON_SW1 + * @arg BUTTON_SW2 + * @arg BUTTON_SW3 + * @retval None. + */ +__weak void BSP_PB_Callback(Button_TypeDef Button) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(Button); + + /* This function should be implemented by the user application. + It is called into this driver when an event on Button is triggered. */ +} + +/** + * @} + */ + +#if (USE_BSP_COM_FEATURE > 0) +/** @addtogroup STM32WLXX_NUCLEO_LOW_LEVEL_COM_Functions + * @{ + */ +/** + * @brief Configures COM port. + * @param COM COM port to be configured. + * This parameter can be COM1 + * @param COM_Init Pointer to a UART_HandleTypeDef structure that contains the + * configuration information for the specified USART peripheral. + * @retval BSP error code + */ +int32_t BSP_COM_Init(COM_TypeDef COM, COM_InitTypeDef *COM_Init) +{ + int32_t ret = BSP_ERROR_NONE; + + if(COM > COMn) + { + ret = BSP_ERROR_WRONG_PARAM; + } + else + { +#if (USE_HAL_UART_REGISTER_CALLBACKS == 0) + /* Init the UART Msp */ + COM1_MspInit(&hcom_uart[COM]); +#else + if(IsComMspCbValid == 0U) + { + if(BSP_COM_RegisterDefaultMspCallbacks(COM) != BSP_ERROR_NONE) + { + return BSP_ERROR_MSP_FAILURE; + } + } +#endif + + if(MX_LPUART1_Init(&hcom_uart[COM], COM_Init) != HAL_OK) + { + return BSP_ERROR_PERIPH_FAILURE; + } + } + + return ret; +} + +/** + * @brief DeInit COM port. + * @param COM COM port to be configured. + * This parameter can be COM1 + * @retval BSP status + */ +int32_t BSP_COM_DeInit(COM_TypeDef COM) +{ + int32_t ret = BSP_ERROR_NONE; + + if(COM >= COMn) + { + ret = BSP_ERROR_WRONG_PARAM; + } + else + { + /* USART configuration */ + hcom_uart[COM].Instance = COM_USART[COM]; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 0) + COM1_MspDeInit(&hcom_uart[COM]); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS == 0) */ + + if(HAL_UART_DeInit(&hcom_uart[COM]) != HAL_OK) + { + return BSP_ERROR_PERIPH_FAILURE; + } + } + + return ret; +} + +/** + * @brief Configures COM port. + * @param huart USART handle + * @param COM_Init Pointer to a UART_HandleTypeDef structure that contains the + * configuration information for the specified USART peripheral. + * @retval HAL error code + */ +__weak HAL_StatusTypeDef MX_LPUART1_Init(UART_HandleTypeDef *huart, MX_UART_InitTypeDef *COM_Init) +{ + /* USART configuration */ + huart->Instance = COM_USART[COM1]; + huart->Init.BaudRate = COM_Init->BaudRate; + huart->Init.Mode = UART_MODE_TX_RX; + huart->Init.Parity = (uint32_t)COM_Init->Parity; + huart->Init.WordLength = COM_Init->WordLength; + huart->Init.StopBits = (uint32_t)COM_Init->StopBits; + huart->Init.HwFlowCtl = (uint32_t)COM_Init->HwFlowCtl; + huart->Init.OverSampling = UART_OVERSAMPLING_8; + + return HAL_UART_Init(huart); +} + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +/** + * @brief Register Default COM Msp Callbacks + * @param COM COM port to be configured. + * This parameter can be COM1 + * @retval BSP status + */ +int32_t BSP_COM_RegisterDefaultMspCallbacks(COM_TypeDef COM) +{ + int32_t ret = BSP_ERROR_NONE; + + if(COM >= COMn) + { + ret = BSP_ERROR_WRONG_PARAM; + } + else + { + __HAL_UART_RESET_HANDLE_STATE(&hcom_uart[COM]); + + /* Register default MspInit/MspDeInit Callback */ + if(HAL_UART_RegisterCallback(&hcom_uart[COM], HAL_UART_MSPINIT_CB_ID, COM1_MspInit) != HAL_OK) + { + ret = BSP_ERROR_PERIPH_FAILURE; + } + else if(HAL_UART_RegisterCallback(&hcom_uart[COM], HAL_UART_MSPDEINIT_CB_ID, COM1_MspDeInit) != HAL_OK) + { + ret = BSP_ERROR_PERIPH_FAILURE; + } + else + { + IsComMspCbValid[COM] = 1U; + } + } + + /* BSP status */ + return ret; +} + +/** + * @brief Register COM Msp Callback registering + * @param COM COM port to be configured. + * This parameter can be COM1 + * @param Callbacks pointer to COM1 MspInit/MspDeInit callback functions + * @retval BSP status + */ +int32_t BSP_COM_RegisterMspCallbacks(COM_TypeDef COM , BSP_COM_Cb_t *Callback) +{ + int32_t ret = BSP_ERROR_NONE; + + if(COM >= COMn) + { + ret = BSP_ERROR_WRONG_PARAM; + } + else + { + __HAL_UART_RESET_HANDLE_STATE(&hcom_uart[COM]); + + /* Register MspInit/MspDeInit Callbacks */ + if(HAL_UART_RegisterCallback(&hcom_uart[COM], HAL_UART_MSPINIT_CB_ID, Callback->pMspInitCb) != HAL_OK) + { + ret = BSP_ERROR_PERIPH_FAILURE; + } + else if(HAL_UART_RegisterCallback(&hcom_uart[COM], HAL_UART_MSPDEINIT_CB_ID, Callback->pMspDeInitCb) != HAL_OK) + { + ret = BSP_ERROR_PERIPH_FAILURE; + } + else + { + IsComMspCbValid[COM] = 1U; + } + } + /* BSP status */ + return ret; +} +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + +#if (USE_COM_LOG > 0) +/** + * @brief Select the active COM port. + * @param COM COM port to be activated. + * This parameter can be COM1 + * @retval BSP status + */ +int32_t BSP_COM_SelectLogPort(COM_TypeDef COM) +{ + if(COM_ActiveLogPort != COM) + { + COM_ActiveLogPort = COM; + } + return BSP_ERROR_NONE; +} + +#if defined(__ICCARM__) +/** + * @brief Retargets the C library __write function to the IAR function iar_fputc. + * @param file: file descriptor. + * @param ptr: pointer to the buffer where the data is stored. + * @param len: length of the data to write in bytes. + * @retval length of the written data in bytes. + */ +size_t __write(int file, unsigned char const *ptr, size_t len) +{ + size_t idx; + unsigned char const *pdata = ptr; + + for (idx = 0; idx < len; idx++) + { + iar_fputc((int)*pdata); + pdata++; + } + return len; +} +#endif /* __ICCARM__ */ + +/** + * @brief Redirect console output to COM + */ +PUTCHAR_PROTOTYPE +{ + (void) HAL_UART_Transmit(&hcom_uart [COM_ActiveLogPort], (uint8_t *) &ch, 1, COM_POLL_TIMEOUT); + return ch; +} +#endif /* USE_COM_LOG */ +/** + * @} + */ +#endif /* (USE_BSP_COM_FEATURE > 0) */ + +/** + * @} + */ + +/** @addtogroup STM32WLXX_NUCLEO_LOW_LEVEL_Private_Functions + * @{ + */ + +/** + * @brief Button SW1 EXTI line detection callback. + * @retval None + */ +static void BUTTON_SW1_EXTI_Callback(void) +{ + BSP_PB_Callback(BUTTON_SW1); +} + +/** + * @brief Button SW2 EXTI line detection callback. + * @retval None + */ +static void BUTTON_SW2_EXTI_Callback(void) +{ + BSP_PB_Callback(BUTTON_SW2); +} + +/** + * @brief Button SW3 EXTI line detection callback. + * @retval None + */ +static void BUTTON_SW3_EXTI_Callback(void) +{ + BSP_PB_Callback(BUTTON_SW3); +} + +#if (USE_BSP_COM_FEATURE > 0) +/** + * @brief Initializes COM1 MSP. + * @param huart UART handle + * @retval BSP status + */ +static void COM1_MspInit(UART_HandleTypeDef *huart) +{ + GPIO_InitTypeDef gpio_init_structure; + + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* Enable GPIO clock */ + COM1_TX_GPIO_CLK_ENABLE(); + COM1_RX_GPIO_CLK_ENABLE(); + + /* Enable USART clock */ + COM1_CLK_ENABLE(); + + /* Configure USART Tx as alternate function */ + gpio_init_structure.Pin = COM1_TX_PIN; + gpio_init_structure.Mode = GPIO_MODE_AF_PP; + gpio_init_structure.Speed = GPIO_SPEED_FREQ_HIGH; + gpio_init_structure.Pull = GPIO_PULLUP; + gpio_init_structure.Alternate = COM1_TX_AF; + HAL_GPIO_Init(COM1_TX_GPIO_PORT, &gpio_init_structure); + + /* Configure USART Rx as alternate function */ + gpio_init_structure.Pin = COM1_RX_PIN; + gpio_init_structure.Mode = GPIO_MODE_AF_PP; + gpio_init_structure.Alternate = COM1_RX_AF; + HAL_GPIO_Init(COM1_RX_GPIO_PORT, &gpio_init_structure); +} + +/** + * @brief DeInitialize COM1 MSP part + * @param huart UART handle + * @retval BSP status + */ +static void COM1_MspDeInit(UART_HandleTypeDef *huart) +{ + GPIO_InitTypeDef gpio_init_structure; + + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* COM GPIO pin configuration */ + gpio_init_structure.Pin = COM1_TX_PIN; + HAL_GPIO_DeInit(COM1_TX_GPIO_PORT, gpio_init_structure.Pin); + + gpio_init_structure.Pin = COM1_RX_PIN; + HAL_GPIO_DeInit(COM1_RX_GPIO_PORT, gpio_init_structure.Pin); + + /* Disable USART clock */ + COM1_CLK_DISABLE(); +} +#endif /* (USE_BSP_COM_FEATURE > 0) */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo.h b/Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo.h new file mode 100644 index 0000000..c9d52aa --- /dev/null +++ b/Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo.h @@ -0,0 +1,352 @@ +/** + ****************************************************************************** + * @file stm32wlxx_nucleo.h + * @author MCD Application Team + * @brief Header for stm32wlxx_nucleo.c + ****************************************************************************** + * @attention + * + * Copyright (c) 2020-2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32WLXX_NUCLEO_H +#define STM32WLXX_NUCLEO_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wlxx_nucleo_errno.h" +#include "stm32wlxx_nucleo_conf.h" + +#if (USE_BSP_COM_FEATURE == 1) +#include "stdio.h" +#endif + +/** @addtogroup BSP + * @{ + */ + +/** @defgroup STM32WLXX_NUCLEO STM32WLXX-NUCLEO + * @{ + */ + +/** @defgroup STM32WLXX_NUCLEO_LOW_LEVEL LOW LEVEL + * @{ + */ + +/** @defgroup STM32WLXX_NUCLEO_LOW_LEVEL_Exported_Types LOW LEVEL Exported Types + * @{ + */ +typedef enum +{ + LED1 = 0, + LED2 = 1, + LED3 = 2, + /* Color led aliases */ + LED_BLUE = LED1, + LED_GREEN = LED2, + LED_RED = LED3 +}Led_TypeDef; + +typedef enum +{ + BUTTON_SW1 = 0, + BUTTON_SW2 = 1, + BUTTON_SW3 = 2, +}Button_TypeDef; + +typedef enum +{ + BUTTON_MODE_GPIO = 0, + BUTTON_MODE_EXTI = 1 +}ButtonMode_TypeDef; + +#if (USE_BSP_COM_FEATURE > 0) +typedef enum +{ + COM1 = 0U, + COMn +}COM_TypeDef; + +typedef enum +{ + COM_STOPBITS_1 = UART_STOPBITS_1, + COM_STOPBITS_2 = UART_STOPBITS_2, +}COM_StopBitsTypeDef; + +typedef enum +{ + COM_PARITY_NONE = UART_PARITY_NONE, + COM_PARITY_EVEN = UART_PARITY_EVEN, + COM_PARITY_ODD = UART_PARITY_ODD, +}COM_ParityTypeDef; + +typedef enum +{ + COM_HWCONTROL_NONE = UART_HWCONTROL_NONE, + COM_HWCONTROL_RTS = UART_HWCONTROL_RTS, + COM_HWCONTROL_CTS = UART_HWCONTROL_CTS, + COM_HWCONTROL_RTS_CTS = UART_HWCONTROL_RTS_CTS, +}COM_HwFlowCtlTypeDef; + +typedef enum +{ + COM_WORDLENGTH_7B = UART_WORDLENGTH_7B, + COM_WORDLENGTH_8B = UART_WORDLENGTH_8B, + COM_WORDLENGTH_9B = UART_WORDLENGTH_9B, +}COM_WordLengthTypeDef; + +typedef struct +{ + uint32_t BaudRate; + COM_WordLengthTypeDef WordLength; + COM_StopBitsTypeDef StopBits; + COM_ParityTypeDef Parity; + COM_HwFlowCtlTypeDef HwFlowCtl; +}COM_InitTypeDef; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +typedef struct +{ + pUART_CallbackTypeDef pMspInitCb; + pUART_CallbackTypeDef pMspDeInitCb; +}BSP_COM_Cb_t; +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS == 1) */ +#endif /* (USE_BSP_COM_FEATURE > 0) */ + +typedef enum +{ + ABSENT = 0, + PRESENT = 1, +}Presence_TypeDef; +/** + * @} + */ + +/** @defgroup STM32WLXX_NUCLEO_LOW_LEVEL_Exported_Constants LOW LEVEL Exported Constants + * @{ + */ + +/** + * @brief STM32WLXX NUCLEO BSP Driver version number + */ +#define __STM32WLXX_NUCLEO_BSP_VERSION_MAIN (0x01U) /*!< [31:24] main version */ +#define __STM32WLXX_NUCLEO_BSP_VERSION_SUB1 (0x03U) /*!< [23:16] sub1 version */ +#define __STM32WLXX_NUCLEO_BSP_VERSION_SUB2 (0x01U) /*!< [15:8] sub2 version */ +#define __STM32WLXX_NUCLEO_BSP_VERSION_RC (0x00U) /*!< [7:0] release candidate */ +#define __STM32WLXX_NUCLEO_BSP_VERSION ((__STM32WLXX_NUCLEO_BSP_VERSION_MAIN << 24)\ + |(__STM32WLXX_NUCLEO_BSP_VERSION_SUB1 << 16)\ + |(__STM32WLXX_NUCLEO_BSP_VERSION_SUB2 << 8 )\ + |(__STM32WLXX_NUCLEO_BSP_VERSION_RC)) + +/** + * @brief Define for STM32WLXX_NUCLEO board + */ +#if !defined (USE_STM32WLXX_NUCLEO) + #define USE_STM32WLXX_NUCLEO +#endif + +/** @defgroup STM32WLXX_NUCLEO_LOW_LEVEL_LED LOW LEVEL LED Constants + * @{ + */ +#define LEDn 3 + +#define LED1_PIN GPIO_PIN_15 +#define LED1_GPIO_PORT GPIOB +#define LED1_GPIO_CLK_ENABLE() __HAL_RCC_GPIOB_CLK_ENABLE() +#define LED1_GPIO_CLK_DISABLE() __HAL_RCC_GPIOB_CLK_DISABLE() + +#define LED2_PIN GPIO_PIN_9 +#define LED2_GPIO_PORT GPIOB +#define LED2_GPIO_CLK_ENABLE() __HAL_RCC_GPIOB_CLK_ENABLE() +#define LED2_GPIO_CLK_DISABLE() __HAL_RCC_GPIOB_CLK_DISABLE() + +#define LED3_PIN GPIO_PIN_11 +#define LED3_GPIO_PORT GPIOB +#define LED3_GPIO_CLK_ENABLE() __HAL_RCC_GPIOB_CLK_ENABLE() +#define LED3_GPIO_CLK_DISABLE() __HAL_RCC_GPIOB_CLK_DISABLE() + +#define LEDx_GPIO_CLK_ENABLE(__INDEX__) __HAL_RCC_GPIOB_CLK_ENABLE() /* All Led on same port */ +#define LEDx_GPIO_CLK_DISABLE(__INDEX__) __HAL_RCC_GPIOB_CLK_DISABLE() /* All Led on same port */ +/** + * @} + */ + +/** @defgroup STM32WLXX_NUCLEO_LOW_LEVEL_BUTTON LOW LEVEL BUTTON Constants + * @{ + */ +#define BUTTONn 3 + +/** + * @brief Key push-buttons + */ +#define BUTTON_SW1_PIN GPIO_PIN_0 +#define BUTTON_SW1_GPIO_PORT GPIOA +#define BUTTON_SW1_GPIO_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE() +#define BUTTON_SW1_GPIO_CLK_DISABLE() __HAL_RCC_GPIOA_CLK_DISABLE() +#define BUTTON_SW1_EXTI_LINE EXTI_LINE_0 +#ifdef CORE_CM0PLUS +#define BUTTON_SW1_EXTI_IRQn EXTI1_0_IRQn +#else +#define BUTTON_SW1_EXTI_IRQn EXTI0_IRQn +#endif +#define H_EXTI_0 hpb_exti[BUTTON_SW1] + +#define BUTTON_SW2_PIN GPIO_PIN_1 +#define BUTTON_SW2_GPIO_PORT GPIOA +#define BUTTON_SW2_GPIO_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE() +#define BUTTON_SW2_GPIO_CLK_DISABLE() __HAL_RCC_GPIOA_CLK_DISABLE() +#define BUTTON_SW2_EXTI_LINE EXTI_LINE_1 +#ifdef CORE_CM0PLUS +#define BUTTON_SW2_EXTI_IRQn EXTI1_0_IRQn +#else +#define BUTTON_SW2_EXTI_IRQn EXTI1_IRQn +#endif +#define H_EXTI_1 hpb_exti[BUTTON_SW2] + +#define BUTTON_SW3_PIN GPIO_PIN_6 +#define BUTTON_SW3_GPIO_PORT GPIOC +#define BUTTON_SW3_GPIO_CLK_ENABLE() __HAL_RCC_GPIOC_CLK_ENABLE() +#define BUTTON_SW3_GPIO_CLK_DISABLE() __HAL_RCC_GPIOC_CLK_DISABLE() +#define BUTTON_SW3_EXTI_LINE EXTI_LINE_6 +#ifdef CORE_CM0PLUS +#define BUTTON_SW3_EXTI_IRQn EXTI15_4_IRQn +#else +#define BUTTON_SW3_EXTI_IRQn EXTI9_5_IRQn +#endif +#define H_EXTI_6 hpb_exti[BUTTON_SW3] + +#define BUTTONx_GPIO_CLK_ENABLE(__INDEX__) do { if ((__INDEX__) == BUTTON_SW1) BUTTON_SW1_GPIO_CLK_ENABLE(); else \ + if ((__INDEX__) == BUTTON_SW2) BUTTON_SW2_GPIO_CLK_ENABLE(); else \ + if ((__INDEX__) == BUTTON_SW3) BUTTON_SW3_GPIO_CLK_ENABLE();} while(0) + +#define BUTTONx_GPIO_CLK_DISABLE(__INDEX__) do { if ((__INDEX__) == BUTTON_SW1) BUTTON_SW1_GPIO_CLK_DISABLE(); else \ + if ((__INDEX__) == BUTTON_SW2) BUTTON_SW2_GPIO_CLK_DISABLE(); else \ + if ((__INDEX__) == BUTTON_SW3) BUTTON_SW3_GPIO_CLK_DISABLE();} while(0) + +/** + * @} + */ + +#if (USE_BSP_COM_FEATURE > 0) +/** @defgroup STM32WLXX_NUCLEO_LOW_LEVEL_COM LOW LEVEL COM Port Constants + * @{ + */ +#define COM1_UART LPUART1 +#define COM1_CLK_ENABLE() __HAL_RCC_LPUART1_CLK_ENABLE() +#define COM1_CLK_DISABLE() __HAL_RCC_LPUART1_CLK_DISABLE() + +#define COM1_TX_PIN GPIO_PIN_2 +#define COM1_TX_GPIO_PORT GPIOA +#define COM1_TX_GPIO_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE() +#define COM1_TX_GPIO_CLK_DISABLE() __HAL_RCC_GPIOA_CLK_DISABLE() +#define COM1_TX_AF GPIO_AF8_LPUART1 + +#define COM1_RX_PIN GPIO_PIN_3 +#define COM1_RX_GPIO_PORT GPIOA +#define COM1_RX_GPIO_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE() +#define COM1_RX_GPIO_CLK_DISABLE() __HAL_RCC_GPIOA_CLK_DISABLE() +#define COM1_RX_AF GPIO_AF8_LPUART1 +#define COM_POLL_TIMEOUT 1000 + +#define MX_UART_InitTypeDef COM_InitTypeDef +/** + * @} + */ +#endif /* (USE_BSP_COM_FEATURE > 0)*/ + +/** + * @} + */ + +/** @addtogroup STM32WLXX_NUCLEO_LOW_LEVEL_Exported_Variables + * @{ + */ +extern EXTI_HandleTypeDef hpb_exti[]; +#if (USE_BSP_COM_FEATURE > 0) +extern UART_HandleTypeDef hcom_uart[]; +#endif /* (USE_BSP_COM_FEATURE > 0) */ +/** + * @} + */ + +/** @defgroup STM32WLXX_NUCLEO_LOW_LEVEL_Exported_Functions LOW LEVEL Exported Functions + * @{ + */ +uint32_t BSP_GetVersion(void); + +/** @defgroup STM32WLXX_NUCLEO_LOW_LEVEL_LED_Functions LOW LEVEL LED Functions + * @{ + */ +int32_t BSP_LED_Init(Led_TypeDef Led); +int32_t BSP_LED_DeInit(Led_TypeDef Led); +int32_t BSP_LED_On(Led_TypeDef Led); +int32_t BSP_LED_Off(Led_TypeDef Led); +int32_t BSP_LED_Toggle(Led_TypeDef Led); +int32_t BSP_LED_GetState(Led_TypeDef Led); +/** + * @} + */ + +/** @defgroup STM32WLXX_NUCLEO_LOW_LEVEL_BUTTON_Functions LOW LEVEL BUTTON Functions + * @{ + */ +int32_t BSP_PB_Init(Button_TypeDef Button, ButtonMode_TypeDef ButtonMode); +int32_t BSP_PB_DeInit(Button_TypeDef Button); +int32_t BSP_PB_GetState(Button_TypeDef Button); +void BSP_PB_Callback(Button_TypeDef Button); +void BSP_PB_IRQHandler(Button_TypeDef Button); +/** + * @} + */ + +#if (USE_BSP_COM_FEATURE > 0) +/** @defgroup STM32WLXX_NUCLEO_LOW_LEVEL_COM_Functions LOW LEVEL COM Port Functions + * @{ + */ +int32_t BSP_COM_Init(COM_TypeDef COM, COM_InitTypeDef *COM_Init); +int32_t BSP_COM_DeInit(COM_TypeDef COM); +#if (USE_COM_LOG > 0) +int32_t BSP_COM_SelectLogPort (COM_TypeDef COM); +#endif +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +int32_t BSP_COM_RegisterDefaultMspCallbacks(COM_TypeDef COM); +int32_t BSP_COM_RegisterMspCallbacks(COM_TypeDef COM , BSP_COM_Cb_t *Callback); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +HAL_StatusTypeDef MX_LPUART1_Init(UART_HandleTypeDef *huart, MX_UART_InitTypeDef *COM_Init); +/** + * @} + */ +#endif /* (USE_BSP_COM_FEATURE > 0) */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32WLXX_NUCLEO_H */ diff --git a/Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo_conf_template.h b/Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo_conf_template.h new file mode 100644 index 0000000..c095e89 --- /dev/null +++ b/Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo_conf_template.h @@ -0,0 +1,74 @@ +/** + ****************************************************************************** + * @file stm32wlxx_nucleo_conf.h + * @author MCD Application Team + * @brief STM32WLxx_Nucleo board configuration file. + ****************************************************************************** + * @attention + * + * Copyright (c) 2020-2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32WLXX_NUCLEO_CONF_H +#define STM32WLXX_NUCLEO_CONF_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wlxx_hal.h" + +/** @addtogroup BSP + * @{ + */ + +/** @addtogroup STM32WLXX_NUCLEO + * @{ + */ + +/** @defgroup STM32WLXX_NUCLEO_CONFIG CONFIG + * @{ + */ + +/** @defgroup STM32WLXX_NUCLEO_CONFIG_Exported_Constants Exported Constants + * @{ + */ +/* COM usage define */ +#define USE_BSP_COM_FEATURE 0U + +/* COM log define */ +#define USE_COM_LOG 0U + +/* IRQ priorities */ +#define BSP_BUTTON_USER_IT_PRIORITY 15U + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32WLXX_NUCLEO_CONF_H */ diff --git a/Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo_errno.h b/Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo_errno.h new file mode 100644 index 0000000..e1d546f --- /dev/null +++ b/Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo_errno.h @@ -0,0 +1,45 @@ +/** + ****************************************************************************** + * @file stm32wlxx_nucleo_errno.h + * @author MCD Application Team + * @brief Error Code. + ****************************************************************************** + * @attention + * + * Copyright (c) 2020-2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32WLXX_NUCLEO_ERRNO_H +#define STM32WLXX_NUCLEO_ERRNO_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Common Error codes */ +#define BSP_ERROR_NONE 0 +#define BSP_ERROR_NO_INIT -1 +#define BSP_ERROR_WRONG_PARAM -2 +#define BSP_ERROR_BUSY -3 +#define BSP_ERROR_PERIPH_FAILURE -4 +#define BSP_ERROR_COMPONENT_FAILURE -5 +#define BSP_ERROR_UNKNOWN_FAILURE -6 +#define BSP_ERROR_UNKNOWN_COMPONENT -7 +#define BSP_ERROR_BUS_FAILURE -8 +#define BSP_ERROR_CLOCK_FAILURE -9 +#define BSP_ERROR_MSP_FAILURE -10 +#define BSP_ERROR_FEATURE_NOT_SUPPORTED -11 + +#ifdef __cplusplus +} +#endif + +#endif /* STM32WLXX_NUCLEO_ERRNO_H */ diff --git a/Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo_radio.c b/Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo_radio.c new file mode 100644 index 0000000..0c11ec6 --- /dev/null +++ b/Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo_radio.c @@ -0,0 +1,220 @@ +/** + ****************************************************************************** + * @file stm32wlxx_nucleo_radio.c + * @author MCD Application Team + * @brief This file provides set of firmware functions to manage: + * - RF circuitry available on STM32WLXX-Nucleo + * Kit from STMicroelectronics + ****************************************************************************** + * @attention + * + * Copyright (c) 2020-2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wlxx_nucleo_radio.h" + +/** @addtogroup BSP + * @{ + */ + +/** @addtogroup STM32WLXX_NUCLEO + * @{ + */ + +/** @addtogroup STM32WLXX_NUCLEO_RADIO_LOW_LEVEL + * @brief This file provides set of firmware functions to Radio switch + * available on STM32WLXX-Nucleo Kit from STMicroelectronics. + * @{ + */ + +/** @addtogroup STM32WLXX_NUCLEO_RADIO_LOW_LEVEL_Exported_Functions + * @{ + */ + +/** + * @brief Init Radio Switch + * @retval BSP status + */ +int32_t BSP_RADIO_Init(void) +{ + GPIO_InitTypeDef gpio_init_structure = {0}; + + /* Enable the Radio Switch Clock */ + RF_SW_CTRL3_GPIO_CLK_ENABLE(); + + /* Configure the Radio Switch pin */ + gpio_init_structure.Pin = RF_SW_CTRL1_PIN; + gpio_init_structure.Mode = GPIO_MODE_OUTPUT_PP; + gpio_init_structure.Pull = GPIO_NOPULL; + gpio_init_structure.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + + HAL_GPIO_Init(RF_SW_CTRL1_GPIO_PORT, &gpio_init_structure); + + gpio_init_structure.Pin = RF_SW_CTRL2_PIN; + HAL_GPIO_Init(RF_SW_CTRL2_GPIO_PORT, &gpio_init_structure); + + gpio_init_structure.Pin = RF_SW_CTRL3_PIN; + HAL_GPIO_Init(RF_SW_CTRL3_GPIO_PORT, &gpio_init_structure); + + HAL_GPIO_WritePin(RF_SW_CTRL2_GPIO_PORT, RF_SW_CTRL2_PIN, GPIO_PIN_RESET); + HAL_GPIO_WritePin(RF_SW_CTRL1_GPIO_PORT, RF_SW_CTRL1_PIN, GPIO_PIN_RESET); + HAL_GPIO_WritePin(RF_SW_CTRL3_GPIO_PORT, RF_SW_CTRL3_PIN, GPIO_PIN_RESET); + + return BSP_ERROR_NONE; +} + +/** + * @brief DeInit Radio Switch + * @retval BSP status + */ +int32_t BSP_RADIO_DeInit(void) +{ + RF_SW_CTRL3_GPIO_CLK_ENABLE(); + + /* Turn off switch */ + HAL_GPIO_WritePin(RF_SW_CTRL1_GPIO_PORT, RF_SW_CTRL1_PIN, GPIO_PIN_RESET); + HAL_GPIO_WritePin(RF_SW_CTRL2_GPIO_PORT, RF_SW_CTRL2_PIN, GPIO_PIN_RESET); + HAL_GPIO_WritePin(RF_SW_CTRL3_GPIO_PORT, RF_SW_CTRL3_PIN, GPIO_PIN_RESET); + + /* DeInit the Radio Switch pin */ + HAL_GPIO_DeInit(RF_SW_CTRL1_GPIO_PORT, RF_SW_CTRL1_PIN); + HAL_GPIO_DeInit(RF_SW_CTRL2_GPIO_PORT, RF_SW_CTRL2_PIN); + HAL_GPIO_DeInit(RF_SW_CTRL3_GPIO_PORT, RF_SW_CTRL3_PIN); + + return BSP_ERROR_NONE; +} + +/** + * @brief Configure Radio Switch. + * @param Config: Specifies the Radio RF switch path to be set. + * This parameter can be one of following parameters: + * @arg RADIO_SWITCH_OFF + * @arg RADIO_SWITCH_RX + * @arg RADIO_SWITCH_RFO_LP + * @arg RADIO_SWITCH_RFO_HP + * @retval BSP status + */ +int32_t BSP_RADIO_ConfigRFSwitch(BSP_RADIO_Switch_TypeDef Config) +{ + switch (Config) + { + case RADIO_SWITCH_OFF: + { + /* Turn off switch */ + HAL_GPIO_WritePin(RF_SW_CTRL3_GPIO_PORT, RF_SW_CTRL3_PIN, GPIO_PIN_RESET); + HAL_GPIO_WritePin(RF_SW_CTRL1_GPIO_PORT, RF_SW_CTRL1_PIN, GPIO_PIN_RESET); + HAL_GPIO_WritePin(RF_SW_CTRL2_GPIO_PORT, RF_SW_CTRL2_PIN, GPIO_PIN_RESET); + break; + } + case RADIO_SWITCH_RX: + { + /*Turns On in Rx Mode the RF Switch */ + HAL_GPIO_WritePin(RF_SW_CTRL3_GPIO_PORT, RF_SW_CTRL3_PIN, GPIO_PIN_SET); + HAL_GPIO_WritePin(RF_SW_CTRL1_GPIO_PORT, RF_SW_CTRL1_PIN, GPIO_PIN_SET); + HAL_GPIO_WritePin(RF_SW_CTRL2_GPIO_PORT, RF_SW_CTRL2_PIN, GPIO_PIN_RESET); + break; + } + case RADIO_SWITCH_RFO_LP: + { + /*Turns On in Tx Low Power the RF Switch */ + HAL_GPIO_WritePin(RF_SW_CTRL3_GPIO_PORT, RF_SW_CTRL3_PIN, GPIO_PIN_SET); + HAL_GPIO_WritePin(RF_SW_CTRL1_GPIO_PORT, RF_SW_CTRL1_PIN, GPIO_PIN_SET); + HAL_GPIO_WritePin(RF_SW_CTRL2_GPIO_PORT, RF_SW_CTRL2_PIN, GPIO_PIN_SET); + break; + } + case RADIO_SWITCH_RFO_HP: + { + /*Turns On in Tx High Power the RF Switch */ + HAL_GPIO_WritePin(RF_SW_CTRL3_GPIO_PORT, RF_SW_CTRL3_PIN, GPIO_PIN_SET); + HAL_GPIO_WritePin(RF_SW_CTRL1_GPIO_PORT, RF_SW_CTRL1_PIN, GPIO_PIN_RESET); + HAL_GPIO_WritePin(RF_SW_CTRL2_GPIO_PORT, RF_SW_CTRL2_PIN, GPIO_PIN_SET); + break; + } + default: + break; + } + + return BSP_ERROR_NONE; +} + +/** + * @brief Return Board Configuration + * @retval + * RADIO_CONF_RFO_LP_HP + * RADIO_CONF_RFO_LP + * RADIO_CONF_RFO_HP + */ +int32_t BSP_RADIO_GetTxConfig(void) +{ + return RADIO_CONF_RFO_LP_HP; +} + +/** + * @brief Get If TCXO is to be present on board + * @note never remove called by MW, + * @retval + * RADIO_CONF_TCXO_NOT_SUPPORTED + * RADIO_CONF_TCXO_SUPPORTED + */ +int32_t BSP_RADIO_IsTCXO(void) +{ + return RADIO_CONF_TCXO_SUPPORTED; +} + +/** + * @brief Get If DCDC is to be present on board + * @note never remove called by MW, + * @retval + * RADIO_CONF_DCDC_NOT_SUPPORTED + * RADIO_CONF_DCDC_SUPPORTED + */ +int32_t BSP_RADIO_IsDCDC(void) +{ + return RADIO_CONF_DCDC_SUPPORTED; +} + +/** + * @brief Return RF Output Max Power Configuration + * @retval + * RADIO_CONF_RFO_LP_MAX_15_dBm for LP mode + * RADIO_CONF_RFO_HP_MAX_22_dBm for HP mode + */ +int32_t BSP_RADIO_GetRFOMaxPowerConfig(BSP_RADIO_RFOMaxPowerConfig_TypeDef Config) +{ + int32_t ret; + + if(Config == RADIO_RFO_LP_MAXPOWER) + { + ret = RADIO_CONF_RFO_LP_MAX_15_dBm; + } + else + { + ret = RADIO_CONF_RFO_HP_MAX_22_dBm; + } + + return ret; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo_radio.h b/Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo_radio.h new file mode 100644 index 0000000..335da05 --- /dev/null +++ b/Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo_radio.h @@ -0,0 +1,157 @@ +/** + ****************************************************************************** + * @file stm32wlxx_nucleo_radio.h + * @author MCD Application Team + * @brief Header for stm32wlxx_nucleo_radio.c + ****************************************************************************** + * @attention + * + * Copyright (c) 2020-2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32WLXX_NUCLEO_RADIO_H +#define STM32WLXX_NUCLEO_RADIO_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wlxx_nucleo_errno.h" +#include "stm32wlxx_nucleo_conf.h" + + +/** @addtogroup BSP + * @{ + */ + +/** @addtogroup STM32WLXX_NUCLEO STM32WLXX-NUCLEO + * @{ + */ + +/** @defgroup STM32WLXX_NUCLEO_RADIO_LOW_LEVEL RADIO LOW LEVEL + * @{ + */ + +/** @defgroup STM32WLXX_NUCLEO_RADIO_LOW_LEVEL_Exported_Types RADIO LOW LEVEL Exported Types + * @{ + */ + +typedef enum +{ + RADIO_SWITCH_OFF = 0, + RADIO_SWITCH_RX = 1, + RADIO_SWITCH_RFO_LP = 2, + RADIO_SWITCH_RFO_HP = 3, +}BSP_RADIO_Switch_TypeDef; + +typedef enum +{ + RADIO_RFO_LP_MAXPOWER = 0, + RADIO_RFO_HP_MAXPOWER, +} BSP_RADIO_RFOMaxPowerConfig_TypeDef; + +/** + * @} + */ + +/** @defgroup STM32WLXX_NUCLEO_RADIO_LOW_LEVEL_Exported_Constants RADIO LOW LEVEL Exported Constants + * @{ + */ + +/** @defgroup STM32WLXX_NUCLEO_RADIO_LOW_LEVEL_RADIOCONFIG RADIO LOW LEVEL RADIO CONFIG Constants + * @{ + */ +#define RADIO_CONF_RFO_LP_HP 0U +#define RADIO_CONF_RFO_LP 1U +#define RADIO_CONF_RFO_HP 2U + +#define RADIO_CONF_TCXO_NOT_SUPPORTED 0U +#define RADIO_CONF_TCXO_SUPPORTED 1U + +#define RADIO_CONF_DCDC_NOT_SUPPORTED 0U +#define RADIO_CONF_DCDC_SUPPORTED 1U + +#define RADIO_CONF_RFO_HP_MAX_22_dBm ((int32_t) 22) +#define RADIO_CONF_RFO_HP_MAX_20_dBm ((int32_t) 20) +#define RADIO_CONF_RFO_HP_MAX_17_dBm ((int32_t) 17) +#define RADIO_CONF_RFO_HP_MAX_14_dBm ((int32_t) 14) +#define RADIO_CONF_RFO_LP_MAX_15_dBm ((int32_t) 15) +#define RADIO_CONF_RFO_LP_MAX_14_dBm ((int32_t) 14) +#define RADIO_CONF_RFO_LP_MAX_10_dBm ((int32_t) 10) + +/** + * @} + */ + +/** @defgroup STM32WLXX_NUCLEO_RADIO_LOW_LEVEL_RFSWITCH RADIO LOW LEVEL RF SWITCH Constants + * @{ + */ + +#define RF_SW_CTRL3_PIN GPIO_PIN_3 +#define RF_SW_CTRL3_GPIO_PORT GPIOC +#define RF_SW_CTRL3_GPIO_CLK_ENABLE() __HAL_RCC_GPIOC_CLK_ENABLE() +#define RF_SW_CTRL3_GPIO_CLK_DISABLE() __HAL_RCC_GPIOC_CLK_DISABLE() + +#define RF_SW_CTRL1_PIN GPIO_PIN_4 +#define RF_SW_CTRL1_GPIO_PORT GPIOC +#define RF_SW_CTRL1_GPIO_CLK_ENABLE() __HAL_RCC_GPIOC_CLK_ENABLE() +#define RF_SW_RX_GPIO_CLK_DISABLE() __HAL_RCC_GPIOC_CLK_DISABLE() + +#define RF_SW_CTRL2_PIN GPIO_PIN_5 +#define RF_SW_CTRL2_GPIO_PORT GPIOC +#define RF_SW_CTRL2_GPIO_CLK_ENABLE() __HAL_RCC_GPIOC_CLK_ENABLE() +#define RF_SW_CTRL2_GPIO_CLK_DISABLE() __HAL_RCC_GPIOC_CLK_DISABLE() + +#define RF_TCXO_VCC_PIN GPIO_PIN_0 +#define RF_TCXO_VCC_GPIO_PORT GPIOB +#define RF_TCXO_VCC_CLK_ENABLE() __HAL_RCC_GPIOB_CLK_ENABLE() +#define RF_TCXO_VCC_CLK_DISABLE() __HAL_RCC_GPIOB_CLK_DISABLE() +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup STM32WLXX_NUCLEO_RADIO_LOW_LEVEL_Exported_Functions RADIO LOW LEVEL Exported Functions + * @{ + */ +int32_t BSP_RADIO_Init(void); +int32_t BSP_RADIO_DeInit(void); +int32_t BSP_RADIO_ConfigRFSwitch(BSP_RADIO_Switch_TypeDef Config); +int32_t BSP_RADIO_GetTxConfig(void); +int32_t BSP_RADIO_IsTCXO(void); +int32_t BSP_RADIO_IsDCDC(void); +int32_t BSP_RADIO_GetRFOMaxPowerConfig(BSP_RADIO_RFOMaxPowerConfig_TypeDef Config); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32WLXX_NUCLEO_RADIO_H */ diff --git a/Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wl55xx.h b/Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wl55xx.h new file mode 100644 index 0000000..9217358 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wl55xx.h @@ -0,0 +1,11558 @@ +/** + ****************************************************************************** + * @file stm32wl55xx.h + * @author MCD Application Team + * @brief CMSIS Cortex Device Peripheral Access Layer Header File. + * This file contains all the peripheral register's definitions, bits + * definitions and memory mapping for stm32wl55xx devices. + * + * This file contains:selected + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripheral's registers hardware + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2020-2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS_Device + * @{ + */ + +/** @addtogroup stm32wl55xx + * @{ + */ + +#ifndef __STM32WL55xx_H +#define __STM32WL55xx_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +#define DUAL_CORE + + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief stm32wl55xx Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ +#if defined(CORE_CM0PLUS) + /*!< Interrupt Number Definition for M0 */ + typedef enum + { + /****** Cortex-M0 Processor Exceptions Numbers ****************************************************************/ + NonMaskableInt_IRQn = -14, /*!< Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< Cortex-M0+ Hard Fault Interrupt */ + SVCall_IRQn = -5, /*!< Cortex-M0+ SV Call Interrupt */ + PendSV_IRQn = -2, /*!< Cortex-M0+ Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< Cortex-M0+ System Tick Interrupt */ + + /************* STM32WLxx specific Interrupt Numbers on M0 core ************************************************/ + TZIC_ILA_IRQn = 0, /*!< Security Interrupt controller illegal access interrupt */ + PVD_PVM_IRQn = 1, /*!< PVD and PVM detector */ + RTC_LSECSS_IRQn = 2, /*!< RTC Wakeup + RTC Tamper and RTC TimeStamp + RTC Alarms (A & B) and*/ + /*!< RTC SSRU Interrupts and LSECSS Interrupts */ + RCC_FLASH_C1SEV_IRQn = 3, /*!< RCC Interrupt, FLASH interrupt and CPU1 SEV */ + EXTI1_0_IRQn = 4, /*!< EXTI Line 1:0 Interrupt */ + EXTI3_2_IRQn = 5, /*!< EXTI Line 3:2 Interrupt */ + EXTI15_4_IRQn = 6, /*!< EXTI Line 15:4 interrupt */ + ADC_COMP_DAC_IRQn = 7, /*!< ADC, COMP1, COMP2, DAC interrupts */ + DMA1_Channel1_2_3_IRQn = 8, /*!< DMA1 Channels 1,2,3 Interrupt */ + DMA1_Channel4_5_6_7_IRQn = 9, /*!< DMA1 Channels 4,5,6,7 Interrupt */ + DMA2_DMAMUX1_OVR_IRQn = 10, /*!< DMA2 Channels[1..7] and DMAMUX1 Overrun Interrupt */ + LPTIM1_IRQn = 11, /*!< LPTIM1 Global Interrupt */ + LPTIM2_IRQn = 12, /*!< LPTIM2 Global Interrupt */ + LPTIM3_IRQn = 13, /*!< LPTIM3 Global Interrupt */ + TIM1_IRQn = 14, /*!< TIM1 Global Interrupt */ + TIM2_IRQn = 15, /*!< TIM2 Global Interrupt */ + TIM16_IRQn = 16, /*!< TIM16 Global Interrupt */ + TIM17_IRQn = 17, /*!< TIM17 Global Interrupt */ + IPCC_C2_RX_C2_TX_IRQn = 18, /*!< IPCC RX Occupied and TX Free Interrupt */ + HSEM_IRQn = 19, /*!< HSEM Interrupt */ + RNG_IRQn = 20, /*!< RNG Interrupt */ + AES_PKA_IRQn = 21, /*!< AES and PKA Interrupt */ + I2C1_IRQn = 22, /*!< I2C1 Event and Error Interrupt */ + I2C2_IRQn = 23, /*!< I2C2 Event and Error Interrupt */ + I2C3_IRQn = 24, /*!< I2C3 Event and Error Interrupt */ + SPI1_IRQn = 25, /*!< SPI1 Interrupt */ + SPI2_IRQn = 26, /*!< SPI2 Interrupt */ + USART1_IRQn = 27, /*!< USART1 Interrupt */ + USART2_IRQn = 28, /*!< USART2 Interrupt */ + LPUART1_IRQn = 29, /*!< LPUART1 Interrupt */ + SUBGHZSPI_IRQn = 30, /*!< SUBGHZSPI Interrupt */ + SUBGHZ_Radio_IRQn = 31, /*!< SUBGHZ Radio Interrupt */ + } IRQn_Type; +#else /* CORE_CM4 */ +/*!< Interrupt Number Definition for M4 */ +typedef enum +{ +/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/ + NonMaskableInt_IRQn = -14, /*!< Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< Cortex-M4 System Tick Interrupt */ + +/************* STM32WLxx specific Interrupt Numbers on M4 core ************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_PVM_IRQn = 1, /*!< PVD and PVM detector */ + TAMP_STAMP_LSECSS_SSRU_IRQn = 2, /*!< RTC Tamper, RTC TimeStamp, LSECSS and RTC SSRU Interrupts */ + RTC_WKUP_IRQn = 3, /*!< RTC Wakeup Interrupt */ + FLASH_IRQn = 4, /*!< FLASH (CFI) global Interrupt */ + RCC_IRQn = 5, /*!< RCC Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line 0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line 1 Interrupt */ + EXTI2_IRQn = 8, /*!< EXTI Line 2 Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line 3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line 4 Interrupt */ + DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 Interrupt */ + DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 Interrupt */ + DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 Interrupt */ + DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 Interrupt */ + DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 Interrupt */ + DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 Interrupt */ + DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 Interrupt */ + ADC_IRQn = 18, /*!< ADC Interrupt */ + DAC_IRQn = 19, /*!< DAC Interrupt */ + C2SEV_PWR_C2H_IRQn = 20, /*!< CPU2 SEV Interrupt */ + COMP_IRQn = 21, /*!< COMP1 and COMP2 Interrupts */ + EXTI9_5_IRQn = 22, /*!< EXTI Lines [9:5] Interrupt */ + TIM1_BRK_IRQn = 23, /*!< TIM1 Break Interrupt */ + TIM1_UP_IRQn = 24, /*!< TIM1 Update Interrupt */ + TIM1_TRG_COM_IRQn = 25, /*!< TIM1 Trigger and Communication Interrupts */ + TIM1_CC_IRQn = 26, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 27, /*!< TIM2 Global Interrupt */ + TIM16_IRQn = 28, /*!< TIM16 Global Interrupt */ + TIM17_IRQn = 29, /*!< TIM17 Global Interrupt */ + I2C1_EV_IRQn = 30, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 31, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 32, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 33, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 34, /*!< SPI1 Interrupt */ + SPI2_IRQn = 35, /*!< SPI2 Interrupt */ + USART1_IRQn = 36, /*!< USART1 Interrupt */ + USART2_IRQn = 37, /*!< USART2 Interrupt */ + LPUART1_IRQn = 38, /*!< LPUART1 Interrupt */ + LPTIM1_IRQn = 39, /*!< LPTIM1 Global Interrupt */ + LPTIM2_IRQn = 40, /*!< LPTIM2 Global Interrupt */ + EXTI15_10_IRQn = 41, /*!< EXTI Lines [15:10] Interrupt */ + RTC_Alarm_IRQn = 42, /*!< RTC Alarms (A and B) Interrupt */ + LPTIM3_IRQn = 43, /*!< LPTIM3 Global Interrupt */ + SUBGHZSPI_IRQn = 44, /*!< SUBGHZSPI Interrupt */ + IPCC_C1_RX_IRQn = 45, /*!< IPCC RX Occupied Interrupt */ + IPCC_C1_TX_IRQn = 46, /*!< IPCC TX Free Interrupt */ + HSEM_IRQn = 47, /*!< HSEM Interrupt */ + I2C3_EV_IRQn = 48, /*!< I2C3 Event Interrupt */ + I2C3_ER_IRQn = 49, /*!< I2C3 Error Interrupt */ + SUBGHZ_Radio_IRQn = 50, /*!< SUBGHZ Radio Interrupt */ + AES_IRQn = 51, /*!< AES Interrupt */ + RNG_IRQn = 52, /*!< RNG Interrupt */ + PKA_IRQn = 53, /*!< PKA Interrupt */ + DMA2_Channel1_IRQn = 54, /*!< DMA2 Channel 1 Interrupt */ + DMA2_Channel2_IRQn = 55, /*!< DMA2 Channel 2 Interrupt */ + DMA2_Channel3_IRQn = 56, /*!< DMA2 Channel 3 Interrupt */ + DMA2_Channel4_IRQn = 57, /*!< DMA2 Channel 4 Interrupt */ + DMA2_Channel5_IRQn = 58, /*!< DMA2 Channel 5 Interrupt */ + DMA2_Channel6_IRQn = 59, /*!< DMA2 Channel 6 Interrupt */ + DMA2_Channel7_IRQn = 60, /*!< DMA2 Channel 7 Interrupt */ + DMAMUX1_OVR_IRQn = 61 /*!< DMAMUX1 overrun Interrupt */ +} IRQn_Type; +/** + * @} + */ +#endif + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ +#if defined(CORE_CM0PLUS) +/** + * @brief Configuration of the Cortex-M0+ Processor and Core Peripherals + */ +#define __CM0PLUS_REV 1U /*!< Core Revision r0p1 */ +#define __MPU_PRESENT 1U /*!< M0 provides an MPU */ +#define __VTOR_PRESENT 1U /*!< Vector Table Register supported */ +#define __NVIC_PRIO_BITS 2U /*!< M0 core uses 2 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 0U /*!< FPU not present */ + +#include "core_cm0plus.h" /* Cortex-M0+ processor and core peripherals */ + +#else /* CORE_CM4 */ +/** + * @brief Configuration of the Cortex-M4 Processor and Core Peripherals + */ +#define __CM4_REV 1U /*!< Core Revision r0p1 */ +#define __MPU_PRESENT 1U /*!< M4 provides an MPU */ +#define __VTOR_PRESENT 1U /*!< Vector Table Register supported */ +#define __NVIC_PRIO_BITS 4U /*!< STM32WLxx uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 0U /*!< FPU not present */ + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ + +#endif + +#include "system_stm32wlxx.h" +#include + +/** + * @} + */ + + + + + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ +typedef struct +{ + __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR1; /*!< ADC configuration register 1, Address offset: 0x0C */ + __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */ + __IO uint32_t SMPR; /*!< ADC sampling time register, Address offset: 0x14 */ + uint32_t RESERVED1; /*!< Reserved, 0x18 */ + uint32_t RESERVED2; /*!< Reserved, 0x1C */ + __IO uint32_t AWD1TR; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */ + __IO uint32_t AWD2TR; /*!< ADC analog watchdog 2 threshold register, Address offset: 0x24 */ + __IO uint32_t CHSELR; /*!< ADC group regular sequencer register, Address offset: 0x28 */ + __IO uint32_t AWD3TR; /*!< ADC analog watchdog 3 threshold register, Address offset: 0x2C */ + uint32_t RESERVED3[4]; /*!< Reserved, 0x30 - 0x3C */ + __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */ + uint32_t RESERVED4[23];/*!< Reserved, 0x44 - 0x9C */ + __IO uint32_t AWD2CR; /*!< ADC analog watchdog 2 configuration register, Address offset: 0xA0 */ + __IO uint32_t AWD3CR; /*!< ADC analog watchdog 3 configuration register, Address offset: 0xA4 */ + uint32_t RESERVED5[3]; /*!< Reserved, 0xA8 - 0xB0 */ + __IO uint32_t CALFACT; /*!< ADC Calibration factor register, Address offset: 0xB4 */ +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: ADC base address + 0x308 */ +} ADC_Common_TypeDef; + +/* Legacy registers naming */ +#define TR1 AWD1TR +#define TR2 AWD2TR +#define TR3 AWD3TR + +/** + * @brief AES hardware accelerator + */ +typedef struct +{ + __IO uint32_t CR; /*!< AES control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< AES status register, Address offset: 0x04 */ + __IO uint32_t DINR; /*!< AES data input register, Address offset: 0x08 */ + __IO uint32_t DOUTR; /*!< AES data output register, Address offset: 0x0C */ + __IO uint32_t KEYR0; /*!< AES key register 0, Address offset: 0x10 */ + __IO uint32_t KEYR1; /*!< AES key register 1, Address offset: 0x14 */ + __IO uint32_t KEYR2; /*!< AES key register 2, Address offset: 0x18 */ + __IO uint32_t KEYR3; /*!< AES key register 3, Address offset: 0x1C */ + __IO uint32_t IVR0; /*!< AES initialization vector register 0, Address offset: 0x20 */ + __IO uint32_t IVR1; /*!< AES initialization vector register 1, Address offset: 0x24 */ + __IO uint32_t IVR2; /*!< AES initialization vector register 2, Address offset: 0x28 */ + __IO uint32_t IVR3; /*!< AES initialization vector register 3, Address offset: 0x2C */ + __IO uint32_t KEYR4; /*!< AES key register 4, Address offset: 0x30 */ + __IO uint32_t KEYR5; /*!< AES key register 5, Address offset: 0x34 */ + __IO uint32_t KEYR6; /*!< AES key register 6, Address offset: 0x38 */ + __IO uint32_t KEYR7; /*!< AES key register 7, Address offset: 0x3C */ + __IO uint32_t SUSP0R; /*!< AES Suspend register 0, Address offset: 0x40 */ + __IO uint32_t SUSP1R; /*!< AES Suspend register 1, Address offset: 0x44 */ + __IO uint32_t SUSP2R; /*!< AES Suspend register 2, Address offset: 0x48 */ + __IO uint32_t SUSP3R; /*!< AES Suspend register 3, Address offset: 0x4C */ + __IO uint32_t SUSP4R; /*!< AES Suspend register 4, Address offset: 0x50 */ + __IO uint32_t SUSP5R; /*!< AES Suspend register 5, Address offset: 0x54 */ + __IO uint32_t SUSP6R; /*!< AES Suspend register 6, Address offset: 0x58 */ + __IO uint32_t SUSP7R; /*!< AES Suspend register 7, Address offset: 0x6C */ +} AES_TypeDef; + +/** + * @brief Comparator + */ +typedef struct +{ + __IO uint32_t CSR; /*!< COMP control and status register, Address offset: 0x00 */ +} COMP_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */ +} COMP_Common_TypeDef; + +/** + * @brief CRC calculation unit + */ +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED2; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + +/** + * @brief Digital to Analog Converter + */ +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + uint32_t RESERVED1; /*!< Reserved Address offset: 0x14 */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x18 */ + uint32_t RESERVED3; /*!< Reserved Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + uint32_t RESERVED4; /*!< Reserved Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ + __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */ + __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */ + __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */ + uint32_t RESERVED5; /*!< Reserved Address offset: 0x44 */ + __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */ + __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */ +} DAC_TypeDef; + +#if defined(CORE_CM0PLUS) +#else +/** + * @brief Debug MCU + */ +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + uint32_t RESERVED1[13]; /*!< Reserved, 0x08-0x38 */ + __IO uint32_t APB1FZR1; /*!< Debug MCU CPU1 APB1 freeze register, Address offset: 0x3C */ + __IO uint32_t C2APB1FZR1; /*!< Debug MCU CPU2 APB1 freeze register, Address offset: 0x40 */ + __IO uint32_t APB1FZR2; /*!< Debug MCU CPU1 APB1 freeze register, Address offset: 0x44 */ + __IO uint32_t C2APB1FZR2; /*!< Debug MCU CPU2 APB1 freeze register, Address offset: 0x48 */ + __IO uint32_t APB2FZR; /*!< Debug MCU CPU1 APB2 freeze register, Address offset: 0x4C */ + __IO uint32_t C2APB2FZR; /*!< Debug MCU CPU2 APB2 freeze register, Address offset: 0x50 */ +} DBGMCU_TypeDef; +#endif + +/** + * @brief DMA Controller + */ +typedef struct +{ + __IO uint32_t CCR; /*!< DMA channel x configuration register */ + __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ + __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ + __IO uint32_t CMAR; /*!< DMA channel x memory address register */ +} DMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ + __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ +} DMA_TypeDef; + +/** + * @brief DMA Multiplexer + */ +typedef struct +{ + __IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register Address offset: 0x0004 * (channel x) */ +}DMAMUX_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< DMA Channel Status Register Address offset: 0x0080 */ + __IO uint32_t CFR; /*!< DMA Channel Clear Flag Register Address offset: 0x0084 */ +}DMAMUX_ChannelStatus_TypeDef; + +typedef struct +{ + __IO uint32_t RGCR; /*!< DMA Request Generator x Control Register Address offset: 0x0100 + 0x0004 * (Req Gen x) */ +}DMAMUX_RequestGen_TypeDef; + +typedef struct +{ + __IO uint32_t RGSR; /*!< DMA Request Generator Status Register Address offset: 0x0140 */ + __IO uint32_t RGCFR; /*!< DMA Request Generator Clear Flag Register Address offset: 0x0144 */ +}DMAMUX_RequestGenStatus_TypeDef; + +/** + * @brief Async Interrupts and Events Controller + */ +typedef struct +{ + __IO uint32_t RTSR1; /*!< EXTI rising trigger selection register [31:0], Address offset: 0x00 */ + __IO uint32_t FTSR1; /*!< EXTI falling trigger selection register [31:0], Address offset: 0x04 */ + __IO uint32_t SWIER1; /*!< EXTI software interrupt event register [31:0], Address offset: 0x08 */ + __IO uint32_t PR1; /*!< EXTI pending register [31:0], Address offset: 0x0C */ + __IO uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x10 - 0x1C */ + __IO uint32_t RTSR2; /*!< EXTI rising trigger selection register [31:0], Address offset: 0x20 */ + __IO uint32_t FTSR2; /*!< EXTI falling trigger selection register [31:0], Address offset: 0x24 */ + __IO uint32_t SWIER2; /*!< EXTI software interrupt event register [31:0], Address offset: 0x28 */ + __IO uint32_t PR2; /*!< EXTI pending register [31:0], Address offset: 0x2C */ + __IO uint32_t RESERVED2[4]; /*!< Reserved, Address offset: 0x30 - 0x3C */ + __IO uint32_t RESERVED3[8]; /*!< Reserved, Address offset: 0x40 - 0x5C */ + __IO uint32_t RESERVED4[8]; /*!< Reserved, Address offset: 0x60 - 0x7C */ + __IO uint32_t IMR1; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x80 */ + __IO uint32_t EMR1; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x84 */ + __IO uint32_t RESERVED5[2]; /*!< Reserved, Address offset: 0x88 - 0x8C */ + __IO uint32_t IMR2; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x90 */ + __IO uint32_t EMR2; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x94 */ + __IO uint32_t RESERVED8[10]; /*!< Reserved, Address offset: 0x98 - 0xBC */ + __IO uint32_t C2IMR1; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xC0 */ + __IO uint32_t C2EMR1; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xC4 */ + __IO uint32_t RESERVED9[2]; /*!< Reserved, Address offset: 0xC8 - 0xCC */ + __IO uint32_t C2IMR2; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xD0 */ + __IO uint32_t C2EMR2; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xD4 */ +}EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH Access control register, Address offset: 0x00 */ + __IO uint32_t ACR2; /*!< FLASH Access control register 2, Address offset: 0x04 */ + __IO uint32_t KEYR; /*!< FLASH Key register, Address offset: 0x08 */ + __IO uint32_t OPTKEYR; /*!< FLASH Option Key register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< FLASH Status register, Address offset: 0x10 */ + __IO uint32_t CR; /*!< FLASH Control register, Address offset: 0x14 */ + __IO uint32_t ECCR; /*!< FLASH ECC register, Address offset: 0x18 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */ + __IO uint32_t OPTR; /*!< FLASH Option register, Address offset: 0x20 */ + __IO uint32_t PCROP1ASR; /*!< FLASH Bank 1 PCROP area A Start address register, Address offset: 0x24 */ + __IO uint32_t PCROP1AER; /*!< FLASH Bank 1 PCROP area A End address register, Address offset: 0x28 */ + __IO uint32_t WRP1AR; /*!< FLASH Bank 1 WRP area A address register, Address offset: 0x2C */ + __IO uint32_t WRP1BR; /*!< FLASH Bank 1 WRP area B address register, Address offset: 0x30 */ + __IO uint32_t PCROP1BSR; /*!< FLASH Bank 1 PCROP area B Start address register, Address offset: 0x34 */ + __IO uint32_t PCROP1BER; /*!< FLASH Bank 1 PCROP area B End address register, Address offset: 0x38 */ + __IO uint32_t IPCCBR; /*!< FLASH IPCC data buffer address, Address offset: 0x3C */ + uint32_t RESERVED2[7]; /*!< Reserved, Address offset: 0x40-0x58 */ + __IO uint32_t C2ACR; /*!< FLASH Core MO+ Access Control Register , Address offset: 0x5C */ + __IO uint32_t C2SR; /*!< FLASH Core MO+ Status Register, Address offset: 0x60 */ + __IO uint32_t C2CR; /*!< FLASH Core MO+ Control register, Address offset: 0x64 */ + uint32_t RESERVED3[6]; /*!< Reserved, Address offset: 0x68-0x7C */ + __IO uint32_t SFR; /*!< FLASH secure start address, Address offset: 0x80 */ + __IO uint32_t SRRVR; /*!< FlASH secure SRAM2 start addr and CPU2 reset vector Address offset: 0x84 */ +} FLASH_TypeDef; + +/** + * @brief General Purpose I/O + */ +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ + __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ +} GPIO_TypeDef; + +/** + * @brief Global Security Controller + */ +typedef struct{ + __IO uint32_t CR; /*!< TZSC control register, Address offset: 0x00 */ + uint32_t RESERVED1[3]; /*!< Reserved1, Address offset: 0x04-0x0C */ + __IO uint32_t SECCFGR1; /*!< TZSC secure configuration register 1, Address offset: 0x10 */ + uint32_t RESERVED2[3]; /*!< Reserved2, Address offset: 0x14-0x1C */ + __IO uint32_t PRIVCFGR1; /*!< TZSC privilege configuration register 1, Address offset: 0x20 */ + uint32_t RESERVED3[67]; /*!< Reserved3, Address offset: 0x24-0x12C */ + __IO uint32_t MPCWM1_UPWMR; /*!< TZSC Unprivileged Water Mark 1 register, Address offset: 0x130 */ + __IO uint32_t MPCWM1_UPWWMR; /*!< TZSC Unprivileged Writable Water Mark 1 register, Address offset: 0x134 */ + __IO uint32_t MPCWM2_UPWMR; /*!< TZSC Unprivileged Water Mark 2 register, Address offset: 0x138 */ + uint32_t RESERVED4; /*!< Reserved4, Address offset: 0x13C */ + __IO uint32_t MPCWM3_UPWMR; /*!< TZSC Unprivileged Water Mark 2 register, Address offset: 0x140 */ +} GTZC_TZSC_TypeDef; + +typedef struct{ + __IO uint32_t IER1; /*!< TZIC interrupt enable register 1, Address offset: 0x00 */ + uint32_t RESERVED1[3]; /*!< Reserved1, Address offset: 0x0C */ + __IO uint32_t MISR1; /*!< TZIC interrupt status register 1, Address offset: 0x10 */ + uint32_t RESERVED2[3]; /*!< Reserved2, Address offset: 0x1C */ + __IO uint32_t ICR1; /*!< TZIC interrupt clear register 1, Address offset: 0x20 */ +} GTZC_TZIC_TypeDef; + +/** + * @brief HW Semaphore HSEM + */ +typedef struct +{ + __IO uint32_t R[16]; /*!< HSEM 2-step write lock and read back registers, Address offset: 00h-3Ch */ + uint32_t Reserved1[16]; /*!< Reserved Address offset: 40h-7Ch */ + __IO uint32_t RLR[16]; /*!< HSEM 1-step read lock registers, Address offset: 80h-BCh */ + uint32_t Reserved2[16]; /*!< Reserved Address offset: C0h-FCh */ + __IO uint32_t C1IER; /*!< HSEM CPU1 interrupt enable register , Address offset: 100h */ + __IO uint32_t C1ICR; /*!< HSEM CPU1 interrupt clear register , Address offset: 104h */ + __IO uint32_t C1ISR; /*!< HSEM CPU1 interrupt status register , Address offset: 108h */ + __IO uint32_t C1MISR; /*!< HSEM CPU1 masked interrupt status register , Address offset: 10Ch */ + __IO uint32_t C2IER; /*!< HSEM CPU2 interrupt enable register , Address offset: 110h */ + __IO uint32_t C2ICR; /*!< HSEM CPU2 interrupt clear register , Address offset: 114h */ + __IO uint32_t C2ISR; /*!< HSEM CPU2 interrupt status register , Address offset: 118h */ + __IO uint32_t C2MISR; /*!< HSEM CPU2 masked interrupt status register , Address offset: 11Ch */ + uint32_t Reserved[8]; /*!< Reserved Address offset: 120h-13Ch*/ + __IO uint32_t CR; /*!< HSEM Semaphore clear register , Address offset: 140h */ + __IO uint32_t KEYR; /*!< HSEM Semaphore clear key register , Address offset: 144h */ +} HSEM_TypeDef; + +typedef struct +{ + __IO uint32_t IER; /*!< HSEM interrupt enable register , Address offset: 0h */ + __IO uint32_t ICR; /*!< HSEM interrupt clear register , Address offset: 4h */ + __IO uint32_t ISR; /*!< HSEM interrupt status register , Address offset: 8h */ + __IO uint32_t MISR; /*!< HSEM masked interrupt status register , Address offset: Ch */ +} HSEM_Common_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ +} I2C_TypeDef; + +/** + * @brief Inter-Processor Communication + */ +typedef struct +{ + __IO uint32_t C1CR; /*!< Inter-Processor Communication: C1 control register, Address offset: 0x000 */ + __IO uint32_t C1MR ; /*!< Inter-Processor Communication: C1 mask register, Address offset: 0x004 */ + __IO uint32_t C1SCR; /*!< Inter-Processor Communication: C1 status set clear register, Address offset: 0x008 */ + __IO uint32_t C1TOC2SR; /*!< Inter-Processor Communication: C1 to processor M4 status register, Address offset: 0x00C */ + __IO uint32_t C2CR; /*!< Inter-Processor Communication: C2 control register, Address offset: 0x010 */ + __IO uint32_t C2MR ; /*!< Inter-Processor Communication: C2 mask register, Address offset: 0x014 */ + __IO uint32_t C2SCR; /*!< Inter-Processor Communication: C2 status set clear register, Address offset: 0x018 */ + __IO uint32_t C2TOC1SR; /*!< Inter-Processor Communication: C2 to processor M4 status register, Address offset: 0x01C */ +} IPCC_TypeDef; + +typedef struct +{ + __IO uint32_t CR; /*!< Control register, Address offset: 0x000 */ + __IO uint32_t MR; /*!< Mask register, Address offset: 0x004 */ + __IO uint32_t SCR; /*!< Status set clear register, Address offset: 0x008 */ + __IO uint32_t SR; /*!< Status register, Address offset: 0x00C */ +} IPCC_CommonTypeDef; + +/** + * @brief Independent WATCHDOG + */ +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ + __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ +} IWDG_TypeDef; + +/** + * @brief LPTIMER + */ +typedef struct +{ + __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ + __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ + __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */ + __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ + __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ + __IO uint32_t OR; /*!< LPTIM Option register, Address offset: 0x20 */ + __IO uint32_t RESERVED; /*!< Reserved, Address offset: 0x24 */ + __IO uint32_t RCR; /*!< LPTIM repetition register, Address offset: 0x28 */ +} LPTIM_TypeDef; + +/** + * @brief Public Key Accelerator (PKA) + */ +typedef struct +{ + __IO uint32_t CR; /*!< PKA control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< PKA status register, Address offset: 0x04 */ + __IO uint32_t CLRFR; /*!< PKA clear flag register, Address offset: 0x08 */ + uint32_t Reserved1[253]; /*!< Reserved Address offset: 0x000C-0x03FC*/ + __IO uint32_t RAM[894]; /*!< PKA RAM, Address offset: 0x0400-0x11F4 */ +} PKA_TypeDef; + +/** + * @brief Power Control + */ +typedef struct +{ + __IO uint32_t CR1; /*!< PWR Power Control Register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< PWR Power Control Register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< PWR Power Control Register 3, Address offset: 0x08 */ + __IO uint32_t CR4; /*!< PWR Power Control Register 4, Address offset: 0x0C */ + __IO uint32_t SR1; /*!< PWR Power Status Register 1, Address offset: 0x10 */ + __IO uint32_t SR2; /*!< PWR Power Status Register 2, Address offset: 0x14 */ + __IO uint32_t SCR; /*!< PWR Power Status Reset Register, Address offset: 0x18 */ + __IO uint32_t CR5; /*!< PWR Power Control Register 5, Address offset: 0x1C */ + __IO uint32_t PUCRA; /*!< PWR Pull-Up Control Register of port A, Address offset: 0x20 */ + __IO uint32_t PDCRA; /*!< PWR Pull-Down Control Register of port A, Address offset: 0x24 */ + __IO uint32_t PUCRB; /*!< PWR Pull-Up Control Register of port B, Address offset: 0x28 */ + __IO uint32_t PDCRB; /*!< PWR Pull-Down Control Register of port B, Address offset: 0x2C */ + __IO uint32_t PUCRC; /*!< PWR Pull-Up Control Register of port C, Address offset: 0x30 */ + __IO uint32_t PDCRC; /*!< PWR Pull-Down Control Register of port C, Address offset: 0x34 */ + uint32_t RESERVED0[8]; /*!< Reserved, Address offset: 0x38-0x54 */ + __IO uint32_t PUCRH; /*!< PWR Pull-Up Control Register of port H, Address offset: 0x58 */ + __IO uint32_t PDCRH; /*!< PWR Pull-Down Control Register of port H, Address offset: 0x5C */ + uint32_t RESERVED1[8]; /*!< Reserved, Address offset: 0x60-0x7C */ + __IO uint32_t C2CR1; /*!< PWR Power Control Register 1 for CPU2, Address offset: 0x80 */ + __IO uint32_t C2CR3; /*!< PWR Power Control Register 3 for CPU2, Address offset: 0x84 */ + __IO uint32_t EXTSCR; /*!< PWR Power Status Reset Register for CPU2, Address offset: 0x88 */ + __IO uint32_t SECCFGR; /*!< PWR Security Configuration Register, Address offset: 0x8C */ + __IO uint32_t SUBGHZSPICR; /*!< PWR SUBGHZSPI Control Register, Address offset: 0x90 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x94 */ + __IO uint32_t RSSCMDR; /*!< PWR RSS Command Register, Address offset: 0x98 */ +} PWR_TypeDef; + +/** + * @brief Reset and Clock Control + */ +typedef struct +{ + __IO uint32_t CR; /*!< RCC clock Control Register, Address offset: 0x00 */ + __IO uint32_t ICSCR; /*!< RCC Internal Clock Sources Calibration Register, Address offset: 0x04 */ + __IO uint32_t CFGR; /*!< RCC Clocks Configuration Register, Address offset: 0x08 */ + __IO uint32_t PLLCFGR; /*!< RCC System PLL configuration Register, Address offset: 0x0C */ +uint32_t RESERVED0; /*!< Reserved, Address offset: 0x10 */ +uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */ + __IO uint32_t CIER; /*!< RCC Clock Interrupt Enable Register, Address offset: 0x18 */ + __IO uint32_t CIFR; /*!< RCC Clock Interrupt Flag Register, Address offset: 0x1C */ + __IO uint32_t CICR; /*!< RCC Clock Interrupt Clear Register, Address offset: 0x20 */ +uint32_t RESERVED2; /*!< Reserved, Address offset: 0x24 */ + __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x28 */ + __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x2C */ + __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x30 */ +uint32_t RESERVED3; /*!< Reserved, Address offset: 0x34 */ + __IO uint32_t APB1RSTR1; /*!< RCC APB1 peripheral reset register 1, Address offset: 0x38 */ + __IO uint32_t APB1RSTR2; /*!< RCC APB1 peripheral reset register 2, Address offset: 0x3C */ + __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x40 */ + __IO uint32_t APB3RSTR; /*!< RCC APB3 peripheral reset register, Address offset: 0x44 */ + __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clocks enable register, Address offset: 0x48 */ + __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clocks enable register, Address offset: 0x4C */ + __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clocks enable register, Address offset: 0x50 */ +uint32_t RESERVED4; /*!< Reserved, Address offset: 0x54 */ + __IO uint32_t APB1ENR1; /*!< RCC APB1 peripheral clocks enable register 1, Address offset: 0x58 */ + __IO uint32_t APB1ENR2; /*!< RCC APB1 peripheral clocks enable register 2, Address offset: 0x5C */ + __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clocks enable register, Address offset: 0x60 */ + __IO uint32_t APB3ENR; /*!< RCC APB3 peripheral clocks enable register, Address offset: 0x64 */ + __IO uint32_t AHB1SMENR; /*!< RCC AHB1 peripheral clocks enable in sleep and stop modes register, Address offset: 0x68 */ + __IO uint32_t AHB2SMENR; /*!< RCC AHB2 peripheral clocks enable in sleep and stop modes register, Address offset: 0x6C */ + __IO uint32_t AHB3SMENR; /*!< RCC AHB3 & AHB4 peripheral clocks enable in sleep and stop modes register, Address offset: 0x70 */ +uint32_t RESERVED5; /*!< Reserved, Address offset: 0x74 */ + __IO uint32_t APB1SMENR1; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 1, Address offset: 0x78 */ + __IO uint32_t APB1SMENR2; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 2, Address offset: 0x7C */ + __IO uint32_t APB2SMENR; /*!< RCC APB2 peripheral clocks enable in sleep mode and stop modes register, Address offset: 0x80 */ + __IO uint32_t APB3SMENR; /*!< RCC APB3 peripheral clocks enable in sleep mode and stop modes register, Address offset: 0x84 */ + __IO uint32_t CCIPR; /*!< RCC Peripherals Clock Configuration Independent Register, Address offset: 0x88 */ +uint32_t RESERVED6; /*!< Reserved, Address offset: 0x8C */ + __IO uint32_t BDCR; /*!< RCC Backup Domain Control Register, Address offset: 0x90 */ + __IO uint32_t CSR; /*!< RCC Control and Status Register, Address offset: 0x94 */ +uint32_t RESERVED7[28]; /*!< Reserved, Address offset: 0x98-0x104 */ + __IO uint32_t EXTCFGR; /*!< RCC Extended Clock Recovery Register, Address offset: 0x108 */ + __IO uint32_t RESERVED8[15]; /*!< Reserved, Address offset: 0x10C-0x144 */ + __IO uint32_t C2AHB1ENR; /*!< RRCC AHB1 peripheral CPU2 clocks enable register, Address offset: 0x148 */ + __IO uint32_t C2AHB2ENR; /*!< RCC AHB2 peripheral CPU2 clocks enable register, Address offset: 0x14C */ + __IO uint32_t C2AHB3ENR; /*!< RCC AHB3 & AHB4 peripheral CPU2 clocks enable register,, Address offset: 0x150 */ +uint32_t RESERVED9; /*!< Reserved, Address offset: 0x154 */ + __IO uint32_t C2APB1ENR1; /*!< RCC APB1 peripheral CPU2 clocks enable register 1, Address offset: 0x158 */ + __IO uint32_t C2APB1ENR2; /*!< RCC APB1 peripheral CPU2 clocks enable register 2, Address offset: 0x15C */ + __IO uint32_t C2APB2ENR; /*!< RCC APB2 peripheral CPU2 clocks enable register 1, Address offset: 0x160 */ + __IO uint32_t C2APB3ENR; /*!< RCC APB3 peripheral CPU2 clocks enable register 1, Address offset: 0x164 */ + __IO uint32_t C2AHB1SMENR; /*!< RCC AHB1 peripheral CPU2 clocks enable in sleep and stop modes register, Address offset: 0x168 */ + __IO uint32_t C2AHB2SMENR; /*!< RCC AHB2 peripheral CPU2 clocks enable in sleep and stop modes register, Address offset: 0x16C */ + __IO uint32_t C2AHB3SMENR; /*!< RCC AHB3 & AHB4 peripheral CPU2 clocks enable in sleep and stop modes register, Address offset: 0x170 */ +uint32_t RESERVED10; /*!< Reserved, */ + __IO uint32_t C2APB1SMENR1;/*!< RCC APB1 peripheral CPU2 clocks enable in sleep mode and stop modes register 1, Address offset: 0x178 */ + __IO uint32_t C2APB1SMENR2;/*!< RCC APB1 peripheral CPU2 clocks enable in sleep mode and stop modes register 2, Address offset: 0x17C */ + __IO uint32_t C2APB2SMENR; /*!< RCC APB2 peripheral CPU2 clocks enable in sleep mode and stop modes register, Address offset: 0x180 */ + __IO uint32_t C2APB3SMENR; /*!< RCC APB3 peripheral CPU2 clocks enable in sleep mode and stop modes register, Address offset: 0x184 */ +} RCC_TypeDef; + +/** + * @brief RNG + */ +typedef struct +{ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x0C */ + __IO uint32_t HTCR; /*!< RNG health test control register, Address offset: 0x10 */ +} RNG_TypeDef; + +/** + * @brief RTC Specific device feature definitions + */ +#define RTC_BACKUP_NB 20u +#define RTC_TAMP_NB 3u + +/** + * @brief Real-Time Clock + */ +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */ + __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x1C */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x3C */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ + __IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */ + __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x58 */ + __IO uint32_t SCR; /*!< RTC status Clear register, Address offset: 0x5C */ + uint32_t RESERVED4[4];/*!< Reserved, Address offset: 0x58 */ + __IO uint32_t ALRABINR;/*!< RTC alarm A binary mode register, Address offset: 0x70 */ + __IO uint32_t ALRBBINR;/*!< RTC alarm B binary mode register, Address offset: 0x74 */ +} RTC_TypeDef; + +/** + * @brief Serial Peripheral Interface + */ +typedef struct +{ + __IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */ + __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ + __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */ + __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ + __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */ + __IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */ + __IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */ + __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ + __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ +} SPI_TypeDef; + +/** + * @brief System configuration controller + */ +typedef struct +{ + __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register Address offset: 0x00 */ + __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */ + __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ + __IO uint32_t SCSR; /*!< SYSCFG SRAM2 control and status register, Address offset: 0x18 */ + __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x1C */ + __IO uint32_t SWPR; /*!< SYSCFG SRAM2 write protection register part, Address offset: 0x20 */ + __IO uint32_t SKR; /*!< SYSCFG SRAM2 key register, Address offset: 0x24 */ + uint32_t RESERVED1[54]; /*!< Reserved, Address offset: 0x28-0xFC */ + __IO uint32_t IMR1; /*!< SYSCFG CPU1 (CORTEX M4) interrupt masks control-status register part 1, Address offset: 0x100 */ + __IO uint32_t IMR2; /*!< SYSCFG CPU1 (CORTEX M4) interrupt masks control-status register part 2, Address offset: 0x104 */ + __IO uint32_t C2IMR1; /*!< SYSCFG CPU2 (CORTEX M0) interrupt masks control-status register part 1, Address offset: 0x108 */ + __IO uint32_t C2IMR2; /*!< SYSCFG CPU2 (CORTEX M0) interrupt masks control-status register part 2, Address offset: 0x10C */ + uint32_t RESERVED2[62]; /*!< Reserved, Address offset: 0x110-0x204*/ + __IO uint32_t RFDCR; /*!< SYSCFG CPU2 radio debug control register, Address offset: 0x208 */ +} SYSCFG_TypeDef; + +/** + * @brief Tamper and backup registers + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TAMP configuration register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TAMP configuration register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< TAMP configuration register 3, Address offset: 0x08 */ + __IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */ + uint32_t RESERVED0[7];/*!< Reserved, Address offset: 0x10 */ + __IO uint32_t IER; /*!< TAMP interrupt enable register, Address offset: 0x2C */ + __IO uint32_t SR; /*!< TAMP status register, Address offset: 0x30 */ + __IO uint32_t MISR; /*!< TAMP masked interrupt status register, Address offset: 0x34 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x38 */ + __IO uint32_t SCR; /*!< TAMP status clear register, Address offset: 0x3C */ + __IO uint32_t COUNTR; /*!< TAMP monotonic counter register, Address offset: 0x40 */ + uint32_t RESERVED2[47];/*!< Reserved, Address offset: 0x54 - 0xFC */ + __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ + __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ + __IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */ + __IO uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */ + __IO uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */ + __IO uint32_t BKP5R; /*!< TAMP backup register 5, Address offset: 0x114 */ + __IO uint32_t BKP6R; /*!< TAMP backup register 6, Address offset: 0x118 */ + __IO uint32_t BKP7R; /*!< TAMP backup register 7, Address offset: 0x11C */ + __IO uint32_t BKP8R; /*!< TAMP backup register 8, Address offset: 0x120 */ + __IO uint32_t BKP9R; /*!< TAMP backup register 9, Address offset: 0x124 */ + __IO uint32_t BKP10R; /*!< TAMP backup register 10, Address offset: 0x128 */ + __IO uint32_t BKP11R; /*!< TAMP backup register 11, Address offset: 0x12C */ + __IO uint32_t BKP12R; /*!< TAMP backup register 12, Address offset: 0x130 */ + __IO uint32_t BKP13R; /*!< TAMP backup register 13, Address offset: 0x134 */ + __IO uint32_t BKP14R; /*!< TAMP backup register 14, Address offset: 0x138 */ + __IO uint32_t BKP15R; /*!< TAMP backup register 15, Address offset: 0x13C */ + __IO uint32_t BKP16R; /*!< TAMP backup register 16, Address offset: 0x140 */ + __IO uint32_t BKP17R; /*!< TAMP backup register 17, Address offset: 0x144 */ + __IO uint32_t BKP18R; /*!< TAMP backup register 18, Address offset: 0x148 */ + __IO uint32_t BKP19R; /*!< TAMP backup register 19, Address offset: 0x14C */ +} TAMP_TypeDef; + +/** + * @brief TIM + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ + __IO uint32_t OR1; /*!< TIM option register Address offset: 0x50 */ + __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */ + __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */ + __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */ + __IO uint32_t AF1; /*!< TIM Alternate function option register 1, Address offset: 0x60 */ + __IO uint32_t AF2; /*!< TIM Alternate function option register 2, Address offset: 0x64 */ +} TIM_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ +typedef struct +{ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ + __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ + __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ + __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ + __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */ +} USART_TypeDef; + +/** + * @brief VREFBUF + */ +typedef struct +{ + __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */ + __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */ +} VREFBUF_TypeDef; + +/** + * @brief Window WATCHDOG + */ +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + +/** + * @} + */ + +/** @addtogroup Peripheral_memory_map + * @{ + */ +/*!< Boundary memory map */ +#define FLASH_BASE 0x08000000UL /*!< FLASH(up to 256 KB) base address */ +#define SYSTEM_FLASH_BASE 0x1FFF0000UL /*!< System FLASH(28Kb) base address */ +#define SRAM1_BASE 0x20000000UL /*!< SRAM1(up to 32 KB) base address */ +#define SRAM2_BASE 0x20008000UL /*!< SRAM2(up to 32 KB) base address */ +#define PERIPH_BASE 0x40000000UL /*!< Peripheral base address */ + +#define FLASH_SIZE (((*((uint32_t *)FLASHSIZE_BASE)) & 0xFFFFU) << 10U) +#define SRAM1_SIZE 0x00008000UL /*!< SRAM1 default size : 32 kB */ +#define SRAM2_SIZE 0x00008000UL /*!< SRAM2 default size : 32 kB */ + +/*!< Memory, OTP and Option bytes */ +#define RSSLIB_PFUNC_BASE (SYSTEM_FLASH_BASE + 0x00003A00UL) /*!< RSS area */ +#define OTP_AREA_BASE (SYSTEM_FLASH_BASE + 0x00007000UL) /*!< OTP area : 1kB (0x1FFF7000 - 0x1FFF73FF) */ +#define ENGI_BYTES_BASE (SYSTEM_FLASH_BASE + 0x00007400UL) /*!< Engi Bytes : 1kB (0x1FFF7400 - 0x1FFF77FF) */ +#define OPTION_BYTES_BASE (SYSTEM_FLASH_BASE + 0x00007800UL) /*!< Option Bytes : 2kB (0x1FFF7800 - 0x1FFF7FFF) */ + +/*!< Device Electronic Signature */ +#define PACKAGE_BASE (ENGI_BYTES_BASE + 0x00000100UL) /*!< Package data register base address */ +#define UID64_BASE (ENGI_BYTES_BASE + 0x00000180UL) /*!< 64-bit Unique device Identification */ +#define UID_BASE (ENGI_BYTES_BASE + 0x00000190UL) /*!< Unique device ID register base address */ +#define FLASHSIZE_BASE (ENGI_BYTES_BASE + 0x000001E0UL) /*!< Flash size data register base address */ + +#define SYSTEM_MEMORY_END_ADDR (0x1FFF6FFFUL) /*!< System Memory : 28KB (0x1FFF0000 - 0x1FFF6FFF) */ +#define OTP_AREA_END_ADDR (0x1FFF73FFUL) /*!< OTP area : 1KB (0x1FFF7000 - 0x1FFF73FF) */ +#define ENGI_BYTE_END_ADDR (0x1FFF77FFUL) /*!< Engi Bytes : 1kB (0x1FFF7400 - 0x1FFF77FF) */ +#define OPTION_BYTE_END_ADDR (0x1FFF7FFFUL) /*!< Option Bytes : 2KB (0x1FFF7800 - 0x1FFF7FFF) */ + +/*!< Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE +#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) +#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) +#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL) +#define AHB3PERIPH_BASE (PERIPH_BASE + 0x18000000UL) +#define APB3PERIPH_BASE (PERIPH_BASE + 0x18010000UL) + +/*!< APB1 peripherals */ +#define TIM2_BASE (APB1PERIPH_BASE + 0x00000000UL) +#define RTC_BASE (APB1PERIPH_BASE + 0x00002800UL) +#define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00UL) +#define IWDG_BASE (APB1PERIPH_BASE + 0x00003000UL) +#define SPI2_BASE (APB1PERIPH_BASE + 0x00003800UL) +#define USART2_BASE (APB1PERIPH_BASE + 0x00004400UL) +#define I2C1_BASE (APB1PERIPH_BASE + 0x00005400UL) +#define I2C2_BASE (APB1PERIPH_BASE + 0x00005800UL) +#define I2C3_BASE (APB1PERIPH_BASE + 0x00005C00UL) +#define DAC_BASE (APB1PERIPH_BASE + 0x00007400UL) +#define LPTIM1_BASE (APB1PERIPH_BASE + 0x00007C00UL) +#define LPUART1_BASE (APB1PERIPH_BASE + 0x00008000UL) +#define LPTIM2_BASE (APB1PERIPH_BASE + 0x00009400UL) +#define LPTIM3_BASE (APB1PERIPH_BASE + 0x00009800UL) +#define TAMP_BASE (APB1PERIPH_BASE + 0x0000B000UL) + +/*!< APB2 peripherals */ +#define SYSCFG_BASE (APB2PERIPH_BASE + 0x00000000UL) +#define VREFBUF_BASE (APB2PERIPH_BASE + 0x00000030UL) +#define COMP1_BASE (APB2PERIPH_BASE + 0x00000200UL) +#define COMP2_BASE (APB2PERIPH_BASE + 0x00000204UL) +#define ADC_BASE (APB2PERIPH_BASE + 0x00002400UL) +#define ADC_COMMON_BASE (APB2PERIPH_BASE + 0x00002708UL) +#define TIM1_BASE (APB2PERIPH_BASE + 0x00002C00UL) +#define SPI1_BASE (APB2PERIPH_BASE + 0x00003000UL) +#define USART1_BASE (APB2PERIPH_BASE + 0x00003800UL) +#define TIM16_BASE (APB2PERIPH_BASE + 0x00004400UL) +#define TIM17_BASE (APB2PERIPH_BASE + 0x00004800UL) + +/*!< AHB1 peripherals */ +#define DMA1_BASE (AHB1PERIPH_BASE + 0x00000000UL) +#define DMA2_BASE (AHB1PERIPH_BASE + 0x00000400UL) +#define DMAMUX1_BASE (AHB1PERIPH_BASE + 0x00000800UL) +#define CRC_BASE (AHB1PERIPH_BASE + 0x00003000UL) + +#define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008UL) +#define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CUL) +#define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030UL) +#define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044UL) +#define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058UL) +#define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006CUL) +#define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080UL) + +#define DMA2_Channel1_BASE (DMA2_BASE + 0x00000008UL) +#define DMA2_Channel2_BASE (DMA2_BASE + 0x0000001CUL) +#define DMA2_Channel3_BASE (DMA2_BASE + 0x00000030UL) +#define DMA2_Channel4_BASE (DMA2_BASE + 0x00000044UL) +#define DMA2_Channel5_BASE (DMA2_BASE + 0x00000058UL) +#define DMA2_Channel6_BASE (DMA2_BASE + 0x0000006CUL) +#define DMA2_Channel7_BASE (DMA2_BASE + 0x00000080UL) + +#define DMAMUX1_Channel0_BASE (DMAMUX1_BASE) +#define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x00000004UL) +#define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x00000008UL) +#define DMAMUX1_Channel3_BASE (DMAMUX1_BASE + 0x0000000CUL) +#define DMAMUX1_Channel4_BASE (DMAMUX1_BASE + 0x00000010UL) +#define DMAMUX1_Channel5_BASE (DMAMUX1_BASE + 0x00000014UL) +#define DMAMUX1_Channel6_BASE (DMAMUX1_BASE + 0x00000018UL) +#define DMAMUX1_Channel7_BASE (DMAMUX1_BASE + 0x0000001CUL) +#define DMAMUX1_Channel8_BASE (DMAMUX1_BASE + 0x00000020UL) +#define DMAMUX1_Channel9_BASE (DMAMUX1_BASE + 0x00000024UL) +#define DMAMUX1_Channel10_BASE (DMAMUX1_BASE + 0x00000028UL) +#define DMAMUX1_Channel11_BASE (DMAMUX1_BASE + 0x0000002CUL) +#define DMAMUX1_Channel12_BASE (DMAMUX1_BASE + 0x00000030UL) +#define DMAMUX1_Channel13_BASE (DMAMUX1_BASE + 0x00000034UL) + +#define DMAMUX1_RequestGenerator0_BASE (DMAMUX1_BASE + 0x00000100UL) +#define DMAMUX1_RequestGenerator1_BASE (DMAMUX1_BASE + 0x00000104UL) +#define DMAMUX1_RequestGenerator2_BASE (DMAMUX1_BASE + 0x00000108UL) +#define DMAMUX1_RequestGenerator3_BASE (DMAMUX1_BASE + 0x0000010CUL) + +#define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x00000080UL) +#define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x00000140UL) + +/*!< AHB2 peripherals */ +#define IOPORT_BASE (AHB2PERIPH_BASE + 0x00000000UL) +#define GPIOA_BASE (IOPORT_BASE + 0x00000000UL) +#define GPIOB_BASE (IOPORT_BASE + 0x00000400UL) +#define GPIOC_BASE (IOPORT_BASE + 0x00000800UL) +#define GPIOH_BASE (IOPORT_BASE + 0x00001C00UL) + +/*!< AHB3 peripherals */ +#define PWR_BASE (AHB3PERIPH_BASE + 0x00000400UL) +#define EXTI_BASE (AHB3PERIPH_BASE + 0x00000800UL) +#define IPCC_BASE (AHB3PERIPH_BASE + 0x00000C00UL) +#define RCC_BASE (AHB3PERIPH_BASE + 0x00000000UL) +#define RNG_BASE (AHB3PERIPH_BASE + 0x00001000UL) +#define HSEM_BASE (AHB3PERIPH_BASE + 0x00001400UL) +#define AES_BASE (AHB3PERIPH_BASE + 0x00001800UL) +#define PKA_BASE (AHB3PERIPH_BASE + 0x00002000UL) +#define FLASH_REG_BASE (AHB3PERIPH_BASE + 0x00004000UL) +#define GTZC_TZSC_BASE (AHB3PERIPH_BASE + 0x00004400UL) +#define GTZC_TZIC_BASE (AHB3PERIPH_BASE + 0x00004800UL) + +/*!< APB3 peripherals */ +#define SUBGHZSPI_BASE (APB3PERIPH_BASE + 0x00000000UL) + +#if defined(CORE_CM0PLUS) +#else +/*!< Peripherals available on CPU1 external PPB bus */ +#define DBGMCU_BASE (0xE0042000UL) +#endif + +/** + * @} + */ + +/** @addtogroup Peripheral_declaration + * @{ + */ + +/* Peripherals available on APB1 bus */ +#define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#define IWDG ((IWDG_TypeDef *) IWDG_BASE) +#define WWDG ((WWDG_TypeDef *) WWDG_BASE) +#define DAC ((DAC_TypeDef *) DAC_BASE) +#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE) +#define LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE) +#define LPTIM3 ((LPTIM_TypeDef *) LPTIM3_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) +#define I2C3 ((I2C_TypeDef *) I2C3_BASE) +#define TAMP ((TAMP_TypeDef *) TAMP_BASE) +#define USART2 ((USART_TypeDef *) USART2_BASE) +#define LPUART1 ((USART_TypeDef *) LPUART1_BASE) + +/* Peripherals available on APB2 bus */ +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) +#define VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE) +#define COMP1 ((COMP_TypeDef *) COMP1_BASE) +#define COMP2 ((COMP_TypeDef *) COMP2_BASE) +#define COMP12_COMMON ((COMP_Common_TypeDef *) COMP2_BASE) +#define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define ADC ((ADC_TypeDef *) ADC_BASE) +#define ADC_COMMON ((ADC_Common_TypeDef *) ADC_COMMON_BASE) +#define TIM16 ((TIM_TypeDef *) TIM16_BASE) +#define TIM17 ((TIM_TypeDef *) TIM17_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) + +/* Peripherals available on AHB1 bus */ +#define DMA1 ((DMA_TypeDef *) DMA1_BASE) +#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) +#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) +#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) +#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) +#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) +#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) +#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) + +#define DMA2 ((DMA_TypeDef *) DMA2_BASE) +#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE) +#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE) +#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE) +#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE) +#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE) +#define DMA2_Channel6 ((DMA_Channel_TypeDef *) DMA2_Channel6_BASE) +#define DMA2_Channel7 ((DMA_Channel_TypeDef *) DMA2_Channel7_BASE) + +#define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE) +#define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE) +#define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE) +#define DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE) +#define DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE) +#define DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE) +#define DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE) +#define DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE) +#define DMAMUX1_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE) +#define DMAMUX1_Channel8 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE) +#define DMAMUX1_Channel9 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE) +#define DMAMUX1_Channel10 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE) +#define DMAMUX1_Channel11 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE) +#define DMAMUX1_Channel12 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE) +#define DMAMUX1_Channel13 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE) + +#define DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE) +#define DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE) +#define DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE) +#define DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE) + +#define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE) +#define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE) + +#define CRC ((CRC_TypeDef *) CRC_BASE) + +/* Peripherals available on AHB2 bus */ +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) + +/* Peripherals available on AH3 bus */ +#define AES ((AES_TypeDef *) AES_BASE) + +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define IPCC ((IPCC_TypeDef *) IPCC_BASE) +#define IPCC_C1 ((IPCC_CommonTypeDef *) IPCC_BASE) +#define IPCC_C2 ((IPCC_CommonTypeDef *) (IPCC_BASE + 0x10U)) +#define RCC ((RCC_TypeDef *) RCC_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define RNG ((RNG_TypeDef *) RNG_BASE) +#define HSEM ((HSEM_TypeDef *) HSEM_BASE) +#if defined(CORE_CM0PLUS) +#define HSEM_COMMON ((HSEM_Common_TypeDef *) (HSEM_BASE + 0x110U)) +#else +#define HSEM_COMMON ((HSEM_Common_TypeDef *) (HSEM_BASE + 0x100U)) +#endif +#define PKA ((PKA_TypeDef *) PKA_BASE) +#define FLASH ((FLASH_TypeDef *) FLASH_REG_BASE) +#define GTZC_TZSC ((GTZC_TZSC_TypeDef *) GTZC_TZSC_BASE) +#define GTZC_TZIC ((GTZC_TZIC_TypeDef *) GTZC_TZIC_BASE) + +/* Peripherals available on APB3 bus */ +#define SUBGHZSPI ((SPI_TypeDef *) SUBGHZSPI_BASE) + +#if defined(CORE_CM0PLUS) +#else +/* Peripherals available on CPU1 external PPB bus */ +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) +#endif + +/** + * @} + */ + +/** @addtogroup Exported_constants + * @{ + */ + +/** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */ + +/** + * @} + */ + +/** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* Peripheral Registers Bits Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter (ADC) */ +/* */ +/******************************************************************************/ +/******************** Bit definition for ADC_ISR register *******************/ +#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */ +#define ADC_ISR_EOSMP_Pos (1U) +#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ +#define ADC_ISR_EOC_Pos (2U) +#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ +#define ADC_ISR_EOS_Pos (3U) +#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ +#define ADC_ISR_OVR_Pos (4U) +#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ +#define ADC_ISR_AWD1_Pos (7U) +#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */ +#define ADC_ISR_AWD2_Pos (8U) +#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */ +#define ADC_ISR_AWD3_Pos (9U) +#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */ +#define ADC_ISR_EOCAL_Pos (11U) +#define ADC_ISR_EOCAL_Msk (0x1UL << ADC_ISR_EOCAL_Pos) /*!< 0x00000800 */ +#define ADC_ISR_EOCAL ADC_ISR_EOCAL_Msk /*!< ADC end of calibration flag */ +#define ADC_ISR_CCRDY_Pos (13U) +#define ADC_ISR_CCRDY_Msk (0x1UL << ADC_ISR_CCRDY_Pos) /*!< 0x00002000 */ +#define ADC_ISR_CCRDY ADC_ISR_CCRDY_Msk /*!< ADC channel configuration ready flag */ + +/******************** Bit definition for ADC_IER register *******************/ +#define ADC_IER_ADRDYIE_Pos (0U) +#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */ +#define ADC_IER_EOSMPIE_Pos (1U) +#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ +#define ADC_IER_EOCIE_Pos (2U) +#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */ +#define ADC_IER_EOSIE_Pos (3U) +#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ +#define ADC_IER_OVRIE_Pos (4U) +#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ +#define ADC_IER_AWD1IE_Pos (7U) +#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */ +#define ADC_IER_AWD2IE_Pos (8U) +#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */ +#define ADC_IER_AWD3IE_Pos (9U) +#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */ +#define ADC_IER_EOCALIE_Pos (11U) +#define ADC_IER_EOCALIE_Msk (0x1UL << ADC_IER_EOCALIE_Pos) /*!< 0x00000800 */ +#define ADC_IER_EOCALIE ADC_IER_EOCALIE_Msk /*!< ADC end of calibration interrupt */ +#define ADC_IER_CCRDYIE_Pos (13U) +#define ADC_IER_CCRDYIE_Msk (0x1UL << ADC_IER_CCRDYIE_Pos) /*!< 0x00002000 */ +#define ADC_IER_CCRDYIE ADC_IER_CCRDYIE_Msk /*!< ADC channel configuration ready interrupt */ + +/******************** Bit definition for ADC_CR register ********************/ +#define ADC_CR_ADEN_Pos (0U) +#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ +#define ADC_CR_ADDIS_Pos (1U) +#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */ +#define ADC_CR_ADSTART_Pos (2U) +#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ +#define ADC_CR_ADSTP_Pos (4U) +#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */ +#define ADC_CR_ADVREGEN_Pos (28U) +#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */ +#define ADC_CR_ADCAL_Pos (31U) +#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ + +/******************** Bit definition for ADC_CFGR1 register *****************/ +#define ADC_CFGR1_DMAEN_Pos (0U) +#define ADC_CFGR1_DMAEN_Msk (0x1UL << ADC_CFGR1_DMAEN_Pos) /*!< 0x00000001 */ +#define ADC_CFGR1_DMAEN ADC_CFGR1_DMAEN_Msk /*!< ADC DMA transfer enable */ +#define ADC_CFGR1_DMACFG_Pos (1U) +#define ADC_CFGR1_DMACFG_Msk (0x1UL << ADC_CFGR1_DMACFG_Pos) /*!< 0x00000002 */ +#define ADC_CFGR1_DMACFG ADC_CFGR1_DMACFG_Msk /*!< ADC DMA transfer configuration */ + +#define ADC_CFGR1_SCANDIR_Pos (2U) +#define ADC_CFGR1_SCANDIR_Msk (0x1UL << ADC_CFGR1_SCANDIR_Pos) /*!< 0x00000004 */ +#define ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR_Msk /*!< ADC group regular sequencer scan direction */ + +#define ADC_CFGR1_RES_Pos (3U) +#define ADC_CFGR1_RES_Msk (0x3UL << ADC_CFGR1_RES_Pos) /*!< 0x00000018 */ +#define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< ADC data resolution */ +#define ADC_CFGR1_RES_0 (0x1UL << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */ +#define ADC_CFGR1_RES_1 (0x2UL << ADC_CFGR1_RES_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR1_ALIGN_Pos (5U) +#define ADC_CFGR1_ALIGN_Msk (0x1UL << ADC_CFGR1_ALIGN_Pos) /*!< 0x00000020 */ +#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< ADC data alignment */ + +#define ADC_CFGR1_EXTSEL_Pos (6U) +#define ADC_CFGR1_EXTSEL_Msk (0x7UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */ +#define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< ADC group regular external trigger source */ +#define ADC_CFGR1_EXTSEL_0 (0x1UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR1_EXTSEL_1 (0x2UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR1_EXTSEL_2 (0x4UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR1_EXTEN_Pos (10U) +#define ADC_CFGR1_EXTEN_Msk (0x3UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< ADC group regular external trigger polarity */ +#define ADC_CFGR1_EXTEN_0 (0x1UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR1_EXTEN_1 (0x2UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */ + +#define ADC_CFGR1_OVRMOD_Pos (12U) +#define ADC_CFGR1_OVRMOD_Msk (0x1UL << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< ADC group regular overrun configuration */ +#define ADC_CFGR1_CONT_Pos (13U) +#define ADC_CFGR1_CONT_Msk (0x1UL << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< ADC group regular continuous conversion mode */ +#define ADC_CFGR1_WAIT_Pos (14U) +#define ADC_CFGR1_WAIT_Msk (0x1UL << ADC_CFGR1_WAIT_Pos) /*!< 0x00004000 */ +#define ADC_CFGR1_WAIT ADC_CFGR1_WAIT_Msk /*!< ADC low power auto wait */ +#define ADC_CFGR1_AUTOFF_Pos (15U) +#define ADC_CFGR1_AUTOFF_Msk (0x1UL << ADC_CFGR1_AUTOFF_Pos) /*!< 0x00008000 */ +#define ADC_CFGR1_AUTOFF ADC_CFGR1_AUTOFF_Msk /*!< ADC low power auto power off */ +#define ADC_CFGR1_DISCEN_Pos (16U) +#define ADC_CFGR1_DISCEN_Msk (0x1UL << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ +#define ADC_CFGR1_CHSELRMOD_Pos (21U) +#define ADC_CFGR1_CHSELRMOD_Msk (0x1UL << ADC_CFGR1_CHSELRMOD_Pos) /*!< 0x00200000 */ +#define ADC_CFGR1_CHSELRMOD ADC_CFGR1_CHSELRMOD_Msk /*!< ADC group regular sequencer mode */ + +#define ADC_CFGR1_AWD1SGL_Pos (22U) +#define ADC_CFGR1_AWD1SGL_Msk (0x1UL << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR1_AWD1SGL ADC_CFGR1_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ +#define ADC_CFGR1_AWD1EN_Pos (23U) +#define ADC_CFGR1_AWD1EN_Msk (0x1UL << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR1_AWD1EN ADC_CFGR1_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ + +#define ADC_CFGR1_AWD1CH_Pos (26U) +#define ADC_CFGR1_AWD1CH_Msk (0x1FUL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR1_AWD1CH ADC_CFGR1_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ +#define ADC_CFGR1_AWD1CH_0 (0x01UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR1_AWD1CH_1 (0x02UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR1_AWD1CH_2 (0x04UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR1_AWD1CH_3 (0x08UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR1_AWD1CH_4 (0x10UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_CFGR2 register *****************/ +#define ADC_CFGR2_OVSE_Pos (0U) +#define ADC_CFGR2_OVSE_Msk (0x1UL << ADC_CFGR2_OVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_OVSE ADC_CFGR2_OVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */ + +#define ADC_CFGR2_OVSR_Pos (2U) +#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ +#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ +#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ +#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ +#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR2_OVSS_Pos (5U) +#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */ +#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR2_TOVS_Pos (9U) +#define ADC_CFGR2_TOVS_Msk (0x1UL << ADC_CFGR2_TOVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TOVS ADC_CFGR2_TOVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */ + +#define ADC_CFGR2_LFTRIG_Pos (29U) +#define ADC_CFGR2_LFTRIG_Msk (0x1UL << ADC_CFGR2_LFTRIG_Pos) /*!< 0x20000000 */ +#define ADC_CFGR2_LFTRIG ADC_CFGR2_LFTRIG_Msk /*!< ADC low frequency trigger mode */ + +#define ADC_CFGR2_CKMODE_Pos (30U) +#define ADC_CFGR2_CKMODE_Msk (0x3UL << ADC_CFGR2_CKMODE_Pos) /*!< 0xC0000000 */ +#define ADC_CFGR2_CKMODE ADC_CFGR2_CKMODE_Msk /*!< ADC clock source and prescaler (prescaler only for clock source synchronous) */ +#define ADC_CFGR2_CKMODE_1 (0x2UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x80000000 */ +#define ADC_CFGR2_CKMODE_0 (0x1UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_SMPR register ******************/ +#define ADC_SMPR_SMP1_Pos (0U) +#define ADC_SMPR_SMP1_Msk (0x7UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000007 */ +#define ADC_SMPR_SMP1 ADC_SMPR_SMP1_Msk /*!< ADC group of channels sampling time 1 */ +#define ADC_SMPR_SMP1_0 (0x1UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000001 */ +#define ADC_SMPR_SMP1_1 (0x2UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000002 */ +#define ADC_SMPR_SMP1_2 (0x4UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR_SMP2_Pos (4U) +#define ADC_SMPR_SMP2_Msk (0x7UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000070 */ +#define ADC_SMPR_SMP2 ADC_SMPR_SMP2_Msk /*!< ADC group of channels sampling time 2 */ +#define ADC_SMPR_SMP2_0 (0x1UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000010 */ +#define ADC_SMPR_SMP2_1 (0x2UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000020 */ +#define ADC_SMPR_SMP2_2 (0x4UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000040 */ + +#define ADC_SMPR_SMPSEL_Pos (8U) +#define ADC_SMPR_SMPSEL_Msk (0x3FFFFUL << ADC_SMPR_SMPSEL_Pos) /*!< 0x03FFFF00 */ +#define ADC_SMPR_SMPSEL ADC_SMPR_SMPSEL_Msk /*!< ADC all channels sampling time selection */ +#define ADC_SMPR_SMPSEL0_Pos (8U) +#define ADC_SMPR_SMPSEL0_Msk (0x1UL << ADC_SMPR_SMPSEL0_Pos) /*!< 0x00000100 */ +#define ADC_SMPR_SMPSEL0 ADC_SMPR_SMPSEL0_Msk /*!< ADC channel 0 sampling time selection */ +#define ADC_SMPR_SMPSEL1_Pos (9U) +#define ADC_SMPR_SMPSEL1_Msk (0x1UL << ADC_SMPR_SMPSEL1_Pos) /*!< 0x00000200 */ +#define ADC_SMPR_SMPSEL1 ADC_SMPR_SMPSEL1_Msk /*!< ADC channel 1 sampling time selection */ +#define ADC_SMPR_SMPSEL2_Pos (10U) +#define ADC_SMPR_SMPSEL2_Msk (0x1UL << ADC_SMPR_SMPSEL2_Pos) /*!< 0x00000400 */ +#define ADC_SMPR_SMPSEL2 ADC_SMPR_SMPSEL2_Msk /*!< ADC channel 2 sampling time selection */ +#define ADC_SMPR_SMPSEL3_Pos (11U) +#define ADC_SMPR_SMPSEL3_Msk (0x1UL << ADC_SMPR_SMPSEL3_Pos) /*!< 0x00000800 */ +#define ADC_SMPR_SMPSEL3 ADC_SMPR_SMPSEL3_Msk /*!< ADC channel 3 sampling time selection */ +#define ADC_SMPR_SMPSEL4_Pos (12U) +#define ADC_SMPR_SMPSEL4_Msk (0x1UL << ADC_SMPR_SMPSEL4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR_SMPSEL4 ADC_SMPR_SMPSEL4_Msk /*!< ADC channel 4 sampling time selection */ +#define ADC_SMPR_SMPSEL5_Pos (13U) +#define ADC_SMPR_SMPSEL5_Msk (0x1UL << ADC_SMPR_SMPSEL5_Pos) /*!< 0x00002000 */ +#define ADC_SMPR_SMPSEL5 ADC_SMPR_SMPSEL5_Msk /*!< ADC channel 5 sampling time selection */ +#define ADC_SMPR_SMPSEL6_Pos (14U) +#define ADC_SMPR_SMPSEL6_Msk (0x1UL << ADC_SMPR_SMPSEL6_Pos) /*!< 0x00004000 */ +#define ADC_SMPR_SMPSEL6 ADC_SMPR_SMPSEL6_Msk /*!< ADC channel 6 sampling time selection */ +#define ADC_SMPR_SMPSEL7_Pos (15U) +#define ADC_SMPR_SMPSEL7_Msk (0x1UL << ADC_SMPR_SMPSEL7_Pos) /*!< 0x00008000 */ +#define ADC_SMPR_SMPSEL7 ADC_SMPR_SMPSEL7_Msk /*!< ADC channel 7 sampling time selection */ +#define ADC_SMPR_SMPSEL8_Pos (16U) +#define ADC_SMPR_SMPSEL8_Msk (0x1UL << ADC_SMPR_SMPSEL8_Pos) /*!< 0x00010000 */ +#define ADC_SMPR_SMPSEL8 ADC_SMPR_SMPSEL8_Msk /*!< ADC channel 8 sampling time selection */ +#define ADC_SMPR_SMPSEL9_Pos (17U) +#define ADC_SMPR_SMPSEL9_Msk (0x1UL << ADC_SMPR_SMPSEL9_Pos) /*!< 0x00020000 */ +#define ADC_SMPR_SMPSEL9 ADC_SMPR_SMPSEL9_Msk /*!< ADC channel 9 sampling time selection */ +#define ADC_SMPR_SMPSEL10_Pos (18U) +#define ADC_SMPR_SMPSEL10_Msk (0x1UL << ADC_SMPR_SMPSEL10_Pos) /*!< 0x00040000 */ +#define ADC_SMPR_SMPSEL10 ADC_SMPR_SMPSEL10_Msk /*!< ADC channel 10 sampling time selection */ +#define ADC_SMPR_SMPSEL11_Pos (19U) +#define ADC_SMPR_SMPSEL11_Msk (0x1UL << ADC_SMPR_SMPSEL11_Pos) /*!< 0x00080000 */ +#define ADC_SMPR_SMPSEL11 ADC_SMPR_SMPSEL11_Msk /*!< ADC channel 11 sampling time selection */ +#define ADC_SMPR_SMPSEL12_Pos (20U) +#define ADC_SMPR_SMPSEL12_Msk (0x1UL << ADC_SMPR_SMPSEL12_Pos) /*!< 0x00100000 */ +#define ADC_SMPR_SMPSEL12 ADC_SMPR_SMPSEL12_Msk /*!< ADC channel 12 sampling time selection */ +#define ADC_SMPR_SMPSEL13_Pos (21U) +#define ADC_SMPR_SMPSEL13_Msk (0x1UL << ADC_SMPR_SMPSEL13_Pos) /*!< 0x00200000 */ +#define ADC_SMPR_SMPSEL13 ADC_SMPR_SMPSEL13_Msk /*!< ADC channel 13 sampling time selection */ +#define ADC_SMPR_SMPSEL14_Pos (22U) +#define ADC_SMPR_SMPSEL14_Msk (0x1UL << ADC_SMPR_SMPSEL14_Pos) /*!< 0x00400000 */ +#define ADC_SMPR_SMPSEL14 ADC_SMPR_SMPSEL14_Msk /*!< ADC channel 14 sampling time selection */ +#define ADC_SMPR_SMPSEL15_Pos (23U) +#define ADC_SMPR_SMPSEL15_Msk (0x1UL << ADC_SMPR_SMPSEL15_Pos) /*!< 0x00800000 */ +#define ADC_SMPR_SMPSEL15 ADC_SMPR_SMPSEL15_Msk /*!< ADC channel 15 sampling time selection */ +#define ADC_SMPR_SMPSEL16_Pos (24U) +#define ADC_SMPR_SMPSEL16_Msk (0x1UL << ADC_SMPR_SMPSEL16_Pos) /*!< 0x01000000 */ +#define ADC_SMPR_SMPSEL16 ADC_SMPR_SMPSEL16_Msk /*!< ADC channel 16 sampling time selection */ +#define ADC_SMPR_SMPSEL17_Pos (25U) +#define ADC_SMPR_SMPSEL17_Msk (0x1UL << ADC_SMPR_SMPSEL17_Pos) /*!< 0x02000000 */ +#define ADC_SMPR_SMPSEL17 ADC_SMPR_SMPSEL17_Msk /*!< ADC channel 17 sampling time selection */ + +/******************** Bit definition for ADC_AWD1TR register ****************/ +#define ADC_AWD1TR_LT1_Pos (0U) +#define ADC_AWD1TR_LT1_Msk (0xFFFUL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000FFF */ +#define ADC_AWD1TR_LT1 ADC_AWD1TR_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ +#define ADC_AWD1TR_LT1_0 (0x001UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000001 */ +#define ADC_AWD1TR_LT1_1 (0x002UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000002 */ +#define ADC_AWD1TR_LT1_2 (0x004UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000004 */ +#define ADC_AWD1TR_LT1_3 (0x008UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000008 */ +#define ADC_AWD1TR_LT1_4 (0x010UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000010 */ +#define ADC_AWD1TR_LT1_5 (0x020UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000020 */ +#define ADC_AWD1TR_LT1_6 (0x040UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000040 */ +#define ADC_AWD1TR_LT1_7 (0x080UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000080 */ +#define ADC_AWD1TR_LT1_8 (0x100UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000100 */ +#define ADC_AWD1TR_LT1_9 (0x200UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000200 */ +#define ADC_AWD1TR_LT1_10 (0x400UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000400 */ +#define ADC_AWD1TR_LT1_11 (0x800UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000800 */ + +#define ADC_AWD1TR_HT1_Pos (16U) +#define ADC_AWD1TR_HT1_Msk (0xFFFUL << ADC_AWD1TR_HT1_Pos) /*!< 0x0FFF0000 */ +#define ADC_AWD1TR_HT1 ADC_AWD1TR_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */ +#define ADC_AWD1TR_HT1_0 (0x001UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00010000 */ +#define ADC_AWD1TR_HT1_1 (0x002UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00020000 */ +#define ADC_AWD1TR_HT1_2 (0x004UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00040000 */ +#define ADC_AWD1TR_HT1_3 (0x008UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00080000 */ +#define ADC_AWD1TR_HT1_4 (0x010UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00100000 */ +#define ADC_AWD1TR_HT1_5 (0x020UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00200000 */ +#define ADC_AWD1TR_HT1_6 (0x040UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00400000 */ +#define ADC_AWD1TR_HT1_7 (0x080UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00800000 */ +#define ADC_AWD1TR_HT1_8 (0x100UL << ADC_AWD1TR_HT1_Pos) /*!< 0x01000000 */ +#define ADC_AWD1TR_HT1_9 (0x200UL << ADC_AWD1TR_HT1_Pos) /*!< 0x02000000 */ +#define ADC_AWD1TR_HT1_10 (0x400UL << ADC_AWD1TR_HT1_Pos) /*!< 0x04000000 */ +#define ADC_AWD1TR_HT1_11 (0x800UL << ADC_AWD1TR_HT1_Pos) /*!< 0x08000000 */ + +/* Legacy definitions */ +#define ADC_TR1_LT1 ADC_AWD1TR_LT1 +#define ADC_TR1_LT1_0 ADC_AWD1TR_LT1_0 +#define ADC_TR1_LT1_1 ADC_AWD1TR_LT1_1 +#define ADC_TR1_LT1_2 ADC_AWD1TR_LT1_2 +#define ADC_TR1_LT1_3 ADC_AWD1TR_LT1_3 +#define ADC_TR1_LT1_4 ADC_AWD1TR_LT1_4 +#define ADC_TR1_LT1_5 ADC_AWD1TR_LT1_5 +#define ADC_TR1_LT1_6 ADC_AWD1TR_LT1_6 +#define ADC_TR1_LT1_7 ADC_AWD1TR_LT1_7 +#define ADC_TR1_LT1_8 ADC_AWD1TR_LT1_8 +#define ADC_TR1_LT1_9 ADC_AWD1TR_LT1_9 +#define ADC_TR1_LT1_10 ADC_AWD1TR_LT1_10 +#define ADC_TR1_LT1_11 ADC_AWD1TR_LT1_11 + +#define ADC_TR1_HT1 ADC_AWD1TR_HT1 +#define ADC_TR1_HT1_0 ADC_AWD1TR_HT1_0 +#define ADC_TR1_HT1_1 ADC_AWD1TR_HT1_1 +#define ADC_TR1_HT1_2 ADC_AWD1TR_HT1_2 +#define ADC_TR1_HT1_3 ADC_AWD1TR_HT1_3 +#define ADC_TR1_HT1_4 ADC_AWD1TR_HT1_4 +#define ADC_TR1_HT1_5 ADC_AWD1TR_HT1_5 +#define ADC_TR1_HT1_6 ADC_AWD1TR_HT1_6 +#define ADC_TR1_HT1_7 ADC_AWD1TR_HT1_7 +#define ADC_TR1_HT1_8 ADC_AWD1TR_HT1_8 +#define ADC_TR1_HT1_9 ADC_AWD1TR_HT1_9 +#define ADC_TR1_HT1_10 ADC_AWD1TR_HT1_10 +#define ADC_TR1_HT1_11 ADC_AWD1TR_HT1_11 + +/******************** Bit definition for ADC_AWD2TR register *******************/ +#define ADC_AWD2TR_LT2_Pos (0U) +#define ADC_AWD2TR_LT2_Msk (0xFFFUL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000FFF */ +#define ADC_AWD2TR_LT2 ADC_AWD2TR_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ +#define ADC_AWD2TR_LT2_0 (0x001UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000001 */ +#define ADC_AWD2TR_LT2_1 (0x002UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000002 */ +#define ADC_AWD2TR_LT2_2 (0x004UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000004 */ +#define ADC_AWD2TR_LT2_3 (0x008UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000008 */ +#define ADC_AWD2TR_LT2_4 (0x010UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000010 */ +#define ADC_AWD2TR_LT2_5 (0x020UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000020 */ +#define ADC_AWD2TR_LT2_6 (0x040UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000040 */ +#define ADC_AWD2TR_LT2_7 (0x080UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000080 */ +#define ADC_AWD2TR_LT2_8 (0x100UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000100 */ +#define ADC_AWD2TR_LT2_9 (0x200UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000200 */ +#define ADC_AWD2TR_LT2_10 (0x400UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000400 */ +#define ADC_AWD2TR_LT2_11 (0x800UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000800 */ + +#define ADC_AWD2TR_HT2_Pos (16U) +#define ADC_AWD2TR_HT2_Msk (0xFFFUL << ADC_AWD2TR_HT2_Pos) /*!< 0x0FFF0000 */ +#define ADC_AWD2TR_HT2 ADC_AWD2TR_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ +#define ADC_AWD2TR_HT2_0 (0x001UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00010000 */ +#define ADC_AWD2TR_HT2_1 (0x002UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00020000 */ +#define ADC_AWD2TR_HT2_2 (0x004UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00040000 */ +#define ADC_AWD2TR_HT2_3 (0x008UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00080000 */ +#define ADC_AWD2TR_HT2_4 (0x010UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00100000 */ +#define ADC_AWD2TR_HT2_5 (0x020UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00200000 */ +#define ADC_AWD2TR_HT2_6 (0x040UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00400000 */ +#define ADC_AWD2TR_HT2_7 (0x080UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00800000 */ +#define ADC_AWD2TR_HT2_8 (0x100UL << ADC_AWD2TR_HT2_Pos) /*!< 0x01000000 */ +#define ADC_AWD2TR_HT2_9 (0x200UL << ADC_AWD2TR_HT2_Pos) /*!< 0x02000000 */ +#define ADC_AWD2TR_HT2_10 (0x400UL << ADC_AWD2TR_HT2_Pos) /*!< 0x04000000 */ +#define ADC_AWD2TR_HT2_11 (0x800UL << ADC_AWD2TR_HT2_Pos) /*!< 0x08000000 */ + +/* Legacy definitions */ +#define ADC_TR2_LT2 ADC_AWD2TR_LT2 +#define ADC_TR2_LT2_0 ADC_AWD2TR_LT2_0 +#define ADC_TR2_LT2_1 ADC_AWD2TR_LT2_1 +#define ADC_TR2_LT2_2 ADC_AWD2TR_LT2_2 +#define ADC_TR2_LT2_3 ADC_AWD2TR_LT2_3 +#define ADC_TR2_LT2_4 ADC_AWD2TR_LT2_4 +#define ADC_TR2_LT2_5 ADC_AWD2TR_LT2_5 +#define ADC_TR2_LT2_6 ADC_AWD2TR_LT2_6 +#define ADC_TR2_LT2_7 ADC_AWD2TR_LT2_7 +#define ADC_TR2_LT2_8 ADC_AWD2TR_LT2_8 +#define ADC_TR2_LT2_9 ADC_AWD2TR_LT2_9 +#define ADC_TR2_LT2_10 ADC_AWD2TR_LT2_10 +#define ADC_TR2_LT2_11 ADC_AWD2TR_LT2_11 + +#define ADC_TR2_HT2 ADC_AWD2TR_HT2 +#define ADC_TR2_HT2_0 ADC_AWD2TR_HT2_0 +#define ADC_TR2_HT2_1 ADC_AWD2TR_HT2_1 +#define ADC_TR2_HT2_2 ADC_AWD2TR_HT2_2 +#define ADC_TR2_HT2_3 ADC_AWD2TR_HT2_3 +#define ADC_TR2_HT2_4 ADC_AWD2TR_HT2_4 +#define ADC_TR2_HT2_5 ADC_AWD2TR_HT2_5 +#define ADC_TR2_HT2_6 ADC_AWD2TR_HT2_6 +#define ADC_TR2_HT2_7 ADC_AWD2TR_HT2_7 +#define ADC_TR2_HT2_8 ADC_AWD2TR_HT2_8 +#define ADC_TR2_HT2_9 ADC_AWD2TR_HT2_9 +#define ADC_TR2_HT2_10 ADC_AWD2TR_HT2_10 +#define ADC_TR2_HT2_11 ADC_AWD2TR_HT2_11 + +/******************** Bit definition for ADC_CHSELR register ****************/ +#define ADC_CHSELR_CHSEL_Pos (0U) +#define ADC_CHSELR_CHSEL_Msk (0x3FFFFUL << ADC_CHSELR_CHSEL_Pos) /*!< 0x0003FFFF */ +#define ADC_CHSELR_CHSEL ADC_CHSELR_CHSEL_Msk /*!< ADC group regular sequencer channels, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL17_Pos (17U) +#define ADC_CHSELR_CHSEL17_Msk (0x1UL << ADC_CHSELR_CHSEL17_Pos) /*!< 0x00020000 */ +#define ADC_CHSELR_CHSEL17 ADC_CHSELR_CHSEL17_Msk /*!< ADC group regular sequencer channel 17, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL16_Pos (16U) +#define ADC_CHSELR_CHSEL16_Msk (0x1UL << ADC_CHSELR_CHSEL16_Pos) /*!< 0x00010000 */ +#define ADC_CHSELR_CHSEL16 ADC_CHSELR_CHSEL16_Msk /*!< ADC group regular sequencer channel 16, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL15_Pos (15U) +#define ADC_CHSELR_CHSEL15_Msk (0x1UL << ADC_CHSELR_CHSEL15_Pos) /*!< 0x00008000 */ +#define ADC_CHSELR_CHSEL15 ADC_CHSELR_CHSEL15_Msk /*!< ADC group regular sequencer channel 15, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL14_Pos (14U) +#define ADC_CHSELR_CHSEL14_Msk (0x1UL << ADC_CHSELR_CHSEL14_Pos) /*!< 0x00004000 */ +#define ADC_CHSELR_CHSEL14 ADC_CHSELR_CHSEL14_Msk /*!< ADC group regular sequencer channel 14, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL13_Pos (13U) +#define ADC_CHSELR_CHSEL13_Msk (0x1UL << ADC_CHSELR_CHSEL13_Pos) /*!< 0x00002000 */ +#define ADC_CHSELR_CHSEL13 ADC_CHSELR_CHSEL13_Msk /*!< ADC group regular sequencer channel 13, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL12_Pos (12U) +#define ADC_CHSELR_CHSEL12_Msk (0x1UL << ADC_CHSELR_CHSEL12_Pos) /*!< 0x00001000 */ +#define ADC_CHSELR_CHSEL12 ADC_CHSELR_CHSEL12_Msk /*!< ADC group regular sequencer channel 12, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL11_Pos (11U) +#define ADC_CHSELR_CHSEL11_Msk (0x1UL << ADC_CHSELR_CHSEL11_Pos) /*!< 0x00000800 */ +#define ADC_CHSELR_CHSEL11 ADC_CHSELR_CHSEL11_Msk /*!< ADC group regular sequencer channel 11, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL10_Pos (10U) +#define ADC_CHSELR_CHSEL10_Msk (0x1UL << ADC_CHSELR_CHSEL10_Pos) /*!< 0x00000400 */ +#define ADC_CHSELR_CHSEL10 ADC_CHSELR_CHSEL10_Msk /*!< ADC group regular sequencer channel 10, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL9_Pos (9U) +#define ADC_CHSELR_CHSEL9_Msk (0x1UL << ADC_CHSELR_CHSEL9_Pos) /*!< 0x00000200 */ +#define ADC_CHSELR_CHSEL9 ADC_CHSELR_CHSEL9_Msk /*!< ADC group regular sequencer channel 9, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL8_Pos (8U) +#define ADC_CHSELR_CHSEL8_Msk (0x1UL << ADC_CHSELR_CHSEL8_Pos) /*!< 0x00000100 */ +#define ADC_CHSELR_CHSEL8 ADC_CHSELR_CHSEL8_Msk /*!< ADC group regular sequencer channel 8, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL7_Pos (7U) +#define ADC_CHSELR_CHSEL7_Msk (0x1UL << ADC_CHSELR_CHSEL7_Pos) /*!< 0x00000080 */ +#define ADC_CHSELR_CHSEL7 ADC_CHSELR_CHSEL7_Msk /*!< ADC group regular sequencer channel 7, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL6_Pos (6U) +#define ADC_CHSELR_CHSEL6_Msk (0x1UL << ADC_CHSELR_CHSEL6_Pos) /*!< 0x00000040 */ +#define ADC_CHSELR_CHSEL6 ADC_CHSELR_CHSEL6_Msk /*!< ADC group regular sequencer channel 6, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL5_Pos (5U) +#define ADC_CHSELR_CHSEL5_Msk (0x1UL << ADC_CHSELR_CHSEL5_Pos) /*!< 0x00000020 */ +#define ADC_CHSELR_CHSEL5 ADC_CHSELR_CHSEL5_Msk /*!< ADC group regular sequencer channel 5, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL4_Pos (4U) +#define ADC_CHSELR_CHSEL4_Msk (0x1UL << ADC_CHSELR_CHSEL4_Pos) /*!< 0x00000010 */ +#define ADC_CHSELR_CHSEL4 ADC_CHSELR_CHSEL4_Msk /*!< ADC group regular sequencer channel 4, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL3_Pos (3U) +#define ADC_CHSELR_CHSEL3_Msk (0x1UL << ADC_CHSELR_CHSEL3_Pos) /*!< 0x00000008 */ +#define ADC_CHSELR_CHSEL3 ADC_CHSELR_CHSEL3_Msk /*!< ADC group regular sequencer channel 3, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL2_Pos (2U) +#define ADC_CHSELR_CHSEL2_Msk (0x1UL << ADC_CHSELR_CHSEL2_Pos) /*!< 0x00000004 */ +#define ADC_CHSELR_CHSEL2 ADC_CHSELR_CHSEL2_Msk /*!< ADC group regular sequencer channel 2, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL1_Pos (1U) +#define ADC_CHSELR_CHSEL1_Msk (0x1UL << ADC_CHSELR_CHSEL1_Pos) /*!< 0x00000002 */ +#define ADC_CHSELR_CHSEL1 ADC_CHSELR_CHSEL1_Msk /*!< ADC group regular sequencer channel 1, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL0_Pos (0U) +#define ADC_CHSELR_CHSEL0_Msk (0x1UL << ADC_CHSELR_CHSEL0_Pos) /*!< 0x00000001 */ +#define ADC_CHSELR_CHSEL0 ADC_CHSELR_CHSEL0_Msk /*!< ADC group regular sequencer channel 0, available when ADC_CFGR1_CHSELRMOD is reset */ + +#define ADC_CHSELR_SQ_ALL_Pos (0U) +#define ADC_CHSELR_SQ_ALL_Msk (0xFFFFFFFFUL << ADC_CHSELR_SQ_ALL_Pos) /*!< 0xFFFFFFFF */ +#define ADC_CHSELR_SQ_ALL ADC_CHSELR_SQ_ALL_Msk /*!< ADC group regular sequencer all ranks, available when ADC_CFGR1_CHSELRMOD is set */ + +#define ADC_CHSELR_SQ8_Pos (28U) +#define ADC_CHSELR_SQ8_Msk (0xFUL << ADC_CHSELR_SQ8_Pos) /*!< 0xF0000000 */ +#define ADC_CHSELR_SQ8 ADC_CHSELR_SQ8_Msk /*!< ADC group regular sequencer rank 8, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ8_0 (0x1UL << ADC_CHSELR_SQ8_Pos) /*!< 0x10000000 */ +#define ADC_CHSELR_SQ8_1 (0x2UL << ADC_CHSELR_SQ8_Pos) /*!< 0x20000000 */ +#define ADC_CHSELR_SQ8_2 (0x4UL << ADC_CHSELR_SQ8_Pos) /*!< 0x40000000 */ +#define ADC_CHSELR_SQ8_3 (0x8UL << ADC_CHSELR_SQ8_Pos) /*!< 0x80000000 */ + +#define ADC_CHSELR_SQ7_Pos (24U) +#define ADC_CHSELR_SQ7_Msk (0xFUL << ADC_CHSELR_SQ7_Pos) /*!< 0x0F000000 */ +#define ADC_CHSELR_SQ7 ADC_CHSELR_SQ7_Msk /*!< ADC group regular sequencer rank 7, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ7_0 (0x1UL << ADC_CHSELR_SQ7_Pos) /*!< 0x01000000 */ +#define ADC_CHSELR_SQ7_1 (0x2UL << ADC_CHSELR_SQ7_Pos) /*!< 0x02000000 */ +#define ADC_CHSELR_SQ7_2 (0x4UL << ADC_CHSELR_SQ7_Pos) /*!< 0x04000000 */ +#define ADC_CHSELR_SQ7_3 (0x8UL << ADC_CHSELR_SQ7_Pos) /*!< 0x08000000 */ + +#define ADC_CHSELR_SQ6_Pos (20U) +#define ADC_CHSELR_SQ6_Msk (0xFUL << ADC_CHSELR_SQ6_Pos) /*!< 0x00F00000 */ +#define ADC_CHSELR_SQ6 ADC_CHSELR_SQ6_Msk /*!< ADC group regular sequencer rank 6, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ6_0 (0x1UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00100000 */ +#define ADC_CHSELR_SQ6_1 (0x2UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00200000 */ +#define ADC_CHSELR_SQ6_2 (0x4UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00400000 */ +#define ADC_CHSELR_SQ6_3 (0x8UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00800000 */ + +#define ADC_CHSELR_SQ5_Pos (16U) +#define ADC_CHSELR_SQ5_Msk (0xFUL << ADC_CHSELR_SQ5_Pos) /*!< 0x000F0000 */ +#define ADC_CHSELR_SQ5 ADC_CHSELR_SQ5_Msk /*!< ADC group regular sequencer rank 5, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ5_0 (0x1UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00010000 */ +#define ADC_CHSELR_SQ5_1 (0x2UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00020000 */ +#define ADC_CHSELR_SQ5_2 (0x4UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_SQ5_3 (0x8UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00080000 */ + +#define ADC_CHSELR_SQ4_Pos (12U) +#define ADC_CHSELR_SQ4_Msk (0xFUL << ADC_CHSELR_SQ4_Pos) /*!< 0x0000F000 */ +#define ADC_CHSELR_SQ4 ADC_CHSELR_SQ4_Msk /*!< ADC group regular sequencer rank 4, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ4_0 (0x1UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00001000 */ +#define ADC_CHSELR_SQ4_1 (0x2UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00002000 */ +#define ADC_CHSELR_SQ4_2 (0x4UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00004000 */ +#define ADC_CHSELR_SQ4_3 (0x8UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00008000 */ + +#define ADC_CHSELR_SQ3_Pos (8U) +#define ADC_CHSELR_SQ3_Msk (0xFUL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000F00 */ +#define ADC_CHSELR_SQ3 ADC_CHSELR_SQ3_Msk /*!< ADC group regular sequencer rank 3, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ3_0 (0x1UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000100 */ +#define ADC_CHSELR_SQ3_1 (0x2UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000200 */ +#define ADC_CHSELR_SQ3_2 (0x4UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000400 */ +#define ADC_CHSELR_SQ3_3 (0x8UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000800 */ + +#define ADC_CHSELR_SQ2_Pos (4U) +#define ADC_CHSELR_SQ2_Msk (0xFUL << ADC_CHSELR_SQ2_Pos) /*!< 0x000000F0 */ +#define ADC_CHSELR_SQ2 ADC_CHSELR_SQ2_Msk /*!< ADC group regular sequencer rank 2, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ2_0 (0x1UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000010 */ +#define ADC_CHSELR_SQ2_1 (0x2UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000020 */ +#define ADC_CHSELR_SQ2_2 (0x4UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000040 */ +#define ADC_CHSELR_SQ2_3 (0x8UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000080 */ + +#define ADC_CHSELR_SQ1_Pos (0U) +#define ADC_CHSELR_SQ1_Msk (0xFUL << ADC_CHSELR_SQ1_Pos) /*!< 0x0000000F */ +#define ADC_CHSELR_SQ1 ADC_CHSELR_SQ1_Msk /*!< ADC group regular sequencer rank 1, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ1_0 (0x1UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000001 */ +#define ADC_CHSELR_SQ1_1 (0x2UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000002 */ +#define ADC_CHSELR_SQ1_2 (0x4UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000004 */ +#define ADC_CHSELR_SQ1_3 (0x8UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000008 */ + +/******************** Bit definition for ADC_AWD3TR register *******************/ +#define ADC_AWD3TR_LT3_Pos (0U) +#define ADC_AWD3TR_LT3_Msk (0xFFFUL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000FFF */ +#define ADC_AWD3TR_LT3 ADC_AWD3TR_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ +#define ADC_AWD3TR_LT3_0 (0x001UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000001 */ +#define ADC_AWD3TR_LT3_1 (0x002UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000002 */ +#define ADC_AWD3TR_LT3_2 (0x004UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000004 */ +#define ADC_AWD3TR_LT3_3 (0x008UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000008 */ +#define ADC_AWD3TR_LT3_4 (0x010UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000010 */ +#define ADC_AWD3TR_LT3_5 (0x020UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000020 */ +#define ADC_AWD3TR_LT3_6 (0x040UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000040 */ +#define ADC_AWD3TR_LT3_7 (0x080UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000080 */ +#define ADC_AWD3TR_LT3_8 (0x100UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000100 */ +#define ADC_AWD3TR_LT3_9 (0x200UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000200 */ +#define ADC_AWD3TR_LT3_10 (0x400UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000400 */ +#define ADC_AWD3TR_LT3_11 (0x800UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000800 */ + +#define ADC_AWD3TR_HT3_Pos (16U) +#define ADC_AWD3TR_HT3_Msk (0xFFFUL << ADC_AWD3TR_HT3_Pos) /*!< 0x0FFF0000 */ +#define ADC_AWD3TR_HT3 ADC_AWD3TR_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ +#define ADC_AWD3TR_HT3_0 (0x001UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00010000 */ +#define ADC_AWD3TR_HT3_1 (0x002UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00020000 */ +#define ADC_AWD3TR_HT3_2 (0x004UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00040000 */ +#define ADC_AWD3TR_HT3_3 (0x008UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00080000 */ +#define ADC_AWD3TR_HT3_4 (0x010UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00100000 */ +#define ADC_AWD3TR_HT3_5 (0x020UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00200000 */ +#define ADC_AWD3TR_HT3_6 (0x040UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00400000 */ +#define ADC_AWD3TR_HT3_7 (0x080UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00800000 */ +#define ADC_AWD3TR_HT3_8 (0x100UL << ADC_AWD3TR_HT3_Pos) /*!< 0x01000000 */ +#define ADC_AWD3TR_HT3_9 (0x200UL << ADC_AWD3TR_HT3_Pos) /*!< 0x02000000 */ +#define ADC_AWD3TR_HT3_10 (0x400UL << ADC_AWD3TR_HT3_Pos) /*!< 0x04000000 */ +#define ADC_AWD3TR_HT3_11 (0x800UL << ADC_AWD3TR_HT3_Pos) /*!< 0x08000000 */ + +/* Legacy definitions */ +#define ADC_TR3_LT3 ADC_AWD3TR_LT3 +#define ADC_TR3_LT3_0 ADC_AWD3TR_LT3_0 +#define ADC_TR3_LT3_1 ADC_AWD3TR_LT3_1 +#define ADC_TR3_LT3_2 ADC_AWD3TR_LT3_2 +#define ADC_TR3_LT3_3 ADC_AWD3TR_LT3_3 +#define ADC_TR3_LT3_4 ADC_AWD3TR_LT3_4 +#define ADC_TR3_LT3_5 ADC_AWD3TR_LT3_5 +#define ADC_TR3_LT3_6 ADC_AWD3TR_LT3_6 +#define ADC_TR3_LT3_7 ADC_AWD3TR_LT3_7 +#define ADC_TR3_LT3_8 ADC_AWD3TR_LT3_8 +#define ADC_TR3_LT3_9 ADC_AWD3TR_LT3_9 +#define ADC_TR3_LT3_10 ADC_AWD3TR_LT3_10 +#define ADC_TR3_LT3_11 ADC_AWD3TR_LT3_11 + +#define ADC_TR3_HT3 ADC_AWD3TR_HT3 +#define ADC_TR3_HT3_0 ADC_AWD3TR_HT3_0 +#define ADC_TR3_HT3_1 ADC_AWD3TR_HT3_1 +#define ADC_TR3_HT3_2 ADC_AWD3TR_HT3_2 +#define ADC_TR3_HT3_3 ADC_AWD3TR_HT3_3 +#define ADC_TR3_HT3_4 ADC_AWD3TR_HT3_4 +#define ADC_TR3_HT3_5 ADC_AWD3TR_HT3_5 +#define ADC_TR3_HT3_6 ADC_AWD3TR_HT3_6 +#define ADC_TR3_HT3_7 ADC_AWD3TR_HT3_7 +#define ADC_TR3_HT3_8 ADC_AWD3TR_HT3_8 +#define ADC_TR3_HT3_9 ADC_AWD3TR_HT3_9 +#define ADC_TR3_HT3_10 ADC_AWD3TR_HT3_10 +#define ADC_TR3_HT3_11 ADC_AWD3TR_HT3_11 +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_DATA_Pos (0U) +#define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */ +#define ADC_DR_DATA ADC_DR_DATA_Msk /*!< ADC group regular conversion data */ +#define ADC_DR_DATA_0 (0x0001UL << ADC_DR_DATA_Pos) /*!< 0x00000001 */ +#define ADC_DR_DATA_1 (0x0002UL << ADC_DR_DATA_Pos) /*!< 0x00000002 */ +#define ADC_DR_DATA_2 (0x0004UL << ADC_DR_DATA_Pos) /*!< 0x00000004 */ +#define ADC_DR_DATA_3 (0x0008UL << ADC_DR_DATA_Pos) /*!< 0x00000008 */ +#define ADC_DR_DATA_4 (0x0010UL << ADC_DR_DATA_Pos) /*!< 0x00000010 */ +#define ADC_DR_DATA_5 (0x0020UL << ADC_DR_DATA_Pos) /*!< 0x00000020 */ +#define ADC_DR_DATA_6 (0x0040UL << ADC_DR_DATA_Pos) /*!< 0x00000040 */ +#define ADC_DR_DATA_7 (0x0080UL << ADC_DR_DATA_Pos) /*!< 0x00000080 */ +#define ADC_DR_DATA_8 (0x0100UL << ADC_DR_DATA_Pos) /*!< 0x00000100 */ +#define ADC_DR_DATA_9 (0x0200UL << ADC_DR_DATA_Pos) /*!< 0x00000200 */ +#define ADC_DR_DATA_10 (0x0400UL << ADC_DR_DATA_Pos) /*!< 0x00000400 */ +#define ADC_DR_DATA_11 (0x0800UL << ADC_DR_DATA_Pos) /*!< 0x00000800 */ +#define ADC_DR_DATA_12 (0x1000UL << ADC_DR_DATA_Pos) /*!< 0x00001000 */ +#define ADC_DR_DATA_13 (0x2000UL << ADC_DR_DATA_Pos) /*!< 0x00002000 */ +#define ADC_DR_DATA_14 (0x4000UL << ADC_DR_DATA_Pos) /*!< 0x00004000 */ +#define ADC_DR_DATA_15 (0x8000UL << ADC_DR_DATA_Pos) /*!< 0x00008000 */ + +/******************** Bit definition for ADC_AWD2CR register ****************/ +#define ADC_AWD2CR_AWD2CH_Pos (0U) +#define ADC_AWD2CR_AWD2CH_Msk (0x3FFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0003FFFF */ +#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */ +#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ + +/******************** Bit definition for ADC_AWD3CR register ****************/ +#define ADC_AWD3CR_AWD3CH_Pos (0U) +#define ADC_AWD3CR_AWD3CH_Msk (0x3FFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0003FFFF */ +#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */ +#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ + +/******************** Bit definition for ADC_CALFACT register ***************/ +#define ADC_CALFACT_CALFACT_Pos (0U) +#define ADC_CALFACT_CALFACT_Msk (0x7FUL << ADC_CALFACT_CALFACT_Pos) /*!< 0x0000007F */ +#define ADC_CALFACT_CALFACT ADC_CALFACT_CALFACT_Msk /*!< ADC calibration factor in single-ended mode */ +#define ADC_CALFACT_CALFACT_0 (0x01UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_CALFACT_1 (0x02UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_CALFACT_2 (0x04UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_CALFACT_3 (0x08UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_CALFACT_4 (0x10UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_CALFACT_5 (0x20UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_CALFACT_6 (0x40UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000040 */ + +/************************* ADC Common registers *****************************/ +/******************** Bit definition for ADC_CCR register *******************/ +#define ADC_CCR_PRESC_Pos (18U) +#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ +#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */ +#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ +#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ +#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ +#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ + +#define ADC_CCR_VREFEN_Pos (22U) +#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */ +#define ADC_CCR_TSEN_Pos (23U) +#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */ +#define ADC_CCR_VBATEN_Pos (24U) +#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ +#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */ + +/******************************************************************************/ +/* */ +/* Analog Comparators (COMP) */ +/* */ +/******************************************************************************/ +/********************** Bit definition for COMP_CSR register ****************/ +#define COMP_CSR_EN_Pos (0U) +#define COMP_CSR_EN_Msk (0x1UL << COMP_CSR_EN_Pos) /*!< 0x00000001 */ +#define COMP_CSR_EN COMP_CSR_EN_Msk /*!< Comparator enable */ + +#define COMP_CSR_PWRMODE_Pos (2U) +#define COMP_CSR_PWRMODE_Msk (0x3UL << COMP_CSR_PWRMODE_Pos) /*!< 0x0000000C */ +#define COMP_CSR_PWRMODE COMP_CSR_PWRMODE_Msk /*!< Comparator power mode */ +#define COMP_CSR_PWRMODE_0 (0x1UL << COMP_CSR_PWRMODE_Pos) /*!< 0x00000004 */ +#define COMP_CSR_PWRMODE_1 (0x2UL << COMP_CSR_PWRMODE_Pos) /*!< 0x00000008 */ + +#define COMP_CSR_INMSEL_Pos (4U) +#define COMP_CSR_INMSEL_Msk (0x7UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000070 */ +#define COMP_CSR_INMSEL COMP_CSR_INMSEL_Msk /*!< Comparator input minus selection */ +#define COMP_CSR_INMSEL_0 (0x1UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000010 */ +#define COMP_CSR_INMSEL_1 (0x2UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000020 */ +#define COMP_CSR_INMSEL_2 (0x4UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000040 */ + +#define COMP_CSR_INPSEL_Pos (7U) +#define COMP_CSR_INPSEL_Msk (0x3UL << COMP_CSR_INPSEL_Pos) /*!< 0x00000180 */ +#define COMP_CSR_INPSEL COMP_CSR_INPSEL_Msk /*!< Comparator input plus selection */ +#define COMP_CSR_INPSEL_0 (0x1UL << COMP_CSR_INPSEL_Pos) /*!< 0x00000080 */ +#define COMP_CSR_INPSEL_1 (0x2UL << COMP_CSR_INPSEL_Pos) /*!< 0x00000100 */ + +#define COMP_CSR_WINMODE_Pos (9U) +#define COMP_CSR_WINMODE_Msk (0x1UL << COMP_CSR_WINMODE_Pos) /*!< 0x00000200 */ +#define COMP_CSR_WINMODE COMP_CSR_WINMODE_Msk /*!< Pair of comparators window mode. Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */ + +#define COMP_CSR_POLARITY_Pos (15U) +#define COMP_CSR_POLARITY_Msk (0x1UL << COMP_CSR_POLARITY_Pos) /*!< 0x00008000 */ +#define COMP_CSR_POLARITY COMP_CSR_POLARITY_Msk /*!< Comparator output polarity */ + +#define COMP_CSR_HYST_Pos (16U) +#define COMP_CSR_HYST_Msk (0x3UL << COMP_CSR_HYST_Pos) /*!< 0x00030000 */ +#define COMP_CSR_HYST COMP_CSR_HYST_Msk /*!< Comparator hysteresis */ +#define COMP_CSR_HYST_0 (0x1UL << COMP_CSR_HYST_Pos) /*!< 0x00010000 */ +#define COMP_CSR_HYST_1 (0x2UL << COMP_CSR_HYST_Pos) /*!< 0x00020000 */ + +#define COMP_CSR_BLANKING_Pos (18U) +#define COMP_CSR_BLANKING_Msk (0x7UL << COMP_CSR_BLANKING_Pos) /*!< 0x001C0000 */ +#define COMP_CSR_BLANKING COMP_CSR_BLANKING_Msk /*!< Comparator blanking source */ +#define COMP_CSR_BLANKING_0 (0x1UL << COMP_CSR_BLANKING_Pos) /*!< 0x00040000 */ +#define COMP_CSR_BLANKING_1 (0x2UL << COMP_CSR_BLANKING_Pos) /*!< 0x00080000 */ +#define COMP_CSR_BLANKING_2 (0x4UL << COMP_CSR_BLANKING_Pos) /*!< 0x00100000 */ + +#define COMP_CSR_BRGEN_Pos (22U) +#define COMP_CSR_BRGEN_Msk (0x1UL << COMP_CSR_BRGEN_Pos) /*!< 0x00400000 */ +#define COMP_CSR_BRGEN COMP_CSR_BRGEN_Msk /*!< Comparator voltage scaler enable */ +#define COMP_CSR_SCALEN_Pos (23U) +#define COMP_CSR_SCALEN_Msk (0x1UL << COMP_CSR_SCALEN_Pos) /*!< 0x00800000 */ +#define COMP_CSR_SCALEN COMP_CSR_SCALEN_Msk /*!< Comparator scaler bridge enable */ + +#define COMP_CSR_INMESEL_Pos (25U) +#define COMP_CSR_INMESEL_Msk (0x3UL << COMP_CSR_INMESEL_Pos) /*!< 0x06000000 */ +#define COMP_CSR_INMESEL COMP_CSR_INMESEL_Msk /*!< Comparator input minus extended selection */ +#define COMP_CSR_INMESEL_0 (0x1UL << COMP_CSR_INMESEL_Pos) /*!< 0x02000000 */ +#define COMP_CSR_INMESEL_1 (0x2UL << COMP_CSR_INMESEL_Pos) /*!< 0x04000000 */ + +#define COMP_CSR_VALUE_Pos (30U) +#define COMP_CSR_VALUE_Msk (0x1UL << COMP_CSR_VALUE_Pos) /*!< 0x40000000 */ +#define COMP_CSR_VALUE COMP_CSR_VALUE_Msk /*!< Comparator output level */ + +#define COMP_CSR_LOCK_Pos (31U) +#define COMP_CSR_LOCK_Msk (0x1UL << COMP_CSR_LOCK_Pos) /*!< 0x80000000 */ +#define COMP_CSR_LOCK COMP_CSR_LOCK_Msk /*!< Comparator lock */ + +/******************************************************************************/ +/* */ +/* Digital to Analog Converter */ +/* */ +/******************************************************************************/ +/* +* @brief Specific device feature definitions +*/ + +/******************** Bit definition for DAC_CR register ********************/ +#define DAC_CR_EN1_Pos (0U) +#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */ +#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!*/ +#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ + +/***************** Bit definition for DAC_SWTRIGR register ******************/ +#define DAC_SWTRIGR_SWTRIG1_Pos (0U) +#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ +#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!>2) /*!< Input modulus number of bits */ +#define PKA_MONTGOMERY_PARAM_IN_MODULUS ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Compute Montgomery parameter output data */ +#define PKA_MONTGOMERY_PARAM_OUT_PARAMETER ((0x594U - PKA_RAM_OFFSET)>>2) /*!< Output Montgomery parameter */ + +/* Compute modular exponentiation input data */ +#define PKA_MODULAR_EXP_IN_EXP_NB_BITS ((0x400U - PKA_RAM_OFFSET)>>2) /*!< Input exponent number of bits */ +#define PKA_MODULAR_EXP_IN_OP_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM ((0x594U - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ +#define PKA_MODULAR_EXP_IN_EXPONENT_BASE ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */ +#define PKA_MODULAR_EXP_IN_EXPONENT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Input exponent to process */ +#define PKA_MODULAR_EXP_IN_MODULUS ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Compute modular exponentiation output data */ +#define PKA_MODULAR_EXP_OUT_MONTGOMERY_PARAM ((0x594U - PKA_RAM_OFFSET)>>2) /*!< Output storage area for Montgomery parameter */ +#define PKA_MODULAR_EXP_OUT_SM_ALGO_ACC1 ((0x724U - PKA_RAM_OFFSET)>>2) /*!< Output SM algorithm accumulator 1 */ +#define PKA_MODULAR_EXP_OUT_SM_ALGO_ACC2 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Output SM algorithm accumulator 2 */ +#define PKA_MODULAR_EXP_OUT_EXPONENT_BASE ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Output base of the exponentiation */ +#define PKA_MODULAR_EXP_OUT_SM_ALGO_ACC3 ((0xE3CU - PKA_RAM_OFFSET)>>2) /*!< Output SM algorithm accumulator 3 */ + +/* Compute ECC scalar multiplication input data */ +#define PKA_ECC_SCALAR_MUL_IN_EXP_NB_BITS ((0x400U - PKA_RAM_OFFSET)>>2) /*!< Input exponent number of bits */ +#define PKA_ECC_SCALAR_MUL_IN_OP_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ECC_SCALAR_MUL_IN_A_COEFF_SIGN ((0x408U - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_A_COEFF ((0x40CU - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_MOD_GF ((0x460U - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_SCALAR_MUL_IN_MONTGOMERY_PARAM ((0x4B4U - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ +#define PKA_ECC_SCALAR_MUL_IN_K ((0x508U - PKA_RAM_OFFSET)>>2) /*!< Input 'k' of KP */ +#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X ((0x55CU - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y ((0x5B0U - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ + +/* Compute ECC scalar multiplication output data */ +#define PKA_ECC_SCALAR_MUL_OUT_RESULT_X ((0x55CU - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_RESULT_Y ((0x5B0U - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_LAST_DOUBLE_X1 ((0xDE8U - PKA_RAM_OFFSET)>>2) /*!< Output last double X1 coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_LAST_DOUBLE_Y1 ((0xE3CU - PKA_RAM_OFFSET)>>2) /*!< Output last double Y1 coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_LAST_DOUBLE_Z1 ((0xE90U - PKA_RAM_OFFSET)>>2) /*!< Output last double Z1 coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_CHECK_POINT_X2 ((0xEE4U - PKA_RAM_OFFSET)>>2) /*!< Output check point X2 coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_CHECK_POINT_Y2 ((0xF38U - PKA_RAM_OFFSET)>>2) /*!< Output check point Y2 coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_CHECK_POINT_Z2 ((0xF8CU - PKA_RAM_OFFSET)>>2) /*!< Output check point Z2 coordinate */ + +/* Point check input data */ +#define PKA_POINT_CHECK_IN_MOD_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_POINT_CHECK_IN_A_COEFF_SIGN ((0x408U - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_POINT_CHECK_IN_A_COEFF ((0x40CU - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_POINT_CHECK_IN_B_COEFF ((0x7FCU - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_POINT_CHECK_IN_MOD_GF ((0x460U - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_POINT_CHECK_IN_INITIAL_POINT_X ((0x55CU - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_POINT_CHECK_IN_INITIAL_POINT_Y ((0x5B0U - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ + +/* Point check output data */ +#define PKA_POINT_CHECK_OUT_ERROR ((0x400U - PKA_RAM_OFFSET)>>2) /*!< Output error */ + +/* ECDSA signature input data */ +#define PKA_ECDSA_SIGN_IN_ORDER_NB_BITS ((0x400U - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */ +#define PKA_ECDSA_SIGN_IN_MOD_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECDSA_SIGN_IN_A_COEFF_SIGN ((0x408U - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECDSA_SIGN_IN_A_COEFF ((0x40CU - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECDSA_SIGN_IN_MOD_GF ((0x460U - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECDSA_SIGN_IN_K ((0x508U - PKA_RAM_OFFSET)>>2) /*!< Input k value of the ECDSA */ +#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_X ((0x55CU - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_Y ((0x5B0U - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECDSA_SIGN_IN_HASH_E ((0xDE8U - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */ +#define PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D ((0xE3CU - PKA_RAM_OFFSET)>>2) /*!< Input d, private key */ +#define PKA_ECDSA_SIGN_IN_ORDER_N ((0xE94U - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ + +/* ECDSA signature output data */ +#define PKA_ECDSA_SIGN_OUT_ERROR ((0xEE8U - PKA_RAM_OFFSET)>>2) /*!< Output error */ +#define PKA_ECDSA_SIGN_OUT_SIGNATURE_R ((0x700U - PKA_RAM_OFFSET)>>2) /*!< Output signature r */ +#define PKA_ECDSA_SIGN_OUT_SIGNATURE_S ((0x754U - PKA_RAM_OFFSET)>>2) /*!< Output signature s */ +#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_X ((0x103CU - PKA_RAM_OFFSET)>>2) /*!< Output final point kP X coordinate */ +#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_Y ((0x1090U - PKA_RAM_OFFSET)>>2) /*!< Output final point kP Y coordinate */ + +/* ECDSA verification input data */ +#define PKA_ECDSA_VERIF_IN_ORDER_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */ +#define PKA_ECDSA_VERIF_IN_MOD_NB_BITS ((0x4B4U - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECDSA_VERIF_IN_A_COEFF_SIGN ((0x45CU - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECDSA_VERIF_IN_A_COEFF ((0x460U - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECDSA_VERIF_IN_MOD_GF ((0x4B8U - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_X ((0x5E8U - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_Y ((0x63CU - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_X ((0xF40U - PKA_RAM_OFFSET)>>2) /*!< Input public key point X coordinate */ +#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_Y ((0xF94U - PKA_RAM_OFFSET)>>2) /*!< Input public key point Y coordinate */ +#define PKA_ECDSA_VERIF_IN_SIGNATURE_R ((0x1098U - PKA_RAM_OFFSET)>>2) /*!< Input r, part of the signature */ +#define PKA_ECDSA_VERIF_IN_SIGNATURE_S ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input s, part of the signature */ +#define PKA_ECDSA_VERIF_IN_HASH_E ((0xFE8U - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */ +#define PKA_ECDSA_VERIF_IN_ORDER_N ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ + +/* ECDSA verification output data */ +#define PKA_ECDSA_VERIF_OUT_RESULT ((0x5B0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* RSA CRT exponentiation input data */ +#define PKA_RSA_CRT_EXP_IN_MOD_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operands number of bits */ +#define PKA_RSA_CRT_EXP_IN_DP_CRT ((0x65CU - PKA_RAM_OFFSET)>>2) /*!< Input Dp CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_DQ_CRT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Input Dq CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_QINV_CRT ((0x7ECU - PKA_RAM_OFFSET)>>2) /*!< Input qInv CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_PRIME_P ((0x97CU - PKA_RAM_OFFSET)>>2) /*!< Input Prime p */ +#define PKA_RSA_CRT_EXP_IN_PRIME_Q ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input Prime q */ +#define PKA_RSA_CRT_EXP_IN_EXPONENT_BASE ((0xEECU - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */ + +/* RSA CRT exponentiation output data */ +#define PKA_RSA_CRT_EXP_OUT_RESULT ((0x724U - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular reduction input data */ +#define PKA_MODULAR_REDUC_IN_OP_LENGTH ((0x400U - PKA_RAM_OFFSET)>>2) /*!< Input operand length */ +#define PKA_MODULAR_REDUC_IN_OPERAND ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand */ +#define PKA_MODULAR_REDUC_IN_MOD_LENGTH ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input modulus length */ +#define PKA_MODULAR_REDUC_IN_MODULUS ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Modular reduction output data */ +#define PKA_MODULAR_REDUC_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic addition input data */ +#define PKA_ARITHMETIC_ADD_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_ADD_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_ADD_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic addition output data */ +#define PKA_ARITHMETIC_ADD_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic subtraction input data */ +#define PKA_ARITHMETIC_SUB_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_SUB_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_SUB_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic subtraction output data */ +#define PKA_ARITHMETIC_SUB_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic multiplication input data */ +#define PKA_ARITHMETIC_MUL_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_MUL_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_MUL_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic multiplication output data */ +#define PKA_ARITHMETIC_MUL_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Comparison input data */ +#define PKA_COMPARISON_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_COMPARISON_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_COMPARISON_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Comparison output data */ +#define PKA_COMPARISON_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular addition input data */ +#define PKA_MODULAR_ADD_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_ADD_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_ADD_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MODULAR_ADD_IN_OP3_MOD ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 (modulus) */ + +/* Modular addition output data */ +#define PKA_MODULAR_ADD_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular inversion input data */ +#define PKA_MODULAR_INV_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_INV_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_INV_IN_OP2_MOD ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 (modulus) */ + +/* Modular inversion output data */ +#define PKA_MODULAR_INV_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular subtraction input data */ +#define PKA_MODULAR_SUB_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_SUB_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_SUB_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MODULAR_SUB_IN_OP3_MOD ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 */ + +/* Modular subtraction output data */ +#define PKA_MODULAR_SUB_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Montgomery multiplication input data */ +#define PKA_MONTGOMERY_MUL_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MONTGOMERY_MUL_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MONTGOMERY_MUL_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MONTGOMERY_MUL_IN_OP3_MOD ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Montgomery multiplication output data */ +#define PKA_MONTGOMERY_MUL_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Generic Arithmetic input data */ +#define PKA_ARITHMETIC_ALL_OPS_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP3 ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Generic Arithmetic output data */ +#define PKA_ARITHMETIC_ALL_OPS_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/******************************************************************************/ +/* */ +/* Power Control */ +/* */ +/******************************************************************************/ + +/******************** Bit definition for PWR_CR1 register ********************/ +#define PWR_CR1_LPMS_Pos (0U) +#define PWR_CR1_LPMS_Msk (0x7UL << PWR_CR1_LPMS_Pos) /*!< 0x00000007 */ +#define PWR_CR1_LPMS PWR_CR1_LPMS_Msk /*!< Low Power Mode Selection for CPU1 */ +#define PWR_CR1_LPMS_0 (0x1UL << PWR_CR1_LPMS_Pos) /*!< 0x00000001 */ +#define PWR_CR1_LPMS_1 (0x2UL << PWR_CR1_LPMS_Pos) /*!< 0x00000002 */ +#define PWR_CR1_LPMS_2 (0x4UL << PWR_CR1_LPMS_Pos) /*!< 0x00000004 */ + +#define PWR_CR1_SUBGHZSPINSSSEL_Pos (3U) +#define PWR_CR1_SUBGHZSPINSSSEL_Msk (0x1UL << PWR_CR1_SUBGHZSPINSSSEL_Pos) /*!< 0x00000008 */ +#define PWR_CR1_SUBGHZSPINSSSEL PWR_CR1_SUBGHZSPINSSSEL_Msk /*!< Sub-GHz radio SPI NSS source select */ + +#define PWR_CR1_FPDR_Pos (4U) +#define PWR_CR1_FPDR_Msk (0x1UL << PWR_CR1_FPDR_Pos) /*!< 0x00000010 */ +#define PWR_CR1_FPDR PWR_CR1_FPDR_Msk /*!< Flash power down mode during LPrun for CPU1 */ + +#define PWR_CR1_FPDS_Pos (5U) +#define PWR_CR1_FPDS_Msk (0x1UL << PWR_CR1_FPDS_Pos) /*!< 0x00000020 */ +#define PWR_CR1_FPDS PWR_CR1_FPDS_Msk /*!< Flash power down mode during LPsleep for CPU1 */ + +#define PWR_CR1_DBP_Pos (8U) +#define PWR_CR1_DBP_Msk (0x1UL << PWR_CR1_DBP_Pos) /*!< 0x00000100 */ +#define PWR_CR1_DBP PWR_CR1_DBP_Msk /*!< Disable Backup Domain write protection */ + +#define PWR_CR1_VOS_Pos (9U) +#define PWR_CR1_VOS_Msk (0x3UL << PWR_CR1_VOS_Pos) /*!< 0x00000600 */ +#define PWR_CR1_VOS PWR_CR1_VOS_Msk /*!< Voltage scaling range selection */ +#define PWR_CR1_VOS_0 (0x1UL << PWR_CR1_VOS_Pos) /*!< 0x00000200 */ +#define PWR_CR1_VOS_1 (0x2UL << PWR_CR1_VOS_Pos) /*!< 0x00000400 */ + +#define PWR_CR1_LPR_Pos (14U) +#define PWR_CR1_LPR_Msk (0x1UL << PWR_CR1_LPR_Pos) /*!< 0x00004000 */ +#define PWR_CR1_LPR PWR_CR1_LPR_Msk /*!< Regulator Low-Power Run mode */ + +/******************** Bit definition for PWR_CR2 register ********************/ +#define PWR_CR2_PVDE_Pos (0U) +#define PWR_CR2_PVDE_Msk (0x1UL << PWR_CR2_PVDE_Pos) /*!< 0x00000001 */ +#define PWR_CR2_PVDE PWR_CR2_PVDE_Msk /*!< Power voltage detector enable */ + +#define PWR_CR2_PLS_Pos (1U) +#define PWR_CR2_PLS_Msk (0x7UL << PWR_CR2_PLS_Pos) /*!< 0x0000000E */ +#define PWR_CR2_PLS PWR_CR2_PLS_Msk /*!< Power voltage detector level selection */ +#define PWR_CR2_PLS_0 (0x1UL << PWR_CR2_PLS_Pos) /*!< 0x00000002 */ +#define PWR_CR2_PLS_1 (0x2UL << PWR_CR2_PLS_Pos) /*!< 0x00000004 */ +#define PWR_CR2_PLS_2 (0x4UL << PWR_CR2_PLS_Pos) /*!< 0x00000008 */ + +#define PWR_CR2_PVME3_Pos (6U) +#define PWR_CR2_PVME3_Msk (0x1UL << PWR_CR2_PVME3_Pos) /*!< 0x00000040 */ +#define PWR_CR2_PVME3 PWR_CR2_PVME3_Msk /*!< Peripherical Voltage Monitor Vdda Enable */ + +/******************** Bit definition for PWR_CR3 register ********************/ +#define PWR_CR3_EWUP_Pos (0U) +#define PWR_CR3_EWUP_Msk (0x07UL << PWR_CR3_EWUP_Pos) /*!< 0x00000007 */ +#define PWR_CR3_EWUP PWR_CR3_EWUP_Msk /*!< Enable all external Wake-Up lines */ +#define PWR_CR3_EWUP1_Pos (0U) +#define PWR_CR3_EWUP1_Msk (0x1UL << PWR_CR3_EWUP1_Pos) /*!< 0x00000001 */ +#define PWR_CR3_EWUP1 PWR_CR3_EWUP1_Msk /*!< Enable external WKUP Pin 1 [line 0] */ +#define PWR_CR3_EWUP2_Pos (1U) +#define PWR_CR3_EWUP2_Msk (0x1UL << PWR_CR3_EWUP2_Pos) /*!< 0x00000002 */ +#define PWR_CR3_EWUP2 PWR_CR3_EWUP2_Msk /*!< Enable external WKUP Pin 2 [line 1] */ +#define PWR_CR3_EWUP3_Pos (2U) +#define PWR_CR3_EWUP3_Msk (0x1UL << PWR_CR3_EWUP3_Pos) /*!< 0x00000004 */ +#define PWR_CR3_EWUP3 PWR_CR3_EWUP3_Msk /*!< Enable external WKUP Pin 3 [line 2] */ + +#define PWR_CR3_ULPEN_Pos (7U) +#define PWR_CR3_ULPEN_Msk (0x1UL << PWR_CR3_ULPEN_Pos) /*!< 0x00000080 */ +#define PWR_CR3_ULPEN PWR_CR3_ULPEN_Msk /*!< Enable periodical sampling of supply voltage in Stop and Standby modes for detecting condition of PDR and BOR reset */ + +#define PWR_CR3_EWPVD_Pos (8U) +#define PWR_CR3_EWPVD_Msk (0x1UL << PWR_CR3_EWPVD_Pos) /*!< 0x00000100 */ +#define PWR_CR3_EWPVD PWR_CR3_EWPVD_Msk /*!< Enable wakeup PVD for CPU1 */ + +#define PWR_CR3_RRS_Pos (9U) +#define PWR_CR3_RRS_Msk (0x1UL << PWR_CR3_RRS_Pos) /*!< 0x00000200 */ +#define PWR_CR3_RRS PWR_CR3_RRS_Msk /*!< SRAM2 retention in STANDBY mode */ + +#define PWR_CR3_APC_Pos (10U) +#define PWR_CR3_APC_Msk (0x1UL << PWR_CR3_APC_Pos) /*!< 0x00000400 */ +#define PWR_CR3_APC PWR_CR3_APC_Msk /*!< Apply pull-up and pull-down configuration for CPU1 */ + +#define PWR_CR3_EWRFBUSY_Pos (11U) +#define PWR_CR3_EWRFBUSY_Msk (0x1UL << PWR_CR3_EWRFBUSY_Pos) /*!< 0x00008000 */ +#define PWR_CR3_EWRFBUSY PWR_CR3_EWRFBUSY_Msk /*!< Enable Radio busy IRQ and wake-up for CPU1 */ +#define PWR_CR3_EWRFIRQ_Pos (13U) +#define PWR_CR3_EWRFIRQ_Msk (0x1UL << PWR_CR3_EWRFIRQ_Pos) /*!< 0x00020000 */ +#define PWR_CR3_EWRFIRQ PWR_CR3_EWRFIRQ_Msk /*!< Enable Radio IRQ[2:0] and wake-up for CPU1 */ + +#define PWR_CR3_EC2H_Pos (14U) +#define PWR_CR3_EC2H_Msk (0x1UL << PWR_CR3_EC2H_Pos) /*!< 0x00040000 */ +#define PWR_CR3_EC2H PWR_CR3_EC2H_Msk /*!< CPU2 Hold interrupt for CPU1 */ + +#define PWR_CR3_EIWUL_Pos (15U) +#define PWR_CR3_EIWUL_Msk (0x1UL << PWR_CR3_EIWUL_Pos) /*!< 0x00080000 */ +#define PWR_CR3_EIWUL PWR_CR3_EIWUL_Msk /*!< Internal Wake-Up line interrupt for CPU1 */ + +/******************** Bit definition for PWR_CR4 register ********************/ +#define PWR_CR4_WP1_Pos (0U) +#define PWR_CR4_WP1_Msk (0x1UL << PWR_CR4_WP1_Pos) /*!< 0x00000001 */ +#define PWR_CR4_WP1 PWR_CR4_WP1_Msk /*!< Wake-Up Pin 1 [line 0] polarity */ +#define PWR_CR4_WP2_Pos (1U) +#define PWR_CR4_WP2_Msk (0x1UL << PWR_CR4_WP2_Pos) /*!< 0x00000002 */ +#define PWR_CR4_WP2 PWR_CR4_WP2_Msk /*!< Wake-Up Pin 2 [line 1] polarity */ +#define PWR_CR4_WP3_Pos (2U) +#define PWR_CR4_WP3_Msk (0x1UL << PWR_CR4_WP3_Pos) /*!< 0x00000004 */ +#define PWR_CR4_WP3 PWR_CR4_WP3_Msk /*!< Wake-Up Pin 3 [line 2] polarity */ + +#define PWR_CR4_VBE_Pos (8U) +#define PWR_CR4_VBE_Msk (0x1UL << PWR_CR4_VBE_Pos) /*!< 0x00000100 */ +#define PWR_CR4_VBE PWR_CR4_VBE_Msk /*!< VBAT battery charging enable */ +#define PWR_CR4_VBRS_Pos (9U) +#define PWR_CR4_VBRS_Msk (0x1UL << PWR_CR4_VBRS_Pos) /*!< 0x00000200 */ +#define PWR_CR4_VBRS PWR_CR4_VBRS_Msk /*!< VBAT battery charging resistor selection */ + +#define PWR_CR4_WRFBUSYP_Pos (11U) +#define PWR_CR4_WRFBUSYP_Msk (0x1UL << PWR_CR4_WRFBUSYP_Pos) /*!< 0x00008000 */ +#define PWR_CR4_WRFBUSYP PWR_CR4_WRFBUSYP_Msk /*!< Wake-up radio busy polarity */ + +#define PWR_CR4_C2BOOT_Pos (15U) +#define PWR_CR4_C2BOOT_Msk (0x1UL << PWR_CR4_C2BOOT_Pos) /*!< 0x00008000 */ +#define PWR_CR4_C2BOOT PWR_CR4_C2BOOT_Msk /*!< Boot CPU2 after reset or wakeup from Stop or Standby modes */ + +/******************** Bit definition for PWR_SR1 register ********************/ +#define PWR_SR1_WUF_Pos (0U) +#define PWR_SR1_WUF_Msk (0x1FUL << PWR_SR1_WUF_Pos) /*!< 0x00000007 */ +#define PWR_SR1_WUF PWR_SR1_WUF_Msk /*!< Wakeup Flags of all pins */ +#define PWR_SR1_WUF1_Pos (0U) +#define PWR_SR1_WUF1_Msk (0x1UL << PWR_SR1_WUF1_Pos) /*!< 0x00000001 */ +#define PWR_SR1_WUF1 PWR_SR1_WUF1_Msk /*!< Wakeup Pin 1 [Flag 0] */ +#define PWR_SR1_WUF2_Pos (1U) +#define PWR_SR1_WUF2_Msk (0x1UL << PWR_SR1_WUF2_Pos) /*!< 0x00000002 */ +#define PWR_SR1_WUF2 PWR_SR1_WUF2_Msk /*!< Wakeup Pin 2 [Flag 1] */ +#define PWR_SR1_WUF3_Pos (2U) +#define PWR_SR1_WUF3_Msk (0x1UL << PWR_SR1_WUF3_Pos) /*!< 0x00000004 */ +#define PWR_SR1_WUF3 PWR_SR1_WUF3_Msk /*!< Wakeup Pin 3 [Flag 2] */ + +#define PWR_SR1_WPVDF_Pos (8U) +#define PWR_SR1_WPVDF_Msk (0x1UL << PWR_SR1_WPVDF_Pos) /*!< 0x00000100 */ +#define PWR_SR1_WPVDF PWR_SR1_WPVDF_Msk /*!< Wakeup PVD flag */ + +#define PWR_SR1_WRFBUSYF_Pos (11U) +#define PWR_SR1_WRFBUSYF_Msk (0x1UL << PWR_SR1_WRFBUSYF_Pos) /*!< 0x00000800 */ +#define PWR_SR1_WRFBUSYF PWR_SR1_WRFBUSYF_Msk /*!< Wakeup radio busy flag */ + +#define PWR_SR1_C2HF_Pos (14U) +#define PWR_SR1_C2HF_Msk (0x1UL << PWR_SR1_C2HF_Pos) /*!< 0x00004000 */ +#define PWR_SR1_C2HF PWR_SR1_C2HF_Msk /*!< CPU2 Hold interrupt flag */ + +#define PWR_SR1_WUFI_Pos (15U) +#define PWR_SR1_WUFI_Msk (0x1UL << PWR_SR1_WUFI_Pos) /*!< 0x00008000 */ +#define PWR_SR1_WUFI PWR_SR1_WUFI_Msk /*!< Internal wakeup interrupt flag */ + +/******************** Bit definition for PWR_SR2 register ********************/ +#define PWR_SR2_C2BOOTS_Pos (0U) +#define PWR_SR2_C2BOOTS_Msk (0x1UL << PWR_SR2_C2BOOTS_Pos) /*!< 0x00000001 */ +#define PWR_SR2_C2BOOTS PWR_SR2_C2BOOTS_Msk /*!< CPU2 boot or wakeup request source information */ + +#define PWR_SR2_RFBUSYS_Pos (1U) +#define PWR_SR2_RFBUSYS_Msk (0x1UL << PWR_SR2_RFBUSYS_Pos) /*!< 0x00000002 */ +#define PWR_SR2_RFBUSYS PWR_SR2_RFBUSYS_Msk /*!< Radio busy signal status */ + +#define PWR_SR2_RFBUSYMS_Pos (2U) +#define PWR_SR2_RFBUSYMS_Msk (0x1UL << PWR_SR2_RFBUSYMS_Pos) /*!< 0x00000004 */ +#define PWR_SR2_RFBUSYMS PWR_SR2_RFBUSYMS_Msk /*!< Radio busy masked signal status */ + +#define PWR_SR2_SMPSRDY_Pos (3U) +#define PWR_SR2_SMPSRDY_Msk (0x1UL << PWR_SR2_SMPSRDY_Pos) /*!< 0x00000008 */ +#define PWR_SR2_SMPSRDY PWR_SR2_SMPSRDY_Msk /*!< SMPS ready flag */ +#define PWR_SR2_LDORDY_Pos (4U) +#define PWR_SR2_LDORDY_Msk (0x1UL << PWR_SR2_LDORDY_Pos) /*!< 0x00000010 */ +#define PWR_SR2_LDORDY PWR_SR2_LDORDY_Msk /*!< LDO ready flag */ + +#define PWR_SR2_RFEOLF_Pos (5U) +#define PWR_SR2_RFEOLF_Msk (0x1UL << PWR_SR2_RFEOLF_Pos) /*!< 0x00000020 */ +#define PWR_SR2_RFEOLF PWR_SR2_RFEOLF_Msk /*!< Radio end of life flag */ + +#define PWR_SR2_REGMRS_Pos (6U) +#define PWR_SR2_REGMRS_Msk (0x1UL << PWR_SR2_REGMRS_Pos) /*!< 0x00000040 */ +#define PWR_SR2_REGMRS PWR_SR2_REGMRS_Msk /*!< Main regulator status */ + +#define PWR_SR2_FLASHRDY_Pos (7U) +#define PWR_SR2_FLASHRDY_Msk (0x1UL << PWR_SR2_FLASHRDY_Pos) /*!< 0x00000080 */ +#define PWR_SR2_FLASHRDY PWR_SR2_FLASHRDY_Msk /*!< Flash ready */ + +#define PWR_SR2_REGLPS_Pos (8U) +#define PWR_SR2_REGLPS_Msk (0x1UL << PWR_SR2_REGLPS_Pos) /*!< 0x00000100 */ +#define PWR_SR2_REGLPS PWR_SR2_REGLPS_Msk /*!< Low-power regulator ready */ +#define PWR_SR2_REGLPF_Pos (9U) +#define PWR_SR2_REGLPF_Msk (0x1UL << PWR_SR2_REGLPF_Pos) /*!< 0x00000200 */ +#define PWR_SR2_REGLPF PWR_SR2_REGLPF_Msk /*!< Low-power regulator being used */ + +#define PWR_SR2_VOSF_Pos (10U) +#define PWR_SR2_VOSF_Msk (0x1UL << PWR_SR2_VOSF_Pos) /*!< 0x00000400 */ +#define PWR_SR2_VOSF PWR_SR2_VOSF_Msk /*!< Voltage scaling flag */ +#define PWR_SR2_PVDO_Pos (11U) +#define PWR_SR2_PVDO_Msk (0x1UL << PWR_SR2_PVDO_Pos) /*!< 0x00000800 */ +#define PWR_SR2_PVDO PWR_SR2_PVDO_Msk /*!< Power voltage detector output */ + +#define PWR_SR2_PVMO3_Pos (14U) +#define PWR_SR2_PVMO3_Msk (0x1UL << PWR_SR2_PVMO3_Pos) /*!< 0x00004000 */ +#define PWR_SR2_PVMO3 PWR_SR2_PVMO3_Msk /*!< Peripheral voltage monitor output 3: VDDA vs. 1.62V */ + +/******************** Bit definition for PWR_SCR register ********************/ +#define PWR_SCR_CWUF_Pos (0U) +#define PWR_SCR_CWUF_Msk (0x7UL << PWR_SCR_CWUF_Pos) /*!< 0x00000007 */ +#define PWR_SCR_CWUF PWR_SCR_CWUF_Msk /*!< Clear Wake-up Flags for all pins */ +#define PWR_SCR_CWUF1_Pos (0U) +#define PWR_SCR_CWUF1_Msk (0x1UL << PWR_SCR_CWUF1_Pos) /*!< 0x00000001 */ +#define PWR_SCR_CWUF1 PWR_SCR_CWUF1_Msk /*!< Clear Wake-up Pin 1 [Flag 0] */ +#define PWR_SCR_CWUF2_Pos (1U) +#define PWR_SCR_CWUF2_Msk (0x1UL << PWR_SCR_CWUF2_Pos) /*!< 0x00000002 */ +#define PWR_SCR_CWUF2 PWR_SCR_CWUF2_Msk /*!< Clear Wake-up Pin 2 [Flag 1] */ +#define PWR_SCR_CWUF3_Pos (2U) +#define PWR_SCR_CWUF3_Msk (0x1UL << PWR_SCR_CWUF3_Pos) /*!< 0x00000004 */ +#define PWR_SCR_CWUF3 PWR_SCR_CWUF3_Msk /*!< Clear Wake-up Pin 3 [Flag 2] */ + +#define PWR_SCR_CWPVDF_Pos (8U) +#define PWR_SCR_CWPVDF_Msk (0x1UL << PWR_SCR_CWPVDF_Pos) /*!< 0x00000100 */ +#define PWR_SCR_CWPVDF PWR_SCR_CWPVDF_Msk /*!< Clear wakeup PVD interrupt flag */ + +#define PWR_SCR_CWRFBUSYF_Pos (11U) +#define PWR_SCR_CWRFBUSYF_Msk (0x1UL << PWR_SCR_CWRFBUSYF_Pos) /*!< 0x00000800 */ +#define PWR_SCR_CWRFBUSYF PWR_SCR_CWRFBUSYF_Msk /*!< Clear Radio busy interrupt flag */ + +#define PWR_SCR_CC2HF_Pos (14U) +#define PWR_SCR_CC2HF_Msk (0x1UL << PWR_SCR_CC2HF_Pos) /*!< 0x00004000 */ +#define PWR_SCR_CC2HF PWR_SCR_CC2HF_Msk /*!< Clear CPU2 Hold interrupt flag */ + +/******************** Bit definition for PWR_CR5 register ********************/ +#define PWR_CR5_RFEOLEN_Pos (14U) +#define PWR_CR5_RFEOLEN_Msk (0x1UL << PWR_CR5_RFEOLEN_Pos) /*!< 0x00004000 */ +#define PWR_CR5_RFEOLEN PWR_CR5_RFEOLEN_Msk /*!< Enable Radio End Of Life detector enabled */ + +#define PWR_CR5_SMPSEN_Pos (15U) +#define PWR_CR5_SMPSEN_Msk (0x1UL << PWR_CR5_SMPSEN_Pos) /*!< 0x00008000 */ +#define PWR_CR5_SMPSEN PWR_CR5_SMPSEN_Msk /*!< Enable SMPS Step Down converter SMPS mode enable */ + +/******************** Bit definition for PWR_PUCRA register *****************/ +#define PWR_PUCRA_PA0_Pos (0U) +#define PWR_PUCRA_PA0_Msk (0x1UL << PWR_PUCRA_PA0_Pos) /*!< 0x00000001 */ +#define PWR_PUCRA_PA0 PWR_PUCRA_PA0_Msk /*!< Pin PA0 Pull-Up set */ +#define PWR_PUCRA_PA1_Pos (1U) +#define PWR_PUCRA_PA1_Msk (0x1UL << PWR_PUCRA_PA1_Pos) /*!< 0x00000002 */ +#define PWR_PUCRA_PA1 PWR_PUCRA_PA1_Msk /*!< Pin PA1 Pull-Up set */ +#define PWR_PUCRA_PA2_Pos (2U) +#define PWR_PUCRA_PA2_Msk (0x1UL << PWR_PUCRA_PA2_Pos) /*!< 0x00000004 */ +#define PWR_PUCRA_PA2 PWR_PUCRA_PA2_Msk /*!< Pin PA2 Pull-Up set */ +#define PWR_PUCRA_PA3_Pos (3U) +#define PWR_PUCRA_PA3_Msk (0x1UL << PWR_PUCRA_PA3_Pos) /*!< 0x00000008 */ +#define PWR_PUCRA_PA3 PWR_PUCRA_PA3_Msk /*!< Pin PA3 Pull-Up set */ +#define PWR_PUCRA_PA4_Pos (4U) +#define PWR_PUCRA_PA4_Msk (0x1UL << PWR_PUCRA_PA4_Pos) /*!< 0x00000010 */ +#define PWR_PUCRA_PA4 PWR_PUCRA_PA4_Msk /*!< Pin PA4 Pull-Up set */ +#define PWR_PUCRA_PA5_Pos (5U) +#define PWR_PUCRA_PA5_Msk (0x1UL << PWR_PUCRA_PA5_Pos) /*!< 0x00000020 */ +#define PWR_PUCRA_PA5 PWR_PUCRA_PA5_Msk /*!< Pin PA5 Pull-Up set */ +#define PWR_PUCRA_PA6_Pos (6U) +#define PWR_PUCRA_PA6_Msk (0x1UL << PWR_PUCRA_PA6_Pos) /*!< 0x00000040 */ +#define PWR_PUCRA_PA6 PWR_PUCRA_PA6_Msk /*!< Pin PA6 Pull-Up set */ +#define PWR_PUCRA_PA7_Pos (7U) +#define PWR_PUCRA_PA7_Msk (0x1UL << PWR_PUCRA_PA7_Pos) /*!< 0x00000080 */ +#define PWR_PUCRA_PA7 PWR_PUCRA_PA7_Msk /*!< Pin PA7 Pull-Up set */ +#define PWR_PUCRA_PA8_Pos (8U) +#define PWR_PUCRA_PA8_Msk (0x1UL << PWR_PUCRA_PA8_Pos) /*!< 0x00000100 */ +#define PWR_PUCRA_PA8 PWR_PUCRA_PA8_Msk /*!< Pin PA8 Pull-Up set */ +#define PWR_PUCRA_PA9_Pos (9U) +#define PWR_PUCRA_PA9_Msk (0x1UL << PWR_PUCRA_PA9_Pos) /*!< 0x00000200 */ +#define PWR_PUCRA_PA9 PWR_PUCRA_PA9_Msk /*!< Pin PA9 Pull-Up set */ +#define PWR_PUCRA_PA10_Pos (10U) +#define PWR_PUCRA_PA10_Msk (0x1UL << PWR_PUCRA_PA10_Pos) /*!< 0x00000400 */ +#define PWR_PUCRA_PA10 PWR_PUCRA_PA10_Msk /*!< Pin PA10 Pull-Up set */ +#define PWR_PUCRA_PA11_Pos (11U) +#define PWR_PUCRA_PA11_Msk (0x1UL << PWR_PUCRA_PA11_Pos) /*!< 0x00000800 */ +#define PWR_PUCRA_PA11 PWR_PUCRA_PA11_Msk /*!< Pin PA11 Pull-Up set */ +#define PWR_PUCRA_PA12_Pos (12U) +#define PWR_PUCRA_PA12_Msk (0x1UL << PWR_PUCRA_PA12_Pos) /*!< 0x00001000 */ +#define PWR_PUCRA_PA12 PWR_PUCRA_PA12_Msk /*!< Pin PA12 Pull-Up set */ +#define PWR_PUCRA_PA13_Pos (13U) +#define PWR_PUCRA_PA13_Msk (0x1UL << PWR_PUCRA_PA13_Pos) /*!< 0x00002000 */ +#define PWR_PUCRA_PA13 PWR_PUCRA_PA13_Msk /*!< Pin PA13 Pull-Up set */ +#define PWR_PUCRA_PA14_Pos (14U) +#define PWR_PUCRA_PA14_Msk (0x1UL << PWR_PUCRA_PA14_Pos) /*!< 0x00004000 */ +#define PWR_PUCRA_PA14 PWR_PUCRA_PA14_Msk /*!< Pin PA14 Pull-Up set */ +#define PWR_PUCRA_PA15_Pos (15U) +#define PWR_PUCRA_PA15_Msk (0x1UL << PWR_PUCRA_PA15_Pos) /*!< 0x00008000 */ +#define PWR_PUCRA_PA15 PWR_PUCRA_PA15_Msk /*!< Pin PA15 Pull-Up set */ + +/******************** Bit definition for PWR_PDCRA register *****************/ +#define PWR_PDCRA_PA0_Pos (0U) +#define PWR_PDCRA_PA0_Msk (0x1UL << PWR_PDCRA_PA0_Pos) /*!< 0x00000001 */ +#define PWR_PDCRA_PA0 PWR_PDCRA_PA0_Msk /*!< Pin PA0 Pull-Down set */ +#define PWR_PDCRA_PA1_Pos (1U) +#define PWR_PDCRA_PA1_Msk (0x1UL << PWR_PDCRA_PA1_Pos) /*!< 0x00000002 */ +#define PWR_PDCRA_PA1 PWR_PDCRA_PA1_Msk /*!< Pin PA1 Pull-Down set */ +#define PWR_PDCRA_PA2_Pos (2U) +#define PWR_PDCRA_PA2_Msk (0x1UL << PWR_PDCRA_PA2_Pos) /*!< 0x00000004 */ +#define PWR_PDCRA_PA2 PWR_PDCRA_PA2_Msk /*!< Pin PA2 Pull-Down set */ +#define PWR_PDCRA_PA3_Pos (3U) +#define PWR_PDCRA_PA3_Msk (0x1UL << PWR_PDCRA_PA3_Pos) /*!< 0x00000008 */ +#define PWR_PDCRA_PA3 PWR_PDCRA_PA3_Msk /*!< Pin PA3 Pull-Down set */ +#define PWR_PDCRA_PA4_Pos (4U) +#define PWR_PDCRA_PA4_Msk (0x1UL << PWR_PDCRA_PA4_Pos) /*!< 0x00000010 */ +#define PWR_PDCRA_PA4 PWR_PDCRA_PA4_Msk /*!< Pin PA4 Pull-Down set */ +#define PWR_PDCRA_PA5_Pos (5U) +#define PWR_PDCRA_PA5_Msk (0x1UL << PWR_PDCRA_PA5_Pos) /*!< 0x00000020 */ +#define PWR_PDCRA_PA5 PWR_PDCRA_PA5_Msk /*!< Pin PA5 Pull-Down set */ +#define PWR_PDCRA_PA6_Pos (6U) +#define PWR_PDCRA_PA6_Msk (0x1UL << PWR_PDCRA_PA6_Pos) /*!< 0x00000040 */ +#define PWR_PDCRA_PA6 PWR_PDCRA_PA6_Msk /*!< Pin PA6 Pull-Down set */ +#define PWR_PDCRA_PA7_Pos (7U) +#define PWR_PDCRA_PA7_Msk (0x1UL << PWR_PDCRA_PA7_Pos) /*!< 0x00000080 */ +#define PWR_PDCRA_PA7 PWR_PDCRA_PA7_Msk /*!< Pin PA7 Pull-Down set */ +#define PWR_PDCRA_PA8_Pos (8U) +#define PWR_PDCRA_PA8_Msk (0x1UL << PWR_PDCRA_PA8_Pos) /*!< 0x00000100 */ +#define PWR_PDCRA_PA8 PWR_PDCRA_PA8_Msk /*!< Pin PA8 Pull-Down set */ +#define PWR_PDCRA_PA9_Pos (9U) +#define PWR_PDCRA_PA9_Msk (0x1UL << PWR_PDCRA_PA9_Pos) /*!< 0x00000200 */ +#define PWR_PDCRA_PA9 PWR_PDCRA_PA9_Msk /*!< Pin PA9 Pull-Down set */ +#define PWR_PDCRA_PA10_Pos (10U) +#define PWR_PDCRA_PA10_Msk (0x1UL << PWR_PDCRA_PA10_Pos) /*!< 0x00000400 */ +#define PWR_PDCRA_PA10 PWR_PDCRA_PA10_Msk /*!< Pin PA10 Pull-Down set */ +#define PWR_PDCRA_PA11_Pos (11U) +#define PWR_PDCRA_PA11_Msk (0x1UL << PWR_PDCRA_PA11_Pos) /*!< 0x00000800 */ +#define PWR_PDCRA_PA11 PWR_PDCRA_PA11_Msk /*!< Pin PA11 Pull-Down set */ +#define PWR_PDCRA_PA12_Pos (12U) +#define PWR_PDCRA_PA12_Msk (0x1UL << PWR_PDCRA_PA12_Pos) /*!< 0x00001000 */ +#define PWR_PDCRA_PA12 PWR_PDCRA_PA12_Msk /*!< Pin PA12 Pull-Down set */ +#define PWR_PDCRA_PA13_Pos (13U) +#define PWR_PDCRA_PA13_Msk (0x1UL << PWR_PDCRA_PA13_Pos) /*!< 0x00002000 */ +#define PWR_PDCRA_PA13 PWR_PDCRA_PA13_Msk /*!< Pin PA13 Pull-Down set */ +#define PWR_PDCRA_PA14_Pos (14U) +#define PWR_PDCRA_PA14_Msk (0x1UL << PWR_PDCRA_PA14_Pos) /*!< 0x00004000 */ +#define PWR_PDCRA_PA14 PWR_PDCRA_PA14_Msk /*!< Pin PA14 Pull-Down set */ +#define PWR_PDCRA_PA15_Pos (15U) +#define PWR_PDCRA_PA15_Msk (0x1UL << PWR_PDCRA_PA15_Pos) /*!< 0x00008000 */ +#define PWR_PDCRA_PA15 PWR_PDCRA_PA15_Msk /*!< Pin PA15 Pull-Down set */ + +/******************** Bit definition for PWR_PUCRB register *****************/ +#define PWR_PUCRB_PB0_Pos (0U) +#define PWR_PUCRB_PB0_Msk (0x1UL << PWR_PUCRB_PB0_Pos) /*!< 0x00000001 */ +#define PWR_PUCRB_PB0 PWR_PUCRB_PB0_Msk /*!< Pin PB0 Pull-Up set */ +#define PWR_PUCRB_PB1_Pos (1U) +#define PWR_PUCRB_PB1_Msk (0x1UL << PWR_PUCRB_PB1_Pos) /*!< 0x00000002 */ +#define PWR_PUCRB_PB1 PWR_PUCRB_PB1_Msk /*!< Pin PB1 Pull-Up set */ +#define PWR_PUCRB_PB2_Pos (2U) +#define PWR_PUCRB_PB2_Msk (0x1UL << PWR_PUCRB_PB2_Pos) /*!< 0x00000004 */ +#define PWR_PUCRB_PB2 PWR_PUCRB_PB2_Msk /*!< Pin PB2 Pull-Up set */ +#define PWR_PUCRB_PB3_Pos (3U) +#define PWR_PUCRB_PB3_Msk (0x1UL << PWR_PUCRB_PB3_Pos) /*!< 0x00000008 */ +#define PWR_PUCRB_PB3 PWR_PUCRB_PB3_Msk /*!< Pin PB3 Pull-Up set */ +#define PWR_PUCRB_PB4_Pos (4U) +#define PWR_PUCRB_PB4_Msk (0x1UL << PWR_PUCRB_PB4_Pos) /*!< 0x00000010 */ +#define PWR_PUCRB_PB4 PWR_PUCRB_PB4_Msk /*!< Pin PB4 Pull-Up set */ +#define PWR_PUCRB_PB5_Pos (5U) +#define PWR_PUCRB_PB5_Msk (0x1UL << PWR_PUCRB_PB5_Pos) /*!< 0x00000020 */ +#define PWR_PUCRB_PB5 PWR_PUCRB_PB5_Msk /*!< Pin PB5 Pull-Up set */ +#define PWR_PUCRB_PB6_Pos (6U) +#define PWR_PUCRB_PB6_Msk (0x1UL << PWR_PUCRB_PB6_Pos) /*!< 0x00000040 */ +#define PWR_PUCRB_PB6 PWR_PUCRB_PB6_Msk /*!< Pin PB6 Pull-Up set */ +#define PWR_PUCRB_PB7_Pos (7U) +#define PWR_PUCRB_PB7_Msk (0x1UL << PWR_PUCRB_PB7_Pos) /*!< 0x00000080 */ +#define PWR_PUCRB_PB7 PWR_PUCRB_PB7_Msk /*!< Pin PB7 Pull-Up set */ +#define PWR_PUCRB_PB8_Pos (8U) +#define PWR_PUCRB_PB8_Msk (0x1UL << PWR_PUCRB_PB8_Pos) /*!< 0x00000100 */ +#define PWR_PUCRB_PB8 PWR_PUCRB_PB8_Msk /*!< Pin PB8 Pull-Up set */ +#define PWR_PUCRB_PB9_Pos (9U) +#define PWR_PUCRB_PB9_Msk (0x1UL << PWR_PUCRB_PB9_Pos) /*!< 0x00000200 */ +#define PWR_PUCRB_PB9 PWR_PUCRB_PB9_Msk /*!< Pin PB9 Pull-Up set */ +#define PWR_PUCRB_PB10_Pos (10U) +#define PWR_PUCRB_PB10_Msk (0x1UL << PWR_PUCRB_PB10_Pos) /*!< 0x00000400 */ +#define PWR_PUCRB_PB10 PWR_PUCRB_PB10_Msk /*!< Pin PB10 Pull-Up set */ +#define PWR_PUCRB_PB11_Pos (11U) +#define PWR_PUCRB_PB11_Msk (0x1UL << PWR_PUCRB_PB11_Pos) /*!< 0x00000800 */ +#define PWR_PUCRB_PB11 PWR_PUCRB_PB11_Msk /*!< Pin PB11 Pull-Up set */ +#define PWR_PUCRB_PB12_Pos (12U) +#define PWR_PUCRB_PB12_Msk (0x1UL << PWR_PUCRB_PB12_Pos) /*!< 0x00001000 */ +#define PWR_PUCRB_PB12 PWR_PUCRB_PB12_Msk /*!< Pin PB12 Pull-Up set */ +#define PWR_PUCRB_PB13_Pos (13U) +#define PWR_PUCRB_PB13_Msk (0x1UL << PWR_PUCRB_PB13_Pos) /*!< 0x00002000 */ +#define PWR_PUCRB_PB13 PWR_PUCRB_PB13_Msk /*!< Pin PB13 Pull-Up set */ +#define PWR_PUCRB_PB14_Pos (14U) +#define PWR_PUCRB_PB14_Msk (0x1UL << PWR_PUCRB_PB14_Pos) /*!< 0x00004000 */ +#define PWR_PUCRB_PB14 PWR_PUCRB_PB14_Msk /*!< Pin PB14 Pull-Up set */ +#define PWR_PUCRB_PB15_Pos (15U) +#define PWR_PUCRB_PB15_Msk (0x1UL << PWR_PUCRB_PB15_Pos) /*!< 0x00008000 */ +#define PWR_PUCRB_PB15 PWR_PUCRB_PB15_Msk /*!< Pin PB15 Pull-Up set */ + +/******************** Bit definition for PWR_PDCRB register *****************/ +#define PWR_PDCRB_PB0_Pos (0U) +#define PWR_PDCRB_PB0_Msk (0x1UL << PWR_PDCRB_PB0_Pos) /*!< 0x00000001 */ +#define PWR_PDCRB_PB0 PWR_PDCRB_PB0_Msk /*!< Pin PB0 Pull-Down set */ +#define PWR_PDCRB_PB1_Pos (1U) +#define PWR_PDCRB_PB1_Msk (0x1UL << PWR_PDCRB_PB1_Pos) /*!< 0x00000002 */ +#define PWR_PDCRB_PB1 PWR_PDCRB_PB1_Msk /*!< Pin PB1 Pull-Down set */ +#define PWR_PDCRB_PB2_Pos (2U) +#define PWR_PDCRB_PB2_Msk (0x1UL << PWR_PDCRB_PB2_Pos) /*!< 0x00000004 */ +#define PWR_PDCRB_PB2 PWR_PDCRB_PB2_Msk /*!< Pin PB2 Pull-Down set */ +#define PWR_PDCRB_PB3_Pos (3U) +#define PWR_PDCRB_PB3_Msk (0x1UL << PWR_PDCRB_PB3_Pos) /*!< 0x00000008 */ +#define PWR_PDCRB_PB3 PWR_PDCRB_PB3_Msk /*!< Pin PB3 Pull-Down set */ +#define PWR_PDCRB_PB4_Pos (4U) +#define PWR_PDCRB_PB4_Msk (0x1UL << PWR_PDCRB_PB4_Pos) /*!< 0x00000010 */ +#define PWR_PDCRB_PB4 PWR_PDCRB_PB4_Msk /*!< Pin PB4 Pull-Down set */ +#define PWR_PDCRB_PB5_Pos (5U) +#define PWR_PDCRB_PB5_Msk (0x1UL << PWR_PDCRB_PB5_Pos) /*!< 0x00000020 */ +#define PWR_PDCRB_PB5 PWR_PDCRB_PB5_Msk /*!< Pin PB5 Pull-Down set */ +#define PWR_PDCRB_PB6_Pos (6U) +#define PWR_PDCRB_PB6_Msk (0x1UL << PWR_PDCRB_PB6_Pos) /*!< 0x00000040 */ +#define PWR_PDCRB_PB6 PWR_PDCRB_PB6_Msk /*!< Pin PB6 Pull-Down set */ +#define PWR_PDCRB_PB7_Pos (7U) +#define PWR_PDCRB_PB7_Msk (0x1UL << PWR_PDCRB_PB7_Pos) /*!< 0x00000080 */ +#define PWR_PDCRB_PB7 PWR_PDCRB_PB7_Msk /*!< Pin PB7 Pull-Down set */ +#define PWR_PDCRB_PB8_Pos (8U) +#define PWR_PDCRB_PB8_Msk (0x1UL << PWR_PDCRB_PB8_Pos) /*!< 0x00000100 */ +#define PWR_PDCRB_PB8 PWR_PDCRB_PB8_Msk /*!< Pin PB8 Pull-Down set */ +#define PWR_PDCRB_PB9_Pos (9U) +#define PWR_PDCRB_PB9_Msk (0x1UL << PWR_PDCRB_PB9_Pos) /*!< 0x00000200 */ +#define PWR_PDCRB_PB9 PWR_PDCRB_PB9_Msk /*!< Pin PB9 Pull-Down set */ +#define PWR_PDCRB_PB10_Pos (10U) +#define PWR_PDCRB_PB10_Msk (0x1UL << PWR_PDCRB_PB10_Pos) /*!< 0x00000400 */ +#define PWR_PDCRB_PB10 PWR_PDCRB_PB10_Msk /*!< Pin PB10 Pull-Down set */ +#define PWR_PDCRB_PB11_Pos (11U) +#define PWR_PDCRB_PB11_Msk (0x1UL << PWR_PDCRB_PB11_Pos) /*!< 0x00000800 */ +#define PWR_PDCRB_PB11 PWR_PDCRB_PB11_Msk /*!< Pin PB11 Pull-Down set */ +#define PWR_PDCRB_PB12_Pos (12U) +#define PWR_PDCRB_PB12_Msk (0x1UL << PWR_PDCRB_PB12_Pos) /*!< 0x00001000 */ +#define PWR_PDCRB_PB12 PWR_PDCRB_PB12_Msk /*!< Pin PB12 Pull-Down set */ +#define PWR_PDCRB_PB13_Pos (13U) +#define PWR_PDCRB_PB13_Msk (0x1UL << PWR_PDCRB_PB13_Pos) /*!< 0x00002000 */ +#define PWR_PDCRB_PB13 PWR_PDCRB_PB13_Msk /*!< Pin PB13 Pull-Down set */ +#define PWR_PDCRB_PB14_Pos (14U) +#define PWR_PDCRB_PB14_Msk (0x1UL << PWR_PDCRB_PB14_Pos) /*!< 0x00004000 */ +#define PWR_PDCRB_PB14 PWR_PDCRB_PB14_Msk /*!< Pin PB14 Pull-Down set */ +#define PWR_PDCRB_PB15_Pos (15U) +#define PWR_PDCRB_PB15_Msk (0x1UL << PWR_PDCRB_PB15_Pos) /*!< 0x00008000 */ +#define PWR_PDCRB_PB15 PWR_PDCRB_PB15_Msk /*!< Pin PB15 Pull-Down set */ + +/******************** Bit definition for PWR_PUCRC register *****************/ +#define PWR_PUCRC_PC0_Pos (0U) +#define PWR_PUCRC_PC0_Msk (0x1UL << PWR_PUCRC_PC0_Pos) /*!< 0x00000001 */ +#define PWR_PUCRC_PC0 PWR_PUCRC_PC0_Msk /*!< Pin PC0 Pull-Up set */ +#define PWR_PUCRC_PC1_Pos (1U) +#define PWR_PUCRC_PC1_Msk (0x1UL << PWR_PUCRC_PC1_Pos) /*!< 0x00000002 */ +#define PWR_PUCRC_PC1 PWR_PUCRC_PC1_Msk /*!< Pin PC1 Pull-Up set */ +#define PWR_PUCRC_PC2_Pos (2U) +#define PWR_PUCRC_PC2_Msk (0x1UL << PWR_PUCRC_PC2_Pos) /*!< 0x00000004 */ +#define PWR_PUCRC_PC2 PWR_PUCRC_PC2_Msk /*!< Pin PC2 Pull-Up set */ +#define PWR_PUCRC_PC3_Pos (3U) +#define PWR_PUCRC_PC3_Msk (0x1UL << PWR_PUCRC_PC3_Pos) /*!< 0x00000008 */ +#define PWR_PUCRC_PC3 PWR_PUCRC_PC3_Msk /*!< Pin PC3 Pull-Up set */ +#define PWR_PUCRC_PC4_Pos (4U) +#define PWR_PUCRC_PC4_Msk (0x1UL << PWR_PUCRC_PC4_Pos) /*!< 0x00000010 */ +#define PWR_PUCRC_PC4 PWR_PUCRC_PC4_Msk /*!< Pin PC4 Pull-Up set */ +#define PWR_PUCRC_PC5_Pos (5U) +#define PWR_PUCRC_PC5_Msk (0x1UL << PWR_PUCRC_PC5_Pos) /*!< 0x00000020 */ +#define PWR_PUCRC_PC5 PWR_PUCRC_PC5_Msk /*!< Pin PC5 Pull-Up set */ +#define PWR_PUCRC_PC6_Pos (6U) +#define PWR_PUCRC_PC6_Msk (0x1UL << PWR_PUCRC_PC6_Pos) /*!< 0x00000040 */ +#define PWR_PUCRC_PC6 PWR_PUCRC_PC6_Msk /*!< Pin PC6 Pull-Up set */ +#define PWR_PUCRC_PC13_Pos (13U) +#define PWR_PUCRC_PC13_Msk (0x1UL << PWR_PUCRC_PC13_Pos) /*!< 0x00002000 */ +#define PWR_PUCRC_PC13 PWR_PUCRC_PC13_Msk /*!< Pin PC13 Pull-Up set */ +#define PWR_PUCRC_PC14_Pos (14U) +#define PWR_PUCRC_PC14_Msk (0x1UL << PWR_PUCRC_PC14_Pos) /*!< 0x00004000 */ +#define PWR_PUCRC_PC14 PWR_PUCRC_PC14_Msk /*!< Pin PC14 Pull-Up set */ +#define PWR_PUCRC_PC15_Pos (15U) +#define PWR_PUCRC_PC15_Msk (0x1UL << PWR_PUCRC_PC15_Pos) /*!< 0x00008000 */ +#define PWR_PUCRC_PC15 PWR_PUCRC_PC15_Msk /*!< Pin PC15 Pull-Up set */ + +/******************** Bit definition for PWR_PDCRC register *****************/ +#define PWR_PDCRC_PC0_Pos (0U) +#define PWR_PDCRC_PC0_Msk (0x1UL << PWR_PDCRC_PC0_Pos) /*!< 0x00000001 */ +#define PWR_PDCRC_PC0 PWR_PDCRC_PC0_Msk /*!< Pin PC0 Pull-Down set */ +#define PWR_PDCRC_PC1_Pos (1U) +#define PWR_PDCRC_PC1_Msk (0x1UL << PWR_PDCRC_PC1_Pos) /*!< 0x00000002 */ +#define PWR_PDCRC_PC1 PWR_PDCRC_PC1_Msk /*!< Pin PC1 Pull-Down set */ +#define PWR_PDCRC_PC2_Pos (2U) +#define PWR_PDCRC_PC2_Msk (0x1UL << PWR_PDCRC_PC2_Pos) /*!< 0x00000004 */ +#define PWR_PDCRC_PC2 PWR_PDCRC_PC2_Msk /*!< Pin PC2 Pull-Down set */ +#define PWR_PDCRC_PC3_Pos (3U) +#define PWR_PDCRC_PC3_Msk (0x1UL << PWR_PDCRC_PC3_Pos) /*!< 0x00000008 */ +#define PWR_PDCRC_PC3 PWR_PDCRC_PC3_Msk /*!< Pin PC3 Pull-Down set */ +#define PWR_PDCRC_PC4_Pos (4U) +#define PWR_PDCRC_PC4_Msk (0x1UL << PWR_PDCRC_PC4_Pos) /*!< 0x00000010 */ +#define PWR_PDCRC_PC4 PWR_PDCRC_PC4_Msk /*!< Pin PC4 Pull-Down set */ +#define PWR_PDCRC_PC5_Pos (5U) +#define PWR_PDCRC_PC5_Msk (0x1UL << PWR_PDCRC_PC5_Pos) /*!< 0x00000020 */ +#define PWR_PDCRC_PC5 PWR_PDCRC_PC5_Msk /*!< Pin PC5 Pull-Down set */ +#define PWR_PDCRC_PC6_Pos (6U) +#define PWR_PDCRC_PC6_Msk (0x1UL << PWR_PDCRC_PC6_Pos) /*!< 0x00000040 */ +#define PWR_PDCRC_PC6 PWR_PDCRC_PC6_Msk /*!< Pin PC6 Pull-Down set */ +#define PWR_PDCRC_PC13_Pos (13U) +#define PWR_PDCRC_PC13_Msk (0x1UL << PWR_PDCRC_PC13_Pos) /*!< 0x00002000 */ +#define PWR_PDCRC_PC13 PWR_PDCRC_PC13_Msk /*!< Pin PC13 Pull-Down set */ +#define PWR_PDCRC_PC14_Pos (14U) +#define PWR_PDCRC_PC14_Msk (0x1UL << PWR_PDCRC_PC14_Pos) /*!< 0x00004000 */ +#define PWR_PDCRC_PC14 PWR_PDCRC_PC14_Msk /*!< Pin PC14 Pull-Down set */ +#define PWR_PDCRC_PC15_Pos (15U) +#define PWR_PDCRC_PC15_Msk (0x1UL << PWR_PDCRC_PC15_Pos) /*!< 0x00008000 */ +#define PWR_PDCRC_PC15 PWR_PDCRC_PC15_Msk /*!< Pin PC15 Pull-Down set */ + +/******************** Bit definition for PWR_PUCRH register *****************/ +#define PWR_PUCRH_PH3_Pos (3U) +#define PWR_PUCRH_PH3_Msk (0x1UL << PWR_PUCRH_PH3_Pos) /*!< 0x00000004 */ +#define PWR_PUCRH_PH3 PWR_PUCRH_PH3_Msk /*!< Pin PH3 Pull-Up set */ + +/******************** Bit definition for PWR_PDCRH register *****************/ +#define PWR_PDCRH_PH3_Pos (3U) +#define PWR_PDCRH_PH3_Msk (0x1UL << PWR_PDCRH_PH3_Pos) /*!< 0x00000004 */ +#define PWR_PDCRH_PH3 PWR_PDCRH_PH3_Msk /*!< Pin PH3 Pull-Down set */ + +/******************** Bit definition for PWR_C2CR1 register ********************/ +#define PWR_C2CR1_LPMS_Pos (0U) +#define PWR_C2CR1_LPMS_Msk (0x7UL << PWR_C2CR1_LPMS_Pos) /*!< 0x00000007 */ +#define PWR_C2CR1_LPMS PWR_C2CR1_LPMS_Msk /*!< Low Power Mode Selection for CPU2 */ +#define PWR_C2CR1_LPMS_0 (0x1UL << PWR_C2CR1_LPMS_Pos) /*!< 0x00000001 */ +#define PWR_C2CR1_LPMS_1 (0x2UL << PWR_C2CR1_LPMS_Pos) /*!< 0x00000002 */ +#define PWR_C2CR1_LPMS_2 (0x4UL << PWR_C2CR1_LPMS_Pos) /*!< 0x00000004 */ + +#define PWR_C2CR1_FPDR_Pos (4U) +#define PWR_C2CR1_FPDR_Msk (0x1UL << PWR_C2CR1_FPDR_Pos) /*!< 0x00000010 */ +#define PWR_C2CR1_FPDR PWR_C2CR1_FPDR_Msk /*!< Flash power down mode during LPrun for CPU2 */ + +#define PWR_C2CR1_FPDS_Pos (5U) +#define PWR_C2CR1_FPDS_Msk (0x1UL << PWR_C2CR1_FPDS_Pos) /*!< 0x00000020 */ +#define PWR_C2CR1_FPDS PWR_C2CR1_FPDS_Msk /*!< Flash power down mode during LPsleep for CPU2 */ + +/******************** Bit definition for PWR_C2CR3 register ********************/ +#define PWR_C2CR3_EWUP_Pos (0U) +#define PWR_C2CR3_EWUP_Msk (0x07UL << PWR_C2CR3_EWUP_Pos) /*!< 0x00000007 */ +#define PWR_C2CR3_EWUP PWR_C2CR3_EWUP_Msk /*!< Enable all external Wake-Up lines for CPU2 */ +#define PWR_C2CR3_EWUP1_Pos (0U) +#define PWR_C2CR3_EWUP1_Msk (0x1UL << PWR_C2CR3_EWUP1_Pos) /*!< 0x00000001 */ +#define PWR_C2CR3_EWUP1 PWR_C2CR3_EWUP1_Msk /*!< Enable external WKUP Pin 1 [line 0] for CPU2 */ +#define PWR_C2CR3_EWUP2_Pos (1U) +#define PWR_C2CR3_EWUP2_Msk (0x1UL << PWR_C2CR3_EWUP2_Pos) /*!< 0x00000002 */ +#define PWR_C2CR3_EWUP2 PWR_C2CR3_EWUP2_Msk /*!< Enable external WKUP Pin 2 [line 1] for CPU2 */ +#define PWR_C2CR3_EWUP3_Pos (2U) +#define PWR_C2CR3_EWUP3_Msk (0x1UL << PWR_C2CR3_EWUP3_Pos) /*!< 0x00000004 */ +#define PWR_C2CR3_EWUP3 PWR_C2CR3_EWUP3_Msk /*!< Enable external WKUP Pin 3 [line 2] for CPU2 */ + +#define PWR_C2CR3_EWPVD_Pos (8U) +#define PWR_C2CR3_EWPVD_Msk (0x1UL << PWR_C2CR3_EWPVD_Pos) /*!< 0x00000100 */ +#define PWR_C2CR3_EWPVD PWR_C2CR3_EWPVD_Msk /*!< Enable wakeup PVD for CPU2 */ + +#define PWR_C2CR3_APC_Pos (10U) +#define PWR_C2CR3_APC_Msk (0x1UL << PWR_C2CR3_APC_Pos) /*!< 0x00000400 */ +#define PWR_C2CR3_APC PWR_C2CR3_APC_Msk /*!< Apply pull-up and pull-down configuration for CPU2 */ + +#define PWR_C2CR3_EWRFBUSY_Pos (11U) +#define PWR_C2CR3_EWRFBUSY_Msk (0x1UL << PWR_C2CR3_EWRFBUSY_Pos) /*!< 0x00000800 */ +#define PWR_C2CR3_EWRFBUSY PWR_C2CR3_EWRFBUSY_Msk /*!< Enable Radio busy IRQ and wake-up for CPU2 */ +#define PWR_C2CR3_EWRFIRQ_Pos (13U) +#define PWR_C2CR3_EWRFIRQ_Msk (0x1UL << PWR_C2CR3_EWRFIRQ_Pos) /*!< 0x00002000 */ +#define PWR_C2CR3_EWRFIRQ PWR_C2CR3_EWRFIRQ_Msk /*!< Enable Radio IRQ[2:0] and wake-up for CPU2 */ + +#define PWR_C2CR3_EIWUL_Pos (15U) +#define PWR_C2CR3_EIWUL_Msk (0x1UL << PWR_C2CR3_EIWUL_Pos) /*!< 0x00008000 */ +#define PWR_C2CR3_EIWUL PWR_C2CR3_EIWUL_Msk /*!< Internal Wake-Up line interrupt for CPU2 */ + +/******************** Bit definition for PWR_EXTSCR register ********************/ +#define PWR_EXTSCR_C1CSSF_Pos (0U) +#define PWR_EXTSCR_C1CSSF_Msk (0x1UL << PWR_EXTSCR_C1CSSF_Pos) /*!< 0x00000001 */ +#define PWR_EXTSCR_C1CSSF PWR_EXTSCR_C1CSSF_Msk /*!< Clear standby and stop flags for CPU1 */ +#define PWR_EXTSCR_C2CSSF_Pos (1U) +#define PWR_EXTSCR_C2CSSF_Msk (0x1UL << PWR_EXTSCR_C2CSSF_Pos) /*!< 0x00000002 */ +#define PWR_EXTSCR_C2CSSF PWR_EXTSCR_C2CSSF_Msk /*!< Clear standby and stop flags for CPU2 */ + +#define PWR_EXTSCR_C1SBF_Pos (8U) +#define PWR_EXTSCR_C1SBF_Msk (0x1UL << PWR_EXTSCR_C1SBF_Pos) /*!< 0x00000100 */ +#define PWR_EXTSCR_C1SBF PWR_EXTSCR_C1SBF_Msk /*!< System standby flag for CPU1 */ +#define PWR_EXTSCR_C1STOP2F_Pos (9U) +#define PWR_EXTSCR_C1STOP2F_Msk (0x1UL << PWR_EXTSCR_C1STOP2F_Pos) /*!< 0x00000200 */ +#define PWR_EXTSCR_C1STOP2F PWR_EXTSCR_C1STOP2F_Msk /*!< System stop2 flag for CPU1 */ +#define PWR_EXTSCR_C1STOPF_Pos (10U) +#define PWR_EXTSCR_C1STOPF_Msk (0x1UL << PWR_EXTSCR_C1STOPF_Pos) /*!< 0x00000400 */ +#define PWR_EXTSCR_C1STOPF PWR_EXTSCR_C1STOPF_Msk /*!< System stop0 or stop1 flag for CPU1 */ + +#define PWR_EXTSCR_C2SBF_Pos (11U) +#define PWR_EXTSCR_C2SBF_Msk (0x1UL << PWR_EXTSCR_C2SBF_Pos) /*!< 0x00000800 */ +#define PWR_EXTSCR_C2SBF PWR_EXTSCR_C2SBF_Msk /*!< System standby flag for CPU2 */ +#define PWR_EXTSCR_C2STOP2F_Pos (12U) +#define PWR_EXTSCR_C2STOP2F_Msk (0x1UL << PWR_EXTSCR_C2STOP2F_Pos) /*!< 0x00001000 */ +#define PWR_EXTSCR_C2STOP2F PWR_EXTSCR_C2STOP2F_Msk /*!< System stop2 flag for CPU2 */ +#define PWR_EXTSCR_C2STOPF_Pos (13U) +#define PWR_EXTSCR_C2STOPF_Msk (0x1UL << PWR_EXTSCR_C2STOPF_Pos) /*!< 0x00002000 */ +#define PWR_EXTSCR_C2STOPF PWR_EXTSCR_C2STOPF_Msk /*!< System stop0 or stop1 flag for CPU2 */ + +#define PWR_EXTSCR_C1DS_Pos (14U) +#define PWR_EXTSCR_C1DS_Msk (0x1UL << PWR_EXTSCR_C1DS_Pos) /*!< 0x00004000 */ +#define PWR_EXTSCR_C1DS PWR_EXTSCR_C1DS_Msk /*!< CPU1 deepsleep mode flag */ +#define PWR_EXTSCR_C2DS_Pos (15U) +#define PWR_EXTSCR_C2DS_Msk (0x1UL << PWR_EXTSCR_C2DS_Pos) /*!< 0x00008000 */ +#define PWR_EXTSCR_C2DS PWR_EXTSCR_C2DS_Msk /*!< CPU2 deepsleep mode flag */ + +/******************** Bit definition for PWR_SECCFGR register ********************/ +#define PWR_SECCFGR_C2EWILA_Pos (15U) +#define PWR_SECCFGR_C2EWILA_Msk (0x1UL << PWR_SECCFGR_C2EWILA_Pos) /*!< 0x00008000 */ +#define PWR_SECCFGR_C2EWILA PWR_SECCFGR_C2EWILA_Msk /*!< CPU2 illegal access interrupt enable */ + +/******************** Bit definition for PWR_SUBGHZSPICR register ********************/ +#define PWR_SUBGHZSPICR_NSS_Pos (15U) +#define PWR_SUBGHZSPICR_NSS_Msk (0x1UL << PWR_SUBGHZSPICR_NSS_Pos) /*!< 0x00008000 */ +#define PWR_SUBGHZSPICR_NSS PWR_SUBGHZSPICR_NSS_Msk /*!< Sub-GHz radio SUBGHZSPI_NSS control */ + +/******************** Bit definition for PWR_RSSCMDR register ********************/ +#define PWR_RSSCMDR_RSSCMD_Pos (0U) +#define PWR_RSSCMDR_RSSCMD_Msk (0xFFUL << PWR_RSSCMDR_RSSCMD_Pos) /*!< 0x000000FF */ +#define PWR_RSSCMDR_RSSCMD PWR_RSSCMDR_RSSCMD_Msk /*!< RSS command */ +#define PWR_RSSCMDR_RSSCMD_0 (0x01UL << PWR_RSSCMDR_RSSCMD_Pos) /*!< 0x00000001 */ +#define PWR_RSSCMDR_RSSCMD_1 (0x02UL << PWR_RSSCMDR_RSSCMD_Pos) /*!< 0x00000002 */ +#define PWR_RSSCMDR_RSSCMD_2 (0x04UL << PWR_RSSCMDR_RSSCMD_Pos) /*!< 0x00000004 */ +#define PWR_RSSCMDR_RSSCMD_3 (0x08UL << PWR_RSSCMDR_RSSCMD_Pos) /*!< 0x00000008 */ +#define PWR_RSSCMDR_RSSCMD_4 (0x10UL << PWR_RSSCMDR_RSSCMD_Pos) /*!< 0x00000010 */ +#define PWR_RSSCMDR_RSSCMD_5 (0x20UL << PWR_RSSCMDR_RSSCMD_Pos) /*!< 0x00000020 */ +#define PWR_RSSCMDR_RSSCMD_6 (0x40UL << PWR_RSSCMDR_RSSCMD_Pos) /*!< 0x00000040 */ +#define PWR_RSSCMDR_RSSCMD_7 (0x80UL << PWR_RSSCMDR_RSSCMD_Pos) /*!< 0x00000080 */ + +/******************************************************************************/ +/* */ +/* Reset and Clock Control */ +/* */ +/******************************************************************************/ + +/******************** Bit definition for RCC_CR register *****************/ +#define RCC_CR_MSION_Pos (0U) +#define RCC_CR_MSION_Msk (0x1UL << RCC_CR_MSION_Pos) /*!< 0x00000001 */ +#define RCC_CR_MSION RCC_CR_MSION_Msk /*!< Internal Multi Speed oscillator (MSI) clock enable */ +#define RCC_CR_MSIRDY_Pos (1U) +#define RCC_CR_MSIRDY_Msk (0x1UL << RCC_CR_MSIRDY_Pos) /*!< 0x00000002 */ +#define RCC_CR_MSIRDY RCC_CR_MSIRDY_Msk /*!< Internal Multi Speed oscillator (MSI) clock ready flag */ +#define RCC_CR_MSIPLLEN_Pos (2U) +#define RCC_CR_MSIPLLEN_Msk (0x1UL << RCC_CR_MSIPLLEN_Pos) /*!< 0x00000004 */ +#define RCC_CR_MSIPLLEN RCC_CR_MSIPLLEN_Msk /*!< Internal Multi Speed oscillator (MSI) PLL enable */ +#define RCC_CR_MSIRGSEL_Pos (3U) +#define RCC_CR_MSIRGSEL_Msk (0x1UL << RCC_CR_MSIRGSEL_Pos) /*!< 0x00000008 */ +#define RCC_CR_MSIRGSEL RCC_CR_MSIRGSEL_Msk /*!< Internal Multi Speed oscillator (MSI) range selection */ + +/*!< MSIRANGE configuration : 12 frequency ranges available */ +#define RCC_CR_MSIRANGE_Pos (4U) +#define RCC_CR_MSIRANGE_Msk (0xFUL << RCC_CR_MSIRANGE_Pos) /*!< 0x000000F0 */ +#define RCC_CR_MSIRANGE RCC_CR_MSIRANGE_Msk /*!< Internal Multi Speed oscillator (MSI) clock Range */ +#define RCC_CR_MSIRANGE_0 (0x0UL << RCC_CR_MSIRANGE_Pos) /*!< 0x00000000 */ +#define RCC_CR_MSIRANGE_1 (0x1UL << RCC_CR_MSIRANGE_Pos) /*!< 0x00000010 */ +#define RCC_CR_MSIRANGE_2 (0x2UL << RCC_CR_MSIRANGE_Pos) /*!< 0x00000020 */ +#define RCC_CR_MSIRANGE_3 (0x3UL << RCC_CR_MSIRANGE_Pos) /*!< 0x00000030 */ +#define RCC_CR_MSIRANGE_4 (0x4UL << RCC_CR_MSIRANGE_Pos) /*!< 0x00000040 */ +#define RCC_CR_MSIRANGE_5 (0x5UL << RCC_CR_MSIRANGE_Pos) /*!< 0x00000050 */ +#define RCC_CR_MSIRANGE_6 (0x6UL << RCC_CR_MSIRANGE_Pos) /*!< 0x00000060 */ +#define RCC_CR_MSIRANGE_7 (0x7UL << RCC_CR_MSIRANGE_Pos) /*!< 0x00000070 */ +#define RCC_CR_MSIRANGE_8 (0x8UL << RCC_CR_MSIRANGE_Pos) /*!< 0x00000080 */ +#define RCC_CR_MSIRANGE_9 (0x9UL << RCC_CR_MSIRANGE_Pos) /*!< 0x00000090 */ +#define RCC_CR_MSIRANGE_10 (0xAUL << RCC_CR_MSIRANGE_Pos) /*!< 0x000000A0 */ +#define RCC_CR_MSIRANGE_11 (0xBUL << RCC_CR_MSIRANGE_Pos) /*!< 0x000000B0 */ + +#define RCC_CR_HSION_Pos (8U) +#define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos) /*!< 0x00000100 */ +#define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed oscillator (HSI16) clock enable */ +#define RCC_CR_HSIKERON_Pos (9U) +#define RCC_CR_HSIKERON_Msk (0x1UL << RCC_CR_HSIKERON_Pos) /*!< 0x00000200 */ +#define RCC_CR_HSIKERON RCC_CR_HSIKERON_Msk /*!< Internal High Speed oscillator (HSI16) clock enable for some IPs Kernel */ +#define RCC_CR_HSIRDY_Pos (10U) +#define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos) /*!< 0x00000400 */ +#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed oscillator (HSI16) clock ready flag */ +#define RCC_CR_HSIASFS_Pos (11U) +#define RCC_CR_HSIASFS_Msk (0x1UL << RCC_CR_HSIASFS_Pos) /*!< 0x00000800 */ +#define RCC_CR_HSIASFS RCC_CR_HSIASFS_Msk /*!< HSI16 Automatic Start from Stop */ +#define RCC_CR_HSIKERDY_Pos (12U) +#define RCC_CR_HSIKERDY_Msk (0x1UL << RCC_CR_HSIKERDY_Pos) /*!< 0x00001000 */ +#define RCC_CR_HSIKERDY RCC_CR_HSIKERDY_Msk /*!< Internal High Speed oscillator (HSI16) clock enable for some IPs Kernel ready flag*/ + +#define RCC_CR_HSEON_Pos (16U) +#define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos) /*!< 0x00010000 */ +#define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed oscillator (HSE) clock enable */ +#define RCC_CR_HSERDY_Pos (17U) +#define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */ +#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed oscillator (HSE) clock ready */ +#define RCC_CR_CSSON_Pos (19U) +#define RCC_CR_CSSON_Msk (0x1UL << RCC_CR_CSSON_Pos) /*!< 0x00080000 */ +#define RCC_CR_CSSON RCC_CR_CSSON_Msk /*!< HSE Clock Security System enable */ +#define RCC_CR_HSEPRE_Pos (20U) +#define RCC_CR_HSEPRE_Msk (0x1UL << RCC_CR_HSEPRE_Pos) /*!< 0x00100000 */ +#define RCC_CR_HSEPRE RCC_CR_HSEPRE_Msk /*!< HSE sysclk prescaler */ +#define RCC_CR_HSEBYPPWR_Pos (21U) +#define RCC_CR_HSEBYPPWR_Msk (0x1UL << RCC_CR_HSEBYPPWR_Pos) /*!< 0x00200000 */ +#define RCC_CR_HSEBYPPWR RCC_CR_HSEBYPPWR_Msk /*!< Enable HSE32 VDDTCXO */ + +#define RCC_CR_PLLON_Pos (24U) +#define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos) /*!< 0x01000000 */ +#define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< System PLL clock enable */ +#define RCC_CR_PLLRDY_Pos (25U) +#define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */ +#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< System PLL clock ready */ + +/******************** Bit definition for RCC_ICSCR register ***************/ +/*!< MSICAL configuration */ +#define RCC_ICSCR_MSICAL_Pos (0U) +#define RCC_ICSCR_MSICAL_Msk (0xFFUL << RCC_ICSCR_MSICAL_Pos) /*!< 0x000000FF */ +#define RCC_ICSCR_MSICAL RCC_ICSCR_MSICAL_Msk /*!< MSICAL[7:0] bits */ + +/*!< MSITRIM configuration */ +#define RCC_ICSCR_MSITRIM_Pos (8U) +#define RCC_ICSCR_MSITRIM_Msk (0xFFUL << RCC_ICSCR_MSITRIM_Pos) /*!< 0x0000FF00 */ +#define RCC_ICSCR_MSITRIM RCC_ICSCR_MSITRIM_Msk /*!< MSITRIM[7:0] bits */ + +/*!< HSICAL configuration */ +#define RCC_ICSCR_HSICAL_Pos (16U) +#define RCC_ICSCR_HSICAL_Msk (0xFFUL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00FF0000 */ +#define RCC_ICSCR_HSICAL RCC_ICSCR_HSICAL_Msk /*!< HSICAL[7:0] bits */ + +/*!< HSITRIM configuration */ +#define RCC_ICSCR_HSITRIM_Pos (24U) +#define RCC_ICSCR_HSITRIM_Msk (0x7FUL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x7F000000 */ +#define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk /*!< HSITRIM[6:0] bits */ + +/******************** Bit definition for RCC_CFGR register ******************/ +/*!< SW configuration */ +#define RCC_CFGR_SW_Pos (0U) +#define RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos) /*!< 0x00000003 */ +#define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */ +#define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos) /*!< 0x00000001 */ +#define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos) /*!< 0x00000002 */ + +/*!< SWS configuration */ +#define RCC_CFGR_SWS_Pos (2U) +#define RCC_CFGR_SWS_Msk (0x3UL << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */ +#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */ +#define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */ +#define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */ + +/*!< HPRE configuration */ +#define RCC_CFGR_HPRE_Pos (4U) +#define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */ +#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */ +#define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */ +#define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */ +#define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */ +#define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */ + +/*!< PPRE1 configuration */ +#define RCC_CFGR_PPRE1_Pos (8U) +#define RCC_CFGR_PPRE1_Msk (0x7UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000700 */ +#define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */ +#define RCC_CFGR_PPRE1_0 (0x1UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000100 */ +#define RCC_CFGR_PPRE1_1 (0x2UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */ +#define RCC_CFGR_PPRE1_2 (0x4UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */ + +/*!< PPRE2 configuration */ +#define RCC_CFGR_PPRE2_Pos (11U) +#define RCC_CFGR_PPRE2_Msk (0x7UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00003800 */ +#define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */ +#define RCC_CFGR_PPRE2_0 (0x1UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00000800 */ +#define RCC_CFGR_PPRE2_1 (0x2UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */ +#define RCC_CFGR_PPRE2_2 (0x4UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */ + +/*!< STOPWUCK configuration */ +#define RCC_CFGR_STOPWUCK_Pos (15U) +#define RCC_CFGR_STOPWUCK_Msk (0x1UL << RCC_CFGR_STOPWUCK_Pos) /*!< 0x00008000 */ +#define RCC_CFGR_STOPWUCK RCC_CFGR_STOPWUCK_Msk /*!< Wake Up from stop and CSS backup clock selection */ + +/*!< HPREF configuration */ +#define RCC_CFGR_HPREF_Pos (16U) +#define RCC_CFGR_HPREF_Msk (0x1UL << RCC_CFGR_HPREF_Pos) /*!< 0x00010000 */ +#define RCC_CFGR_HPREF RCC_CFGR_HPREF_Msk /*!< AHB prescaler flag */ + +/*!< PPRE1F configuration */ +#define RCC_CFGR_PPRE1F_Pos (17U) +#define RCC_CFGR_PPRE1F_Msk (0x1UL << RCC_CFGR_PPRE1F_Pos) /*!< 0x00020000 */ +#define RCC_CFGR_PPRE1F RCC_CFGR_PPRE1F_Msk /*!< CPU1 APB1 prescaler flag */ + +/*!< PPRE2F configuration */ +#define RCC_CFGR_PPRE2F_Pos (18U) +#define RCC_CFGR_PPRE2F_Msk (0x1UL << RCC_CFGR_PPRE2F_Pos) /*!< 0x00040000 */ +#define RCC_CFGR_PPRE2F RCC_CFGR_PPRE2F_Msk /*!< APB2 prescaler flag */ + +/*!< MCOSEL configuration */ +#define RCC_CFGR_MCOSEL_Pos (24U) +#define RCC_CFGR_MCOSEL_Msk (0xFUL << RCC_CFGR_MCOSEL_Pos) /*!< 0x0F000000 */ +#define RCC_CFGR_MCOSEL RCC_CFGR_MCOSEL_Msk /*!< MCOSEL [3:0] bits (Clock output selection) */ +#define RCC_CFGR_MCOSEL_0 (0x1UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x01000000 */ +#define RCC_CFGR_MCOSEL_1 (0x2UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x02000000 */ +#define RCC_CFGR_MCOSEL_2 (0x4UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x04000000 */ +#define RCC_CFGR_MCOSEL_3 (0x8UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x08000000 */ + +/*!< MCOPRE configuration */ +#define RCC_CFGR_MCOPRE_Pos (28U) +#define RCC_CFGR_MCOPRE_Msk (0x7UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x70000000 */ +#define RCC_CFGR_MCOPRE RCC_CFGR_MCOPRE_Msk /*!< MCO prescaler */ +#define RCC_CFGR_MCOPRE_0 (0x1UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x10000000 */ +#define RCC_CFGR_MCOPRE_1 (0x2UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x20000000 */ +#define RCC_CFGR_MCOPRE_2 (0x4UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for RCC_PLLCFGR register ***************/ +#define RCC_PLLCFGR_PLLSRC_Pos (0U) +#define RCC_PLLCFGR_PLLSRC_Msk (0x3UL << RCC_PLLCFGR_PLLSRC_Pos)/*!< 0x00000003 */ +#define RCC_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_Msk +#define RCC_PLLCFGR_PLLSRC_0 (0x1UL << RCC_PLLCFGR_PLLSRC_Pos)/*!< 0x00000001 */ +#define RCC_PLLCFGR_PLLSRC_1 (0x2UL << RCC_PLLCFGR_PLLSRC_Pos)/*!< 0x00000002 */ + +#define RCC_PLLCFGR_PLLM_Pos (4U) +#define RCC_PLLCFGR_PLLM_Msk (0x7UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000070 */ +#define RCC_PLLCFGR_PLLM RCC_PLLCFGR_PLLM_Msk +#define RCC_PLLCFGR_PLLM_0 (0x1UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000010 */ +#define RCC_PLLCFGR_PLLM_1 (0x2UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000020 */ +#define RCC_PLLCFGR_PLLM_2 (0x4UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000040 */ + +#define RCC_PLLCFGR_PLLN_Pos (8U) +#define RCC_PLLCFGR_PLLN_Msk (0x7FUL << RCC_PLLCFGR_PLLN_Pos)/*!< 0x00007F00 */ +#define RCC_PLLCFGR_PLLN RCC_PLLCFGR_PLLN_Msk +#define RCC_PLLCFGR_PLLN_0 (0x01UL << RCC_PLLCFGR_PLLN_Pos)/*!< 0x00000100 */ +#define RCC_PLLCFGR_PLLN_1 (0x02UL << RCC_PLLCFGR_PLLN_Pos)/*!< 0x00000200 */ +#define RCC_PLLCFGR_PLLN_2 (0x04UL << RCC_PLLCFGR_PLLN_Pos)/*!< 0x00000400 */ +#define RCC_PLLCFGR_PLLN_3 (0x08UL << RCC_PLLCFGR_PLLN_Pos)/*!< 0x00000800 */ +#define RCC_PLLCFGR_PLLN_4 (0x10UL << RCC_PLLCFGR_PLLN_Pos)/*!< 0x00001000 */ +#define RCC_PLLCFGR_PLLN_5 (0x20UL << RCC_PLLCFGR_PLLN_Pos)/*!< 0x00002000 */ +#define RCC_PLLCFGR_PLLN_6 (0x40UL << RCC_PLLCFGR_PLLN_Pos)/*!< 0x00004000 */ + +#define RCC_PLLCFGR_PLLPEN_Pos (16U) +#define RCC_PLLCFGR_PLLPEN_Msk (0x1UL << RCC_PLLCFGR_PLLPEN_Pos)/*!< 0x00010000 */ +#define RCC_PLLCFGR_PLLPEN RCC_PLLCFGR_PLLPEN_Msk +#define RCC_PLLCFGR_PLLP_Pos (17U) +#define RCC_PLLCFGR_PLLP_Msk (0x1FUL << RCC_PLLCFGR_PLLP_Pos)/*!< 0x003E0000 */ +#define RCC_PLLCFGR_PLLP RCC_PLLCFGR_PLLP_Msk +#define RCC_PLLCFGR_PLLP_0 (0x01UL << RCC_PLLCFGR_PLLP_Pos)/*!< 0x00020000 */ +#define RCC_PLLCFGR_PLLP_1 (0x02UL << RCC_PLLCFGR_PLLP_Pos)/*!< 0x00040000 */ +#define RCC_PLLCFGR_PLLP_2 (0x04UL << RCC_PLLCFGR_PLLP_Pos)/*!< 0x00080000 */ +#define RCC_PLLCFGR_PLLP_3 (0x08UL << RCC_PLLCFGR_PLLP_Pos)/*!< 0x00100000 */ +#define RCC_PLLCFGR_PLLP_4 (0x10UL << RCC_PLLCFGR_PLLP_Pos)/*!< 0x00200000 */ + +#define RCC_PLLCFGR_PLLQEN_Pos (24U) +#define RCC_PLLCFGR_PLLQEN_Msk (0x1UL << RCC_PLLCFGR_PLLQEN_Pos)/*!< 0x01000000 */ +#define RCC_PLLCFGR_PLLQEN RCC_PLLCFGR_PLLQEN_Msk +#define RCC_PLLCFGR_PLLQ_Pos (25U) +#define RCC_PLLCFGR_PLLQ_Msk (0x7UL << RCC_PLLCFGR_PLLQ_Pos)/*!< 0x0E000000 */ +#define RCC_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_Msk +#define RCC_PLLCFGR_PLLQ_0 (0x1UL << RCC_PLLCFGR_PLLQ_Pos)/*!< 0x02000000 */ +#define RCC_PLLCFGR_PLLQ_1 (0x2UL << RCC_PLLCFGR_PLLQ_Pos)/*!< 0x04000000 */ +#define RCC_PLLCFGR_PLLQ_2 (0x4UL << RCC_PLLCFGR_PLLQ_Pos)/*!< 0x08000000 */ + +#define RCC_PLLCFGR_PLLREN_Pos (28U) +#define RCC_PLLCFGR_PLLREN_Msk (0x1UL << RCC_PLLCFGR_PLLREN_Pos)/*!< 0x10000000 */ +#define RCC_PLLCFGR_PLLREN RCC_PLLCFGR_PLLREN_Msk +#define RCC_PLLCFGR_PLLR_Pos (29U) +#define RCC_PLLCFGR_PLLR_Msk (0x7UL << RCC_PLLCFGR_PLLR_Pos)/*!< 0xE0000000 */ +#define RCC_PLLCFGR_PLLR RCC_PLLCFGR_PLLR_Msk +#define RCC_PLLCFGR_PLLR_0 (0x1UL << RCC_PLLCFGR_PLLR_Pos)/*!< 0x20000000 */ +#define RCC_PLLCFGR_PLLR_1 (0x2UL << RCC_PLLCFGR_PLLR_Pos)/*!< 0x40000000 */ +#define RCC_PLLCFGR_PLLR_2 (0x4UL << RCC_PLLCFGR_PLLR_Pos)/*!< 0x80000000 */ + + +/******************** Bit definition for RCC_CIER register ******************/ +#define RCC_CIER_LSIRDYIE_Pos (0U) +#define RCC_CIER_LSIRDYIE_Msk (0x1UL << RCC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ +#define RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE_Msk +#define RCC_CIER_LSERDYIE_Pos (1U) +#define RCC_CIER_LSERDYIE_Msk (0x1UL << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ +#define RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE_Msk +#define RCC_CIER_MSIRDYIE_Pos (2U) +#define RCC_CIER_MSIRDYIE_Msk (0x1UL << RCC_CIER_MSIRDYIE_Pos) /*!< 0x00000004 */ +#define RCC_CIER_MSIRDYIE RCC_CIER_MSIRDYIE_Msk +#define RCC_CIER_HSIRDYIE_Pos (3U) +#define RCC_CIER_HSIRDYIE_Msk (0x1UL << RCC_CIER_HSIRDYIE_Pos) /*!< 0x00000008 */ +#define RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE_Msk +#define RCC_CIER_HSERDYIE_Pos (4U) +#define RCC_CIER_HSERDYIE_Msk (0x1UL << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000010 */ +#define RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE_Msk +#define RCC_CIER_PLLRDYIE_Pos (5U) +#define RCC_CIER_PLLRDYIE_Msk (0x1UL << RCC_CIER_PLLRDYIE_Pos)/*!< 0x00000020 */ +#define RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE_Msk +#define RCC_CIER_LSECSSIE_Pos (9U) +#define RCC_CIER_LSECSSIE_Msk (0x1UL << RCC_CIER_LSECSSIE_Pos) /*!< 0x00000200 */ +#define RCC_CIER_LSECSSIE RCC_CIER_LSECSSIE_Msk + +/******************** Bit definition for RCC_CIFR register ******************/ +#define RCC_CIFR_LSIRDYF_Pos (0U) +#define RCC_CIFR_LSIRDYF_Msk (0x1UL << RCC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ +#define RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF_Msk +#define RCC_CIFR_LSERDYF_Pos (1U) +#define RCC_CIFR_LSERDYF_Msk (0x1UL << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ +#define RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF_Msk +#define RCC_CIFR_MSIRDYF_Pos (2U) +#define RCC_CIFR_MSIRDYF_Msk (0x1UL << RCC_CIFR_MSIRDYF_Pos) /*!< 0x00000004 */ +#define RCC_CIFR_MSIRDYF RCC_CIFR_MSIRDYF_Msk +#define RCC_CIFR_HSIRDYF_Pos (3U) +#define RCC_CIFR_HSIRDYF_Msk (0x1UL << RCC_CIFR_HSIRDYF_Pos) /*!< 0x00000008 */ +#define RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF_Msk +#define RCC_CIFR_HSERDYF_Pos (4U) +#define RCC_CIFR_HSERDYF_Msk (0x1UL << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000010 */ +#define RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF_Msk +#define RCC_CIFR_PLLRDYF_Pos (5U) +#define RCC_CIFR_PLLRDYF_Msk (0x1UL << RCC_CIFR_PLLRDYF_Pos)/*!< 0x00000020 */ +#define RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF_Msk +#define RCC_CIFR_CSSF_Pos (8U) +#define RCC_CIFR_CSSF_Msk (0x1UL << RCC_CIFR_CSSF_Pos) /*!< 0x00000100 */ +#define RCC_CIFR_CSSF RCC_CIFR_CSSF_Msk +#define RCC_CIFR_LSECSSF_Pos (9U) +#define RCC_CIFR_LSECSSF_Msk (0x1UL << RCC_CIFR_LSECSSF_Pos) /*!< 0x00000200 */ +#define RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF_Msk + +/******************** Bit definition for RCC_CICR register ******************/ +#define RCC_CICR_LSIRDYC_Pos (0U) +#define RCC_CICR_LSIRDYC_Msk (0x1UL << RCC_CICR_LSIRDYC_Pos) /*!< 0x00000001 */ +#define RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC_Msk +#define RCC_CICR_LSERDYC_Pos (1U) +#define RCC_CICR_LSERDYC_Msk (0x1UL << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */ +#define RCC_CICR_LSERDYC RCC_CICR_LSERDYC_Msk +#define RCC_CICR_MSIRDYC_Pos (2U) +#define RCC_CICR_MSIRDYC_Msk (0x1UL << RCC_CICR_MSIRDYC_Pos) /*!< 0x00000004 */ +#define RCC_CICR_MSIRDYC RCC_CICR_MSIRDYC_Msk +#define RCC_CICR_HSIRDYC_Pos (3U) +#define RCC_CICR_HSIRDYC_Msk (0x1UL << RCC_CICR_HSIRDYC_Pos) /*!< 0x00000008 */ +#define RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC_Msk +#define RCC_CICR_HSERDYC_Pos (4U) +#define RCC_CICR_HSERDYC_Msk (0x1UL << RCC_CICR_HSERDYC_Pos) /*!< 0x00000010 */ +#define RCC_CICR_HSERDYC RCC_CICR_HSERDYC_Msk +#define RCC_CICR_PLLRDYC_Pos (5U) +#define RCC_CICR_PLLRDYC_Msk (0x1UL << RCC_CICR_PLLRDYC_Pos)/*!< 0x00000020 */ +#define RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC_Msk +#define RCC_CICR_CSSC_Pos (8U) +#define RCC_CICR_CSSC_Msk (0x1UL << RCC_CICR_CSSC_Pos) /*!< 0x00000100 */ +#define RCC_CICR_CSSC RCC_CICR_CSSC_Msk +#define RCC_CICR_LSECSSC_Pos (9U) +#define RCC_CICR_LSECSSC_Msk (0x1UL << RCC_CICR_LSECSSC_Pos) /*!< 0x00000200 */ +#define RCC_CICR_LSECSSC RCC_CICR_LSECSSC_Msk + +/******************** Bit definition for RCC_AHB1RSTR register **************/ +#define RCC_AHB1RSTR_DMA1RST_Pos (0U) +#define RCC_AHB1RSTR_DMA1RST_Msk (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos)/*!< 0x00000001 */ +#define RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk +#define RCC_AHB1RSTR_DMA2RST_Pos (1U) +#define RCC_AHB1RSTR_DMA2RST_Msk (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos)/*!< 0x00000002 */ +#define RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk +#define RCC_AHB1RSTR_DMAMUX1RST_Pos (2U) +#define RCC_AHB1RSTR_DMAMUX1RST_Msk (0x1UL << RCC_AHB1RSTR_DMAMUX1RST_Pos)/*!< 0x00000004 */ +#define RCC_AHB1RSTR_DMAMUX1RST RCC_AHB1RSTR_DMAMUX1RST_Msk +#define RCC_AHB1RSTR_CRCRST_Pos (12U) +#define RCC_AHB1RSTR_CRCRST_Msk (0x1UL << RCC_AHB1RSTR_CRCRST_Pos)/*!< 0x00001000 */ +#define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk + +/******************** Bit definition for RCC_AHB2RSTR register ***************/ +#define RCC_AHB2RSTR_GPIOARST_Pos (0U) +#define RCC_AHB2RSTR_GPIOARST_Msk (0x1UL << RCC_AHB2RSTR_GPIOARST_Pos)/*!< 0x00000001 */ +#define RCC_AHB2RSTR_GPIOARST RCC_AHB2RSTR_GPIOARST_Msk +#define RCC_AHB2RSTR_GPIOBRST_Pos (1U) +#define RCC_AHB2RSTR_GPIOBRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOBRST_Pos)/*!< 0x00000002 */ +#define RCC_AHB2RSTR_GPIOBRST RCC_AHB2RSTR_GPIOBRST_Msk +#define RCC_AHB2RSTR_GPIOCRST_Pos (2U) +#define RCC_AHB2RSTR_GPIOCRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOCRST_Pos)/*!< 0x00000004 */ +#define RCC_AHB2RSTR_GPIOCRST RCC_AHB2RSTR_GPIOCRST_Msk +#define RCC_AHB2RSTR_GPIOHRST_Pos (7U) +#define RCC_AHB2RSTR_GPIOHRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOHRST_Pos)/*!< 0x00000080 */ +#define RCC_AHB2RSTR_GPIOHRST RCC_AHB2RSTR_GPIOHRST_Msk + +/******************** Bit definition for RCC_AHB3RSTR register ***************/ +#define RCC_AHB3RSTR_PKARST_Pos (16U) +#define RCC_AHB3RSTR_PKARST_Msk (0x1UL << RCC_AHB3RSTR_PKARST_Pos) /*!< 0x00010000 */ +#define RCC_AHB3RSTR_PKARST RCC_AHB3RSTR_PKARST_Msk +#define RCC_AHB3RSTR_AESRST_Pos (17U) +#define RCC_AHB3RSTR_AESRST_Msk (0x1UL << RCC_AHB3RSTR_AESRST_Pos)/*!< 0x00020000 */ +#define RCC_AHB3RSTR_AESRST RCC_AHB3RSTR_AESRST_Msk +#define RCC_AHB3RSTR_RNGRST_Pos (18U) +#define RCC_AHB3RSTR_RNGRST_Msk (0x1UL << RCC_AHB3RSTR_RNGRST_Pos)/*!< 0x00040000 */ +#define RCC_AHB3RSTR_RNGRST RCC_AHB3RSTR_RNGRST_Msk + +#define RCC_AHB3RSTR_HSEMRST_Pos (19U) +#define RCC_AHB3RSTR_HSEMRST_Msk (0x1UL << RCC_AHB3RSTR_HSEMRST_Pos)/*!< 0x00080000 */ +#define RCC_AHB3RSTR_HSEMRST RCC_AHB3RSTR_HSEMRST_Msk +#define RCC_AHB3RSTR_IPCCRST_Pos (20U) +#define RCC_AHB3RSTR_IPCCRST_Msk (0x1UL << RCC_AHB3RSTR_IPCCRST_Pos)/*!< 0x00100000 */ +#define RCC_AHB3RSTR_IPCCRST RCC_AHB3RSTR_IPCCRST_Msk +#define RCC_AHB3RSTR_FLASHRST_Pos (25U) +#define RCC_AHB3RSTR_FLASHRST_Msk (0x1UL << RCC_AHB3RSTR_FLASHRST_Pos) /*!< 0x02000000 */ +#define RCC_AHB3RSTR_FLASHRST RCC_AHB3RSTR_FLASHRST_Msk + +/******************** Bit definition for RCC_APB1RSTR1 register **************/ +#define RCC_APB1RSTR1_TIM2RST_Pos (0U) +#define RCC_APB1RSTR1_TIM2RST_Msk (0x1UL << RCC_APB1RSTR1_TIM2RST_Pos)/*!< 0x00000001 */ +#define RCC_APB1RSTR1_TIM2RST RCC_APB1RSTR1_TIM2RST_Msk +#define RCC_APB1RSTR1_SPI2RST_Pos (14U) +#define RCC_APB1RSTR1_SPI2RST_Msk (0x1UL << RCC_APB1RSTR1_SPI2RST_Pos)/*!< 0x00004000 */ +#define RCC_APB1RSTR1_SPI2RST RCC_APB1RSTR1_SPI2RST_Msk +#define RCC_APB1RSTR1_USART2RST_Pos (17U) +#define RCC_APB1RSTR1_USART2RST_Msk (0x1UL << RCC_APB1RSTR1_USART2RST_Pos)/*!< 0x00020000 */ +#define RCC_APB1RSTR1_USART2RST RCC_APB1RSTR1_USART2RST_Msk +#define RCC_APB1RSTR1_I2C1RST_Pos (21U) +#define RCC_APB1RSTR1_I2C1RST_Msk (0x1UL << RCC_APB1RSTR1_I2C1RST_Pos)/*!< 0x00200000 */ +#define RCC_APB1RSTR1_I2C1RST RCC_APB1RSTR1_I2C1RST_Msk +#define RCC_APB1RSTR1_I2C2RST_Pos (22U) +#define RCC_APB1RSTR1_I2C2RST_Msk (0x1UL << RCC_APB1RSTR1_I2C2RST_Pos)/*!< 0x00400000 */ +#define RCC_APB1RSTR1_I2C2RST RCC_APB1RSTR1_I2C2RST_Msk +#define RCC_APB1RSTR1_I2C3RST_Pos (23U) +#define RCC_APB1RSTR1_I2C3RST_Msk (0x1UL << RCC_APB1RSTR1_I2C3RST_Pos)/*!< 0x00800000 */ +#define RCC_APB1RSTR1_I2C3RST RCC_APB1RSTR1_I2C3RST_Msk +#define RCC_APB1RSTR1_DACRST_Pos (29U) +#define RCC_APB1RSTR1_DACRST_Msk (0x1UL << RCC_APB1RSTR1_DACRST_Pos)/*!< 0x20000000 */ +#define RCC_APB1RSTR1_DACRST RCC_APB1RSTR1_DACRST_Msk +#define RCC_APB1RSTR1_LPTIM1RST_Pos (31U) +#define RCC_APB1RSTR1_LPTIM1RST_Msk (0x1UL << RCC_APB1RSTR1_LPTIM1RST_Pos)/*!< 0x80000000 */ +#define RCC_APB1RSTR1_LPTIM1RST RCC_APB1RSTR1_LPTIM1RST_Msk + +/******************** Bit definition for RCC_APB1RSTR2 register **************/ +#define RCC_APB1RSTR2_LPUART1RST_Pos (0U) +#define RCC_APB1RSTR2_LPUART1RST_Msk (0x1UL << RCC_APB1RSTR2_LPUART1RST_Pos)/*!< 0x00000001 */ +#define RCC_APB1RSTR2_LPUART1RST RCC_APB1RSTR2_LPUART1RST_Msk +#define RCC_APB1RSTR2_LPTIM2RST_Pos (5U) +#define RCC_APB1RSTR2_LPTIM2RST_Msk (0x1UL << RCC_APB1RSTR2_LPTIM2RST_Pos)/*!< 0x00000020 */ +#define RCC_APB1RSTR2_LPTIM2RST RCC_APB1RSTR2_LPTIM2RST_Msk +#define RCC_APB1RSTR2_LPTIM3RST_Pos (6U) +#define RCC_APB1RSTR2_LPTIM3RST_Msk (0x1UL << RCC_APB1RSTR2_LPTIM3RST_Pos)/*!< 0x00000040 */ +#define RCC_APB1RSTR2_LPTIM3RST RCC_APB1RSTR2_LPTIM3RST_Msk + +/******************** Bit definition for RCC_APB2RSTR register **************/ +#define RCC_APB2RSTR_ADCRST_Pos (9U) +#define RCC_APB2RSTR_ADCRST_Msk (0x1UL << RCC_APB2RSTR_ADCRST_Pos)/*!< 0x00000200 */ +#define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk +#define RCC_APB2RSTR_TIM1RST_Pos (11U) +#define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos)/*!< 0x00000800 */ +#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk +#define RCC_APB2RSTR_SPI1RST_Pos (12U) +#define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos)/*!< 0x00001000 */ +#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk +#define RCC_APB2RSTR_USART1RST_Pos (14U) +#define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos)/*!< 0x00004000 */ +#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk +#define RCC_APB2RSTR_TIM16RST_Pos (17U) +#define RCC_APB2RSTR_TIM16RST_Msk (0x1UL << RCC_APB2RSTR_TIM16RST_Pos)/*!< 0x00020000 */ +#define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk +#define RCC_APB2RSTR_TIM17RST_Pos (18U) +#define RCC_APB2RSTR_TIM17RST_Msk (0x1UL << RCC_APB2RSTR_TIM17RST_Pos)/*!< 0x00040000 */ +#define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk + +/******************** Bit definition for RCC_APB3RSTR register **************/ +#define RCC_APB3RSTR_SUBGHZSPIRST_Pos (0U) +#define RCC_APB3RSTR_SUBGHZSPIRST_Msk (0x1UL << RCC_APB3RSTR_SUBGHZSPIRST_Pos) /*!< 0x00000001 */ +#define RCC_APB3RSTR_SUBGHZSPIRST RCC_APB3RSTR_SUBGHZSPIRST_Msk + +/******************** Bit definition for RCC_AHB1ENR register ****************/ +#define RCC_AHB1ENR_DMA1EN_Pos (0U) +#define RCC_AHB1ENR_DMA1EN_Msk (0x1UL << RCC_AHB1ENR_DMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk +#define RCC_AHB1ENR_DMA2EN_Pos (1U) +#define RCC_AHB1ENR_DMA2EN_Msk (0x1UL << RCC_AHB1ENR_DMA2EN_Pos) /*!< 0x00000002 */ +#define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk +#define RCC_AHB1ENR_DMAMUX1EN_Pos (2U) +#define RCC_AHB1ENR_DMAMUX1EN_Msk (0x1UL << RCC_AHB1ENR_DMAMUX1EN_Pos)/*!< 0x00000004 */ +#define RCC_AHB1ENR_DMAMUX1EN RCC_AHB1ENR_DMAMUX1EN_Msk +#define RCC_AHB1ENR_CRCEN_Pos (12U) +#define RCC_AHB1ENR_CRCEN_Msk (0x1UL << RCC_AHB1ENR_CRCEN_Pos) /*!< 0x00001000 */ +#define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk + +/******************** Bit definition for RCC_AHB2ENR register ***************/ +#define RCC_AHB2ENR_GPIOAEN_Pos (0U) +#define RCC_AHB2ENR_GPIOAEN_Msk (0x1UL << RCC_AHB2ENR_GPIOAEN_Pos) /*!< 0x00000001 */ +#define RCC_AHB2ENR_GPIOAEN RCC_AHB2ENR_GPIOAEN_Msk +#define RCC_AHB2ENR_GPIOBEN_Pos (1U) +#define RCC_AHB2ENR_GPIOBEN_Msk (0x1UL << RCC_AHB2ENR_GPIOBEN_Pos) /*!< 0x00000002 */ +#define RCC_AHB2ENR_GPIOBEN RCC_AHB2ENR_GPIOBEN_Msk +#define RCC_AHB2ENR_GPIOCEN_Pos (2U) +#define RCC_AHB2ENR_GPIOCEN_Msk (0x1UL << RCC_AHB2ENR_GPIOCEN_Pos) /*!< 0x00000004 */ +#define RCC_AHB2ENR_GPIOCEN RCC_AHB2ENR_GPIOCEN_Msk +#define RCC_AHB2ENR_GPIOHEN_Pos (7U) +#define RCC_AHB2ENR_GPIOHEN_Msk (0x1UL << RCC_AHB2ENR_GPIOHEN_Pos) /*!< 0x00000080 */ +#define RCC_AHB2ENR_GPIOHEN RCC_AHB2ENR_GPIOHEN_Msk + +/******************** Bit definition for RCC_AHB3ENR register ***************/ +#define RCC_AHB3ENR_PKAEN_Pos (16U) +#define RCC_AHB3ENR_PKAEN_Msk (0x1UL << RCC_AHB3ENR_PKAEN_Pos) /*!< 0x00010000 */ +#define RCC_AHB3ENR_PKAEN RCC_AHB3ENR_PKAEN_Msk +#define RCC_AHB3ENR_AESEN_Pos (17U) +#define RCC_AHB3ENR_AESEN_Msk (0x1UL << RCC_AHB3ENR_AESEN_Pos)/*!< 0x00020000 */ +#define RCC_AHB3ENR_AESEN RCC_AHB3ENR_AESEN_Msk +#define RCC_AHB3ENR_RNGEN_Pos (18U) +#define RCC_AHB3ENR_RNGEN_Msk (0x1UL << RCC_AHB3ENR_RNGEN_Pos) /*!< 0x00040000 */ +#define RCC_AHB3ENR_RNGEN RCC_AHB3ENR_RNGEN_Msk +#define RCC_AHB3ENR_HSEMEN_Pos (19U) +#define RCC_AHB3ENR_HSEMEN_Msk (0x1UL << RCC_AHB3ENR_HSEMEN_Pos) /*!< 0x00080000 */ +#define RCC_AHB3ENR_HSEMEN RCC_AHB3ENR_HSEMEN_Msk +#define RCC_AHB3ENR_IPCCEN_Pos (20U) +#define RCC_AHB3ENR_IPCCEN_Msk (0x1UL << RCC_AHB3ENR_IPCCEN_Pos) /*!< 0x00100000 */ +#define RCC_AHB3ENR_IPCCEN RCC_AHB3ENR_IPCCEN_Msk +#define RCC_AHB3ENR_FLASHEN_Pos (25U) +#define RCC_AHB3ENR_FLASHEN_Msk (0x1UL << RCC_AHB3ENR_FLASHEN_Pos) /*!< 0x02000000 */ +#define RCC_AHB3ENR_FLASHEN RCC_AHB3ENR_FLASHEN_Msk + +/******************** Bit definition for RCC_APB1ENR1 register **************/ +#define RCC_APB1ENR1_TIM2EN_Pos (0U) +#define RCC_APB1ENR1_TIM2EN_Msk (0x1UL << RCC_APB1ENR1_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_APB1ENR1_TIM2EN RCC_APB1ENR1_TIM2EN_Msk +#define RCC_APB1ENR1_RTCAPBEN_Pos (10U) +#define RCC_APB1ENR1_RTCAPBEN_Msk (0x1UL << RCC_APB1ENR1_RTCAPBEN_Pos)/*!< 0x00000400 */ +#define RCC_APB1ENR1_RTCAPBEN RCC_APB1ENR1_RTCAPBEN_Msk +#define RCC_APB1ENR1_WWDGEN_Pos (11U) +#define RCC_APB1ENR1_WWDGEN_Msk (0x1UL << RCC_APB1ENR1_WWDGEN_Pos) /*!< 0x00000800 */ +#define RCC_APB1ENR1_WWDGEN RCC_APB1ENR1_WWDGEN_Msk +#define RCC_APB1ENR1_SPI2EN_Pos (14U) +#define RCC_APB1ENR1_SPI2EN_Msk (0x1UL << RCC_APB1ENR1_SPI2EN_Pos) /*!< 0x00004000 */ +#define RCC_APB1ENR1_SPI2EN RCC_APB1ENR1_SPI2EN_Msk +#define RCC_APB1ENR1_USART2EN_Pos (17U) +#define RCC_APB1ENR1_USART2EN_Msk (0x1UL << RCC_APB1ENR1_USART2EN_Pos) /*!< 0x00020000 */ +#define RCC_APB1ENR1_USART2EN RCC_APB1ENR1_USART2EN_Msk +#define RCC_APB1ENR1_I2C1EN_Pos (21U) +#define RCC_APB1ENR1_I2C1EN_Msk (0x1UL << RCC_APB1ENR1_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_APB1ENR1_I2C1EN RCC_APB1ENR1_I2C1EN_Msk +#define RCC_APB1ENR1_I2C2EN_Pos (22U) +#define RCC_APB1ENR1_I2C2EN_Msk (0x1UL << RCC_APB1ENR1_I2C2EN_Pos) /*!< 0x00400000 */ +#define RCC_APB1ENR1_I2C2EN RCC_APB1ENR1_I2C2EN_Msk +#define RCC_APB1ENR1_I2C3EN_Pos (23U) +#define RCC_APB1ENR1_I2C3EN_Msk (0x1UL << RCC_APB1ENR1_I2C3EN_Pos) /*!< 0x00800000 */ +#define RCC_APB1ENR1_I2C3EN RCC_APB1ENR1_I2C3EN_Msk +#define RCC_APB1ENR1_DACEN_Pos (29U) +#define RCC_APB1ENR1_DACEN_Msk (0x1UL << RCC_APB1ENR1_DACEN_Pos)/*!< 0x20000000 */ +#define RCC_APB1ENR1_DACEN RCC_APB1ENR1_DACEN_Msk +#define RCC_APB1ENR1_LPTIM1EN_Pos (31U) +#define RCC_APB1ENR1_LPTIM1EN_Msk (0x1UL << RCC_APB1ENR1_LPTIM1EN_Pos)/*!< 0x80000000 */ +#define RCC_APB1ENR1_LPTIM1EN RCC_APB1ENR1_LPTIM1EN_Msk + +/******************** Bit definition for RCC_APB1ENR2 register **************/ +#define RCC_APB1ENR2_LPUART1EN_Pos (0U) +#define RCC_APB1ENR2_LPUART1EN_Msk (0x1UL << RCC_APB1ENR2_LPUART1EN_Pos)/*!< 0x00000001 */ +#define RCC_APB1ENR2_LPUART1EN RCC_APB1ENR2_LPUART1EN_Msk +#define RCC_APB1ENR2_LPTIM2EN_Pos (5U) +#define RCC_APB1ENR2_LPTIM2EN_Msk (0x1UL << RCC_APB1ENR2_LPTIM2EN_Pos)/*!< 0x00000020 */ +#define RCC_APB1ENR2_LPTIM2EN RCC_APB1ENR2_LPTIM2EN_Msk +#define RCC_APB1ENR2_LPTIM3EN_Pos (6U) +#define RCC_APB1ENR2_LPTIM3EN_Msk (0x1UL << RCC_APB1ENR2_LPTIM3EN_Pos)/*!< 0x00000040 */ +#define RCC_APB1ENR2_LPTIM3EN RCC_APB1ENR2_LPTIM3EN_Msk + +/******************** Bit definition for RCC_APB2ENR register **************/ +#define RCC_APB2ENR_ADCEN_Pos (9U) +#define RCC_APB2ENR_ADCEN_Msk (0x1UL << RCC_APB2ENR_ADCEN_Pos) /*!< 0x00000200 */ +#define RCC_APB2ENR_ADCEN RCC_APB2ENR_ADCEN_Msk +#define RCC_APB2ENR_TIM1EN_Pos (11U) +#define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */ +#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk +#define RCC_APB2ENR_SPI1EN_Pos (12U) +#define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */ +#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk +#define RCC_APB2ENR_USART1EN_Pos (14U) +#define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos)/*!< 0x00004000 */ +#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk +#define RCC_APB2ENR_TIM16EN_Pos (17U) +#define RCC_APB2ENR_TIM16EN_Msk (0x1UL << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */ +#define RCC_APB2ENR_TIM16EN RCC_APB2ENR_TIM16EN_Msk +#define RCC_APB2ENR_TIM17EN_Pos (18U) +#define RCC_APB2ENR_TIM17EN_Msk (0x1UL << RCC_APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */ +#define RCC_APB2ENR_TIM17EN RCC_APB2ENR_TIM17EN_Msk + +/******************** Bit definition for RCC_APB3ENR register **************/ +#define RCC_APB3ENR_SUBGHZSPIEN_Pos (0U) +#define RCC_APB3ENR_SUBGHZSPIEN_Msk (0x1UL << RCC_APB3ENR_SUBGHZSPIEN_Pos)/*!< 0x00000001 */ +#define RCC_APB3ENR_SUBGHZSPIEN RCC_APB3ENR_SUBGHZSPIEN_Msk + +/******************** Bit definition for RCC_AHB1SMENR register ****************/ +#define RCC_AHB1SMENR_DMA1SMEN_Pos (0U) +#define RCC_AHB1SMENR_DMA1SMEN_Msk (0x1UL << RCC_AHB1SMENR_DMA1SMEN_Pos)/*!< 0x00000001 */ +#define RCC_AHB1SMENR_DMA1SMEN RCC_AHB1SMENR_DMA1SMEN_Msk +#define RCC_AHB1SMENR_DMA2SMEN_Pos (1U) +#define RCC_AHB1SMENR_DMA2SMEN_Msk (0x1UL << RCC_AHB1SMENR_DMA2SMEN_Pos)/*!< 0x00000002 */ +#define RCC_AHB1SMENR_DMA2SMEN RCC_AHB1SMENR_DMA2SMEN_Msk +#define RCC_AHB1SMENR_DMAMUX1SMEN_Pos (2U) +#define RCC_AHB1SMENR_DMAMUX1SMEN_Msk (0x1UL << RCC_AHB1SMENR_DMAMUX1SMEN_Pos)/*!< 0x00000004 */ +#define RCC_AHB1SMENR_DMAMUX1SMEN RCC_AHB1SMENR_DMAMUX1SMEN_Msk +#define RCC_AHB1SMENR_CRCSMEN_Pos (12U) +#define RCC_AHB1SMENR_CRCSMEN_Msk (0x1UL << RCC_AHB1SMENR_CRCSMEN_Pos)/*!< 0x00001000 */ +#define RCC_AHB1SMENR_CRCSMEN RCC_AHB1SMENR_CRCSMEN_Msk + +/******************** Bit definition for RCC_AHB2SMENR register ***************/ +#define RCC_AHB2SMENR_GPIOASMEN_Pos (0U) +#define RCC_AHB2SMENR_GPIOASMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOASMEN_Pos)/*!< 0x00000001 */ +#define RCC_AHB2SMENR_GPIOASMEN RCC_AHB2SMENR_GPIOASMEN_Msk +#define RCC_AHB2SMENR_GPIOBSMEN_Pos (1U) +#define RCC_AHB2SMENR_GPIOBSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOBSMEN_Pos)/*!< 0x00000002 */ +#define RCC_AHB2SMENR_GPIOBSMEN RCC_AHB2SMENR_GPIOBSMEN_Msk +#define RCC_AHB2SMENR_GPIOCSMEN_Pos (2U) +#define RCC_AHB2SMENR_GPIOCSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOCSMEN_Pos)/*!< 0x00000004 */ +#define RCC_AHB2SMENR_GPIOCSMEN RCC_AHB2SMENR_GPIOCSMEN_Msk +#define RCC_AHB2SMENR_GPIOHSMEN_Pos (7U) +#define RCC_AHB2SMENR_GPIOHSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOHSMEN_Pos)/*!< 0x00000080 */ +#define RCC_AHB2SMENR_GPIOHSMEN RCC_AHB2SMENR_GPIOHSMEN_Msk + +/******************** Bit definition for RCC_AHB3SMENR register ***************/ +#define RCC_AHB3SMENR_PKASMEN_Pos (16U) +#define RCC_AHB3SMENR_PKASMEN_Msk (0x1UL << RCC_AHB3SMENR_PKASMEN_Pos) /*!< 0x00010000 */ +#define RCC_AHB3SMENR_PKASMEN RCC_AHB3SMENR_PKASMEN_Msk +#define RCC_AHB3SMENR_AESSMEN_Pos (17U) +#define RCC_AHB3SMENR_AESSMEN_Msk (0x1UL << RCC_AHB3SMENR_AESSMEN_Pos) /*!< 0x00020000 */ +#define RCC_AHB3SMENR_AESSMEN RCC_AHB3SMENR_AESSMEN_Msk +#define RCC_AHB3SMENR_RNGSMEN_Pos (18U) +#define RCC_AHB3SMENR_RNGSMEN_Msk (0x1UL << RCC_AHB3SMENR_RNGSMEN_Pos)/*!< 0x00040000 */ +#define RCC_AHB3SMENR_RNGSMEN RCC_AHB3SMENR_RNGSMEN_Msk +#define RCC_AHB3SMENR_SRAM1SMEN_Pos (23U) +#define RCC_AHB3SMENR_SRAM1SMEN_Msk (0x1UL << RCC_AHB3SMENR_SRAM1SMEN_Pos)/*!< 0x00800000 */ +#define RCC_AHB3SMENR_SRAM1SMEN RCC_AHB3SMENR_SRAM1SMEN_Msk +#define RCC_AHB3SMENR_SRAM2SMEN_Pos (24U) +#define RCC_AHB3SMENR_SRAM2SMEN_Msk (0x1UL << RCC_AHB3SMENR_SRAM2SMEN_Pos)/*!< 0x01000000 */ +#define RCC_AHB3SMENR_SRAM2SMEN RCC_AHB3SMENR_SRAM2SMEN_Msk +#define RCC_AHB3SMENR_FLASHSMEN_Pos (25U) +#define RCC_AHB3SMENR_FLASHSMEN_Msk (0x1UL << RCC_AHB3SMENR_FLASHSMEN_Pos)/*!< 0x02000000 */ +#define RCC_AHB3SMENR_FLASHSMEN RCC_AHB3SMENR_FLASHSMEN_Msk + +/******************** Bit definition for RCC_APB1SMENR1 register **************/ +#define RCC_APB1SMENR1_TIM2SMEN_Pos (0U) +#define RCC_APB1SMENR1_TIM2SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM2SMEN_Pos)/*!< 0x00000001 */ +#define RCC_APB1SMENR1_TIM2SMEN RCC_APB1SMENR1_TIM2SMEN_Msk +#define RCC_APB1SMENR1_RTCAPBSMEN_Pos (10U) +#define RCC_APB1SMENR1_RTCAPBSMEN_Msk (0x1UL << RCC_APB1SMENR1_RTCAPBSMEN_Pos)/*!< 0x00000400 */ +#define RCC_APB1SMENR1_RTCAPBSMEN RCC_APB1SMENR1_RTCAPBSMEN_Msk +#define RCC_APB1SMENR1_WWDGSMEN_Pos (11U) +#define RCC_APB1SMENR1_WWDGSMEN_Msk (0x1UL << RCC_APB1SMENR1_WWDGSMEN_Pos)/*!< 0x00000800 */ +#define RCC_APB1SMENR1_WWDGSMEN RCC_APB1SMENR1_WWDGSMEN_Msk +#define RCC_APB1SMENR1_SPI2SMEN_Pos (14U) +#define RCC_APB1SMENR1_SPI2SMEN_Msk (0x1UL << RCC_APB1SMENR1_SPI2SMEN_Pos)/*!< 0x00004000 */ +#define RCC_APB1SMENR1_SPI2SMEN RCC_APB1SMENR1_SPI2SMEN_Msk +#define RCC_APB1SMENR1_USART2SMEN_Pos (17U) +#define RCC_APB1SMENR1_USART2SMEN_Msk (0x1UL << RCC_APB1SMENR1_USART2SMEN_Pos)/*!< 0x00020000 */ +#define RCC_APB1SMENR1_USART2SMEN RCC_APB1SMENR1_USART2SMEN_Msk +#define RCC_APB1SMENR1_I2C1SMEN_Pos (21U) +#define RCC_APB1SMENR1_I2C1SMEN_Msk (0x1UL << RCC_APB1SMENR1_I2C1SMEN_Pos)/*!< 0x00200000 */ +#define RCC_APB1SMENR1_I2C1SMEN RCC_APB1SMENR1_I2C1SMEN_Msk +#define RCC_APB1SMENR1_I2C2SMEN_Pos (22U) +#define RCC_APB1SMENR1_I2C2SMEN_Msk (0x1UL << RCC_APB1SMENR1_I2C2SMEN_Pos)/*!< 0x00400000 */ +#define RCC_APB1SMENR1_I2C2SMEN RCC_APB1SMENR1_I2C2SMEN_Msk +#define RCC_APB1SMENR1_I2C3SMEN_Pos (23U) +#define RCC_APB1SMENR1_I2C3SMEN_Msk (0x1UL << RCC_APB1SMENR1_I2C3SMEN_Pos)/*!< 0x00800000 */ +#define RCC_APB1SMENR1_I2C3SMEN RCC_APB1SMENR1_I2C3SMEN_Msk +#define RCC_APB1SMENR1_DACSMEN_Pos (29U) +#define RCC_APB1SMENR1_DACSMEN_Msk (0x1UL << RCC_APB1SMENR1_DACSMEN_Pos)/*!< 0x20000000 */ +#define RCC_APB1SMENR1_DACSMEN RCC_APB1SMENR1_DACSMEN_Msk +#define RCC_APB1SMENR1_LPTIM1SMEN_Pos (31U) +#define RCC_APB1SMENR1_LPTIM1SMEN_Msk (0x1UL << RCC_APB1SMENR1_LPTIM1SMEN_Pos)/*!< 0x80000000 */ +#define RCC_APB1SMENR1_LPTIM1SMEN RCC_APB1SMENR1_LPTIM1SMEN_Msk + +/******************** Bit definition for RCC_APB1SMENR2 register **************/ +#define RCC_APB1SMENR2_LPUART1SMEN_Pos (0U) +#define RCC_APB1SMENR2_LPUART1SMEN_Msk (0x1UL << RCC_APB1SMENR2_LPUART1SMEN_Pos)/*!< 0x00000001 */ +#define RCC_APB1SMENR2_LPUART1SMEN RCC_APB1SMENR2_LPUART1SMEN_Msk +#define RCC_APB1SMENR2_LPTIM2SMEN_Pos (5U) +#define RCC_APB1SMENR2_LPTIM2SMEN_Msk (0x1UL << RCC_APB1SMENR2_LPTIM2SMEN_Pos)/*!< 0x00000020 */ +#define RCC_APB1SMENR2_LPTIM2SMEN RCC_APB1SMENR2_LPTIM2SMEN_Msk +#define RCC_APB1SMENR2_LPTIM3SMEN_Pos (6U) +#define RCC_APB1SMENR2_LPTIM3SMEN_Msk (0x1UL << RCC_APB1SMENR2_LPTIM3SMEN_Pos)/*!< 0x00000040 */ +#define RCC_APB1SMENR2_LPTIM3SMEN RCC_APB1SMENR2_LPTIM3SMEN_Msk + +/******************** Bit definition for RCC_APB2SMENR register **************/ +#define RCC_APB2SMENR_ADCSMEN_Pos (9U) +#define RCC_APB2SMENR_ADCSMEN_Msk (0x1UL << RCC_APB2SMENR_ADCSMEN_Pos)/*!< 0x00000200 */ +#define RCC_APB2SMENR_ADCSMEN RCC_APB2SMENR_ADCSMEN_Msk +#define RCC_APB2SMENR_TIM1SMEN_Pos (11U) +#define RCC_APB2SMENR_TIM1SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM1SMEN_Pos)/*!< 0x00000800 */ +#define RCC_APB2SMENR_TIM1SMEN RCC_APB2SMENR_TIM1SMEN_Msk +#define RCC_APB2SMENR_SPI1SMEN_Pos (12U) +#define RCC_APB2SMENR_SPI1SMEN_Msk (0x1UL << RCC_APB2SMENR_SPI1SMEN_Pos)/*!< 0x00001000 */ +#define RCC_APB2SMENR_SPI1SMEN RCC_APB2SMENR_SPI1SMEN_Msk +#define RCC_APB2SMENR_USART1SMEN_Pos (14U) +#define RCC_APB2SMENR_USART1SMEN_Msk (0x1UL << RCC_APB2SMENR_USART1SMEN_Pos)/*!< 0x00004000 */ +#define RCC_APB2SMENR_USART1SMEN RCC_APB2SMENR_USART1SMEN_Msk +#define RCC_APB2SMENR_TIM16SMEN_Pos (17U) +#define RCC_APB2SMENR_TIM16SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM16SMEN_Pos)/*!< 0x00020000 */ +#define RCC_APB2SMENR_TIM16SMEN RCC_APB2SMENR_TIM16SMEN_Msk +#define RCC_APB2SMENR_TIM17SMEN_Pos (18U) +#define RCC_APB2SMENR_TIM17SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM17SMEN_Pos)/*!< 0x00040000 */ +#define RCC_APB2SMENR_TIM17SMEN RCC_APB2SMENR_TIM17SMEN_Msk + +/******************** Bit definition for RCC_APB3SMENR register **************/ +#define RCC_APB3SMENR_SUBGHZSPISMEN_Pos (0U) +#define RCC_APB3SMENR_SUBGHZSPISMEN_Msk (0x1UL << RCC_APB3SMENR_SUBGHZSPISMEN_Pos)/*!< 0x00000001 */ +#define RCC_APB3SMENR_SUBGHZSPISMEN RCC_APB3SMENR_SUBGHZSPISMEN_Msk + +/******************** Bit definition for RCC_CCIPR register ******************/ +#define RCC_CCIPR_USART1SEL_Pos (0U) +#define RCC_CCIPR_USART1SEL_Msk (0x3UL << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000003 */ +#define RCC_CCIPR_USART1SEL RCC_CCIPR_USART1SEL_Msk +#define RCC_CCIPR_USART1SEL_0 (0x1UL << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000001 */ +#define RCC_CCIPR_USART1SEL_1 (0x2UL << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000002 */ + +#define RCC_CCIPR_USART2SEL_Pos (2U) +#define RCC_CCIPR_USART2SEL_Msk (0x3UL << RCC_CCIPR_USART2SEL_Pos) /*!< 0x0000000C */ +#define RCC_CCIPR_USART2SEL RCC_CCIPR_USART2SEL_Msk +#define RCC_CCIPR_USART2SEL_0 (0x1UL << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000004 */ +#define RCC_CCIPR_USART2SEL_1 (0x2UL << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000008 */ + +#define RCC_CCIPR_I2S2SEL_Pos (8U) +#define RCC_CCIPR_I2S2SEL_Msk (0x3UL << RCC_CCIPR_I2S2SEL_Pos) /*!< 0x00000300 */ +#define RCC_CCIPR_I2S2SEL RCC_CCIPR_I2S2SEL_Msk +#define RCC_CCIPR_I2S2SEL_0 (0x1UL << RCC_CCIPR_I2S2SEL_Pos) /*!< 0x00000100 */ +#define RCC_CCIPR_I2S2SEL_1 (0x2UL << RCC_CCIPR_I2S2SEL_Pos) /*!< 0x00000200 */ + +#define RCC_CCIPR_LPUART1SEL_Pos (10U) +#define RCC_CCIPR_LPUART1SEL_Msk (0x3UL << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000C00 */ +#define RCC_CCIPR_LPUART1SEL RCC_CCIPR_LPUART1SEL_Msk +#define RCC_CCIPR_LPUART1SEL_0 (0x1UL << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000400 */ +#define RCC_CCIPR_LPUART1SEL_1 (0x2UL << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000800 */ + +#define RCC_CCIPR_I2C1SEL_Pos (12U) +#define RCC_CCIPR_I2C1SEL_Msk (0x3UL << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00003000 */ +#define RCC_CCIPR_I2C1SEL RCC_CCIPR_I2C1SEL_Msk +#define RCC_CCIPR_I2C1SEL_0 (0x1UL << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00001000 */ +#define RCC_CCIPR_I2C1SEL_1 (0x2UL << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00002000 */ + +#define RCC_CCIPR_I2C2SEL_Pos (14U) +#define RCC_CCIPR_I2C2SEL_Msk (0x3UL << RCC_CCIPR_I2C2SEL_Pos) /*!< 0x0000C000 */ +#define RCC_CCIPR_I2C2SEL RCC_CCIPR_I2C2SEL_Msk +#define RCC_CCIPR_I2C2SEL_0 (0x1UL << RCC_CCIPR_I2C2SEL_Pos) /*!< 0x00004000 */ +#define RCC_CCIPR_I2C2SEL_1 (0x2UL << RCC_CCIPR_I2C2SEL_Pos) /*!< 0x00008000 */ + +#define RCC_CCIPR_I2C3SEL_Pos (16U) +#define RCC_CCIPR_I2C3SEL_Msk (0x3UL << RCC_CCIPR_I2C3SEL_Pos) /*!< 0x00030000 */ +#define RCC_CCIPR_I2C3SEL RCC_CCIPR_I2C3SEL_Msk +#define RCC_CCIPR_I2C3SEL_0 (0x1UL << RCC_CCIPR_I2C3SEL_Pos) /*!< 0x00010000 */ +#define RCC_CCIPR_I2C3SEL_1 (0x2UL << RCC_CCIPR_I2C3SEL_Pos) /*!< 0x00020000 */ + +#define RCC_CCIPR_LPTIM1SEL_Pos (18U) +#define RCC_CCIPR_LPTIM1SEL_Msk (0x3UL << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x000C0000 */ +#define RCC_CCIPR_LPTIM1SEL RCC_CCIPR_LPTIM1SEL_Msk +#define RCC_CCIPR_LPTIM1SEL_0 (0x1UL << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00040000 */ +#define RCC_CCIPR_LPTIM1SEL_1 (0x2UL << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00080000 */ + +#define RCC_CCIPR_LPTIM2SEL_Pos (20U) +#define RCC_CCIPR_LPTIM2SEL_Msk (0x3UL << RCC_CCIPR_LPTIM2SEL_Pos) /*!< 0x00300000 */ +#define RCC_CCIPR_LPTIM2SEL RCC_CCIPR_LPTIM2SEL_Msk +#define RCC_CCIPR_LPTIM2SEL_0 (0x1UL << RCC_CCIPR_LPTIM2SEL_Pos) /*!< 0x00100000 */ +#define RCC_CCIPR_LPTIM2SEL_1 (0x2UL << RCC_CCIPR_LPTIM2SEL_Pos) /*!< 0x00200000 */ + +#define RCC_CCIPR_LPTIM3SEL_Pos (22U) +#define RCC_CCIPR_LPTIM3SEL_Msk (0x3UL << RCC_CCIPR_LPTIM3SEL_Pos) /*!< 0x00C00000 */ +#define RCC_CCIPR_LPTIM3SEL RCC_CCIPR_LPTIM3SEL_Msk +#define RCC_CCIPR_LPTIM3SEL_0 (0x1UL << RCC_CCIPR_LPTIM3SEL_Pos) /*!< 0x00400000 */ +#define RCC_CCIPR_LPTIM3SEL_1 (0x2UL << RCC_CCIPR_LPTIM3SEL_Pos) /*!< 0x00800000 */ + +#define RCC_CCIPR_ADCSEL_Pos (28U) +#define RCC_CCIPR_ADCSEL_Msk (0x3UL << RCC_CCIPR_ADCSEL_Pos) /*!< 0x30000000 */ +#define RCC_CCIPR_ADCSEL RCC_CCIPR_ADCSEL_Msk +#define RCC_CCIPR_ADCSEL_0 (0x1UL << RCC_CCIPR_ADCSEL_Pos) /*!< 0x10000000 */ +#define RCC_CCIPR_ADCSEL_1 (0x2UL << RCC_CCIPR_ADCSEL_Pos) /*!< 0x20000000 */ + +#define RCC_CCIPR_RNGSEL_Pos (30U) +#define RCC_CCIPR_RNGSEL_Msk (0x3UL << RCC_CCIPR_RNGSEL_Pos) /*!< 0xC0000000 */ +#define RCC_CCIPR_RNGSEL RCC_CCIPR_RNGSEL_Msk +#define RCC_CCIPR_RNGSEL_0 (0x1UL << RCC_CCIPR_RNGSEL_Pos) /*!< 0x40000000 */ +#define RCC_CCIPR_RNGSEL_1 (0x2UL << RCC_CCIPR_RNGSEL_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for RCC_BDCR register ******************/ +#define RCC_BDCR_LSEON_Pos (0U) +#define RCC_BDCR_LSEON_Msk (0x1UL << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */ +#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk +#define RCC_BDCR_LSERDY_Pos (1U) +#define RCC_BDCR_LSERDY_Msk (0x1UL << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */ +#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk +#define RCC_BDCR_LSEBYP_Pos (2U) +#define RCC_BDCR_LSEBYP_Msk (0x1UL << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */ +#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk + +#define RCC_BDCR_LSEDRV_Pos (3U) +#define RCC_BDCR_LSEDRV_Msk (0x3UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000018 */ +#define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk +#define RCC_BDCR_LSEDRV_0 (0x1UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000008 */ +#define RCC_BDCR_LSEDRV_1 (0x2UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */ + +#define RCC_BDCR_LSECSSON_Pos (5U) +#define RCC_BDCR_LSECSSON_Msk (0x1UL << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000020 */ +#define RCC_BDCR_LSECSSON RCC_BDCR_LSECSSON_Msk +#define RCC_BDCR_LSECSSD_Pos (6U) +#define RCC_BDCR_LSECSSD_Msk (0x1UL << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000040 */ +#define RCC_BDCR_LSECSSD RCC_BDCR_LSECSSD_Msk +#define RCC_BDCR_LSESYSEN_Pos (7U) +#define RCC_BDCR_LSESYSEN_Msk (0x1UL << RCC_BDCR_LSESYSEN_Pos) /*!< 0x00000080 */ +#define RCC_BDCR_LSESYSEN RCC_BDCR_LSESYSEN_Msk + +#define RCC_BDCR_RTCSEL_Pos (8U) +#define RCC_BDCR_RTCSEL_Msk (0x3UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */ +#define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk +#define RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */ +#define RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */ + +#define RCC_BDCR_LSESYSRDY_Pos (11U) +#define RCC_BDCR_LSESYSRDY_Msk (0x1UL << RCC_BDCR_LSESYSRDY_Pos) /*!< 0x00000800 */ +#define RCC_BDCR_LSESYSRDY RCC_BDCR_LSESYSRDY_Msk + +#define RCC_BDCR_RTCEN_Pos (15U) +#define RCC_BDCR_RTCEN_Msk (0x1UL << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */ +#define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk + +#define RCC_BDCR_BDRST_Pos (16U) +#define RCC_BDCR_BDRST_Msk (0x1UL << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */ +#define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk + +#define RCC_BDCR_LSCOEN_Pos (24U) +#define RCC_BDCR_LSCOEN_Msk (0x1UL << RCC_BDCR_LSCOEN_Pos) /*!< 0x01000000 */ +#define RCC_BDCR_LSCOEN RCC_BDCR_LSCOEN_Msk +#define RCC_BDCR_LSCOSEL_Pos (25U) +#define RCC_BDCR_LSCOSEL_Msk (0x1UL << RCC_BDCR_LSCOSEL_Pos) /*!< 0x02000000 */ +#define RCC_BDCR_LSCOSEL RCC_BDCR_LSCOSEL_Msk + +/******************** Bit definition for RCC_CSR register *******************/ +#define RCC_CSR_LSION_Pos (0U) +#define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos) /*!< 0x00000001 */ +#define RCC_CSR_LSION RCC_CSR_LSION_Msk +#define RCC_CSR_LSIRDY_Pos (1U) +#define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */ +#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk +#define RCC_CSR_LSIPRE_Pos (4U) +#define RCC_CSR_LSIPRE_Msk (0x1UL << RCC_CSR_LSIPRE_Pos) /*!< 0x00000010 */ +#define RCC_CSR_LSIPRE RCC_CSR_LSIPRE_Msk + +#define RCC_CSR_MSISRANGE_Pos (8U) +#define RCC_CSR_MSISRANGE_Msk (0xFUL << RCC_CSR_MSISRANGE_Pos) /*!< 0x00000F00 */ +#define RCC_CSR_MSISRANGE RCC_CSR_MSISRANGE_Msk +#define RCC_CSR_MSISRANGE_1 (0x4UL << RCC_CSR_MSISRANGE_Pos) /*!< 0x00000400 */ +#define RCC_CSR_MSISRANGE_2 (0x5UL << RCC_CSR_MSISRANGE_Pos) /*!< 0x00000500 */ +#define RCC_CSR_MSISRANGE_4 (0x6UL << RCC_CSR_MSISRANGE_Pos) /*!< 0x00000600 */ +#define RCC_CSR_MSISRANGE_8 (0x7UL << RCC_CSR_MSISRANGE_Pos) /*!< 0x00000700 */ + +#define RCC_CSR_RFRSTF_Pos (14U) +#define RCC_CSR_RFRSTF_Msk (0x1UL << RCC_CSR_RFRSTF_Pos) /*!< 0x0004000 */ +#define RCC_CSR_RFRSTF RCC_CSR_RFRSTF_Msk +#define RCC_CSR_RFRST_Pos (15U) +#define RCC_CSR_RFRST_Msk (0x1UL << RCC_CSR_RFRST_Pos) /*!< 0x0008000 */ +#define RCC_CSR_RFRST RCC_CSR_RFRST_Msk + +#define RCC_CSR_RMVF_Pos (23U) +#define RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos) /*!< 0x00800000 */ +#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk +#define RCC_CSR_RFILARSTF_Pos (24U) +#define RCC_CSR_RFILARSTF_Msk (0x1UL << RCC_CSR_RFILARSTF_Pos) /*!< 0x01000000 */ +#define RCC_CSR_RFILARSTF RCC_CSR_RFILARSTF_Msk +#define RCC_CSR_OBLRSTF_Pos (25U) +#define RCC_CSR_OBLRSTF_Msk (0x1UL << RCC_CSR_OBLRSTF_Pos) /*!< 0x02000000 */ +#define RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF_Msk +#define RCC_CSR_PINRSTF_Pos (26U) +#define RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */ +#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk +#define RCC_CSR_BORRSTF_Pos (27U) +#define RCC_CSR_BORRSTF_Msk (0x1UL << RCC_CSR_BORRSTF_Pos) /*!< 0x08000000 */ +#define RCC_CSR_BORRSTF RCC_CSR_BORRSTF_Msk +#define RCC_CSR_SFTRSTF_Pos (28U) +#define RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */ +#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk +#define RCC_CSR_IWDGRSTF_Pos (29U) +#define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */ +#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk +#define RCC_CSR_WWDGRSTF_Pos (30U) +#define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */ +#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk +#define RCC_CSR_LPWRRSTF_Pos (31U) +#define RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */ +#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk + +/******************** Bit definition for RCC_EXTCFGR register *******************/ +#define RCC_EXTCFGR_SHDHPRE_Pos (0U) +#define RCC_EXTCFGR_SHDHPRE_Msk (0xFUL << RCC_EXTCFGR_SHDHPRE_Pos) /*!< 0x0000000F */ +#define RCC_EXTCFGR_SHDHPRE RCC_EXTCFGR_SHDHPRE_Msk +#define RCC_EXTCFGR_SHDHPRE_0 (0x1UL << RCC_EXTCFGR_SHDHPRE_Pos) /*!< 0x00000001 */ +#define RCC_EXTCFGR_SHDHPRE_1 (0x2UL << RCC_EXTCFGR_SHDHPRE_Pos) /*!< 0x00000002 */ +#define RCC_EXTCFGR_SHDHPRE_2 (0x4UL << RCC_EXTCFGR_SHDHPRE_Pos) /*!< 0x00000004 */ +#define RCC_EXTCFGR_SHDHPRE_3 (0x8UL << RCC_EXTCFGR_SHDHPRE_Pos) /*!< 0x00000008 */ + +#define RCC_EXTCFGR_C2HPRE_Pos (4U) +#define RCC_EXTCFGR_C2HPRE_Msk (0xFUL << RCC_EXTCFGR_C2HPRE_Pos)/*!< 0x000000F0 */ +#define RCC_EXTCFGR_C2HPRE RCC_EXTCFGR_C2HPRE_Msk +#define RCC_EXTCFGR_C2HPRE_0 (0x1UL << RCC_EXTCFGR_C2HPRE_Pos)/*!< 0x00000010 */ +#define RCC_EXTCFGR_C2HPRE_1 (0x2UL << RCC_EXTCFGR_C2HPRE_Pos)/*!< 0x00000020 */ +#define RCC_EXTCFGR_C2HPRE_2 (0x4UL << RCC_EXTCFGR_C2HPRE_Pos)/*!< 0x00000040 */ +#define RCC_EXTCFGR_C2HPRE_3 (0x8UL << RCC_EXTCFGR_C2HPRE_Pos)/*!< 0x00000080 */ + +#define RCC_EXTCFGR_SHDHPREF_Pos (16U) +#define RCC_EXTCFGR_SHDHPREF_Msk (0x1UL << RCC_EXTCFGR_SHDHPREF_Pos)/*!< 0x00010000 */ +#define RCC_EXTCFGR_SHDHPREF RCC_EXTCFGR_SHDHPREF_Msk +#define RCC_EXTCFGR_C2HPREF_Pos (17U) +#define RCC_EXTCFGR_C2HPREF_Msk (0x1UL << RCC_EXTCFGR_C2HPREF_Pos)/*!< 0x00020000 */ +#define RCC_EXTCFGR_C2HPREF RCC_EXTCFGR_C2HPREF_Msk + +/******************** Bit definition for RCC_C2AHB1ENR register ****************/ +#define RCC_C2AHB1ENR_DMA1EN_Pos (0U) +#define RCC_C2AHB1ENR_DMA1EN_Msk (0x1UL << RCC_C2AHB1ENR_DMA1EN_Pos)/*!< 0x00000001 */ +#define RCC_C2AHB1ENR_DMA1EN RCC_C2AHB1ENR_DMA1EN_Msk +#define RCC_C2AHB1ENR_DMA2EN_Pos (1U) +#define RCC_C2AHB1ENR_DMA2EN_Msk (0x1UL << RCC_C2AHB1ENR_DMA2EN_Pos)/*!< 0x00000002 */ +#define RCC_C2AHB1ENR_DMA2EN RCC_C2AHB1ENR_DMA2EN_Msk +#define RCC_C2AHB1ENR_DMAMUX1EN_Pos (2U) +#define RCC_C2AHB1ENR_DMAMUX1EN_Msk (0x1UL << RCC_C2AHB1ENR_DMAMUX1EN_Pos)/*!< 0x00000004 */ +#define RCC_C2AHB1ENR_DMAMUX1EN RCC_C2AHB1ENR_DMAMUX1EN_Msk +#define RCC_C2AHB1ENR_CRCEN_Pos (12U) +#define RCC_C2AHB1ENR_CRCEN_Msk (0x1UL << RCC_C2AHB1ENR_CRCEN_Pos)/*!< 0x00001000 */ +#define RCC_C2AHB1ENR_CRCEN RCC_C2AHB1ENR_CRCEN_Msk + +/******************** Bit definition for RCC_C2AHB2ENR register ***************/ +#define RCC_C2AHB2ENR_GPIOAEN_Pos (0U) +#define RCC_C2AHB2ENR_GPIOAEN_Msk (0x1UL << RCC_C2AHB2ENR_GPIOAEN_Pos)/*!< 0x00000001 */ +#define RCC_C2AHB2ENR_GPIOAEN RCC_C2AHB2ENR_GPIOAEN_Msk +#define RCC_C2AHB2ENR_GPIOBEN_Pos (1U) +#define RCC_C2AHB2ENR_GPIOBEN_Msk (0x1UL << RCC_C2AHB2ENR_GPIOBEN_Pos)/*!< 0x00000002 */ +#define RCC_C2AHB2ENR_GPIOBEN RCC_C2AHB2ENR_GPIOBEN_Msk +#define RCC_C2AHB2ENR_GPIOCEN_Pos (2U) +#define RCC_C2AHB2ENR_GPIOCEN_Msk (0x1UL << RCC_C2AHB2ENR_GPIOCEN_Pos)/*!< 0x00000004 */ +#define RCC_C2AHB2ENR_GPIOCEN RCC_C2AHB2ENR_GPIOCEN_Msk +#define RCC_C2AHB2ENR_GPIOHEN_Pos (7U) +#define RCC_C2AHB2ENR_GPIOHEN_Msk (0x1UL << RCC_C2AHB2ENR_GPIOHEN_Pos)/*!< 0x00000080 */ +#define RCC_C2AHB2ENR_GPIOHEN RCC_C2AHB2ENR_GPIOHEN_Msk + +/******************** Bit definition for RCC_C2AHB3ENR register ***************/ +#define RCC_C2AHB3ENR_PKAEN_Pos (16U) +#define RCC_C2AHB3ENR_PKAEN_Msk (0x1UL << RCC_C2AHB3ENR_PKAEN_Pos) /*!< 0x00010000 */ +#define RCC_C2AHB3ENR_PKAEN RCC_C2AHB3ENR_PKAEN_Msk +#define RCC_C2AHB3ENR_AESEN_Pos (17U) +#define RCC_C2AHB3ENR_AESEN_Msk (0x1UL << RCC_C2AHB3ENR_AESEN_Pos)/*!< 0x00020000 */ +#define RCC_C2AHB3ENR_AESEN RCC_C2AHB3ENR_AESEN_Msk +#define RCC_C2AHB3ENR_RNGEN_Pos (18U) +#define RCC_C2AHB3ENR_RNGEN_Msk (0x1UL << RCC_C2AHB3ENR_RNGEN_Pos)/*!< 0x00040000 */ +#define RCC_C2AHB3ENR_RNGEN RCC_C2AHB3ENR_RNGEN_Msk +#define RCC_C2AHB3ENR_HSEMEN_Pos (19U) +#define RCC_C2AHB3ENR_HSEMEN_Msk (0x1UL << RCC_C2AHB3ENR_HSEMEN_Pos)/*!< 0x00080000 */ +#define RCC_C2AHB3ENR_HSEMEN RCC_C2AHB3ENR_HSEMEN_Msk +#define RCC_C2AHB3ENR_IPCCEN_Pos (20U) +#define RCC_C2AHB3ENR_IPCCEN_Msk (0x1UL << RCC_C2AHB3ENR_IPCCEN_Pos)/*!< 0x00100000 */ +#define RCC_C2AHB3ENR_IPCCEN RCC_C2AHB3ENR_IPCCEN_Msk +#define RCC_C2AHB3ENR_FLASHEN_Pos (25U) +#define RCC_C2AHB3ENR_FLASHEN_Msk (0x1UL << RCC_C2AHB3ENR_FLASHEN_Pos)/*!< 0x02000000 */ +#define RCC_C2AHB3ENR_FLASHEN RCC_C2AHB3ENR_FLASHEN_Msk + +/******************** Bit definition for RCC_C2APB1ENR1 register **************/ +#define RCC_C2APB1ENR1_TIM2EN_Pos (0U) +#define RCC_C2APB1ENR1_TIM2EN_Msk (0x1UL << RCC_C2APB1ENR1_TIM2EN_Pos)/*!< 0x00000001 */ +#define RCC_C2APB1ENR1_TIM2EN RCC_C2APB1ENR1_TIM2EN_Msk +#define RCC_C2APB1ENR1_RTCAPBEN_Pos (10U) +#define RCC_C2APB1ENR1_RTCAPBEN_Msk (0x1UL << RCC_C2APB1ENR1_RTCAPBEN_Pos)/*!< 0x00000400 */ +#define RCC_C2APB1ENR1_RTCAPBEN RCC_C2APB1ENR1_RTCAPBEN_Msk +#define RCC_C2APB1ENR1_SPI2EN_Pos (14U) +#define RCC_C2APB1ENR1_SPI2EN_Msk (0x1UL << RCC_C2APB1ENR1_SPI2EN_Pos)/*!< 0x00004000 */ +#define RCC_C2APB1ENR1_SPI2EN RCC_C2APB1ENR1_SPI2EN_Msk +#define RCC_C2APB1ENR1_USART2EN_Pos (17U) +#define RCC_C2APB1ENR1_USART2EN_Msk (0x1UL << RCC_C2APB1ENR1_USART2EN_Pos)/*!< 0x00020000 */ +#define RCC_C2APB1ENR1_USART2EN RCC_C2APB1ENR1_USART2EN_Msk +#define RCC_C2APB1ENR1_I2C1EN_Pos (21U) +#define RCC_C2APB1ENR1_I2C1EN_Msk (0x1UL << RCC_C2APB1ENR1_I2C1EN_Pos)/*!< 0x00200000 */ +#define RCC_C2APB1ENR1_I2C1EN RCC_C2APB1ENR1_I2C1EN_Msk +#define RCC_C2APB1ENR1_I2C2EN_Pos (22U) +#define RCC_C2APB1ENR1_I2C2EN_Msk (0x1UL << RCC_C2APB1ENR1_I2C2EN_Pos)/*!< 0x00400000 */ +#define RCC_C2APB1ENR1_I2C2EN RCC_C2APB1ENR1_I2C2EN_Msk +#define RCC_C2APB1ENR1_I2C3EN_Pos (23U) +#define RCC_C2APB1ENR1_I2C3EN_Msk (0x1UL << RCC_C2APB1ENR1_I2C3EN_Pos)/*!< 0x00800000 */ +#define RCC_C2APB1ENR1_I2C3EN RCC_C2APB1ENR1_I2C3EN_Msk +#define RCC_C2APB1ENR1_DACEN_Pos (29U) +#define RCC_C2APB1ENR1_DACEN_Msk (0x1UL << RCC_C2APB1ENR1_DACEN_Pos)/*!< 0x20000000 */ +#define RCC_C2APB1ENR1_DACEN RCC_C2APB1ENR1_DACEN_Msk +#define RCC_C2APB1ENR1_LPTIM1EN_Pos (31U) +#define RCC_C2APB1ENR1_LPTIM1EN_Msk (0x1UL << RCC_C2APB1ENR1_LPTIM1EN_Pos)/*!< 0x80000000 */ +#define RCC_C2APB1ENR1_LPTIM1EN RCC_C2APB1ENR1_LPTIM1EN_Msk + +/******************** Bit definition for RCC_C2APB1ENR2 register **************/ +#define RCC_C2APB1ENR2_LPUART1EN_Pos (0U) +#define RCC_C2APB1ENR2_LPUART1EN_Msk (0x1UL << RCC_C2APB1ENR2_LPUART1EN_Pos)/*!< 0x00000001 */ +#define RCC_C2APB1ENR2_LPUART1EN RCC_C2APB1ENR2_LPUART1EN_Msk +#define RCC_C2APB1ENR2_LPTIM2EN_Pos (5U) +#define RCC_C2APB1ENR2_LPTIM2EN_Msk (0x1UL << RCC_C2APB1ENR2_LPTIM2EN_Pos)/*!< 0x00000020 */ +#define RCC_C2APB1ENR2_LPTIM2EN RCC_C2APB1ENR2_LPTIM2EN_Msk +#define RCC_C2APB1ENR2_LPTIM3EN_Pos (6U) +#define RCC_C2APB1ENR2_LPTIM3EN_Msk (0x1UL << RCC_C2APB1ENR2_LPTIM3EN_Pos)/*!< 0x00000040 */ +#define RCC_C2APB1ENR2_LPTIM3EN RCC_C2APB1ENR2_LPTIM3EN_Msk + +/******************** Bit definition for RCC_C2APB2ENR register **************/ +#define RCC_C2APB2ENR_ADCEN_Pos (9U) +#define RCC_C2APB2ENR_ADCEN_Msk (0x1UL << RCC_C2APB2ENR_ADCEN_Pos)/*!< 0x00000200 */ +#define RCC_C2APB2ENR_ADCEN RCC_C2APB2ENR_ADCEN_Msk +#define RCC_C2APB2ENR_TIM1EN_Pos (11U) +#define RCC_C2APB2ENR_TIM1EN_Msk (0x1UL << RCC_C2APB2ENR_TIM1EN_Pos)/*!< 0x00000800 */ +#define RCC_C2APB2ENR_TIM1EN RCC_C2APB2ENR_TIM1EN_Msk +#define RCC_C2APB2ENR_SPI1EN_Pos (12U) +#define RCC_C2APB2ENR_SPI1EN_Msk (0x1UL << RCC_C2APB2ENR_SPI1EN_Pos)/*!< 0x00001000 */ +#define RCC_C2APB2ENR_SPI1EN RCC_C2APB2ENR_SPI1EN_Msk +#define RCC_C2APB2ENR_USART1EN_Pos (14U) +#define RCC_C2APB2ENR_USART1EN_Msk (0x1UL << RCC_C2APB2ENR_USART1EN_Pos)/*!< 0x00004000 */ +#define RCC_C2APB2ENR_USART1EN RCC_C2APB2ENR_USART1EN_Msk +#define RCC_C2APB2ENR_TIM16EN_Pos (17U) +#define RCC_C2APB2ENR_TIM16EN_Msk (0x1UL << RCC_C2APB2ENR_TIM16EN_Pos)/*!< 0x00020000 */ +#define RCC_C2APB2ENR_TIM16EN RCC_C2APB2ENR_TIM16EN_Msk +#define RCC_C2APB2ENR_TIM17EN_Pos (18U) +#define RCC_C2APB2ENR_TIM17EN_Msk (0x1UL << RCC_C2APB2ENR_TIM17EN_Pos)/*!< 0x00040000 */ +#define RCC_C2APB2ENR_TIM17EN RCC_C2APB2ENR_TIM17EN_Msk +#define RCC_C2APB2ENR_SAI1EN_Pos (21U) +#define RCC_C2APB2ENR_SAI1EN_Msk (0x1UL << RCC_C2APB2ENR_SAI1EN_Pos)/*!< 0x00200000 */ +#define RCC_C2APB2ENR_SAI1EN RCC_C2APB2ENR_SAI1EN_Msk + +/******************** Bit definition for RCC_C2APB3ENR register **************/ +#define RCC_C2APB3ENR_SUBGHZSPIEN_Pos (0U) +#define RCC_C2APB3ENR_SUBGHZSPIEN_Msk (0x1UL << RCC_C2APB3ENR_SUBGHZSPIEN_Pos)/*!< 0x00000001 */ +#define RCC_C2APB3ENR_SUBGHZSPIEN RCC_C2APB3ENR_SUBGHZSPIEN_Msk + +/******************** Bit definition for RCC_C2AHB1SMENR register ****************/ +#define RCC_C2AHB1SMENR_DMA1SMEN_Pos (0U) +#define RCC_C2AHB1SMENR_DMA1SMEN_Msk (0x1UL << RCC_C2AHB1SMENR_DMA1SMEN_Pos)/*!< 0x00000001 */ +#define RCC_C2AHB1SMENR_DMA1SMEN RCC_C2AHB1SMENR_DMA1SMEN_Msk +#define RCC_C2AHB1SMENR_DMA2SMEN_Pos (1U) +#define RCC_C2AHB1SMENR_DMA2SMEN_Msk (0x1UL << RCC_C2AHB1SMENR_DMA2SMEN_Pos)/*!< 0x00000002 */ +#define RCC_C2AHB1SMENR_DMA2SMEN RCC_C2AHB1SMENR_DMA2SMEN_Msk +#define RCC_C2AHB1SMENR_DMAMUX1SMEN_Pos (2U) +#define RCC_C2AHB1SMENR_DMAMUX1SMEN_Msk (0x1UL << RCC_C2AHB1SMENR_DMAMUX1SMEN_Pos)/*!< 0x00000004 */ +#define RCC_C2AHB1SMENR_DMAMUX1SMEN RCC_C2AHB1SMENR_DMAMUX1SMEN_Msk +#define RCC_C2AHB1SMENR_CRCSMEN_Pos (12U) +#define RCC_C2AHB1SMENR_CRCSMEN_Msk (0x1UL << RCC_C2AHB1SMENR_CRCSMEN_Pos)/*!< 0x00001000 */ +#define RCC_C2AHB1SMENR_CRCSMEN RCC_C2AHB1SMENR_CRCSMEN_Msk + +/******************** Bit definition for RCC_C2AHB2SMENR register ***************/ +#define RCC_C2AHB2SMENR_GPIOASMEN_Pos (0U) +#define RCC_C2AHB2SMENR_GPIOASMEN_Msk (0x1UL << RCC_C2AHB2SMENR_GPIOASMEN_Pos)/*!< 0x00000001 */ +#define RCC_C2AHB2SMENR_GPIOASMEN RCC_C2AHB2SMENR_GPIOASMEN_Msk +#define RCC_C2AHB2SMENR_GPIOBSMEN_Pos (1U) +#define RCC_C2AHB2SMENR_GPIOBSMEN_Msk (0x1UL << RCC_C2AHB2SMENR_GPIOBSMEN_Pos)/*!< 0x00000002 */ +#define RCC_C2AHB2SMENR_GPIOBSMEN RCC_C2AHB2SMENR_GPIOBSMEN_Msk +#define RCC_C2AHB2SMENR_GPIOCSMEN_Pos (2U) +#define RCC_C2AHB2SMENR_GPIOCSMEN_Msk (0x1UL << RCC_C2AHB2SMENR_GPIOCSMEN_Pos)/*!< 0x00000004 */ +#define RCC_C2AHB2SMENR_GPIOCSMEN RCC_C2AHB2SMENR_GPIOCSMEN_Msk +#define RCC_C2AHB2SMENR_GPIOHSMEN_Pos (7U) +#define RCC_C2AHB2SMENR_GPIOHSMEN_Msk (0x1UL << RCC_C2AHB2SMENR_GPIOHSMEN_Pos)/*!< 0x00000080 */ +#define RCC_C2AHB2SMENR_GPIOHSMEN RCC_C2AHB2SMENR_GPIOHSMEN_Msk + +/******************** Bit definition for RCC_C2AHB3SMENR register ***************/ +#define RCC_C2AHB3SMENR_PKASMEN_Pos (16U) +#define RCC_C2AHB3SMENR_PKASMEN_Msk (0x1UL << RCC_C2AHB3SMENR_PKASMEN_Pos) /*!< 0x00010000 */ +#define RCC_C2AHB3SMENR_PKASMEN RCC_C2AHB3SMENR_PKASMEN_Msk +#define RCC_C2AHB3SMENR_AESSMEN_Pos (17U) +#define RCC_C2AHB3SMENR_AESSMEN_Msk (0x1UL << RCC_C2AHB3SMENR_AESSMEN_Pos)/*!< 0x00020000 */ +#define RCC_C2AHB3SMENR_AESSMEN RCC_C2AHB3SMENR_AESSMEN_Msk +#define RCC_C2AHB3SMENR_RNGSMEN_Pos (18U) +#define RCC_C2AHB3SMENR_RNGSMEN_Msk (0x1UL << RCC_C2AHB3SMENR_RNGSMEN_Pos)/*!< 0x00040000 */ +#define RCC_C2AHB3SMENR_RNGSMEN RCC_C2AHB3SMENR_RNGSMEN_Msk +#define RCC_C2AHB3SMENR_SRAM1SMEN_Pos (23U) +#define RCC_C2AHB3SMENR_SRAM1SMEN_Msk (0x1UL << RCC_C2AHB3SMENR_SRAM1SMEN_Pos)/*!< 0x00000200 */ +#define RCC_C2AHB3SMENR_SRAM1SMEN RCC_C2AHB3SMENR_SRAM1SMEN_Msk +#define RCC_C2AHB3SMENR_SRAM2SMEN_Pos (24U) +#define RCC_C2AHB3SMENR_SRAM2SMEN_Msk (0x1UL << RCC_C2AHB3SMENR_SRAM2SMEN_Pos)/*!< 0x01000000 */ +#define RCC_C2AHB3SMENR_SRAM2SMEN RCC_C2AHB3SMENR_SRAM2SMEN_Msk +#define RCC_C2AHB3SMENR_FLASHSMEN_Pos (25U) +#define RCC_C2AHB3SMENR_FLASHSMEN_Msk (0x1UL << RCC_C2AHB3SMENR_FLASHSMEN_Pos)/*!< 0x02000000 */ +#define RCC_C2AHB3SMENR_FLASHSMEN RCC_C2AHB3SMENR_FLASHSMEN_Msk + +/******************** Bit definition for RCC_C2APB1SMENR1 register **************/ +#define RCC_C2APB1SMENR1_TIM2SMEN_Pos (0U) +#define RCC_C2APB1SMENR1_TIM2SMEN_Msk (0x1UL << RCC_C2APB1SMENR1_TIM2SMEN_Pos)/*!< 0x00000001 */ +#define RCC_C2APB1SMENR1_TIM2SMEN RCC_C2APB1SMENR1_TIM2SMEN_Msk +#define RCC_C2APB1SMENR1_RTCAPBSMEN_Pos (10U) +#define RCC_C2APB1SMENR1_RTCAPBSMEN_Msk (0x1UL << RCC_C2APB1SMENR1_RTCAPBSMEN_Pos)/*!< 0x00000400 */ +#define RCC_C2APB1SMENR1_RTCAPBSMEN RCC_C2APB1SMENR1_RTCAPBSMEN_Msk +#define RCC_C2APB1SMENR1_SPI2SMEN_Pos (14U) +#define RCC_C2APB1SMENR1_SPI2SMEN_Msk (0x1UL << RCC_C2APB1SMENR1_SPI2SMEN_Pos)/*!< 0x00004000 */ +#define RCC_C2APB1SMENR1_SPI2SMEN RCC_C2APB1SMENR1_SPI2SMEN_Msk +#define RCC_C2APB1SMENR1_USART2SMEN_Pos (17U) +#define RCC_C2APB1SMENR1_USART2SMEN_Msk (0x1UL << RCC_C2APB1SMENR1_USART2SMEN_Pos)/*!< 0x00020000 */ +#define RCC_C2APB1SMENR1_USART2SMEN RCC_C2APB1SMENR1_USART2SMEN_Msk +#define RCC_C2APB1SMENR1_I2C1SMEN_Pos (21U) +#define RCC_C2APB1SMENR1_I2C1SMEN_Msk (0x1UL << RCC_C2APB1SMENR1_I2C1SMEN_Pos)/*!< 0x00200000 */ +#define RCC_C2APB1SMENR1_I2C1SMEN RCC_C2APB1SMENR1_I2C1SMEN_Msk +#define RCC_C2APB1SMENR1_I2C2SMEN_Pos (22U) +#define RCC_C2APB1SMENR1_I2C2SMEN_Msk (0x1UL << RCC_C2APB1SMENR1_I2C2SMEN_Pos)/*!< 0x00400000 */ +#define RCC_C2APB1SMENR1_I2C2SMEN RCC_C2APB1SMENR1_I2C2SMEN_Msk +#define RCC_C2APB1SMENR1_I2C3SMEN_Pos (23U) +#define RCC_C2APB1SMENR1_I2C3SMEN_Msk (0x1UL << RCC_C2APB1SMENR1_I2C3SMEN_Pos)/*!< 0x00800000 */ +#define RCC_C2APB1SMENR1_I2C3SMEN RCC_C2APB1SMENR1_I2C3SMEN_Msk +#define RCC_C2APB1SMENR1_DACSMEN_Pos (29U) +#define RCC_C2APB1SMENR1_DACSMEN_Msk (0x1UL << RCC_C2APB1SMENR1_DACSMEN_Pos)/*!< 0x20000000 */ +#define RCC_C2APB1SMENR1_DACSMEN RCC_C2APB1SMENR1_DACSMEN_Msk +#define RCC_C2APB1SMENR1_LPTIM1SMEN_Pos (31U) +#define RCC_C2APB1SMENR1_LPTIM1SMEN_Msk (0x1UL << RCC_C2APB1SMENR1_LPTIM1SMEN_Pos)/*!< 0x80000000 */ +#define RCC_C2APB1SMENR1_LPTIM1SMEN RCC_C2APB1SMENR1_LPTIM1SMEN_Msk + +/******************** Bit definition for RCC_C2APB1SMENR2 register **************/ +#define RCC_C2APB1SMENR2_LPUART1SMEN_Pos (0U) +#define RCC_C2APB1SMENR2_LPUART1SMEN_Msk (0x1UL << RCC_C2APB1SMENR2_LPUART1SMEN_Pos)/*!< 0x00000001 */ +#define RCC_C2APB1SMENR2_LPUART1SMEN RCC_C2APB1SMENR2_LPUART1SMEN_Msk +#define RCC_C2APB1SMENR2_LPTIM2SMEN_Pos (5U) +#define RCC_C2APB1SMENR2_LPTIM2SMEN_Msk (0x1UL << RCC_C2APB1SMENR2_LPTIM2SMEN_Pos)/*!< 0x00000020 */ +#define RCC_C2APB1SMENR2_LPTIM2SMEN RCC_C2APB1SMENR2_LPTIM2SMEN_Msk +#define RCC_C2APB1SMENR2_LPTIM3SMEN_Pos (6U) +#define RCC_C2APB1SMENR2_LPTIM3SMEN_Msk (0x1UL << RCC_C2APB1SMENR2_LPTIM3SMEN_Pos)/*!< 0x00000040 */ +#define RCC_C2APB1SMENR2_LPTIM3SMEN RCC_C2APB1SMENR2_LPTIM3SMEN_Msk + +/******************** Bit definition for RCC_C2APB2SMENR register **************/ +#define RCC_C2APB2SMENR_ADCSMEN_Pos (9U) +#define RCC_C2APB2SMENR_ADCSMEN_Msk (0x1UL << RCC_C2APB2SMENR_ADCSMEN_Pos)/*!< 0x00000200 */ +#define RCC_C2APB2SMENR_ADCSMEN RCC_C2APB2SMENR_ADCSMEN_Msk +#define RCC_C2APB2SMENR_TIM1SMEN_Pos (11U) +#define RCC_C2APB2SMENR_TIM1SMEN_Msk (0x1UL << RCC_C2APB2SMENR_TIM1SMEN_Pos)/*!< 0x00000800 */ +#define RCC_C2APB2SMENR_TIM1SMEN RCC_C2APB2SMENR_TIM1SMEN_Msk +#define RCC_C2APB2SMENR_SPI1SMEN_Pos (12U) +#define RCC_C2APB2SMENR_SPI1SMEN_Msk (0x1UL << RCC_C2APB2SMENR_SPI1SMEN_Pos)/*!< 0x00001000 */ +#define RCC_C2APB2SMENR_SPI1SMEN RCC_C2APB2SMENR_SPI1SMEN_Msk +#define RCC_C2APB2SMENR_USART1SMEN_Pos (14U) +#define RCC_C2APB2SMENR_USART1SMEN_Msk (0x1UL << RCC_C2APB2SMENR_USART1SMEN_Pos)/*!< 0x00004000 */ +#define RCC_C2APB2SMENR_USART1SMEN RCC_C2APB2SMENR_USART1SMEN_Msk +#define RCC_C2APB2SMENR_TIM16SMEN_Pos (17U) +#define RCC_C2APB2SMENR_TIM16SMEN_Msk (0x1UL << RCC_C2APB2SMENR_TIM16SMEN_Pos)/*!< 0x00020000 */ +#define RCC_C2APB2SMENR_TIM16SMEN RCC_C2APB2SMENR_TIM16SMEN_Msk +#define RCC_C2APB2SMENR_TIM17SMEN_Pos (18U) +#define RCC_C2APB2SMENR_TIM17SMEN_Msk (0x1UL << RCC_C2APB2SMENR_TIM17SMEN_Pos)/*!< 0x00040000 */ +#define RCC_C2APB2SMENR_TIM17SMEN RCC_C2APB2SMENR_TIM17SMEN_Msk + +/******************** Bit definition for RCC_C2APB3SMENR register **************/ +#define RCC_C2APB3SMENR_SUBGHZSPISMEN_Pos (0U) +#define RCC_C2APB3SMENR_SUBGHZSPISMEN_Msk (0x1UL << RCC_C2APB3SMENR_SUBGHZSPISMEN_Pos)/*!< 0x00000001 */ +#define RCC_C2APB3SMENR_SUBGHZSPISMEN RCC_C2APB3SMENR_SUBGHZSPISMEN_Msk + +/******************************************************************************/ +/* */ +/* RNG */ +/* */ +/******************************************************************************/ +/* + * @brief Specific device feature definitions + */ +#define RNG_VER_3_2 + +/******************** Bits definition for RNG_CR register *******************/ +#define RNG_CR_RNGEN_Pos (2U) +#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */ +#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk +#define RNG_CR_IE_Pos (3U) +#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */ +#define RNG_CR_IE RNG_CR_IE_Msk +#define RNG_CR_CED_Pos (5U) +#define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */ +#define RNG_CR_CED RNG_CR_CED_Msk +#define RNG_CR_RNG_CONFIG3_Pos (8U) +#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) /*!< 0x00000F00 */ +#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk +#define RNG_CR_NISTC_Pos (12U) +#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) /*!< 0x00001000 */ +#define RNG_CR_NISTC RNG_CR_NISTC_Msk +#define RNG_CR_RNG_CONFIG2_Pos (13U) +#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) /*!< 0x0000E000 */ +#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk +#define RNG_CR_CLKDIV_Pos (16U) +#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) /*!< 0x000F0000 */ +#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk +#define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ +#define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ +#define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ +#define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ +#define RNG_CR_RNG_CONFIG1_Pos (20U) +#define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos) /*!< 0x03F00000 */ +#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk +#define RNG_CR_CONDRST_Pos (30U) +#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) /*!< 0x40000000 */ +#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk +#define RNG_CR_CONFIGLOCK_Pos (31U) +#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) /*!< 0x80000000 */ +#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk + +/******************** Bits definition for RNG_SR register *******************/ +#define RNG_SR_DRDY_Pos (0U) +#define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos) /*!< 0x00000001 */ +#define RNG_SR_DRDY RNG_SR_DRDY_Msk +#define RNG_SR_CECS_Pos (1U) +#define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos) /*!< 0x00000002 */ +#define RNG_SR_CECS RNG_SR_CECS_Msk +#define RNG_SR_SECS_Pos (2U) +#define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos) /*!< 0x00000004 */ +#define RNG_SR_SECS RNG_SR_SECS_Msk +#define RNG_SR_CEIS_Pos (5U) +#define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos) /*!< 0x00000020 */ +#define RNG_SR_CEIS RNG_SR_CEIS_Msk +#define RNG_SR_SEIS_Pos (6U) +#define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos) /*!< 0x00000040 */ +#define RNG_SR_SEIS RNG_SR_SEIS_Msk + +/******************** Bits definition for RNG_DR register *******************/ +#define RNG_DR_RNDATA_Pos (0U) +#define RNG_DR_RNDATA_Msk (0xFFFFFFFFUL << RNG_DR_RNDATA_Pos) /*!< 0xFFFFFFFF */ +#define RNG_DR_RNDATA RNG_DR_RNDATA_Msk + +/******************** Bits definition for RNG_HTCR register *****************/ +#define RNG_HTCR_HTCFG_Pos (0U) +#define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ +#define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk + +/******************************************************************************/ +/* */ +/* Real-Time Clock (RTC) */ +/* */ +/******************************************************************************/ +/******************** Bits definition for RTC_TR register *******************/ +#define RTC_TR_PM_Pos (22U) +#define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos) /*!< 0x00400000 */ +#define RTC_TR_PM RTC_TR_PM_Msk +#define RTC_TR_HT_Pos (20U) +#define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos) /*!< 0x00300000 */ +#define RTC_TR_HT RTC_TR_HT_Msk +#define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos) /*!< 0x00100000 */ +#define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos) /*!< 0x00200000 */ +#define RTC_TR_HU_Pos (16U) +#define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_TR_HU RTC_TR_HU_Msk +#define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos) /*!< 0x00010000 */ +#define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos) /*!< 0x00020000 */ +#define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos) /*!< 0x00040000 */ +#define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos) /*!< 0x00080000 */ +#define RTC_TR_MNT_Pos (12U) +#define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_TR_MNT RTC_TR_MNT_Msk +#define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_TR_MNU_Pos (8U) +#define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_TR_MNU RTC_TR_MNU_Msk +#define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_TR_ST_Pos (4U) +#define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos) /*!< 0x00000070 */ +#define RTC_TR_ST RTC_TR_ST_Msk +#define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos) /*!< 0x00000010 */ +#define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos) /*!< 0x00000020 */ +#define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos) /*!< 0x00000040 */ +#define RTC_TR_SU_Pos (0U) +#define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos) /*!< 0x0000000F */ +#define RTC_TR_SU RTC_TR_SU_Msk +#define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos) /*!< 0x00000001 */ +#define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos) /*!< 0x00000002 */ +#define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos) /*!< 0x00000004 */ +#define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos) /*!< 0x00000008 */ + +/******************** Bits definition for RTC_DR register *******************/ +#define RTC_DR_YT_Pos (20U) +#define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos) /*!< 0x00F00000 */ +#define RTC_DR_YT RTC_DR_YT_Msk +#define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos) /*!< 0x00100000 */ +#define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos) /*!< 0x00200000 */ +#define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos) /*!< 0x00400000 */ +#define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos) /*!< 0x00800000 */ +#define RTC_DR_YU_Pos (16U) +#define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos) /*!< 0x000F0000 */ +#define RTC_DR_YU RTC_DR_YU_Msk +#define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos) /*!< 0x00010000 */ +#define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos) /*!< 0x00020000 */ +#define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos) /*!< 0x00040000 */ +#define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos) /*!< 0x00080000 */ +#define RTC_DR_WDU_Pos (13U) +#define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos) /*!< 0x0000E000 */ +#define RTC_DR_WDU RTC_DR_WDU_Msk +#define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos) /*!< 0x00002000 */ +#define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos) /*!< 0x00004000 */ +#define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos) /*!< 0x00008000 */ +#define RTC_DR_MT_Pos (12U) +#define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos) /*!< 0x00001000 */ +#define RTC_DR_MT RTC_DR_MT_Msk +#define RTC_DR_MU_Pos (8U) +#define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos) /*!< 0x00000F00 */ +#define RTC_DR_MU RTC_DR_MU_Msk +#define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos) /*!< 0x00000100 */ +#define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos) /*!< 0x00000200 */ +#define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos) /*!< 0x00000400 */ +#define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos) /*!< 0x00000800 */ +#define RTC_DR_DT_Pos (4U) +#define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos) /*!< 0x00000030 */ +#define RTC_DR_DT RTC_DR_DT_Msk +#define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos) /*!< 0x00000010 */ +#define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos) /*!< 0x00000020 */ +#define RTC_DR_DU_Pos (0U) +#define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos) /*!< 0x0000000F */ +#define RTC_DR_DU RTC_DR_DU_Msk +#define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos) /*!< 0x00000001 */ +#define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos) /*!< 0x00000002 */ +#define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos) /*!< 0x00000004 */ +#define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos) /*!< 0x00000008 */ + +/******************** Bits definition for RTC_SSR register ******************/ +#define RTC_SSR_SS_Pos (0U) +#define RTC_SSR_SS_Msk (0xFFFFFFFFUL << RTC_SSR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_SSR_SS RTC_SSR_SS_Msk + +/******************** Bits definition for RTC_ICSR register ******************/ +#define RTC_ICSR_RECALPF_Pos (16U) +#define RTC_ICSR_RECALPF_Msk (0x1UL << RTC_ICSR_RECALPF_Pos) /*!< 0x00010000 */ +#define RTC_ICSR_RECALPF RTC_ICSR_RECALPF_Msk +#define RTC_ICSR_BCDU_Pos (10U) +#define RTC_ICSR_BCDU_Msk (0x7UL << RTC_ICSR_BCDU_Pos) /*!< 0x00001C00 */ +#define RTC_ICSR_BCDU RTC_ICSR_BCDU_Msk +#define RTC_ICSR_BCDU_0 (0x1UL << RTC_ICSR_BCDU_Pos) /*!< 0x00000400 */ +#define RTC_ICSR_BCDU_1 (0x2UL << RTC_ICSR_BCDU_Pos) /*!< 0x00000800 */ +#define RTC_ICSR_BCDU_2 (0x4UL << RTC_ICSR_BCDU_Pos) /*!< 0x00001000 */ +#define RTC_ICSR_BIN_Pos (8U) +#define RTC_ICSR_BIN_Msk (0x3UL << RTC_ICSR_BIN_Pos) /*!< 0x00000300 */ +#define RTC_ICSR_BIN RTC_ICSR_BIN_Msk +#define RTC_ICSR_BIN_0 (0x1UL << RTC_ICSR_BIN_Pos) /*!< 0x00000100 */ +#define RTC_ICSR_BIN_1 (0x2UL << RTC_ICSR_BIN_Pos) /*!< 0x00000200 */ +#define RTC_ICSR_INIT_Pos (7U) +#define RTC_ICSR_INIT_Msk (0x1UL << RTC_ICSR_INIT_Pos) /*!< 0x00000080 */ +#define RTC_ICSR_INIT RTC_ICSR_INIT_Msk +#define RTC_ICSR_INITF_Pos (6U) +#define RTC_ICSR_INITF_Msk (0x1UL << RTC_ICSR_INITF_Pos) /*!< 0x00000040 */ +#define RTC_ICSR_INITF RTC_ICSR_INITF_Msk +#define RTC_ICSR_RSF_Pos (5U) +#define RTC_ICSR_RSF_Msk (0x1UL << RTC_ICSR_RSF_Pos) /*!< 0x00000020 */ +#define RTC_ICSR_RSF RTC_ICSR_RSF_Msk +#define RTC_ICSR_INITS_Pos (4U) +#define RTC_ICSR_INITS_Msk (0x1UL << RTC_ICSR_INITS_Pos) /*!< 0x00000010 */ +#define RTC_ICSR_INITS RTC_ICSR_INITS_Msk +#define RTC_ICSR_SHPF_Pos (3U) +#define RTC_ICSR_SHPF_Msk (0x1UL << RTC_ICSR_SHPF_Pos) /*!< 0x00000008 */ +#define RTC_ICSR_SHPF RTC_ICSR_SHPF_Msk +#define RTC_ICSR_WUTWF_Pos (2U) +#define RTC_ICSR_WUTWF_Msk (0x1UL << RTC_ICSR_WUTWF_Pos) /*!< 0x00000004 */ +#define RTC_ICSR_WUTWF RTC_ICSR_WUTWF_Msk + +/******************** Bits definition for RTC_PRER register *****************/ +#define RTC_PRER_PREDIV_A_Pos (16U) +#define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */ +#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk +#define RTC_PRER_PREDIV_S_Pos (0U) +#define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */ +#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk + +/******************** Bits definition for RTC_WUTR register *****************/ +#define RTC_WUTR_WUTOCLR_Pos (16U) +#define RTC_WUTR_WUTOCLR_Msk (0xFFFFUL << RTC_WUTR_WUTOCLR_Pos) /*!< 0x0000FFFF */ +#define RTC_WUTR_WUTOCLR RTC_WUTR_WUTOCLR_Msk +#define RTC_WUTR_WUT_Pos (0U) +#define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */ +#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk + +/******************** Bits definition for RTC_CR register *******************/ +#define RTC_CR_OUT2EN_Pos (31U) +#define RTC_CR_OUT2EN_Msk (0x1UL << RTC_CR_OUT2EN_Pos) /*!< 0x80000000 */ +#define RTC_CR_OUT2EN RTC_CR_OUT2EN_Msk /*! + +/** @addtogroup STM32WLxx_System_Includes + * @{ + */ + +/** + * @} + */ + + +/** @addtogroup STM32WLxx_System_Exported_types + * @{ + */ + /* The SystemCoreClock variable is updated in three ways: + 1) from within HAL_Init() + 2) by calling CMSIS function SystemCoreClockUpdate() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + */ + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency */ + +extern const uint32_t AHBPrescTable[16]; /*!< AHB prescalers table values */ +extern const uint32_t APBPrescTable[8]; /*!< APB prescalers table values */ +extern const uint32_t MSIRangeTable[16]; /*!< MSI ranges table values */ + +/** + * @} + */ + +/** @addtogroup STM32WLxx_System_Exported_Constants + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32WLxx_System_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32WLxx_System_Exported_Functions + * @{ + */ + +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /*__SYSTEM_STM32WLXX_H */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/Drivers/CMSIS/Device/ST/STM32WLxx/LICENSE.txt b/Drivers/CMSIS/Device/ST/STM32WLxx/LICENSE.txt new file mode 100644 index 0000000..872e82b --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32WLxx/LICENSE.txt @@ -0,0 +1,6 @@ +This software component is provided to you as part of a software package and +applicable license terms are in the Package_license file. If you received this +software component outside of a package or without applicable license terms, +the terms of the Apache-2.0 license shall apply. +You may obtain a copy of the Apache-2.0 at: +https://opensource.org/licenses/Apache-2.0 diff --git a/Drivers/CMSIS/Include/cmsis_armcc.h b/Drivers/CMSIS/Include/cmsis_armcc.h new file mode 100644 index 0000000..59f173a --- /dev/null +++ b/Drivers/CMSIS/Include/cmsis_armcc.h @@ -0,0 +1,894 @@ +/**************************************************************************//** + * @file cmsis_armcc.h + * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file + * @version V5.1.0 + * @date 08. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_ARMCC_H +#define __CMSIS_ARMCC_H + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) + #error "Please use Arm Compiler Toolchain V4.0.677 or later!" +#endif + +/* CMSIS compiler control architecture macros */ +#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \ + (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) ) + #define __ARM_ARCH_6M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1)) + #define __ARM_ARCH_7M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1)) + #define __ARM_ARCH_7EM__ 1 +#endif + + /* __ARM_ARCH_8M_BASE__ not applicable */ + /* __ARM_ARCH_8M_MAIN__ not applicable */ + +/* CMSIS compiler control DSP macros */ +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __ARM_FEATURE_DSP 1 +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE static __forceinline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __declspec(noreturn) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed)) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT __packed struct +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION __packed union +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr))) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr))) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __memory_changed() +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET"))) +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); */ + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xFFU); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + register uint32_t __regBasePriMax __ASM("basepri_max"); + __regBasePriMax = (basePri & 0xFFU); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1U); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() do {\ + __schedule_barrier();\ + __isb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() do {\ + __schedule_barrier();\ + __dsb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() do {\ + __schedule_barrier();\ + __dmb(0xF);\ + __schedule_barrier();\ + } while (0U) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __RBIT __rbit +#else +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ + return result; +} +#endif + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) +#else + #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) +#else + #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) +#else + #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXB(value, ptr) __strex(value, ptr) +#else + #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXH(value, ptr) __strex(value, ptr) +#else + #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXW(value, ptr) __strex(value, ptr) +#else + #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32U) ) >> 32U)) + +#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCC_H */ diff --git a/Drivers/CMSIS/Include/cmsis_armclang.h b/Drivers/CMSIS/Include/cmsis_armclang.h new file mode 100644 index 0000000..e917f35 --- /dev/null +++ b/Drivers/CMSIS/Include/cmsis_armclang.h @@ -0,0 +1,1444 @@ +/**************************************************************************//** + * @file cmsis_armclang.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V5.2.0 + * @date 08. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +#ifndef __ARM_COMPAT_H +#include /* Compatibility header for Arm Compiler 5 intrinsics */ +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET"))) +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); see arm_compat.h */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); see arm_compat.h */ + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq /* see arm_compat.h */ + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq /* see arm_compat.h */ + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +#define __SADD8 __builtin_arm_sadd8 +#define __QADD8 __builtin_arm_qadd8 +#define __SHADD8 __builtin_arm_shadd8 +#define __UADD8 __builtin_arm_uadd8 +#define __UQADD8 __builtin_arm_uqadd8 +#define __UHADD8 __builtin_arm_uhadd8 +#define __SSUB8 __builtin_arm_ssub8 +#define __QSUB8 __builtin_arm_qsub8 +#define __SHSUB8 __builtin_arm_shsub8 +#define __USUB8 __builtin_arm_usub8 +#define __UQSUB8 __builtin_arm_uqsub8 +#define __UHSUB8 __builtin_arm_uhsub8 +#define __SADD16 __builtin_arm_sadd16 +#define __QADD16 __builtin_arm_qadd16 +#define __SHADD16 __builtin_arm_shadd16 +#define __UADD16 __builtin_arm_uadd16 +#define __UQADD16 __builtin_arm_uqadd16 +#define __UHADD16 __builtin_arm_uhadd16 +#define __SSUB16 __builtin_arm_ssub16 +#define __QSUB16 __builtin_arm_qsub16 +#define __SHSUB16 __builtin_arm_shsub16 +#define __USUB16 __builtin_arm_usub16 +#define __UQSUB16 __builtin_arm_uqsub16 +#define __UHSUB16 __builtin_arm_uhsub16 +#define __SASX __builtin_arm_sasx +#define __QASX __builtin_arm_qasx +#define __SHASX __builtin_arm_shasx +#define __UASX __builtin_arm_uasx +#define __UQASX __builtin_arm_uqasx +#define __UHASX __builtin_arm_uhasx +#define __SSAX __builtin_arm_ssax +#define __QSAX __builtin_arm_qsax +#define __SHSAX __builtin_arm_shsax +#define __USAX __builtin_arm_usax +#define __UQSAX __builtin_arm_uqsax +#define __UHSAX __builtin_arm_uhsax +#define __USAD8 __builtin_arm_usad8 +#define __USADA8 __builtin_arm_usada8 +#define __SSAT16 __builtin_arm_ssat16 +#define __USAT16 __builtin_arm_usat16 +#define __UXTB16 __builtin_arm_uxtb16 +#define __UXTAB16 __builtin_arm_uxtab16 +#define __SXTB16 __builtin_arm_sxtb16 +#define __SXTAB16 __builtin_arm_sxtab16 +#define __SMUAD __builtin_arm_smuad +#define __SMUADX __builtin_arm_smuadx +#define __SMLAD __builtin_arm_smlad +#define __SMLADX __builtin_arm_smladx +#define __SMLALD __builtin_arm_smlald +#define __SMLALDX __builtin_arm_smlaldx +#define __SMUSD __builtin_arm_smusd +#define __SMUSDX __builtin_arm_smusdx +#define __SMLSD __builtin_arm_smlsd +#define __SMLSDX __builtin_arm_smlsdx +#define __SMLSLD __builtin_arm_smlsld +#define __SMLSLDX __builtin_arm_smlsldx +#define __SEL __builtin_arm_sel +#define __QADD __builtin_arm_qadd +#define __QSUB __builtin_arm_qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/Drivers/CMSIS/Include/cmsis_armclang_ltm.h b/Drivers/CMSIS/Include/cmsis_armclang_ltm.h new file mode 100644 index 0000000..feec324 --- /dev/null +++ b/Drivers/CMSIS/Include/cmsis_armclang_ltm.h @@ -0,0 +1,1891 @@ +/**************************************************************************//** + * @file cmsis_armclang_ltm.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V1.2.0 + * @date 08. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2018-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +#ifndef __ARM_COMPAT_H +#include /* Compatibility header for Arm Compiler 5 intrinsics */ +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET"))) +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); see arm_compat.h */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); see arm_compat.h */ + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq /* see arm_compat.h */ + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq /* see arm_compat.h */ + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/Drivers/CMSIS/Include/cmsis_compiler.h b/Drivers/CMSIS/Include/cmsis_compiler.h new file mode 100644 index 0000000..adbf296 --- /dev/null +++ b/Drivers/CMSIS/Include/cmsis_compiler.h @@ -0,0 +1,283 @@ +/**************************************************************************//** + * @file cmsis_compiler.h + * @brief CMSIS compiler generic header file + * @version V5.1.0 + * @date 09. October 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include + +/* + * Arm Compiler 4/5 + */ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + + +/* + * Arm Compiler 6.6 LTM (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100) + #include "cmsis_armclang_ltm.h" + + /* + * Arm Compiler above 6.10.1 (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) + #include "cmsis_armclang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + #include + + +/* + * TI Arm Compiler + */ +#elif defined ( __TI_ARM__ ) + #include + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed)) + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed)) + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __RESTRICT + #define __RESTRICT __restrict + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __packed__ + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __packed__ + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __packed__ + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __packed__ T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __align(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) + #include + + #ifndef __ASM + #define __ASM _asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + // NO RETURN is automatically detected hence no warning here + #define __NO_RETURN + #endif + #ifndef __USED + #warning No compiler specific solution for __USED. __USED is ignored. + #define __USED + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __PACKED + #define __PACKED @packed + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT @packed struct + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION @packed union + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + @packed struct T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +#else + #error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + diff --git a/Drivers/CMSIS/Include/cmsis_gcc.h b/Drivers/CMSIS/Include/cmsis_gcc.h new file mode 100644 index 0000000..3ddcc58 --- /dev/null +++ b/Drivers/CMSIS/Include/cmsis_gcc.h @@ -0,0 +1,2168 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler GCC header file + * @version V5.2.0 + * @date 08. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START + +/** + \brief Initializes data and bss sections + \details This default implementations initialized all data and additional bss + sections relying on .copy.table and .zero.table specified properly + in the used linker script. + + */ +__STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void) +{ + extern void _start(void) __NO_RETURN; + + typedef struct { + uint32_t const* src; + uint32_t* dest; + uint32_t wlen; + } __copy_table_t; + + typedef struct { + uint32_t* dest; + uint32_t wlen; + } __zero_table_t; + + extern const __copy_table_t __copy_table_start__; + extern const __copy_table_t __copy_table_end__; + extern const __zero_table_t __zero_table_start__; + extern const __zero_table_t __zero_table_end__; + + for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = pTable->src[i]; + } + } + + for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = 0u; + } + } + + _start(); +} + +#define __PROGRAM_START __cmsis_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP __StackTop +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT __StackLimit +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section(".vectors"))) +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory"); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_get_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + return __builtin_arm_get_fpscr(); +#else + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#endif +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_set_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + __builtin_arm_set_fpscr(fpscr); +#else + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); +#endif +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __ASM volatile ("nop") + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __ASM volatile ("wfi") + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __ASM volatile ("wfe") + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __ASM volatile ("sev") + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (int16_t)__builtin_bswap16(value); +#else + int16_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return result; +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__STATIC_FORCEINLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ + __extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#if 0 +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) +#endif + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ diff --git a/Drivers/CMSIS/Include/cmsis_iccarm.h b/Drivers/CMSIS/Include/cmsis_iccarm.h new file mode 100644 index 0000000..12d68fd --- /dev/null +++ b/Drivers/CMSIS/Include/cmsis_iccarm.h @@ -0,0 +1,964 @@ +/**************************************************************************//** + * @file cmsis_iccarm.h + * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file + * @version V5.1.0 + * @date 08. May 2019 + ******************************************************************************/ + +//------------------------------------------------------------------------------ +// +// Copyright (c) 2017-2019 IAR Systems +// Copyright (c) 2017-2019 Arm Limited. All rights reserved. +// +// Licensed under the Apache License, Version 2.0 (the "License") +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//------------------------------------------------------------------------------ + + +#ifndef __CMSIS_ICCARM_H__ +#define __CMSIS_ICCARM_H__ + +#ifndef __ICCARM__ + #error This file should only be compiled by ICCARM +#endif + +#pragma system_include + +#define __IAR_FT _Pragma("inline=forced") __intrinsic + +#if (__VER__ >= 8000000) + #define __ICCARM_V8 1 +#else + #define __ICCARM_V8 0 +#endif + +#ifndef __ALIGNED + #if __ICCARM_V8 + #define __ALIGNED(x) __attribute__((aligned(x))) + #elif (__VER__ >= 7080000) + /* Needs IAR language extensions */ + #define __ALIGNED(x) __attribute__((aligned(x))) + #else + #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. + #define __ALIGNED(x) + #endif +#endif + + +/* Define compiler macros for CPU architecture, used in CMSIS 5. + */ +#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__ +/* Macros already defined */ +#else + #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' + #if __ARM_ARCH == 6 + #define __ARM_ARCH_6M__ 1 + #elif __ARM_ARCH == 7 + #if __ARM_FEATURE_DSP + #define __ARM_ARCH_7EM__ 1 + #else + #define __ARM_ARCH_7M__ 1 + #endif + #endif /* __ARM_ARCH */ + #endif /* __ARM_ARCH_PROFILE == 'M' */ +#endif + +/* Alternativ core deduction for older ICCARM's */ +#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \ + !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__) + #if defined(__ARM6M__) && (__CORE__ == __ARM6M__) + #define __ARM_ARCH_6M__ 1 + #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__) + #define __ARM_ARCH_7M__ 1 + #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__) + #define __ARM_ARCH_7EM__ 1 + #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #else + #error "Unknown target." + #endif +#endif + + + +#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1 + #define __IAR_M0_FAMILY 1 +#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1 + #define __IAR_M0_FAMILY 1 +#else + #define __IAR_M0_FAMILY 0 +#endif + + +#ifndef __ASM + #define __ASM __asm +#endif + +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +#ifndef __INLINE + #define __INLINE inline +#endif + +#ifndef __NO_RETURN + #if __ICCARM_V8 + #define __NO_RETURN __attribute__((__noreturn__)) + #else + #define __NO_RETURN _Pragma("object_attribute=__noreturn") + #endif +#endif + +#ifndef __PACKED + #if __ICCARM_V8 + #define __PACKED __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED __packed + #endif +#endif + +#ifndef __PACKED_STRUCT + #if __ICCARM_V8 + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_STRUCT __packed struct + #endif +#endif + +#ifndef __PACKED_UNION + #if __ICCARM_V8 + #define __PACKED_UNION union __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_UNION __packed union + #endif +#endif + +#ifndef __RESTRICT + #if __ICCARM_V8 + #define __RESTRICT __restrict + #else + /* Needs IAR language extensions */ + #define __RESTRICT restrict + #endif +#endif + +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif + +#ifndef __FORCEINLINE + #define __FORCEINLINE _Pragma("inline=forced") +#endif + +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE +#endif + +#ifndef __UNALIGNED_UINT16_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint16_t __iar_uint16_read(void const *ptr) +{ + return *(__packed uint16_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) +#endif + + +#ifndef __UNALIGNED_UINT16_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) +{ + *(__packed uint16_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint32_t __iar_uint32_read(void const *ptr) +{ + return *(__packed uint32_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) +#endif + +#ifndef __UNALIGNED_UINT32_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) +{ + *(__packed uint32_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32 /* deprecated */ +#pragma language=save +#pragma language=extended +__packed struct __iar_u32 { uint32_t v; }; +#pragma language=restore +#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) +#endif + +#ifndef __USED + #if __ICCARM_V8 + #define __USED __attribute__((used)) + #else + #define __USED _Pragma("__root") + #endif +#endif + +#ifndef __WEAK + #if __ICCARM_V8 + #define __WEAK __attribute__((weak)) + #else + #define __WEAK _Pragma("__weak") + #endif +#endif + +#ifndef __PROGRAM_START +#define __PROGRAM_START __iar_program_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP CSTACK$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT CSTACK$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __vector_table +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE @".intvec" +#endif + +#ifndef __ICCARM_INTRINSICS_VERSION__ + #define __ICCARM_INTRINSICS_VERSION__ 0 +#endif + +#if __ICCARM_INTRINSICS_VERSION__ == 2 + + #if defined(__CLZ) + #undef __CLZ + #endif + #if defined(__REVSH) + #undef __REVSH + #endif + #if defined(__RBIT) + #undef __RBIT + #endif + #if defined(__SSAT) + #undef __SSAT + #endif + #if defined(__USAT) + #undef __USAT + #endif + + #include "iccarm_builtin.h" + + #define __disable_fault_irq __iar_builtin_disable_fiq + #define __disable_irq __iar_builtin_disable_interrupt + #define __enable_fault_irq __iar_builtin_enable_fiq + #define __enable_irq __iar_builtin_enable_interrupt + #define __arm_rsr __iar_builtin_rsr + #define __arm_wsr __iar_builtin_wsr + + + #define __get_APSR() (__arm_rsr("APSR")) + #define __get_BASEPRI() (__arm_rsr("BASEPRI")) + #define __get_CONTROL() (__arm_rsr("CONTROL")) + #define __get_FAULTMASK() (__arm_rsr("FAULTMASK")) + + #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + #define __get_FPSCR() (__arm_rsr("FPSCR")) + #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) + #else + #define __get_FPSCR() ( 0 ) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #define __get_IPSR() (__arm_rsr("IPSR")) + #define __get_MSP() (__arm_rsr("MSP")) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __get_MSPLIM() (0U) + #else + #define __get_MSPLIM() (__arm_rsr("MSPLIM")) + #endif + #define __get_PRIMASK() (__arm_rsr("PRIMASK")) + #define __get_PSP() (__arm_rsr("PSP")) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __get_PSPLIM() (0U) + #else + #define __get_PSPLIM() (__arm_rsr("PSPLIM")) + #endif + + #define __get_xPSR() (__arm_rsr("xPSR")) + + #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE))) + #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE))) + #define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE))) + #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE))) + #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __set_MSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE))) + #endif + #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE))) + #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE))) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __set_PSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE))) + #endif + + #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS")) + #define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE))) + #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS")) + #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE))) + #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS")) + #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE))) + #define __TZ_get_SP_NS() (__arm_rsr("SP_NS")) + #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE))) + #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS")) + #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE))) + #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS")) + #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE))) + #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS")) + #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __TZ_get_PSPLIM_NS() (0U) + #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE)) + #else + #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) + #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) + #endif + + #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) + #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) + + #define __NOP __iar_builtin_no_operation + + #define __CLZ __iar_builtin_CLZ + #define __CLREX __iar_builtin_CLREX + + #define __DMB __iar_builtin_DMB + #define __DSB __iar_builtin_DSB + #define __ISB __iar_builtin_ISB + + #define __LDREXB __iar_builtin_LDREXB + #define __LDREXH __iar_builtin_LDREXH + #define __LDREXW __iar_builtin_LDREX + + #define __RBIT __iar_builtin_RBIT + #define __REV __iar_builtin_REV + #define __REV16 __iar_builtin_REV16 + + __IAR_FT int16_t __REVSH(int16_t val) + { + return (int16_t) __iar_builtin_REVSH(val); + } + + #define __ROR __iar_builtin_ROR + #define __RRX __iar_builtin_RRX + + #define __SEV __iar_builtin_SEV + + #if !__IAR_M0_FAMILY + #define __SSAT __iar_builtin_SSAT + #endif + + #define __STREXB __iar_builtin_STREXB + #define __STREXH __iar_builtin_STREXH + #define __STREXW __iar_builtin_STREX + + #if !__IAR_M0_FAMILY + #define __USAT __iar_builtin_USAT + #endif + + #define __WFE __iar_builtin_WFE + #define __WFI __iar_builtin_WFI + + #if __ARM_MEDIA__ + #define __SADD8 __iar_builtin_SADD8 + #define __QADD8 __iar_builtin_QADD8 + #define __SHADD8 __iar_builtin_SHADD8 + #define __UADD8 __iar_builtin_UADD8 + #define __UQADD8 __iar_builtin_UQADD8 + #define __UHADD8 __iar_builtin_UHADD8 + #define __SSUB8 __iar_builtin_SSUB8 + #define __QSUB8 __iar_builtin_QSUB8 + #define __SHSUB8 __iar_builtin_SHSUB8 + #define __USUB8 __iar_builtin_USUB8 + #define __UQSUB8 __iar_builtin_UQSUB8 + #define __UHSUB8 __iar_builtin_UHSUB8 + #define __SADD16 __iar_builtin_SADD16 + #define __QADD16 __iar_builtin_QADD16 + #define __SHADD16 __iar_builtin_SHADD16 + #define __UADD16 __iar_builtin_UADD16 + #define __UQADD16 __iar_builtin_UQADD16 + #define __UHADD16 __iar_builtin_UHADD16 + #define __SSUB16 __iar_builtin_SSUB16 + #define __QSUB16 __iar_builtin_QSUB16 + #define __SHSUB16 __iar_builtin_SHSUB16 + #define __USUB16 __iar_builtin_USUB16 + #define __UQSUB16 __iar_builtin_UQSUB16 + #define __UHSUB16 __iar_builtin_UHSUB16 + #define __SASX __iar_builtin_SASX + #define __QASX __iar_builtin_QASX + #define __SHASX __iar_builtin_SHASX + #define __UASX __iar_builtin_UASX + #define __UQASX __iar_builtin_UQASX + #define __UHASX __iar_builtin_UHASX + #define __SSAX __iar_builtin_SSAX + #define __QSAX __iar_builtin_QSAX + #define __SHSAX __iar_builtin_SHSAX + #define __USAX __iar_builtin_USAX + #define __UQSAX __iar_builtin_UQSAX + #define __UHSAX __iar_builtin_UHSAX + #define __USAD8 __iar_builtin_USAD8 + #define __USADA8 __iar_builtin_USADA8 + #define __SSAT16 __iar_builtin_SSAT16 + #define __USAT16 __iar_builtin_USAT16 + #define __UXTB16 __iar_builtin_UXTB16 + #define __UXTAB16 __iar_builtin_UXTAB16 + #define __SXTB16 __iar_builtin_SXTB16 + #define __SXTAB16 __iar_builtin_SXTAB16 + #define __SMUAD __iar_builtin_SMUAD + #define __SMUADX __iar_builtin_SMUADX + #define __SMMLA __iar_builtin_SMMLA + #define __SMLAD __iar_builtin_SMLAD + #define __SMLADX __iar_builtin_SMLADX + #define __SMLALD __iar_builtin_SMLALD + #define __SMLALDX __iar_builtin_SMLALDX + #define __SMUSD __iar_builtin_SMUSD + #define __SMUSDX __iar_builtin_SMUSDX + #define __SMLSD __iar_builtin_SMLSD + #define __SMLSDX __iar_builtin_SMLSDX + #define __SMLSLD __iar_builtin_SMLSLD + #define __SMLSLDX __iar_builtin_SMLSLDX + #define __SEL __iar_builtin_SEL + #define __QADD __iar_builtin_QADD + #define __QSUB __iar_builtin_QSUB + #define __PKHBT __iar_builtin_PKHBT + #define __PKHTB __iar_builtin_PKHTB + #endif + +#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #define __CLZ __cmsis_iar_clz_not_active + #define __SSAT __cmsis_iar_ssat_not_active + #define __USAT __cmsis_iar_usat_not_active + #define __RBIT __cmsis_iar_rbit_not_active + #define __get_APSR __cmsis_iar_get_APSR_not_active + #endif + + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #define __get_FPSCR __cmsis_iar_get_FPSR_not_active + #define __set_FPSCR __cmsis_iar_set_FPSR_not_active + #endif + + #ifdef __INTRINSICS_INCLUDED + #error intrinsics.h is already included previously! + #endif + + #include + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #undef __CLZ + #undef __SSAT + #undef __USAT + #undef __RBIT + #undef __get_APSR + + __STATIC_INLINE uint8_t __CLZ(uint32_t data) + { + if (data == 0U) { return 32U; } + + uint32_t count = 0U; + uint32_t mask = 0x80000000U; + + while ((data & mask) == 0U) + { + count += 1U; + mask = mask >> 1U; + } + return count; + } + + __STATIC_INLINE uint32_t __RBIT(uint32_t v) + { + uint8_t sc = 31U; + uint32_t r = v; + for (v >>= 1U; v; v >>= 1U) + { + r <<= 1U; + r |= v & 1U; + sc--; + } + return (r << sc); + } + + __STATIC_INLINE uint32_t __get_APSR(void) + { + uint32_t res; + __asm("MRS %0,APSR" : "=r" (res)); + return res; + } + + #endif + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #undef __get_FPSCR + #undef __set_FPSCR + #define __get_FPSCR() (0) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #pragma diag_suppress=Pe940 + #pragma diag_suppress=Pe177 + + #define __enable_irq __enable_interrupt + #define __disable_irq __disable_interrupt + #define __NOP __no_operation + + #define __get_xPSR __get_PSR + + #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0) + + __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) + { + return __LDREX((unsigned long *)ptr); + } + + __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) + { + return __STREX(value, (unsigned long *)ptr); + } + #endif + + + /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + #if (__CORTEX_M >= 0x03) + + __IAR_FT uint32_t __RRX(uint32_t value) + { + uint32_t result; + __ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc"); + return(result); + } + + __IAR_FT void __set_BASEPRI_MAX(uint32_t value) + { + __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value)); + } + + + #define __enable_fault_irq __enable_fiq + #define __disable_fault_irq __disable_fiq + + + #endif /* (__CORTEX_M >= 0x03) */ + + __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) + { + return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); + } + + #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + __IAR_FT uint32_t __get_MSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,MSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_MSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR MSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __get_PSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_PSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_CONTROL_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,CONTROL_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) + { + __asm volatile("MSR CONTROL_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PSP_NS(uint32_t value) + { + __asm volatile("MSR PSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_MSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSP_NS(uint32_t value) + { + __asm volatile("MSR MSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_SP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,SP_NS" : "=r" (res)); + return res; + } + __IAR_FT void __TZ_set_SP_NS(uint32_t value) + { + __asm volatile("MSR SP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) + { + __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) + { + __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) + { + __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) + { + __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value)); + } + + #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + +#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) + +#if __IAR_M0_FAMILY + __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) + { + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; + } + + __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) + { + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; + } +#endif + +#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + + __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) + { + uint32_t res; + __ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) + { + uint32_t res; + __ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDRT(volatile uint32_t *addr) + { + uint32_t res; + __ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return res; + } + + __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) + { + __ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) + { + __ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) + { + __ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); + } + +#endif /* (__CORTEX_M >= 0x03) */ + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + + __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) + { + __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) + { + __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) + { + __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + +#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#undef __IAR_FT +#undef __IAR_M0_FAMILY +#undef __ICCARM_V8 + +#pragma diag_default=Pe940 +#pragma diag_default=Pe177 + +#endif /* __CMSIS_ICCARM_H__ */ diff --git a/Drivers/CMSIS/Include/cmsis_version.h b/Drivers/CMSIS/Include/cmsis_version.h new file mode 100644 index 0000000..f2e2746 --- /dev/null +++ b/Drivers/CMSIS/Include/cmsis_version.h @@ -0,0 +1,39 @@ +/**************************************************************************//** + * @file cmsis_version.h + * @brief CMSIS Core(M) Version definitions + * @version V5.0.3 + * @date 24. June 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_VERSION_H +#define __CMSIS_VERSION_H + +/* CMSIS Version definitions */ +#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ +#define __CM_CMSIS_VERSION_SUB ( 3U) /*!< [15:0] CMSIS Core(M) sub version */ +#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ + __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ +#endif diff --git a/Drivers/CMSIS/Include/core_armv81mml.h b/Drivers/CMSIS/Include/core_armv81mml.h new file mode 100644 index 0000000..8441e57 --- /dev/null +++ b/Drivers/CMSIS/Include/core_armv81mml.h @@ -0,0 +1,2968 @@ +/**************************************************************************//** + * @file core_armv81mml.h + * @brief CMSIS Armv8.1-M Mainline Core Peripheral Access Layer Header File + * @version V1.0.0 + * @date 15. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2018-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_ARMV81MML_H_GENERIC +#define __CORE_ARMV81MML_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMV81MML + @{ + */ + +#include "cmsis_version.h" + +#define __ARM_ARCH_8M_MAIN__ 1 // patching for now +/* CMSIS ARMV81MML definitions */ +#define __ARMv81MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv81MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv81MML_CMSIS_VERSION ((__ARMv81MML_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv81MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (81U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV81MML_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV81MML_H_DEPENDANT +#define __CORE_ARMV81MML_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv81MML_REV + #define __ARMv81MML_REV 0x0000U + #warning "__ARMv81MML_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv81MML */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */ +#define MPU_RLAR_PXN_Msk (0x1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV81MML_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Include/core_armv8mbl.h b/Drivers/CMSIS/Include/core_armv8mbl.h new file mode 100644 index 0000000..344dca5 --- /dev/null +++ b/Drivers/CMSIS/Include/core_armv8mbl.h @@ -0,0 +1,1921 @@ +/**************************************************************************//** + * @file core_armv8mbl.h + * @brief CMSIS Armv8-M Baseline Core Peripheral Access Layer Header File + * @version V5.0.8 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_ARMV8MBL_H_GENERIC +#define __CORE_ARMV8MBL_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MBL + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS definitions */ +#define __ARMv8MBL_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv8MBL_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv8MBL_CMSIS_VERSION ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MBL_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M ( 2U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MBL_H_DEPENDANT +#define __CORE_ARMV8MBL_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv8MBL_REV + #define __ARMv8MBL_REV 0x0000U + #warning "__ARMv8MBL_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif + + #ifndef __ETM_PRESENT + #define __ETM_PRESENT 0U + #warning "__ETM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MTB_PRESENT + #define __MTB_PRESENT 0U + #warning "__MTB_PRESENT not defined in device header file; using default!" + #endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MBL */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t RESERVED0[6U]; + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */ +#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Include/core_armv8mml.h b/Drivers/CMSIS/Include/core_armv8mml.h new file mode 100644 index 0000000..5ddb8ae --- /dev/null +++ b/Drivers/CMSIS/Include/core_armv8mml.h @@ -0,0 +1,2835 @@ +/**************************************************************************//** + * @file core_armv8mml.h + * @brief CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 12. September 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_ARMV8MML_H_GENERIC +#define __CORE_ARMV8MML_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MML + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS Armv8MML definitions */ +#define __ARMv8MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv8MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv8MML_CMSIS_VERSION ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (81U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MML_H_DEPENDANT +#define __CORE_ARMV8MML_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv8MML_REV + #define __ARMv8MML_REV 0x0000U + #warning "__ARMv8MML_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MML */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Include/core_cm0.h b/Drivers/CMSIS/Include/core_cm0.h new file mode 100644 index 0000000..cafae5a --- /dev/null +++ b/Drivers/CMSIS/Include/core_cm0.h @@ -0,0 +1,952 @@ +/**************************************************************************//** + * @file core_cm0.h + * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File + * @version V5.0.6 + * @date 13. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0_H_GENERIC +#define __CORE_CM0_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M0 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0 definitions */ +#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \ + __CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0_H_DEPENDANT +#define __CORE_CM0_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0_REV + #define __CM0_REV 0x0000U + #warning "__CM0_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M0 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + Address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t vectors = 0x0U; + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + /* ARM Application Note 321 states that the M0 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t vectors = 0x0U; + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Include/core_cm0plus.h b/Drivers/CMSIS/Include/core_cm0plus.h new file mode 100644 index 0000000..d104965 --- /dev/null +++ b/Drivers/CMSIS/Include/core_cm0plus.h @@ -0,0 +1,1085 @@ +/**************************************************************************//** + * @file core_cm0plus.h + * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File + * @version V5.0.7 + * @date 13. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0PLUS_H_GENERIC +#define __CORE_CM0PLUS_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex-M0+ + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0+ definitions */ +#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ + __CM0PLUS_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0PLUS_H_DEPENDANT +#define __CORE_CM0PLUS_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0PLUS_REV + #define __CM0PLUS_REV 0x0000U + #warning "__CM0PLUS_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex-M0+ */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0+ header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t vectors = SCB->VTOR; +#else + uint32_t vectors = 0x0U; +#endif + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + /* ARM Application Note 321 states that the M0+ does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t vectors = SCB->VTOR; +#else + uint32_t vectors = 0x0U; +#endif + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Include/core_cm1.h b/Drivers/CMSIS/Include/core_cm1.h new file mode 100644 index 0000000..76b4569 --- /dev/null +++ b/Drivers/CMSIS/Include/core_cm1.h @@ -0,0 +1,979 @@ +/**************************************************************************//** + * @file core_cm1.h + * @brief CMSIS Cortex-M1 Core Peripheral Access Layer Header File + * @version V1.0.1 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM1_H_GENERIC +#define __CORE_CM1_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M1 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM1 definitions */ +#define __CM1_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM1_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM1_CMSIS_VERSION ((__CM1_CMSIS_VERSION_MAIN << 16U) | \ + __CM1_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (1U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM1_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM1_H_DEPENDANT +#define __CORE_CM1_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM1_REV + #define __CM1_REV 0x0100U + #warning "__CM1_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M1 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_ITCMUAEN_Pos 4U /*!< ACTLR: Instruction TCM Upper Alias Enable Position */ +#define SCnSCB_ACTLR_ITCMUAEN_Msk (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos) /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */ + +#define SCnSCB_ACTLR_ITCMLAEN_Pos 3U /*!< ACTLR: Instruction TCM Lower Alias Enable Position */ +#define SCnSCB_ACTLR_ITCMLAEN_Msk (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos) /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M1 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M1 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + Address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)0x0U; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M1 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)0x0U; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM1_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Include/core_cm23.h b/Drivers/CMSIS/Include/core_cm23.h new file mode 100644 index 0000000..b79c6af --- /dev/null +++ b/Drivers/CMSIS/Include/core_cm23.h @@ -0,0 +1,1996 @@ +/**************************************************************************//** + * @file core_cm23.h + * @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File + * @version V5.0.8 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM23_H_GENERIC +#define __CORE_CM23_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M23 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS definitions */ +#define __CM23_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM23_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM23_CMSIS_VERSION ((__CM23_CMSIS_VERSION_MAIN << 16U) | \ + __CM23_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (23U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM23_H_DEPENDANT +#define __CORE_CM23_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM23_REV + #define __CM23_REV 0x0000U + #warning "__CM23_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif + + #ifndef __ETM_PRESENT + #define __ETM_PRESENT 0U + #warning "__ETM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MTB_PRESENT + #define __MTB_PRESENT 0U + #warning "__MTB_PRESENT not defined in device header file; using default!" + #endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M23 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t RESERVED0[6U]; + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */ +#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M23 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M23 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Include/core_cm3.h b/Drivers/CMSIS/Include/core_cm3.h new file mode 100644 index 0000000..8157ca7 --- /dev/null +++ b/Drivers/CMSIS/Include/core_cm3.h @@ -0,0 +1,1937 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 13. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM3_H_GENERIC +#define __CORE_CM3_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M3 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM3 definitions */ +#define __CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \ + __CM3_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (3U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM3_H_DEPENDANT +#define __CORE_CM3_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM3_REV + #define __CM3_REV 0x0200U + #warning "__CM3_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M3 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#else +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +#else + uint32_t RESERVED1[1U]; +#endif +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ +#endif + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + /* ARM Application Note 321 states that the M3 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Include/core_cm33.h b/Drivers/CMSIS/Include/core_cm33.h new file mode 100644 index 0000000..7fed59a --- /dev/null +++ b/Drivers/CMSIS/Include/core_cm33.h @@ -0,0 +1,2910 @@ +/**************************************************************************//** + * @file core_cm33.h + * @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM33_H_GENERIC +#define __CORE_CM33_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M33 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM33 definitions */ +#define __CM33_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM33_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) | \ + __CM33_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (33U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM33_H_DEPENDANT +#define __CORE_CM33_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM33_REV + #define __CM33_REV 0x0000U + #warning "__CM33_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M33 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Include/core_cm35p.h b/Drivers/CMSIS/Include/core_cm35p.h new file mode 100644 index 0000000..5579c82 --- /dev/null +++ b/Drivers/CMSIS/Include/core_cm35p.h @@ -0,0 +1,2910 @@ +/**************************************************************************//** + * @file core_cm35p.h + * @brief CMSIS Cortex-M35P Core Peripheral Access Layer Header File + * @version V1.0.0 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM35P_H_GENERIC +#define __CORE_CM35P_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M35P + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM35P definitions */ +#define __CM35P_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM35P_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM35P_CMSIS_VERSION ((__CM35P_CMSIS_VERSION_MAIN << 16U) | \ + __CM35P_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (35U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM35P_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM35P_H_DEPENDANT +#define __CORE_CM35P_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM35P_REV + #define __CM35P_REV 0x0000U + #warning "__CM35P_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M35P */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM35P_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Include/core_cm4.h b/Drivers/CMSIS/Include/core_cm4.h new file mode 100644 index 0000000..12c023b --- /dev/null +++ b/Drivers/CMSIS/Include/core_cm4.h @@ -0,0 +1,2124 @@ +/**************************************************************************//** + * @file core_cm4.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 13. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM4_H_GENERIC +#define __CORE_CM4_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M4 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM4 definitions */ +#define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ + __CM4_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (4U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM4_H_DEPENDANT +#define __CORE_CM4_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM4_REV + #define __CM4_REV 0x0000U + #warning "__CM4_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M4 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +#define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ +#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + /* ARM Application Note 321 states that the M4 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Include/core_cm7.h b/Drivers/CMSIS/Include/core_cm7.h new file mode 100644 index 0000000..c4515d8 --- /dev/null +++ b/Drivers/CMSIS/Include/core_cm7.h @@ -0,0 +1,2725 @@ +/**************************************************************************//** + * @file core_cm7.h + * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File + * @version V5.1.1 + * @date 28. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM7_H_GENERIC +#define __CORE_CM7_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M7 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM7 definitions */ +#define __CM7_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM7_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \ + __CM7_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (7U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM7_H_DEPENDANT +#define __CORE_CM7_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM7_REV + #define __CM7_REV 0x0000U + #warning "__CM7_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DTCM_PRESENT + #define __DTCM_PRESENT 0U + #warning "__DTCM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M7 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[1U]; + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED3[93U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ + +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISDYNADD_Pos 26U /*!< ACTLR: DISDYNADD Position */ +#define SCnSCB_ACTLR_DISDYNADD_Msk (1UL << SCnSCB_ACTLR_DISDYNADD_Pos) /*!< ACTLR: DISDYNADD Mask */ + +#define SCnSCB_ACTLR_DISISSCH1_Pos 21U /*!< ACTLR: DISISSCH1 Position */ +#define SCnSCB_ACTLR_DISISSCH1_Msk (0x1FUL << SCnSCB_ACTLR_DISISSCH1_Pos) /*!< ACTLR: DISISSCH1 Mask */ + +#define SCnSCB_ACTLR_DISDI_Pos 16U /*!< ACTLR: DISDI Position */ +#define SCnSCB_ACTLR_DISDI_Msk (0x1FUL << SCnSCB_ACTLR_DISDI_Pos) /*!< ACTLR: DISDI Mask */ + +#define SCnSCB_ACTLR_DISCRITAXIRUR_Pos 15U /*!< ACTLR: DISCRITAXIRUR Position */ +#define SCnSCB_ACTLR_DISCRITAXIRUR_Msk (1UL << SCnSCB_ACTLR_DISCRITAXIRUR_Pos) /*!< ACTLR: DISCRITAXIRUR Mask */ + +#define SCnSCB_ACTLR_DISBTACALLOC_Pos 14U /*!< ACTLR: DISBTACALLOC Position */ +#define SCnSCB_ACTLR_DISBTACALLOC_Msk (1UL << SCnSCB_ACTLR_DISBTACALLOC_Pos) /*!< ACTLR: DISBTACALLOC Mask */ + +#define SCnSCB_ACTLR_DISBTACREAD_Pos 13U /*!< ACTLR: DISBTACREAD Position */ +#define SCnSCB_ACTLR_DISBTACREAD_Msk (1UL << SCnSCB_ACTLR_DISBTACREAD_Pos) /*!< ACTLR: DISBTACREAD Mask */ + +#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */ +#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ + +#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ +#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED3[981U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +#define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ +#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = SCB->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## Cache functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_CacheFunctions Cache Functions + \brief Functions that configure Instruction and Data cache. + @{ + */ + +/* Cache Size ID Register Macros */ +#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) + +#define __SCB_DCACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ +#define __SCB_ICACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ + +/** + \brief Enable I-Cache + \details Turns on I-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ + + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable I-Cache + \details Turns off I-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate I-Cache + \details Invalidates I-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; + __DSB(); + __ISB(); + #endif +} + + +/** + \brief I-Cache Invalidate by address + \details Invalidates I-Cache for the given address. + I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + I-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] isize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (void *addr, int32_t isize) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if ( isize > 0 ) { + int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_ICACHE_LINE_SIZE; + op_size -= __SCB_ICACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief Enable D-Cache + \details Turns on D-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + __DSB(); + + SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable D-Cache + \details Turns off D-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate D-Cache + \details Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean D-Cache + \details Cleans D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | + ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean & Invalidate D-Cache + \details Cleans and Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Invalidate by address + \details Invalidates D-Cache for the given address. + D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean by address + \details Cleans D-Cache for the given address + D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean and Invalidate by address + \details Cleans and invalidates D_Cache for the given address + D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned and invalidated. + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + +/*@} end of CMSIS_Core_CacheFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Include/core_sc000.h b/Drivers/CMSIS/Include/core_sc000.h new file mode 100644 index 0000000..cf92577 --- /dev/null +++ b/Drivers/CMSIS/Include/core_sc000.h @@ -0,0 +1,1025 @@ +/**************************************************************************//** + * @file core_sc000.h + * @brief CMSIS SC000 Core Peripheral Access Layer Header File + * @version V5.0.6 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC000_H_GENERIC +#define __CORE_SC000_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC000 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS SC000 definitions */ +#define __SC000_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __SC000_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \ + __SC000_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_SC (000U) /*!< Cortex secure core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC000_H_DEPENDANT +#define __CORE_SC000_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC000_REV + #define __SC000_REV 0x0000U + #warning "__SC000_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC000 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + uint32_t RESERVED1[154U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the SC000 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M0 and M0+ do not require the architectural barrier - assume SC000 is the same */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Include/core_sc300.h b/Drivers/CMSIS/Include/core_sc300.h new file mode 100644 index 0000000..40f3af8 --- /dev/null +++ b/Drivers/CMSIS/Include/core_sc300.h @@ -0,0 +1,1912 @@ +/**************************************************************************//** + * @file core_sc300.h + * @brief CMSIS SC300 Core Peripheral Access Layer Header File + * @version V5.0.8 + * @date 31. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC300_H_GENERIC +#define __CORE_SC300_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC3000 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS SC300 definitions */ +#define __SC300_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __SC300_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \ + __SC300_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_SC (300U) /*!< Cortex secure core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC300_H_DEPENDANT +#define __CORE_SC300_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC300_REV + #define __SC300_REV 0x0000U + #warning "__SC300_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC300 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED1[129U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + /* ARM Application Note 321 states that the M3 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Include/mpu_armv7.h b/Drivers/CMSIS/Include/mpu_armv7.h new file mode 100644 index 0000000..66ef59b --- /dev/null +++ b/Drivers/CMSIS/Include/mpu_armv7.h @@ -0,0 +1,272 @@ +/****************************************************************************** + * @file mpu_armv7.h + * @brief CMSIS MPU API for Armv7-M MPU + * @version V5.1.0 + * @date 08. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2017-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV7_H +#define ARM_MPU_ARMV7_H + +#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes +#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes +#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes +#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes +#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes +#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte +#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes +#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes +#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes +#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes +#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes +#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes +#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes +#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes +#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes +#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte +#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes +#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes +#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes +#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes +#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes +#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes +#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes +#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes +#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes +#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte +#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes +#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes + +#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access +#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only +#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only +#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access +#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only +#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access + +/** MPU Region Base Address Register Value +* +* \param Region The region to be configured, number 0 to 15. +* \param BaseAddress The base address for the region. +*/ +#define ARM_MPU_RBAR(Region, BaseAddress) \ + (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ + ((Region) & MPU_RBAR_REGION_Msk) | \ + (MPU_RBAR_VALID_Msk)) + +/** +* MPU Memory Access Attributes +* +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +*/ +#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ + ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ + (((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ + (((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ + (((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk)) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \ + ((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ + (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ + (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \ + (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \ + (((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \ + (((MPU_RASR_ENABLE_Msk)))) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ + ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size) + +/** +* MPU Memory Access Attribute for strongly ordered memory. +* - TEX: 000b +* - Shareable +* - Non-cacheable +* - Non-bufferable +*/ +#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U) + +/** +* MPU Memory Access Attribute for device memory. +* - TEX: 000b (if shareable) or 010b (if non-shareable) +* - Shareable or non-shareable +* - Non-cacheable +* - Bufferable (if shareable) or non-bufferable (if non-shareable) +* +* \param IsShareable Configures the device memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U)) + +/** +* MPU Memory Access Attribute for normal memory. +* - TEX: 1BBb (reflecting outer cacheability rules) +* - Shareable or non-shareable +* - Cacheable or non-cacheable (reflecting inner cacheability rules) +* - Bufferable or non-bufferable (reflecting inner cacheability rules) +* +* \param OuterCp Configures the outer cache policy. +* \param InnerCp Configures the inner cache policy. +* \param IsShareable Configures the memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U)) + +/** +* MPU Memory Access Attribute non-cacheable policy. +*/ +#define ARM_MPU_CACHEP_NOCACHE 0U + +/** +* MPU Memory Access Attribute write-back, write and read allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_WRA 1U + +/** +* MPU Memory Access Attribute write-through, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WT_NWA 2U + +/** +* MPU Memory Access Attribute write-back, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_NWA 3U + + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; //!< The region base address register value (RBAR) + uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + MPU->RNR = rnr; + MPU->RASR = 0U; +} + +/** Configure an MPU region. +* \param rbar Value for RBAR register. +* \param rsar Value for RSAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) +{ + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rsar Value for RSAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) +{ + MPU->RNR = rnr; + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Memcopy with strictly ordered memory access, e.g. for register targets. +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + while (cnt > MPU_TYPE_RALIASES) { + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); + table += MPU_TYPE_RALIASES; + cnt -= MPU_TYPE_RALIASES; + } + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); +} + +#endif diff --git a/Drivers/CMSIS/Include/mpu_armv8.h b/Drivers/CMSIS/Include/mpu_armv8.h new file mode 100644 index 0000000..0041d4d --- /dev/null +++ b/Drivers/CMSIS/Include/mpu_armv8.h @@ -0,0 +1,346 @@ +/****************************************************************************** + * @file mpu_armv8.h + * @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU + * @version V5.1.0 + * @date 08. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2017-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV8_H +#define ARM_MPU_ARMV8_H + +/** \brief Attribute for device memory (outer only) */ +#define ARM_MPU_ATTR_DEVICE ( 0U ) + +/** \brief Attribute for non-cacheable, normal memory */ +#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U ) + +/** \brief Attribute for normal memory (outer and inner) +* \param NT Non-Transient: Set to 1 for non-transient data. +* \param WB Write-Back: Set to 1 to use write-back update policy. +* \param RA Read Allocation: Set to 1 to use cache allocation on read miss. +* \param WA Write Allocation: Set to 1 to use cache allocation on write miss. +*/ +#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \ + (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U)) + +/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U) + +/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRE (1U) + +/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGRE (2U) + +/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_GRE (3U) + +/** \brief Memory Attribute +* \param O Outer memory attributes +* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes +*/ +#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U))) + +/** \brief Normal memory non-shareable */ +#define ARM_MPU_SH_NON (0U) + +/** \brief Normal memory outer shareable */ +#define ARM_MPU_SH_OUTER (2U) + +/** \brief Normal memory inner shareable */ +#define ARM_MPU_SH_INNER (3U) + +/** \brief Memory access permissions +* \param RO Read-Only: Set to 1 for read-only memory. +* \param NP Non-Privileged: Set to 1 for non-privileged memory. +*/ +#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U)) + +/** \brief Region Base Address Register value +* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned. +* \param SH Defines the Shareability domain for this memory region. +* \param RO Read-Only: Set to 1 for a read-only memory region. +* \param NP Non-Privileged: Set to 1 for a non-privileged memory region. +* \oaram XN eXecute Never: Set to 1 for a non-executable memory region. +*/ +#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ + ((BASE & MPU_RBAR_BASE_Msk) | \ + ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \ + ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \ + ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk)) + +/** \brief Region Limit Address Register value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR(LIMIT, IDX) \ + ((LIMIT & MPU_RLAR_LIMIT_Msk) | \ + ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#if defined(MPU_RLAR_PXN_Pos) + +/** \brief Region Limit Address Register with PXN value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \ + ((LIMIT & MPU_RLAR_LIMIT_Msk) | \ + ((PXN << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \ + ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#endif + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; /*!< Region Base Address Register value */ + uint32_t RLAR; /*!< Region Limit Address Register value */ +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} + +#ifdef MPU_NS +/** Enable the Non-secure MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control) +{ + MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the Non-secure MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable_NS(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} +#endif + +/** Set the memory attribute encoding to the given MPU. +* \param mpu Pointer to the MPU to be configured. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr) +{ + const uint8_t reg = idx / 4U; + const uint32_t pos = ((idx % 4U) * 8U); + const uint32_t mask = 0xFFU << pos; + + if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { + return; // invalid index + } + + mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); +} + +/** Set the memory attribute encoding. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU, idx, attr); +} + +#ifdef MPU_NS +/** Set the memory attribute encoding to the Non-secure MPU. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr); +} +#endif + +/** Clear and disable the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr) +{ + mpu->RNR = rnr; + mpu->RLAR = 0U; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU, rnr); +} + +#ifdef MPU_NS +/** Clear and disable the given Non-secure MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU_NS, rnr); +} +#endif + +/** Configure the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + mpu->RNR = rnr; + mpu->RBAR = rbar; + mpu->RLAR = rlar; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); +} + +#ifdef MPU_NS +/** Configure the given Non-secure MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); +} +#endif + +/** Memcopy with strictly ordered memory access, e.g. for register targets. +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table to the given MPU. +* \param mpu Pointer to the MPU registers to be used. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + if (cnt == 1U) { + mpu->RNR = rnr; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); + } else { + uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); + uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; + + mpu->RNR = rnrBase; + while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { + uint32_t c = MPU_TYPE_RALIASES - rnrOffset; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); + table += c; + cnt -= c; + rnrOffset = 0U; + rnrBase += MPU_TYPE_RALIASES; + mpu->RNR = rnrBase; + } + + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); + } +} + +/** Load the given number of MPU regions from a table. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU, rnr, table, cnt); +} + +#ifdef MPU_NS +/** Load the given number of MPU regions from a table to the Non-secure MPU. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); +} +#endif + +#endif + diff --git a/Drivers/CMSIS/Include/tz_context.h b/Drivers/CMSIS/Include/tz_context.h new file mode 100644 index 0000000..0d09749 --- /dev/null +++ b/Drivers/CMSIS/Include/tz_context.h @@ -0,0 +1,70 @@ +/****************************************************************************** + * @file tz_context.h + * @brief Context Management for Armv8-M TrustZone + * @version V1.0.1 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2017-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef TZ_CONTEXT_H +#define TZ_CONTEXT_H + +#include + +#ifndef TZ_MODULEID_T +#define TZ_MODULEID_T +/// \details Data type that identifies secure software modules called by a process. +typedef uint32_t TZ_ModuleId_t; +#endif + +/// \details TZ Memory ID identifies an allocated memory slot. +typedef uint32_t TZ_MemoryId_t; + +/// Initialize secure context memory system +/// \return execution status (1: success, 0: error) +uint32_t TZ_InitContextSystem_S (void); + +/// Allocate context memory for calling secure software modules in TrustZone +/// \param[in] module identifies software modules called from non-secure mode +/// \return value != 0 id TrustZone memory slot identifier +/// \return value 0 no memory available or internal error +TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module); + +/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id); + +/// Load secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_LoadContext_S (TZ_MemoryId_t id); + +/// Store secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_StoreContext_S (TZ_MemoryId_t id); + +#endif // TZ_CONTEXT_H diff --git a/Drivers/CMSIS/LICENSE.txt b/Drivers/CMSIS/LICENSE.txt new file mode 100644 index 0000000..8dada3e --- /dev/null +++ b/Drivers/CMSIS/LICENSE.txt @@ -0,0 +1,201 @@ + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + + TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + + 1. 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b/Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h @@ -0,0 +1,4436 @@ +/** + ****************************************************************************** + * @file stm32_hal_legacy.h + * @author MCD Application Team + * @brief This file contains aliases definition for the STM32Cube HAL constants + * macros and functions maintained for legacy purpose. + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32_HAL_LEGACY +#define STM32_HAL_LEGACY + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose + * @{ + */ +#define AES_FLAG_RDERR CRYP_FLAG_RDERR +#define AES_FLAG_WRERR CRYP_FLAG_WRERR +#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF +#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR +#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR +#if defined(STM32H7) || defined(STM32MP1) +#define CRYP_DATATYPE_32B CRYP_NO_SWAP +#define CRYP_DATATYPE_16B CRYP_HALFWORD_SWAP +#define CRYP_DATATYPE_8B CRYP_BYTE_SWAP +#define CRYP_DATATYPE_1B CRYP_BIT_SWAP +#endif /* STM32H7 || STM32MP1 */ +/** + * @} + */ + +/** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose + * @{ + */ +#define ADC_RESOLUTION12b ADC_RESOLUTION_12B +#define ADC_RESOLUTION10b ADC_RESOLUTION_10B +#define ADC_RESOLUTION8b ADC_RESOLUTION_8B +#define ADC_RESOLUTION6b ADC_RESOLUTION_6B +#define OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN +#define OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED +#define EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV +#define EOC_SEQ_CONV ADC_EOC_SEQ_CONV +#define EOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONV +#define REGULAR_GROUP ADC_REGULAR_GROUP +#define INJECTED_GROUP ADC_INJECTED_GROUP +#define REGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUP +#define AWD_EVENT ADC_AWD_EVENT +#define AWD1_EVENT ADC_AWD1_EVENT +#define AWD2_EVENT ADC_AWD2_EVENT +#define AWD3_EVENT ADC_AWD3_EVENT +#define OVR_EVENT ADC_OVR_EVENT +#define JQOVF_EVENT ADC_JQOVF_EVENT +#define ALL_CHANNELS ADC_ALL_CHANNELS +#define REGULAR_CHANNELS ADC_REGULAR_CHANNELS +#define INJECTED_CHANNELS ADC_INJECTED_CHANNELS +#define SYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSOR +#define SYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINT +#define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1 +#define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2 +#define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4 +#define ADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6 +#define ADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8 +#define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO +#define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2 +#define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO +#define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4 +#define ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO +#define ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11 +#define ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1 +#define ADC_EXTERNALTRIG_EDGE_NONE ADC_EXTERNALTRIGCONVEDGE_NONE +#define ADC_EXTERNALTRIG_EDGE_RISING ADC_EXTERNALTRIGCONVEDGE_RISING +#define ADC_EXTERNALTRIG_EDGE_FALLING ADC_EXTERNALTRIGCONVEDGE_FALLING +#define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING +#define ADC_SAMPLETIME_2CYCLE_5 ADC_SAMPLETIME_2CYCLES_5 + +#define HAL_ADC_STATE_BUSY_REG HAL_ADC_STATE_REG_BUSY +#define HAL_ADC_STATE_BUSY_INJ HAL_ADC_STATE_INJ_BUSY +#define HAL_ADC_STATE_EOC_REG HAL_ADC_STATE_REG_EOC +#define HAL_ADC_STATE_EOC_INJ HAL_ADC_STATE_INJ_EOC +#define HAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNAL +#define HAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNAL +#define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1 + +#if defined(STM32H7) +#define ADC_CHANNEL_VBAT_DIV4 ADC_CHANNEL_VBAT +#endif /* STM32H7 */ + +#if defined(STM32U5) +#define ADC_SAMPLETIME_5CYCLE ADC_SAMPLETIME_5CYCLES +#define ADC_SAMPLETIME_391CYCLES_5 ADC_SAMPLETIME_391CYCLES +#define ADC4_SAMPLETIME_160CYCLES_5 ADC4_SAMPLETIME_814CYCLES_5 +#endif /* STM32U5 */ + +#if defined(STM32H5) +#define ADC_CHANNEL_VCORE ADC_CHANNEL_VDDCORE +#endif /* STM32H5 */ +/** + * @} + */ + +/** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG + +/** + * @} + */ + +/** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose + * @{ + */ +#define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE +#define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE +#define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1 +#define COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2 +#define COMP_EXTI_LINE_COMP3_EVENT COMP_EXTI_LINE_COMP3 +#define COMP_EXTI_LINE_COMP4_EVENT COMP_EXTI_LINE_COMP4 +#define COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5 +#define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6 +#define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7 +#if defined(STM32L0) +#define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM + input 1 for COMP1, LPTIM input 2 for COMP2 */ +#endif +#define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR +#if defined(STM32F373xC) || defined(STM32F378xx) +#define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1 +#define COMP_OUTPUT_TIM3OCREFCLR COMP_OUTPUT_COMP1_TIM3OCREFCLR +#endif /* STM32F373xC || STM32F378xx */ + +#if defined(STM32L0) || defined(STM32L4) +#define COMP_WINDOWMODE_ENABLE COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON + +#define COMP_NONINVERTINGINPUT_IO1 COMP_INPUT_PLUS_IO1 +#define COMP_NONINVERTINGINPUT_IO2 COMP_INPUT_PLUS_IO2 +#define COMP_NONINVERTINGINPUT_IO3 COMP_INPUT_PLUS_IO3 +#define COMP_NONINVERTINGINPUT_IO4 COMP_INPUT_PLUS_IO4 +#define COMP_NONINVERTINGINPUT_IO5 COMP_INPUT_PLUS_IO5 +#define COMP_NONINVERTINGINPUT_IO6 COMP_INPUT_PLUS_IO6 + +#define COMP_INVERTINGINPUT_1_4VREFINT COMP_INPUT_MINUS_1_4VREFINT +#define COMP_INVERTINGINPUT_1_2VREFINT COMP_INPUT_MINUS_1_2VREFINT +#define COMP_INVERTINGINPUT_3_4VREFINT COMP_INPUT_MINUS_3_4VREFINT +#define COMP_INVERTINGINPUT_VREFINT COMP_INPUT_MINUS_VREFINT +#define COMP_INVERTINGINPUT_DAC1_CH1 COMP_INPUT_MINUS_DAC1_CH1 +#define COMP_INVERTINGINPUT_DAC1_CH2 COMP_INPUT_MINUS_DAC1_CH2 +#define COMP_INVERTINGINPUT_DAC1 COMP_INPUT_MINUS_DAC1_CH1 +#define COMP_INVERTINGINPUT_DAC2 COMP_INPUT_MINUS_DAC1_CH2 +#define COMP_INVERTINGINPUT_IO1 COMP_INPUT_MINUS_IO1 +#if defined(STM32L0) +/* Issue fixed on STM32L0 COMP driver: only 2 dedicated IO (IO1 and IO2), */ +/* IO2 was wrongly assigned to IO shared with DAC and IO3 was corresponding */ +/* to the second dedicated IO (only for COMP2). */ +#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_DAC1_CH2 +#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO2 +#else +#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_IO2 +#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO3 +#endif +#define COMP_INVERTINGINPUT_IO4 COMP_INPUT_MINUS_IO4 +#define COMP_INVERTINGINPUT_IO5 COMP_INPUT_MINUS_IO5 + +#define COMP_OUTPUTLEVEL_LOW COMP_OUTPUT_LEVEL_LOW +#define COMP_OUTPUTLEVEL_HIGH COMP_OUTPUT_LEVEL_HIGH + +/* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose. */ +/* To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()". */ +#if defined(COMP_CSR_LOCK) +#define COMP_FLAG_LOCK COMP_CSR_LOCK +#elif defined(COMP_CSR_COMP1LOCK) +#define COMP_FLAG_LOCK COMP_CSR_COMP1LOCK +#elif defined(COMP_CSR_COMPxLOCK) +#define COMP_FLAG_LOCK COMP_CSR_COMPxLOCK +#endif + +#if defined(STM32L4) +#define COMP_BLANKINGSRCE_TIM1OC5 COMP_BLANKINGSRC_TIM1_OC5_COMP1 +#define COMP_BLANKINGSRCE_TIM2OC3 COMP_BLANKINGSRC_TIM2_OC3_COMP1 +#define COMP_BLANKINGSRCE_TIM3OC3 COMP_BLANKINGSRC_TIM3_OC3_COMP1 +#define COMP_BLANKINGSRCE_TIM3OC4 COMP_BLANKINGSRC_TIM3_OC4_COMP2 +#define COMP_BLANKINGSRCE_TIM8OC5 COMP_BLANKINGSRC_TIM8_OC5_COMP2 +#define COMP_BLANKINGSRCE_TIM15OC1 COMP_BLANKINGSRC_TIM15_OC1_COMP2 +#define COMP_BLANKINGSRCE_NONE COMP_BLANKINGSRC_NONE +#endif + +#if defined(STM32L0) +#define COMP_MODE_HIGHSPEED COMP_POWERMODE_MEDIUMSPEED +#define COMP_MODE_LOWSPEED COMP_POWERMODE_ULTRALOWPOWER +#else +#define COMP_MODE_HIGHSPEED COMP_POWERMODE_HIGHSPEED +#define COMP_MODE_MEDIUMSPEED COMP_POWERMODE_MEDIUMSPEED +#define COMP_MODE_LOWPOWER COMP_POWERMODE_LOWPOWER +#define COMP_MODE_ULTRALOWPOWER COMP_POWERMODE_ULTRALOWPOWER +#endif + +#endif + +#if defined(STM32U5) +#define __HAL_COMP_COMP1_EXTI_CLEAR_RASING_FLAG __HAL_COMP_COMP1_EXTI_CLEAR_RISING_FLAG +#endif + +/** + * @} + */ + +/** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose + * @{ + */ +#define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig +#if defined(STM32U5) +#define MPU_DEVICE_nGnRnE MPU_DEVICE_NGNRNE +#define MPU_DEVICE_nGnRE MPU_DEVICE_NGNRE +#define MPU_DEVICE_nGRE MPU_DEVICE_NGRE +#endif /* STM32U5 */ +/** + * @} + */ + +/** @defgroup CRC_Aliases CRC API aliases + * @{ + */ +#if defined(STM32H5) || defined(STM32C0) +#else +#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for + inter STM32 series compatibility */ +#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for + inter STM32 series compatibility */ +#endif +/** + * @} + */ + +/** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE +#define CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE + +/** + * @} + */ + +/** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define DAC1_CHANNEL_1 DAC_CHANNEL_1 +#define DAC1_CHANNEL_2 DAC_CHANNEL_2 +#define DAC2_CHANNEL_1 DAC_CHANNEL_1 +#define DAC_WAVE_NONE 0x00000000U +#define DAC_WAVE_NOISE DAC_CR_WAVE1_0 +#define DAC_WAVE_TRIANGLE DAC_CR_WAVE1_1 +#define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE +#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE +#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE + +#if defined(STM32G4) || defined(STM32H7) || defined (STM32U5) +#define DAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL +#define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL +#endif + +#if defined(STM32U5) +#define DAC_TRIGGER_STOP_LPTIM1_OUT DAC_TRIGGER_STOP_LPTIM1_CH1 +#define DAC_TRIGGER_STOP_LPTIM3_OUT DAC_TRIGGER_STOP_LPTIM3_CH1 +#define DAC_TRIGGER_LPTIM1_OUT DAC_TRIGGER_LPTIM1_CH1 +#define DAC_TRIGGER_LPTIM3_OUT DAC_TRIGGER_LPTIM3_CH1 +#endif + +#if defined(STM32H5) +#define DAC_TRIGGER_LPTIM1_OUT DAC_TRIGGER_LPTIM1_CH1 +#define DAC_TRIGGER_LPTIM2_OUT DAC_TRIGGER_LPTIM2_CH1 +#endif + +#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || \ + defined(STM32F4) || defined(STM32G4) +#define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID +#define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID +#endif + +/** + * @} + */ + +/** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose + * @{ + */ +#define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2 +#define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4 +#define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5 +#define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4 +#define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2 +#define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32 +#define HAL_REMAPDMA_TIM16_DMA_CH6 DMA_REMAP_TIM16_DMA_CH6 +#define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7 +#define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67 +#define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67 +#define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76 +#define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6 +#define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7 +#define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6 + +#define IS_HAL_REMAPDMA IS_DMA_REMAP +#define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE +#define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE + +#if defined(STM32L4) + +#define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI1 HAL_DMAMUX1_REQ_GEN_EXTI1 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI2 HAL_DMAMUX1_REQ_GEN_EXTI2 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI3 HAL_DMAMUX1_REQ_GEN_EXTI3 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI4 HAL_DMAMUX1_REQ_GEN_EXTI4 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI5 HAL_DMAMUX1_REQ_GEN_EXTI5 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI6 HAL_DMAMUX1_REQ_GEN_EXTI6 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI7 HAL_DMAMUX1_REQ_GEN_EXTI7 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI8 HAL_DMAMUX1_REQ_GEN_EXTI8 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI9 HAL_DMAMUX1_REQ_GEN_EXTI9 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI10 HAL_DMAMUX1_REQ_GEN_EXTI10 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI11 HAL_DMAMUX1_REQ_GEN_EXTI11 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI12 HAL_DMAMUX1_REQ_GEN_EXTI12 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI13 HAL_DMAMUX1_REQ_GEN_EXTI13 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI14 HAL_DMAMUX1_REQ_GEN_EXTI14 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI15 HAL_DMAMUX1_REQ_GEN_EXTI15 +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH3_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT +#define HAL_DMAMUX1_REQUEST_GEN_DSI_TE HAL_DMAMUX1_REQ_GEN_DSI_TE +#define HAL_DMAMUX1_REQUEST_GEN_DSI_EOT HAL_DMAMUX1_REQ_GEN_DSI_EOT +#define HAL_DMAMUX1_REQUEST_GEN_DMA2D_EOT HAL_DMAMUX1_REQ_GEN_DMA2D_EOT +#define HAL_DMAMUX1_REQUEST_GEN_LTDC_IT HAL_DMAMUX1_REQ_GEN_LTDC_IT + +#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT +#define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING +#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING +#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING + +#if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || \ + defined(STM32L4S7xx) || defined(STM32L4S9xx) +#define DMA_REQUEST_DCMI_PSSI DMA_REQUEST_DCMI +#elif defined(STM32L4P5xx) || defined(STM32L4Q5xx) +#define DMA_REQUEST_PSSI DMA_REQUEST_DCMI_PSSI +#define LL_DMAMUX_REQ_PSSI LL_DMAMUX_REQ_DCMI_PSSI +#endif /* STM32L4R5xx || STM32L4R9xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + +#endif /* STM32L4 */ + +#if defined(STM32G0) +#define DMA_REQUEST_DAC1_CHANNEL1 DMA_REQUEST_DAC1_CH1 +#define DMA_REQUEST_DAC1_CHANNEL2 DMA_REQUEST_DAC1_CH2 +#define DMA_REQUEST_TIM16_TRIG_COM DMA_REQUEST_TIM16_COM +#define DMA_REQUEST_TIM17_TRIG_COM DMA_REQUEST_TIM17_COM + +#define LL_DMAMUX_REQ_TIM16_TRIG_COM LL_DMAMUX_REQ_TIM16_COM +#define LL_DMAMUX_REQ_TIM17_TRIG_COM LL_DMAMUX_REQ_TIM17_COM +#endif + +#if defined(STM32H7) + +#define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1 +#define DMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2 + +#define BDMA_REQUEST_LP_UART1_RX BDMA_REQUEST_LPUART1_RX +#define BDMA_REQUEST_LP_UART1_TX BDMA_REQUEST_LPUART1_TX + +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT +#define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0 +#define HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO HAL_DMAMUX1_REQ_GEN_TIM12_TRGO + +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT +#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP HAL_DMAMUX2_REQ_GEN_I2C4_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP HAL_DMAMUX2_REQ_GEN_SPI6_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT HAL_DMAMUX2_REQ_GEN_COMP1_OUT +#define HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT HAL_DMAMUX2_REQ_GEN_COMP2_OUT +#define HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP HAL_DMAMUX2_REQ_GEN_RTC_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_EXTI0 HAL_DMAMUX2_REQ_GEN_EXTI0 +#define HAL_DMAMUX2_REQUEST_GEN_EXTI2 HAL_DMAMUX2_REQ_GEN_EXTI2 +#define HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT +#define HAL_DMAMUX2_REQUEST_GEN_SPI6_IT HAL_DMAMUX2_REQ_GEN_SPI6_IT +#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT +#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT +#define HAL_DMAMUX2_REQUEST_GEN_ADC3_IT HAL_DMAMUX2_REQ_GEN_ADC3_IT +#define HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT +#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT +#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT + +#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT +#define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING +#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING +#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING + +#define DFSDM_FILTER_EXT_TRIG_LPTIM1 DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT +#define DFSDM_FILTER_EXT_TRIG_LPTIM2 DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT +#define DFSDM_FILTER_EXT_TRIG_LPTIM3 DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT + +#define DAC_TRIGGER_LP1_OUT DAC_TRIGGER_LPTIM1_OUT +#define DAC_TRIGGER_LP2_OUT DAC_TRIGGER_LPTIM2_OUT + +#endif /* STM32H7 */ + +#if defined(STM32U5) +#define GPDMA1_REQUEST_DCMI GPDMA1_REQUEST_DCMI_PSSI +#endif /* STM32U5 */ +/** + * @} + */ + +/** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose + * @{ + */ + +#define TYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE +#define TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD +#define TYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD +#define TYPEPROGRAM_DOUBLEWORD FLASH_TYPEPROGRAM_DOUBLEWORD +#define TYPEERASE_SECTORS FLASH_TYPEERASE_SECTORS +#define TYPEERASE_PAGES FLASH_TYPEERASE_PAGES +#define TYPEERASE_PAGEERASE FLASH_TYPEERASE_PAGES +#define TYPEERASE_MASSERASE FLASH_TYPEERASE_MASSERASE +#define WRPSTATE_DISABLE OB_WRPSTATE_DISABLE +#define WRPSTATE_ENABLE OB_WRPSTATE_ENABLE +#define HAL_FLASH_TIMEOUT_VALUE FLASH_TIMEOUT_VALUE +#define OBEX_PCROP OPTIONBYTE_PCROP +#define OBEX_BOOTCONFIG OPTIONBYTE_BOOTCONFIG +#define PCROPSTATE_DISABLE OB_PCROP_STATE_DISABLE +#define PCROPSTATE_ENABLE OB_PCROP_STATE_ENABLE +#define TYPEERASEDATA_BYTE FLASH_TYPEERASEDATA_BYTE +#define TYPEERASEDATA_HALFWORD FLASH_TYPEERASEDATA_HALFWORD +#define TYPEERASEDATA_WORD FLASH_TYPEERASEDATA_WORD +#define TYPEPROGRAMDATA_BYTE FLASH_TYPEPROGRAMDATA_BYTE +#define TYPEPROGRAMDATA_HALFWORD FLASH_TYPEPROGRAMDATA_HALFWORD +#define TYPEPROGRAMDATA_WORD FLASH_TYPEPROGRAMDATA_WORD +#define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE +#define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD +#define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD +#if !defined(STM32F2) && !defined(STM32F4) && !defined(STM32F7) && !defined(STM32H7) && !defined(STM32H5) +#define PAGESIZE FLASH_PAGE_SIZE +#endif /* STM32F2 && STM32F4 && STM32F7 && STM32H7 && STM32H5 */ +#define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE +#define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD +#define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD +#define VOLTAGE_RANGE_1 FLASH_VOLTAGE_RANGE_1 +#define VOLTAGE_RANGE_2 FLASH_VOLTAGE_RANGE_2 +#define VOLTAGE_RANGE_3 FLASH_VOLTAGE_RANGE_3 +#define VOLTAGE_RANGE_4 FLASH_VOLTAGE_RANGE_4 +#define TYPEPROGRAM_FAST FLASH_TYPEPROGRAM_FAST +#define TYPEPROGRAM_FAST_AND_LAST FLASH_TYPEPROGRAM_FAST_AND_LAST +#define WRPAREA_BANK1_AREAA OB_WRPAREA_BANK1_AREAA +#define WRPAREA_BANK1_AREAB OB_WRPAREA_BANK1_AREAB +#define WRPAREA_BANK2_AREAA OB_WRPAREA_BANK2_AREAA +#define WRPAREA_BANK2_AREAB OB_WRPAREA_BANK2_AREAB +#define IWDG_STDBY_FREEZE OB_IWDG_STDBY_FREEZE +#define IWDG_STDBY_ACTIVE OB_IWDG_STDBY_RUN +#define IWDG_STOP_FREEZE OB_IWDG_STOP_FREEZE +#define IWDG_STOP_ACTIVE OB_IWDG_STOP_RUN +#define FLASH_ERROR_NONE HAL_FLASH_ERROR_NONE +#define FLASH_ERROR_RD HAL_FLASH_ERROR_RD +#define FLASH_ERROR_PG HAL_FLASH_ERROR_PROG +#define FLASH_ERROR_PGP HAL_FLASH_ERROR_PGS +#define FLASH_ERROR_WRP HAL_FLASH_ERROR_WRP +#define FLASH_ERROR_OPTV HAL_FLASH_ERROR_OPTV +#define FLASH_ERROR_OPTVUSR HAL_FLASH_ERROR_OPTVUSR +#define FLASH_ERROR_PROG HAL_FLASH_ERROR_PROG +#define FLASH_ERROR_OP HAL_FLASH_ERROR_OPERATION +#define FLASH_ERROR_PGA HAL_FLASH_ERROR_PGA +#define FLASH_ERROR_SIZE HAL_FLASH_ERROR_SIZE +#define FLASH_ERROR_SIZ HAL_FLASH_ERROR_SIZE +#define FLASH_ERROR_PGS HAL_FLASH_ERROR_PGS +#define FLASH_ERROR_MIS HAL_FLASH_ERROR_MIS +#define FLASH_ERROR_FAST HAL_FLASH_ERROR_FAST +#define FLASH_ERROR_FWWERR HAL_FLASH_ERROR_FWWERR +#define FLASH_ERROR_NOTZERO HAL_FLASH_ERROR_NOTZERO +#define FLASH_ERROR_OPERATION HAL_FLASH_ERROR_OPERATION +#define FLASH_ERROR_ERS HAL_FLASH_ERROR_ERS +#define OB_WDG_SW OB_IWDG_SW +#define OB_WDG_HW OB_IWDG_HW +#define OB_SDADC12_VDD_MONITOR_SET OB_SDACD_VDD_MONITOR_SET +#define OB_SDADC12_VDD_MONITOR_RESET OB_SDACD_VDD_MONITOR_RESET +#define OB_RAM_PARITY_CHECK_SET OB_SRAM_PARITY_SET +#define OB_RAM_PARITY_CHECK_RESET OB_SRAM_PARITY_RESET +#define IS_OB_SDADC12_VDD_MONITOR IS_OB_SDACD_VDD_MONITOR +#define OB_RDP_LEVEL0 OB_RDP_LEVEL_0 +#define OB_RDP_LEVEL1 OB_RDP_LEVEL_1 +#define OB_RDP_LEVEL2 OB_RDP_LEVEL_2 +#if defined(STM32G0) || defined(STM32C0) +#define OB_BOOT_LOCK_DISABLE OB_BOOT_ENTRY_FORCED_NONE +#define OB_BOOT_LOCK_ENABLE OB_BOOT_ENTRY_FORCED_FLASH +#else +#define OB_BOOT_ENTRY_FORCED_NONE OB_BOOT_LOCK_DISABLE +#define OB_BOOT_ENTRY_FORCED_FLASH OB_BOOT_LOCK_ENABLE +#endif +#if defined(STM32H7) +#define FLASH_FLAG_SNECCE_BANK1RR FLASH_FLAG_SNECCERR_BANK1 +#define FLASH_FLAG_DBECCE_BANK1RR FLASH_FLAG_DBECCERR_BANK1 +#define FLASH_FLAG_STRBER_BANK1R FLASH_FLAG_STRBERR_BANK1 +#define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2 +#define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2 +#define FLASH_FLAG_STRBER_BANK2R FLASH_FLAG_STRBERR_BANK2 +#define FLASH_FLAG_WDW FLASH_FLAG_WBNE +#define OB_WRP_SECTOR_All OB_WRP_SECTOR_ALL +#endif /* STM32H7 */ +#if defined(STM32H7RS) +#define FLASH_OPTKEY1 FLASH_OPT_KEY1 +#define FLASH_OPTKEY2 FLASH_OPT_KEY2 +#endif /* STM32H7RS */ +#if defined(STM32U5) +#define OB_USER_nRST_STOP OB_USER_NRST_STOP +#define OB_USER_nRST_STDBY OB_USER_NRST_STDBY +#define OB_USER_nRST_SHDW OB_USER_NRST_SHDW +#define OB_USER_nSWBOOT0 OB_USER_NSWBOOT0 +#define OB_USER_nBOOT0 OB_USER_NBOOT0 +#define OB_nBOOT0_RESET OB_NBOOT0_RESET +#define OB_nBOOT0_SET OB_NBOOT0_SET +#define OB_USER_SRAM134_RST OB_USER_SRAM_RST +#define OB_SRAM134_RST_ERASE OB_SRAM_RST_ERASE +#define OB_SRAM134_RST_NOT_ERASE OB_SRAM_RST_NOT_ERASE +#endif /* STM32U5 */ +#if defined(STM32U0) +#define OB_USER_nRST_STOP OB_USER_NRST_STOP +#define OB_USER_nRST_STDBY OB_USER_NRST_STDBY +#define OB_USER_nRST_SHDW OB_USER_NRST_SHDW +#define OB_USER_nBOOT_SEL OB_USER_NBOOT_SEL +#define OB_USER_nBOOT0 OB_USER_NBOOT0 +#define OB_USER_nBOOT1 OB_USER_NBOOT1 +#define OB_nBOOT0_RESET OB_NBOOT0_RESET +#define OB_nBOOT0_SET OB_NBOOT0_SET +#endif /* STM32U0 */ +#if defined(STM32H5) +#define FLASH_ECC_AREA_EDATA FLASH_ECC_AREA_EDATA_BANK1 +#endif /* STM32H5 */ + +/** + * @} + */ + +/** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose + * @{ + */ + +#if defined(STM32H7) +#define __HAL_RCC_JPEG_CLK_ENABLE __HAL_RCC_JPGDECEN_CLK_ENABLE +#define __HAL_RCC_JPEG_CLK_DISABLE __HAL_RCC_JPGDECEN_CLK_DISABLE +#define __HAL_RCC_JPEG_FORCE_RESET __HAL_RCC_JPGDECRST_FORCE_RESET +#define __HAL_RCC_JPEG_RELEASE_RESET __HAL_RCC_JPGDECRST_RELEASE_RESET +#define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE +#define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE +#endif /* STM32H7 */ + +/** + * @} + */ + +/** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose + * @{ + */ + +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9 I2C_FASTMODEPLUS_PA9 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10 I2C_FASTMODEPLUS_PA10 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9 +#define HAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1 +#define HAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2 +#define HAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3 +#if defined(STM32G4) + +#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SYSCFG_EnableIOSwitchBooster +#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SYSCFG_DisableIOSwitchBooster +#define HAL_SYSCFG_EnableIOAnalogSwitchVDD HAL_SYSCFG_EnableIOSwitchVDD +#define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD +#endif /* STM32G4 */ + +#if defined(STM32U5) + +#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SYSCFG_EnableIOAnalogBooster +#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SYSCFG_DisableIOAnalogBooster +#define HAL_SYSCFG_EnableIOAnalogSwitchVoltageSelection HAL_SYSCFG_EnableIOAnalogVoltageSelection +#define HAL_SYSCFG_DisableIOAnalogSwitchVoltageSelection HAL_SYSCFG_DisableIOAnalogVoltageSelection + +#endif /* STM32U5 */ + +#if defined(STM32H5) +#define SYSCFG_IT_FPU_IOC SBS_IT_FPU_IOC +#define SYSCFG_IT_FPU_DZC SBS_IT_FPU_DZC +#define SYSCFG_IT_FPU_UFC SBS_IT_FPU_UFC +#define SYSCFG_IT_FPU_OFC SBS_IT_FPU_OFC +#define SYSCFG_IT_FPU_IDC SBS_IT_FPU_IDC +#define SYSCFG_IT_FPU_IXC SBS_IT_FPU_IXC + +#define SYSCFG_BREAK_FLASH_ECC SBS_BREAK_FLASH_ECC +#define SYSCFG_BREAK_PVD SBS_BREAK_PVD +#define SYSCFG_BREAK_SRAM_ECC SBS_BREAK_SRAM_ECC +#define SYSCFG_BREAK_LOCKUP SBS_BREAK_LOCKUP + +#define SYSCFG_VREFBUF_VOLTAGE_SCALE0 VREFBUF_VOLTAGE_SCALE0 +#define SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_VOLTAGE_SCALE1 +#define SYSCFG_VREFBUF_VOLTAGE_SCALE2 VREFBUF_VOLTAGE_SCALE2 +#define SYSCFG_VREFBUF_VOLTAGE_SCALE3 VREFBUF_VOLTAGE_SCALE3 + +#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE VREFBUF_HIGH_IMPEDANCE_DISABLE +#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_HIGH_IMPEDANCE_ENABLE + +#define SYSCFG_FASTMODEPLUS_PB6 SBS_FASTMODEPLUS_PB6 +#define SYSCFG_FASTMODEPLUS_PB7 SBS_FASTMODEPLUS_PB7 +#define SYSCFG_FASTMODEPLUS_PB8 SBS_FASTMODEPLUS_PB8 +#define SYSCFG_FASTMODEPLUS_PB9 SBS_FASTMODEPLUS_PB9 + +#define SYSCFG_ETH_MII SBS_ETH_MII +#define SYSCFG_ETH_RMII SBS_ETH_RMII +#define IS_SYSCFG_ETHERNET_CONFIG IS_SBS_ETHERNET_CONFIG + +#define SYSCFG_MEMORIES_ERASE_FLAG_IPMEE SBS_MEMORIES_ERASE_FLAG_IPMEE +#define SYSCFG_MEMORIES_ERASE_FLAG_MCLR SBS_MEMORIES_ERASE_FLAG_MCLR +#define IS_SYSCFG_MEMORIES_ERASE_FLAG IS_SBS_MEMORIES_ERASE_FLAG + +#define IS_SYSCFG_CODE_CONFIG IS_SBS_CODE_CONFIG + +#define SYSCFG_MPU_NSEC SBS_MPU_NSEC +#define SYSCFG_VTOR_NSEC SBS_VTOR_NSEC +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define SYSCFG_SAU SBS_SAU +#define SYSCFG_MPU_SEC SBS_MPU_SEC +#define SYSCFG_VTOR_AIRCR_SEC SBS_VTOR_AIRCR_SEC +#define SYSCFG_LOCK_ALL SBS_LOCK_ALL +#else +#define SYSCFG_LOCK_ALL SBS_LOCK_ALL +#endif /* __ARM_FEATURE_CMSE */ + +#define SYSCFG_CLK SBS_CLK +#define SYSCFG_CLASSB SBS_CLASSB +#define SYSCFG_FPU SBS_FPU +#define SYSCFG_ALL SBS_ALL + +#define SYSCFG_SEC SBS_SEC +#define SYSCFG_NSEC SBS_NSEC + +#define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE __HAL_SBS_FPU_INTERRUPT_ENABLE +#define __HAL_SYSCFG_FPU_INTERRUPT_DISABLE __HAL_SBS_FPU_INTERRUPT_DISABLE + +#define __HAL_SYSCFG_BREAK_ECC_LOCK __HAL_SBS_BREAK_ECC_LOCK +#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK __HAL_SBS_BREAK_LOCKUP_LOCK +#define __HAL_SYSCFG_BREAK_PVD_LOCK __HAL_SBS_BREAK_PVD_LOCK +#define __HAL_SYSCFG_BREAK_SRAM_ECC_LOCK __HAL_SBS_BREAK_SRAM_ECC_LOCK + +#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE __HAL_SBS_FASTMODEPLUS_ENABLE +#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE __HAL_SBS_FASTMODEPLUS_DISABLE + +#define __HAL_SYSCFG_GET_MEMORIES_ERASE_STATUS __HAL_SBS_GET_MEMORIES_ERASE_STATUS +#define __HAL_SYSCFG_CLEAR_MEMORIES_ERASE_STATUS __HAL_SBS_CLEAR_MEMORIES_ERASE_STATUS + +#define IS_SYSCFG_FPU_INTERRUPT IS_SBS_FPU_INTERRUPT +#define IS_SYSCFG_BREAK_CONFIG IS_SBS_BREAK_CONFIG +#define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE IS_VREFBUF_VOLTAGE_SCALE +#define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE IS_VREFBUF_HIGH_IMPEDANCE +#define IS_SYSCFG_VREFBUF_TRIMMING IS_VREFBUF_TRIMMING +#define IS_SYSCFG_FASTMODEPLUS IS_SBS_FASTMODEPLUS +#define IS_SYSCFG_ITEMS_ATTRIBUTES IS_SBS_ITEMS_ATTRIBUTES +#define IS_SYSCFG_ATTRIBUTES IS_SBS_ATTRIBUTES +#define IS_SYSCFG_LOCK_ITEMS IS_SBS_LOCK_ITEMS + +#define HAL_SYSCFG_VREFBUF_VoltageScalingConfig HAL_VREFBUF_VoltageScalingConfig +#define HAL_SYSCFG_VREFBUF_HighImpedanceConfig HAL_VREFBUF_HighImpedanceConfig +#define HAL_SYSCFG_VREFBUF_TrimmingConfig HAL_VREFBUF_TrimmingConfig +#define HAL_SYSCFG_EnableVREFBUF HAL_EnableVREFBUF +#define HAL_SYSCFG_DisableVREFBUF HAL_DisableVREFBUF + +#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SBS_EnableIOAnalogSwitchBooster +#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SBS_DisableIOAnalogSwitchBooster +#define HAL_SYSCFG_ETHInterfaceSelect HAL_SBS_ETHInterfaceSelect + +#define HAL_SYSCFG_Lock HAL_SBS_Lock +#define HAL_SYSCFG_GetLock HAL_SBS_GetLock + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define HAL_SYSCFG_ConfigAttributes HAL_SBS_ConfigAttributes +#define HAL_SYSCFG_GetConfigAttributes HAL_SBS_GetConfigAttributes +#endif /* __ARM_FEATURE_CMSE */ + +#endif /* STM32H5 */ + + +/** + * @} + */ + + +/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose + * @{ + */ +#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7) || defined(STM32G4) +#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE +#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE +#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8 +#define FMC_NAND_PCC_MEM_BUS_WIDTH_16 FMC_NAND_MEM_BUS_WIDTH_16 +#elif defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) +#define FMC_NAND_WAIT_FEATURE_DISABLE FMC_NAND_PCC_WAIT_FEATURE_DISABLE +#define FMC_NAND_WAIT_FEATURE_ENABLE FMC_NAND_PCC_WAIT_FEATURE_ENABLE +#define FMC_NAND_MEM_BUS_WIDTH_8 FMC_NAND_PCC_MEM_BUS_WIDTH_8 +#define FMC_NAND_MEM_BUS_WIDTH_16 FMC_NAND_PCC_MEM_BUS_WIDTH_16 +#endif +/** + * @} + */ + +/** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define FSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef +#define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef +/** + * @} + */ + +/** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose + * @{ + */ +#define GET_GPIO_SOURCE GPIO_GET_INDEX +#define GET_GPIO_INDEX GPIO_GET_INDEX + +#if defined(STM32F4) +#define GPIO_AF12_SDMMC GPIO_AF12_SDIO +#define GPIO_AF12_SDMMC1 GPIO_AF12_SDIO +#endif + +#if defined(STM32F7) +#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1 +#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1 +#endif + +#if defined(STM32L4) +#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1 +#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1 +#endif + +#if defined(STM32H7) +#define GPIO_AF7_SDIO1 GPIO_AF7_SDMMC1 +#define GPIO_AF8_SDIO1 GPIO_AF8_SDMMC1 +#define GPIO_AF12_SDIO1 GPIO_AF12_SDMMC1 +#define GPIO_AF9_SDIO2 GPIO_AF9_SDMMC2 +#define GPIO_AF10_SDIO2 GPIO_AF10_SDMMC2 +#define GPIO_AF11_SDIO2 GPIO_AF11_SDMMC2 + +#if defined (STM32H743xx) || defined (STM32H753xx) || defined (STM32H750xx) || defined (STM32H742xx) || \ + defined (STM32H745xx) || defined (STM32H755xx) || defined (STM32H747xx) || defined (STM32H757xx) +#define GPIO_AF10_OTG2_HS GPIO_AF10_OTG2_FS +#define GPIO_AF10_OTG1_FS GPIO_AF10_OTG1_HS +#define GPIO_AF12_OTG2_FS GPIO_AF12_OTG1_FS +#endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || \ + STM32H757xx */ +#endif /* STM32H7 */ + +#define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1 +#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1 +#define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1 + +#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || \ + defined(STM32G4) || defined(STM32H7) || defined(STM32WB) || defined(STM32U5) +#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW +#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM +#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH +#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH +#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7 || STM32WB || STM32U5*/ + +#if defined(STM32L1) +#define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW +#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM +#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH +#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH +#endif /* STM32L1 */ + +#if defined(STM32F0) || defined(STM32F3) || defined(STM32F1) +#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW +#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM +#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH +#endif /* STM32F0 || STM32F3 || STM32F1 */ + +#define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1 + +#if defined(STM32U5) || defined(STM32H5) +#define GPIO_AF0_RTC_50Hz GPIO_AF0_RTC_50HZ +#endif /* STM32U5 || STM32H5 */ +#if defined(STM32U5) +#define GPIO_AF0_S2DSTOP GPIO_AF0_SRDSTOP +#define GPIO_AF11_LPGPIO GPIO_AF11_LPGPIO1 +#endif /* STM32U5 */ + +#if defined(STM32WBA) +#define GPIO_AF11_RF_ANTSW0 GPIO_AF11_RF +#define GPIO_AF11_RF_ANTSW1 GPIO_AF11_RF +#define GPIO_AF11_RF_ANTSW2 GPIO_AF11_RF +#define GPIO_AF11_RF_IO1 GPIO_AF11_RF +#define GPIO_AF11_RF_IO2 GPIO_AF11_RF +#define GPIO_AF11_RF_IO3 GPIO_AF11_RF +#define GPIO_AF11_RF_IO4 GPIO_AF11_RF +#define GPIO_AF11_RF_IO5 GPIO_AF11_RF +#define GPIO_AF11_RF_IO6 GPIO_AF11_RF +#define GPIO_AF11_RF_IO7 GPIO_AF11_RF +#define GPIO_AF11_RF_IO8 GPIO_AF11_RF +#define GPIO_AF11_RF_IO9 GPIO_AF11_RF +#endif /* STM32WBA */ +/** + * @} + */ + +/** @defgroup HAL_GTZC_Aliased_Defines HAL GTZC Aliased Defines maintained for legacy purpose + * @{ + */ +#if defined(STM32U5) +#define GTZC_PERIPH_DCMI GTZC_PERIPH_DCMI_PSSI +#define GTZC_PERIPH_LTDC GTZC_PERIPH_LTDCUSB +#endif /* STM32U5 */ +#if defined(STM32H5) +#define GTZC_PERIPH_DAC12 GTZC_PERIPH_DAC1 +#define GTZC_PERIPH_ADC12 GTZC_PERIPH_ADC +#define GTZC_PERIPH_USBFS GTZC_PERIPH_USB +#endif /* STM32H5 */ +#if defined(STM32H5) || defined(STM32U5) +#define GTZC_MCPBB_NB_VCTR_REG_MAX GTZC_MPCBB_NB_VCTR_REG_MAX +#define GTZC_MCPBB_NB_LCK_VCTR_REG_MAX GTZC_MPCBB_NB_LCK_VCTR_REG_MAX +#define GTZC_MCPBB_SUPERBLOCK_UNLOCKED GTZC_MPCBB_SUPERBLOCK_UNLOCKED +#define GTZC_MCPBB_SUPERBLOCK_LOCKED GTZC_MPCBB_SUPERBLOCK_LOCKED +#define GTZC_MCPBB_BLOCK_NSEC GTZC_MPCBB_BLOCK_NSEC +#define GTZC_MCPBB_BLOCK_SEC GTZC_MPCBB_BLOCK_SEC +#define GTZC_MCPBB_BLOCK_NPRIV GTZC_MPCBB_BLOCK_NPRIV +#define GTZC_MCPBB_BLOCK_PRIV GTZC_MPCBB_BLOCK_PRIV +#define GTZC_MCPBB_LOCK_OFF GTZC_MPCBB_LOCK_OFF +#define GTZC_MCPBB_LOCK_ON GTZC_MPCBB_LOCK_ON +#endif /* STM32H5 || STM32U5 */ +/** + * @} + */ + +/** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose + * @{ + */ +#define HRTIM_TIMDELAYEDPROTECTION_DISABLED HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6 +#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7 +#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7 + +#define __HAL_HRTIM_SetCounter __HAL_HRTIM_SETCOUNTER +#define __HAL_HRTIM_GetCounter __HAL_HRTIM_GETCOUNTER +#define __HAL_HRTIM_SetPeriod __HAL_HRTIM_SETPERIOD +#define __HAL_HRTIM_GetPeriod __HAL_HRTIM_GETPERIOD +#define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER +#define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER +#define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE +#define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE + +#if defined(STM32F3) || defined(STM32G4) || defined(STM32H7) +#define HRTIMInterruptResquests HRTIMInterruptRequests +#endif /* STM32F3 || STM32G4 || STM32H7 */ + +#if defined(STM32G4) +#define HAL_HRTIM_ExternalEventCounterConfig HAL_HRTIM_ExtEventCounterConfig +#define HAL_HRTIM_ExternalEventCounterEnable HAL_HRTIM_ExtEventCounterEnable +#define HAL_HRTIM_ExternalEventCounterDisable HAL_HRTIM_ExtEventCounterDisable +#define HAL_HRTIM_ExternalEventCounterReset HAL_HRTIM_ExtEventCounterReset +#define HRTIM_TIMEEVENT_A HRTIM_EVENTCOUNTER_A +#define HRTIM_TIMEEVENT_B HRTIM_EVENTCOUNTER_B +#define HRTIM_TIMEEVENTRESETMODE_UNCONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_UNCONDITIONAL +#define HRTIM_TIMEEVENTRESETMODE_CONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_CONDITIONAL +#endif /* STM32G4 */ + +#if defined(STM32H7) +#define HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9 + +#define HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9 +#endif /* STM32H7 */ + +#if defined(STM32F3) +/** @brief Constants defining available sources associated to external events. + */ +#define HRTIM_EVENTSRC_1 (0x00000000U) +#define HRTIM_EVENTSRC_2 (HRTIM_EECR1_EE1SRC_0) +#define HRTIM_EVENTSRC_3 (HRTIM_EECR1_EE1SRC_1) +#define HRTIM_EVENTSRC_4 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) + +/** @brief Constants defining the DLL calibration periods (in micro seconds) + */ +#define HRTIM_CALIBRATIONRATE_7300 0x00000000U +#define HRTIM_CALIBRATIONRATE_910 (HRTIM_DLLCR_CALRTE_0) +#define HRTIM_CALIBRATIONRATE_114 (HRTIM_DLLCR_CALRTE_1) +#define HRTIM_CALIBRATIONRATE_14 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0) +#endif /* STM32F3 */ + +/** + * @} + */ + +/** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose + * @{ + */ +#define I2C_DUALADDRESS_DISABLED I2C_DUALADDRESS_DISABLE +#define I2C_DUALADDRESS_ENABLED I2C_DUALADDRESS_ENABLE +#define I2C_GENERALCALL_DISABLED I2C_GENERALCALL_DISABLE +#define I2C_GENERALCALL_ENABLED I2C_GENERALCALL_ENABLE +#define I2C_NOSTRETCH_DISABLED I2C_NOSTRETCH_DISABLE +#define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE +#define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE +#define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE +#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || \ + defined(STM32L1) || defined(STM32F7) +#define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX +#define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX +#define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX +#define HAL_I2C_STATE_MASTER_BUSY_RX HAL_I2C_STATE_BUSY_RX +#define HAL_I2C_STATE_SLAVE_BUSY_TX HAL_I2C_STATE_BUSY_TX +#define HAL_I2C_STATE_SLAVE_BUSY_RX HAL_I2C_STATE_BUSY_RX +#endif +/** + * @} + */ + +/** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose + * @{ + */ +#define IRDA_ONE_BIT_SAMPLE_DISABLED IRDA_ONE_BIT_SAMPLE_DISABLE +#define IRDA_ONE_BIT_SAMPLE_ENABLED IRDA_ONE_BIT_SAMPLE_ENABLE + +/** + * @} + */ + +/** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose + * @{ + */ +#define KR_KEY_RELOAD IWDG_KEY_RELOAD +#define KR_KEY_ENABLE IWDG_KEY_ENABLE +#define KR_KEY_EWA IWDG_KEY_WRITE_ACCESS_ENABLE +#define KR_KEY_DWA IWDG_KEY_WRITE_ACCESS_DISABLE +/** + * @} + */ + +/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose + * @{ + */ + +#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION +#define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS LPTIM_CLOCKSAMPLETIME_2TRANSITIONS +#define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS LPTIM_CLOCKSAMPLETIME_4TRANSITIONS +#define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS LPTIM_CLOCKSAMPLETIME_8TRANSITIONS + +#define LPTIM_CLOCKPOLARITY_RISINGEDGE LPTIM_CLOCKPOLARITY_RISING +#define LPTIM_CLOCKPOLARITY_FALLINGEDGE LPTIM_CLOCKPOLARITY_FALLING +#define LPTIM_CLOCKPOLARITY_BOTHEDGES LPTIM_CLOCKPOLARITY_RISING_FALLING + +#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION +#define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS LPTIM_TRIGSAMPLETIME_2TRANSITIONS +#define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS LPTIM_TRIGSAMPLETIME_4TRANSITIONS +#define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS + +/* The following 3 definition have also been present in a temporary version of lptim.h */ +/* They need to be renamed also to the right name, just in case */ +#define LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSITIONS +#define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS +#define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS + + +/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose + * @{ + */ +#define HAL_LPTIM_ReadCompare HAL_LPTIM_ReadCapturedValue +/** + * @} + */ + +#if defined(STM32U5) +#define LPTIM_ISR_CC1 LPTIM_ISR_CC1IF +#define LPTIM_ISR_CC2 LPTIM_ISR_CC2IF +#define LPTIM_CHANNEL_ALL 0x00000000U +#endif /* STM32U5 */ +/** + * @} + */ + +/** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose + * @{ + */ +#define HAL_NAND_Read_Page HAL_NAND_Read_Page_8b +#define HAL_NAND_Write_Page HAL_NAND_Write_Page_8b +#define HAL_NAND_Read_SpareArea HAL_NAND_Read_SpareArea_8b +#define HAL_NAND_Write_SpareArea HAL_NAND_Write_SpareArea_8b + +#define NAND_AddressTypedef NAND_AddressTypeDef + +#define __ARRAY_ADDRESS ARRAY_ADDRESS +#define __ADDR_1st_CYCLE ADDR_1ST_CYCLE +#define __ADDR_2nd_CYCLE ADDR_2ND_CYCLE +#define __ADDR_3rd_CYCLE ADDR_3RD_CYCLE +#define __ADDR_4th_CYCLE ADDR_4TH_CYCLE +/** + * @} + */ + +/** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose + * @{ + */ +#define NOR_StatusTypedef HAL_NOR_StatusTypeDef +#define NOR_SUCCESS HAL_NOR_STATUS_SUCCESS +#define NOR_ONGOING HAL_NOR_STATUS_ONGOING +#define NOR_ERROR HAL_NOR_STATUS_ERROR +#define NOR_TIMEOUT HAL_NOR_STATUS_TIMEOUT + +#define __NOR_WRITE NOR_WRITE +#define __NOR_ADDR_SHIFT NOR_ADDR_SHIFT +/** + * @} + */ + +/** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose + * @{ + */ + +#define OPAMP_NONINVERTINGINPUT_VP0 OPAMP_NONINVERTINGINPUT_IO0 +#define OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1 +#define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2 +#define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3 + +#define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0 +#define OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1 +#define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2 +#define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3 + +#define OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 +#define OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 + +#define IOPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 +#define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 + +#define OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0 +#define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1 + +#define OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1 + +#define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO +#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 +#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1 + +#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4) || defined(STM32U5) +#define HAL_OPAMP_MSP_INIT_CB_ID HAL_OPAMP_MSPINIT_CB_ID +#define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID +#endif + +#if defined(STM32L4) || defined(STM32L5) +#define OPAMP_POWERMODE_NORMAL OPAMP_POWERMODE_NORMALPOWER +#elif defined(STM32G4) +#define OPAMP_POWERMODE_NORMAL OPAMP_POWERMODE_NORMALSPEED +#endif + +/** + * @} + */ + +/** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose + * @{ + */ +#define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS + +#if defined(STM32H7) +#define I2S_IT_TXE I2S_IT_TXP +#define I2S_IT_RXNE I2S_IT_RXP + +#define I2S_FLAG_TXE I2S_FLAG_TXP +#define I2S_FLAG_RXNE I2S_FLAG_RXP +#endif + +#if defined(STM32F7) +#define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL +#endif +/** + * @} + */ + +/** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose + * @{ + */ + +/* Compact Flash-ATA registers description */ +#define CF_DATA ATA_DATA +#define CF_SECTOR_COUNT ATA_SECTOR_COUNT +#define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER +#define CF_CYLINDER_LOW ATA_CYLINDER_LOW +#define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH +#define CF_CARD_HEAD ATA_CARD_HEAD +#define CF_STATUS_CMD ATA_STATUS_CMD +#define CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE +#define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA + +/* Compact Flash-ATA commands */ +#define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD +#define CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD +#define CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD +#define CF_IDENTIFY_CMD ATA_IDENTIFY_CMD + +#define PCCARD_StatusTypedef HAL_PCCARD_StatusTypeDef +#define PCCARD_SUCCESS HAL_PCCARD_STATUS_SUCCESS +#define PCCARD_ONGOING HAL_PCCARD_STATUS_ONGOING +#define PCCARD_ERROR HAL_PCCARD_STATUS_ERROR +#define PCCARD_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT +/** + * @} + */ + +/** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define FORMAT_BIN RTC_FORMAT_BIN +#define FORMAT_BCD RTC_FORMAT_BCD + +#define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE +#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE +#define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE +#define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE + +#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE +#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE +#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE +#define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT +#define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT + +#define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT +#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1 +#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1 +#define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2 + +#define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE +#define RTC_OUTPUT_REMAP_PB14 RTC_OUTPUT_REMAP_POS1 +#define RTC_OUTPUT_REMAP_PB2 RTC_OUTPUT_REMAP_POS1 + +#define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT +#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 +#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1 + +#if defined(STM32H5) || defined(STM32H7RS) || defined(STM32N6) +#define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE +#define TAMP_SECRETDEVICE_ERASE_BKP_SRAM TAMP_DEVICESECRETS_ERASE_BKPSRAM +#endif /* STM32H5 || STM32H7RS || STM32N6 */ + +#if defined(STM32WBA) +#define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE +#define TAMP_SECRETDEVICE_ERASE_SRAM2 TAMP_DEVICESECRETS_ERASE_SRAM2 +#define TAMP_SECRETDEVICE_ERASE_RHUK TAMP_DEVICESECRETS_ERASE_RHUK +#define TAMP_SECRETDEVICE_ERASE_ICACHE TAMP_DEVICESECRETS_ERASE_ICACHE +#define TAMP_SECRETDEVICE_ERASE_SAES_AES_HASH TAMP_DEVICESECRETS_ERASE_SAES_AES_HASH +#define TAMP_SECRETDEVICE_ERASE_PKA_SRAM TAMP_DEVICESECRETS_ERASE_PKA_SRAM +#define TAMP_SECRETDEVICE_ERASE_ALL TAMP_DEVICESECRETS_ERASE_ALL +#endif /* STM32WBA */ + +#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) || defined(STM32N6) +#define TAMP_SECRETDEVICE_ERASE_DISABLE TAMP_DEVICESECRETS_ERASE_NONE +#define TAMP_SECRETDEVICE_ERASE_ENABLE TAMP_SECRETDEVICE_ERASE_ALL +#endif /* STM32H5 || STM32WBA || STM32H7RS || STM32N6 */ + +#if defined(STM32F7) || defined(STM32WB) +#define RTC_TAMPCR_TAMPXE RTC_TAMPER_ENABLE_BITS_MASK +#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_IT_ENABLE_BITS_MASK +#endif /* STM32F7 || STM32WB */ + +#if defined(STM32H7) +#define RTC_TAMPCR_TAMPXE RTC_TAMPER_X +#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_X_INTERRUPT +#endif /* STM32H7 */ + +#if defined(STM32F7) || defined(STM32H7) || defined(STM32L0) || defined(STM32WB) +#define RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1 +#define RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2 +#define RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3 +#define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMP +#endif /* STM32F7 || STM32H7 || STM32L0 || STM32WB */ + +/** + * @} + */ + + +/** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose + * @{ + */ +#define SMARTCARD_NACK_ENABLED SMARTCARD_NACK_ENABLE +#define SMARTCARD_NACK_DISABLED SMARTCARD_NACK_DISABLE + +#define SMARTCARD_ONEBIT_SAMPLING_DISABLED SMARTCARD_ONE_BIT_SAMPLE_DISABLE +#define SMARTCARD_ONEBIT_SAMPLING_ENABLED SMARTCARD_ONE_BIT_SAMPLE_ENABLE +#define SMARTCARD_ONEBIT_SAMPLING_DISABLE SMARTCARD_ONE_BIT_SAMPLE_DISABLE +#define SMARTCARD_ONEBIT_SAMPLING_ENABLE SMARTCARD_ONE_BIT_SAMPLE_ENABLE + +#define SMARTCARD_TIMEOUT_DISABLED SMARTCARD_TIMEOUT_DISABLE +#define SMARTCARD_TIMEOUT_ENABLED SMARTCARD_TIMEOUT_ENABLE + +#define SMARTCARD_LASTBIT_DISABLED SMARTCARD_LASTBIT_DISABLE +#define SMARTCARD_LASTBIT_ENABLED SMARTCARD_LASTBIT_ENABLE +/** + * @} + */ + + +/** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose + * @{ + */ +#define SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE +#define SMBUS_DUALADDRESS_ENABLED SMBUS_DUALADDRESS_ENABLE +#define SMBUS_GENERALCALL_DISABLED SMBUS_GENERALCALL_DISABLE +#define SMBUS_GENERALCALL_ENABLED SMBUS_GENERALCALL_ENABLE +#define SMBUS_NOSTRETCH_DISABLED SMBUS_NOSTRETCH_DISABLE +#define SMBUS_NOSTRETCH_ENABLED SMBUS_NOSTRETCH_ENABLE +#define SMBUS_ANALOGFILTER_ENABLED SMBUS_ANALOGFILTER_ENABLE +#define SMBUS_ANALOGFILTER_DISABLED SMBUS_ANALOGFILTER_DISABLE +#define SMBUS_PEC_DISABLED SMBUS_PEC_DISABLE +#define SMBUS_PEC_ENABLED SMBUS_PEC_ENABLE +#define HAL_SMBUS_STATE_SLAVE_LISTEN HAL_SMBUS_STATE_LISTEN +/** + * @} + */ + +/** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose + * @{ + */ +#define SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE +#define SPI_TIMODE_ENABLED SPI_TIMODE_ENABLE + +#define SPI_CRCCALCULATION_DISABLED SPI_CRCCALCULATION_DISABLE +#define SPI_CRCCALCULATION_ENABLED SPI_CRCCALCULATION_ENABLE + +#define SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE +#define SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE + +#if defined(STM32H7) + +#define SPI_FLAG_TXE SPI_FLAG_TXP +#define SPI_FLAG_RXNE SPI_FLAG_RXP + +#define SPI_IT_TXE SPI_IT_TXP +#define SPI_IT_RXNE SPI_IT_RXP + +#define SPI_FRLVL_EMPTY SPI_RX_FIFO_0PACKET +#define SPI_FRLVL_QUARTER_FULL SPI_RX_FIFO_1PACKET +#define SPI_FRLVL_HALF_FULL SPI_RX_FIFO_2PACKET +#define SPI_FRLVL_FULL SPI_RX_FIFO_3PACKET + +#endif /* STM32H7 */ + +/** + * @} + */ + +/** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose + * @{ + */ +#define CCER_CCxE_MASK TIM_CCER_CCxE_MASK +#define CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK + +#define TIM_DMABase_CR1 TIM_DMABASE_CR1 +#define TIM_DMABase_CR2 TIM_DMABASE_CR2 +#define TIM_DMABase_SMCR TIM_DMABASE_SMCR +#define TIM_DMABase_DIER TIM_DMABASE_DIER +#define TIM_DMABase_SR TIM_DMABASE_SR +#define TIM_DMABase_EGR TIM_DMABASE_EGR +#define TIM_DMABase_CCMR1 TIM_DMABASE_CCMR1 +#define TIM_DMABase_CCMR2 TIM_DMABASE_CCMR2 +#define TIM_DMABase_CCER TIM_DMABASE_CCER +#define TIM_DMABase_CNT TIM_DMABASE_CNT +#define TIM_DMABase_PSC TIM_DMABASE_PSC +#define TIM_DMABase_ARR TIM_DMABASE_ARR +#define TIM_DMABase_RCR TIM_DMABASE_RCR +#define TIM_DMABase_CCR1 TIM_DMABASE_CCR1 +#define TIM_DMABase_CCR2 TIM_DMABASE_CCR2 +#define TIM_DMABase_CCR3 TIM_DMABASE_CCR3 +#define TIM_DMABase_CCR4 TIM_DMABASE_CCR4 +#define TIM_DMABase_BDTR TIM_DMABASE_BDTR +#define TIM_DMABase_DCR TIM_DMABASE_DCR +#define TIM_DMABase_DMAR TIM_DMABASE_DMAR +#define TIM_DMABase_OR1 TIM_DMABASE_OR1 +#define TIM_DMABase_CCMR3 TIM_DMABASE_CCMR3 +#define TIM_DMABase_CCR5 TIM_DMABASE_CCR5 +#define TIM_DMABase_CCR6 TIM_DMABASE_CCR6 +#define TIM_DMABase_OR2 TIM_DMABASE_OR2 +#define TIM_DMABase_OR3 TIM_DMABASE_OR3 +#define TIM_DMABase_OR TIM_DMABASE_OR + +#define TIM_EventSource_Update TIM_EVENTSOURCE_UPDATE +#define TIM_EventSource_CC1 TIM_EVENTSOURCE_CC1 +#define TIM_EventSource_CC2 TIM_EVENTSOURCE_CC2 +#define TIM_EventSource_CC3 TIM_EVENTSOURCE_CC3 +#define TIM_EventSource_CC4 TIM_EVENTSOURCE_CC4 +#define TIM_EventSource_COM TIM_EVENTSOURCE_COM +#define TIM_EventSource_Trigger TIM_EVENTSOURCE_TRIGGER +#define TIM_EventSource_Break TIM_EVENTSOURCE_BREAK +#define TIM_EventSource_Break2 TIM_EVENTSOURCE_BREAK2 + +#define TIM_DMABurstLength_1Transfer TIM_DMABURSTLENGTH_1TRANSFER +#define TIM_DMABurstLength_2Transfers TIM_DMABURSTLENGTH_2TRANSFERS +#define TIM_DMABurstLength_3Transfers TIM_DMABURSTLENGTH_3TRANSFERS +#define TIM_DMABurstLength_4Transfers TIM_DMABURSTLENGTH_4TRANSFERS +#define TIM_DMABurstLength_5Transfers TIM_DMABURSTLENGTH_5TRANSFERS +#define TIM_DMABurstLength_6Transfers TIM_DMABURSTLENGTH_6TRANSFERS +#define TIM_DMABurstLength_7Transfers TIM_DMABURSTLENGTH_7TRANSFERS +#define TIM_DMABurstLength_8Transfers TIM_DMABURSTLENGTH_8TRANSFERS +#define TIM_DMABurstLength_9Transfers TIM_DMABURSTLENGTH_9TRANSFERS +#define TIM_DMABurstLength_10Transfers TIM_DMABURSTLENGTH_10TRANSFERS +#define TIM_DMABurstLength_11Transfers TIM_DMABURSTLENGTH_11TRANSFERS +#define TIM_DMABurstLength_12Transfers TIM_DMABURSTLENGTH_12TRANSFERS +#define TIM_DMABurstLength_13Transfers TIM_DMABURSTLENGTH_13TRANSFERS +#define TIM_DMABurstLength_14Transfers TIM_DMABURSTLENGTH_14TRANSFERS +#define TIM_DMABurstLength_15Transfers TIM_DMABURSTLENGTH_15TRANSFERS +#define TIM_DMABurstLength_16Transfers TIM_DMABURSTLENGTH_16TRANSFERS +#define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS +#define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS + +#if defined(STM32L0) +#define TIM22_TI1_GPIO1 TIM22_TI1_GPIO +#define TIM22_TI1_GPIO2 TIM22_TI1_GPIO +#endif + +#if defined(STM32F3) +#define IS_TIM_HALL_INTERFACE_INSTANCE IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE +#endif + +#if defined(STM32H7) +#define TIM_TIM1_ETR_COMP1_OUT TIM_TIM1_ETR_COMP1 +#define TIM_TIM1_ETR_COMP2_OUT TIM_TIM1_ETR_COMP2 +#define TIM_TIM8_ETR_COMP1_OUT TIM_TIM8_ETR_COMP1 +#define TIM_TIM8_ETR_COMP2_OUT TIM_TIM8_ETR_COMP2 +#define TIM_TIM2_ETR_COMP1_OUT TIM_TIM2_ETR_COMP1 +#define TIM_TIM2_ETR_COMP2_OUT TIM_TIM2_ETR_COMP2 +#define TIM_TIM3_ETR_COMP1_OUT TIM_TIM3_ETR_COMP1 +#define TIM_TIM1_TI1_COMP1_OUT TIM_TIM1_TI1_COMP1 +#define TIM_TIM8_TI1_COMP2_OUT TIM_TIM8_TI1_COMP2 +#define TIM_TIM2_TI4_COMP1_OUT TIM_TIM2_TI4_COMP1 +#define TIM_TIM2_TI4_COMP2_OUT TIM_TIM2_TI4_COMP2 +#define TIM_TIM2_TI4_COMP1COMP2_OUT TIM_TIM2_TI4_COMP1_COMP2 +#define TIM_TIM3_TI1_COMP1_OUT TIM_TIM3_TI1_COMP1 +#define TIM_TIM3_TI1_COMP2_OUT TIM_TIM3_TI1_COMP2 +#define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2 +#endif + +#if defined(STM32U5) || defined(STM32MP2) +#define OCREF_CLEAR_SELECT_Pos OCREF_CLEAR_SELECT_POS +#define OCREF_CLEAR_SELECT_Msk OCREF_CLEAR_SELECT_MSK +#endif +/** + * @} + */ + +/** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose + * @{ + */ +#define TSC_SYNC_POL_FALL TSC_SYNC_POLARITY_FALLING +#define TSC_SYNC_POL_RISE_HIGH TSC_SYNC_POLARITY_RISING +/** + * @} + */ + +/** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose + * @{ + */ +#define UART_ONEBIT_SAMPLING_DISABLED UART_ONE_BIT_SAMPLE_DISABLE +#define UART_ONEBIT_SAMPLING_ENABLED UART_ONE_BIT_SAMPLE_ENABLE +#define UART_ONE_BIT_SAMPLE_DISABLED UART_ONE_BIT_SAMPLE_DISABLE +#define UART_ONE_BIT_SAMPLE_ENABLED UART_ONE_BIT_SAMPLE_ENABLE + +#define __HAL_UART_ONEBIT_ENABLE __HAL_UART_ONE_BIT_SAMPLE_ENABLE +#define __HAL_UART_ONEBIT_DISABLE __HAL_UART_ONE_BIT_SAMPLE_DISABLE + +#define __DIV_SAMPLING16 UART_DIV_SAMPLING16 +#define __DIVMANT_SAMPLING16 UART_DIVMANT_SAMPLING16 +#define __DIVFRAQ_SAMPLING16 UART_DIVFRAQ_SAMPLING16 +#define __UART_BRR_SAMPLING16 UART_BRR_SAMPLING16 + +#define __DIV_SAMPLING8 UART_DIV_SAMPLING8 +#define __DIVMANT_SAMPLING8 UART_DIVMANT_SAMPLING8 +#define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8 +#define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8 + +#define __DIV_LPUART UART_DIV_LPUART + +#define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE +#define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK + +/** + * @} + */ + + +/** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose + * @{ + */ + +#define USART_CLOCK_DISABLED USART_CLOCK_DISABLE +#define USART_CLOCK_ENABLED USART_CLOCK_ENABLE + +#define USARTNACK_ENABLED USART_NACK_ENABLE +#define USARTNACK_DISABLED USART_NACK_DISABLE +/** + * @} + */ + +/** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose + * @{ + */ +#define CFR_BASE WWDG_CFR_BASE + +/** + * @} + */ + +/** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose + * @{ + */ +#define CAN_FilterFIFO0 CAN_FILTER_FIFO0 +#define CAN_FilterFIFO1 CAN_FILTER_FIFO1 +#define CAN_IT_RQCP0 CAN_IT_TME +#define CAN_IT_RQCP1 CAN_IT_TME +#define CAN_IT_RQCP2 CAN_IT_TME +#define INAK_TIMEOUT CAN_TIMEOUT_VALUE +#define SLAK_TIMEOUT CAN_TIMEOUT_VALUE +#define CAN_TXSTATUS_FAILED ((uint8_t)0x00U) +#define CAN_TXSTATUS_OK ((uint8_t)0x01U) +#define CAN_TXSTATUS_PENDING ((uint8_t)0x02U) + +/** + * @} + */ + +/** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose + * @{ + */ + +#define VLAN_TAG ETH_VLAN_TAG +#define MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD +#define MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD +#define JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD +#define MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK +#define MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK +#define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK +#define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK + +#define ETH_MMCCR 0x00000100U +#define ETH_MMCRIR 0x00000104U +#define ETH_MMCTIR 0x00000108U +#define ETH_MMCRIMR 0x0000010CU +#define ETH_MMCTIMR 0x00000110U +#define ETH_MMCTGFSCCR 0x0000014CU +#define ETH_MMCTGFMSCCR 0x00000150U +#define ETH_MMCTGFCR 0x00000168U +#define ETH_MMCRFCECR 0x00000194U +#define ETH_MMCRFAECR 0x00000198U +#define ETH_MMCRGUFCR 0x000001C4U + +#define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */ +#define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */ +#define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */ +#define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */ +#define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to + the MAC transmitter) */ +#define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from + MAC transmitter */ +#define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus + or flushing the TxFIFO */ +#define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status + of previous frame or IFG/backoff period to be over */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and + transmitting a Pause control frame (in full duplex mode) */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input + frame for transmission */ +#define ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U /* MAC MII transmit engine active */ +#define ETH_MAC_RXFIFO_EMPTY 0x00000000U /* Rx FIFO fill level: empty */ +#define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control + de-activate threshold */ +#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control + activate threshold */ +#define ETH_MAC_RXFIFO_FULL 0x00000300U /* Rx FIFO fill level: full */ +#if defined(STM32F1) +#else +#define ETH_MAC_READCONTROLLER_IDLE 0x00000000U /* Rx FIFO read controller IDLE state */ +#define ETH_MAC_READCONTROLLER_READING_DATA 0x00000020U /* Rx FIFO read controller Reading frame data */ +#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status + (or time-stamp) */ +#endif +#define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and + status */ +#define ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U /* Rx FIFO write controller active */ +#define ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U /* MAC small FIFO read / write controllers not active */ +#define ETH_MAC_SMALL_FIFO_READ_ACTIVE 0x00000002U /* MAC small FIFO read controller active */ +#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE 0x00000004U /* MAC small FIFO write controller active */ +#define ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */ +#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */ + +#define ETH_TxPacketConfig ETH_TxPacketConfigTypeDef /* Transmit Packet Configuration structure definition */ + +/** + * @} + */ + +/** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose + * @{ + */ +#define HAL_DCMI_ERROR_OVF HAL_DCMI_ERROR_OVR +#define DCMI_IT_OVF DCMI_IT_OVR +#define DCMI_FLAG_OVFRI DCMI_FLAG_OVRRI +#define DCMI_FLAG_OVFMI DCMI_FLAG_OVRMI + +#define HAL_DCMI_ConfigCROP HAL_DCMI_ConfigCrop +#define HAL_DCMI_EnableCROP HAL_DCMI_EnableCrop +#define HAL_DCMI_DisableCROP HAL_DCMI_DisableCrop + +/** + * @} + */ + +#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \ + || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \ + || defined(STM32H7) +/** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose + * @{ + */ +#define DMA2D_ARGB8888 DMA2D_OUTPUT_ARGB8888 +#define DMA2D_RGB888 DMA2D_OUTPUT_RGB888 +#define DMA2D_RGB565 DMA2D_OUTPUT_RGB565 +#define DMA2D_ARGB1555 DMA2D_OUTPUT_ARGB1555 +#define DMA2D_ARGB4444 DMA2D_OUTPUT_ARGB4444 + +#define CM_ARGB8888 DMA2D_INPUT_ARGB8888 +#define CM_RGB888 DMA2D_INPUT_RGB888 +#define CM_RGB565 DMA2D_INPUT_RGB565 +#define CM_ARGB1555 DMA2D_INPUT_ARGB1555 +#define CM_ARGB4444 DMA2D_INPUT_ARGB4444 +#define CM_L8 DMA2D_INPUT_L8 +#define CM_AL44 DMA2D_INPUT_AL44 +#define CM_AL88 DMA2D_INPUT_AL88 +#define CM_L4 DMA2D_INPUT_L4 +#define CM_A8 DMA2D_INPUT_A8 +#define CM_A4 DMA2D_INPUT_A4 +/** + * @} + */ +#endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 */ + +#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \ + || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \ + || defined(STM32H7) || defined(STM32U5) +/** @defgroup DMA2D_Aliases DMA2D API Aliases + * @{ + */ +#define HAL_DMA2D_DisableCLUT HAL_DMA2D_CLUTLoading_Abort /*!< Aliased to HAL_DMA2D_CLUTLoading_Abort + for compatibility with legacy code */ +/** + * @} + */ + +#endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 || STM32U5 */ + +/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose + * @{ + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback +/** + * @} + */ + +/** @defgroup HAL_DCACHE_Aliased_Functions HAL DCACHE Aliased Functions maintained for legacy purpose + * @{ + */ + +#if defined(STM32U5) +#define HAL_DCACHE_CleanInvalidateByAddr HAL_DCACHE_CleanInvalidByAddr +#define HAL_DCACHE_CleanInvalidateByAddr_IT HAL_DCACHE_CleanInvalidByAddr_IT +#endif /* STM32U5 */ + +/** + * @} + */ + +#if !defined(STM32F2) +/** @defgroup HASH_alias HASH API alias + * @{ + */ +#define HAL_HASHEx_IRQHandler HAL_HASH_IRQHandler /*!< Redirection for compatibility with legacy code */ +/** + * + * @} + */ +#endif /* STM32F2 */ +/** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_HASH_STATETypeDef HAL_HASH_StateTypeDef +#define HAL_HASHPhaseTypeDef HAL_HASH_PhaseTypeDef +#define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish +#define HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish +#define HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish +#define HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish + +/*HASH Algorithm Selection*/ + +#define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1 +#define HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224 +#define HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256 +#define HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5 + +#define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH +#define HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC + +#define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY +#define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY + +#if defined(STM32L4) || defined(STM32L5) || defined(STM32F2) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7) + +#define HAL_HASH_MD5_Accumulate HAL_HASH_MD5_Accmlt +#define HAL_HASH_MD5_Accumulate_End HAL_HASH_MD5_Accmlt_End +#define HAL_HASH_MD5_Accumulate_IT HAL_HASH_MD5_Accmlt_IT +#define HAL_HASH_MD5_Accumulate_End_IT HAL_HASH_MD5_Accmlt_End_IT + +#define HAL_HASH_SHA1_Accumulate HAL_HASH_SHA1_Accmlt +#define HAL_HASH_SHA1_Accumulate_End HAL_HASH_SHA1_Accmlt_End +#define HAL_HASH_SHA1_Accumulate_IT HAL_HASH_SHA1_Accmlt_IT +#define HAL_HASH_SHA1_Accumulate_End_IT HAL_HASH_SHA1_Accmlt_End_IT + +#define HAL_HASHEx_SHA224_Accumulate HAL_HASHEx_SHA224_Accmlt +#define HAL_HASHEx_SHA224_Accumulate_End HAL_HASHEx_SHA224_Accmlt_End +#define HAL_HASHEx_SHA224_Accumulate_IT HAL_HASHEx_SHA224_Accmlt_IT +#define HAL_HASHEx_SHA224_Accumulate_End_IT HAL_HASHEx_SHA224_Accmlt_End_IT + +#define HAL_HASHEx_SHA256_Accumulate HAL_HASHEx_SHA256_Accmlt +#define HAL_HASHEx_SHA256_Accumulate_End HAL_HASHEx_SHA256_Accmlt_End +#define HAL_HASHEx_SHA256_Accumulate_IT HAL_HASHEx_SHA256_Accmlt_IT +#define HAL_HASHEx_SHA256_Accumulate_End_IT HAL_HASHEx_SHA256_Accmlt_End_IT + +#endif /* STM32L4 || STM32L5 || STM32F2 || STM32F4 || STM32F7 || STM32H7 */ +/** + * @} + */ + +/** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode +#define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode +#define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode +#define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode +#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode +#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode +#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd\ + )==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : \ + HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph)) +#define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect +#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT()) +#if defined(STM32L0) +#else +#define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT()) +#endif +#define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT()) +#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd\ + )==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : \ + HAL_ADCEx_DisableVREFINTTempSensor()) +#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || \ + defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ) +#define HAL_EnableSRDomainDBGStopMode HAL_EnableDomain3DBGStopMode +#define HAL_DisableSRDomainDBGStopMode HAL_DisableDomain3DBGStopMode +#define HAL_EnableSRDomainDBGStandbyMode HAL_EnableDomain3DBGStandbyMode +#define HAL_DisableSRDomainDBGStandbyMode HAL_DisableDomain3DBGStandbyMode +#endif /* STM32H7A3xx || STM32H7B3xx || STM32H7B0xx || STM32H7A3xxQ || STM32H7B3xxQ || STM32H7B0xxQ */ + +/** + * @} + */ + +/** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose + * @{ + */ +#define FLASH_HalfPageProgram HAL_FLASHEx_HalfPageProgram +#define FLASH_EnableRunPowerDown HAL_FLASHEx_EnableRunPowerDown +#define FLASH_DisableRunPowerDown HAL_FLASHEx_DisableRunPowerDown +#define HAL_DATA_EEPROMEx_Unlock HAL_FLASHEx_DATAEEPROM_Unlock +#define HAL_DATA_EEPROMEx_Lock HAL_FLASHEx_DATAEEPROM_Lock +#define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase +#define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program + +/** + * @} + */ + +/** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter +#define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter +#define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter +#define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter + +#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd) == ENABLE)? \ + HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): \ + HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) + +#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || \ + defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || \ + defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1) +#define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT +#define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT +#define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT +#define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT +#endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || + STM32L4 || STM32L5 || STM32G4 || STM32L1 */ +#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || \ + defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)|| defined(STM32L1) +#define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA +#define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA +#define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA +#define HAL_I2C_Slave_Sequential_Receive_DMA HAL_I2C_Slave_Seq_Receive_DMA +#endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */ + +#if defined(STM32F4) +#define HAL_FMPI2C_Master_Sequential_Transmit_IT HAL_FMPI2C_Master_Seq_Transmit_IT +#define HAL_FMPI2C_Master_Sequential_Receive_IT HAL_FMPI2C_Master_Seq_Receive_IT +#define HAL_FMPI2C_Slave_Sequential_Transmit_IT HAL_FMPI2C_Slave_Seq_Transmit_IT +#define HAL_FMPI2C_Slave_Sequential_Receive_IT HAL_FMPI2C_Slave_Seq_Receive_IT +#define HAL_FMPI2C_Master_Sequential_Transmit_DMA HAL_FMPI2C_Master_Seq_Transmit_DMA +#define HAL_FMPI2C_Master_Sequential_Receive_DMA HAL_FMPI2C_Master_Seq_Receive_DMA +#define HAL_FMPI2C_Slave_Sequential_Transmit_DMA HAL_FMPI2C_Slave_Seq_Transmit_DMA +#define HAL_FMPI2C_Slave_Sequential_Receive_DMA HAL_FMPI2C_Slave_Seq_Receive_DMA +#endif /* STM32F4 */ +/** + * @} + */ + +/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose + * @{ + */ + +#if defined(STM32G0) +#define HAL_PWR_ConfigPVD HAL_PWREx_ConfigPVD +#define HAL_PWR_EnablePVD HAL_PWREx_EnablePVD +#define HAL_PWR_DisablePVD HAL_PWREx_DisablePVD +#define HAL_PWR_PVD_IRQHandler HAL_PWREx_PVD_IRQHandler +#endif +#define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD +#define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg +#define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown +#define HAL_PWR_DisableVddio2Monitor HAL_PWREx_DisableVddio2Monitor +#define HAL_PWR_EnableBkUpReg HAL_PWREx_EnableBkUpReg +#define HAL_PWR_EnableFlashPowerDown HAL_PWREx_EnableFlashPowerDown +#define HAL_PWR_EnableVddio2Monitor HAL_PWREx_EnableVddio2Monitor +#define HAL_PWR_PVD_PVM_IRQHandler HAL_PWREx_PVD_PVM_IRQHandler +#define HAL_PWR_PVDLevelConfig HAL_PWR_ConfigPVD +#define HAL_PWR_Vddio2Monitor_IRQHandler HAL_PWREx_Vddio2Monitor_IRQHandler +#define HAL_PWR_Vddio2MonitorCallback HAL_PWREx_Vddio2MonitorCallback +#define HAL_PWREx_ActivateOverDrive HAL_PWREx_EnableOverDrive +#define HAL_PWREx_DeactivateOverDrive HAL_PWREx_DisableOverDrive +#define HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC +#define HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC +#define HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM + +#define PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL +#define PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING +#define PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING +#define PWR_MODE_IT_RISING_FALLING PWR_PVD_MODE_IT_RISING_FALLING +#define PWR_MODE_EVENT_RISING PWR_PVD_MODE_EVENT_RISING +#define PWR_MODE_EVENT_FALLING PWR_PVD_MODE_EVENT_FALLING +#define PWR_MODE_EVENT_RISING_FALLING PWR_PVD_MODE_EVENT_RISING_FALLING + +#define CR_OFFSET_BB PWR_CR_OFFSET_BB +#define CSR_OFFSET_BB PWR_CSR_OFFSET_BB +#define PMODE_BIT_NUMBER VOS_BIT_NUMBER +#define CR_PMODE_BB CR_VOS_BB + +#define DBP_BitNumber DBP_BIT_NUMBER +#define PVDE_BitNumber PVDE_BIT_NUMBER +#define PMODE_BitNumber PMODE_BIT_NUMBER +#define EWUP_BitNumber EWUP_BIT_NUMBER +#define FPDS_BitNumber FPDS_BIT_NUMBER +#define ODEN_BitNumber ODEN_BIT_NUMBER +#define ODSWEN_BitNumber ODSWEN_BIT_NUMBER +#define MRLVDS_BitNumber MRLVDS_BIT_NUMBER +#define LPLVDS_BitNumber LPLVDS_BIT_NUMBER +#define BRE_BitNumber BRE_BIT_NUMBER + +#define PWR_MODE_EVT PWR_PVD_MODE_NORMAL + +#if defined (STM32U5) +#define PWR_SRAM1_PAGE1_STOP_RETENTION PWR_SRAM1_PAGE1_STOP +#define PWR_SRAM1_PAGE2_STOP_RETENTION PWR_SRAM1_PAGE2_STOP +#define PWR_SRAM1_PAGE3_STOP_RETENTION PWR_SRAM1_PAGE3_STOP +#define PWR_SRAM1_PAGE4_STOP_RETENTION PWR_SRAM1_PAGE4_STOP +#define PWR_SRAM1_PAGE5_STOP_RETENTION PWR_SRAM1_PAGE5_STOP +#define PWR_SRAM1_PAGE6_STOP_RETENTION PWR_SRAM1_PAGE6_STOP +#define PWR_SRAM1_PAGE7_STOP_RETENTION PWR_SRAM1_PAGE7_STOP +#define PWR_SRAM1_PAGE8_STOP_RETENTION PWR_SRAM1_PAGE8_STOP +#define PWR_SRAM1_PAGE9_STOP_RETENTION PWR_SRAM1_PAGE9_STOP +#define PWR_SRAM1_PAGE10_STOP_RETENTION PWR_SRAM1_PAGE10_STOP +#define PWR_SRAM1_PAGE11_STOP_RETENTION PWR_SRAM1_PAGE11_STOP +#define PWR_SRAM1_PAGE12_STOP_RETENTION PWR_SRAM1_PAGE12_STOP +#define PWR_SRAM1_FULL_STOP_RETENTION PWR_SRAM1_FULL_STOP + +#define PWR_SRAM2_PAGE1_STOP_RETENTION PWR_SRAM2_PAGE1_STOP +#define PWR_SRAM2_PAGE2_STOP_RETENTION PWR_SRAM2_PAGE2_STOP +#define PWR_SRAM2_FULL_STOP_RETENTION PWR_SRAM2_FULL_STOP + +#define PWR_SRAM3_PAGE1_STOP_RETENTION PWR_SRAM3_PAGE1_STOP +#define PWR_SRAM3_PAGE2_STOP_RETENTION PWR_SRAM3_PAGE2_STOP +#define PWR_SRAM3_PAGE3_STOP_RETENTION PWR_SRAM3_PAGE3_STOP +#define PWR_SRAM3_PAGE4_STOP_RETENTION PWR_SRAM3_PAGE4_STOP +#define PWR_SRAM3_PAGE5_STOP_RETENTION PWR_SRAM3_PAGE5_STOP +#define PWR_SRAM3_PAGE6_STOP_RETENTION PWR_SRAM3_PAGE6_STOP +#define PWR_SRAM3_PAGE7_STOP_RETENTION PWR_SRAM3_PAGE7_STOP +#define PWR_SRAM3_PAGE8_STOP_RETENTION PWR_SRAM3_PAGE8_STOP +#define PWR_SRAM3_PAGE9_STOP_RETENTION PWR_SRAM3_PAGE9_STOP +#define PWR_SRAM3_PAGE10_STOP_RETENTION PWR_SRAM3_PAGE10_STOP +#define PWR_SRAM3_PAGE11_STOP_RETENTION PWR_SRAM3_PAGE11_STOP +#define PWR_SRAM3_PAGE12_STOP_RETENTION PWR_SRAM3_PAGE12_STOP +#define PWR_SRAM3_PAGE13_STOP_RETENTION PWR_SRAM3_PAGE13_STOP +#define PWR_SRAM3_FULL_STOP_RETENTION PWR_SRAM3_FULL_STOP + +#define PWR_SRAM4_FULL_STOP_RETENTION PWR_SRAM4_FULL_STOP + +#define PWR_SRAM5_PAGE1_STOP_RETENTION PWR_SRAM5_PAGE1_STOP +#define PWR_SRAM5_PAGE2_STOP_RETENTION PWR_SRAM5_PAGE2_STOP +#define PWR_SRAM5_PAGE3_STOP_RETENTION PWR_SRAM5_PAGE3_STOP +#define PWR_SRAM5_PAGE4_STOP_RETENTION PWR_SRAM5_PAGE4_STOP +#define PWR_SRAM5_PAGE5_STOP_RETENTION PWR_SRAM5_PAGE5_STOP +#define PWR_SRAM5_PAGE6_STOP_RETENTION PWR_SRAM5_PAGE6_STOP +#define PWR_SRAM5_PAGE7_STOP_RETENTION PWR_SRAM5_PAGE7_STOP +#define PWR_SRAM5_PAGE8_STOP_RETENTION PWR_SRAM5_PAGE8_STOP +#define PWR_SRAM5_PAGE9_STOP_RETENTION PWR_SRAM5_PAGE9_STOP +#define PWR_SRAM5_PAGE10_STOP_RETENTION PWR_SRAM5_PAGE10_STOP +#define PWR_SRAM5_PAGE11_STOP_RETENTION PWR_SRAM5_PAGE11_STOP +#define PWR_SRAM5_PAGE12_STOP_RETENTION PWR_SRAM5_PAGE12_STOP +#define PWR_SRAM5_PAGE13_STOP_RETENTION PWR_SRAM5_PAGE13_STOP +#define PWR_SRAM5_FULL_STOP_RETENTION PWR_SRAM5_FULL_STOP + +#define PWR_SRAM6_PAGE1_STOP_RETENTION PWR_SRAM6_PAGE1_STOP +#define PWR_SRAM6_PAGE2_STOP_RETENTION PWR_SRAM6_PAGE2_STOP +#define PWR_SRAM6_PAGE3_STOP_RETENTION PWR_SRAM6_PAGE3_STOP +#define PWR_SRAM6_PAGE4_STOP_RETENTION PWR_SRAM6_PAGE4_STOP +#define PWR_SRAM6_PAGE5_STOP_RETENTION PWR_SRAM6_PAGE5_STOP +#define PWR_SRAM6_PAGE6_STOP_RETENTION PWR_SRAM6_PAGE6_STOP +#define PWR_SRAM6_PAGE7_STOP_RETENTION PWR_SRAM6_PAGE7_STOP +#define PWR_SRAM6_PAGE8_STOP_RETENTION PWR_SRAM6_PAGE8_STOP +#define PWR_SRAM6_FULL_STOP_RETENTION PWR_SRAM6_FULL_STOP + + +#define PWR_ICACHE_FULL_STOP_RETENTION PWR_ICACHE_FULL_STOP +#define PWR_DCACHE1_FULL_STOP_RETENTION PWR_DCACHE1_FULL_STOP +#define PWR_DCACHE2_FULL_STOP_RETENTION PWR_DCACHE2_FULL_STOP +#define PWR_DMA2DRAM_FULL_STOP_RETENTION PWR_DMA2DRAM_FULL_STOP +#define PWR_PERIPHRAM_FULL_STOP_RETENTION PWR_PERIPHRAM_FULL_STOP +#define PWR_PKA32RAM_FULL_STOP_RETENTION PWR_PKA32RAM_FULL_STOP +#define PWR_GRAPHICPRAM_FULL_STOP_RETENTION PWR_GRAPHICPRAM_FULL_STOP +#define PWR_DSIRAM_FULL_STOP_RETENTION PWR_DSIRAM_FULL_STOP +#define PWR_JPEGRAM_FULL_STOP_RETENTION PWR_JPEGRAM_FULL_STOP + + +#define PWR_SRAM2_PAGE1_STANDBY_RETENTION PWR_SRAM2_PAGE1_STANDBY +#define PWR_SRAM2_PAGE2_STANDBY_RETENTION PWR_SRAM2_PAGE2_STANDBY +#define PWR_SRAM2_FULL_STANDBY_RETENTION PWR_SRAM2_FULL_STANDBY + +#define PWR_SRAM1_FULL_RUN_RETENTION PWR_SRAM1_FULL_RUN +#define PWR_SRAM2_FULL_RUN_RETENTION PWR_SRAM2_FULL_RUN +#define PWR_SRAM3_FULL_RUN_RETENTION PWR_SRAM3_FULL_RUN +#define PWR_SRAM4_FULL_RUN_RETENTION PWR_SRAM4_FULL_RUN +#define PWR_SRAM5_FULL_RUN_RETENTION PWR_SRAM5_FULL_RUN +#define PWR_SRAM6_FULL_RUN_RETENTION PWR_SRAM6_FULL_RUN + +#define PWR_ALL_RAM_RUN_RETENTION_MASK PWR_ALL_RAM_RUN_MASK +#endif + +/** + * @} + */ + +/** @defgroup HAL_RTC_Aliased_Functions HAL RTC Aliased Functions maintained for legacy purpose + * @{ + */ +#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) || defined(STM32N6) +#define HAL_RTCEx_SetBoothardwareKey HAL_RTCEx_LockBootHardwareKey +#define HAL_RTCEx_BKUPBlock_Enable HAL_RTCEx_BKUPBlock +#define HAL_RTCEx_BKUPBlock_Disable HAL_RTCEx_BKUPUnblock +#define HAL_RTCEx_Erase_SecretDev_Conf HAL_RTCEx_ConfigEraseDeviceSecrets +#endif /* STM32H5 || STM32WBA || STM32H7RS || STM32N6 */ + +/** + * @} + */ + +/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT +#define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback +#define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback +/** + * @} + */ + +/** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo +/** + * @} + */ + +/** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_TIM_DMADelayPulseCplt TIM_DMADelayPulseCplt +#define HAL_TIM_DMAError TIM_DMAError +#define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt +#define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt +#if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || \ + defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) +#define HAL_TIM_SlaveConfigSynchronization HAL_TIM_SlaveConfigSynchro +#define HAL_TIM_SlaveConfigSynchronization_IT HAL_TIM_SlaveConfigSynchro_IT +#define HAL_TIMEx_CommutationCallback HAL_TIMEx_CommutCallback +#define HAL_TIMEx_ConfigCommutationEvent HAL_TIMEx_ConfigCommutEvent +#define HAL_TIMEx_ConfigCommutationEvent_IT HAL_TIMEx_ConfigCommutEvent_IT +#define HAL_TIMEx_ConfigCommutationEvent_DMA HAL_TIMEx_ConfigCommutEvent_DMA +#endif /* STM32H7 || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 */ +/** + * @} + */ + +/** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback +/** + * @} + */ + +/** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback +#define HAL_LTDC_Relaod HAL_LTDC_Reload +#define HAL_LTDC_StructInitFromVideoConfig HAL_LTDCEx_StructInitFromVideoConfig +#define HAL_LTDC_StructInitFromAdaptedCommandConfig HAL_LTDCEx_StructInitFromAdaptedCommandConfig +/** + * @} + */ + + +/** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose + * @{ + */ + +/** + * @} + */ + +/* Exported macros ------------------------------------------------------------*/ + +/** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose + * @{ + */ +#define AES_IT_CC CRYP_IT_CC +#define AES_IT_ERR CRYP_IT_ERR +#define AES_FLAG_CCF CRYP_FLAG_CCF +/** + * @} + */ + +/** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_GET_BOOT_MODE __HAL_SYSCFG_GET_BOOT_MODE +#define __HAL_REMAPMEMORY_FLASH __HAL_SYSCFG_REMAPMEMORY_FLASH +#define __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH +#define __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM +#define __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC +#define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM +#define __HAL_REMAPMEMORY_FSMC __HAL_SYSCFG_REMAPMEMORY_FSMC +#define __HAL_REMAPMEMORY_QUADSPI __HAL_SYSCFG_REMAPMEMORY_QUADSPI +#define __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK +#define __HAL_GET_FLAG __HAL_SYSCFG_GET_FLAG +#define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG +#define __HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE +#define __HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE +#define __HAL_SYSCFG_SRAM2_WRP_ENABLE __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE + +#define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY +#define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48 +#define IS_SYSCFG_FASTMODEPLUS_CONFIG IS_I2C_FASTMODEPLUS +#define UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER +#define CMP_PD_BitNumber CMP_PD_BIT_NUMBER + +#if defined(STM32H7RS) || defined(STM32N6) +#define FMC_SWAPBMAP_DISABLE FMC_SWAPBANK_MODE0 +#define FMC_SWAPBMAP_SDRAM_SRAM FMC_SWAPBANK_MODE1 +#define HAL_SetFMCMemorySwappingConfig HAL_FMC_SetBankSwapConfig +#define HAL_GetFMCMemorySwappingConfig HAL_FMC_GetBankSwapConfig +#endif /* STM32H7RS || STM32N6 */ + +/** + * @} + */ + + +/** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose + * @{ + */ +#define __ADC_ENABLE __HAL_ADC_ENABLE +#define __ADC_DISABLE __HAL_ADC_DISABLE +#define __HAL_ADC_ENABLING_CONDITIONS ADC_ENABLING_CONDITIONS +#define __HAL_ADC_DISABLING_CONDITIONS ADC_DISABLING_CONDITIONS +#define __HAL_ADC_IS_ENABLED ADC_IS_ENABLE +#define __ADC_IS_ENABLED ADC_IS_ENABLE +#define __HAL_ADC_IS_SOFTWARE_START_REGULAR ADC_IS_SOFTWARE_START_REGULAR +#define __HAL_ADC_IS_SOFTWARE_START_INJECTED ADC_IS_SOFTWARE_START_INJECTED +#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED +#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR ADC_IS_CONVERSION_ONGOING_REGULAR +#define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED ADC_IS_CONVERSION_ONGOING_INJECTED +#define __HAL_ADC_IS_CONVERSION_ONGOING ADC_IS_CONVERSION_ONGOING +#define __HAL_ADC_CLEAR_ERRORCODE ADC_CLEAR_ERRORCODE + +#define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION +#define __HAL_ADC_JSQR_RK ADC_JSQR_RK +#define __HAL_ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_SHIFT +#define __HAL_ADC_CFGR_AWD23CR ADC_CFGR_AWD23CR +#define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION ADC_CFGR_INJECT_AUTO_CONVERSION +#define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE ADC_CFGR_INJECT_CONTEXT_QUEUE +#define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS ADC_CFGR_INJECT_DISCCONTINUOUS +#define __HAL_ADC_CFGR_REG_DISCCONTINUOUS ADC_CFGR_REG_DISCCONTINUOUS +#define __HAL_ADC_CFGR_DISCONTINUOUS_NUM ADC_CFGR_DISCONTINUOUS_NUM +#define __HAL_ADC_CFGR_AUTOWAIT ADC_CFGR_AUTOWAIT +#define __HAL_ADC_CFGR_CONTINUOUS ADC_CFGR_CONTINUOUS +#define __HAL_ADC_CFGR_OVERRUN ADC_CFGR_OVERRUN +#define __HAL_ADC_CFGR_DMACONTREQ ADC_CFGR_DMACONTREQ +#define __HAL_ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_SET +#define __HAL_ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_SET +#define __HAL_ADC_OFR_CHANNEL ADC_OFR_CHANNEL +#define __HAL_ADC_DIFSEL_CHANNEL ADC_DIFSEL_CHANNEL +#define __HAL_ADC_CALFACT_DIFF_SET ADC_CALFACT_DIFF_SET +#define __HAL_ADC_CALFACT_DIFF_GET ADC_CALFACT_DIFF_GET +#define __HAL_ADC_TRX_HIGHTHRESHOLD ADC_TRX_HIGHTHRESHOLD + +#define __HAL_ADC_OFFSET_SHIFT_RESOLUTION ADC_OFFSET_SHIFT_RESOLUTION +#define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION ADC_AWD1THRESHOLD_SHIFT_RESOLUTION +#define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION ADC_AWD23THRESHOLD_SHIFT_RESOLUTION +#define __HAL_ADC_COMMON_REGISTER ADC_COMMON_REGISTER +#define __HAL_ADC_COMMON_CCR_MULTI ADC_COMMON_CCR_MULTI +#define __HAL_ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE +#define __ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE +#define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER ADC_NONMULTIMODE_OR_MULTIMODEMASTER +#define __HAL_ADC_COMMON_ADC_OTHER ADC_COMMON_ADC_OTHER +#define __HAL_ADC_MULTI_SLAVE ADC_MULTI_SLAVE + +#define __HAL_ADC_SQR1_L ADC_SQR1_L_SHIFT +#define __HAL_ADC_JSQR_JL ADC_JSQR_JL_SHIFT +#define __HAL_ADC_JSQR_RK_JL ADC_JSQR_RK_JL +#define __HAL_ADC_CR1_DISCONTINUOUS_NUM ADC_CR1_DISCONTINUOUS_NUM +#define __HAL_ADC_CR1_SCAN ADC_CR1_SCAN_SET +#define __HAL_ADC_CONVCYCLES_MAX_RANGE ADC_CONVCYCLES_MAX_RANGE +#define __HAL_ADC_CLOCK_PRESCALER_RANGE ADC_CLOCK_PRESCALER_RANGE +#define __HAL_ADC_GET_CLOCK_PRESCALER ADC_GET_CLOCK_PRESCALER + +#define __HAL_ADC_SQR1 ADC_SQR1 +#define __HAL_ADC_SMPR1 ADC_SMPR1 +#define __HAL_ADC_SMPR2 ADC_SMPR2 +#define __HAL_ADC_SQR3_RK ADC_SQR3_RK +#define __HAL_ADC_SQR2_RK ADC_SQR2_RK +#define __HAL_ADC_SQR1_RK ADC_SQR1_RK +#define __HAL_ADC_CR2_CONTINUOUS ADC_CR2_CONTINUOUS +#define __HAL_ADC_CR1_DISCONTINUOUS ADC_CR1_DISCONTINUOUS +#define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV +#define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection +#define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq +#define __HAL_ADC_JSQR ADC_JSQR + +#define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL +#define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS ADC_CFGR1_REG_DISCCONTINUOUS +#define __HAL_ADC_CFGR1_AUTOOFF ADC_CFGR1_AUTOOFF +#define __HAL_ADC_CFGR1_AUTOWAIT ADC_CFGR1_AUTOWAIT +#define __HAL_ADC_CFGR1_CONTINUOUS ADC_CFGR1_CONTINUOUS +#define __HAL_ADC_CFGR1_OVERRUN ADC_CFGR1_OVERRUN +#define __HAL_ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR +#define __HAL_ADC_CFGR1_DMACONTREQ ADC_CFGR1_DMACONTREQ + +/** + * @} + */ + +/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_DHR12R1_ALIGNEMENT DAC_DHR12R1_ALIGNMENT +#define __HAL_DHR12R2_ALIGNEMENT DAC_DHR12R2_ALIGNMENT +#define __HAL_DHR12RD_ALIGNEMENT DAC_DHR12RD_ALIGNMENT +#define IS_DAC_GENERATE_WAVE IS_DAC_WAVE + +/** + * @} + */ + +/** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1 +#define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1 +#define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2 +#define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2 +#define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3 +#define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3 +#define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4 +#define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4 +#define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5 +#define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5 +#define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6 +#define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6 +#define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7 +#define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7 +#define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8 +#define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8 + +#define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9 +#define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9 +#define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10 +#define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10 +#define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11 +#define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11 +#define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12 +#define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12 +#define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13 +#define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13 +#define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14 +#define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14 +#define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2 +#define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2 + + +#define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15 +#define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15 +#define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16 +#define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16 +#define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17 +#define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17 +#define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC +#define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC +#if defined(STM32H7) +#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG1 +#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UnFreeze_WWDG1 +#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG1 +#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UnFreeze_IWDG1 +#else +#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG +#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG +#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG +#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG +#endif /* STM32H7 */ +#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT +#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT +#define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT +#define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT +#define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT +#define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT +#define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1 +#define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1 +#define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1 +#define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1 +#define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2 +#define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2 + +/** + * @} + */ + +/** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose + * @{ + */ +#if defined(STM32F3) +#define COMP_START __HAL_COMP_ENABLE +#define COMP_STOP __HAL_COMP_DISABLE +#define COMP_LOCK __HAL_COMP_LOCK + +#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || \ + defined(STM32F334x8) || defined(STM32F328xx) +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP6_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) +#endif +#if defined(STM32F302xE) || defined(STM32F302xC) +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP6_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) +#endif +#if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx) +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP7_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP7_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP7_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP7_EXTI_CLEAR_FLAG()) +#endif +#if defined(STM32F373xC) ||defined(STM32F378xx) +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP2_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) +#endif +#else +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP2_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) +#endif + +#define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE + +#if defined(STM32L0) || defined(STM32L4) +/* Note: On these STM32 families, the only argument of this macro */ +/* is COMP_FLAG_LOCK. */ +/* This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle */ +/* argument. */ +#define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_COMP_IS_LOCKED(__HANDLE__)) +#endif +/** + * @} + */ + +#if defined(STM32L0) || defined(STM32L4) +/** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is + done into HAL_COMP_Init() */ +#define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is + done into HAL_COMP_Init() */ +/** + * @} + */ +#endif + +/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose + * @{ + */ + +#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \ + ((WAVE) == DAC_WAVE_NOISE)|| \ + ((WAVE) == DAC_WAVE_TRIANGLE)) + +/** + * @} + */ + +/** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose + * @{ + */ + +#define IS_WRPAREA IS_OB_WRPAREA +#define IS_TYPEPROGRAM IS_FLASH_TYPEPROGRAM +#define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM +#define IS_TYPEERASE IS_FLASH_TYPEERASE +#define IS_NBSECTORS IS_FLASH_NBSECTORS +#define IS_OB_WDG_SOURCE IS_OB_IWDG_SOURCE + +/** + * @} + */ + +/** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_I2C_RESET_CR2 I2C_RESET_CR2 +#define __HAL_I2C_GENERATE_START I2C_GENERATE_START +#if defined(STM32F1) +#define __HAL_I2C_FREQ_RANGE I2C_FREQRANGE +#else +#define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE +#endif /* STM32F1 */ +#define __HAL_I2C_RISE_TIME I2C_RISE_TIME +#define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD +#define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST +#define __HAL_I2C_SPEED I2C_SPEED +#define __HAL_I2C_7BIT_ADD_WRITE I2C_7BIT_ADD_WRITE +#define __HAL_I2C_7BIT_ADD_READ I2C_7BIT_ADD_READ +#define __HAL_I2C_10BIT_ADDRESS I2C_10BIT_ADDRESS +#define __HAL_I2C_10BIT_HEADER_WRITE I2C_10BIT_HEADER_WRITE +#define __HAL_I2C_10BIT_HEADER_READ I2C_10BIT_HEADER_READ +#define __HAL_I2C_MEM_ADD_MSB I2C_MEM_ADD_MSB +#define __HAL_I2C_MEM_ADD_LSB I2C_MEM_ADD_LSB +#define __HAL_I2C_FREQRANGE I2C_FREQRANGE +/** + * @} + */ + +/** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose + * @{ + */ + +#define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE +#define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT + +#if defined(STM32H7) +#define __HAL_I2S_CLEAR_FREFLAG __HAL_I2S_CLEAR_TIFREFLAG +#endif + +/** + * @} + */ + +/** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __IRDA_DISABLE __HAL_IRDA_DISABLE +#define __IRDA_ENABLE __HAL_IRDA_ENABLE + +#define __HAL_IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE +#define __HAL_IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION +#define __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE +#define __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION + +#define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE + + +/** + * @} + */ + + +/** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_IWDG_ENABLE_WRITE_ACCESS IWDG_ENABLE_WRITE_ACCESS +#define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS +/** + * @} + */ + + +/** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_LPTIM_ENABLE_INTERRUPT __HAL_LPTIM_ENABLE_IT +#define __HAL_LPTIM_DISABLE_INTERRUPT __HAL_LPTIM_DISABLE_IT +#define __HAL_LPTIM_GET_ITSTATUS __HAL_LPTIM_GET_IT_SOURCE + +/** + * @} + */ + + +/** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose + * @{ + */ +#define __OPAMP_CSR_OPAXPD OPAMP_CSR_OPAXPD +#define __OPAMP_CSR_S3SELX OPAMP_CSR_S3SELX +#define __OPAMP_CSR_S4SELX OPAMP_CSR_S4SELX +#define __OPAMP_CSR_S5SELX OPAMP_CSR_S5SELX +#define __OPAMP_CSR_S6SELX OPAMP_CSR_S6SELX +#define __OPAMP_CSR_OPAXCAL_L OPAMP_CSR_OPAXCAL_L +#define __OPAMP_CSR_OPAXCAL_H OPAMP_CSR_OPAXCAL_H +#define __OPAMP_CSR_OPAXLPM OPAMP_CSR_OPAXLPM +#define __OPAMP_CSR_ALL_SWITCHES OPAMP_CSR_ALL_SWITCHES +#define __OPAMP_CSR_ANAWSELX OPAMP_CSR_ANAWSELX +#define __OPAMP_CSR_OPAXCALOUT OPAMP_CSR_OPAXCALOUT +#define __OPAMP_OFFSET_TRIM_BITSPOSITION OPAMP_OFFSET_TRIM_BITSPOSITION +#define __OPAMP_OFFSET_TRIM_SET OPAMP_OFFSET_TRIM_SET + +/** + * @} + */ + + +/** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_PVD_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT +#define __HAL_PVD_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT +#define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE +#define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE +#define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE +#define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE +#define __HAL_PVM_EVENT_DISABLE __HAL_PWR_PVM_EVENT_DISABLE +#define __HAL_PVM_EVENT_ENABLE __HAL_PWR_PVM_EVENT_ENABLE +#define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE +#define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE +#define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE +#define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE +#define __HAL_PWR_INTERNALWAKEUP_DISABLE HAL_PWREx_DisableInternalWakeUpLine +#define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine +#define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig +#define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig +#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); \ + __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \ + } while(0) +#define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT +#define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT +#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE +#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE +#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE +#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE +#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE +#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE +#define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2(); \ + HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); \ + } while(0) +#define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2(); \ + HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); \ + } while(0) +#define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention +#define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention +#define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2 +#define __HAL_PWR_VDDIO2_ENABLE HAL_PWREx_EnableVddIO2 +#define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE +#define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE +#define __HAL_PWR_VDDUSB_DISABLE HAL_PWREx_DisableVddUSB +#define __HAL_PWR_VDDUSB_ENABLE HAL_PWREx_EnableVddUSB + +#if defined (STM32F4) +#define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_ENABLE_IT() +#define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_DISABLE_IT() +#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG() +#define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_CLEAR_FLAG() +#define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GENERATE_SWIT() +#else +#define __HAL_PVD_EXTI_CLEAR_FLAG __HAL_PWR_PVD_EXTI_CLEAR_FLAG +#define __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT +#define __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT +#define __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT +#define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG +#endif /* STM32F4 */ +/** + * @} + */ + + +/** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose + * @{ + */ + +#define RCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI +#define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI + +#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback +#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? \ + HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT()) + +#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE +#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE +#define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE +#define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE +#define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET +#define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET +#define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE +#define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE +#define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET +#define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET +#define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE +#define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE +#define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE +#define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE +#define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET +#define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET +#define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE +#define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE +#define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET +#define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET +#define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE +#define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE +#define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE +#define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE +#define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET +#define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET +#define __CRYP_CLK_SLEEP_ENABLE __HAL_RCC_CRYP_CLK_SLEEP_ENABLE +#define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE +#define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE +#define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE +#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET +#define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET +#define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE +#define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE +#define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET +#define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET +#define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET +#define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET +#define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET +#define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET +#define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET +#define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET +#define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET +#define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET +#define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET +#define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET +#define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET +#define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET +#if defined(STM32C0) +#define __HAL_RCC_APB1_FORCE_RESET __HAL_RCC_APB1_GRP1_FORCE_RESET +#define __HAL_RCC_APB1_RELEASE_RESET __HAL_RCC_APB1_GRP1_RELEASE_RESET +#define __HAL_RCC_APB2_FORCE_RESET __HAL_RCC_APB1_GRP2_FORCE_RESET +#define __HAL_RCC_APB2_RELEASE_RESET __HAL_RCC_APB1_GRP2_RELEASE_RESET +#endif /* STM32C0 */ +#define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE +#define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE +#define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET +#define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET +#define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE +#define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE +#define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE +#define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE +#define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET +#define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET +#define __CAN_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE +#define __CAN_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE +#define __CAN_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET +#define __CAN_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET +#define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE +#define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE +#define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET +#define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET +#define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE +#define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE +#define __COMP_CLK_DISABLE __HAL_RCC_COMP_CLK_DISABLE +#define __COMP_CLK_ENABLE __HAL_RCC_COMP_CLK_ENABLE +#define __COMP_FORCE_RESET __HAL_RCC_COMP_FORCE_RESET +#define __COMP_RELEASE_RESET __HAL_RCC_COMP_RELEASE_RESET +#define __COMP_CLK_SLEEP_ENABLE __HAL_RCC_COMP_CLK_SLEEP_ENABLE +#define __COMP_CLK_SLEEP_DISABLE __HAL_RCC_COMP_CLK_SLEEP_DISABLE +#define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET +#define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET +#define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE +#define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE +#define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE +#define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE +#define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET +#define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET +#define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE +#define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE +#define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET +#define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET +#define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE +#define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE +#define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE +#define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE +#define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET +#define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET +#define __DBGMCU_CLK_ENABLE __HAL_RCC_DBGMCU_CLK_ENABLE +#define __DBGMCU_CLK_DISABLE __HAL_RCC_DBGMCU_CLK_DISABLE +#define __DBGMCU_FORCE_RESET __HAL_RCC_DBGMCU_FORCE_RESET +#define __DBGMCU_RELEASE_RESET __HAL_RCC_DBGMCU_RELEASE_RESET +#define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE +#define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE +#define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE +#define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE +#define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET +#define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET +#define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE +#define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE +#define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE +#define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE +#define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET +#define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET +#define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE +#define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE +#define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE +#define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE +#define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET +#define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET +#define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE +#define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE +#define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET +#define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET +#define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE +#define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE +#define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE +#define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE +#define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE +#define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE +#define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE +#define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE +#define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE +#define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE +#define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET +#define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET +#define __FLITF_CLK_DISABLE __HAL_RCC_FLITF_CLK_DISABLE +#define __FLITF_CLK_ENABLE __HAL_RCC_FLITF_CLK_ENABLE +#define __FLITF_FORCE_RESET __HAL_RCC_FLITF_FORCE_RESET +#define __FLITF_RELEASE_RESET __HAL_RCC_FLITF_RELEASE_RESET +#define __FLITF_CLK_SLEEP_ENABLE __HAL_RCC_FLITF_CLK_SLEEP_ENABLE +#define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE +#define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE +#define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE +#define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE +#define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE +#define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET +#define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET +#define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE +#define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE +#define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE +#define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE +#define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE +#define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE +#define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET +#define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET +#define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE +#define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE +#define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE +#define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE +#define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET +#define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET +#define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE +#define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE +#define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE +#define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE +#define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET +#define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET +#define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE +#define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE +#define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE +#define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE +#define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET +#define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET +#define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE +#define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE +#define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE +#define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE +#define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET +#define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET +#define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE +#define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE +#define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE +#define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE +#define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET +#define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET +#define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE +#define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE +#define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE +#define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE +#define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET +#define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET +#define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE +#define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE +#define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE +#define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE +#define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET +#define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET +#define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE +#define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE +#define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE +#define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE +#define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET +#define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET +#define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE +#define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE +#define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE +#define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE +#define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET +#define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET +#define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE +#define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE +#define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE +#define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE +#define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET +#define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET +#define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE +#define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE +#define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE +#define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE +#define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET +#define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET +#define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE +#define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE +#define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE +#define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE +#define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET +#define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET +#define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE +#define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE +#define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE +#define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE +#define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET +#define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET +#define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE +#define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE +#define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE +#define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE +#define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET +#define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET +#define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE +#define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE +#define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE +#define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE +#define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET +#define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET +#define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE +#define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE +#define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE +#define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE +#define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET +#define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET +#define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE +#define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE +#define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE +#define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE +#define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET +#define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET +#define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE +#define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE +#define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE +#define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE +#define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET +#define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET + +#if defined(STM32WB) +#define __HAL_RCC_QSPI_CLK_DISABLE __HAL_RCC_QUADSPI_CLK_DISABLE +#define __HAL_RCC_QSPI_CLK_ENABLE __HAL_RCC_QUADSPI_CLK_ENABLE +#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QUADSPI_CLK_SLEEP_DISABLE +#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QUADSPI_CLK_SLEEP_ENABLE +#define __HAL_RCC_QSPI_FORCE_RESET __HAL_RCC_QUADSPI_FORCE_RESET +#define __HAL_RCC_QSPI_RELEASE_RESET __HAL_RCC_QUADSPI_RELEASE_RESET +#define __HAL_RCC_QSPI_IS_CLK_ENABLED __HAL_RCC_QUADSPI_IS_CLK_ENABLED +#define __HAL_RCC_QSPI_IS_CLK_DISABLED __HAL_RCC_QUADSPI_IS_CLK_DISABLED +#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_ENABLED +#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_DISABLED +#define QSPI_IRQHandler QUADSPI_IRQHandler +#endif /* __HAL_RCC_QUADSPI_CLK_ENABLE */ + +#define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE +#define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE +#define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE +#define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE +#define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET +#define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET +#define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE +#define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE +#define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE +#define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE +#define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET +#define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET +#define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE +#define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE +#define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE +#define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE +#define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET +#define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET +#define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE +#define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE +#define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE +#define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE +#define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE +#define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE +#define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET +#define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET +#define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE +#define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE +#define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE +#define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE +#define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET +#define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET +#define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE +#define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE +#define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE +#define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE +#define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET +#define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET +#define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE +#define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE +#define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE +#define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE +#define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET +#define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET +#define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE +#define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE +#define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE +#define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE +#define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE +#define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE +#define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE +#define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE +#define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE +#define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE +#define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET +#define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET +#define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE +#define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE +#define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE +#define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE +#define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET +#define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET +#define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE +#define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE +#define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE +#define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE +#define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET +#define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET +#define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE +#define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE +#define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET +#define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET +#define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE +#define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE +#define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET +#define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET +#define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE +#define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE +#define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET +#define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET +#define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE +#define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE +#define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET +#define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET +#define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE +#define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE +#define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET +#define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET +#define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE +#define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE +#define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE +#define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE +#define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET +#define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET +#define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE +#define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE +#define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE +#define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE +#define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET +#define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET +#define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE +#define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE +#define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE +#define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE +#define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET +#define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET +#define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE +#define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE +#define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE +#define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE +#define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET +#define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET +#define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE +#define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE +#define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE +#define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE +#define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET +#define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET +#define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE +#define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE +#define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE +#define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE +#define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET +#define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET +#define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE +#define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE +#define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE +#define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE +#define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET +#define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET +#define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE +#define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE +#define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE +#define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE +#define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET +#define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET +#define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE +#define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE +#define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE +#define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE +#define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET +#define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET +#define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE +#define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE +#define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE +#define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE +#define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET +#define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET +#define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE +#define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE +#define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET +#define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET +#define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE +#define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE +#define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE +#define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE +#define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET +#define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET +#define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE +#define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE +#define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE +#define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE +#define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET +#define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET +#define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE +#define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE +#define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE +#define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE +#define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET +#define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET +#define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE +#define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE +#define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE +#define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE +#define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET +#define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET +#define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE +#define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE +#define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE +#define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE +#define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET +#define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET +#define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE +#define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE +#define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE +#define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE +#define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET +#define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET +#define __USART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE +#define __USART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE +#define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE +#define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE +#define __USART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET +#define __USART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET +#define __USART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE +#define __USART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE +#define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE +#define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE +#define __USART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET +#define __USART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET +#define __USART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE +#define __USART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE +#define __USART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET +#define __USART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET +#define __USART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE +#define __USART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE +#define __USART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET +#define __USART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET +#define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE +#define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE +#define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET +#define __USB_CLK_SLEEP_ENABLE __HAL_RCC_USB_CLK_SLEEP_ENABLE +#define __USB_CLK_SLEEP_DISABLE __HAL_RCC_USB_CLK_SLEEP_DISABLE +#define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE +#define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE +#define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET + +#if defined(STM32H7) +#define __HAL_RCC_WWDG_CLK_DISABLE __HAL_RCC_WWDG1_CLK_DISABLE +#define __HAL_RCC_WWDG_CLK_ENABLE __HAL_RCC_WWDG1_CLK_ENABLE +#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG1_CLK_SLEEP_DISABLE +#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG1_CLK_SLEEP_ENABLE + +#define __HAL_RCC_WWDG_FORCE_RESET ((void)0U) /* Not available on the STM32H7*/ +#define __HAL_RCC_WWDG_RELEASE_RESET ((void)0U) /* Not available on the STM32H7*/ + + +#define __HAL_RCC_WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG1_IS_CLK_ENABLED +#define __HAL_RCC_WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG1_IS_CLK_DISABLED +#define RCC_SPI4CLKSOURCE_D2PCLK1 RCC_SPI4CLKSOURCE_D2PCLK2 +#define RCC_SPI5CLKSOURCE_D2PCLK1 RCC_SPI5CLKSOURCE_D2PCLK2 +#define RCC_SPI45CLKSOURCE_D2PCLK1 RCC_SPI45CLKSOURCE_D2PCLK2 +#define RCC_SPI45CLKSOURCE_CDPCLK1 RCC_SPI45CLKSOURCE_CDPCLK2 +#define RCC_SPI45CLKSOURCE_PCLK1 RCC_SPI45CLKSOURCE_PCLK2 +#endif + +#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE +#define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE +#define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE +#define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE +#define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET +#define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET + +#define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE +#define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE +#define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET +#define __TIM21_RELEASE_RESET __HAL_RCC_TIM21_RELEASE_RESET +#define __TIM21_CLK_SLEEP_ENABLE __HAL_RCC_TIM21_CLK_SLEEP_ENABLE +#define __TIM21_CLK_SLEEP_DISABLE __HAL_RCC_TIM21_CLK_SLEEP_DISABLE +#define __TIM22_CLK_ENABLE __HAL_RCC_TIM22_CLK_ENABLE +#define __TIM22_CLK_DISABLE __HAL_RCC_TIM22_CLK_DISABLE +#define __TIM22_FORCE_RESET __HAL_RCC_TIM22_FORCE_RESET +#define __TIM22_RELEASE_RESET __HAL_RCC_TIM22_RELEASE_RESET +#define __TIM22_CLK_SLEEP_ENABLE __HAL_RCC_TIM22_CLK_SLEEP_ENABLE +#define __TIM22_CLK_SLEEP_DISABLE __HAL_RCC_TIM22_CLK_SLEEP_DISABLE +#define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE +#define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE +#define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE +#define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE +#define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET +#define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET +#define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE +#define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE + +#define __USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET +#define __USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET +#define __USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE +#define __USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE +#define __USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE +#define __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE +#define __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE +#define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE +#define __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE +#define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE +#define __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE +#define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE +#define __TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE +#define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE +#define __ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE +#define __ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE +#define __ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE +#define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE +#define __HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE +#define __HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET +#define __HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET +#define __HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE +#define __HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE +#define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE +#define __SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE +#define __SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE +#define __SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET +#define __SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET +#define __SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE +#define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE +#define __SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE +#define __SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE +#define __SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET +#define __SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET +#define __SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE +#define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE +#define __LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE +#define __LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE +#define __LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET +#define __LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET +#define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE +#define __ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE +#define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE +#define __ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE +#define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE +#define __ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE +#define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE +#define __TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE +#define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE +#define __TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE +#define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE +#define __TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE +#define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE +#define __BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE +#define __BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE +#define __BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE +#define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE +#define __CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE +#define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE +#define __USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE +#define __USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE +#define __USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET +#define __USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET +#define __USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE +#define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE +#define __SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE +#define __SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE +#define __SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET +#define __SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET +#define __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE +#define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE +#define __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE +#define __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE +#define __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET +#define __GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET +#define __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE +#define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE +#define __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE +#define __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE +#define __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET +#define __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET +#define __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE +#define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE +#define __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE +#define __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE +#define __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET +#define __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE +#define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE +#define __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE +#define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE +#define __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE +#define __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE +#define __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET +#define __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET +#define __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE +#define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE +#define __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE +#define __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE +#define __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET +#define __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET +#define __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE +#define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE +#define __UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE +#define __UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE +#define __UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET +#define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET +#define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE +#define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE +#define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE +#define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE +#define __OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET +#define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET +#define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE +#define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE +#define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE +#define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE +#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED +#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED +#define __HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET +#define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET +#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE +#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE +#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED +#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED +#define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE +#define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE +#define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE +#define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE +#define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE +#define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE +#define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE +#define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE +#define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE +#define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET +#define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET +#define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE +#define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE +#define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET +#define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET +#define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE +#define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE +#define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE +#define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE +#define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET +#define __DMA2D_RELEASE_RESET __HAL_RCC_DMA2D_RELEASE_RESET +#define __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE +#define __DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE + +/* alias define maintained for legacy */ +#define __HAL_RCC_OTGFS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET +#define __HAL_RCC_OTGFS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET + +#define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE +#define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE +#define __ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLE +#define __ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE +#define __DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE +#define __DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE +#define __TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE +#define __TIM18_CLK_DISABLE __HAL_RCC_TIM18_CLK_DISABLE +#define __TIM19_CLK_ENABLE __HAL_RCC_TIM19_CLK_ENABLE +#define __TIM19_CLK_DISABLE __HAL_RCC_TIM19_CLK_DISABLE +#define __TIM20_CLK_ENABLE __HAL_RCC_TIM20_CLK_ENABLE +#define __TIM20_CLK_DISABLE __HAL_RCC_TIM20_CLK_DISABLE +#define __HRTIM1_CLK_ENABLE __HAL_RCC_HRTIM1_CLK_ENABLE +#define __HRTIM1_CLK_DISABLE __HAL_RCC_HRTIM1_CLK_DISABLE +#define __SDADC1_CLK_ENABLE __HAL_RCC_SDADC1_CLK_ENABLE +#define __SDADC2_CLK_ENABLE __HAL_RCC_SDADC2_CLK_ENABLE +#define __SDADC3_CLK_ENABLE __HAL_RCC_SDADC3_CLK_ENABLE +#define __SDADC1_CLK_DISABLE __HAL_RCC_SDADC1_CLK_DISABLE +#define __SDADC2_CLK_DISABLE __HAL_RCC_SDADC2_CLK_DISABLE +#define __SDADC3_CLK_DISABLE __HAL_RCC_SDADC3_CLK_DISABLE + +#define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET +#define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET +#define __ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET +#define __ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESET +#define __DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESET +#define __DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESET +#define __TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESET +#define __TIM18_RELEASE_RESET __HAL_RCC_TIM18_RELEASE_RESET +#define __TIM19_FORCE_RESET __HAL_RCC_TIM19_FORCE_RESET +#define __TIM19_RELEASE_RESET __HAL_RCC_TIM19_RELEASE_RESET +#define __TIM20_FORCE_RESET __HAL_RCC_TIM20_FORCE_RESET +#define __TIM20_RELEASE_RESET __HAL_RCC_TIM20_RELEASE_RESET +#define __HRTIM1_FORCE_RESET __HAL_RCC_HRTIM1_FORCE_RESET +#define __HRTIM1_RELEASE_RESET __HAL_RCC_HRTIM1_RELEASE_RESET +#define __SDADC1_FORCE_RESET __HAL_RCC_SDADC1_FORCE_RESET +#define __SDADC2_FORCE_RESET __HAL_RCC_SDADC2_FORCE_RESET +#define __SDADC3_FORCE_RESET __HAL_RCC_SDADC3_FORCE_RESET +#define __SDADC1_RELEASE_RESET __HAL_RCC_SDADC1_RELEASE_RESET +#define __SDADC2_RELEASE_RESET __HAL_RCC_SDADC2_RELEASE_RESET +#define __SDADC3_RELEASE_RESET __HAL_RCC_SDADC3_RELEASE_RESET + +#define __ADC1_IS_CLK_ENABLED __HAL_RCC_ADC1_IS_CLK_ENABLED +#define __ADC1_IS_CLK_DISABLED __HAL_RCC_ADC1_IS_CLK_DISABLED +#define __ADC12_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED +#define __ADC12_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED +#define __ADC34_IS_CLK_ENABLED __HAL_RCC_ADC34_IS_CLK_ENABLED +#define __ADC34_IS_CLK_DISABLED __HAL_RCC_ADC34_IS_CLK_DISABLED +#define __CEC_IS_CLK_ENABLED __HAL_RCC_CEC_IS_CLK_ENABLED +#define __CEC_IS_CLK_DISABLED __HAL_RCC_CEC_IS_CLK_DISABLED +#define __CRC_IS_CLK_ENABLED __HAL_RCC_CRC_IS_CLK_ENABLED +#define __CRC_IS_CLK_DISABLED __HAL_RCC_CRC_IS_CLK_DISABLED +#define __DAC1_IS_CLK_ENABLED __HAL_RCC_DAC1_IS_CLK_ENABLED +#define __DAC1_IS_CLK_DISABLED __HAL_RCC_DAC1_IS_CLK_DISABLED +#define __DAC2_IS_CLK_ENABLED __HAL_RCC_DAC2_IS_CLK_ENABLED +#define __DAC2_IS_CLK_DISABLED __HAL_RCC_DAC2_IS_CLK_DISABLED +#define __DMA1_IS_CLK_ENABLED __HAL_RCC_DMA1_IS_CLK_ENABLED +#define __DMA1_IS_CLK_DISABLED __HAL_RCC_DMA1_IS_CLK_DISABLED +#define __DMA2_IS_CLK_ENABLED __HAL_RCC_DMA2_IS_CLK_ENABLED +#define __DMA2_IS_CLK_DISABLED __HAL_RCC_DMA2_IS_CLK_DISABLED +#define __FLITF_IS_CLK_ENABLED __HAL_RCC_FLITF_IS_CLK_ENABLED +#define __FLITF_IS_CLK_DISABLED __HAL_RCC_FLITF_IS_CLK_DISABLED +#define __FMC_IS_CLK_ENABLED __HAL_RCC_FMC_IS_CLK_ENABLED +#define __FMC_IS_CLK_DISABLED __HAL_RCC_FMC_IS_CLK_DISABLED +#define __GPIOA_IS_CLK_ENABLED __HAL_RCC_GPIOA_IS_CLK_ENABLED +#define __GPIOA_IS_CLK_DISABLED __HAL_RCC_GPIOA_IS_CLK_DISABLED +#define __GPIOB_IS_CLK_ENABLED __HAL_RCC_GPIOB_IS_CLK_ENABLED +#define __GPIOB_IS_CLK_DISABLED __HAL_RCC_GPIOB_IS_CLK_DISABLED +#define __GPIOC_IS_CLK_ENABLED __HAL_RCC_GPIOC_IS_CLK_ENABLED +#define __GPIOC_IS_CLK_DISABLED __HAL_RCC_GPIOC_IS_CLK_DISABLED +#define __GPIOD_IS_CLK_ENABLED __HAL_RCC_GPIOD_IS_CLK_ENABLED +#define __GPIOD_IS_CLK_DISABLED __HAL_RCC_GPIOD_IS_CLK_DISABLED +#define __GPIOE_IS_CLK_ENABLED __HAL_RCC_GPIOE_IS_CLK_ENABLED +#define __GPIOE_IS_CLK_DISABLED __HAL_RCC_GPIOE_IS_CLK_DISABLED +#define __GPIOF_IS_CLK_ENABLED __HAL_RCC_GPIOF_IS_CLK_ENABLED +#define __GPIOF_IS_CLK_DISABLED __HAL_RCC_GPIOF_IS_CLK_DISABLED +#define __GPIOG_IS_CLK_ENABLED __HAL_RCC_GPIOG_IS_CLK_ENABLED +#define __GPIOG_IS_CLK_DISABLED __HAL_RCC_GPIOG_IS_CLK_DISABLED +#define __GPIOH_IS_CLK_ENABLED __HAL_RCC_GPIOH_IS_CLK_ENABLED +#define __GPIOH_IS_CLK_DISABLED __HAL_RCC_GPIOH_IS_CLK_DISABLED +#define __HRTIM1_IS_CLK_ENABLED __HAL_RCC_HRTIM1_IS_CLK_ENABLED +#define __HRTIM1_IS_CLK_DISABLED __HAL_RCC_HRTIM1_IS_CLK_DISABLED +#define __I2C1_IS_CLK_ENABLED __HAL_RCC_I2C1_IS_CLK_ENABLED +#define __I2C1_IS_CLK_DISABLED __HAL_RCC_I2C1_IS_CLK_DISABLED +#define __I2C2_IS_CLK_ENABLED __HAL_RCC_I2C2_IS_CLK_ENABLED +#define __I2C2_IS_CLK_DISABLED __HAL_RCC_I2C2_IS_CLK_DISABLED +#define __I2C3_IS_CLK_ENABLED __HAL_RCC_I2C3_IS_CLK_ENABLED +#define __I2C3_IS_CLK_DISABLED __HAL_RCC_I2C3_IS_CLK_DISABLED +#define __PWR_IS_CLK_ENABLED __HAL_RCC_PWR_IS_CLK_ENABLED +#define __PWR_IS_CLK_DISABLED __HAL_RCC_PWR_IS_CLK_DISABLED +#define __SYSCFG_IS_CLK_ENABLED __HAL_RCC_SYSCFG_IS_CLK_ENABLED +#define __SYSCFG_IS_CLK_DISABLED __HAL_RCC_SYSCFG_IS_CLK_DISABLED +#define __SPI1_IS_CLK_ENABLED __HAL_RCC_SPI1_IS_CLK_ENABLED +#define __SPI1_IS_CLK_DISABLED __HAL_RCC_SPI1_IS_CLK_DISABLED +#define __SPI2_IS_CLK_ENABLED __HAL_RCC_SPI2_IS_CLK_ENABLED +#define __SPI2_IS_CLK_DISABLED __HAL_RCC_SPI2_IS_CLK_DISABLED +#define __SPI3_IS_CLK_ENABLED __HAL_RCC_SPI3_IS_CLK_ENABLED +#define __SPI3_IS_CLK_DISABLED __HAL_RCC_SPI3_IS_CLK_DISABLED +#define __SPI4_IS_CLK_ENABLED __HAL_RCC_SPI4_IS_CLK_ENABLED +#define __SPI4_IS_CLK_DISABLED __HAL_RCC_SPI4_IS_CLK_DISABLED +#define __SDADC1_IS_CLK_ENABLED __HAL_RCC_SDADC1_IS_CLK_ENABLED +#define __SDADC1_IS_CLK_DISABLED __HAL_RCC_SDADC1_IS_CLK_DISABLED +#define __SDADC2_IS_CLK_ENABLED __HAL_RCC_SDADC2_IS_CLK_ENABLED +#define __SDADC2_IS_CLK_DISABLED __HAL_RCC_SDADC2_IS_CLK_DISABLED +#define __SDADC3_IS_CLK_ENABLED __HAL_RCC_SDADC3_IS_CLK_ENABLED +#define __SDADC3_IS_CLK_DISABLED __HAL_RCC_SDADC3_IS_CLK_DISABLED +#define __SRAM_IS_CLK_ENABLED __HAL_RCC_SRAM_IS_CLK_ENABLED +#define __SRAM_IS_CLK_DISABLED __HAL_RCC_SRAM_IS_CLK_DISABLED +#define __TIM1_IS_CLK_ENABLED __HAL_RCC_TIM1_IS_CLK_ENABLED +#define __TIM1_IS_CLK_DISABLED __HAL_RCC_TIM1_IS_CLK_DISABLED +#define __TIM2_IS_CLK_ENABLED __HAL_RCC_TIM2_IS_CLK_ENABLED +#define __TIM2_IS_CLK_DISABLED __HAL_RCC_TIM2_IS_CLK_DISABLED +#define __TIM3_IS_CLK_ENABLED __HAL_RCC_TIM3_IS_CLK_ENABLED +#define __TIM3_IS_CLK_DISABLED __HAL_RCC_TIM3_IS_CLK_DISABLED +#define __TIM4_IS_CLK_ENABLED __HAL_RCC_TIM4_IS_CLK_ENABLED +#define __TIM4_IS_CLK_DISABLED __HAL_RCC_TIM4_IS_CLK_DISABLED +#define __TIM5_IS_CLK_ENABLED __HAL_RCC_TIM5_IS_CLK_ENABLED +#define __TIM5_IS_CLK_DISABLED __HAL_RCC_TIM5_IS_CLK_DISABLED +#define __TIM6_IS_CLK_ENABLED __HAL_RCC_TIM6_IS_CLK_ENABLED +#define __TIM6_IS_CLK_DISABLED __HAL_RCC_TIM6_IS_CLK_DISABLED +#define __TIM7_IS_CLK_ENABLED __HAL_RCC_TIM7_IS_CLK_ENABLED +#define __TIM7_IS_CLK_DISABLED __HAL_RCC_TIM7_IS_CLK_DISABLED +#define __TIM8_IS_CLK_ENABLED __HAL_RCC_TIM8_IS_CLK_ENABLED +#define __TIM8_IS_CLK_DISABLED __HAL_RCC_TIM8_IS_CLK_DISABLED +#define __TIM12_IS_CLK_ENABLED __HAL_RCC_TIM12_IS_CLK_ENABLED +#define __TIM12_IS_CLK_DISABLED __HAL_RCC_TIM12_IS_CLK_DISABLED +#define __TIM13_IS_CLK_ENABLED __HAL_RCC_TIM13_IS_CLK_ENABLED +#define __TIM13_IS_CLK_DISABLED __HAL_RCC_TIM13_IS_CLK_DISABLED +#define __TIM14_IS_CLK_ENABLED __HAL_RCC_TIM14_IS_CLK_ENABLED +#define __TIM14_IS_CLK_DISABLED __HAL_RCC_TIM14_IS_CLK_DISABLED +#define __TIM15_IS_CLK_ENABLED __HAL_RCC_TIM15_IS_CLK_ENABLED +#define __TIM15_IS_CLK_DISABLED __HAL_RCC_TIM15_IS_CLK_DISABLED +#define __TIM16_IS_CLK_ENABLED __HAL_RCC_TIM16_IS_CLK_ENABLED +#define __TIM16_IS_CLK_DISABLED __HAL_RCC_TIM16_IS_CLK_DISABLED +#define __TIM17_IS_CLK_ENABLED __HAL_RCC_TIM17_IS_CLK_ENABLED +#define __TIM17_IS_CLK_DISABLED __HAL_RCC_TIM17_IS_CLK_DISABLED +#define __TIM18_IS_CLK_ENABLED __HAL_RCC_TIM18_IS_CLK_ENABLED +#define __TIM18_IS_CLK_DISABLED __HAL_RCC_TIM18_IS_CLK_DISABLED +#define __TIM19_IS_CLK_ENABLED __HAL_RCC_TIM19_IS_CLK_ENABLED +#define __TIM19_IS_CLK_DISABLED __HAL_RCC_TIM19_IS_CLK_DISABLED +#define __TIM20_IS_CLK_ENABLED __HAL_RCC_TIM20_IS_CLK_ENABLED +#define __TIM20_IS_CLK_DISABLED __HAL_RCC_TIM20_IS_CLK_DISABLED +#define __TSC_IS_CLK_ENABLED __HAL_RCC_TSC_IS_CLK_ENABLED +#define __TSC_IS_CLK_DISABLED __HAL_RCC_TSC_IS_CLK_DISABLED +#define __UART4_IS_CLK_ENABLED __HAL_RCC_UART4_IS_CLK_ENABLED +#define __UART4_IS_CLK_DISABLED __HAL_RCC_UART4_IS_CLK_DISABLED +#define __UART5_IS_CLK_ENABLED __HAL_RCC_UART5_IS_CLK_ENABLED +#define __UART5_IS_CLK_DISABLED __HAL_RCC_UART5_IS_CLK_DISABLED +#define __USART1_IS_CLK_ENABLED __HAL_RCC_USART1_IS_CLK_ENABLED +#define __USART1_IS_CLK_DISABLED __HAL_RCC_USART1_IS_CLK_DISABLED +#define __USART2_IS_CLK_ENABLED __HAL_RCC_USART2_IS_CLK_ENABLED +#define __USART2_IS_CLK_DISABLED __HAL_RCC_USART2_IS_CLK_DISABLED +#define __USART3_IS_CLK_ENABLED __HAL_RCC_USART3_IS_CLK_ENABLED +#define __USART3_IS_CLK_DISABLED __HAL_RCC_USART3_IS_CLK_DISABLED +#define __USB_IS_CLK_ENABLED __HAL_RCC_USB_IS_CLK_ENABLED +#define __USB_IS_CLK_DISABLED __HAL_RCC_USB_IS_CLK_DISABLED +#define __WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLED +#define __WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED + +#if defined(STM32L1) +#define __HAL_RCC_CRYP_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE +#define __HAL_RCC_CRYP_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE +#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE +#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE +#define __HAL_RCC_CRYP_FORCE_RESET __HAL_RCC_AES_FORCE_RESET +#define __HAL_RCC_CRYP_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET +#endif /* STM32L1 */ + +#if defined(STM32F4) +#define __HAL_RCC_SDMMC1_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET +#define __HAL_RCC_SDMMC1_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET +#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE +#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE +#define __HAL_RCC_SDMMC1_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE +#define __HAL_RCC_SDMMC1_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE +#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED __HAL_RCC_SDIO_IS_CLK_ENABLED +#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED __HAL_RCC_SDIO_IS_CLK_DISABLED +#define Sdmmc1ClockSelection SdioClockSelection +#define RCC_PERIPHCLK_SDMMC1 RCC_PERIPHCLK_SDIO +#define RCC_SDMMC1CLKSOURCE_CLK48 RCC_SDIOCLKSOURCE_CK48 +#define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_SDIOCLKSOURCE_SYSCLK +#define __HAL_RCC_SDMMC1_CONFIG __HAL_RCC_SDIO_CONFIG +#define __HAL_RCC_GET_SDMMC1_SOURCE __HAL_RCC_GET_SDIO_SOURCE +#endif + +#if defined(STM32F7) || defined(STM32L4) +#define __HAL_RCC_SDIO_FORCE_RESET __HAL_RCC_SDMMC1_FORCE_RESET +#define __HAL_RCC_SDIO_RELEASE_RESET __HAL_RCC_SDMMC1_RELEASE_RESET +#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE +#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE +#define __HAL_RCC_SDIO_CLK_ENABLE __HAL_RCC_SDMMC1_CLK_ENABLE +#define __HAL_RCC_SDIO_CLK_DISABLE __HAL_RCC_SDMMC1_CLK_DISABLE +#define __HAL_RCC_SDIO_IS_CLK_ENABLED __HAL_RCC_SDMMC1_IS_CLK_ENABLED +#define __HAL_RCC_SDIO_IS_CLK_DISABLED __HAL_RCC_SDMMC1_IS_CLK_DISABLED +#define SdioClockSelection Sdmmc1ClockSelection +#define RCC_PERIPHCLK_SDIO RCC_PERIPHCLK_SDMMC1 +#define __HAL_RCC_SDIO_CONFIG __HAL_RCC_SDMMC1_CONFIG +#define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE +#endif + +#if defined(STM32F7) +#define RCC_SDIOCLKSOURCE_CLK48 RCC_SDMMC1CLKSOURCE_CLK48 +#define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK +#endif + +#if defined(STM32H7) +#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_ENABLE() +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE() +#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_DISABLE() +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE() +#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() __HAL_RCC_USB1_OTG_HS_FORCE_RESET() +#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() __HAL_RCC_USB1_OTG_HS_RELEASE_RESET() +#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE() +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE() +#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE() +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE() + +#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_ENABLE() +#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE() +#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_DISABLE() +#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE() +#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() __HAL_RCC_USB2_OTG_FS_FORCE_RESET() +#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() __HAL_RCC_USB2_OTG_FS_RELEASE_RESET() +#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE() +#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE() +#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE() +#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE() +#endif + +#define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG +#define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG + +#define __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE + +#define IS_RCC_MSIRANGE IS_RCC_MSI_CLOCK_RANGE +#define IS_RCC_RTCCLK_SOURCE IS_RCC_RTCCLKSOURCE +#define IS_RCC_SYSCLK_DIV IS_RCC_HCLK +#define IS_RCC_HCLK_DIV IS_RCC_PCLK +#define IS_RCC_PERIPHCLK IS_RCC_PERIPHCLOCK + +#define RCC_IT_HSI14 RCC_IT_HSI14RDY + +#define RCC_IT_CSSLSE RCC_IT_LSECSS +#define RCC_IT_CSSHSE RCC_IT_CSS + +#define RCC_PLLMUL_3 RCC_PLL_MUL3 +#define RCC_PLLMUL_4 RCC_PLL_MUL4 +#define RCC_PLLMUL_6 RCC_PLL_MUL6 +#define RCC_PLLMUL_8 RCC_PLL_MUL8 +#define RCC_PLLMUL_12 RCC_PLL_MUL12 +#define RCC_PLLMUL_16 RCC_PLL_MUL16 +#define RCC_PLLMUL_24 RCC_PLL_MUL24 +#define RCC_PLLMUL_32 RCC_PLL_MUL32 +#define RCC_PLLMUL_48 RCC_PLL_MUL48 + +#define RCC_PLLDIV_2 RCC_PLL_DIV2 +#define RCC_PLLDIV_3 RCC_PLL_DIV3 +#define RCC_PLLDIV_4 RCC_PLL_DIV4 + +#define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE +#define __HAL_RCC_MCO_CONFIG __HAL_RCC_MCO1_CONFIG +#define RCC_MCO_NODIV RCC_MCODIV_1 +#define RCC_MCO_DIV1 RCC_MCODIV_1 +#define RCC_MCO_DIV2 RCC_MCODIV_2 +#define RCC_MCO_DIV4 RCC_MCODIV_4 +#define RCC_MCO_DIV8 RCC_MCODIV_8 +#define RCC_MCO_DIV16 RCC_MCODIV_16 +#define RCC_MCO_DIV32 RCC_MCODIV_32 +#define RCC_MCO_DIV64 RCC_MCODIV_64 +#define RCC_MCO_DIV128 RCC_MCODIV_128 +#define RCC_MCOSOURCE_NONE RCC_MCO1SOURCE_NOCLOCK +#define RCC_MCOSOURCE_LSI RCC_MCO1SOURCE_LSI +#define RCC_MCOSOURCE_LSE RCC_MCO1SOURCE_LSE +#define RCC_MCOSOURCE_SYSCLK RCC_MCO1SOURCE_SYSCLK +#define RCC_MCOSOURCE_HSI RCC_MCO1SOURCE_HSI +#define RCC_MCOSOURCE_HSI14 RCC_MCO1SOURCE_HSI14 +#define RCC_MCOSOURCE_HSI48 RCC_MCO1SOURCE_HSI48 +#define RCC_MCOSOURCE_HSE RCC_MCO1SOURCE_HSE +#define RCC_MCOSOURCE_PLLCLK_DIV1 RCC_MCO1SOURCE_PLLCLK +#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK +#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2 + +#if defined(STM32U0) +#define RCC_SYSCLKSOURCE_STATUS_PLLR RCC_SYSCLKSOURCE_STATUS_PLLCLK +#endif + + +#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || \ + defined(STM32WL) || defined(STM32C0) || defined(STM32N6) || defined(STM32H7RS) || \ + defined(STM32U0) +#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE +#else +#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK +#endif + +#define RCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1 +#define RCC_USBCLK_PLL RCC_USBCLKSOURCE_PLL +#define RCC_USBCLK_MSI RCC_USBCLKSOURCE_MSI +#define RCC_USBCLKSOURCE_PLLCLK RCC_USBCLKSOURCE_PLL +#define RCC_USBPLLCLK_DIV1 RCC_USBCLKSOURCE_PLL +#define RCC_USBPLLCLK_DIV1_5 RCC_USBCLKSOURCE_PLL_DIV1_5 +#define RCC_USBPLLCLK_DIV2 RCC_USBCLKSOURCE_PLL_DIV2 +#define RCC_USBPLLCLK_DIV3 RCC_USBCLKSOURCE_PLL_DIV3 + +#define HSION_BitNumber RCC_HSION_BIT_NUMBER +#define HSION_BITNUMBER RCC_HSION_BIT_NUMBER +#define HSEON_BitNumber RCC_HSEON_BIT_NUMBER +#define HSEON_BITNUMBER RCC_HSEON_BIT_NUMBER +#define MSION_BITNUMBER RCC_MSION_BIT_NUMBER +#define CSSON_BitNumber RCC_CSSON_BIT_NUMBER +#define CSSON_BITNUMBER RCC_CSSON_BIT_NUMBER +#define PLLON_BitNumber RCC_PLLON_BIT_NUMBER +#define PLLON_BITNUMBER RCC_PLLON_BIT_NUMBER +#define PLLI2SON_BitNumber RCC_PLLI2SON_BIT_NUMBER +#define I2SSRC_BitNumber RCC_I2SSRC_BIT_NUMBER +#define RTCEN_BitNumber RCC_RTCEN_BIT_NUMBER +#define RTCEN_BITNUMBER RCC_RTCEN_BIT_NUMBER +#define BDRST_BitNumber RCC_BDRST_BIT_NUMBER +#define BDRST_BITNUMBER RCC_BDRST_BIT_NUMBER +#define RTCRST_BITNUMBER RCC_RTCRST_BIT_NUMBER +#define LSION_BitNumber RCC_LSION_BIT_NUMBER +#define LSION_BITNUMBER RCC_LSION_BIT_NUMBER +#define LSEON_BitNumber RCC_LSEON_BIT_NUMBER +#define LSEON_BITNUMBER RCC_LSEON_BIT_NUMBER +#define LSEBYP_BITNUMBER RCC_LSEBYP_BIT_NUMBER +#define PLLSAION_BitNumber RCC_PLLSAION_BIT_NUMBER +#define TIMPRE_BitNumber RCC_TIMPRE_BIT_NUMBER +#define RMVF_BitNumber RCC_RMVF_BIT_NUMBER +#define RMVF_BITNUMBER RCC_RMVF_BIT_NUMBER +#define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER +#define CR_BYTE2_ADDRESS RCC_CR_BYTE2_ADDRESS +#define CIR_BYTE1_ADDRESS RCC_CIR_BYTE1_ADDRESS +#define CIR_BYTE2_ADDRESS RCC_CIR_BYTE2_ADDRESS +#define BDCR_BYTE0_ADDRESS RCC_BDCR_BYTE0_ADDRESS +#define DBP_TIMEOUT_VALUE RCC_DBP_TIMEOUT_VALUE +#define LSE_TIMEOUT_VALUE RCC_LSE_TIMEOUT_VALUE + +#define CR_HSION_BB RCC_CR_HSION_BB +#define CR_CSSON_BB RCC_CR_CSSON_BB +#define CR_PLLON_BB RCC_CR_PLLON_BB +#define CR_PLLI2SON_BB RCC_CR_PLLI2SON_BB +#define CR_MSION_BB RCC_CR_MSION_BB +#define CSR_LSION_BB RCC_CSR_LSION_BB +#define CSR_LSEON_BB RCC_CSR_LSEON_BB +#define CSR_LSEBYP_BB RCC_CSR_LSEBYP_BB +#define CSR_RTCEN_BB RCC_CSR_RTCEN_BB +#define CSR_RTCRST_BB RCC_CSR_RTCRST_BB +#define CFGR_I2SSRC_BB RCC_CFGR_I2SSRC_BB +#define BDCR_RTCEN_BB RCC_BDCR_RTCEN_BB +#define BDCR_BDRST_BB RCC_BDCR_BDRST_BB +#define CR_HSEON_BB RCC_CR_HSEON_BB +#define CSR_RMVF_BB RCC_CSR_RMVF_BB +#define CR_PLLSAION_BB RCC_CR_PLLSAION_BB +#define DCKCFGR_TIMPRE_BB RCC_DCKCFGR_TIMPRE_BB + +#define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE +#define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE +#define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE +#define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE +#define __HAL_RCC_CRS_CALCULATE_RELOADVALUE __HAL_RCC_CRS_RELOADVALUE_CALCULATE + +#define __HAL_RCC_GET_IT_SOURCE __HAL_RCC_GET_IT + +#define RCC_CRS_SYNCWARM RCC_CRS_SYNCWARN +#define RCC_CRS_TRIMOV RCC_CRS_TRIMOVF + +#define RCC_PERIPHCLK_CK48 RCC_PERIPHCLK_CLK48 +#define RCC_CK48CLKSOURCE_PLLQ RCC_CLK48CLKSOURCE_PLLQ +#define RCC_CK48CLKSOURCE_PLLSAIP RCC_CLK48CLKSOURCE_PLLSAIP +#define RCC_CK48CLKSOURCE_PLLI2SQ RCC_CLK48CLKSOURCE_PLLI2SQ +#define IS_RCC_CK48CLKSOURCE IS_RCC_CLK48CLKSOURCE +#define RCC_SDIOCLKSOURCE_CK48 RCC_SDIOCLKSOURCE_CLK48 + +#define __HAL_RCC_DFSDM_CLK_ENABLE __HAL_RCC_DFSDM1_CLK_ENABLE +#define __HAL_RCC_DFSDM_CLK_DISABLE __HAL_RCC_DFSDM1_CLK_DISABLE +#define __HAL_RCC_DFSDM_IS_CLK_ENABLED __HAL_RCC_DFSDM1_IS_CLK_ENABLED +#define __HAL_RCC_DFSDM_IS_CLK_DISABLED __HAL_RCC_DFSDM1_IS_CLK_DISABLED +#define __HAL_RCC_DFSDM_FORCE_RESET __HAL_RCC_DFSDM1_FORCE_RESET +#define __HAL_RCC_DFSDM_RELEASE_RESET __HAL_RCC_DFSDM1_RELEASE_RESET +#define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE +#define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE +#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED +#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED +#define DfsdmClockSelection Dfsdm1ClockSelection +#define RCC_PERIPHCLK_DFSDM RCC_PERIPHCLK_DFSDM1 +#define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2 +#define RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK +#define __HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG +#define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE +#define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2 +#define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1 +#if !defined(STM32U0) +#define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1 +#define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1 +#endif + +#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1 +#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2 +#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM2AUDIOCLKSOURCE_I2S1 +#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM2AUDIOCLKSOURCE_I2S2 +#define RCC_DFSDM1CLKSOURCE_APB2 RCC_DFSDM1CLKSOURCE_PCLK2 +#define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2 +#define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1 +#if defined(STM32U5) +#define MSIKPLLModeSEL RCC_MSIKPLL_MODE_SEL +#define MSISPLLModeSEL RCC_MSISPLL_MODE_SEL +#define __HAL_RCC_AHB21_CLK_DISABLE __HAL_RCC_AHB2_1_CLK_DISABLE +#define __HAL_RCC_AHB22_CLK_DISABLE __HAL_RCC_AHB2_2_CLK_DISABLE +#define __HAL_RCC_AHB1_CLK_Disable_Clear __HAL_RCC_AHB1_CLK_ENABLE +#define __HAL_RCC_AHB21_CLK_Disable_Clear __HAL_RCC_AHB2_1_CLK_ENABLE +#define __HAL_RCC_AHB22_CLK_Disable_Clear __HAL_RCC_AHB2_2_CLK_ENABLE +#define __HAL_RCC_AHB3_CLK_Disable_Clear __HAL_RCC_AHB3_CLK_ENABLE +#define __HAL_RCC_APB1_CLK_Disable_Clear __HAL_RCC_APB1_CLK_ENABLE +#define __HAL_RCC_APB2_CLK_Disable_Clear __HAL_RCC_APB2_CLK_ENABLE +#define __HAL_RCC_APB3_CLK_Disable_Clear __HAL_RCC_APB3_CLK_ENABLE +#define IS_RCC_MSIPLLModeSelection IS_RCC_MSIPLLMODE_SELECT +#define RCC_PERIPHCLK_CLK48 RCC_PERIPHCLK_ICLK +#define RCC_CLK48CLKSOURCE_HSI48 RCC_ICLK_CLKSOURCE_HSI48 +#define RCC_CLK48CLKSOURCE_PLL2 RCC_ICLK_CLKSOURCE_PLL2 +#define RCC_CLK48CLKSOURCE_PLL1 RCC_ICLK_CLKSOURCE_PLL1 +#define RCC_CLK48CLKSOURCE_MSIK RCC_ICLK_CLKSOURCE_MSIK +#define __HAL_RCC_ADC1_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE +#define __HAL_RCC_ADC1_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE +#define __HAL_RCC_ADC1_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED +#define __HAL_RCC_ADC1_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED +#define __HAL_RCC_ADC1_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET +#define __HAL_RCC_ADC1_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET +#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC12_CLK_SLEEP_ENABLE +#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC12_CLK_SLEEP_DISABLE +#define __HAL_RCC_GET_CLK48_SOURCE __HAL_RCC_GET_ICLK_SOURCE +#define __HAL_RCC_PLLFRACN_ENABLE __HAL_RCC_PLL_FRACN_ENABLE +#define __HAL_RCC_PLLFRACN_DISABLE __HAL_RCC_PLL_FRACN_DISABLE +#define __HAL_RCC_PLLFRACN_CONFIG __HAL_RCC_PLL_FRACN_CONFIG +#define IS_RCC_PLLFRACN_VALUE IS_RCC_PLL_FRACN_VALUE +#endif /* STM32U5 */ + +#if defined(STM32H5) +#define __HAL_RCC_PLLFRACN_ENABLE __HAL_RCC_PLL_FRACN_ENABLE +#define __HAL_RCC_PLLFRACN_DISABLE __HAL_RCC_PLL_FRACN_DISABLE +#define __HAL_RCC_PLLFRACN_CONFIG __HAL_RCC_PLL_FRACN_CONFIG +#define IS_RCC_PLLFRACN_VALUE IS_RCC_PLL_FRACN_VALUE + +#define RCC_PLLSOURCE_NONE RCC_PLL1_SOURCE_NONE +#define RCC_PLLSOURCE_HSI RCC_PLL1_SOURCE_HSI +#define RCC_PLLSOURCE_CSI RCC_PLL1_SOURCE_CSI +#define RCC_PLLSOURCE_HSE RCC_PLL1_SOURCE_HSE +#define RCC_PLLVCIRANGE_0 RCC_PLL1_VCIRANGE_0 +#define RCC_PLLVCIRANGE_1 RCC_PLL1_VCIRANGE_1 +#define RCC_PLLVCIRANGE_2 RCC_PLL1_VCIRANGE_2 +#define RCC_PLLVCIRANGE_3 RCC_PLL1_VCIRANGE_3 +#define RCC_PLL1VCOWIDE RCC_PLL1_VCORANGE_WIDE +#define RCC_PLL1VCOMEDIUM RCC_PLL1_VCORANGE_MEDIUM + +#define IS_RCC_PLLSOURCE IS_RCC_PLL1_SOURCE +#define IS_RCC_PLLRGE_VALUE IS_RCC_PLL1_VCIRGE_VALUE +#define IS_RCC_PLLVCORGE_VALUE IS_RCC_PLL1_VCORGE_VALUE +#define IS_RCC_PLLCLOCKOUT_VALUE IS_RCC_PLL1_CLOCKOUT_VALUE +#define IS_RCC_PLL_FRACN_VALUE IS_RCC_PLL1_FRACN_VALUE +#define IS_RCC_PLLM_VALUE IS_RCC_PLL1_DIVM_VALUE +#define IS_RCC_PLLN_VALUE IS_RCC_PLL1_MULN_VALUE +#define IS_RCC_PLLP_VALUE IS_RCC_PLL1_DIVP_VALUE +#define IS_RCC_PLLQ_VALUE IS_RCC_PLL1_DIVQ_VALUE +#define IS_RCC_PLLR_VALUE IS_RCC_PLL1_DIVR_VALUE + +#define __HAL_RCC_PLL_ENABLE __HAL_RCC_PLL1_ENABLE +#define __HAL_RCC_PLL_DISABLE __HAL_RCC_PLL1_DISABLE +#define __HAL_RCC_PLL_FRACN_ENABLE __HAL_RCC_PLL1_FRACN_ENABLE +#define __HAL_RCC_PLL_FRACN_DISABLE __HAL_RCC_PLL1_FRACN_DISABLE +#define __HAL_RCC_PLL_CONFIG __HAL_RCC_PLL1_CONFIG +#define __HAL_RCC_PLL_PLLSOURCE_CONFIG __HAL_RCC_PLL1_PLLSOURCE_CONFIG +#define __HAL_RCC_PLL_DIVM_CONFIG __HAL_RCC_PLL1_DIVM_CONFIG +#define __HAL_RCC_PLL_FRACN_CONFIG __HAL_RCC_PLL1_FRACN_CONFIG +#define __HAL_RCC_PLL_VCIRANGE __HAL_RCC_PLL1_VCIRANGE +#define __HAL_RCC_PLL_VCORANGE __HAL_RCC_PLL1_VCORANGE +#define __HAL_RCC_GET_PLL_OSCSOURCE __HAL_RCC_GET_PLL1_OSCSOURCE +#define __HAL_RCC_PLLCLKOUT_ENABLE __HAL_RCC_PLL1_CLKOUT_ENABLE +#define __HAL_RCC_PLLCLKOUT_DISABLE __HAL_RCC_PLL1_CLKOUT_DISABLE +#define __HAL_RCC_GET_PLLCLKOUT_CONFIG __HAL_RCC_GET_PLL1_CLKOUT_CONFIG + +#define __HAL_RCC_PLL2FRACN_ENABLE __HAL_RCC_PLL2_FRACN_ENABLE +#define __HAL_RCC_PLL2FRACN_DISABLE __HAL_RCC_PLL2_FRACN_DISABLE +#define __HAL_RCC_PLL2CLKOUT_ENABLE __HAL_RCC_PLL2_CLKOUT_ENABLE +#define __HAL_RCC_PLL2CLKOUT_DISABLE __HAL_RCC_PLL2_CLKOUT_DISABLE +#define __HAL_RCC_PLL2FRACN_CONFIG __HAL_RCC_PLL2_FRACN_CONFIG +#define __HAL_RCC_GET_PLL2CLKOUT_CONFIG __HAL_RCC_GET_PLL2_CLKOUT_CONFIG + +#define __HAL_RCC_PLL3FRACN_ENABLE __HAL_RCC_PLL3_FRACN_ENABLE +#define __HAL_RCC_PLL3FRACN_DISABLE __HAL_RCC_PLL3_FRACN_DISABLE +#define __HAL_RCC_PLL3CLKOUT_ENABLE __HAL_RCC_PLL3_CLKOUT_ENABLE +#define __HAL_RCC_PLL3CLKOUT_DISABLE __HAL_RCC_PLL3_CLKOUT_DISABLE +#define __HAL_RCC_PLL3FRACN_CONFIG __HAL_RCC_PLL3_FRACN_CONFIG +#define __HAL_RCC_GET_PLL3CLKOUT_CONFIG __HAL_RCC_GET_PLL3_CLKOUT_CONFIG + +#define RCC_PLL2VCIRANGE_0 RCC_PLL2_VCIRANGE_0 +#define RCC_PLL2VCIRANGE_1 RCC_PLL2_VCIRANGE_1 +#define RCC_PLL2VCIRANGE_2 RCC_PLL2_VCIRANGE_2 +#define RCC_PLL2VCIRANGE_3 RCC_PLL2_VCIRANGE_3 + +#define RCC_PLL2VCOWIDE RCC_PLL2_VCORANGE_WIDE +#define RCC_PLL2VCOMEDIUM RCC_PLL2_VCORANGE_MEDIUM + +#define RCC_PLL2SOURCE_NONE RCC_PLL2_SOURCE_NONE +#define RCC_PLL2SOURCE_HSI RCC_PLL2_SOURCE_HSI +#define RCC_PLL2SOURCE_CSI RCC_PLL2_SOURCE_CSI +#define RCC_PLL2SOURCE_HSE RCC_PLL2_SOURCE_HSE + +#define RCC_PLL3VCIRANGE_0 RCC_PLL3_VCIRANGE_0 +#define RCC_PLL3VCIRANGE_1 RCC_PLL3_VCIRANGE_1 +#define RCC_PLL3VCIRANGE_2 RCC_PLL3_VCIRANGE_2 +#define RCC_PLL3VCIRANGE_3 RCC_PLL3_VCIRANGE_3 + +#define RCC_PLL3VCOWIDE RCC_PLL3_VCORANGE_WIDE +#define RCC_PLL3VCOMEDIUM RCC_PLL3_VCORANGE_MEDIUM + +#define RCC_PLL3SOURCE_NONE RCC_PLL3_SOURCE_NONE +#define RCC_PLL3SOURCE_HSI RCC_PLL3_SOURCE_HSI +#define RCC_PLL3SOURCE_CSI RCC_PLL3_SOURCE_CSI +#define RCC_PLL3SOURCE_HSE RCC_PLL3_SOURCE_HSE + + +#endif /* STM32H5 */ + +/** + * @} + */ + +/** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose + * @{ + */ +#define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit) + +/** + * @} + */ + +/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose + * @{ + */ +#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || \ + defined (STM32L4P5xx)|| defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \ + defined (STM32WBA) || defined (STM32H5) || defined (STM32C0) || defined (STM32N6) || \ + defined (STM32H7RS) || defined (STM32U0) || defined (STM32U3) +#else +#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG +#endif +#define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT +#define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT + +#if defined (STM32F1) +#define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() + +#define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_ENABLE_IT() + +#define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_DISABLE_IT() + +#define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GET_FLAG() + +#define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() +#else +#define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG())) +#define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT())) +#define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT())) +#define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG())) +#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT())) +#endif /* STM32F1 */ + +#if defined (STM32F0) || defined (STM32F2) || defined (STM32F3) || defined (STM32F4) || defined (STM32F7) || \ + defined (STM32H7) || \ + defined (STM32L0) || defined (STM32L1) || \ + defined (STM32WB) +#define __HAL_RTC_TAMPER_GET_IT __HAL_RTC_TAMPER_GET_FLAG +#endif + +#define IS_ALARM IS_RTC_ALARM +#define IS_ALARM_MASK IS_RTC_ALARM_MASK +#define IS_TAMPER IS_RTC_TAMPER +#define IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE +#define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER +#define IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT +#define IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE +#define IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION +#define IS_TAMPER_PULLUP_STATE IS_RTC_TAMPER_PULLUP_STATE +#define IS_TAMPER_SAMPLING_FREQ IS_RTC_TAMPER_SAMPLING_FREQ +#define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION +#define IS_TAMPER_TRIGGER IS_RTC_TAMPER_TRIGGER +#define IS_WAKEUP_CLOCK IS_RTC_WAKEUP_CLOCK +#define IS_WAKEUP_COUNTER IS_RTC_WAKEUP_COUNTER + +#define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE +#define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE + +#if defined (STM32H5) +#define __HAL_RCC_RTCAPB_CLK_ENABLE __HAL_RCC_RTC_CLK_ENABLE +#define __HAL_RCC_RTCAPB_CLK_DISABLE __HAL_RCC_RTC_CLK_DISABLE +#endif /* STM32H5 */ + +/** + * @} + */ + +/** @defgroup HAL_SD_Aliased_Macros HAL SD/MMC Aliased Macros maintained for legacy purpose + * @{ + */ + +#define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE +#define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS + +#if !defined(STM32F1) && !defined(STM32F2) && !defined(STM32F4) && !defined(STM32L1) +#define eMMC_HIGH_VOLTAGE_RANGE EMMC_HIGH_VOLTAGE_RANGE +#define eMMC_DUAL_VOLTAGE_RANGE EMMC_DUAL_VOLTAGE_RANGE +#define eMMC_LOW_VOLTAGE_RANGE EMMC_LOW_VOLTAGE_RANGE + +#define SDMMC_NSpeed_CLK_DIV SDMMC_NSPEED_CLK_DIV +#define SDMMC_HSpeed_CLK_DIV SDMMC_HSPEED_CLK_DIV +#endif + +#if defined(STM32F4) || defined(STM32F2) +#define SD_SDMMC_DISABLED SD_SDIO_DISABLED +#define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY +#define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED +#define SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION +#define SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND +#define SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT +#define SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED +#define __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE +#define __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE +#define __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE +#define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL +#define __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT +#define __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT +#define __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG +#define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG +#define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT +#define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT +#define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS +#define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT +#define SD_SDMMC_SEND_IF_COND SD_SDIO_SEND_IF_COND +/* alias CMSIS */ +#define SDMMC1_IRQn SDIO_IRQn +#define SDMMC1_IRQHandler SDIO_IRQHandler +#endif + +#if defined(STM32F7) || defined(STM32L4) +#define SD_SDIO_DISABLED SD_SDMMC_DISABLED +#define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY +#define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED +#define SD_SDIO_UNKNOWN_FUNCTION SD_SDMMC_UNKNOWN_FUNCTION +#define SD_CMD_SDIO_SEN_OP_COND SD_CMD_SDMMC_SEN_OP_COND +#define SD_CMD_SDIO_RW_DIRECT SD_CMD_SDMMC_RW_DIRECT +#define SD_CMD_SDIO_RW_EXTENDED SD_CMD_SDMMC_RW_EXTENDED +#define __HAL_SD_SDIO_ENABLE __HAL_SD_SDMMC_ENABLE +#define __HAL_SD_SDIO_DISABLE __HAL_SD_SDMMC_DISABLE +#define __HAL_SD_SDIO_DMA_ENABLE __HAL_SD_SDMMC_DMA_ENABLE +#define __HAL_SD_SDIO_DMA_DISABL __HAL_SD_SDMMC_DMA_DISABLE +#define __HAL_SD_SDIO_ENABLE_IT __HAL_SD_SDMMC_ENABLE_IT +#define __HAL_SD_SDIO_DISABLE_IT __HAL_SD_SDMMC_DISABLE_IT +#define __HAL_SD_SDIO_GET_FLAG __HAL_SD_SDMMC_GET_FLAG +#define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG +#define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT +#define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT +#define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS +#define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT +#define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND +/* alias CMSIS for compatibilities */ +#define SDIO_IRQn SDMMC1_IRQn +#define SDIO_IRQHandler SDMMC1_IRQHandler +#endif + +#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2) || defined(STM32L4) || defined(STM32H7) +#define HAL_SD_CardCIDTypedef HAL_SD_CardCIDTypeDef +#define HAL_SD_CardCSDTypedef HAL_SD_CardCSDTypeDef +#define HAL_SD_CardStatusTypedef HAL_SD_CardStatusTypeDef +#define HAL_SD_CardStateTypedef HAL_SD_CardStateTypeDef +#endif + +#if defined(STM32H7) || defined(STM32L5) +#define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback HAL_MMCEx_Read_DMADoubleBuf0CpltCallback +#define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback HAL_MMCEx_Read_DMADoubleBuf1CpltCallback +#define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback HAL_MMCEx_Write_DMADoubleBuf0CpltCallback +#define HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback HAL_MMCEx_Write_DMADoubleBuf1CpltCallback +#define HAL_SDEx_Read_DMADoubleBuffer0CpltCallback HAL_SDEx_Read_DMADoubleBuf0CpltCallback +#define HAL_SDEx_Read_DMADoubleBuffer1CpltCallback HAL_SDEx_Read_DMADoubleBuf1CpltCallback +#define HAL_SDEx_Write_DMADoubleBuffer0CpltCallback HAL_SDEx_Write_DMADoubleBuf0CpltCallback +#define HAL_SDEx_Write_DMADoubleBuffer1CpltCallback HAL_SDEx_Write_DMADoubleBuf1CpltCallback +#define HAL_SD_DriveTransciver_1_8V_Callback HAL_SD_DriveTransceiver_1_8V_Callback +#endif +/** + * @} + */ + +/** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __SMARTCARD_ENABLE_IT __HAL_SMARTCARD_ENABLE_IT +#define __SMARTCARD_DISABLE_IT __HAL_SMARTCARD_DISABLE_IT +#define __SMARTCARD_ENABLE __HAL_SMARTCARD_ENABLE +#define __SMARTCARD_DISABLE __HAL_SMARTCARD_DISABLE +#define __SMARTCARD_DMA_REQUEST_ENABLE __HAL_SMARTCARD_DMA_REQUEST_ENABLE +#define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE + +#define __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE +#define __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE + +#define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE + +/** + * @} + */ + +/** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_SMBUS_RESET_CR1 SMBUS_RESET_CR1 +#define __HAL_SMBUS_RESET_CR2 SMBUS_RESET_CR2 +#define __HAL_SMBUS_GENERATE_START SMBUS_GENERATE_START +#define __HAL_SMBUS_GET_ADDR_MATCH SMBUS_GET_ADDR_MATCH +#define __HAL_SMBUS_GET_DIR SMBUS_GET_DIR +#define __HAL_SMBUS_GET_STOP_MODE SMBUS_GET_STOP_MODE +#define __HAL_SMBUS_GET_PEC_MODE SMBUS_GET_PEC_MODE +#define __HAL_SMBUS_GET_ALERT_ENABLED SMBUS_GET_ALERT_ENABLED +/** + * @} + */ + +/** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_SPI_1LINE_TX SPI_1LINE_TX +#define __HAL_SPI_1LINE_RX SPI_1LINE_RX +#define __HAL_SPI_RESET_CRC SPI_RESET_CRC + +/** + * @} + */ + +/** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE +#define __HAL_UART_MASK_COMPUTATION UART_MASK_COMPUTATION +#define __UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE +#define __UART_MASK_COMPUTATION UART_MASK_COMPUTATION + +#define IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD + +#define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE +#define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE + +/** + * @} + */ + + +/** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __USART_ENABLE_IT __HAL_USART_ENABLE_IT +#define __USART_DISABLE_IT __HAL_USART_DISABLE_IT +#define __USART_ENABLE __HAL_USART_ENABLE +#define __USART_DISABLE __HAL_USART_DISABLE + +#define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE +#define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE + +#if defined(STM32F0) || defined(STM32F3) || defined(STM32F7) +#define USART_OVERSAMPLING_16 0x00000000U +#define USART_OVERSAMPLING_8 USART_CR1_OVER8 + +#define IS_USART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == USART_OVERSAMPLING_16) || \ + ((__SAMPLING__) == USART_OVERSAMPLING_8)) +#endif /* STM32F0 || STM32F3 || STM32F7 */ +/** + * @} + */ + +/** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose + * @{ + */ +#define USB_EXTI_LINE_WAKEUP USB_WAKEUP_EXTI_LINE + +#define USB_FS_EXTI_TRIGGER_RISING_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE +#define USB_FS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE +#define USB_FS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE +#define USB_FS_EXTI_LINE_WAKEUP USB_OTG_FS_WAKEUP_EXTI_LINE + +#define USB_HS_EXTI_TRIGGER_RISING_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE +#define USB_HS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE +#define USB_HS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE +#define USB_HS_EXTI_LINE_WAKEUP USB_OTG_HS_WAKEUP_EXTI_LINE + +#define __HAL_USB_EXTI_ENABLE_IT __HAL_USB_WAKEUP_EXTI_ENABLE_IT +#define __HAL_USB_EXTI_DISABLE_IT __HAL_USB_WAKEUP_EXTI_DISABLE_IT +#define __HAL_USB_EXTI_GET_FLAG __HAL_USB_WAKEUP_EXTI_GET_FLAG +#define __HAL_USB_EXTI_CLEAR_FLAG __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG +#define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE +#define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE +#define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE + +#define __HAL_USB_FS_EXTI_ENABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT +#define __HAL_USB_FS_EXTI_DISABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT +#define __HAL_USB_FS_EXTI_GET_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG +#define __HAL_USB_FS_EXTI_CLEAR_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG +#define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE +#define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE +#define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE +#define __HAL_USB_FS_EXTI_GENERATE_SWIT __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT + +#define __HAL_USB_HS_EXTI_ENABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT +#define __HAL_USB_HS_EXTI_DISABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT +#define __HAL_USB_HS_EXTI_GET_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG +#define __HAL_USB_HS_EXTI_CLEAR_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG +#define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE +#define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE +#define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE +#define __HAL_USB_HS_EXTI_GENERATE_SWIT __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT + +#define HAL_PCD_ActiveRemoteWakeup HAL_PCD_ActivateRemoteWakeup +#define HAL_PCD_DeActiveRemoteWakeup HAL_PCD_DeActivateRemoteWakeup + +#define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo +#define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo +#if defined(STM32U5) +#define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSVLD +#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINTMSK +#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPC +#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_PSRST +#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_GONAKEFF +#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUPINT +#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_IPXFRM_IISOOXFRM +#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_CHNUM +#define USB_OTG_GLPMCFG_L1ResumeOK USB_OTG_GLPMCFG_L1RSMOK +#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFSIZ +#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MCNT +#define USB_OTG_HCCHAR_MC_0 USB_OTG_HCCHAR_MCNT_0 +#define USB_OTG_HCCHAR_MC_1 USB_OTG_HCCHAR_MCNT_1 +#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERRM +#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPNG +#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OUTPKTERRM +#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SD1PID_SODDFRM +#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MCNT +#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SD1PID_SODDFRM +#define USB_OTG_DOEPCTL_DPID USB_OTG_DOEPCTL_DPID_EONUM +#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_RXDPID +#define USB_OTG_DOEPTSIZ_STUPCNT_0 USB_OTG_DOEPTSIZ_RXDPID_0 +#define USB_OTG_DOEPTSIZ_STUPCNT_1 USB_OTG_DOEPTSIZ_RXDPID_1 +#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STPPCLK +#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATEHCLK +#endif +/** + * @} + */ + +/** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_TIM_SetICPrescalerValue TIM_SET_ICPRESCALERVALUE +#define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE + +#define TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE +#define TIM_GET_CLEAR_IT __HAL_TIM_CLEAR_IT + +#define __HAL_TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE + +#define __HAL_TIM_DIRECTION_STATUS __HAL_TIM_IS_TIM_COUNTING_DOWN +#define __HAL_TIM_PRESCALER __HAL_TIM_SET_PRESCALER +#define __HAL_TIM_SetCounter __HAL_TIM_SET_COUNTER +#define __HAL_TIM_GetCounter __HAL_TIM_GET_COUNTER +#define __HAL_TIM_SetAutoreload __HAL_TIM_SET_AUTORELOAD +#define __HAL_TIM_GetAutoreload __HAL_TIM_GET_AUTORELOAD +#define __HAL_TIM_SetClockDivision __HAL_TIM_SET_CLOCKDIVISION +#define __HAL_TIM_GetClockDivision __HAL_TIM_GET_CLOCKDIVISION +#define __HAL_TIM_SetICPrescaler __HAL_TIM_SET_ICPRESCALER +#define __HAL_TIM_GetICPrescaler __HAL_TIM_GET_ICPRESCALER +#define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE +#define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE + +#define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1 + +#define TIM_OCMODE_ASSYMETRIC_PWM1 TIM_OCMODE_ASYMMETRIC_PWM1 +#define TIM_OCMODE_ASSYMETRIC_PWM2 TIM_OCMODE_ASYMMETRIC_PWM2 +/** + * @} + */ + +/** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT +#define __HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT +#define __HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG +#define __HAL_ETH_EXTI_CLEAR_FLAG __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG +#define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER +#define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER +#define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER + +#define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE +#define ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE +#define IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE +/** + * @} + */ + +/** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_LTDC_LAYER LTDC_LAYER +#define __HAL_LTDC_RELOAD_CONFIG __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG +/** + * @} + */ + +/** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose + * @{ + */ +#define SAI_OUTPUTDRIVE_DISABLED SAI_OUTPUTDRIVE_DISABLE +#define SAI_OUTPUTDRIVE_ENABLED SAI_OUTPUTDRIVE_ENABLE +#define SAI_MASTERDIVIDER_ENABLED SAI_MASTERDIVIDER_ENABLE +#define SAI_MASTERDIVIDER_DISABLED SAI_MASTERDIVIDER_DISABLE +#define SAI_STREOMODE SAI_STEREOMODE +#define SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY +#define SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL +#define SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL +#define SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL +#define SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL +#define SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL +#define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE +#define SAI_SYNCHRONOUS_EXT SAI_SYNCHRONOUS_EXT_SAI1 +#define SAI_SYNCEXT_IN_ENABLE SAI_SYNCEXT_OUTBLOCKA_ENABLE +/** + * @} + */ + +/** @defgroup HAL_SPDIFRX_Aliased_Macros HAL SPDIFRX Aliased Macros maintained for legacy purpose + * @{ + */ +#if defined(STM32H7) +#define HAL_SPDIFRX_ReceiveControlFlow HAL_SPDIFRX_ReceiveCtrlFlow +#define HAL_SPDIFRX_ReceiveControlFlow_IT HAL_SPDIFRX_ReceiveCtrlFlow_IT +#define HAL_SPDIFRX_ReceiveControlFlow_DMA HAL_SPDIFRX_ReceiveCtrlFlow_DMA +#endif +/** + * @} + */ + +/** @defgroup HAL_HRTIM_Aliased_Functions HAL HRTIM Aliased Functions maintained for legacy purpose + * @{ + */ +#if defined (STM32H7) || defined (STM32G4) || defined (STM32F3) +#define HAL_HRTIM_WaveformCounterStart_IT HAL_HRTIM_WaveformCountStart_IT +#define HAL_HRTIM_WaveformCounterStart_DMA HAL_HRTIM_WaveformCountStart_DMA +#define HAL_HRTIM_WaveformCounterStart HAL_HRTIM_WaveformCountStart +#define HAL_HRTIM_WaveformCounterStop_IT HAL_HRTIM_WaveformCountStop_IT +#define HAL_HRTIM_WaveformCounterStop_DMA HAL_HRTIM_WaveformCountStop_DMA +#define HAL_HRTIM_WaveformCounterStop HAL_HRTIM_WaveformCountStop +#endif +/** + * @} + */ + +/** @defgroup HAL_QSPI_Aliased_Macros HAL QSPI Aliased Macros maintained for legacy purpose + * @{ + */ +#if defined (STM32L4) || defined (STM32F4) || defined (STM32F7) || defined(STM32H7) +#define HAL_QPSI_TIMEOUT_DEFAULT_VALUE HAL_QSPI_TIMEOUT_DEFAULT_VALUE +#endif /* STM32L4 || STM32F4 || STM32F7 */ +/** + * @} + */ + +/** @defgroup HAL_Generic_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose + * @{ + */ +#if defined (STM32F7) +#define ART_ACCLERATOR_ENABLE ART_ACCELERATOR_ENABLE +#endif /* STM32F7 */ +/** + * @} + */ + +/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose + * @{ + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32_HAL_LEGACY */ + + diff --git a/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h b/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h new file mode 100644 index 0000000..d6e2028 --- /dev/null +++ b/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h @@ -0,0 +1,860 @@ +/** + ****************************************************************************** + * @file stm32wlxx_hal.h + * @author MCD Application Team + * @brief This file contains all the functions prototypes for the HAL + * module driver. + ****************************************************************************** + * @attention + * + * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32WLxx_HAL_H +#define __STM32WLxx_HAL_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wlxx_hal_conf.h" +#include "stm32wlxx_ll_system.h" + +/** @addtogroup STM32WLxx_HAL_Driver + * @{ + */ + +/** @defgroup HAL HAL + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup HAL_Exported_Structures HAL Exported Structures + * @{ + */ + +/** @defgroup HAL_TICK_FREQ Tick Frequency + * @{ + */ +typedef enum +{ + HAL_TICK_FREQ_10HZ = 100U, + HAL_TICK_FREQ_100HZ = 10U, + HAL_TICK_FREQ_1KHZ = 1U, + HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ +} HAL_TickFreqTypeDef; + +/** + * @} + */ + +#if defined(DUAL_CORE) +/** @defgroup HAL_SYSCFG_IM HAL SYSCFG Interrupt Mask + * @{ + */ +/** + * @brief SYSCFG Interrupt Mask structure definition + */ +typedef struct +{ + uint32_t InterruptMask1; /*!< The SYSCFG Interrupt Mask to be configured. + This parameter can be a combination of @ref SYSCFG_IM_GRP1 */ + uint32_t InterruptMask2; /*!< The SYSCFG Interrupt Mask to be configured. + This parameter can be a combination of @ref SYSCFG_IM_GRP2 */ +} SYSCFG_InterruptTypeDef; + +/** + * @} + */ +#endif /* DUAL_CORE */ + +#if defined(STM32WL5Mxx) +/** @defgroup HAL_RADIO_SWITCH_CONFIG RADIO Switch Config + * @{ + */ +typedef enum +{ + RADIO_SWITCH_OFF = 0, + RADIO_SWITCH_RX = 1, + RADIO_SWITCH_RFO_LP = 2, + RADIO_SWITCH_RFO_HP = 3, +} HAL_RADIO_SwitchConfig_TypeDef; + +typedef enum +{ + RADIO_RFO_LP_MAXPOWER = 0, + RADIO_RFO_HP_MAXPOWER, +} HAL_RADIO_RFOMaxPowerConfig_TypeDef; + +/** + * @} + */ +#endif /* STM32WL5Mxx */ + +/** + * @} + */ + + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup HAL_Exported_Constants HAL Exported Constants + * @{ + */ + +/** @defgroup SYSCFG_Exported_Constants SYSCFG Exported Constants + * @{ + */ + +/** @defgroup SYSCFG_BootMode BOOT Mode + * @{ + */ +#define SYSCFG_BOOT_MAINFLASH LL_SYSCFG_REMAP_FLASH /*!< Main Flash memory mapped at 0x00000000 */ +#define SYSCFG_BOOT_SYSTEMFLASH LL_SYSCFG_REMAP_SYSTEMFLASH /*!< System Flash memory mapped at 0x00000000 */ +#define SYSCFG_BOOT_SRAM LL_SYSCFG_REMAP_SRAM /*!< SRAM1 mapped at 0x00000000 */ +/** + * @} + */ + +/** @defgroup SYSCFG_SRAM2WRP SRAM2 Page Write protection (0 to 31) + * @{ + */ +#define SYSCFG_SRAM2WRP_PAGE0 LL_SYSCFG_SRAM2WRP_PAGE0 /*!< SRAM2 Write protection page 0 */ +#define SYSCFG_SRAM2WRP_PAGE1 LL_SYSCFG_SRAM2WRP_PAGE1 /*!< SRAM2 Write protection page 1 */ +#define SYSCFG_SRAM2WRP_PAGE2 LL_SYSCFG_SRAM2WRP_PAGE2 /*!< SRAM2 Write protection page 2 */ +#define SYSCFG_SRAM2WRP_PAGE3 LL_SYSCFG_SRAM2WRP_PAGE3 /*!< SRAM2 Write protection page 3 */ +#define SYSCFG_SRAM2WRP_PAGE4 LL_SYSCFG_SRAM2WRP_PAGE4 /*!< SRAM2 Write protection page 4 */ +#define SYSCFG_SRAM2WRP_PAGE5 LL_SYSCFG_SRAM2WRP_PAGE5 /*!< SRAM2 Write protection page 5 */ +#define SYSCFG_SRAM2WRP_PAGE6 LL_SYSCFG_SRAM2WRP_PAGE6 /*!< SRAM2 Write protection page 6 */ +#define SYSCFG_SRAM2WRP_PAGE7 LL_SYSCFG_SRAM2WRP_PAGE7 /*!< SRAM2 Write protection page 7 */ +#define SYSCFG_SRAM2WRP_PAGE8 LL_SYSCFG_SRAM2WRP_PAGE8 /*!< SRAM2 Write protection page 8 */ +#define SYSCFG_SRAM2WRP_PAGE9 LL_SYSCFG_SRAM2WRP_PAGE9 /*!< SRAM2 Write protection page 9 */ +#define SYSCFG_SRAM2WRP_PAGE10 LL_SYSCFG_SRAM2WRP_PAGE10 /*!< SRAM2 Write protection page 10 */ +#define SYSCFG_SRAM2WRP_PAGE11 LL_SYSCFG_SRAM2WRP_PAGE11 /*!< SRAM2 Write protection page 11 */ +#define SYSCFG_SRAM2WRP_PAGE12 LL_SYSCFG_SRAM2WRP_PAGE12 /*!< SRAM2 Write protection page 12 */ +#define SYSCFG_SRAM2WRP_PAGE13 LL_SYSCFG_SRAM2WRP_PAGE13 /*!< SRAM2 Write protection page 13 */ +#define SYSCFG_SRAM2WRP_PAGE14 LL_SYSCFG_SRAM2WRP_PAGE14 /*!< SRAM2 Write protection page 14 */ +#define SYSCFG_SRAM2WRP_PAGE15 LL_SYSCFG_SRAM2WRP_PAGE15 /*!< SRAM2 Write protection page 15 */ +#define SYSCFG_SRAM2WRP_PAGE16 LL_SYSCFG_SRAM2WRP_PAGE16 /*!< SRAM2 Write protection page 16 */ +#define SYSCFG_SRAM2WRP_PAGE17 LL_SYSCFG_SRAM2WRP_PAGE17 /*!< SRAM2 Write protection page 17 */ +#define SYSCFG_SRAM2WRP_PAGE18 LL_SYSCFG_SRAM2WRP_PAGE18 /*!< SRAM2 Write protection page 18 */ +#define SYSCFG_SRAM2WRP_PAGE19 LL_SYSCFG_SRAM2WRP_PAGE19 /*!< SRAM2 Write protection page 19 */ +#define SYSCFG_SRAM2WRP_PAGE20 LL_SYSCFG_SRAM2WRP_PAGE20 /*!< SRAM2 Write protection page 20 */ +#define SYSCFG_SRAM2WRP_PAGE21 LL_SYSCFG_SRAM2WRP_PAGE21 /*!< SRAM2 Write protection page 21 */ +#define SYSCFG_SRAM2WRP_PAGE22 LL_SYSCFG_SRAM2WRP_PAGE22 /*!< SRAM2 Write protection page 22 */ +#define SYSCFG_SRAM2WRP_PAGE23 LL_SYSCFG_SRAM2WRP_PAGE23 /*!< SRAM2 Write protection page 23 */ +#define SYSCFG_SRAM2WRP_PAGE24 LL_SYSCFG_SRAM2WRP_PAGE24 /*!< SRAM2 Write protection page 24 */ +#define SYSCFG_SRAM2WRP_PAGE25 LL_SYSCFG_SRAM2WRP_PAGE25 /*!< SRAM2 Write protection page 25 */ +#define SYSCFG_SRAM2WRP_PAGE26 LL_SYSCFG_SRAM2WRP_PAGE26 /*!< SRAM2 Write protection page 26 */ +#define SYSCFG_SRAM2WRP_PAGE27 LL_SYSCFG_SRAM2WRP_PAGE27 /*!< SRAM2 Write protection page 27 */ +#define SYSCFG_SRAM2WRP_PAGE28 LL_SYSCFG_SRAM2WRP_PAGE28 /*!< SRAM2 Write protection page 28 */ +#define SYSCFG_SRAM2WRP_PAGE29 LL_SYSCFG_SRAM2WRP_PAGE29 /*!< SRAM2 Write protection page 29 */ +#define SYSCFG_SRAM2WRP_PAGE30 LL_SYSCFG_SRAM2WRP_PAGE30 /*!< SRAM2 Write protection page 30 */ +#define SYSCFG_SRAM2WRP_PAGE31 LL_SYSCFG_SRAM2WRP_PAGE31 /*!< SRAM2 Write protection page 31 */ + +/** + * @} + */ + +#if defined(VREFBUF) +/** @defgroup SYSCFG_VREFBUF_VoltageScale VREFBUF Voltage Scale + * @{ + */ +#define SYSCFG_VREFBUF_VOLTAGE_SCALE0 LL_VREFBUF_VOLTAGE_SCALE0 /*!< Voltage reference scale 0 (VREF_OUT1) */ +#define SYSCFG_VREFBUF_VOLTAGE_SCALE1 LL_VREFBUF_VOLTAGE_SCALE1 /*!< Voltage reference scale 1 (VREF_OUT2) */ + +/** + * @} + */ + +/** @defgroup SYSCFG_VREFBUF_HighImpedance VREFBUF High Impedance + * @{ + */ +#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE 0x00000000U /*!< VREF_plus pin is internally connected to Voltage reference buffer output */ +#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_CSR_HIZ /*!< VREF_plus pin is high impedance */ + +/** + * @} + */ +#endif /* VREFBUF */ + +/** @defgroup SYSCFG_SRAM_flags_definition SRAM Flags + * @{ + */ + +#define SYSCFG_FLAG_SRAM2_PE SYSCFG_CFGR2_SPF /*!< SRAM2 parity error */ +#define SYSCFG_FLAG_SRAM_BUSY SYSCFG_SCSR_SRAMBSY /*!< SRAM1 or SRAM2 erase operation is ongoing */ +#define SYSCFG_FLAG_PKASRAM_BUSY SYSCFG_SCSR_PKASRAMBSY /*!< PKA SRAM busy by erase operation */ +/** + * @} + */ + +/** @defgroup SYSCFG_FastModePlus_GPIO Fast-mode Plus on GPIO + * @{ + */ + +/** @brief Fast-mode Plus driving capability on a specific GPIO + */ +#define SYSCFG_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP /*!< Enable Fast-mode Plus on PB6 */ +#define SYSCFG_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP /*!< Enable Fast-mode Plus on PB7 */ +#define SYSCFG_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP /*!< Enable Fast-mode Plus on PB8 */ +#define SYSCFG_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /*!< Enable Fast-mode Plus on PB9 */ + +/** + * @} + */ + +#if defined(DUAL_CORE) +/** @defgroup SYSCFG_IM_GRP1 SYSCFG INTERRUPT MASK GROUP1 + * @{ + */ + +#define HAL_SYSCFG_GRP1_RESERVED 0x00U /*!< Define user to differentiate Group1 to Group 2 */ + +#if defined(CORE_CM0PLUS) +/** @brief Interrupt mask related to CPU2 NVIC + */ +#define HAL_SYSCFG_GRP1_RTCSTAMP_RTCTAMP_LSECSS (LL_C2_SYSCFG_GRP1_RTCSTAMP_RTCTAMP_LSECSS | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from RTC TimeStamp, RTC Tampers + and LSE Clock Security System to CPU2 */ +#define HAL_SYSCFG_GRP1_RTCALARM (LL_C2_SYSCFG_GRP1_RTCALARM | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from RTC Alarms to CPU2 */ +#define HAL_SYSCFG_GRP1_RTCSSRU (LL_C2_SYSCFG_GRP1_RTCSSRU | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from RTC SSRU to CPU2 */ +#define HAL_SYSCFG_GRP1_RTCWKUP (LL_C2_SYSCFG_GRP1_RTCWKUP | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from RTC Wakeup to CPU2 */ +#define HAL_SYSCFG_GRP1_RCC (LL_C2_SYSCFG_GRP1_RCC | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from RCC to CPU2 */ +#define HAL_SYSCFG_GRP1_FLASH (LL_C2_SYSCFG_GRP1_FLASH | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from FLASH to CPU2 */ +#define HAL_SYSCFG_GRP1_PKA (LL_C2_SYSCFG_GRP1_PKA | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from PKA to CPU2 */ +#define HAL_SYSCFG_GRP1_AES (LL_C2_SYSCFG_GRP1_AES | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from AES to CPU2 */ +#define HAL_SYSCFG_GRP1_COMP (LL_C2_SYSCFG_GRP1_COMP | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from Comparator to CPU2 */ +#define HAL_SYSCFG_GRP1_ADC (LL_C2_SYSCFG_GRP1_ADC | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from Analog Digital Converter to CPU2 */ +#define HAL_SYSCFG_GRP1_DAC (LL_C2_SYSCFG_GRP1_DAC | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from Digital Analog Converter to CPU2 */ + +#define HAL_SYSCFG_GRP1_EXTI0 (LL_C2_SYSCFG_GRP1_EXTI0 | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from External Interrupt Line 0 to CPU2 */ +#define HAL_SYSCFG_GRP1_EXTI1 (LL_C2_SYSCFG_GRP1_EXTI1 | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from External Interrupt Line 1 to CPU2 */ +#define HAL_SYSCFG_GRP1_EXTI2 (LL_C2_SYSCFG_GRP1_EXTI2 | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from External Interrupt Line 2 to CPU2 */ +#define HAL_SYSCFG_GRP1_EXTI3 (LL_C2_SYSCFG_GRP1_EXTI3 | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from External Interrupt Line 3 to CPU2 */ +#define HAL_SYSCFG_GRP1_EXTI4 (LL_C2_SYSCFG_GRP1_EXTI4 | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from External Interrupt Line 4 to CPU2 */ +#define HAL_SYSCFG_GRP1_EXTI5 (LL_C2_SYSCFG_GRP1_EXTI5 | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from External Interrupt Line 5 to CPU2 */ +#define HAL_SYSCFG_GRP1_EXTI6 (LL_C2_SYSCFG_GRP1_EXTI6 | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from External Interrupt Line 6 to CPU2 */ +#define HAL_SYSCFG_GRP1_EXTI7 (LL_C2_SYSCFG_GRP1_EXTI7 | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from External Interrupt Line 7 to CPU2 */ +#define HAL_SYSCFG_GRP1_EXTI8 (LL_C2_SYSCFG_GRP1_EXTI8 | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from External Interrupt Line 8 to CPU2 */ +#define HAL_SYSCFG_GRP1_EXTI9 (LL_C2_SYSCFG_GRP1_EXTI9 | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from External Interrupt Line 9 to CPU2 */ +#define HAL_SYSCFG_GRP1_EXTI10 (LL_C2_SYSCFG_GRP1_EXTI10 | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from External Interrupt Line 10 to CPU2 */ +#define HAL_SYSCFG_GRP1_EXTI11 (LL_C2_SYSCFG_GRP1_EXTI11 | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from External Interrupt Line 11 to CPU2 */ +#define HAL_SYSCFG_GRP1_EXTI12 (LL_C2_SYSCFG_GRP1_EXTI12 | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from External Interrupt Line 12 to CPU2 */ +#define HAL_SYSCFG_GRP1_EXTI13 (LL_C2_SYSCFG_GRP1_EXTI13 | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from External Interrupt Line 13 to CPU2 */ +#define HAL_SYSCFG_GRP1_EXTI14 (LL_C2_SYSCFG_GRP1_EXTI14 | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from External Interrupt Line 14 to CPU2 */ +#define HAL_SYSCFG_GRP1_EXTI15 (LL_C2_SYSCFG_GRP1_EXTI15 | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from External Interrupt Line 15 to CPU2 */ + +#else + +/** @brief Interrupt mask related to CPU1 NVIC + */ +#define HAL_SYSCFG_GRP1_RTCSTAMPTAMPLSECSS (LL_SYSCFG_GRP1_RTCSTAMPTAMPLSECSS | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from RTCSTAMPTAMPLSECSS to CPU1 */ +#define HAL_SYSCFG_GRP1_RTCSSRU (LL_SYSCFG_GRP1_RTCSSRU | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from RTC SSRU to CPU1 */ +#define HAL_SYSCFG_GRP1_EXTI5 (LL_SYSCFG_GRP1_EXTI5 | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from External Interrupt Line 5 to CPU1 */ +#define HAL_SYSCFG_GRP1_EXTI6 (LL_SYSCFG_GRP1_EXTI6 | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from External Interrupt Line 6 to CPU1 */ +#define HAL_SYSCFG_GRP1_EXTI7 (LL_SYSCFG_GRP1_EXTI7 | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from External Interrupt Line 7 to CPU1 */ +#define HAL_SYSCFG_GRP1_EXTI8 (LL_SYSCFG_GRP1_EXTI8 | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from External Interrupt Line 8 to CPU1 */ +#define HAL_SYSCFG_GRP1_EXTI9 (LL_SYSCFG_GRP1_EXTI9 | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from External Interrupt Line 9 to CPU1 */ +#define HAL_SYSCFG_GRP1_EXTI10 (LL_SYSCFG_GRP1_EXTI10 | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from External Interrupt Line 10 to CPU1 */ +#define HAL_SYSCFG_GRP1_EXTI11 (LL_SYSCFG_GRP1_EXTI11 | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from External Interrupt Line 11 to CPU1 */ +#define HAL_SYSCFG_GRP1_EXTI12 (LL_SYSCFG_GRP1_EXTI12 | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from External Interrupt Line 12 to CPU1 */ +#define HAL_SYSCFG_GRP1_EXTI13 (LL_SYSCFG_GRP1_EXTI13 | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from External Interrupt Line 13 to CPU1 */ +#define HAL_SYSCFG_GRP1_EXTI14 (LL_SYSCFG_GRP1_EXTI14 | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from External Interrupt Line 14 to CPU1 */ +#define HAL_SYSCFG_GRP1_EXTI15 (LL_SYSCFG_GRP1_EXTI15 | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from External Interrupt Line 15 to CPU1 */ + +#endif + +/** + * @} + */ + +/** @defgroup SYSCFG_IM_GRP2 SYSCFG INTERRUPT MASK GROUP2 + * @{ + */ + +#define HAL_SYSCFG_GRP2_RESERVED 0x80U /*!< Define user to differentiate Group1 to Group 2 */ + +#if defined(CORE_CM0PLUS) +/** @brief Interrupt mask related to CPU2 NVIC + */ +#define HAL_SYSCFG_GRP2_DMA1CH1 (LL_C2_SYSCFG_GRP2_DMA1CH1 | HAL_SYSCFG_GRP2_RESERVED) /*!< Enabling of interrupt from DMA1 Channel 1 to CPU2 */ +#define HAL_SYSCFG_GRP2_DMA1CH2 (LL_C2_SYSCFG_GRP2_DMA1CH2 | HAL_SYSCFG_GRP2_RESERVED) /*!< Enabling of interrupt from DMA1 Channel 2 to CPU2 */ +#define HAL_SYSCFG_GRP2_DMA1CH3 (LL_C2_SYSCFG_GRP2_DMA1CH3 | HAL_SYSCFG_GRP2_RESERVED) /*!< Enabling of interrupt from DMA1 Channel 3 to CPU2 */ +#define HAL_SYSCFG_GRP2_DMA1CH4 (LL_C2_SYSCFG_GRP2_DMA1CH4 | HAL_SYSCFG_GRP2_RESERVED) /*!< Enabling of interrupt from DMA1 Channel 4 to CPU2 */ +#define HAL_SYSCFG_GRP2_DMA1CH5 (LL_C2_SYSCFG_GRP2_DMA1CH5 | HAL_SYSCFG_GRP2_RESERVED) /*!< Enabling of interrupt from DMA1 Channel 5 to CPU2 */ +#define HAL_SYSCFG_GRP2_DMA1CH6 (LL_C2_SYSCFG_GRP2_DMA1CH6 | HAL_SYSCFG_GRP2_RESERVED) /*!< Enabling of interrupt from DMA1 Channel 6 to CPU2 */ +#define HAL_SYSCFG_GRP2_DMA1CH7 (LL_C2_SYSCFG_GRP2_DMA1CH7 | HAL_SYSCFG_GRP2_RESERVED) /*!< Enabling of interrupt from DMA1 Channel 7 to CPU2 */ + +#define HAL_SYSCFG_GRP2_DMA2CH1 (LL_C2_SYSCFG_GRP2_DMA2CH1 | HAL_SYSCFG_GRP2_RESERVED) /*!< Enabling of interrupt from DMA2 Channel 1 to CPU2 */ +#define HAL_SYSCFG_GRP2_DMA2CH2 (LL_C2_SYSCFG_GRP2_DMA2CH2 | HAL_SYSCFG_GRP2_RESERVED) /*!< Enabling of interrupt from DMA2 Channel 2 to CPU2 */ +#define HAL_SYSCFG_GRP2_DMA2CH3 (LL_C2_SYSCFG_GRP2_DMA2CH3 | HAL_SYSCFG_GRP2_RESERVED) /*!< Enabling of interrupt from DMA2 Channel 3 to CPU2 */ +#define HAL_SYSCFG_GRP2_DMA2CH4 (LL_C2_SYSCFG_GRP2_DMA2CH4 | HAL_SYSCFG_GRP2_RESERVED) /*!< Enabling of interrupt from DMA2 Channel 4 to CPU2 */ +#define HAL_SYSCFG_GRP2_DMA2CH5 (LL_C2_SYSCFG_GRP2_DMA2CH5 | HAL_SYSCFG_GRP2_RESERVED) /*!< Enabling of interrupt from DMA2 Channel 5 to CPU2 */ +#define HAL_SYSCFG_GRP2_DMA2CH6 (LL_C2_SYSCFG_GRP2_DMA2CH6 | HAL_SYSCFG_GRP2_RESERVED) /*!< Enabling of interrupt from DMA2 Channel 6 to CPU2 */ +#define HAL_SYSCFG_GRP2_DMA2CH7 (LL_C2_SYSCFG_GRP2_DMA2CH7 | HAL_SYSCFG_GRP2_RESERVED) /*!< Enabling of interrupt from DMA2 Channel 7 to CPU2 */ + +#define HAL_SYSCFG_GRP2_DMAMUX1 (LL_C2_SYSCFG_GRP2_DMAMUX1 | HAL_SYSCFG_GRP2_RESERVED) /*!< Enabling of interrupt from DMAMUX1 to CPU2 */ + +#define HAL_SYSCFG_GRP2_PVM3 (LL_C2_SYSCFG_GRP2_PVM3 | HAL_SYSCFG_GRP2_RESERVED) /*!< Enabling of interrupt from Power Voltage Monitoring 3 to CPU2 */ +#define HAL_SYSCFG_GRP2_PVD (LL_C2_SYSCFG_GRP2_PVD | HAL_SYSCFG_GRP2_RESERVED) /*!< Enabling of interrupt from Power Voltage Detector to CPU2 */ + +#else + +/** @brief Interrupt mask related to CPU1 NVIC + */ +#define HAL_SYSCFG_GRP2_PVM3 (LL_SYSCFG_GRP2_PVM3 | HAL_SYSCFG_GRP2_RESERVED) /*!< Enabling of interrupt from Power Voltage Monitoring 3 to CPU1 */ +#define HAL_SYSCFG_GRP2_PVD (LL_SYSCFG_GRP2_PVD | HAL_SYSCFG_GRP2_RESERVED) /*!< Enabling of interrupt from Power Voltage Detector to CPU1 */ + +#endif +/** + * @} + */ +#endif /* DUAL_CORE */ + +#if defined(STM32WL5Mxx) +/** @defgroup RADIO_Exported_Constants RADIO Exported Constants + * @{ + */ +#define RADIO_CONF_TCXO_NOT_SUPPORTED 0U +#define RADIO_CONF_TCXO_SUPPORTED 1U + +#define RADIO_CONF_DCDC_NOT_SUPPORTED 0U +#define RADIO_CONF_DCDC_SUPPORTED 1U + +#define RADIO_CONF_RFO_HP_MAX_22_dBm ((int32_t) 22) +#define RADIO_CONF_RFO_HP_MAX_20_dBm ((int32_t) 20) +#define RADIO_CONF_RFO_HP_MAX_17_dBm ((int32_t) 17) +#define RADIO_CONF_RFO_HP_MAX_14_dBm ((int32_t) 14) +#define RADIO_CONF_RFO_LP_MAX_15_dBm ((int32_t) 15) +#define RADIO_CONF_RFO_LP_MAX_14_dBm ((int32_t) 14) +#define RADIO_CONF_RFO_LP_MAX_10_dBm ((int32_t) 10) + +/** + * @} + */ +#endif /* STM32WL5Mxx */ + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup HAL_Exported_Macros HAL Exported Macros + * @{ + */ + +/** @defgroup DBGMCU_Exported_Macros DBGMCU Exported Macros + * @{ + */ + +/** @brief Freeze and Unfreeze Peripherals in Debug mode + */ + +/** @defgroup DBGMCU_APBx_GRPx_STOP_IP DBGMCU CPU1 APBx GRPx STOP IP + * @{ + */ +#if defined(LL_DBGMCU_APB1_GRP1_TIM2_STOP) +#define __HAL_DBGMCU_FREEZE_TIM2() LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_TIM2_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM2() LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_APB1_GRP1_TIM2_STOP) +#endif + +#if defined(LL_DBGMCU_APB1_GRP1_RTC_STOP) +#define __HAL_DBGMCU_FREEZE_RTC() LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_RTC_STOP) +#define __HAL_DBGMCU_UNFREEZE_RTC() LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_APB1_GRP1_RTC_STOP) +#endif + +#if defined(LL_DBGMCU_APB1_GRP1_WWDG_STOP) +#define __HAL_DBGMCU_FREEZE_WWDG() LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_WWDG_STOP) +#define __HAL_DBGMCU_UNFREEZE_WWDG() LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_APB1_GRP1_WWDG_STOP) +#endif + +#if defined(LL_DBGMCU_APB1_GRP1_IWDG_STOP) +#define __HAL_DBGMCU_FREEZE_IWDG() LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_IWDG_STOP) +#define __HAL_DBGMCU_UNFREEZE_IWDG() LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_APB1_GRP1_IWDG_STOP) +#endif + +#if defined(LL_DBGMCU_APB1_GRP1_I2C1_STOP) +#define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_I2C1_STOP) +#define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_APB1_GRP1_I2C1_STOP) +#endif + +#if defined(LL_DBGMCU_APB1_GRP1_I2C2_STOP) +#define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_I2C2_STOP) +#define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_APB1_GRP1_I2C2_STOP) +#endif + +#if defined(LL_DBGMCU_APB1_GRP1_I2C3_STOP) +#define __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT() LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_I2C3_STOP) +#define __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT() LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_APB1_GRP1_I2C3_STOP) +#endif + +#if defined(LL_DBGMCU_APB1_GRP1_LPTIM1_STOP) +#define __HAL_DBGMCU_FREEZE_LPTIM1() LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_LPTIM1_STOP) +#define __HAL_DBGMCU_UNFREEZE_LPTIM1() LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_APB1_GRP1_LPTIM1_STOP) +#endif + +#if defined(LL_DBGMCU_APB1_GRP2_LPTIM2_STOP) +#define __HAL_DBGMCU_FREEZE_LPTIM2() LL_DBGMCU_APB1_GRP2_FreezePeriph(LL_DBGMCU_APB1_GRP2_LPTIM2_STOP) +#define __HAL_DBGMCU_UNFREEZE_LPTIM2() LL_DBGMCU_APB1_GRP2_UnFreezePeriph(LL_DBGMCU_APB1_GRP2_LPTIM2_STOP) +#endif + +#if defined(LL_DBGMCU_APB1_GRP2_LPTIM3_STOP) +#define __HAL_DBGMCU_FREEZE_LPTIM3() LL_DBGMCU_APB1_GRP2_FreezePeriph(LL_DBGMCU_APB1_GRP2_LPTIM3_STOP) +#define __HAL_DBGMCU_UNFREEZE_LPTIM3() LL_DBGMCU_APB1_GRP2_UnFreezePeriph(LL_DBGMCU_APB1_GRP2_LPTIM3_STOP) +#endif + +#if defined(LL_DBGMCU_APB2_GRP1_TIM1_STOP) +#define __HAL_DBGMCU_FREEZE_TIM1() LL_DBGMCU_APB2_GRP1_FreezePeriph(LL_DBGMCU_APB2_GRP1_TIM1_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM1() LL_DBGMCU_APB2_GRP1_UnFreezePeriph(LL_DBGMCU_APB2_GRP1_TIM1_STOP) +#endif + +#if defined(LL_DBGMCU_APB2_GRP1_TIM16_STOP) +#define __HAL_DBGMCU_FREEZE_TIM16() LL_DBGMCU_APB2_GRP1_FreezePeriph(LL_DBGMCU_APB2_GRP1_TIM16_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM16() LL_DBGMCU_APB2_GRP1_UnFreezePeriph(LL_DBGMCU_APB2_GRP1_TIM16_STOP) +#endif + +#if defined(LL_DBGMCU_APB2_GRP1_TIM17_STOP) +#define __HAL_DBGMCU_FREEZE_TIM17() LL_DBGMCU_APB2_GRP1_FreezePeriph(LL_DBGMCU_APB2_GRP1_TIM17_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM17() LL_DBGMCU_APB2_GRP1_UnFreezePeriph(LL_DBGMCU_APB2_GRP1_TIM17_STOP) +#endif + +/** + * @} + */ + +/** @defgroup DBGMCU_C2_APBx_GRPx_STOP_IP DBGMCU CPU2 APBx GRPx STOP IP + * @{ + */ +#if defined(LL_C2_DBGMCU_APB1_GRP1_TIM2_STOP) +#define __HAL_C2_DBGMCU_FREEZE_TIM2() LL_C2_DBGMCU_APB1_GRP1_FreezePeriph(LL_C2_DBGMCU_APB1_GRP1_TIM2_STOP) +#define __HAL_C2_DBGMCU_UNFREEZE_TIM2() LL_C2_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB1_GRP1_TIM2_STOP) +#endif + +#if defined(LL_C2_DBGMCU_APB1_GRP1_RTC_STOP) +#define __HAL_C2_DBGMCU_FREEZE_RTC() LL_C2_DBGMCU_APB1_GRP1_FreezePeriph(LL_C2_DBGMCU_APB1_GRP1_RTC_STOP) +#define __HAL_C2_DBGMCU_UNFREEZE_RTC() LL_C2_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB1_GRP1_RTC_STOP) +#endif + +#if defined(LL_C2_DBGMCU_APB1_GRP1_IWDG_STOP) +#define __HAL_C2_DBGMCU_FREEZE_IWDG() LL_C2_DBGMCU_APB1_GRP1_FreezePeriph(LL_C2_DBGMCU_APB1_GRP1_IWDG_STOP) +#define __HAL_C2_DBGMCU_UNFREEZE_IWDG() LL_C2_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB1_GRP1_IWDG_STOP) +#endif + +#if defined(LL_C2_DBGMCU_APB1_GRP1_I2C1_STOP) +#define __HAL_C2_DBGMCU_FREEZE_I2C1_TIMEOUT() LL_C2_DBGMCU_APB1_GRP1_FreezePeriph(LL_C2_DBGMCU_APB1_GRP1_I2C1_STOP) +#define __HAL_C2_DBGMCU_UNFREEZE_I2C1_TIMEOUT() LL_C2_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB1_GRP1_I2C1_STOP) +#endif + +#if defined(LL_C2_DBGMCU_APB1_GRP1_I2C2_STOP) +#define __HAL_C2_DBGMCU_FREEZE_I2C2_TIMEOUT() LL_C2_DBGMCU_APB1_GRP1_FreezePeriph(LL_C2_DBGMCU_APB1_GRP1_I2C2_STOP) +#define __HAL_C2_DBGMCU_UNFREEZE_I2C2_TIMEOUT() LL_C2_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB1_GRP1_I2C2_STOP) +#endif + +#if defined(LL_C2_DBGMCU_APB1_GRP1_I2C3_STOP) +#define __HAL_C2_DBGMCU_FREEZE_I2C3_TIMEOUT() LL_C2_DBGMCU_APB1_GRP1_FreezePeriph(LL_C2_DBGMCU_APB1_GRP1_I2C3_STOP) +#define __HAL_C2_DBGMCU_UNFREEZE_I2C3_TIMEOUT() LL_C2_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB1_GRP1_I2C3_STOP) +#endif + +#if defined(LL_C2_DBGMCU_APB1_GRP1_LPTIM1_STOP) +#define __HAL_C2_DBGMCU_FREEZE_LPTIM1() LL_C2_DBGMCU_APB1_GRP1_FreezePeriph(LL_C2_DBGMCU_APB1_GRP1_LPTIM1_STOP) +#define __HAL_C2_DBGMCU_UNFREEZE_LPTIM1() LL_C2_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB1_GRP1_LPTIM1_STOP) +#endif + +#if defined(LL_C2_DBGMCU_APB1_GRP2_LPTIM2_STOP) +#define __HAL_C2_DBGMCU_FREEZE_LPTIM2() LL_C2_DBGMCU_APB1_GRP2_FreezePeriph(LL_C2_DBGMCU_APB1_GRP2_LPTIM2_STOP) +#define __HAL_C2_DBGMCU_UNFREEZE_LPTIM2() LL_C2_DBGMCU_APB1_GRP2_UnFreezePeriph(LL_C2_DBGMCU_APB1_GRP2_LPTIM2_STOP) +#endif + +#if defined(LL_C2_DBGMCU_APB1_GRP2_LPTIM3_STOP) +#define __HAL_C2_DBGMCU_FREEZE_LPTIM3() LL_C2_DBGMCU_APB1_GRP2_FreezePeriph(LL_C2_DBGMCU_APB1_GRP2_LPTIM3_STOP) +#define __HAL_C2_DBGMCU_UNFREEZE_LPTIM3() LL_C2_DBGMCU_APB1_GRP2_UnFreezePeriph(LL_C2_DBGMCU_APB1_GRP2_LPTIM3_STOP) +#endif + +#if defined(LL_C2_DBGMCU_APB2_GRP1_TIM1_STOP) +#define __HAL_C2_DBGMCU_FREEZE_TIM1() LL_C2_DBGMCU_APB2_GRP1_FreezePeriph(LL_C2_DBGMCU_APB2_GRP1_TIM1_STOP) +#define __HAL_C2_DBGMCU_UNFREEZE_TIM1() LL_C2_DBGMCU_APB2_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB2_GRP1_TIM1_STOP) +#endif + +#if defined(LL_C2_DBGMCU_APB2_GRP1_TIM16_STOP) +#define __HAL_C2_DBGMCU_FREEZE_TIM16() LL_C2_DBGMCU_APB2_GRP1_FreezePeriph(LL_C2_DBGMCU_APB2_GRP1_TIM16_STOP) +#define __HAL_C2_DBGMCU_UNFREEZE_TIM16() LL_C2_DBGMCU_APB2_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB2_GRP1_TIM16_STOP) +#endif + +#if defined(LL_C2_DBGMCU_APB2_GRP1_TIM17_STOP) +#define __HAL_C2_DBGMCU_FREEZE_TIM17() LL_C2_DBGMCU_APB2_GRP1_FreezePeriph(LL_C2_DBGMCU_APB2_GRP1_TIM17_STOP) +#define __HAL_C2_DBGMCU_UNFREEZE_TIM17() LL_C2_DBGMCU_APB2_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB2_GRP1_TIM17_STOP) +#endif + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup SYSCFG_Exported_Macros SYSCFG Exported Macros + * @{ + */ + +/** @brief Main Flash memory mapped at 0x00000000 + */ +#define __HAL_SYSCFG_REMAPMEMORY_FLASH() LL_SYSCFG_SetRemapMemory(LL_SYSCFG_REMAP_FLASH) + +/** @brief System Flash memory mapped at 0x00000000 + */ +#define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() LL_SYSCFG_SetRemapMemory(LL_SYSCFG_REMAP_SYSTEMFLASH) + +/** @brief Embedded SRAM mapped at 0x00000000 + */ +#define __HAL_SYSCFG_REMAPMEMORY_SRAM() LL_SYSCFG_SetRemapMemory(LL_SYSCFG_REMAP_SRAM) + +/** + * @brief Return the boot mode as configured by user. + * @retval The boot mode as configured by user. The returned value can be one + * of the following values: + * @arg @ref SYSCFG_BOOT_MAINFLASH + * @arg @ref SYSCFG_BOOT_SYSTEMFLASH + * @arg @ref SYSCFG_BOOT_SRAM + */ +#define __HAL_SYSCFG_GET_BOOT_MODE() LL_SYSCFG_GetRemapMemory() + +/** @brief SRAM2 page 0 to 31 write protection enable macro + * @param __SRAM2WRP__ This parameter can be a combination of values of @ref SYSCFG_SRAM2WRP + * @note Write protection can only be disabled by a system reset + */ +/* Legacy define */ +#define __HAL_SYSCFG_SRAM2_WRP_1_31_ENABLE __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE +#define __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE(__SRAM2WRP__) do { assert_param(IS_SYSCFG_SRAM2WRP_PAGE((__SRAM2WRP__)));\ + LL_SYSCFG_EnableSRAM2PageWRP_0_31(__SRAM2WRP__); \ + } while(0) + +/** @brief SRAM2 page write protection unlock prior to erase + * @note Writing a wrong key reactivates the write protection + */ +#define __HAL_SYSCFG_SRAM2_WRP_UNLOCK() LL_SYSCFG_UnlockSRAM2WRP() + +/** @brief SRAM2 erase + * @note __SYSCFG_GET_FLAG(SYSCFG_FLAG_SRAM_BUSY) may be used to check end of erase + */ +#define __HAL_SYSCFG_SRAM2_ERASE() LL_SYSCFG_EnableSRAM2Erase() + +/** @brief SYSCFG Break ECC lock. + * Enable and lock the connection of Flash ECC error connection to TIM1/16/17 Break input. + * @note The selected configuration is locked and can be unlocked only by system reset. + */ +#define __HAL_SYSCFG_BREAK_ECC_LOCK() LL_SYSCFG_SetTIMBreakInputs(LL_SYSCFG_TIMBREAK_ECC) + +/** @brief SYSCFG Break Cortex-M4 Lockup lock. + * Enable and lock the connection of Cortex-M4 LOCKUP (Hardfault) output to TIM1/16/17 Break input. + * @note The selected configuration is locked and can be unlocked only by system reset. + */ +#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() LL_SYSCFG_SetTIMBreakInputs(LL_SYSCFG_TIMBREAK_LOCKUP) + +/** @brief SYSCFG Break PVD lock. + * Enable and lock the PVD connection to Timer1/16/17 Break input, as well as the PVDE and PLS[2:0] in the PWR_CR2 register. + * @note The selected configuration is locked and can be unlocked only by system reset. + */ +#define __HAL_SYSCFG_BREAK_PVD_LOCK() LL_SYSCFG_SetTIMBreakInputs(LL_SYSCFG_TIMBREAK_PVD) + +/** @brief SYSCFG Break SRAM2 parity lock. + * Enable and lock the SRAM2 parity error signal connection to TIM1/16/17 Break input. + * @note The selected configuration is locked and can be unlocked by system reset. + */ +#define __HAL_SYSCFG_BREAK_SRAM2PARITY_LOCK() LL_SYSCFG_SetTIMBreakInputs(LL_SYSCFG_TIMBREAK_SRAM2_PARITY) + +/** @brief Check SYSCFG flag is set or not. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg @ref SYSCFG_FLAG_SRAM2_PE SRAM2 Parity Error Flag + * @arg @ref SYSCFG_FLAG_SRAM_BUSY SRAM2 Erase Ongoing + * @arg @ref SYSCFG_FLAG_PKASRAM_BUSY PKA SRAM Erase Ongoing + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_SYSCFG_GET_FLAG(__FLAG__) ((((((__FLAG__) == SYSCFG_FLAG_SRAM2_PE)? SYSCFG->CFGR2 : SYSCFG->SCSR) &\ + (__FLAG__))!= 0) ? 1 : 0) + +/** @brief Set the SPF bit to clear the SRAM Parity Error Flag. + */ +#define __HAL_SYSCFG_CLEAR_FLAG() LL_SYSCFG_ClearFlag_SP() + +/** @brief Fast mode Plus driving capability enable/disable macros + * @param __FASTMODEPLUS__ This parameter can be a value of @ref SYSCFG_FastModePlus_GPIO + */ +#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) do { assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__))); \ + LL_SYSCFG_EnableFastModePlus(__FASTMODEPLUS__); \ + } while(0) + +#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do { assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__))); \ + LL_SYSCFG_DisableFastModePlus(__FASTMODEPLUS__); \ + } while(0) + +/** + * @} + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup HAL_Private_Macros HAL Private Macros + * @{ + */ + +/** @defgroup SYSCFG_Private_Macros SYSCFG Private Macros + * @{ + */ + +#define IS_SYSCFG_SRAM2WRP_PAGE(__PAGE__) (((__PAGE__) > 0U) && ((__PAGE__) <= 0xFFFFFFFFU)) + +#define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(__SCALE__) (((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE0) || \ + ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE1)) + +#define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(__VALUE__) (((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE) || \ + ((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE)) + +#define IS_SYSCFG_VREFBUF_TRIMMING(__VALUE__) (((__VALUE__) > 0U) && ((__VALUE__) <= VREFBUF_CCR_TRIM)) + +#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \ + (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \ + (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \ + (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9)) + + +#if defined(DUAL_CORE) +#if defined(CORE_CM0PLUS) +#define IS_SYSCFG_IM_GRP1(__VALUE__) ((((__VALUE__) & 0x80U) == HAL_SYSCFG_GRP1_RESERVED) && \ + ((((__VALUE__) & HAL_SYSCFG_GRP1_RTCSTAMP_RTCTAMP_LSECSS) == HAL_SYSCFG_GRP1_RTCSTAMP_RTCTAMP_LSECSS) || \ + (((__VALUE__) & HAL_SYSCFG_GRP1_RTCALARM ) == HAL_SYSCFG_GRP1_RTCALARM ) || \ + (((__VALUE__) & HAL_SYSCFG_GRP1_RTCSSRU ) == HAL_SYSCFG_GRP1_RTCSSRU ) || \ + (((__VALUE__) & HAL_SYSCFG_GRP1_RTCWKUP ) == HAL_SYSCFG_GRP1_RTCWKUP ) || \ + (((__VALUE__) & HAL_SYSCFG_GRP1_RCC ) == HAL_SYSCFG_GRP1_RCC ) || \ + (((__VALUE__) & HAL_SYSCFG_GRP1_FLASH ) == HAL_SYSCFG_GRP1_FLASH ) || \ + (((__VALUE__) & HAL_SYSCFG_GRP1_PKA ) == HAL_SYSCFG_GRP1_PKA ) || \ + (((__VALUE__) & HAL_SYSCFG_GRP1_AES ) == HAL_SYSCFG_GRP1_AES ) || \ + (((__VALUE__) & HAL_SYSCFG_GRP1_COMP ) == HAL_SYSCFG_GRP1_COMP ) || \ + (((__VALUE__) & HAL_SYSCFG_GRP1_ADC ) == HAL_SYSCFG_GRP1_ADC ) || \ + (((__VALUE__) & HAL_SYSCFG_GRP1_DAC ) == HAL_SYSCFG_GRP1_DAC ) || \ + (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI0 ) == HAL_SYSCFG_GRP1_EXTI0 ) || \ + (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI1 ) == HAL_SYSCFG_GRP1_EXTI1 ) || \ + (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI2 ) == HAL_SYSCFG_GRP1_EXTI2 ) || \ + (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI3 ) == HAL_SYSCFG_GRP1_EXTI3 ) || \ + (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI4 ) == HAL_SYSCFG_GRP1_EXTI4 ) || \ + (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI5 ) == HAL_SYSCFG_GRP1_EXTI5 ) || \ + (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI6 ) == HAL_SYSCFG_GRP1_EXTI6 ) || \ + (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI7 ) == HAL_SYSCFG_GRP1_EXTI7 ) || \ + (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI8 ) == HAL_SYSCFG_GRP1_EXTI8 ) || \ + (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI9 ) == HAL_SYSCFG_GRP1_EXTI9 ) || \ + (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI10 ) == HAL_SYSCFG_GRP1_EXTI10 ) || \ + (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI11 ) == HAL_SYSCFG_GRP1_EXTI11 ) || \ + (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI12 ) == HAL_SYSCFG_GRP1_EXTI12 ) || \ + (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI13 ) == HAL_SYSCFG_GRP1_EXTI13 ) || \ + (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI14 ) == HAL_SYSCFG_GRP1_EXTI14 ) || \ + (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI15 ) == HAL_SYSCFG_GRP1_EXTI15 ))) + +#define IS_SYSCFG_IM_GRP2(__VALUE__) ((((__VALUE__) & 0x80U) == HAL_SYSCFG_GRP2_RESERVED) && \ + ((((__VALUE__) & HAL_SYSCFG_GRP2_DMA1CH1) == HAL_SYSCFG_GRP2_DMA1CH1) || \ + (((__VALUE__) & HAL_SYSCFG_GRP2_DMA1CH2) == HAL_SYSCFG_GRP2_DMA1CH2) || \ + (((__VALUE__) & HAL_SYSCFG_GRP2_DMA1CH3) == HAL_SYSCFG_GRP2_DMA1CH3) || \ + (((__VALUE__) & HAL_SYSCFG_GRP2_DMA1CH4) == HAL_SYSCFG_GRP2_DMA1CH4) || \ + (((__VALUE__) & HAL_SYSCFG_GRP2_DMA1CH5) == HAL_SYSCFG_GRP2_DMA1CH5) || \ + (((__VALUE__) & HAL_SYSCFG_GRP2_DMA1CH6) == HAL_SYSCFG_GRP2_DMA1CH6) || \ + (((__VALUE__) & HAL_SYSCFG_GRP2_DMA1CH7) == HAL_SYSCFG_GRP2_DMA1CH7) || \ + (((__VALUE__) & HAL_SYSCFG_GRP2_DMA2CH1) == HAL_SYSCFG_GRP2_DMA2CH1) || \ + (((__VALUE__) & HAL_SYSCFG_GRP2_DMA2CH2) == HAL_SYSCFG_GRP2_DMA2CH2) || \ + (((__VALUE__) & HAL_SYSCFG_GRP2_DMA2CH3) == HAL_SYSCFG_GRP2_DMA2CH3) || \ + (((__VALUE__) & HAL_SYSCFG_GRP2_DMA2CH4) == HAL_SYSCFG_GRP2_DMA2CH4) || \ + (((__VALUE__) & HAL_SYSCFG_GRP2_DMA2CH5) == HAL_SYSCFG_GRP2_DMA2CH5) || \ + (((__VALUE__) & HAL_SYSCFG_GRP2_DMA2CH6) == HAL_SYSCFG_GRP2_DMA2CH6) || \ + (((__VALUE__) & HAL_SYSCFG_GRP2_DMA2CH7) == HAL_SYSCFG_GRP2_DMA2CH7) || \ + (((__VALUE__) & HAL_SYSCFG_GRP2_DMAMUX1) == HAL_SYSCFG_GRP2_DMAMUX1) || \ + (((__VALUE__) & HAL_SYSCFG_GRP2_PVM3 ) == HAL_SYSCFG_GRP2_PVM3 ) || \ + (((__VALUE__) & HAL_SYSCFG_GRP2_PVD ) == HAL_SYSCFG_GRP2_PVD ))) + +#else /* !CORE_CM0PLUS */ + +#define IS_SYSCFG_IM_GRP1(__VALUE__) ((((__VALUE__) & 0x80U) == HAL_SYSCFG_GRP1_RESERVED) && \ + ((((__VALUE__) & HAL_SYSCFG_GRP1_RTCSTAMPTAMPLSECSS) == HAL_SYSCFG_GRP1_RTCSTAMPTAMPLSECSS) || \ + (((__VALUE__) & HAL_SYSCFG_GRP1_RTCSSRU ) == HAL_SYSCFG_GRP1_RTCSSRU ) || \ + (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI5 ) == HAL_SYSCFG_GRP1_EXTI5 ) || \ + (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI6 ) == HAL_SYSCFG_GRP1_EXTI6 ) || \ + (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI7 ) == HAL_SYSCFG_GRP1_EXTI7 ) || \ + (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI8 ) == HAL_SYSCFG_GRP1_EXTI8 ) || \ + (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI9 ) == HAL_SYSCFG_GRP1_EXTI9 ) || \ + (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI10 ) == HAL_SYSCFG_GRP1_EXTI10 ) || \ + (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI11 ) == HAL_SYSCFG_GRP1_EXTI11 ) || \ + (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI12 ) == HAL_SYSCFG_GRP1_EXTI12 ) || \ + (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI13 ) == HAL_SYSCFG_GRP1_EXTI13 ) || \ + (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI14 ) == HAL_SYSCFG_GRP1_EXTI14 ) || \ + (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI15 ) == HAL_SYSCFG_GRP1_EXTI15 ))) + +#define IS_SYSCFG_IM_GRP2(__VALUE__) ((((__VALUE__) & 0x80U) == HAL_SYSCFG_GRP2_RESERVED) && \ + ((((__VALUE__) & HAL_SYSCFG_GRP2_PVM3) == HAL_SYSCFG_GRP2_PVM3) || \ + (((__VALUE__) & HAL_SYSCFG_GRP2_PVD ) == HAL_SYSCFG_GRP2_PVD ))) + +#endif /* CORE_CM0PLUS */ +#endif /* DUAL_CORE */ + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup HAL_Private_Macros HAL Private Macros + * @{ + */ +#define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || \ + ((FREQ) == HAL_TICK_FREQ_100HZ) || \ + ((FREQ) == HAL_TICK_FREQ_1KHZ)) +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup HAL_Exported_Functions HAL Exported Functions + * @{ + */ + +/** @defgroup HAL_Exported_Functions_Group1 HAL Initialization and Configuration functions + * @{ + */ + +/* Initialization and Configuration functions ******************************/ +HAL_StatusTypeDef HAL_Init(void); +HAL_StatusTypeDef HAL_DeInit(void); +void HAL_MspInit(void); +void HAL_MspDeInit(void); + +HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority); + +/** + * @} + */ + +/* Exported variables ---------------------------------------------------------*/ +/** @addtogroup HAL_Exported_Variables + * @{ + */ +extern __IO uint32_t uwTick; +extern uint32_t uwTickPrio; +extern HAL_TickFreqTypeDef uwTickFreq; +/** + * @} + */ + +/** @defgroup HAL_Exported_Functions_Group2 HAL Control functions + * @{ + */ + +/* Peripheral Control functions ************************************************/ +void HAL_IncTick(void); +void HAL_Delay(uint32_t Delay); +uint32_t HAL_GetTick(void); +uint32_t HAL_GetTickPrio(void); +HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq); +HAL_TickFreqTypeDef HAL_GetTickFreq(void); +void HAL_SuspendTick(void); +void HAL_ResumeTick(void); +uint32_t HAL_GetHalVersion(void); +uint32_t HAL_GetREVID(void); +uint32_t HAL_GetDEVID(void); +uint32_t HAL_GetUIDw0(void); +uint32_t HAL_GetUIDw1(void); +uint32_t HAL_GetUIDw2(void); + +/** + * @} + */ + +/** @defgroup HAL_Exported_Functions_Group3 HAL Debug functions + * @{ + */ + +/* DBGMCU Peripheral Control functions *****************************************/ +void HAL_DBGMCU_EnableDBGSleepMode(void); +void HAL_DBGMCU_DisableDBGSleepMode(void); +void HAL_DBGMCU_EnableDBGStopMode(void); +void HAL_DBGMCU_DisableDBGStopMode(void); +void HAL_DBGMCU_EnableDBGStandbyMode(void); +void HAL_DBGMCU_DisableDBGStandbyMode(void); +/** + * @} + */ + +/** @addtogroup HAL_Exported_Functions_Group4 HAL System Configuration functions + * @{ + */ + +/* SYSCFG Control functions ****************************************************/ +void HAL_SYSCFG_SRAM2Erase(void); + +void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling); +void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode); +void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue); +HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void); +void HAL_SYSCFG_DisableVREFBUF(void); + +void HAL_SYSCFG_EnableIOAnalogSwitchBooster(void); +void HAL_SYSCFG_DisableIOAnalogSwitchBooster(void); + +#if defined(DUAL_CORE) +void HAL_SYSCFG_EnableIT(const SYSCFG_InterruptTypeDef *Interrupt); +void HAL_SYSCFG_DisableIT(const SYSCFG_InterruptTypeDef *Interrupt); +#endif +/** + * @} + */ + +#if defined( STM32WL5Mxx) +/** @addtogroup HAL_Exported_Functions_Group5 HAL Radio Configuration functions + * @{ + */ + +/* RADIO Control functions ****************************************************/ +HAL_StatusTypeDef HAL_RADIO_Init(void); +HAL_StatusTypeDef HAL_RADIO_DeInit(void); +HAL_StatusTypeDef HAL_RADIO_SetSwitchConfig(HAL_RADIO_SwitchConfig_TypeDef Config); +uint8_t HAL_RADIO_IsTCXO(void); +uint8_t HAL_RADIO_IsDCDC(void); +int32_t HAL_RADIO_GetRFOMaxPowerConfig(HAL_RADIO_RFOMaxPowerConfig_TypeDef Config); + +/** + * @} + */ +#endif /* STM32WL5Mxx */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __STM32WLxx_HAL_H */ diff --git a/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h b/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h new file mode 100644 index 0000000..8dacda6 --- /dev/null +++ b/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h @@ -0,0 +1,472 @@ +/** + ****************************************************************************** + * @file stm32wlxx_hal_cortex.h + * @author MCD Application Team + * @brief Header file of CORTEX HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32WLxx_HAL_CORTEX_H +#define __STM32WLxx_HAL_CORTEX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wlxx_hal_def.h" + +/** @addtogroup STM32WLxx_HAL_Driver + * @{ + */ + +/** @defgroup CORTEX CORTEX + * @brief CORTEX HAL module driver + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup CORTEX_Exported_Types CORTEX Exported Types + * @{ + */ + +#if (__MPU_PRESENT == 1) +/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition + * @brief MPU Region initialization structure + * @{ + */ +typedef struct +{ + uint8_t Enable; /*!< Specifies the status of the region. + This parameter can be a value of @ref CORTEX_MPU_Region_Enable */ + uint8_t Number; /*!< Specifies the number of the region to protect. + This parameter can be a value of @ref CORTEX_MPU_Region_Number */ + uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. + */ + uint8_t Size; /*!< Specifies the size of the region to protect. + This parameter can be a value of @ref CORTEX_MPU_Region_Size */ + uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ +#ifdef CORE_CM0PLUS +#else + uint8_t TypeExtField; /*!< Specifies the TEX field level. + This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */ +#endif /* CORE_CM0PLUS */ + + uint8_t AccessPermission; /*!< Specifies the region access permission type. + This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */ + uint8_t DisableExec; /*!< Specifies the instruction access status. + This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */ + uint8_t IsShareable; /*!< Specifies the shareability status of the protected region. + This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */ + uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected. + This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */ + uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region. + This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */ +} MPU_Region_InitTypeDef; +/** + * @} + */ +#endif /* __MPU_PRESENT */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants + * @{ + */ +#ifdef CORE_CM0PLUS +#else +/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group + * @{ + */ +#define NVIC_PRIORITYGROUP_0 (0x00000007U) /*!< 0 bit for pre-emption priority, + 4 bits for subpriority */ +#define NVIC_PRIORITYGROUP_1 (0x00000006U) /*!< 1 bit for pre-emption priority, + 3 bits for subpriority */ +#define NVIC_PRIORITYGROUP_2 (0x00000005U) /*!< 2 bits for pre-emption priority, + 2 bits for subpriority */ +#define NVIC_PRIORITYGROUP_3 (0x00000004U) /*!< 3 bits for pre-emption priority, + 1 bit for subpriority */ +#define NVIC_PRIORITYGROUP_4 (0x00000003U) /*!< 4 bits for pre-emption priority, + 0 bit for subpriority */ +/** + * @} + */ +#endif /* CORE_CM0PLUS */ + +/** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source + * @{ + */ +#define SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U +#define SYSTICK_CLKSOURCE_HCLK 0x00000004U + +/** + * @} + */ + +#if (__MPU_PRESENT == 1) +/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control CORTEX MPU HFNMI and PRIVILEGED Access control + * @{ + */ +#define MPU_HFNMI_PRIVDEF_NONE 0x00000000U +#define MPU_HARDFAULT_NMI (MPU_CTRL_HFNMIENA_Msk) +#define MPU_PRIVILEGED_DEFAULT (MPU_CTRL_PRIVDEFENA_Msk) +#define MPU_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable + * @{ + */ +#define MPU_REGION_ENABLE ((uint8_t)0x01) +#define MPU_REGION_DISABLE ((uint8_t)0x00) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access + * @{ + */ +#define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00) +#define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable + * @{ + */ +#define MPU_ACCESS_SHAREABLE ((uint8_t)0x01) +#define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable + * @{ + */ +#define MPU_ACCESS_CACHEABLE ((uint8_t)0x01) +#define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable + * @{ + */ +#define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01) +#define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_TEX_Levels CORTEX MPU TEX Levels + * @{ + */ +#if defined(CORE_CM0PLUS) +#else +#define MPU_TEX_LEVEL0 ((uint8_t)0x00) +#define MPU_TEX_LEVEL1 ((uint8_t)0x01) +#define MPU_TEX_LEVEL2 ((uint8_t)0x02) +#endif /* CORE_CM0PLUS */ + +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size + * @{ + */ +#if defined(CORE_CM0PLUS) +#else +#define MPU_REGION_SIZE_32B ((uint8_t)0x04) +#define MPU_REGION_SIZE_64B ((uint8_t)0x05) +#define MPU_REGION_SIZE_128B ((uint8_t)0x06) +#endif /* CORE_CM0PLUS */ +#define MPU_REGION_SIZE_256B ((uint8_t)0x07) +#define MPU_REGION_SIZE_512B ((uint8_t)0x08) +#define MPU_REGION_SIZE_1KB ((uint8_t)0x09) +#define MPU_REGION_SIZE_2KB ((uint8_t)0x0A) +#define MPU_REGION_SIZE_4KB ((uint8_t)0x0B) +#define MPU_REGION_SIZE_8KB ((uint8_t)0x0C) +#define MPU_REGION_SIZE_16KB ((uint8_t)0x0D) +#define MPU_REGION_SIZE_32KB ((uint8_t)0x0E) +#define MPU_REGION_SIZE_64KB ((uint8_t)0x0F) +#define MPU_REGION_SIZE_128KB ((uint8_t)0x10) +#define MPU_REGION_SIZE_256KB ((uint8_t)0x11) +#define MPU_REGION_SIZE_512KB ((uint8_t)0x12) +#define MPU_REGION_SIZE_1MB ((uint8_t)0x13) +#define MPU_REGION_SIZE_2MB ((uint8_t)0x14) +#define MPU_REGION_SIZE_4MB ((uint8_t)0x15) +#define MPU_REGION_SIZE_8MB ((uint8_t)0x16) +#define MPU_REGION_SIZE_16MB ((uint8_t)0x17) +#define MPU_REGION_SIZE_32MB ((uint8_t)0x18) +#define MPU_REGION_SIZE_64MB ((uint8_t)0x19) +#define MPU_REGION_SIZE_128MB ((uint8_t)0x1A) +#define MPU_REGION_SIZE_256MB ((uint8_t)0x1B) +#define MPU_REGION_SIZE_512MB ((uint8_t)0x1C) +#define MPU_REGION_SIZE_1GB ((uint8_t)0x1D) +#define MPU_REGION_SIZE_2GB ((uint8_t)0x1E) +#define MPU_REGION_SIZE_4GB ((uint8_t)0x1F) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes + * @{ + */ +#define MPU_REGION_NO_ACCESS ((uint8_t)0x00) +#define MPU_REGION_PRIV_RW ((uint8_t)0x01) +#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02) +#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03) +#define MPU_REGION_PRIV_RO ((uint8_t)0x05) +#define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number + * @{ + */ +#define MPU_REGION_NUMBER0 ((uint8_t)0x00) +#define MPU_REGION_NUMBER1 ((uint8_t)0x01) +#define MPU_REGION_NUMBER2 ((uint8_t)0x02) +#define MPU_REGION_NUMBER3 ((uint8_t)0x03) +#define MPU_REGION_NUMBER4 ((uint8_t)0x04) +#define MPU_REGION_NUMBER5 ((uint8_t)0x05) +#define MPU_REGION_NUMBER6 ((uint8_t)0x06) +#define MPU_REGION_NUMBER7 ((uint8_t)0x07) +/** + * @} + */ +#endif /* __MPU_PRESENT */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup CORTEX_Exported_Macros CORTEX Exported Macros + * @{ + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions + * @{ + */ + +/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and Configuration functions + * @brief Initialization and Configuration functions + * @{ + */ +/* Initialization and Configuration functions *****************************/ +#ifdef CORE_CM0PLUS +#else +void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup); +#endif /* CORE_CM0PLUS */ +void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority); +void HAL_NVIC_EnableIRQ(IRQn_Type IRQn); +void HAL_NVIC_DisableIRQ(IRQn_Type IRQn); +void HAL_NVIC_SystemReset(void); +uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb); +/** + * @} + */ + +/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions + * @brief Cortex control functions + * @{ + */ +/* Peripheral Control functions *************************************************/ +#ifdef CORE_CM0PLUS +uint32_t HAL_NVIC_GetPriority(IRQn_Type IRQn); +#else +void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority); +uint32_t HAL_NVIC_GetPriorityGrouping(void); +uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn); +#endif /* CORE_CM0PLUS */ +uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn); +void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn); +void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn); +void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource); +void HAL_SYSTICK_IRQHandler(void); +void HAL_SYSTICK_Callback(void); + +#if (__MPU_PRESENT == 1U) +void HAL_MPU_Enable(uint32_t MPU_Control); +void HAL_MPU_Disable(void); +void HAL_MPU_EnableRegion(uint32_t RegionNumber); +void HAL_MPU_DisableRegion(uint32_t RegionNumber); +void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init); +#endif /* __MPU_PRESENT */ +/** + * @} + */ + +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @defgroup CORTEX_Private_Macros CORTEX Private Macros + * @{ + */ +#ifdef CORE_CM0PLUS +#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x4U) +#else +#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \ + ((GROUP) == NVIC_PRIORITYGROUP_1) || \ + ((GROUP) == NVIC_PRIORITYGROUP_2) || \ + ((GROUP) == NVIC_PRIORITYGROUP_3) || \ + ((GROUP) == NVIC_PRIORITYGROUP_4)) + +#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U) + +#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U) +#endif /* CORE_CM0PLUS */ + +#define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) > SysTick_IRQn) + +#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \ + ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8)) + +#if (__MPU_PRESENT == 1) +#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \ + ((STATE) == MPU_REGION_DISABLE)) + +#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \ + ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE)) + +#define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \ + ((STATE) == MPU_ACCESS_NOT_SHAREABLE)) + +#define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \ + ((STATE) == MPU_ACCESS_NOT_CACHEABLE)) + +#define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \ + ((STATE) == MPU_ACCESS_NOT_BUFFERABLE)) + +#if defined(CORE_CM0PLUS) +#else +#define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \ + ((TYPE) == MPU_TEX_LEVEL1) || \ + ((TYPE) == MPU_TEX_LEVEL2)) +#endif /* CORE_CM0PLUS */ + +#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \ + ((TYPE) == MPU_REGION_PRIV_RW) || \ + ((TYPE) == MPU_REGION_PRIV_RW_URO) || \ + ((TYPE) == MPU_REGION_FULL_ACCESS) || \ + ((TYPE) == MPU_REGION_PRIV_RO) || \ + ((TYPE) == MPU_REGION_PRIV_RO_URO)) + +#define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \ + ((NUMBER) == MPU_REGION_NUMBER1) || \ + ((NUMBER) == MPU_REGION_NUMBER2) || \ + ((NUMBER) == MPU_REGION_NUMBER3) || \ + ((NUMBER) == MPU_REGION_NUMBER4) || \ + ((NUMBER) == MPU_REGION_NUMBER5) || \ + ((NUMBER) == MPU_REGION_NUMBER6) || \ + ((NUMBER) == MPU_REGION_NUMBER7)) + +#if defined(CORE_CM0PLUS) +#define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_256B) || \ + ((SIZE) == MPU_REGION_SIZE_512B) || \ + ((SIZE) == MPU_REGION_SIZE_1KB) || \ + ((SIZE) == MPU_REGION_SIZE_2KB) || \ + ((SIZE) == MPU_REGION_SIZE_4KB) || \ + ((SIZE) == MPU_REGION_SIZE_8KB) || \ + ((SIZE) == MPU_REGION_SIZE_16KB) || \ + ((SIZE) == MPU_REGION_SIZE_32KB) || \ + ((SIZE) == MPU_REGION_SIZE_64KB) || \ + ((SIZE) == MPU_REGION_SIZE_128KB) || \ + ((SIZE) == MPU_REGION_SIZE_256KB) || \ + ((SIZE) == MPU_REGION_SIZE_512KB) || \ + ((SIZE) == MPU_REGION_SIZE_1MB) || \ + ((SIZE) == MPU_REGION_SIZE_2MB) || \ + ((SIZE) == MPU_REGION_SIZE_4MB) || \ + ((SIZE) == MPU_REGION_SIZE_8MB) || \ + ((SIZE) == MPU_REGION_SIZE_16MB) || \ + ((SIZE) == MPU_REGION_SIZE_32MB) || \ + ((SIZE) == MPU_REGION_SIZE_64MB) || \ + ((SIZE) == MPU_REGION_SIZE_128MB) || \ + ((SIZE) == MPU_REGION_SIZE_256MB) || \ + ((SIZE) == MPU_REGION_SIZE_512MB) || \ + ((SIZE) == MPU_REGION_SIZE_1GB) || \ + ((SIZE) == MPU_REGION_SIZE_2GB) || \ + ((SIZE) == MPU_REGION_SIZE_4GB)) +#else +#define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_32B) || \ + ((SIZE) == MPU_REGION_SIZE_64B) || \ + ((SIZE) == MPU_REGION_SIZE_128B) || \ + ((SIZE) == MPU_REGION_SIZE_256B) || \ + ((SIZE) == MPU_REGION_SIZE_512B) || \ + ((SIZE) == MPU_REGION_SIZE_1KB) || \ + ((SIZE) == MPU_REGION_SIZE_2KB) || \ + ((SIZE) == MPU_REGION_SIZE_4KB) || \ + ((SIZE) == MPU_REGION_SIZE_8KB) || \ + ((SIZE) == MPU_REGION_SIZE_16KB) || \ + ((SIZE) == MPU_REGION_SIZE_32KB) || \ + ((SIZE) == MPU_REGION_SIZE_64KB) || \ + ((SIZE) == MPU_REGION_SIZE_128KB) || \ + ((SIZE) == MPU_REGION_SIZE_256KB) || \ + ((SIZE) == MPU_REGION_SIZE_512KB) || \ + ((SIZE) == MPU_REGION_SIZE_1MB) || \ + ((SIZE) == MPU_REGION_SIZE_2MB) || \ + ((SIZE) == MPU_REGION_SIZE_4MB) || \ + ((SIZE) == MPU_REGION_SIZE_8MB) || \ + ((SIZE) == MPU_REGION_SIZE_16MB) || \ + ((SIZE) == MPU_REGION_SIZE_32MB) || \ + ((SIZE) == MPU_REGION_SIZE_64MB) || \ + ((SIZE) == MPU_REGION_SIZE_128MB) || \ + ((SIZE) == MPU_REGION_SIZE_256MB) || \ + ((SIZE) == MPU_REGION_SIZE_512MB) || \ + ((SIZE) == MPU_REGION_SIZE_1GB) || \ + ((SIZE) == MPU_REGION_SIZE_2GB) || \ + ((SIZE) == MPU_REGION_SIZE_4GB)) +#endif /* CORE_CM0PLUS */ +#define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FFU) +#endif /* __MPU_PRESENT */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32WLxx_HAL_CORTEX_H */ diff --git a/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h b/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h new file mode 100644 index 0000000..5d09387 --- /dev/null +++ b/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h @@ -0,0 +1,211 @@ +/** + ****************************************************************************** + * @file stm32wlxx_hal_def.h + * @author MCD Application Team + * @brief This file contains HAL common defines, enumeration, macros and + * structures definitions. + ****************************************************************************** + * @attention + * + * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32WLxx_HAL_DEF +#define __STM32WLxx_HAL_DEF + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wlxx.h" +#include "Legacy/stm32_hal_legacy.h" /* Aliases file for old names compatibility */ +#include + +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief HAL Status structures definition + */ +typedef enum +{ + HAL_OK = 0x00, + HAL_ERROR = 0x01, + HAL_BUSY = 0x02, + HAL_TIMEOUT = 0x03 +} HAL_StatusTypeDef; + +/** + * @brief HAL Lock structures definition + */ +typedef enum +{ + HAL_UNLOCKED = 0x00, + HAL_LOCKED = 0x01 +} HAL_LockTypeDef; + +/* Exported macros -----------------------------------------------------------*/ + +#if !defined(UNUSED) +#define UNUSED(X) (void)X /* To avoid gcc/g++ warnings */ +#endif /* UNUSED */ + +#define HAL_MAX_DELAY 0xFFFFFFFFU + +#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) == (BIT)) +#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == 0U) + +#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \ + do{ \ + (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \ + (__DMA_HANDLE__).Parent = (__HANDLE__); \ + } while(0) + +/** @brief Reset the Handle's State field. + * @param __HANDLE__ specifies the Peripheral Handle. + * @note This macro can be used for the following purpose: + * - When the Handle is declared as local variable; before passing it as parameter + * to HAL_PPP_Init() for the first time, it is mandatory to use this macro + * to set to 0 the Handle's "State" field. + * Otherwise, "State" field may have any random value and the first time the function + * HAL_PPP_Init() is called, the low level hardware initialization will be missed + * (i.e. HAL_PPP_MspInit() will not be executed). + * - When there is a need to reconfigure the low level hardware: instead of calling + * HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init(). + * In this later function, when the Handle's "State" field is set to 0, it will execute the function + * HAL_PPP_MspInit() which will reconfigure the low level hardware. + * @retval None + */ +#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0) + +#if (USE_RTOS == 1) +/* Reserved for future use */ +#error " USE_RTOS should be 0 in the current HAL release " +#else +#define __HAL_LOCK(__HANDLE__) \ + do { \ + if ((__HANDLE__)->Lock == HAL_LOCKED) \ + { \ + return HAL_BUSY; \ + } \ + else \ + { \ + (__HANDLE__)->Lock = HAL_LOCKED; \ + } \ + } while (0) + +#define __HAL_UNLOCK(__HANDLE__) \ + do{ \ + (__HANDLE__)->Lock = HAL_UNLOCKED; \ + }while (0) +#endif /* USE_RTOS */ + + +#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */ +#ifndef __weak +#define __weak __attribute__((weak)) +#endif +#ifndef __packed +#define __packed __attribute__((packed)) +#endif +#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ +#ifndef __weak +#define __weak __attribute__((weak)) +#endif /* __weak */ +#ifndef __packed +#define __packed __attribute__((__packed__)) +#endif /* __packed */ +#endif /* __GNUC__ */ + + +/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */ +#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */ +#ifndef __ALIGN_BEGIN +#define __ALIGN_BEGIN +#endif +#ifndef __ALIGN_END +#define __ALIGN_END __attribute__ ((aligned (4))) +#endif +#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ +#ifndef __ALIGN_END +#define __ALIGN_END __attribute__ ((aligned (4))) +#endif /* __ALIGN_END */ +#ifndef __ALIGN_BEGIN +#define __ALIGN_BEGIN +#endif /* __ALIGN_BEGIN */ +#else +#ifndef __ALIGN_END +#define __ALIGN_END +#endif /* __ALIGN_END */ +#ifndef __ALIGN_BEGIN +#if defined (__CC_ARM) /* ARM Compiler V5 */ +#define __ALIGN_BEGIN __align(4) +#elif defined (__ICCARM__) /* IAR Compiler */ +#define __ALIGN_BEGIN +#endif /* __CC_ARM */ +#endif /* __ALIGN_BEGIN */ +#endif /* __GNUC__ */ + +/** + * @brief __RAM_FUNC definition + */ +#if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) +/* ARM Compiler V4/V5 and V6 + -------------------------- + RAM functions are defined using the toolchain options. + Functions that are executed in RAM should reside in a separate source module. + Using the 'Options for File' dialog you can simply change the 'Code / Const' + area of a module to a memory space in physical RAM. + Available memory areas are declared in the 'Target' tab of the 'Options for Target' + dialog. +*/ +#define __RAM_FUNC + +#elif defined ( __ICCARM__ ) +/* ICCARM Compiler + --------------- + RAM functions are defined using a specific toolchain keyword "__ramfunc". +*/ +#define __RAM_FUNC __ramfunc + +#elif defined ( __GNUC__ ) +/* GNU Compiler + ------------ + RAM functions are defined using a specific toolchain attribute + "__attribute__((section(".RamFunc")))". +*/ +#define __RAM_FUNC __attribute__((section(".RamFunc"))) + +#endif + +/** + * @brief __NOINLINE definition + */ +#if defined (__CC_ARM) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || defined ( __GNUC__ ) +/* ARM V4/V5 and V6 & GNU Compiler + ------------------------------- +*/ +#define __NOINLINE __attribute__ ( (noinline) ) + +#elif defined ( __ICCARM__ ) +/* ICCARM Compiler + --------------- +*/ +#define __NOINLINE _Pragma("optimize = no_inline") + +#endif + + +#ifdef __cplusplus +} +#endif + +#endif /* ___STM32WLxx_HAL_DEF */ diff --git a/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h b/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h new file mode 100644 index 0000000..ea98d8f --- /dev/null +++ b/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h @@ -0,0 +1,688 @@ +/** + ****************************************************************************** + * @file stm32wlxx_hal_dma.h + * @author MCD Application Team + * @brief Header file of DMA HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32WLxx_HAL_DMA_H +#define STM32WLxx_HAL_DMA_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wlxx_hal_def.h" +#include "stm32wlxx_ll_dma.h" + +/** @addtogroup STM32WLxx_HAL_Driver + * @{ + */ + +/** @addtogroup DMA + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup DMA_Exported_Types DMA Exported Types + * @{ + */ + +/** + * @brief DMA Configuration Structure definition + */ +typedef struct +{ + uint32_t Request; /*!< Specifies the request selected for the specified channel. + This parameter can be a value of @ref DMA_request */ + + uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, + from memory to memory or from peripheral to memory. + This parameter can be a value of @ref DMA_Data_transfer_direction */ + + uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not. + This parameter can be a value of @ref DMA_Peripheral_incremented_mode */ + + uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not. + This parameter can be a value of @ref DMA_Memory_incremented_mode */ + + uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width. + This parameter can be a value of @ref DMA_Peripheral_data_size */ + + uint32_t MemDataAlignment; /*!< Specifies the Memory data width. + This parameter can be a value of @ref DMA_Memory_data_size */ + + uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx. + This parameter can be a value of @ref DMA_mode + @note The circular buffer mode cannot be used if the memory-to-memory + data transfer is configured on the selected Channel */ + + uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx. + This parameter can be a value of @ref DMA_Priority_level */ +} DMA_InitTypeDef; + +/** + * @brief HAL DMA State structures definition + */ +typedef enum +{ + HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */ + HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */ + HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */ + HAL_DMA_STATE_TIMEOUT = 0x03U, /*!< DMA timeout state */ +} HAL_DMA_StateTypeDef; + +/** + * @brief HAL DMA Error Code structure definition + */ +typedef enum +{ + HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */ + HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */ +} HAL_DMA_LevelCompleteTypeDef; + +/** + * @brief HAL DMA Callback ID structure definition + */ +typedef enum +{ + HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */ + HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half transfer */ + HAL_DMA_XFER_ERROR_CB_ID = 0x02U, /*!< Error */ + HAL_DMA_XFER_ABORT_CB_ID = 0x03U, /*!< Abort */ + HAL_DMA_XFER_ALL_CB_ID = 0x04U /*!< All */ + +} HAL_DMA_CallbackIDTypeDef; + +/** + * @brief DMA handle Structure definition + */ +typedef struct __DMA_HandleTypeDef +{ + DMA_Channel_TypeDef *Instance; /*!< Register base address */ + + DMA_InitTypeDef Init; /*!< DMA communication parameters */ + + HAL_LockTypeDef Lock; /*!< DMA locking object */ + + __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ + + void *Parent; /*!< Parent object state */ + + void (* XferCpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer complete callback */ + + void (* XferHalfCpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA Half transfer complete callback */ + + void (* XferErrorCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer error callback */ + + void (* XferAbortCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer abort callback */ + + __IO uint32_t ErrorCode; /*!< DMA Error code */ + + DMA_TypeDef *DmaBaseAddress; /*!< DMA Channel Base Address */ + + uint32_t ChannelIndex; /*!< DMA Channel Index */ + + DMAMUX_Channel_TypeDef *DMAmuxChannel; /*!< Register base address */ + + DMAMUX_ChannelStatus_TypeDef *DMAmuxChannelStatus; /*!< DMAMUX Channels Status Base Address */ + + uint32_t DMAmuxChannelStatusMask; /*!< DMAMUX Channel Status Mask */ + + DMAMUX_RequestGen_TypeDef *DMAmuxRequestGen; /*!< DMAMUX request generator Base Address */ + + DMAMUX_RequestGenStatus_TypeDef *DMAmuxRequestGenStatus; /*!< DMAMUX request generator Address */ + + uint32_t DMAmuxRequestGenStatusMask; /*!< DMAMUX request generator Status mask */ +} DMA_HandleTypeDef; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup DMA_Exported_Constants DMA Exported Constants + * @{ + */ + +/** @defgroup DMA_Error_Code DMA Error Code + * @{ + */ +#define HAL_DMA_ERROR_NONE 0x00000000U /*!< No error */ +#define HAL_DMA_ERROR_TE 0x00000001U /*!< Transfer error */ +#define HAL_DMA_ERROR_NO_XFER 0x00000004U /*!< Abort requested with no Xfer ongoing */ +#define HAL_DMA_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */ +#define HAL_DMA_ERROR_PARAM 0x00000040U /*!< Parameter error */ +#define HAL_DMA_ERROR_BUSY 0x00000080U /*!< DMA Busy error */ +#define HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U /*!< Not supported mode */ +#define HAL_DMA_ERROR_SYNC 0x00000200U /*!< DMAMUX sync overrun error */ +#define HAL_DMA_ERROR_REQGEN 0x00000400U /*!< DMAMUX request generator overrun error */ + +/** + * @} + */ + +/** @defgroup DMA_request DMA request + * @{ + */ +#define DMA_REQUEST_MEM2MEM LL_DMAMUX_REQ_MEM2MEM /*!< memory to memory transfer */ +#define DMA_REQUEST_GENERATOR0 LL_DMAMUX_REQ_GENERATOR0 /*!< DMAMUX request generator 0 */ +#define DMA_REQUEST_GENERATOR1 LL_DMAMUX_REQ_GENERATOR1 /*!< DMAMUX request generator 1 */ +#define DMA_REQUEST_GENERATOR2 LL_DMAMUX_REQ_GENERATOR2 /*!< DMAMUX request generator 2 */ +#define DMA_REQUEST_GENERATOR3 LL_DMAMUX_REQ_GENERATOR3 /*!< DMAMUX request generator 3 */ +#define DMA_REQUEST_ADC LL_DMAMUX_REQ_ADC /*!< DMAMUX ADC request */ +#define DMA_REQUEST_DAC_OUT1 LL_DMAMUX_REQ_DAC_OUT1 /*!< DMAMUX DAC OUT request */ +#define DMA_REQUEST_SPI1_RX LL_DMAMUX_REQ_SPI1_RX /*!< DMAMUX SPI1 RX request */ +#define DMA_REQUEST_SPI1_TX LL_DMAMUX_REQ_SPI1_TX /*!< DMAMUX SPI1 TX request */ +#define DMA_REQUEST_SPI2_RX LL_DMAMUX_REQ_SPI2_RX /*!< DMAMUX SPI2 RX request */ +#define DMA_REQUEST_SPI2_TX LL_DMAMUX_REQ_SPI2_TX /*!< DMAMUX SPI2 TX request */ +#define DMA_REQUEST_I2C1_RX LL_DMAMUX_REQ_I2C1_RX /*!< DMAMUX I2C1 RX request */ +#define DMA_REQUEST_I2C1_TX LL_DMAMUX_REQ_I2C1_TX /*!< DMAMUX I2C1 TX request */ +#define DMA_REQUEST_I2C2_RX LL_DMAMUX_REQ_I2C2_RX /*!< DMAMUX I2C2 RX request */ +#define DMA_REQUEST_I2C2_TX LL_DMAMUX_REQ_I2C2_TX /*!< DMAMUX I2C2 TX request */ +#define DMA_REQUEST_I2C3_RX LL_DMAMUX_REQ_I2C3_RX /*!< DMAMUX I2C3 RX request */ +#define DMA_REQUEST_I2C3_TX LL_DMAMUX_REQ_I2C3_TX /*!< DMAMUX I2C3 TX request */ +#define DMA_REQUEST_USART1_RX LL_DMAMUX_REQ_USART1_RX /*!< DMAMUX USART1 RX request */ +#define DMA_REQUEST_USART1_TX LL_DMAMUX_REQ_USART1_TX /*!< DMAMUX USART1 TX request */ +#define DMA_REQUEST_USART2_RX LL_DMAMUX_REQ_USART2_RX /*!< DMAMUX USART2 RX request */ +#define DMA_REQUEST_USART2_TX LL_DMAMUX_REQ_USART2_TX /*!< DMAMUX USART2 TX request */ +#define DMA_REQUEST_LPUART1_RX LL_DMAMUX_REQ_LPUART1_RX /*!< DMAMUX LPUART1 RX request */ +#define DMA_REQUEST_LPUART1_TX LL_DMAMUX_REQ_LPUART1_TX /*!< DMAMUX LPUART1 TX request */ +#define DMA_REQUEST_TIM1_CH1 LL_DMAMUX_REQ_TIM1_CH1 /*!< DMAMUX TIM1 CH1 request */ +#define DMA_REQUEST_TIM1_CH2 LL_DMAMUX_REQ_TIM1_CH2 /*!< DMAMUX TIM1 CH2 request */ +#define DMA_REQUEST_TIM1_CH3 LL_DMAMUX_REQ_TIM1_CH3 /*!< DMAMUX TIM1 CH3 request */ +#define DMA_REQUEST_TIM1_CH4 LL_DMAMUX_REQ_TIM1_CH4 /*!< DMAMUX TIM1 CH4 request */ +#define DMA_REQUEST_TIM1_UP LL_DMAMUX_REQ_TIM1_UP /*!< DMAMUX TIM1 UP request */ +#define DMA_REQUEST_TIM1_TRIG LL_DMAMUX_REQ_TIM1_TRIG /*!< DMAMUX TIM1 TRIG request */ +#define DMA_REQUEST_TIM1_COM LL_DMAMUX_REQ_TIM1_COM /*!< DMAMUX TIM1 COM request */ +#define DMA_REQUEST_TIM2_CH1 LL_DMAMUX_REQ_TIM2_CH1 /*!< DMAMUX TIM2 CH1 request */ +#define DMA_REQUEST_TIM2_CH2 LL_DMAMUX_REQ_TIM2_CH2 /*!< DMAMUX TIM2 CH2 request */ +#define DMA_REQUEST_TIM2_CH3 LL_DMAMUX_REQ_TIM2_CH3 /*!< DMAMUX TIM2 CH3 request */ +#define DMA_REQUEST_TIM2_CH4 LL_DMAMUX_REQ_TIM2_CH4 /*!< DMAMUX TIM2 CH4 request */ +#define DMA_REQUEST_TIM2_UP LL_DMAMUX_REQ_TIM2_UP /*!< DMAMUX TIM2 UP request */ +#define DMA_REQUEST_TIM16_CH1 LL_DMAMUX_REQ_TIM16_CH1 /*!< DMAMUX TIM16 CH1 request */ +#define DMA_REQUEST_TIM16_UP LL_DMAMUX_REQ_TIM16_UP /*!< DMAMUX TIM16 UP request */ +#define DMA_REQUEST_TIM17_CH1 LL_DMAMUX_REQ_TIM17_CH1 /*!< DMAMUX TIM17 CH1 request */ +#define DMA_REQUEST_TIM17_UP LL_DMAMUX_REQ_TIM17_UP /*!< DMAMUX TIM17 UP request */ +#define DMA_REQUEST_AES_IN LL_DMAMUX_REQ_AES_IN /*!< DMAMUX AES_IN request */ +#define DMA_REQUEST_AES_OUT LL_DMAMUX_REQ_AES_OUT /*!< DMAMUX AES_OUT request */ +#define DMA_REQUEST_SUBGHZSPI_RX LL_DMAMUX_REQ_SUBGHZSPI_RX /*!< DMAMUX SUBGHZSPI RX request*/ +#define DMA_REQUEST_SUBGHZSPI_TX LL_DMAMUX_REQ_SUBGHZSPI_TX /*!< DMAMUX SUBGHZSPI TX request*/ + +#define DMA_MAX_REQUEST LL_DMAMUX_MAX_REQ +/** + * @} + */ + +/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction + * @{ + */ +#define DMA_PERIPH_TO_MEMORY LL_DMA_DIRECTION_PERIPH_TO_MEMORY /*!< Peripheral to memory direction */ +#define DMA_MEMORY_TO_PERIPH LL_DMA_DIRECTION_MEMORY_TO_PERIPH /*!< Memory to peripheral direction */ +#define DMA_MEMORY_TO_MEMORY LL_DMA_DIRECTION_MEMORY_TO_MEMORY /*!< Memory to memory direction */ + +/** + * @} + */ + +/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode + * @{ + */ +#define DMA_PINC_ENABLE LL_DMA_PERIPH_INCREMENT /*!< Peripheral increment mode Enable */ +#define DMA_PINC_DISABLE LL_DMA_PERIPH_NOINCREMENT /*!< Peripheral increment mode Disable */ +/** + * @} + */ + +/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode + * @{ + */ +#define DMA_MINC_ENABLE LL_DMA_MEMORY_INCREMENT /*!< Memory increment mode Enable */ +#define DMA_MINC_DISABLE LL_DMA_MEMORY_NOINCREMENT /*!< Memory increment mode Disable */ +/** + * @} + */ + +/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size + * @{ + */ +#define DMA_PDATAALIGN_BYTE LL_DMA_PDATAALIGN_BYTE /*!< Peripheral data alignment : Byte */ +#define DMA_PDATAALIGN_HALFWORD LL_DMA_PDATAALIGN_HALFWORD /*!< Peripheral data alignment : HalfWord */ +#define DMA_PDATAALIGN_WORD LL_DMA_PDATAALIGN_WORD /*!< Peripheral data alignment : Word */ +/** + * @} + */ + +/** @defgroup DMA_Memory_data_size DMA Memory data size + * @{ + */ +#define DMA_MDATAALIGN_BYTE LL_DMA_MDATAALIGN_BYTE /*!< Memory data alignment : Byte */ +#define DMA_MDATAALIGN_HALFWORD LL_DMA_MDATAALIGN_HALFWORD /*!< Memory data alignment : HalfWord */ +#define DMA_MDATAALIGN_WORD LL_DMA_MDATAALIGN_WORD /*!< Memory data alignment : Word */ +/** + * @} + */ + +/** @defgroup DMA_mode DMA mode + * @{ + */ +#define DMA_NORMAL LL_DMA_MODE_NORMAL /*!< Normal mode */ +#define DMA_CIRCULAR LL_DMA_MODE_CIRCULAR /*!< Circular mode */ +/** + * @} + */ + +/** @defgroup DMA_Priority_level DMA Priority level + * @{ + */ +#define DMA_PRIORITY_LOW LL_DMA_PRIORITY_LOW /*!< Priority level : Low */ +#define DMA_PRIORITY_MEDIUM LL_DMA_PRIORITY_MEDIUM /*!< Priority level : Medium */ +#define DMA_PRIORITY_HIGH LL_DMA_PRIORITY_HIGH /*!< Priority level : High */ +#define DMA_PRIORITY_VERY_HIGH LL_DMA_PRIORITY_VERYHIGH /*!< Priority level : Very_High */ +/** + * @} + */ + +/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions + * @{ + */ +#define DMA_IT_TC DMA_CCR_TCIE /*!< Transfer Complete interrupt */ +#define DMA_IT_HT DMA_CCR_HTIE /*!< Half Transfer Complete interrupt */ +#define DMA_IT_TE DMA_CCR_TEIE /*!< Transfer Error interrupt */ +/** + * @} + */ + +/** @defgroup DMA_flag_definitions DMA flag definitions + * @{ + */ + +#define DMA_FLAG_GI1 DMA_ISR_GIF1 /*!< Global Interrupt flag for Channel 1 */ +#define DMA_FLAG_TC1 DMA_ISR_TCIF1 /*!< Transfer Complete flag for Channel 1 */ +#define DMA_FLAG_HT1 DMA_ISR_HTIF1 /*!< Half Transfer flag for Channel 1 */ +#define DMA_FLAG_TE1 DMA_ISR_TEIF1 /*!< Transfer Error flag for Channel 1 */ +#define DMA_FLAG_GI2 DMA_ISR_GIF2 /*!< Global Interrupt flag for Channel 2 */ +#define DMA_FLAG_TC2 DMA_ISR_TCIF2 /*!< Transfer Complete flag for Channel 2 */ +#define DMA_FLAG_HT2 DMA_ISR_HTIF2 /*!< Half Transfer flag for Channel 2 */ +#define DMA_FLAG_TE2 DMA_ISR_TEIF2 /*!< Transfer Error flag for Channel 2 */ +#define DMA_FLAG_GI3 DMA_ISR_GIF3 /*!< Global Interrupt flag for Channel 3 */ +#define DMA_FLAG_TC3 DMA_ISR_TCIF3 /*!< Transfer Complete flag for Channel 3 */ +#define DMA_FLAG_HT3 DMA_ISR_HTIF3 /*!< Half Transfer flag for Channel 3 */ +#define DMA_FLAG_TE3 DMA_ISR_TEIF3 /*!< Transfer Error flag for Channel 3 */ +#define DMA_FLAG_GI4 DMA_ISR_GIF4 /*!< Global Interrupt flag for Channel 4 */ +#define DMA_FLAG_TC4 DMA_ISR_TCIF4 /*!< Transfer Complete flag for Channel 4 */ +#define DMA_FLAG_HT4 DMA_ISR_HTIF4 /*!< Half Transfer flag for Channel 4 */ +#define DMA_FLAG_TE4 DMA_ISR_TEIF4 /*!< Transfer Error flag for Channel 4 */ +#define DMA_FLAG_GI5 DMA_ISR_GIF5 /*!< Global Interrupt flag for Channel 5 */ +#define DMA_FLAG_TC5 DMA_ISR_TCIF5 /*!< Transfer Complete flag for Channel 5 */ +#define DMA_FLAG_HT5 DMA_ISR_HTIF5 /*!< Half Transfer flag for Channel 5 */ +#define DMA_FLAG_TE5 DMA_ISR_TEIF5 /*!< Transfer Error for Channel 5 */ +#define DMA_FLAG_GI6 DMA_ISR_GIF6 /*!< Global Interrupt flag for Channel 6 */ +#define DMA_FLAG_TC6 DMA_ISR_TCIF6 /*!< Transfer Complete flag for Channel 6 */ +#define DMA_FLAG_HT6 DMA_ISR_HTIF6 /*!< Half Transfer flag for Channel 6 */ +#define DMA_FLAG_TE6 DMA_ISR_TEIF6 /*!< Transfer Error flag for Channel 6 */ +#define DMA_FLAG_GI7 DMA_ISR_GIF7 /*!< Global Interrupt flag for Channel 7 */ +#define DMA_FLAG_TC7 DMA_ISR_TCIF7 /*!< Transfer Complete flag for Channel 7 */ +#define DMA_FLAG_HT7 DMA_ISR_HTIF7 /*!< Half Transfer flag for Channel 7 */ +#define DMA_FLAG_TE7 DMA_ISR_TEIF7 /*!< Transfer Error flag for Channel 7 */ +/** + * @} + */ + +#if defined(DMA_CCR_SECM) && defined(DMA_CCR_PRIV) +/** @defgroup DMA_Channel_Attributes DMA Channel Attributes + * @brief DMA channel secure or non-secure and privileged or non-privileged attributes + * @note Secure and non-secure attributes are only available from secure when the system + * implements the security (ESE=1) + * @{ + */ + +#define DMA_CHANNEL_ATTR_PRIV_MASK (DMA_CCR_PRIV >> 16U) +#define DMA_CHANNEL_ATTR_SEC_MASK (DMA_CCR_SECM >> 16U) +#if defined (CORE_CM0PLUS) +#define DMA_CHANNEL_ATTR_SEC_SRC_MASK (DMA_CCR_SSEC >> 16U) +#define DMA_CHANNEL_ATTR_SEC_DEST_MASK (DMA_CCR_DSEC >> 16U) +#endif /* CORE_CM0PLUS */ + +#define DMA_CHANNEL_PRIV (DMA_CHANNEL_ATTR_PRIV_MASK | DMA_CCR_PRIV) /*!< Channel is privileged */ +#define DMA_CHANNEL_NPRIV (DMA_CHANNEL_ATTR_PRIV_MASK) /*!< Channel is unprivileged */ +#define DMA_CHANNEL_SEC (DMA_CHANNEL_ATTR_SEC_MASK | DMA_CCR_SECM) /*!< Channel is secure */ +#define DMA_CHANNEL_NSEC (DMA_CHANNEL_ATTR_SEC_MASK) /*!< Channel is non-secure */ +#if defined (CORE_CM0PLUS) +#define DMA_CHANNEL_SRC_SEC (DMA_CHANNEL_ATTR_SEC_SRC_MASK | DMA_CCR_SSEC) /*!< Channel source is secure */ +#define DMA_CHANNEL_SRC_NSEC (DMA_CHANNEL_ATTR_SEC_SRC_MASK) /*!< Channel source is non-secure */ +#define DMA_CHANNEL_DEST_SEC (DMA_CHANNEL_ATTR_SEC_DEST_MASK | DMA_CCR_DSEC) /*!< Channel destination is secure */ +#define DMA_CHANNEL_DEST_NSEC (DMA_CHANNEL_ATTR_SEC_DEST_MASK) /*!< Channel destination is non-secure */ +#endif /* CORE_CM0PLUS */ +/** + * @} + */ + +#endif /* DMA_SECURE_SWITCH */ +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup DMA_Exported_Macros DMA Exported Macros + * @{ + */ + +/** @brief Reset DMA handle state + * @param __HANDLE__ DMA handle + * @retval None + */ +#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET) + +/** + * @brief Enable the specified DMA Channel. + * @param __HANDLE__ DMA handle + * @retval None + */ +#define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN) + +/** + * @brief Disable the specified DMA Channel. + * @param __HANDLE__ DMA handle + * @retval None + */ +#define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN) + +/** + * @brief Return the current DMA Channel transfer complete flag. + * @param __HANDLE__ DMA handle + * @retval The specified transfer complete flag index. + */ +#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TC5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_TC6 :\ + DMA_FLAG_TC7) + +/** + * @brief Return the current DMA Channel half transfer complete flag. + * @param __HANDLE__ DMA handle + * @retval The specified half transfer complete flag index. + */ +#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__) \ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_HT5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_HT6 :\ + DMA_FLAG_HT7) + +/** + * @brief Return the current DMA Channel transfer error flag. + * @param __HANDLE__ DMA handle + * @retval The specified transfer error flag index. + */ +#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__) \ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TE5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_TE6 :\ + DMA_FLAG_TE7) + +/** + * @brief Return the current DMA Channel Global interrupt flag. + * @param __HANDLE__ DMA handle + * @retval The specified transfer error flag index. + */ +#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__) \ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GI1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_GI1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GI2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_GI2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GI3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_GI3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GI4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_GI4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_GI5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_GI5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_GI6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_GI6 :\ + DMA_FLAG_GI7) + +/** + * @brief Get the DMA Channel pending flags. + * @param __HANDLE__ DMA handle + * @param __FLAG__ Get the specified flag. + * This parameter can be any combination of the following values: + * @arg DMA_FLAG_TCx: Transfer complete flag + * @arg DMA_FLAG_HTx: Half transfer complete flag + * @arg DMA_FLAG_TEx: Transfer error flag + * @arg DMA_FLAG_GIx: Global interrupt flag + * Where x can be 1 to max Channel supported by the product to select the DMA Channel flag. + * @retval The state of FLAG (SET or RESET). + */ +#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \ + (DMA2->ISR & (__FLAG__)) : (DMA1->ISR & (__FLAG__))) + +/** + * @brief Clear the DMA Channel pending flags. + * @param __HANDLE__ DMA handle + * @param __FLAG__ specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg DMA_FLAG_TCx: Transfer complete flag + * @arg DMA_FLAG_HTx: Half transfer complete flag + * @arg DMA_FLAG_TEx: Transfer error flag + * @arg DMA_FLAG_GIx: Global interrupt flag + * Where x can be 1 to max Channel supported by the product to select the DMA Channel flag. + * @retval None + */ +#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \ + (DMA2->IFCR = (__FLAG__)) : (DMA1->IFCR = (__FLAG__))) + +/** + * @brief Enable the specified DMA Channel interrupts. + * @param __HANDLE__ DMA handle + * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg DMA_IT_TC: Transfer complete interrupt mask + * @arg DMA_IT_HT: Half transfer complete interrupt mask + * @arg DMA_IT_TE: Transfer error interrupt mask + * @retval None + */ +#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__)) + +/** + * @brief Disable the specified DMA Channel interrupts. + * @param __HANDLE__ DMA handle + * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg DMA_IT_TC: Transfer complete interrupt mask + * @arg DMA_IT_HT: Half transfer complete interrupt mask + * @arg DMA_IT_TE: Transfer error interrupt mask + * @retval None + */ +#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__)) + +/** + * @brief Check whether the specified DMA Channel interrupt is enabled or disabled. + * @param __HANDLE__ DMA handle + * @param __INTERRUPT__ specifies the DMA interrupt source to check. + * This parameter can be one of the following values: + * @arg DMA_IT_TC: Transfer complete interrupt mask + * @arg DMA_IT_HT: Half transfer complete interrupt mask + * @arg DMA_IT_TE: Transfer error interrupt mask + * @retval The state of DMA_IT (SET or RESET). + */ +#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__))) + +/** + * @brief Returns the number of remaining data units in the current DMA Channel transfer. + * @param __HANDLE__ DMA handle + * @retval The number of remaining data units in the current DMA Channel transfer. + */ +#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR) + +/** + * @} + */ + +/* Include DMA HAL Extension module */ +#include "stm32wlxx_hal_dma_ex.h" + +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup DMA_Exported_Functions + * @{ + */ + +/** @addtogroup DMA_Exported_Functions_Group1 + * @{ + */ +/* Initialization and de-initialization functions *****************************/ +HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); +HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma); +/** + * @} + */ + +/** @addtogroup DMA_Exported_Functions_Group2 + * @{ + */ +/* IO operation functions *****************************************************/ +HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); +HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, + uint32_t DataLength); +HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma); +HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma); +HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, + uint32_t Timeout); +void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma); +HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma)); +HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID); + +/** + * @} + */ + +/** @addtogroup DMA_Exported_Functions_Group3 + * @{ + */ +/* Peripheral State and Error functions ***************************************/ +HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma); +uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); +/** + * @} + */ + +#if defined(DMA_CCR_SECM) && defined(DMA_CCR_PRIV) +/** @addtogroup DMA_Exported_Functions_Group4 + * @{ + */ +/* DMA Attributes functions ********************************************/ +HAL_StatusTypeDef HAL_DMA_ConfigChannelAttributes(DMA_HandleTypeDef *hdma, uint32_t ChannelAttributes); +HAL_StatusTypeDef HAL_DMA_GetConfigChannelAttributes(DMA_HandleTypeDef *hdma, uint32_t *ChannelAttributes); +/** + * @} + */ + +#endif /* DMA_SECURE_SWITCH */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup DMA_Private_Macros DMA Private Macros + * @{ + */ + +#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \ + ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ + ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) + +#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < DMA_CNDTR_NDT)) + +#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \ + ((STATE) == DMA_PINC_DISABLE)) + +#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \ + ((STATE) == DMA_MINC_DISABLE)) + +#define IS_DMA_ALL_REQUEST(REQUEST) ((REQUEST) <= DMA_MAX_REQUEST) + +#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \ + ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \ + ((SIZE) == DMA_PDATAALIGN_WORD)) + +#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \ + ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \ + ((SIZE) == DMA_MDATAALIGN_WORD )) + +#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \ + ((MODE) == DMA_CIRCULAR)) + +#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \ + ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \ + ((PRIORITY) == DMA_PRIORITY_HIGH) || \ + ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) + +#if defined(DMA_CCR_SECM) && defined(DMA_CCR_PRIV) +#if defined (CORE_CM0PLUS) +#define IS_DMA_ATTRIBUTES(ATTRIBUTE) ((((ATTRIBUTE)\ + & (~(0x001E001EU))) == 0U) && (((ATTRIBUTE) & 0x0000001EU) != 0U)) +#else +#define IS_DMA_ATTRIBUTES(ATTRIBUTE) ((((ATTRIBUTE)\ + & (~(0x00100010U))) == 0U) && (((ATTRIBUTE) & 0x00000010U) != 0U)) +#endif /* CORE_CM0PLUS */ +#endif /* DMA_SECURE_SWITCH */ +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32WLxx_HAL_DMA_H */ + diff --git a/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h b/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h new file mode 100644 index 0000000..ba5b5a8 --- /dev/null +++ b/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h @@ -0,0 +1,266 @@ +/** + ****************************************************************************** + * @file stm32wlxx_hal_dma_ex.h + * @author MCD Application Team + * @brief Header file of DMA HAL extension module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32WLxx_HAL_DMA_EX_H +#define STM32WLxx_HAL_DMA_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wlxx_hal_def.h" +#include "stm32wlxx_ll_dmamux.h" + +/** @addtogroup STM32WLxx_HAL_Driver + * @{ + */ + +/** @addtogroup DMAEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup DMAEx_Exported_Types DMAEx Exported Types + * @{ + */ + +/** + * @brief HAL DMAMUX Synchronization configuration structure definition + */ +typedef struct +{ + uint32_t SyncSignalID; /*!< Specifies the synchronization signal gating the DMA request in periodic mode. + This parameter can be a value of @ref DMAEx_DMAMUX_SyncSignalID_selection */ + + uint32_t SyncPolarity; /*!< Specifies the polarity of the signal on which the DMA request is synchronized. + This parameter can be a value of @ref DMAEx_DMAMUX_SyncPolarity_selection */ + + FunctionalState SyncEnable; /*!< Specifies if the synchronization shall be enabled or disabled + This parameter can take the value ENABLE or DISABLE */ + + FunctionalState EventEnable; /*!< Specifies if an event shall be generated once the RequestNumber is reached. + This parameter can take the value ENABLE or DISABLE */ + + uint32_t RequestNumber; /*!< Specifies the number of DMA request that will be authorized after a sync event + This parameter must be a number between Min_Data = 1 and Max_Data = 32 */ + + +} HAL_DMA_MuxSyncConfigTypeDef; + + +/** + * @brief HAL DMAMUX request generator parameters structure definition + */ +typedef struct +{ + uint32_t SignalID; /*!< Specifies the ID of the signal used for DMAMUX request generator + This parameter can be a value of @ref DMAEx_DMAMUX_SignalGeneratorID_selection */ + + uint32_t Polarity; /*!< Specifies the polarity of the signal on which the request is generated. + This parameter can be a value of @ref DMAEx_DMAMUX_RequestGeneneratorPolarity_selection */ + + uint32_t RequestNumber; /*!< Specifies the number of DMA request that will be generated after a signal event + This parameter must be a number between Min_Data = 1 and Max_Data = 32 */ + +} HAL_DMA_MuxRequestGeneratorConfigTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup DMAEx_Exported_Constants DMAEx Exported Constants + * @{ + */ + +/** @defgroup DMAEx_DMAMUX_SyncSignalID_selection DMAMUX SyncSignalID selection + * @{ + */ +#define HAL_DMAMUX1_SYNC_EXTI0 LL_DMAMUX_SYNC_EXTI_LINE0 /*!< Synchronization signal from EXTI Line0 */ +#define HAL_DMAMUX1_SYNC_EXTI1 LL_DMAMUX_SYNC_EXTI_LINE1 /*!< Synchronization signal from EXTI Line1 */ +#define HAL_DMAMUX1_SYNC_EXTI2 LL_DMAMUX_SYNC_EXTI_LINE2 /*!< Synchronization signal from EXTI Line2 */ +#define HAL_DMAMUX1_SYNC_EXTI3 LL_DMAMUX_SYNC_EXTI_LINE3 /*!< Synchronization signal from EXTI Line3 */ +#define HAL_DMAMUX1_SYNC_EXTI4 LL_DMAMUX_SYNC_EXTI_LINE4 /*!< Synchronization signal from EXTI Line4 */ +#define HAL_DMAMUX1_SYNC_EXTI5 LL_DMAMUX_SYNC_EXTI_LINE5 /*!< Synchronization signal from EXTI Line5 */ +#define HAL_DMAMUX1_SYNC_EXTI6 LL_DMAMUX_SYNC_EXTI_LINE6 /*!< Synchronization signal from EXTI Line6 */ +#define HAL_DMAMUX1_SYNC_EXTI7 LL_DMAMUX_SYNC_EXTI_LINE7 /*!< Synchronization signal from EXTI Line7 */ +#define HAL_DMAMUX1_SYNC_EXTI8 LL_DMAMUX_SYNC_EXTI_LINE8 /*!< Synchronization signal from EXTI Line8 */ +#define HAL_DMAMUX1_SYNC_EXTI9 LL_DMAMUX_SYNC_EXTI_LINE9 /*!< Synchronization signal from EXTI Line9 */ +#define HAL_DMAMUX1_SYNC_EXTI10 LL_DMAMUX_SYNC_EXTI_LINE10 /*!< Synchronization signal from EXTI Line10 */ +#define HAL_DMAMUX1_SYNC_EXTI11 LL_DMAMUX_SYNC_EXTI_LINE11 /*!< Synchronization signal from EXTI Line11 */ +#define HAL_DMAMUX1_SYNC_EXTI12 LL_DMAMUX_SYNC_EXTI_LINE12 /*!< Synchronization signal from EXTI Line12 */ +#define HAL_DMAMUX1_SYNC_EXTI13 LL_DMAMUX_SYNC_EXTI_LINE13 /*!< Synchronization signal from EXTI Line13 */ +#define HAL_DMAMUX1_SYNC_EXTI14 LL_DMAMUX_SYNC_EXTI_LINE14 /*!< Synchronization signal from EXTI Line14 */ +#define HAL_DMAMUX1_SYNC_EXTI15 LL_DMAMUX_SYNC_EXTI_LINE15 /*!< Synchronization signal from EXTI Line15 */ +#define HAL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT LL_DMAMUX_SYNC_DMAMUX_CH0 /*!< Synchronization signal from DMAMUX channel0 Event */ +#define HAL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT LL_DMAMUX_SYNC_DMAMUX_CH1 /*!< Synchronization signal from DMAMUX channel1 Event */ +#define HAL_DMAMUX1_SYNC_LPTIM1_OUT LL_DMAMUX_SYNC_LPTIM1_OUT /*!< Synchronization signal from LPTIM1 Output */ +#define HAL_DMAMUX1_SYNC_LPTIM2_OUT LL_DMAMUX_SYNC_LPTIM2_OUT /*!< Synchronization signal from LPTIM2 Output */ +#define HAL_DMAMUX1_SYNC_LPTIM3_OUT LL_DMAMUX_SYNC_LPTIM3_OUT /*!< Synchronization signal from LPTIM3 Output */ + +#define HAL_DMAMUX1_MAX_SYNC HAL_DMAMUX1_SYNC_LPTIM3_OUT +/** + * @} + */ + +/** @defgroup DMAEx_DMAMUX_SyncPolarity_selection DMAMUX SyncPolarity selection + * @{ + */ +#define HAL_DMAMUX_SYNC_NO_EVENT LL_DMAMUX_SYNC_NO_EVENT /*!< block synchronization events */ +#define HAL_DMAMUX_SYNC_RISING LL_DMAMUX_SYNC_POL_RISING /*!< synchronize with rising edge events */ +#define HAL_DMAMUX_SYNC_FALLING LL_DMAMUX_SYNC_POL_FALLING /*!< synchronize with falling edge events */ +#define HAL_DMAMUX_SYNC_RISING_FALLING LL_DMAMUX_SYNC_POL_RISING_FALLING /*!< synchronize with rising and falling edge events */ + +/** + * @} + */ + +/** @defgroup DMAEx_DMAMUX_SignalGeneratorID_selection DMAMUX SignalGeneratorID selection + * @{ + */ +#define HAL_DMAMUX1_REQ_GEN_EXTI0 LL_DMAMUX_REQ_GEN_EXTI_LINE0 /*!< Request signal generation from EXTI Line0 */ +#define HAL_DMAMUX1_REQ_GEN_EXTI1 LL_DMAMUX_REQ_GEN_EXTI_LINE1 /*!< Request signal generation from EXTI Line1 */ +#define HAL_DMAMUX1_REQ_GEN_EXTI2 LL_DMAMUX_REQ_GEN_EXTI_LINE2 /*!< Request signal generation from EXTI Line2 */ +#define HAL_DMAMUX1_REQ_GEN_EXTI3 LL_DMAMUX_REQ_GEN_EXTI_LINE3 /*!< Request signal generation from EXTI Line3 */ +#define HAL_DMAMUX1_REQ_GEN_EXTI4 LL_DMAMUX_REQ_GEN_EXTI_LINE4 /*!< Request signal generation from EXTI Line4 */ +#define HAL_DMAMUX1_REQ_GEN_EXTI5 LL_DMAMUX_REQ_GEN_EXTI_LINE5 /*!< Request signal generation from EXTI Line5 */ +#define HAL_DMAMUX1_REQ_GEN_EXTI6 LL_DMAMUX_REQ_GEN_EXTI_LINE6 /*!< Request signal generation from EXTI Line6 */ +#define HAL_DMAMUX1_REQ_GEN_EXTI7 LL_DMAMUX_REQ_GEN_EXTI_LINE7 /*!< Request signal generation from EXTI Line7 */ +#define HAL_DMAMUX1_REQ_GEN_EXTI8 LL_DMAMUX_REQ_GEN_EXTI_LINE8 /*!< Request signal generation from EXTI Line8 */ +#define HAL_DMAMUX1_REQ_GEN_EXTI9 LL_DMAMUX_REQ_GEN_EXTI_LINE9 /*!< Request signal generation from EXTI Line9 */ +#define HAL_DMAMUX1_REQ_GEN_EXTI10 LL_DMAMUX_REQ_GEN_EXTI_LINE10 /*!< Request signal generation from EXTI Line10 */ +#define HAL_DMAMUX1_REQ_GEN_EXTI11 LL_DMAMUX_REQ_GEN_EXTI_LINE11 /*!< Request signal generation from EXTI Line11 */ +#define HAL_DMAMUX1_REQ_GEN_EXTI12 LL_DMAMUX_REQ_GEN_EXTI_LINE12 /*!< Request signal generation from EXTI Line12 */ +#define HAL_DMAMUX1_REQ_GEN_EXTI13 LL_DMAMUX_REQ_GEN_EXTI_LINE13 /*!< Request signal generation from EXTI Line13 */ +#define HAL_DMAMUX1_REQ_GEN_EXTI14 LL_DMAMUX_REQ_GEN_EXTI_LINE14 /*!< Request signal generation from EXTI Line14 */ +#define HAL_DMAMUX1_REQ_GEN_EXTI15 LL_DMAMUX_REQ_GEN_EXTI_LINE15 /*!< Request signal generation from EXTI Line15 */ +#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT LL_DMAMUX_REQ_GEN_DMAMUX_CH0 /*!< Request signal generation from DMAMUX channel0 Event */ +#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT LL_DMAMUX_REQ_GEN_DMAMUX_CH1 /*!< Request signal generation from DMAMUX channel1 Event */ +#define HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT LL_DMAMUX_REQ_GEN_LPTIM1_OUT /*!< Request signal generation from LPTIM1 Output */ +#define HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT LL_DMAMUX_REQ_GEN_LPTIM2_OUT /*!< Request signal generation from LPTIM2 Output */ +#define HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT LL_DMAMUX_REQ_GEN_LPTIM3_OUT /*!< Request signal generation from LPTIM3 Output */ + +#define HAL_DMAMUX1_MAX_REQ_GEN HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT +/** + * @} + */ + +/** @defgroup DMAEx_DMAMUX_RequestGeneneratorPolarity_selection DMAMUX RequestGeneneratorPolarity selection + * @{ + */ +#define HAL_DMAMUX_REQ_GEN_NO_EVENT LL_DMAMUX_REQ_GEN_NO_EVENT /*!< block request generator events */ +#define HAL_DMAMUX_REQ_GEN_RISING LL_DMAMUX_REQ_GEN_POL_RISING /*!< generate request on rising edge events */ +#define HAL_DMAMUX_REQ_GEN_FALLING LL_DMAMUX_REQ_GEN_POL_FALLING /*!< generate request on falling edge events */ +#define HAL_DMAMUX_REQ_GEN_RISING_FALLING LL_DMAMUX_REQ_GEN_POL_RISING_FALLING /*!< generate request on rising and falling edge events */ + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup DMAEx_Exported_Functions + * @{ + */ + +/* IO operation functions *****************************************************/ +/** @addtogroup DMAEx_Exported_Functions_Group1 + * @{ + */ + +/* ------------------------- REQUEST -----------------------------------------*/ +HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator(DMA_HandleTypeDef *hdma, + HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig); +HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator(DMA_HandleTypeDef *hdma); +HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator(DMA_HandleTypeDef *hdma); +/* -------------------------------------------------------------------------- */ + +/* ------------------------- SYNCHRO -----------------------------------------*/ +HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(DMA_HandleTypeDef *hdma, HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig); +/* -------------------------------------------------------------------------- */ + +void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma); + +/** + * @} + */ + +/** + * @} + */ + + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup DMAEx_Private_Macros DMAEx Private Macros + * @brief DMAEx private macros + * @{ + */ + +#define IS_DMAMUX_SYNC_SIGNAL_ID(SIGNAL_ID) (((SIGNAL_ID) == HAL_DMAMUX1_SYNC_EXTI0) || \ + (((SIGNAL_ID) >= HAL_DMAMUX1_SYNC_EXTI1) && \ + ((SIGNAL_ID) <= HAL_DMAMUX1_MAX_SYNC))) + +#define IS_DMAMUX_SYNC_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0U) && ((REQUEST_NUMBER) <= 32U)) + +#define IS_DMAMUX_SYNC_POLARITY(POLARITY) (((POLARITY) == HAL_DMAMUX_SYNC_NO_EVENT) || \ + ((POLARITY) == HAL_DMAMUX_SYNC_RISING) || \ + ((POLARITY) == HAL_DMAMUX_SYNC_FALLING) || \ + ((POLARITY) == HAL_DMAMUX_SYNC_RISING_FALLING)) + +#define IS_DMAMUX_SYNC_STATE(SYNC) (((SYNC) == DISABLE) || ((SYNC) == ENABLE)) + +#define IS_DMAMUX_SYNC_EVENT(EVENT) (((EVENT) == DISABLE) || \ + ((EVENT) == ENABLE)) + +#define IS_DMAMUX_REQUEST_GEN_SIGNAL_ID(SIGNAL_ID) (((SIGNAL_ID) == HAL_DMAMUX1_REQ_GEN_EXTI0) || \ + (((SIGNAL_ID) >= HAL_DMAMUX1_REQ_GEN_EXTI1) && \ + ((SIGNAL_ID) <= HAL_DMAMUX1_MAX_REQ_GEN))) + +#define IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0U) && ((REQUEST_NUMBER) <= 32U)) + +#define IS_DMAMUX_REQUEST_GEN_POLARITY(POLARITY) (((POLARITY) == HAL_DMAMUX_REQ_GEN_NO_EVENT)|| \ + ((POLARITY) == HAL_DMAMUX_REQ_GEN_RISING) || \ + ((POLARITY) == HAL_DMAMUX_REQ_GEN_FALLING) || \ + ((POLARITY) == HAL_DMAMUX_REQ_GEN_RISING_FALLING)) + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32WLxx_HAL_DMA_EX_H */ + diff --git a/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h b/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h new file mode 100644 index 0000000..6efa9d3 --- /dev/null +++ b/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h @@ -0,0 +1,327 @@ +/** + ****************************************************************************** + * @file stm32wlxx_hal_exti.h + * @author MCD Application Team + * @brief Header file of EXTI HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32WLxx_HAL_EXTI_H +#define STM32WLxx_HAL_EXTI_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wlxx_hal_def.h" + +/** @addtogroup STM32WLxx_HAL_Driver + * @{ + */ + +/** @defgroup EXTI EXTI + * @brief EXTI HAL module driver + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup EXTI_Exported_Types EXTI Exported Types + * @{ + */ +typedef enum +{ + HAL_EXTI_COMMON_CB_ID = 0x00U, +} EXTI_CallbackIDTypeDef; + + +/** + * @brief EXTI Handle structure definition + */ +typedef struct +{ + uint32_t Line; /*!< Exti line number */ + void (* PendingCallback)(void); /*!< Exti pending callback */ +} EXTI_HandleTypeDef; + +/** + * @brief EXTI Configuration structure definition + */ +typedef struct +{ + uint32_t Line; /*!< The Exti line to be configured. This parameter + can be a value of @ref EXTI_Line */ + uint32_t Mode; /*!< The Exit Mode to be configured for a core. + This parameter can be a combination of @ref EXTI_Mode */ + uint32_t Trigger; /*!< The Exti Trigger to be configured. This parameter + can be a value of @ref EXTI_Trigger */ + uint32_t GPIOSel; /*!< The Exti GPIO multiplexer selection to be configured. + This parameter is only possible for line 0 to 15. It + can be a value of @ref EXTI_GPIOSel */ +} EXTI_ConfigTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup EXTI_Exported_Constants EXTI Exported Constants + * @{ + */ + +/** @defgroup EXTI_Line EXTI Line + * @{ + */ +#define EXTI_LINE_0 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x00u) +#define EXTI_LINE_1 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x01u) +#define EXTI_LINE_2 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x02u) +#define EXTI_LINE_3 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x03u) +#define EXTI_LINE_4 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x04u) +#define EXTI_LINE_5 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x05u) +#define EXTI_LINE_6 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x06u) +#define EXTI_LINE_7 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x07u) +#define EXTI_LINE_8 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x08u) +#define EXTI_LINE_9 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x09u) +#define EXTI_LINE_10 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x0Au) +#define EXTI_LINE_11 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x0Bu) +#define EXTI_LINE_12 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x0Cu) +#define EXTI_LINE_13 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x0Du) +#define EXTI_LINE_14 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x0Eu) +#define EXTI_LINE_15 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x0Fu) +#define EXTI_LINE_16 (EXTI_CONFIG | EXTI_REG1 | 0x10u) +#define EXTI_LINE_17 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG1 | 0x11u) +#define EXTI_LINE_18 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG1 | 0x12u) +#define EXTI_LINE_19 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG1 | 0x13u) +#define EXTI_LINE_20 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG1 | 0x14u) +#define EXTI_LINE_21 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG1 | 0x15u) +#define EXTI_LINE_22 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG1 | 0x16u) +#define EXTI_LINE_23 (EXTI_DIRECT | EXTI_REG1 | 0x17u) +#define EXTI_LINE_24 (EXTI_DIRECT | EXTI_REG1 | 0x18u) +#define EXTI_LINE_25 (EXTI_DIRECT | EXTI_REG1 | 0x19u) +#define EXTI_LINE_26 (EXTI_DIRECT | EXTI_REG1 | 0x1Au) +#define EXTI_LINE_27 (EXTI_DIRECT | EXTI_REG1 | 0x1Bu) +#define EXTI_LINE_28 (EXTI_DIRECT | EXTI_REG1 | 0x1Cu) +#define EXTI_LINE_29 (EXTI_DIRECT | EXTI_REG1 | 0x1Du) +#define EXTI_LINE_30 (EXTI_DIRECT | EXTI_REG1 | 0x1Eu) +#define EXTI_LINE_31 (EXTI_DIRECT | EXTI_REG1 | 0x1Fu) +#define EXTI_LINE_32 (EXTI_RESERVED | EXTI_REG2 | 0x00u) +#define EXTI_LINE_33 (EXTI_RESERVED | EXTI_REG2 | 0x01u) +#define EXTI_LINE_34 (EXTI_CONFIG | EXTI_REG2 | 0x02u) +#define EXTI_LINE_35 (EXTI_RESERVED | EXTI_REG2 | 0x03u) +#if defined (DUAL_CORE) +#define EXTI_LINE_36 (EXTI_DIRECT | EXTI_REG2 | 0x04u) +#define EXTI_LINE_37 (EXTI_DIRECT | EXTI_REG2 | 0x05u) +#else +#define EXTI_LINE_36 (EXTI_RESERVED | EXTI_REG2 | 0x04u) +#define EXTI_LINE_37 (EXTI_RESERVED | EXTI_REG2 | 0x05u) +#endif /* DUAL_CORE */ +#define EXTI_LINE_38 (EXTI_DIRECT | EXTI_REG2 | 0x06u) +#if defined (DUAL_CORE) +#define EXTI_LINE_39 (EXTI_DIRECT | EXTI_REG2 | 0x07u) +#define EXTI_LINE_40 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG2 | 0x08u) +#define EXTI_LINE_41 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG2 | 0x09u) +#else +#define EXTI_LINE_39 (EXTI_RESERVED | EXTI_REG2 | 0x07u) +#define EXTI_LINE_40 (EXTI_RESERVED | EXTI_REG2 | 0x08u) +#define EXTI_LINE_41 (EXTI_RESERVED | EXTI_REG2 | 0x09u) +#endif /* DUAL_CORE */ +#define EXTI_LINE_42 (EXTI_DIRECT | EXTI_REG2 | 0x0Au) +#define EXTI_LINE_43 (EXTI_DIRECT | EXTI_REG2 | 0x0Bu) +#define EXTI_LINE_44 (EXTI_DIRECT | EXTI_REG2 | 0x0Cu) +#define EXTI_LINE_45 (EXTI_CONFIG | EXTI_REG2 | 0x0Du) +#define EXTI_LINE_46 (EXTI_DIRECT | EXTI_REG2 | 0x0Eu) +/** + * @} + */ + +/** @defgroup EXTI_Mode EXTI Mode + * @{ + */ +#define EXTI_MODE_NONE 0x00000000u +#define EXTI_MODE_INTERRUPT 0x00000001u +#define EXTI_MODE_EVENT 0x00000002u +/** + * @} + */ + +/** @defgroup EXTI_Trigger EXTI Trigger + * @{ + */ +#define EXTI_TRIGGER_NONE 0x00000000u +#define EXTI_TRIGGER_RISING 0x00000001u +#define EXTI_TRIGGER_FALLING 0x00000002u +#define EXTI_TRIGGER_RISING_FALLING (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING) +/** + * @} + */ + +/** @defgroup EXTI_GPIOSel EXTI GPIOSel + * @brief + * @{ + */ +#define EXTI_GPIOA 0x00000000u +#define EXTI_GPIOB 0x00000001u +#define EXTI_GPIOC 0x00000002u +#define EXTI_GPIOH 0x00000007u +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup EXTI_Exported_Macros EXTI Exported Macros + * @{ + */ + +/** + * @} + */ + +/* Private constants --------------------------------------------------------*/ +/** @defgroup EXTI_Private_Constants EXTI Private Constants + * @{ + */ +/** + * @brief EXTI Line property definition + */ +#define EXTI_PROPERTY_SHIFT 24u +#define EXTI_DIRECT (0x01uL << EXTI_PROPERTY_SHIFT) +#define EXTI_CONFIG (0x02uL << EXTI_PROPERTY_SHIFT) +#define EXTI_GPIO ((0x04uL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG) +#define EXTI_RESERVED (0x08uL << EXTI_PROPERTY_SHIFT) +#define EXTI_PROPERTY_MASK (EXTI_DIRECT | EXTI_CONFIG | EXTI_GPIO) + +/** + * @brief EXTI Event presence definition + */ +#define EXTI_EVENT_PRESENCE_SHIFT 28u +#define EXTI_EVENT_PRESENCE_MASK (0x01uL << EXTI_EVENT_PRESENCE_SHIFT) +#define EXTI_EVENT EXTI_EVENT_PRESENCE_MASK + +/** + * @brief EXTI Register and bit usage + */ +#define EXTI_REG_SHIFT 16u +#define EXTI_REG1 (0x00uL << EXTI_REG_SHIFT) +#define EXTI_REG2 (0x01uL << EXTI_REG_SHIFT) +#define EXTI_REG_MASK (EXTI_REG1 | EXTI_REG2) +#define EXTI_PIN_MASK 0x0000001Fu + +/** + * @brief EXTI Mask for interrupt & event mode + */ +#define EXTI_MODE_MASK (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT) + +/** + * @brief EXTI Mask for trigger possibilities + */ +#define EXTI_TRIGGER_MASK (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING) + +/** + * @brief EXTI Line number + */ +#define EXTI_LINE_NB 47uL + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup EXTI_Private_Macros EXTI Private Macros + * @{ + */ +#define IS_EXTI_LINE(__EXTI_LINE__) ((((__EXTI_LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_EVENT_PRESENCE_MASK | EXTI_REG_MASK | EXTI_PIN_MASK)) == 0x00u) && \ + ((((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_DIRECT) || \ + (((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || \ + (((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) && \ + (((__EXTI_LINE__) & (EXTI_REG_MASK | EXTI_PIN_MASK)) < \ + (((EXTI_LINE_NB / 32u) << EXTI_REG_SHIFT) | (EXTI_LINE_NB % 32u)))) + +#define IS_EXTI_MODE(__EXTI_LINE__) ((((__EXTI_LINE__) & EXTI_MODE_MASK) != 0x00u) && \ + (((__EXTI_LINE__) & ~EXTI_MODE_MASK) == 0x00u)) + +#define IS_EXTI_TRIGGER(__EXTI_LINE__) (((__EXTI_LINE__) & ~EXTI_TRIGGER_MASK) == 0x00u) + +#define IS_EXTI_PENDING_EDGE(__EXTI_LINE__) ((__EXTI_LINE__) == EXTI_TRIGGER_RISING_FALLING) + +#define IS_EXTI_CONFIG_LINE(__EXTI_LINE__) (((__EXTI_LINE__) & EXTI_CONFIG) != 0x00u) + +#define IS_EXTI_EVENT_PRESENT(__EXTI_LINE__) (((__EXTI_LINE__) & EXTI_EVENT) != 0x00u) + +#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ + ((__PORT__) == EXTI_GPIOB) || \ + ((__PORT__) == EXTI_GPIOC) || \ + ((__PORT__) == EXTI_GPIOH)) + +#define IS_EXTI_GPIO_PIN(__PIN__) ((__PIN__) < 16u) +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup EXTI_Exported_Functions EXTI Exported Functions + * @brief EXTI Exported Functions + * @{ + */ + +/** @defgroup EXTI_Exported_Functions_Group1 Configuration functions + * @brief Configuration functions + * @{ + */ +/* Configuration functions ****************************************************/ +HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig); +HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig); +HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(const EXTI_HandleTypeDef *hexti); +HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void)); +HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine); +/** + * @} + */ + +/** @defgroup EXTI_Exported_Functions_Group2 IO operation functions + * @brief IO operation functions + * @{ + */ +/* IO operation functions *****************************************************/ +void HAL_EXTI_IRQHandler(const EXTI_HandleTypeDef *hexti); +uint32_t HAL_EXTI_GetPending(const EXTI_HandleTypeDef *hexti, uint32_t Edge); +void HAL_EXTI_ClearPending(const EXTI_HandleTypeDef *hexti, uint32_t Edge); +void HAL_EXTI_GenerateSWI(const EXTI_HandleTypeDef *hexti); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32WLxx_HAL_EXTI_H */ diff --git a/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h b/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h new file mode 100644 index 0000000..3eaa6bf --- /dev/null +++ b/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h @@ -0,0 +1,1026 @@ +/** + ****************************************************************************** + * @file stm32wlxx_hal_flash.h + * @author MCD Application Team + * @brief Header file of FLASH HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32WLxx_HAL_FLASH_H +#define STM32WLxx_HAL_FLASH_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wlxx_hal_def.h" + +/** @addtogroup STM32WLxx_HAL_Driver + * @{ + */ + +/** @addtogroup FLASH + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup FLASH_Exported_Types FLASH Exported Types + * @{ + */ + +/** + * @brief FLASH Erase structure definition + */ +typedef struct +{ + uint32_t TypeErase; /*!< Mass erase or page erase. + This parameter can be a value of @ref FLASH_TYPE_ERASE */ + uint32_t Page; /*!< Initial Flash page to erase when page erase is enabled + This parameter must be a value between 0 and (FLASH_PAGE_NB - 1) */ + uint32_t NbPages; /*!< Number of pages to be erased. + This parameter must be a value between 1 and (FLASH_PAGE_NB - value of initial page)*/ +} FLASH_EraseInitTypeDef; + +/** + * @brief FLASH Option Bytes Program structure definition + */ +typedef struct +{ + uint32_t OptionType; /*!< Option byte to be configured. + This parameter can be a combination of the values of @ref FLASH_OB_TYPE */ + uint32_t WRPArea; /*!< Write protection area to be programmed (used for OPTIONBYTE_WRP). + Only one WRP area could be programmed at the same time. + This parameter can be value of @ref FLASH_OB_WRP_AREA */ + uint32_t WRPStartOffset; /*!< Write protection start offset (used for OPTIONBYTE_WRP). + This parameter must be a value between 0 and (max number of pages - 1) */ + uint32_t WRPEndOffset; /*!< Write protection end offset (used for OPTIONBYTE_WRP). + This parameter must be a value between WRPStartOffset and (max number of pages - 1) */ + uint32_t RDPLevel; /*!< Set the read protection level (used for OPTIONBYTE_RDP). + This parameter can be a value of @ref FLASH_OB_READ_PROTECTION */ + uint32_t UserType; /*!< User option byte(s) to be configured (used for OPTIONBYTE_USER). + This parameter can be a combination of @ref FLASH_OB_USER_TYPE */ +#if defined(DUAL_CORE) /* Comment duplicated for Document generation */ + uint32_t UserConfig; /*!< Value of the user option byte (used for OPTIONBYTE_USER). + This parameter can be a combination of the values of + @ref FLASH_OB_USER_BOR_LEVEL + @ref FLASH_OB_USER_nRST_STOP, @ref FLASH_OB_USER_nRST_STANDBY, + @ref FLASH_OB_USER_nRST_SHUTDOWN, @ref FLASH_OB_USER_IWDG_SW, + @ref FLASH_OB_USER_IWDG_STOP, @ref FLASH_OB_USER_IWDG_STANDBY, + @ref FLASH_OB_USER_WWDG_SW, @ref FLASH_OB_USER_nBOOT1, + @ref FLASH_OB_USER_SRAM2_PE, @ref FLASH_OB_USER_SRAM_RST, + @ref FLASH_OB_USER_nSWBOOT0, @ref FLASH_OB_USER_nBOOT0, + @ref FLASH_OB_USER_BOOT_LOCK, @ref FLASH_OB_USER_C2BOOT_LOCK */ +#else + uint32_t UserConfig; /*!< Value of the user option byte (used for OPTIONBYTE_USER). + This parameter can be a combination of the values of + @ref FLASH_OB_USER_BOR_LEVEL + @ref FLASH_OB_USER_nRST_STOP, @ref FLASH_OB_USER_nRST_STANDBY, + @ref FLASH_OB_USER_nRST_SHUTDOWN, @ref FLASH_OB_USER_IWDG_SW, + @ref FLASH_OB_USER_IWDG_STOP, @ref FLASH_OB_USER_IWDG_STANDBY, + @ref FLASH_OB_USER_WWDG_SW, @ref FLASH_OB_USER_nBOOT1, + @ref FLASH_OB_USER_SRAM2_PE, @ref FLASH_OB_USER_SRAM_RST, + @ref FLASH_OB_USER_nSWBOOT0, @ref FLASH_OB_USER_nBOOT0, + @ref FLASH_OB_USER_BOOT_LOCK */ +#endif + uint32_t PCROPConfig; /*!< Configuration of the PCROP (used for OPTIONBYTE_PCROP). + This parameter must be a combination of values of @ref FLASH_OB_PCROP_ZONE + and @ref FLASH_OB_PCROP_RDP */ + uint32_t PCROP1AStartAddr; /*!< PCROP Zone A Start address (used for OPTIONBYTE_PCROP). It represents first address of start block + to protect. Make sure this parameter is multiple of PCROP granularity */ + uint32_t PCROP1AEndAddr; /*!< PCROP Zone A End address (used for OPTIONBYTE_PCROP). It represents first address of end block + to protect. Make sure this parameter is multiple of PCROP granularity */ + uint32_t PCROP1BStartAddr; /*!< PCROP Zone B Start address (used for OPTIONBYTE_PCROP). It represents first address of start block + to protect. Make sure this parameter is multiple of PCROP granularity */ + uint32_t PCROP1BEndAddr; /*!< PCROP Zone B End address (used for OPTIONBYTE_PCROP). It represents first address of end block + to protect. Make sure this parameter is multiple of PCROP granularity */ +#if defined(DUAL_CORE) + uint32_t SecureFlashStartAddr; /*!< Secure Flash start address (used for OPTIONBYTE_SECURE_MODE). + This parameter must be a value between begin and end of Flash bank + => Contains the start address of the first 2kB page of the secure Flash area */ + uint32_t SecureSRAM2StartAddr; /*!< Secure Backup SRAM2 start address (used for OPTIONBYTE_SECURE_MODE). + This parameter must be aligned on 1kB boundary */ + uint32_t SecureSRAM1StartAddr; /*!< Secure non-Backup SRAM1 start address (used for OPTIONBYTE_SECURE_MODE) + This parameter must be aligned on 1kB boundary */ + uint32_t HideProtectionStartAddr;/*!< Hide Protection area start address (used for OPTIONBYTE_SECURE_MODE) + This parameter must be aligned on 2kB boundary */ + uint32_t SecureMode; /*!< Secure mode activated or deactivated. + This parameter can be a value of @ref FLASH_OB_SECURITY_MODE */ + uint32_t SUBGHZSPISecureAccess; /*!< Sub-GHz radio SPI security access enabled or disabled (used for OPTIONBYTE_SUBGHZSPI_SECURE_ACCESS). + This parameter can be a value of @ref FLASH_OB_SUBGHZSPI_SECURE_ACCESS */ + uint32_t C2DebugAccessMode; /*!< CPU2 debug access enabled or disabled (used for OPTIONBYTE_C2_DEBUG_ACCESS). + This parameter can be a value of @ref FLASH_OB_C2_DEBUG_ACCESS */ + uint32_t C2BootRegion; /*!< CPU2 Secure Boot memory region(used for OPTIONBYTE_C2_BOOT_VECT). + This parameter can be a value of @ref FLASH_OB_C2_BOOT_REGION */ + uint32_t C2SecureBootVectAddr; /*!< CPU2 Secure Boot reset vector (used for OPTIONBYTE_C2_BOOT_VECT). + This parameter contains the CPU2 boot reset start address within + the selected memory region. Make sure this parameter is word aligned. */ + uint32_t IPCCdataBufAddr; /*!< IPCC mailbox data buffer base address (used for OPTIONBYTE_IPCC_BUF_ADDR). + This parameter contains the IPCC mailbox data buffer start address area + in SRAM1 or SRAM2. Make sure this parameter is double-word aligned. */ +#endif /* DUAL_CORE */ +} FLASH_OBProgramInitTypeDef; + +/** + * @brief FLASH handle Structure definition + */ +typedef struct +{ + HAL_LockTypeDef Lock; /* FLASH locking object */ + uint32_t ErrorCode; /* FLASH error code */ + uint32_t ProcedureOnGoing; /* Internal variable to indicate which procedure is ongoing or not in IT context */ + uint32_t Address; /* Internal variable to save address selected for program in IT context */ + uint32_t Page; /* Internal variable to define the current page which is erasing in IT context */ + uint32_t NbPagesToErase; /* Internal variable to save the remaining pages to erase in IT context */ +} FLASH_ProcessTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup FLASH_Exported_Constants FLASH Exported Constants + * @{ + */ + +/** @defgroup FLASH_KEYS FLASH Keys + * @{ + */ +#define FLASH_KEY1 0x45670123U /*!< Flash key1 */ +#define FLASH_KEY2 0xCDEF89ABU /*!< Flash key2: used with FLASH_KEY1 + to unlock the FLASH registers access */ + +#define FLASH_OPTKEY1 0x08192A3BU /*!< Flash option byte key1 */ +#define FLASH_OPTKEY2 0x4C5D6E7FU /*!< Flash option byte key2: used with FLASH_OPTKEY1 + to allow option bytes operations */ +/** + * @} + */ + +/** @defgroup FLASH_LATENCY FLASH Latency + * @{ + */ +#define FLASH_LATENCY_0 0x00000000U /*!< FLASH Zero wait state */ +#define FLASH_LATENCY_1 FLASH_ACR_LATENCY_0 /*!< FLASH One wait state */ +#define FLASH_LATENCY_2 FLASH_ACR_LATENCY_1 /*!< FLASH Two wait states */ +/** + * @} + */ + +/** @defgroup FLASH_FLAGS FLASH Flags Definition + * @{ + */ +#ifdef CORE_CM0PLUS +#define FLASH_FLAG_EOP FLASH_C2SR_EOP /*!< CPU2 FLASH End of operation flag */ +#define FLASH_FLAG_OPERR FLASH_C2SR_OPERR /*!< CPU2 FLASH Operation error flag */ +#define FLASH_FLAG_PROGERR FLASH_C2SR_PROGERR /*!< CPU2 FLASH Programming error flag */ +#define FLASH_FLAG_WRPERR FLASH_C2SR_WRPERR /*!< CPU2 FLASH Write protection error flag */ +#define FLASH_FLAG_PGAERR FLASH_C2SR_PGAERR /*!< CPU2 FLASH Programming alignment error flag */ +#define FLASH_FLAG_SIZERR FLASH_C2SR_SIZERR /*!< CPU2 FLASH Size error flag */ +#define FLASH_FLAG_PGSERR FLASH_C2SR_PGSERR /*!< CPU2 FLASH Programming sequence error flag */ +#define FLASH_FLAG_MISERR FLASH_C2SR_MISERR /*!< CPU2 FLASH Fast programming data miss error flag */ +#define FLASH_FLAG_FASTERR FLASH_C2SR_FASTERR /*!< CPU2 FLASH Fast programming error flag */ +#define FLASH_FLAG_OPTNV FLASH_C2SR_OPTNV /*!< CPU2 FLASH User Option OPTVAL indication */ +#define FLASH_FLAG_RDERR FLASH_C2SR_RDERR /*!< CPU2 FLASH PCROP read error flag */ +#define FLASH_FLAG_OPTVERR FLASH_SR_OPTVERR /*!< FLASH Option validity error flag */ +#define FLASH_FLAG_BSY FLASH_C2SR_BSY /*!< CPU2 FLASH Busy flag */ +#define FLASH_FLAG_CFGBSY FLASH_C2SR_CFGBSY /*!< CPU2 FLASH Programming/erase configuration busy */ +#define FLASH_FLAG_PESD FLASH_C2SR_PESD /*!< CPU2 FLASH Programming/erase operation suspended */ +#else +#define FLASH_FLAG_EOP FLASH_SR_EOP /*!< FLASH End of operation flag */ +#define FLASH_FLAG_OPERR FLASH_SR_OPERR /*!< FLASH Operation error flag */ +#define FLASH_FLAG_PROGERR FLASH_SR_PROGERR /*!< FLASH Programming error flag */ +#define FLASH_FLAG_WRPERR FLASH_SR_WRPERR /*!< FLASH Write protection error flag */ +#define FLASH_FLAG_PGAERR FLASH_SR_PGAERR /*!< FLASH Programming alignment error flag */ +#define FLASH_FLAG_SIZERR FLASH_SR_SIZERR /*!< FLASH Size error flag */ +#define FLASH_FLAG_PGSERR FLASH_SR_PGSERR /*!< FLASH Programming sequence error flag */ +#define FLASH_FLAG_MISERR FLASH_SR_MISERR /*!< FLASH Fast programming data miss error flag */ +#define FLASH_FLAG_FASTERR FLASH_SR_FASTERR /*!< FLASH Fast programming error flag */ +#define FLASH_FLAG_OPTNV FLASH_SR_OPTNV /*!< FLASH User Option OPTVAL indication */ +#define FLASH_FLAG_RDERR FLASH_SR_RDERR /*!< FLASH PCROP read error flag */ +#define FLASH_FLAG_OPTVERR FLASH_SR_OPTVERR /*!< FLASH Option validity error flag */ +#define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */ +#define FLASH_FLAG_CFGBSY FLASH_SR_CFGBSY /*!< FLASH Programming/erase configuration busy */ +#define FLASH_FLAG_PESD FLASH_SR_PESD /*!< FLASH Programming/erase operation suspended */ +#endif + +#define FLASH_FLAG_SR_ERRORS (FLASH_FLAG_OPERR | FLASH_FLAG_PROGERR | FLASH_FLAG_WRPERR | \ + FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR | FLASH_FLAG_PGSERR | \ + FLASH_FLAG_MISERR | FLASH_FLAG_FASTERR | FLASH_FLAG_RDERR | \ + FLASH_FLAG_OPTVERR) /*!< All SR error flags */ + +#define FLASH_FLAG_ECCC FLASH_ECCR_ECCC /*!< FLASH ECC correction */ +#define FLASH_FLAG_ECCD FLASH_ECCR_ECCD /*!< FLASH ECC detection */ + +#define FLASH_FLAG_ECCR_ERRORS (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD) + +#define FLASH_FLAG_ALL_ERRORS (FLASH_FLAG_SR_ERRORS | FLASH_FLAG_ECCR_ERRORS) + +/** @defgroup FLASH_INTERRUPT_DEFINITION FLASH Interrupts Definition + * @brief FLASH Interrupt definition + * @{ + */ +#define FLASH_IT_EOP FLASH_CR_EOPIE /*!< End of FLASH Operation Interrupt source */ +#define FLASH_IT_OPERR FLASH_CR_ERRIE /*!< Error Interrupt source */ +#define FLASH_IT_RDERR FLASH_CR_RDERRIE /*!< PCROP Read Error Interrupt source */ +#define FLASH_IT_ECCC (FLASH_ECCR_ECCCIE >> FLASH_ECCR_ECCCIE_Pos) /*!< ECC Correction Interrupt source */ +/** + * @} + */ + +/** @defgroup FLASH_ERROR FLASH Error + * @{ + */ +#define HAL_FLASH_ERROR_NONE 0x00000000U +#define HAL_FLASH_ERROR_OP FLASH_FLAG_OPERR +#define HAL_FLASH_ERROR_PROG FLASH_FLAG_PROGERR +#define HAL_FLASH_ERROR_WRP FLASH_FLAG_WRPERR +#define HAL_FLASH_ERROR_PGA FLASH_FLAG_PGAERR +#define HAL_FLASH_ERROR_SIZ FLASH_FLAG_SIZERR +#define HAL_FLASH_ERROR_PGS FLASH_FLAG_PGSERR +#define HAL_FLASH_ERROR_MIS FLASH_FLAG_MISERR +#define HAL_FLASH_ERROR_FAST FLASH_FLAG_FASTERR +#define HAL_FLASH_ERROR_RD FLASH_FLAG_RDERR +#define HAL_FLASH_ERROR_OPTV FLASH_FLAG_OPTVERR +/** + * @} + */ + +/** @defgroup FLASH_TYPE_ERASE FLASH Erase Type + * @{ + */ +#define FLASH_TYPEERASE_PAGES FLASH_CR_PER /*!< Pages erase only*/ +#define FLASH_TYPEERASE_MASSERASE FLASH_CR_MER /*!< Flash mass erase activation*/ +/** + * @} + */ + +/** @defgroup FLASH_TYPE_PROGRAM FLASH Program Type + * @{ + */ +#define FLASH_TYPEPROGRAM_DOUBLEWORD FLASH_CR_PG /*!< Program a double-word (64-bit) at a specified address.*/ +#define FLASH_TYPEPROGRAM_FAST FLASH_CR_FSTPG /*!< Fast program a 32 double-word (64-bit) row at a specified address. + And another 32 double-word (64-bit) row will be programmed */ +/** + * @} + */ + +/** @defgroup FLASH_OB_TYPE FLASH Option Bytes Type + * @{ + */ +#define OPTIONBYTE_WRP 0x00000001U /*!< WRP option byte configuration */ +#define OPTIONBYTE_RDP 0x00000002U /*!< RDP option byte configuration */ +#define OPTIONBYTE_USER 0x00000004U /*!< User option byte configuration */ +#define OPTIONBYTE_PCROP 0x00000008U /*!< PCROP option byte configuration */ +#if defined(DUAL_CORE) +#define OPTIONBYTE_IPCC_BUF_ADDR 0x00000010U /*!< IPCC mailbox buffer address configuration */ +#define OPTIONBYTE_C2_BOOT_VECT 0x00000100U /*!< CPU2 Secure Boot reset vector */ +#define OPTIONBYTE_SECURE_MODE 0x00000200U /*!< Secure mode on activated or not */ +#define OPTIONBYTE_C2_DEBUG_ACCESS 0x00000400U /*!< CPU2 debug access enabled or disabled */ +#define OPTIONBYTE_SUBGHZSPI_SECURE_ACCESS 0x00000800U /*!< Sub-GHz radio SPI security access enabled or disabled */ + +#define OPTIONBYTE_ALL (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | \ + OPTIONBYTE_PCROP | OPTIONBYTE_IPCC_BUF_ADDR | OPTIONBYTE_C2_BOOT_VECT | \ + OPTIONBYTE_SECURE_MODE | OPTIONBYTE_C2_DEBUG_ACCESS | OPTIONBYTE_SUBGHZSPI_SECURE_ACCESS) /*!< All option byte configuration */ +#else + +#define OPTIONBYTE_ALL (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | \ + OPTIONBYTE_PCROP) /*!< All option byte configuration */ +#endif /* DUAL_CORE */ + +/** + * @} + */ + +/** @defgroup FLASH_OB_WRP_AREA FLASH WRP Area + * @{ + */ +#define OB_WRPAREA_BANK1_AREAA 0x00000000U /*!< Flash Area A */ +#define OB_WRPAREA_BANK1_AREAB 0x00000001U /*!< Flash Area B */ +/** + * @} + */ + +/** @defgroup FLASH_OB_READ_PROTECTION FLASH Option Bytes Read Protection + * @{ + */ +#define OB_RDP_LEVEL_0 0x000000AAU +#define OB_RDP_LEVEL_1 0x000000BBU +#define OB_RDP_LEVEL_2 0x000000CCU /*!< Warning: When enabling read protection level 2 + it's no more possible to go back to level 1 or 0 */ +/** + * @} + */ + +/** @defgroup FLASH_OB_USER_TYPE FLASH Option Bytes User Type + * @{ + */ +#define OB_USER_BOR_LEV FLASH_OPTR_BOR_LEV /*!< BOR reset Level */ +#define OB_USER_nRST_STOP FLASH_OPTR_nRST_STOP /*!< Reset generated when entering the stop mode */ +#define OB_USER_nRST_STDBY FLASH_OPTR_nRST_STDBY /*!< Reset generated when entering the standby mode */ +#define OB_USER_nRST_SHDW FLASH_OPTR_nRST_SHDW /*!< Reset generated when entering the shutdown mode */ +#define OB_USER_IWDG_SW FLASH_OPTR_IWDG_SW /*!< Independent watchdog selection */ +#define OB_USER_IWDG_STOP FLASH_OPTR_IWDG_STOP /*!< Independent watchdog counter freeze in stop mode */ +#define OB_USER_IWDG_STDBY FLASH_OPTR_IWDG_STDBY /*!< Independent watchdog counter freeze in standby mode */ +#define OB_USER_WWDG_SW FLASH_OPTR_WWDG_SW /*!< Window watchdog selection */ +#define OB_USER_nBOOT1 FLASH_OPTR_nBOOT1 /*!< Boot configuration */ +#define OB_USER_SRAM2_PE FLASH_OPTR_SRAM2_PE /*!< SRAM2 parity check enable */ +#define OB_USER_SRAM_RST FLASH_OPTR_SRAM_RST /*!< SRAM1 and SRAM2 erase when system reset */ +#define OB_USER_nSWBOOT0 FLASH_OPTR_nSWBOOT0 /*!< Software BOOT0 */ +#define OB_USER_nBOOT0 FLASH_OPTR_nBOOT0 /*!< nBOOT0 option bit */ +#define OB_USER_BOOT_LOCK FLASH_OPTR_BOOT_LOCK /*!< CPU1 Boot Lock enable option bit */ +#if defined(DUAL_CORE) +#define OB_USER_C2BOOT_LOCK FLASH_OPTR_C2BOOT_LOCK /*!< CPU2 Boot Lock enable option bit */ +#endif + +#if defined(DUAL_CORE) +#define OB_USER_ALL (OB_USER_BOR_LEV | OB_USER_nRST_STOP | OB_USER_nRST_STDBY | \ + OB_USER_nRST_SHDW | OB_USER_IWDG_SW | OB_USER_IWDG_STOP | \ + OB_USER_IWDG_STDBY | OB_USER_WWDG_SW | OB_USER_nBOOT1 | \ + OB_USER_SRAM2_PE | OB_USER_SRAM_RST | OB_USER_nSWBOOT0 | \ + OB_USER_nBOOT0 | OB_USER_BOOT_LOCK | OB_USER_C2BOOT_LOCK) /*!< all option bits */ +#else +#define OB_USER_ALL (OB_USER_BOR_LEV | OB_USER_nRST_STOP | OB_USER_nRST_STDBY | \ + OB_USER_nRST_SHDW | OB_USER_IWDG_SW | OB_USER_IWDG_STOP | \ + OB_USER_IWDG_STDBY | OB_USER_WWDG_SW | OB_USER_nBOOT1 | \ + OB_USER_SRAM2_PE | OB_USER_SRAM_RST | OB_USER_nSWBOOT0 | \ + OB_USER_nBOOT0 | OB_USER_BOOT_LOCK) /*!< all option bits */ +#endif + +/** + * @} + */ + +/** @defgroup FLASH_OB_USER_BOR_LEVEL FLASH Option Bytes User BOR Level + * @{ + */ +#define OB_BOR_LEVEL_0 0x00000000U /*!< Reset level threshold is around 1.7V */ +#define OB_BOR_LEVEL_1 FLASH_OPTR_BOR_LEV_0 /*!< Reset level threshold is around 2.0V */ +#define OB_BOR_LEVEL_2 FLASH_OPTR_BOR_LEV_1 /*!< Reset level threshold is around 2.2V */ +#define OB_BOR_LEVEL_3 (FLASH_OPTR_BOR_LEV_0 | FLASH_OPTR_BOR_LEV_1) /*!< Reset level threshold is around 2.5V */ +#define OB_BOR_LEVEL_4 FLASH_OPTR_BOR_LEV_2 /*!< Reset level threshold is around 2.8V */ +/** + * @} + */ + +/** @defgroup FLASH_OB_USER_nRST_STOP FLASH Option Bytes User Reset On Stop + * @{ + */ +#define OB_STOP_RST 0x00000000U /*!< Reset generated when entering the stop mode */ +#define OB_STOP_NORST FLASH_OPTR_nRST_STOP /*!< No reset generated when entering the stop mode */ +/** + * @} + */ + +/** @defgroup FLASH_OB_USER_nRST_STANDBY FLASH Option Bytes User Reset On Standby + * @{ + */ +#define OB_STANDBY_RST 0x00000000U /*!< Reset generated when entering the standby mode */ +#define OB_STANDBY_NORST FLASH_OPTR_nRST_STDBY /*!< No reset generated when entering the standby mode */ +/** + * @} + */ + +/** @defgroup FLASH_OB_USER_nRST_SHUTDOWN FLASH Option Bytes User Reset On Shutdown + * @{ + */ +#define OB_SHUTDOWN_RST 0x00000000U /*!< Reset generated when entering the shutdown mode */ +#define OB_SHUTDOWN_NORST FLASH_OPTR_nRST_SHDW /*!< No reset generated when entering the shutdown mode */ +/** + * @} + */ + +/** @defgroup FLASH_OB_USER_IWDG_SW FLASH Option Bytes User IWDG Type + * @{ + */ +#define OB_IWDG_HW 0x00000000U /*!< Hardware independent watchdog */ +#define OB_IWDG_SW FLASH_OPTR_IWDG_SW /*!< Software independent watchdog */ +/** + * @} + */ + +/** @defgroup FLASH_OB_USER_IWDG_STOP FLASH Option Bytes User IWDG Mode On Stop + * @{ + */ +#define OB_IWDG_STOP_FREEZE 0x00000000U /*!< Independent watchdog counter is frozen in Stop mode */ +#define OB_IWDG_STOP_RUN FLASH_OPTR_IWDG_STOP /*!< Independent watchdog counter is running in Stop mode */ +/** + * @} + */ + +/** @defgroup FLASH_OB_USER_IWDG_STANDBY FLASH Option Bytes User IWDG Mode On Standby + * @{ + */ +#define OB_IWDG_STDBY_FREEZE 0x00000000U /*!< Independent watchdog counter is frozen in Standby mode */ +#define OB_IWDG_STDBY_RUN FLASH_OPTR_IWDG_STDBY /*!< Independent watchdog counter is running in Standby mode */ +/** + * @} + */ + +/** @defgroup FLASH_OB_USER_WWDG_SW FLASH Option Bytes User WWDG Type + * @{ + */ +#define OB_WWDG_HW 0x00000000U /*!< Hardware window watchdog */ +#define OB_WWDG_SW FLASH_OPTR_WWDG_SW /*!< Software window watchdog */ +/** + * @} + */ + +/** @defgroup FLASH_OB_USER_SRAM2_PE FLASH Option Bytes SRAM2 parity check + * @{ + */ +#define OB_SRAM2_PARITY_ENABLE 0x00000000U /*!< SRAM2 parity check enable */ +#define OB_SRAM2_PARITY_DISABLE FLASH_OPTR_SRAM2_PE /*!< SRAM2 parity check disable */ +/** + * @} + */ + +/** @defgroup FLASH_OB_USER_SRAM_RST FLASH Option Bytes SRAM1 and SRAM2 erase when system reset + * @{ + */ +#define OB_SRAM_RST_ERASE 0x00000000U /*!< SRAM2 and SRAM1 erased when a system reset */ +#define OB_SRAM_RST_NOT_ERASE FLASH_OPTR_SRAM_RST /*!< SRAM2 and SRAM1 is not erased when a system reset */ +/** + * @} + */ + +/** @defgroup FLASH_OB_USER_nBOOT1 FLASH Option Bytes User BOOT1 Type + * @{ + */ +#define OB_BOOT1_RESET 0x00000000U /*!< nBOOT1 = 0 */ +#define OB_BOOT1_SET FLASH_OPTR_nBOOT1 /*!< nBOOT1 = 1 */ +/** + * @} + */ + +/** @defgroup FLASH_OB_USER_nSWBOOT0 FLASH Option Bytes User Software BOOT0 + * @{ + */ +#define OB_BOOT0_FROM_OB 0x00000000U /*!< BOOT0 taken from the option bit nBOOT0 */ +#define OB_BOOT0_FROM_PIN FLASH_OPTR_nSWBOOT0 /*!< BOOT0 taken from PH3/BOOT0 pin */ +/** + * @} + */ + +/** @defgroup FLASH_OB_USER_nBOOT0 FLASH Option Bytes User nBOOT0 option bit + * @{ + */ +#define OB_BOOT0_RESET 0x00000000U /*!< nBOOT0 = 0 */ +#define OB_BOOT0_SET FLASH_OPTR_nBOOT0 /*!< nBOOT0 = 1 */ +/** + * @} + */ + +/** @defgroup FLASH_OB_USER_BOOT_LOCK FLASH Option Bytes CPU1 Boot Lock option bit + * @{ + */ +#define OB_BOOT_LOCK_DISABLE 0x00000000U /*!< BOOT_LOCK = 0 */ +#define OB_BOOT_LOCK_ENABLE FLASH_OPTR_BOOT_LOCK /*!< BOOT_LOCK = 1 */ +/** + * @} + */ + +#if defined(DUAL_CORE) +/** @defgroup FLASH_OB_USER_C2BOOT_LOCK FLASH Option Bytes CPU2 Boot Lock option bit + * @{ + */ +#define OB_C2BOOT_LOCK_DISABLE 0x00000000U /*!< C2BOOT_LOCK = 0 */ +#define OB_C2BOOT_LOCK_ENABLE FLASH_OPTR_C2BOOT_LOCK /*!< C2BOOT_LOCK = 1 */ +/** + * @} + */ +#endif /* DUAL_CORE */ + +/** @defgroup FLASH_OB_PCROP_ZONE FLASH PCROP ZONE + * @{ + */ +#define OB_PCROP_ZONE_A 0x00000001U /*!< PCROP Zone A */ +#define OB_PCROP_ZONE_B 0x00000002U /*!< PCROP Zone B */ +/** + * @} + */ + +/** @defgroup FLASH_OB_PCROP_RDP FLASH Option Bytes PCROP On RDP Level Type + * @{ + */ +#define OB_PCROP_RDP_NOT_ERASE 0x00000000U /*!< PCROP area is not erased when the RDP level + is decreased from Level 1 to Level 0 */ +#define OB_PCROP_RDP_ERASE FLASH_PCROP1AER_PCROP_RDP /*!< PCROP area is erased when the RDP level is + decreased from Level 1 to Level 0 (full mass erase) */ +/** + * @} + */ + +#if defined(DUAL_CORE) +/** @defgroup FLASH_OB_SECURITY_MODE Option Bytes FLASH Secure mode + * @{ + */ +#define OB_SECURE_SYSTEM_AND_FLASH_ENABLE 0x00000001U /*!< Flash and System secure area enabled */ +#define OB_SECURE_HIDE_PROTECTION_ENABLE 0x00000002U /*!< Hide Protection area enabled */ +#define OB_SECURE_SRAM1_ENABLE 0x00000004U /*!< SRAM1 area enabled */ +#define OB_SECURE_SRAM2_ENABLE 0x00000008U /*!< SRAM2 area enabled */ +#define OB_SECURE_SYSTEM_AND_FLASH_DISABLE 0x00000010U /*!< Flash and System secure area disabled */ +#define OB_SECURE_HIDE_PROTECTION_DISABLE 0x00000020U /*!< Hide Protection area disabled */ +#define OB_SECURE_SRAM1_DISABLE 0x00000040U /*!< SRAM1 area disabled */ +#define OB_SECURE_SRAM2_DISABLE 0x00000080U /*!< SRAM2 area disabled */ +#define OB_SECURE_SYSTEM_AND_ALL_AREAS_ENABLE (OB_SECURE_SYSTEM_AND_FLASH_ENABLE | OB_SECURE_HIDE_PROTECTION_ENABLE | \ + OB_SECURE_SRAM1_ENABLE | OB_SECURE_SRAM2_ENABLE) /*!< All System in Secure mode : Security enabled on all areas */ +#define OB_SECURE_SYSTEM_AND_ALL_AREAS_DISABLE (OB_SECURE_SYSTEM_AND_FLASH_DISABLE | OB_SECURE_HIDE_PROTECTION_DISABLE | \ + OB_SECURE_SRAM1_DISABLE | OB_SECURE_SRAM2_DISABLE) /*!< Unsecure mode: Security disabled */ +/** + * @} + */ + +/** @defgroup FLASH_OB_SUBGHZSPI_SECURE_ACCESS Option Bytes Sub-GHz radio SPI Secure Access + * @{ + */ +#define OB_SUBGHZSPI_SECURE_ACCESS_DISABLE FLASH_SFR_SUBGHZSPISD /*!< Sub-GHz radio SPI Secure access disabled */ +#define OB_SUBGHZSPI_SECURE_ACCESS_ENABLE 0x00000000U /*!< Sub-GHz radio SPI Secure access enabled */ +/** + * @} + */ + +/** @defgroup FLASH_OB_C2_DEBUG_ACCESS Option Bytes CPU2 Debug Access + * @{ + */ +#define OB_C2_DEBUG_ACCESS_DISABLE FLASH_SFR_DDS /*!< CPU2 debug access disabled */ +#define OB_C2_DEBUG_ACCESS_ENABLE 0x00000000U /*!< CPU2 debug access enabled (when also enabled by FLASH_ACR2_C2SWDBGEN) */ +/** + * @} + */ + +/** @defgroup FLASH_OB_C2_BOOT_REGION CPU2 Option Bytes Reset Boot Vector + * @{ + */ +#define OB_C2_BOOT_FROM_SRAM 0x00000000U /*!< CPU2 boot from SRAM1 or SRAM2 */ +#define OB_C2_BOOT_FROM_FLASH FLASH_SRRVR_C2OPT /*!< CPU2 boot from Flash */ +/** + * @} + */ +#endif /* DUAL_CORE */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup FLASH_Exported_Macros FLASH Exported Macros + * @brief macros to control FLASH features + * @{ + */ + +/** + * @brief Set the FLASH Latency. + * @param __LATENCY__ FLASH Latency + * This parameter can be one of the following values : + * @arg @ref FLASH_LATENCY_0 FLASH Zero wait state + * @arg @ref FLASH_LATENCY_1 FLASH One wait state + * @arg @ref FLASH_LATENCY_2 FLASH Two wait states + * @retval None + */ +#define __HAL_FLASH_SET_LATENCY(__LATENCY__) MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (__LATENCY__)) + +/** + * @brief Get the FLASH Latency. + * @retval FLASH Latency + * Returned value can be one of the following values : + * @arg @ref FLASH_LATENCY_0 FLASH Zero wait state + * @arg @ref FLASH_LATENCY_1 FLASH One wait state + * @arg @ref FLASH_LATENCY_2 FLASH Two wait states + */ +#define __HAL_FLASH_GET_LATENCY() READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY) + +/** + * @brief Enable the FLASH prefetch buffer. + * @retval None + */ +#ifdef CORE_CM0PLUS +#define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() SET_BIT(FLASH->C2ACR, FLASH_C2ACR_PRFTEN) +#else +#define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) +#endif + +/** + * @brief Disable the FLASH prefetch buffer. + * @retval None + */ +#ifdef CORE_CM0PLUS +#define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() CLEAR_BIT(FLASH->C2ACR, FLASH_C2ACR_PRFTEN) +#else +#define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) +#endif + +/** + * @brief Enable the FLASH instruction cache. + * @retval none + */ +#ifdef CORE_CM0PLUS +#define __HAL_FLASH_INSTRUCTION_CACHE_ENABLE() SET_BIT(FLASH->C2ACR, FLASH_C2ACR_ICEN) +#else +#define __HAL_FLASH_INSTRUCTION_CACHE_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_ICEN) +#endif + +/** + * @brief Disable the FLASH instruction cache. + * @retval none + */ +#ifdef CORE_CM0PLUS +#define __HAL_FLASH_INSTRUCTION_CACHE_DISABLE() CLEAR_BIT(FLASH->C2ACR, FLASH_C2ACR_ICEN) +#else +#define __HAL_FLASH_INSTRUCTION_CACHE_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICEN) +#endif + +/** + * @brief Enable the FLASH data cache. + * @retval none + */ +#ifdef CORE_CM0PLUS +#else +#define __HAL_FLASH_DATA_CACHE_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_DCEN) +#endif + +/** + * @brief Disable the FLASH data cache. + * @retval none + */ +#ifdef CORE_CM0PLUS +#else +#define __HAL_FLASH_DATA_CACHE_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCEN) +#endif + +/** + * @brief Reset the FLASH instruction Cache. + * @note This function must be used only when the Instruction Cache is disabled. + * @retval None + */ +#ifdef CORE_CM0PLUS +#define __HAL_FLASH_INSTRUCTION_CACHE_RESET() do { SET_BIT(FLASH->C2ACR, FLASH_C2ACR_ICRST); \ + CLEAR_BIT(FLASH->C2ACR, FLASH_C2ACR_ICRST); \ + } while (0) +#else +#define __HAL_FLASH_INSTRUCTION_CACHE_RESET() do { SET_BIT(FLASH->ACR, FLASH_ACR_ICRST); \ + CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICRST); \ + } while (0) +#endif + +/** + * @brief Reset the FLASH data Cache. + * @note This function must be used only when the data Cache is disabled. + * @retval None + */ +#ifdef CORE_CM0PLUS +#else +#define __HAL_FLASH_DATA_CACHE_RESET() do { SET_BIT(FLASH->ACR, FLASH_ACR_DCRST); \ + CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCRST); \ + } while (0) +#endif + +/** + * @} + */ + +/** @defgroup FLASH_Interrupt FLASH Interrupts Macros + * @brief macros to handle FLASH interrupts + * @{ + */ + +/** + * @brief Enable the specified FLASH interrupt. + * @param __INTERRUPT__ FLASH interrupt + * This parameter can be any combination of the following values: + * @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt + * @arg @ref FLASH_IT_OPERR Error Interrupt + * @arg @ref FLASH_IT_RDERR PCROP Read Error Interrupt + * @arg @ref FLASH_IT_ECCC ECC Correction Interrupt + * @retval none + */ +#ifdef CORE_CM0PLUS +#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) { SET_BIT(FLASH->ECCR, FLASH_ECCR_ECCCIE); }\ + if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) { SET_BIT(FLASH->C2CR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\ + } while(0) +#else +#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) { SET_BIT(FLASH->ECCR, FLASH_ECCR_ECCCIE); }\ + if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) { SET_BIT(FLASH->CR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\ + } while(0) +#endif + +/** + * @brief Disable the specified FLASH interrupt. + * @param __INTERRUPT__ FLASH interrupt + * This parameter can be any combination of the following values: + * @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt + * @arg @ref FLASH_IT_OPERR Error Interrupt + * @arg @ref FLASH_IT_RDERR PCROP Read Error Interrupt + * @arg @ref FLASH_IT_ECCC ECC Correction Interrupt + * @retval none + */ +#ifdef CORE_CM0PLUS +#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) { CLEAR_BIT(FLASH->ECCR, FLASH_ECCR_ECCCIE); }\ + if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) { CLEAR_BIT(FLASH->C2CR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\ + } while(0) +#else +#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) { CLEAR_BIT(FLASH->ECCR, FLASH_ECCR_ECCCIE); }\ + if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) { CLEAR_BIT(FLASH->CR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\ + } while(0) +#endif + +/** + * @brief Check whether the specified FLASH flag is set or not. + * @param __FLAG__ specifies the FLASH flag to check. + * This parameter can be one of the following values: + * @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag + * @arg @ref FLASH_FLAG_OPERR FLASH Operation error flag + * @arg @ref FLASH_FLAG_PROGERR FLASH Programming error flag + * @arg @ref FLASH_FLAG_WRPERR FLASH Write protection error flag + * @arg @ref FLASH_FLAG_PGAERR FLASH Programming alignment error flag + * @arg @ref FLASH_FLAG_SIZERR FLASH Size error flag + * @arg @ref FLASH_FLAG_PGSERR FLASH Programming sequence error flag + * @arg @ref FLASH_FLAG_MISERR FLASH Fast programming data miss error flag + * @arg @ref FLASH_FLAG_FASTERR FLASH Fast programming error flag + * @arg @ref FLASH_FLAG_OPTNV FLASH User Option OPTVAL indication + * @arg @ref FLASH_FLAG_RDERR FLASH PCROP read error flag + * @arg @ref FLASH_FLAG_OPTVERR FLASH Option validity error flag + * @arg @ref FLASH_FLAG_BSY FLASH write/erase operations in progress flag + * @arg @ref FLASH_FLAG_CFGBSY Programming/erase configuration busy + * @arg @ref FLASH_FLAG_PESD FLASH Programming/erase operation suspended + * @arg @ref FLASH_FLAG_ECCC FLASH one ECC error has been detected and corrected + * @arg @ref FLASH_FLAG_ECCD FLASH two ECC errors have been detected + * @retval The new state of FLASH_FLAG (SET or RESET). + */ +#ifdef CORE_CM0PLUS +#define __HAL_FLASH_GET_FLAG(__FLAG__) ((((__FLAG__) & (FLASH_FLAG_ECCR_ERRORS)) != 0U) ? \ + (READ_BIT(FLASH->ECCR, (__FLAG__)) == (__FLAG__)) : \ + ((((__FLAG__) & FLASH_FLAG_OPTVERR) != 0U) ? \ + (READ_BIT(FLASH->SR, (__FLAG__)) == (__FLAG__)) : \ + (READ_BIT(FLASH->C2SR, (__FLAG__)) == (__FLAG__)))) +#else +#define __HAL_FLASH_GET_FLAG(__FLAG__) ((((__FLAG__) & (FLASH_FLAG_ECCR_ERRORS)) != 0U) ? \ + (READ_BIT(FLASH->ECCR, (__FLAG__)) == (__FLAG__)) : \ + (READ_BIT(FLASH->SR, (__FLAG__)) == (__FLAG__))) +#endif +/** + * @brief Clear the FLASH's pending flags. + * @param __FLAG__ specifies the FLASH flags to clear. + * This parameter can be any combination of the following values: + * @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag + * @arg @ref FLASH_FLAG_OPERR FLASH Operation error flag + * @arg @ref FLASH_FLAG_PROGERR FLASH Programming error flag + * @arg @ref FLASH_FLAG_WRPERR FLASH Write protection error flag + * @arg @ref FLASH_FLAG_PGAERR FLASH Programming alignment error flag + * @arg @ref FLASH_FLAG_SIZERR FLASH Size error flag + * @arg @ref FLASH_FLAG_PGSERR FLASH Programming sequence error flag + * @arg @ref FLASH_FLAG_MISERR FLASH Fast programming data miss error flag + * @arg @ref FLASH_FLAG_FASTERR FLASH Fast programming error flag + * @arg @ref FLASH_FLAG_RDERR FLASH PCROP read error flag + * @arg @ref FLASH_FLAG_OPTVERR FLASH Option validity error flag + * @arg @ref FLASH_FLAG_ECCC FLASH one ECC error has been detected and corrected + * @arg @ref FLASH_FLAG_ECCD FLASH two ECC errors have been detected + * @arg @ref FLASH_FLAG_SR_ERRORS FLASH All SR errors flags + * @arg @ref FLASH_FLAG_ECCR_ERRORS FLASH All ECCR errors flags + * @arg @ref FLASH_FLAG_ALL_ERRORS FLASH All errors flags + * @retval None + */ +#ifdef CORE_CM0PLUS +#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) do { if(((__FLAG__) & (FLASH_FLAG_ECCR_ERRORS)) != 0U) { SET_BIT(FLASH->ECCR, ((__FLAG__) & (FLASH_FLAG_ECCR_ERRORS))); }\ + if(((__FLAG__) & FLASH_FLAG_OPTVERR) != 0U) { SET_BIT(FLASH->SR, FLASH_FLAG_OPTVERR); }\ + if(((__FLAG__) & ~(FLASH_FLAG_ECCR_ERRORS)) != 0U) { WRITE_REG(FLASH->C2SR, ((__FLAG__) & ~(FLASH_FLAG_ECCR_ERRORS))); }\ + } while(0) +#else +#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) do { if(((__FLAG__) & (FLASH_FLAG_ECCR_ERRORS)) != 0U) { SET_BIT(FLASH->ECCR, ((__FLAG__) & (FLASH_FLAG_ECCR_ERRORS))); }\ + if(((__FLAG__) & ~(FLASH_FLAG_ECCR_ERRORS)) != 0U) { WRITE_REG(FLASH->SR, ((__FLAG__) & ~(FLASH_FLAG_ECCR_ERRORS))); }\ + } while(0) +#endif +/** + * @} + */ + +/* Include FLASH HAL Extended module */ +#include "stm32wlxx_hal_flash_ex.h" +/* Exported variables --------------------------------------------------------*/ +/** @defgroup FLASH_Exported_Variables FLASH Exported Variables + * @{ + */ +extern FLASH_ProcessTypeDef pFlash; +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup FLASH_Exported_Functions + * @{ + */ + +/* Program operation functions ***********************************************/ +/** @addtogroup FLASH_Exported_Functions_Group1 + * @{ + */ +HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data); +HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data); +/* FLASH IRQ handler method */ +void HAL_FLASH_IRQHandler(void); +/* Callbacks in non blocking modes */ +void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue); +void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue); +/** + * @} + */ + +/* Peripheral Control functions **********************************************/ +/** @addtogroup FLASH_Exported_Functions_Group2 + * @{ + */ +HAL_StatusTypeDef HAL_FLASH_Unlock(void); +HAL_StatusTypeDef HAL_FLASH_Lock(void); +/* Option bytes control */ +HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void); +HAL_StatusTypeDef HAL_FLASH_OB_Lock(void); +HAL_StatusTypeDef HAL_FLASH_OB_Launch(void); +/** + * @} + */ + +/* Peripheral State functions ************************************************/ +/** @addtogroup FLASH_Exported_Functions_Group3 + * @{ + */ +uint32_t HAL_FLASH_GetError(void); +/** + * @} + */ + +/** + * @} + */ + +/* Private types --------------------------------------------------------*/ +/** @defgroup FLASH_Private_types FLASH Private Types + * @{ + */ +HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); +/** + * @} + */ + +/* Private constants --------------------------------------------------------*/ +/** @defgroup FLASH_Private_Constants FLASH Private Constants + * @{ + */ +#define FLASH_END_ADDR (FLASH_BASE + FLASH_SIZE - 1U) + +#define FLASH_BANK_SIZE FLASH_SIZE /*!< FLASH Bank Size */ +#define FLASH_PAGE_SIZE 0x00000800U /*!< FLASH Page Size, 2 KBytes */ +#define FLASH_PAGE_NB 128U +#define FLASH_TIMEOUT_VALUE 1000U /*!< FLASH Execution Timeout, 1 s */ + +#define FLASH_PCROP_GRANULARITY_OFFSET 10U /*!< FLASH Code Readout Protection granularity offset */ +#define FLASH_PCROP_GRANULARITY (1UL << FLASH_PCROP_GRANULARITY_OFFSET) /*!< FLASH Code Readout Protection granularity, 1 KBytes */ + +#define FLASH_TYPENONE 0x00000000U /*!< No Programmation Procedure On Going */ + +/** @defgroup SRAM_MEMORY_SIZE SRAM memory size + * @{ + */ +#define SRAM_SECURE_PAGE_GRANULARITY_OFFSET 10U /*!< Secure SRAM1 and SRAM2 Protection granularity offset */ +#define SRAM_SECURE_PAGE_GRANULARITY (1UL << FLASH_PCROP_GRANULARITY_OFFSET) /*!< Secure SRAM1 and SRAM2 Protection granularity, 1KBytes */ +/** + * @} + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup FLASH_Private_Macros FLASH Private Macros + * @{ + */ +#define IS_FLASH_MAIN_MEM_ADDRESS(__VALUE__) (((__VALUE__) >= FLASH_BASE) &&\ + ((__VALUE__) <= (FLASH_BASE + FLASH_SIZE - 1UL))) + +#define IS_FLASH_FAST_PROGRAM_ADDRESS(__VALUE__) (((__VALUE__) >= FLASH_BASE) &&\ + ((__VALUE__) <= (FLASH_BASE + FLASH_SIZE - 256UL)) && (((__VALUE__) % 256UL) == 0UL)) + +#define IS_FLASH_PROGRAM_MAIN_MEM_ADDRESS(__VALUE__) (((__VALUE__) >= FLASH_BASE) &&\ + ((__VALUE__) <= (FLASH_BASE + FLASH_SIZE - 8UL)) && (((__VALUE__) % 8UL) == 0UL)) + +#define IS_FLASH_PROGRAM_OTP_ADDRESS(__VALUE__) (((__VALUE__) >= OTP_AREA_BASE) &&\ + ((__VALUE__) <= (OTP_AREA_END_ADDR + 1UL - 8UL)) && (((__VALUE__) % 8UL) == 0UL)) + +#define IS_FLASH_PROGRAM_ADDRESS(__VALUE__) (IS_FLASH_PROGRAM_MAIN_MEM_ADDRESS(__VALUE__) ||\ + IS_FLASH_PROGRAM_OTP_ADDRESS(__VALUE__)) + +#define IS_FLASH_PAGE(__VALUE__) ((__VALUE__) < FLASH_PAGE_NB) + +#define IS_ADDR_ALIGNED_64BITS(__VALUE__) (((__VALUE__) & 0x7U) == (0x00UL)) + +#define IS_FLASH_TYPEERASE(__VALUE__) (((__VALUE__) == FLASH_TYPEERASE_PAGES) || \ + ((__VALUE__) == FLASH_TYPEERASE_MASSERASE)) + +#define IS_FLASH_TYPEPROGRAM(__VALUE__) (((__VALUE__) == FLASH_TYPEPROGRAM_DOUBLEWORD) || \ + ((__VALUE__) == FLASH_TYPEPROGRAM_FAST)) + +#if defined(DUAL_CORE) +#define IS_OB_SFSA_START_ADDR(__VALUE__) (((__VALUE__) >= FLASH_BASE) &&\ + ((__VALUE__) <= FLASH_END_ADDR) && (((__VALUE__) & ~0x7FFU) == (__VALUE__))) +#define IS_OB_HDPSA_START_ADDR(__VALUE__) IS_OB_SFSA_START_ADDR(__VALUE__) +#define IS_OB_SBRSA_START_ADDR(__VALUE__) (((__VALUE__) >= SRAM2_BASE) &&\ + ((__VALUE__) <= (SRAM2_BASE + SRAM2_SIZE)) && (((__VALUE__) & ~0x3FFU) == (__VALUE__))) +#define IS_OB_SNBRSA_START_ADDR(__VALUE__) (((__VALUE__) >= SRAM1_BASE) &&\ + ((__VALUE__) <= (SRAM1_BASE + SRAM1_SIZE)) && (((__VALUE__) & ~0x3FFU) == (__VALUE__))) + +#define IS_OB_SECURE_MODE(__VALUE__) ( (((__VALUE__) & (OB_SECURE_SYSTEM_AND_ALL_AREAS_ENABLE | OB_SECURE_SYSTEM_AND_ALL_AREAS_DISABLE)) != 0U) && \ + (((__VALUE__) & ~(OB_SECURE_SYSTEM_AND_ALL_AREAS_ENABLE | OB_SECURE_SYSTEM_AND_ALL_AREAS_DISABLE)) == 0U) && \ + (((__VALUE__) & (OB_SECURE_SYSTEM_AND_FLASH_ENABLE | OB_SECURE_SYSTEM_AND_FLASH_DISABLE)) != (OB_SECURE_SYSTEM_AND_FLASH_ENABLE | OB_SECURE_SYSTEM_AND_FLASH_DISABLE)) && \ + (((__VALUE__) & (OB_SECURE_HIDE_PROTECTION_ENABLE | OB_SECURE_HIDE_PROTECTION_DISABLE)) != (OB_SECURE_HIDE_PROTECTION_ENABLE | OB_SECURE_HIDE_PROTECTION_DISABLE)) && \ + (((__VALUE__) & (OB_SECURE_SRAM1_ENABLE | OB_SECURE_SRAM1_DISABLE)) != (OB_SECURE_SRAM1_ENABLE | OB_SECURE_SRAM1_DISABLE)) && \ + (((__VALUE__) & (OB_SECURE_SRAM2_ENABLE | OB_SECURE_SRAM2_DISABLE)) != (OB_SECURE_SRAM2_ENABLE | OB_SECURE_SRAM2_DISABLE)) ) +#endif /* DUAL_CORE */ + +#if defined(DUAL_CORE) +#define IS_OPTIONBYTE(__VALUE__) ((__VALUE__) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_PCROP | \ + OPTIONBYTE_IPCC_BUF_ADDR | OPTIONBYTE_C2_BOOT_VECT | OPTIONBYTE_SECURE_MODE | \ + OPTIONBYTE_C2_DEBUG_ACCESS | OPTIONBYTE_SUBGHZSPI_SECURE_ACCESS)) + +#else + +#define IS_OPTIONBYTE(__VALUE__) ((__VALUE__) <= (OPTIONBYTE_WRP |\ + OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_PCROP)) +#endif /* DUAL_CORE */ + +#define IS_OB_WRPAREA(__VALUE__) (((__VALUE__) == OB_WRPAREA_BANK1_AREAA) ||\ + ((__VALUE__) == OB_WRPAREA_BANK1_AREAB)) + +#define IS_OB_RDP_LEVEL(__VALUE__) (((__VALUE__) == OB_RDP_LEVEL_0) ||\ + ((__VALUE__) == OB_RDP_LEVEL_1) ||\ + ((__VALUE__) == OB_RDP_LEVEL_2)) + +#define IS_OB_USER_TYPE(__VALUE__) ((((__VALUE__) & OB_USER_ALL) != 0U) && \ + (((__VALUE__) & ~OB_USER_ALL) == 0U)) + +#define IS_OB_USER_CONFIG(__TYPE__, __VALUE__) ((((__TYPE__) & OB_USER_BOR_LEV) == OB_USER_BOR_LEV) \ + ? ((((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_BOR_LEV)) == OB_BOR_LEVEL_0) || \ + (((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_BOR_LEV)) == OB_BOR_LEVEL_1) || \ + (((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_BOR_LEV)) == OB_BOR_LEVEL_2) || \ + (((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_BOR_LEV)) == OB_BOR_LEVEL_3) || \ + (((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_BOR_LEV)) == OB_BOR_LEVEL_4)) \ + : ((~(__TYPE__) & (__VALUE__)) == 0U)) + +#define IS_OB_USER_BOR_LEVEL(__VALUE__) (((__VALUE__) == OB_BOR_LEVEL_0) || ((__VALUE__) == OB_BOR_LEVEL_1) || \ + ((__VALUE__) == OB_BOR_LEVEL_2) || ((__VALUE__) == OB_BOR_LEVEL_3) || \ + ((__VALUE__) == OB_BOR_LEVEL_4)) + +#define IS_OB_PCROP_CONFIG(__VALUE__) (((__VALUE__) &\ + ~(OB_PCROP_ZONE_A | OB_PCROP_ZONE_B | OB_PCROP_RDP_ERASE)) == 0U) + +#if defined(DUAL_CORE) +#define IS_OB_IPCC_BUF_ADDR(__VALUE__) (IS_OB_SBRSA_START_ADDR(__VALUE__) ||\ + IS_OB_SNBRSA_START_ADDR(__VALUE__)) + +#define IS_OB_BOOT_VECTOR_ADDR(__VALUE__) (IS_OB_SFSA_START_ADDR(__VALUE__) ||\ + IS_OB_SBRSA_START_ADDR(__VALUE__) || IS_OB_SNBRSA_START_ADDR(__VALUE__)) +#define IS_OB_BOOT_REGION(__VALUE__) (((__VALUE__) == OB_C2_BOOT_FROM_FLASH) ||\ + ((__VALUE__) == OB_C2_BOOT_FROM_SRAM)) + +#define IS_OB_SUBGHZSPI_SECURE_ACCESS(__VALUE__) (((__VALUE__) == OB_SUBGHZSPI_SECURE_ACCESS_ENABLE) ||\ + ((__VALUE__) == OB_SUBGHZSPI_SECURE_ACCESS_DISABLE)) + +#define IS_OB_C2_DEBUG_MODE(__VALUE__) (((__VALUE__) == OB_C2_DEBUG_ACCESS_ENABLE) ||\ + ((__VALUE__) == OB_C2_DEBUG_ACCESS_DISABLE)) +#endif /* DUAL_CORE */ + +#define IS_FLASH_LATENCY(__VALUE__) (((__VALUE__) == FLASH_LATENCY_0) || \ + ((__VALUE__) == FLASH_LATENCY_1) || \ + ((__VALUE__) == FLASH_LATENCY_2)) + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32WLxx_HAL_FLASH_H */ + diff --git a/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h b/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h new file mode 100644 index 0000000..06cffff --- /dev/null +++ b/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h @@ -0,0 +1,133 @@ +/** + ****************************************************************************** + * @file stm32wlxx_hal_flash_ex.h + * @author MCD Application Team + * @brief Header file of FLASH HAL Extended module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32WLxx_HAL_FLASH_EX_H +#define STM32WLxx_HAL_FLASH_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wlxx_hal_def.h" + +/** @addtogroup STM32WLxx_HAL_Driver + * @{ + */ + +/** @addtogroup FLASHEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup FLASHEx_Exported_Constants FLASH Exported Constants + * @{ + */ +/** @defgroup FLASHEx_EMPTY_CHECK FLASHEx Empty Check + * @{ + */ +#define FLASH_PROG_NOT_EMPTY 0x00000000U /*!< 1st location in Flash is programmed */ +#define FLASH_PROG_EMPTY FLASH_ACR_EMPTY /*!< 1st location in Flash is empty */ +/** + * @} + */ + +/** @defgroup FLASHEx_PRIV_MODE_CFG FLASHEx privilege mode configuration + * @{ + */ +#define FLASH_PRIV_GRANTED 0x00000000U /*!< access to Flash registers is granted */ +#define FLASH_PRIV_DENIED FLASH_ACR2_PRIVMODE /*!< access to Flash registers is denied to non-privilege access */ +/** + * @} + */ +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup FLASHEx_Exported_Functions + * @{ + */ + +/* Extended Program operation functions *************************************/ +/** @addtogroup FLASHEx_Exported_Functions_Group1 + * @{ + */ +HAL_StatusTypeDef HAL_FLASHEx_Erase(const FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError); +HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit); +uint32_t HAL_FLASHEx_FlashEmptyCheck(void); +void HAL_FLASHEx_ForceFlashEmpty(uint32_t FlashEmpty); +HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit); +void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit); +void HAL_FLASHEx_SuspendOperation(void); +void HAL_FLASHEx_AllowOperation(void); +uint32_t HAL_FLASHEx_IsOperationSuspended(void); +#if defined(DUAL_CORE) +void HAL_FLASHEx_DisableC2Debug(void); +void HAL_FLASHEx_EnableC2Debug(void); +void HAL_FLASHEx_EnableSecHideProtection(void); +void HAL_FLASHEx_ConfigPrivMode(uint32_t PrivMode); +uint32_t HAL_FLASHEx_GetPrivMode(void); +#endif /* DUAL_CORE */ +/** + * @} + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup FLASHEx_Private_Macros FLASHEx Private Macros + * @{ + */ +#define IS_FLASH_EMPTY_CHECK(__VALUE__) (((__VALUE__) == FLASH_PROG_EMPTY) ||\ + ((__VALUE__) == FLASH_PROG_NOT_EMPTY)) + +#define IS_FLASH_CFGPRIVMODE(__VALUE__) (((__VALUE__) == FLASH_PRIV_GRANTED) ||\ + ((__VALUE__) == FLASH_PRIV_DENIED)) +/** + * @} + */ + +/* Private Functions ---------------------------------------------------------*/ +/** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions + * @{ + */ +void FLASH_PageErase(uint32_t Page); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32WLxx_HAL_FLASH_EX_H */ + diff --git a/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h b/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h new file mode 100644 index 0000000..5c5112f --- /dev/null +++ b/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h @@ -0,0 +1,327 @@ +/** + ****************************************************************************** + * @file stm32wlxx_hal_gpio.h + * @author MCD Application Team + * @brief Header file of GPIO HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32WLxx_HAL_GPIO_H +#define STM32WLxx_HAL_GPIO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wlxx_hal_def.h" + +/** @addtogroup STM32WLxx_HAL_Driver + * @{ + */ + +/** @defgroup GPIO GPIO + * @brief GPIO HAL module driver + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup GPIO_Exported_Types GPIO Exported Types + * @{ + */ +/** + * @brief GPIO Init structure definition + */ +typedef struct +{ + uint32_t Pin; /*!< Specifies the GPIO pins to be configured. + This parameter can be any value of @ref GPIO_pins */ + + uint32_t Mode; /*!< Specifies the operating mode for the selected pins. + This parameter can be a value of @ref GPIO_mode */ + + uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins. + This parameter can be a value of @ref GPIO_pull */ + + uint32_t Speed; /*!< Specifies the speed for the selected pins. + This parameter can be a value of @ref GPIO_speed */ + + uint32_t Alternate; /*!< Peripheral to be connected to the selected pins + This parameter can be a value of @ref GPIOEx_Alternate_function_selection */ +} GPIO_InitTypeDef; + +/** + * @brief GPIO Bit SET and Bit RESET enumeration + */ +typedef enum +{ + GPIO_PIN_RESET = 0U, + GPIO_PIN_SET +} GPIO_PinState; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup GPIO_Exported_Constants GPIO Exported Constants + * @{ + */ +/** @defgroup GPIO_pins GPIO pins + * @{ + */ +#define GPIO_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */ +#define GPIO_PIN_1 ((uint16_t)0x0002) /* Pin 1 selected */ +#define GPIO_PIN_2 ((uint16_t)0x0004) /* Pin 2 selected */ +#define GPIO_PIN_3 ((uint16_t)0x0008) /* Pin 3 selected */ +#define GPIO_PIN_4 ((uint16_t)0x0010) /* Pin 4 selected */ +#define GPIO_PIN_5 ((uint16_t)0x0020) /* Pin 5 selected */ +#define GPIO_PIN_6 ((uint16_t)0x0040) /* Pin 6 selected */ +#define GPIO_PIN_7 ((uint16_t)0x0080) /* Pin 7 selected */ +#define GPIO_PIN_8 ((uint16_t)0x0100) /* Pin 8 selected */ +#define GPIO_PIN_9 ((uint16_t)0x0200) /* Pin 9 selected */ +#define GPIO_PIN_10 ((uint16_t)0x0400) /* Pin 10 selected */ +#define GPIO_PIN_11 ((uint16_t)0x0800) /* Pin 11 selected */ +#define GPIO_PIN_12 ((uint16_t)0x1000) /* Pin 12 selected */ +#define GPIO_PIN_13 ((uint16_t)0x2000) /* Pin 13 selected */ +#define GPIO_PIN_14 ((uint16_t)0x4000) /* Pin 14 selected */ +#define GPIO_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */ +#define GPIO_PIN_All ((uint16_t)0xFFFF) /* All pins selected */ + +#define GPIO_PIN_MASK (0x0000FFFFu) /* PIN mask for assert test */ +/** + * @} + */ + +/** @defgroup GPIO_mode GPIO mode + * @brief GPIO Configuration Mode + * Elements values convention: 0x00WX00YZ + * - W : EXTI trigger detection on 3 bits + * - X : EXTI mode (IT or Event) on 2 bits + * - Y : Output type (Push Pull or Open Drain) on 1 bit + * - Z : GPIO mode (Input, Output, Alternate or Analog) on 2 bits + * @{ + */ +#define GPIO_MODE_INPUT MODE_INPUT /*!< Input Floating Mode */ +#define GPIO_MODE_OUTPUT_PP (MODE_OUTPUT | OUTPUT_PP) /*!< Output Push Pull Mode */ +#define GPIO_MODE_OUTPUT_OD (MODE_OUTPUT | OUTPUT_OD) /*!< Output Open Drain Mode */ +#define GPIO_MODE_AF_PP (MODE_AF | OUTPUT_PP) /*!< Alternate Function Push Pull Mode */ +#define GPIO_MODE_AF_OD (MODE_AF | OUTPUT_OD) /*!< Alternate Function Open Drain Mode */ +#define GPIO_MODE_ANALOG MODE_ANALOG /*!< Analog Mode */ +#define GPIO_MODE_IT_RISING (MODE_INPUT | EXTI_IT | TRIGGER_RISING) /*!< External Interrupt Mode with Rising edge trigger detection */ +#define GPIO_MODE_IT_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_FALLING) /*!< External Interrupt Mode with Falling edge trigger detection */ +#define GPIO_MODE_IT_RISING_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_RISING | TRIGGER_FALLING) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ +#define GPIO_MODE_EVT_RISING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING) /*!< External Event Mode with Rising edge trigger detection */ +#define GPIO_MODE_EVT_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_FALLING) /*!< External Event Mode with Falling edge trigger detection */ +#define GPIO_MODE_EVT_RISING_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING | TRIGGER_FALLING) /*!< External Event Mode with Rising/Falling edge trigger detection */ +/** + * @} + */ + +/** @defgroup GPIO_speed GPIO speed + * @brief GPIO Output Maximum frequency + * @{ + */ +#define GPIO_SPEED_FREQ_LOW 0x00000000u /*!< Low speed */ +#define GPIO_SPEED_FREQ_MEDIUM 0x00000001u /*!< Medium speed */ +#define GPIO_SPEED_FREQ_HIGH 0x00000002u /*!< High speed */ +#define GPIO_SPEED_FREQ_VERY_HIGH 0x00000003u /*!< Very high speed */ +/** + * @} + */ + +/** @defgroup GPIO_pull GPIO pull + * @brief GPIO Pull-Up or Pull-Down Activation + * @{ + */ +#define GPIO_NOPULL 0x00000000u /*!< No Pull-up or Pull-down activation */ +#define GPIO_PULLUP 0x00000001u /*!< Pull-up activation */ +#define GPIO_PULLDOWN 0x00000002u /*!< Pull-down activation */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup GPIO_Exported_Macros GPIO Exported Macros + * @{ + */ + +/** + * @brief Check whether the specified EXTI line flag is set or not. + * @param __EXTI_LINE__ specifies the EXTI line flag to check. + * This parameter can be GPIO_PIN_x where x can be(0..15) + * @retval The new state of __EXTI_LINE__ (SET or RESET). + */ +#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR1 & (__EXTI_LINE__)) + +/** + * @brief Clear the EXTI's line pending flags. + * @param __EXTI_LINE__ specifies the EXTI lines flags to clear. + * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) + * @retval None + */ +#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR1 = (__EXTI_LINE__)) + +/** + * @brief Check whether the specified EXTI line is asserted or not. + * @param __EXTI_LINE__ specifies the EXTI line to check. + * This parameter can be GPIO_PIN_x where x can be(0..15) + * @retval The new state of __EXTI_LINE__ (SET or RESET). + */ +#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR1 & (__EXTI_LINE__)) + +/** + * @brief Clear the EXTI's line pending bits. + * @param __EXTI_LINE__ specifies the EXTI lines to clear. + * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) + * @retval None + */ +#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR1 = (__EXTI_LINE__)) + +/** + * @brief Generate a Software interrupt on selected EXTI line. + * @param __EXTI_LINE__ specifies the EXTI line to check. + * This parameter can be GPIO_PIN_x where x can be(0..15) + * @retval None + */ +#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER1 |= (__EXTI_LINE__)) + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup GPIO_Private_Constants GPIO Private Constants + * @{ + */ +#define GPIO_MODE_Pos 0u +#define GPIO_MODE (0x3uL << GPIO_MODE_Pos) +#define MODE_INPUT (0x0uL << GPIO_MODE_Pos) +#define MODE_OUTPUT (0x1uL << GPIO_MODE_Pos) +#define MODE_AF (0x2uL << GPIO_MODE_Pos) +#define MODE_ANALOG (0x3uL << GPIO_MODE_Pos) +#define OUTPUT_TYPE_Pos 4u +#define OUTPUT_TYPE (0x1uL << OUTPUT_TYPE_Pos) +#define OUTPUT_PP (0x0uL << OUTPUT_TYPE_Pos) +#define OUTPUT_OD (0x1uL << OUTPUT_TYPE_Pos) +#define EXTI_MODE_Pos 16u +#define EXTI_MODE (0x3uL << EXTI_MODE_Pos) +#define EXTI_IT (0x1uL << EXTI_MODE_Pos) +#define EXTI_EVT (0x2uL << EXTI_MODE_Pos) +#define TRIGGER_MODE_Pos 20u +#define TRIGGER_MODE (0x7uL << TRIGGER_MODE_Pos) +#define TRIGGER_RISING (0x1uL << TRIGGER_MODE_Pos) +#define TRIGGER_FALLING (0x2uL << TRIGGER_MODE_Pos) + +/** + * @} + */ + +/** @defgroup GPIO_Private_Macros GPIO Private Macros + * @{ + */ +#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET)) + +#define IS_GPIO_PIN(__PIN__) ((((uint32_t)(__PIN__) & GPIO_PIN_MASK) != 0x00U) &&\ + (((uint32_t)(__PIN__) & ~GPIO_PIN_MASK) == 0x00U)) + +#define IS_GPIO_COMMON_PIN(__RESETMASK__, __SETMASK__) \ + (((uint32_t)(__RESETMASK__) & (uint32_t)(__SETMASK__)) == 0x00u) + +#define IS_GPIO_MODE(__MODE__) (((__MODE__) == GPIO_MODE_INPUT) ||\ + ((__MODE__) == GPIO_MODE_OUTPUT_PP) ||\ + ((__MODE__) == GPIO_MODE_OUTPUT_OD) ||\ + ((__MODE__) == GPIO_MODE_AF_PP) ||\ + ((__MODE__) == GPIO_MODE_AF_OD) ||\ + ((__MODE__) == GPIO_MODE_IT_RISING) ||\ + ((__MODE__) == GPIO_MODE_IT_FALLING) ||\ + ((__MODE__) == GPIO_MODE_IT_RISING_FALLING) ||\ + ((__MODE__) == GPIO_MODE_EVT_RISING) ||\ + ((__MODE__) == GPIO_MODE_EVT_FALLING) ||\ + ((__MODE__) == GPIO_MODE_EVT_RISING_FALLING) ||\ + ((__MODE__) == GPIO_MODE_ANALOG)) + +#define IS_GPIO_SPEED(__SPEED__) (((__SPEED__) == GPIO_SPEED_FREQ_LOW) ||\ + ((__SPEED__) == GPIO_SPEED_FREQ_MEDIUM) ||\ + ((__SPEED__) == GPIO_SPEED_FREQ_HIGH) ||\ + ((__SPEED__) == GPIO_SPEED_FREQ_VERY_HIGH)) + +#define IS_GPIO_PULL(__PULL__) (((__PULL__) == GPIO_NOPULL) ||\ + ((__PULL__) == GPIO_PULLUP) || \ + ((__PULL__) == GPIO_PULLDOWN)) +/** + * @} + */ + +/* Include GPIO HAL Extended module */ +#include "stm32wlxx_hal_gpio_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup GPIO_Exported_Functions GPIO Exported Functions + * @brief GPIO Exported Functions + * @{ + */ + +/** @defgroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions + * @brief Initialization and Configuration functions + * @{ + */ + +/* Initialization and de-initialization functions *****************************/ +void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, const GPIO_InitTypeDef *GPIO_Init); +void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin); + +/** + * @} + */ + +/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions + * @brief IO operation functions + * @{ + */ + +/* IO operation functions *****************************************************/ +GPIO_PinState HAL_GPIO_ReadPin(const GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); +void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState); +void HAL_GPIO_WriteMultipleStatePin(GPIO_TypeDef *GPIOx, uint16_t PinReset, uint16_t PinSet); +void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); +HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); +void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin); +void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32WLxx_HAL_GPIO_H */ diff --git a/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h b/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h new file mode 100644 index 0000000..4e634ee --- /dev/null +++ b/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h @@ -0,0 +1,181 @@ +/** + ****************************************************************************** + * @file stm32wlxx_hal_gpio_ex.h + * @author MCD Application Team + * @brief Header file of GPIO HAL Extended module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32WLxx_HAL_GPIO_EX_H +#define STM32WLxx_HAL_GPIO_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wlxx_hal_def.h" + +/** @addtogroup STM32WLxx_HAL_Driver + * @{ + */ + +/** @defgroup GPIOEx GPIOEx + * @brief GPIO Extended HAL module driver + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup GPIOEx_Exported_Constants GPIOEx Exported Constants + * @{ + */ + +/** @defgroup GPIOEx_Alternate_function_selection GPIOEx Alternate function selection + * @{ + */ + +/** + * @brief AF 0 selection + */ +#define GPIO_AF0_MCO ((uint8_t)0x00) /*!< MCO Alternate Function mapping */ +#define GPIO_AF0_LSCO ((uint8_t)0x00) /*!< LSCO Alternate Function mapping */ +#define GPIO_AF0_JTAG ((uint8_t)0x00) /*!< JTAG Alternate Function mapping */ +#define GPIO_AF0_SWD ((uint8_t)0x00) /*!< SWD Alternate Function mapping */ +#define GPIO_AF0_RTC ((uint8_t)0x00) /*!< RCT_OUT Alternate Function mapping */ + +/** + * @brief AF 1 selection + */ +#define GPIO_AF1_LPTIM1 ((uint8_t)0x01) /*!< LPTIM3 Alternate Function mapping */ +#define GPIO_AF1_TIM1 ((uint8_t)0x01) /*!< TIM1 Alternate Function mapping */ +#define GPIO_AF1_TIM2 ((uint8_t)0x01) /*!< TIM2 Alternate Function mapping */ + +/** + * @brief AF 2 selection + */ +#define GPIO_AF2_TIM2 ((uint8_t)0x02) /*!< TIM2 Alternate Function mapping */ +#define GPIO_AF2_TIM1 ((uint8_t)0x02) /*!< TIM1 Alternate Function mapping */ + +/** + * @brief AF 3 selection + */ +#define GPIO_AF3_SPI2 ((uint8_t)0x03) /*!< SPI2 Alternate Function mapping */ +#define GPIO_AF3_LPTIM3 ((uint8_t)0x03) /*!< LPTIM3 Alternate Function mapping */ +#define GPIO_AF3_TIM1 ((uint8_t)0x03) /*!< TIM1 Alternate Function mapping */ + +/** + * @brief AF 4 selection + */ +#define GPIO_AF4_I2C1 ((uint8_t)0x04) /*!< I2C1 Alternate Function mapping */ +#define GPIO_AF4_I2C2 ((uint8_t)0x04) /*!< I2C1 Alternate Function mapping */ +#define GPIO_AF4_I2C3 ((uint8_t)0x04) /*!< I2C3 Alternate Function mapping */ + +/** + * @brief AF 5 selection + */ +#define GPIO_AF5_SPI1 ((uint8_t)0x05) /*!< SPI1 Alternate Function mapping */ +#define GPIO_AF5_SPI2 ((uint8_t)0x05) /*!< SPI2 Alternate Function mapping */ + +/** + * @brief AF 6 selection + */ +#define GPIO_AF6_RF_BUSY ((uint8_t)0x06) /*!< RF_BUSY Alternate Function mapping */ + +/** + * @brief AF 7 selection + */ +#define GPIO_AF7_USART1 ((uint8_t)0x07) /*!< USART1 Alternate Function mapping */ +#define GPIO_AF7_USART2 ((uint8_t)0x07) /*!< USART1 Alternate Function mapping */ + +/** + * @brief AF 8 selection + */ +#define GPIO_AF8_LPUART1 ((uint8_t)0x08) /*!< LPUART1 Alternate Function mapping */ +#define GPIO_AF8_IR ((uint8_t)0x08) /*!< IR Alternate Function mapping */ + +/** + * @brief AF 12 selection + */ +#define GPIO_AF12_COMP1 ((uint8_t)0x0C) /*!< COMP1 Alternate Function mapping */ +#define GPIO_AF12_COMP2 ((uint8_t)0x0C) /*!< COMP2 Alternate Function mapping */ +#define GPIO_AF12_TIM1 ((uint8_t)0x0C) /*!< TIM1 Alternate Function mapping */ + +/** + * @brief AF 13 selection + */ +#define GPIO_AF13_DEBUG_PWR ((uint8_t)0x0D) /*!< Debug PWR Alternate Function mapping */ +#define GPIO_AF13_DEBUG_RF ((uint8_t)0x0D) /*!< Debug RF Alternate Function mapping */ +#define GPIO_AF13_DEBUG_SUBGHZSPI ((uint8_t)0x0D) /*!< Debug SUBGHZSPI Alternate Function mapping */ + +/** + * @brief AF 14 selection + */ +#define GPIO_AF14_LPTIM2 ((uint8_t)0x0E) /*!< LPTIM2 Alternate Function mapping */ +#define GPIO_AF14_TIM2 ((uint8_t)0x0E) /*!< TIM2 Alternate Function mapping */ +#define GPIO_AF14_TIM16 ((uint8_t)0x0E) /*!< TIM16 Alternate Function mapping */ +#define GPIO_AF14_TIM17 ((uint8_t)0x0E) /*!< TIM17 Alternate Function mapping */ + +/** + * @brief AF 15 selection + */ + +#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /*!< EVENTOUT Alternate Function mapping */ + +#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x0F) + + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup GPIOEx_Exported_Macros GPIOEx Exported Macros + * @{ + */ + +/** @defgroup GPIOEx_Get_Port_Index GPIOEx Get Port Index + * @{ + */ + +#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0uL :\ + ((__GPIOx__) == (GPIOB))? 1uL :\ + ((__GPIOx__) == (GPIOC))? 2uL : 7uL) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32WLxx_HAL_GPIO_EX_H */ diff --git a/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h b/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h new file mode 100644 index 0000000..4a82fff --- /dev/null +++ b/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h @@ -0,0 +1,583 @@ +/** + ****************************************************************************** + * @file stm32wlxx_hal_pwr.h + * @author MCD Application Team + * @brief Header file of PWR HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32WLxx_HAL_PWR_H +#define STM32WLxx_HAL_PWR_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wlxx_hal_def.h" + +/* Include low level driver */ +#include "stm32wlxx_ll_pwr.h" + +/** @addtogroup STM32WLxx_HAL_Driver + * @{ + */ + +/** @defgroup PWR PWR + * @brief PWR HAL module driver + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup PWR_Exported_Types PWR Exported Types + * @{ + */ + +/** + * @brief PWR PVD configuration structure definition + */ +typedef struct +{ + uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level. + This parameter can be a value of @ref PWR_PVD_detection_level. */ + + uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins. + This parameter can be a value of @ref PWR_PVD_Mode. */ +} PWR_PVDTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup PWR_Exported_Constants PWR Exported Constants + * @{ + */ + +/** @defgroup PWR_PVD_detection_level Power Voltage Detector Level selection + * @note Refer datasheet for selection voltage value + * @{ + */ +#define PWR_PVDLEVEL_0 (0x00000000UL) /*!< PVD threshold around 2.0 V */ +#define PWR_PVDLEVEL_1 ( PWR_CR2_PLS_0) /*!< PVD threshold around 2.2 V */ +#define PWR_PVDLEVEL_2 ( PWR_CR2_PLS_1 ) /*!< PVD threshold around 2.4 V */ +#define PWR_PVDLEVEL_3 ( PWR_CR2_PLS_1 | PWR_CR2_PLS_0) /*!< PVD threshold around 2.5 V */ +#define PWR_PVDLEVEL_4 (PWR_CR2_PLS_2 ) /*!< PVD threshold around 2.6 V */ +#define PWR_PVDLEVEL_5 (PWR_CR2_PLS_2 | PWR_CR2_PLS_0) /*!< PVD threshold around 2.8 V */ +#define PWR_PVDLEVEL_6 (PWR_CR2_PLS_2 | PWR_CR2_PLS_1 ) /*!< PVD threshold around 2.9 V */ +#define PWR_PVDLEVEL_7 (PWR_CR2_PLS_2 | PWR_CR2_PLS_1 | PWR_CR2_PLS_0) /*!< External input analog voltage (compared internally to VREFINT) */ +/** + * @} + */ + +/** @defgroup PWR_PVD_Mode PWR PVD interrupt and event mode + * @{ + */ +/* Note: On STM32WL series, power PVD event is not available on EXTI lines */ +/* (only interruption is available through EXTI line 16). */ +#define PWR_PVD_MODE_NORMAL (0x00000000UL) /*!< PVD in polling mode (PVD flag update without interruption) */ + +#define PWR_PVD_MODE_IT_RISING (PVD_MODE_IT | PVD_RISING_EDGE) /*!< PVD in interrupt mode with rising edge trigger detection */ +#define PWR_PVD_MODE_IT_FALLING (PVD_MODE_IT | PVD_FALLING_EDGE) /*!< PVD in interrupt mode with falling edge trigger detection */ +#define PWR_PVD_MODE_IT_RISING_FALLING (PVD_MODE_IT | PVD_RISING_FALLING_EDGE) /*!< PVD in interrupt mode with rising/falling edge trigger detection */ +/** + * @} + */ + +/** @defgroup PWR_Low_Power_Mode_Selection PWR Low Power Mode Selection + * @{ + */ +#ifdef CORE_CM0PLUS +#define PWR_LOWPOWERMODE_STOP0 (0x00000000UL) /*!< Stop 0: Stop mode with main regulator */ +#define PWR_LOWPOWERMODE_STOP1 (PWR_C2CR1_LPMS_0) /*!< Stop 1: Stop mode with low power regulator */ +#define PWR_LOWPOWERMODE_STOP2 (PWR_C2CR1_LPMS_1) /*!< Stop 2: Stop mode with low power regulator and VDD12I interruptible digital core domain supply OFF (less peripherals activated than low power mode stop 1 to reduce power consumption)*/ +#define PWR_LOWPOWERMODE_STANDBY (PWR_C2CR1_LPMS_0 | PWR_C2CR1_LPMS_1) /*!< Standby mode */ +#define PWR_LOWPOWERMODE_SHUTDOWN (PWR_C2CR1_LPMS_2 | PWR_C2CR1_LPMS_1 | PWR_C2CR1_LPMS_0) /*!< Shutdown mode */ +#else +#define PWR_LOWPOWERMODE_STOP0 (0x00000000UL) /*!< Stop 0: Stop mode with main regulator */ +#define PWR_LOWPOWERMODE_STOP1 (PWR_CR1_LPMS_0) /*!< Stop 1: Stop mode with low power regulator */ +#define PWR_LOWPOWERMODE_STOP2 (PWR_CR1_LPMS_1) /*!< Stop 2: Stop mode with low power regulator and VDD12I interruptible digital core domain supply OFF (less peripherals activated than low power mode stop 1 to reduce power consumption)*/ +#define PWR_LOWPOWERMODE_STANDBY (PWR_CR1_LPMS_0 | PWR_CR1_LPMS_1) /*!< Standby mode */ +#define PWR_LOWPOWERMODE_SHUTDOWN (PWR_CR1_LPMS_2 | PWR_CR1_LPMS_1 | PWR_CR1_LPMS_0) /*!< Shutdown mode */ +#endif /* CORE_CM0PLUS */ +/** + * @} + */ + +/** @defgroup PWR_Regulator_state_in_SLEEP_STOP_mode PWR regulator mode + * @{ + */ +#define PWR_MAINREGULATOR_ON (0x00000000UL) /*!< Regulator in main mode */ +#define PWR_LOWPOWERREGULATOR_ON (PWR_CR1_LPR) /*!< Regulator in low-power mode */ +/** + * @} + */ + +/** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry + * @{ + */ +#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01) /*!< Wait For Interruption instruction to enter Sleep mode */ +#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02) /*!< Wait For Event instruction to enter Sleep mode */ +/** + * @} + */ + +/** @defgroup PWR_STOP_mode_entry PWR STOP mode entry + * @{ + */ +#define PWR_STOPENTRY_WFI ((uint8_t)0x01) /*!< Wait For Interruption instruction to enter Stop mode */ +#define PWR_STOPENTRY_WFE ((uint8_t)0x02) /*!< Wait For Event instruction to enter Stop mode */ +/** + * @} + */ + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup PWR_Private_Constants PWR Private Constants + * @{ + */ + +/** @defgroup PWR_PVD_EXTI_LINE PWR PVD external interrupt line + * @{ + */ +#define PWR_EXTI_LINE_PVD (LL_EXTI_LINE_16) /*!< External interrupt line 16 Connected to the PWR PVD */ +/** + * @} + */ + +/** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask + * @{ + */ +/* Note: On STM32WL series, power PVD event is not available on EXTI lines */ +/* (only interruption is available through EXTI line 16). */ +#define PVD_MODE_IT (0x00010000UL) /*!< Mask for interruption yielded by PVD threshold crossing */ +#define PVD_RISING_EDGE (0x00000001UL) /*!< Mask for rising edge set as PVD trigger */ +#define PVD_FALLING_EDGE (0x00000002UL) /*!< Mask for falling edge set as PVD trigger */ +#define PVD_RISING_FALLING_EDGE (0x00000003UL) /*!< Mask for rising and falling edges set as PVD trigger */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup PWR_Exported_Macros PWR Exported Macros + * @{ + */ +#if defined(DUAL_CORE) +/** @brief Check whether or not a specific PWR flag is set. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * + * /--------------------------------SR1-------------------------------/ + * @arg @ref PWR_FLAG_WUF1 Wake Up Flag 1. Indicates that a wakeup event + * was received from the WKUP pin 1. + * @arg @ref PWR_FLAG_WUF2 Wake Up Flag 2. Indicates that a wakeup event + * was received from the WKUP pin 2. + * @arg @ref PWR_FLAG_WUF3 Wake Up Flag 3. Indicates that a wakeup event + * was received from the WKUP pin 3. + * + * @arg @ref PWR_FLAG_WPVD Wakeup PVD flag + * + * @arg @ref PWR_FLAG_HOLDC2I CPU2 on-Hold Interrupt Flag + * @arg @ref PWR_FLAG_WUFI Wake-Up Flag Internal. Set when a wakeup is detected on + * the internal wakeup line. + * + * @arg @ref PWR_FLAG_WRFBUSY Wake-up radio busy flag (triggered status: wake-up event or interruption occurred at least once. Can be cleared by software) + * + * /--------------------------------SR2-------------------------------/ + * @arg @ref PWR_FLAG_LDORDY Main LDO ready flag + * @arg @ref PWR_FLAG_SMPSRDY SMPS ready Flag + * + * @arg @ref PWR_FLAG_REGLPS Low-power Regulator 1 started: Indicates whether the regulator + * is ready after a power-on reset or a Standby/Shutdown. + * @arg @ref PWR_FLAG_REGLPF Low-power Regulator 1 flag: Indicates whether the + * regulator 1 is in main mode or is in low-power mode. + * + * @arg @ref PWR_FLAG_REGMRS Low-power regulator (main regulator or low-power regulator used) flag. + * + * @arg @ref PWR_FLAG_FLASHRDY Flash ready flag + * + * @arg @ref PWR_FLAG_VOSF Voltage Scaling Flag. Indicates whether the regulator is ready + * in the selected voltage range or is still changing to the required voltage level. + * @arg @ref PWR_FLAG_PVDO Power Voltage Detector Output. Indicates whether VDD voltage is below + * or above the selected PVD threshold. + * + * @arg @ref PWR_FLAG_PVMO3 Peripheral Voltage Monitoring Output 3. Indicates whether VDDA voltage is + * is below or above PVM3 threshold. + * + * @arg @ref PWR_FLAG_RFEOL Indicate whether supply voltage is below radio operating level (radio "end of life"). + * + * @arg @ref PWR_FLAG_RFBUSYS Radio busy signal flag (current status). + * @arg @ref PWR_FLAG_RFBUSYMS Radio busy masked signal flag (current status). + * + * @arg @ref PWR_FLAG_C2BOOTS CPU2 boot request source information flag. + * + * /----------------------------EXTSCR--------------------------/ + * @arg @ref PWR_FLAG_STOP System Stop 0 or Stop1 Flag for CPU1. + * @arg @ref PWR_FLAG_STOP2 System Stop 2 Flag for CPU1. + * @arg @ref PWR_FLAG_SB System Standby Flag for CPU1. + * + * @arg @ref PWR_FLAG_C2STOP System Stop 0 or Stop1 Flag for CPU2. + * @arg @ref PWR_FLAG_C2STOP2 System Stop 2 Flag for CPU2. + * @arg @ref PWR_FLAG_C2SB System Standby Flag for CPU2. + * + * @arg @ref PWR_FLAG_C1DEEPSLEEP CPU1 DeepSleep Flag. + * @arg @ref PWR_FLAG_C2DEEPSLEEP CPU2 DeepSleep Flag. + * + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#else +/** @brief Check whether or not a specific PWR flag is set. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * + * /--------------------------------SR1-------------------------------/ + * @arg @ref PWR_FLAG_WUF1 Wake Up Flag 1. Indicates that a wakeup event + * was received from the WKUP pin 1. + * @arg @ref PWR_FLAG_WUF2 Wake Up Flag 2. Indicates that a wakeup event + * was received from the WKUP pin 2. + * @arg @ref PWR_FLAG_WUF3 Wake Up Flag 3. Indicates that a wakeup event + * was received from the WKUP pin 3. + * + * @arg @ref PWR_FLAG_WPVD Wakeup PVD flag + * + * @arg @ref PWR_FLAG_WUFI Wake-Up Flag Internal. Set when a wakeup is detected on + * the internal wakeup line. + * + * @arg @ref PWR_FLAG_WRFBUSY Wake-up radio busy flag (triggered status: wake-up event or interruption occurred at least once. Can be cleared by software) + * + * /--------------------------------SR2-------------------------------/ + * @arg @ref PWR_FLAG_LDORDY Main LDO ready flag + * @arg @ref PWR_FLAG_SMPSRDY SMPS ready Flag + * + * @arg @ref PWR_FLAG_REGLPS Low-power Regulator 1 started: Indicates whether the regulator + * is ready after a power-on reset or a Standby/Shutdown. + * @arg @ref PWR_FLAG_REGLPF Low-power Regulator 1 flag: Indicates whether the + * regulator 1 is in main mode or is in low-power mode. + * + * @arg @ref PWR_FLAG_REGMRS Low-power regulator (main regulator or low-power regulator used) flag. + * + * @arg @ref PWR_FLAG_FLASHRDY Flash ready flag + * + * @arg @ref PWR_FLAG_VOSF Voltage Scaling Flag. Indicates whether the regulator is ready + * in the selected voltage range or is still changing to the required voltage level. + * @arg @ref PWR_FLAG_PVDO Power Voltage Detector Output. Indicates whether VDD voltage is below + * or above the selected PVD threshold. + * + * @arg @ref PWR_FLAG_PVMO3 Peripheral Voltage Monitoring Output 3. Indicates whether VDDA voltage is + * is below or above PVM3 threshold. + * + * @arg @ref PWR_FLAG_RFEOL Indicate whether supply voltage is below radio operating level (radio "end of life"). + * + * @arg @ref PWR_FLAG_RFBUSYS Radio busy signal flag (current status). + * @arg @ref PWR_FLAG_RFBUSYMS Radio busy masked signal flag (current status). + * + * /----------------------------EXTSCR--------------------------/ + * @arg @ref PWR_FLAG_STOP System Stop 0 or Stop1 Flag for CPU1. + * @arg @ref PWR_FLAG_STOP2 System Stop 2 Flag for CPU1. + * @arg @ref PWR_FLAG_SB System Standby Flag for CPU1. + * + * @arg @ref PWR_FLAG_C1DEEPSLEEP CPU1 DeepSleep Flag. + * + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#endif /* DUAL_CORE */ +#define __HAL_PWR_GET_FLAG(__FLAG__) ((((__FLAG__) & PWR_FLAG_REG_MASK) == PWR_FLAG_REG_SR1) ? \ + ( \ + PWR->SR1 & (1UL << ((__FLAG__) & 31UL)) \ + ) \ + : \ + ( \ + (((__FLAG__) & PWR_FLAG_REG_MASK) == PWR_FLAG_REG_SR2) ? \ + ( \ + PWR->SR2 & (1UL << ((__FLAG__) & 31UL)) \ + ) \ + : \ + ( \ + PWR->EXTSCR & (1UL << ((__FLAG__) & 31UL)) \ + ) \ + ) \ + ) + +#if defined(DUAL_CORE) +/** @brief Clear a specific PWR flag. + * @note Clearing of flags {PWR_FLAG_STOP, PWR_FLAG_STOP2, PWR_FLAG_SB} + * and flags {PWR_FLAG_C2STOP, PWR_FLAG_C2SB} are grouped: + * clearing of one flag also clears the other ones. + * @param __FLAG__ specifies the flag to clear. + * This parameter can be one of the following values: + * + * /--------------------------------SCR (SRR)------------------------------/ + * @arg @ref PWR_FLAG_WU Wake Up Flag of all pins. + * @arg @ref PWR_FLAG_WUF1 Wake Up Flag 1. Indicates that a wakeup event + * was received from the WKUP pin 1. + * @arg @ref PWR_FLAG_WUF2 Wake Up Flag 2. Indicates that a wakeup event + * was received from the WKUP pin 2. + * @arg @ref PWR_FLAG_WUF3 Wake Up Flag 3. Indicates that a wakeup event + * was received from the WKUP pin 3. + * + * @arg @ref PWR_FLAG_WPVD Wakeup PVD flag + * + * @arg @ref PWR_FLAG_HOLDC2I CPU2 on-Hold Interrupt Flag + * + * @arg @ref PWR_FLAG_WRFBUSY Wake-up radio busy flag (triggered status: wake-up event or interruption occurred at least once. Can be cleared by software) + * + * /----------------------------EXTSCR--------------------------/ + * @arg @ref PWR_FLAG_LPMODES System Standby Flag for CPU1. + * @arg @ref PWR_FLAG_C2LPMODES System Standby Flag for CPU2. + * + * @retval None + */ +#else +/** @brief Clear a specific PWR flag. + * @note Clearing of flags {PWR_FLAG_STOP, PWR_FLAG_STOP2, PWR_FLAG_SB} + * are grouped: + * clearing of one flag also clears the other ones. + * @param __FLAG__ specifies the flag to clear. + * This parameter can be one of the following values: + * + * /--------------------------------SCR (SRR)------------------------------/ + * @arg @ref PWR_FLAG_WU Wake Up Flag of all pins. + * @arg @ref PWR_FLAG_WUF1 Wake Up Flag 1. Indicates that a wakeup event + * was received from the WKUP pin 1. + * @arg @ref PWR_FLAG_WUF2 Wake Up Flag 2. Indicates that a wakeup event + * was received from the WKUP pin 2. + * @arg @ref PWR_FLAG_WUF3 Wake Up Flag 3. Indicates that a wakeup event + * was received from the WKUP pin 3. + * + * @arg @ref PWR_FLAG_WPVD Wakeup PVD flag + * + * @arg @ref PWR_FLAG_WRFBUSY Wake-up radio busy flag (triggered status: wake-up event or interruption occurred at least once. Can be cleared by software) + * + * /----------------------------EXTSCR--------------------------/ + * @arg @ref PWR_FLAG_LPMODES System Standby Flag for CPU1. + * + * @retval None + */ +#endif /* DUAL_CORE */ +#define __HAL_PWR_CLEAR_FLAG(__FLAG__) ((((__FLAG__) & PWR_FLAG_REG_MASK) == PWR_FLAG_REG_EXTSCR) ? \ + ( \ + PWR->EXTSCR = (1UL << (((__FLAG__) & PWR_FLAG_EXTSCR_CLR_MASK) >> PWR_FLAG_EXTSCR_CLR_POS)) \ + ) \ + : \ + ( \ + (((__FLAG__)) == PWR_FLAG_WU) ? \ + (PWR->SCR = PWR_SCR_CWUF) : \ + (PWR->SCR = (1UL << ((__FLAG__) & 31UL))) \ + ) \ + ) + +/** + * @brief Enable the PVD Extended Interrupt line. + * @retval None + */ +#if defined(CORE_CM0PLUS) +#define __HAL_PWR_PVD_EXTI_ENABLE_IT() LL_C2_EXTI_EnableIT_0_31(PWR_EXTI_LINE_PVD) +#else +#define __HAL_PWR_PVD_EXTI_ENABLE_IT() LL_EXTI_EnableIT_0_31(PWR_EXTI_LINE_PVD) +#endif /* CORE_CM0PLUS */ + +/** + * @brief Disable the PVD Extended Interrupt line. + * @retval None + */ +#if defined(CORE_CM0PLUS) +#define __HAL_PWR_PVD_EXTI_DISABLE_IT() LL_C2_EXTI_DisableIT_0_31(PWR_EXTI_LINE_PVD) +#else +#define __HAL_PWR_PVD_EXTI_DISABLE_IT() LL_EXTI_DisableIT_0_31(PWR_EXTI_LINE_PVD) +#endif /* CORE_CM0PLUS */ + +/* Note: On STM32WL series, power PVD event is not available on EXTI lines */ +/* (only interruption is available through EXTI line 16). */ + +/** + * @brief Enable the PVD Extended Interrupt Rising Trigger. + * @note PVD flag polarity is inverted compared to EXTI line, therefore + * EXTI rising and falling logic edges are inverted versus PVD voltage edges. + * @retval None + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() LL_EXTI_EnableFallingTrig_0_31(PWR_EXTI_LINE_PVD) + +/** + * @brief Disable the PVD Extended Interrupt Rising Trigger. + * @note PVD flag polarity is inverted compared to EXTI line, therefore + * EXTI rising and falling logic edges are inverted versus PVD voltage edges. + * @retval None + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() LL_EXTI_DisableFallingTrig_0_31(PWR_EXTI_LINE_PVD) + +/** + * @brief Enable the PVD Extended Interrupt Falling Trigger. + * @note PVD flag polarity is inverted compared to EXTI line, therefore + * EXTI rising and falling logic edges are inverted versus PVD voltage edges. + * @retval None + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() LL_EXTI_EnableRisingTrig_0_31(PWR_EXTI_LINE_PVD) + +/** + * @brief Disable the PVD Extended Interrupt Falling Trigger. + * @note PVD flag polarity is inverted compared to EXTI line, therefore + * EXTI rising and falling logic edges are inverted versus PVD voltage edges. + * @retval None + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() LL_EXTI_DisableRisingTrig_0_31(PWR_EXTI_LINE_PVD) + +/** + * @brief Enable the PVD Extended Interrupt Rising & Falling Trigger. + * @retval None + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() \ + do { \ + __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); \ + __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); \ + } while(0) + +/** + * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger. + * @retval None + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() \ + do { \ + __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); \ + __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \ + } while(0) + +/** + * @brief Generate a Software interrupt on selected EXTI line. + * @retval None + */ +#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() LL_EXTI_GenerateSWI_0_31(PWR_EXTI_LINE_PVD) + +/** + * @brief Check whether or not the PVD EXTI interrupt flag is set. + * @retval EXTI PVD Line Status. + */ +#define __HAL_PWR_PVD_EXTI_GET_FLAG() LL_EXTI_ReadFlag_0_31(PWR_EXTI_LINE_PVD) + +/** + * @brief Clear the PVD EXTI interrupt flag. + * @retval None + */ +#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() LL_EXTI_ClearFlag_0_31(PWR_EXTI_LINE_PVD) + +/** + * @} + */ + + +/* Private macros --------------------------------------------------------*/ +/** @defgroup PWR_Private_Macros PWR Private Macros + * @{ + */ +#define IS_PWR_PVD_LEVEL(__LEVEL__) (((__LEVEL__) == PWR_PVDLEVEL_0) || ((__LEVEL__) == PWR_PVDLEVEL_1)|| \ + ((__LEVEL__) == PWR_PVDLEVEL_2) || ((__LEVEL__) == PWR_PVDLEVEL_3)|| \ + ((__LEVEL__) == PWR_PVDLEVEL_4) || ((__LEVEL__) == PWR_PVDLEVEL_5)|| \ + ((__LEVEL__) == PWR_PVDLEVEL_6) || ((__LEVEL__) == PWR_PVDLEVEL_7)) + +#define IS_PWR_PVD_MODE(__MODE__) (((__MODE__) == PWR_PVD_MODE_NORMAL) ||\ + ((__MODE__) == PWR_PVD_MODE_IT_RISING) ||\ + ((__MODE__) == PWR_PVD_MODE_IT_FALLING) ||\ + ((__MODE__) == PWR_PVD_MODE_IT_RISING_FALLING)) + +#define IS_PWR_REGULATOR(__REGULATOR__) (((__REGULATOR__) == PWR_MAINREGULATOR_ON) || \ + ((__REGULATOR__) == PWR_LOWPOWERREGULATOR_ON)) + +#define IS_PWR_SLEEP_ENTRY(__ENTRY__) (((__ENTRY__) == PWR_SLEEPENTRY_WFI) || \ + ((__ENTRY__) == PWR_SLEEPENTRY_WFE)) + +#define IS_PWR_STOP_ENTRY(__ENTRY__) (((__ENTRY__) == PWR_STOPENTRY_WFI) || \ + ((__ENTRY__) == PWR_STOPENTRY_WFE)) +/** + * @} + */ + +/* Include PWR HAL Extended module */ +#include "stm32wlxx_hal_pwr_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup PWR_Exported_Functions PWR Exported Functions + * @{ + */ + +/** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ + +/* Initialization and de-initialization functions *******************************/ +void HAL_PWR_DeInit(void); + +void HAL_PWR_EnableBkUpAccess(void); +void HAL_PWR_DisableBkUpAccess(void); +/** + * @} + */ + +/** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions + * @{ + */ +/* Peripheral Control functions ************************************************/ +HAL_StatusTypeDef HAL_PWR_ConfigPVD(const PWR_PVDTypeDef *sConfigPVD); +void HAL_PWR_EnablePVD(void); +void HAL_PWR_DisablePVD(void); + +/* WakeUp pins configuration functions ****************************************/ +void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity); +void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx); + +/* Low Power modes configuration functions ************************************/ +void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry); +void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry); +void HAL_PWR_EnterSTANDBYMode(void); + +void HAL_PWR_EnableSleepOnExit(void); +void HAL_PWR_DisableSleepOnExit(void); + +void HAL_PWR_EnableSEVOnPend(void); +void HAL_PWR_DisableSEVOnPend(void); + +void HAL_PWR_PVDCallback(void); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + + +#endif /* STM32WLxx_HAL_PWR_H */ + diff --git a/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h b/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h new file mode 100644 index 0000000..ce9821e --- /dev/null +++ b/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h @@ -0,0 +1,652 @@ +/** + ****************************************************************************** + * @file stm32wlxx_hal_pwr_ex.h + * @author MCD Application Team + * @brief Header file of PWR HAL Extended module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32WLxx_HAL_PWR_EX_H +#define STM32WLxx_HAL_PWR_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wlxx_hal_def.h" + +/** @addtogroup STM32WLxx_HAL_Driver + * @{ + */ + +/** @defgroup PWREx PWREx + * @brief PWR Extended HAL module driver + * @{ + */ + + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup PWREx_Exported_Types PWR Extended Exported Types + * @{ + */ + +/** + * @brief PWR PVM configuration structure definition + */ +typedef struct +{ + uint32_t PVMType; /*!< PVMType: Specifies which voltage is monitored and against which threshold. + This parameter can be a value of @ref PWREx_PVM_Type. + @arg @ref PWR_PVM_3 Peripheral Voltage Monitoring 3 enable: VDDA versus 1.62 V. + */ + uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins. + This parameter can be a value of @ref PWREx_PVM_Mode. */ +} PWR_PVMTypeDef; + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup PWREx_Private_Constants PWR Extended Private Constants + * @{ + */ +#define PWR_WUP_POLARITY_SHIFT 0x05 /*!< Internal constant used to retrieve wakeup pin polarity */ + +/** @defgroup PWR_FLAG_REG PWR flag register + * @{ + */ +#define PWR_FLAG_REG_SR1 (0x20UL) /* Bitfield to indicate PWR flag located in register PWR_SR1 */ +#define PWR_FLAG_REG_SR2 (0x40UL) /* Bitfield to indicate PWR flag located in register PWR_SR2 */ +#define PWR_FLAG_REG_EXTSCR (0x60UL) /* Bitfield to indicate PWR flag located in register PWR_EXTSCR */ +#define PWR_FLAG_REG_MASK_POS (5UL) /* Bitfield mask position to indicate PWR flag location in PWR register */ +#define PWR_FLAG_REG_MASK (PWR_FLAG_REG_SR1 | PWR_FLAG_REG_SR2 | PWR_FLAG_REG_EXTSCR) /* Bitfield mask to indicate PWR flag location in PWR register */ +#define PWR_FLAG_EXTSCR_CLR_POS (16UL) /* Bitfield for register PWR_EXTSCR clearable bits positions: position of bitfield in flag literals */ +#if defined(DUAL_CORE) +#define PWR_FLAG_EXTSCR_CLR_MASK ((PWR_EXTSCR_C1CSSF_Pos | PWR_EXTSCR_C2CSSF_Pos) << PWR_FLAG_EXTSCR_CLR_POS) /* Bitfield for register PWR_EXTSCR clearable bits positions: mask of bitfield in flag literals */ +#else +#define PWR_FLAG_EXTSCR_CLR_MASK ((PWR_EXTSCR_C1CSSF_Pos) << PWR_FLAG_EXTSCR_CLR_POS) /* Bitfield for register PWR_EXTSCR clearable bits positions: mask of bitfield in flag literals */ +#endif /* DUAL_CORE */ +/** + * @} + */ + +/** @defgroup PWR_PVM_Mode_Mask PWR PVM Mode Mask + * @{ + */ +/* Note: On STM32WL series, power PVD event is not available on EXTI lines */ +/* (only interruption is available through EXTI line 16). */ +#define PVM_MODE_IT (0x00010000UL) /*!< Mask for interruption yielded by PVM threshold crossing */ +#define PVM_RISING_EDGE (0x00000001UL) /*!< Mask for rising edge set as PVM trigger */ +#define PVM_FALLING_EDGE (0x00000002UL) /*!< Mask for falling edge set as PVM trigger */ +#define PVM_RISING_FALLING_EDGE (0x00000003UL) /*!< Mask for rising and falling edges set as PVM trigger */ + +/** + * @} + */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup PWREx_Exported_Constants PWR Extended Exported Constants + * @{ + */ + +/** @defgroup PWREx_WakeUp_Pins PWR wake-up pins + * @{ + */ +#define PWR_WAKEUP_PIN1_HIGH PWR_CR3_EWUP1 /*!< Wakeup pin 1 (with high level polarity) */ +#define PWR_WAKEUP_PIN2_HIGH PWR_CR3_EWUP2 /*!< Wakeup pin 2 (with high level polarity) */ +#define PWR_WAKEUP_PIN3_HIGH PWR_CR3_EWUP3 /*!< Wakeup pin 3 (with high level polarity) */ + +#define PWR_WAKEUP_PIN1_LOW ((PWR_CR4_WP1<CR1, PWR_CR1_VOS, (__REGULATOR__)); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(PWR->CR1, PWR_CR1_VOS); \ + UNUSED(tmpreg); \ + } while(0) + +/** + * @} + */ + +/* Private macros --------------------------------------------------------*/ +/** @addtogroup PWREx_Private_Macros PWR Extended Private Macros + * @{ + */ + +#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1_HIGH) || \ + ((PIN) == PWR_WAKEUP_PIN2_HIGH) || \ + ((PIN) == PWR_WAKEUP_PIN3_HIGH) || \ + ((PIN) == PWR_WAKEUP_PIN1_LOW) || \ + ((PIN) == PWR_WAKEUP_PIN2_LOW) || \ + ((PIN) == PWR_WAKEUP_PIN3_LOW)) + +#define IS_PWR_PVM_TYPE(__TYPE__) (((__TYPE__) == PWR_PVM_3)) + +#define IS_PWR_PVM_MODE(__MODE__) (((__MODE__) == PWR_PVM_MODE_NORMAL) ||\ + ((__MODE__) == PWR_PVM_MODE_IT_RISING) ||\ + ((__MODE__) == PWR_PVM_MODE_IT_FALLING) ||\ + ((__MODE__) == PWR_PVM_MODE_IT_RISING_FALLING)) + +#define IS_PWR_FLASH_POWERDOWN(__MODE__) ((((__MODE__) & (PWR_FLASHPD_LPRUN | PWR_FLASHPD_LPSLEEP)) != 0x00UL) && \ + (((__MODE__) & ~(PWR_FLASHPD_LPRUN | PWR_FLASHPD_LPSLEEP)) == 0x00UL)) + +#define IS_PWR_VOLTAGE_SCALING_RANGE(__RANGE__) (((__RANGE__) == PWR_REGULATOR_VOLTAGE_SCALE1) || \ + ((__RANGE__) == PWR_REGULATOR_VOLTAGE_SCALE2)) + +#define IS_PWR_BATTERY_RESISTOR_SELECT(__RESISTOR__) (((__RESISTOR__) == PWR_BATTERY_CHARGING_RESISTOR_5) ||\ + ((__RESISTOR__) == PWR_BATTERY_CHARGING_RESISTOR_1_5)) + +#define IS_PWR_BATTERY_CHARGING(__CHARGING__) (((__CHARGING__) == PWR_BATTERY_CHARGING_DISABLE) ||\ + ((__CHARGING__) == PWR_BATTERY_CHARGING_ENABLE)) + +#define IS_PWR_GPIO_BIT_NUMBER(__BIT_NUMBER__) (((__BIT_NUMBER__) & GPIO_PIN_MASK) != (uint32_t)0x00) + +#define IS_PWR_GPIO(__GPIO__) (((__GPIO__) == PWR_GPIO_A) ||\ + ((__GPIO__) == PWR_GPIO_B) ||\ + ((__GPIO__) == PWR_GPIO_C) ||\ + ((__GPIO__) == PWR_GPIO_H)) + +#define IS_PWR_SMPS_MODE(__SMPS_MODE__) (((__SMPS_MODE__) == PWR_SMPS_BYPASS) ||\ + ((__SMPS_MODE__) == PWR_SMPS_STEP_DOWN)) + +#define IS_RADIO_BUSY_POLARITY(__RADIO_BUSY_POLARITY__) (((__RADIO_BUSY_POLARITY__) == PWR_RADIO_BUSY_POLARITY_RISING) ||\ + ((__RADIO_BUSY_POLARITY__) == PWR_RADIO_BUSY_POLARITY_FALLING)) + +#define IS_PWR_RADIO_BUSY_TRIGGER(__RADIO_BUSY_TRIGGER__) (((__RADIO_BUSY_TRIGGER__) == PWR_RADIO_BUSY_TRIGGER_NONE) ||\ + ((__RADIO_BUSY_TRIGGER__) == PWR_RADIO_BUSY_TRIGGER_WU_IT)) + +#define IS_RADIO_IRQ_TRIGGER(__RADIO_IRQ_TRIGGER__) (((__RADIO_IRQ_TRIGGER__) == PWR_RADIO_IRQ_TRIGGER_NONE) ||\ + ((__RADIO_IRQ_TRIGGER__) == PWR_RADIO_IRQ_TRIGGER_WU_IT)) + +#if defined(DUAL_CORE) +#define IS_PWR_CORE(__CPU__) (((__CPU__) == PWR_CORE_CPU1) || ((__CPU__) == PWR_CORE_CPU2)) +#else +#define IS_PWR_CORE(__CPU__) (((__CPU__) == PWR_CORE_CPU1)) +#endif /* DUAL_CORE */ + +#if defined(DUAL_CORE) +#define IS_PWR_CORE_HOLD_RELEASE(__CPU__) ((__CPU__) == PWR_CORE_CPU2) +#endif /* DUAL_CORE */ + +/** + * @} + */ + + +/** @addtogroup PWREx_Exported_Functions PWR Extended Exported Functions + * @{ + */ + +/** @addtogroup PWREx_Exported_Functions_Group1 Extended Peripheral Control functions + * @{ + */ + + +/* Peripheral Control functions **********************************************/ +uint32_t HAL_PWREx_GetVoltageRange(void); +HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling); + +void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorSelection); +void HAL_PWREx_DisableBatteryCharging(void); + +void HAL_PWREx_EnableInternalWakeUpLine(void); +void HAL_PWREx_DisableInternalWakeUpLine(void); + +void HAL_PWREx_SetRadioBusyPolarity(uint32_t RadioBusyPolarity); +void HAL_PWREx_SetRadioBusyTrigger(uint32_t RadioBusyTrigger); +void HAL_PWREx_SetRadioIRQTrigger(uint32_t RadioIRQTrigger); + +void HAL_PWREx_EnableHOLDC2IT(void); +void HAL_PWREx_DisableHOLDC2IT(void); + +void HAL_PWREx_HoldCore(uint32_t CPU); +void HAL_PWREx_ReleaseCore(uint32_t CPU); + +#ifdef CORE_CM0PLUS +void HAL_PWREx_EnableWakeUp_ILAC(void); +void HAL_PWREx_DisableWakeUp_ILAC(void); +uint32_t HAL_PWREx_IsEnabledWakeUp_ILAC(void); +#endif /* CORE_CM0PLUS */ + +HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber); +HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber); +HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber); +HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber); +void HAL_PWREx_EnablePullUpPullDownConfig(void); +void HAL_PWREx_DisablePullUpPullDownConfig(void); + +void HAL_PWREx_EnableSRAMRetention(void); +void HAL_PWREx_DisableSRAMRetention(void); + +void HAL_PWREx_EnableFlashPowerDown(uint32_t PowerMode); +void HAL_PWREx_DisableFlashPowerDown(uint32_t PowerMode); + +void HAL_PWREx_EnableWPVD(void); +void HAL_PWREx_DisableWPVD(void); +void HAL_PWREx_EnableBORPVD_ULP(void); +void HAL_PWREx_DisableBORPVD_ULP(void); + +void HAL_PWREx_EnablePVM3(void); +void HAL_PWREx_DisablePVM3(void); + +HAL_StatusTypeDef HAL_PWREx_ConfigPVM(const PWR_PVMTypeDef *sConfigPVM); + +void HAL_PWREx_SetRadioEOL(uint32_t RadioEOL); +void HAL_PWREx_SMPS_SetMode(uint32_t OperatingMode); +uint32_t HAL_PWREx_SMPS_GetEffectiveMode(void); + +/* Low Power modes configuration functions ************************************/ +void HAL_PWREx_EnableLowPowerRunMode(void); +HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void); + +void HAL_PWREx_EnterSTOP0Mode(uint8_t STOPEntry); +void HAL_PWREx_EnterSTOP1Mode(uint8_t STOPEntry); +void HAL_PWREx_EnterSTOP2Mode(uint8_t STOPEntry); +void HAL_PWREx_EnterSHUTDOWNMode(void); + +void HAL_PWREx_PVD_PVM_IRQHandler(void); + +void HAL_PWREx_PVM3Callback(void); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + + +#endif /* STM32WLxx_HAL_PWR_EX_H */ + diff --git a/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h b/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h new file mode 100644 index 0000000..99dc420 --- /dev/null +++ b/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h @@ -0,0 +1,2431 @@ +/** + ****************************************************************************** + * @file stm32wlxx_hal_rcc.h + * @author MCD Application Team + * @brief Header file of RCC HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32WLxx_HAL_RCC_H +#define STM32WLxx_HAL_RCC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wlxx_hal_def.h" +#include "stm32wlxx_ll_rcc.h" +#include "stm32wlxx_ll_bus.h" + + +/** @addtogroup STM32WLxx_HAL_Driver + * @{ + */ + +/** @addtogroup RCC + * @{ + */ + +/* Private constants ---------------------------------------------------------*/ +/** @addtogroup RCC_Private_Constants + * @{ + */ +/* Defines used for Flags */ +#define CR_REG_INDEX 1U +#define BDCR_REG_INDEX 2U +#define CSR_REG_INDEX 3U +#define REG_INDEX_POS 5U + +#define RCC_FLAG_MASK 0x1FU + +/* Defines Oscillator Masks */ +#define RCC_OSCILLATORTYPE_ALL (RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_MSI | \ + RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_LSE) /*!< All Oscillator to configure */ + +/** @defgroup RCC_Timeout_Value Timeout Values + * @{ + */ +#define RCC_DBP_TIMEOUT_VALUE 2U /*!< 2 ms (minimum Tick + 1) */ +#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT /*!< LSE timeout in ms */ +#define PLL_TIMEOUT_VALUE 10U /*!< 10 ms (minimum Tick + 1) */ +/** + * @} + */ + +/** @defgroup RCC_Reset_Flag Reset Flag + * @{ + */ +#define RCC_RESET_FLAG_OBL RCC_CSR_OBLRSTF /*!< Option Byte Loader reset flag */ +#define RCC_RESET_FLAG_PIN RCC_CSR_PINRSTF /*!< PIN reset flag */ +#define RCC_RESET_FLAG_PWR RCC_CSR_BORRSTF /*!< BOR or POR/PDR reset flag */ +#define RCC_RESET_FLAG_SW RCC_CSR_SFTRSTF /*!< Software Reset flag */ +#define RCC_RESET_FLAG_IWDG RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset flag */ +#define RCC_RESET_FLAG_WWDG RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag */ +#define RCC_RESET_FLAG_LPWR RCC_CSR_LPWRRSTF /*!< Low power reset flag */ +#define RCC_RESET_FLAG_ALL (RCC_RESET_FLAG_OBL | RCC_RESET_FLAG_PIN | RCC_RESET_FLAG_PWR | \ + RCC_RESET_FLAG_SW | RCC_RESET_FLAG_IWDG | RCC_RESET_FLAG_WWDG | \ + RCC_RESET_FLAG_LPWR) +/** + * @} + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup RCC_Private_Macros + * @{ + */ + +#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \ + (((__OSCILLATOR__) & ~RCC_OSCILLATORTYPE_ALL) == 0x00U)) + + +#define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \ + ((__HSE__) == RCC_HSE_BYPASS_PWR)) + +#define IS_RCC_HSEDIV(__HSEDIV__) (((__HSEDIV__) == RCC_HSE_DIV1) || ((__HSEDIV__) == RCC_HSE_DIV2)) + +#define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || \ + ((__LSE__) == RCC_LSE_ON) || ((__LSE__) == RCC_LSE_ON_RTC_ONLY) || \ + ((__LSE__) == RCC_LSE_BYPASS) || ((__LSE__) == RCC_LSE_BYPASS_RTC_ONLY)) + +#define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON)) + +#define IS_RCC_HSI_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= (uint32_t)127U) + +#define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON)) + +#define IS_RCC_LSIDIV(__LSIDIV__) (((__LSIDIV__) == RCC_LSI_DIV1) || ((__LSIDIV__) == RCC_LSI_DIV128)) + +#define IS_RCC_MSI(__MSI__) (((__MSI__) == RCC_MSI_OFF) || ((__MSI__) == RCC_MSI_ON)) + +#define IS_RCC_MSI_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= (uint32_t)255U) + +#define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) ||((__PLL__) == RCC_PLL_OFF) || \ + ((__PLL__) == RCC_PLL_ON)) + +#define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_MSI) || \ + ((__SOURCE__) == RCC_PLLSOURCE_HSI) || \ + ((__SOURCE__) == RCC_PLLSOURCE_HSE)) + +#define IS_RCC_PLLM_VALUE(__VALUE__) (((__VALUE__) == RCC_PLLM_DIV1) || \ + ((__VALUE__) == RCC_PLLM_DIV2) || \ + ((__VALUE__) == RCC_PLLM_DIV3) || \ + ((__VALUE__) == RCC_PLLM_DIV4) || \ + ((__VALUE__) == RCC_PLLM_DIV5) || \ + ((__VALUE__) == RCC_PLLM_DIV6) || \ + ((__VALUE__) == RCC_PLLM_DIV7) || \ + ((__VALUE__) == RCC_PLLM_DIV8)) + +#define IS_RCC_PLLN_VALUE(__VALUE__) ((6U <= (__VALUE__)) && ((__VALUE__) <= 127U)) + +#define IS_RCC_PLLP_VALUE(__VALUE__) ((RCC_PLLP_DIV2 <= (__VALUE__)) && ((__VALUE__) <= RCC_PLLP_DIV32)) + +#define IS_RCC_PLLQ_VALUE(__VALUE__) ((RCC_PLLQ_DIV2 <= (__VALUE__)) && ((__VALUE__) <= RCC_PLLQ_DIV8)) + +#define IS_RCC_PLLR_VALUE(__VALUE__) ((RCC_PLLR_DIV2 <= (__VALUE__)) && ((__VALUE__) <= RCC_PLLR_DIV8)) + +#define IS_RCC_MSI_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIRANGE_0) || \ + ((__RANGE__) == RCC_MSIRANGE_1) || \ + ((__RANGE__) == RCC_MSIRANGE_2) || \ + ((__RANGE__) == RCC_MSIRANGE_3) || \ + ((__RANGE__) == RCC_MSIRANGE_4) || \ + ((__RANGE__) == RCC_MSIRANGE_5) || \ + ((__RANGE__) == RCC_MSIRANGE_6) || \ + ((__RANGE__) == RCC_MSIRANGE_7) || \ + ((__RANGE__) == RCC_MSIRANGE_8) || \ + ((__RANGE__) == RCC_MSIRANGE_9) || \ + ((__RANGE__) == RCC_MSIRANGE_10) || \ + ((__RANGE__) == RCC_MSIRANGE_11)) + +#if defined(DUAL_CORE) +#define IS_RCC_CLOCKTYPE(__CLK__) ((1U <= (__CLK__)) && ((__CLK__) <= (RCC_CLOCKTYPE_SYSCLK | \ + RCC_CLOCKTYPE_HCLK | \ + RCC_CLOCKTYPE_PCLK1 | \ + RCC_CLOCKTYPE_PCLK2 | \ + RCC_CLOCKTYPE_HCLK2 | \ + RCC_CLOCKTYPE_HCLK3))) +#else +#define IS_RCC_CLOCKTYPE(__CLK__) ((1U <= (__CLK__)) && ((__CLK__) <= (RCC_CLOCKTYPE_SYSCLK | \ + RCC_CLOCKTYPE_HCLK | \ + RCC_CLOCKTYPE_PCLK1 | \ + RCC_CLOCKTYPE_PCLK2 | \ + RCC_CLOCKTYPE_HCLK3))) +#endif /* DUAL_CORE */ + +#define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_MSI) || \ + ((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \ + ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK)) + +#define IS_RCC_HCLKx(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \ + ((__HCLK__) == RCC_SYSCLK_DIV3) || ((__HCLK__) == RCC_SYSCLK_DIV4) || \ + ((__HCLK__) == RCC_SYSCLK_DIV5) || ((__HCLK__) == RCC_SYSCLK_DIV6) || \ + ((__HCLK__) == RCC_SYSCLK_DIV8) || ((__HCLK__) == RCC_SYSCLK_DIV10) || \ + ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV32) || \ + ((__HCLK__) == RCC_SYSCLK_DIV64) || ((__HCLK__) == RCC_SYSCLK_DIV128) || \ + ((__HCLK__) == RCC_SYSCLK_DIV256) || ((__HCLK__) == RCC_SYSCLK_DIV512)) + +#define IS_RCC_PCLKx(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \ + ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \ + ((__PCLK__) == RCC_HCLK_DIV16)) + +#define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NONE) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV32)) + +#define IS_RCC_MCO(__MCOX__) ((__MCOX__) == RCC_MCO1_PA8) + +#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || \ + ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \ + ((__SOURCE__) == RCC_MCO1SOURCE_MSI) || \ + ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || \ + ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || \ + ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || \ + ((__SOURCE__) == RCC_MCO1SOURCE_LSI) || \ + ((__SOURCE__) == RCC_MCO1SOURCE_LSE) || \ + ((__SOURCE__) == RCC_MCO1SOURCE_PLLPCLK) || \ + ((__SOURCE__) == RCC_MCO1SOURCE_PLLQCLK)) + +#define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1) || ((__DIV__) == RCC_MCODIV_2) || \ + ((__DIV__) == RCC_MCODIV_4) || ((__DIV__) == RCC_MCODIV_8) || \ + ((__DIV__) == RCC_MCODIV_16)) + + +#define IS_RCC_STOP_WAKEUPCLOCK(__SOURCE__) (((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_MSI) || \ + ((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_HSI)) +/** + * @} + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup RCC_Exported_Types RCC Exported Types + * @{ + */ + + +/** + * @brief RCC PLL configuration structure definition + */ +typedef struct +{ + uint32_t PLLState; /*!< The new state of the PLL. + This parameter must be a value of @ref RCC_PLL_Config */ + + uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source. + This parameter must be a value of @ref RCC_PLL_Clock_Source */ + + uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock. + This parameter must be a value of @ref RCC_PLLM_Clock_Divider */ + + uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock. + This parameter must be a number between Min_Data = 6 and Max_Data = 127 */ + + uint32_t PLLP; /*!< PLLP: Division factor for ADC clock. + This parameter must be a value of @ref RCC_PLLP_Clock_Divider */ + + uint32_t PLLQ; /*!< PLLQ: Division factor for I2S2 and RNG clock. + This parameter must be a value of @ref RCC_PLLQ_Clock_Divider */ + + uint32_t PLLR; /*!< PLLR: Division for the main system clock. + User has to set the PLLR parameter correctly to not exceed max frequency 48 MHZ. + This parameter must be a value of @ref RCC_PLLR_Clock_Divider */ + +} RCC_PLLInitTypeDef; + +/** + * @brief RCC Internal/External Oscillator (HSE, HSI, MSI, LSE and LSI) configuration structure definition + */ +typedef struct +{ + uint32_t OscillatorType; /*!< The oscillators to be configured. + This parameter can be a combination of @ref RCC_Oscillator_Type */ + + uint32_t HSEState; /*!< The new state of the HSE. + This parameter can be a value of @ref RCC_HSE_Config */ + + uint32_t HSEDiv; /*!< The division factor of the HSE. + This parameter can be a value of @ref RCC_HSE_Div */ + + uint32_t LSEState; /*!< The new state of the LSE. + This parameter can be a value of @ref RCC_LSE_Config */ + + uint32_t HSIState; /*!< The new state of the HSI. + This parameter can be a value of @ref RCC_HSI_Config */ + + uint32_t HSICalibrationValue; /*!< The calibration trimming value (default is @ref RCC_HSICALIBRATION_DEFAULT). + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F */ + + uint32_t LSIState; /*!< The new state of the LSI. + This parameter can be a value of @ref RCC_LSI_Config */ + + uint32_t LSIDiv; /*!< The division factor of the LSI. + This parameter can be a value of @ref RCC_LSI_Div */ + + uint32_t MSIState; /*!< The new state of the MSI. + This parameter can be a value of @ref RCC_MSI_Config */ + + uint32_t MSICalibrationValue; /*!< The calibration trimming value (default is @ref RCC_MSICALIBRATION_DEFAULT). + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ + + uint32_t MSIClockRange; /*!< The MSI frequency range. + This parameter can be a value of @ref RCC_MSI_Clock_Range */ + + RCC_PLLInitTypeDef PLL; /*!< Main PLL structure parameters */ + +} RCC_OscInitTypeDef; + +/** + * @brief RCC System, AHB and APB buses clock configuration structure definition + */ +typedef struct +{ + uint32_t ClockType; /*!< The clock to be configured. + This parameter can be a combination of @ref RCC_System_Clock_Type */ + + uint32_t SYSCLKSource; /*!< The clock source used as system clock (SYSCLK). + This parameter can be a value of @ref RCC_System_Clock_Source */ + + uint32_t AHBCLKDivider; /*!< The AHBx clock (HCLK1) divider. This clock is derived from the system clock (SYSCLK). + This parameter can be a value of @ref RCC_AHBx_Clock_Source */ + + uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). + This parameter can be a value of @ref RCC_APBx_Clock_Source */ + + uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK). + This parameter can be a value of @ref RCC_APBx_Clock_Source */ + +#if defined(DUAL_CORE) + uint32_t AHBCLK2Divider; /*!< The AHB clock (HCLK2) divider. This clock is derived from the system clock (SYSCLK). + This parameter can be a value of @ref RCC_AHBx_Clock_Source */ + +#endif /* DUAL_CORE */ + uint32_t AHBCLK3Divider; /*!< The AHB shared clock (HCLK3) divider. This clock is derived from the system clock (SYSCLK). + This parameter can be a value of @ref RCC_AHBx_Clock_Source */ + +} RCC_ClkInitTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup RCC_Exported_Constants RCC Exported Constants + * @{ + */ + +/** @defgroup RCC_Oscillator_Type Oscillator Type + * @{ + */ +#define RCC_OSCILLATORTYPE_NONE 0x00000000U /*!< Oscillator configuration unchanged */ +#define RCC_OSCILLATORTYPE_HSE 0x00000001U /*!< HSE to configure */ +#define RCC_OSCILLATORTYPE_HSI 0x00000002U /*!< HSI to configure */ +#define RCC_OSCILLATORTYPE_LSE 0x00000004U /*!< LSE to configure */ +#define RCC_OSCILLATORTYPE_LSI 0x00000008U /*!< LSI to configure */ +#define RCC_OSCILLATORTYPE_MSI 0x00000020U /*!< MSI to configure */ +/** + * @} + */ + +/** @defgroup RCC_HSE_Config HSE Config + * @{ + */ +#define RCC_HSE_OFF 0x00000000U /*!< HSE clock deactivation */ +#define RCC_HSE_ON RCC_CR_HSEON /*!< HSE clock activation */ +#define RCC_HSE_BYPASS_PWR ((uint32_t)(RCC_CR_HSEBYPPWR | RCC_CR_HSEON)) /*!< TCXO external clock source for HSE clock */ +/** + * @} + */ + +/** @defgroup RCC_HSE_Div HSE Div + * @{ + */ +#define RCC_HSE_DIV1 0x00000000U /*!< HSE clock not divided */ +#define RCC_HSE_DIV2 RCC_CR_HSEPRE /*!< HSE clock divided by 2 */ +/** + * @} + */ + +/** @defgroup RCC_LSE_Config LSE Config + * @{ + */ +#define RCC_LSE_OFF 0U /*!< LSE clock deactivation */ +#define RCC_LSE_ON_RTC_ONLY RCC_BDCR_LSEON /*!< LSE clock activation for RTC only */ +#define RCC_LSE_ON ((uint32_t)(RCC_BDCR_LSESYSEN | RCC_BDCR_LSEON)) /*!< LSE clock activation for RTC and other peripherals */ +#define RCC_LSE_BYPASS_RTC_ONLY ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON)) /*!< External clock source for LSE clock */ +#define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSESYSEN | RCC_BDCR_LSEON)) /*!< External clock source for LSE clock */ + +/** + * @} + */ + +/** @defgroup RCC_HSI_Config HSI Config + * @{ + */ +#define RCC_HSI_OFF 0x00000000U /*!< HSI clock deactivation */ +#define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */ + +#define RCC_HSICALIBRATION_DEFAULT 64U /*!< Default HSI calibration trimming value */ +/** + * @} + */ + +/** @defgroup RCC_LSI_Config LSI Config + * @{ + */ +#define RCC_LSI_OFF 0x00000000U /*!< LSI clock deactivation */ +#define RCC_LSI_ON RCC_CSR_LSION /*!< LSI clock activation */ +/** + * @} + */ + +/** @defgroup RCC_LSI_Div LSI Div + * @{ + */ +#define RCC_LSI_DIV1 LL_RCC_LSI_PREDIV_1 /*!< LSI clock not divided */ +#define RCC_LSI_DIV128 LL_RCC_LSI_PREDIV_128 /*!< LSI clock divided by 128 */ +/** + * @} + */ + +/** @defgroup RCC_MSI_Config MSI Config + * @{ + */ +#define RCC_MSI_OFF 0x00000000U /*!< MSI clock deactivation */ +#define RCC_MSI_ON RCC_CR_MSION /*!< MSI clock activation */ + +#define RCC_MSICALIBRATION_DEFAULT 0U /*!< Default MSI calibration trimming value */ +/** + * @} + */ + + +/** @defgroup RCC_PLL_Config PLL Config + * @{ + */ +#define RCC_PLL_NONE 0x00000000U /*!< PLL configuration unchanged */ +#define RCC_PLL_OFF 0x00000001U /*!< PLL deactivation */ +#define RCC_PLL_ON 0x00000002U /*!< PLL activation */ +/** + * @} + */ + +/** @defgroup RCC_PLLM_Clock_Divider PLLM Clock Divider + * @{ + */ +#define RCC_PLLM_DIV1 LL_RCC_PLLM_DIV_1 /*!< PLLM division factor = 1 */ +#define RCC_PLLM_DIV2 LL_RCC_PLLM_DIV_2 /*!< PLLM division factor = 2 */ +#define RCC_PLLM_DIV3 LL_RCC_PLLM_DIV_3 /*!< PLLM division factor = 3 */ +#define RCC_PLLM_DIV4 LL_RCC_PLLM_DIV_4 /*!< PLLM division factor = 4 */ +#define RCC_PLLM_DIV5 LL_RCC_PLLM_DIV_5 /*!< PLLM division factor = 5 */ +#define RCC_PLLM_DIV6 LL_RCC_PLLM_DIV_6 /*!< PLLM division factor = 6 */ +#define RCC_PLLM_DIV7 LL_RCC_PLLM_DIV_7 /*!< PLLM division factor = 7 */ +#define RCC_PLLM_DIV8 LL_RCC_PLLM_DIV_8 /*!< PLLM division factor = 8 */ +/** + * @} + */ + +/** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider + * @{ + */ +#define RCC_PLLP_DIV2 LL_RCC_PLLP_DIV_2 /*!< PLLP division factor = 2 */ +#define RCC_PLLP_DIV3 LL_RCC_PLLP_DIV_3 /*!< PLLP division factor = 3 */ +#define RCC_PLLP_DIV4 LL_RCC_PLLP_DIV_4 /*!< PLLP division factor = 4 */ +#define RCC_PLLP_DIV5 LL_RCC_PLLP_DIV_5 /*!< PLLP division factor = 5 */ +#define RCC_PLLP_DIV6 LL_RCC_PLLP_DIV_6 /*!< PLLP division factor = 6 */ +#define RCC_PLLP_DIV7 LL_RCC_PLLP_DIV_7 /*!< PLLP division factor = 7 */ +#define RCC_PLLP_DIV8 LL_RCC_PLLP_DIV_8 /*!< PLLP division factor = 8 */ +#define RCC_PLLP_DIV9 LL_RCC_PLLP_DIV_9 /*!< PLLP division factor = 9 */ +#define RCC_PLLP_DIV10 LL_RCC_PLLP_DIV_10 /*!< PLLP division factor = 10 */ +#define RCC_PLLP_DIV11 LL_RCC_PLLP_DIV_11 /*!< PLLP division factor = 11 */ +#define RCC_PLLP_DIV12 LL_RCC_PLLP_DIV_12 /*!< PLLP division factor = 12 */ +#define RCC_PLLP_DIV13 LL_RCC_PLLP_DIV_13 /*!< PLLP division factor = 13 */ +#define RCC_PLLP_DIV14 LL_RCC_PLLP_DIV_14 /*!< PLLP division factor = 14 */ +#define RCC_PLLP_DIV15 LL_RCC_PLLP_DIV_15 /*!< PLLP division factor = 15 */ +#define RCC_PLLP_DIV16 LL_RCC_PLLP_DIV_16 /*!< PLLP division factor = 16 */ +#define RCC_PLLP_DIV17 LL_RCC_PLLP_DIV_17 /*!< PLLP division factor = 17 */ +#define RCC_PLLP_DIV18 LL_RCC_PLLP_DIV_18 /*!< PLLP division factor = 18 */ +#define RCC_PLLP_DIV19 LL_RCC_PLLP_DIV_19 /*!< PLLP division factor = 19 */ +#define RCC_PLLP_DIV20 LL_RCC_PLLP_DIV_20 /*!< PLLP division factor = 20 */ +#define RCC_PLLP_DIV21 LL_RCC_PLLP_DIV_21 /*!< PLLP division factor = 21 */ +#define RCC_PLLP_DIV22 LL_RCC_PLLP_DIV_22 /*!< PLLP division factor = 22 */ +#define RCC_PLLP_DIV23 LL_RCC_PLLP_DIV_23 /*!< PLLP division factor = 23 */ +#define RCC_PLLP_DIV24 LL_RCC_PLLP_DIV_24 /*!< PLLP division factor = 24 */ +#define RCC_PLLP_DIV25 LL_RCC_PLLP_DIV_25 /*!< PLLP division factor = 25 */ +#define RCC_PLLP_DIV26 LL_RCC_PLLP_DIV_26 /*!< PLLP division factor = 26 */ +#define RCC_PLLP_DIV27 LL_RCC_PLLP_DIV_27 /*!< PLLP division factor = 27 */ +#define RCC_PLLP_DIV28 LL_RCC_PLLP_DIV_28 /*!< PLLP division factor = 28 */ +#define RCC_PLLP_DIV29 LL_RCC_PLLP_DIV_29 /*!< PLLP division factor = 29 */ +#define RCC_PLLP_DIV30 LL_RCC_PLLP_DIV_30 /*!< PLLP division factor = 30 */ +#define RCC_PLLP_DIV31 LL_RCC_PLLP_DIV_31 /*!< PLLP division factor = 31 */ +#define RCC_PLLP_DIV32 LL_RCC_PLLP_DIV_32 /*!< PLLP division factor = 32 */ +/** + * @} + */ + +/** @defgroup RCC_PLLQ_Clock_Divider PLLQ Clock Divider + * @{ + */ +#define RCC_PLLQ_DIV2 LL_RCC_PLLQ_DIV_2 /*!< PLLQ division factor = 2 */ +#define RCC_PLLQ_DIV3 LL_RCC_PLLQ_DIV_3 /*!< PLLQ division factor = 3 */ +#define RCC_PLLQ_DIV4 LL_RCC_PLLQ_DIV_4 /*!< PLLQ division factor = 4 */ +#define RCC_PLLQ_DIV5 LL_RCC_PLLQ_DIV_5 /*!< PLLQ division factor = 5 */ +#define RCC_PLLQ_DIV6 LL_RCC_PLLQ_DIV_6 /*!< PLLQ division factor = 6 */ +#define RCC_PLLQ_DIV7 LL_RCC_PLLQ_DIV_7 /*!< PLLQ division factor = 7 */ +#define RCC_PLLQ_DIV8 LL_RCC_PLLQ_DIV_8 /*!< PLLQ division factor = 8 */ +/** + * @} + */ + +/** @defgroup RCC_PLLR_Clock_Divider PLLR Clock Divider + * @{ + */ +#define RCC_PLLR_DIV2 LL_RCC_PLLR_DIV_2 /*!< PLLR division factor = 2 */ +#define RCC_PLLR_DIV3 LL_RCC_PLLR_DIV_3 /*!< PLLR division factor = 3 */ +#define RCC_PLLR_DIV4 LL_RCC_PLLR_DIV_4 /*!< PLLR division factor = 4 */ +#define RCC_PLLR_DIV5 LL_RCC_PLLR_DIV_5 /*!< PLLR division factor = 5 */ +#define RCC_PLLR_DIV6 LL_RCC_PLLR_DIV_6 /*!< PLLR division factor = 6 */ +#define RCC_PLLR_DIV7 LL_RCC_PLLR_DIV_7 /*!< PLLR division factor = 7 */ +#define RCC_PLLR_DIV8 LL_RCC_PLLR_DIV_8 /*!< PLLR division factor = 8 */ +/** + * @} + */ + +/** @defgroup RCC_PLL_Clock_Source PLL Clock Source + * @{ + */ +#define RCC_PLLSOURCE_NONE LL_RCC_PLLSOURCE_NONE /*!< No clock selected as PLL entry clock source */ +#define RCC_PLLSOURCE_MSI LL_RCC_PLLSOURCE_MSI /*!< MSI clock selected as PLL entry clock source */ +#define RCC_PLLSOURCE_HSI LL_RCC_PLLSOURCE_HSI /*!< HSI clock selected as PLL entry clock source */ +#define RCC_PLLSOURCE_HSE LL_RCC_PLLSOURCE_HSE /*!< HSE clock selected as PLL entry clock source */ +/** + * @} + */ + +/** @defgroup RCC_PLL_Clock_Output PLL Clock Output + * @{ + */ +#define RCC_PLL_SYSCLK RCC_PLLCFGR_PLLREN /*!< PLLCLK selected from main PLL */ +#define RCC_PLL_I2S2CLK RCC_PLLCFGR_PLLQEN /*!< PLLI2S2CLK selected from main PLL */ +#define RCC_PLL_RNGCLK RCC_PLLCFGR_PLLQEN /*!< PLLRNGCLK selected from main PLL */ +#define RCC_PLL_ADCCLK RCC_PLLCFGR_PLLPEN /*!< PLLADCCLK selected from main PLL */ +/** + * @} + */ + +/** @defgroup RCC_MSI_Clock_Range MSI Clock Range + * @{ + */ +#define RCC_MSIRANGE_0 LL_RCC_MSIRANGE_0 /*!< MSI = 100 KHz */ +#define RCC_MSIRANGE_1 LL_RCC_MSIRANGE_1 /*!< MSI = 200 KHz */ +#define RCC_MSIRANGE_2 LL_RCC_MSIRANGE_2 /*!< MSI = 400 KHz */ +#define RCC_MSIRANGE_3 LL_RCC_MSIRANGE_3 /*!< MSI = 800 KHz */ +#define RCC_MSIRANGE_4 LL_RCC_MSIRANGE_4 /*!< MSI = 1 MHz */ +#define RCC_MSIRANGE_5 LL_RCC_MSIRANGE_5 /*!< MSI = 2 MHz */ +#define RCC_MSIRANGE_6 LL_RCC_MSIRANGE_6 /*!< MSI = 4 MHz */ +#define RCC_MSIRANGE_7 LL_RCC_MSIRANGE_7 /*!< MSI = 8 MHz */ +#define RCC_MSIRANGE_8 LL_RCC_MSIRANGE_8 /*!< MSI = 16 MHz */ +#define RCC_MSIRANGE_9 LL_RCC_MSIRANGE_9 /*!< MSI = 24 MHz */ +#define RCC_MSIRANGE_10 LL_RCC_MSIRANGE_10 /*!< MSI = 32 MHz */ +#define RCC_MSIRANGE_11 LL_RCC_MSIRANGE_11 /*!< MSI = 48 MHz */ +/** + * @} + */ + +/** @defgroup RCC_System_Clock_Type System Clock Type + * @{ + */ +#define RCC_CLOCKTYPE_SYSCLK 0x00000001U /*!< SYSCLK to configure */ +#define RCC_CLOCKTYPE_HCLK 0x00000002U /*!< HCLK to configure */ +#define RCC_CLOCKTYPE_PCLK1 0x00000004U /*!< PCLK1 to configure */ +#define RCC_CLOCKTYPE_PCLK2 0x00000008U /*!< PCLK2 to configure */ +#if defined(DUAL_CORE) +#define RCC_CLOCKTYPE_HCLK2 0x00000020U /*!< HCLK2 to configure */ +#endif /* DUAL_CORE */ +#define RCC_CLOCKTYPE_HCLK3 0x00000040U /*!< HCLK3 to configure */ +/** + * @} + */ + +/** @defgroup RCC_System_Clock_Source System Clock Source + * @{ + */ +#define RCC_SYSCLKSOURCE_MSI LL_RCC_SYS_CLKSOURCE_MSI /*!< MSI selected as system clock */ +#define RCC_SYSCLKSOURCE_HSI LL_RCC_SYS_CLKSOURCE_HSI /*!< HSI selected as system clock */ +#define RCC_SYSCLKSOURCE_HSE LL_RCC_SYS_CLKSOURCE_HSE /*!< HSE selected as system clock */ +#define RCC_SYSCLKSOURCE_PLLCLK LL_RCC_SYS_CLKSOURCE_PLL /*!< PLL selected as system clock */ +/** + * @} + */ + +/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status + * @{ + */ +#define RCC_SYSCLKSOURCE_STATUS_MSI LL_RCC_SYS_CLKSOURCE_STATUS_MSI /*!< MSI used as system clock */ +#define RCC_SYSCLKSOURCE_STATUS_HSI LL_RCC_SYS_CLKSOURCE_STATUS_HSI /*!< HSI used as system clock */ +#define RCC_SYSCLKSOURCE_STATUS_HSE LL_RCC_SYS_CLKSOURCE_STATUS_HSE /*!< HSE used as system clock */ +#define RCC_SYSCLKSOURCE_STATUS_PLLCLK LL_RCC_SYS_CLKSOURCE_STATUS_PLL /*!< PLL used as system clock */ +/** + * @} + */ + +/** @defgroup RCC_AHBx_Clock_Source AHB Clock Source + * @{ + */ +#define RCC_SYSCLK_DIV1 LL_RCC_SYSCLK_DIV_1 /*!< SYSCLK not divided */ +#define RCC_SYSCLK_DIV2 LL_RCC_SYSCLK_DIV_2 /*!< SYSCLK divided by 2 */ +#define RCC_SYSCLK_DIV3 LL_RCC_SYSCLK_DIV_3 /*!< SYSCLK divided by 3 */ +#define RCC_SYSCLK_DIV4 LL_RCC_SYSCLK_DIV_4 /*!< SYSCLK divided by 4 */ +#define RCC_SYSCLK_DIV5 LL_RCC_SYSCLK_DIV_5 /*!< SYSCLK divided by 5 */ +#define RCC_SYSCLK_DIV6 LL_RCC_SYSCLK_DIV_6 /*!< SYSCLK divided by 6 */ +#define RCC_SYSCLK_DIV8 LL_RCC_SYSCLK_DIV_8 /*!< SYSCLK divided by 8 */ +#define RCC_SYSCLK_DIV10 LL_RCC_SYSCLK_DIV_10 /*!< SYSCLK divided by 10 */ +#define RCC_SYSCLK_DIV16 LL_RCC_SYSCLK_DIV_16 /*!< SYSCLK divided by 16 */ +#define RCC_SYSCLK_DIV32 LL_RCC_SYSCLK_DIV_32 /*!< SYSCLK divided by 32 */ +#define RCC_SYSCLK_DIV64 LL_RCC_SYSCLK_DIV_64 /*!< SYSCLK divided by 64 */ +#define RCC_SYSCLK_DIV128 LL_RCC_SYSCLK_DIV_128 /*!< SYSCLK divided by 128 */ +#define RCC_SYSCLK_DIV256 LL_RCC_SYSCLK_DIV_256 /*!< SYSCLK divided by 256 */ +#define RCC_SYSCLK_DIV512 LL_RCC_SYSCLK_DIV_512 /*!< SYSCLK divided by 512 */ +/** + * @} + */ + +/** @defgroup RCC_APBx_Clock_Source APB1 Clock Source + * @{ + */ +#define RCC_HCLK_DIV1 LL_RCC_APB1_DIV_1 /*!< HCLK not divided */ +#define RCC_HCLK_DIV2 LL_RCC_APB1_DIV_2 /*!< HCLK divided by 2 */ +#define RCC_HCLK_DIV4 LL_RCC_APB1_DIV_4 /*!< HCLK divided by 4 */ +#define RCC_HCLK_DIV8 LL_RCC_APB1_DIV_8 /*!< HCLK divided by 8 */ +#define RCC_HCLK_DIV16 LL_RCC_APB1_DIV_16 /*!< HCLK divided by 16 */ +/** + * @} + */ + +/** @defgroup RCC_RTC_Clock_Source RTC Clock Source + * @{ + */ +#define RCC_RTCCLKSOURCE_NONE LL_RCC_RTC_CLKSOURCE_NONE /*!< No clock used as RTC clock */ +#define RCC_RTCCLKSOURCE_LSE LL_RCC_RTC_CLKSOURCE_LSE /*!< LSE oscillator clock used as RTC clock */ +#define RCC_RTCCLKSOURCE_LSI LL_RCC_RTC_CLKSOURCE_LSI /*!< LSI oscillator clock used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV32 LL_RCC_RTC_CLKSOURCE_HSE_DIV32 /*!< HSE oscillator clock divided by 32 used as RTC clock */ +/** + * @} + */ + +/** @defgroup RCC_MCO_Index MCO Index + * @{ + */ + +/* @cond */ +/* 32 28 20 16 0 + -------------------------------- + | MCO | GPIO | GPIO | GPIO | + | Index | AF | Port | Pin | + -------------------------------*/ + +#define RCC_MCO_GPIOPORT_POS 16U +#define RCC_MCO_GPIOPORT_MASK (0xFUL << RCC_MCO_GPIOPORT_POS) +#define RCC_MCO_GPIOAF_POS 20U +#define RCC_MCO_GPIOAF_MASK (0xFFUL << RCC_MCO_GPIOAF_POS) +#define RCC_MCO_INDEX_POS 28U +#define RCC_MCO_INDEX_MASK (0x1UL << RCC_MCO_INDEX_POS) + +#define RCC_MCO1_INDEX (0x0UL << RCC_MCO_INDEX_POS) /*!< MCO1 index */ +/* @endcond */ + +#define RCC_MCO1_PA8 (RCC_MCO1_INDEX | (GPIO_AF0_MCO << RCC_MCO_GPIOAF_POS) | \ + (GPIO_GET_INDEX(GPIOA) << RCC_MCO_GPIOPORT_POS) | GPIO_PIN_8) +#define RCC_MCO1 RCC_MCO1_PA8 + +#define RCC_MCO RCC_MCO1 /*!< MCO1 to be compliant with other families with 1 MCO */ +/** + * @} + */ + +/** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source + * @{ + */ +#define RCC_MCO1SOURCE_NOCLOCK LL_RCC_MCO1SOURCE_NOCLOCK /*!< MCO1 output disabled, no clock on MCO1 */ +#define RCC_MCO1SOURCE_SYSCLK LL_RCC_MCO1SOURCE_SYSCLK /*!< SYSCLK selected as MCO1 source */ +#define RCC_MCO1SOURCE_MSI LL_RCC_MCO1SOURCE_MSI /*!< MSI selected as MCO1 source */ +#define RCC_MCO1SOURCE_HSI LL_RCC_MCO1SOURCE_HSI /*!< HSI selected as MCO1 source */ +#define RCC_MCO1SOURCE_HSE LL_RCC_MCO1SOURCE_HSE /*!< HSE after stabilization selected as MCO1 source */ +#define RCC_MCO1SOURCE_PLLCLK LL_RCC_MCO1SOURCE_PLLCLK /*!< Main PLLRCLK selected as MCO1 source */ +#define RCC_MCO1SOURCE_LSI LL_RCC_MCO1SOURCE_LSI /*!< LSI selected as MCO1 source */ +#define RCC_MCO1SOURCE_LSE LL_RCC_MCO1SOURCE_LSE /*!< LSE selected as MCO1 source */ +#define RCC_MCO1SOURCE_PLLPCLK LL_RCC_MCO1SOURCE_PLLPCLK /*!< Main PLLPCLK selected as MCO1 source */ +#define RCC_MCO1SOURCE_PLLQCLK LL_RCC_MCO1SOURCE_PLLQCLK /*!< Main PLLQCLK selected as MCO1 source */ +/** + * @} + */ + +/** @defgroup RCC_MCOx_Clock_Prescaler MCO Clock Prescaler + * @{ + */ +#define RCC_MCODIV_1 LL_RCC_MCO1_DIV_1 /*!< MCO not divided */ +#define RCC_MCODIV_2 LL_RCC_MCO1_DIV_2 /*!< MCO divided by 2 */ +#define RCC_MCODIV_4 LL_RCC_MCO1_DIV_4 /*!< MCO divided by 4 */ +#define RCC_MCODIV_8 LL_RCC_MCO1_DIV_8 /*!< MCO divided by 8 */ +#define RCC_MCODIV_16 LL_RCC_MCO1_DIV_16 /*!< MCO divided by 16 */ +/** + * @} + */ + + +/** @defgroup RCC_Interrupt Interrupts + * @{ + */ +#define RCC_IT_LSIRDY LL_RCC_CIFR_LSIRDYF /*!< LSI Ready Interrupt flag */ +#define RCC_IT_LSERDY LL_RCC_CIFR_LSERDYF /*!< LSE Ready Interrupt flag */ +#define RCC_IT_MSIRDY LL_RCC_CIFR_MSIRDYF /*!< MSI Ready Interrupt flag */ +#define RCC_IT_HSIRDY LL_RCC_CIFR_HSIRDYF /*!< HSI Ready Interrupt flag */ +#define RCC_IT_HSERDY LL_RCC_CIFR_HSERDYF /*!< HSE Ready Interrupt flag */ +#define RCC_IT_PLLRDY LL_RCC_CIFR_PLLRDYF /*!< PLL Ready Interrupt flag */ +#define RCC_IT_HSECSS LL_RCC_CIFR_CSSF /*!< HSE Clock Security System Interrupt flag */ +#define RCC_IT_LSECSS LL_RCC_CIFR_LSECSSF /*!< LSE Clock Security System Interrupt flag */ +/** + * @} + */ + + +/** @defgroup RCC_Flag Flags + * Elements values convention: XXXYYYYYb + * - YYYYY : Flag position in the register + * - XXX : Register index + * - 001: CR register + * - 010: BDCR register + * - 011: CSR register + * @{ + */ +/* Flags in the CR register */ +#define RCC_FLAG_MSIRDY ((CR_REG_INDEX << REG_INDEX_POS) | RCC_CR_MSIRDY_Pos) /*!< MSI Ready flag */ +#define RCC_FLAG_HSIRDY ((CR_REG_INDEX << REG_INDEX_POS) | RCC_CR_HSIRDY_Pos) /*!< HSI Ready flag */ +#define RCC_FLAG_HSIKERDY ((CR_REG_INDEX << REG_INDEX_POS) | RCC_CR_HSIKERDY_Pos) /*!< HSI Ready flag */ +#define RCC_FLAG_HSERDY ((CR_REG_INDEX << REG_INDEX_POS) | RCC_CR_HSERDY_Pos) /*!< HSE Ready flag */ +#define RCC_FLAG_PLLRDY ((CR_REG_INDEX << REG_INDEX_POS) | RCC_CR_PLLRDY_Pos) /*!< PLL Ready flag */ + +/* Flags in the BDCR register */ +#define RCC_FLAG_LSERDY ((BDCR_REG_INDEX << REG_INDEX_POS) | RCC_BDCR_LSERDY_Pos) /*!< LSE Ready flag */ +#define RCC_FLAG_LSECSSD ((BDCR_REG_INDEX << REG_INDEX_POS) | RCC_BDCR_LSECSSD_Pos) /*!< LSE Clock Security System failure detection flag */ +#define RCC_FLAG_LSESYSRDY ((BDCR_REG_INDEX << REG_INDEX_POS) | RCC_BDCR_LSESYSRDY_Pos) /*!< LSE system clock ready flag */ + +/* Flags in the CSR register */ +#define RCC_FLAG_LSIRDY ((CSR_REG_INDEX << REG_INDEX_POS) | RCC_CSR_LSIRDY_Pos) /*!< LSI Ready flag */ +#define RCC_FLAG_RFRST ((CSR_REG_INDEX << REG_INDEX_POS) | RCC_CSR_RFRSTF_Pos) /*!< Sub-GHz radio reset flag */ +#define RCC_FLAG_RFILARSTF ((CSR_REG_INDEX << REG_INDEX_POS) | RCC_CSR_RFILARSTF_Pos) /*!< Sub-GHz radio illegal command flag */ +#define RCC_FLAG_OBLRST ((CSR_REG_INDEX << REG_INDEX_POS) | RCC_CSR_OBLRSTF_Pos) /*!< Option Byte Loader reset flag */ +#define RCC_FLAG_PINRST ((CSR_REG_INDEX << REG_INDEX_POS) | RCC_CSR_PINRSTF_Pos) /*!< Pin reset flag (NRST pin) */ +#define RCC_FLAG_BORRST ((CSR_REG_INDEX << REG_INDEX_POS) | RCC_CSR_BORRSTF_Pos) /*!< BOR reset flag */ +#define RCC_FLAG_SFTRST ((CSR_REG_INDEX << REG_INDEX_POS) | RCC_CSR_SFTRSTF_Pos) /*!< Software Reset flag */ +#define RCC_FLAG_IWDGRST ((CSR_REG_INDEX << REG_INDEX_POS) | RCC_CSR_IWDGRSTF_Pos) /*!< Watchdog reset flag */ +#define RCC_FLAG_WWDGRST ((CSR_REG_INDEX << REG_INDEX_POS) | RCC_CSR_WWDGRSTF_Pos) /*!< Window watchdog reset flag */ +#define RCC_FLAG_LPWRRST ((CSR_REG_INDEX << REG_INDEX_POS) | RCC_CSR_LPWRRSTF_Pos) /*!< Low-Power reset flag */ +/** + * @} + */ + +/** @defgroup RCC_LSEDrive_Config LSE Drive Configuration + * @{ + */ +#define RCC_LSEDRIVE_LOW LL_RCC_LSEDRIVE_LOW /*!< LSE low drive capability */ +#define RCC_LSEDRIVE_MEDIUMLOW LL_RCC_LSEDRIVE_MEDIUMLOW /*!< LSE medium low drive capability */ +#define RCC_LSEDRIVE_MEDIUMHIGH LL_RCC_LSEDRIVE_MEDIUMHIGH /*!< LSE medium high drive capability */ +#define RCC_LSEDRIVE_HIGH LL_RCC_LSEDRIVE_HIGH /*!< LSE high drive capability */ +/** + * @} + */ + +/** @defgroup RCC_Stop_WakeUpClock Wake-Up from STOP Clock + * @{ + */ +#define RCC_STOP_WAKEUPCLOCK_MSI LL_RCC_STOP_WAKEUPCLOCK_MSI /*!< MSI selected after wake-up from STOP */ +#define RCC_STOP_WAKEUPCLOCK_HSI LL_RCC_STOP_WAKEUPCLOCK_HSI /*!< HSI selected after wake-up from STOP */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ + +/** @defgroup RCC_Exported_Macros RCC Exported Macros + * @{ + */ + +/** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable + * @brief Enable or disable the AHB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#if defined(CORE_CM0PLUS) +#define __HAL_RCC_DMA1_CLK_ENABLE() LL_C2_AHB1_GRP1_EnableClock(LL_C2_AHB1_GRP1_PERIPH_DMA1) +#define __HAL_RCC_DMA2_CLK_ENABLE() LL_C2_AHB1_GRP1_EnableClock(LL_C2_AHB1_GRP1_PERIPH_DMA2) +#define __HAL_RCC_DMAMUX1_CLK_ENABLE() LL_C2_AHB1_GRP1_EnableClock(LL_C2_AHB1_GRP1_PERIPH_DMAMUX1) +#define __HAL_RCC_CRC_CLK_ENABLE() LL_C2_AHB1_GRP1_EnableClock(LL_C2_AHB1_GRP1_PERIPH_CRC) + +#define __HAL_RCC_DMA1_CLK_DISABLE() LL_C2_AHB1_GRP1_DisableClock(LL_C2_AHB1_GRP1_PERIPH_DMA1) +#define __HAL_RCC_DMA2_CLK_DISABLE() LL_C2_AHB1_GRP1_DisableClock(LL_C2_AHB1_GRP1_PERIPH_DMA2) +#define __HAL_RCC_DMAMUX1_CLK_DISABLE() LL_C2_AHB1_GRP1_DisableClock(LL_C2_AHB1_GRP1_PERIPH_DMAMUX1) +#define __HAL_RCC_CRC_CLK_DISABLE() LL_C2_AHB1_GRP1_DisableClock(LL_C2_AHB1_GRP1_PERIPH_CRC) +#else +#define __HAL_RCC_DMA1_CLK_ENABLE() LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_DMA1) +#define __HAL_RCC_DMA2_CLK_ENABLE() LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_DMA2) +#define __HAL_RCC_DMAMUX1_CLK_ENABLE() LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_DMAMUX1) +#define __HAL_RCC_CRC_CLK_ENABLE() LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_CRC) + +#define __HAL_RCC_DMA1_CLK_DISABLE() LL_AHB1_GRP1_DisableClock(LL_AHB1_GRP1_PERIPH_DMA1) +#define __HAL_RCC_DMA2_CLK_DISABLE() LL_AHB1_GRP1_DisableClock(LL_AHB1_GRP1_PERIPH_DMA2) +#define __HAL_RCC_DMAMUX1_CLK_DISABLE() LL_AHB1_GRP1_DisableClock(LL_AHB1_GRP1_PERIPH_DMAMUX1) +#define __HAL_RCC_CRC_CLK_DISABLE() LL_AHB1_GRP1_DisableClock(LL_AHB1_GRP1_PERIPH_CRC) +#endif /* CORE_CM0PLUS */ +/** + * @} + */ + +/** @defgroup RCC_AHB2_Peripheral_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable + * @brief Enable or disable the AHB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#if defined(CORE_CM0PLUS) +#define __HAL_RCC_GPIOA_CLK_ENABLE() LL_C2_AHB2_GRP1_EnableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOA) +#define __HAL_RCC_GPIOB_CLK_ENABLE() LL_C2_AHB2_GRP1_EnableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOB) +#define __HAL_RCC_GPIOC_CLK_ENABLE() LL_C2_AHB2_GRP1_EnableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOC) +#define __HAL_RCC_GPIOH_CLK_ENABLE() LL_C2_AHB2_GRP1_EnableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOH) + +#define __HAL_RCC_GPIOA_CLK_DISABLE() LL_C2_AHB2_GRP1_DisableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOA) +#define __HAL_RCC_GPIOB_CLK_DISABLE() LL_C2_AHB2_GRP1_DisableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOB) +#define __HAL_RCC_GPIOC_CLK_DISABLE() LL_C2_AHB2_GRP1_DisableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOC) +#define __HAL_RCC_GPIOH_CLK_DISABLE() LL_C2_AHB2_GRP1_DisableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOH) +#else +#define __HAL_RCC_GPIOA_CLK_ENABLE() LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOA) +#define __HAL_RCC_GPIOB_CLK_ENABLE() LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOB) +#define __HAL_RCC_GPIOC_CLK_ENABLE() LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOC) +#define __HAL_RCC_GPIOH_CLK_ENABLE() LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOH) + +#define __HAL_RCC_GPIOA_CLK_DISABLE() LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_GPIOA) +#define __HAL_RCC_GPIOB_CLK_DISABLE() LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_GPIOB) +#define __HAL_RCC_GPIOC_CLK_DISABLE() LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_GPIOC) +#define __HAL_RCC_GPIOH_CLK_DISABLE() LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_GPIOH) +#endif /* CORE_CM0PLUS */ +/** + * @} + */ + +/** @defgroup RCC_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable + * @brief Enable or disable the AHB3 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#if defined(CORE_CM0PLUS) +#define __HAL_RCC_PKA_CLK_ENABLE() LL_C2_AHB3_GRP1_EnableClock(LL_C2_AHB3_GRP1_PERIPH_PKA) +#define __HAL_RCC_AES_CLK_ENABLE() LL_C2_AHB3_GRP1_EnableClock(LL_C2_AHB3_GRP1_PERIPH_AES) +#define __HAL_RCC_RNG_CLK_ENABLE() LL_C2_AHB3_GRP1_EnableClock(LL_C2_AHB3_GRP1_PERIPH_RNG) +#define __HAL_RCC_HSEM_CLK_ENABLE() LL_C2_AHB3_GRP1_EnableClock(LL_C2_AHB3_GRP1_PERIPH_HSEM) +#define __HAL_RCC_IPCC_CLK_ENABLE() LL_C2_AHB3_GRP1_EnableClock(LL_C2_AHB3_GRP1_PERIPH_IPCC) +#define __HAL_RCC_FLASH_CLK_ENABLE() LL_C2_AHB3_GRP1_EnableClock(LL_C2_AHB3_GRP1_PERIPH_FLASH) + +#define __HAL_RCC_PKA_CLK_DISABLE() LL_C2_AHB3_GRP1_DisableClock(LL_C2_AHB3_GRP1_PERIPH_PKA) +#define __HAL_RCC_AES_CLK_DISABLE() LL_C2_AHB3_GRP1_DisableClock(LL_C2_AHB3_GRP1_PERIPH_AES) +#define __HAL_RCC_RNG_CLK_DISABLE() LL_C2_AHB3_GRP1_DisableClock(LL_C2_AHB3_GRP1_PERIPH_RNG) +#define __HAL_RCC_HSEM_CLK_DISABLE() LL_C2_AHB3_GRP1_DisableClock(LL_C2_AHB3_GRP1_PERIPH_HSEM) +#define __HAL_RCC_IPCC_CLK_DISABLE() LL_C2_AHB3_GRP1_DisableClock(LL_C2_AHB3_GRP1_PERIPH_IPCC) +#define __HAL_RCC_FLASH_CLK_DISABLE() LL_C2_AHB3_GRP1_DisableClock(LL_C2_AHB3_GRP1_PERIPH_FLASH) +#else +#define __HAL_RCC_PKA_CLK_ENABLE() LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_PKA) +#define __HAL_RCC_AES_CLK_ENABLE() LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_AES) +#define __HAL_RCC_RNG_CLK_ENABLE() LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_RNG) +#define __HAL_RCC_HSEM_CLK_ENABLE() LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_HSEM) +#define __HAL_RCC_IPCC_CLK_ENABLE() LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_IPCC) +#define __HAL_RCC_FLASH_CLK_ENABLE() LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_FLASH) + +#define __HAL_RCC_PKA_CLK_DISABLE() LL_AHB3_GRP1_DisableClock(LL_AHB3_GRP1_PERIPH_PKA) +#define __HAL_RCC_AES_CLK_DISABLE() LL_AHB3_GRP1_DisableClock(LL_AHB3_GRP1_PERIPH_AES) +#define __HAL_RCC_RNG_CLK_DISABLE() LL_AHB3_GRP1_DisableClock(LL_AHB3_GRP1_PERIPH_RNG) +#define __HAL_RCC_HSEM_CLK_DISABLE() LL_AHB3_GRP1_DisableClock(LL_AHB3_GRP1_PERIPH_HSEM) +#define __HAL_RCC_IPCC_CLK_DISABLE() LL_AHB3_GRP1_DisableClock(LL_AHB3_GRP1_PERIPH_IPCC) +#define __HAL_RCC_FLASH_CLK_DISABLE() LL_AHB3_GRP1_DisableClock(LL_AHB3_GRP1_PERIPH_FLASH) +#endif /* CORE_CM0PLUS */ +/** + * @} + */ + +/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable + * @brief Enable or disable the APB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#if defined(CORE_CM0PLUS) +#define __HAL_RCC_TIM2_CLK_ENABLE() LL_C2_APB1_GRP1_EnableClock(LL_C2_APB1_GRP1_PERIPH_TIM2) +#define __HAL_RCC_RTCAPB_CLK_ENABLE() LL_C2_APB1_GRP1_EnableClock(LL_C2_APB1_GRP1_PERIPH_RTCAPB) +#define __HAL_RCC_SPI2_CLK_ENABLE() LL_C2_APB1_GRP1_EnableClock(LL_C2_APB1_GRP1_PERIPH_SPI2) +#define __HAL_RCC_USART2_CLK_ENABLE() LL_C2_APB1_GRP1_EnableClock(LL_C2_APB1_GRP1_PERIPH_USART2) +#define __HAL_RCC_I2C1_CLK_ENABLE() LL_C2_APB1_GRP1_EnableClock(LL_C2_APB1_GRP1_PERIPH_I2C1) +#define __HAL_RCC_I2C2_CLK_ENABLE() LL_C2_APB1_GRP1_EnableClock(LL_C2_APB1_GRP1_PERIPH_I2C2) +#define __HAL_RCC_I2C3_CLK_ENABLE() LL_C2_APB1_GRP1_EnableClock(LL_C2_APB1_GRP1_PERIPH_I2C3) +#define __HAL_RCC_DAC_CLK_ENABLE() LL_C2_APB1_GRP1_EnableClock(LL_C2_APB1_GRP1_PERIPH_DAC) +#define __HAL_RCC_LPTIM1_CLK_ENABLE() LL_C2_APB1_GRP1_EnableClock(LL_C2_APB1_GRP1_PERIPH_LPTIM1) + +#define __HAL_RCC_LPTIM2_CLK_ENABLE() LL_C2_APB1_GRP2_EnableClock(LL_C2_APB1_GRP2_PERIPH_LPTIM2) +#define __HAL_RCC_LPTIM3_CLK_ENABLE() LL_C2_APB1_GRP2_EnableClock(LL_C2_APB1_GRP2_PERIPH_LPTIM3) +#define __HAL_RCC_LPUART1_CLK_ENABLE() LL_C2_APB1_GRP2_EnableClock(LL_C2_APB1_GRP2_PERIPH_LPUART1) + +#define __HAL_RCC_TIM2_CLK_DISABLE() LL_C2_APB1_GRP1_DisableClock(LL_C2_APB1_GRP1_PERIPH_TIM2) +#define __HAL_RCC_RTCAPB_CLK_DISABLE() LL_C2_APB1_GRP1_DisableClock(LL_C2_APB1_GRP1_PERIPH_RTCAPB) +#define __HAL_RCC_SPI2_CLK_DISABLE() LL_C2_APB1_GRP1_DisableClock(LL_C2_APB1_GRP1_PERIPH_SPI2) +#define __HAL_RCC_USART2_CLK_DISABLE() LL_C2_APB1_GRP1_DisableClock(LL_C2_APB1_GRP1_PERIPH_USART2) +#define __HAL_RCC_I2C1_CLK_DISABLE() LL_C2_APB1_GRP1_DisableClock(LL_C2_APB1_GRP1_PERIPH_I2C1) +#define __HAL_RCC_I2C2_CLK_DISABLE() LL_C2_APB1_GRP1_DisableClock(LL_C2_APB1_GRP1_PERIPH_I2C2) +#define __HAL_RCC_I2C3_CLK_DISABLE() LL_C2_APB1_GRP1_DisableClock(LL_C2_APB1_GRP1_PERIPH_I2C3) +#define __HAL_RCC_DAC_CLK_DISABLE() LL_C2_APB1_GRP1_DisableClock(LL_C2_APB1_GRP1_PERIPH_DAC) +#define __HAL_RCC_LPTIM1_CLK_DISABLE() LL_C2_APB1_GRP1_DisableClock(LL_C2_APB1_GRP1_PERIPH_LPTIM1) + +#define __HAL_RCC_LPTIM2_CLK_DISABLE() LL_C2_APB1_GRP2_DisableClock(LL_C2_APB1_GRP2_PERIPH_LPTIM2) +#define __HAL_RCC_LPTIM3_CLK_DISABLE() LL_C2_APB1_GRP2_DisableClock(LL_C2_APB1_GRP2_PERIPH_LPTIM3) +#define __HAL_RCC_LPUART1_CLK_DISABLE() LL_C2_APB1_GRP2_DisableClock(LL_C2_APB1_GRP2_PERIPH_LPUART1) +#else +#define __HAL_RCC_TIM2_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM2) +#define __HAL_RCC_RTCAPB_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_RTCAPB) +#define __HAL_RCC_SPI2_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_SPI2) +#define __HAL_RCC_USART2_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_USART2) +#define __HAL_RCC_I2C1_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_I2C1) +#define __HAL_RCC_I2C2_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_I2C2) +#define __HAL_RCC_I2C3_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_I2C3) +#define __HAL_RCC_DAC_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_DAC) +#define __HAL_RCC_LPTIM1_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_LPTIM1) + +#define __HAL_RCC_LPTIM2_CLK_ENABLE() LL_APB1_GRP2_EnableClock(LL_APB1_GRP2_PERIPH_LPTIM2) +#define __HAL_RCC_LPTIM3_CLK_ENABLE() LL_APB1_GRP2_EnableClock(LL_APB1_GRP2_PERIPH_LPTIM3) +#define __HAL_RCC_LPUART1_CLK_ENABLE() LL_APB1_GRP2_EnableClock(LL_APB1_GRP2_PERIPH_LPUART1) + +#define __HAL_RCC_TIM2_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_TIM2) +#define __HAL_RCC_RTCAPB_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_RTCAPB) +#define __HAL_RCC_SPI2_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_SPI2) +#define __HAL_RCC_USART2_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_USART2) +#define __HAL_RCC_I2C1_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_I2C1) +#define __HAL_RCC_I2C2_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_I2C2) +#define __HAL_RCC_I2C3_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_I2C3) +#define __HAL_RCC_DAC_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_DAC) +#define __HAL_RCC_LPTIM1_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_LPTIM1) + +#define __HAL_RCC_LPTIM2_CLK_DISABLE() LL_APB1_GRP2_DisableClock(LL_APB1_GRP2_PERIPH_LPTIM2) +#define __HAL_RCC_LPTIM3_CLK_DISABLE() LL_APB1_GRP2_DisableClock(LL_APB1_GRP2_PERIPH_LPTIM3) +#define __HAL_RCC_LPUART1_CLK_DISABLE() LL_APB1_GRP2_DisableClock(LL_APB1_GRP2_PERIPH_LPUART1) +#endif /* CORE_CM0PLUS */ + +#define __HAL_RCC_WWDG_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_WWDG) + +#define __HAL_RCC_WWDG_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_WWDG) + +/** + * @} + */ + +/** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable + * @brief Enable or disable the APB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#if defined(CORE_CM0PLUS) +#define __HAL_RCC_ADC_CLK_ENABLE() LL_C2_APB2_GRP1_EnableClock(LL_C2_APB2_GRP1_PERIPH_ADC) +#define __HAL_RCC_TIM1_CLK_ENABLE() LL_C2_APB2_GRP1_EnableClock(LL_C2_APB2_GRP1_PERIPH_TIM1) +#define __HAL_RCC_SPI1_CLK_ENABLE() LL_C2_APB2_GRP1_EnableClock(LL_C2_APB2_GRP1_PERIPH_SPI1) +#define __HAL_RCC_USART1_CLK_ENABLE() LL_C2_APB2_GRP1_EnableClock(LL_C2_APB2_GRP1_PERIPH_USART1) +#define __HAL_RCC_TIM16_CLK_ENABLE() LL_C2_APB2_GRP1_EnableClock(LL_C2_APB2_GRP1_PERIPH_TIM16) +#define __HAL_RCC_TIM17_CLK_ENABLE() LL_C2_APB2_GRP1_EnableClock(LL_C2_APB2_GRP1_PERIPH_TIM17) + +#define __HAL_RCC_ADC_CLK_DISABLE() LL_C2_APB2_GRP1_DisableClock(LL_C2_APB2_GRP1_PERIPH_ADC) +#define __HAL_RCC_TIM1_CLK_DISABLE() LL_C2_APB2_GRP1_DisableClock(LL_C2_APB2_GRP1_PERIPH_TIM1) +#define __HAL_RCC_SPI1_CLK_DISABLE() LL_C2_APB2_GRP1_DisableClock(LL_C2_APB2_GRP1_PERIPH_SPI1) +#define __HAL_RCC_USART1_CLK_DISABLE() LL_C2_APB2_GRP1_DisableClock(LL_C2_APB2_GRP1_PERIPH_USART1) +#define __HAL_RCC_TIM16_CLK_DISABLE() LL_C2_APB2_GRP1_DisableClock(LL_C2_APB2_GRP1_PERIPH_TIM16) +#define __HAL_RCC_TIM17_CLK_DISABLE() LL_C2_APB2_GRP1_DisableClock(LL_C2_APB2_GRP1_PERIPH_TIM17) +#else +#define __HAL_RCC_ADC_CLK_ENABLE() LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_ADC) +#define __HAL_RCC_TIM1_CLK_ENABLE() LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_TIM1) +#define __HAL_RCC_SPI1_CLK_ENABLE() LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_SPI1) +#define __HAL_RCC_USART1_CLK_ENABLE() LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_USART1) +#define __HAL_RCC_TIM16_CLK_ENABLE() LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_TIM16) +#define __HAL_RCC_TIM17_CLK_ENABLE() LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_TIM17) + +#define __HAL_RCC_ADC_CLK_DISABLE() LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_ADC) +#define __HAL_RCC_TIM1_CLK_DISABLE() LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_TIM1) +#define __HAL_RCC_SPI1_CLK_DISABLE() LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_SPI1) +#define __HAL_RCC_USART1_CLK_DISABLE() LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_USART1) +#define __HAL_RCC_TIM16_CLK_DISABLE() LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_TIM16) +#define __HAL_RCC_TIM17_CLK_DISABLE() LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_TIM17) +#endif /* CORE_CM0PLUS */ +/** + * @} + */ + + +/** @defgroup RCC_APB3_Clock_Enable_Disable APB3 Peripheral Clock Enable Disable + * @brief Enable or disable the APB3 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#if defined(CORE_CM0PLUS) +#define __HAL_RCC_SUBGHZSPI_CLK_ENABLE() LL_C2_APB3_GRP1_EnableClock(LL_C2_APB3_GRP1_PERIPH_SUBGHZSPI) + +#define __HAL_RCC_SUBGHZSPI_CLK_DISABLE() LL_C2_APB3_GRP1_DisableClock(LL_C2_APB3_GRP1_PERIPH_SUBGHZSPI) +#else +#define __HAL_RCC_SUBGHZSPI_CLK_ENABLE() LL_APB3_GRP1_EnableClock(LL_APB3_GRP1_PERIPH_SUBGHZSPI) + +#define __HAL_RCC_SUBGHZSPI_CLK_DISABLE() LL_APB3_GRP1_DisableClock(LL_APB3_GRP1_PERIPH_SUBGHZSPI) +#endif /* CORE_CM0PLUS */ + + +/* Aliases used by CubeMX for HAL SUBGHZ Init, MspInit and DeInit generation */ +#define __HAL_RCC_SUBGHZ_CLK_ENABLE() __HAL_RCC_SUBGHZSPI_CLK_ENABLE() +#define __HAL_RCC_SUBGHZ_CLK_DISABLE() __HAL_RCC_SUBGHZSPI_CLK_DISABLE() +/** + * @} + */ + +/** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enabled or Disabled Status + * @brief Check whether the AHB1 peripheral clock is enabled or not. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#if defined(CORE_CM0PLUS) +#define __HAL_RCC_DMA1_IS_CLK_ENABLED() LL_C2_AHB1_GRP1_IsEnabledClock(LL_C2_AHB1_GRP1_PERIPH_DMA1) +#define __HAL_RCC_DMA2_IS_CLK_ENABLED() LL_C2_AHB1_GRP1_IsEnabledClock(LL_C2_AHB1_GRP1_PERIPH_DMA2) +#define __HAL_RCC_DMAMUX1_IS_CLK_ENABLED() LL_C2_AHB1_GRP1_IsEnabledClock(LL_C2_AHB1_GRP1_PERIPH_DMAMUX1) +#define __HAL_RCC_CRC_IS_CLK_ENABLED() LL_C2_AHB1_GRP1_IsEnabledClock(LL_C2_AHB1_GRP1_PERIPH_CRC) +#else +#define __HAL_RCC_DMA1_IS_CLK_ENABLED() LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_DMA1) +#define __HAL_RCC_DMA2_IS_CLK_ENABLED() LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_DMA2) +#define __HAL_RCC_DMAMUX1_IS_CLK_ENABLED() LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_DMAMUX1) +#define __HAL_RCC_CRC_IS_CLK_ENABLED() LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_CRC) +#endif /* CORE_CM0PLUS */ +/** + * @} + */ + +/** @defgroup RCC_AHB2_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enabled or Disabled Status + * @brief Check whether the AHB2 peripheral clock is enabled or not. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#if defined(CORE_CM0PLUS) +#define __HAL_RCC_GPIOA_IS_CLK_ENABLED() LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_GPIOA) +#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_GPIOB) +#define __HAL_RCC_GPIOC_IS_CLK_ENABLED() LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_GPIOC) +#define __HAL_RCC_GPIOH_IS_CLK_ENABLED() LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_GPIOH) +#else +#define __HAL_RCC_GPIOA_IS_CLK_ENABLED() LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOA) +#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOB) +#define __HAL_RCC_GPIOC_IS_CLK_ENABLED() LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOC) +#define __HAL_RCC_GPIOH_IS_CLK_ENABLED() LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOH) +#endif /* CORE_CM0PLUS */ +/** + * @} + */ + +/** @defgroup RCC_AHB3_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enabled or Disabled Status + * @brief Check whether the AHB3 peripheral clock is enabled or not. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#if defined(CORE_CM0PLUS) +#define __HAL_RCC_PKA_IS_CLK_ENABLED() LL_C2_AHB3_GRP1_IsEnabledClock(LL_C2_AHB3_GRP1_PERIPH_PKA) +#define __HAL_RCC_AES_IS_CLK_ENABLED() LL_C2_AHB3_GRP1_IsEnabledClock(LL_C2_AHB3_GRP1_PERIPH_AES) +#define __HAL_RCC_RNG_IS_CLK_ENABLED() LL_C2_AHB3_GRP1_IsEnabledClock(LL_C2_AHB3_GRP1_PERIPH_RNG) +#define __HAL_RCC_HSEM_IS_CLK_ENABLED() LL_C2_AHB3_GRP1_IsEnabledClock(LL_C2_AHB3_GRP1_PERIPH_HSEM) +#define __HAL_RCC_IPCC_IS_CLK_ENABLED() LL_C2_AHB3_GRP1_IsEnabledClock(LL_C2_AHB3_GRP1_PERIPH_IPCC) +#define __HAL_RCC_FLASH_IS_CLK_ENABLED() LL_C2_AHB3_GRP1_IsEnabledClock(LL_C2_AHB3_GRP1_PERIPH_FLASH) +#else +#define __HAL_RCC_PKA_IS_CLK_ENABLED() LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_PKA) +#define __HAL_RCC_AES_IS_CLK_ENABLED() LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_AES) +#define __HAL_RCC_RNG_IS_CLK_ENABLED() LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_RNG) +#define __HAL_RCC_HSEM_IS_CLK_ENABLED() LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_HSEM) +#define __HAL_RCC_IPCC_IS_CLK_ENABLED() LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_IPCC) +#define __HAL_RCC_FLASH_IS_CLK_ENABLED() LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_FLASH) +#endif /* CORE_CM0PLUS */ +/** + * @} + */ + +/** @defgroup RCC_APB1_Clock_Enable_Disable_Status APB1 Peripheral Clock Enabled or Disabled Status + * @brief Check whether the APB1 peripheral clock is enabled or not. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#if defined(CORE_CM0PLUS) +#define __HAL_RCC_TIM2_IS_CLK_ENABLED() LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_TIM2) +#define __HAL_RCC_RTCAPB_IS_CLK_ENABLED() LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_RTCAPB) +#define __HAL_RCC_SPI2_IS_CLK_ENABLED() LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_SPI2) +#define __HAL_RCC_USART2_IS_CLK_ENABLED() LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_USART2) +#define __HAL_RCC_I2C1_IS_CLK_ENABLED() LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_I2C1) +#define __HAL_RCC_I2C2_IS_CLK_ENABLED() LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_I2C2) +#define __HAL_RCC_I2C3_IS_CLK_ENABLED() LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_I2C3) +#define __HAL_RCC_DAC_IS_CLK_ENABLED() LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_DAC) +#define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_LPTIM1) + +#define __HAL_RCC_LPTIM2_IS_CLK_ENABLED() LL_C2_APB1_GRP2_IsEnabledClock(LL_C2_APB1_GRP2_PERIPH_LPTIM2) +#define __HAL_RCC_LPTIM3_IS_CLK_ENABLED() LL_C2_APB1_GRP2_IsEnabledClock(LL_C2_APB1_GRP2_PERIPH_LPTIM3) +#define __HAL_RCC_LPUART1_IS_CLK_ENABLED() LL_C2_APB1_GRP2_IsEnabledClock(LL_C2_APB1_GRP2_PERIPH_LPUART1) +#else +#define __HAL_RCC_TIM2_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_TIM2) +#define __HAL_RCC_RTCAPB_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_RTCAPB) +#define __HAL_RCC_SPI2_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_SPI2) +#define __HAL_RCC_USART2_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_USART2) +#define __HAL_RCC_I2C1_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_I2C1) +#define __HAL_RCC_I2C2_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_I2C2) +#define __HAL_RCC_I2C3_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_I2C3) +#define __HAL_RCC_DAC_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_DAC) +#define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_LPTIM1) + +#define __HAL_RCC_LPTIM2_IS_CLK_ENABLED() LL_APB1_GRP2_IsEnabledClock(LL_APB1_GRP2_PERIPH_LPTIM2) +#define __HAL_RCC_LPTIM3_IS_CLK_ENABLED() LL_APB1_GRP2_IsEnabledClock(LL_APB1_GRP2_PERIPH_LPTIM3) +#define __HAL_RCC_LPUART1_IS_CLK_ENABLED() LL_APB1_GRP2_IsEnabledClock(LL_APB1_GRP2_PERIPH_LPUART1) +#endif /* CORE_CM0PLUS */ + +#define __HAL_RCC_WWDG_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_WWDG) +/** + * @} + */ + +/** @defgroup RCC_APB2_Clock_Enable_Disable_Status APB2 Peripheral Clock Enabled or Disabled Status + * @brief Check whether the APB2 peripheral clock is enabled or not. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#if defined(CORE_CM0PLUS) +#define __HAL_RCC_ADC_IS_CLK_ENABLED() LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_ADC) +#define __HAL_RCC_TIM1_IS_CLK_ENABLED() LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_TIM1) +#define __HAL_RCC_SPI1_IS_CLK_ENABLED() LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_SPI1) +#define __HAL_RCC_USART1_IS_CLK_ENABLED() LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_USART1) +#define __HAL_RCC_TIM16_IS_CLK_ENABLED() LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_TIM16) +#define __HAL_RCC_TIM17_IS_CLK_ENABLED() LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_TIM17) +#else +#define __HAL_RCC_ADC_IS_CLK_ENABLED() LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_ADC) +#define __HAL_RCC_TIM1_IS_CLK_ENABLED() LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_TIM1) +#define __HAL_RCC_SPI1_IS_CLK_ENABLED() LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_SPI1) +#define __HAL_RCC_USART1_IS_CLK_ENABLED() LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_USART1) +#define __HAL_RCC_TIM16_IS_CLK_ENABLED() LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_TIM16) +#define __HAL_RCC_TIM17_IS_CLK_ENABLED() LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_TIM17) +#endif /* CORE_CM0PLUS */ +/** + * @} + */ + +/** @defgroup RCC_APB3_Clock_Enable_Disable_Status APB3 Peripheral Clock Enabled or Disabled Status + * @brief Check whether the APB3 peripheral clock is enabled or not. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#if defined(CORE_CM0PLUS) +#define __HAL_RCC_SUBGHZSPI_IS_CLK_ENABLED() LL_C2_APB3_GRP1_IsEnabledClock(LL_C2_APB3_GRP1_PERIPH_SUBGHZSPI) +#else +#define __HAL_RCC_SUBGHZSPI_IS_CLK_ENABLED() LL_APB3_GRP1_IsEnabledClock(LL_APB3_GRP1_PERIPH_SUBGHZSPI) +#endif /* CORE_CM0PLUS */ + +/* Aliases used by CubeMX for HAL SUBGHZ Init, MspInit and DeInit generation */ +#define __HAL_RCC_SUBGHZ_IS_CLK_ENABLED() __HAL_RCC_SUBGHZSPI_IS_CLK_ENABLED() +/** + * @} + */ + +/** @defgroup RCC_AHB1_Force_Release_Reset AHB1 Peripheral Force Release Reset + * @brief Force or release AHB1 peripheral reset. + * @{ + */ +#define __HAL_RCC_AHB1_FORCE_RESET() LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_ALL) +#define __HAL_RCC_DMA1_FORCE_RESET() LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA1) +#define __HAL_RCC_DMA2_FORCE_RESET() LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA2) +#define __HAL_RCC_DMAMUX1_FORCE_RESET() LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMAMUX1) +#define __HAL_RCC_CRC_FORCE_RESET() LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_CRC) + +#define __HAL_RCC_AHB1_RELEASE_RESET() LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_ALL) +#define __HAL_RCC_DMA1_RELEASE_RESET() LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA1) +#define __HAL_RCC_DMA2_RELEASE_RESET() LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA2) +#define __HAL_RCC_DMAMUX1_RELEASE_RESET() LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMAMUX1) +#define __HAL_RCC_CRC_RELEASE_RESET() LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_CRC) +/** + * @} + */ + +/** @defgroup RCC_AHB2_Force_Release_Reset AHB2 Peripheral Force Release Reset + * @brief Force or release AHB2 peripheral reset. + * @{ + */ +#define __HAL_RCC_AHB2_FORCE_RESET() LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_ALL) +#define __HAL_RCC_GPIOA_FORCE_RESET() LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOA) +#define __HAL_RCC_GPIOB_FORCE_RESET() LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOB) +#define __HAL_RCC_GPIOC_FORCE_RESET() LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOC) +#define __HAL_RCC_GPIOH_FORCE_RESET() LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOH) + +#define __HAL_RCC_AHB2_RELEASE_RESET() LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_ALL) +#define __HAL_RCC_GPIOA_RELEASE_RESET() LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOA) +#define __HAL_RCC_GPIOB_RELEASE_RESET() LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOB) +#define __HAL_RCC_GPIOC_RELEASE_RESET() LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOC) +#define __HAL_RCC_GPIOH_RELEASE_RESET() LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOH) +/** + * @} + */ + +/** @defgroup RCC_AHB3_Force_Release_Reset AHB3 Peripheral Force Release Reset + * @brief Force or release AHB3 peripheral reset. + * @{ + */ +#if defined (DUAL_CORE) +#define __HAL_RCC_IPCC_FORCE_RESET() LL_AHB3_GRP1_ForceReset(LL_AHB3_GRP1_PERIPH_IPCC) +#define __HAL_RCC_IPCC_RELEASE_RESET() LL_AHB3_GRP1_ReleaseReset(LL_AHB3_GRP1_PERIPH_IPCC) +#endif /* DUAL_CORE */ + +#define __HAL_RCC_AHB3_FORCE_RESET() LL_AHB3_GRP1_ForceReset(LL_AHB3_GRP1_PERIPH_ALL) +#define __HAL_RCC_PKA_FORCE_RESET() LL_AHB3_GRP1_ForceReset(LL_AHB3_GRP1_PERIPH_PKA) +#define __HAL_RCC_AES_FORCE_RESET() LL_AHB3_GRP1_ForceReset(LL_AHB3_GRP1_PERIPH_AES) +#define __HAL_RCC_RNG_FORCE_RESET() LL_AHB3_GRP1_ForceReset(LL_AHB3_GRP1_PERIPH_RNG) +#define __HAL_RCC_HSEM_FORCE_RESET() LL_AHB3_GRP1_ForceReset(LL_AHB3_GRP1_PERIPH_HSEM) +#define __HAL_RCC_FLASH_FORCE_RESET() LL_AHB3_GRP1_ForceReset(LL_AHB3_GRP1_PERIPH_FLASH) + +#define __HAL_RCC_AHB3_RELEASE_RESET() LL_AHB3_GRP1_ReleaseReset(LL_AHB3_GRP1_PERIPH_ALL) +#define __HAL_RCC_PKA_RELEASE_RESET() LL_AHB3_GRP1_ReleaseReset(LL_AHB3_GRP1_PERIPH_PKA) +#define __HAL_RCC_AES_RELEASE_RESET() LL_AHB3_GRP1_ReleaseReset(LL_AHB3_GRP1_PERIPH_AES) +#define __HAL_RCC_RNG_RELEASE_RESET() LL_AHB3_GRP1_ReleaseReset(LL_AHB3_GRP1_PERIPH_RNG) +#define __HAL_RCC_HSEM_RELEASE_RESET() LL_AHB3_GRP1_ReleaseReset(LL_AHB3_GRP1_PERIPH_HSEM) +#define __HAL_RCC_FLASH_RELEASE_RESET() LL_AHB3_GRP1_ReleaseReset(LL_AHB3_GRP1_PERIPH_FLASH) +/** + * @} + */ + +/** @defgroup RCC_APB1_Force_Release_Reset APB1 Peripheral Force Release Reset + * @brief Force or release APB1 peripheral reset. + * @{ + */ +#define __HAL_RCC_APB1L_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_ALL) +#define __HAL_RCC_TIM2_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2) +#define __HAL_RCC_SPI2_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI2) +#define __HAL_RCC_USART2_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART2) +#define __HAL_RCC_I2C1_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C1) +#define __HAL_RCC_I2C2_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C2) +#define __HAL_RCC_I2C3_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C3) +#define __HAL_RCC_DAC_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_DAC) +#define __HAL_RCC_LPTIM1_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_LPTIM1) + +#define __HAL_RCC_APB1H_FORCE_RESET() LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_ALL) +#define __HAL_RCC_LPUART1_FORCE_RESET() LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_LPUART1) +#define __HAL_RCC_LPTIM2_FORCE_RESET() LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_LPTIM2) +#define __HAL_RCC_LPTIM3_FORCE_RESET() LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_LPTIM3) + +#define __HAL_RCC_APB1_FORCE_RESET() do { \ + __HAL_RCC_APB1L_FORCE_RESET();\ + __HAL_RCC_APB1H_FORCE_RESET();\ + } while(0U) + +#define __HAL_RCC_APB1L_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_ALL) +#define __HAL_RCC_TIM2_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2) +#define __HAL_RCC_USART2_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART2) +#define __HAL_RCC_SPI2_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI2) +#define __HAL_RCC_I2C1_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C1) +#define __HAL_RCC_I2C2_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C2) +#define __HAL_RCC_I2C3_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C3) +#define __HAL_RCC_DAC_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_DAC) +#define __HAL_RCC_LPTIM1_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_LPTIM1) + +#define __HAL_RCC_APB1H_RELEASE_RESET() LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_ALL) +#define __HAL_RCC_LPUART1_RELEASE_RESET() LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_LPUART1) +#define __HAL_RCC_LPTIM2_RELEASE_RESET() LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_LPTIM2) +#define __HAL_RCC_LPTIM3_RELEASE_RESET() LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_LPTIM3) + +#define __HAL_RCC_APB1_RELEASE_RESET() do { \ + __HAL_RCC_APB1L_RELEASE_RESET();\ + __HAL_RCC_APB1H_RELEASE_RESET();\ + } while(0U) +/** + * @} + */ + +/** @defgroup RCC_APB2_Force_Release_Reset APB2 Peripheral Force Release Reset + * @brief Force or release APB2 peripheral reset. + * @{ + */ +#define __HAL_RCC_APB2_FORCE_RESET() LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_ALL) +#define __HAL_RCC_ADC_FORCE_RESET() LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_ADC) +#define __HAL_RCC_TIM1_FORCE_RESET() LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM1) +#define __HAL_RCC_SPI1_FORCE_RESET() LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI1) +#define __HAL_RCC_USART1_FORCE_RESET() LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_USART1) +#define __HAL_RCC_TIM16_FORCE_RESET() LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM16) +#define __HAL_RCC_TIM17_FORCE_RESET() LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM17) + +#define __HAL_RCC_APB2_RELEASE_RESET() LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_ALL) +#define __HAL_RCC_ADC_RELEASE_RESET() LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_ADC) +#define __HAL_RCC_TIM1_RELEASE_RESET() LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM1) +#define __HAL_RCC_SPI1_RELEASE_RESET() LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI1) +#define __HAL_RCC_USART1_RELEASE_RESET() LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_USART1) +#define __HAL_RCC_TIM16_RELEASE_RESET() LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM16) +#define __HAL_RCC_TIM17_RELEASE_RESET() LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM17) +/** + * @} + */ + +/** @defgroup RCC_APB3_Force_Release_Reset APB3 Peripheral Force Release Reset + * @brief Force or release APB3 peripheral reset. + * @{ + */ +#define __HAL_RCC_APB3_FORCE_RESET() LL_APB3_GRP1_ForceReset(LL_APB3_GRP1_PERIPH_ALL) +#define __HAL_RCC_SUBGHZSPI_FORCE_RESET() LL_APB3_GRP1_ForceReset(LL_APB3_GRP1_PERIPH_SUBGHZSPI) + +#define __HAL_RCC_APB3_RELEASE_RESET() LL_APB3_GRP1_ReleaseReset(LL_APB3_GRP1_PERIPH_ALL) +#define __HAL_RCC_SUBGHZSPI_RELEASE_RESET() LL_APB3_GRP1_ReleaseReset(LL_APB3_GRP1_PERIPH_SUBGHZSPI) + +/* Aliases used by CubeMX for HAL SUBGHZ Init, MspInit and DeInit generation */ +#define __HAL_RCC_SUBGHZ_FORCE_RESET() __HAL_RCC_SUBGHZSPI_FORCE_RESET() +#define __HAL_RCC_SUBGHZ_RELEASE_RESET() __HAL_RCC_SUBGHZSPI_RELEASE_RESET() +/** + * @} + */ + +/** @defgroup RCC_SUBGHZ_Force_Release_Reset SUBGHZ Radio Force Release Reset + * @brief Force or release SUBGHZ Radio reset. + * @{ + */ +#define __HAL_RCC_SUBGHZ_RADIO_FORCE_RESET() SET_BIT(RCC->CSR, RCC_CSR_RFRST) + +#define __HAL_RCC_SUBGHZ_RADIO_RELEASE_RESET() CLEAR_BIT(RCC->CSR, RCC_CSR_RFRST) +/** + * @} + */ + +/** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable AHB1 Peripheral Clock Sleep Enable Disable + * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#if defined(CORE_CM0PLUS) +#define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() LL_C2_AHB1_GRP1_EnableClockSleep(LL_C2_AHB1_GRP1_PERIPH_DMA1) +#define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() LL_C2_AHB1_GRP1_EnableClockSleep(LL_C2_AHB1_GRP1_PERIPH_DMA2) +#define __HAL_RCC_DMAMUX1_CLK_SLEEP_ENABLE() LL_C2_AHB1_GRP1_EnableClockSleep(LL_C2_AHB1_GRP1_PERIPH_DMAMUX1) +#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() LL_C2_AHB1_GRP1_EnableClockSleep(LL_C2_AHB1_GRP1_PERIPH_CRC) + +#define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() LL_C2_AHB1_GRP1_DisableClockSleep(LL_C2_AHB1_GRP1_PERIPH_DMA1) +#define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() LL_C2_AHB1_GRP1_DisableClockSleep(LL_C2_AHB1_GRP1_PERIPH_DMA2) +#define __HAL_RCC_DMAMUX1_CLK_SLEEP_DISABLE() LL_C2_AHB1_GRP1_DisableClockSleep(LL_C2_AHB1_GRP1_PERIPH_DMAMUX1) +#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() LL_C2_AHB1_GRP1_DisableClockSleep(LL_C2_AHB1_GRP1_PERIPH_CRC) +#else +#define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() LL_AHB1_GRP1_EnableClockSleep(LL_AHB1_GRP1_PERIPH_DMA1) +#define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() LL_AHB1_GRP1_EnableClockSleep(LL_AHB1_GRP1_PERIPH_DMA2) +#define __HAL_RCC_DMAMUX1_CLK_SLEEP_ENABLE() LL_AHB1_GRP1_EnableClockSleep(LL_AHB1_GRP1_PERIPH_DMAMUX1) +#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() LL_AHB1_GRP1_EnableClockSleep(LL_AHB1_GRP1_PERIPH_CRC) + +#define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() LL_AHB1_GRP1_DisableClockSleep(LL_AHB1_GRP1_PERIPH_DMA1) +#define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() LL_AHB1_GRP1_DisableClockSleep(LL_AHB1_GRP1_PERIPH_DMA2) +#define __HAL_RCC_DMAMUX1_CLK_SLEEP_DISABLE() LL_AHB1_GRP1_DisableClockSleep(LL_AHB1_GRP1_PERIPH_DMAMUX1) +#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() LL_AHB1_GRP1_DisableClockSleep(LL_AHB1_GRP1_PERIPH_CRC) +#endif /* CORE_CM0PLUS */ +/** + * @} + */ + +/** @defgroup RCC_AHB2_Clock_Sleep_Enable_Disable AHB2 Peripheral Clock Sleep Enable Disable + * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#if defined(CORE_CM0PLUS) +#define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() LL_C2_AHB2_GRP1_EnableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOA) +#define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() LL_C2_AHB2_GRP1_EnableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOB) +#define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() LL_C2_AHB2_GRP1_EnableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOC) +#define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() LL_C2_AHB2_GRP1_EnableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOH) + +#define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() LL_C2_AHB2_GRP1_DisableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOA) +#define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() LL_C2_AHB2_GRP1_DisableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOB) +#define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() LL_C2_AHB2_GRP1_DisableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOC) +#define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() LL_C2_AHB2_GRP1_DisableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOH) +#else +#define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() LL_AHB2_GRP1_EnableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOA) +#define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() LL_AHB2_GRP1_EnableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOB) +#define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() LL_AHB2_GRP1_EnableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOC) +#define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() LL_AHB2_GRP1_EnableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOH) + +#define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() LL_AHB2_GRP1_DisableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOA) +#define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() LL_AHB2_GRP1_DisableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOB) +#define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() LL_AHB2_GRP1_DisableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOC) +#define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() LL_AHB2_GRP1_DisableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOH) +#endif /* CORE_CM0PLUS */ +/** + * @} + */ + +/** @defgroup RCC_AHB3_Clock_Sleep_Enable_Disable AHB3 Peripheral Clock Sleep Enable Disable + * @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#if defined(CORE_CM0PLUS) +#define __HAL_RCC_PKA_CLK_SLEEP_ENABLE() LL_C2_AHB3_GRP1_EnableClockSleep(LL_C2_AHB3_GRP1_PERIPH_PKA) +#define __HAL_RCC_AES_CLK_SLEEP_ENABLE() LL_C2_AHB3_GRP1_EnableClockSleep(LL_C2_AHB3_GRP1_PERIPH_AES) +#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() LL_C2_AHB3_GRP1_EnableClockSleep(LL_C2_AHB3_GRP1_PERIPH_RNG) +#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() LL_C2_AHB3_GRP1_EnableClockSleep(LL_C2_AHB3_GRP1_PERIPH_SRAM1) +#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() LL_C2_AHB3_GRP1_EnableClockSleep(LL_C2_AHB3_GRP1_PERIPH_SRAM2) +#define __HAL_RCC_FLASH_CLK_SLEEP_ENABLE() LL_C2_AHB3_GRP1_EnableClockSleep(LL_C2_AHB3_GRP1_PERIPH_FLASH) + +#define __HAL_RCC_PKA_CLK_SLEEP_DISABLE() LL_C2_AHB3_GRP1_DisableClockSleep(LL_C2_AHB3_GRP1_PERIPH_PKA) +#define __HAL_RCC_AES_CLK_SLEEP_DISABLE() LL_C2_AHB3_GRP1_DisableClockSleep(LL_C2_AHB3_GRP1_PERIPH_AES) +#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() LL_C2_AHB3_GRP1_DisableClockSleep(LL_C2_AHB3_GRP1_PERIPH_RNG) +#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() LL_C2_AHB3_GRP1_DisableClockSleep(LL_C2_AHB3_GRP1_PERIPH_SRAM1) +#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() LL_C2_AHB3_GRP1_DisableClockSleep(LL_C2_AHB3_GRP1_PERIPH_SRAM2) +#define __HAL_RCC_FLASH_CLK_SLEEP_DISABLE() LL_C2_AHB3_GRP1_DisableClockSleep(LL_C2_AHB3_GRP1_PERIPH_FLASH) +#else +#define __HAL_RCC_PKA_CLK_SLEEP_ENABLE() LL_AHB3_GRP1_EnableClockSleep(LL_AHB3_GRP1_PERIPH_PKA) +#define __HAL_RCC_AES_CLK_SLEEP_ENABLE() LL_AHB3_GRP1_EnableClockSleep(LL_AHB3_GRP1_PERIPH_AES) +#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() LL_AHB3_GRP1_EnableClockSleep(LL_AHB3_GRP1_PERIPH_RNG) +#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() LL_AHB3_GRP1_EnableClockSleep(LL_AHB3_GRP1_PERIPH_SRAM1) +#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() LL_AHB3_GRP1_EnableClockSleep(LL_AHB3_GRP1_PERIPH_SRAM2) +#define __HAL_RCC_FLASH_CLK_SLEEP_ENABLE() LL_AHB3_GRP1_EnableClockSleep(LL_AHB3_GRP1_PERIPH_FLASH) + +#define __HAL_RCC_PKA_CLK_SLEEP_DISABLE() LL_AHB3_GRP1_DisableClockSleep(LL_AHB3_GRP1_PERIPH_PKA) +#define __HAL_RCC_AES_CLK_SLEEP_DISABLE() LL_AHB3_GRP1_DisableClockSleep(LL_AHB3_GRP1_PERIPH_AES) +#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() LL_AHB3_GRP1_DisableClockSleep(LL_AHB3_GRP1_PERIPH_RNG) +#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() LL_AHB3_GRP1_DisableClockSleep(LL_AHB3_GRP1_PERIPH_SRAM1) +#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() LL_AHB3_GRP1_DisableClockSleep(LL_AHB3_GRP1_PERIPH_SRAM2) +#define __HAL_RCC_FLASH_CLK_SLEEP_DISABLE() LL_AHB3_GRP1_DisableClockSleep(LL_AHB3_GRP1_PERIPH_FLASH) +#endif /* CORE_CM0PLUS */ +/** + * @} + */ + +/** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable APB1 Peripheral Clock Sleep Enable Disable + * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#if defined(CORE_CM0PLUS) +#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() LL_C2_APB1_GRP1_EnableClockSleep(LL_C2_APB1_GRP1_PERIPH_TIM2) +#define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() LL_C2_APB1_GRP1_EnableClockSleep(LL_C2_APB1_GRP1_PERIPH_RTCAPB) +#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() LL_C2_APB1_GRP1_EnableClockSleep(LL_C2_APB1_GRP1_PERIPH_SPI2) +#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() LL_C2_APB1_GRP1_EnableClockSleep(LL_C2_APB1_GRP1_PERIPH_USART2) +#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() LL_C2_APB1_GRP1_EnableClockSleep(LL_C2_APB1_GRP1_PERIPH_I2C1) +#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() LL_C2_APB1_GRP1_EnableClockSleep(LL_C2_APB1_GRP1_PERIPH_I2C2) +#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() LL_C2_APB1_GRP1_EnableClockSleep(LL_C2_APB1_GRP1_PERIPH_I2C3) +#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() LL_C2_APB1_GRP1_EnableClockSleep(LL_C2_APB1_GRP1_PERIPH_DAC) +#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() LL_C2_APB1_GRP1_EnableClockSleep(LL_C2_APB1_GRP1_PERIPH_LPTIM1) + +#define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() LL_C2_APB1_GRP2_EnableClockSleep(LL_C2_APB1_GRP2_PERIPH_LPUART1) +#define __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE() LL_C2_APB1_GRP2_EnableClockSleep(LL_C2_APB1_GRP2_PERIPH_LPTIM2) +#define __HAL_RCC_LPTIM3_CLK_SLEEP_ENABLE() LL_C2_APB1_GRP2_EnableClockSleep(LL_C2_APB1_GRP2_PERIPH_LPTIM3) + +#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() LL_C2_APB1_GRP1_DisableClockSleep(LL_C2_APB1_GRP1_PERIPH_TIM2) +#define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() LL_C2_APB1_GRP1_DisableClockSleep(LL_C2_APB1_GRP1_PERIPH_RTCAPB) +#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() LL_C2_APB1_GRP1_DisableClockSleep(LL_C2_APB1_GRP1_PERIPH_USART2) +#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() LL_C2_APB1_GRP1_DisableClockSleep(LL_C2_APB1_GRP1_PERIPH_SPI2) +#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() LL_C2_APB1_GRP1_DisableClockSleep(LL_C2_APB1_GRP1_PERIPH_I2C1) +#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() LL_C2_APB1_GRP1_DisableClockSleep(LL_C2_APB1_GRP1_PERIPH_I2C2) +#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() LL_C2_APB1_GRP1_DisableClockSleep(LL_C2_APB1_GRP1_PERIPH_I2C3) +#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() LL_C2_APB1_GRP1_DisableClockSleep(LL_C2_APB1_GRP1_PERIPH_DAC) +#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() LL_C2_APB1_GRP1_DisableClockSleep(LL_C2_APB1_GRP1_PERIPH_LPTIM1) + +#define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() LL_C2_APB1_GRP2_DisableClockSleep(LL_C2_APB1_GRP2_PERIPH_LPUART1) +#define __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE() LL_C2_APB1_GRP2_DisableClockSleep(LL_C2_APB1_GRP2_PERIPH_LPTIM2) +#define __HAL_RCC_LPTIM3_CLK_SLEEP_DISABLE() LL_C2_APB1_GRP2_DisableClockSleep(LL_C2_APB1_GRP2_PERIPH_LPTIM3) +#else +#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockSleep(LL_APB1_GRP1_PERIPH_TIM2) +#define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockSleep(LL_APB1_GRP1_PERIPH_RTCAPB) +#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockSleep(LL_APB1_GRP1_PERIPH_SPI2) +#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockSleep(LL_APB1_GRP1_PERIPH_USART2) +#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockSleep(LL_APB1_GRP1_PERIPH_I2C1) +#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockSleep(LL_APB1_GRP1_PERIPH_I2C2) +#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockSleep(LL_APB1_GRP1_PERIPH_I2C3) +#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockSleep(LL_APB1_GRP1_PERIPH_DAC) +#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockSleep(LL_APB1_GRP1_PERIPH_LPTIM1) + +#define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() LL_APB1_GRP2_EnableClockSleep(LL_APB1_GRP2_PERIPH_LPUART1) +#define __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE() LL_APB1_GRP2_EnableClockSleep(LL_APB1_GRP2_PERIPH_LPTIM2) +#define __HAL_RCC_LPTIM3_CLK_SLEEP_ENABLE() LL_APB1_GRP2_EnableClockSleep(LL_APB1_GRP2_PERIPH_LPTIM3) + +#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockSleep(LL_APB1_GRP1_PERIPH_TIM2) +#define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockSleep(LL_APB1_GRP1_PERIPH_RTCAPB) +#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockSleep(LL_APB1_GRP1_PERIPH_USART2) +#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockSleep(LL_APB1_GRP1_PERIPH_SPI2) +#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockSleep(LL_APB1_GRP1_PERIPH_I2C1) +#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockSleep(LL_APB1_GRP1_PERIPH_I2C2) +#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockSleep(LL_APB1_GRP1_PERIPH_I2C3) +#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockSleep(LL_APB1_GRP1_PERIPH_DAC) +#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockSleep(LL_APB1_GRP1_PERIPH_LPTIM1) + +#define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() LL_APB1_GRP2_DisableClockSleep(LL_APB1_GRP2_PERIPH_LPUART1) +#define __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE() LL_APB1_GRP2_DisableClockSleep(LL_APB1_GRP2_PERIPH_LPTIM2) +#define __HAL_RCC_LPTIM3_CLK_SLEEP_DISABLE() LL_APB1_GRP2_DisableClockSleep(LL_APB1_GRP2_PERIPH_LPTIM3) +#endif /* CORE_CM0PLUS */ + +#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockSleep(LL_APB1_GRP1_PERIPH_WWDG) + +#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockSleep(LL_APB1_GRP1_PERIPH_WWDG) +/** + * @} + */ + +/** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable APB2 Peripheral Clock Sleep Enable Disable + * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#if defined(CORE_CM0PLUS) +#define __HAL_RCC_ADC_CLK_SLEEP_ENABLE() LL_C2_APB2_GRP1_EnableClockSleep(LL_C2_APB2_GRP1_PERIPH_ADC) +#define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() LL_C2_APB2_GRP1_EnableClockSleep(LL_C2_APB2_GRP1_PERIPH_TIM1) +#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() LL_C2_APB2_GRP1_EnableClockSleep(LL_C2_APB2_GRP1_PERIPH_SPI1) +#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() LL_C2_APB2_GRP1_EnableClockSleep(LL_C2_APB2_GRP1_PERIPH_USART1) +#define __HAL_RCC_TIM16_CLK_SLEEP_ENABLE() LL_C2_APB2_GRP1_EnableClockSleep(LL_C2_APB2_GRP1_PERIPH_TIM16) +#define __HAL_RCC_TIM17_CLK_SLEEP_ENABLE() LL_C2_APB2_GRP1_EnableClockSleep(LL_C2_APB2_GRP1_PERIPH_TIM17) + +#define __HAL_RCC_ADC_CLK_SLEEP_DISABLE() LL_C2_APB2_GRP1_DisableClockSleep(LL_C2_APB2_GRP1_PERIPH_ADC) +#define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() LL_C2_APB2_GRP1_DisableClockSleep(LL_C2_APB2_GRP1_PERIPH_TIM1) +#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() LL_C2_APB2_GRP1_DisableClockSleep(LL_C2_APB2_GRP1_PERIPH_SPI1) +#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() LL_C2_APB2_GRP1_DisableClockSleep(LL_C2_APB2_GRP1_PERIPH_USART1) +#define __HAL_RCC_TIM16_CLK_SLEEP_DISABLE() LL_C2_APB2_GRP1_DisableClockSleep(LL_C2_APB2_GRP1_PERIPH_TIM16) +#define __HAL_RCC_TIM17_CLK_SLEEP_DISABLE() LL_C2_APB2_GRP1_DisableClockSleep(LL_C2_APB2_GRP1_PERIPH_TIM17) +#else +#define __HAL_RCC_ADC_CLK_SLEEP_ENABLE() LL_APB2_GRP1_EnableClockSleep(LL_APB2_GRP1_PERIPH_ADC) +#define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() LL_APB2_GRP1_EnableClockSleep(LL_APB2_GRP1_PERIPH_TIM1) +#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() LL_APB2_GRP1_EnableClockSleep(LL_APB2_GRP1_PERIPH_SPI1) +#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() LL_APB2_GRP1_EnableClockSleep(LL_APB2_GRP1_PERIPH_USART1) +#define __HAL_RCC_TIM16_CLK_SLEEP_ENABLE() LL_APB2_GRP1_EnableClockSleep(LL_APB2_GRP1_PERIPH_TIM16) +#define __HAL_RCC_TIM17_CLK_SLEEP_ENABLE() LL_APB2_GRP1_EnableClockSleep(LL_APB2_GRP1_PERIPH_TIM17) + +#define __HAL_RCC_ADC_CLK_SLEEP_DISABLE() LL_APB2_GRP1_DisableClockSleep(LL_APB2_GRP1_PERIPH_ADC) +#define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() LL_APB2_GRP1_DisableClockSleep(LL_APB2_GRP1_PERIPH_TIM1) +#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() LL_APB2_GRP1_DisableClockSleep(LL_APB2_GRP1_PERIPH_SPI1) +#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() LL_APB2_GRP1_DisableClockSleep(LL_APB2_GRP1_PERIPH_USART1) +#define __HAL_RCC_TIM16_CLK_SLEEP_DISABLE() LL_APB2_GRP1_DisableClockSleep(LL_APB2_GRP1_PERIPH_TIM16) +#define __HAL_RCC_TIM17_CLK_SLEEP_DISABLE() LL_APB2_GRP1_DisableClockSleep(LL_APB2_GRP1_PERIPH_TIM17) +#endif /* CORE_CM0PLUS */ +/** + * @} + */ + +/** @defgroup RCC_APB3_Clock_Sleep_Enable_Disable APB3 Peripheral Clock Sleep Enable Disable + * @brief Enable or disable the APB3 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#if defined(CORE_CM0PLUS) +#define __HAL_RCC_SUBGHZSPI_CLK_SLEEP_ENABLE() LL_C2_APB3_GRP1_EnableClockSleep(LL_C2_APB3_GRP1_PERIPH_SUBGHZSPI) + +#define __HAL_RCC_SUBGHZSPI_CLK_SLEEP_DISABLE() LL_C2_APB3_GRP1_DisableClockSleep(LL_C2_APB3_GRP1_PERIPH_SUBGHZSPI) +#else +#define __HAL_RCC_SUBGHZSPI_CLK_SLEEP_ENABLE() LL_APB3_GRP1_EnableClockSleep(LL_APB3_GRP1_PERIPH_SUBGHZSPI) + +#define __HAL_RCC_SUBGHZSPI_CLK_SLEEP_DISABLE() LL_APB3_GRP1_DisableClockSleep(LL_APB3_GRP1_PERIPH_SUBGHZSPI) +#endif /* CORE_CM0PLUS */ + +/* Aliases used by CubeMX for HAL SUBGHZ Init, MspInit and DeInit generation */ +#define __HAL_RCC_SUBGHZ_CLK_SLEEP_ENABLE() __HAL_RCC_SUBGHZSPI_CLK_SLEEP_ENABLE() +#define __HAL_RCC_SUBGHZ_CLK_SLEEP_DISABLE() __HAL_RCC_SUBGHZSPI_CLK_SLEEP_DISABLE() +/** + * @} + */ + +/** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable_Status AHB1 Peripheral Clock Sleep Enabled or Disabled Status + * @brief Check whether the AHB1 peripheral clock during Low Power (Sleep) mode is enabled or not. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#if defined(CORE_CM0PLUS) +#define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() LL_C2_AHB1_GRP1_IsEnabledClockSleep(LL_AHB1_GRP1_PERIPH_DMA1) +#define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED() LL_C2_AHB1_GRP1_IsEnabledClockSleep(LL_AHB1_GRP1_PERIPH_DMA2) +#define __HAL_RCC_DMAMUX1_IS_CLK_SLEEP_ENABLED() LL_C2_AHB1_GRP1_IsEnabledClockSleep(LL_AHB1_GRP1_PERIPH_DMAMUX1) +#define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() LL_C2_AHB1_GRP1_IsEnabledClockSleep(LL_AHB1_GRP1_PERIPH_CRC) +#else +#define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() LL_AHB1_GRP1_IsEnabledClockSleep(LL_AHB1_GRP1_PERIPH_DMA1) +#define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED() LL_AHB1_GRP1_IsEnabledClockSleep(LL_AHB1_GRP1_PERIPH_DMA2) +#define __HAL_RCC_DMAMUX1_IS_CLK_SLEEP_ENABLED() LL_AHB1_GRP1_IsEnabledClockSleep(LL_AHB1_GRP1_PERIPH_DMAMUX1) +#define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() LL_AHB1_GRP1_IsEnabledClockSleep(LL_AHB1_GRP1_PERIPH_CRC) +#endif /* CORE_CM0PLUS */ +/** + * @} + */ + +/** @defgroup RCC_AHB2_Clock_Sleep_Enable_Disable_Status AHB2 Peripheral Clock Sleep Enabled or Disabled Status + * @brief Check whether the AHB2 peripheral clock during Low Power (Sleep) mode is enabled or not. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#if defined(CORE_CM0PLUS) +#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() LL_C2_AHB2_GRP1_IsEnabledClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOA) +#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() LL_C2_AHB2_GRP1_IsEnabledClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOB) +#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() LL_C2_AHB2_GRP1_IsEnabledClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOC) +#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED() LL_C2_AHB2_GRP1_IsEnabledClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOH) +#else +#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() LL_AHB2_GRP1_IsEnabledClockSleep(LL_AHB2_GRP1_PERIPH_GPIOA) +#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() LL_AHB2_GRP1_IsEnabledClockSleep(LL_AHB2_GRP1_PERIPH_GPIOB) +#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() LL_AHB2_GRP1_IsEnabledClockSleep(LL_AHB2_GRP1_PERIPH_GPIOC) +#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED() LL_AHB2_GRP1_IsEnabledClockSleep(LL_AHB2_GRP1_PERIPH_GPIOH) +#endif /* CORE_CM0PLUS */ +/** + * @} + */ + +/** @defgroup RCC_AHB3_Clock_Sleep_Enable_Disable_Status AHB3 Peripheral Clock Sleep Enabled or Disabled Status + * @brief Check whether the AHB3 peripheral clock during Low Power (Sleep) mode is enabled or not. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#if defined(CORE_CM0PLUS) +#define __HAL_RCC_PKA_IS_CLK_SLEEP_ENABLED() LL_C2_AHB3_GRP1_IsEnabledClockSleep(LL_AHB3_GRP1_PERIPH_PKA) +#define __HAL_RCC_AES_IS_CLK_SLEEP_ENABLED() LL_C2_AHB3_GRP1_IsEnabledClockSleep(LL_AHB3_GRP1_PERIPH_AES) +#define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() LL_C2_AHB3_GRP1_IsEnabledClockSleep(LL_AHB3_GRP1_PERIPH_RNG) +#define __HAL_RCC_SRAM1_IS_CLK_SLEEP_ENABLED() LL_C2_AHB3_GRP1_IsEnabledClockSleep(LL_AHB3_GRP1_PERIPH_SRAM1) +#define __HAL_RCC_SRAM2_IS_CLK_SLEEP_ENABLED() LL_C2_AHB3_GRP1_IsEnabledClockSleep(LL_AHB3_GRP1_PERIPH_SRAM2) +#define __HAL_RCC_FLASH_IS_CLK_SLEEP_ENABLED() LL_C2_AHB3_GRP1_IsEnabledClockSleep(LL_AHB3_GRP1_PERIPH_FLASH) +#else +#define __HAL_RCC_PKA_IS_CLK_SLEEP_ENABLED() LL_AHB3_GRP1_IsEnabledClockSleep(LL_AHB3_GRP1_PERIPH_PKA) +#define __HAL_RCC_AES_IS_CLK_SLEEP_ENABLED() LL_AHB3_GRP1_IsEnabledClockSleep(LL_AHB3_GRP1_PERIPH_AES) +#define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() LL_AHB3_GRP1_IsEnabledClockSleep(LL_AHB3_GRP1_PERIPH_RNG) +#define __HAL_RCC_SRAM1_IS_CLK_SLEEP_ENABLED() LL_AHB3_GRP1_IsEnabledClockSleep(LL_AHB3_GRP1_PERIPH_SRAM1) +#define __HAL_RCC_SRAM2_IS_CLK_SLEEP_ENABLED() LL_AHB3_GRP1_IsEnabledClockSleep(LL_AHB3_GRP1_PERIPH_SRAM2) +#define __HAL_RCC_FLASH_IS_CLK_SLEEP_ENABLED() LL_AHB3_GRP1_IsEnabledClockSleep(LL_AHB3_GRP1_PERIPH_FLASH) +#endif /* CORE_CM0PLUS */ +/** + * @} + */ + +/** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable_Status APB1 Peripheral Clock Sleep Enabled or Disabled Status + * @brief Check whether the APB1 peripheral clock during Low Power (Sleep) mode is enabled or not. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#if defined(CORE_CM0PLUS) +#define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() LL_C2_APB1_GRP1_IsEnabledClockSleep(LL_C2_APB1_GRP1_PERIPH_TIM2) +#define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_ENABLED() LL_C2_APB1_GRP1_IsEnabledClockSleep(LL_C2_APB1_GRP1_PERIPH_RTCAPB) +#define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() LL_C2_APB1_GRP1_IsEnabledClockSleep(LL_C2_APB1_GRP1_PERIPH_USART2) +#define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() LL_C2_APB1_GRP1_IsEnabledClockSleep(LL_C2_APB1_GRP1_PERIPH_SPI2) +#define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() LL_C2_APB1_GRP1_IsEnabledClockSleep(LL_C2_APB1_GRP1_PERIPH_I2C1) +#define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED() LL_C2_APB1_GRP1_IsEnabledClockSleep(LL_C2_APB1_GRP1_PERIPH_I2C2) +#define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED() LL_C2_APB1_GRP1_IsEnabledClockSleep(LL_C2_APB1_GRP1_PERIPH_I2C3) +#define __HAL_RCC_DAC_IS_CLK_SLEEP_ENABLED() LL_C2_APB1_GRP1_IsEnabledClockSleep(LL_C2_APB1_GRP1_PERIPH_DAC) +#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() LL_C2_APB1_GRP1_IsEnabledClockSleep(LL_C2_APB1_GRP1_PERIPH_LPTIM1) + +#define __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED() LL_C2_APB1_GRP2_IsEnabledClockSleep(LL_C2_APB1_GRP2_PERIPH_LPUART1) +#define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_ENABLED() LL_C2_APB1_GRP2_IsEnabledClockSleep(LL_C2_APB1_GRP2_PERIPH_LPTIM2) +#define __HAL_RCC_LPTIM3_IS_CLK_SLEEP_ENABLED() LL_C2_APB1_GRP2_IsEnabledClockSleep(LL_C2_APB1_GRP2_PERIPH_LPTIM3) +#else +#define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() LL_APB1_GRP1_IsEnabledClockSleep(LL_APB1_GRP1_PERIPH_TIM2) +#define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_ENABLED() LL_APB1_GRP1_IsEnabledClockSleep(LL_APB1_GRP1_PERIPH_RTCAPB) +#define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() LL_APB1_GRP1_IsEnabledClockSleep(LL_APB1_GRP1_PERIPH_USART2) +#define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() LL_APB1_GRP1_IsEnabledClockSleep(LL_APB1_GRP1_PERIPH_SPI2) +#define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() LL_APB1_GRP1_IsEnabledClockSleep(LL_APB1_GRP1_PERIPH_I2C1) +#define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED() LL_APB1_GRP1_IsEnabledClockSleep(LL_APB1_GRP1_PERIPH_I2C2) +#define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED() LL_APB1_GRP1_IsEnabledClockSleep(LL_APB1_GRP1_PERIPH_I2C3) +#define __HAL_RCC_DAC_IS_CLK_SLEEP_ENABLED() LL_APB1_GRP1_IsEnabledClockSleep(LL_APB1_GRP1_PERIPH_DAC) +#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() LL_APB1_GRP1_IsEnabledClockSleep(LL_APB1_GRP1_PERIPH_LPTIM1) + +#define __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED() LL_APB1_GRP2_IsEnabledClockSleep(LL_APB1_GRP2_PERIPH_LPUART1) +#define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_ENABLED() LL_APB1_GRP2_IsEnabledClockSleep(LL_APB1_GRP2_PERIPH_LPTIM2) +#define __HAL_RCC_LPTIM3_IS_CLK_SLEEP_ENABLED() LL_APB1_GRP2_IsEnabledClockSleep(LL_APB1_GRP2_PERIPH_LPTIM3) +#endif /* CORE_CM0PLUS */ + +#define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED() LL_APB1_GRP1_IsEnabledClockSleep(LL_APB1_GRP1_PERIPH_WWDG) +/** + * @} + */ + +/** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable_Status APB2 Peripheral Clock Sleep Enabled or Disabled Status + * @brief Check whether the APB2 peripheral clock during Low Power (Sleep) mode is enabled or not. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#if defined(CORE_CM0PLUS) +#define __HAL_RCC_ADC_IS_CLK_SLEEP_ENABLED() LL_C2_APB2_GRP1_IsEnabledClockSleep(LL_C2_APB2_GRP1_PERIPH_ADC) +#define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED() LL_C2_APB2_GRP1_IsEnabledClockSleep(LL_C2_APB2_GRP1_PERIPH_TIM1) +#define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() LL_C2_APB2_GRP1_IsEnabledClockSleep(LL_C2_APB2_GRP1_PERIPH_SPI1) +#define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() LL_C2_APB2_GRP1_IsEnabledClockSleep(LL_C2_APB2_GRP1_PERIPH_USART1) +#define __HAL_RCC_TIM16_IS_CLK_SLEEP_ENABLED() LL_C2_APB2_GRP1_IsEnabledClockSleep(LL_C2_APB2_GRP1_PERIPH_TIM16) +#define __HAL_RCC_TIM17_IS_CLK_SLEEP_ENABLED() LL_C2_APB2_GRP1_IsEnabledClockSleep(LL_C2_APB2_GRP1_PERIPH_TIM17) +#else +#define __HAL_RCC_ADC_IS_CLK_SLEEP_ENABLED() LL_APB2_GRP1_IsEnabledClockSleep(LL_APB2_GRP1_PERIPH_ADC) +#define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED() LL_APB2_GRP1_IsEnabledClockSleep(LL_APB2_GRP1_PERIPH_TIM1) +#define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() LL_APB2_GRP1_IsEnabledClockSleep(LL_APB2_GRP1_PERIPH_SPI1) +#define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() LL_APB2_GRP1_IsEnabledClockSleep(LL_APB2_GRP1_PERIPH_USART1) +#define __HAL_RCC_TIM16_IS_CLK_SLEEP_ENABLED() LL_APB2_GRP1_IsEnabledClockSleep(LL_APB2_GRP1_PERIPH_TIM16) +#define __HAL_RCC_TIM17_IS_CLK_SLEEP_ENABLED() LL_APB2_GRP1_IsEnabledClockSleep(LL_APB2_GRP1_PERIPH_TIM17) +#endif /* CORE_CM0PLUS */ +/** + * @} + */ + +/** @defgroup RCC_APB3_Clock_Sleep_Enable_Disable_Status APB3 Peripheral Clock Sleep Enabled or Disabled Status + * @brief Check whether the APB3 peripheral clock during Low Power (Sleep) mode is enabled or not. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#if defined(CORE_CM0PLUS) +#define __HAL_RCC_SUBGHZSPI_IS_CLK_SLEEP_ENABLED() \ + LL_C2_APB3_GRP1_IsEnabledClockSleep(LL_C2_APB3_GRP1_PERIPH_SUBGHZSPI) +#else +#define __HAL_RCC_SUBGHZSPI_IS_CLK_SLEEP_ENABLED() \ + LL_APB3_GRP1_IsEnabledClockSleep(LL_APB3_GRP1_PERIPH_SUBGHZSPI) +#endif /* CORE_CM0PLUS */ + +/* Aliases used by CubeMX for HAL SUBGHZ Init, MspInit and DeInit generation */ +#define __HAL_RCC_SUBGHZ_IS_CLK_SLEEP_ENABLED() __HAL_RCC_SUBGHZSPI_IS_CLK_SLEEP_ENABLED() +/** + * @} + */ + +/** @defgroup RCC_Backup_Domain_Reset RCC Backup Domain Reset + * @{ + */ + +/** @brief Macros to force or release the Backup domain reset. + * @note This function resets the RTC peripheral (including the backup registers) + * and the RTC clock source selection in RCC_CSR register. + * @note The SRAM2 is not affected by this reset. + * @retval None + */ +#define __HAL_RCC_BACKUPRESET_FORCE() LL_RCC_ForceBackupDomainReset() +#define __HAL_RCC_BACKUPRESET_RELEASE() LL_RCC_ReleaseBackupDomainReset() +/** + * @} + */ + +/** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration + * @{ + */ + +/** @brief Macros to enable or disable the RTC clock. + * @note As the RTC is in the Backup domain and write access is denied to + * this domain after reset, you have to enable write access using + * HAL_PWR_EnableBkUpAccess() function before to configure the RTC + * (to be done once after reset). + * @note These macros must be used after the RTC clock source was selected. + * @retval None + */ +#define __HAL_RCC_RTC_ENABLE() LL_RCC_EnableRTC() +#define __HAL_RCC_RTC_DISABLE() LL_RCC_DisableRTC() +/** + * @} + */ + +/** @brief Macros to enable the Internal High Speed oscillator (HSI). + * @note The HSI is stopped by hardware when entering STOP, STANDBY or SHUTDOWN modes. + * It is enabled by hardware to force the HSI oscillator ON when STOPWUCK=1 + * or HSIASFS = 1 when leaving Stop modes, or in case of failure of the HSE + * crystal oscillator and Security System CSS is enabled. + * @note After enabling the HSI, the application software should wait on HSIRDY + * flag to be set indicating that HSI clock is stable and can be used as + * system clock source. + * @retval None + */ +#define __HAL_RCC_HSI_ENABLE() LL_RCC_HSI_Enable() + +/** @brief Macro to disable the Internal High Speed oscillator (HSI). + * @note HSI can not be stopped if it is used as system clock source. In this case, + * you have to select another source of the system clock then stop the HSI. + * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator + * clock cycles. + * @retval None + */ +#define __HAL_RCC_HSI_DISABLE() LL_RCC_HSI_Disable() + +/** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value. + * @note The calibration is used to compensate for the variations in voltage + * and temperature that influence the frequency of the internal HSI RC. + * @param __HSICALIBRATIONVALUE__ specifies the calibration trimming value + * (default is RCC_HSICALIBRATION_DEFAULT). + * This parameter must be a number between Min_data=0 and Max_Data=127. + * @retval None + */ +#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) \ + LL_RCC_HSI_SetCalibTrimming(__HSICALIBRATIONVALUE__) + +/** + * @brief Macros to enable or disable the wakeup the Internal High Speed oscillator (HSI) + * in parallel to the Internal Multi Speed oscillator (MSI) used at system wakeup. + * @note The enable of this function has not effect on the HSION bit. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +#define __HAL_RCC_HSIAUTOMATIC_START_ENABLE() LL_RCC_HSI_EnableAutoFromStop() +#define __HAL_RCC_HSIAUTOMATIC_START_DISABLE() LL_RCC_HSI_DisableAutoFromStop() + +/** + * @brief Macros to enable or disable the force of the Internal High Speed oscillator (HSI) + * in STOP mode to be quickly available as kernel clock for USARTs and I2Cs. + * @note Keeping the HSI ON in STOP mode allows to avoid slowing down the communication + * speed because of the HSI startup time. + * @note The enable of this function has not effect on the HSION bit. + * @retval None + */ +#define __HAL_RCC_HSISTOP_ENABLE() LL_RCC_HSI_EnableInStopMode() +#define __HAL_RCC_HSISTOP_DISABLE() LL_RCC_HSI_DisableInStopMode() + +/** + * @brief Macros to enable or disable the Internal Multi Speed oscillator (MSI). + * @note The MSI is stopped by hardware when entering STOP and STANDBY modes. + * It is used (enabled by hardware) as system clock source after + * startup from Reset, wakeup from STOP and STANDBY mode, or in case + * of failure of the HSE used directly or indirectly as system clock + * (if the Clock Security System CSS is enabled). + * @note MSI can not be stopped if it is used as system clock source. + * In this case, you have to select another source of the system + * clock then stop the MSI. + * @note After enabling the MSI, the application software should wait on + * MSIRDY flag to be set indicating that MSI clock is stable and can + * be used as system clock source. + * @note When the MSI is stopped, MSIRDY flag goes low after 6 MSI oscillator + * clock cycles. + * @retval None + */ +#define __HAL_RCC_MSI_ENABLE() LL_RCC_MSI_Enable() +#define __HAL_RCC_MSI_DISABLE() LL_RCC_MSI_Disable() + +/** @brief Macro to adjust the Internal Multi Speed oscillator (MSI) calibration value. + * @note The calibration is used to compensate for the variations in voltage + * and temperature that influence the frequency of the internal MSI RC. + * Refer to the Application Note AN3300 for more details on how to + * calibrate the MSI. + * @param __MSICALIBRATIONVALUE__ specifies the calibration trimming value + * (default is @ref RCC_MSICALIBRATION_DEFAULT). + * This parameter must be a number between 0 and 255. + * @retval None + */ +#define __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(__MSICALIBRATIONVALUE__) \ + LL_RCC_MSI_SetCalibTrimming(__MSICALIBRATIONVALUE__) + +/** + * @brief Macro configures the Internal Multi Speed oscillator (MSI) clock range in run mode + * @note After restart from Reset , the MSI clock is around 4 MHz. + * After stop the startup clock can be MSI (at any of its possible + * frequencies, the one that was used before entering stop mode) or HSI. + * After Standby its frequency can be selected between 4 possible values + * (1, 2, 4 or 8 MHz). + * @note MSIRANGE can be modified when MSI is OFF (MSION=0) or when MSI is ready + * (MSIRDY=1). + * @note The MSI clock range after reset can be modified on the fly. + * @param __MSIRANGEVALUE__ specifies the MSI clock range. + * This parameter must be one of the following values: + * @arg @ref RCC_MSIRANGE_0 MSI clock is around 100 KHz + * @arg @ref RCC_MSIRANGE_1 MSI clock is around 200 KHz + * @arg @ref RCC_MSIRANGE_2 MSI clock is around 400 KHz + * @arg @ref RCC_MSIRANGE_3 MSI clock is around 800 KHz + * @arg @ref RCC_MSIRANGE_4 MSI clock is around 1 MHz + * @arg @ref RCC_MSIRANGE_5 MSI clock is around 2 MHz + * @arg @ref RCC_MSIRANGE_6 MSI clock is around 4 MHz (default after Reset) + * @arg @ref RCC_MSIRANGE_7 MSI clock is around 8 MHz + * @arg @ref RCC_MSIRANGE_8 MSI clock is around 16 MHz + * @arg @ref RCC_MSIRANGE_9 MSI clock is around 24 MHz + * @arg @ref RCC_MSIRANGE_10 MSI clock is around 32 MHz + * @arg @ref RCC_MSIRANGE_11 MSI clock is around 48 MHz + * @retval None + */ +#define __HAL_RCC_MSI_RANGE_CONFIG(__MSIRANGEVALUE__) do { \ + SET_BIT(RCC->CR, RCC_CR_MSIRGSEL); \ + MODIFY_REG(RCC->CR, RCC_CR_MSIRANGE, (__MSIRANGEVALUE__)); \ + } while(0) + +/** + * @brief Macro configures the Internal Multi Speed oscillator (MSI) clock range after Standby mode + * After Standby its frequency can be selected between 4 possible values (1, 2, 4 or 8 MHz). + * @param __MSIRANGEVALUE__ specifies the MSI clock range. + * This parameter must be one of the following values: + * @arg @ref RCC_MSIRANGE_4 MSI clock is around 1 MHz + * @arg @ref RCC_MSIRANGE_5 MSI clock is around 2 MHz + * @arg @ref RCC_MSIRANGE_6 MSI clock is around 4 MHz (default after Reset) + * @arg @ref RCC_MSIRANGE_7 MSI clock is around 8 MHz + * @retval None + */ +#define __HAL_RCC_MSI_STANDBY_RANGE_CONFIG(__MSIRANGEVALUE__) \ + MODIFY_REG(RCC->CSR, RCC_CSR_MSISRANGE, (__MSIRANGEVALUE__) << 4U) + +/** @brief Macro to get the Internal Multi Speed oscillator (MSI) clock range in run mode + * @retval MSI clock range. + * This parameter must be one of the following values: + * @arg @ref RCC_MSIRANGE_0 MSI clock is around 100 KHz + * @arg @ref RCC_MSIRANGE_1 MSI clock is around 200 KHz + * @arg @ref RCC_MSIRANGE_2 MSI clock is around 400 KHz + * @arg @ref RCC_MSIRANGE_3 MSI clock is around 800 KHz + * @arg @ref RCC_MSIRANGE_4 MSI clock is around 1 MHz + * @arg @ref RCC_MSIRANGE_5 MSI clock is around 2 MHz + * @arg @ref RCC_MSIRANGE_6 MSI clock is around 4 MHz (default after Reset) + * @arg @ref RCC_MSIRANGE_7 MSI clock is around 8 MHz + * @arg @ref RCC_MSIRANGE_8 MSI clock is around 16 MHz + * @arg @ref RCC_MSIRANGE_9 MSI clock is around 24 MHz + * @arg @ref RCC_MSIRANGE_10 MSI clock is around 32 MHz + * @arg @ref RCC_MSIRANGE_11 MSI clock is around 48 MHz + */ +#define __HAL_RCC_GET_MSI_RANGE() ((READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) != 0U) ? \ + (uint32_t)(READ_BIT(RCC->CR, RCC_CR_MSIRANGE)) : \ + (uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_MSISRANGE) >> 4)) + +/** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI). + * @note After enabling the LSI, the application software should wait on + * LSIRDY flag to be set indicating that LSI clock is stable and can + * be used to clock the IWDG and/or the RTC. + * @note LSI can not be disabled if the IWDG is running. + * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator + * clock cycles. + * @retval None + */ +#define __HAL_RCC_LSI_ENABLE() LL_RCC_LSI_Enable() +#define __HAL_RCC_LSI_DISABLE() LL_RCC_LSI_Disable() + +/** + * @brief Macro to configure the External High Speed oscillator (HSE). + * @note Transition RCC_HSE_BYPASS_PWR to RCC_HSE_ON and RCC_HSE_ON to + * RCC_HSE_BYPASS_PWR are not supported by this macro. User should + * request a transition to RCC_HSE_OFF first and then RCC_HSE_ON or + * RCC_HSE_BYPASS_PWR. + * @note After enabling the HSE (RCC_HSE_ON, RCC_HSE_BYPASS_PWR), + * the application software should wait on HSERDY flag to be set indicating + * that HSE clock is stable and can be used to clock the PLL and/or system clock. + * @note HSE state can not be changed if it is used directly or through the + * PLL as system clock. In this case, you have to select another source + * of the system clock then change the HSE state (ex. disable it). + * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. + * @note PB0 must be configured in analog mode prior enabling the HSE with + * RCC_HSE_BYPASS_PWR. + * @param __STATE__ specifies the new state of the HSE. + * This parameter can be one of the following values: + * @arg @ref RCC_HSE_OFF Turn OFF the HSE oscillator, HSERDY flag + * goes low after 6 HSE oscillator clock cycles. + * @arg @ref RCC_HSE_ON Turn ON the HSE oscillator. + * @arg @ref RCC_HSE_BYPASS_PWR HSE32 driven from an external TCXO powered by the PB0-VDDTCXO pin. + * @retval None + */ +#define __HAL_RCC_HSE_CONFIG(__STATE__) do { \ + if((__STATE__) == RCC_HSE_ON) \ + { \ + LL_RCC_HSE_Enable(); \ + } \ + else if((__STATE__) == RCC_HSE_BYPASS_PWR) \ + { \ + LL_RCC_HSE_EnableTcxo(); \ + LL_RCC_HSE_Enable(); \ + } \ + else \ + { \ + LL_RCC_HSE_Disable(); \ + LL_RCC_HSE_DisableTcxo(); \ + } \ + } while(0U) + +/** @brief Macros to enable or disable the HSE Prescaler + * @note HSE prescaler shall be enabled when HSE is used as + * system clock source and Voltage scaling range 1 + * (Low-power range) is selected. + * @retval None + */ +#define __HAL_RCC_HSE_DIV2_ENABLE() LL_RCC_HSE_EnableDiv2() +#define __HAL_RCC_HSE_DIV2_DISABLE() LL_RCC_HSE_DisableDiv2() + +/** + * @brief Macro to configure the External Low Speed oscillator (LSE). + * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not + * supported by this macro. User should request a transition to LSE Off + * first and then LSE On or LSE Bypass. + * @note As the LSE is in the Backup domain and write access is denied to + * this domain after reset, you have to enable write access using + * HAL_PWR_EnableBkUpAccess() function before to configure the LSE + * (to be done once after reset). + * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application + * software should wait on LSERDY flag to be set indicating that LSE clock + * is stable and can be used to clock the RTC. + * @param __STATE__ specifies the new state of the LSE. + * This parameter can be one of the following values: + * @arg @ref RCC_LSE_OFF Turn OFF the LSE oscillator, LSERDY flag goes low after + * 6 LSE oscillator clock cycles. + * @arg @ref RCC_LSE_ON_RTC_ONLY Turn ON the LSE oscillator to be used only for RTC. + * @arg @ref RCC_LSE_ON Turn ON the LSE oscillator to be used by any peripheral. + * @arg @ref RCC_LSE_BYPASS_RTC_ONLY LSE oscillator bypassed with external clock to be used only for RTC. + * @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock to be used by any peripheral. + * @retval None + */ +#define __HAL_RCC_LSE_CONFIG(__STATE__) \ + do { \ + if((__STATE__) == RCC_LSE_ON_RTC_ONLY) \ + { \ + SET_BIT(RCC->BDCR,RCC_BDCR_LSEON); \ + } \ + else if((__STATE__) == RCC_LSE_ON) \ + { \ + SET_BIT(RCC->BDCR, (RCC_BDCR_LSEON | RCC_BDCR_LSESYSEN)); \ + } \ + else if((__STATE__) == RCC_LSE_BYPASS_RTC_ONLY) \ + { \ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ + } \ + else if((__STATE__) == RCC_LSE_BYPASS) \ + { \ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ + SET_BIT(RCC->BDCR, (RCC_BDCR_LSEON | RCC_BDCR_LSESYSEN)); \ + } \ + else \ + { \ + CLEAR_BIT(RCC->BDCR, (RCC_BDCR_LSEON | RCC_BDCR_LSESYSEN)); \ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ + } \ + } while(0) + +/** @brief Macro to configure the RTC clock (RTCCLK). + * @note As the RTC clock configuration bits are in the Backup domain and write + * access is denied to this domain after reset, you have to enable write + * access using the Power Backup Access macro before to configure + * the RTC clock source (to be done once after reset). + * @note Once the RTC clock is configured it cannot be changed unless the + * Backup domain is reset using @ref __HAL_RCC_BACKUPRESET_FORCE() macro, or by + * a Power On Reset (POR). + * + * @param __RTC_CLKSOURCE__ specifies the RTC clock source. + * This parameter can be one of the following values:* + * @arg @ref RCC_RTCCLKSOURCE_NONE none clock selected as RTC clock. + * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock. + * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock. + * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 selected + * + * @note If the LSE or LSI is used as RTC clock source, the RTC continues to + * work in STOP and STANDBY modes, and can be used as wakeup source. + * However, when the HSE clock is used as RTC clock source, the RTC + * cannot be used in STOP and STANDBY modes. + * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as + * RTC clock source). + * @retval None + */ +#define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) LL_RCC_SetRTCClockSource(__RTC_CLKSOURCE__) + +/** @brief Macro to get the RTC clock source. + * @retval The returned value can be one of the following: + * @arg @ref RCC_RTCCLKSOURCE_NONE none clock selected as RTC clock. + * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock. + * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock. + * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 selected + */ +#define __HAL_RCC_GET_RTC_SOURCE() LL_RCC_GetRTCClockSource() + +/** @brief Macros to enable or disable the main PLL. + * @note After enabling the main PLL, the application software should wait on + * PLLRDY flag to be set indicating that PLL clock is stable and can + * be used as system clock source. + * @note The main PLL can not be disabled if it is used as system clock source + * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes. + * @retval None + */ +#define __HAL_RCC_PLL_ENABLE() LL_RCC_PLL_Enable() +#define __HAL_RCC_PLL_DISABLE() LL_RCC_PLL_Disable() + +/** @brief Macro to configure the PLL clock source. + * @note This function must be used only when the main PLL is disabled. + * @param __PLLSOURCE__ specifies the PLL entry clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_PLLSOURCE_NONE No clock selected as PLL clock entry + * @arg @ref RCC_PLLSOURCE_MSI MSI oscillator clock selected as PLL clock entry + * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry + * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry + * @retval None + * + */ +#define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) \ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__)) +/** + * @brief Macro to configure the main PLL clock source, multiplication and division factors. + * @note This function must be used only when the main PLL is disabled. + * + * @param __PLLSOURCE__ specifies the PLL entry clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_PLLSOURCE_NONE No clock selected as PLL clock entry + * @arg @ref RCC_PLLSOURCE_MSI MSI oscillator clock selected as PLL clock entry + * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry + * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry + * + * @param __PLLM__ specifies the division factor for PLL VCO input clock. + * This parameter must be a value of @ref RCC_PLLM_Clock_Divider. + * @note You have to set the PLLM parameter correctly to ensure that the VCO input + * frequency ranges from 2.66 to 16 MHz. It is recommended to select a frequency + * of 16 MHz to limit PLL jitter. + * + * @param __PLLN__ specifies the multiplication factor for PLL VCO output clock. + * This parameter must be a number between 6 and 127. + * @note You have to set the PLLN parameter correctly to ensure that the VCO + * output frequency is between 96 and 344 MHz. + * + * @param __PLLP__ specifies the division factor for ADC clock. + * This parameter must be a value of @ref RCC_PLLP_Clock_Divider. + * + * @param __PLLQ__ specifies the division factor for I2S2 and RNG clocks. + * This parameter must be a value of @ref RCC_PLLQ_Clock_Divider + * + * @note RNG need a frequency lower than or equal to 48 MHz to work correctly. + * + * @param __PLLR__ specifies the division factor for the main system clock. + * This parameter must be a value of @ref RCC_PLLR_Clock_Divider + * @note You have to set the PLLR parameter correctly to not exceed 48 MHZ. + * @retval None + */ +#define __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__ ) \ + MODIFY_REG(RCC->PLLCFGR, \ + (RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | \ + RCC_PLLCFGR_PLLP | RCC_PLLCFGR_PLLQ | RCC_PLLCFGR_PLLR), \ + ((uint32_t) (__PLLSOURCE__) | \ + (uint32_t) (__PLLM__) | \ + (uint32_t) ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \ + (uint32_t) (__PLLP__) | \ + (uint32_t) (__PLLQ__) | \ + (uint32_t) (__PLLR__))) + +/** @brief Macro to get the oscillator used as PLL clock source. + * @retval The oscillator used as PLL clock source. The returned value can be one + * of the following: + * @arg @ref RCC_PLLSOURCE_NONE No oscillator is used as PLL clock source. + * @arg @ref RCC_PLLSOURCE_MSI MSI oscillator is used as PLL clock source. + * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator is used as PLL clock source. + * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator is used as PLL clock source. + */ +#define __HAL_RCC_GET_PLL_OSCSOURCE() LL_RCC_PLL_GetMainSource() + +/** + * @brief Enable or disable each clock output (RCC_PLL_SYSCLK, RCC_PLL_I2S2CLK, RCC_PLL_RNGCLK, RCC_PLL_ADCCLK) + * @note Enabling/disabling clock outputs RCC_PLL_I2S2CLK, RCC_PLL_RNGCLK and RCC_PLL_ADCCLK can be done at anytime + * without the need to stop the PLL in order to save power. But RCC_PLL_SYSCLK cannot + * be stopped if used as System Clock. + * @param __PLLCLOCKOUT__ specifies the PLL clock to be output. + * This parameter can be one or a combination of the following values: + * @arg @ref RCC_PLL_ADCCLK This clock is used to generate the clock for ADC + * @arg @ref RCC_PLL_I2S2CLK This Clock is used to generate the clock for the I2S + * @arg @ref RCC_PLL_RNGCLK This clock is used to generate the clock for RNG + * @arg @ref RCC_PLL_SYSCLK This Clock is used to generate the high speed system clock (up to 48 MHz) + * @retval None + */ +#define __HAL_RCC_PLLCLKOUT_ENABLE(__PLLCLOCKOUT__) SET_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__)) + +#define __HAL_RCC_PLLCLKOUT_DISABLE(__PLLCLOCKOUT__) CLEAR_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__)) + +/** + * @brief Get clock output enable status (RCC_PLL_SYSCLK, RCC_PLL_I2S2CLK, RCC_PLL_RNGCLK, RCC_PLL_ADCCLK) + * @param __PLLCLOCKOUT__ specifies the output PLL clock to be checked. + * This parameter can be one of the following values: + * @arg @ref RCC_PLL_ADCCLK same + * @arg @ref RCC_PLL_I2S2CLK This Clock is used to generate the clock for the I2S + * @arg @ref RCC_PLL_RNGCLK This clock is used to generate the clock for RNG + * @arg @ref RCC_PLL_SYSCLK This Clock is used to generate the high speed system clock (up to 48 MHz) + * @retval SET / RESET + */ +#define __HAL_RCC_GET_PLLCLKOUT_CONFIG(__PLLCLOCKOUT__) READ_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__)) + +/** + * @brief Macro to configure the system clock source. + * @param __SYSCLKSOURCE__ specifies the system clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_SYSCLKSOURCE_MSI MSI oscillator is used as system clock source. + * @arg @ref RCC_SYSCLKSOURCE_HSI HSI oscillator is used as system clock source. + * @arg @ref RCC_SYSCLKSOURCE_HSE HSE oscillator is used as system clock source. + * @arg @ref RCC_SYSCLKSOURCE_PLLCLK PLL output is used as system clock source. + * @retval None + */ +#define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) LL_RCC_SetSysClkSource(__SYSCLKSOURCE__) + +/** @brief Macro to get the clock source used as system clock. + * @retval The clock source used as system clock. The returned value can be one + * of the following: + * @arg @ref RCC_SYSCLKSOURCE_STATUS_MSI MSI used as system clock. + * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSI HSI used as system clock. + * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSE HSE used as system clock. + * @arg @ref RCC_SYSCLKSOURCE_STATUS_PLLCLK PLL used as system clock. + */ +#define __HAL_RCC_GET_SYSCLK_SOURCE() LL_RCC_GetSysClkSource() + +/** + * @brief Macro to configure the External Low Speed oscillator (LSE) drive capability. + * @note As the LSE is in the Backup domain and write access is denied to + * this domain after reset, you have to enable write access using + * HAL_PWR_EnableBkUpAccess() function before to configure the LSE + * (to be done once after reset). + * @param __LSEDRIVE__ specifies the new state of the LSE drive capability. + * This parameter can be one of the following values: + * @arg @ref RCC_LSEDRIVE_LOW LSE oscillator low drive capability. + * @arg @ref RCC_LSEDRIVE_MEDIUMLOW LSE oscillator medium low drive capability. + * @arg @ref RCC_LSEDRIVE_MEDIUMHIGH LSE oscillator medium high drive capability. + * @arg @ref RCC_LSEDRIVE_HIGH LSE oscillator high drive capability. + * @retval None + */ +#define __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) LL_RCC_LSE_SetDriveCapability(__LSEDRIVE__) + +/** + * @brief Macro to configure the wake up from stop clock. + * @param __STOPWUCLK__ specifies the clock source used after wake up from stop. + * This parameter can be one of the following values: + * @arg @ref RCC_STOP_WAKEUPCLOCK_MSI MSI selected as system clock source + * @arg @ref RCC_STOP_WAKEUPCLOCK_HSI HSI selected as system clock source + * @retval None + */ +#define __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(__STOPWUCLK__) LL_RCC_SetClkAfterWakeFromStop(__STOPWUCLK__) + + +/** @brief Macro to configure the MCO clock. + * @param __MCOCLKSOURCE__ specifies the MCO clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_MCO1SOURCE_NOCLOCK MCO output disabled + * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock selected as MCO source + * @arg @ref RCC_MCO1SOURCE_MSI MSI clock selected as MCO source + * @arg @ref RCC_MCO1SOURCE_HSI HSI clock selected as MCO source + * @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO source + * @arg @ref RCC_MCO1SOURCE_PLLCLK Main PLL clock selected as MCO source + * @arg @ref RCC_MCO1SOURCE_LSI LSI clock selected as MCO source + * @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO source + * @arg @ref RCC_MCO1SOURCE_PLLPCLK main PLLP clock selected as MCO source + * @arg @ref RCC_MCO1SOURCE_PLLQCLK main PLLQ clock selected as MCO source + * @param __MCODIV__ specifies the MCO clock prescaler. + * This parameter can be one of the following values: + * @arg @ref RCC_MCODIV_1 MCO clock source is divided by 1 + * @arg @ref RCC_MCODIV_2 MCO clock source is divided by 2 + * @arg @ref RCC_MCODIV_4 MCO clock source is divided by 4 + * @arg @ref RCC_MCODIV_8 MCO clock source is divided by 8 + * @arg @ref RCC_MCODIV_16 MCO clock source is divided by 16 + */ +#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) LL_RCC_ConfigMCO((__MCOCLKSOURCE__), (__MCODIV__)) + +/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management + * @brief macros to manage the specified RCC Flags and interrupts. + * @{ + */ + +/** @brief Enable RCC interrupt. + * @param __INTERRUPT__ specifies the RCC interrupt sources to be enabled. + * This parameter can be any combination of the following values: + * @arg @ref RCC_IT_LSIRDY LSI ready interrupt enable + * @arg @ref RCC_IT_LSERDY LSE ready interrupt enable + * @arg @ref RCC_IT_MSIRDY HSI ready interrupt enable + * @arg @ref RCC_IT_HSIRDY HSI ready interrupt enable + * @arg @ref RCC_IT_HSERDY HSE ready interrupt enable + * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt enable + * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt enable + * @retval None + */ +#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__)) + +/** @brief Disable RCC interrupt. + * @param __INTERRUPT__ specifies the RCC interrupt sources to be disabled. + * This parameter can be any combination of the following values: + * @arg @ref RCC_IT_LSIRDY LSI ready interrupt enable + * @arg @ref RCC_IT_LSERDY LSE ready interrupt enable + * @arg @ref RCC_IT_MSIRDY HSI ready interrupt enable + * @arg @ref RCC_IT_HSIRDY HSI ready interrupt enable + * @arg @ref RCC_IT_HSERDY HSE ready interrupt enable + * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt enable + * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt enable + * @retval None + */ +#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__)) + +/** @brief Clear RCC interrupt pending bits (Perform Byte access to RCC_CICR[17:0] + * bits to clear the selected interrupt pending bits. + * @param __INTERRUPT__ specifies the interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg @ref RCC_IT_LSIRDY LSI ready interrupt clear + * @arg @ref RCC_IT_LSERDY LSE ready interrupt clear + * @arg @ref RCC_IT_MSIRDY HSI ready interrupt clear + * @arg @ref RCC_IT_HSIRDY HSI ready interrupt clear + * @arg @ref RCC_IT_HSERDY HSE ready interrupt clear + * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt clear + * @arg @ref RCC_IT_HSECSS HSE Clock security system interrupt clear + * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt clear + */ +#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (RCC->CICR = (__INTERRUPT__)) + +/** @brief Check whether the RCC interrupt has occurred or not. + * @param __INTERRUPT__ specifies the RCC interrupt source to check. + * This parameter can be one of the following values: + * @arg @ref RCC_IT_LSIRDY LSI ready interrupt flag + * @arg @ref RCC_IT_LSERDY LSE ready interrupt flag + * @arg @ref RCC_IT_MSIRDY HSI ready interrupt flag + * @arg @ref RCC_IT_HSIRDY HSI ready interrupt flag + * @arg @ref RCC_IT_HSERDY HSE ready interrupt flag + * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt flag + * @arg @ref RCC_IT_HSECSS HSE Clock security system interrupt flag + * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt flag + * @retval The new state of __INTERRUPT__ (TRUE or FALSE). + */ +#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__)) + +/** @brief Set RMVF bit to clear the reset flags. + * The reset flags are: LPWRRSTF, WWDGRSTF, IWDGRSTF, SFTRSTF, + BORRSTF, PINRSTF, OBLRSTF, and RFILARSTF. + * @retval None + */ +#define __HAL_RCC_CLEAR_RESET_FLAGS() LL_RCC_ClearResetFlags() + +/** @brief Check whether the selected RCC flag is set or not. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg @ref RCC_FLAG_MSIRDY MSI oscillator clock ready + * @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready + * @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready + * @arg @ref RCC_FLAG_PLLRDY Main PLL clock ready + * @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready + * @arg @ref RCC_FLAG_LSECSSD Clock security system failure on LSE oscillator detection + * @arg @ref RCC_FLAG_LSESYSRDY LSE system clock ready flag + * @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready + * @arg @ref RCC_FLAG_RFRST Sub-GHz radio reset flag + * @arg @ref RCC_FLAG_RFILARSTF Sub-GHz radio illegal command flag + * @arg @ref RCC_FLAG_BORRST BOR reset + * @arg @ref RCC_FLAG_OBLRST OBLRST reset + * @arg @ref RCC_FLAG_PINRST Pin reset + * @arg @ref RCC_FLAG_SFTRST Software reset + * @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset + * @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset + * @arg @ref RCC_FLAG_LPWRRST Low Power reset + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_RCC_GET_FLAG(__FLAG__) \ + (((((((__FLAG__) >> REG_INDEX_POS) == CR_REG_INDEX) ? RCC->CR : \ + ((((__FLAG__) >> REG_INDEX_POS) == BDCR_REG_INDEX) ? RCC->BDCR : \ + ((((__FLAG__) >> REG_INDEX_POS) == CSR_REG_INDEX) ? RCC->CSR : RCC->CIFR))) & \ + (1U << ((__FLAG__) & RCC_FLAG_MASK))) != RESET) ? 1UL : 0UL) + +/** + * @} + */ + +/** + * @} + */ + +/* Include RCC HAL Extended module */ +#include "stm32wlxx_hal_rcc_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup RCC_Exported_Functions + * @{ + */ + + +/** @addtogroup RCC_Exported_Functions_Group1 + * @{ + */ + +/* Initialization and de-initialization functions ****************************/ +HAL_StatusTypeDef HAL_RCC_DeInit(void); +HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); +HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency); + +/** + * @} + */ + +/** @addtogroup RCC_Exported_Functions_Group2 + * @{ + */ + +/* Peripheral Control functions **********************************************/ +void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv); +void HAL_RCC_EnableCSS(void); +uint32_t HAL_RCC_GetSysClockFreq(void); + +uint32_t HAL_RCC_GetHCLKFreq(void); +#if defined(DUAL_CORE) +uint32_t HAL_RCC_GetHCLK2Freq(void); +#endif /* DUAL_CORE */ +uint32_t HAL_RCC_GetHCLK3Freq(void); + +uint32_t HAL_RCC_GetPCLK1Freq(void); +uint32_t HAL_RCC_GetPCLK2Freq(void); + +void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); +void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency); +/* LSE & HSE CSS NMI IRQ handler */ +void HAL_RCC_NMI_IRQHandler(void); +/* User Callbacks in non blocking mode (IT mode) */ +void HAL_RCC_CSSCallback(void); + +uint32_t HAL_RCC_GetResetSource(void); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32WLxx_HAL_RCC_H */ diff --git a/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h b/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h new file mode 100644 index 0000000..b02b788 --- /dev/null +++ b/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h @@ -0,0 +1,701 @@ +/** + ****************************************************************************** + * @file stm32wlxx_hal_rcc_ex.h + * @author MCD Application Team + * @brief Header file of RCC HAL Extended module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32WLxx_HAL_RCC_EX_H +#define STM32WLxx_HAL_RCC_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wlxx_hal_def.h" +#include "stm32wlxx_ll_exti.h" +#include "stm32wlxx_ll_pwr.h" + +/** @addtogroup STM32WLxx_HAL_Driver + * @{ + */ + +/** @addtogroup RCCEx + * @{ + */ +/* Private constants ---------------------------------------------------------*/ +/** @addtogroup RCCEx_Private_Constants + * @{ + */ +/* Define used for IS_RCC_* macros below */ +#define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_I2S2 | \ + RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \ + RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | \ + RCC_PERIPHCLK_LPTIM3 | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_RNG | \ + RCC_PERIPHCLK_RTC ) +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup RCCEx_Private_Macros + * @{ + */ + +#define IS_RCC_LSCOSOURCE(__SOURCE__) (((__SOURCE__) == RCC_LSCOSOURCE_LSI) || \ + ((__SOURCE__) == RCC_LSCOSOURCE_LSE)) + +#define IS_RCC_PERIPHCLOCK(__SELECTION__) ((((__SELECTION__) & RCC_PERIPHCLOCK_ALL) != 0x00u) && \ + (((__SELECTION__) & ~RCC_PERIPHCLOCK_ALL) == 0x00u)) + +#define IS_RCC_USART1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK2) || \ + ((__SOURCE__) == RCC_USART1CLKSOURCE_SYSCLK) || \ + ((__SOURCE__) == RCC_USART1CLKSOURCE_LSE) || \ + ((__SOURCE__) == RCC_USART1CLKSOURCE_HSI)) + +#define IS_RCC_USART2CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_USART2CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_USART2CLKSOURCE_SYSCLK) || \ + ((__SOURCE__) == RCC_USART2CLKSOURCE_LSE) || \ + ((__SOURCE__) == RCC_USART2CLKSOURCE_HSI)) + +#define IS_RCC_I2S2CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2S2CLKSOURCE_PLL) || \ + ((__SOURCE__) == RCC_I2S2CLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_I2S2CLKSOURCE_PIN)) + +#define IS_RCC_LPUART1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_LPUART1CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_LPUART1CLKSOURCE_SYSCLK) || \ + ((__SOURCE__) == RCC_LPUART1CLKSOURCE_LSE) || \ + ((__SOURCE__) == RCC_LPUART1CLKSOURCE_HSI)) + +#define IS_RCC_I2C1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2C1CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK)|| \ + ((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI)) + +#define IS_RCC_I2C2CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2C2CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_I2C2CLKSOURCE_SYSCLK)|| \ + ((__SOURCE__) == RCC_I2C2CLKSOURCE_HSI)) + + +#define IS_RCC_I2C3CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2C3CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_I2C3CLKSOURCE_SYSCLK)|| \ + ((__SOURCE__) == RCC_I2C3CLKSOURCE_HSI)) + +#define IS_RCC_LPTIM1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_LPTIM1CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSI) || \ + ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSE)) + +#define IS_RCC_LPTIM2CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_LPTIM2CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSI) || \ + ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSE)) + +#define IS_RCC_LPTIM3CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_LPTIM3CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_LPTIM3CLKSOURCE_LSI) || \ + ((__SOURCE__) == RCC_LPTIM3CLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_LPTIM3CLKSOURCE_LSE)) + +#define IS_RCC_RNGCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RNGCLKSOURCE_PLL) || \ + ((__SOURCE__) == RCC_RNGCLKSOURCE_LSI) || \ + ((__SOURCE__) == RCC_RNGCLKSOURCE_LSE) || \ + ((__SOURCE__) == RCC_RNGCLKSOURCE_MSI)) + +#define IS_RCC_ADCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_ADCCLKSOURCE_NONE) || \ + ((__SOURCE__) == RCC_ADCCLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_ADCCLKSOURCE_PLL) || \ + ((__SOURCE__) == RCC_ADCCLKSOURCE_SYSCLK)) + +/** + * @} + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup RCCEx_Exported_Types RCCEx Exported Types + * @{ + */ + +/** + * @brief RCC extended clocks structure definition + */ +typedef struct +{ + uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. + This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ + + uint32_t Usart1ClockSelection; /*!< Specifies USART1 clock source. + This parameter can be a value of @ref RCCEx_USART1_Clock_Source */ + + uint32_t Usart2ClockSelection; /*!< Specifies USART2 clock source. + This parameter can be a value of @ref RCCEx_USART2_Clock_Source */ + + uint32_t I2s2ClockSelection; /*!< Specifies I2S2 clock source. + This parameter can be a value of @ref RCCEx_I2S2_Clock_Source */ + + uint32_t Lpuart1ClockSelection; /*!< Specifies LPUART1 clock source. + This parameter can be a value of @ref RCCEx_LPUART1_Clock_Source */ + + uint32_t I2c1ClockSelection; /*!< Specifies I2C1 clock source. + This parameter can be a value of @ref RCCEx_I2C1_Clock_Source */ + + uint32_t I2c2ClockSelection; /*!< Specifies I2C2 clock source. + This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */ + + uint32_t I2c3ClockSelection; /*!< Specifies I2C3 clock source. + This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */ + + uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 clock source. + This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */ + + uint32_t Lptim2ClockSelection; /*!< Specifies LPTIM2 clock source. + This parameter can be a value of @ref RCCEx_LPTIM2_Clock_Source */ + + uint32_t Lptim3ClockSelection; /*!< Specifies LPTIM3 clock source. + This parameter can be a value of @ref RCCEx_LPTIM3_Clock_Source */ + + uint32_t AdcClockSelection; /*!< Specifies ADC interface clock source. + This parameter can be a value of @ref RCCEx_ADC_Clock_Source */ + + uint32_t RngClockSelection; /*!< Specifies RNG clock source. + This parameter can be a value of @ref RCCEx_RNG_Clock_Source */ + + uint32_t RTCClockSelection; /*!< Specifies RTC clock source. + This parameter can be a value of @ref RCC_RTC_Clock_Source */ + +} RCC_PeriphCLKInitTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants + * @{ + */ + +/** @defgroup RCCEx_LSCO_Clock_Source Low Speed Clock Source + * @{ + */ +#define RCC_LSCOSOURCE_LSI LL_RCC_LSCO_CLKSOURCE_LSI /*!< LSI selection for low speed clock output */ +#define RCC_LSCOSOURCE_LSE LL_RCC_LSCO_CLKSOURCE_LSE /*!< LSE selection for low speed clock output */ +/** + * @} + */ + +/** @defgroup RCCEx_Periph_Clock_Selection Periph Clock Selection + * @{ + */ +#define RCC_PERIPHCLK_USART1 0x00000001U /*!< USART1 Peripheral Clock Selection */ +#define RCC_PERIPHCLK_USART2 0x00000002U /*!< USART2 Peripheral Clock Selection */ +#define RCC_PERIPHCLK_I2S2 0x00000010U /*!< I2S2 Peripheral Clock Selection */ +#define RCC_PERIPHCLK_LPUART1 0x00000020U /*!< LPUART1 Peripheral Clock Selection */ +#define RCC_PERIPHCLK_I2C1 0x00000040U /*!< I2C1 Peripheral Clock Selection */ +#define RCC_PERIPHCLK_I2C2 0x00000080U /*!< I2C2 Peripheral Clock Selection */ +#define RCC_PERIPHCLK_I2C3 0x00000100U /*!< I2C3 Peripheral Clock Selection */ +#define RCC_PERIPHCLK_LPTIM1 0x00000200U /*!< LPTIM1 Peripheral Clock Selection */ +#define RCC_PERIPHCLK_LPTIM2 0x00000400U /*!< LPTIM2 Peripheral Clock Selection */ +#define RCC_PERIPHCLK_LPTIM3 0x00000800U /*!< LPTIM3 Peripheral Clock Selection */ +#define RCC_PERIPHCLK_ADC 0x00004000U /*!< ADC Peripheral Clock Selection */ +#define RCC_PERIPHCLK_RNG 0x00008000U /*!< RNG Peripheral Clock Selection */ +#define RCC_PERIPHCLK_RTC 0x00010000U /*!< RTC Peripheral Clock Selection */ +/** + * @} + */ + +/** @defgroup RCCEx_USART1_Clock_Source USART1 Clock Source + * @{ + */ +#define RCC_USART1CLKSOURCE_PCLK2 LL_RCC_USART1_CLKSOURCE_PCLK2 /*!< APB2 clock selected as USART1 clock */ +#define RCC_USART1CLKSOURCE_SYSCLK LL_RCC_USART1_CLKSOURCE_SYSCLK /*!< SYSCLK clock selected as USART1 clock */ +#define RCC_USART1CLKSOURCE_HSI LL_RCC_USART1_CLKSOURCE_HSI /*!< HSI clock selected as USART1 clock */ +#define RCC_USART1CLKSOURCE_LSE LL_RCC_USART1_CLKSOURCE_LSE /*!< LSE clock selected as USART1 clock */ +/** + * @} + */ + +/** @defgroup RCCEx_USART2_Clock_Source USART2 Clock Source + * @{ + */ +#define RCC_USART2CLKSOURCE_PCLK1 LL_RCC_USART2_CLKSOURCE_PCLK1 /*!< APB1 clock selected as USART2 clock*/ +#define RCC_USART2CLKSOURCE_SYSCLK LL_RCC_USART2_CLKSOURCE_SYSCLK /*!< SYSCLK clock selected as USART2 clock*/ +#define RCC_USART2CLKSOURCE_HSI LL_RCC_USART2_CLKSOURCE_HSI /*!< HSI clock selected as USART2 clock*/ +#define RCC_USART2CLKSOURCE_LSE LL_RCC_USART2_CLKSOURCE_LSE /*!< LSE clock selected as USART2 clock*/ +/** + * @} + */ + +/** @defgroup RCCEx_I2S2_Clock_Source I2S Clock Source + * @{ + */ +#define RCC_I2S2CLKSOURCE_PLL LL_RCC_I2S2_CLKSOURCE_PLL /*!< PLL "Q" clock selected as I2S2 clock source */ +#define RCC_I2S2CLKSOURCE_HSI LL_RCC_I2S2_CLKSOURCE_HSI /*!< HSI clock selected as I2S2 clock */ +#define RCC_I2S2CLKSOURCE_PIN LL_RCC_I2S2_CLKSOURCE_PIN /*!< External clock selected as I2S2 clock */ +/** + * @} + */ + +/** @defgroup RCCEx_LPUART1_Clock_Source LPUART1 Clock Source + * @{ + */ +#define RCC_LPUART1CLKSOURCE_PCLK1 LL_RCC_LPUART1_CLKSOURCE_PCLK1 /*!< APB1 clock selected as LPUART1 clock*/ +#define RCC_LPUART1CLKSOURCE_SYSCLK LL_RCC_LPUART1_CLKSOURCE_SYSCLK /*!< SYSCLK clock selected as LPUART1 clock*/ +#define RCC_LPUART1CLKSOURCE_HSI LL_RCC_LPUART1_CLKSOURCE_HSI /*!< HSI clock selected as LPUART1 clock*/ +#define RCC_LPUART1CLKSOURCE_LSE LL_RCC_LPUART1_CLKSOURCE_LSE /*!< LSE clock selected as LPUART1 clock*/ +/** + * @} + */ + +/** @defgroup RCCEx_I2C1_Clock_Source I2C1 Clock Source + * @{ + */ +#define RCC_I2C1CLKSOURCE_PCLK1 LL_RCC_I2C1_CLKSOURCE_PCLK1 /*!< APB1 clock selected as I2C1 clock */ +#define RCC_I2C1CLKSOURCE_SYSCLK LL_RCC_I2C1_CLKSOURCE_SYSCLK /*!< SYSCLK clock selected as I2C1 clock */ +#define RCC_I2C1CLKSOURCE_HSI LL_RCC_I2C1_CLKSOURCE_HSI /*!< HSI clock selected as I2C1 clock */ +/** + * @} + */ + +/** @defgroup RCCEx_I2C2_Clock_Source I2C2 Clock Source + * @{ + */ +#define RCC_I2C2CLKSOURCE_PCLK1 LL_RCC_I2C2_CLKSOURCE_PCLK1 /*!< APB1 clock selected as I2C2 clock */ +#define RCC_I2C2CLKSOURCE_SYSCLK LL_RCC_I2C2_CLKSOURCE_SYSCLK /*!< SYSCLK clock selected as I2C2 clock */ +#define RCC_I2C2CLKSOURCE_HSI LL_RCC_I2C2_CLKSOURCE_HSI /*!< HSI clock selected as I2C2 clock */ +/** + * @} + */ + +/** @defgroup RCCEx_I2C3_Clock_Source I2C3 Clock Source + * @{ + */ +#define RCC_I2C3CLKSOURCE_PCLK1 LL_RCC_I2C3_CLKSOURCE_PCLK1 /*!< APB1 clock selected as I2C3 clock */ +#define RCC_I2C3CLKSOURCE_SYSCLK LL_RCC_I2C3_CLKSOURCE_SYSCLK /*!< SYSCLK clock selected as I2C3 clock */ +#define RCC_I2C3CLKSOURCE_HSI LL_RCC_I2C3_CLKSOURCE_HSI /*!< HSI clock selected as I2C3 clock */ +/** + * @} + */ + +/** @defgroup RCCEx_LPTIM1_Clock_Source LPTIM1 Clock Source + * @{ + */ +#define RCC_LPTIM1CLKSOURCE_PCLK1 LL_RCC_LPTIM1_CLKSOURCE_PCLK1 /*!< APB1 clock selected as LPTIM1 clock */ +#define RCC_LPTIM1CLKSOURCE_LSI LL_RCC_LPTIM1_CLKSOURCE_LSI /*!< LSI clock selected as LPTIM1 clock */ +#define RCC_LPTIM1CLKSOURCE_HSI LL_RCC_LPTIM1_CLKSOURCE_HSI /*!< HSI clock selected as LPTIM1 clock */ +#define RCC_LPTIM1CLKSOURCE_LSE LL_RCC_LPTIM1_CLKSOURCE_LSE /*!< LSE clock selected as LPTIM1 clock */ +/** + * @} + */ + +/** @defgroup RCCEx_LPTIM2_Clock_Source LPTIM2 Clock Source + * @{ + */ +#define RCC_LPTIM2CLKSOURCE_PCLK1 LL_RCC_LPTIM2_CLKSOURCE_PCLK1 /*!< APB1 clock selected as LPTIM2 clock */ +#define RCC_LPTIM2CLKSOURCE_LSI LL_RCC_LPTIM2_CLKSOURCE_LSI /*!< LSI clock selected as LPTIM2 clock */ +#define RCC_LPTIM2CLKSOURCE_HSI LL_RCC_LPTIM2_CLKSOURCE_HSI /*!< HSI clock selected as LPTIM2 clock */ +#define RCC_LPTIM2CLKSOURCE_LSE LL_RCC_LPTIM2_CLKSOURCE_LSE /*!< LSE clock selected as LPTIM2 clock */ +/** + * @} + */ + +/** @defgroup RCCEx_LPTIM3_Clock_Source LPTIM3 Clock Source + * @{ + */ +#define RCC_LPTIM3CLKSOURCE_PCLK1 LL_RCC_LPTIM3_CLKSOURCE_PCLK1 /*!< APB1 clock selected as LPTIM3 clock */ +#define RCC_LPTIM3CLKSOURCE_LSI LL_RCC_LPTIM3_CLKSOURCE_LSI /*!< LSI clock selected as LPTIM3 clock */ +#define RCC_LPTIM3CLKSOURCE_HSI LL_RCC_LPTIM3_CLKSOURCE_HSI /*!< HSI clock selected as LPTIM3 clock */ +#define RCC_LPTIM3CLKSOURCE_LSE LL_RCC_LPTIM3_CLKSOURCE_LSE /*!< LSE clock selected as LPTIM3 clock */ +/** + * @} + */ + +/** @defgroup RCCEx_RNG_Clock_Source RNG Clock Source + * @{ + */ +#define RCC_RNGCLKSOURCE_PLL LL_RCC_RNG_CLKSOURCE_PLL /*!< PLL "Q" clock selected as RNG clock */ +#define RCC_RNGCLKSOURCE_LSI LL_RCC_RNG_CLKSOURCE_LSI /*!< LSI clock selected as RNG clock */ +#define RCC_RNGCLKSOURCE_LSE LL_RCC_RNG_CLKSOURCE_LSE /*!< LSE clock selected as RNG clock */ +#define RCC_RNGCLKSOURCE_MSI LL_RCC_RNG_CLKSOURCE_MSI /*!< MSI clock selected as RNG clock */ +/** + * @} + */ + +/** @defgroup RCCEx_ADC_Clock_Source ADC Clock Source + * @{ + */ +#define RCC_ADCCLKSOURCE_NONE LL_RCC_ADC_CLKSOURCE_NONE /*!< None clock selected as ADC clock */ +#define RCC_ADCCLKSOURCE_HSI LL_RCC_ADC_CLKSOURCE_HSI /*!< HSI clock selected as ADC clock */ +#define RCC_ADCCLKSOURCE_PLL LL_RCC_ADC_CLKSOURCE_PLL /*!< PLL "P" clock selected as ADC clock */ +#define RCC_ADCCLKSOURCE_SYSCLK LL_RCC_ADC_CLKSOURCE_SYSCLK /*!< SYSCLK clock selected as ADC clock */ +/** + * @} + */ + +/** @defgroup RCCEx_EXTI_LINE_LSECSS RCC LSE CSS external interrupt line + * @{ + */ +#define RCC_EXTI_LINE_LSECSS EXTI_IMR1_IM19 /*!< External interrupt line 18 connected to the LSE CSS EXTI Line */ +/** + * @} + */ + +/** @defgroup RCCEx_EXTI_LINE_HSECSS RCC HSE CSS external interrupt line + * @{ + */ +#define RCC_EXTI_LINE_HSECSS EXTI_IMR2_IM43 /*!< External interrupt line 43 connected to the HSE CSS EXTI Line */ +/** + * @} + */ + + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros + * @{ + */ + +/*============================================================================*/ + +/** @brief Macro to configure the USART1 clock (USART1CLK). + * @param __USART1_CLKSOURCE__ specifies the USART1 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock + * @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock + * @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock + * @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock + * @retval None + */ +#define __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) LL_RCC_SetUSARTClockSource(__USART1_CLKSOURCE__) + +/** @brief Macro to get the USART1 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock + * @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock + * @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock + * @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock + */ +#define __HAL_RCC_GET_USART1_SOURCE() LL_RCC_GetUSARTClockSource(LL_RCC_USART1_CLKSOURCE) + +/** @brief Macro to configure the USART2 clock (USART2CLK). + * @param __USART2_CLKSOURCE__ specifies the USART2 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock + * @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock + * @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock + * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock + * @retval None + */ +#define __HAL_RCC_USART2_CONFIG(__USART2_CLKSOURCE__) LL_RCC_SetUSARTClockSource(__USART2_CLKSOURCE__) + +/** @brief Macro to get the USART2 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock + * @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock + * @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock + * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock + */ +#define __HAL_RCC_GET_USART2_SOURCE() LL_RCC_GetUSARTClockSource(LL_RCC_USART2_CLKSOURCE) + +/** @brief Macro to configure the I2S2 clock (I2S2CLK). + * @param __I2S2_CLKSOURCE__ specifies the I2S2 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_I2S2CLKSOURCE_PLL PLL "Q" selected as I2S2 clock + * @arg @ref RCC_I2S2CLKSOURCE_HSI HSI selected as I2S2 clock + * @arg @ref RCC_I2S2CLKSOURCE_PIN External clock selected as I2S2 clock + * @retval None + */ +#define __HAL_RCC_I2S2_CONFIG(__I2S2_CLKSOURCE__) LL_RCC_SetI2SClockSource(__I2S2_CLKSOURCE__) + +/** @brief Macro to get the I2S2 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_I2S2CLKSOURCE_PLL PLL "Q" selected as I2S2 clock + * @arg @ref RCC_I2S2CLKSOURCE_HSI HSI selected as I2S2 clock + * @arg @ref RCC_I2S2CLKSOURCE_PIN External clock selected as I2S2 clock + */ +#define __HAL_RCC_GET_I2S2_SOURCE() LL_RCC_GetI2SClockSource(LL_RCC_I2S2_CLKSOURCE) + +/** @brief Macro to configure the LPUART clock (LPUART1CLK). + * @param __LPUART1_CLKSOURCE__ specifies the LPUART1 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_LPUART1CLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock + * @arg @ref RCC_LPUART1CLKSOURCE_HSI HSI selected as LPUART1 clock + * @arg @ref RCC_LPUART1CLKSOURCE_SYSCLK System Clock selected as LPUART1 clock + * @arg @ref RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock + * @retval None + */ +#define __HAL_RCC_LPUART1_CONFIG(__LPUART1_CLKSOURCE__) LL_RCC_SetLPUARTClockSource(__LPUART1_CLKSOURCE__) + +/** @brief Macro to get the LPUART1 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_LPUART1CLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock + * @arg @ref RCC_LPUART1CLKSOURCE_HSI HSI selected as LPUART1 clock + * @arg @ref RCC_LPUART1CLKSOURCE_SYSCLK System Clock selected as LPUART1 clock + * @arg @ref RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock + */ +#define __HAL_RCC_GET_LPUART1_SOURCE() LL_RCC_GetLPUARTClockSource(LL_RCC_LPUART1_CLKSOURCE) + +/** @brief Macro to configure the I2C1 clock (I2C1CLK). + * @param __I2C1_CLKSOURCE__ specifies the I2C1 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_I2C1CLKSOURCE_PCLK1 PCLK1 selected as I2C1 clock + * @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock + * @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock + * @retval None + */ +#define __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) LL_RCC_SetI2CClockSource(__I2C1_CLKSOURCE__) + +/** @brief Macro to get the I2C1 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_I2C1CLKSOURCE_PCLK1 PCLK1 selected as I2C1 clock + * @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock + * @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock + */ +#define __HAL_RCC_GET_I2C1_SOURCE() LL_RCC_GetI2CClockSource(LL_RCC_I2C1_CLKSOURCE) + +/** @brief Macro to configure the I2C2 clock (I2C2CLK). + * @param __I2C2_CLKSOURCE__ specifies the I2C2 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_I2C2CLKSOURCE_PCLK1 PCLK1 selected as I2C2 clock + * @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock + * @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock + * @retval None + */ +#define __HAL_RCC_I2C2_CONFIG(__I2C2_CLKSOURCE__) LL_RCC_SetI2CClockSource(__I2C2_CLKSOURCE__) + +/** @brief Macro to get the I2C2 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_I2C2CLKSOURCE_PCLK1 PCLK1 selected as I2C2 clock + * @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock + * @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock + */ +#define __HAL_RCC_GET_I2C2_SOURCE() LL_RCC_GetI2CClockSource(LL_RCC_I2C2_CLKSOURCE) + +/** @brief Macro to configure the I2C3 clock (I2C3CLK). + * @param __I2C3_CLKSOURCE__ specifies the I2C3 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_I2C3CLKSOURCE_PCLK1 PCLK1 selected as I2C3 clock + * @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock + * @arg @ref RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock + * @retval None + */ +#define __HAL_RCC_I2C3_CONFIG(__I2C3_CLKSOURCE__) LL_RCC_SetI2CClockSource(__I2C3_CLKSOURCE__) + +/** @brief Macro to get the I2C3 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_I2C3CLKSOURCE_PCLK1 PCLK1 selected as I2C3 clock + * @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock + * @arg @ref RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock + */ +#define __HAL_RCC_GET_I2C3_SOURCE() LL_RCC_GetI2CClockSource(LL_RCC_I2C3_CLKSOURCE) + +/** @brief Macro to configure the LPTIM1 clock (LPTIM1CLK). + * @param __LPTIM1_CLKSOURCE__ specifies the LPTIM1 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_LPTIM1CLKSOURCE_PCLK1 PCLK selected as LPTIM1 clock + * @arg @ref RCC_LPTIM1CLKSOURCE_LSI HSI selected as LPTIM1 clock + * @arg @ref RCC_LPTIM1CLKSOURCE_HSI LSI selected as LPTIM1 clock + * @arg @ref RCC_LPTIM1CLKSOURCE_LSE LSE selected as LPTIM1 clock + * @retval None + */ +#define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) LL_RCC_SetLPTIMClockSource(__LPTIM1_CLKSOURCE__) + +/** @brief Macro to get the LPTIM1 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_LPTIM1CLKSOURCE_PCLK1 PCLK selected as LPTIM1 clock + * @arg @ref RCC_LPTIM1CLKSOURCE_LSI HSI selected as LPTIM1 clock + * @arg @ref RCC_LPTIM1CLKSOURCE_HSI System Clock selected as LPTIM1 clock + * @arg @ref RCC_LPTIM1CLKSOURCE_LSE LSE selected as LPTIM1 clock + */ +#define __HAL_RCC_GET_LPTIM1_SOURCE() LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM1_CLKSOURCE) + +/** @brief Macro to configure the LPTIM2 clock (LPTIM2CLK). + * @param __LPTIM2_CLKSOURCE__ specifies the LPTIM2 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_LPTIM2CLKSOURCE_PCLK1 PCLK selected as LPTIM2 clock + * @arg @ref RCC_LPTIM2CLKSOURCE_LSI HSI selected as LPTIM2 clock + * @arg @ref RCC_LPTIM2CLKSOURCE_HSI LSI selected as LPTIM2 clock + * @arg @ref RCC_LPTIM2CLKSOURCE_LSE LSE selected as LPTIM2 clock + * @retval None + */ +#define __HAL_RCC_LPTIM2_CONFIG(__LPTIM2_CLKSOURCE__) LL_RCC_SetLPTIMClockSource(__LPTIM2_CLKSOURCE__) + +/** @brief Macro to get the LPTIM2 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_LPTIM2CLKSOURCE_PCLK1 PCLK selected as LPTIM2 clock + * @arg @ref RCC_LPTIM2CLKSOURCE_LSI HSI selected as LPTIM2 clock + * @arg @ref RCC_LPTIM2CLKSOURCE_HSI System Clock selected as LPTIM2 clock + * @arg @ref RCC_LPTIM2CLKSOURCE_LSE LSE selected as LPTIM2 clock + */ +#define __HAL_RCC_GET_LPTIM2_SOURCE() LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM2_CLKSOURCE) + +/** @brief Macro to configure the LPTIM3 clock (LPTIM3CLK). + * @param __LPTIM3_CLKSOURCE__ specifies the LPTIM3 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_LPTIM3CLKSOURCE_PCLK1 PCLK selected as LPTIM3 clock + * @arg @ref RCC_LPTIM3CLKSOURCE_LSI HSI selected as LPTIM3 clock + * @arg @ref RCC_LPTIM3CLKSOURCE_HSI LSI selected as LPTIM3 clock + * @arg @ref RCC_LPTIM3CLKSOURCE_LSE LSE selected as LPTIM3 clock + * @retval None + */ +#define __HAL_RCC_LPTIM3_CONFIG(__LPTIM3_CLKSOURCE__) LL_RCC_SetLPTIMClockSource(__LPTIM3_CLKSOURCE__) + +/** @brief Macro to get the LPTIM3 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_LPTIM3CLKSOURCE_PCLK1 PCLK selected as LPTIM3 clock + * @arg @ref RCC_LPTIM3CLKSOURCE_LSI HSI selected as LPTIM3 clock + * @arg @ref RCC_LPTIM3CLKSOURCE_HSI System Clock selected as LPTIM3 clock + * @arg @ref RCC_LPTIM3CLKSOURCE_LSE LSE selected as LPTIM3 clock + */ +#define __HAL_RCC_GET_LPTIM3_SOURCE() LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM3_CLKSOURCE) + +/** @brief Macro to configure the RNG clock. + * @param __RNG_CLKSOURCE__ specifies the RNG clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_RNGCLKSOURCE_PLL PLL "Q" Clock selected as RNG clock + * @arg @ref RCC_RNGCLKSOURCE_LSI LSI selected as RNG clock + * @arg @ref RCC_RNGCLKSOURCE_LSE LSE selected as RNG clock + * @arg @ref RCC_RNGCLKSOURCE_MSI MSI selected as RNG clock + * @retval None + */ +#define __HAL_RCC_RNG_CONFIG(__RNG_CLKSOURCE__) LL_RCC_SetRNGClockSource(__RNG_CLKSOURCE__) + +/** @brief Macro to get the RNG clock. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_RNGCLKSOURCE_PLL PLL "Q" Clock selected as RNG clock + * @arg @ref RCC_RNGCLKSOURCE_LSI LSI selected as RNG clock + * @arg @ref RCC_RNGCLKSOURCE_LSE LSE selected as RNG clock + * @arg @ref RCC_RNGCLKSOURCE_MSI MSI selected as RNG clock + */ +#define __HAL_RCC_GET_RNG_SOURCE() LL_RCC_GetRNGClockSource(LL_RCC_RNG_CLKSOURCE) + +/** @brief Macro to configure the ADC interface clock. + * @param __ADC_CLKSOURCE__ specifies the ADC digital interface clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_ADCCLKSOURCE_NONE No clock selected as ADC clock + * @arg @ref RCC_ADCCLKSOURCE_HSI HSI Clock selected as ADC clock + * @arg @ref RCC_ADCCLKSOURCE_PLL PLL "P" Clock selected as ADC clock + * @arg @ref RCC_ADCCLKSOURCE_SYSCLK System Clock selected as ADC clock + * @retval None + */ +#define __HAL_RCC_ADC_CONFIG(__ADC_CLKSOURCE__) LL_RCC_SetADCClockSource(__ADC_CLKSOURCE__) + +/** @brief Macro to get the ADC clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_ADCCLKSOURCE_NONE No clock selected as ADC clock + * @arg @ref RCC_ADCCLKSOURCE_HSI HSI Clock selected as ADC clock + * @arg @ref RCC_ADCCLKSOURCE_PLL PLL "P" Clock selected as ADC clock + * @arg @ref RCC_ADCCLKSOURCE_SYSCLK System Clock selected as ADC clock + */ +#define __HAL_RCC_GET_ADC_SOURCE() LL_RCC_GetADCClockSource(LL_RCC_ADC_CLKSOURCE) + + +#if defined(DUAL_CORE) + +#if defined(CORE_CM0PLUS) +#define __HAL_RCC_LSECSS_EXTI_ENABLE_IT() LL_C2_EXTI_EnableIT_0_31(RCC_EXTI_LINE_LSECSS) +#define __HAL_RCC_LSECSS_EXTI_DISABLE_IT() LL_C2_EXTI_DisableIT_0_31(RCC_EXTI_LINE_LSECSS) +#define __HAL_RCC_LSECSS_EXTI_ENABLE_EVENT() LL_C2_EXTI_EnableEvent_0_31(RCC_EXTI_LINE_LSECSS) +#define __HAL_RCC_LSECSS_EXTI_DISABLE_EVENT() LL_C2_EXTI_DisableEvent_0_31(RCC_EXTI_LINE_LSECSS) + +#define __HAL_RCC_HSECSS_EXTI_ENABLE_IT() LL_C2_EXTI_EnableIT_32_63(RCC_EXTI_LINE_HSECSS) +#define __HAL_RCC_HSECSS_EXTI_DISABLE_IT() LL_C2_EXTI_DisableIT_32_63(RCC_EXTI_LINE_HSECSS) +#else +#define __HAL_RCC_LSECSS_EXTI_ENABLE_IT() LL_EXTI_EnableIT_0_31(RCC_EXTI_LINE_LSECSS) +#define __HAL_RCC_LSECSS_EXTI_DISABLE_IT() LL_EXTI_DisableIT_0_31(RCC_EXTI_LINE_LSECSS) +#define __HAL_RCC_LSECSS_EXTI_ENABLE_EVENT() LL_EXTI_EnableEvent_0_31(RCC_EXTI_LINE_LSECSS) +#define __HAL_RCC_LSECSS_EXTI_DISABLE_EVENT() LL_EXTI_DisableEvent_0_31(RCC_EXTI_LINE_LSECSS) + +#define __HAL_RCC_HSECSS_EXTI_ENABLE_IT() LL_EXTI_EnableIT_32_63(RCC_EXTI_LINE_HSECSS) +#define __HAL_RCC_HSECSS_EXTI_DISABLE_IT() LL_EXTI_DisableIT_32_63(RCC_EXTI_LINE_HSECSS) +#endif /* CORE_CM0PLUS */ + +#else + +#define __HAL_RCC_LSECSS_EXTI_ENABLE_IT() LL_EXTI_EnableIT_0_31(RCC_EXTI_LINE_LSECSS) +#define __HAL_RCC_LSECSS_EXTI_DISABLE_IT() LL_EXTI_DisableIT_0_31(RCC_EXTI_LINE_LSECSS) +#define __HAL_RCC_LSECSS_EXTI_ENABLE_EVENT() LL_EXTI_EnableEvent_0_31(RCC_EXTI_LINE_LSECSS) +#define __HAL_RCC_LSECSS_EXTI_DISABLE_EVENT() LL_EXTI_DisableEvent_0_31(RCC_EXTI_LINE_LSECSS) + +#define __HAL_RCC_HSECSS_EXTI_ENABLE_IT() LL_EXTI_EnableIT_32_63(RCC_EXTI_LINE_HSECSS) +#define __HAL_RCC_HSECSS_EXTI_DISABLE_IT() LL_EXTI_DisableIT_32_63(RCC_EXTI_LINE_HSECSS) + +#endif /* DUAL_CORE */ + +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup RCCEx_Exported_Functions + * @{ + */ + +/** @addtogroup RCCEx_Exported_Functions_Group1 + * @{ + */ + +HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); +void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); +uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk); + +/** + * @} + */ + +/** @addtogroup RCCEx_Exported_Functions_Group2 + * @{ + */ + +void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk); + +void HAL_RCCEx_EnableLSECSS(void); +void HAL_RCCEx_DisableLSECSS(void); +void HAL_RCCEx_EnableLSECSS_IT(void); +void HAL_RCCEx_LSECSS_IRQHandler(void); +void HAL_RCCEx_LSECSS_Callback(void); + +void HAL_RCCEx_EnableLSCO(uint32_t LSCOSource); +void HAL_RCCEx_DisableLSCO(void); + +void HAL_RCCEx_EnableMSIPLLMode(void); +void HAL_RCCEx_DisableMSIPLLMode(void); + + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32WLxx_HAL_RCC_EX_H */ diff --git a/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h b/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h new file mode 100644 index 0000000..5305f08 --- /dev/null +++ b/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h @@ -0,0 +1,976 @@ +/** + ****************************************************************************** + * @file stm32wlxx_hal_rtc.h + * @author MCD Application Team + * @brief Header file of RTC HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32WLxx_HAL_RTC_H +#define STM32WLxx_HAL_RTC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wlxx_hal_def.h" + +/** @addtogroup STM32WLxx_HAL_Driver + * @{ + */ + +/** @defgroup RTC RTC + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup RTC_Exported_Types RTC Exported Types + * @{ + */ + +/** + * @brief HAL State structures definition + */ +typedef enum +{ + HAL_RTC_STATE_RESET = 0x00U, /*!< RTC not yet initialized or disabled */ + HAL_RTC_STATE_READY = 0x01U, /*!< RTC initialized and ready for use */ + HAL_RTC_STATE_BUSY = 0x02U, /*!< RTC process is ongoing */ + HAL_RTC_STATE_TIMEOUT = 0x03U, /*!< RTC timeout state */ + HAL_RTC_STATE_ERROR = 0x04U /*!< RTC error state */ + +} HAL_RTCStateTypeDef; + +/** + * @brief RTC Configuration Structure definition + */ +typedef struct +{ + uint32_t HourFormat; /*!< Specifies the RTC Hour Format. + This parameter can be a value of @ref RTC_Hour_Formats */ + + uint32_t AsynchPrediv; /*!< Specifies the RTC Asynchronous Predivider value. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F */ + + uint32_t SynchPrediv; /*!< Specifies the RTC Synchronous Predivider value. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FFF */ + + uint32_t OutPut; /*!< Specifies which signal will be routed to the RTC output. + This parameter can be a value of @ref RTCEx_Output_selection_Definitions */ + + uint32_t OutPutRemap; /*!< Specifies the remap for RTC output. + This parameter can be a value of @ref RTC_Output_ALARM_OUT_Remap */ + + uint32_t OutPutPolarity; /*!< Specifies the polarity of the output signal. + This parameter can be a value of @ref RTC_Output_Polarity_Definitions */ + + uint32_t OutPutType; /*!< Specifies the RTC Output Pin mode. + This parameter can be a value of @ref RTC_Output_Type_ALARM_OUT */ + + uint32_t OutPutPullUp; /*!< Specifies the RTC Output Pull-Up mode. + This parameter can be a value of @ref RTC_Output_PullUp_ALARM_OUT */ + + uint32_t BinMode; /*!< Specifies the RTC binary mode. + This parameter can be a value of @ref RTCEx_Binary_Mode */ + + uint32_t BinMixBcdU; /*!< Specifies the BCD calendar update if and only if BinMode = RTC_BINARY_MIX. + This parameter can be a value of @ref RTCEx_Binary_mix_BCDU */ +} RTC_InitTypeDef; + + +/** + * @brief RTC Enabled features Structure definition + */ +typedef struct +{ + uint32_t RtcFeatures; + uint32_t TampFeatures; +} RTC_IsEnabledTypeDef; + + +/** + * @brief RTC Time structure definition + */ +typedef struct +{ + uint8_t Hours; /*!< Specifies the RTC Time Hour. + This parameter must be a number between Min_Data = 0 and Max_Data = 12 if the RTC_HourFormat_12 is selected. + This parameter must be a number between Min_Data = 0 and Max_Data = 23 if the RTC_HourFormat_24 is selected */ + + uint8_t Minutes; /*!< Specifies the RTC Time Minutes. + This parameter must be a number between Min_Data = 0 and Max_Data = 59 */ + + uint8_t Seconds; /*!< Specifies the RTC Time Seconds. + This parameter must be a number between Min_Data = 0 and Max_Data = 59 */ + + uint8_t TimeFormat; /*!< Specifies the RTC AM/PM Time. + This parameter can be a value of @ref RTC_AM_PM_Definitions */ + + uint32_t SubSeconds; /*!< Specifies the RTC_SSR RTC Sub Second register content. + This field is not used by HAL_RTC_SetTime. + If the free running 32 bit counter is not activated (mode binary none) + - This parameter corresponds to a time unit range between [0-1] Second with [1 Sec / SecondFraction +1] granularity + else + - This parameter corresponds to the free running 32 bit counter. */ + + uint32_t SecondFraction; /*!< Specifies the range or granularity of Sub Second register content + corresponding to Synchronous pre-scaler factor value (PREDIV_S) + This parameter corresponds to a time unit range between [0-1] Second + with [1 Sec / SecondFraction +1] granularity. + This field will be used only by HAL_RTC_GetTime function */ + + uint32_t DayLightSaving; /*!< This interface is deprecated. To manage Daylight Saving Time, please use HAL_RTC_DST_xxx functions */ + + uint32_t StoreOperation; /*!< This interface is deprecated. To manage Daylight Saving Time, please use HAL_RTC_DST_xxx functions */ +} RTC_TimeTypeDef; + +/** + * @brief RTC Date structure definition + */ +typedef struct +{ + uint8_t WeekDay; /*!< Specifies the RTC Date WeekDay. + This parameter can be a value of @ref RTC_WeekDay_Definitions */ + + uint8_t Month; /*!< Specifies the RTC Date Month (in BCD format). + This parameter can be a value of @ref RTC_Month_Date_Definitions */ + + uint8_t Date; /*!< Specifies the RTC Date. + This parameter must be a number between Min_Data = 1 and Max_Data = 31 */ + + uint8_t Year; /*!< Specifies the RTC Date Year. + This parameter must be a number between Min_Data = 0 and Max_Data = 99 */ + +} RTC_DateTypeDef; + +/** + * @brief RTC Alarm structure definition + */ +typedef struct +{ + RTC_TimeTypeDef AlarmTime; /*!< Specifies the RTC Alarm Time members */ + + uint32_t AlarmMask; /*!< Specifies the RTC Alarm Masks. + This parameter can be a value of @ref RTC_AlarmMask_Definitions */ + + uint32_t AlarmSubSecondMask; /*!< Specifies the RTC Alarm SubSeconds Masks. + if Binary mode is RTC_BINARY_ONLY or is RTC_BINARY_MIX + This parameter can be a value of @ref RTCEx_Alarm_Sub_Seconds_binary_Masks_Definitions + else if Binary mode is RTC_BINARY_NONE + This parameter can be a value of @ref RTC_Alarm_Sub_Seconds_Masks_Definitions */ + + uint32_t BinaryAutoClr; /*!< Clear synchronously counter (RTC_SSR) on binary alarm. + RTC_ALARMSUBSECONDBIN_AUTOCLR_YES must only be used if Binary mode is RTC_BINARY_ONLY + This parameter can be a value of @ref RTCEx_Alarm_Sub_Seconds_binary_Clear_Definitions */ + + uint32_t AlarmDateWeekDaySel; /*!< Specifies the RTC Alarm is on Date or WeekDay. + This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */ + + uint8_t AlarmDateWeekDay; /*!< Specifies the RTC Alarm Date/WeekDay. + If the Alarm Date is selected, this parameter must be set to a value in the 1-31 range. + If the Alarm WeekDay is selected, this parameter can be a value of @ref RTC_WeekDay_Definitions */ + + uint32_t Alarm; /*!< Specifies the alarm . + This parameter can be a value of @ref RTC_Alarms_Definitions */ +} RTC_AlarmTypeDef; + +/** + * @brief RTC Handle Structure definition + */ +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) +typedef struct __RTC_HandleTypeDef +#else +typedef struct +#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */ +{ + RTC_TypeDef *Instance; /*!< Legacy register base address. Not used anymore, the driver directly uses cmsis base address */ + + RTC_InitTypeDef Init; /*!< RTC required parameters */ + + HAL_LockTypeDef Lock; /*!< RTC locking object */ + + __IO HAL_RTCStateTypeDef State; /*!< Time communication state */ + + RTC_IsEnabledTypeDef IsEnabled; /*!< Flag to avoid treatment of the interrupts activated by the other core */ + +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + void (* AlarmAEventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Alarm A Event callback */ + void (* AlarmBEventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Alarm B Event callback */ + void (* TimeStampEventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC TimeStamp Event callback */ + void (* WakeUpTimerEventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC WakeUpTimer Event callback */ + void (* SSRUEventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC SSRU Event callback */ + void (* Tamper1EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Tamper 1 Event callback */ + void (* Tamper2EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Tamper 2 Event callback */ + void (* Tamper3EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Tamper 3 Event callback */ + void (* InternalTamper3EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Internal Tamper 3 Event callback */ + void (* InternalTamper5EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Internal Tamper 5 Event callback */ + void (* InternalTamper6EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Internal Tamper 6 Event callback */ + void (* InternalTamper8EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Internal Tamper 8 Event callback */ + void (* MspInitCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Msp Init callback */ + void (* MspDeInitCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Msp DeInit callback */ + +#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */ + +} RTC_HandleTypeDef; + +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) +/** + * @brief HAL RTC Callback ID enumeration definition + */ +typedef enum +{ + HAL_RTC_ALARM_A_EVENT_CB_ID = 0u, /*!< RTC Alarm A Event Callback ID */ + HAL_RTC_ALARM_B_EVENT_CB_ID = 1u, /*!< RTC Alarm B Event Callback ID */ + HAL_RTC_TIMESTAMP_EVENT_CB_ID = 2u, /*!< RTC TimeStamp Event Callback ID */ + HAL_RTC_WAKEUPTIMER_EVENT_CB_ID = 3u, /*!< RTC WakeUp Timer Event Callback ID */ + HAL_RTC_SSRU_EVENT_CB_ID = 4u, /*!< RTC SSR Underflow Event Callback ID */ + HAL_RTC_TAMPER1_EVENT_CB_ID = 5u, /*!< RTC Tamper 1 Callback ID */ + HAL_RTC_TAMPER2_EVENT_CB_ID = 6u, /*!< RTC Tamper 2 Callback ID */ + HAL_RTC_TAMPER3_EVENT_CB_ID = 7u, /*!< RTC Tamper 3 Callback ID */ + HAL_RTC_INTERNAL_TAMPER3_EVENT_CB_ID = 8u, /*!< RTC Internal Tamper 3 Callback ID */ + HAL_RTC_INTERNAL_TAMPER5_EVENT_CB_ID = 9u, /*!< RTC Internal Tamper 5 Callback ID */ + HAL_RTC_INTERNAL_TAMPER6_EVENT_CB_ID = 10u, /*!< RTC Internal Tamper 6 Callback ID */ + HAL_RTC_INTERNAL_TAMPER8_EVENT_CB_ID = 11u, /*!< RTC Internal Tamper 8 Callback ID */ + HAL_RTC_MSPINIT_CB_ID = 12u, /*!< RTC Msp Init callback ID */ + HAL_RTC_MSPDEINIT_CB_ID = 13u /*!< RTC Msp DeInit callback ID */ +} HAL_RTC_CallbackIDTypeDef; + +/** + * @brief HAL RTC Callback pointer definition + */ +typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to an RTC callback function */ +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup RTC_Exported_Constants RTC Exported Constants + * @{ + */ + +/** @defgroup RTC_Hour_Formats RTC Hour Formats + * @{ + */ +#define RTC_HOURFORMAT_24 0x00000000u +#define RTC_HOURFORMAT_12 RTC_CR_FMT +/** + * @} + */ + +/** @defgroup RTCEx_Output_selection_Definitions RTCEx Output Selection Definition + * @{ + */ +#define RTC_OUTPUT_DISABLE 0x00000000u +#define RTC_OUTPUT_ALARMA RTC_CR_OSEL_0 +#define RTC_OUTPUT_ALARMB RTC_CR_OSEL_1 +#define RTC_OUTPUT_WAKEUP RTC_CR_OSEL +#define RTC_OUTPUT_TAMPER RTC_CR_TAMPOE +/** + * @} + */ + + +/** @defgroup RTC_Output_Polarity_Definitions RTC Output Polarity Definitions + * @{ + */ +#define RTC_OUTPUT_POLARITY_HIGH 0x00000000u +#define RTC_OUTPUT_POLARITY_LOW RTC_CR_POL +/** + * @} + */ + +/** @defgroup RTC_Output_Type_ALARM_OUT RTC Output Type ALARM OUT + * @{ + */ +#define RTC_OUTPUT_TYPE_PUSHPULL 0x00000000u +#define RTC_OUTPUT_TYPE_OPENDRAIN RTC_CR_TAMPALRM_TYPE +/** + * @} + */ + +/** @defgroup RTC_Output_PullUp_ALARM_OUT RTC Output Pull-Up ALARM OUT + * @{ + */ +#define RTC_OUTPUT_PULLUP_NONE 0x00000000u +#define RTC_OUTPUT_PULLUP_ON RTC_CR_TAMPALRM_PU +/** + * @} + */ + +/** @defgroup RTC_Output_ALARM_OUT_Remap RTC Output ALARM OUT Remap + * @{ + */ +#define RTC_OUTPUT_REMAP_NONE 0x00000000u +#define RTC_OUTPUT_REMAP_POS1 RTC_CR_OUT2EN +/** + * @} + */ + +/** @defgroup RTC_AM_PM_Definitions RTC AM PM Definitions + * @{ + */ +#define RTC_HOURFORMAT12_AM 0x0u +#define RTC_HOURFORMAT12_PM 0x1u +/** + * @} + */ + +/** @defgroup RTC_DayLightSaving_Definitions RTC DayLightSaving Definitions + * @{ + */ +#define RTC_DAYLIGHTSAVING_SUB1H RTC_CR_SUB1H +#define RTC_DAYLIGHTSAVING_ADD1H RTC_CR_ADD1H +#define RTC_DAYLIGHTSAVING_NONE 0x00000000u +/** + * @} + */ + +/** @defgroup RTC_StoreOperation_Definitions RTC StoreOperation Definitions + * @{ + */ +#define RTC_STOREOPERATION_RESET 0x00000000u +#define RTC_STOREOPERATION_SET RTC_CR_BKP +/** + * @} + */ + +/** @defgroup RTC_Input_parameter_format_definitions RTC input or output data format for date (Year, Month, Weekday) and time (Hours, Minutes, Seconds). + * Warning : It Should not be confused with the Binary mode @ref RTCEx_Binary_Mode. + * @{ + */ +#define RTC_FORMAT_BIN 0x00000000u /* This parameter will trigger a SW conversion to fit with the native BCD format of the HW Calendar. + It should not be confused with the Binary mode @ref RTCEx_Binary_Mode. */ + +#define RTC_FORMAT_BCD 0x00000001u /* Native format of the HW Calendar. + It should not be confused with the Binary mode @ref RTCEx_Binary_Mode. */ +/** + * @} + */ + +/** @defgroup RTC_Month_Date_Definitions RTC Month Date Definitions + * @{ + */ + +/* Coded in BCD format */ +#define RTC_MONTH_JANUARY ((uint8_t)0x01U) +#define RTC_MONTH_FEBRUARY ((uint8_t)0x02U) +#define RTC_MONTH_MARCH ((uint8_t)0x03U) +#define RTC_MONTH_APRIL ((uint8_t)0x04U) +#define RTC_MONTH_MAY ((uint8_t)0x05U) +#define RTC_MONTH_JUNE ((uint8_t)0x06U) +#define RTC_MONTH_JULY ((uint8_t)0x07U) +#define RTC_MONTH_AUGUST ((uint8_t)0x08U) +#define RTC_MONTH_SEPTEMBER ((uint8_t)0x09U) +#define RTC_MONTH_OCTOBER ((uint8_t)0x10U) +#define RTC_MONTH_NOVEMBER ((uint8_t)0x11U) +#define RTC_MONTH_DECEMBER ((uint8_t)0x12U) + +/** + * @} + */ + +/** @defgroup RTC_WeekDay_Definitions RTC WeekDay Definitions + * @{ + */ +#define RTC_WEEKDAY_MONDAY ((uint8_t)0x01U) +#define RTC_WEEKDAY_TUESDAY ((uint8_t)0x02U) +#define RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03U) +#define RTC_WEEKDAY_THURSDAY ((uint8_t)0x04U) +#define RTC_WEEKDAY_FRIDAY ((uint8_t)0x05U) +#define RTC_WEEKDAY_SATURDAY ((uint8_t)0x06U) +#define RTC_WEEKDAY_SUNDAY ((uint8_t)0x07U) + +/** + * @} + */ + +/** @defgroup RTC_AlarmDateWeekDay_Definitions RTC AlarmDateWeekDay Definitions + * @{ + */ +#define RTC_ALARMDATEWEEKDAYSEL_DATE 0x00000000u +#define RTC_ALARMDATEWEEKDAYSEL_WEEKDAY RTC_ALRMAR_WDSEL + +/** + * @} + */ + +/** @defgroup RTC_AlarmMask_Definitions RTC AlarmMask Definitions + * @{ + */ +#define RTC_ALARMMASK_NONE 0x00000000u +#define RTC_ALARMMASK_DATEWEEKDAY RTC_ALRMAR_MSK4 +#define RTC_ALARMMASK_HOURS RTC_ALRMAR_MSK3 +#define RTC_ALARMMASK_MINUTES RTC_ALRMAR_MSK2 +#define RTC_ALARMMASK_SECONDS RTC_ALRMAR_MSK1 +#define RTC_ALARMMASK_ALL (RTC_ALARMMASK_DATEWEEKDAY | RTC_ALARMMASK_HOURS | \ + RTC_ALARMMASK_MINUTES | RTC_ALARMMASK_SECONDS) + +/** + * @} + */ + +/** @defgroup RTC_Alarms_Definitions RTC Alarms Definitions + * @{ + */ +#define RTC_ALARM_A RTC_CR_ALRAE +#define RTC_ALARM_B RTC_CR_ALRBE + +/** + * @} + */ + + +/** @defgroup RTC_Alarm_Sub_Seconds_Masks_Definitions RTC Alarm Sub Seconds Masks Definitions + * @{ + */ +#define RTC_ALARMSUBSECONDMASK_ALL 0x00000000u /*!< All Alarm SS fields are masked. + There is no comparison on sub seconds + for Alarm */ +#define RTC_ALARMSUBSECONDMASK_SS14_1 RTC_ALRMASSR_MASKSS_0 /*!< SS[14:1] not used in Alarm + comparison. Only SS[0] is compared. */ +#define RTC_ALARMSUBSECONDMASK_SS14_2 RTC_ALRMASSR_MASKSS_1 /*!< SS[14:2] not used in Alarm + comparison. Only SS[1:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14_3 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1) /*!< SS[14:3] not used in Alarm + comparison. Only SS[2:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14_4 RTC_ALRMASSR_MASKSS_2 /*!< SS[14:4] not used in Alarm + comparison. Only SS[3:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14_5 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_2) /*!< SS[14:5] not used in Alarm + comparison. Only SS[4:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14_6 (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2) /*!< SS[14:6] not used in Alarm + comparison. Only SS[5:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14_7 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2) /*!< SS[14:7] not used in Alarm + comparison. Only SS[6:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14_8 RTC_ALRMASSR_MASKSS_3 /*!< SS[14:8] not used in Alarm + comparison. Only SS[7:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14_9 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_3) /*!< SS[14:9] not used in Alarm + comparison. Only SS[8:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14_10 (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_3) /*!< SS[14:10] not used in Alarm + comparison. Only SS[9:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14_11 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_3) /*!< SS[14:11] not used in Alarm + comparison. Only SS[10:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14_12 (RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3) /*!< SS[14:12] not used in Alarm + comparison.Only SS[11:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14_13 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3) /*!< SS[14:13] not used in Alarm + comparison. Only SS[12:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14 (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3) /*!< SS[14] not used in Alarm + comparison. Only SS[13:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_NONE RTC_ALRMASSR_MASKSS /*!< SS[14:0] are compared and must match + to activate alarm. */ +/** + * @} + */ + +/** @defgroup RTC_Interrupts_Definitions RTC Interrupts Definitions + * @{ + */ +#define RTC_IT_TS RTC_CR_TSIE /*!< Enable Timestamp Interrupt */ +#define RTC_IT_WUT RTC_CR_WUTIE /*!< Enable Wakeup timer Interrupt */ +#define RTC_IT_SSRU RTC_CR_SSRUIE /*!< Enable SSR Underflow Interrupt */ +#define RTC_IT_ALRA RTC_CR_ALRAIE /*!< Enable Alarm A Interrupt */ +#define RTC_IT_ALRB RTC_CR_ALRBIE /*!< Enable Alarm B Interrupt */ +/** + * @} + */ + +/** @defgroup RTC_Flag_Mask RTC Flag Mask (5bits) describe in RTC_Flags_Definitions + * @{ + */ +#define RTC_FLAG_MASK 0x001Fu /*!< RTC flags mask (5bits) */ +/** + * @} + */ + +/** @defgroup RTC_Flags_Definitions RTC Flags Definitions + * Elements values convention: 000000XX000YYYYYb + * - YYYYY : Interrupt flag position in the XX register (5bits) + * - XX : Interrupt status register (2bits) + * - 01: ICSR register + * - 10: SR or SCR or MISR or SMISR registers + * @{ + */ +#define RTC_FLAG_RECALPF (0x00000100U | RTC_ICSR_RECALPF_Pos) /*!< Recalibration pending Flag */ +#define RTC_FLAG_INITF (0x00000100U | RTC_ICSR_INITF_Pos) /*!< Initialization flag */ +#define RTC_FLAG_RSF (0x00000100U | RTC_ICSR_RSF_Pos) /*!< Registers synchronization flag */ +#define RTC_FLAG_INITS (0x00000100U | RTC_ICSR_INITS_Pos) /*!< Initialization status flag */ +#define RTC_FLAG_SHPF (0x00000100U | RTC_ICSR_SHPF_Pos) /*!< Shift operation pending flag */ +#define RTC_FLAG_WUTWF (0x00000100U | RTC_ICSR_WUTWF_Pos) /*!< Wakeup timer write flag */ +#define RTC_FLAG_SSRUF (0x00000200U | RTC_SR_SSRUF_Pos) /*!< SSR underflow flag */ +#define RTC_FLAG_ITSF (0x00000200U | RTC_SR_ITSF_Pos) /*!< Internal Time-stamp flag */ +#define RTC_FLAG_TSOVF (0x00000200U | RTC_SR_TSOVF_Pos) /*!< Time-stamp overflow flag */ +#define RTC_FLAG_TSF (0x00000200U | RTC_SR_TSF_Pos) /*!< Time-stamp flag */ +#define RTC_FLAG_WUTF (0x00000200U | RTC_SR_WUTF_Pos) /*!< Wakeup timer flag */ +#define RTC_FLAG_ALRBF (0x00000200U | RTC_SR_ALRBF_Pos) /*!< Alarm B flag */ +#define RTC_FLAG_ALRAF (0x00000200U | RTC_SR_ALRAF_Pos) /*!< Alarm A flag */ +/** + * @} + */ + +/** @defgroup RTC_Clear_Flags_Definitions RTC Clear Flags Definitions + * @{ + */ +#define RTC_CLEAR_SSRUF RTC_SCR_CSSRUF /*!< Clear SSR underflow flag */ +#define RTC_CLEAR_ITSF RTC_SCR_CITSF /*!< Clear Internal Time-stamp flag */ +#define RTC_CLEAR_TSOVF RTC_SCR_CTSOVF /*!< Clear Time-stamp overflow flag */ +#define RTC_CLEAR_TSF RTC_SCR_CTSF /*!< Clear Time-stamp flag */ +#define RTC_CLEAR_WUTF RTC_SCR_CWUTF /*!< Clear Wakeup timer flag */ +#define RTC_CLEAR_ALRBF RTC_SCR_CALRBF /*!< Clear Alarm B flag */ +#define RTC_CLEAR_ALRAF RTC_SCR_CALRAF /*!< Clear Alarm A flag */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup RTC_Exported_Macros RTC Exported Macros + * @{ + */ + +/** @brief Reset RTC handle state + * @param __HANDLE__ RTC handle. + * @retval None + */ +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) +#define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) do{\ + (__HANDLE__)->State = HAL_RTC_STATE_RESET;\ + (__HANDLE__)->MspInitCallback = NULL;\ + (__HANDLE__)->MspDeInitCallback = NULL;\ + }while(0) +#else +#define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RTC_STATE_RESET) +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ + +/** + * @brief Disable the write protection for RTC registers. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__) \ + do{ \ + UNUSED(__HANDLE__); \ + RTC->WPR = 0xCAU; \ + RTC->WPR = 0x53U; \ + } while(0U) + +/** + * @brief Enable the write protection for RTC registers. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__) \ + do{ \ + UNUSED(__HANDLE__); \ + RTC->WPR = 0xFFU; \ + } while(0U) + +/** + * @brief Add 1 hour (summer time change). + * @note This interface is deprecated. + * To manage Daylight Saving Time, please use HAL_RTC_DST_xxx functions + * @param __HANDLE__ specifies the RTC handle. + * @param __BKP__ Backup + * This parameter can be: + * @arg @ref RTC_STOREOPERATION_RESET + * @arg @ref RTC_STOREOPERATION_SET + * @retval None + */ +#define __HAL_RTC_DAYLIGHT_SAVING_TIME_ADD1H(__HANDLE__, __BKP__) \ + do { \ + __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__); \ + SET_BIT(RTC->CR, RTC_CR_ADD1H); \ + MODIFY_REG(RTC->CR, RTC_CR_BKP , (__BKP__)); \ + __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__); \ + } while(0U); + +/** + * @brief Subtract 1 hour (winter time change). + * @note This interface is deprecated. + * To manage Daylight Saving Time, please use HAL_RTC_DST_xxx functions + * @param __HANDLE__ specifies the RTC handle. + * @param __BKP__ Backup + * This parameter can be: + * @arg @ref RTC_STOREOPERATION_RESET + * @arg @ref RTC_STOREOPERATION_SET + * @retval None + */ +#define __HAL_RTC_DAYLIGHT_SAVING_TIME_SUB1H(__HANDLE__, __BKP__) \ + do { \ + __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__); \ + SET_BIT(RTC->CR, RTC_CR_SUB1H); \ + MODIFY_REG(RTC->CR, RTC_CR_BKP , (__BKP__)); \ + __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__); \ + } while(0U); + +/** + * @brief Enable the RTC ALARMA peripheral. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_ALARMA_ENABLE(__HANDLE__) (UNUSED(__HANDLE__), (RTC->CR |= (RTC_CR_ALRAE))) + +/** + * @brief Disable the RTC ALARMA peripheral. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_ALARMA_DISABLE(__HANDLE__) (UNUSED(__HANDLE__), (RTC->CR &= ~(RTC_CR_ALRAE))) + +/** + * @brief Enable the RTC ALARMB peripheral. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_ALARMB_ENABLE(__HANDLE__) (UNUSED(__HANDLE__), (RTC->CR |= (RTC_CR_ALRBE))) + +/** + * @brief Disable the RTC ALARMB peripheral. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_ALARMB_DISABLE(__HANDLE__) (UNUSED(__HANDLE__), (RTC->CR &= ~(RTC_CR_ALRBE))) + +/** + * @brief Enable the RTC Alarm interrupt. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC Alarm interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg @ref RTC_IT_ALRA Alarm A interrupt + * @arg @ref RTC_IT_ALRB Alarm B interrupt + * @retval None + */ +#define __HAL_RTC_ALARM_ENABLE_IT(__HANDLE__, __INTERRUPT__) (UNUSED(__HANDLE__), (RTC->CR |= (__INTERRUPT__))) + +/** + * @brief Disable the RTC Alarm interrupt. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC Alarm interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg @ref RTC_IT_ALRA Alarm A interrupt + * @arg @ref RTC_IT_ALRB Alarm B interrupt + * @retval None + */ +#define __HAL_RTC_ALARM_DISABLE_IT(__HANDLE__, __INTERRUPT__) (UNUSED(__HANDLE__), (RTC->CR &= ~(__INTERRUPT__))) + +/** + * @brief Check whether the specified RTC Alarm interrupt has occurred or not. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC Alarm interrupt sources to check. + * This parameter can be: + * @arg @ref RTC_IT_ALRA Alarm A interrupt + * @arg @ref RTC_IT_ALRB Alarm B interrupt + * @retval None + */ +#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__) (UNUSED(__HANDLE__), ((((RTC->MISR) & ((__INTERRUPT__)>> 12U)) != 0U) ? 1UL : 0UL)) + +/** + * @brief Check whether the specified RTC Alarm interrupt has been enabled or not. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC Alarm interrupt sources to check. + * This parameter can be: + * @arg @ref RTC_IT_ALRA Alarm A interrupt + * @arg @ref RTC_IT_ALRB Alarm B interrupt + * @retval None + */ +#define __HAL_RTC_ALARM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (UNUSED(__HANDLE__), ((((RTC->CR) & (__INTERRUPT__)) != 0U) ? 1UL : 0UL)) + +/** + * @brief Get the selected RTC Alarms flag status. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC Alarm Flag sources to check. + * This parameter can be: + * @arg @ref RTC_FLAG_ALRAF + * @arg @ref RTC_FLAG_ALRBF + * @retval None + */ +#define __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__) (UNUSED(__HANDLE__), (__HAL_RTC_GET_FLAG((__HANDLE__), (__FLAG__)))) + +/** + * @brief Clear the RTC Alarms pending flags. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC Alarm Flag sources to clear. + * This parameter can be: + * @arg @ref RTC_FLAG_ALRAF + * @arg @ref RTC_FLAG_ALRBF + * @retval None + */ +#define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__) (UNUSED(__HANDLE__), \ + (((__FLAG__) == RTC_FLAG_ALRAF) ? (RTC->SCR = (RTC_CLEAR_ALRAF)) : \ + (RTC->SCR = (RTC_CLEAR_ALRBF)))) +/** + * @brief Check whether the RTC Calendar is initialized. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_IS_CALENDAR_INITIALIZED(__HANDLE__) ((((RTC->ICSR) & (RTC_ICSR_INITS)) == RTC_ICSR_INITS) ? 1U : 0U) + +/** + * @brief Get Binary mode + * @param __HANDLE__ specifies the RTC handle. + * @retval Selected Binary mode (RTC_BINARY_NONE, RTC_BINARY_ONLY, or RTC_BINARY_MIX) + */ +#define __HAL_RTC_GET_BINARY_MODE(__HANDLE__) (READ_REG(RTC->ICSR & RTC_ICSR_BIN)) + +#if defined(CORE_CM0PLUS) +#define __HAL_RTC_ALARM_EXTI_ENABLE_IT() (EXTI->C2IMR1 |= RTC_EXTI_LINE_ALARM_EVENT) +#define __HAL_RTC_ALARM_EXTI_DISABLE_IT() (EXTI->C2IMR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT)) +#define __HAL_RTC_ALARM_EXTI_ENABLE_EVENT() (EXTI->C2EMR1 |= RTC_EXTI_LINE_ALARM_EVENT) +#define __HAL_RTC_ALARM_EXTI_DISABLE_EVENT() (EXTI->C2EMR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT)) +#else +#define __HAL_RTC_ALARM_EXTI_ENABLE_IT() (EXTI->IMR1 |= RTC_EXTI_LINE_ALARM_EVENT) +#define __HAL_RTC_ALARM_EXTI_DISABLE_IT() (EXTI->IMR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT)) +#define __HAL_RTC_ALARM_EXTI_ENABLE_EVENT() (EXTI->EMR1 |= RTC_EXTI_LINE_ALARM_EVENT) +#define __HAL_RTC_ALARM_EXTI_DISABLE_EVENT() (EXTI->EMR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT)) +#endif /* CORE_CM0PLUS */ + + +/** + * @} + */ + +/* Include RTC HAL Extended module */ +#include "stm32wlxx_hal_rtc_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup RTC_Exported_Functions RTC Exported Functions + * @{ + */ + +/** @defgroup RTC_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ +/* Initialization and de-initialization functions ****************************/ +HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc); +HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc); + +void HAL_RTC_MspInit(RTC_HandleTypeDef *hrtc); +void HAL_RTC_MspDeInit(RTC_HandleTypeDef *hrtc); + +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_RTC_RegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID, + pRTC_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_RTC_UnRegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup RTC_Exported_Functions_Group2 RTC Time and Date functions + * @{ + */ +/* RTC Time and Date functions ************************************************/ +HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format); +HAL_StatusTypeDef HAL_RTC_GetTime(const RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format); +HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format); +HAL_StatusTypeDef HAL_RTC_GetDate(const RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format); +void HAL_RTC_DST_Add1Hour(const RTC_HandleTypeDef *hrtc); +void HAL_RTC_DST_Sub1Hour(const RTC_HandleTypeDef *hrtc); +void HAL_RTC_DST_SetStoreOperation(const RTC_HandleTypeDef *hrtc); +void HAL_RTC_DST_ClearStoreOperation(const RTC_HandleTypeDef *hrtc); +uint32_t HAL_RTC_DST_ReadStoreOperation(const RTC_HandleTypeDef *hrtc); +/** + * @} + */ + +/** @defgroup RTC_Exported_Functions_Group3 RTC Alarm functions + * @{ + */ +/* RTC Alarm functions ********************************************************/ +HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format); +HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format); +HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm); +HAL_StatusTypeDef HAL_RTC_GetAlarm(const RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format); +void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc); +HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout); +void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc); +/** + * @} + */ + +/** @defgroup RTC_Exported_Functions_Group4 Peripheral Control functions + * @{ + */ +/* Peripheral Control functions ***********************************************/ +HAL_StatusTypeDef HAL_RTC_WaitForSynchro(const RTC_HandleTypeDef *hrtc); +/** + * @} + */ + +/** @defgroup RTC_Exported_Functions_Group5 Peripheral State functions + * @{ + */ +/* Peripheral State functions *************************************************/ +HAL_RTCStateTypeDef HAL_RTC_GetState(const RTC_HandleTypeDef *hrtc); +/** + * @} + */ + +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup RTC_Private_Constants RTC Private Constants + * @{ + */ +/* Masks Definition */ +#define RTC_TR_RESERVED_MASK (RTC_TR_PM | RTC_TR_HT | RTC_TR_HU | \ + RTC_TR_MNT | RTC_TR_MNU| RTC_TR_ST | \ + RTC_TR_SU) +#define RTC_DR_RESERVED_MASK (RTC_DR_YT | RTC_DR_YU | RTC_DR_WDU | \ + RTC_DR_MT | RTC_DR_MU | RTC_DR_DT | \ + RTC_DR_DU) +#define RTC_INIT_MASK 0xFFFFFFFFu +#define RTC_RSF_MASK (~(RTC_ICSR_INIT | RTC_ICSR_RSF)) + +#define RTC_TIMEOUT_VALUE 1000u + +#define RTC_EXTI_LINE_ALARM_EVENT EXTI_IMR1_IM17 /*!< External interrupt line 17 Connected to the RTC Alarm event */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup RTC_Private_Macros RTC Private Macros + * @{ + */ + +/** @defgroup RTC_IS_RTC_Definitions RTC Private macros to check input parameters + * @{ + */ +#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_OUTPUT_DISABLE) || \ + ((OUTPUT) == RTC_OUTPUT_ALARMA) || \ + ((OUTPUT) == RTC_OUTPUT_ALARMB) || \ + ((OUTPUT) == RTC_OUTPUT_WAKEUP) || \ + ((OUTPUT) == RTC_OUTPUT_TAMPER)) + +#define IS_RTC_HOUR_FORMAT(FORMAT) (((FORMAT) == RTC_HOURFORMAT_12) || \ + ((FORMAT) == RTC_HOURFORMAT_24)) + +#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OUTPUT_POLARITY_HIGH) || \ + ((POL) == RTC_OUTPUT_POLARITY_LOW)) + +#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OUTPUT_TYPE_OPENDRAIN) || \ + ((TYPE) == RTC_OUTPUT_TYPE_PUSHPULL)) + +#define IS_RTC_OUTPUT_PULLUP(TYPE) (((TYPE) == RTC_OUTPUT_PULLUP_NONE) || \ + ((TYPE) == RTC_OUTPUT_PULLUP_ON)) + +#define IS_RTC_OUTPUT_REMAP(REMAP) (((REMAP) == RTC_OUTPUT_REMAP_NONE) || \ + ((REMAP) == RTC_OUTPUT_REMAP_POS1)) + +#define IS_RTC_HOURFORMAT12(PM) (((PM) == RTC_HOURFORMAT12_AM) || \ + ((PM) == RTC_HOURFORMAT12_PM)) + +#define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DAYLIGHTSAVING_SUB1H) || \ + ((SAVE) == RTC_DAYLIGHTSAVING_ADD1H) || \ + ((SAVE) == RTC_DAYLIGHTSAVING_NONE)) + +#define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_STOREOPERATION_RESET) || \ + ((OPERATION) == RTC_STOREOPERATION_SET)) + +#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_FORMAT_BIN) || \ + ((FORMAT) == RTC_FORMAT_BCD)) + +#define IS_RTC_YEAR(YEAR) ((YEAR) <= 99u) + +#define IS_RTC_MONTH(MONTH) (((MONTH) >= 1u) && ((MONTH) <= 12u)) + +#define IS_RTC_DATE(DATE) (((DATE) >= 1u) && ((DATE) <= 31u)) + +#define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || \ + ((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || \ + ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \ + ((WEEKDAY) == RTC_WEEKDAY_THURSDAY) || \ + ((WEEKDAY) == RTC_WEEKDAY_FRIDAY) || \ + ((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || \ + ((WEEKDAY) == RTC_WEEKDAY_SUNDAY)) + +#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) >0u) && ((DATE) <= 31u)) + +#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || \ + ((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || \ + ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \ + ((WEEKDAY) == RTC_WEEKDAY_THURSDAY) || \ + ((WEEKDAY) == RTC_WEEKDAY_FRIDAY) || \ + ((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || \ + ((WEEKDAY) == RTC_WEEKDAY_SUNDAY)) + +#define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_ALARMDATEWEEKDAYSEL_DATE) || \ + ((SEL) == RTC_ALARMDATEWEEKDAYSEL_WEEKDAY)) + +#define IS_RTC_ALARM_MASK(MASK) (((MASK) & ~(RTC_ALARMMASK_ALL)) == 0UL) + +#define IS_RTC_ALARM(ALARM) (((ALARM) == RTC_ALARM_A) || \ + ((ALARM) == RTC_ALARM_B)) + +#define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= RTC_ALRMASSR_SS) + +#define IS_RTC_ALARM_SUB_SECOND_MASK(MASK) (((MASK) == 0UL) || \ + (((MASK) >= RTC_ALARMSUBSECONDMASK_SS14_1) && ((MASK) <= RTC_ALARMSUBSECONDMASK_NONE))) + +#define IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= (RTC_PRER_PREDIV_A >> RTC_PRER_PREDIV_A_Pos)) + +#define IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= (RTC_PRER_PREDIV_S >> RTC_PRER_PREDIV_S_Pos)) + +#define IS_RTC_HOUR12(HOUR) (((HOUR) > 0u) && ((HOUR) <= 12u)) + +#define IS_RTC_HOUR24(HOUR) ((HOUR) <= 23u) + +#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= 59u) + +#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= 59u) + +/** + * @} + */ + +/** + * @} + */ + +/* Private functions -------------------------------------------------------------*/ +/** @defgroup RTC_Private_Functions RTC Private Functions + * @{ + */ +HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef *hrtc); +HAL_StatusTypeDef RTC_ExitInitMode(RTC_HandleTypeDef *hrtc); +uint8_t RTC_ByteToBcd2(uint8_t Value); +uint8_t RTC_Bcd2ToByte(uint8_t Value); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32WLxx_HAL_RTC_H */ diff --git a/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h b/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h new file mode 100644 index 0000000..d8eb6ef --- /dev/null +++ b/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h @@ -0,0 +1,1384 @@ +/** + ****************************************************************************** + * @file stm32wlxx_hal_rtc_ex.h + * @author MCD Application Team + * @brief Header file of RTC HAL Extended module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32WLxx_HAL_RTC_EX_H +#define STM32WLxx_HAL_RTC_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wlxx_hal_def.h" + +/** @addtogroup STM32WLxx_HAL_Driver + * @{ + */ + +/** @defgroup RTCEx RTCEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup RTCEx_Exported_Types RTCEx Exported Types + * @{ + */ + +/** @defgroup RTCEx_Tamper_structure_definition RTCEx Tamper structure definition + * @{ + */ +typedef struct +{ + uint32_t Tamper; /*!< Specifies the Tamper Pin. + This parameter can be a value of @ref RTCEx_Tamper_Pins */ + + uint32_t Trigger; /*!< Specifies the Tamper Trigger. + This parameter can be a value of @ref RTCEx_Tamper_Trigger */ + + uint32_t NoErase; /*!< Specifies the Tamper no erase mode. + This parameter can be a value of @ref RTCEx_Tamper_EraseBackUp */ + + uint32_t MaskFlag; /*!< Specifies the Tamper Flag masking. + This parameter can be a value of @ref RTCEx_Tamper_MaskFlag */ + + uint32_t Filter; /*!< Specifies the TAMP Filter Tamper. + This parameter can be a value of @ref RTCEx_Tamper_Filter */ + + uint32_t SamplingFrequency; /*!< Specifies the sampling frequency. + This parameter can be a value of @ref RTCEx_Tamper_Sampling_Frequencies */ + + uint32_t PrechargeDuration; /*!< Specifies the Precharge Duration . + This parameter can be a value of @ref RTCEx_Tamper_Pin_Precharge_Duration */ + + uint32_t TamperPullUp; /*!< Specifies the Tamper PullUp . + This parameter can be a value of @ref RTCEx_Tamper_Pull_UP */ + + uint32_t TimeStampOnTamperDetection; /*!< Specifies the TimeStampOnTamperDetection. + This parameter can be a value of @ref RTCEx_Tamper_TimeStampOnTamperDetection */ +} RTC_TamperTypeDef; +/** + * @} + */ + +/** @defgroup RTCEx_Internal_Tamper_structure_definition RTCEx Internal Tamper structure definition + * @{ + */ +typedef struct +{ + uint32_t IntTamper; /*!< Specifies the Internal Tamper Pin. + This parameter can be a value of @ref RTCEx_Internal_Tamper_Pins */ + + uint32_t TimeStampOnTamperDetection; /*!< Specifies the TimeStampOnTamperDetection. + This parameter can be a value of @ref RTCEx_Tamper_TimeStampOnTamperDetection */ + + uint32_t NoErase; /*!< Specifies the internal Tamper no erase mode. + This parameter can be a value of @ref RTCEx_Tamper_EraseBackUp */ +} RTC_InternalTamperTypeDef; +/** + * @} + */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup RTCEx_Exported_Constants RTCEx Exported Constants + * @{ + */ + +/** @defgroup RTCEx_Time_Stamp_Edges_definitions RTCEx Time Stamp Edges definition + * @{ + */ +#define RTC_TIMESTAMPEDGE_RISING 0x00000000u +#define RTC_TIMESTAMPEDGE_FALLING RTC_CR_TSEDGE +/** + * @} + */ + +/** @defgroup RTCEx_TimeStamp_Pin_Selections RTCEx TimeStamp Pin Selection + * @{ + */ +#define RTC_TIMESTAMPPIN_DEFAULT 0x00000000u +/** + * @} + */ + +/** @defgroup RTCEx_Wakeup_Timer_Definitions RTCEx Wakeup Timer Definitions + * @{ + */ +#define RTC_WAKEUPCLOCK_RTCCLK_DIV16 0x00000000u +#define RTC_WAKEUPCLOCK_RTCCLK_DIV8 RTC_CR_WUCKSEL_0 +#define RTC_WAKEUPCLOCK_RTCCLK_DIV4 RTC_CR_WUCKSEL_1 +#define RTC_WAKEUPCLOCK_RTCCLK_DIV2 (RTC_CR_WUCKSEL_0 | RTC_CR_WUCKSEL_1) +#define RTC_WAKEUPCLOCK_CK_SPRE_16BITS RTC_CR_WUCKSEL_2 +#define RTC_WAKEUPCLOCK_CK_SPRE_17BITS (RTC_CR_WUCKSEL_1 | RTC_CR_WUCKSEL_2) +/** + * @} + */ + +/** @defgroup RTCEx_Smooth_calib_period_Definitions RTCEx Smooth calib period Definitions + * @{ + */ +#define RTC_SMOOTHCALIB_PERIOD_32SEC 0x00000000u /*!< If RTCCLK = 32768 Hz, Smooth calibration + period is 32s, else 2exp20 RTCCLK pulses */ +#define RTC_SMOOTHCALIB_PERIOD_16SEC RTC_CALR_CALW16 /*!< If RTCCLK = 32768 Hz, Smooth calibration + period is 16s, else 2exp19 RTCCLK pulses */ +#define RTC_SMOOTHCALIB_PERIOD_8SEC RTC_CALR_CALW8 /*!< If RTCCLK = 32768 Hz, Smooth calibration + period is 8s, else 2exp18 RTCCLK pulses */ +/** + * @} + */ + +/** @defgroup RTCEx_Smooth_calib_Plus_pulses_Definitions RTCEx Smooth calib Plus pulses Definitions + * @{ + */ +#define RTC_SMOOTHCALIB_PLUSPULSES_SET RTC_CALR_CALP /*!< The number of RTCCLK pulses added + during a X -second window = Y - CALM[8:0] + with Y = 512, 256, 128 when X = 32, 16, 8 */ +#define RTC_SMOOTHCALIB_PLUSPULSES_RESET 0x00000000u /*!< The number of RTCCLK pulses subbstited + during a 32-second window = CALM[8:0] */ +/** + * @} + */ + +/** @defgroup RTCEx_Smooth_calib_low_power_Definitions RTCEx Smooth calib Low Power Definitions + * @{ + */ +#define RTC_LPCAL_SET RTC_CALR_LPCAL /*!< Calibration window is 220 ck_apre, + which is the required configuration for + ultra-low consumption mode. */ +#define RTC_LPCAL_RESET 0x00000000u /*!< Calibration window is 220 RTCCLK, + which is a high-consumption mode. + This mode should be set only when less + than 32s calibration window is required. */ +/** + * @} + */ + +/** @defgroup RTCEx_Calib_Output_selection_Definitions RTCEx Calib Output selection Definitions + * @{ + */ +#define RTC_CALIBOUTPUT_512HZ 0x00000000u +#define RTC_CALIBOUTPUT_1HZ RTC_CR_COSEL + +/** + * @} + */ + + +/** @defgroup RTCEx_Add_1_Second_Parameter_Definition RTCEx Add 1 Second Parameter Definitions + * @{ + */ +#define RTC_SHIFTADD1S_RESET 0x00000000u +#define RTC_SHIFTADD1S_SET RTC_SHIFTR_ADD1S +/** + * @} + */ + +/** @defgroup RTCEx_Tamper_Pins RTCEx Tamper Pins Definition + * @{ + */ +#define RTC_TAMPER_1 TAMP_CR1_TAMP1E +#define RTC_TAMPER_2 TAMP_CR1_TAMP2E +#define RTC_TAMPER_3 TAMP_CR1_TAMP3E +#define RTC_TAMPER_ALL (TAMP_CR1_TAMP1E | TAMP_CR1_TAMP2E | TAMP_CR1_TAMP3E) +/** + * @} + */ + +/** @defgroup RTCEx_Internal_Tamper_Pins RTCEx Internal Tamper Pins Definition + * @{ + */ +#define RTC_INT_TAMPER_3 TAMP_CR1_ITAMP3E +#define RTC_INT_TAMPER_5 TAMP_CR1_ITAMP5E +#define RTC_INT_TAMPER_6 TAMP_CR1_ITAMP6E +#define RTC_INT_TAMPER_8 TAMP_CR1_ITAMP8E +#define RTC_INT_TAMPER_ALL (TAMP_CR1_ITAMP3E | TAMP_CR1_ITAMP5E | TAMP_CR1_ITAMP6E | TAMP_CR1_ITAMP8E) +/** + * @} + */ + +/** @defgroup RTCEx_Tamper_Trigger RTCEx Tamper Trigger + * @{ + */ +#define RTC_TAMPERTRIGGER_RISINGEDGE 0x00u /*!< Warning : Filter must be RTC_TAMPERFILTER_DISABLE */ +#define RTC_TAMPERTRIGGER_FALLINGEDGE 0x01u /*!< Warning : Filter must be RTC_TAMPERFILTER_DISABLE */ +#define RTC_TAMPERTRIGGER_LOWLEVEL 0x02u /*!< Warning : Filter must not be RTC_TAMPERFILTER_DISABLE */ +#define RTC_TAMPERTRIGGER_HIGHLEVEL 0x03u /*!< Warning : Filter must not be RTC_TAMPERFILTER_DISABLE */ +/** + * @} + */ + +/** @defgroup RTCEx_Tamper_MaskFlag RTCEx Tamper MaskFlag + * @{ + */ +#define RTC_TAMPERMASK_FLAG_DISABLE 0x00u +#define RTC_TAMPERMASK_FLAG_ENABLE 0x01u +/** + * @} + */ + +/** @defgroup RTCEx_Tamper_EraseBackUp RTCEx Tamper EraseBackUp + * @{ + */ +#define RTC_TAMPER_ERASE_BACKUP_ENABLE 0x00u +#define RTC_TAMPER_ERASE_BACKUP_DISABLE 0x01u +/** + * @} + */ + +/** @defgroup RTCEx_Tamper_Filter RTCEx Tamper Filter + * @{ + */ +#define RTC_TAMPERFILTER_DISABLE 0x00000000U /*!< Tamper filter is disabled */ +#define RTC_TAMPERFILTER_2SAMPLE TAMP_FLTCR_TAMPFLT_0 /*!< Tamper is activated after 2 + consecutive samples at the active level */ +#define RTC_TAMPERFILTER_4SAMPLE TAMP_FLTCR_TAMPFLT_1 /*!< Tamper is activated after 4 + consecutive samples at the active level */ +#define RTC_TAMPERFILTER_8SAMPLE TAMP_FLTCR_TAMPFLT /*!< Tamper is activated after 8 + consecutive samples at the active level */ +/** + * @} + */ + +/** @defgroup RTCEx_Tamper_Sampling_Frequencies RTCEx Tamper Sampling Frequencies + * @{ + */ +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768 0x00000000U /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 32768 */ +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384 TAMP_FLTCR_TAMPFREQ_0 /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 16384 */ +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192 TAMP_FLTCR_TAMPFREQ_1 /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 8192 */ +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096 (TAMP_FLTCR_TAMPFREQ_0 | TAMP_FLTCR_TAMPFREQ_1) /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 4096 */ +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048 TAMP_FLTCR_TAMPFREQ_2 /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 2048 */ +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024 (TAMP_FLTCR_TAMPFREQ_0 | TAMP_FLTCR_TAMPFREQ_2) /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 1024 */ +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512 (TAMP_FLTCR_TAMPFREQ_1 | TAMP_FLTCR_TAMPFREQ_2) /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 512 */ +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256 (TAMP_FLTCR_TAMPFREQ_0 | TAMP_FLTCR_TAMPFREQ_1 | \ + TAMP_FLTCR_TAMPFREQ_2) /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 256 */ +/** + * @} + */ + +/** @defgroup RTCEx_Tamper_Pin_Precharge_Duration RTCEx Tamper Pin Precharge Duration + * @{ + */ +#define RTC_TAMPERPRECHARGEDURATION_1RTCCLK 0x00000000U /*!< Tamper pins are pre-charged before + sampling during 1 RTCCLK cycle */ +#define RTC_TAMPERPRECHARGEDURATION_2RTCCLK TAMP_FLTCR_TAMPPRCH_0 /*!< Tamper pins are pre-charged before + sampling during 2 RTCCLK cycles */ +#define RTC_TAMPERPRECHARGEDURATION_4RTCCLK TAMP_FLTCR_TAMPPRCH_1 /*!< Tamper pins are pre-charged before + sampling during 4 RTCCLK cycles */ +#define RTC_TAMPERPRECHARGEDURATION_8RTCCLK (TAMP_FLTCR_TAMPPRCH_0 | TAMP_FLTCR_TAMPPRCH_1) /*!< Tamper pins are pre-charged before + sampling during 8 RTCCLK cycles */ +/** + * @} + */ + +/** @defgroup RTCEx_Tamper_Pull_UP RTCEx Tamper Pull UP + * @{ + */ +#define RTC_TAMPER_PULLUP_ENABLE 0x00000000u /*!< Tamper pins are pre-charged before sampling */ +#define RTC_TAMPER_PULLUP_DISABLE TAMP_FLTCR_TAMPPUDIS /*!< Tamper pins pre-charge is disabled */ +/** + * @} + */ + +/** @defgroup RTCEx_Tamper_TimeStampOnTamperDetection RTCEx Tamper TimeStamp On Tamper Detection Definitions + * @{ + */ +#define RTC_TIMESTAMPONTAMPERDETECTION_DISABLE 0x00000000u /*!< TimeStamp on Tamper Detection event is not saved */ +#define RTC_TIMESTAMPONTAMPERDETECTION_ENABLE RTC_CR_TAMPTS /*!< TimeStamp on Tamper Detection event saved */ +/** + * @} + */ + +/** @defgroup RTCEx_Internal_Tamper_Interrupt RTCEx Internal Tamper Interrupt + * @{ + */ +#define RTC_IT_TAMP_1 TAMP_IER_TAMP1IE /*!< Tamper 1 Interrupt */ +#define RTC_IT_TAMP_2 TAMP_IER_TAMP2IE /*!< Tamper 2 Interrupt */ +#define RTC_IT_TAMP_3 TAMP_IER_TAMP3IE /*!< Tamper 3 Interrupt */ +#define RTC_IT_TAMP_ALL (TAMP_IER_TAMP1IE | TAMP_IER_TAMP2IE | TAMP_IER_TAMP3IE) + +#define RTC_IT_INT_TAMP_3 TAMP_IER_ITAMP3IE +#define RTC_IT_INT_TAMP_5 TAMP_IER_ITAMP5IE +#define RTC_IT_INT_TAMP_6 TAMP_IER_ITAMP6IE +#define RTC_IT_INT_TAMP_8 TAMP_IER_ITAMP8IE +#define RTC_IT_INT_TAMP_ALL (TAMP_IER_ITAMP3IE |\ + TAMP_IER_ITAMP5IE | TAMP_IER_ITAMP6IE | TAMP_IER_ITAMP8IE) +/** + * @} + */ + +/** @defgroup RTCEx_Flags RTCEx Flags + * @{ + */ +#define RTC_FLAG_TAMP_1 TAMP_SR_TAMP1F +#define RTC_FLAG_TAMP_2 TAMP_SR_TAMP2F +#define RTC_FLAG_TAMP_3 TAMP_SR_TAMP3F +#define RTC_FLAG_TAMP_ALL (RTC_FLAG_TAMP1 | RTC_FLAG_TAMP2 | RTC_FLAG_TAMP3 ) + + +#define RTC_FLAG_INT_TAMP_3 TAMP_SR_ITAMP3F +#define RTC_FLAG_INT_TAMP_5 TAMP_SR_ITAMP5F +#define RTC_FLAG_INT_TAMP_6 TAMP_SR_ITAMP6F +#define RTC_FLAG_INT_TAMP_8 TAMP_SR_ITAMP8F +#define RTC_FLAG_INT_TAMP_ALL (RTC_FLAG_INT_TAMP3 |\ + RTC_FLAG_INT_TAMP5 | RTC_FLAG_INT_TAMP6 | RTC_FLAG_INT_TAMP8) +/** + * @} + */ + + +/** @defgroup RTCEx_MonotonicCounter_Instance RTCEx Monotonic Counter Instance Definition + * @{ + */ +#define RTC_MONOTONIC_COUNTER_1 0u /*!< Monotonic counter 1 */ +/** + * @} + */ + + +/** @defgroup RTCEx_Backup_Registers RTCEx Backup Registers Definition + * @{ + */ +#define RTC_BKP_NUMBER RTC_BACKUP_NB +#define RTC_BKP_DR0 0x00u +#define RTC_BKP_DR1 0x01u +#define RTC_BKP_DR2 0x02u +#define RTC_BKP_DR3 0x03u +#define RTC_BKP_DR4 0x04u +#define RTC_BKP_DR5 0x05u +#define RTC_BKP_DR6 0x06u +#define RTC_BKP_DR7 0x07u +#define RTC_BKP_DR8 0x08u +#define RTC_BKP_DR9 0x09u +#define RTC_BKP_DR10 0x0Au +#define RTC_BKP_DR11 0x0Bu +#define RTC_BKP_DR12 0x0Cu +#define RTC_BKP_DR13 0x0Du +#define RTC_BKP_DR14 0x0Eu +#define RTC_BKP_DR15 0x0Fu +#define RTC_BKP_DR16 0x10u +#define RTC_BKP_DR17 0x11u +#define RTC_BKP_DR18 0x12u +#define RTC_BKP_DR19 0x13u +/** + * @} + */ + +/** @defgroup RTCEx_Binary_Mode RTC Binary Mode (32-bit free-running counter configuration). + * Warning : It Should not be confused with the Binary format @ref RTC_Input_parameter_format_definitions. + * @{ + */ +#define RTC_BINARY_NONE 0x00000000u /*!< Free running BCD calendar mode (Binary mode disabled). */ +#define RTC_BINARY_ONLY RTC_ICSR_BIN_0 /*!< Free running Binary mode (BCD mode disabled) */ +#define RTC_BINARY_MIX RTC_ICSR_BIN_1 /*!< Free running BCD calendar and Binary mode */ +/** + * @} + */ + +/** @defgroup RTCEx_Binary_mix_BCDU If Binary mode is RTC_BINARY_MIX, the BCD calendar second is incremented using the SSR Least Significant Bits. + * @{ + */ +#define RTC_BINARY_MIX_BCDU_0 0x00000000u /*!< The 1s BCD calendar increment is generated each time SS[7:0] = 0 */ +#define RTC_BINARY_MIX_BCDU_1 (0x1UL << RTC_ICSR_BCDU_Pos) /*!< The 1s BCD calendar increment is generated each time SS[8:0] = 0 */ +#define RTC_BINARY_MIX_BCDU_2 (0x2UL << RTC_ICSR_BCDU_Pos) /*!< The 1s BCD calendar increment is generated each time SS[9:0] = 0 */ +#define RTC_BINARY_MIX_BCDU_3 (0x3UL << RTC_ICSR_BCDU_Pos) /*!< The 1s BCD calendar increment is generated each time SS[10:0] = 0 */ +#define RTC_BINARY_MIX_BCDU_4 (0x4UL << RTC_ICSR_BCDU_Pos) /*!< The 1s BCD calendar increment is generated each time SS[11:0] = 0 */ +#define RTC_BINARY_MIX_BCDU_5 (0x5UL << RTC_ICSR_BCDU_Pos) /*!< The 1s BCD calendar increment is generated each time SS[12:0] = 0 */ +#define RTC_BINARY_MIX_BCDU_6 (0x6UL << RTC_ICSR_BCDU_Pos) /*!< The 1s BCD calendar increment is generated each time SS[13:0] = 0 */ +#define RTC_BINARY_MIX_BCDU_7 (0x7UL << RTC_ICSR_BCDU_Pos) /*!< The 1s BCD calendar increment is generated each time SS[14:0] = 0 */ +/** + * @} + */ + +/** @defgroup RTCEx_Alarm_Sub_Seconds_binary_Masks_Definitions RTC Alarm Sub Seconds with binary mode Masks Definitions + * @{ + */ +#define RTC_ALARMSUBSECONDBINMASK_ALL 0x00000000u /*!< All Alarm SS fields are masked. + There is no comparison on sub seconds for Alarm */ +#define RTC_ALARMSUBSECONDBINMASK_SS31_1 (1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:1] are don't care in Alarm + comparison. Only SS[0] is compared. */ +#define RTC_ALARMSUBSECONDBINMASK_SS31_2 (2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:2] are don't care in Alarm + comparison. Only SS[1:0] are compared */ +#define RTC_ALARMSUBSECONDBINMASK_SS31_3 (3UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:3] are don't care in Alarm + comparison. Only SS[2:0] are compared */ +#define RTC_ALARMSUBSECONDBINMASK_SS31_4 (4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:4] are don't care in Alarm + comparison. Only SS[3:0] are compared */ +#define RTC_ALARMSUBSECONDBINMASK_SS31_5 (5UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:5] are don't care in Alarm + comparison. Only SS[4:0] are compared */ +#define RTC_ALARMSUBSECONDBINMASK_SS31_6 (6UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:6] are don't care in Alarm + comparison. Only SS[5:0] are compared */ +#define RTC_ALARMSUBSECONDBINMASK_SS31_7 (7UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:7] are don't care in Alarm + comparison. Only SS[6:0] are compared */ +#define RTC_ALARMSUBSECONDBINMASK_SS31_8 (8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:8] are don't care in Alarm + comparison. Only SS[7:0] are compared */ +#define RTC_ALARMSUBSECONDBINMASK_SS31_9 (9UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:9] are don't care in Alarm + comparison. Only SS[8:0] are compared */ +#define RTC_ALARMSUBSECONDBINMASK_SS31_10 (10UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:10] are don't care in Alarm + comparison. Only SS[9:0] are compared */ +#define RTC_ALARMSUBSECONDBINMASK_SS31_11 (11UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:11] are don't care in Alarm + comparison. Only SS[10:0] are compared */ +#define RTC_ALARMSUBSECONDBINMASK_SS31_12 (12UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:12] are don't care in Alarm + comparison.Only SS[11:0] are compared */ +#define RTC_ALARMSUBSECONDBINMASK_SS31_13 (13UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:13] are don't care in Alarm + comparison. Only SS[12:0] are compared */ +#define RTC_ALARMSUBSECONDBINMASK_SS31_14 (14UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:14] are don't care in Alarm + comparison. Only SS[13:0] are compared */ +#define RTC_ALARMSUBSECONDBINMASK_SS31_15 (15UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:15] are don't care in Alarm + comparison. Only SS[14:0] are compared */ +#define RTC_ALARMSUBSECONDBINMASK_SS31_16 (16UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:16] are don't care in Alarm + comparison. Only SS[15:0] are compared */ +#define RTC_ALARMSUBSECONDBINMASK_SS31_17 (17UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:17] are don't care in Alarm + comparison. Only SS[16:0] are compared */ +#define RTC_ALARMSUBSECONDBINMASK_SS31_18 (18UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:18] are don't care in Alarm + comparison. Only SS[17:0] are compared */ +#define RTC_ALARMSUBSECONDBINMASK_SS31_19 (19UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:19] are don't care in Alarm + comparison. Only SS[18:0] are compared */ +#define RTC_ALARMSUBSECONDBINMASK_SS31_20 (20UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:20] are don't care in Alarm + comparison. Only SS[19:0] are compared */ +#define RTC_ALARMSUBSECONDBINMASK_SS31_21 (21UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:21] are don't care in Alarm + comparison. Only SS[20:0] are compared */ +#define RTC_ALARMSUBSECONDBINMASK_SS31_22 (22UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:22] are don't care in Alarm + comparison. Only SS[21:0] are compared */ +#define RTC_ALARMSUBSECONDBINMASK_SS31_23 (23UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:23] are don't care in Alarm + comparison. Only SS[22:0] are compared */ +#define RTC_ALARMSUBSECONDBINMASK_SS31_24 (24UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:24] are don't care in Alarm + comparison. Only SS[23:0] are compared */ +#define RTC_ALARMSUBSECONDBINMASK_SS31_25 (25UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:25] are don't care in Alarm + comparison. Only SS[24:0] are compared */ +#define RTC_ALARMSUBSECONDBINMASK_SS31_26 (26UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:26] are don't care in Alarm + comparison. Only SS[25:0] are compared */ +#define RTC_ALARMSUBSECONDBINMASK_SS31_27 (27UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:27] are don't care in Alarm + comparison. Only SS[26:0] are compared */ +#define RTC_ALARMSUBSECONDBINMASK_SS31_28 (28UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:28] are don't care in Alarm + comparison. Only SS[27:0] are compared */ +#define RTC_ALARMSUBSECONDBINMASK_SS31_29 (29UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:29] are don't care in Alarm + comparison. Only SS[28:0] are compared */ +#define RTC_ALARMSUBSECONDBINMASK_SS31_30 (30UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:30] are don't care in Alarm + comparison. Only SS[29:0] are compared */ +#define RTC_ALARMSUBSECONDBINMASK_SS31 (31UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31] is don't care in Alarm + comparison. Only SS[30:0] are compared */ +#define RTC_ALARMSUBSECONDBINMASK_NONE (32UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:0] are compared and must match to activate alarm. */ +/** + * @} + */ + +/** @defgroup RTCEx_Alarm_Sub_Seconds_binary_Clear_Definitions RTC Alarm Sub Seconds with binary mode auto clear Definitions + * @{ + */ +#define RTC_ALARMSUBSECONDBIN_AUTOCLR_NO 0UL /*!< The synchronous Binary counter (SS[31:0] in RTC_SSR) is free-running. */ +#define RTC_ALARMSUBSECONDBIN_AUTOCLR_YES RTC_ALRMASSR_SSCLR /*!< The synchronous Binary counter (SS[31:0] in RTC_SSR) is running from 0xFFFF FFFF to + RTC_ALRMABINR -> SS[31:0] value and is automatically reloaded with 0xFFFF FFFF + whenreaching RTC_ALRMABINR -> SS[31:0]. */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup RTCEx_Exported_Macros RTCEx Exported Macros + * @{ + */ + +/** @brief Clear the specified RTC pending flag. + * @param __HANDLE__ specifies the RTC Handle. + * @param __FLAG__ specifies the flag to check. + * This parameter can be any combination of the following values: + * @arg @ref RTC_CLEAR_ITSF Clear Internal Time-stamp flag + * @arg @ref RTC_CLEAR_TSOVF Clear Time-stamp overflow flag + * @arg @ref RTC_CLEAR_TSF Clear Time-stamp flag + * @arg @ref RTC_CLEAR_WUTF Clear Wakeup timer flag + * @arg @ref RTC_CLEAR_ALRBF Clear Alarm B flag + * @arg @ref RTC_CLEAR_ALRAF Clear Alarm A flag + * @retval None + */ +#define __HAL_RTC_CLEAR_FLAG(__HANDLE__, __FLAG__) (UNUSED(__HANDLE__), (RTC->SCR = (__FLAG__))) + +/** @brief Check whether the specified RTC flag is set or not. + * @param __HANDLE__ specifies the RTC Handle. + * @param __FLAG__ specifies the flag to check. + * This parameter can be any combination of the following values: + * @arg @ref RTC_FLAG_RECALPF Recalibration pending Flag + * @arg @ref RTC_FLAG_INITF Initialization flag + * @arg @ref RTC_FLAG_RSF Registers synchronization flag + * @arg @ref RTC_FLAG_INITS Initialization status flag + * @arg @ref RTC_FLAG_SHPF Shift operation pending flag + * @arg @ref RTC_FLAG_WUTWF Wakeup timer write flag + * @arg @ref RTC_FLAG_ITSF Internal Time-stamp flag + * @arg @ref RTC_FLAG_TSOVF Time-stamp overflow flag + * @arg @ref RTC_FLAG_TSF Time-stamp flag + * @arg @ref RTC_FLAG_WUTF Wakeup timer flag + * @arg @ref RTC_FLAG_ALRBF Alarm B flag + * @arg @ref RTC_FLAG_ALRAF Alarm A flag + * @retval None + */ +#define __HAL_RTC_GET_FLAG(__HANDLE__, __FLAG__) (UNUSED(__HANDLE__), (((((__FLAG__)) >> 8U) == 1U) ? (RTC->ICSR & (1U << (((uint16_t)(__FLAG__)) & RTC_FLAG_MASK))) : \ + (RTC->SR & (1U << (((uint16_t)(__FLAG__)) & RTC_FLAG_MASK))))) + +/* ---------------------------------WAKEUPTIMER---------------------------------*/ +/** @defgroup RTCEx_WakeUp_Timer RTC WakeUp Timer + * @{ + */ +/** + * @brief Enable the RTC WakeUp Timer peripheral. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_WAKEUPTIMER_ENABLE(__HANDLE__) (UNUSED(__HANDLE__), (RTC->CR |= (RTC_CR_WUTE))) + +/** + * @brief Disable the RTC WakeUp Timer peripheral. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_WAKEUPTIMER_DISABLE(__HANDLE__) (UNUSED(__HANDLE__), (RTC->CR &= ~(RTC_CR_WUTE))) + +/** + * @brief Enable the RTC WakeUpTimer interrupt. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC WakeUpTimer interrupt sources to be enabled. + * This parameter can be: + * @arg @ref RTC_IT_WUT WakeUpTimer interrupt + * @retval None + */ +#define __HAL_RTC_WAKEUPTIMER_ENABLE_IT(__HANDLE__, __INTERRUPT__) (UNUSED(__HANDLE__), (RTC->CR |= (__INTERRUPT__))) + +/** + * @brief Disable the RTC WakeUpTimer interrupt. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC WakeUpTimer interrupt sources to be disabled. + * This parameter can be: + * @arg @ref RTC_IT_WUT WakeUpTimer interrupt + * @retval None + */ +#define __HAL_RTC_WAKEUPTIMER_DISABLE_IT(__HANDLE__, __INTERRUPT__) (UNUSED(__HANDLE__), (RTC->CR &= ~(__INTERRUPT__))) + + +/** + * @brief Check whether the specified RTC WakeUpTimer interrupt has occurred or not. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC WakeUpTimer interrupt to check. + * This parameter can be: + * @arg @ref RTC_IT_WUT WakeUpTimer interrupt + * @retval None + */ +#define __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __INTERRUPT__) (UNUSED(__HANDLE__), ((((RTC->MISR) & ((__INTERRUPT__)>> 12U)) != 0UL) ? 1UL : 0UL)) + +/** + * @brief Check whether the specified RTC Wake Up timer interrupt has been enabled or not. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC Wake Up timer interrupt sources to check. + * This parameter can be: + * @arg @ref RTC_IT_WUT WakeUpTimer interrupt + * @retval None + */ +#define __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (UNUSED(__HANDLE__), ((((RTC->CR) & (__INTERRUPT__)) != 0UL) ? 1UL : 0UL)) + +/** + * @brief Get the selected RTC WakeUpTimers flag status. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC WakeUpTimer Flag is pending or not. + * This parameter can be: + * @arg @ref RTC_FLAG_WUTF + * @arg @ref RTC_FLAG_WUTWF + * @retval None + */ +#define __HAL_RTC_WAKEUPTIMER_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_GET_FLAG((__HANDLE__), (__FLAG__))) + +/** + * @brief Clear the RTC Wake Up timers pending flags. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC WakeUpTimer Flag to clear. + * This parameter can be: + * @arg @ref RTC_FLAG_WUTF + * @retval None + */ +#define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_CLEAR_FLAG((__HANDLE__), RTC_CLEAR_WUTF)) + +/* WAKE-UP TIMER EXTI */ +/* ------------------ */ +#if defined(CORE_CM0PLUS) +#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() (EXTI->C2IMR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT) +#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() (EXTI->C2IMR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT)) +#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_EVENT() (EXTI->C2EMR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT) +#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_EVENT() (EXTI->C2EMR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT)) +#else +#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() (EXTI->IMR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT) +#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() (EXTI->IMR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT)) +#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_EVENT() (EXTI->EMR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT) +#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_EVENT() (EXTI->EMR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT)) +#endif /* CORE_CM0PLUS */ + +/** + * @} + */ + + + + + +/* ---------------------------------TIMESTAMP---------------------------------*/ +/** @defgroup RTCEx_Timestamp RTC Timestamp + * @{ + */ +/** + * @brief Enable the RTC TimeStamp peripheral. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_TIMESTAMP_ENABLE(__HANDLE__) (UNUSED(__HANDLE__), (RTC->CR |= (RTC_CR_TSE))) + +/** + * @brief Disable the RTC TimeStamp peripheral. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_TIMESTAMP_DISABLE(__HANDLE__) (UNUSED(__HANDLE__), (RTC->CR &= ~(RTC_CR_TSE))) + +/** + * @brief Enable the RTC TimeStamp interrupt. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC TimeStamp interrupt source to be enabled. + * This parameter can be: + * @arg @ref RTC_IT_TS TimeStamp interrupt + * @retval None + */ +#define __HAL_RTC_TIMESTAMP_ENABLE_IT(__HANDLE__, __INTERRUPT__) (UNUSED(__HANDLE__), (RTC->CR |= (__INTERRUPT__))) + +/** + * @brief Disable the RTC TimeStamp interrupt. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC TimeStamp interrupt source to be disabled. + * This parameter can be: + * @arg @ref RTC_IT_TS TimeStamp interrupt + * @retval None + */ +#define __HAL_RTC_TIMESTAMP_DISABLE_IT(__HANDLE__, __INTERRUPT__) (UNUSED(__HANDLE__), (RTC->CR &= ~(__INTERRUPT__))) + +/** + * @brief Check whether the specified RTC TimeStamp interrupt has occurred or not. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC TimeStamp interrupt to check. + * This parameter can be: + * @arg @ref RTC_IT_TS TimeStamp interrupt + * @retval None + */ +#define __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __INTERRUPT__) (UNUSED(__HANDLE__),((((RTC->MISR) & ((__INTERRUPT__)>> 12U)) != 0U) ? 1UL : 0UL)) + +/** + * @brief Check whether the specified RTC Time Stamp interrupt has been enabled or not. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC Time Stamp interrupt source to check. + * This parameter can be: + * @arg @ref RTC_IT_TS TimeStamp interrupt + * @retval None + */ +#define __HAL_RTC_TIMESTAMP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (UNUSED(__HANDLE__), ((((RTC->CR) & (__INTERRUPT__)) != 0U) ? 1UL : 0UL)) + +/** + * @brief Get the selected RTC TimeStamps flag status. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC TimeStamp Flag is pending or not. + * This parameter can be: + * @arg @ref RTC_FLAG_TSF + * @arg @ref RTC_FLAG_TSOVF + * @retval None + */ +#define __HAL_RTC_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_GET_FLAG((__HANDLE__),(__FLAG__))) + +/** + * @brief Clear the RTC Time Stamps pending flags. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC TimeStamp Flag to clear. + * This parameter can be: + * @arg @ref RTC_FLAG_TSF + * @arg @ref RTC_FLAG_TSOVF + * @retval None + */ +#define __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_CLEAR_FLAG((__HANDLE__), (__FLAG__))) + +/* TIMESTAMP EXTI */ +/* -------------- */ +#if defined(CORE_CM0PLUS) +#define __HAL_RTC_TIMESTAMP_EXTI_ENABLE_IT() (EXTI->C2IMR1 |= RTC_EXTI_LINE_TIMESTAMP_EVENT) +#define __HAL_RTC_TIMESTAMP_EXTI_DISABLE_IT() (EXTI->C2IMR1 &= ~(RTC_EXTI_LINE_TIMESTAMP_EVENT)) +#define __HAL_RTC_TIMESTAMP_EXTI_ENABLE_EVENT() (EXTI->C2EMR1 |= RTC_EXTI_LINE_TIMESTAMP_EVENT) +#define __HAL_RTC_TIMESTAMP_EXTI_DISABLE_EVENT() (EXTI->C2EMR1 &= ~(RTC_EXTI_LINE_TIMESTAMP_EVENT)) +#else +#define __HAL_RTC_TIMESTAMP_EXTI_ENABLE_IT() (EXTI->IMR1 |= RTC_EXTI_LINE_TIMESTAMP_EVENT) +#define __HAL_RTC_TIMESTAMP_EXTI_DISABLE_IT() (EXTI->IMR1 &= ~(RTC_EXTI_LINE_TIMESTAMP_EVENT)) +#define __HAL_RTC_TIMESTAMP_EXTI_ENABLE_EVENT() (EXTI->EMR1 |= RTC_EXTI_LINE_TIMESTAMP_EVENT) +#define __HAL_RTC_TIMESTAMP_EXTI_DISABLE_EVENT() (EXTI->EMR1 &= ~(RTC_EXTI_LINE_TIMESTAMP_EVENT)) +#endif /* CORE_CM0PLUS */ + +/** + * @brief Enable the RTC internal TimeStamp peripheral. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_INTERNAL_TIMESTAMP_ENABLE(__HANDLE__) (UNUSED(__HANDLE__), (RTC->CR |= (RTC_CR_ITSE))) + +/** + * @brief Disable the RTC internal TimeStamp peripheral. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_INTERNAL_TIMESTAMP_DISABLE(__HANDLE__) (UNUSED(__HANDLE__), (RTC->CR &= ~(RTC_CR_ITSE))) + +/** + * @brief Get the selected RTC Internal Time Stamps flag status. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC Internal Time Stamp Flag is pending or not. + * This parameter can be: + * @arg @ref RTC_FLAG_ITSF + * @retval None + */ +#define __HAL_RTC_INTERNAL_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_GET_FLAG((__HANDLE__),(__FLAG__))) + +/** + * @brief Clear the RTC Internal Time Stamps pending flags. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC Internal Time Stamp Flag source to clear. + * This parameter can be: + * @arg @ref RTC_FLAG_ITSF + * @retval None + */ +#define __HAL_RTC_INTERNAL_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_CLEAR_FLAG((__HANDLE__), RTC_CLEAR_ITSF)) + +/** + * @brief Enable the RTC TimeStamp on Tamper detection. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_TAMPTS_ENABLE(__HANDLE__) (UNUSED(__HANDLE__), (RTC->CR |= (RTC_CR_TAMPTS))) + +/** + * @brief Disable the RTC TimeStamp on Tamper detection. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_TAMPTS_DISABLE(__HANDLE__) (UNUSED(__HANDLE__), (RTC->CR &= ~(RTC_CR_TAMPTS))) + +/** + * @brief Enable the RTC Tamper detection output. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_TAMPOE_ENABLE(__HANDLE__) (UNUSED(__HANDLE__), (RTC->CR |= (RTC_CR_TAMPOE))) + +/** + * @brief Disable the RTC Tamper detection output. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_TAMPOE_DISABLE(__HANDLE__) (UNUSED(__HANDLE__), (RTC->CR &= ~(RTC_CR_TAMPOE))) + + +/** + * @} + */ + + +/* ------------------------------Calibration----------------------------------*/ +/** @defgroup RTCEx_Calibration RTC Calibration + * @{ + */ + +/** + * @brief Enable the RTC calibration output. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(__HANDLE__) (UNUSED(__HANDLE__), (RTC->CR |= (RTC_CR_COE))) + +/** + * @brief Disable the calibration output. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(__HANDLE__) (UNUSED(__HANDLE__), (RTC->CR &= ~(RTC_CR_COE))) + + +/** + * @brief Enable the clock reference detection. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_CLOCKREF_DETECTION_ENABLE(__HANDLE__) (UNUSED(__HANDLE__), (RTC->CR |= (RTC_CR_REFCKON))) + +/** + * @brief Disable the clock reference detection. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_CLOCKREF_DETECTION_DISABLE(__HANDLE__) (UNUSED(__HANDLE__), (RTC->CR &= ~(RTC_CR_REFCKON))) + + +/** + * @brief Get the selected RTC shift operations flag status. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC shift operation Flag is pending or not. + * This parameter can be: + * @arg @ref RTC_FLAG_SHPF + * @retval None + */ +#define __HAL_RTC_SHIFT_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_GET_FLAG((__HANDLE__), (__FLAG__))) +/** + * @} + */ + + +/* ------------------------------Tamper----------------------------------*/ +/** @defgroup RTCEx_Tamper RTCEx tamper + * @{ + */ +/** + * @brief Enable the TAMP Tamper input detection. + * @param __HANDLE__ specifies the RTC handle. + * @param __TAMPER__ specifies the RTC Tamper source to be enabled. + * This parameter can be any combination of the following values: + * @arg RTC_TAMPER_ALL: All tampers + * @arg RTC_TAMPER_1: Tamper1 + * @arg RTC_TAMPER_2: Tamper2 + * @arg RTC_TAMPER_3: Tamper3 + * @arg RTC_IT_INT_TAMP_ALL: All Internal Tamper interrupts + * @arg RTC_IT_INT_TAMP_3: Internal Tamper3 interrupt + * @arg RTC_IT_INT_TAMP_5: Internal Tamper5 interrupt + * @arg RTC_IT_INT_TAMP_6: Internal Tamper6 interrupt + * @arg RTC_IT_INT_TAMP_8: Internal Tamper8 interrupt + * @retval None + */ +#define __HAL_RTC_TAMPER_ENABLE(__HANDLE__, __TAMPER__) (UNUSED(__HANDLE__), (TAMP->CR1 |= (__TAMPER__))) + +/** + * @brief Disable the TAMP Tamper input detection. + * @param __HANDLE__ specifies the RTC handle. + * @param __TAMPER__ specifies the RTC Tamper sources to be enabled. + * This parameter can be any combination of the following values: + * @arg RTC_TAMPER_ALL: All tampers + * @arg RTC_TAMPER_1: Tamper1 + * @arg RTC_TAMPER_2: Tamper2 + * @arg RTC_TAMPER_3: Tamper3 + * @arg RTC_IT_INT_TAMP_ALL: All Internal Tamper interrupts + * @arg RTC_IT_INT_TAMP_3: Internal Tamper3 interrupt + * @arg RTC_IT_INT_TAMP_5: Internal Tamper5 interrupt + * @arg RTC_IT_INT_TAMP_6: Internal Tamper6 interrupt + * @arg RTC_IT_INT_TAMP_8: Internal Tamper8 interrupt + */ +#define __HAL_RTC_TAMPER_DISABLE(__HANDLE__, __TAMPER__) (UNUSED(__HANDLE__), (TAMP->CR1 &= ~(__TAMPER__))) + + +/**************************************************************************************************/ +/** + * @brief Enable the TAMP Tamper interrupt. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC Tamper interrupt sources to be enabled. + * This parameter can be any combination of the following values: + * @arg RTC_IT_TAMP_ALL: All tampers interrupts + * @arg RTC_IT_TAMP_1: Tamper1 interrupt + * @arg RTC_IT_TAMP_2: Tamper2 interrupt + * @arg RTC_IT_TAMP_3: Tamper3 interrupt + * @arg RTC_IT_INT_TAMP_ALL: All Internal Tamper interrupts + * @arg RTC_IT_INT_TAMP_3: Internal Tamper3 interrupt + * @arg RTC_IT_INT_TAMP_5: Internal Tamper5 interrupt + * @arg RTC_IT_INT_TAMP_6: Internal Tamper6 interrupt + * @arg RTC_IT_INT_TAMP_8: Internal Tamper8 interrupt + * @retval None + */ +#define __HAL_RTC_TAMPER_ENABLE_IT(__HANDLE__, __INTERRUPT__) (UNUSED(__HANDLE__), (TAMP->IER |= (__INTERRUPT__))) + +/** + * @brief Disable the TAMP Tamper interrupt. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC Tamper interrupt sources to be disabled. + * This parameter can be any combination of the following values: + * @arg RTC_IT_TAMP_ALL: All tampers interrupts + * @arg RTC_IT_TAMP_1: Tamper1 interrupt + * @arg RTC_IT_TAMP_2: Tamper2 interrupt + * @arg RTC_IT_TAMP_3: Tamper3 interrupt + * @arg RTC_IT_INT_TAMP_ALL: All Internal Tamper interrupts + * @arg RTC_IT_INT_TAMP_3: Internal Tamper3 interrupt + * @arg RTC_IT_INT_TAMP_5: Internal Tamper5 interrupt + * @arg RTC_IT_INT_TAMP_6: Internal Tamper6 interrupt + * @arg RTC_IT_INT_TAMP_8: Internal Tamper8 interrupt + * @retval None + */ +#define __HAL_RTC_TAMPER_DISABLE_IT(__HANDLE__, __INTERRUPT__) (UNUSED(__HANDLE__), (TAMP->IER &= ~(__INTERRUPT__))) + + +/**************************************************************************************************/ +/** + * @brief Check whether the specified RTC Tamper interrupt has occurred or not. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC Tamper interrupt to check. + * This parameter can be: + * @arg RTC_IT_TAMP_ALL: All tampers interrupts + * @arg RTC_IT_TAMP_1: Tamper1 interrupt + * @arg RTC_IT_TAMP_2: Tamper2 interrupt + * @arg RTC_IT_TAMP_3: Tamper3 interrupt + * @arg RTC_IT_INT_TAMP_ALL: All Internal Tamper interrupts + * @arg RTC_IT_INT_TAMP_3: Internal Tamper3 interrupt + * @arg RTC_IT_INT_TAMP_5: Internal Tamper5 interrupt + * @arg RTC_IT_INT_TAMP_6: Internal Tamper6 interrupt + * @arg RTC_IT_INT_TAMP_8: Internal Tamper8 interrupt + * @retval None + */ +#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__) (UNUSED(__HANDLE__), ((((TAMP->MISR) & (__INTERRUPT__)) != 0U) ? 1UL : 0UL)) + +/** + * @brief Check whether the specified RTC Tamper interrupt has been enabled or not. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC Tamper interrupt source to check. + * This parameter can be: + * @arg RTC_IT_TAMP_ALL: All tampers interrupts + * @arg RTC_IT_TAMP_1: Tamper1 interrupt + * @arg RTC_IT_TAMP_2: Tamper2 interrupt + * @arg RTC_IT_TAMP_3: Tamper3 interrupt + * @arg RTC_IT_INT_TAMP_ALL: All internal tampers interrupts + * @arg RTC_IT_INT_TAMP_3: Internal Tamper3 interrupt + * @arg RTC_IT_INT_TAMP_5: Internal Tamper5 interrupt + * @arg RTC_IT_INT_TAMP_6: Internal Tamper6 interrupt + * @arg RTC_IT_INT_TAMP_8: Internal Tamper8 interrupt + * @retval None + */ +#define __HAL_RTC_TAMPER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (UNUSED(__HANDLE__), ((((TAMP->IER) & (__INTERRUPT__)) != 0U) ? 1UL : 0UL)) + + +/** + * @brief Get the selected RTC Tampers flag status. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC Tamper Flag is pending or not. + * This parameter can be: + * @arg RTC_FLAG_TAMP_1: Tamper1 flag + * @arg RTC_FLAG_TAMP_2: Tamper2 flag + * @arg RTC_FLAG_TAMP_3: Tamper3 flag + * @arg RTC_FLAG_INT_TAMP_3: Internal Tamper3 interrupt + * @arg RTC_FLAG_INT_TAMP_5: Internal Tamper5 interrupt + * @arg RTC_FLAG_INT_TAMP_6: Internal Tamper6 interrupt + * @arg RTC_FLAG_INT_TAMP_8: Internal Tamper8 interrupt + * @retval None + */ +#define __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__) (UNUSED(__HANDLE__), (((TAMP->SR) & (__FLAG__)) != 0UL)) + +/** + * @brief Clear the RTC Tamper's pending flags. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC Tamper Flag to clear. + * This parameter can be: + * @arg RTC_FLAG_TAMP_ALL: All tampers flag + * @arg RTC_FLAG_TAMP_1: Tamper1 flag + * @arg RTC_FLAG_TAMP_2: Tamper2 flag + * @arg RTC_FLAG_TAMP_3: Tamper3 flag + * @arg RTC_FLAG_INT_TAMP_ALL: All Internal Tamper flags + * @arg RTC_FLAG_INT_TAMP_3: Internal Tamper3 interrupt + * @arg RTC_FLAG_INT_TAMP_5: Internal Tamper5 interrupt + * @arg RTC_FLAG_INT_TAMP_6: Internal Tamper6 interrupt + * @arg RTC_FLAG_INT_TAMP_8: Internal Tamper8 interrupt + * @retval None + */ +#define __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__) (UNUSED(__HANDLE__), ((TAMP->SCR) = (__FLAG__))) + +/* TAMPER EXTI */ +/* ----------- */ +#if defined(CORE_CM0PLUS) +#define __HAL_RTC_TAMPER_EXTI_ENABLE_IT() (EXTI->C2IMR1 |= RTC_EXTI_LINE_TAMPER_EVENT) +#define __HAL_RTC_TAMPER_EXTI_DISABLE_IT() (EXTI->C2IMR1 &= ~(RTC_EXTI_LINE_TAMPER_EVENT)) +#define __HAL_RTC_TAMPER_EXTI_ENABLE_EVENT() (EXTI->C2EMR1 |= RTC_EXTI_LINE_TAMPER_EVENT) +#define __HAL_RTC_TAMPER_EXTI_DISABLE_EVENT() (EXTI->C2EMR1 &= ~(RTC_EXTI_LINE_TAMPER_EVENT)) +#else +#define __HAL_RTC_TAMPER_EXTI_ENABLE_IT() (EXTI->IMR1 |= RTC_EXTI_LINE_TAMPER_EVENT) +#define __HAL_RTC_TAMPER_EXTI_DISABLE_IT() (EXTI->IMR1 &= ~(RTC_EXTI_LINE_TAMPER_EVENT)) +#define __HAL_RTC_TAMPER_EXTI_ENABLE_EVENT() (EXTI->EMR1 |= RTC_EXTI_LINE_TAMPER_EVENT) +#define __HAL_RTC_TAMPER_EXTI_DISABLE_EVENT() (EXTI->EMR1 &= ~(RTC_EXTI_LINE_TAMPER_EVENT)) +#endif /* CORE_CM0PLUS */ + +/** + * @} + */ + +/* --------------------------------- SSR Underflow ---------------------------------*/ +/** @defgroup RTCEx_SSR_Underflow RTC SSR Underflow + * @{ + */ + +/** + * @brief Enable the RTC SSRU interrupt. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC SSRU interrupt sources to be enabled. + * This parameter can be: + * @arg @ref RTC_IT_SSRU SSRU interrupt + * @retval None + */ +#define __HAL_RTC_SSRU_ENABLE_IT(__HANDLE__, __INTERRUPT__) \ + do{ \ + UNUSED(__HANDLE__); \ + RTC->CR |= (__INTERRUPT__); \ + } while(0U); + +/** + * @brief Disable the RTC SSRU interrupt. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC SSRU interrupt sources to be disabled. + * This parameter can be: + * @arg @ref RTC_IT_SSRU SSRU interrupt + * @retval None + */ +#define __HAL_RTC_SSRU_DISABLE_IT(__HANDLE__, __INTERRUPT__) \ + do{ \ + UNUSED(__HANDLE__); \ + RTC->CR &= ~(__INTERRUPT__); \ + } while(0U); + +/** + * @brief Check whether the specified RTC SSRU interrupt has occurred or not. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC SSRU interrupt to check. + * This parameter can be: + * @arg @ref RTC_IT_SSRU SSRU interrupt + * @retval None + */ +#define __HAL_RTC_SSRU_GET_IT(__HANDLE__, __INTERRUPT__) (UNUSED(__HANDLE__), (((RTC->MISR) & ((__INTERRUPT__) >> 1) != 0U) ? 1U : 0U)) +/** + * @brief Check whether the specified RTC Wake Up timer interrupt has been enabled or not. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC Wake Up timer interrupt sources to check. + * This parameter can be: + * @arg @ref RTC_IT_SSRU SSRU interrupt + * @retval None + */ +#define __HAL_RTC_SSRU_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (UNUSED(__HANDLE__), ((((RTC->CR) & (__INTERRUPT__)) != 0U) ? 1U : 0U)) + +/** + * @brief Get the selected RTC SSRU's flag status. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC SSRU Flag is pending or not. + * This parameter can be: + * @arg @ref RTC_FLAG_SSRUF + * @retval None + */ +#define __HAL_RTC_SSRU_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_GET_FLAG((__HANDLE__), (__FLAG__))) + +/** + * @brief Clear the RTC Wake Up timer's pending flags. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC SSRU Flag to clear. + * This parameter can be: + * @arg @ref RTC_FLAG_SSRUF + * @retval None + */ +#define __HAL_RTC_SSRU_CLEAR_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_CLEAR_FLAG((__HANDLE__), RTC_CLEAR_SSRUF)) + +/* SSR Underflow EXTI */ +/* ------------------ */ +#if defined(CORE_CM0PLUS) +#define __HAL_RTC_SSRU_EXTI_ENABLE_IT() (EXTI->C2IMR1 |= RTC_EXTI_LINE_SSRU_EVENT) +#define __HAL_RTC_SSRU_EXTI_DISABLE_IT() (EXTI->C2IMR1 &= ~(RTC_EXTI_LINE_SSRU_EVENT)) +#define __HAL_RTC_SSRU_EXTI_ENABLE_EVENT() (EXTI->C2EMR1 |= RTC_EXTI_LINE_SSRU_EVENT) +#define __HAL_RTC_SSRU_EXTI_DISABLE_EVENT() (EXTI->C2EMR1 &= ~(RTC_EXTI_LINE_SSRU_EVENT)) +#else +#define __HAL_RTC_SSRU_EXTI_ENABLE_IT() (EXTI->IMR1 |= RTC_EXTI_LINE_SSRU_EVENT) +#define __HAL_RTC_SSRU_EXTI_DISABLE_IT() (EXTI->IMR1 &= ~(RTC_EXTI_LINE_SSRU_EVENT)) +#define __HAL_RTC_SSRU_EXTI_ENABLE_EVENT() (EXTI->EMR1 |= RTC_EXTI_LINE_SSRU_EVENT) +#define __HAL_RTC_SSRU_EXTI_DISABLE_EVENT() (EXTI->EMR1 &= ~(RTC_EXTI_LINE_SSRU_EVENT)) +#endif /* CORE_CM0PLUS */ + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup RTCEx_Exported_Functions RTCEx Exported Functions + * @{ + */ + +/* RTC TimeStamp functions *****************************************/ +/** @defgroup RTCEx_Exported_Functions_Group1 Extended RTC TimeStamp functions + * @{ + */ + +HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin); +HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin); +HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc); +HAL_StatusTypeDef HAL_RTCEx_SetInternalTimeStamp(RTC_HandleTypeDef *hrtc); +HAL_StatusTypeDef HAL_RTCEx_DeactivateInternalTimeStamp(RTC_HandleTypeDef *hrtc); +HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTimeStamp, + RTC_DateTypeDef *sTimeStampDate, uint32_t Format); +void HAL_RTCEx_TimeStampIRQHandler(RTC_HandleTypeDef *hrtc); +HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout); +void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc); +/** + * @} + */ + + +/* RTC Wake-up functions ******************************************************/ +/** @defgroup RTCEx_Exported_Functions_Group2 Extended RTC Wake-up functions + * @{ + */ + +HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock); +HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock, + uint32_t WakeUpAutoClr); +HAL_StatusTypeDef HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc); +uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc); +void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc); +void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc); +HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout); +/** + * @} + */ + +/* Extended Control functions ************************************************/ +/** @defgroup RTCEx_Exported_Functions_Group3 Extended Peripheral Control functions + * @{ + */ + +HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef *hrtc, uint32_t SmoothCalibPeriod, + uint32_t SmoothCalibPlusPulses, uint32_t SmoothCalibMinusPulsesValue); +HAL_StatusTypeDef HAL_RTCEx_SetLowPowerCalib(RTC_HandleTypeDef *hrtc, uint32_t LowPowerCalib); +HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef *hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS); +HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef *hrtc, uint32_t CalibOutput); +HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef *hrtc); +HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef *hrtc); +HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef *hrtc); +HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef *hrtc); +HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef *hrtc); +HAL_StatusTypeDef HAL_RTCEx_MonotonicCounterIncrement(RTC_HandleTypeDef *hrtc, uint32_t Instance); +HAL_StatusTypeDef HAL_RTCEx_MonotonicCounterGet(RTC_HandleTypeDef *hrtc, uint32_t Instance, uint32_t *Value); +HAL_StatusTypeDef HAL_RTCEx_SetSSRU_IT(RTC_HandleTypeDef *hrtc); +HAL_StatusTypeDef HAL_RTCEx_DeactivateSSRU(RTC_HandleTypeDef *hrtc); +void HAL_RTCEx_SSRUIRQHandler(RTC_HandleTypeDef *hrtc); +void HAL_RTCEx_SSRUEventCallback(RTC_HandleTypeDef *hrtc); +/** + * @} + */ + +/* Extended RTC features functions *******************************************/ +/** @defgroup RTCEx_Exported_Functions_Group4 Extended features functions + * @{ + */ + +void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc); +HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout); +/** + * @} + */ + +/** @defgroup RTCEx_Exported_Functions_Group5 Extended RTC Tamper functions + * @{ + */ +HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper); +HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper); +HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper); +HAL_StatusTypeDef HAL_RTCEx_PollForTamperEvent(RTC_HandleTypeDef *hrtc, uint32_t Tamper, uint32_t Timeout); +HAL_StatusTypeDef HAL_RTCEx_SetInternalTamper(RTC_HandleTypeDef *hrtc, RTC_InternalTamperTypeDef *sIntTamper); +HAL_StatusTypeDef HAL_RTCEx_SetInternalTamper_IT(RTC_HandleTypeDef *hrtc, RTC_InternalTamperTypeDef *sIntTamper); +HAL_StatusTypeDef HAL_RTCEx_DeactivateInternalTamper(RTC_HandleTypeDef *hrtc, uint32_t IntTamper); +HAL_StatusTypeDef HAL_RTCEx_PollForInternalTamperEvent(RTC_HandleTypeDef *hrtc, uint32_t IntTamper, uint32_t Timeout); +void HAL_RTCEx_TamperIRQHandler(RTC_HandleTypeDef *hrtc); +void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc); +void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc); +void HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef *hrtc); +void HAL_RTCEx_InternalTamper3EventCallback(RTC_HandleTypeDef *hrtc); +void HAL_RTCEx_InternalTamper5EventCallback(RTC_HandleTypeDef *hrtc); +void HAL_RTCEx_InternalTamper6EventCallback(RTC_HandleTypeDef *hrtc); +void HAL_RTCEx_InternalTamper8EventCallback(RTC_HandleTypeDef *hrtc); +/** + * @} + */ + +/** @defgroup RTCEx_Exported_Functions_Group6 Extended RTC Backup register functions + * @{ + */ +void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data); +uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister); +/** + * @} + */ + +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup RTCEx_Private_Constants RTCEx Private Constants + * @{ + */ +/*#define RTC_EXTI_LINE_ALARM_EVENT EXTI_IMR1_IM17 */ /*!< External interrupt line 17 Connected to the RTC Alarm event (defined in rtc.h) */ +#define RTC_EXTI_LINE_SSRU_EVENT EXTI_IMR1_IM18 /*!< External interrupt line 18 Connected to the RTC SSR Underflow event */ +#define RTC_EXTI_LINE_TIMESTAMP_EVENT EXTI_IMR1_IM19 /*!< External interrupt line 19 Connected to the RTC Time Stamp events */ +#define RTC_EXTI_LINE_WAKEUPTIMER_EVENT EXTI_IMR1_IM20 /*!< External interrupt line 20 Connected to the RTC Wakeup event */ +#define RTC_EXTI_LINE_TAMPER_EVENT EXTI_IMR1_IM19 /*!< External interrupt line 19 Connected to the RTC tamper events */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup RTCEx_Private_Macros RTCEx Private Macros + * @{ + */ + +/** @defgroup RTCEx_IS_RTC_Definitions Private macros to check input parameters + * @{ + */ +#define IS_TIMESTAMP_EDGE(EDGE) (((EDGE) == RTC_TIMESTAMPEDGE_RISING) || \ + ((EDGE) == RTC_TIMESTAMPEDGE_FALLING)) + + +#define IS_RTC_TIMESTAMP_PIN(PIN) (((PIN) == RTC_TIMESTAMPPIN_DEFAULT)) + + + +#define IS_RTC_TIMESTAMPONTAMPER_DETECTION(DETECTION) (((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_ENABLE) || \ + ((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_DISABLE)) + +#define IS_RTC_TAMPER_TAMPERDETECTIONOUTPUT(MODE) (((MODE) == RTC_TAMPERDETECTIONOUTPUT_ENABLE) || \ + ((MODE) == RTC_TAMPERDETECTIONOUTPUT_DISABLE)) + +#define IS_RTC_WAKEUP_CLOCK(CLOCK) (((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV16) || \ + ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV8) || \ + ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV4) || \ + ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV2) || \ + ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_16BITS) || \ + ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_17BITS)) + +#define IS_RTC_WAKEUP_COUNTER(COUNTER) ((COUNTER) <= RTC_WUTR_WUT) + +#define IS_RTC_SMOOTH_CALIB_PERIOD(PERIOD) (((PERIOD) == RTC_SMOOTHCALIB_PERIOD_32SEC) || \ + ((PERIOD) == RTC_SMOOTHCALIB_PERIOD_16SEC) || \ + ((PERIOD) == RTC_SMOOTHCALIB_PERIOD_8SEC)) + +#define IS_RTC_SMOOTH_CALIB_PLUS(PLUS) (((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_SET) || \ + ((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_RESET)) + +#define IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= RTC_CALR_CALM) + +#define IS_RTC_LOW_POWER_CALIB(LPCAL) (((LPCAL) == RTC_LPCAL_SET) || \ + ((LPCAL) == RTC_LPCAL_RESET)) + + +#define IS_RTC_TAMPER(__TAMPER__) ((((__TAMPER__) & RTC_TAMPER_ALL) != 0x00U) && \ + (((__TAMPER__) & ~RTC_TAMPER_ALL) == 0x00U)) + +#define IS_RTC_INTERNAL_TAMPER(__INT_TAMPER__) ((((__INT_TAMPER__) & RTC_INT_TAMPER_ALL) != 0x00U) && \ + (((__INT_TAMPER__) & ~RTC_INT_TAMPER_ALL) == 0x00U)) + +#define IS_RTC_TAMPER_TRIGGER(__TRIGGER__) (((__TRIGGER__) == RTC_TAMPERTRIGGER_RISINGEDGE) || \ + ((__TRIGGER__) == RTC_TAMPERTRIGGER_FALLINGEDGE) || \ + ((__TRIGGER__) == RTC_TAMPERTRIGGER_LOWLEVEL) || \ + ((__TRIGGER__) == RTC_TAMPERTRIGGER_HIGHLEVEL)) + +#define IS_RTC_TAMPER_ERASE_MODE(__MODE__) (((__MODE__) == RTC_TAMPER_ERASE_BACKUP_ENABLE) || \ + ((__MODE__) == RTC_TAMPER_ERASE_BACKUP_DISABLE)) + +#define IS_RTC_TAMPER_MASKFLAG_STATE(__STATE__) (((__STATE__) == RTC_TAMPERMASK_FLAG_ENABLE) || \ + ((__STATE__) == RTC_TAMPERMASK_FLAG_DISABLE)) + +#define IS_RTC_TAMPER_FILTER(__FILTER__) (((__FILTER__) == RTC_TAMPERFILTER_DISABLE) || \ + ((__FILTER__) == RTC_TAMPERFILTER_2SAMPLE) || \ + ((__FILTER__) == RTC_TAMPERFILTER_4SAMPLE) || \ + ((__FILTER__) == RTC_TAMPERFILTER_8SAMPLE)) + +#define IS_RTC_TAMPER_SAMPLING_FREQ(__FREQ__) (((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768)|| \ + ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384)|| \ + ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192) || \ + ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096) || \ + ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048) || \ + ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024) || \ + ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512) || \ + ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256)) + +#define IS_RTC_TAMPER_PRECHARGE_DURATION(__DURATION__) (((__DURATION__) == RTC_TAMPERPRECHARGEDURATION_1RTCCLK) || \ + ((__DURATION__) == RTC_TAMPERPRECHARGEDURATION_2RTCCLK) || \ + ((__DURATION__) == RTC_TAMPERPRECHARGEDURATION_4RTCCLK) || \ + ((__DURATION__) == RTC_TAMPERPRECHARGEDURATION_8RTCCLK)) + +#define IS_RTC_TAMPER_PULLUP_STATE(__STATE__) (((__STATE__) == RTC_TAMPER_PULLUP_ENABLE) || \ + ((__STATE__) == RTC_TAMPER_PULLUP_DISABLE)) + +#define IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(DETECTION) (((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_ENABLE) || \ + ((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_DISABLE)) + +#define IS_RTC_BKP(__BKP__) ((__BKP__) < RTC_BKP_NUMBER) + +#define IS_RTC_SHIFT_ADD1S(SEL) (((SEL) == RTC_SHIFTADD1S_RESET) || \ + ((SEL) == RTC_SHIFTADD1S_SET)) + +#define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= RTC_SHIFTR_SUBFS) + +#define IS_RTC_CALIB_OUTPUT(OUTPUT) (((OUTPUT) == RTC_CALIBOUTPUT_512HZ) || \ + ((OUTPUT) == RTC_CALIBOUTPUT_1HZ)) + +#define IS_RTC_BINARY_MODE(MODE) (((MODE) == RTC_BINARY_NONE) || \ + ((MODE) == RTC_BINARY_ONLY) || \ + ((MODE) == RTC_BINARY_MIX )) + +#define IS_RTC_BINARY_MIX_BCDU(BDCU) (((BDCU) == RTC_BINARY_MIX_BCDU_0) || \ + ((BDCU) == RTC_BINARY_MIX_BCDU_1) || \ + ((BDCU) == RTC_BINARY_MIX_BCDU_2) || \ + ((BDCU) == RTC_BINARY_MIX_BCDU_3) || \ + ((BDCU) == RTC_BINARY_MIX_BCDU_4) || \ + ((BDCU) == RTC_BINARY_MIX_BCDU_5) || \ + ((BDCU) == RTC_BINARY_MIX_BCDU_6) || \ + ((BDCU) == RTC_BINARY_MIX_BCDU_7)) + +#define IS_RTC_ALARM_SUB_SECOND_BINARY_MASK(MASK) (((MASK) == 0u) || \ + (((MASK) >= RTC_ALARMSUBSECONDBINMASK_SS31_1) && ((MASK) <= RTC_ALARMSUBSECONDBINMASK_NONE))) + +#define IS_RTC_ALARMSUBSECONDBIN_AUTOCLR(SEL) (((SEL) == RTC_ALARMSUBSECONDBIN_AUTOCLR_NO) || \ + ((SEL) == RTC_ALARMSUBSECONDBIN_AUTOCLR_YES)) +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32WLxx_HAL_RTC_EX_H */ diff --git a/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h b/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h new file mode 100644 index 0000000..007306c --- /dev/null +++ b/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h @@ -0,0 +1,426 @@ +/** + ****************************************************************************** + * @file stm32wlxx_hal_subghz.h + * @author MCD Application Team + * @brief Header file of SUBGHZ HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32WLxx_HAL_SUBGHZ_H +#define STM32WLxx_HAL_SUBGHZ_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wlxx_hal_def.h" + +/* Include low level driver */ +#include "stm32wlxx_ll_spi.h" + +/** @addtogroup STM32WLxx_HAL_Driver + * @{ + */ + +/** @addtogroup SUBGHZ + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup SUBGHZ_Exported_Types SUBGHZ Exported Types + * @{ + */ + +/** + * @brief SPI Configuration Structure definition + */ +typedef struct +{ + uint32_t BaudratePrescaler; /*!< Specifies the Baud Rate prescaler value which will be + used to configure SUBGHZSPI clock. + This parameter can be a value of @ref SUBGHZ_SPI_BAUDRATE_Prescaler */ +} SUBGHZ_InitTypeDef; + +/** + * @brief HAL SUBGHZ State structure definition + */ +typedef enum +{ + HAL_SUBGHZ_STATE_RESET = 0x00U, /*!< Peripheral not Initialized */ + HAL_SUBGHZ_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ + HAL_SUBGHZ_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */ + HAL_SUBGHZ_STATE_RESET_RF_READY = 0x03U, /*!< Peripheral not Initialized but RF is */ +} HAL_SUBGHZ_StateTypeDef; + +/** + * @brief HAL SUBGHZ CAD Status structure definition + */ +typedef enum +{ + HAL_SUBGHZ_CAD_CLEAR = 0x00U, /*!< Channel activity cleared */ + HAL_SUBGHZ_CAD_DETECTED = 0x01U, /*!< Channel activity detected */ +} HAL_SUBGHZ_CadStatusTypeDef; + +/** + * @brief SUBGHZ handle Structure definition + */ +#if (USE_HAL_SUBGHZ_REGISTER_CALLBACKS == 1) +typedef struct __SUBGHZ_HandleTypeDef +#else +typedef struct +#endif /* USE_HAL_SUBGHZ_REGISTER_CALLBACKS */ +{ + SUBGHZ_InitTypeDef Init; /*!< SUBGHZ communication parameters */ + + uint8_t DeepSleep; /*!< SUBGHZ deep sleep state */ + + HAL_LockTypeDef Lock; /*!< Locking object */ + + __IO HAL_SUBGHZ_StateTypeDef State; /*!< SUBGHZ communication state */ + + __IO uint32_t ErrorCode; /*!< SUBGHZ Error code */ + +#if (USE_HAL_SUBGHZ_REGISTER_CALLBACKS == 1) + void (* TxCpltCallback)(struct __SUBGHZ_HandleTypeDef *hsubghz); /*!< SUBGHZ Tx Completed callback */ + void (* RxCpltCallback)(struct __SUBGHZ_HandleTypeDef *hsubghz); /*!< SUBGHZ Rx Completed callback */ + void (* PreambleDetectedCallback)(struct __SUBGHZ_HandleTypeDef *hsubghz); /*!< SUBGHZ Preamble detected callback */ + void (* SyncWordValidCallback)(struct __SUBGHZ_HandleTypeDef *hsubghz); /*!< SUBGHZ Synchro word valid callback */ + void (* HeaderValidCallback)(struct __SUBGHZ_HandleTypeDef *hsubghz); /*!< SUBGHZ Header valid callback */ + void (* HeaderErrorCallback)(struct __SUBGHZ_HandleTypeDef *hsubghz); /*!< SUBGHZ Header error callback */ + void (* CRCErrorCallback)(struct __SUBGHZ_HandleTypeDef *hsubghz); /*!< SUBGHZ CRC Error callback */ + void (* CADStatusCallback)(struct __SUBGHZ_HandleTypeDef *hsubghz, HAL_SUBGHZ_CadStatusTypeDef cadstatus); /*!< SUBGHZ CAD Status callback */ + void (* RxTxTimeoutCallback)(struct __SUBGHZ_HandleTypeDef *hsubghz); /*!< SUBGHZ Rx Tx Timeout callback */ + void (* MspInitCallback)(struct __SUBGHZ_HandleTypeDef *hsubghz); /*!< SUBGHZ Msp Init callback */ + void (* MspDeInitCallback)(struct __SUBGHZ_HandleTypeDef *hsubghz); /*!< SUBGHZ Msp DeInit callback */ + void (* LrFhssHopCallback)(struct __SUBGHZ_HandleTypeDef *hsubghz); /*!< SUBGHZ LR FHSS Hop callback */ +#endif /* USE_HAL_SUBGHZ_REGISTER_CALLBACKS */ +} SUBGHZ_HandleTypeDef; + +#if (USE_HAL_SUBGHZ_REGISTER_CALLBACKS == 1) +/** + * @brief HAL SUBGHZ Callback ID enumeration definition + */ +typedef enum +{ + HAL_SUBGHZ_TX_COMPLETE_CB_ID = 0x00U, /*!< SUBGHZ Tx Completed callback ID */ + HAL_SUBGHZ_RX_COMPLETE_CB_ID = 0x01U, /*!< SUBGHZ Rx Completed callback ID */ + HAL_SUBGHZ_PREAMBLE_DETECTED_CB_ID = 0x02U, /*!< SUBGHZ Preamble detected callback ID */ + HAL_SUBGHZ_SYNCWORD_VALID_CB_ID = 0x03U, /*!< SUBGHZ Synchro word valid callback ID */ + HAL_SUBGHZ_HEADER_VALID_CB_ID = 0x04U, /*!< SUBGHZ Header valid callback ID */ + HAL_SUBGHZ_HEADER_ERROR_CB_ID = 0x05U, /*!< SUBGHZ Header error callback ID */ + HAL_SUBGHZ_CRC_ERROR_CB_ID = 0x06U, /*!< SUBGHZ CRC error callback ID */ + HAL_SUBGHZ_RX_TX_TIMEOUT_CB_ID = 0x07U, /*!< SUBGHZ Rx Tx timeout callback ID */ + HAL_SUBGHZ_MSPINIT_CB_ID = 0x08U, /*!< SUBGHZ Msp Init callback ID */ + HAL_SUBGHZ_MSPDEINIT_CB_ID = 0x09U, /*!< SUBGHZ Msp DeInit callback ID */ + HAL_SUBGHZ_LR_FHSS_HOP_CB_ID = 0x0AU, /*!< SUBGHZ LR FHSS Hop callback ID */ +} HAL_SUBGHZ_CallbackIDTypeDef; + +/** + * @brief HAL SUBGHZ Callback pointer definition + */ +typedef void (*pSUBGHZ_CallbackTypeDef)(SUBGHZ_HandleTypeDef *hsubghz); /*!< pointer to an SUBGHZ callback function */ +typedef void (*pSUBGHZ_CadStatusCallbackTypeDef)(SUBGHZ_HandleTypeDef *hsubghz, HAL_SUBGHZ_CadStatusTypeDef cadstatus); /*!< pointer to an CAD Status callback function */ +#endif /* USE_HAL_SUBGHZ_REGISTER_CALLBACKS */ + +/* + * @brief HAL SUBGHZ Radio Set Command enumeration definition + */ +typedef enum +{ + RADIO_SET_SLEEP = 0x84U, + RADIO_SET_STANDBY = 0x80U, + RADIO_SET_FS = 0xC1U, + RADIO_SET_TX = 0x83U, + RADIO_SET_RX = 0x82U, + RADIO_SET_RXDUTYCYCLE = 0x94U, + RADIO_SET_CAD = 0xC5U, + RADIO_SET_TXCONTINUOUSWAVE = 0xD1U, + RADIO_SET_TXCONTINUOUSPREAMBLE = 0xD2U, + RADIO_SET_PACKETTYPE = 0x8AU, + RADIO_SET_RFFREQUENCY = 0x86U, + RADIO_SET_TXPARAMS = 0x8EU, + RADIO_SET_PACONFIG = 0x95U, + RADIO_SET_CADPARAMS = 0x88U, + RADIO_SET_BUFFERBASEADDRESS = 0x8FU, + RADIO_SET_MODULATIONPARAMS = 0x8BU, + RADIO_SET_PACKETPARAMS = 0x8CU, + RADIO_RESET_STATS = 0x00U, + RADIO_CFG_DIOIRQ = 0x08U, + RADIO_CLR_IRQSTATUS = 0x02U, + RADIO_CALIBRATE = 0x89U, + RADIO_CALIBRATEIMAGE = 0x98U, + RADIO_SET_REGULATORMODE = 0x96U, + RADIO_SET_TCXOMODE = 0x97U, + RADIO_SET_TXFALLBACKMODE = 0x93U, + RADIO_SET_RFSWITCHMODE = 0x9DU, + RADIO_SET_STOPRXTIMERONPREAMBLE = 0x9FU, + RADIO_SET_LORASYMBTIMEOUT = 0xA0U, + RADIO_CLR_ERROR = 0x07U +} SUBGHZ_RadioSetCmd_t; + + +/** + * @brief HAL SUBGHZ Radio Get Command enumeration definition + */ +typedef enum +{ + RADIO_GET_STATUS = 0xC0U, + RADIO_GET_PACKETTYPE = 0x11U, + RADIO_GET_RXBUFFERSTATUS = 0x13U, + RADIO_GET_PACKETSTATUS = 0x14U, + RADIO_GET_RSSIINST = 0x15U, + RADIO_GET_STATS = 0x10U, + RADIO_GET_IRQSTATUS = 0x12U, + RADIO_GET_ERROR = 0x17U +} SUBGHZ_RadioGetCmd_t; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup SUBGHZ_Exported_Constants SUBGHZ Exported Constants + * @{ + */ + +/** @defgroup SUBGHZ_Error_Code SUBGHZ Error Code definition + * @brief SUBGHZ Error Code definition + * @{ + */ +#define HAL_SUBGHZ_ERROR_NONE (0x00000000U) /*!< No error */ +#define HAL_SUBGHZ_ERROR_TIMEOUT (0x00000001U) /*!< Timeout Error */ +#define HAL_SUBGHZ_ERROR_RF_BUSY (0x00000002U) /*!< RF Busy Error */ +#define HAL_SUBGHZ_ERROR_CRC_MISMATCH (0x00000004U) /*!< CRC mismatch Error */ +#if (USE_HAL_SUBGHZ_REGISTER_CALLBACKS == 1) +#define HAL_SUBGHZ_ERROR_INVALID_CALLBACK (0x00000080U) /*!< Invalid Callback error */ +#endif /* USE_HAL_SUBGHZ_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @defgroup SUBGHZ_SPI_BAUDRATE_Prescaler SUBGHZ BaudRate Prescaler + * @{ + */ +#define SUBGHZSPI_BAUDRATEPRESCALER_2 (0x00000000U) +#define SUBGHZSPI_BAUDRATEPRESCALER_4 (SPI_CR1_BR_0) +#define SUBGHZSPI_BAUDRATEPRESCALER_8 (SPI_CR1_BR_1) +#define SUBGHZSPI_BAUDRATEPRESCALER_16 (SPI_CR1_BR_1 | SPI_CR1_BR_0) +#define SUBGHZSPI_BAUDRATEPRESCALER_32 (SPI_CR1_BR_2) +#define SUBGHZSPI_BAUDRATEPRESCALER_64 (SPI_CR1_BR_2 | SPI_CR1_BR_0) +#define SUBGHZSPI_BAUDRATEPRESCALER_128 (SPI_CR1_BR_2 | SPI_CR1_BR_1) +#define SUBGHZSPI_BAUDRATEPRESCALER_256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0) +/** + * @} + */ + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup SUBGHZ_Private_Constants SUBGHZ Private Constants + * @{ + */ + +/** + * @brief SUBGHZSPI_Interrupts SUBGHZSPI Interrupts + */ +#define SUBGHZ_IT_TX_CPLT 0x0001U +#define SUBGHZ_IT_RX_CPLT 0x0002U +#define SUBGHZ_IT_PREAMBLE_DETECTED 0x0004U +#define SUBGHZ_IT_SYNCWORD_VALID 0x0008U +#define SUBGHZ_IT_HEADER_VALID 0x0010U +#define SUBGHZ_IT_HEADER_ERROR 0x0020U +#define SUBGHZ_IT_CRC_ERROR 0x0040U +#define SUBGHZ_IT_CAD_DONE 0x0080U +#define SUBGHZ_IT_CAD_ACTIVITY_DETECTED 0x0100U +#define SUBGHZ_IT_RX_TX_TIMEOUT 0x0200U +#define SUBGHZ_IT_LR_FHSS_HOP 0x4000U +/** + * @brief SUBGHZ Radio Read/Write Command definition + */ +#define SUBGHZ_RADIO_WRITE_REGISTER 0x0DU +#define SUBGHZ_RADIO_READ_REGISTER 0x1DU +#define SUBGHZ_RADIO_WRITE_BUFFER 0x0EU +#define SUBGHZ_RADIO_READ_BUFFER 0x1EU +/** + * @} + */ + + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup SUBGHZ_Exported_Macros SUBGHZ Exported Macros + * @{ + */ + +/** @brief Reset SUBGHZ handle state. + * @param __HANDLE__ specifies the SUBGHZ Handle. + * @retval None + */ +#if (USE_HAL_SUBGHZ_REGISTER_CALLBACKS == 1) +#define __HAL_SUBGHZ_RESET_HANDLE_STATE(__HANDLE__) \ + do{ \ + (__HANDLE__)->State = HAL_SUBGHZ_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0U) + +#define __HAL_SUBGHZ_RESET_HANDLE_STATE_RF_READY(__HANDLE__) \ + do{ \ + (__HANDLE__)->State = HAL_SUBGHZ_STATE_RESET_RF_READY; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0U) +#else +#define __HAL_SUBGHZ_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SUBGHZ_STATE_RESET) +#define __HAL_SUBGHZ_RESET_HANDLE_STATE_RF_READY(__HANDLE__) ((__HANDLE__)->State = HAL_SUBGHZ_STATE_RESET_RF_READY) +#endif /* USE_HAL_SUBGHZ_REGISTER_CALLBACKS */ +/** + * @} + */ + +/* Private macros -----------------------------------------------------------*/ +/** @defgroup SUBGHZ_Private_Macros SUBGHZ Private Macros + * @{ + */ + +/** @brief Check whether the specified SPI Interrupt is set or not. + * @param __SUBGHZ_IRQ__ copy of SUBGHZ IRQ Register. + * @param __INTERRUPT__ specifies the SUBGHZ interrupt source to check. + * This parameter can be one of the following values: + * @arg SUBGHZ_IT_TX_DONE + * @arg SUBGHZ_IT_RX_DONE + * @arg SUBGHZ_IT_PREAMBLE_DETECTED + * @arg SUBGHZ_IT_SYNCWORD_VALID + * @arg SUBGHZ_IT_HEADER_VALID + * @arg SUBGHZ_IT_HEADER_ERROR + * @arg SUBGHZ_IT_CRC_ERROR + * @arg SUBGHZ_IT_CAD_DONE + * @arg SUBGHZ_IT_CAD_ACTIVITY_DETECTED + * @arg SUBGHZ_IT_RX_TX_TIMEOUT + * @arg SUBGHZ_IT_LR_FHSS_HOP + * @retval SET or RESET. + */ +#define SUBGHZ_CHECK_IT_SOURCE(__SUBGHZ_IRQ__, __INTERRUPT__) \ + ((((__SUBGHZ_IRQ__) & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) + +/** @brief Checks if SUBGHZSPI Baudrate prescaler parameter is in allowed range. + * @param __PRESCALER__ specifies the SUBGHZSPI Baudrate prescaler. + * This parameter can be a value of @ref SUBGHZ_SPI_BAUDRATE_Prescaler + * @retval None + */ +#define IS_SUBGHZSPI_BAUDRATE_PRESCALER(__PRESCALER__) (((__PRESCALER__) == SUBGHZSPI_BAUDRATEPRESCALER_2) || \ + ((__PRESCALER__) == SUBGHZSPI_BAUDRATEPRESCALER_4) || \ + ((__PRESCALER__) == SUBGHZSPI_BAUDRATEPRESCALER_8) || \ + ((__PRESCALER__) == SUBGHZSPI_BAUDRATEPRESCALER_16) || \ + ((__PRESCALER__) == SUBGHZSPI_BAUDRATEPRESCALER_32) || \ + ((__PRESCALER__) == SUBGHZSPI_BAUDRATEPRESCALER_64) || \ + ((__PRESCALER__) == SUBGHZSPI_BAUDRATEPRESCALER_128) || \ + ((__PRESCALER__) == SUBGHZSPI_BAUDRATEPRESCALER_256)) +/** + * @} + */ + +/* Exported functions ------------------------------------------------------- */ +/** @addtogroup SUBGHZ_Exported_Functions + * @{ + */ + +/** @addtogroup SUBGHZ_Exported_Functions_Group1 + * @{ + */ +/* Initialization/de-initialization functions ********************************/ +HAL_StatusTypeDef HAL_SUBGHZ_Init(SUBGHZ_HandleTypeDef *hsubghz); +HAL_StatusTypeDef HAL_SUBGHZ_DeInit(SUBGHZ_HandleTypeDef *hsubghz); +void HAL_SUBGHZ_MspInit(SUBGHZ_HandleTypeDef *hsubghz); +void HAL_SUBGHZ_MspDeInit(SUBGHZ_HandleTypeDef *hsubghz); + +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_SUBGHZ_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_SUBGHZ_RegisterCallback(SUBGHZ_HandleTypeDef *hsubghz, + HAL_SUBGHZ_CallbackIDTypeDef CallbackID, + pSUBGHZ_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_SUBGHZ_UnRegisterCallback(SUBGHZ_HandleTypeDef *hsubghz, + HAL_SUBGHZ_CallbackIDTypeDef CallbackID); +HAL_StatusTypeDef HAL_SUBGHZ_RegisterCadStatusCallback(SUBGHZ_HandleTypeDef *hsubghz, + pSUBGHZ_CadStatusCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_SUBGHZ_UnRegisterCadStatusCallback(SUBGHZ_HandleTypeDef *hsubghz); +#endif /* USE_HAL_SUBGHZ_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @addtogroup SUBGHZ_Exported_Functions_Group2 + * @{ + */ +/* I/O operation functions ***************************************************/ +HAL_StatusTypeDef HAL_SUBGHZ_ExecSetCmd(SUBGHZ_HandleTypeDef *hsubghz, SUBGHZ_RadioSetCmd_t Command, uint8_t *pBuffer, + uint16_t Size); +HAL_StatusTypeDef HAL_SUBGHZ_ExecGetCmd(SUBGHZ_HandleTypeDef *hsubghz, SUBGHZ_RadioGetCmd_t Command, uint8_t *pBuffer, + uint16_t Size); +HAL_StatusTypeDef HAL_SUBGHZ_WriteBuffer(SUBGHZ_HandleTypeDef *hsubghz, uint8_t Offset, uint8_t *pBuffer, + uint16_t Size); +HAL_StatusTypeDef HAL_SUBGHZ_ReadBuffer(SUBGHZ_HandleTypeDef *hsubghz, uint8_t Offset, uint8_t *pBuffer, + uint16_t Size); +HAL_StatusTypeDef HAL_SUBGHZ_WriteRegisters(SUBGHZ_HandleTypeDef *hsubghz, uint16_t Address, uint8_t *pBuffer, + uint16_t Size); +HAL_StatusTypeDef HAL_SUBGHZ_ReadRegisters(SUBGHZ_HandleTypeDef *hsubghz, uint16_t Address, uint8_t *pBuffer, + uint16_t Size); + +HAL_StatusTypeDef HAL_SUBGHZ_WriteRegister(SUBGHZ_HandleTypeDef *hsubghz, uint16_t Address, uint8_t Value); +HAL_StatusTypeDef HAL_SUBGHZ_ReadRegister(SUBGHZ_HandleTypeDef *hsubghz, uint16_t Address, uint8_t *pValue); + +void HAL_SUBGHZ_IRQHandler(SUBGHZ_HandleTypeDef *hsubghz); +void HAL_SUBGHZ_TxCpltCallback(SUBGHZ_HandleTypeDef *hsubghz); +void HAL_SUBGHZ_RxCpltCallback(SUBGHZ_HandleTypeDef *hsubghz); +void HAL_SUBGHZ_PreambleDetectedCallback(SUBGHZ_HandleTypeDef *hsubghz); +void HAL_SUBGHZ_SyncWordValidCallback(SUBGHZ_HandleTypeDef *hsubghz); +void HAL_SUBGHZ_HeaderValidCallback(SUBGHZ_HandleTypeDef *hsubghz); +void HAL_SUBGHZ_HeaderErrorCallback(SUBGHZ_HandleTypeDef *hsubghz); +void HAL_SUBGHZ_CRCErrorCallback(SUBGHZ_HandleTypeDef *hsubghz); +void HAL_SUBGHZ_CADStatusCallback(SUBGHZ_HandleTypeDef *hsubghz, HAL_SUBGHZ_CadStatusTypeDef cadstatus); +void HAL_SUBGHZ_RxTxTimeoutCallback(SUBGHZ_HandleTypeDef *hsubghz); +void HAL_SUBGHZ_LrFhssHopCallback(SUBGHZ_HandleTypeDef *hsubghz); +/** + * @} + */ + +/** @addtogroup SUBGHZ_Exported_Functions_Group3 + * @{ + */ +/* Peripheral State and Error functions ***************************************/ +HAL_SUBGHZ_StateTypeDef HAL_SUBGHZ_GetState(const SUBGHZ_HandleTypeDef *hsubghz); +uint32_t HAL_SUBGHZ_GetError(const SUBGHZ_HandleTypeDef *hsubghz); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32WLxx_HAL_SUBGHZ_H */ + diff --git a/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h b/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h new file mode 100644 index 0000000..94f4a63 --- /dev/null +++ b/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h @@ -0,0 +1,1743 @@ +/** + ****************************************************************************** + * @file stm32wlxx_hal_uart.h + * @author MCD Application Team + * @brief Header file of UART HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32WLxx_HAL_UART_H +#define STM32WLxx_HAL_UART_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wlxx_hal_def.h" + +/** @addtogroup STM32WLxx_HAL_Driver + * @{ + */ + +/** @addtogroup UART + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup UART_Exported_Types UART Exported Types + * @{ + */ + +/** + * @brief UART Init Structure definition + */ +typedef struct +{ + uint32_t BaudRate; /*!< This member configures the UART communication baud rate. + The baud rate register is computed using the following formula: + @note For LPUART : + Baud Rate Register = ((256 * lpuart_ker_ckpres) / ((huart->Init.BaudRate))) + where lpuart_ker_ck_pres is the UART input clock divided by a prescaler. + @note For UART : + - If oversampling is 16 or in LIN mode, + Baud Rate Register = ((uart_ker_ckpres) / ((huart->Init.BaudRate))) + - If oversampling is 8, + Baud Rate Register[15:4] = ((2 * uart_ker_ckpres) / + ((huart->Init.BaudRate)))[15:4] + Baud Rate Register[3] = 0 + Baud Rate Register[2:0] = (((2 * uart_ker_ckpres) / + ((huart->Init.BaudRate)))[3:0]) >> 1 + where uart_ker_ck_pres is the UART input clock divided by a prescaler */ + + uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. + This parameter can be a value of @ref UARTEx_Word_Length. */ + + uint32_t StopBits; /*!< Specifies the number of stop bits transmitted. + This parameter can be a value of @ref UART_Stop_Bits. */ + + uint32_t Parity; /*!< Specifies the parity mode. + This parameter can be a value of @ref UART_Parity + @note When parity is enabled, the computed parity is inserted + at the MSB position of the transmitted data (9th bit when + the word length is set to 9 data bits; 8th bit when the + word length is set to 8 data bits). */ + + uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled. + This parameter can be a value of @ref UART_Mode. */ + + uint32_t HwFlowCtl; /*!< Specifies whether the hardware flow control mode is enabled + or disabled. + This parameter can be a value of @ref UART_Hardware_Flow_Control. */ + + uint32_t OverSampling; /*!< Specifies whether the Over sampling 8 is enabled or disabled, + to achieve higher speed (up to f_PCLK/8). + This parameter can be a value of @ref UART_Over_Sampling. */ + + uint32_t OneBitSampling; /*!< Specifies whether a single sample or three samples' majority vote is selected. + Selecting the single sample method increases the receiver tolerance to clock + deviations. This parameter can be a value of @ref UART_OneBit_Sampling. */ + + uint32_t ClockPrescaler; /*!< Specifies the prescaler value used to divide the UART clock source. + This parameter can be a value of @ref UART_ClockPrescaler. */ + +} UART_InitTypeDef; + +/** + * @brief UART Advanced Features initialization structure definition + */ +typedef struct +{ + uint32_t AdvFeatureInit; /*!< Specifies which advanced UART features is initialized. Several + Advanced Features may be initialized at the same time . + This parameter can be a value of + @ref UART_Advanced_Features_Initialization_Type. */ + + uint32_t TxPinLevelInvert; /*!< Specifies whether the TX pin active level is inverted. + This parameter can be a value of @ref UART_Tx_Inv. */ + + uint32_t RxPinLevelInvert; /*!< Specifies whether the RX pin active level is inverted. + This parameter can be a value of @ref UART_Rx_Inv. */ + + uint32_t DataInvert; /*!< Specifies whether data are inverted (positive/direct logic + vs negative/inverted logic). + This parameter can be a value of @ref UART_Data_Inv. */ + + uint32_t Swap; /*!< Specifies whether TX and RX pins are swapped. + This parameter can be a value of @ref UART_Rx_Tx_Swap. */ + + uint32_t OverrunDisable; /*!< Specifies whether the reception overrun detection is disabled. + This parameter can be a value of @ref UART_Overrun_Disable. */ + + uint32_t DMADisableonRxError; /*!< Specifies whether the DMA is disabled in case of reception error. + This parameter can be a value of @ref UART_DMA_Disable_on_Rx_Error. */ + + uint32_t AutoBaudRateEnable; /*!< Specifies whether auto Baud rate detection is enabled. + This parameter can be a value of @ref UART_AutoBaudRate_Enable. */ + + uint32_t AutoBaudRateMode; /*!< If auto Baud rate detection is enabled, specifies how the rate + detection is carried out. + This parameter can be a value of @ref UART_AutoBaud_Rate_Mode. */ + + uint32_t MSBFirst; /*!< Specifies whether MSB is sent first on UART line. + This parameter can be a value of @ref UART_MSB_First. */ +} UART_AdvFeatureInitTypeDef; + +/** + * @brief HAL UART State definition + * @note HAL UART State value is a combination of 2 different substates: + * gState and RxState (see @ref UART_State_Definition). + * - gState contains UART state information related to global Handle management + * and also information related to Tx operations. + * gState value coding follow below described bitmap : + * b7-b6 Error information + * 00 : No Error + * 01 : (Not Used) + * 10 : Timeout + * 11 : Error + * b5 Peripheral initialization status + * 0 : Reset (Peripheral not initialized) + * 1 : Init done (Peripheral initialized. HAL UART Init function already called) + * b4-b3 (not used) + * xx : Should be set to 00 + * b2 Intrinsic process state + * 0 : Ready + * 1 : Busy (Peripheral busy with some configuration or internal operations) + * b1 (not used) + * x : Should be set to 0 + * b0 Tx state + * 0 : Ready (no Tx operation ongoing) + * 1 : Busy (Tx operation ongoing) + * - RxState contains information related to Rx operations. + * RxState value coding follow below described bitmap : + * b7-b6 (not used) + * xx : Should be set to 00 + * b5 Peripheral initialization status + * 0 : Reset (Peripheral not initialized) + * 1 : Init done (Peripheral initialized) + * b4-b2 (not used) + * xxx : Should be set to 000 + * b1 Rx state + * 0 : Ready (no Rx operation ongoing) + * 1 : Busy (Rx operation ongoing) + * b0 (not used) + * x : Should be set to 0. + */ +typedef uint32_t HAL_UART_StateTypeDef; + +/** + * @brief UART clock sources definition + */ +typedef enum +{ + UART_CLOCKSOURCE_PCLK1 = 0x00U, /*!< PCLK1 clock source */ + UART_CLOCKSOURCE_PCLK2 = 0x01U, /*!< PCLK2 clock source */ + UART_CLOCKSOURCE_HSI = 0x02U, /*!< HSI clock source */ + UART_CLOCKSOURCE_SYSCLK = 0x04U, /*!< SYSCLK clock source */ + UART_CLOCKSOURCE_LSE = 0x08U, /*!< LSE clock source */ + UART_CLOCKSOURCE_UNDEFINED = 0x10U /*!< Undefined clock source */ +} UART_ClockSourceTypeDef; + +/** + * @brief HAL UART Reception type definition + * @note HAL UART Reception type value aims to identify which type of Reception is ongoing. + * This parameter can be a value of @ref UART_Reception_Type_Values : + * HAL_UART_RECEPTION_STANDARD = 0x00U, + * HAL_UART_RECEPTION_TOIDLE = 0x01U, + * HAL_UART_RECEPTION_TORTO = 0x02U, + * HAL_UART_RECEPTION_TOCHARMATCH = 0x03U, + */ +typedef uint32_t HAL_UART_RxTypeTypeDef; + +/** + * @brief HAL UART Rx Event type definition + * @note HAL UART Rx Event type value aims to identify which type of Event has occurred + * leading to call of the RxEvent callback. + * This parameter can be a value of @ref UART_RxEvent_Type_Values : + * HAL_UART_RXEVENT_TC = 0x00U, + * HAL_UART_RXEVENT_HT = 0x01U, + * HAL_UART_RXEVENT_IDLE = 0x02U, + */ +typedef uint32_t HAL_UART_RxEventTypeTypeDef; + +/** + * @brief UART handle Structure definition + */ +typedef struct __UART_HandleTypeDef +{ + USART_TypeDef *Instance; /*!< UART registers base address */ + + UART_InitTypeDef Init; /*!< UART communication parameters */ + + UART_AdvFeatureInitTypeDef AdvancedInit; /*!< UART Advanced Features initialization parameters */ + + const uint8_t *pTxBuffPtr; /*!< Pointer to UART Tx transfer Buffer */ + + uint16_t TxXferSize; /*!< UART Tx Transfer size */ + + __IO uint16_t TxXferCount; /*!< UART Tx Transfer Counter */ + + uint8_t *pRxBuffPtr; /*!< Pointer to UART Rx transfer Buffer */ + + uint16_t RxXferSize; /*!< UART Rx Transfer size */ + + __IO uint16_t RxXferCount; /*!< UART Rx Transfer Counter */ + + uint16_t Mask; /*!< UART Rx RDR register mask */ + + uint32_t FifoMode; /*!< Specifies if the FIFO mode is being used. + This parameter can be a value of @ref UARTEx_FIFO_mode. */ + + uint16_t NbRxDataToProcess; /*!< Number of data to process during RX ISR execution */ + + uint16_t NbTxDataToProcess; /*!< Number of data to process during TX ISR execution */ + + __IO HAL_UART_RxTypeTypeDef ReceptionType; /*!< Type of ongoing reception */ + + __IO HAL_UART_RxEventTypeTypeDef RxEventType; /*!< Type of Rx Event */ + + void (*RxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Rx IRQ handler */ + + void (*TxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Tx IRQ handler */ + + DMA_HandleTypeDef *hdmatx; /*!< UART Tx DMA Handle parameters */ + + DMA_HandleTypeDef *hdmarx; /*!< UART Rx DMA Handle parameters */ + + HAL_LockTypeDef Lock; /*!< Locking object */ + + __IO HAL_UART_StateTypeDef gState; /*!< UART state information related to global Handle management + and also related to Tx operations. This parameter + can be a value of @ref HAL_UART_StateTypeDef */ + + __IO HAL_UART_StateTypeDef RxState; /*!< UART state information related to Rx operations. This + parameter can be a value of @ref HAL_UART_StateTypeDef */ + + __IO uint32_t ErrorCode; /*!< UART Error code */ + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + void (* TxHalfCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Tx Half Complete Callback */ + void (* TxCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Tx Complete Callback */ + void (* RxHalfCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Rx Half Complete Callback */ + void (* RxCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Rx Complete Callback */ + void (* ErrorCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Error Callback */ + void (* AbortCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Complete Callback */ + void (* AbortTransmitCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Transmit Complete Callback */ + void (* AbortReceiveCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Receive Complete Callback */ + void (* WakeupCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Wakeup Callback */ + void (* RxFifoFullCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Rx Fifo Full Callback */ + void (* TxFifoEmptyCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Tx Fifo Empty Callback */ + void (* RxEventCallback)(struct __UART_HandleTypeDef *huart, uint16_t Pos); /*!< UART Reception Event Callback */ + + void (* MspInitCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Msp Init callback */ + void (* MspDeInitCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Msp DeInit callback */ +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + +} UART_HandleTypeDef; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +/** + * @brief HAL UART Callback ID enumeration definition + */ +typedef enum +{ + HAL_UART_TX_HALFCOMPLETE_CB_ID = 0x00U, /*!< UART Tx Half Complete Callback ID */ + HAL_UART_TX_COMPLETE_CB_ID = 0x01U, /*!< UART Tx Complete Callback ID */ + HAL_UART_RX_HALFCOMPLETE_CB_ID = 0x02U, /*!< UART Rx Half Complete Callback ID */ + HAL_UART_RX_COMPLETE_CB_ID = 0x03U, /*!< UART Rx Complete Callback ID */ + HAL_UART_ERROR_CB_ID = 0x04U, /*!< UART Error Callback ID */ + HAL_UART_ABORT_COMPLETE_CB_ID = 0x05U, /*!< UART Abort Complete Callback ID */ + HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x06U, /*!< UART Abort Transmit Complete Callback ID */ + HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID = 0x07U, /*!< UART Abort Receive Complete Callback ID */ + HAL_UART_WAKEUP_CB_ID = 0x08U, /*!< UART Wakeup Callback ID */ + HAL_UART_RX_FIFO_FULL_CB_ID = 0x09U, /*!< UART Rx Fifo Full Callback ID */ + HAL_UART_TX_FIFO_EMPTY_CB_ID = 0x0AU, /*!< UART Tx Fifo Empty Callback ID */ + + HAL_UART_MSPINIT_CB_ID = 0x0BU, /*!< UART MspInit callback ID */ + HAL_UART_MSPDEINIT_CB_ID = 0x0CU /*!< UART MspDeInit callback ID */ + +} HAL_UART_CallbackIDTypeDef; + +/** + * @brief HAL UART Callback pointer definition + */ +typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer to an UART callback function */ +typedef void (*pUART_RxEventCallbackTypeDef) +(struct __UART_HandleTypeDef *huart, uint16_t Pos); /*!< pointer to a UART Rx Event specific callback function */ + +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup UART_Exported_Constants UART Exported Constants + * @{ + */ + +/** @defgroup UART_State_Definition UART State Code Definition + * @{ + */ +#define HAL_UART_STATE_RESET 0x00000000U /*!< Peripheral is not initialized + Value is allowed for gState and RxState */ +#define HAL_UART_STATE_READY 0x00000020U /*!< Peripheral Initialized and ready for use + Value is allowed for gState and RxState */ +#define HAL_UART_STATE_BUSY 0x00000024U /*!< an internal process is ongoing + Value is allowed for gState only */ +#define HAL_UART_STATE_BUSY_TX 0x00000021U /*!< Data Transmission process is ongoing + Value is allowed for gState only */ +#define HAL_UART_STATE_BUSY_RX 0x00000022U /*!< Data Reception process is ongoing + Value is allowed for RxState only */ +#define HAL_UART_STATE_BUSY_TX_RX 0x00000023U /*!< Data Transmission and Reception process is ongoing + Not to be used for neither gState nor RxState.Value is result + of combination (Or) between gState and RxState values */ +#define HAL_UART_STATE_TIMEOUT 0x000000A0U /*!< Timeout state + Value is allowed for gState only */ +#define HAL_UART_STATE_ERROR 0x000000E0U /*!< Error + Value is allowed for gState only */ +/** + * @} + */ + +/** @defgroup UART_Error_Definition UART Error Definition + * @{ + */ +#define HAL_UART_ERROR_NONE (0x00000000U) /*!< No error */ +#define HAL_UART_ERROR_PE (0x00000001U) /*!< Parity error */ +#define HAL_UART_ERROR_NE (0x00000002U) /*!< Noise error */ +#define HAL_UART_ERROR_FE (0x00000004U) /*!< Frame error */ +#define HAL_UART_ERROR_ORE (0x00000008U) /*!< Overrun error */ +#define HAL_UART_ERROR_DMA (0x00000010U) /*!< DMA transfer error */ +#define HAL_UART_ERROR_RTO (0x00000020U) /*!< Receiver Timeout error */ + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +#define HAL_UART_ERROR_INVALID_CALLBACK (0x00000040U) /*!< Invalid Callback error */ +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @defgroup UART_Stop_Bits UART Number of Stop Bits + * @{ + */ +#define UART_STOPBITS_0_5 USART_CR2_STOP_0 /*!< UART frame with 0.5 stop bit */ +#define UART_STOPBITS_1 0x00000000U /*!< UART frame with 1 stop bit */ +#define UART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1) /*!< UART frame with 1.5 stop bits */ +#define UART_STOPBITS_2 USART_CR2_STOP_1 /*!< UART frame with 2 stop bits */ +/** + * @} + */ + +/** @defgroup UART_Parity UART Parity + * @{ + */ +#define UART_PARITY_NONE 0x00000000U /*!< No parity */ +#define UART_PARITY_EVEN USART_CR1_PCE /*!< Even parity */ +#define UART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Odd parity */ +/** + * @} + */ + +/** @defgroup UART_Hardware_Flow_Control UART Hardware Flow Control + * @{ + */ +#define UART_HWCONTROL_NONE 0x00000000U /*!< No hardware control */ +#define UART_HWCONTROL_RTS USART_CR3_RTSE /*!< Request To Send */ +#define UART_HWCONTROL_CTS USART_CR3_CTSE /*!< Clear To Send */ +#define UART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) /*!< Request and Clear To Send */ +/** + * @} + */ + +/** @defgroup UART_Mode UART Transfer Mode + * @{ + */ +#define UART_MODE_RX USART_CR1_RE /*!< RX mode */ +#define UART_MODE_TX USART_CR1_TE /*!< TX mode */ +#define UART_MODE_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< RX and TX mode */ +/** + * @} + */ + +/** @defgroup UART_State UART State + * @{ + */ +#define UART_STATE_DISABLE 0x00000000U /*!< UART disabled */ +#define UART_STATE_ENABLE USART_CR1_UE /*!< UART enabled */ +/** + * @} + */ + +/** @defgroup UART_Over_Sampling UART Over Sampling + * @{ + */ +#define UART_OVERSAMPLING_16 0x00000000U /*!< Oversampling by 16 */ +#define UART_OVERSAMPLING_8 USART_CR1_OVER8 /*!< Oversampling by 8 */ +/** + * @} + */ + +/** @defgroup UART_OneBit_Sampling UART One Bit Sampling Method + * @{ + */ +#define UART_ONE_BIT_SAMPLE_DISABLE 0x00000000U /*!< One-bit sampling disable */ +#define UART_ONE_BIT_SAMPLE_ENABLE USART_CR3_ONEBIT /*!< One-bit sampling enable */ +/** + * @} + */ + +/** @defgroup UART_ClockPrescaler UART Clock Prescaler + * @{ + */ +#define UART_PRESCALER_DIV1 0x00000000U /*!< fclk_pres = fclk */ +#define UART_PRESCALER_DIV2 0x00000001U /*!< fclk_pres = fclk/2 */ +#define UART_PRESCALER_DIV4 0x00000002U /*!< fclk_pres = fclk/4 */ +#define UART_PRESCALER_DIV6 0x00000003U /*!< fclk_pres = fclk/6 */ +#define UART_PRESCALER_DIV8 0x00000004U /*!< fclk_pres = fclk/8 */ +#define UART_PRESCALER_DIV10 0x00000005U /*!< fclk_pres = fclk/10 */ +#define UART_PRESCALER_DIV12 0x00000006U /*!< fclk_pres = fclk/12 */ +#define UART_PRESCALER_DIV16 0x00000007U /*!< fclk_pres = fclk/16 */ +#define UART_PRESCALER_DIV32 0x00000008U /*!< fclk_pres = fclk/32 */ +#define UART_PRESCALER_DIV64 0x00000009U /*!< fclk_pres = fclk/64 */ +#define UART_PRESCALER_DIV128 0x0000000AU /*!< fclk_pres = fclk/128 */ +#define UART_PRESCALER_DIV256 0x0000000BU /*!< fclk_pres = fclk/256 */ +/** + * @} + */ + +/** @defgroup UART_AutoBaud_Rate_Mode UART Advanced Feature AutoBaud Rate Mode + * @{ + */ +#define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT 0x00000000U /*!< Auto Baud rate detection + on start bit */ +#define UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE USART_CR2_ABRMODE_0 /*!< Auto Baud rate detection + on falling edge */ +#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME USART_CR2_ABRMODE_1 /*!< Auto Baud rate detection + on 0x7F frame detection */ +#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME USART_CR2_ABRMODE /*!< Auto Baud rate detection + on 0x55 frame detection */ +/** + * @} + */ + +/** @defgroup UART_Receiver_Timeout UART Receiver Timeout + * @{ + */ +#define UART_RECEIVER_TIMEOUT_DISABLE 0x00000000U /*!< UART Receiver Timeout disable */ +#define UART_RECEIVER_TIMEOUT_ENABLE USART_CR2_RTOEN /*!< UART Receiver Timeout enable */ +/** + * @} + */ + +/** @defgroup UART_LIN UART Local Interconnection Network mode + * @{ + */ +#define UART_LIN_DISABLE 0x00000000U /*!< Local Interconnect Network disable */ +#define UART_LIN_ENABLE USART_CR2_LINEN /*!< Local Interconnect Network enable */ +/** + * @} + */ + +/** @defgroup UART_LIN_Break_Detection UART LIN Break Detection + * @{ + */ +#define UART_LINBREAKDETECTLENGTH_10B 0x00000000U /*!< LIN 10-bit break detection length */ +#define UART_LINBREAKDETECTLENGTH_11B USART_CR2_LBDL /*!< LIN 11-bit break detection length */ +/** + * @} + */ + +/** @defgroup UART_DMA_Tx UART DMA Tx + * @{ + */ +#define UART_DMA_TX_DISABLE 0x00000000U /*!< UART DMA TX disabled */ +#define UART_DMA_TX_ENABLE USART_CR3_DMAT /*!< UART DMA TX enabled */ +/** + * @} + */ + +/** @defgroup UART_DMA_Rx UART DMA Rx + * @{ + */ +#define UART_DMA_RX_DISABLE 0x00000000U /*!< UART DMA RX disabled */ +#define UART_DMA_RX_ENABLE USART_CR3_DMAR /*!< UART DMA RX enabled */ +/** + * @} + */ + +/** @defgroup UART_Half_Duplex_Selection UART Half Duplex Selection + * @{ + */ +#define UART_HALF_DUPLEX_DISABLE 0x00000000U /*!< UART half-duplex disabled */ +#define UART_HALF_DUPLEX_ENABLE USART_CR3_HDSEL /*!< UART half-duplex enabled */ +/** + * @} + */ + +/** @defgroup UART_WakeUp_Methods UART WakeUp Methods + * @{ + */ +#define UART_WAKEUPMETHOD_IDLELINE 0x00000000U /*!< UART wake-up on idle line */ +#define UART_WAKEUPMETHOD_ADDRESSMARK USART_CR1_WAKE /*!< UART wake-up on address mark */ +/** + * @} + */ + +/** @defgroup UART_Request_Parameters UART Request Parameters + * @{ + */ +#define UART_AUTOBAUD_REQUEST USART_RQR_ABRRQ /*!< Auto-Baud Rate Request */ +#define UART_SENDBREAK_REQUEST USART_RQR_SBKRQ /*!< Send Break Request */ +#define UART_MUTE_MODE_REQUEST USART_RQR_MMRQ /*!< Mute Mode Request */ +#define UART_RXDATA_FLUSH_REQUEST USART_RQR_RXFRQ /*!< Receive Data flush Request */ +#define UART_TXDATA_FLUSH_REQUEST USART_RQR_TXFRQ /*!< Transmit data flush Request */ +/** + * @} + */ + +/** @defgroup UART_Advanced_Features_Initialization_Type UART Advanced Feature Initialization Type + * @{ + */ +#define UART_ADVFEATURE_NO_INIT 0x00000000U /*!< No advanced feature initialization */ +#define UART_ADVFEATURE_TXINVERT_INIT 0x00000001U /*!< TX pin active level inversion */ +#define UART_ADVFEATURE_RXINVERT_INIT 0x00000002U /*!< RX pin active level inversion */ +#define UART_ADVFEATURE_DATAINVERT_INIT 0x00000004U /*!< Binary data inversion */ +#define UART_ADVFEATURE_SWAP_INIT 0x00000008U /*!< TX/RX pins swap */ +#define UART_ADVFEATURE_RXOVERRUNDISABLE_INIT 0x00000010U /*!< RX overrun disable */ +#define UART_ADVFEATURE_DMADISABLEONERROR_INIT 0x00000020U /*!< DMA disable on Reception Error */ +#define UART_ADVFEATURE_AUTOBAUDRATE_INIT 0x00000040U /*!< Auto Baud rate detection initialization */ +#define UART_ADVFEATURE_MSBFIRST_INIT 0x00000080U /*!< Most significant bit sent/received first */ +/** + * @} + */ + +/** @defgroup UART_Tx_Inv UART Advanced Feature TX Pin Active Level Inversion + * @{ + */ +#define UART_ADVFEATURE_TXINV_DISABLE 0x00000000U /*!< TX pin active level inversion disable */ +#define UART_ADVFEATURE_TXINV_ENABLE USART_CR2_TXINV /*!< TX pin active level inversion enable */ +/** + * @} + */ + +/** @defgroup UART_Rx_Inv UART Advanced Feature RX Pin Active Level Inversion + * @{ + */ +#define UART_ADVFEATURE_RXINV_DISABLE 0x00000000U /*!< RX pin active level inversion disable */ +#define UART_ADVFEATURE_RXINV_ENABLE USART_CR2_RXINV /*!< RX pin active level inversion enable */ +/** + * @} + */ + +/** @defgroup UART_Data_Inv UART Advanced Feature Binary Data Inversion + * @{ + */ +#define UART_ADVFEATURE_DATAINV_DISABLE 0x00000000U /*!< Binary data inversion disable */ +#define UART_ADVFEATURE_DATAINV_ENABLE USART_CR2_DATAINV /*!< Binary data inversion enable */ +/** + * @} + */ + +/** @defgroup UART_Rx_Tx_Swap UART Advanced Feature RX TX Pins Swap + * @{ + */ +#define UART_ADVFEATURE_SWAP_DISABLE 0x00000000U /*!< TX/RX pins swap disable */ +#define UART_ADVFEATURE_SWAP_ENABLE USART_CR2_SWAP /*!< TX/RX pins swap enable */ +/** + * @} + */ + +/** @defgroup UART_Overrun_Disable UART Advanced Feature Overrun Disable + * @{ + */ +#define UART_ADVFEATURE_OVERRUN_ENABLE 0x00000000U /*!< RX overrun enable */ +#define UART_ADVFEATURE_OVERRUN_DISABLE USART_CR3_OVRDIS /*!< RX overrun disable */ +/** + * @} + */ + +/** @defgroup UART_AutoBaudRate_Enable UART Advanced Feature Auto BaudRate Enable + * @{ + */ +#define UART_ADVFEATURE_AUTOBAUDRATE_DISABLE 0x00000000U /*!< RX Auto Baud rate detection enable */ +#define UART_ADVFEATURE_AUTOBAUDRATE_ENABLE USART_CR2_ABREN /*!< RX Auto Baud rate detection disable */ +/** + * @} + */ + +/** @defgroup UART_DMA_Disable_on_Rx_Error UART Advanced Feature DMA Disable On Rx Error + * @{ + */ +#define UART_ADVFEATURE_DMA_ENABLEONRXERROR 0x00000000U /*!< DMA enable on Reception Error */ +#define UART_ADVFEATURE_DMA_DISABLEONRXERROR USART_CR3_DDRE /*!< DMA disable on Reception Error */ +/** + * @} + */ + +/** @defgroup UART_MSB_First UART Advanced Feature MSB First + * @{ + */ +#define UART_ADVFEATURE_MSBFIRST_DISABLE 0x00000000U /*!< Most significant bit sent/received + first disable */ +#define UART_ADVFEATURE_MSBFIRST_ENABLE USART_CR2_MSBFIRST /*!< Most significant bit sent/received + first enable */ +/** + * @} + */ + +/** @defgroup UART_Stop_Mode_Enable UART Advanced Feature Stop Mode Enable + * @{ + */ +#define UART_ADVFEATURE_STOPMODE_DISABLE 0x00000000U /*!< UART stop mode disable */ +#define UART_ADVFEATURE_STOPMODE_ENABLE USART_CR1_UESM /*!< UART stop mode enable */ +/** + * @} + */ + +/** @defgroup UART_Mute_Mode UART Advanced Feature Mute Mode Enable + * @{ + */ +#define UART_ADVFEATURE_MUTEMODE_DISABLE 0x00000000U /*!< UART mute mode disable */ +#define UART_ADVFEATURE_MUTEMODE_ENABLE USART_CR1_MME /*!< UART mute mode enable */ +/** + * @} + */ + +/** @defgroup UART_CR2_ADDRESS_LSB_POS UART Address-matching LSB Position In CR2 Register + * @{ + */ +#define UART_CR2_ADDRESS_LSB_POS 24U /*!< UART address-matching LSB position in CR2 register */ +/** + * @} + */ + +/** @defgroup UART_WakeUp_from_Stop_Selection UART WakeUp From Stop Selection + * @{ + */ +#define UART_WAKEUP_ON_ADDRESS 0x00000000U /*!< UART wake-up on address */ +#define UART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1 /*!< UART wake-up on start bit */ +#define UART_WAKEUP_ON_READDATA_NONEMPTY USART_CR3_WUS /*!< UART wake-up on receive data register + not empty or RXFIFO is not empty */ +/** + * @} + */ + +/** @defgroup UART_DriverEnable_Polarity UART DriverEnable Polarity + * @{ + */ +#define UART_DE_POLARITY_HIGH 0x00000000U /*!< Driver enable signal is active high */ +#define UART_DE_POLARITY_LOW USART_CR3_DEP /*!< Driver enable signal is active low */ +/** + * @} + */ + +/** @defgroup UART_CR1_DEAT_ADDRESS_LSB_POS UART Driver Enable Assertion Time LSB Position In CR1 Register + * @{ + */ +#define UART_CR1_DEAT_ADDRESS_LSB_POS 21U /*!< UART Driver Enable assertion time LSB + position in CR1 register */ +/** + * @} + */ + +/** @defgroup UART_CR1_DEDT_ADDRESS_LSB_POS UART Driver Enable DeAssertion Time LSB Position In CR1 Register + * @{ + */ +#define UART_CR1_DEDT_ADDRESS_LSB_POS 16U /*!< UART Driver Enable de-assertion time LSB + position in CR1 register */ +/** + * @} + */ + +/** @defgroup UART_Interruption_Mask UART Interruptions Flag Mask + * @{ + */ +#define UART_IT_MASK 0x001FU /*!< UART interruptions flags mask */ +/** + * @} + */ + +/** @defgroup UART_TimeOut_Value UART polling-based communications time-out value + * @{ + */ +#define HAL_UART_TIMEOUT_VALUE 0x1FFFFFFU /*!< UART polling-based communications time-out value */ +/** + * @} + */ + +/** @defgroup UART_Flags UART Status Flags + * Elements values convention: 0xXXXX + * - 0xXXXX : Flag mask in the ISR register + * @{ + */ +#define UART_FLAG_TXFT USART_ISR_TXFT /*!< UART TXFIFO threshold flag */ +#define UART_FLAG_RXFT USART_ISR_RXFT /*!< UART RXFIFO threshold flag */ +#define UART_FLAG_RXFF USART_ISR_RXFF /*!< UART RXFIFO Full flag */ +#define UART_FLAG_TXFE USART_ISR_TXFE /*!< UART TXFIFO Empty flag */ +#define UART_FLAG_REACK USART_ISR_REACK /*!< UART receive enable acknowledge flag */ +#define UART_FLAG_TEACK USART_ISR_TEACK /*!< UART transmit enable acknowledge flag */ +#define UART_FLAG_WUF USART_ISR_WUF /*!< UART wake-up from stop mode flag */ +#define UART_FLAG_RWU USART_ISR_RWU /*!< UART receiver wake-up from mute mode flag */ +#define UART_FLAG_SBKF USART_ISR_SBKF /*!< UART send break flag */ +#define UART_FLAG_CMF USART_ISR_CMF /*!< UART character match flag */ +#define UART_FLAG_BUSY USART_ISR_BUSY /*!< UART busy flag */ +#define UART_FLAG_ABRF USART_ISR_ABRF /*!< UART auto Baud rate flag */ +#define UART_FLAG_ABRE USART_ISR_ABRE /*!< UART auto Baud rate error */ +#define UART_FLAG_RTOF USART_ISR_RTOF /*!< UART receiver timeout flag */ +#define UART_FLAG_CTS USART_ISR_CTS /*!< UART clear to send flag */ +#define UART_FLAG_CTSIF USART_ISR_CTSIF /*!< UART clear to send interrupt flag */ +#define UART_FLAG_LBDF USART_ISR_LBDF /*!< UART LIN break detection flag */ +#define UART_FLAG_TXE USART_ISR_TXE_TXFNF /*!< UART transmit data register empty */ +#define UART_FLAG_TXFNF USART_ISR_TXE_TXFNF /*!< UART TXFIFO not full */ +#define UART_FLAG_TC USART_ISR_TC /*!< UART transmission complete */ +#define UART_FLAG_RXNE USART_ISR_RXNE_RXFNE /*!< UART read data register not empty */ +#define UART_FLAG_RXFNE USART_ISR_RXNE_RXFNE /*!< UART RXFIFO not empty */ +#define UART_FLAG_IDLE USART_ISR_IDLE /*!< UART idle flag */ +#define UART_FLAG_ORE USART_ISR_ORE /*!< UART overrun error */ +#define UART_FLAG_NE USART_ISR_NE /*!< UART noise error */ +#define UART_FLAG_FE USART_ISR_FE /*!< UART frame error */ +#define UART_FLAG_PE USART_ISR_PE /*!< UART parity error */ +/** + * @} + */ + +/** @defgroup UART_Interrupt_definition UART Interrupts Definition + * Elements values convention: 000ZZZZZ0XXYYYYYb + * - YYYYY : Interrupt source position in the XX register (5bits) + * - XX : Interrupt source register (2bits) + * - 01: CR1 register + * - 10: CR2 register + * - 11: CR3 register + * - ZZZZZ : Flag position in the ISR register(5bits) + * Elements values convention: 000000000XXYYYYYb + * - YYYYY : Interrupt source position in the XX register (5bits) + * - XX : Interrupt source register (2bits) + * - 01: CR1 register + * - 10: CR2 register + * - 11: CR3 register + * Elements values convention: 0000ZZZZ00000000b + * - ZZZZ : Flag position in the ISR register(4bits) + * @{ + */ +#define UART_IT_PE 0x0028U /*!< UART parity error interruption */ +#define UART_IT_TXE 0x0727U /*!< UART transmit data register empty interruption */ +#define UART_IT_TXFNF 0x0727U /*!< UART TX FIFO not full interruption */ +#define UART_IT_TC 0x0626U /*!< UART transmission complete interruption */ +#define UART_IT_RXNE 0x0525U /*!< UART read data register not empty interruption */ +#define UART_IT_RXFNE 0x0525U /*!< UART RXFIFO not empty interruption */ +#define UART_IT_IDLE 0x0424U /*!< UART idle interruption */ +#define UART_IT_LBD 0x0846U /*!< UART LIN break detection interruption */ +#define UART_IT_CTS 0x096AU /*!< UART CTS interruption */ +#define UART_IT_CM 0x112EU /*!< UART character match interruption */ +#define UART_IT_WUF 0x1476U /*!< UART wake-up from stop mode interruption */ +#define UART_IT_RXFF 0x183FU /*!< UART RXFIFO full interruption */ +#define UART_IT_TXFE 0x173EU /*!< UART TXFIFO empty interruption */ +#define UART_IT_RXFT 0x1A7CU /*!< UART RXFIFO threshold reached interruption */ +#define UART_IT_TXFT 0x1B77U /*!< UART TXFIFO threshold reached interruption */ +#define UART_IT_RTO 0x0B3AU /*!< UART receiver timeout interruption */ + +#define UART_IT_ERR 0x0060U /*!< UART error interruption */ + +#define UART_IT_ORE 0x0300U /*!< UART overrun error interruption */ +#define UART_IT_NE 0x0200U /*!< UART noise error interruption */ +#define UART_IT_FE 0x0100U /*!< UART frame error interruption */ +/** + * @} + */ + +/** @defgroup UART_IT_CLEAR_Flags UART Interruption Clear Flags + * @{ + */ +#define UART_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */ +#define UART_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */ +#define UART_CLEAR_NEF USART_ICR_NECF /*!< Noise Error detected Clear Flag */ +#define UART_CLEAR_OREF USART_ICR_ORECF /*!< Overrun Error Clear Flag */ +#define UART_CLEAR_IDLEF USART_ICR_IDLECF /*!< IDLE line detected Clear Flag */ +#define UART_CLEAR_TXFECF USART_ICR_TXFECF /*!< TXFIFO empty clear flag */ +#define UART_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */ +#define UART_CLEAR_LBDF USART_ICR_LBDCF /*!< LIN Break Detection Clear Flag */ +#define UART_CLEAR_CTSF USART_ICR_CTSCF /*!< CTS Interrupt Clear Flag */ +#define UART_CLEAR_CMF USART_ICR_CMCF /*!< Character Match Clear Flag */ +#define UART_CLEAR_WUF USART_ICR_WUCF /*!< Wake Up from stop mode Clear Flag */ +#define UART_CLEAR_RTOF USART_ICR_RTOCF /*!< UART receiver timeout clear flag */ +/** + * @} + */ + +/** @defgroup UART_Reception_Type_Values UART Reception type values + * @{ + */ +#define HAL_UART_RECEPTION_STANDARD (0x00000000U) /*!< Standard reception */ +#define HAL_UART_RECEPTION_TOIDLE (0x00000001U) /*!< Reception till completion or IDLE event */ +#define HAL_UART_RECEPTION_TORTO (0x00000002U) /*!< Reception till completion or RTO event */ +#define HAL_UART_RECEPTION_TOCHARMATCH (0x00000003U) /*!< Reception till completion or CM event */ +/** + * @} + */ + +/** @defgroup UART_RxEvent_Type_Values UART RxEvent type values + * @{ + */ +#define HAL_UART_RXEVENT_TC (0x00000000U) /*!< RxEvent linked to Transfer Complete event */ +#define HAL_UART_RXEVENT_HT (0x00000001U) /*!< RxEvent linked to Half Transfer event */ +#define HAL_UART_RXEVENT_IDLE (0x00000002U) /*!< RxEvent linked to IDLE event */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup UART_Exported_Macros UART Exported Macros + * @{ + */ + +/** @brief Reset UART handle states. + * @param __HANDLE__ UART handle. + * @retval None + */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->gState = HAL_UART_STATE_RESET; \ + (__HANDLE__)->RxState = HAL_UART_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0U) +#else +#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->gState = HAL_UART_STATE_RESET; \ + (__HANDLE__)->RxState = HAL_UART_STATE_RESET; \ + } while(0U) +#endif /*USE_HAL_UART_REGISTER_CALLBACKS */ + +/** @brief Flush the UART Data registers. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__) \ + do{ \ + SET_BIT((__HANDLE__)->Instance->RQR, UART_RXDATA_FLUSH_REQUEST); \ + SET_BIT((__HANDLE__)->Instance->RQR, UART_TXDATA_FLUSH_REQUEST); \ + } while(0U) + +/** @brief Clear the specified UART pending flag. + * @param __HANDLE__ specifies the UART Handle. + * @param __FLAG__ specifies the flag to check. + * This parameter can be any combination of the following values: + * @arg @ref UART_CLEAR_PEF Parity Error Clear Flag + * @arg @ref UART_CLEAR_FEF Framing Error Clear Flag + * @arg @ref UART_CLEAR_NEF Noise detected Clear Flag + * @arg @ref UART_CLEAR_OREF Overrun Error Clear Flag + * @arg @ref UART_CLEAR_IDLEF IDLE line detected Clear Flag + * @arg @ref UART_CLEAR_TXFECF TXFIFO empty clear Flag + * @arg @ref UART_CLEAR_TCF Transmission Complete Clear Flag + * @arg @ref UART_CLEAR_RTOF Receiver Timeout clear flag + * @arg @ref UART_CLEAR_LBDF LIN Break Detection Clear Flag + * @arg @ref UART_CLEAR_CTSF CTS Interrupt Clear Flag + * @arg @ref UART_CLEAR_CMF Character Match Clear Flag + * @arg @ref UART_CLEAR_WUF Wake Up from stop mode Clear Flag + * @retval None + */ +#define __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) + +/** @brief Clear the UART PE pending flag. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_CLEAR_PEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_PEF) + +/** @brief Clear the UART FE pending flag. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_CLEAR_FEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_FEF) + +/** @brief Clear the UART NE pending flag. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_CLEAR_NEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_NEF) + +/** @brief Clear the UART ORE pending flag. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_CLEAR_OREFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_OREF) + +/** @brief Clear the UART IDLE pending flag. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_IDLEF) + +/** @brief Clear the UART TX FIFO empty clear flag. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_CLEAR_TXFECF(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_TXFECF) + +/** @brief Check whether the specified UART flag is set or not. + * @param __HANDLE__ specifies the UART Handle. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg @ref UART_FLAG_TXFT TXFIFO threshold flag + * @arg @ref UART_FLAG_RXFT RXFIFO threshold flag + * @arg @ref UART_FLAG_RXFF RXFIFO Full flag + * @arg @ref UART_FLAG_TXFE TXFIFO Empty flag + * @arg @ref UART_FLAG_REACK Receive enable acknowledge flag + * @arg @ref UART_FLAG_TEACK Transmit enable acknowledge flag + * @arg @ref UART_FLAG_WUF Wake up from stop mode flag + * @arg @ref UART_FLAG_RWU Receiver wake up flag (if the UART in mute mode) + * @arg @ref UART_FLAG_SBKF Send Break flag + * @arg @ref UART_FLAG_CMF Character match flag + * @arg @ref UART_FLAG_BUSY Busy flag + * @arg @ref UART_FLAG_ABRF Auto Baud rate detection flag + * @arg @ref UART_FLAG_ABRE Auto Baud rate detection error flag + * @arg @ref UART_FLAG_CTS CTS Change flag + * @arg @ref UART_FLAG_LBDF LIN Break detection flag + * @arg @ref UART_FLAG_TXE Transmit data register empty flag + * @arg @ref UART_FLAG_TXFNF UART TXFIFO not full flag + * @arg @ref UART_FLAG_TC Transmission Complete flag + * @arg @ref UART_FLAG_RXNE Receive data register not empty flag + * @arg @ref UART_FLAG_RXFNE UART RXFIFO not empty flag + * @arg @ref UART_FLAG_RTOF Receiver Timeout flag + * @arg @ref UART_FLAG_IDLE Idle Line detection flag + * @arg @ref UART_FLAG_ORE Overrun Error flag + * @arg @ref UART_FLAG_NE Noise Error flag + * @arg @ref UART_FLAG_FE Framing Error flag + * @arg @ref UART_FLAG_PE Parity Error flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__)) + +/** @brief Enable the specified UART interrupt. + * @param __HANDLE__ specifies the UART Handle. + * @param __INTERRUPT__ specifies the UART interrupt source to enable. + * This parameter can be one of the following values: + * @arg @ref UART_IT_RXFF RXFIFO Full interrupt + * @arg @ref UART_IT_TXFE TXFIFO Empty interrupt + * @arg @ref UART_IT_RXFT RXFIFO threshold interrupt + * @arg @ref UART_IT_TXFT TXFIFO threshold interrupt + * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt + * @arg @ref UART_IT_CM Character match interrupt + * @arg @ref UART_IT_CTS CTS change interrupt + * @arg @ref UART_IT_LBD LIN Break detection interrupt + * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt + * @arg @ref UART_IT_TXFNF TX FIFO not full interrupt + * @arg @ref UART_IT_TC Transmission complete interrupt + * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt + * @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt + * @arg @ref UART_IT_RTO Receive Timeout interrupt + * @arg @ref UART_IT_IDLE Idle line detection interrupt + * @arg @ref UART_IT_PE Parity Error interrupt + * @arg @ref UART_IT_ERR Error interrupt (frame error, noise error, overrun error) + * @retval None + */ +#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (\ + ((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)?\ + ((__HANDLE__)->Instance->CR1 |= (1U <<\ + ((__INTERRUPT__) & UART_IT_MASK))): \ + ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)?\ + ((__HANDLE__)->Instance->CR2 |= (1U <<\ + ((__INTERRUPT__) & UART_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 |= (1U <<\ + ((__INTERRUPT__) & UART_IT_MASK)))) + +/** @brief Disable the specified UART interrupt. + * @param __HANDLE__ specifies the UART Handle. + * @param __INTERRUPT__ specifies the UART interrupt source to disable. + * This parameter can be one of the following values: + * @arg @ref UART_IT_RXFF RXFIFO Full interrupt + * @arg @ref UART_IT_TXFE TXFIFO Empty interrupt + * @arg @ref UART_IT_RXFT RXFIFO threshold interrupt + * @arg @ref UART_IT_TXFT TXFIFO threshold interrupt + * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt + * @arg @ref UART_IT_CM Character match interrupt + * @arg @ref UART_IT_CTS CTS change interrupt + * @arg @ref UART_IT_LBD LIN Break detection interrupt + * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt + * @arg @ref UART_IT_TXFNF TX FIFO not full interrupt + * @arg @ref UART_IT_TC Transmission complete interrupt + * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt + * @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt + * @arg @ref UART_IT_RTO Receive Timeout interrupt + * @arg @ref UART_IT_IDLE Idle line detection interrupt + * @arg @ref UART_IT_PE Parity Error interrupt + * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error) + * @retval None + */ +#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (\ + ((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)?\ + ((__HANDLE__)->Instance->CR1 &= ~ (1U <<\ + ((__INTERRUPT__) & UART_IT_MASK))): \ + ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)?\ + ((__HANDLE__)->Instance->CR2 &= ~ (1U <<\ + ((__INTERRUPT__) & UART_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 &= ~ (1U <<\ + ((__INTERRUPT__) & UART_IT_MASK)))) + +/** @brief Check whether the specified UART interrupt has occurred or not. + * @param __HANDLE__ specifies the UART Handle. + * @param __INTERRUPT__ specifies the UART interrupt to check. + * This parameter can be one of the following values: + * @arg @ref UART_IT_RXFF RXFIFO Full interrupt + * @arg @ref UART_IT_TXFE TXFIFO Empty interrupt + * @arg @ref UART_IT_RXFT RXFIFO threshold interrupt + * @arg @ref UART_IT_TXFT TXFIFO threshold interrupt + * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt + * @arg @ref UART_IT_CM Character match interrupt + * @arg @ref UART_IT_CTS CTS change interrupt + * @arg @ref UART_IT_LBD LIN Break detection interrupt + * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt + * @arg @ref UART_IT_TXFNF TX FIFO not full interrupt + * @arg @ref UART_IT_TC Transmission complete interrupt + * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt + * @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt + * @arg @ref UART_IT_RTO Receive Timeout interrupt + * @arg @ref UART_IT_IDLE Idle line detection interrupt + * @arg @ref UART_IT_PE Parity Error interrupt + * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error) + * @retval The new state of __INTERRUPT__ (SET or RESET). + */ +#define __HAL_UART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\ + & (1U << ((__INTERRUPT__)>> 8U))) != RESET) ? SET : RESET) + +/** @brief Check whether the specified UART interrupt source is enabled or not. + * @param __HANDLE__ specifies the UART Handle. + * @param __INTERRUPT__ specifies the UART interrupt source to check. + * This parameter can be one of the following values: + * @arg @ref UART_IT_RXFF RXFIFO Full interrupt + * @arg @ref UART_IT_TXFE TXFIFO Empty interrupt + * @arg @ref UART_IT_RXFT RXFIFO threshold interrupt + * @arg @ref UART_IT_TXFT TXFIFO threshold interrupt + * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt + * @arg @ref UART_IT_CM Character match interrupt + * @arg @ref UART_IT_CTS CTS change interrupt + * @arg @ref UART_IT_LBD LIN Break detection interrupt + * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt + * @arg @ref UART_IT_TXFNF TX FIFO not full interrupt + * @arg @ref UART_IT_TC Transmission complete interrupt + * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt + * @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt + * @arg @ref UART_IT_RTO Receive Timeout interrupt + * @arg @ref UART_IT_IDLE Idle line detection interrupt + * @arg @ref UART_IT_PE Parity Error interrupt + * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error) + * @retval The new state of __INTERRUPT__ (SET or RESET). + */ +#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U) ?\ + (__HANDLE__)->Instance->CR1 : \ + (((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U) ?\ + (__HANDLE__)->Instance->CR2 : \ + (__HANDLE__)->Instance->CR3)) & (1U <<\ + (((uint16_t)(__INTERRUPT__)) &\ + UART_IT_MASK))) != RESET) ? SET : RESET) + +/** @brief Clear the specified UART ISR flag, in setting the proper ICR register flag. + * @param __HANDLE__ specifies the UART Handle. + * @param __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set + * to clear the corresponding interrupt + * This parameter can be one of the following values: + * @arg @ref UART_CLEAR_PEF Parity Error Clear Flag + * @arg @ref UART_CLEAR_FEF Framing Error Clear Flag + * @arg @ref UART_CLEAR_NEF Noise detected Clear Flag + * @arg @ref UART_CLEAR_OREF Overrun Error Clear Flag + * @arg @ref UART_CLEAR_IDLEF IDLE line detected Clear Flag + * @arg @ref UART_CLEAR_RTOF Receiver timeout clear flag + * @arg @ref UART_CLEAR_TXFECF TXFIFO empty Clear Flag + * @arg @ref UART_CLEAR_TCF Transmission Complete Clear Flag + * @arg @ref UART_CLEAR_LBDF LIN Break Detection Clear Flag + * @arg @ref UART_CLEAR_CTSF CTS Interrupt Clear Flag + * @arg @ref UART_CLEAR_CMF Character Match Clear Flag + * @arg @ref UART_CLEAR_WUF Wake Up from stop mode Clear Flag + * @retval None + */ +#define __HAL_UART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__)) + +/** @brief Set a specific UART request flag. + * @param __HANDLE__ specifies the UART Handle. + * @param __REQ__ specifies the request flag to set + * This parameter can be one of the following values: + * @arg @ref UART_AUTOBAUD_REQUEST Auto-Baud Rate Request + * @arg @ref UART_SENDBREAK_REQUEST Send Break Request + * @arg @ref UART_MUTE_MODE_REQUEST Mute Mode Request + * @arg @ref UART_RXDATA_FLUSH_REQUEST Receive Data flush Request + * @arg @ref UART_TXDATA_FLUSH_REQUEST Transmit data flush Request + * @retval None + */ +#define __HAL_UART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__)) + +/** @brief Enable the UART one bit sample method. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT) + +/** @brief Disable the UART one bit sample method. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= ~USART_CR3_ONEBIT) + +/** @brief Enable UART. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE) + +/** @brief Disable UART. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE) + +/** @brief Enable CTS flow control. + * @note This macro allows to enable CTS hardware flow control for a given UART instance, + * without need to call HAL_UART_Init() function. + * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. + * @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need + * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : + * - UART instance should have already been initialised (through call of HAL_UART_Init() ) + * - macro could only be called when corresponding UART instance is disabled + * (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable + * macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__) \ + do{ \ + ATOMIC_SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \ + (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE; \ + } while(0U) + +/** @brief Disable CTS flow control. + * @note This macro allows to disable CTS hardware flow control for a given UART instance, + * without need to call HAL_UART_Init() function. + * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. + * @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need + * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : + * - UART instance should have already been initialised (through call of HAL_UART_Init() ) + * - macro could only be called when corresponding UART instance is disabled + * (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable + * macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__) \ + do{ \ + ATOMIC_CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \ + (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE); \ + } while(0U) + +/** @brief Enable RTS flow control. + * @note This macro allows to enable RTS hardware flow control for a given UART instance, + * without need to call HAL_UART_Init() function. + * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. + * @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need + * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : + * - UART instance should have already been initialised (through call of HAL_UART_Init() ) + * - macro could only be called when corresponding UART instance is disabled + * (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable + * macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__) \ + do{ \ + ATOMIC_SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \ + (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE; \ + } while(0U) + +/** @brief Disable RTS flow control. + * @note This macro allows to disable RTS hardware flow control for a given UART instance, + * without need to call HAL_UART_Init() function. + * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. + * @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need + * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : + * - UART instance should have already been initialised (through call of HAL_UART_Init() ) + * - macro could only be called when corresponding UART instance is disabled + * (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable + * macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__) \ + do{ \ + ATOMIC_CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\ + (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE); \ + } while(0U) +/** + * @} + */ + +/* Private macros --------------------------------------------------------*/ +/** @defgroup UART_Private_Macros UART Private Macros + * @{ + */ +/** @brief Get UART clock division factor from clock prescaler value. + * @param __CLOCKPRESCALER__ UART prescaler value. + * @retval UART clock division factor + */ +#define UART_GET_DIV_FACTOR(__CLOCKPRESCALER__) \ + (((__CLOCKPRESCALER__) == UART_PRESCALER_DIV1) ? 1U : \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV2) ? 2U : \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV4) ? 4U : \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV6) ? 6U : \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV8) ? 8U : \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV10) ? 10U : \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV12) ? 12U : \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV16) ? 16U : \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV32) ? 32U : \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV64) ? 64U : \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV128) ? 128U : 256U) + +/** @brief BRR division operation to set BRR register with LPUART. + * @param __PCLK__ LPUART clock. + * @param __BAUD__ Baud rate set by the user. + * @param __CLOCKPRESCALER__ UART prescaler value. + * @retval Division result + */ +#define UART_DIV_LPUART(__PCLK__, __BAUD__, __CLOCKPRESCALER__) \ + ((uint32_t)((((((uint64_t)(__PCLK__))/(UARTPrescTable[(__CLOCKPRESCALER__)]))*256U)+ \ + (uint32_t)((__BAUD__)/2U)) / (__BAUD__)) \ + ) + +/** @brief BRR division operation to set BRR register in 8-bit oversampling mode. + * @param __PCLK__ UART clock. + * @param __BAUD__ Baud rate set by the user. + * @param __CLOCKPRESCALER__ UART prescaler value. + * @retval Division result + */ +#define UART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__) \ + (((((__PCLK__)/UARTPrescTable[(__CLOCKPRESCALER__)])*2U) + ((__BAUD__)/2U)) / (__BAUD__)) + +/** @brief BRR division operation to set BRR register in 16-bit oversampling mode. + * @param __PCLK__ UART clock. + * @param __BAUD__ Baud rate set by the user. + * @param __CLOCKPRESCALER__ UART prescaler value. + * @retval Division result + */ +#define UART_DIV_SAMPLING16(__PCLK__, __BAUD__, __CLOCKPRESCALER__) \ + ((((__PCLK__)/UARTPrescTable[(__CLOCKPRESCALER__)]) + ((__BAUD__)/2U)) / (__BAUD__)) + +/** @brief Check whether or not UART instance is Low Power UART. + * @param __HANDLE__ specifies the UART Handle. + * @retval SET (instance is LPUART) or RESET (instance isn't LPUART) + */ +#define UART_INSTANCE_LOWPOWER(__HANDLE__) (IS_LPUART_INSTANCE((__HANDLE__)->Instance)) + +/** @brief Check UART Baud rate. + * @param __BAUDRATE__ Baudrate specified by the user. + * The maximum Baud Rate is derived from the maximum clock on WL (i.e. 48 MHz) + * divided by the smallest oversampling used on the USART (i.e. 8) + * @retval SET (__BAUDRATE__ is valid) or RESET (__BAUDRATE__ is invalid) + */ +#define IS_UART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 6000001U) + +/** @brief Check UART assertion time. + * @param __TIME__ 5-bit value assertion time. + * @retval Test result (TRUE or FALSE). + */ +#define IS_UART_ASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1FU) + +/** @brief Check UART deassertion time. + * @param __TIME__ 5-bit value deassertion time. + * @retval Test result (TRUE or FALSE). + */ +#define IS_UART_DEASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1FU) + +/** + * @brief Ensure that UART frame number of stop bits is valid. + * @param __STOPBITS__ UART frame number of stop bits. + * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid) + */ +#define IS_UART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == UART_STOPBITS_0_5) || \ + ((__STOPBITS__) == UART_STOPBITS_1) || \ + ((__STOPBITS__) == UART_STOPBITS_1_5) || \ + ((__STOPBITS__) == UART_STOPBITS_2)) + +/** + * @brief Ensure that LPUART frame number of stop bits is valid. + * @param __STOPBITS__ LPUART frame number of stop bits. + * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid) + */ +#define IS_LPUART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == UART_STOPBITS_1) || \ + ((__STOPBITS__) == UART_STOPBITS_2)) + +/** + * @brief Ensure that UART frame parity is valid. + * @param __PARITY__ UART frame parity. + * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid) + */ +#define IS_UART_PARITY(__PARITY__) (((__PARITY__) == UART_PARITY_NONE) || \ + ((__PARITY__) == UART_PARITY_EVEN) || \ + ((__PARITY__) == UART_PARITY_ODD)) + +/** + * @brief Ensure that UART hardware flow control is valid. + * @param __CONTROL__ UART hardware flow control. + * @retval SET (__CONTROL__ is valid) or RESET (__CONTROL__ is invalid) + */ +#define IS_UART_HARDWARE_FLOW_CONTROL(__CONTROL__)\ + (((__CONTROL__) == UART_HWCONTROL_NONE) || \ + ((__CONTROL__) == UART_HWCONTROL_RTS) || \ + ((__CONTROL__) == UART_HWCONTROL_CTS) || \ + ((__CONTROL__) == UART_HWCONTROL_RTS_CTS)) + +/** + * @brief Ensure that UART communication mode is valid. + * @param __MODE__ UART communication mode. + * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) + */ +#define IS_UART_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(UART_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U)) + +/** + * @brief Ensure that UART state is valid. + * @param __STATE__ UART state. + * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid) + */ +#define IS_UART_STATE(__STATE__) (((__STATE__) == UART_STATE_DISABLE) || \ + ((__STATE__) == UART_STATE_ENABLE)) + +/** + * @brief Ensure that UART oversampling is valid. + * @param __SAMPLING__ UART oversampling. + * @retval SET (__SAMPLING__ is valid) or RESET (__SAMPLING__ is invalid) + */ +#define IS_UART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == UART_OVERSAMPLING_16) || \ + ((__SAMPLING__) == UART_OVERSAMPLING_8)) + +/** + * @brief Ensure that UART frame sampling is valid. + * @param __ONEBIT__ UART frame sampling. + * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid) + */ +#define IS_UART_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == UART_ONE_BIT_SAMPLE_DISABLE) || \ + ((__ONEBIT__) == UART_ONE_BIT_SAMPLE_ENABLE)) + +/** + * @brief Ensure that UART auto Baud rate detection mode is valid. + * @param __MODE__ UART auto Baud rate detection mode. + * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) + */ +#define IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(__MODE__) (((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT) || \ + ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE) || \ + ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME) || \ + ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME)) + +/** + * @brief Ensure that UART receiver timeout setting is valid. + * @param __TIMEOUT__ UART receiver timeout setting. + * @retval SET (__TIMEOUT__ is valid) or RESET (__TIMEOUT__ is invalid) + */ +#define IS_UART_RECEIVER_TIMEOUT(__TIMEOUT__) (((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_DISABLE) || \ + ((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_ENABLE)) + +/** @brief Check the receiver timeout value. + * @note The maximum UART receiver timeout value is 0xFFFFFF. + * @param __TIMEOUTVALUE__ receiver timeout value. + * @retval Test result (TRUE or FALSE) + */ +#define IS_UART_RECEIVER_TIMEOUT_VALUE(__TIMEOUTVALUE__) ((__TIMEOUTVALUE__) <= 0xFFFFFFU) + +/** + * @brief Ensure that UART LIN state is valid. + * @param __LIN__ UART LIN state. + * @retval SET (__LIN__ is valid) or RESET (__LIN__ is invalid) + */ +#define IS_UART_LIN(__LIN__) (((__LIN__) == UART_LIN_DISABLE) || \ + ((__LIN__) == UART_LIN_ENABLE)) + +/** + * @brief Ensure that UART LIN break detection length is valid. + * @param __LENGTH__ UART LIN break detection length. + * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid) + */ +#define IS_UART_LIN_BREAK_DETECT_LENGTH(__LENGTH__) (((__LENGTH__) == UART_LINBREAKDETECTLENGTH_10B) || \ + ((__LENGTH__) == UART_LINBREAKDETECTLENGTH_11B)) + +/** + * @brief Ensure that UART DMA TX state is valid. + * @param __DMATX__ UART DMA TX state. + * @retval SET (__DMATX__ is valid) or RESET (__DMATX__ is invalid) + */ +#define IS_UART_DMA_TX(__DMATX__) (((__DMATX__) == UART_DMA_TX_DISABLE) || \ + ((__DMATX__) == UART_DMA_TX_ENABLE)) + +/** + * @brief Ensure that UART DMA RX state is valid. + * @param __DMARX__ UART DMA RX state. + * @retval SET (__DMARX__ is valid) or RESET (__DMARX__ is invalid) + */ +#define IS_UART_DMA_RX(__DMARX__) (((__DMARX__) == UART_DMA_RX_DISABLE) || \ + ((__DMARX__) == UART_DMA_RX_ENABLE)) + +/** + * @brief Ensure that UART half-duplex state is valid. + * @param __HDSEL__ UART half-duplex state. + * @retval SET (__HDSEL__ is valid) or RESET (__HDSEL__ is invalid) + */ +#define IS_UART_HALF_DUPLEX(__HDSEL__) (((__HDSEL__) == UART_HALF_DUPLEX_DISABLE) || \ + ((__HDSEL__) == UART_HALF_DUPLEX_ENABLE)) + +/** + * @brief Ensure that UART wake-up method is valid. + * @param __WAKEUP__ UART wake-up method . + * @retval SET (__WAKEUP__ is valid) or RESET (__WAKEUP__ is invalid) + */ +#define IS_UART_WAKEUPMETHOD(__WAKEUP__) (((__WAKEUP__) == UART_WAKEUPMETHOD_IDLELINE) || \ + ((__WAKEUP__) == UART_WAKEUPMETHOD_ADDRESSMARK)) + +/** + * @brief Ensure that UART request parameter is valid. + * @param __PARAM__ UART request parameter. + * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid) + */ +#define IS_UART_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == UART_AUTOBAUD_REQUEST) || \ + ((__PARAM__) == UART_SENDBREAK_REQUEST) || \ + ((__PARAM__) == UART_MUTE_MODE_REQUEST) || \ + ((__PARAM__) == UART_RXDATA_FLUSH_REQUEST) || \ + ((__PARAM__) == UART_TXDATA_FLUSH_REQUEST)) + +/** + * @brief Ensure that UART advanced features initialization is valid. + * @param __INIT__ UART advanced features initialization. + * @retval SET (__INIT__ is valid) or RESET (__INIT__ is invalid) + */ +#define IS_UART_ADVFEATURE_INIT(__INIT__) ((__INIT__) <= (UART_ADVFEATURE_NO_INIT | \ + UART_ADVFEATURE_TXINVERT_INIT | \ + UART_ADVFEATURE_RXINVERT_INIT | \ + UART_ADVFEATURE_DATAINVERT_INIT | \ + UART_ADVFEATURE_SWAP_INIT | \ + UART_ADVFEATURE_RXOVERRUNDISABLE_INIT | \ + UART_ADVFEATURE_DMADISABLEONERROR_INIT | \ + UART_ADVFEATURE_AUTOBAUDRATE_INIT | \ + UART_ADVFEATURE_MSBFIRST_INIT)) + +/** + * @brief Ensure that UART frame TX inversion setting is valid. + * @param __TXINV__ UART frame TX inversion setting. + * @retval SET (__TXINV__ is valid) or RESET (__TXINV__ is invalid) + */ +#define IS_UART_ADVFEATURE_TXINV(__TXINV__) (((__TXINV__) == UART_ADVFEATURE_TXINV_DISABLE) || \ + ((__TXINV__) == UART_ADVFEATURE_TXINV_ENABLE)) + +/** + * @brief Ensure that UART frame RX inversion setting is valid. + * @param __RXINV__ UART frame RX inversion setting. + * @retval SET (__RXINV__ is valid) or RESET (__RXINV__ is invalid) + */ +#define IS_UART_ADVFEATURE_RXINV(__RXINV__) (((__RXINV__) == UART_ADVFEATURE_RXINV_DISABLE) || \ + ((__RXINV__) == UART_ADVFEATURE_RXINV_ENABLE)) + +/** + * @brief Ensure that UART frame data inversion setting is valid. + * @param __DATAINV__ UART frame data inversion setting. + * @retval SET (__DATAINV__ is valid) or RESET (__DATAINV__ is invalid) + */ +#define IS_UART_ADVFEATURE_DATAINV(__DATAINV__) (((__DATAINV__) == UART_ADVFEATURE_DATAINV_DISABLE) || \ + ((__DATAINV__) == UART_ADVFEATURE_DATAINV_ENABLE)) + +/** + * @brief Ensure that UART frame RX/TX pins swap setting is valid. + * @param __SWAP__ UART frame RX/TX pins swap setting. + * @retval SET (__SWAP__ is valid) or RESET (__SWAP__ is invalid) + */ +#define IS_UART_ADVFEATURE_SWAP(__SWAP__) (((__SWAP__) == UART_ADVFEATURE_SWAP_DISABLE) || \ + ((__SWAP__) == UART_ADVFEATURE_SWAP_ENABLE)) + +/** + * @brief Ensure that UART frame overrun setting is valid. + * @param __OVERRUN__ UART frame overrun setting. + * @retval SET (__OVERRUN__ is valid) or RESET (__OVERRUN__ is invalid) + */ +#define IS_UART_OVERRUN(__OVERRUN__) (((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_ENABLE) || \ + ((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_DISABLE)) + +/** + * @brief Ensure that UART auto Baud rate state is valid. + * @param __AUTOBAUDRATE__ UART auto Baud rate state. + * @retval SET (__AUTOBAUDRATE__ is valid) or RESET (__AUTOBAUDRATE__ is invalid) + */ +#define IS_UART_ADVFEATURE_AUTOBAUDRATE(__AUTOBAUDRATE__) (((__AUTOBAUDRATE__) == \ + UART_ADVFEATURE_AUTOBAUDRATE_DISABLE) || \ + ((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)) + +/** + * @brief Ensure that UART DMA enabling or disabling on error setting is valid. + * @param __DMA__ UART DMA enabling or disabling on error setting. + * @retval SET (__DMA__ is valid) or RESET (__DMA__ is invalid) + */ +#define IS_UART_ADVFEATURE_DMAONRXERROR(__DMA__) (((__DMA__) == UART_ADVFEATURE_DMA_ENABLEONRXERROR) || \ + ((__DMA__) == UART_ADVFEATURE_DMA_DISABLEONRXERROR)) + +/** + * @brief Ensure that UART frame MSB first setting is valid. + * @param __MSBFIRST__ UART frame MSB first setting. + * @retval SET (__MSBFIRST__ is valid) or RESET (__MSBFIRST__ is invalid) + */ +#define IS_UART_ADVFEATURE_MSBFIRST(__MSBFIRST__) (((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_DISABLE) || \ + ((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_ENABLE)) + +/** + * @brief Ensure that UART stop mode state is valid. + * @param __STOPMODE__ UART stop mode state. + * @retval SET (__STOPMODE__ is valid) or RESET (__STOPMODE__ is invalid) + */ +#define IS_UART_ADVFEATURE_STOPMODE(__STOPMODE__) (((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_DISABLE) || \ + ((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_ENABLE)) + +/** + * @brief Ensure that UART mute mode state is valid. + * @param __MUTE__ UART mute mode state. + * @retval SET (__MUTE__ is valid) or RESET (__MUTE__ is invalid) + */ +#define IS_UART_MUTE_MODE(__MUTE__) (((__MUTE__) == UART_ADVFEATURE_MUTEMODE_DISABLE) || \ + ((__MUTE__) == UART_ADVFEATURE_MUTEMODE_ENABLE)) + +/** + * @brief Ensure that UART wake-up selection is valid. + * @param __WAKE__ UART wake-up selection. + * @retval SET (__WAKE__ is valid) or RESET (__WAKE__ is invalid) + */ +#define IS_UART_WAKEUP_SELECTION(__WAKE__) (((__WAKE__) == UART_WAKEUP_ON_ADDRESS) || \ + ((__WAKE__) == UART_WAKEUP_ON_STARTBIT) || \ + ((__WAKE__) == UART_WAKEUP_ON_READDATA_NONEMPTY)) + +/** + * @brief Ensure that UART driver enable polarity is valid. + * @param __POLARITY__ UART driver enable polarity. + * @retval SET (__POLARITY__ is valid) or RESET (__POLARITY__ is invalid) + */ +#define IS_UART_DE_POLARITY(__POLARITY__) (((__POLARITY__) == UART_DE_POLARITY_HIGH) || \ + ((__POLARITY__) == UART_DE_POLARITY_LOW)) + +/** + * @brief Ensure that UART Prescaler is valid. + * @param __CLOCKPRESCALER__ UART Prescaler value. + * @retval SET (__CLOCKPRESCALER__ is valid) or RESET (__CLOCKPRESCALER__ is invalid) + */ +#define IS_UART_PRESCALER(__CLOCKPRESCALER__) (((__CLOCKPRESCALER__) == UART_PRESCALER_DIV1) || \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV2) || \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV4) || \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV6) || \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV8) || \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV10) || \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV12) || \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV16) || \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV32) || \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV64) || \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV128) || \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV256)) + +/** + * @} + */ + +/* Include UART HAL Extended module */ +#include "stm32wlxx_hal_uart_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup UART_Exported_Functions UART Exported Functions + * @{ + */ + +/** @addtogroup UART_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ + +/* Initialization and de-initialization functions ****************************/ +HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength); +HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod); +HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart); +void HAL_UART_MspInit(UART_HandleTypeDef *huart); +void HAL_UART_MspDeInit(UART_HandleTypeDef *huart); + +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, + pUART_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID); + +HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(UART_HandleTypeDef *huart, pUART_RxEventCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @addtogroup UART_Exported_Functions_Group2 IO operation functions + * @{ + */ + +/* IO operation functions *****************************************************/ +HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart); +/* Transfer Abort functions */ +HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart); + +void HAL_UART_IRQHandler(UART_HandleTypeDef *huart); +void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart); +void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart); +void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart); +void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart); +void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart); +void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart); +void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart); +void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart); + +void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size); + +/** + * @} + */ + +/** @addtogroup UART_Exported_Functions_Group3 Peripheral Control functions + * @{ + */ + +/* Peripheral Control functions ************************************************/ +void HAL_UART_ReceiverTimeout_Config(UART_HandleTypeDef *huart, uint32_t TimeoutValue); +HAL_StatusTypeDef HAL_UART_EnableReceiverTimeout(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_DisableReceiverTimeout(UART_HandleTypeDef *huart); + +HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart); +void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart); + +/** + * @} + */ + +/** @addtogroup UART_Exported_Functions_Group4 Peripheral State and Error functions + * @{ + */ + +/* Peripheral State and Errors functions **************************************************/ +HAL_UART_StateTypeDef HAL_UART_GetState(const UART_HandleTypeDef *huart); +uint32_t HAL_UART_GetError(const UART_HandleTypeDef *huart); + +/** + * @} + */ + +/** + * @} + */ + +/* Private functions -----------------------------------------------------------*/ +/** @addtogroup UART_Private_Functions UART Private Functions + * @{ + */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart); +HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart); +HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, + uint32_t Tickstart, uint32_t Timeout); +void UART_AdvFeatureConfig(UART_HandleTypeDef *huart); +HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); + +/** + * @} + */ + +/* Private variables -----------------------------------------------------------*/ +/** @defgroup UART_Private_variables UART Private variables + * @{ + */ +/* Prescaler Table used in BRR computation macros. + Declared as extern here to allow use of private UART macros, outside of HAL UART functions */ +extern const uint16_t UARTPrescTable[12]; +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32WLxx_HAL_UART_H */ + diff --git a/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h b/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h new file mode 100644 index 0000000..206becd --- /dev/null +++ b/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h @@ -0,0 +1,383 @@ +/** + ****************************************************************************** + * @file stm32wlxx_hal_uart_ex.h + * @author MCD Application Team + * @brief Header file of UART HAL Extended module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32WLxx_HAL_UART_EX_H +#define STM32WLxx_HAL_UART_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wlxx_hal_def.h" + +/** @addtogroup STM32WLxx_HAL_Driver + * @{ + */ + +/** @addtogroup UARTEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup UARTEx_Exported_Types UARTEx Exported Types + * @{ + */ + +/** + * @brief UART wake up from stop mode parameters + */ +typedef struct +{ + uint32_t WakeUpEvent; /*!< Specifies which event will activate the Wakeup from Stop mode flag (WUF). + This parameter can be a value of @ref UART_WakeUp_from_Stop_Selection. + If set to UART_WAKEUP_ON_ADDRESS, the two other fields below must + be filled up. */ + + uint16_t AddressLength; /*!< Specifies whether the address is 4 or 7-bit long. + This parameter can be a value of @ref UARTEx_WakeUp_Address_Length. */ + + uint8_t Address; /*!< UART/USART node address (7-bit long max). */ +} UART_WakeUpTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup UARTEx_Exported_Constants UARTEx Exported Constants + * @{ + */ + +/** @defgroup UARTEx_Word_Length UARTEx Word Length + * @{ + */ +#define UART_WORDLENGTH_7B USART_CR1_M1 /*!< 7-bit long UART frame */ +#define UART_WORDLENGTH_8B 0x00000000U /*!< 8-bit long UART frame */ +#define UART_WORDLENGTH_9B USART_CR1_M0 /*!< 9-bit long UART frame */ +/** + * @} + */ + +/** @defgroup UARTEx_WakeUp_Address_Length UARTEx WakeUp Address Length + * @{ + */ +#define UART_ADDRESS_DETECT_4B 0x00000000U /*!< 4-bit long wake-up address */ +#define UART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit long wake-up address */ +/** + * @} + */ + +/** @defgroup UARTEx_FIFO_mode UARTEx FIFO mode + * @brief UART FIFO mode + * @{ + */ +#define UART_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable */ +#define UART_FIFOMODE_ENABLE USART_CR1_FIFOEN /*!< FIFO mode enable */ +/** + * @} + */ + +/** @defgroup UARTEx_TXFIFO_threshold_level UARTEx TXFIFO threshold level + * @brief UART TXFIFO threshold level + * @{ + */ +#define UART_TXFIFO_THRESHOLD_1_8 0x00000000U /*!< TX FIFO reaches 1/8 of its depth */ +#define UART_TXFIFO_THRESHOLD_1_4 USART_CR3_TXFTCFG_0 /*!< TX FIFO reaches 1/4 of its depth */ +#define UART_TXFIFO_THRESHOLD_1_2 USART_CR3_TXFTCFG_1 /*!< TX FIFO reaches 1/2 of its depth */ +#define UART_TXFIFO_THRESHOLD_3_4 (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1) /*!< TX FIFO reaches 3/4 of its depth */ +#define UART_TXFIFO_THRESHOLD_7_8 USART_CR3_TXFTCFG_2 /*!< TX FIFO reaches 7/8 of its depth */ +#define UART_TXFIFO_THRESHOLD_8_8 (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0) /*!< TX FIFO becomes empty */ +/** + * @} + */ + +/** @defgroup UARTEx_RXFIFO_threshold_level UARTEx RXFIFO threshold level + * @brief UART RXFIFO threshold level + * @{ + */ +#define UART_RXFIFO_THRESHOLD_1_8 0x00000000U /*!< RX FIFO reaches 1/8 of its depth */ +#define UART_RXFIFO_THRESHOLD_1_4 USART_CR3_RXFTCFG_0 /*!< RX FIFO reaches 1/4 of its depth */ +#define UART_RXFIFO_THRESHOLD_1_2 USART_CR3_RXFTCFG_1 /*!< RX FIFO reaches 1/2 of its depth */ +#define UART_RXFIFO_THRESHOLD_3_4 (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1) /*!< RX FIFO reaches 3/4 of its depth */ +#define UART_RXFIFO_THRESHOLD_7_8 USART_CR3_RXFTCFG_2 /*!< RX FIFO reaches 7/8 of its depth */ +#define UART_RXFIFO_THRESHOLD_8_8 (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0) /*!< RX FIFO becomes full */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup UARTEx_Exported_Functions + * @{ + */ + +/** @addtogroup UARTEx_Exported_Functions_Group1 + * @{ + */ + +/* Initialization and de-initialization functions ****************************/ +HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, + uint32_t DeassertionTime); + +/** + * @} + */ + +/** @addtogroup UARTEx_Exported_Functions_Group2 + * @{ + */ + +void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart); + +void HAL_UARTEx_RxFifoFullCallback(UART_HandleTypeDef *huart); +void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart); + +/** + * @} + */ + +/** @addtogroup UARTEx_Exported_Functions_Group3 + * @{ + */ + +/* Peripheral Control functions **********************************************/ +HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection); +HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart); + +HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength); + +HAL_StatusTypeDef HAL_UARTEx_EnableFifoMode(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold); +HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold); + +HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen, + uint32_t Timeout); +HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); + +HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(const UART_HandleTypeDef *huart); + + +/** + * @} + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup UARTEx_Private_Macros UARTEx Private Macros + * @{ + */ + +/** @brief Report the UART clock source. + * @param __HANDLE__ specifies the UART Handle. + * @param __CLOCKSOURCE__ output variable. + * @retval UART clocking source, written in __CLOCKSOURCE__. + */ +#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ + do { \ + if((__HANDLE__)->Instance == USART1) \ + { \ + switch(__HAL_RCC_GET_USART1_SOURCE()) \ + { \ + case RCC_USART1CLKSOURCE_PCLK2: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2; \ + break; \ + case RCC_USART1CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART1CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART1CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART2) \ + { \ + switch(__HAL_RCC_GET_USART2_SOURCE()) \ + { \ + case RCC_USART2CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART2CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART2CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART2CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == LPUART1) \ + { \ + switch(__HAL_RCC_GET_LPUART1_SOURCE()) \ + { \ + case RCC_LPUART1CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_LPUART1CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_LPUART1CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_LPUART1CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else \ + { \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + } \ + } while(0U) + +/** @brief Report the UART mask to apply to retrieve the received data + * according to the word length and to the parity bits activation. + * @note If PCE = 1, the parity bit is not included in the data extracted + * by the reception API(). + * This masking operation is not carried out in the case of + * DMA transfers. + * @param __HANDLE__ specifies the UART Handle. + * @retval None, the mask to apply to UART RDR register is stored in (__HANDLE__)->Mask field. + */ +#define UART_MASK_COMPUTATION(__HANDLE__) \ + do { \ + if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_9B) \ + { \ + if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \ + { \ + (__HANDLE__)->Mask = 0x01FFU ; \ + } \ + else \ + { \ + (__HANDLE__)->Mask = 0x00FFU ; \ + } \ + } \ + else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_8B) \ + { \ + if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \ + { \ + (__HANDLE__)->Mask = 0x00FFU ; \ + } \ + else \ + { \ + (__HANDLE__)->Mask = 0x007FU ; \ + } \ + } \ + else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_7B) \ + { \ + if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \ + { \ + (__HANDLE__)->Mask = 0x007FU ; \ + } \ + else \ + { \ + (__HANDLE__)->Mask = 0x003FU ; \ + } \ + } \ + else \ + { \ + (__HANDLE__)->Mask = 0x0000U; \ + } \ + } while(0U) + +/** + * @brief Ensure that UART frame length is valid. + * @param __LENGTH__ UART frame length. + * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid) + */ +#define IS_UART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == UART_WORDLENGTH_7B) || \ + ((__LENGTH__) == UART_WORDLENGTH_8B) || \ + ((__LENGTH__) == UART_WORDLENGTH_9B)) + +/** + * @brief Ensure that UART wake-up address length is valid. + * @param __ADDRESS__ UART wake-up address length. + * @retval SET (__ADDRESS__ is valid) or RESET (__ADDRESS__ is invalid) + */ +#define IS_UART_ADDRESSLENGTH_DETECT(__ADDRESS__) (((__ADDRESS__) == UART_ADDRESS_DETECT_4B) || \ + ((__ADDRESS__) == UART_ADDRESS_DETECT_7B)) + +/** + * @brief Ensure that UART TXFIFO threshold level is valid. + * @param __THRESHOLD__ UART TXFIFO threshold level. + * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid) + */ +#define IS_UART_TXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_8) || \ + ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_4) || \ + ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_2) || \ + ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_3_4) || \ + ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_7_8) || \ + ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_8_8)) + +/** + * @brief Ensure that UART RXFIFO threshold level is valid. + * @param __THRESHOLD__ UART RXFIFO threshold level. + * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid) + */ +#define IS_UART_RXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_8) || \ + ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_4) || \ + ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_2) || \ + ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_3_4) || \ + ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_7_8) || \ + ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_8_8)) + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32WLxx_HAL_UART_EX_H */ + diff --git a/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h b/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h new file mode 100644 index 0000000..0c519ee --- /dev/null +++ b/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h @@ -0,0 +1,2525 @@ +/** + ****************************************************************************** + * @file stm32wlxx_ll_bus.h + * @author MCD Application Team + * @brief Header file of BUS LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ##### RCC Limitations ##### + ============================================================================== + [..] + A delay between an RCC peripheral clock enable and the effective peripheral + enabling should be taken into account in order to manage the peripheral read/write + from/to registers.w< + (+) This delay depends on the peripheral mapping. + (++) AHB & APB peripherals, 1 dummy read is necessary + + [..] + Workarounds: + (#) For AHB & APB peripherals, a dummy read to the peripheral register has been + inserted in each LL_{BUS}_GRP{x}_EnableClock() function. + + @endverbatim + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32WLxx_LL_BUS_H +#define __STM32WLxx_LL_BUS_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wlxx.h" + +/** @addtogroup STM32WLxx_LL_Driver + * @{ + */ + +#if defined(RCC) + +/** @defgroup BUS_LL BUS + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ + +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup BUS_LL_Exported_Constants BUS Exported Constants + * @{ + */ + +/** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH + * @{ + */ +#define LL_AHB1_GRP1_PERIPH_ALL (0xFFFFFFFFU) +#define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHB1ENR_DMA1EN +#define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHB1ENR_DMA2EN +#define LL_AHB1_GRP1_PERIPH_DMAMUX1 RCC_AHB1ENR_DMAMUX1EN +#define LL_AHB1_GRP1_PERIPH_CRC RCC_AHB1ENR_CRCEN +/** + * @} + */ + +/** @defgroup BUS_LL_EC_AHB2_GRP1_PERIPH AHB2 GRP1 PERIPH + * @{ + */ +#define LL_AHB2_GRP1_PERIPH_ALL (0xFFFFFFFFU) +#define LL_AHB2_GRP1_PERIPH_GPIOA RCC_AHB2ENR_GPIOAEN +#define LL_AHB2_GRP1_PERIPH_GPIOB RCC_AHB2ENR_GPIOBEN +#define LL_AHB2_GRP1_PERIPH_GPIOC RCC_AHB2ENR_GPIOCEN +#define LL_AHB2_GRP1_PERIPH_GPIOH RCC_AHB2ENR_GPIOHEN +/** + * @} + */ + +/** @defgroup BUS_LL_EC_AHB3_GRP1_PERIPH AHB3 GRP1 PERIPH + * @{ + */ +#define LL_AHB3_GRP1_PERIPH_ALL (0xFFFFFFFFU) +#define LL_AHB3_GRP1_PERIPH_PKA RCC_AHB3ENR_PKAEN +#define LL_AHB3_GRP1_PERIPH_AES RCC_AHB3ENR_AESEN +#define LL_AHB3_GRP1_PERIPH_RNG RCC_AHB3ENR_RNGEN +#define LL_AHB3_GRP1_PERIPH_HSEM RCC_AHB3ENR_HSEMEN +#if defined(DUAL_CORE) +#define LL_AHB3_GRP1_PERIPH_IPCC RCC_AHB3ENR_IPCCEN +#endif /* DUAL_CORE */ +#define LL_AHB3_GRP1_PERIPH_SRAM1 RCC_AHB3SMENR_SRAM1SMEN +#define LL_AHB3_GRP1_PERIPH_SRAM2 RCC_AHB3SMENR_SRAM2SMEN +#define LL_AHB3_GRP1_PERIPH_FLASH RCC_AHB3ENR_FLASHEN +/** + * @} + */ + +/** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH + * @{ + */ +#define LL_APB1_GRP1_PERIPH_ALL (0xFFFFFFFFU) +#define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR1_TIM2EN +#define LL_APB1_GRP1_PERIPH_RTCAPB RCC_APB1ENR1_RTCAPBEN +#define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR1_WWDGEN +#define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR1_SPI2EN +#define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR1_USART2EN +#define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR1_I2C1EN +#define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR1_I2C2EN +#define LL_APB1_GRP1_PERIPH_I2C3 RCC_APB1ENR1_I2C3EN +#define LL_APB1_GRP1_PERIPH_DAC RCC_APB1ENR1_DACEN +#define LL_APB1_GRP1_PERIPH_LPTIM1 RCC_APB1ENR1_LPTIM1EN +/** + * @} + */ + + +/** @defgroup BUS_LL_EC_APB1_GRP2_PERIPH APB1 GRP2 PERIPH + * @{ + */ +#define LL_APB1_GRP2_PERIPH_ALL (0xFFFFFFFFU) +#define LL_APB1_GRP2_PERIPH_LPUART1 RCC_APB1ENR2_LPUART1EN +#define LL_APB1_GRP2_PERIPH_LPTIM2 RCC_APB1ENR2_LPTIM2EN +#define LL_APB1_GRP2_PERIPH_LPTIM3 RCC_APB1ENR2_LPTIM3EN +/** + * @} + */ + +/** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH + * @{ + */ +#define LL_APB2_GRP1_PERIPH_ALL (0xFFFFFFFFU) +#define LL_APB2_GRP1_PERIPH_ADC RCC_APB2ENR_ADCEN +#define LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN +#define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN +#define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN +#define LL_APB2_GRP1_PERIPH_TIM16 RCC_APB2ENR_TIM16EN +#define LL_APB2_GRP1_PERIPH_TIM17 RCC_APB2ENR_TIM17EN +/** + * @} + */ + +/** @defgroup BUS_LL_EC_APB3_GRP1_PERIPH APB3 GRP1 PERIPH + * @{ + */ +#define LL_APB3_GRP1_PERIPH_ALL (0xFFFFFFFFU) +#define LL_APB3_GRP1_PERIPH_SUBGHZSPI RCC_APB3ENR_SUBGHZSPIEN +/** + * @} + */ + +#if defined(DUAL_CORE) +/** @defgroup BUS_LL_EC_C2_AHB1_GRP1_PERIPH C2 AHB1 GRP1 PERIPH + * @{ + */ +#define LL_C2_AHB1_GRP1_PERIPH_DMA1 RCC_C2AHB1ENR_DMA1EN +#define LL_C2_AHB1_GRP1_PERIPH_DMA2 RCC_C2AHB1ENR_DMA2EN +#define LL_C2_AHB1_GRP1_PERIPH_DMAMUX1 RCC_C2AHB1ENR_DMAMUX1EN +#define LL_C2_AHB1_GRP1_PERIPH_CRC RCC_C2AHB1ENR_CRCEN +/** + * @} + */ + + +/** @defgroup BUS_LL_EC_C2_AHB2_GRP1_PERIPH C2 AHB2 GRP1 PERIPH + * @{ + */ +#define LL_C2_AHB2_GRP1_PERIPH_GPIOA RCC_C2AHB2ENR_GPIOAEN +#define LL_C2_AHB2_GRP1_PERIPH_GPIOB RCC_C2AHB2ENR_GPIOBEN +#define LL_C2_AHB2_GRP1_PERIPH_GPIOC RCC_C2AHB2ENR_GPIOCEN +#define LL_C2_AHB2_GRP1_PERIPH_GPIOH RCC_C2AHB2ENR_GPIOHEN +/** + * @} + */ + + +/** @defgroup BUS_LL_EC_C2_AHB3_GRP1_PERIPH C2 AHB3 GRP1 PERIPH + * @{ + */ +#define LL_C2_AHB3_GRP1_PERIPH_PKA RCC_C2AHB3ENR_PKAEN +#define LL_C2_AHB3_GRP1_PERIPH_AES RCC_C2AHB3ENR_AESEN +#define LL_C2_AHB3_GRP1_PERIPH_RNG RCC_C2AHB3ENR_RNGEN +#define LL_C2_AHB3_GRP1_PERIPH_HSEM RCC_C2AHB3ENR_HSEMEN +#define LL_C2_AHB3_GRP1_PERIPH_IPCC RCC_C2AHB3ENR_IPCCEN +#define LL_C2_AHB3_GRP1_PERIPH_FLASH RCC_C2AHB3ENR_FLASHEN +#define LL_C2_AHB3_GRP1_PERIPH_SRAM1 RCC_C2AHB3SMENR_SRAM1SMEN +#define LL_C2_AHB3_GRP1_PERIPH_SRAM2 RCC_C2AHB3SMENR_SRAM2SMEN +/** + * @} + */ + + +/** @defgroup BUS_LL_EC_C2_APB1_GRP1_PERIPH C2 APB1 GRP1 PERIPH + * @{ + */ +#define LL_C2_APB1_GRP1_PERIPH_TIM2 RCC_C2APB1ENR1_TIM2EN +#define LL_C2_APB1_GRP1_PERIPH_RTCAPB RCC_C2APB1ENR1_RTCAPBEN +#define LL_C2_APB1_GRP1_PERIPH_SPI2 RCC_C2APB1ENR1_SPI2EN +#define LL_C2_APB1_GRP1_PERIPH_USART2 RCC_C2APB1ENR1_USART2EN +#define LL_C2_APB1_GRP1_PERIPH_I2C1 RCC_C2APB1ENR1_I2C1EN +#define LL_C2_APB1_GRP1_PERIPH_I2C2 RCC_C2APB1ENR1_I2C2EN +#define LL_C2_APB1_GRP1_PERIPH_I2C3 RCC_C2APB1ENR1_I2C3EN +#define LL_C2_APB1_GRP1_PERIPH_DAC RCC_C2APB1ENR1_DACEN +#define LL_C2_APB1_GRP1_PERIPH_LPTIM1 RCC_C2APB1ENR1_LPTIM1EN +/** + * @} + */ + + +/** @defgroup BUS_LL_EC_C2_APB1_GRP2_PERIPH C2 APB1 GRP2 PERIPH + * @{ + */ +#define LL_C2_APB1_GRP2_PERIPH_LPUART1 RCC_C2APB1ENR2_LPUART1EN +#define LL_C2_APB1_GRP2_PERIPH_LPTIM2 RCC_C2APB1ENR2_LPTIM2EN +#define LL_C2_APB1_GRP2_PERIPH_LPTIM3 RCC_C2APB1ENR2_LPTIM3EN +/** + * @} + */ + + +/** @defgroup BUS_LL_EC_C2_APB2_GRP1_PERIPH C2 APB2 GRP1 PERIPH + * @{ + */ +#define LL_C2_APB2_GRP1_PERIPH_ADC RCC_C2APB2ENR_ADCEN +#define LL_C2_APB2_GRP1_PERIPH_TIM1 RCC_C2APB2ENR_TIM1EN +#define LL_C2_APB2_GRP1_PERIPH_SPI1 RCC_C2APB2ENR_SPI1EN +#define LL_C2_APB2_GRP1_PERIPH_USART1 RCC_C2APB2ENR_USART1EN +#define LL_C2_APB2_GRP1_PERIPH_TIM16 RCC_C2APB2ENR_TIM16EN +#define LL_C2_APB2_GRP1_PERIPH_TIM17 RCC_C2APB2ENR_TIM17EN +/** + * @} + */ + + +/** @defgroup BUS_LL_EC_C2_APB3_GRP1_PERIPH C2 APB3 GRP1 PERIPH + * @{ + */ +#define LL_C2_APB3_GRP1_PERIPH_SUBGHZSPI RCC_C2APB3ENR_SUBGHZSPIEN +/** + * @} + */ +#endif /* DUAL_CORE */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup BUS_LL_Exported_Functions BUS Exported Functions + * @{ + */ + +/** @defgroup BUS_LL_EF_AHB1 AHB1 + * @{ + */ + +/** + * @brief Enable AHB1 peripherals clock. + * @rmtoll AHB1ENR DMA1EN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR DMA2EN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR DMAMUX1EN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR CRCEN LL_AHB1_GRP1_EnableClock\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1 + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @retval None + */ +__STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->AHB1ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHB1ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if AHB1 peripheral clock is enabled or not + * @rmtoll AHB1ENR DMA1EN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR DMA2EN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR DMAMUX1EN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1 + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @retval uint32_t + */ +__STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC->AHB1ENR, Periphs) == (Periphs)) ? 1UL : 0UL); +} + +/** + * @brief Disable AHB1 peripherals clock. + * @rmtoll AHB1ENR DMA1EN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR DMA2EN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR DMAMUX1EN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR CRCEN LL_AHB1_GRP1_DisableClock\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1 + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @retval None + */ +__STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB1ENR, Periphs); +} + +/** + * @brief Force AHB1 peripherals reset. + * @rmtoll AHB1RSTR DMA1RST LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR DMA2RST LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR DMAMUX1RST LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR CRCRST LL_AHB1_GRP1_ForceReset\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_ALL + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1 + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @retval None + */ +__STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->AHB1RSTR, Periphs); +} + +/** + * @brief Release AHB1 peripherals reset. + * @rmtoll AHB1RSTR DMA1RST LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR DMA2RST LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR DMAMUX1RST LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR CRCRST LL_AHB1_GRP1_ReleaseReset\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_ALL + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1 + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @retval None + */ +__STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB1RSTR, Periphs); +} + +/** + * @brief Enable AHB1 peripherals clock during Low Power (Sleep) mode. + * @rmtoll AHB1SMENR DMA1SMEN LL_AHB1_GRP1_EnableClockSleep\n + * AHB1SMENR DMA2SMEN LL_AHB1_GRP1_EnableClockSleep\n + * AHB1SMENR DMAMUX1SMEN LL_AHB1_GRP1_EnableClockSleep\n + * AHB1SMENR CRCSMEN LL_AHB1_GRP1_EnableClockSleep\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1 + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @retval None + */ +__STATIC_INLINE void LL_AHB1_GRP1_EnableClockSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->AHB1SMENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHB1SMENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if AHB1 peripheral clock is enabled by the clock gating during CPU1 CSleep mode + * @rmtoll AHB1SMENR DMA1SMEN LL_AHB1_GRP1_IsEnabledClockSleep\n + * AHB1SMENR DMA2SMEN LL_AHB1_GRP1_IsEnabledClockSleep\n + * AHB1SMENR DMAMUX1SMEN LL_AHB1_GRP1_IsEnabledClockSleep\n + * AHB1SMENR CRCSMEN LL_AHB1_GRP1_IsEnabledClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1 + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @retval uint32_t + */ +__STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClockSleep(uint32_t Periphs) +{ + return ((READ_BIT(RCC->AHB1SMENR, Periphs) == (Periphs)) ? 1UL : 0UL); +} + +/** + * @brief Disable AHB1 peripherals clock during Low Power (Sleep) mode. + * @rmtoll AHB1SMENR DMA1SMEN LL_AHB1_GRP1_DisableClockSleep\n + * AHB1SMENR DMA2SMEN LL_AHB1_GRP1_DisableClockSleep\n + * AHB1SMENR DMAMUX1SMEN LL_AHB1_GRP1_DisableClockSleep\n + * AHB1SMENR CRCSMEN LL_AHB1_GRP1_DisableClockSleep\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1 + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @retval None + */ +__STATIC_INLINE void LL_AHB1_GRP1_DisableClockSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB1SMENR, Periphs); +} + +/** + * @} + */ + +/** @defgroup BUS_LL_EF_AHB2 AHB2 + * @{ + */ + +/** + * @brief Enable AHB2 peripherals clock. + * @rmtoll AHB2ENR GPIOAEN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR GPIOBEN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR GPIOCEN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR GPIOHEN LL_AHB2_GRP1_EnableClock\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH + * @retval None + */ +__STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->AHB2ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHB2ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if AHB2 peripheral clock is enabled or not + * @rmtoll AHB2ENR GPIOAEN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR GPIOBEN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR GPIOCEN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR GPIOHEN LL_AHB2_GRP1_IsEnabledClock\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH + * @retval uint32_t + */ +__STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC->AHB2ENR, Periphs) == (Periphs)) ? 1UL : 0UL); +} + +/** + * @brief Disable AHB2 peripherals clock. + * @rmtoll AHB2ENR GPIOAEN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR GPIOBEN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR GPIOCEN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR GPIOHEN LL_AHB2_GRP1_DisableClock\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH + * @retval None + */ +__STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB2ENR, Periphs); +} + +/** + * @brief Force AHB2 peripherals reset. + * @rmtoll AHB2RSTR GPIOARST LL_AHB2_GRP1_ForceReset\n + * AHB2RSTR GPIOBRST LL_AHB2_GRP1_ForceReset\n + * AHB2RSTR GPIOCRST LL_AHB2_GRP1_ForceReset\n + * AHB2RSTR GPIOHRST LL_AHB2_GRP1_ForceReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_ALL + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH + * @retval None + */ +__STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->AHB2RSTR, Periphs); +} + +/** + * @brief Release AHB2 peripherals reset. + * @rmtoll AHB2RSTR GPIOARST LL_AHB2_GRP1_ReleaseReset\n + * AHB2RSTR GPIOBRST LL_AHB2_GRP1_ReleaseReset\n + * AHB2RSTR GPIOCRST LL_AHB2_GRP1_ReleaseReset\n + * AHB2RSTR GPIOHRST LL_AHB2_GRP1_ReleaseReset\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_ALL + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH + * @retval None + */ +__STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB2RSTR, Periphs); +} + +/** + * @brief Enable AHB2 peripherals clock during Low Power (Sleep) mode. + * @rmtoll AHB2SMENR GPIOASMEN LL_AHB2_GRP1_EnableClockSleep\n + * AHB2SMENR GPIOBSMEN LL_AHB2_GRP1_EnableClockSleep\n + * AHB2SMENR GPIOCSMEN LL_AHB2_GRP1_EnableClockSleep\n + * AHB2SMENR GPIOHSMEN LL_AHB2_GRP1_EnableClockSleep\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH + * @retval None + */ +__STATIC_INLINE void LL_AHB2_GRP1_EnableClockSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->AHB2SMENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHB2SMENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if AHB2 peripheral clock is enabled by the clock gating during CPU1 CSleep mode + * @rmtoll AHB2SMENR GPIOASMEN LL_AHB2_GRP1_IsEnabledClockSleep\n + * AHB2SMENR GPIOBSMEN LL_AHB2_GRP1_IsEnabledClockSleep\n + * AHB2SMENR GPIOCSMEN LL_AHB2_GRP1_IsEnabledClockSleep\n + * AHB2SMENR GPIOHSMEN LL_AHB2_GRP1_IsEnabledClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH + * @retval uint32_t + */ +__STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClockSleep(uint32_t Periphs) +{ + return ((READ_BIT(RCC->AHB2SMENR, Periphs) == (Periphs)) ? 1UL : 0UL); +} + +/** + * @brief Disable AHB2 peripherals clock during Low Power (Sleep) mode. + * @rmtoll AHB2SMENR GPIOASMEN LL_AHB2_GRP1_DisableClockSleep\n + * AHB2SMENR GPIOBSMEN LL_AHB2_GRP1_DisableClockSleep\n + * AHB2SMENR GPIOCSMEN LL_AHB2_GRP1_DisableClockSleep\n + * AHB2SMENR GPIOHSMEN LL_AHB2_GRP1_DisableClockSleep\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH + * @retval None + */ +__STATIC_INLINE void LL_AHB2_GRP1_DisableClockSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB2SMENR, Periphs); +} + +/** + * @} + */ + +/** @defgroup BUS_LL_EF_AHB3 AHB3 + * @{ + */ + +#if defined(DUAL_CORE) /* Switch added for Documentation generation purpose to exclude IPCC in else case*/ +/** + * @brief Enable AHB3 peripherals clock. + * @rmtoll AHB3ENR PKAEN LL_AHB3_GRP1_EnableClock\n + * AHB3ENR AESEN LL_AHB3_GRP1_EnableClock\n + * AHB3ENR RNGEN LL_AHB3_GRP1_EnableClock\n + * AHB3ENR HSEMEN LL_AHB3_GRP1_EnableClock\n + * AHB3ENR IPCCEN LL_AHB3_GRP1_EnableClock\n + * AHB3ENR FLASHEN LL_AHB3_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB3_GRP1_PERIPH_PKA + * @arg @ref LL_AHB3_GRP1_PERIPH_AES + * @arg @ref LL_AHB3_GRP1_PERIPH_RNG + * @arg @ref LL_AHB3_GRP1_PERIPH_HSEM + * @arg @ref LL_AHB3_GRP1_PERIPH_IPCC + * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH + * @retval None + */ + +#else +/** + * @brief Enable AHB3 peripherals clock. + * @rmtoll AHB3ENR PKAEN LL_AHB3_GRP1_EnableClock\n + * AHB3ENR AESEN LL_AHB3_GRP1_EnableClock\n + * AHB3ENR RNGEN LL_AHB3_GRP1_EnableClock\n + * AHB3ENR HSEMEN LL_AHB3_GRP1_EnableClock\n + * AHB3ENR FLASHEN LL_AHB3_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB3_GRP1_PERIPH_PKA + * @arg @ref LL_AHB3_GRP1_PERIPH_AES + * @arg @ref LL_AHB3_GRP1_PERIPH_RNG + * @arg @ref LL_AHB3_GRP1_PERIPH_HSEM + * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH + * @retval None + */ +#endif /* DUAL_CORE */ +__STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->AHB3ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHB3ENR, Periphs); + (void)tmpreg; +} + +#if defined(DUAL_CORE) /* Switch added for Documentation generation purpose to exclude IPCC in else case*/ +/** + * @brief Check if AHB3 peripheral clock is enabled or not + * @rmtoll AHB3ENR PKAEN LL_AHB3_GRP1_IsEnabledClock\n + * AHB3ENR AESEN LL_AHB3_GRP1_IsEnabledClock\n + * AHB3ENR RNGEN LL_AHB3_GRP1_IsEnabledClock\n + * AHB3ENR HSEMEN LL_AHB3_GRP1_IsEnabledClock\n + * AHB3ENR IPCCEN LL_AHB3_GRP1_IsEnabledClock\n + * AHB3ENR FLASHEN LL_AHB3_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB3_GRP1_PERIPH_PKA + * @arg @ref LL_AHB3_GRP1_PERIPH_AES + * @arg @ref LL_AHB3_GRP1_PERIPH_RNG + * @arg @ref LL_AHB3_GRP1_PERIPH_HSEM + * @arg @ref LL_AHB3_GRP1_PERIPH_IPCC + * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH + * @retval uint32_t + */ +#else +/** + * @brief Check if AHB3 peripheral clock is enabled or not + * @rmtoll AHB3ENR PKAEN LL_AHB3_GRP1_IsEnabledClock\n + * AHB3ENR AESEN LL_AHB3_GRP1_IsEnabledClock\n + * AHB3ENR RNGEN LL_AHB3_GRP1_IsEnabledClock\n + * AHB3ENR HSEMEN LL_AHB3_GRP1_IsEnabledClock\n + * AHB3ENR FLASHEN LL_AHB3_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB3_GRP1_PERIPH_PKA + * @arg @ref LL_AHB3_GRP1_PERIPH_AES + * @arg @ref LL_AHB3_GRP1_PERIPH_RNG + * @arg @ref LL_AHB3_GRP1_PERIPH_HSEM + * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH + * @retval uint32_t + */ + +#endif /* DUAL_CORE */ +__STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC->AHB3ENR, Periphs) == (Periphs)) ? 1UL : 0UL); +} + +#if defined(DUAL_CORE) /* Switch added for Documentation generation purpose to exclude IPCC in else case*/ +/** + * @brief Disable AHB3 peripherals clock. + * @rmtoll AHB3ENR PKAEN LL_AHB3_GRP1_DisableClock\n + * AHB3ENR AESEN LL_AHB3_GRP1_DisableClock\n + * AHB3ENR RNGEN LL_AHB3_GRP1_DisableClock\n + * AHB3ENR HSEMEN LL_AHB3_GRP1_DisableClock\n + * AHB3ENR IPCCEN LL_AHB3_GRP1_DisableClock\n + * AHB3ENR FLASHEN LL_AHB3_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB3_GRP1_PERIPH_PKA + * @arg @ref LL_AHB3_GRP1_PERIPH_AES + * @arg @ref LL_AHB3_GRP1_PERIPH_RNG + * @arg @ref LL_AHB3_GRP1_PERIPH_HSEM + * @arg @ref LL_AHB3_GRP1_PERIPH_IPCC + * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH + * @retval None + */ + +#else +/** + * @brief Disable AHB3 peripherals clock. + * @rmtoll AHB3ENR PKAEN LL_AHB3_GRP1_DisableClock\n + * AHB3ENR AESEN LL_AHB3_GRP1_DisableClock\n + * AHB3ENR RNGEN LL_AHB3_GRP1_DisableClock\n + * AHB3ENR HSEMEN LL_AHB3_GRP1_DisableClock\n + * AHB3ENR FLASHEN LL_AHB3_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB3_GRP1_PERIPH_PKA + * @arg @ref LL_AHB3_GRP1_PERIPH_AES + * @arg @ref LL_AHB3_GRP1_PERIPH_RNG + * @arg @ref LL_AHB3_GRP1_PERIPH_HSEM + * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH + * @retval None + */ +#endif /* DUAL_CORE */ +__STATIC_INLINE void LL_AHB3_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB3ENR, Periphs); +} + +#if defined(DUAL_CORE) /* Switch added for Documentation generation purpose to exclude IPCC in else case*/ +/** + * @brief Force AHB3 peripherals reset. + * @rmtoll AHB3RSTR PKARST LL_AHB3_GRP1_ForceReset\n + * AHB3RSTR AESRST LL_AHB3_GRP1_ForceReset\n + * AHB3RSTR RNGRST LL_AHB3_GRP1_ForceReset\n + * AHB3RSTR HSEMRST LL_AHB3_GRP1_ForceReset\n + * AHB3RSTR IPCCRST LL_AHB3_GRP1_ForceReset\n + * AHB3RSTR FLASHRST LL_AHB3_GRP1_ForceReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB3_GRP1_PERIPH_ALL + * @arg @ref LL_AHB3_GRP1_PERIPH_AES + * @arg @ref LL_AHB3_GRP1_PERIPH_PKA + * @arg @ref LL_AHB3_GRP1_PERIPH_RNG + * @arg @ref LL_AHB3_GRP1_PERIPH_HSEM + * @arg @ref LL_AHB3_GRP1_PERIPH_IPCC + * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH + * @retval None + */ +#else +/** + * @brief Force AHB3 peripherals reset. + * @rmtoll AHB3RSTR PKARST LL_AHB3_GRP1_ForceReset\n + * AHB3RSTR AESRST LL_AHB3_GRP1_ForceReset\n + * AHB3RSTR RNGRST LL_AHB3_GRP1_ForceReset\n + * AHB3RSTR HSEMRST LL_AHB3_GRP1_ForceReset\n + * AHB3RSTR FLASHRST LL_AHB3_GRP1_ForceReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB3_GRP1_PERIPH_ALL + * @arg @ref LL_AHB3_GRP1_PERIPH_AES + * @arg @ref LL_AHB3_GRP1_PERIPH_PKA + * @arg @ref LL_AHB3_GRP1_PERIPH_RNG + * @arg @ref LL_AHB3_GRP1_PERIPH_HSEM + * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH + * @retval None + */ + +#endif /* DUAL_CORE */ +__STATIC_INLINE void LL_AHB3_GRP1_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->AHB3RSTR, Periphs); +} + +#if defined(DUAL_CORE) /* Switch added for Documentation generation purpose to exclude IPCC in else case*/ +/** + * @brief Release AHB3 peripherals reset. + * @rmtoll AHB3RSTR PKARST LL_AHB3_GRP1_ReleaseReset\n + * AHB3RSTR AESRST LL_AHB3_GRP1_ReleaseReset\n + * AHB3RSTR RNGRST LL_AHB3_GRP1_ReleaseReset\n + * AHB3RSTR HSEMRST LL_AHB3_GRP1_ReleaseReset\n + * AHB3RSTR IPCCRST LL_AHB3_GRP1_ReleaseReset\n + * AHB3RSTR FLASHRST LL_AHB3_GRP1_ReleaseReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB3_GRP1_PERIPH_ALL + * @arg @ref LL_AHB3_GRP1_PERIPH_PKA + * @arg @ref LL_AHB3_GRP1_PERIPH_AES + * @arg @ref LL_AHB3_GRP1_PERIPH_RNG + * @arg @ref LL_AHB3_GRP1_PERIPH_HSEM + * @arg @ref LL_AHB3_GRP1_PERIPH_IPCC + * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH + * @retval None + */ +#else +/** + * @brief Release AHB3 peripherals reset. + * @rmtoll AHB3RSTR PKARST LL_AHB3_GRP1_ReleaseReset\n + * AHB3RSTR AESRST LL_AHB3_GRP1_ReleaseReset\n + * AHB3RSTR RNGRST LL_AHB3_GRP1_ReleaseReset\n + * AHB3RSTR HSEMRST LL_AHB3_GRP1_ReleaseReset\n + * AHB3RSTR FLASHRST LL_AHB3_GRP1_ReleaseReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB3_GRP1_PERIPH_ALL + * @arg @ref LL_AHB3_GRP1_PERIPH_PKA + * @arg @ref LL_AHB3_GRP1_PERIPH_AES + * @arg @ref LL_AHB3_GRP1_PERIPH_RNG + * @arg @ref LL_AHB3_GRP1_PERIPH_HSEM + * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH + * @retval None + */ + +#endif /* DUAL_CORE */ +__STATIC_INLINE void LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB3RSTR, Periphs); +} + +/** + * @brief Enable AHB3 peripherals clock during Low Power (Sleep) mode. + * @rmtoll AHB3SMENR PKASMEN LL_AHB3_GRP1_EnableClockSleep\n + * AHB3SMENR AESSMEN LL_AHB3_GRP1_EnableClockSleep\n + * AHB3SMENR RNGSMEN LL_AHB3_GRP1_EnableClockSleep\n + * AHB1SMENR SRAM1SMEN LL_AHB1_GRP1_EnableClockSleep\n + * AHB3SMENR SRAM2SMEN LL_AHB3_GRP1_EnableClockSleep\n + * AHB3SMENR FLASHSMEN LL_AHB3_GRP1_EnableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB3_GRP1_PERIPH_PKA + * @arg @ref LL_AHB3_GRP1_PERIPH_AES + * @arg @ref LL_AHB3_GRP1_PERIPH_RNG + * @arg @ref LL_AHB3_GRP1_PERIPH_SRAM1 + * @arg @ref LL_AHB3_GRP1_PERIPH_SRAM2 + * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH + * @retval None + */ +__STATIC_INLINE void LL_AHB3_GRP1_EnableClockSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->AHB3SMENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHB3SMENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if AHB3 peripheral clock is enabled by the clock gating during CPU1 CSleep mode + * @rmtoll AHB3SMENR PKASMEN LL_AHB3_GRP1_IsEnabledClockSleep\n + * AHB3SMENR AESSMEN LL_AHB3_GRP1_IsEnabledClockSleep\n + * AHB3SMENR RNGSMEN LL_AHB3_GRP1_IsEnabledClockSleep\n + * AHB1SMENR SRAM1SMEN LL_AHB3_GRP1_IsEnabledClockSleep\n + * AHB3SMENR SRAM2SMEN LL_AHB3_GRP1_IsEnabledClockSleep\n + * AHB3SMENR FLASHSMEN LL_AHB3_GRP1_IsEnabledClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB3_GRP1_PERIPH_PKA + * @arg @ref LL_AHB3_GRP1_PERIPH_AES + * @arg @ref LL_AHB3_GRP1_PERIPH_RNG + * @arg @ref LL_AHB3_GRP1_PERIPH_SRAM1 + * @arg @ref LL_AHB3_GRP1_PERIPH_SRAM2 + * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH + * @retval None + */ +__STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClockSleep(uint32_t Periphs) +{ + return ((READ_BIT(RCC->AHB3SMENR, Periphs) == (Periphs)) ? 1UL : 0UL); +} + +/** + * @brief Disable AHB3 peripherals clock during Low Power (Sleep) mode. + * @rmtoll AHB3SMENR PKASMEN LL_AHB3_GRP1_DisableClockSleep\n + * AHB3SMENR AESSMEN LL_AHB3_GRP1_DisableClockSleep\n + * AHB3SMENR RNGSMEN LL_AHB3_GRP1_DisableClockSleep\n + * AHB3SMENR SRAM1SMEN LL_AHB3_GRP1_DisableClockSleep\n + * AHB3SMENR SRAM2SMEN LL_AHB3_GRP1_DisableClockSleep\n + * AHB3SMENR FLASHSMEN LL_AHB3_GRP1_DisableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB3_GRP1_PERIPH_PKA + * @arg @ref LL_AHB3_GRP1_PERIPH_AES + * @arg @ref LL_AHB3_GRP1_PERIPH_RNG + * @arg @ref LL_AHB3_GRP1_PERIPH_SRAM1 + * @arg @ref LL_AHB3_GRP1_PERIPH_SRAM2 + * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH + * @retval None + */ +__STATIC_INLINE void LL_AHB3_GRP1_DisableClockSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB3SMENR, Periphs); +} + +/** + * @} + */ + +/** @defgroup BUS_LL_EF_APB1 APB1 + * @{ + */ + +/** + * @brief Enable APB1 peripherals clock. + * @rmtoll APB1ENR1 TIM2EN LL_APB1_GRP1_EnableClock\n + * APB1ENR1 RTCAPBEN LL_APB1_GRP1_EnableClock\n + * APB1ENR1 WWDGEN LL_APB1_GRP1_EnableClock\n + * APB1ENR1 SPI2EN LL_APB1_GRP1_EnableClock\n + * APB1ENR1 USART2EN LL_APB1_GRP1_EnableClock\n + * APB1ENR1 I2C1EN LL_APB1_GRP1_EnableClock\n + * APB1ENR1 I2C2EN LL_APB1_GRP1_EnableClock\n + * APB1ENR1 I2C3EN LL_APB1_GRP1_EnableClock\n + * APB1ENR1 DACEN LL_APB1_GRP1_EnableClock\n + * APB1ENR1 LPTIM1EN LL_APB1_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 + * @arg @ref LL_APB1_GRP1_PERIPH_DAC + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + * @retval None + */ +__STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->APB1ENR1, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB1ENR1, Periphs); + (void)tmpreg; +} + +/** + * @brief Enable APB1 peripherals clock. + * @rmtoll APB1ENR2 LPUART1EN LL_APB1_GRP2_EnableClock\n + * APB1ENR2 LPTIM2EN LL_APB1_GRP2_EnableClock + * APB1ENR2 LPTIM3EN LL_APB1_GRP2_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1 + * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2 + * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM3 + + * @retval None + */ +__STATIC_INLINE void LL_APB1_GRP2_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->APB1ENR2, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB1ENR2, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if APB1 peripheral clock is enabled or not + * @rmtoll APB1ENR1 TIM2EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR1 RTCAPBEN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR1 WWDGEN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR1 SPI2EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR1 USART2EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR1 I2C1EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR1 I2C2EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR1 I2C3EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR1 DACEN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR1 LPTIM1EN LL_APB1_GRP1_IsEnabledClock + + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 + * @arg @ref LL_APB1_GRP1_PERIPH_DAC + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + + * @retval uint32_t + */ +__STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC->APB1ENR1, Periphs) == (Periphs)) ? 1UL : 0UL); +} + +/** + * @brief Check if APB1 peripheral clock is enabled or not + * @rmtoll APB1ENR2 LPUART1EN LL_APB1_GRP2_IsEnabledClock\n + * APB1ENR2 LPTIM2EN LL_APB1_GRP2_IsEnabledClock + * APB1ENR2 LPTIM3EN LL_APB1_GRP2_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1 + * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2 + * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM3 + * @retval uint32_t + */ +__STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC->APB1ENR2, Periphs) == (Periphs)) ? 1UL : 0UL); +} + +/** + * @brief Disable APB1 peripherals clock. + * @rmtoll APB1ENR1 TIM2EN LL_APB1_GRP1_DisableClock\n + * APB1ENR1 RTCAPBEN LL_APB1_GRP1_DisableClock\n + * APB1ENR1 SPI2EN LL_APB1_GRP1_DisableClock\n + * APB1ENR1 USART2EN LL_APB1_GRP1_DisableClock\n + * APB1ENR1 I2C1EN LL_APB1_GRP1_DisableClock\n + * APB1ENR1 I2C2EN LL_APB1_GRP1_DisableClock\n + * APB1ENR1 I2C3EN LL_APB1_GRP1_DisableClock\n + * APB1ENR1 DACEN LL_APB1_GRP1_DisableClock\n + * APB1ENR1 LPTIM1EN LL_APB1_GRP1_DisableClock + + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 + * @arg @ref LL_APB1_GRP1_PERIPH_DAC + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + + * @retval None + */ +__STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB1ENR1, Periphs); +} + +/** + * @brief Disable APB1 peripherals clock. + * @rmtoll APB1ENR2 LPUART1EN LL_APB1_GRP2_DisableClock\n + * APB1ENR2 LPTIM2EN LL_APB1_GRP2_DisableClock + * APB1ENR2 LPTIM3EN LL_APB1_GRP2_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1 + * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2 + * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM3 + * @retval None + */ +__STATIC_INLINE void LL_APB1_GRP2_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB1ENR2, Periphs); +} + +/** + * @brief Force APB1 peripherals reset. + * @rmtoll APB1RSTR1 TIM2RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR1 SPI2RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR1 USART2RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR1 I2C1RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR1 I2C2RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR1 I2C3RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR1 DACRST LL_APB1_GRP1_ForceReset\n + * APB1RSTR1 LPTIM1RST LL_APB1_GRP1_ForceReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_ALL + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 + * @arg @ref LL_APB1_GRP1_PERIPH_DAC + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + + * @retval None + */ +__STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->APB1RSTR1, Periphs); +} + +/** + * @brief Force APB1 peripherals reset. + * @rmtoll APB1RSTR2 LPUART1RST LL_APB1_GRP2_ForceReset\n + * APB1RSTR2 LPTIM2RST LL_APB1_GRP2_ForceReset + * APB1RSTR2 LPTIM3RST LL_APB1_GRP2_ForceReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_ALL + * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1 + * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2 + * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM3 + * @retval None + */ +__STATIC_INLINE void LL_APB1_GRP2_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->APB1RSTR2, Periphs); +} + +/** + * @brief Release APB1 peripherals reset. + * @rmtoll APB1RSTR1 TIM2RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR1 SPI2RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR1 DACRST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR1 I2C1RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR1 I2C2RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR1 I2C3RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR1 DACRST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR1 LPTIM1RST LL_APB1_GRP1_ReleaseReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_ALL + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 + * @arg @ref LL_APB1_GRP1_PERIPH_DAC + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + + * @retval None + */ +__STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB1RSTR1, Periphs); +} + +/** + * @brief Release APB1 peripherals reset. + * @rmtoll APB1RSTR2 LPUART1RST LL_APB1_GRP2_ReleaseReset\n + * APB1RSTR2 LPTIM2RST LL_APB1_GRP2_ReleaseReset + * APB1RSTR2 LPTIM3RST LL_APB1_GRP2_ReleaseReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_ALL + * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1 + * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2 + * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM3 + * @retval None + */ +__STATIC_INLINE void LL_APB1_GRP2_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB1RSTR2, Periphs); +} + +/** + * @brief Enable APB1 peripherals clock during Low Power (Sleep) mode. + * @rmtoll APB1SMENR1 TIM2SMEN LL_APB1_GRP1_EnableClockSleep\n + * APB1SMENR1 RTCAPBSMEN LL_APB1_GRP1_EnableClockSleep\n + * APB1SMENR1 WWDGSMEN LL_APB1_GRP1_EnableClockSleep\n + * APB1SMENR1 SPI2SMEN LL_APB1_GRP1_EnableClockSleep\n + * APB1SMENR1 USART2SMEN LL_APB1_GRP1_EnableClockSleep\n + * APB1SMENR1 I2C1SMEN LL_APB1_GRP1_EnableClockSleep\n + * APB1SMENR1 I2C2SMEN LL_APB1_GRP1_EnableClockSleep\n + * APB1SMENR1 I2C3SMEN LL_APB1_GRP1_EnableClockSleep\n + * APB1SMENR1 DACSMEN LL_APB1_GRP1_EnableClockSleep\n + * APB1SMENR1 LPTIM1SMEN LL_APB1_GRP1_EnableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 + * @arg @ref LL_APB1_GRP1_PERIPH_DAC + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + + * @retval None + */ +__STATIC_INLINE void LL_APB1_GRP1_EnableClockSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->APB1SMENR1, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB1SMENR1, Periphs); + (void)tmpreg; +} + +/** + * @brief Enable APB1 peripherals clock during Low Power (Sleep) mode. + * @rmtoll APB1SMENR2 LPUART1SMEN LL_APB1_GRP2_EnableClockSleep\n + * APB1SMENR2 LPTIM2SMEN LL_APB1_GRP2_EnableClockSleep + * APB1SMENR2 LPTIM3SMEN LL_APB1_GRP2_EnableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1 + * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2 + * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM3 + * @retval None + */ +__STATIC_INLINE void LL_APB1_GRP2_EnableClockSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->APB1SMENR2, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB1SMENR2, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if APB1 clock is enabled by the clock gating during CPU1 CSleep mode + * @rmtoll APB1SMENR1 TIM2SMEN LL_APB1_GRP1_IsEnabledClockSleep\n + * APB1SMENR1 RTCAPBSMEN LL_APB1_GRP1_IsEnabledClockSleep\n + * APB1SMENR1 WWDGSMEN LL_APB1_GRP1_IsEnabledClockSleep\n + * APB1SMENR1 SPI2SMEN LL_APB1_GRP1_IsEnabledClockSleep\n + * APB1SMENR1 USART2SMEN LL_APB1_GRP1_IsEnabledClockSleep\n + * APB1SMENR1 I2C1SMEN LL_APB1_GRP1_IsEnabledClockSleep\n + * APB1SMENR1 I2C2SMEN LL_APB1_GRP1_IsEnabledClockSleep\n + * APB1SMENR1 I2C3SMEN LL_APB1_GRP1_IsEnabledClockSleep\n + * APB1SMENR1 DACSMEN LL_APB1_GRP1_IsEnabledClockSleep\n + * APB1SMENR1 LPTIM1SMEN LL_APB1_GRP1_IsEnabledClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 + * @arg @ref LL_APB1_GRP1_PERIPH_DAC + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + + * @retval None + */ +__STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClockSleep(uint32_t Periphs) +{ + return ((READ_BIT(RCC->APB1SMENR1, Periphs) == (Periphs)) ? 1UL : 0UL); +} + +/** + * @brief Check if APB1 clock is enabled by the clock gating during CPU1 CSleep mode + * @rmtoll APB1SMENR2 LPUART1SMEN LL_APB1_GRP2_IsEnabledClockSleep\n + * APB1SMENR2 LPTIM2SMEN LL_APB1_GRP2_IsEnabledClockSleep\n + * APB1SMENR2 LPTIM3SMEN LL_APB1_GRP2_IsEnabledClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1 + * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2 + * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM3 + * @retval None + */ +__STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClockSleep(uint32_t Periphs) +{ + return ((READ_BIT(RCC->APB1SMENR2, Periphs) == (Periphs)) ? 1UL : 0UL); +} + +/** + * @brief Disable APB1 peripherals clock during Low Power (Sleep) mode. + * @rmtoll APB1SMENR1 TIM2SMEN LL_APB1_GRP1_DisableClockSleep\n + * APB1SMENR1 RTCAPBSMEN LL_APB1_GRP1_DisableClockSleep\n + * APB1SMENR1 WWDGSMEN LL_APB1_GRP1_DisableClockSleep\n + * APB1SMENR1 SPI2SMEN LL_APB1_GRP1_DisableClockSleep\n + * APB1SMENR1 USART2SMEN LL_APB1_GRP1_DisableClockSleep\n + * APB1SMENR1 I2C1SMEN LL_APB1_GRP1_DisableClockSleep\n + * APB1SMENR1 I2C2SMEN LL_APB1_GRP1_DisableClockSleep\n + * APB1SMENR1 I2C3SMEN LL_APB1_GRP1_DisableClockSleep\n + * APB1SMENR1 DACSMEN LL_APB1_GRP1_DisableClockSleep\n + * APB1SMENR1 LPTIM1SMEN LL_APB1_GRP1_DisableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 + * @arg @ref LL_APB1_GRP1_PERIPH_DAC + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + + * @retval None + */ +__STATIC_INLINE void LL_APB1_GRP1_DisableClockSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB1SMENR1, Periphs); +} + +/** + * @brief Disable APB1 peripherals clock during Low Power (Sleep) mode. + * @rmtoll APB1SMENR2 LPUART1SMEN LL_APB1_GRP2_DisableClockSleep\n + * APB1SMENR2 LPTIM2SMEN LL_APB1_GRP2_DisableClockSleep + * APB1SMENR2 LPTIM3SMEN LL_APB1_GRP2_DisableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1 + * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2 + * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM3 + * @retval None + */ +__STATIC_INLINE void LL_APB1_GRP2_DisableClockSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB1SMENR2, Periphs); +} + +/** + * @} + */ + +/** @defgroup BUS_LL_EF_APB2 APB2 + * @{ + */ + +/** + * @brief Enable APB2 peripherals clock. + * @rmtoll APB2ENR ADCEN LL_APB2_GRP1_EnableClock\n + * APB2ENR TIM1EN LL_APB2_GRP1_EnableClock\n + * APB2ENR SPI1EN LL_APB2_GRP1_EnableClock\n + * APB2ENR USART1EN LL_APB2_GRP1_EnableClock\n + * APB2ENR TIM16EN LL_APB2_GRP1_EnableClock\n + * APB2ENR TIM17EN LL_APB2_GRP1_EnableClock\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_ADC + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 + * @retval None + */ +__STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->APB2ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB2ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if APB2 peripheral clock is enabled or not + * @rmtoll APB2ENR ADCEN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR TIM1EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR TIM16EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR TIM17EN LL_APB2_GRP1_IsEnabledClock\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_ADC + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 + * @retval uint32_t + */ +__STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC->APB2ENR, Periphs) == (Periphs)) ? 1UL : 0UL); +} + +/** + * @brief Disable APB2 peripherals clock. + * @rmtoll APB2ENR ADCEN LL_APB2_GRP1_DisableClock\n + * APB2ENR TIM1EN LL_APB2_GRP1_DisableClock\n + * APB2ENR SPI1EN LL_APB2_GRP1_DisableClock\n + * APB2ENR USART1EN LL_APB2_GRP1_DisableClock\n + * APB2ENR TIM16EN LL_APB2_GRP1_DisableClock\n + * APB2ENR TIM17EN LL_APB2_GRP1_DisableClock\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_ADC + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 + * @retval None + */ +__STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB2ENR, Periphs); +} + +/** + * @brief Force APB2 peripherals reset. + * @rmtoll APB2RSTR ADCRST LL_APB2_GRP1_ForceReset\n + * APB2RSTR TIM1RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR USART1RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR TIM16RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR TIM17RST LL_APB2_GRP1_ForceReset\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_ALL + * @arg @ref LL_APB2_GRP1_PERIPH_ADC + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 + * @retval None + */ +__STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->APB2RSTR, Periphs); +} + +/** + * @brief Release APB2 peripherals reset. + * @rmtoll APB2RSTR ADCRST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR TIM1RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR SPI1RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR USART1RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR TIM16RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR TIM17RST LL_APB2_GRP1_ReleaseReset\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_ALL + * @arg @ref LL_APB2_GRP1_PERIPH_ADC + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 + * @retval None + */ +__STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB2RSTR, Periphs); +} + +/** + * @brief Enable APB2 peripherals clock during Low Power (Sleep) mode. + * @rmtoll APB2SMENR ADCSMEN LL_APB2_GRP1_EnableClockSleep\n + * APB2SMENR TIM1SMEN LL_APB2_GRP1_EnableClockSleep\n + * APB2SMENR SPI1SMEN LL_APB2_GRP1_EnableClockSleep\n + * APB2SMENR USART1SMEN LL_APB2_GRP1_EnableClockSleep\n + * APB2SMENR TIM16SMEN LL_APB2_GRP1_EnableClockSleep\n + * APB2SMENR TIM17SMEN LL_APB2_GRP1_EnableClockSleep\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_ADC + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 + * @retval None + */ +__STATIC_INLINE void LL_APB2_GRP1_EnableClockSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->APB2SMENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB2SMENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if APB2 clock is enabled by the clock gating during CPU1 CSleep mode + * @rmtoll APB2SMENR ADCSMEN LL_APB2_GRP1_IsEnabledClockSleep\n + * APB2SMENR TIM1SMEN LL_APB2_GRP1_IsEnabledClockSleep\n + * APB2SMENR SPI1SMEN LL_APB2_GRP1_IsEnabledClockSleep\n + * APB2SMENR USART1SMEN LL_APB2_GRP1_IsEnabledClockSleep\n + * APB2SMENR TIM16SMEN LL_APB2_GRP1_IsEnabledClockSleep\n + * APB2SMENR TIM17SMEN LL_APB2_GRP1_IsEnabledClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_ADC + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 + * @retval None + */ +__STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClockSleep(uint32_t Periphs) +{ + return ((READ_BIT(RCC->APB2SMENR, Periphs) == (Periphs)) ? 1UL : 0UL); +} + +/** + * @brief Disable APB2 peripherals clock during Low Power (Sleep) mode. + * @rmtoll APB2SMENR ADCSMEN LL_APB2_GRP1_DisableClockSleep\n + * APB2SMENR TIM1SMEN LL_APB2_GRP1_DisableClockSleep\n + * APB2SMENR SPI1SMEN LL_APB2_GRP1_DisableClockSleep\n + * APB2SMENR USART1SMEN LL_APB2_GRP1_DisableClockSleep\n + * APB2SMENR TIM16SMEN LL_APB2_GRP1_DisableClockSleep\n + * APB2SMENR TIM17SMEN LL_APB2_GRP1_DisableClockSleep\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_ADC + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 + * @retval None + */ +__STATIC_INLINE void LL_APB2_GRP1_DisableClockSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB2SMENR, Periphs); +} + +/** + * @} + */ + +/** @defgroup BUS_LL_EF_APB3 APB3 + * @{ + */ + +/** + * @brief Enable APB3 peripherals clock. + * @rmtoll APB3ENR SUBGHZSPIEN LL_APB3_GRP1_EnableClock\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB3_GRP1_PERIPH_SUBGHZSPI + * @retval None + */ +__STATIC_INLINE void LL_APB3_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->APB3ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB3ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if APB3 peripheral clock is enabled or not + * @rmtoll APB3ENR SUBGHZSPIEN LL_APB3_GRP1_IsEnabledClock\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB3_GRP1_PERIPH_SUBGHZSPI + * @retval uint32_t + */ +__STATIC_INLINE uint32_t LL_APB3_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC->APB3ENR, Periphs) == (Periphs)) ? 1UL : 0UL); +} + +/** + * @brief Disable APB3 peripherals clock. + * @rmtoll APB3ENR SUBGHZSPIEN LL_APB3_GRP1_DisableClock\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB3_GRP1_PERIPH_SUBGHZSPI + * @retval None + */ +__STATIC_INLINE void LL_APB3_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB3ENR, Periphs); +} + + +/** + * @brief Force APB3 peripherals reset. + * @rmtoll APB3RSTR SUBGHZSPIRST LL_APB3_GRP1_ForceReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB3_GRP1_PERIPH_SUBGHZSPI + * @retval None + */ +__STATIC_INLINE void LL_APB3_GRP1_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->APB3RSTR, Periphs); +} + +/** + * @brief Release APB3 peripherals reset. + * @rmtoll APB3RSTR SUBGHZSPIRST LL_APB3_GRP1_ReleaseReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB3_GRP1_PERIPH_SUBGHZSPI + * @retval None + */ +__STATIC_INLINE void LL_APB3_GRP1_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB3RSTR, Periphs); +} + +/** + * @brief Enable APB3 peripherals clock during Low Power (Sleep) mode. + * @rmtoll APB3SMENR SUBGHZSPISMEN LL_APB3_GRP1_EnableClockSleep\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB3_GRP1_PERIPH_SUBGHZSPI + * @retval None + */ +__STATIC_INLINE void LL_APB3_GRP1_EnableClockSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->APB3SMENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB3SMENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if APB3 clock is enabled by the clock gating during CPU1 CSleep mode + * @rmtoll APB3SMENR SUBGHZSPISMEN LL_APB3_GRP1_IsEnabledClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB3_GRP1_PERIPH_SUBGHZSPI + * @retval None + */ +__STATIC_INLINE uint32_t LL_APB3_GRP1_IsEnabledClockSleep(uint32_t Periphs) +{ + return ((READ_BIT(RCC->APB3SMENR, Periphs) == (Periphs)) ? 1UL : 0UL); +} + +/** + * @brief Disable APB3 peripherals clock during Low Power (Sleep) mode. + * @rmtoll APB3SMENR SUBGHZSPISMEN LL_APB3_GRP1_DisableClockSleep\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB3_GRP1_PERIPH_SUBGHZSPI + * @retval None + */ +__STATIC_INLINE void LL_APB3_GRP1_DisableClockSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB3SMENR, Periphs); +} + + +/** + * @} + */ + +#if defined(DUAL_CORE) +/** @defgroup BUS_LL_EF_C2_AHB1 C2 AHB1 + * @{ + */ +/** + * @brief Enable C2AHB1 peripherals clock. + * @rmtoll C2AHB1ENR DMA1EN LL_C2_AHB1_GRP1_EnableClock\n + * C2AHB1ENR DMA2EN LL_C2_AHB1_GRP1_EnableClock\n + * C2AHB1ENR DMAMUX1EN LL_C2_AHB1_GRP1_EnableClock\n + * C2AHB1ENR CRCEN LL_C2_AHB1_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMAMUX1 + * @arg @ref LL_C2_AHB1_GRP1_PERIPH_CRC + * @retval None + */ +__STATIC_INLINE void LL_C2_AHB1_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->C2AHB1ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->C2AHB1ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if C2AHB1 peripheral clock is enabled or not + * @rmtoll C2AHB1ENR DMA1EN LL_C2_AHB1_GRP1_IsEnabledClock\n + * C2AHB1ENR DMA2EN LL_C2_AHB1_GRP1_IsEnabledClock\n + * C2AHB1ENR DMAMUX1EN LL_C2_AHB1_GRP1_IsEnabledClock\n + * C2AHB1ENR CRCEN LL_C2_AHB1_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMAMUX1 + * @arg @ref LL_C2_AHB1_GRP1_PERIPH_CRC + * @retval uint32_t + */ +__STATIC_INLINE uint32_t LL_C2_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC->C2AHB1ENR, Periphs) == (Periphs)) ? 1UL : 0UL); +} + +/** + * @brief Disable C2AHB1 peripherals clock. + * @rmtoll C2AHB1ENR DMA1EN LL_C2_AHB1_GRP1_DisableClock\n + * C2AHB1ENR DMA2EN LL_C2_AHB1_GRP1_DisableClock\n + * C2AHB1ENR DMAMUX1EN LL_C2_AHB1_GRP1_DisableClock\n + * C2AHB1ENR CRCEN LL_C2_AHB1_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMAMUX1 + * @arg @ref LL_C2_AHB1_GRP1_PERIPH_CRC + * @retval None + */ +__STATIC_INLINE void LL_C2_AHB1_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->C2AHB1ENR, Periphs); +} + +/** + * @brief Enable C2AHB1 peripherals clock during Low Power (Sleep) mode. + * @rmtoll C2AHB1SMENR DMA1SMEN LL_C2_AHB1_GRP1_EnableClockSleep\n + * C2AHB1SMENR DMA2SMEN LL_C2_AHB1_GRP1_EnableClockSleep\n + * C2AHB1SMENR DMAMUX1SMEN LL_C2_AHB1_GRP1_EnableClockSleep\n + * C2AHB1SMENR CRCSMEN LL_C2_AHB1_GRP1_EnableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMAMUX1 + * @arg @ref LL_C2_AHB1_GRP1_PERIPH_CRC + * @retval None + */ +__STATIC_INLINE void LL_C2_AHB1_GRP1_EnableClockSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->C2AHB1SMENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->C2AHB1SMENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if C2AHB1 peripheral clock is enabled by the clock gating during CPU1 CSleep mode. + * @rmtoll C2AHB1SMENR DMA1SMEN LL_C2_AHB1_GRP1_IsEnabledClockSleep\n + * C2AHB1SMENR DMA2SMEN LL_C2_AHB1_GRP1_IsEnabledClockSleep\n + * C2AHB1SMENR DMAMUX1SMEN LL_C2_AHB1_GRP1_IsEnabledClockSleep\n + * C2AHB1SMENR CRCSMEN LL_C2_AHB1_GRP1_IsEnabledClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMAMUX1 + * @arg @ref LL_C2_AHB1_GRP1_PERIPH_CRC + * @retval None + */ +__STATIC_INLINE uint32_t LL_C2_AHB1_GRP1_IsEnabledClockSleep(uint32_t Periphs) +{ + return ((READ_BIT(RCC->C2AHB1SMENR, Periphs) == (Periphs)) ? 1UL : 0UL); +} + +/** + * @brief Disable C2AHB1 peripherals clock during Low Power (Sleep) mode. + * @rmtoll C2AHB1SMENR DMA1SMEN LL_C2_AHB1_GRP1_DisableClockSleep\n + * C2AHB1SMENR DMA2SMEN LL_C2_AHB1_GRP1_DisableClockSleep\n + * C2AHB1SMENR DMAMUX1SMEN LL_C2_AHB1_GRP1_DisableClockSleep\n + * C2AHB1SMENR CRCSMEN LL_C2_AHB1_GRP1_DisableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMAMUX1 + * @arg @ref LL_C2_AHB1_GRP1_PERIPH_CRC + * @retval None + */ +__STATIC_INLINE void LL_C2_AHB1_GRP1_DisableClockSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC->C2AHB1SMENR, Periphs); +} + +/** + * @} + */ + +/** @defgroup BUS_LL_EF_C2_AHB2 C2 AHB2 + * @{ + */ + +/** + * @brief Enable C2AHB2 peripherals clock. + * @rmtoll C2AHB2ENR GPIOAEN LL_C2_AHB2_GRP1_EnableClock\n + * C2AHB2ENR GPIOBEN LL_C2_AHB2_GRP1_EnableClock\n + * C2AHB2ENR GPIOCEN LL_C2_AHB2_GRP1_EnableClock\n + * C2AHB2ENR GPIOHEN LL_C2_AHB2_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOA + * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOB + * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOC + * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOH + * @retval None + */ +__STATIC_INLINE void LL_C2_AHB2_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->C2AHB2ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->C2AHB2ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if C2AHB2 peripheral clock is enabled or not + * @rmtoll C2AHB2ENR GPIOAEN LL_C2_AHB2_GRP1_IsEnabledClock\n + * C2AHB2ENR GPIOBEN LL_C2_AHB2_GRP1_IsEnabledClock\n + * C2AHB2ENR GPIOCEN LL_C2_AHB2_GRP1_IsEnabledClock\n + * C2AHB2ENR GPIOHEN LL_C2_AHB2_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOA + * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOB + * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOC + * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOH + * @retval uint32_t + */ +__STATIC_INLINE uint32_t LL_C2_AHB2_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC->C2AHB2ENR, Periphs) == (Periphs)) ? 1UL : 0UL); +} + +/** + * @brief Disable C2AHB2 peripherals clock. + * @rmtoll C2AHB2ENR GPIOAEN LL_C2_AHB2_GRP1_DisableClock\n + * C2AHB2ENR GPIOBEN LL_C2_AHB2_GRP1_DisableClock\n + * C2AHB2ENR GPIOCEN LL_C2_AHB2_GRP1_DisableClock\n + * C2AHB2ENR GPIOHEN LL_C2_AHB2_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOA + * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOB + * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOC + * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOH + * @retval None + */ +__STATIC_INLINE void LL_C2_AHB2_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->C2AHB2ENR, Periphs); +} + +/** + * @brief Enable C2AHB2 peripherals clock during Low Power (Sleep) mode. + * @rmtoll C2AHB2SMENR GPIOASMEN LL_C2_AHB2_GRP1_EnableClockSleep\n + * C2AHB2SMENR GPIOBSMEN LL_C2_AHB2_GRP1_EnableClockSleep\n + * C2AHB2SMENR GPIOCSMEN LL_C2_AHB2_GRP1_EnableClockSleep\n + * C2AHB2SMENR GPIOHSMEN LL_C2_AHB2_GRP1_EnableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOA + * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOB + * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOC + * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOH + * @retval None + */ +__STATIC_INLINE void LL_C2_AHB2_GRP1_EnableClockSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->C2AHB2SMENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->C2AHB2SMENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if C2AHB2 peripheral clock is enabled by the clock gating during CPU1 CSleep mode. + * @rmtoll C2AHB2SMENR GPIOASMEN LL_C2_AHB2_GRP1_IsEnabledClockSleep\n + * C2AHB2SMENR GPIOBSMEN LL_C2_AHB2_GRP1_IsEnabledClockSleep\n + * C2AHB2SMENR GPIOCSMEN LL_C2_AHB2_GRP1_IsEnabledClockSleep\n + * C2AHB2SMENR GPIOHSMEN LL_C2_AHB2_GRP1_IsEnabledClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOA + * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOB + * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOC + * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOH + * @retval None + */ +__STATIC_INLINE uint32_t LL_C2_AHB2_GRP1_IsEnabledClockSleep(uint32_t Periphs) +{ + return ((READ_BIT(RCC->C2AHB2SMENR, Periphs) == (Periphs)) ? 1UL : 0UL); +} + +/** + * @brief Disable C2AHB2 peripherals clock during Low Power (Sleep) mode. + * @rmtoll C2AHB2SMENR GPIOASMEN LL_C2_AHB2_GRP1_DisableClockSleep\n + * C2AHB2SMENR GPIOBSMEN LL_C2_AHB2_GRP1_DisableClockSleep\n + * C2AHB2SMENR GPIOCSMEN LL_C2_AHB2_GRP1_DisableClockSleep\n + * C2AHB2SMENR GPIOHSMEN LL_C2_AHB2_GRP1_DisableClockSleep\n + + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOA + * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOB + * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOC + * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOH + * @retval None + */ +__STATIC_INLINE void LL_C2_AHB2_GRP1_DisableClockSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC->C2AHB2SMENR, Periphs); +} + +/** + * @} + */ + +/** @defgroup BUS_LL_EF_C2_AHB3 C2 AHB3 + * @{ + */ + +/** + * @brief Enable C2AHB3 peripherals clock. + * @rmtoll C2AHB3ENR PKAEN LL_C2_AHB3_GRP1_EnableClock\n + * C2AHB3ENR AESEN LL_C2_AHB3_GRP1_EnableClock\n + * C2AHB3ENR RNGEN LL_C2_AHB3_GRP1_EnableClock\n + * C2AHB3ENR HSEMEN LL_C2_AHB3_GRP1_EnableClock\n + * C2AHB3ENR IPCCEN LL_C2_AHB3_GRP1_EnableClock\n + * C2AHB3ENR FLASHEN LL_C2_AHB3_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_C2_AHB3_GRP1_PERIPH_PKA + * @arg @ref LL_C2_AHB3_GRP1_PERIPH_AES + * @arg @ref LL_C2_AHB3_GRP1_PERIPH_RNG + * @arg @ref LL_C2_AHB3_GRP1_PERIPH_HSEM + * @arg @ref LL_C2_AHB3_GRP1_PERIPH_IPCC + * @arg @ref LL_C2_AHB3_GRP1_PERIPH_FLASH + * @retval None + */ +__STATIC_INLINE void LL_C2_AHB3_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->C2AHB3ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->C2AHB3ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if C2AHB3 peripheral clock is enabled or not + * @rmtoll C2AHB3ENR PKAEN LL_C2_AHB3_GRP1_IsEnabledClock\n + * C2AHB3ENR AESEN LL_C2_AHB3_GRP1_IsEnabledClock\n + * C2AHB3ENR RNGEN LL_C2_AHB3_GRP1_IsEnabledClock\n + * C2AHB3ENR HSEMEN LL_C2_AHB3_GRP1_IsEnabledClock\n + * C2AHB3ENR IPCCEN LL_C2_AHB3_GRP1_IsEnabledClock\n + * C2AHB3ENR FLASHEN LL_C2_AHB3_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_C2_AHB3_GRP1_PERIPH_PKA + * @arg @ref LL_C2_AHB3_GRP1_PERIPH_AES + * @arg @ref LL_C2_AHB3_GRP1_PERIPH_RNG + * @arg @ref LL_C2_AHB3_GRP1_PERIPH_HSEM + * @arg @ref LL_C2_AHB3_GRP1_PERIPH_IPCC + * @arg @ref LL_C2_AHB3_GRP1_PERIPH_FLASH + * @retval uint32_t + */ +__STATIC_INLINE uint32_t LL_C2_AHB3_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC->C2AHB3ENR, Periphs) == (Periphs)) ? 1UL : 0UL); +} + +/** + * @brief Disable C2AHB3 peripherals clock. + * @rmtoll C2AHB3ENR PKAEN LL_C2_AHB3_GRP1_DisableClock\n + * C2AHB3ENR AESEN LL_C2_AHB3_GRP1_DisableClock\n + * C2AHB3ENR RNGEN LL_C2_AHB3_GRP1_DisableClock\n + * C2AHB3ENR HSEMEN LL_C2_AHB3_GRP1_DisableClock\n + * C2AHB3ENR IPCCEN LL_C2_AHB3_GRP1_DisableClock\n + * C2AHB3ENR FLASHEN LL_C2_AHB3_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_C2_AHB3_GRP1_PERIPH_PKA + * @arg @ref LL_C2_AHB3_GRP1_PERIPH_AES + * @arg @ref LL_C2_AHB3_GRP1_PERIPH_RNG + * @arg @ref LL_C2_AHB3_GRP1_PERIPH_HSEM + * @arg @ref LL_C2_AHB3_GRP1_PERIPH_IPCC + * @arg @ref LL_C2_AHB3_GRP1_PERIPH_FLASH + * @retval None + */ +__STATIC_INLINE void LL_C2_AHB3_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->C2AHB3ENR, Periphs); +} + +/** + * @brief Enable C2AHB3 peripherals clock during Low Power (Sleep) mode. + * @rmtoll C2AHB3SMENR PKASMEN LL_C2_AHB3_GRP1_EnableClockSleep\n + * C2AHB3SMENR AESSMEN LL_C2_AHB3_GRP1_EnableClockSleep\n + * C2AHB3SMENR RNGSMEN LL_C2_AHB3_GRP1_EnableClockSleep\n + * C2AHB3SMENR SRAM1SMEN LL_C2_AHB3_GRP1_EnableClockSleep\n + * C2AHB3SMENR SRAM2SMEN LL_C2_AHB3_GRP1_EnableClockSleep\n + * C2AHB3SMENR FLASHSMEN LL_C2_AHB3_GRP1_EnableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_C2_AHB3_GRP1_PERIPH_PKA + * @arg @ref LL_C2_AHB3_GRP1_PERIPH_AES + * @arg @ref LL_C2_AHB3_GRP1_PERIPH_RNG + * @arg @ref LL_C2_AHB3_GRP1_PERIPH_SRAM1 + * @arg @ref LL_C2_AHB3_GRP1_PERIPH_SRAM2 + * @arg @ref LL_C2_AHB3_GRP1_PERIPH_FLASH + * @retval None + */ +__STATIC_INLINE void LL_C2_AHB3_GRP1_EnableClockSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->C2AHB3SMENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->C2AHB3SMENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if C2AHB3 peripheral clock is enabled by the clock gating during CPU1 CSleep mode. + * @rmtoll C2AHB3SMENR PKASMEN LL_C2_AHB3_GRP1_IsEnabledClockSleep\n + * C2AHB3SMENR AESSMEN LL_C2_AHB3_GRP1_IsEnabledClockSleep\n + * C2AHB3SMENR RNGSMEN LL_C2_AHB3_GRP1_IsEnabledClockSleep\n + * C2AHB3SMENR SRAM1SMEN LL_C2_AHB3_GRP1_IsEnabledClockSleep\n + * C2AHB3SMENR SRAM2SMEN LL_C2_AHB3_GRP1_IsEnabledClockSleep\n + * C2AHB3SMENR FLASHSMEN LL_C2_AHB3_GRP1_IsEnabledClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_C2_AHB3_GRP1_PERIPH_PKA + * @arg @ref LL_C2_AHB3_GRP1_PERIPH_AES + * @arg @ref LL_C2_AHB3_GRP1_PERIPH_RNG + * @arg @ref LL_C2_AHB3_GRP1_PERIPH_SRAM1 + * @arg @ref LL_C2_AHB3_GRP1_PERIPH_SRAM2 + * @arg @ref LL_C2_AHB3_GRP1_PERIPH_FLASH + * @retval None + */ +__STATIC_INLINE uint32_t LL_C2_AHB3_GRP1_IsEnabledClockSleep(uint32_t Periphs) +{ + return ((READ_BIT(RCC->C2AHB3SMENR, Periphs) == (Periphs)) ? 1UL : 0UL); +} + +/** + * @brief Disable C2AHB3 peripherals clock during Low Power (Sleep) mode. + * @rmtoll C2AHB3SMENR PKASMEN LL_C2_AHB3_GRP1_DisableClockSleep\n + * C2AHB3SMENR AESSMEN LL_C2_AHB3_GRP1_DisableClockSleep\n + * C2AHB3SMENR RNGSMEN LL_C2_AHB3_GRP1_DisableClockSleep\n + * C2AHB3SMENR SRAM2SMEN LL_C2_AHB3_GRP1_DisableClockSleep\n + * C2AHB3SMENR FLASHSMEN LL_C2_AHB3_GRP1_DisableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_C2_AHB3_GRP1_PERIPH_PKA + * @arg @ref LL_C2_AHB3_GRP1_PERIPH_AES + * @arg @ref LL_C2_AHB3_GRP1_PERIPH_RNG + * @arg @ref LL_C2_AHB3_GRP1_PERIPH_SRAM2 + * @arg @ref LL_C2_AHB3_GRP1_PERIPH_FLASH + * @retval None + */ +__STATIC_INLINE void LL_C2_AHB3_GRP1_DisableClockSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC->C2AHB3SMENR, Periphs); +} + +/** + * @} + */ + +/** @defgroup BUS_LL_EF_C2_APB1 C2 APB1 + * @{ + */ + +/** + * @brief Enable C2APB1 peripherals clock. + * @rmtoll C2APB1ENR1 TIM2EN LL_C2_APB1_GRP1_EnableClock\n + * C2APB1ENR1 RTCAPBEN LL_C2_APB1_GRP1_EnableClock\n + * C2APB1ENR1 SPI2EN LL_C2_APB1_GRP1_EnableClock\n + * C2APB1ENR1 USART2EN LL_C2_APB1_GRP1_EnableClock\n + * C2APB1ENR1 I2C1EN LL_C2_APB1_GRP1_EnableClock\n + * C2APB1ENR1 I2C2EN LL_C2_APB1_GRP1_EnableClock\n + * C2APB1ENR1 I2C3EN LL_C2_APB1_GRP1_EnableClock\n + * C2APB1ENR1 DACEN LL_C2_APB1_GRP1_EnableClock\n + * C2APB1ENR1 LPTIM1EN LL_C2_APB1_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_C2_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_C2_APB1_GRP1_PERIPH_RTCAPB + * @arg @ref LL_C2_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_C2_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_C2_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_C2_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_C2_APB1_GRP1_PERIPH_I2C3 + * @arg @ref LL_C2_APB1_GRP1_PERIPH_DAC + * @arg @ref LL_C2_APB1_GRP1_PERIPH_LPTIM1 + + * @retval None + */ +__STATIC_INLINE void LL_C2_APB1_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->C2APB1ENR1, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->C2APB1ENR1, Periphs); + (void)tmpreg; +} + +/** + * @brief Enable C2APB1 peripherals clock. + * @rmtoll C2APB1ENR2 LPUART1EN LL_C2_APB1_GRP2_EnableClock\n + * C2APB1ENR2 LPTIM2EN LL_C2_APB1_GRP2_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_C2_APB1_GRP2_PERIPH_LPUART1 + * @arg @ref LL_C2_APB1_GRP2_PERIPH_LPTIM2 + * @retval None + */ +__STATIC_INLINE void LL_C2_APB1_GRP2_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->C2APB1ENR2, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->C2APB1ENR2, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if C2APB1 peripheral clock is enabled or not + * @rmtoll C2APB1ENR1 TIM2EN LL_C2_APB1_GRP1_IsEnabledClock\n + * C2APB1ENR1 RTCAPBEN LL_C2_APB1_GRP1_IsEnabledClock\n + * C2APB1ENR1 SPI2EN LL_C2_APB1_GRP1_IsEnabledClock\n + * C2APB1ENR1 USART2EN LL_C2_APB1_GRP1_IsEnabledClock\n + * C2APB1ENR1 I2C1EN LL_C2_APB1_GRP1_IsEnabledClock\n + * C2APB1ENR1 I2C2EN LL_C2_APB1_GRP1_IsEnabledClock\n + * C2APB1ENR1 I2C3EN LL_C2_APB1_GRP1_IsEnabledClock\n + * C2APB1ENR1 DACEN LL_C2_APB1_GRP1_IsEnabledClock\n + * C2APB1ENR1 LPTIM1EN LL_C2_APB1_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_C2_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_C2_APB1_GRP1_PERIPH_RTCAPB + * @arg @ref LL_C2_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_C2_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_C2_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_C2_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_C2_APB1_GRP1_PERIPH_I2C3 + * @arg @ref LL_C2_APB1_GRP1_PERIPH_DAC + * @arg @ref LL_C2_APB1_GRP1_PERIPH_LPTIM1 + + * @retval uint32_t + */ +__STATIC_INLINE uint32_t LL_C2_APB1_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC->C2APB1ENR1, Periphs) == (Periphs)) ? 1UL : 0UL); +} + +/** + * @brief Check if C2APB1 peripheral clock is enabled or not + * @rmtoll C2APB1ENR2 LPUART1EN LL_C2_APB1_GRP2_IsEnabledClock\n + * C2APB1ENR2 LPTIM2EN LL_C2_APB1_GRP2_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_C2_APB1_GRP2_PERIPH_LPUART1 + * @arg @ref LL_C2_APB1_GRP2_PERIPH_LPTIM2 + * @retval uint32_t + */ +__STATIC_INLINE uint32_t LL_C2_APB1_GRP2_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC->C2APB1ENR2, Periphs) == (Periphs)) ? 1UL : 0UL); +} + +/** + * @brief Disable C2APB1 peripherals clock. + * @rmtoll C2APB1ENR1 TIM2EN LL_C2_APB1_GRP1_DisableClock\n + * C2APB1ENR1 RTCAPBEN LL_C2_APB1_GRP1_DisableClock\n + * C2APB1ENR1 SPI2EN LL_C2_APB1_GRP1_DisableClock\n + * C2APB1ENR1 USART2EN LL_C2_APB1_GRP1_DisableClock\n + * C2APB1ENR1 I2C1EN LL_C2_APB1_GRP1_DisableClock\n + * C2APB1ENR1 I2C2EN LL_C2_APB1_GRP1_DisableClock\n + * C2APB1ENR1 I2C3EN LL_C2_APB1_GRP1_DisableClock\n + * C2APB1ENR1 DACEN LL_C2_APB1_GRP1_DisableClock\n + * C2APB1ENR1 LPTIM1EN LL_C2_APB1_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_C2_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_C2_APB1_GRP1_PERIPH_RTCAPB + * @arg @ref LL_C2_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_C2_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_C2_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_C2_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_C2_APB1_GRP1_PERIPH_I2C3 + * @arg @ref LL_C2_APB1_GRP1_PERIPH_DAC + * @arg @ref LL_C2_APB1_GRP1_PERIPH_LPTIM1 + + * @retval None + */ +__STATIC_INLINE void LL_C2_APB1_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->C2APB1ENR1, Periphs); +} + +/** + * @brief Disable C2APB1 peripherals clock. + * @rmtoll C2APB1ENR2 LPUART1EN LL_C2_APB1_GRP2_DisableClock\n + * C2APB1ENR2 LPTIM2EN LL_C2_APB1_GRP2_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_C2_APB1_GRP2_PERIPH_LPUART1 + * @arg @ref LL_C2_APB1_GRP2_PERIPH_LPTIM2 + * @retval None + */ +__STATIC_INLINE void LL_C2_APB1_GRP2_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->C2APB1ENR2, Periphs); +} + +/** + * @brief Enable C2APB1 peripherals clock during Low Power (Sleep) mode. + * @rmtoll C2APB1SMENR1 TIM2SMEN LL_C2_APB1_GRP1_EnableClockSleep\n + * C2APB1SMENR1 RTCAPBSMEN LL_C2_APB1_GRP1_EnableClockSleep\n + * C2APB1SMENR1 SPI2SMEN LL_C2_APB1_GRP1_EnableClockSleep\n + * C2APB1SMENR1 USART2SMEN LL_C2_APB1_GRP1_EnableClockSleep\n + * C2APB1SMENR1 I2C1SMEN LL_C2_APB1_GRP1_EnableClockSleep\n + * C2APB1SMENR1 I2C2SMEN LL_C2_APB1_GRP1_EnableClockSleep\n + * C2APB1SMENR1 I2C3SMEN LL_C2_APB1_GRP1_EnableClockSleep\n + * C2APB1SMENR1 DACSMEN LL_C2_APB1_GRP1_EnableClockSleep\n + * C2APB1SMENR1 LPTIM1SMEN LL_C2_APB1_GRP1_EnableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_C2_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_C2_APB1_GRP1_PERIPH_RTCAPB + * @arg @ref LL_C2_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_C2_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_C2_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_C2_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_C2_APB1_GRP1_PERIPH_I2C3 + * @arg @ref LL_C2_APB1_GRP1_PERIPH_DAC + * @arg @ref LL_C2_APB1_GRP1_PERIPH_LPTIM1 + * @retval None + */ +__STATIC_INLINE void LL_C2_APB1_GRP1_EnableClockSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->C2APB1SMENR1, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->C2APB1SMENR1, Periphs); + (void)tmpreg; +} + +/** + * @brief Enable C2APB1 peripherals clock during Low Power (Sleep) mode. + * @rmtoll C2APB1SMENR2 LPUART1SMEN LL_C2_APB1_GRP2_EnableClockSleep\n + * C2APB1SMENR2 LPTIM2SMEN LL_C2_APB1_GRP2_EnableClockSleep\n + * C2APB1SMENR2 LPTIM3SMEN LL_C2_APB1_GRP2_EnableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_C2_APB1_GRP2_PERIPH_LPUART1 + * @arg @ref LL_C2_APB1_GRP2_PERIPH_LPTIM2 + * @arg @ref LL_C2_APB1_GRP2_PERIPH_LPTIM3 + * @retval None + */ +__STATIC_INLINE void LL_C2_APB1_GRP2_EnableClockSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->C2APB1SMENR2, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->C2APB1SMENR2, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if C2APB1 peripheral clock is enabled by the clock gating during CPU1 CSleep mode. + * @rmtoll C2APB1SMENR1 TIM2SMEN LL_C2_APB1_GRP1_IsEnabledClockSleep\n + * C2APB1SMENR1 RTCAPBSMEN LL_C2_APB1_GRP1_IsEnabledClockSleep\n + * C2APB1SMENR1 SPI2SMEN LL_C2_APB1_GRP1_IsEnabledClockSleep\n + * C2APB1SMENR1 USART2SMEN LL_C2_APB1_GRP1_IsEnabledClockSleep\n + * C2APB1SMENR1 I2C1SMEN LL_C2_APB1_GRP1_IsEnabledClockSleep\n + * C2APB1SMENR1 I2C2SMEN LL_C2_APB1_GRP1_IsEnabledClockSleep\n + * C2APB1SMENR1 I2C3SMEN LL_C2_APB1_GRP1_IsEnabledClockSleep\n + * C2APB1SMENR1 DACSMEN LL_C2_APB1_GRP1_IsEnabledClockSleep\n + * C2APB1SMENR1 LPTIM1SMEN LL_C2_APB1_GRP1_IsEnabledClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_C2_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_C2_APB1_GRP1_PERIPH_RTCAPB + * @arg @ref LL_C2_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_C2_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_C2_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_C2_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_C2_APB1_GRP1_PERIPH_I2C3 + * @arg @ref LL_C2_APB1_GRP1_PERIPH_DAC + * @arg @ref LL_C2_APB1_GRP1_PERIPH_LPTIM1 + * @retval None + */ +__STATIC_INLINE uint32_t LL_C2_APB1_GRP1_IsEnabledClockSleep(uint32_t Periphs) +{ + return ((READ_BIT(RCC->C2APB1SMENR1, Periphs) == (Periphs)) ? 1UL : 0UL); +} + +/** + * @brief Check if C2APB1 peripheral clock is enabled by the clock gating during CPU1 CSleep mode. + * @rmtoll C2APB1SMENR2 LPUART1SMEN LL_C2_APB1_GRP2_IsEnabledClockSleep\n + * C2APB1SMENR2 LPTIM2SMEN LL_C2_APB1_GRP2_IsEnabledClockSleep\n + * C2APB1SMENR2 LPTIM3SMEN LL_C2_APB1_GRP2_IsEnabledClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_C2_APB1_GRP2_PERIPH_LPUART1 + * @arg @ref LL_C2_APB1_GRP2_PERIPH_LPTIM2 + * @arg @ref LL_C2_APB1_GRP2_PERIPH_LPTIM3 + * @retval None + */ +__STATIC_INLINE uint32_t LL_C2_APB1_GRP2_IsEnabledClockSleep(uint32_t Periphs) +{ + return ((READ_BIT(RCC->C2APB1SMENR2, Periphs) == (Periphs)) ? 1UL : 0UL); +} + +/** + * @brief Disable C2APB1 peripherals clock during Low Power (Sleep) mode. + * @rmtoll C2APB1SMENR1 TIM2SMEN LL_C2_APB1_GRP1_DisableClockSleep\n + * C2APB1SMENR1 RTCAPBSMEN LL_C2_APB1_GRP1_DisableClockSleep\n + * C2APB1SMENR1 SPI2SMEN LL_C2_APB1_GRP1_DisableClockSleep\n + * C2APB1SMENR1 USART2SMEN LL_C2_APB1_GRP1_DisableClockSleep\n + * C2APB1SMENR1 I2C1SMEN LL_C2_APB1_GRP1_DisableClockSleep\n + * C2APB1SMENR1 I2C2SMEN LL_C2_APB1_GRP1_DisableClockSleep\n + * C2APB1SMENR1 I2C3SMEN LL_C2_APB1_GRP1_DisableClockSleep\n + * C2APB1SMENR1 DACSMEN LL_C2_APB1_GRP1_DisableClockSleep\n + * C2APB1SMENR1 LPTIM1SMEN LL_C2_APB1_GRP1_DisableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_C2_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_C2_APB1_GRP1_PERIPH_RTCAPB + * @arg @ref LL_C2_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_C2_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_C2_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_C2_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_C2_APB1_GRP1_PERIPH_I2C3 + * @arg @ref LL_C2_APB1_GRP1_PERIPH_DAC + * @arg @ref LL_C2_APB1_GRP1_PERIPH_LPTIM1 + + * @retval None + */ +__STATIC_INLINE void LL_C2_APB1_GRP1_DisableClockSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC->C2APB1SMENR1, Periphs); +} + +/** + * @brief Disable C2APB1 peripherals clock during Low Power (Sleep) mode. + * @rmtoll C2APB1SMENR2 LPUART1SMEN LL_C2_APB1_GRP2_DisableClockSleep\n + * C2APB1SMENR2 LPTIM2SMEN LL_C2_APB1_GRP2_DisableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_C2_APB1_GRP2_PERIPH_LPUART1 + * @arg @ref LL_C2_APB1_GRP2_PERIPH_LPTIM2 + * @retval None + */ +__STATIC_INLINE void LL_C2_APB1_GRP2_DisableClockSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC->C2APB1SMENR2, Periphs); +} + +/** + * @} + */ + +/** @defgroup BUS_LL_EF_C2_APB2 C2 APB2 + * @{ + */ + +/** + * @brief Enable C2APB2 peripherals clock. + * @rmtoll C2APB2ENR ADCEN LL_C2_APB2_GRP1_EnableClock\n + * C2APB2ENR TIM1EN LL_C2_APB2_GRP1_EnableClock\n + * C2APB2ENR SPI1EN LL_C2_APB2_GRP1_EnableClock\n + * C2APB2ENR USART1EN LL_C2_APB2_GRP1_EnableClock\n + * C2APB2ENR TIM16EN LL_C2_APB2_GRP1_EnableClock\n + * C2APB2ENR TIM17EN LL_C2_APB2_GRP1_EnableClock\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_C2_APB2_GRP1_PERIPH_ADC + * @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_C2_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_C2_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM16 + * @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM17 + * @retval None + */ +__STATIC_INLINE void LL_C2_APB2_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->C2APB2ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->C2APB2ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if C2APB2 peripheral clock is enabled or not + * @rmtoll C2APB2ENR ADCEN LL_C2_APB2_GRP1_IsEnabledClock\n + * C2APB2ENR TIM1EN LL_C2_APB2_GRP1_IsEnabledClock\n + * C2APB2ENR SPI1EN LL_C2_APB2_GRP1_IsEnabledClock\n + * C2APB2ENR USART1EN LL_C2_APB2_GRP1_IsEnabledClock\n + * C2APB2ENR TIM16EN LL_C2_APB2_GRP1_IsEnabledClock\n + * C2APB2ENR TIM17EN LL_C2_APB2_GRP1_IsEnabledClock\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_C2_APB2_GRP1_PERIPH_ADC + * @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_C2_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_C2_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM16 + * @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM17 + * @retval uint32_t + */ +__STATIC_INLINE uint32_t LL_C2_APB2_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC->C2APB2ENR, Periphs) == (Periphs)) ? 1UL : 0UL); +} + +/** + * @brief Disable C2APB2 peripherals clock. + * @rmtoll C2APB2ENR ADCEN LL_C2_APB2_GRP1_DisableClock\n + * C2APB2ENR TIM1EN LL_C2_APB2_GRP1_DisableClock\n + * C2APB2ENR SPI1EN LL_C2_APB2_GRP1_DisableClock\n + * C2APB2ENR USART1EN LL_C2_APB2_GRP1_DisableClock\n + * C2APB2ENR TIM16EN LL_C2_APB2_GRP1_DisableClock\n + * C2APB2ENR TIM17EN LL_C2_APB2_GRP1_DisableClock\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_C2_APB2_GRP1_PERIPH_ADC + * @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_C2_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_C2_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM16 + * @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM17 + * @retval None + */ +__STATIC_INLINE void LL_C2_APB2_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->C2APB2ENR, Periphs); +} + +/** + * @brief Enable C2APB2 peripherals clock during Low Power (Sleep) mode. + * @rmtoll C2APB2SMENR ADCSMEN LL_C2_APB2_GRP1_EnableClockSleep\n + * C2APB2SMENR TIM1SMEN LL_C2_APB2_GRP1_EnableClockSleep\n + * C2APB2SMENR SPI1SMEN LL_C2_APB2_GRP1_EnableClockSleep\n + * C2APB2SMENR USART1SMEN LL_C2_APB2_GRP1_EnableClockSleep\n + * C2APB2SMENR TIM16SMEN LL_C2_APB2_GRP1_EnableClockSleep\n + * C2APB2SMENR TIM17SMEN LL_C2_APB2_GRP1_EnableClockSleep\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_C2_APB2_GRP1_PERIPH_ADC + * @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_C2_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_C2_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM16 + * @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM17 + * @retval None + */ +__STATIC_INLINE void LL_C2_APB2_GRP1_EnableClockSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->C2APB2SMENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->C2APB2SMENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if C2APB2 peripheral clock is enabled by the clock gating during CPU1 CSleep mode. + * @rmtoll C2APB2SMENR ADCSMEN LL_C2_APB2_GRP1_IsEnabledClockSleep\n + * C2APB2SMENR TIM1SMEN LL_C2_APB2_GRP1_IsEnabledClockSleep\n + * C2APB2SMENR SPI1SMEN LL_C2_APB2_GRP1_IsEnabledClockSleep\n + * C2APB2SMENR USART1SMEN LL_C2_APB2_GRP1_IsEnabledClockSleep\n + * C2APB2SMENR TIM16SMEN LL_C2_APB2_GRP1_IsEnabledClockSleep\n + * C2APB2SMENR TIM17SMEN LL_C2_APB2_GRP1_IsEnabledClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_C2_APB2_GRP1_PERIPH_ADC + * @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_C2_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_C2_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM16 + * @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM17 + * @retval None + */ +__STATIC_INLINE uint32_t LL_C2_APB2_GRP1_IsEnabledClockSleep(uint32_t Periphs) +{ + return ((READ_BIT(RCC->C2APB2SMENR, Periphs) == (Periphs)) ? 1UL : 0UL); +} + +/** + * @brief Disable C2APB2 peripherals clock during Low Power (Sleep) mode. + * @rmtoll C2APB2SMENR ADCSMEN LL_C2_APB2_GRP1_DisableClockSleep\n + * C2APB2SMENR TIM1SMEN LL_C2_APB2_GRP1_DisableClockSleep\n + * C2APB2SMENR SPI1SMEN LL_C2_APB2_GRP1_DisableClockSleep\n + * C2APB2SMENR USART1SMEN LL_C2_APB2_GRP1_DisableClockSleep\n + * C2APB2SMENR TIM16SMEN LL_C2_APB2_GRP1_DisableClockSleep\n + * C2APB2SMENR TIM17SMEN LL_C2_APB2_GRP1_DisableClockSleep\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_C2_APB2_GRP1_PERIPH_ADC + * @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_C2_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_C2_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM16 + * @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM17 + * @retval None + */ +__STATIC_INLINE void LL_C2_APB2_GRP1_DisableClockSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC->C2APB2SMENR, Periphs); +} + +/** + * @} + */ + +/** @defgroup BUS_LL_EF_C2_APB3 C2 APB3 + * @{ + */ + +/** + * @brief Enable C2APB3 peripherals clock. + * @rmtoll C2APB3ENR SUBGHZSPIEN LL_C2_APB3_GRP1_EnableClock\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_C2_APB3_GRP1_PERIPH_SUBGHZSPI + * @retval None + */ +__STATIC_INLINE void LL_C2_APB3_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->C2APB3ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->C2APB3ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if C2APB3 peripheral clock is enabled or not + * @rmtoll C2APB3ENR SUBGHZSPIEN LL_C2_APB3_GRP1_IsEnabledClock\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_C2_APB3_GRP1_PERIPH_SUBGHZSPI + * @retval uint32_t + */ +__STATIC_INLINE uint32_t LL_C2_APB3_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC->C2APB3ENR, Periphs) == (Periphs)) ? 1UL : 0UL); +} + +/** + * @brief Disable C2APB3 peripherals clock. + * @rmtoll C2APB3ENR SUBGHZSPIEN LL_C2_APB3_GRP1_DisableClock\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_C2_APB3_GRP1_PERIPH_SUBGHZSPI + * @retval None + */ +__STATIC_INLINE void LL_C2_APB3_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->C2APB3ENR, Periphs); +} + +/** + * @brief Enable C2APB3 peripherals clock during Low Power (Sleep) mode. + * @rmtoll C2APB3SMENR SUBGHZSPISMEN LL_C2_APB3_GRP1_EnableClockSleep\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_C2_APB3_GRP1_PERIPH_SUBGHZSPI + * @retval None + */ +__STATIC_INLINE void LL_C2_APB3_GRP1_EnableClockSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->C2APB3SMENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->C2APB3SMENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if C2APB3 peripheral clock is enabled by the clock gating during CPU1 CSleep mode. + * @rmtoll C2APB3SMENR SUBGHZSPISMEN LL_C2_APB3_GRP1_IsEnabledClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_C2_APB3_GRP1_PERIPH_SUBGHZSPI + * @retval None + */ +__STATIC_INLINE uint32_t LL_C2_APB3_GRP1_IsEnabledClockSleep(uint32_t Periphs) +{ + return ((READ_BIT(RCC->C2APB3SMENR, Periphs) == (Periphs)) ? 1UL : 0UL); +} + +/** + * @brief Disable C2APB3 peripherals clock during Low Power (Sleep) mode. + * @rmtoll C2APB3SMENR SUBGHZSPISMEN LL_C2_APB3_GRP1_DisableClockSleep\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_C2_APB3_GRP1_PERIPH_SUBGHZSPI + * @retval None + */ +__STATIC_INLINE void LL_C2_APB3_GRP1_DisableClockSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC->C2APB3SMENR, Periphs); +} + +/** + * @} + */ +#endif /* DUAL_CORE */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(RCC) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32WLxx_LL_BUS_H */ diff --git a/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_cortex.h b/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_cortex.h new file mode 100644 index 0000000..c4d8395 --- /dev/null +++ b/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_cortex.h @@ -0,0 +1,652 @@ +/** + ****************************************************************************** + * @file stm32wlxx_ll_cortex.h + * @author MCD Application Team + * @brief Header file of CORTEX LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The LL CORTEX driver contains a set of generic APIs that can be + used by user: + (+) SYSTICK configuration used by @ref LL_mDelay and @ref LL_Init1msTick + functions + (+) Low power mode configuration (SCB register of Cortex-MCU) + (+) MPU API to configure and enable regions + (+) API to access to MCU info (CPUID register) + (+) API to enable fault handler (SHCSR accesses) + + @endverbatim + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32WLxx_LL_CORTEX_H +#define __STM32WLxx_LL_CORTEX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wlxx.h" + +/** @addtogroup STM32WLxx_LL_Driver + * @{ + */ + +/** @defgroup CORTEX_LL CORTEX + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ + +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants + * @{ + */ + +/** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source + * @{ + */ +#define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U /*!< AHB clock divided by 8 selected as SysTick clock source.*/ +#define LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk /*!< AHB clock selected as SysTick clock source. */ +/** + * @} + */ + +#if !defined(CORE_CM0PLUS) +/** @defgroup CORTEX_LL_EC_FAULT Handler Fault type + * @{ + */ +#define LL_HANDLER_FAULT_USG SCB_SHCSR_USGFAULTENA_Msk /*!< Usage fault */ +#define LL_HANDLER_FAULT_BUS SCB_SHCSR_BUSFAULTENA_Msk /*!< Bus fault */ +#define LL_HANDLER_FAULT_MEM SCB_SHCSR_MEMFAULTENA_Msk /*!< Memory management fault */ +/** + * @} + */ +#endif /* CORE_CM0PLUS */ + +#if __MPU_PRESENT +/** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF MPU Control + * @{ + */ +#define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0x00000000U /*!< Disable NMI and privileged SW access */ +#define LL_MPU_CTRL_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk /*!< Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers */ +#define LL_MPU_CTRL_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk /*!< Enable privileged software access to default memory map */ +#define LL_MPU_CTRL_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI and privileged SW access */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_REGION MPU Region Number + * @{ + */ +#define LL_MPU_REGION_NUMBER0 0x00U /*!< REGION Number 0 */ +#define LL_MPU_REGION_NUMBER1 0x01U /*!< REGION Number 1 */ +#define LL_MPU_REGION_NUMBER2 0x02U /*!< REGION Number 2 */ +#define LL_MPU_REGION_NUMBER3 0x03U /*!< REGION Number 3 */ +#define LL_MPU_REGION_NUMBER4 0x04U /*!< REGION Number 4 */ +#define LL_MPU_REGION_NUMBER5 0x05U /*!< REGION Number 5 */ +#define LL_MPU_REGION_NUMBER6 0x06U /*!< REGION Number 6 */ +#define LL_MPU_REGION_NUMBER7 0x07U /*!< REGION Number 7 */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_REGION_SIZE MPU Region Size + * @{ + */ +#if defined(CORE_CM0PLUS) +#else +#define LL_MPU_REGION_SIZE_32B (0x04U << MPU_RASR_SIZE_Pos) /*!< 32B Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_64B (0x05U << MPU_RASR_SIZE_Pos) /*!< 64B Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_128B (0x06U << MPU_RASR_SIZE_Pos) /*!< 128B Size of the MPU protection region */ +#endif /* CORE_CM0PLUS */ +#define LL_MPU_REGION_SIZE_256B (0x07U << MPU_RASR_SIZE_Pos) /*!< 256B Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_512B (0x08U << MPU_RASR_SIZE_Pos) /*!< 512B Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_1KB (0x09U << MPU_RASR_SIZE_Pos) /*!< 1KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_2KB (0x0AU << MPU_RASR_SIZE_Pos) /*!< 2KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_4KB (0x0BU << MPU_RASR_SIZE_Pos) /*!< 4KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_8KB (0x0CU << MPU_RASR_SIZE_Pos) /*!< 8KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_16KB (0x0DU << MPU_RASR_SIZE_Pos) /*!< 16KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_32KB (0x0EU << MPU_RASR_SIZE_Pos) /*!< 32KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_64KB (0x0FU << MPU_RASR_SIZE_Pos) /*!< 64KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_128KB (0x10U << MPU_RASR_SIZE_Pos) /*!< 128KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_256KB (0x11U << MPU_RASR_SIZE_Pos) /*!< 256KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_512KB (0x12U << MPU_RASR_SIZE_Pos) /*!< 512KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_1MB (0x13U << MPU_RASR_SIZE_Pos) /*!< 1MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_2MB (0x14U << MPU_RASR_SIZE_Pos) /*!< 2MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_4MB (0x15U << MPU_RASR_SIZE_Pos) /*!< 4MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_8MB (0x16U << MPU_RASR_SIZE_Pos) /*!< 8MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_16MB (0x17U << MPU_RASR_SIZE_Pos) /*!< 16MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_32MB (0x18U << MPU_RASR_SIZE_Pos) /*!< 32MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_64MB (0x19U << MPU_RASR_SIZE_Pos) /*!< 64MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_128MB (0x1AU << MPU_RASR_SIZE_Pos) /*!< 128MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_256MB (0x1BU << MPU_RASR_SIZE_Pos) /*!< 256MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_512MB (0x1CU << MPU_RASR_SIZE_Pos) /*!< 512MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_1GB (0x1DU << MPU_RASR_SIZE_Pos) /*!< 1GB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_2GB (0x1EU << MPU_RASR_SIZE_Pos) /*!< 2GB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_4GB (0x1FU << MPU_RASR_SIZE_Pos) /*!< 4GB Size of the MPU protection region */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_REGION_PRIVILEDGES MPU Region Privileges + * @{ + */ +#define LL_MPU_REGION_NO_ACCESS (0x00U << MPU_RASR_AP_Pos) /*!< No access*/ +#define LL_MPU_REGION_PRIV_RW (0x01U << MPU_RASR_AP_Pos) /*!< RW privileged (privileged access only)*/ +#define LL_MPU_REGION_PRIV_RW_URO (0x02U << MPU_RASR_AP_Pos) /*!< RW privileged - RO user (Write in a user program generates a fault) */ +#define LL_MPU_REGION_FULL_ACCESS (0x03U << MPU_RASR_AP_Pos) /*!< RW privileged & user (Full access) */ +#define LL_MPU_REGION_PRIV_RO (0x05U << MPU_RASR_AP_Pos) /*!< RO privileged (privileged read only)*/ +#define LL_MPU_REGION_PRIV_RO_URO (0x06U << MPU_RASR_AP_Pos) /*!< RO privileged & user (read only) */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_TEX MPU TEX Level + * @{ + */ +#if defined(CORE_CM0PLUS) +#else +#define LL_MPU_TEX_LEVEL0 (0x00U << MPU_RASR_TEX_Pos) /*!< b000 for TEX bits */ +#define LL_MPU_TEX_LEVEL1 (0x01U << MPU_RASR_TEX_Pos) /*!< b001 for TEX bits */ +#define LL_MPU_TEX_LEVEL2 (0x02U << MPU_RASR_TEX_Pos) /*!< b010 for TEX bits */ +#endif /* CORE_CM0PLUS */ + +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_INSTRUCTION_ACCESS MPU Instruction Access + * @{ + */ +#define LL_MPU_INSTRUCTION_ACCESS_ENABLE 0x00U /*!< Instruction fetches enabled */ +#define LL_MPU_INSTRUCTION_ACCESS_DISABLE MPU_RASR_XN_Msk /*!< Instruction fetches disabled*/ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_SHAREABLE_ACCESS MPU Shareable Access + * @{ + */ +#define LL_MPU_ACCESS_SHAREABLE MPU_RASR_S_Msk /*!< Shareable memory attribute */ +#define LL_MPU_ACCESS_NOT_SHAREABLE 0x00U /*!< Not Shareable memory attribute */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_CACHEABLE_ACCESS MPU Cacheable Access + * @{ + */ +#define LL_MPU_ACCESS_CACHEABLE MPU_RASR_C_Msk /*!< Cacheable memory attribute */ +#define LL_MPU_ACCESS_NOT_CACHEABLE 0x00U /*!< Not Cacheable memory attribute */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_BUFFERABLE_ACCESS MPU Bufferable Access + * @{ + */ +#define LL_MPU_ACCESS_BUFFERABLE MPU_RASR_B_Msk /*!< Bufferable memory attribute */ +#define LL_MPU_ACCESS_NOT_BUFFERABLE 0x00U /*!< Not Bufferable memory attribute */ +/** + * @} + */ +#endif /* __MPU_PRESENT */ +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions + * @{ + */ + +/** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK + * @{ + */ + +/** + * @brief This function checks if the Systick counter flag is active or not. + * @note It can be used in timeout function on application side. + * @rmtoll STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void) +{ + return (((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk)) ? 1UL : 0UL); +} + +/** + * @brief Configures the SysTick clock source + * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8 + * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK + * @retval None + */ +__STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source) +{ + if (Source == LL_SYSTICK_CLKSOURCE_HCLK) + { + SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); + } + else + { + CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); + } +} + +/** + * @brief Get the SysTick clock source + * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8 + * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK + */ +__STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void) +{ + return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); +} + +/** + * @brief Enable SysTick exception request + * @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT + * @retval None + */ +__STATIC_INLINE void LL_SYSTICK_EnableIT(void) +{ + SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); +} + +/** + * @brief Disable SysTick exception request + * @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT + * @retval None + */ +__STATIC_INLINE void LL_SYSTICK_DisableIT(void) +{ + CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); +} + +/** + * @brief Checks if the SYSTICK interrupt is enabled or disabled. + * @rmtoll STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void) +{ + return ((READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE + * @{ + */ + +/** + * @brief Processor uses sleep as its low power mode + * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep + * @retval None + */ +__STATIC_INLINE void LL_LPM_EnableSleep(void) +{ + /* Clear SLEEPDEEP bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); +} + +/** + * @brief Processor uses deep sleep as its low power mode + * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep + * @retval None + */ +__STATIC_INLINE void LL_LPM_EnableDeepSleep(void) +{ + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); +} + +/** + * @brief Configures sleep-on-exit when returning from Handler mode to Thread mode. + * @note Setting this bit to 1 enables an interrupt-driven application to avoid returning to an + * empty main application. + * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit + * @retval None + */ +__STATIC_INLINE void LL_LPM_EnableSleepOnExit(void) +{ + /* Set SLEEPONEXIT bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); +} + +/** + * @brief Do not sleep when returning to Thread mode. + * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit + * @retval None + */ +__STATIC_INLINE void LL_LPM_DisableSleepOnExit(void) +{ + /* Clear SLEEPONEXIT bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); +} + +/** + * @brief Enabled events and all interrupts, including disabled interrupts, can wakeup the + * processor. + * @rmtoll SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend + * @retval None + */ +__STATIC_INLINE void LL_LPM_EnableEventOnPend(void) +{ + /* Set SEVEONPEND bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); +} + +/** + * @brief Only enabled interrupts or events can wakeup the processor, disabled interrupts are + * excluded + * @rmtoll SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend + * @retval None + */ +__STATIC_INLINE void LL_LPM_DisableEventOnPend(void) +{ + /* Clear SEVEONPEND bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); +} + +/** + * @} + */ + +#if !defined(CORE_CM0PLUS) +/** @defgroup CORTEX_LL_EF_HANDLER HANDLER + * @{ + */ + +/** + * @brief Enable a fault in System handler control register (SHCSR) + * @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_EnableFault + * @param Fault This parameter can be a combination of the following values: + * @arg @ref LL_HANDLER_FAULT_USG + * @arg @ref LL_HANDLER_FAULT_BUS + * @arg @ref LL_HANDLER_FAULT_MEM + * @retval None + */ +__STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault) +{ + /* Enable the system handler fault */ + SET_BIT(SCB->SHCSR, Fault); +} + +/** + * @brief Disable a fault in System handler control register (SHCSR) + * @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_DisableFault + * @param Fault This parameter can be a combination of the following values: + * @arg @ref LL_HANDLER_FAULT_USG + * @arg @ref LL_HANDLER_FAULT_BUS + * @arg @ref LL_HANDLER_FAULT_MEM + * @retval None + */ +__STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault) +{ + /* Disable the system handler fault */ + CLEAR_BIT(SCB->SHCSR, Fault); +} + +/** + * @} + */ + +#endif /* CORE_CM0PLUS */ +/** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO + * @{ + */ + +/** + * @brief Get Implementer code + * @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer + * @retval Value should be equal to 0x41 for ARM + */ +__STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void) +{ + return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos); +} + +/** + * @brief Get Variant number (The r value in the rnpn product revision identifier) + * @rmtoll SCB_CPUID VARIANT LL_CPUID_GetVariant + * @retval Value between 0 and 255 (0x0: revision 0) + */ +__STATIC_INLINE uint32_t LL_CPUID_GetVariant(void) +{ + return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos); +} + +/** + * @brief Get Architecture number + * @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetArchitecture + * @retval Value should be equal to 0xF for Cortex-M4 devices + */ +__STATIC_INLINE uint32_t LL_CPUID_GetArchitecture(void) +{ + return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos); +} + +/** + * @brief Get Part number + * @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo + * @retval Value should be equal to 0xC24 for Cortex-M4 + */ +__STATIC_INLINE uint32_t LL_CPUID_GetParNo(void) +{ + return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos); +} + +/** + * @brief Get Revision number (The p value in the rnpn product revision identifier, indicates patch release) + * @rmtoll SCB_CPUID REVISION LL_CPUID_GetRevision + * @retval Value between 0 and 255 (0x1: patch 1) + */ +__STATIC_INLINE uint32_t LL_CPUID_GetRevision(void) +{ + return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos); +} + +/** + * @} + */ + +#if __MPU_PRESENT +/** @defgroup CORTEX_LL_EF_MPU MPU + * @{ + */ + +/** + * @brief Enable MPU with input options + * @rmtoll MPU_CTRL ENABLE LL_MPU_Enable + * @param Options This parameter can be one of the following values: + * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE + * @arg @ref LL_MPU_CTRL_HARDFAULT_NMI + * @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT + * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF + * @retval None + */ +__STATIC_INLINE void LL_MPU_Enable(uint32_t Options) +{ + /* Enable the MPU*/ + WRITE_REG(MPU->CTRL, (MPU_CTRL_ENABLE_Msk | Options)); + /* Ensure MPU settings take effects */ + __DSB(); + /* Sequence instruction fetches using update settings */ + __ISB(); +} + +/** + * @brief Disable MPU + * @rmtoll MPU_CTRL ENABLE LL_MPU_Disable + * @retval None + */ +__STATIC_INLINE void LL_MPU_Disable(void) +{ + /* Make sure outstanding transfers are done */ + __DMB(); + /* Disable MPU*/ + WRITE_REG(MPU->CTRL, 0U); +} + +/** + * @brief Check if MPU is enabled or not + * @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_MPU_IsEnabled(void) +{ + return ((READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk)) ? 1UL : 0UL); +} + +/** + * @brief Enable a MPU region + * @rmtoll MPU_RASR ENABLE LL_MPU_EnableRegion + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @retval None + */ +__STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region) +{ + /* Set Region number */ + WRITE_REG(MPU->RNR, Region); + /* Enable the MPU region */ + SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); +} + +/** + * @brief Configure and enable a region + * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion\n + * MPU_RBAR REGION LL_MPU_ConfigRegion\n + * MPU_RBAR ADDR LL_MPU_ConfigRegion\n + * MPU_RASR XN LL_MPU_ConfigRegion\n + * MPU_RASR AP LL_MPU_ConfigRegion\n + * MPU_RASR S LL_MPU_ConfigRegion\n + * MPU_RASR C LL_MPU_ConfigRegion\n + * MPU_RASR B LL_MPU_ConfigRegion\n + * MPU_RASR SIZE LL_MPU_ConfigRegion + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @param Address Value of region base address + * @param SubRegionDisable Sub-region disable value between Min_Data = 0x00 and Max_Data = 0xFF + * @param Attributes This parameter can be a combination of the following values: + * @arg @ref LL_MPU_REGION_SIZE_32B (*) or @ref LL_MPU_REGION_SIZE_64B (*) or @ref LL_MPU_REGION_SIZE_128B (*) + * or @ref LL_MPU_REGION_SIZE_256B or @ref LL_MPU_REGION_SIZE_512B or @ref LL_MPU_REGION_SIZE_1KB + * or @ref LL_MPU_REGION_SIZE_2KB or @ref LL_MPU_REGION_SIZE_4KB or @ref LL_MPU_REGION_SIZE_8KB + * or @ref LL_MPU_REGION_SIZE_16KB or @ref LL_MPU_REGION_SIZE_32KB or @ref LL_MPU_REGION_SIZE_64KB + * or @ref LL_MPU_REGION_SIZE_128KB or @ref LL_MPU_REGION_SIZE_256KB or @ref LL_MPU_REGION_SIZE_512KB + * or @ref LL_MPU_REGION_SIZE_1MB or @ref LL_MPU_REGION_SIZE_2MB or @ref LL_MPU_REGION_SIZE_4MB + * or @ref LL_MPU_REGION_SIZE_8MB or @ref LL_MPU_REGION_SIZE_16MB or @ref LL_MPU_REGION_SIZE_32MB + * or @ref LL_MPU_REGION_SIZE_64MB or @ref LL_MPU_REGION_SIZE_128MB or @ref LL_MPU_REGION_SIZE_256MB + * or @ref LL_MPU_REGION_SIZE_512MB or @ref LL_MPU_REGION_SIZE_1GB or @ref LL_MPU_REGION_SIZE_2GB + * or @ref LL_MPU_REGION_SIZE_4GB + * @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO + * or @ref LL_MPU_REGION_FULL_ACCESS or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO + * @arg @ref LL_MPU_TEX_LEVEL0 (*) or @ref LL_MPU_TEX_LEVEL1 (*) or @ref LL_MPU_TEX_LEVEL2 (*) + * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE + * @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE + * @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE + * @arg @ref LL_MPU_ACCESS_BUFFERABLE or @ref LL_MPU_ACCESS_NOT_BUFFERABLE + * (*) value not defined for CM0+ core. + * @retval None + */ +__STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, + uint32_t Attributes) +{ + /* Set Region number */ + WRITE_REG(MPU->RNR, Region); + /* Set base address */ + WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U)); + /* Configure MPU */ + WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | (SubRegionDisable << MPU_RASR_SRD_Pos))); +} + +/** + * @brief Disable a region + * @rmtoll MPU_RNR REGION LL_MPU_DisableRegion\n + * MPU_RASR ENABLE LL_MPU_DisableRegion + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @retval None + */ +__STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region) +{ + /* Set Region number */ + WRITE_REG(MPU->RNR, Region); + /* Disable the MPU region */ + CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); +} + +/** + * @} + */ + +#endif /* __MPU_PRESENT */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32WLxx_LL_CORTEX_H */ diff --git a/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h b/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h new file mode 100644 index 0000000..ffaeb94 --- /dev/null +++ b/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h @@ -0,0 +1,2489 @@ +/** + ****************************************************************************** + * @file stm32wlxx_ll_dma.h + * @author MCD Application Team + * @brief Header file of DMA LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32WLxx_LL_DMA_H +#define STM32WLxx_LL_DMA_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wlxx.h" +#include "stm32wlxx_ll_dmamux.h" + +/** @addtogroup STM32WLxx_LL_Driver + * @{ + */ + +#if defined (DMA1) || defined (DMA2) + +/** @defgroup DMA_LL DMA + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @defgroup DMA_LL_Private_Variables DMA Private Variables + * @{ + */ +/* Array used to get the DMA channel register offset versus channel index LL_DMA_CHANNEL_x */ +static const uint8_t CHANNEL_OFFSET_TAB[] = +{ + (uint8_t)(DMA1_Channel1_BASE - DMA1_BASE), + (uint8_t)(DMA1_Channel2_BASE - DMA1_BASE), + (uint8_t)(DMA1_Channel3_BASE - DMA1_BASE), + (uint8_t)(DMA1_Channel4_BASE - DMA1_BASE), + (uint8_t)(DMA1_Channel5_BASE - DMA1_BASE), + (uint8_t)(DMA1_Channel6_BASE - DMA1_BASE), + (uint8_t)(DMA1_Channel7_BASE - DMA1_BASE), +}; +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ + +/** @defgroup DMA_LL_Private_Macros DMA Private Macros + * @{ + */ +/** + * @brief Helper macro to convert DMA Instance DMAx into DMAMUX channel + * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. + * DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7. + * @param __DMA_INSTANCE__ DMAx + * @retval Channel_Offset (LL_DMA_CHANNEL_7 or 0). + */ +#define __LL_DMA_INSTANCE_TO_DMAMUX_CHANNEL(__DMA_INSTANCE__) \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) ? 0 : LL_DMA_CHANNEL_7) +/** + * @} + */ +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup DMA_LL_ES_INIT DMA Exported Init structure + * @{ + */ +typedef struct +{ + uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer + or as Source base address in case of memory to memory transfer direction. + + This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */ + + uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer + or as Destination base address in case of memory to memory transfer direction. + + This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */ + + uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, + from memory to memory or from peripheral to memory. + This parameter can be a value of @ref DMA_LL_EC_DIRECTION + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */ + + uint32_t Mode; /*!< Specifies the normal or circular operation mode. + This parameter can be a value of @ref DMA_LL_EC_MODE + @note: The circular buffer mode cannot be used if the memory to memory + data transfer direction is configured on the selected Channel + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */ + + uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction + is incremented or not. + This parameter can be a value of @ref DMA_LL_EC_PERIPH + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */ + + uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction + is incremented or not. + This parameter can be a value of @ref DMA_LL_EC_MEMORY + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */ + + uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word) + in case of memory to memory transfer direction. + This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */ + + uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word) + in case of memory to memory transfer direction. + This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */ + + uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit. + The data unit is equal to the source buffer configuration set in PeripheralSize + or MemorySize parameters depending in the transfer direction. + This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */ + + uint32_t PeriphRequest; /*!< Specifies the peripheral request. + This parameter can be a value of @ref DMAMUX_LL_EC_REQUEST + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphRequest(). */ + + uint32_t Priority; /*!< Specifies the channel priority level. + This parameter can be a value of @ref DMA_LL_EC_PRIORITY + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetChannelPriorityLevel(). */ + +} LL_DMA_InitTypeDef; +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup DMA_LL_Exported_Constants DMA Exported Constants + * @{ + */ +/** @defgroup DMA_LL_EC_CLEAR_FLAG Clear Flags Defines + * @brief Flags defines which can be used with LL_DMA_WriteReg function + * @{ + */ +#define LL_DMA_IFCR_CGIF1 DMA_IFCR_CGIF1 /*!< Channel 1 global flag */ +#define LL_DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1 /*!< Channel 1 transfer complete flag */ +#define LL_DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1 /*!< Channel 1 half transfer flag */ +#define LL_DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1 /*!< Channel 1 transfer error flag */ +#define LL_DMA_IFCR_CGIF2 DMA_IFCR_CGIF2 /*!< Channel 2 global flag */ +#define LL_DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2 /*!< Channel 2 transfer complete flag */ +#define LL_DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2 /*!< Channel 2 half transfer flag */ +#define LL_DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2 /*!< Channel 2 transfer error flag */ +#define LL_DMA_IFCR_CGIF3 DMA_IFCR_CGIF3 /*!< Channel 3 global flag */ +#define LL_DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3 /*!< Channel 3 transfer complete flag */ +#define LL_DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3 /*!< Channel 3 half transfer flag */ +#define LL_DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3 /*!< Channel 3 transfer error flag */ +#define LL_DMA_IFCR_CGIF4 DMA_IFCR_CGIF4 /*!< Channel 4 global flag */ +#define LL_DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4 /*!< Channel 4 transfer complete flag */ +#define LL_DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4 /*!< Channel 4 half transfer flag */ +#define LL_DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4 /*!< Channel 4 transfer error flag */ +#define LL_DMA_IFCR_CGIF5 DMA_IFCR_CGIF5 /*!< Channel 5 global flag */ +#define LL_DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5 /*!< Channel 5 transfer complete flag */ +#define LL_DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5 /*!< Channel 5 half transfer flag */ +#define LL_DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5 /*!< Channel 5 transfer error flag */ +#define LL_DMA_IFCR_CGIF6 DMA_IFCR_CGIF6 /*!< Channel 6 global flag */ +#define LL_DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6 /*!< Channel 6 transfer complete flag */ +#define LL_DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6 /*!< Channel 6 half transfer flag */ +#define LL_DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6 /*!< Channel 6 transfer error flag */ +#define LL_DMA_IFCR_CGIF7 DMA_IFCR_CGIF7 /*!< Channel 7 global flag */ +#define LL_DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7 /*!< Channel 7 transfer complete flag */ +#define LL_DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7 /*!< Channel 7 half transfer flag */ +#define LL_DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7 /*!< Channel 7 transfer error flag */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_DMA_ReadReg function + * @{ + */ +#define LL_DMA_ISR_GIF1 DMA_ISR_GIF1 /*!< Channel 1 global flag */ +#define LL_DMA_ISR_TCIF1 DMA_ISR_TCIF1 /*!< Channel 1 transfer complete flag */ +#define LL_DMA_ISR_HTIF1 DMA_ISR_HTIF1 /*!< Channel 1 half transfer flag */ +#define LL_DMA_ISR_TEIF1 DMA_ISR_TEIF1 /*!< Channel 1 transfer error flag */ +#define LL_DMA_ISR_GIF2 DMA_ISR_GIF2 /*!< Channel 2 global flag */ +#define LL_DMA_ISR_TCIF2 DMA_ISR_TCIF2 /*!< Channel 2 transfer complete flag */ +#define LL_DMA_ISR_HTIF2 DMA_ISR_HTIF2 /*!< Channel 2 half transfer flag */ +#define LL_DMA_ISR_TEIF2 DMA_ISR_TEIF2 /*!< Channel 2 transfer error flag */ +#define LL_DMA_ISR_GIF3 DMA_ISR_GIF3 /*!< Channel 3 global flag */ +#define LL_DMA_ISR_TCIF3 DMA_ISR_TCIF3 /*!< Channel 3 transfer complete flag */ +#define LL_DMA_ISR_HTIF3 DMA_ISR_HTIF3 /*!< Channel 3 half transfer flag */ +#define LL_DMA_ISR_TEIF3 DMA_ISR_TEIF3 /*!< Channel 3 transfer error flag */ +#define LL_DMA_ISR_GIF4 DMA_ISR_GIF4 /*!< Channel 4 global flag */ +#define LL_DMA_ISR_TCIF4 DMA_ISR_TCIF4 /*!< Channel 4 transfer complete flag */ +#define LL_DMA_ISR_HTIF4 DMA_ISR_HTIF4 /*!< Channel 4 half transfer flag */ +#define LL_DMA_ISR_TEIF4 DMA_ISR_TEIF4 /*!< Channel 4 transfer error flag */ +#define LL_DMA_ISR_GIF5 DMA_ISR_GIF5 /*!< Channel 5 global flag */ +#define LL_DMA_ISR_TCIF5 DMA_ISR_TCIF5 /*!< Channel 5 transfer complete flag */ +#define LL_DMA_ISR_HTIF5 DMA_ISR_HTIF5 /*!< Channel 5 half transfer flag */ +#define LL_DMA_ISR_TEIF5 DMA_ISR_TEIF5 /*!< Channel 5 transfer error flag */ +#define LL_DMA_ISR_GIF6 DMA_ISR_GIF6 /*!< Channel 6 global flag */ +#define LL_DMA_ISR_TCIF6 DMA_ISR_TCIF6 /*!< Channel 6 transfer complete flag */ +#define LL_DMA_ISR_HTIF6 DMA_ISR_HTIF6 /*!< Channel 6 half transfer flag */ +#define LL_DMA_ISR_TEIF6 DMA_ISR_TEIF6 /*!< Channel 6 transfer error flag */ +#define LL_DMA_ISR_GIF7 DMA_ISR_GIF7 /*!< Channel 7 global flag */ +#define LL_DMA_ISR_TCIF7 DMA_ISR_TCIF7 /*!< Channel 7 transfer complete flag */ +#define LL_DMA_ISR_HTIF7 DMA_ISR_HTIF7 /*!< Channel 7 half transfer flag */ +#define LL_DMA_ISR_TEIF7 DMA_ISR_TEIF7 /*!< Channel 7 transfer error flag */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_DMA_ReadReg and LL_DMA_WriteReg functions + * @{ + */ +#define LL_DMA_CCR_TCIE DMA_CCR_TCIE /*!< Transfer complete interrupt */ +#define LL_DMA_CCR_HTIE DMA_CCR_HTIE /*!< Half Transfer interrupt */ +#define LL_DMA_CCR_TEIE DMA_CCR_TEIE /*!< Transfer error interrupt */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_CHANNEL CHANNEL + * @{ + */ +#define LL_DMA_CHANNEL_1 0x00000000U /*!< DMA Channel 1 */ +#define LL_DMA_CHANNEL_2 0x00000001U /*!< DMA Channel 2 */ +#define LL_DMA_CHANNEL_3 0x00000002U /*!< DMA Channel 3 */ +#define LL_DMA_CHANNEL_4 0x00000003U /*!< DMA Channel 4 */ +#define LL_DMA_CHANNEL_5 0x00000004U /*!< DMA Channel 5 */ +#define LL_DMA_CHANNEL_6 0x00000005U /*!< DMA Channel 6 */ +#define LL_DMA_CHANNEL_7 0x00000006U /*!< DMA Channel 7 */ +#if defined(USE_FULL_LL_DRIVER) +#define LL_DMA_CHANNEL_ALL 0xFFFF0000U /*!< DMA Channel all (used only for function @ref LL_DMA_DeInit(). */ +#endif /*USE_FULL_LL_DRIVER*/ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_DIRECTION Transfer Direction + * @{ + */ +#define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */ +#define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CCR_DIR /*!< Memory to peripheral direction */ +#define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM /*!< Memory to memory direction */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_MODE Transfer mode + * @{ + */ +#define LL_DMA_MODE_NORMAL 0x00000000U /*!< Normal Mode */ +#define LL_DMA_MODE_CIRCULAR DMA_CCR_CIRC /*!< Circular Mode */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_PERIPH Peripheral increment mode + * @{ + */ +#define LL_DMA_PERIPH_INCREMENT DMA_CCR_PINC /*!< Peripheral increment mode Enable */ +#define LL_DMA_PERIPH_NOINCREMENT 0x00000000U /*!< Peripheral increment mode Disable */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_MEMORY Memory increment mode + * @{ + */ +#define LL_DMA_MEMORY_INCREMENT DMA_CCR_MINC /*!< Memory increment mode Enable */ +#define LL_DMA_MEMORY_NOINCREMENT 0x00000000U /*!< Memory increment mode Disable */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_PDATAALIGN Peripheral data alignment + * @{ + */ +#define LL_DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */ +#define LL_DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */ +#define LL_DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1 /*!< Peripheral data alignment : Word */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_MDATAALIGN Memory data alignment + * @{ + */ +#define LL_DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */ +#define LL_DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0 /*!< Memory data alignment : HalfWord */ +#define LL_DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1 /*!< Memory data alignment : Word */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_PRIORITY Transfer Priority level + * @{ + */ +#define LL_DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */ +#define LL_DMA_PRIORITY_MEDIUM DMA_CCR_PL_0 /*!< Priority level : Medium */ +#define LL_DMA_PRIORITY_HIGH DMA_CCR_PL_1 /*!< Priority level : High */ +#define LL_DMA_PRIORITY_VERYHIGH DMA_CCR_PL /*!< Priority level : Very_High */ +/** + * @} + */ + +#if defined(DMA_CCR_SECM) +/** @defgroup DMA_LL_CHANNEL_SEC_MODE CHANNEL SECURITY MODE + * @{ + */ +#define LL_DMA_CHANNEL_NSEC 0x00000000U /*!< Disable secure DMA channel */ +#define LL_DMA_CHANNEL_SEC DMA_CCR_SECM /*!< Enable secure DMA channel */ +/** + * @} + */ + +#if defined (CORE_CM0PLUS) +/** @defgroup DMA_LL_SOURCE_TRANSFER_SEC_MODE TRANSFER SECURITY SOURCE MODE + * @{ + */ +#define LL_DMA_CHANNEL_SRC_NSEC 0x00000000U /*!< Disable secure DMA transfer from the source */ +#define LL_DMA_CHANNEL_SRC_SEC DMA_CCR_SSEC /*!< Enable secure DMA transfer from the source */ +/** + * @} + */ + +/** @defgroup DMA_LL_DEST_TRANSFER_SEC_MODE TRANSFER SECURITY DESTINATION MODE + * @{ + */ +#define LL_DMA_CHANNEL_DEST_NSEC 0x00000000U /*!< Disable secure DMA transfer to the destination */ +#define LL_DMA_CHANNEL_DEST_SEC DMA_CCR_DSEC /*!< Enable secure DMA transfer to the destination */ +/** + * @} + */ +#endif /* CORE_CM0PLUS */ + +#endif /* DMA_CCR_SECM */ +#if defined(DMA_CCR_PRIV) +/** @defgroup DMA_LL_SEC_PRIVILEGE_MODE PRIVILEGE MODE + * @{ + */ +#define LL_DMA_CHANNEL_NPRIV 0x00000000U /*!< Disable privilege */ +#define LL_DMA_CHANNEL_PRIV DMA_CCR_PRIV /*!< Enable privilege */ +/** + * @} + */ + +#endif /* DMA_CCR_PRIV */ +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup DMA_LL_Exported_Macros DMA Exported Macros + * @{ + */ + +/** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros + * @{ + */ +/** + * @brief Write a value in DMA register + * @param __INSTANCE__ DMA Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in DMA register + * @param __INSTANCE__ DMA Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxChannely + * @{ + */ +/** + * @brief Convert DMAx_Channely into DMAx + * @param __CHANNEL_INSTANCE__ DMAx_Channely + * @retval DMAx + */ +#define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) \ + (((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)DMA1_Channel7)) ? DMA2 : DMA1) + +/** + * @brief Convert DMAx_Channely into LL_DMA_CHANNEL_y + * @param __CHANNEL_INSTANCE__ DMAx_Channely + * @retval LL_DMA_CHANNEL_y + */ +#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \ + (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel6)) ? LL_DMA_CHANNEL_6 : \ + LL_DMA_CHANNEL_7) + +/** + * @brief Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely + * @param __DMA_INSTANCE__ DMAx + * @param __CHANNEL__ LL_DMA_CHANNEL_y + * @retval DMAx_Channely + */ +#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \ + ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA2_Channel6 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_7))) ? DMA1_Channel7 : \ + DMA2_Channel7) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup DMA_LL_Exported_Functions DMA Exported Functions + * @{ + */ + +/** @defgroup DMA_LL_EF_Configuration Configuration + * @{ + */ +/** + * @brief Enable DMA channel. + * @rmtoll CCR EN LL_DMA_EnableChannel + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_EnableChannel(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_EN); +} + +/** + * @brief Disable DMA channel. + * @rmtoll CCR EN LL_DMA_DisableChannel + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_DisableChannel(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_EN); +} + +/** + * @brief Check if DMA channel is enabled or disabled. + * @rmtoll CCR EN LL_DMA_IsEnabledChannel + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, + DMA_CCR_EN) == (DMA_CCR_EN)) ? 1UL : 0UL); +} + +#if defined(DMA_CCR_SECM) +#if defined (CORE_CM0PLUS) +/** + * @brief Configure all secure parameters link to DMA transfer. + * @rmtoll CCR SECM LL_DMA_ConfigChannelSecure\n + * CCR SSEC LL_DMA_ConfigChannelSecure\n + * CCR DSEC LL_DMA_ConfigChannelSecure\n + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param Configuration This parameter must be a combination of all the following values: + * @arg @ref LL_DMA_CHANNEL_SEC or @ref LL_DMA_CHANNEL_NSEC + * @arg @ref LL_DMA_CHANNEL_SRC_SEC or @ref LL_DMA_CHANNEL_SRC_NSEC + * @arg @ref LL_DMA_CHANNEL_DEST_SEC or LL_DMA_CHANNEL_DEST_NSEC + * @retval None + */ +__STATIC_INLINE void LL_DMA_ConfigChannelSecure(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + (uint32_t)(CHANNEL_OFFSET_TAB[Channel])))->CCR, + DMA_CCR_SECM | DMA_CCR_SSEC | DMA_CCR_DSEC, + Configuration); +} + +/** + * @brief Get the configuration of a secure channel. + * @rmtoll CCR SECM LL_DMA_GetConfigChannelSecure\n + * CCR SSEC LL_DMA_GetConfigChannelSecure\n + * CCR DSEC LL_DMA_GetConfigChannelSecure\n + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Configuration This parameter must be a combination of all the following values: + * @arg @ref LL_DMA_CHANNEL_SEC or @ref LL_DMA_CHANNEL_NSEC + * @arg @ref LL_DMA_CHANNEL_SRC_SEC or @ref LL_DMA_CHANNEL_SRC_NSEC + * @arg @ref LL_DMA_CHANNEL_DEST_SEC or LL_DMA_CHANNEL_DEST_NSEC + */ +__STATIC_INLINE uint32_t LL_DMA_GetConfigChannelSecure(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, + DMA_CCR_SECM | DMA_CCR_SSEC | DMA_CCR_DSEC)); +} +#else +/** + * @brief Get the configuration of a secure channel. + * @rmtoll CCR SECM LL_DMA_GetConfigChannelSecure\n + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Configuration This parameter must be a combination of all the following values: + * @arg @ref LL_DMA_CHANNEL_SEC or @ref LL_DMA_CHANNEL_NSEC + */ +__STATIC_INLINE uint32_t LL_DMA_GetConfigChannelSecure(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, + DMA_CCR_SECM)); +} +#endif /* CORE_CM0PLUS */ + +#endif /* DMA_CCR_SECM */ +/** + * @brief Configure all parameters link to DMA transfer. + * @rmtoll CCR DIR LL_DMA_ConfigTransfer\n + * CCR MEM2MEM LL_DMA_ConfigTransfer\n + * CCR CIRC LL_DMA_ConfigTransfer\n + * CCR PINC LL_DMA_ConfigTransfer\n + * CCR MINC LL_DMA_ConfigTransfer\n + * CCR PSIZE LL_DMA_ConfigTransfer\n + * CCR MSIZE LL_DMA_ConfigTransfer\n + * CCR PL LL_DMA_ConfigTransfer + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param Configuration This parameter must be a combination of all the following values: + * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY + * @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR + * @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT + * @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT + * @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD + * @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD + * @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH + * @retval None + */ +__STATIC_INLINE void LL_DMA_ConfigTransfer(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, + DMA_CCR_DIR | DMA_CCR_MEM2MEM | DMA_CCR_CIRC | DMA_CCR_PINC | DMA_CCR_MINC | DMA_CCR_PSIZE | DMA_CCR_MSIZE | DMA_CCR_PL, + Configuration); +} + +/** + * @brief Set Data transfer direction (read from peripheral or from memory). + * @rmtoll CCR DIR LL_DMA_SetDataTransferDirection\n + * CCR MEM2MEM LL_DMA_SetDataTransferDirection + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param Direction This parameter can be one of the following values: + * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetDataTransferDirection(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, + DMA_CCR_DIR | DMA_CCR_MEM2MEM, Direction); +} + +/** + * @brief Get Data transfer direction (read from peripheral or from memory). + * @rmtoll CCR DIR LL_DMA_GetDataTransferDirection\n + * CCR MEM2MEM LL_DMA_GetDataTransferDirection + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY + */ +__STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, + DMA_CCR_DIR | DMA_CCR_MEM2MEM)); +} + +/** + * @brief Set DMA mode circular or normal. + * @note The circular buffer mode cannot be used if the memory-to-memory + * data transfer is configured on the selected Channel. + * @rmtoll CCR CIRC LL_DMA_SetMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param Mode This parameter can be one of the following values: + * @arg @ref LL_DMA_MODE_NORMAL + * @arg @ref LL_DMA_MODE_CIRCULAR + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetMode(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_CIRC, + Mode); +} + +/** + * @brief Get DMA mode circular or normal. + * @rmtoll CCR CIRC LL_DMA_GetMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_MODE_NORMAL + * @arg @ref LL_DMA_MODE_CIRCULAR + */ +__STATIC_INLINE uint32_t LL_DMA_GetMode(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, + DMA_CCR_CIRC)); +} + +/** + * @brief Set Peripheral increment mode. + * @rmtoll CCR PINC LL_DMA_SetPeriphIncMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param PeriphOrM2MSrcIncMode This parameter can be one of the following values: + * @arg @ref LL_DMA_PERIPH_INCREMENT + * @arg @ref LL_DMA_PERIPH_NOINCREMENT + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetPeriphIncMode(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_PINC, + PeriphOrM2MSrcIncMode); +} + +/** + * @brief Get Peripheral increment mode. + * @rmtoll CCR PINC LL_DMA_GetPeriphIncMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_PERIPH_INCREMENT + * @arg @ref LL_DMA_PERIPH_NOINCREMENT + */ +__STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, + DMA_CCR_PINC)); +} + +/** + * @brief Set Memory increment mode. + * @rmtoll CCR MINC LL_DMA_SetMemoryIncMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param MemoryOrM2MDstIncMode This parameter can be one of the following values: + * @arg @ref LL_DMA_MEMORY_INCREMENT + * @arg @ref LL_DMA_MEMORY_NOINCREMENT + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetMemoryIncMode(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_MINC, + MemoryOrM2MDstIncMode); +} + +/** + * @brief Get Memory increment mode. + * @rmtoll CCR MINC LL_DMA_GetMemoryIncMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_MEMORY_INCREMENT + * @arg @ref LL_DMA_MEMORY_NOINCREMENT + */ +__STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, + DMA_CCR_MINC)); +} + +/** + * @brief Set Peripheral size. + * @rmtoll CCR PSIZE LL_DMA_SetPeriphSize + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param PeriphOrM2MSrcDataSize This parameter can be one of the following values: + * @arg @ref LL_DMA_PDATAALIGN_BYTE + * @arg @ref LL_DMA_PDATAALIGN_HALFWORD + * @arg @ref LL_DMA_PDATAALIGN_WORD + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetPeriphSize(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_PSIZE, + PeriphOrM2MSrcDataSize); +} + +/** + * @brief Get Peripheral size. + * @rmtoll CCR PSIZE LL_DMA_GetPeriphSize + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_PDATAALIGN_BYTE + * @arg @ref LL_DMA_PDATAALIGN_HALFWORD + * @arg @ref LL_DMA_PDATAALIGN_WORD + */ +__STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, + DMA_CCR_PSIZE)); +} + +/** + * @brief Set Memory size. + * @rmtoll CCR MSIZE LL_DMA_SetMemorySize + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param MemoryOrM2MDstDataSize This parameter can be one of the following values: + * @arg @ref LL_DMA_MDATAALIGN_BYTE + * @arg @ref LL_DMA_MDATAALIGN_HALFWORD + * @arg @ref LL_DMA_MDATAALIGN_WORD + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetMemorySize(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_MSIZE, + MemoryOrM2MDstDataSize); +} + +/** + * @brief Get Memory size. + * @rmtoll CCR MSIZE LL_DMA_GetMemorySize + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_MDATAALIGN_BYTE + * @arg @ref LL_DMA_MDATAALIGN_HALFWORD + * @arg @ref LL_DMA_MDATAALIGN_WORD + */ +__STATIC_INLINE uint32_t LL_DMA_GetMemorySize(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, + DMA_CCR_MSIZE)); +} + +/** + * @brief Set Channel priority level. + * @rmtoll CCR PL LL_DMA_SetChannelPriorityLevel + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param Priority This parameter can be one of the following values: + * @arg @ref LL_DMA_PRIORITY_LOW + * @arg @ref LL_DMA_PRIORITY_MEDIUM + * @arg @ref LL_DMA_PRIORITY_HIGH + * @arg @ref LL_DMA_PRIORITY_VERYHIGH + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_PL, + Priority); +} + +/** + * @brief Get Channel priority level. + * @rmtoll CCR PL LL_DMA_GetChannelPriorityLevel + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_PRIORITY_LOW + * @arg @ref LL_DMA_PRIORITY_MEDIUM + * @arg @ref LL_DMA_PRIORITY_HIGH + * @arg @ref LL_DMA_PRIORITY_VERYHIGH + */ +__STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, + DMA_CCR_PL)); +} + +#if defined(DMA_CCR_SECM) +#if defined (CORE_CM0PLUS) +/** + * @brief Enable the DMA Channel secure attribute. + * @rmtoll CCR SECM LL_DMA_EnableChannelSecure\n + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_EnableChannelSecure(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_SECM); +} + +/** + * @brief Disable the DMA channel secure attribute. + * @rmtoll CCR SECM LL_DMA_DisableChannelSecure\n + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_DisableChannelSecure(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_SECM); +} +#endif /* CORE_CM0PLUS */ + +/** + * @brief Check if DMA channel is secure or not. + * @rmtoll CCR SECM LL_DMA_IsEnabledChannelSecure\n + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannelSecure(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, + DMA_CCR_SECM) == (DMA_CCR_SECM)) ? 1UL : 0UL); +} + +#if defined (CORE_CM0PLUS) +/** + * @brief Enable the secure attribute on DMA channel source. + * @rmtoll CCR SSEC LL_DMA_EnableChannelSrcSecure\n + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_EnableChannelSrcSecure(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_SSEC); +} + +/** + * @brief Disable the secure attribute on DMA channel source. + * @rmtoll CCR SSEC LL_DMA_DisableChannelSrcSecure\n + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_DisableChannelSrcSecure(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_SSEC); +} + +/** + * @brief Check if DMA channel source attribute is secure or not. + * @rmtoll CCR SSEC LL_DMA_IsEnabledChannelSrcSecure\n + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannelSrcSecure(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, + DMA_CCR_SSEC) == (DMA_CCR_SSEC)) ? 1UL : 0UL); +} + +/** + * @brief Enable the secure attribute on DMA channel destination + * @rmtoll CCR DSEC LL_DMA_EnableChannelDestSecure\n + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_EnableChannelDestSecure(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_DSEC); +} + +/** + * @brief Disable the secure attribute on DMA channel destination. + * @rmtoll CCR DSEC LL_DMA_DisableChannelDestSecure\n + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_DisableChannelDestSecure(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_DSEC); +} + +/** + * @brief Check if DMA channel destination attribute is secure or not. + * @rmtoll CCR DSEC LL_DMA_IsEnabledChannelDestSecure\n + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannelDestSecure(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, + DMA_CCR_DSEC) == (DMA_CCR_DSEC)) ? 1UL : 0UL); +} +#endif /* CORE_CM0PLUS */ +#endif /* DMA_CCR_SECM */ +#if defined(DMA_CCR_PRIV) + +/** + * @brief Enable the privilege attribute on DMA channel. + * @rmtoll CCR PRIV LL_DMA_EnableChannelPrivilege\n + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_EnableChannelPrivilege(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_PRIV); +} + +/** + * @brief Disable the privilege attribute on DMA channel. + * @rmtoll CCR PRIV LL_DMA_DisableChannelPrivilege\n + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_DisableChannelPrivilege(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_PRIV); +} + +/** + * @brief Check if DMA channel attribute is privilege or not. + * @rmtoll CCR PRIV LL_DMA_IsEnabledChannelPrivilege\n + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannelPrivilege(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, + DMA_CCR_PRIV) == (DMA_CCR_PRIV)) ? 1UL : 0UL); +} + +#endif /* DMA_CCR_PRIV */ +/** + * @brief Set Number of data to transfer. + * @note This action has no effect if + * channel is enabled. + * @rmtoll CNDTR NDT LL_DMA_SetDataLength + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param NbData Between Min_Data = 0 and Max_Data = 0x0000FFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetDataLength(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CNDTR, + DMA_CNDTR_NDT, NbData); +} + +/** + * @brief Get Number of data to transfer. + * @note Once the channel is enabled, the return value indicate the + * remaining bytes to be transmitted. + * @rmtoll CNDTR NDT LL_DMA_GetDataLength + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetDataLength(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CNDTR, + DMA_CNDTR_NDT)); +} + +/** + * @brief Configure the Source and Destination addresses. + * @note This API must not be called when the DMA channel is enabled. + * @note Each peripheral using DMA provides an API to get directly the register address (LL_PPP_DMA_GetRegAddr). + * @rmtoll CPAR PA LL_DMA_ConfigAddresses\n + * CMAR MA LL_DMA_ConfigAddresses + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param SrcAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + * @param DstAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + * @param Direction This parameter can be one of the following values: + * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY + * @retval None + */ +__STATIC_INLINE void LL_DMA_ConfigAddresses(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress, + uint32_t DstAddress, uint32_t Direction) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + /* Direction Memory to Periph */ + if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) + { + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CMAR, SrcAddress); + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CPAR, DstAddress); + } + /* Direction Periph to Memory and Memory to Memory */ + else + { + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CPAR, SrcAddress); + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CMAR, DstAddress); + } +} + +/** + * @brief Set the Memory address. + * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. + * @note This API must not be called when the DMA channel is enabled. + * @rmtoll CMAR MA LL_DMA_SetMemoryAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetMemoryAddress(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CMAR, MemoryAddress); +} + +/** + * @brief Set the Peripheral address. + * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. + * @note This API must not be called when the DMA channel is enabled. + * @rmtoll CPAR PA LL_DMA_SetPeriphAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param PeriphAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetPeriphAddress(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CPAR, PeriphAddress); +} + +/** + * @brief Get Memory address. + * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. + * @rmtoll CMAR MA LL_DMA_GetMemoryAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CMAR)); +} + +/** + * @brief Get Peripheral address. + * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. + * @rmtoll CPAR PA LL_DMA_GetPeriphAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CPAR)); +} + +/** + * @brief Set the Memory to Memory Source address. + * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. + * @note This API must not be called when the DMA channel is enabled. + * @rmtoll CPAR PA LL_DMA_SetM2MSrcAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetM2MSrcAddress(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CPAR, MemoryAddress); +} + +/** + * @brief Set the Memory to Memory Destination address. + * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. + * @note This API must not be called when the DMA channel is enabled. + * @rmtoll CMAR MA LL_DMA_SetM2MDstAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetM2MDstAddress(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CMAR, MemoryAddress); +} + +/** + * @brief Get the Memory to Memory Source address. + * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. + * @rmtoll CPAR PA LL_DMA_GetM2MSrcAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CPAR)); +} + +/** + * @brief Get the Memory to Memory Destination address. + * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. + * @rmtoll CMAR MA LL_DMA_GetM2MDstAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CMAR)); +} + +/** + * @brief Set DMA request for DMA Channels on DMAMUX Channel x. + * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. + * DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7. + * @rmtoll CxCR DMAREQ_ID LL_DMA_SetPeriphRequest + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param Request This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_MEM2MEM + * @arg @ref LL_DMAMUX_REQ_GENERATOR0 + * @arg @ref LL_DMAMUX_REQ_GENERATOR1 + * @arg @ref LL_DMAMUX_REQ_GENERATOR2 + * @arg @ref LL_DMAMUX_REQ_GENERATOR3 + * @arg @ref LL_DMAMUX_REQ_ADC + * @arg @ref LL_DMAMUX_REQ_DAC_OUT1 + * @arg @ref LL_DMAMUX_REQ_SPI1_RX + * @arg @ref LL_DMAMUX_REQ_SPI1_TX + * @arg @ref LL_DMAMUX_REQ_SPI2_RX + * @arg @ref LL_DMAMUX_REQ_SPI2_TX + * @arg @ref LL_DMAMUX_REQ_I2C1_RX + * @arg @ref LL_DMAMUX_REQ_I2C1_TX + * @arg @ref LL_DMAMUX_REQ_I2C2_RX + * @arg @ref LL_DMAMUX_REQ_I2C2_TX + * @arg @ref LL_DMAMUX_REQ_I2C3_RX + * @arg @ref LL_DMAMUX_REQ_I2C3_TX + * @arg @ref LL_DMAMUX_REQ_USART1_RX + * @arg @ref LL_DMAMUX_REQ_USART1_TX + * @arg @ref LL_DMAMUX_REQ_USART2_RX + * @arg @ref LL_DMAMUX_REQ_USART2_TX + * @arg @ref LL_DMAMUX_REQ_LPUART1_RX + * @arg @ref LL_DMAMUX_REQ_LPUART1_TX + * @arg @ref LL_DMAMUX_REQ_TIM1_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM1_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM1_CH3 + * @arg @ref LL_DMAMUX_REQ_TIM1_CH4 + * @arg @ref LL_DMAMUX_REQ_TIM1_UP + * @arg @ref LL_DMAMUX_REQ_TIM1_TRIG + * @arg @ref LL_DMAMUX_REQ_TIM1_COM + * @arg @ref LL_DMAMUX_REQ_TIM2_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM2_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM2_CH3 + * @arg @ref LL_DMAMUX_REQ_TIM2_CH4 + * @arg @ref LL_DMAMUX_REQ_TIM2_UP + * @arg @ref LL_DMAMUX_REQ_TIM16_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM16_UP + * @arg @ref LL_DMAMUX_REQ_TIM17_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM17_UP + * @arg @ref LL_DMAMUX_REQ_AES_IN + * @arg @ref LL_DMAMUX_REQ_AES_OUT + * @arg @ref LL_DMAMUX_REQ_SUBGHZSPI_RX + * @arg @ref LL_DMAMUX_REQ_SUBGHZSPI_TX + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetPeriphRequest(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Request) +{ + uint32_t dmamux_ccr_offset = ((((uint32_t)DMAx ^ (uint32_t)DMA1) >> 10U) * 7U); + MODIFY_REG((DMAMUX1_Channel0 + Channel + dmamux_ccr_offset)->CCR, DMAMUX_CxCR_DMAREQ_ID, Request); +} + +/** + * @brief Get DMA request for DMA Channels on DMAMUX Channel x. + * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. + * DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7. + * @rmtoll CxCR DMAREQ_ID LL_DMA_GetPeriphRequest + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_MEM2MEM + * @arg @ref LL_DMAMUX_REQ_GENERATOR0 + * @arg @ref LL_DMAMUX_REQ_GENERATOR1 + * @arg @ref LL_DMAMUX_REQ_GENERATOR2 + * @arg @ref LL_DMAMUX_REQ_GENERATOR3 + * @arg @ref LL_DMAMUX_REQ_ADC + * @arg @ref LL_DMAMUX_REQ_DAC_OUT1 + * @arg @ref LL_DMAMUX_REQ_SPI1_RX + * @arg @ref LL_DMAMUX_REQ_SPI1_TX + * @arg @ref LL_DMAMUX_REQ_SPI2_RX + * @arg @ref LL_DMAMUX_REQ_SPI2_TX + * @arg @ref LL_DMAMUX_REQ_I2C1_RX + * @arg @ref LL_DMAMUX_REQ_I2C1_TX + * @arg @ref LL_DMAMUX_REQ_I2C2_RX + * @arg @ref LL_DMAMUX_REQ_I2C2_TX + * @arg @ref LL_DMAMUX_REQ_I2C3_RX + * @arg @ref LL_DMAMUX_REQ_I2C3_TX + * @arg @ref LL_DMAMUX_REQ_USART1_RX + * @arg @ref LL_DMAMUX_REQ_USART1_TX + * @arg @ref LL_DMAMUX_REQ_USART2_RX + * @arg @ref LL_DMAMUX_REQ_USART2_TX + * @arg @ref LL_DMAMUX_REQ_LPUART1_RX + * @arg @ref LL_DMAMUX_REQ_LPUART1_TX + * @arg @ref LL_DMAMUX_REQ_TIM1_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM1_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM1_CH3 + * @arg @ref LL_DMAMUX_REQ_TIM1_CH4 + * @arg @ref LL_DMAMUX_REQ_TIM1_UP + * @arg @ref LL_DMAMUX_REQ_TIM1_TRIG + * @arg @ref LL_DMAMUX_REQ_TIM1_COM + * @arg @ref LL_DMAMUX_REQ_TIM2_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM2_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM2_CH3 + * @arg @ref LL_DMAMUX_REQ_TIM2_CH4 + * @arg @ref LL_DMAMUX_REQ_TIM2_UP + * @arg @ref LL_DMAMUX_REQ_TIM16_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM16_UP + * @arg @ref LL_DMAMUX_REQ_TIM17_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM17_UP + * @arg @ref LL_DMAMUX_REQ_AES_IN + * @arg @ref LL_DMAMUX_REQ_AES_OUT + * @arg @ref LL_DMAMUX_REQ_SUBGHZSPI_RX + * @arg @ref LL_DMAMUX_REQ_SUBGHZSPI_TX + */ +__STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dmamux_ccr_offset = ((((uint32_t)DMAx ^ (uint32_t)DMA1) >> 10U) * 7U); + return (READ_BIT((DMAMUX1_Channel0 + Channel + dmamux_ccr_offset)->CCR, DMAMUX_CxCR_DMAREQ_ID)); +} + +/** + * @} + */ + +/** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management + * @{ + */ + +/** + * @brief Get Channel 1 global interrupt flag. + * @rmtoll ISR GIF1 LL_DMA_IsActiveFlag_GI1 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(const DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF1) == (DMA_ISR_GIF1)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 2 global interrupt flag. + * @rmtoll ISR GIF2 LL_DMA_IsActiveFlag_GI2 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(const DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF2) == (DMA_ISR_GIF2)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 3 global interrupt flag. + * @rmtoll ISR GIF3 LL_DMA_IsActiveFlag_GI3 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(const DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF3) == (DMA_ISR_GIF3)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 4 global interrupt flag. + * @rmtoll ISR GIF4 LL_DMA_IsActiveFlag_GI4 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4(const DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF4) == (DMA_ISR_GIF4)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 5 global interrupt flag. + * @rmtoll ISR GIF5 LL_DMA_IsActiveFlag_GI5 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5(const DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF5) == (DMA_ISR_GIF5)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 6 global interrupt flag. + * @rmtoll ISR GIF6 LL_DMA_IsActiveFlag_GI6 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6(const DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF6) == (DMA_ISR_GIF6)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 7 global interrupt flag. + * @rmtoll ISR GIF7 LL_DMA_IsActiveFlag_GI7 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7(const DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF7) == (DMA_ISR_GIF7)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 1 transfer complete flag. + * @rmtoll ISR TCIF1 LL_DMA_IsActiveFlag_TC1 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(const DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF1) == (DMA_ISR_TCIF1)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 2 transfer complete flag. + * @rmtoll ISR TCIF2 LL_DMA_IsActiveFlag_TC2 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(const DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF2) == (DMA_ISR_TCIF2)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 3 transfer complete flag. + * @rmtoll ISR TCIF3 LL_DMA_IsActiveFlag_TC3 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(const DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF3) == (DMA_ISR_TCIF3)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 4 transfer complete flag. + * @rmtoll ISR TCIF4 LL_DMA_IsActiveFlag_TC4 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(const DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF4) == (DMA_ISR_TCIF4)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 5 transfer complete flag. + * @rmtoll ISR TCIF5 LL_DMA_IsActiveFlag_TC5 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(const DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF5) == (DMA_ISR_TCIF5)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 6 transfer complete flag. + * @rmtoll ISR TCIF6 LL_DMA_IsActiveFlag_TC6 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(const DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF6) == (DMA_ISR_TCIF6)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 7 transfer complete flag. + * @rmtoll ISR TCIF7 LL_DMA_IsActiveFlag_TC7 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(const DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF7) == (DMA_ISR_TCIF7)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 1 half transfer flag. + * @rmtoll ISR HTIF1 LL_DMA_IsActiveFlag_HT1 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(const DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF1) == (DMA_ISR_HTIF1)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 2 half transfer flag. + * @rmtoll ISR HTIF2 LL_DMA_IsActiveFlag_HT2 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(const DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF2) == (DMA_ISR_HTIF2)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 3 half transfer flag. + * @rmtoll ISR HTIF3 LL_DMA_IsActiveFlag_HT3 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(const DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF3) == (DMA_ISR_HTIF3)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 4 half transfer flag. + * @rmtoll ISR HTIF4 LL_DMA_IsActiveFlag_HT4 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(const DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF4) == (DMA_ISR_HTIF4)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 5 half transfer flag. + * @rmtoll ISR HTIF5 LL_DMA_IsActiveFlag_HT5 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(const DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF5) == (DMA_ISR_HTIF5)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 6 half transfer flag. + * @rmtoll ISR HTIF6 LL_DMA_IsActiveFlag_HT6 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(const DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF6) == (DMA_ISR_HTIF6)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 7 half transfer flag. + * @rmtoll ISR HTIF7 LL_DMA_IsActiveFlag_HT7 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(const DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF7) == (DMA_ISR_HTIF7)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 1 transfer error flag. + * @rmtoll ISR TEIF1 LL_DMA_IsActiveFlag_TE1 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(const DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF1) == (DMA_ISR_TEIF1)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 2 transfer error flag. + * @rmtoll ISR TEIF2 LL_DMA_IsActiveFlag_TE2 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(const DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF2) == (DMA_ISR_TEIF2)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 3 transfer error flag. + * @rmtoll ISR TEIF3 LL_DMA_IsActiveFlag_TE3 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(const DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF3) == (DMA_ISR_TEIF3)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 4 transfer error flag. + * @rmtoll ISR TEIF4 LL_DMA_IsActiveFlag_TE4 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(const DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF4) == (DMA_ISR_TEIF4)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 5 transfer error flag. + * @rmtoll ISR TEIF5 LL_DMA_IsActiveFlag_TE5 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(const DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF5) == (DMA_ISR_TEIF5)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 6 transfer error flag. + * @rmtoll ISR TEIF6 LL_DMA_IsActiveFlag_TE6 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(const DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF6) == (DMA_ISR_TEIF6)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 7 transfer error flag. + * @rmtoll ISR TEIF7 LL_DMA_IsActiveFlag_TE7 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(const DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF7) == (DMA_ISR_TEIF7)) ? 1UL : 0UL); +} + +/** + * @brief Clear Channel 1 global interrupt flag. + * @rmtoll IFCR CGIF1 LL_DMA_ClearFlag_GI1 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_GI1(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF1); +} + +/** + * @brief Clear Channel 2 global interrupt flag. + * @rmtoll IFCR CGIF2 LL_DMA_ClearFlag_GI2 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_GI2(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF2); +} + +/** + * @brief Clear Channel 3 global interrupt flag. + * @rmtoll IFCR CGIF3 LL_DMA_ClearFlag_GI3 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_GI3(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF3); +} + +/** + * @brief Clear Channel 4 global interrupt flag. + * @rmtoll IFCR CGIF4 LL_DMA_ClearFlag_GI4 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_GI4(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF4); +} + +/** + * @brief Clear Channel 5 global interrupt flag. + * @rmtoll IFCR CGIF5 LL_DMA_ClearFlag_GI5 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_GI5(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF5); +} + +/** + * @brief Clear Channel 6 global interrupt flag. + * @rmtoll IFCR CGIF6 LL_DMA_ClearFlag_GI6 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_GI6(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF6); +} + +/** + * @brief Clear Channel 7 global interrupt flag. + * @rmtoll IFCR CGIF7 LL_DMA_ClearFlag_GI7 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_GI7(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF7); +} + +/** + * @brief Clear Channel 1 transfer complete flag. + * @rmtoll IFCR CTCIF1 LL_DMA_ClearFlag_TC1 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF1); +} + +/** + * @brief Clear Channel 2 transfer complete flag. + * @rmtoll IFCR CTCIF2 LL_DMA_ClearFlag_TC2 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF2); +} + +/** + * @brief Clear Channel 3 transfer complete flag. + * @rmtoll IFCR CTCIF3 LL_DMA_ClearFlag_TC3 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF3); +} + +/** + * @brief Clear Channel 4 transfer complete flag. + * @rmtoll IFCR CTCIF4 LL_DMA_ClearFlag_TC4 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF4); +} + +/** + * @brief Clear Channel 5 transfer complete flag. + * @rmtoll IFCR CTCIF5 LL_DMA_ClearFlag_TC5 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF5); +} + +/** + * @brief Clear Channel 6 transfer complete flag. + * @rmtoll IFCR CTCIF6 LL_DMA_ClearFlag_TC6 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF6); +} + +/** + * @brief Clear Channel 7 transfer complete flag. + * @rmtoll IFCR CTCIF7 LL_DMA_ClearFlag_TC7 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF7); +} + +/** + * @brief Clear Channel 1 half transfer flag. + * @rmtoll IFCR CHTIF1 LL_DMA_ClearFlag_HT1 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF1); +} + +/** + * @brief Clear Channel 2 half transfer flag. + * @rmtoll IFCR CHTIF2 LL_DMA_ClearFlag_HT2 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF2); +} + +/** + * @brief Clear Channel 3 half transfer flag. + * @rmtoll IFCR CHTIF3 LL_DMA_ClearFlag_HT3 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF3); +} + +/** + * @brief Clear Channel 4 half transfer flag. + * @rmtoll IFCR CHTIF4 LL_DMA_ClearFlag_HT4 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF4); +} + +/** + * @brief Clear Channel 5 half transfer flag. + * @rmtoll IFCR CHTIF5 LL_DMA_ClearFlag_HT5 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF5); +} + +/** + * @brief Clear Channel 6 half transfer flag. + * @rmtoll IFCR CHTIF6 LL_DMA_ClearFlag_HT6 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF6); +} + +/** + * @brief Clear Channel 7 half transfer flag. + * @rmtoll IFCR CHTIF7 LL_DMA_ClearFlag_HT7 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF7); +} + +/** + * @brief Clear Channel 1 transfer error flag. + * @rmtoll IFCR CTEIF1 LL_DMA_ClearFlag_TE1 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF1); +} + +/** + * @brief Clear Channel 2 transfer error flag. + * @rmtoll IFCR CTEIF2 LL_DMA_ClearFlag_TE2 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF2); +} + +/** + * @brief Clear Channel 3 transfer error flag. + * @rmtoll IFCR CTEIF3 LL_DMA_ClearFlag_TE3 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF3); +} + +/** + * @brief Clear Channel 4 transfer error flag. + * @rmtoll IFCR CTEIF4 LL_DMA_ClearFlag_TE4 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF4); +} + +/** + * @brief Clear Channel 5 transfer error flag. + * @rmtoll IFCR CTEIF5 LL_DMA_ClearFlag_TE5 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF5); +} + +/** + * @brief Clear Channel 6 transfer error flag. + * @rmtoll IFCR CTEIF6 LL_DMA_ClearFlag_TE6 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF6); +} + +/** + * @brief Clear Channel 7 transfer error flag. + * @rmtoll IFCR CTEIF7 LL_DMA_ClearFlag_TE7 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF7); +} + +/** + * @} + */ + +/** @defgroup DMA_LL_EF_IT_Management IT_Management + * @{ + */ +/** + * @brief Enable Transfer complete interrupt. + * @rmtoll CCR TCIE LL_DMA_EnableIT_TC + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_EnableIT_TC(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TCIE); +} + +/** + * @brief Enable Half transfer interrupt. + * @rmtoll CCR HTIE LL_DMA_EnableIT_HT + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_EnableIT_HT(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_HTIE); +} + +/** + * @brief Enable Transfer error interrupt. + * @rmtoll CCR TEIE LL_DMA_EnableIT_TE + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_EnableIT_TE(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TEIE); +} + +/** + * @brief Disable Transfer complete interrupt. + * @rmtoll CCR TCIE LL_DMA_DisableIT_TC + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_DisableIT_TC(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TCIE); +} + +/** + * @brief Disable Half transfer interrupt. + * @rmtoll CCR HTIE LL_DMA_DisableIT_HT + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_DisableIT_HT(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_HTIE); +} + +/** + * @brief Disable Transfer error interrupt. + * @rmtoll CCR TEIE LL_DMA_DisableIT_TE + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_DisableIT_TE(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TEIE); +} + +/** + * @brief Check if Transfer complete Interrupt is enabled. + * @rmtoll CCR TCIE LL_DMA_IsEnabledIT_TC + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, + DMA_CCR_TCIE) == (DMA_CCR_TCIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if Half transfer Interrupt is enabled. + * @rmtoll CCR HTIE LL_DMA_IsEnabledIT_HT + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, + DMA_CCR_HTIE) == (DMA_CCR_HTIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if Transfer error Interrupt is enabled. + * @rmtoll CCR TEIE LL_DMA_IsEnabledIT_TE + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, + DMA_CCR_TEIE) == (DMA_CCR_TEIE)) ? 1UL : 0UL); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions + * @{ + */ +ErrorStatus LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct); +ErrorStatus LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel); +void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct); + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* DMA1 || DMA2 */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32WLxx_LL_DMA_H */ + diff --git a/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h b/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h new file mode 100644 index 0000000..abde82d --- /dev/null +++ b/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h @@ -0,0 +1,1703 @@ +/** + ****************************************************************************** + * @file stm32wlxx_ll_dmamux.h + * @author MCD Application Team + * @brief Header file of DMAMUX LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32WLxx_LL_DMAMUX_H +#define STM32WLxx_LL_DMAMUX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wlxx.h" + +/** @addtogroup STM32WLxx_LL_Driver + * @{ + */ + +#if defined (DMAMUX1) + +/** @defgroup DMAMUX_LL DMAMUX + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup DMAMUX_LL_Private_Constants DMAMUX Private Constants + * @{ + */ +/* Define used to get DMAMUX CCR register size */ +#define DMAMUX_CCR_SIZE 0x00000004UL + +/* Define used to get DMAMUX RGCR register size */ +#define DMAMUX_RGCR_SIZE 0x00000004UL +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup DMAMUX_LL_Exported_Constants DMAMUX Exported Constants + * @{ + */ +/** @defgroup DMAMUX_LL_EC_CLEAR_FLAG Clear Flags Defines + * @brief Flags defines which can be used with LL_DMAMUX_WriteReg function + * @{ + */ +#define LL_DMAMUX_CFR_CSOF0 DMAMUX_CFR_CSOF0 /*!< Synchronization Event Overrun Flag Channel 0 */ +#define LL_DMAMUX_CFR_CSOF1 DMAMUX_CFR_CSOF1 /*!< Synchronization Event Overrun Flag Channel 1 */ +#define LL_DMAMUX_CFR_CSOF2 DMAMUX_CFR_CSOF2 /*!< Synchronization Event Overrun Flag Channel 2 */ +#define LL_DMAMUX_CFR_CSOF3 DMAMUX_CFR_CSOF3 /*!< Synchronization Event Overrun Flag Channel 3 */ +#define LL_DMAMUX_CFR_CSOF4 DMAMUX_CFR_CSOF4 /*!< Synchronization Event Overrun Flag Channel 4 */ +#define LL_DMAMUX_CFR_CSOF5 DMAMUX_CFR_CSOF5 /*!< Synchronization Event Overrun Flag Channel 5 */ +#define LL_DMAMUX_CFR_CSOF6 DMAMUX_CFR_CSOF6 /*!< Synchronization Event Overrun Flag Channel 6 */ +#define LL_DMAMUX_CFR_CSOF7 DMAMUX_CFR_CSOF7 /*!< Synchronization Event Overrun Flag Channel 7 */ +#define LL_DMAMUX_CFR_CSOF8 DMAMUX_CFR_CSOF8 /*!< Synchronization Event Overrun Flag Channel 8 */ +#define LL_DMAMUX_CFR_CSOF9 DMAMUX_CFR_CSOF9 /*!< Synchronization Event Overrun Flag Channel 9 */ +#define LL_DMAMUX_CFR_CSOF10 DMAMUX_CFR_CSOF10 /*!< Synchronization Event Overrun Flag Channel 10 */ +#define LL_DMAMUX_CFR_CSOF11 DMAMUX_CFR_CSOF11 /*!< Synchronization Event Overrun Flag Channel 11 */ +#define LL_DMAMUX_CFR_CSOF12 DMAMUX_CFR_CSOF12 /*!< Synchronization Event Overrun Flag Channel 12 */ +#define LL_DMAMUX_CFR_CSOF13 DMAMUX_CFR_CSOF13 /*!< Synchronization Event Overrun Flag Channel 13 */ +#define LL_DMAMUX_RGCFR_RGCOF0 DMAMUX_RGCFR_COF0 /*!< Request Generator 0 Trigger Event Overrun Flag */ +#define LL_DMAMUX_RGCFR_RGCOF1 DMAMUX_RGCFR_COF1 /*!< Request Generator 1 Trigger Event Overrun Flag */ +#define LL_DMAMUX_RGCFR_RGCOF2 DMAMUX_RGCFR_COF2 /*!< Request Generator 2 Trigger Event Overrun Flag */ +#define LL_DMAMUX_RGCFR_RGCOF3 DMAMUX_RGCFR_COF3 /*!< Request Generator 3 Trigger Event Overrun Flag */ +/** + * @} + */ + +/** @defgroup DMAMUX_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_DMAMUX_ReadReg function + * @{ + */ +#define LL_DMAMUX_CSR_SOF0 DMAMUX_CSR_SOF0 /*!< Synchronization Event Overrun Flag Channel 0 */ +#define LL_DMAMUX_CSR_SOF1 DMAMUX_CSR_SOF1 /*!< Synchronization Event Overrun Flag Channel 1 */ +#define LL_DMAMUX_CSR_SOF2 DMAMUX_CSR_SOF2 /*!< Synchronization Event Overrun Flag Channel 2 */ +#define LL_DMAMUX_CSR_SOF3 DMAMUX_CSR_SOF3 /*!< Synchronization Event Overrun Flag Channel 3 */ +#define LL_DMAMUX_CSR_SOF4 DMAMUX_CSR_SOF4 /*!< Synchronization Event Overrun Flag Channel 4 */ +#define LL_DMAMUX_CSR_SOF5 DMAMUX_CSR_SOF5 /*!< Synchronization Event Overrun Flag Channel 5 */ +#define LL_DMAMUX_CSR_SOF6 DMAMUX_CSR_SOF6 /*!< Synchronization Event Overrun Flag Channel 6 */ +#define LL_DMAMUX_CSR_SOF7 DMAMUX_CSR_SOF7 /*!< Synchronization Event Overrun Flag Channel 7 */ +#define LL_DMAMUX_CSR_SOF8 DMAMUX_CSR_SOF8 /*!< Synchronization Event Overrun Flag Channel 8 */ +#define LL_DMAMUX_CSR_SOF9 DMAMUX_CSR_SOF9 /*!< Synchronization Event Overrun Flag Channel 9 */ +#define LL_DMAMUX_CSR_SOF10 DMAMUX_CSR_SOF10 /*!< Synchronization Event Overrun Flag Channel 10 */ +#define LL_DMAMUX_CSR_SOF11 DMAMUX_CSR_SOF11 /*!< Synchronization Event Overrun Flag Channel 11 */ +#define LL_DMAMUX_CSR_SOF12 DMAMUX_CSR_SOF12 /*!< Synchronization Event Overrun Flag Channel 12 */ +#define LL_DMAMUX_CSR_SOF13 DMAMUX_CSR_SOF13 /*!< Synchronization Event Overrun Flag Channel 13 */ +#define LL_DMAMUX_RGSR_RGOF0 DMAMUX_RGSR_OF0 /*!< Request Generator 0 Trigger Event Overrun Flag */ +#define LL_DMAMUX_RGSR_RGOF1 DMAMUX_RGSR_OF1 /*!< Request Generator 1 Trigger Event Overrun Flag */ +#define LL_DMAMUX_RGSR_RGOF2 DMAMUX_RGSR_OF2 /*!< Request Generator 2 Trigger Event Overrun Flag */ +#define LL_DMAMUX_RGSR_RGOF3 DMAMUX_RGSR_OF3 /*!< Request Generator 3 Trigger Event Overrun Flag */ +/** + * @} + */ + +/** @defgroup DMAMUX_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_DMA_ReadReg and LL_DMAMUX_WriteReg functions + * @{ + */ +#define LL_DMAMUX_CCR_SOIE DMAMUX_CxCR_SOIE /*!< Synchronization Event Overrun Interrupt */ +#define LL_DMAMUX_RGCR_RGOIE DMAMUX_RGxCR_OIE /*!< Request Generation Trigger Event Overrun Interrupt */ +/** + * @} + */ + +/** @defgroup DMAMUX_LL_EC_REQUEST Transfer request + * @{ + */ +#define LL_DMAMUX_REQ_MEM2MEM 0x00000000U /*!< memory to memory transfer */ +#define LL_DMAMUX_REQ_GENERATOR0 0x00000001U /*!< DMAMUX request generator 0 */ +#define LL_DMAMUX_REQ_GENERATOR1 0x00000002U /*!< DMAMUX request generator 1 */ +#define LL_DMAMUX_REQ_GENERATOR2 0x00000003U /*!< DMAMUX request generator 2 */ +#define LL_DMAMUX_REQ_GENERATOR3 0x00000004U /*!< DMAMUX request generator 3 */ +#define LL_DMAMUX_REQ_ADC 0x00000005U /*!< DMAMUX ADC request */ +#define LL_DMAMUX_REQ_DAC_OUT1 0x00000006U /*!< DMAMUX DAC OUT request */ +#define LL_DMAMUX_REQ_SPI1_RX 0x00000007U /*!< DMAMUX SPI1 RX request */ +#define LL_DMAMUX_REQ_SPI1_TX 0x00000008U /*!< DMAMUX SPI1 TX request */ +#define LL_DMAMUX_REQ_SPI2_RX 0x00000009U /*!< DMAMUX SPI2 RX request */ +#define LL_DMAMUX_REQ_SPI2_TX 0x0000000AU /*!< DMAMUX SPI2 TX request */ +#define LL_DMAMUX_REQ_I2C1_RX 0x0000000BU /*!< DMAMUX I2C1 RX request */ +#define LL_DMAMUX_REQ_I2C1_TX 0x0000000CU /*!< DMAMUX I2C1 TX request */ +#define LL_DMAMUX_REQ_I2C2_RX 0x0000000DU /*!< DMAMUX I2C2 RX request */ +#define LL_DMAMUX_REQ_I2C2_TX 0x0000000EU /*!< DMAMUX I2C2 TX request */ +#define LL_DMAMUX_REQ_I2C3_RX 0x0000000FU /*!< DMAMUX I2C3 RX request */ +#define LL_DMAMUX_REQ_I2C3_TX 0x00000010U /*!< DMAMUX I2C3 TX request */ +#define LL_DMAMUX_REQ_USART1_RX 0x00000011U /*!< DMAMUX USART1 RX request */ +#define LL_DMAMUX_REQ_USART1_TX 0x00000012U /*!< DMAMUX USART1 TX request */ +#define LL_DMAMUX_REQ_USART2_RX 0x00000013U /*!< DMAMUX USART2 RX request */ +#define LL_DMAMUX_REQ_USART2_TX 0x00000014U /*!< DMAMUX USART2 TX request */ +#define LL_DMAMUX_REQ_LPUART1_RX 0x00000015U /*!< DMAMUX LPUART1 RX request */ +#define LL_DMAMUX_REQ_LPUART1_TX 0x00000016U /*!< DMAMUX LPUART1 TX request */ +#define LL_DMAMUX_REQ_TIM1_CH1 0x00000017U /*!< DMAMUX TIM1 CH1 request */ +#define LL_DMAMUX_REQ_TIM1_CH2 0x00000018U /*!< DMAMUX TIM1 CH2 request */ +#define LL_DMAMUX_REQ_TIM1_CH3 0x00000019U /*!< DMAMUX TIM1 CH3 request */ +#define LL_DMAMUX_REQ_TIM1_CH4 0x0000001AU /*!< DMAMUX TIM1 CH4 request */ +#define LL_DMAMUX_REQ_TIM1_UP 0x0000001BU /*!< DMAMUX TIM1 UP request */ +#define LL_DMAMUX_REQ_TIM1_TRIG 0x0000001CU /*!< DMAMUX TIM1 TRIG request */ +#define LL_DMAMUX_REQ_TIM1_COM 0x0000001DU /*!< DMAMUX TIM1 COM request */ +#define LL_DMAMUX_REQ_TIM2_CH1 0x0000001EU /*!< DMAMUX TIM2 CH1 request */ +#define LL_DMAMUX_REQ_TIM2_CH2 0x0000001FU /*!< DMAMUX TIM2 CH2 request */ +#define LL_DMAMUX_REQ_TIM2_CH3 0x00000020U /*!< DMAMUX TIM2 CH3 request */ +#define LL_DMAMUX_REQ_TIM2_CH4 0x00000021U /*!< DMAMUX TIM2 CH4 request */ +#define LL_DMAMUX_REQ_TIM2_UP 0x00000022U /*!< DMAMUX TIM2 UP request */ +#define LL_DMAMUX_REQ_TIM16_CH1 0x00000023U /*!< DMAMUX TIM16 CH1 request */ +#define LL_DMAMUX_REQ_TIM16_UP 0x00000024U /*!< DMAMUX TIM16 UP request */ +#define LL_DMAMUX_REQ_TIM17_CH1 0x00000025U /*!< DMAMUX TIM17 CH1 request */ +#define LL_DMAMUX_REQ_TIM17_UP 0x00000026U /*!< DMAMUX TIM17 UP request */ +#define LL_DMAMUX_REQ_AES_IN 0x00000027U /*!< DMAMUX AES_IN request */ +#define LL_DMAMUX_REQ_AES_OUT 0x00000028U /*!< DMAMUX AES_OUT request */ +#define LL_DMAMUX_REQ_SUBGHZSPI_RX 0x00000029U /*!< DMAMUX SUBGHZSPI RX request*/ +#define LL_DMAMUX_REQ_SUBGHZSPI_TX 0x0000002AU /*!< DMAMUX SUBGHZSPI TX request*/ + +#define LL_DMAMUX_MAX_REQ LL_DMAMUX_REQ_SUBGHZSPI_TX +/** + * @} + */ + +/** @defgroup DMAMUX_LL_EC_CHANNEL DMAMUX Channel + * @{ + */ +#define LL_DMAMUX_CHANNEL_0 0x00000000U /*!< DMAMUX Channel 0 connected to DMA1 Channel 1 */ +#define LL_DMAMUX_CHANNEL_1 0x00000001U /*!< DMAMUX Channel 1 connected to DMA1 Channel 2 */ +#define LL_DMAMUX_CHANNEL_2 0x00000002U /*!< DMAMUX Channel 2 connected to DMA1 Channel 3 */ +#define LL_DMAMUX_CHANNEL_3 0x00000003U /*!< DMAMUX Channel 3 connected to DMA1 Channel 4 */ +#define LL_DMAMUX_CHANNEL_4 0x00000004U /*!< DMAMUX Channel 4 connected to DMA1 Channel 5 */ +#define LL_DMAMUX_CHANNEL_5 0x00000005U /*!< DMAMUX Channel 5 connected to DMA1 Channel 6 */ +#define LL_DMAMUX_CHANNEL_6 0x00000006U /*!< DMAMUX Channel 6 connected to DMA1 Channel 7 */ +#define LL_DMAMUX_CHANNEL_7 0x00000007U /*!< DMAMUX Channel 7 connected to DMA2 Channel 1 */ +#define LL_DMAMUX_CHANNEL_8 0x00000008U /*!< DMAMUX Channel 8 connected to DMA2 Channel 2 */ +#define LL_DMAMUX_CHANNEL_9 0x00000009U /*!< DMAMUX Channel 9 connected to DMA2 Channel 3 */ +#define LL_DMAMUX_CHANNEL_10 0x0000000AU /*!< DMAMUX Channel 10 connected to DMA2 Channel 4 */ +#define LL_DMAMUX_CHANNEL_11 0x0000000BU /*!< DMAMUX Channel 11 connected to DMA2 Channel 5 */ +#define LL_DMAMUX_CHANNEL_12 0x0000000CU /*!< DMAMUX Channel 12 connected to DMA2 Channel 6 */ +#define LL_DMAMUX_CHANNEL_13 0x0000000DU /*!< DMAMUX Channel 13 connected to DMA2 Channel 7 */ +/** + * @} + */ + +/** @defgroup DMAMUX_LL_EC_SYNC_NO Synchronization Signal Polarity + * @{ + */ +#define LL_DMAMUX_SYNC_NO_EVENT 0x00000000U /*!< All requests are blocked */ +#define LL_DMAMUX_SYNC_POL_RISING DMAMUX_CxCR_SPOL_0 /*!< Synchronization on event on rising edge */ +#define LL_DMAMUX_SYNC_POL_FALLING DMAMUX_CxCR_SPOL_1 /*!< Synchronization on event on falling edge */ +#define LL_DMAMUX_SYNC_POL_RISING_FALLING (DMAMUX_CxCR_SPOL_0 | DMAMUX_CxCR_SPOL_1) /*!< Synchronization on event on rising and falling edge */ +/** + * @} + */ + +/** @defgroup DMAMUX_LL_EC_SYNC_EVT Synchronization Signal Event + * @{ + */ +#define LL_DMAMUX_SYNC_EXTI_LINE0 0x00000000U /*!< Synchronization signal from EXTI Line0 */ +#define LL_DMAMUX_SYNC_EXTI_LINE1 DMAMUX_CxCR_SYNC_ID_0 /*!< Synchronization signal from EXTI Line1 */ +#define LL_DMAMUX_SYNC_EXTI_LINE2 DMAMUX_CxCR_SYNC_ID_1 /*!< Synchronization signal from EXTI Line2 */ +#define LL_DMAMUX_SYNC_EXTI_LINE3 (DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from EXTI Line3 */ +#define LL_DMAMUX_SYNC_EXTI_LINE4 DMAMUX_CxCR_SYNC_ID_2 /*!< Synchronization signal from EXTI Line4 */ +#define LL_DMAMUX_SYNC_EXTI_LINE5 (DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from EXTI Line5 */ +#define LL_DMAMUX_SYNC_EXTI_LINE6 (DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1) /*!< Synchronization signal from EXTI Line6 */ +#define LL_DMAMUX_SYNC_EXTI_LINE7 (DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from EXTI Line7 */ +#define LL_DMAMUX_SYNC_EXTI_LINE8 DMAMUX_CxCR_SYNC_ID_3 /*!< Synchronization signal from EXTI Line8 */ +#define LL_DMAMUX_SYNC_EXTI_LINE9 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from EXTI Line9 */ +#define LL_DMAMUX_SYNC_EXTI_LINE10 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_1) /*!< Synchronization signal from EXTI Line10 */ +#define LL_DMAMUX_SYNC_EXTI_LINE11 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from EXTI Line11 */ +#define LL_DMAMUX_SYNC_EXTI_LINE12 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_2) /*!< Synchronization signal from EXTI Line12 */ +#define LL_DMAMUX_SYNC_EXTI_LINE13 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from EXTI Line13 */ +#define LL_DMAMUX_SYNC_EXTI_LINE14 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1) /*!< Synchronization signal from EXTI Line14 */ +#define LL_DMAMUX_SYNC_EXTI_LINE15 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from EXTI Line15 */ +#define LL_DMAMUX_SYNC_DMAMUX_CH0 DMAMUX_CxCR_SYNC_ID_4 /*!< Synchronization signal from DMAMUX channel0 Event */ +#define LL_DMAMUX_SYNC_DMAMUX_CH1 (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from DMAMUX channel1 Event */ +#define LL_DMAMUX_SYNC_LPTIM1_OUT (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_1) /*!< Synchronization signal from LPTIM1 Output */ +#define LL_DMAMUX_SYNC_LPTIM2_OUT (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from LPTIM2 Output */ +#define LL_DMAMUX_SYNC_LPTIM3_OUT (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_2) /*!< Synchronization signal from LPTIM3 Output */ +/** + * @} + */ + +/** @defgroup DMAMUX_LL_EC_REQUEST_GENERATOR Request Generator Channel + * @{ + */ +#define LL_DMAMUX_REQ_GEN_0 0x00000000U +#define LL_DMAMUX_REQ_GEN_1 0x00000001U +#define LL_DMAMUX_REQ_GEN_2 0x00000002U +#define LL_DMAMUX_REQ_GEN_3 0x00000003U +/** + * @} + */ + +/** @defgroup DMAMUX_LL_EC_REQUEST_GEN_POLARITY External Request Signal Generation Polarity + * @{ + */ +#define LL_DMAMUX_REQ_GEN_NO_EVENT 0x00000000U /*!< No external DMA request generation */ +#define LL_DMAMUX_REQ_GEN_POL_RISING DMAMUX_RGxCR_GPOL_0 /*!< External DMA request generation on event on rising edge */ +#define LL_DMAMUX_REQ_GEN_POL_FALLING DMAMUX_RGxCR_GPOL_1 /*!< External DMA request generation on event on falling edge */ +#define LL_DMAMUX_REQ_GEN_POL_RISING_FALLING (DMAMUX_RGxCR_GPOL_0 | DMAMUX_RGxCR_GPOL_1) /*!< External DMA request generation on rising and falling edge */ +/** + * @} + */ + +/** @defgroup DMAMUX_LL_EC_REQUEST_GEN External Request Signal Generation + * @{ + */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE0 0x00000000U /*!< Request signal generation from EXTI Line0 */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE1 DMAMUX_RGxCR_SIG_ID_0 /*!< Request signal generation from EXTI Line1 */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE2 DMAMUX_RGxCR_SIG_ID_1 /*!< Request signal generation from EXTI Line2 */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE3 (DMAMUX_RGxCR_SIG_ID_1 |DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from EXTI Line3 */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE4 DMAMUX_RGxCR_SIG_ID_2 /*!< Request signal generation from EXTI Line4 */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE5 (DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from EXTI Line5 */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE6 (DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1) /*!< Request signal generation from EXTI Line6 */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE7 (DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from EXTI Line7 */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE8 DMAMUX_RGxCR_SIG_ID_3 /*!< Request signal generation from EXTI Line8 */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE9 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from EXTI Line9 */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE10 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_1) /*!< Request signal generation from EXTI Line10 */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE11 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_1 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from EXTI Line11 */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE12 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_2) /*!< Request signal generation from EXTI Line12 */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE13 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from EXTI Line13 */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE14 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1) /*!< Request signal generation from EXTI Line14 */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE15 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from EXTI Line15 */ +#define LL_DMAMUX_REQ_GEN_DMAMUX_CH0 DMAMUX_RGxCR_SIG_ID_4 /*!< Request signal generation from DMAMUX channel0 Event */ +#define LL_DMAMUX_REQ_GEN_DMAMUX_CH1 (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from DMAMUX channel1 Event */ +#define LL_DMAMUX_REQ_GEN_LPTIM1_OUT (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_1) /*!< Request signal generation from LPTIM1 Output */ +#define LL_DMAMUX_REQ_GEN_LPTIM2_OUT (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_1 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from LPTIM2 Output */ +#define LL_DMAMUX_REQ_GEN_LPTIM3_OUT (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_2) /*!< Request signal generation from LPTIM3 Output */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup DMAMUX_LL_Exported_Macros DMAMUX Exported Macros + * @{ + */ + +/** @defgroup DMAMUX_LL_EM_WRITE_READ Common Write and read registers macros + * @{ + */ +/** + * @brief Write a value in DMAMUX register + * @param __INSTANCE__ DMAMUX Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_DMAMUX_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in DMAMUX register + * @param __INSTANCE__ DMAMUX Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_DMAMUX_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup DMAMUX_LL_Exported_Functions DMAMUX Exported Functions + * @{ + */ + +/** @defgroup DMAMUX_LL_EF_Configuration Configuration + * @{ + */ +/** + * @brief Set DMAMUX request ID for DMAMUX Channel x. + * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. + * DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7. + * @rmtoll CxCR DMAREQ_ID LL_DMAMUX_SetRequestID + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 + * @arg @ref LL_DMAMUX_CHANNEL_6 + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @arg @ref LL_DMAMUX_CHANNEL_12 + * @arg @ref LL_DMAMUX_CHANNEL_13 + * @param Request This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_MEM2MEM + * @arg @ref LL_DMAMUX_REQ_GENERATOR0 + * @arg @ref LL_DMAMUX_REQ_GENERATOR1 + * @arg @ref LL_DMAMUX_REQ_GENERATOR2 + * @arg @ref LL_DMAMUX_REQ_GENERATOR3 + * @arg @ref LL_DMAMUX_REQ_ADC + * @arg @ref LL_DMAMUX_REQ_DAC_OUT1 + * @arg @ref LL_DMAMUX_REQ_SPI1_RX + * @arg @ref LL_DMAMUX_REQ_SPI1_TX + * @arg @ref LL_DMAMUX_REQ_SPI2_RX + * @arg @ref LL_DMAMUX_REQ_SPI2_TX + * @arg @ref LL_DMAMUX_REQ_I2C1_RX + * @arg @ref LL_DMAMUX_REQ_I2C1_TX + * @arg @ref LL_DMAMUX_REQ_I2C2_RX + * @arg @ref LL_DMAMUX_REQ_I2C2_TX + * @arg @ref LL_DMAMUX_REQ_I2C3_RX + * @arg @ref LL_DMAMUX_REQ_I2C3_TX + * @arg @ref LL_DMAMUX_REQ_USART1_RX + * @arg @ref LL_DMAMUX_REQ_USART1_TX + * @arg @ref LL_DMAMUX_REQ_USART2_RX + * @arg @ref LL_DMAMUX_REQ_USART2_TX + * @arg @ref LL_DMAMUX_REQ_LPUART1_RX + * @arg @ref LL_DMAMUX_REQ_LPUART1_TX + * @arg @ref LL_DMAMUX_REQ_TIM1_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM1_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM1_CH3 + * @arg @ref LL_DMAMUX_REQ_TIM1_CH4 + * @arg @ref LL_DMAMUX_REQ_TIM1_UP + * @arg @ref LL_DMAMUX_REQ_TIM1_TRIG + * @arg @ref LL_DMAMUX_REQ_TIM1_COM + * @arg @ref LL_DMAMUX_REQ_TIM2_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM2_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM2_CH3 + * @arg @ref LL_DMAMUX_REQ_TIM2_CH4 + * @arg @ref LL_DMAMUX_REQ_TIM2_UP + * @arg @ref LL_DMAMUX_REQ_TIM16_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM16_UP + * @arg @ref LL_DMAMUX_REQ_TIM17_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM17_UP + * @arg @ref LL_DMAMUX_REQ_AES_IN + * @arg @ref LL_DMAMUX_REQ_AES_OUT + * @arg @ref LL_DMAMUX_REQ_SUBGHZSPI_RX + * @arg @ref LL_DMAMUX_REQ_SUBGHZSPI_TX + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_SetRequestID(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Request) +{ + (void)(DMAMUXx); + MODIFY_REG((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_DMAREQ_ID, Request); +} + +/** + * @brief Get DMAMUX request ID for DMAMUX Channel x. + * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. + * DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7. + * @rmtoll CxCR DMAREQ_ID LL_DMAMUX_GetRequestID + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 + * @arg @ref LL_DMAMUX_CHANNEL_6 + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @arg @ref LL_DMAMUX_CHANNEL_12 + * @arg @ref LL_DMAMUX_CHANNEL_13 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_MEM2MEM + * @arg @ref LL_DMAMUX_REQ_GENERATOR0 + * @arg @ref LL_DMAMUX_REQ_GENERATOR1 + * @arg @ref LL_DMAMUX_REQ_GENERATOR2 + * @arg @ref LL_DMAMUX_REQ_GENERATOR3 + * @arg @ref LL_DMAMUX_REQ_ADC + * @arg @ref LL_DMAMUX_REQ_DAC_OUT1 + * @arg @ref LL_DMAMUX_REQ_SPI1_RX + * @arg @ref LL_DMAMUX_REQ_SPI1_TX + * @arg @ref LL_DMAMUX_REQ_SPI2_RX + * @arg @ref LL_DMAMUX_REQ_SPI2_TX + * @arg @ref LL_DMAMUX_REQ_I2C1_RX + * @arg @ref LL_DMAMUX_REQ_I2C1_TX + * @arg @ref LL_DMAMUX_REQ_I2C2_RX + * @arg @ref LL_DMAMUX_REQ_I2C2_TX + * @arg @ref LL_DMAMUX_REQ_I2C3_RX + * @arg @ref LL_DMAMUX_REQ_I2C3_TX + * @arg @ref LL_DMAMUX_REQ_USART1_RX + * @arg @ref LL_DMAMUX_REQ_USART1_TX + * @arg @ref LL_DMAMUX_REQ_USART2_RX + * @arg @ref LL_DMAMUX_REQ_USART2_TX + * @arg @ref LL_DMAMUX_REQ_LPUART1_RX + * @arg @ref LL_DMAMUX_REQ_LPUART1_TX + * @arg @ref LL_DMAMUX_REQ_TIM1_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM1_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM1_CH3 + * @arg @ref LL_DMAMUX_REQ_TIM1_CH4 + * @arg @ref LL_DMAMUX_REQ_TIM1_UP + * @arg @ref LL_DMAMUX_REQ_TIM1_TRIG + * @arg @ref LL_DMAMUX_REQ_TIM1_COM + * @arg @ref LL_DMAMUX_REQ_TIM2_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM2_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM2_CH3 + * @arg @ref LL_DMAMUX_REQ_TIM2_CH4 + * @arg @ref LL_DMAMUX_REQ_TIM2_UP + * @arg @ref LL_DMAMUX_REQ_TIM16_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM16_UP + * @arg @ref LL_DMAMUX_REQ_TIM17_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM17_UP + * @arg @ref LL_DMAMUX_REQ_AES_IN + * @arg @ref LL_DMAMUX_REQ_AES_OUT + * @arg @ref LL_DMAMUX_REQ_SUBGHZSPI_RX + * @arg @ref LL_DMAMUX_REQ_SUBGHZSPI_TX + */ +__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestID(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + (void)(DMAMUXx); + return (uint32_t)(READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_DMAREQ_ID)); +} + +/** + * @brief Set the number of DMA request that will be autorized after a synchronization event and/or the number of DMA request needed to generate an event. + * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. + * DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7. + * @rmtoll CxCR NBREQ LL_DMAMUX_SetSyncRequestNb + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 + * @arg @ref LL_DMAMUX_CHANNEL_6 + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @arg @ref LL_DMAMUX_CHANNEL_12 + * @arg @ref LL_DMAMUX_CHANNEL_13 + * @param RequestNb This parameter must be a value between Min_Data = 1 and Max_Data = 32. + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_SetSyncRequestNb(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t RequestNb) +{ + (void)(DMAMUXx); + MODIFY_REG((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_NBREQ, ((RequestNb - 1U) << DMAMUX_CxCR_NBREQ_Pos)); +} + +/** + * @brief Get the number of DMA request that will be autorized after a synchronization event and/or the number of DMA request needed to generate an event. + * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. + * DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7. + * @rmtoll CxCR NBREQ LL_DMAMUX_GetSyncRequestNb + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 + * @arg @ref LL_DMAMUX_CHANNEL_6 + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @arg @ref LL_DMAMUX_CHANNEL_12 + * @arg @ref LL_DMAMUX_CHANNEL_13 + * @retval Between Min_Data = 1 and Max_Data = 32 + */ +__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncRequestNb(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + (void)(DMAMUXx); + return (uint32_t)(((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_NBREQ)) >> DMAMUX_CxCR_NBREQ_Pos) + 1U); +} + +/** + * @brief Set the polarity of the signal on which the DMA request is synchronized. + * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. + * DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7. + * @rmtoll CxCR SPOL LL_DMAMUX_SetSyncPolarity + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 + * @arg @ref LL_DMAMUX_CHANNEL_6 + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @arg @ref LL_DMAMUX_CHANNEL_12 + * @arg @ref LL_DMAMUX_CHANNEL_13 + * @param Polarity This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_SYNC_NO_EVENT + * @arg @ref LL_DMAMUX_SYNC_POL_RISING + * @arg @ref LL_DMAMUX_SYNC_POL_FALLING + * @arg @ref LL_DMAMUX_SYNC_POL_RISING_FALLING + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_SetSyncPolarity(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Polarity) +{ + (void)(DMAMUXx); + MODIFY_REG((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SPOL, Polarity); +} + +/** + * @brief Get the polarity of the signal on which the DMA request is synchronized. + * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. + * DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7. + * @rmtoll CxCR SPOL LL_DMAMUX_GetSyncPolarity + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 + * @arg @ref LL_DMAMUX_CHANNEL_6 + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @arg @ref LL_DMAMUX_CHANNEL_12 + * @arg @ref LL_DMAMUX_CHANNEL_13 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMAMUX_SYNC_NO_EVENT + * @arg @ref LL_DMAMUX_SYNC_POL_RISING + * @arg @ref LL_DMAMUX_SYNC_POL_FALLING + * @arg @ref LL_DMAMUX_SYNC_POL_RISING_FALLING + */ +__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncPolarity(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + (void)(DMAMUXx); + return (uint32_t)(READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SPOL)); +} + +/** + * @brief Enable the Event Generation on DMAMUX channel x. + * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. + * DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7. + * @rmtoll CxCR EGE LL_DMAMUX_EnableEventGeneration + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 + * @arg @ref LL_DMAMUX_CHANNEL_6 + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @arg @ref LL_DMAMUX_CHANNEL_12 + * @arg @ref LL_DMAMUX_CHANNEL_13 + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_EnableEventGeneration(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + (void)(DMAMUXx); + SET_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_EGE); +} + +/** + * @brief Disable the Event Generation on DMAMUX channel x. + * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. + * DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7. + * @rmtoll CxCR EGE LL_DMAMUX_DisableEventGeneration + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 + * @arg @ref LL_DMAMUX_CHANNEL_6 + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @arg @ref LL_DMAMUX_CHANNEL_12 + * @arg @ref LL_DMAMUX_CHANNEL_13 + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_DisableEventGeneration(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + (void)(DMAMUXx); + CLEAR_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_EGE); +} + +/** + * @brief Check if the Event Generation on DMAMUX channel x is enabled or disabled. + * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. + * DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7. + * @rmtoll CxCR EGE LL_DMAMUX_IsEnabledEventGeneration + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 + * @arg @ref LL_DMAMUX_CHANNEL_6 + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @arg @ref LL_DMAMUX_CHANNEL_12 + * @arg @ref LL_DMAMUX_CHANNEL_13 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledEventGeneration(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + (void)(DMAMUXx); + return ((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_EGE) == (DMAMUX_CxCR_EGE)) ? 1UL : 0UL); +} + +/** + * @brief Enable the synchronization mode. + * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. + * DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7. + * @rmtoll CxCR SE LL_DMAMUX_EnableSync + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 + * @arg @ref LL_DMAMUX_CHANNEL_6 + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @arg @ref LL_DMAMUX_CHANNEL_12 + * @arg @ref LL_DMAMUX_CHANNEL_13 + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_EnableSync(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + (void)(DMAMUXx); + SET_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SE); +} + +/** + * @brief Disable the synchronization mode. + * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. + * DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7. + * @rmtoll CxCR SE LL_DMAMUX_DisableSync + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 + * @arg @ref LL_DMAMUX_CHANNEL_6 + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @arg @ref LL_DMAMUX_CHANNEL_12 + * @arg @ref LL_DMAMUX_CHANNEL_13 + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_DisableSync(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + (void)(DMAMUXx); + CLEAR_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SE); +} + +/** + * @brief Check if the synchronization mode is enabled or disabled. + * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. + * DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7. + * @rmtoll CxCR SE LL_DMAMUX_IsEnabledSync + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 + * @arg @ref LL_DMAMUX_CHANNEL_6 + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @arg @ref LL_DMAMUX_CHANNEL_12 + * @arg @ref LL_DMAMUX_CHANNEL_13 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledSync(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + (void)(DMAMUXx); + return ((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SE) == (DMAMUX_CxCR_SE)) ? 1UL : 0UL); +} + +/** + * @brief Set DMAMUX synchronization ID on DMAMUX Channel x. + * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. + * DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7. + * @rmtoll CxCR SYNC_ID LL_DMAMUX_SetSyncID + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 + * @arg @ref LL_DMAMUX_CHANNEL_6 + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @arg @ref LL_DMAMUX_CHANNEL_12 + * @arg @ref LL_DMAMUX_CHANNEL_13 + * @param SyncID This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE0 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE1 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE2 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE3 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE4 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE5 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE6 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE7 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE8 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE9 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE10 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE11 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE12 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE13 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE14 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE15 + * @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH0 + * @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH1 + * @arg @ref LL_DMAMUX_SYNC_LPTIM1_OUT + * @arg @ref LL_DMAMUX_SYNC_LPTIM2_OUT + * @arg @ref LL_DMAMUX_SYNC_LPTIM3_OUT + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_SetSyncID(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t SyncID) +{ + (void)(DMAMUXx); + MODIFY_REG((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SYNC_ID, SyncID); +} + +/** + * @brief Get DMAMUX synchronization ID on DMAMUX Channel x. + * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. + * DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7. + * @rmtoll CxCR SYNC_ID LL_DMAMUX_GetSyncID + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 + * @arg @ref LL_DMAMUX_CHANNEL_6 + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @arg @ref LL_DMAMUX_CHANNEL_12 + * @arg @ref LL_DMAMUX_CHANNEL_13 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE0 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE1 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE2 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE3 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE4 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE5 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE6 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE7 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE8 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE9 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE10 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE11 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE12 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE13 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE14 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE15 + * @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH0 + * @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH1 + * @arg @ref LL_DMAMUX_SYNC_LPTIM1_OUT + * @arg @ref LL_DMAMUX_SYNC_LPTIM2_OUT + * @arg @ref LL_DMAMUX_SYNC_LPTIM3_OUT + */ +__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncID(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + (void)(DMAMUXx); + return (uint32_t)(READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SYNC_ID)); +} + +/** + * @brief Enable the Request Generator. + * @rmtoll RGxCR GE LL_DMAMUX_EnableRequestGen + * @param DMAMUXx DMAMUXx Instance + * @param RequestGenChannel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_0 + * @arg @ref LL_DMAMUX_REQ_GEN_1 + * @arg @ref LL_DMAMUX_REQ_GEN_2 + * @arg @ref LL_DMAMUX_REQ_GEN_3 + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_EnableRequestGen(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +{ + (void)(DMAMUXx); + SET_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * + (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GE); +} + +/** + * @brief Disable the Request Generator. + * @rmtoll RGxCR GE LL_DMAMUX_DisableRequestGen + * @param DMAMUXx DMAMUXx Instance + * @param RequestGenChannel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_0 + * @arg @ref LL_DMAMUX_REQ_GEN_1 + * @arg @ref LL_DMAMUX_REQ_GEN_2 + * @arg @ref LL_DMAMUX_REQ_GEN_3 + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_DisableRequestGen(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +{ + (void)(DMAMUXx); + CLEAR_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * + (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GE); +} + +/** + * @brief Check if the Request Generator is enabled or disabled. + * @rmtoll RGxCR GE LL_DMAMUX_IsEnabledRequestGen + * @param DMAMUXx DMAMUXx Instance + * @param RequestGenChannel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_0 + * @arg @ref LL_DMAMUX_REQ_GEN_1 + * @arg @ref LL_DMAMUX_REQ_GEN_2 + * @arg @ref LL_DMAMUX_REQ_GEN_3 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledRequestGen(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +{ + (void)(DMAMUXx); + return ((READ_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * + (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GE) == (DMAMUX_RGxCR_GE)) ? 1UL : 0UL); +} + +/** + * @brief Set the polarity of the signal on which the DMA request is generated. + * @rmtoll RGxCR GPOL LL_DMAMUX_SetRequestGenPolarity + * @param DMAMUXx DMAMUXx Instance + * @param RequestGenChannel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_0 + * @arg @ref LL_DMAMUX_REQ_GEN_1 + * @arg @ref LL_DMAMUX_REQ_GEN_2 + * @arg @ref LL_DMAMUX_REQ_GEN_3 + * @param Polarity This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_NO_EVENT + * @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING + * @arg @ref LL_DMAMUX_REQ_GEN_POL_FALLING + * @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING_FALLING + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_SetRequestGenPolarity(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, + uint32_t Polarity) +{ + (void)(DMAMUXx); + MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * + (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GPOL, Polarity); +} + +/** + * @brief Get the polarity of the signal on which the DMA request is generated. + * @rmtoll RGxCR GPOL LL_DMAMUX_GetRequestGenPolarity + * @param DMAMUXx DMAMUXx Instance + * @param RequestGenChannel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_0 + * @arg @ref LL_DMAMUX_REQ_GEN_1 + * @arg @ref LL_DMAMUX_REQ_GEN_2 + * @arg @ref LL_DMAMUX_REQ_GEN_3 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_NO_EVENT + * @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING + * @arg @ref LL_DMAMUX_REQ_GEN_POL_FALLING + * @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING_FALLING + */ +__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestGenPolarity(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +{ + (void)(DMAMUXx); + return (uint32_t)(READ_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GPOL)); +} + +/** + * @brief Set the number of DMA request that will be autorized after a generation event. + * @note This field can only be written when Generator is disabled. + * @rmtoll RGxCR GNBREQ LL_DMAMUX_SetGenRequestNb + * @param DMAMUXx DMAMUXx Instance + * @param RequestGenChannel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_0 + * @arg @ref LL_DMAMUX_REQ_GEN_1 + * @arg @ref LL_DMAMUX_REQ_GEN_2 + * @arg @ref LL_DMAMUX_REQ_GEN_3 + * @param RequestNb This parameter must be a value between Min_Data = 1 and Max_Data = 32. + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_SetGenRequestNb(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, + uint32_t RequestNb) +{ + (void)(DMAMUXx); + MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * + (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GNBREQ, (RequestNb - 1U) << DMAMUX_RGxCR_GNBREQ_Pos); +} + +/** + * @brief Get the number of DMA request that will be autorized after a generation event. + * @rmtoll RGxCR GNBREQ LL_DMAMUX_GetGenRequestNb + * @param DMAMUXx DMAMUXx Instance + * @param RequestGenChannel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_0 + * @arg @ref LL_DMAMUX_REQ_GEN_1 + * @arg @ref LL_DMAMUX_REQ_GEN_2 + * @arg @ref LL_DMAMUX_REQ_GEN_3 + * @retval Between Min_Data = 1 and Max_Data = 32 + */ +__STATIC_INLINE uint32_t LL_DMAMUX_GetGenRequestNb(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +{ + (void)(DMAMUXx); + return (uint32_t)((READ_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GNBREQ) >> DMAMUX_RGxCR_GNBREQ_Pos) + 1U); +} + +/** + * @brief Set DMAMUX external Request Signal ID on DMAMUX Request Generation Trigger Event Channel x. + * @rmtoll RGxCR SIG_ID LL_DMAMUX_SetRequestSignalID + * @param DMAMUXx DMAMUXx Instance + * @param RequestGenChannel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_0 + * @arg @ref LL_DMAMUX_REQ_GEN_1 + * @arg @ref LL_DMAMUX_REQ_GEN_2 + * @arg @ref LL_DMAMUX_REQ_GEN_3 + * @param RequestSignalID This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE0 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE1 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE2 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE3 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE4 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE5 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE6 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE7 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE8 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE9 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE10 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE11 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE12 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE13 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE14 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE15 + * @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH0 + * @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH1 + * @arg @ref LL_DMAMUX_REQ_GEN_LPTIM1_OUT + * @arg @ref LL_DMAMUX_REQ_GEN_LPTIM2_OUT + * @arg @ref LL_DMAMUX_REQ_GEN_LPTIM3_OUT + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_SetRequestSignalID(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, + uint32_t RequestSignalID) +{ + (void)(DMAMUXx); + MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * + (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_SIG_ID, RequestSignalID); +} + +/** + * @brief Get DMAMUX external Request Signal ID set on DMAMUX Channel x. + * @rmtoll RGxCR SIG_ID LL_DMAMUX_GetRequestSignalID + * @param DMAMUXx DMAMUXx Instance + * @param RequestGenChannel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_0 + * @arg @ref LL_DMAMUX_REQ_GEN_1 + * @arg @ref LL_DMAMUX_REQ_GEN_2 + * @arg @ref LL_DMAMUX_REQ_GEN_3 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE0 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE1 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE2 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE3 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE4 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE5 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE6 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE7 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE8 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE9 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE10 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE11 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE12 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE13 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE14 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE15 + * @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH0 + * @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH1 + * @arg @ref LL_DMAMUX_REQ_GEN_LPTIM1_OUT + * @arg @ref LL_DMAMUX_REQ_GEN_LPTIM2_OUT + * @arg @ref LL_DMAMUX_REQ_GEN_LPTIM3_OUT + */ +__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestSignalID(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +{ + (void)(DMAMUXx); + return (uint32_t)(READ_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_SIG_ID)); +} + +/** + * @} + */ + +/** @defgroup DMAMUX_LL_EF_FLAG_Management FLAG_Management + * @{ + */ + +/** + * @brief Get Synchronization Event Overrun Flag Channel 0. + * @rmtoll CSR SOF0 LL_DMAMUX_IsActiveFlag_SO0 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO0(const DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF0) == (DMAMUX_CSR_SOF0)) ? 1UL : 0UL); +} + +/** + * @brief Get Synchronization Event Overrun Flag Channel 1. + * @rmtoll CSR SOF1 LL_DMAMUX_IsActiveFlag_SO1 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO1(const DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF1) == (DMAMUX_CSR_SOF1)) ? 1UL : 0UL); +} + +/** + * @brief Get Synchronization Event Overrun Flag Channel 2. + * @rmtoll CSR SOF2 LL_DMAMUX_IsActiveFlag_SO2 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO2(const DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF2) == (DMAMUX_CSR_SOF2)) ? 1UL : 0UL); +} + +/** + * @brief Get Synchronization Event Overrun Flag Channel 3. + * @rmtoll CSR SOF3 LL_DMAMUX_IsActiveFlag_SO3 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO3(const DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF3) == (DMAMUX_CSR_SOF3)) ? 1UL : 0UL); +} + +/** + * @brief Get Synchronization Event Overrun Flag Channel 4. + * @rmtoll CSR SOF4 LL_DMAMUX_IsActiveFlag_SO4 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO4(const DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF4) == (DMAMUX_CSR_SOF4)) ? 1UL : 0UL); +} + +/** + * @brief Get Synchronization Event Overrun Flag Channel 5. + * @rmtoll CSR SOF5 LL_DMAMUX_IsActiveFlag_SO5 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO5(const DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF5) == (DMAMUX_CSR_SOF5)) ? 1UL : 0UL); +} + +/** + * @brief Get Synchronization Event Overrun Flag Channel 6. + * @rmtoll CSR SOF6 LL_DMAMUX_IsActiveFlag_SO6 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO6(const DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF6) == (DMAMUX_CSR_SOF6)) ? 1UL : 0UL); +} + +/** + * @brief Get Synchronization Event Overrun Flag Channel 7. + * @rmtoll CSR SOF7 LL_DMAMUX_IsActiveFlag_SO7 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO7(const DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF7) == (DMAMUX_CSR_SOF7)) ? 1UL : 0UL); +} + +/** + * @brief Get Synchronization Event Overrun Flag Channel 8. + * @rmtoll CSR SOF8 LL_DMAMUX_IsActiveFlag_SO8 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO8(const DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF8) == (DMAMUX_CSR_SOF8)) ? 1UL : 0UL); +} + +/** + * @brief Get Synchronization Event Overrun Flag Channel 9. + * @rmtoll CSR SOF9 LL_DMAMUX_IsActiveFlag_SO9 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO9(const DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF9) == (DMAMUX_CSR_SOF9)) ? 1UL : 0UL); +} + +/** + * @brief Get Synchronization Event Overrun Flag Channel 10. + * @rmtoll CSR SOF10 LL_DMAMUX_IsActiveFlag_SO10 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO10(const DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF10) == (DMAMUX_CSR_SOF10)) ? 1UL : 0UL); +} + +/** + * @brief Get Synchronization Event Overrun Flag Channel 11. + * @rmtoll CSR SOF11 LL_DMAMUX_IsActiveFlag_SO11 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO11(const DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF11) == (DMAMUX_CSR_SOF11)) ? 1UL : 0UL); +} + +/** + * @brief Get Synchronization Event Overrun Flag Channel 12. + * @rmtoll CSR SOF12 LL_DMAMUX_IsActiveFlag_SO12 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO12(const DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF12) == (DMAMUX_CSR_SOF12)) ? 1UL : 0UL); +} + +/** + * @brief Get Synchronization Event Overrun Flag Channel 13. + * @rmtoll CSR SOF13 LL_DMAMUX_IsActiveFlag_SO13 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO13(const DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF13) == (DMAMUX_CSR_SOF13)) ? 1UL : 0UL); +} + +/** + * @brief Get Request Generator 0 Trigger Event Overrun Flag. + * @rmtoll RGSR OF0 LL_DMAMUX_IsActiveFlag_RGO0 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO0(const DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + return ((READ_BIT(DMAMUX1_RequestGenStatus->RGSR, DMAMUX_RGSR_OF0) == (DMAMUX_RGSR_OF0)) ? 1UL : 0UL); +} + +/** + * @brief Get Request Generator 1 Trigger Event Overrun Flag. + * @rmtoll RGSR OF1 LL_DMAMUX_IsActiveFlag_RGO1 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO1(const DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + return ((READ_BIT(DMAMUX1_RequestGenStatus->RGSR, DMAMUX_RGSR_OF1) == (DMAMUX_RGSR_OF1)) ? 1UL : 0UL); +} + +/** + * @brief Get Request Generator 2 Trigger Event Overrun Flag. + * @rmtoll RGSR OF2 LL_DMAMUX_IsActiveFlag_RGO2 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO2(const DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + return ((READ_BIT(DMAMUX1_RequestGenStatus->RGSR, DMAMUX_RGSR_OF2) == (DMAMUX_RGSR_OF2)) ? 1UL : 0UL); +} + +/** + * @brief Get Request Generator 3 Trigger Event Overrun Flag. + * @rmtoll RGSR OF3 LL_DMAMUX_IsActiveFlag_RGO3 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO3(const DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + return ((READ_BIT(DMAMUX1_RequestGenStatus->RGSR, DMAMUX_RGSR_OF3) == (DMAMUX_RGSR_OF3)) ? 1UL : 0UL); +} + +/** + * @brief Clear Synchronization Event Overrun Flag Channel 0. + * @rmtoll CFR CSOF0 LL_DMAMUX_ClearFlag_SO0 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO0(const DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF0); +} + +/** + * @brief Clear Synchronization Event Overrun Flag Channel 1. + * @rmtoll CFR CSOF1 LL_DMAMUX_ClearFlag_SO1 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO1(const DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF1); +} + +/** + * @brief Clear Synchronization Event Overrun Flag Channel 2. + * @rmtoll CFR CSOF2 LL_DMAMUX_ClearFlag_SO2 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO2(const DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF2); +} + +/** + * @brief Clear Synchronization Event Overrun Flag Channel 3. + * @rmtoll CFR CSOF3 LL_DMAMUX_ClearFlag_SO3 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO3(const DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF3); +} + +/** + * @brief Clear Synchronization Event Overrun Flag Channel 4. + * @rmtoll CFR CSOF4 LL_DMAMUX_ClearFlag_SO4 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO4(const DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF4); +} + +/** + * @brief Clear Synchronization Event Overrun Flag Channel 5. + * @rmtoll CFR CSOF5 LL_DMAMUX_ClearFlag_SO5 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO5(const DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF5); +} + +/** + * @brief Clear Synchronization Event Overrun Flag Channel 6. + * @rmtoll CFR CSOF6 LL_DMAMUX_ClearFlag_SO6 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO6(const DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF6); +} + +/** + * @brief Clear Synchronization Event Overrun Flag Channel 7. + * @rmtoll CFR CSOF7 LL_DMAMUX_ClearFlag_SO7 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO7(const DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF7); +} + +/** + * @brief Clear Synchronization Event Overrun Flag Channel 8. + * @rmtoll CFR CSOF8 LL_DMAMUX_ClearFlag_SO8 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO8(const DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF8); +} + +/** + * @brief Clear Synchronization Event Overrun Flag Channel 9. + * @rmtoll CFR CSOF9 LL_DMAMUX_ClearFlag_SO9 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO9(const DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF9); +} + +/** + * @brief Clear Synchronization Event Overrun Flag Channel 10. + * @rmtoll CFR CSOF10 LL_DMAMUX_ClearFlag_SO10 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO10(const DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF10); +} + +/** + * @brief Clear Synchronization Event Overrun Flag Channel 11. + * @rmtoll CFR CSOF11 LL_DMAMUX_ClearFlag_SO11 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO11(const DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF11); +} + +/** + * @brief Clear Synchronization Event Overrun Flag Channel 12. + * @rmtoll CFR CSOF12 LL_DMAMUX_ClearFlag_SO12 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO12(const DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF12); +} + +/** + * @brief Clear Synchronization Event Overrun Flag Channel 13. + * @rmtoll CFR CSOF13 LL_DMAMUX_ClearFlag_SO13 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO13(const DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF13); +} + +/** + * @brief Clear Request Generator 0 Trigger Event Overrun Flag. + * @rmtoll RGCFR COF0 LL_DMAMUX_ClearFlag_RGO0 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO0(const DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + SET_BIT(DMAMUX1_RequestGenStatus->RGCFR, DMAMUX_RGCFR_COF0); +} + +/** + * @brief Clear Request Generator 1 Trigger Event Overrun Flag. + * @rmtoll RGCFR COF1 LL_DMAMUX_ClearFlag_RGO1 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO1(const DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + SET_BIT(DMAMUX1_RequestGenStatus->RGCFR, DMAMUX_RGCFR_COF1); +} + +/** + * @brief Clear Request Generator 2 Trigger Event Overrun Flag. + * @rmtoll RGCFR COF2 LL_DMAMUX_ClearFlag_RGO2 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO2(const DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + SET_BIT(DMAMUX1_RequestGenStatus->RGCFR, DMAMUX_RGCFR_COF2); +} + +/** + * @brief Clear Request Generator 3 Trigger Event Overrun Flag. + * @rmtoll RGCFR COF3 LL_DMAMUX_ClearFlag_RGO3 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO3(const DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + SET_BIT(DMAMUX1_RequestGenStatus->RGCFR, DMAMUX_RGCFR_COF3); +} + +/** + * @} + */ + +/** @defgroup DMAMUX_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable the Synchronization Event Overrun Interrupt on DMAMUX channel x. + * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. + * DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7. + * @rmtoll CxCR SOIE LL_DMAMUX_EnableIT_SO + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 + * @arg @ref LL_DMAMUX_CHANNEL_6 + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @arg @ref LL_DMAMUX_CHANNEL_12 + * @arg @ref LL_DMAMUX_CHANNEL_13 + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_EnableIT_SO(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + (void)(DMAMUXx); + SET_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SOIE); +} + +/** + * @brief Disable the Synchronization Event Overrun Interrupt on DMAMUX channel x. + * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. + * DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7. + * @rmtoll CxCR SOIE LL_DMAMUX_DisableIT_SO + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 + * @arg @ref LL_DMAMUX_CHANNEL_6 + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @arg @ref LL_DMAMUX_CHANNEL_12 + * @arg @ref LL_DMAMUX_CHANNEL_13 + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_DisableIT_SO(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + (void)(DMAMUXx); + CLEAR_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SOIE); +} + +/** + * @brief Check if the Synchronization Event Overrun Interrupt on DMAMUX channel x is enabled or disabled. + * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. + * DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7. + * @rmtoll CxCR SOIE LL_DMAMUX_IsEnabledIT_SO + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 + * @arg @ref LL_DMAMUX_CHANNEL_6 + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @arg @ref LL_DMAMUX_CHANNEL_12 + * @arg @ref LL_DMAMUX_CHANNEL_13 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_SO(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + (void)(DMAMUXx); + return (((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SOIE)) == (DMAMUX_CxCR_SOIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x. + * @rmtoll RGxCR OIE LL_DMAMUX_EnableIT_RGO + * @param DMAMUXx DMAMUXx Instance + * @param RequestGenChannel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_0 + * @arg @ref LL_DMAMUX_REQ_GEN_1 + * @arg @ref LL_DMAMUX_REQ_GEN_2 + * @arg @ref LL_DMAMUX_REQ_GEN_3 + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_EnableIT_RGO(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +{ + (void)(DMAMUXx); + SET_BIT((DMAMUX1_RequestGenerator0 + RequestGenChannel)->RGCR, DMAMUX_RGxCR_OIE); +} + +/** + * @brief Disable the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x. + * @rmtoll RGxCR OIE LL_DMAMUX_DisableIT_RGO + * @param DMAMUXx DMAMUXx Instance + * @param RequestGenChannel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_0 + * @arg @ref LL_DMAMUX_REQ_GEN_1 + * @arg @ref LL_DMAMUX_REQ_GEN_2 + * @arg @ref LL_DMAMUX_REQ_GEN_3 + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_DisableIT_RGO(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +{ + (void)(DMAMUXx); + CLEAR_BIT((DMAMUX1_RequestGenerator0 + RequestGenChannel)->RGCR, DMAMUX_RGxCR_OIE); +} + +/** + * @brief Check if the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x is enabled or disabled. + * @rmtoll RGxCR OIE LL_DMAMUX_IsEnabledIT_RGO + * @param DMAMUXx DMAMUXx Instance + * @param RequestGenChannel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_0 + * @arg @ref LL_DMAMUX_REQ_GEN_1 + * @arg @ref LL_DMAMUX_REQ_GEN_2 + * @arg @ref LL_DMAMUX_REQ_GEN_3 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_RGO(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +{ + (void)(DMAMUXx); + return ((READ_BIT((DMAMUX1_RequestGenerator0 + RequestGenChannel)->RGCR, DMAMUX_RGxCR_OIE) == (DMAMUX_RGxCR_OIE)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* DMAMUX1 */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32WLxx_LL_DMAMUX_H */ + diff --git a/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h b/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h new file mode 100644 index 0000000..b5c4323 --- /dev/null +++ b/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h @@ -0,0 +1,1552 @@ +/** + ****************************************************************************** + * @file stm32wlxx_ll_exti.h + * @author MCD Application Team + * @brief Header file of EXTI LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32WLxx_LL_EXTI_H +#define __STM32WLxx_LL_EXTI_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wlxx.h" + +/** @addtogroup STM32WLxx_LL_Driver + * @{ + */ + +#if defined (EXTI) + +/** @defgroup EXTI_LL EXTI + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private Macros ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup EXTI_LL_Private_Macros EXTI Private Macros + * @{ + */ +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup EXTI_LL_ES_INIT EXTI Exported Init structure + * @{ + */ +typedef struct +{ + + uint32_t Line_0_31; /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 0 to 31 + This parameter can be any combination of @ref EXTI_LL_EC_LINE */ + + uint32_t Line_32_63; /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 32 to 63 + This parameter can be any combination of @ref EXTI_LL_EC_LINE */ + + FunctionalState LineCommand; /*!< Specifies the new state of the selected EXTI lines. + This parameter can be set either to ENABLE or DISABLE */ + + uint8_t Mode; /*!< Specifies the mode for the EXTI lines. + This parameter can be a value of @ref EXTI_LL_EC_MODE. */ + + uint8_t Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines. + This parameter can be a value of @ref EXTI_LL_EC_TRIGGER. */ +} LL_EXTI_InitTypeDef; + +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup EXTI_LL_Exported_Constants EXTI Exported Constants + * @{ + */ + +/** @defgroup EXTI_LL_EC_LINE LINE + * @{ + */ +#define LL_EXTI_LINE_0 EXTI_IMR1_IM0 /*!< Extended line 0 */ +#define LL_EXTI_LINE_1 EXTI_IMR1_IM1 /*!< Extended line 1 */ +#define LL_EXTI_LINE_2 EXTI_IMR1_IM2 /*!< Extended line 2 */ +#define LL_EXTI_LINE_3 EXTI_IMR1_IM3 /*!< Extended line 3 */ +#define LL_EXTI_LINE_4 EXTI_IMR1_IM4 /*!< Extended line 4 */ +#define LL_EXTI_LINE_5 EXTI_IMR1_IM5 /*!< Extended line 5 */ +#define LL_EXTI_LINE_6 EXTI_IMR1_IM6 /*!< Extended line 6 */ +#define LL_EXTI_LINE_7 EXTI_IMR1_IM7 /*!< Extended line 7 */ +#define LL_EXTI_LINE_8 EXTI_IMR1_IM8 /*!< Extended line 8 */ +#define LL_EXTI_LINE_9 EXTI_IMR1_IM9 /*!< Extended line 9 */ +#define LL_EXTI_LINE_10 EXTI_IMR1_IM10 /*!< Extended line 10 */ +#define LL_EXTI_LINE_11 EXTI_IMR1_IM11 /*!< Extended line 11 */ +#define LL_EXTI_LINE_12 EXTI_IMR1_IM12 /*!< Extended line 12 */ +#define LL_EXTI_LINE_13 EXTI_IMR1_IM13 /*!< Extended line 13 */ +#define LL_EXTI_LINE_14 EXTI_IMR1_IM14 /*!< Extended line 14 */ +#define LL_EXTI_LINE_15 EXTI_IMR1_IM15 /*!< Extended line 15 */ +#define LL_EXTI_LINE_16 EXTI_IMR1_IM16 /*!< Extended line 16 */ +#define LL_EXTI_LINE_17 EXTI_IMR1_IM17 /*!< Extended line 17 */ +#define LL_EXTI_LINE_18 EXTI_IMR1_IM18 /*!< Extended line 18 */ +#define LL_EXTI_LINE_19 EXTI_IMR1_IM19 /*!< Extended line 19 */ +#define LL_EXTI_LINE_20 EXTI_IMR1_IM20 /*!< Extended line 20 */ +#define LL_EXTI_LINE_21 EXTI_IMR1_IM21 /*!< Extended line 21 */ +#define LL_EXTI_LINE_22 EXTI_IMR1_IM22 /*!< Extended line 22 */ +#define LL_EXTI_LINE_23 EXTI_IMR1_IM23 /*!< Extended line 23 */ +#define LL_EXTI_LINE_24 EXTI_IMR1_IM24 /*!< Extended line 24 */ +#define LL_EXTI_LINE_25 EXTI_IMR1_IM25 /*!< Extended line 25 */ +#define LL_EXTI_LINE_26 EXTI_IMR1_IM26 /*!< Extended line 26 */ +#define LL_EXTI_LINE_27 EXTI_IMR1_IM27 /*!< Extended line 27 */ +#define LL_EXTI_LINE_28 EXTI_IMR1_IM28 /*!< Extended line 28 */ +#define LL_EXTI_LINE_29 EXTI_IMR1_IM29 /*!< Extended line 29 */ +#define LL_EXTI_LINE_30 EXTI_IMR1_IM30 /*!< Extended line 30 */ +#define LL_EXTI_LINE_31 EXTI_IMR1_IM31 /*!< Extended line 31 */ +#define LL_EXTI_LINE_ALL_0_31 0xFFFFFFFFU /*!< All Extended line not reserved*/ + +#define LL_EXTI_LINE_34 EXTI_IMR2_IM34 /*!< Extended line 34 */ +#if defined(DUAL_CORE) +#define LL_EXTI_LINE_36 EXTI_IMR2_IM36 /*!< Extended line 36 */ +#define LL_EXTI_LINE_37 EXTI_IMR2_IM37 /*!< Extended line 37 */ +#endif /* DUAL_CORE */ +#define LL_EXTI_LINE_38 EXTI_IMR2_IM38 /*!< Extended line 38 */ +#if defined(DUAL_CORE) +#define LL_EXTI_LINE_39 EXTI_IMR2_IM39 /*!< Extended line 39 */ +#define LL_EXTI_LINE_40 EXTI_IMR2_IM40 /*!< Extended line 40 */ +#define LL_EXTI_LINE_41 EXTI_IMR2_IM41 /*!< Extended line 41 */ +#endif /* DUAL_CORE */ +#define LL_EXTI_LINE_42 EXTI_IMR2_IM42 /*!< Extended line 42 */ +#define LL_EXTI_LINE_43 EXTI_IMR2_IM43 /*!< Extended line 43 */ +#define LL_EXTI_LINE_44 EXTI_IMR2_IM44 /*!< Extended line 44 */ +#define LL_EXTI_LINE_45 EXTI_IMR2_IM45 /*!< Extended line 45 */ +#define LL_EXTI_LINE_46 EXTI_IMR2_IM46 /*!< Extended line 46 */ +#if defined(DUAL_CORE) +#define LL_EXTI_LINE_ALL_32_63 (EXTI_IMR2_IM34 | EXTI_IMR2_IM36 | EXTI_IMR2_IM37 | \ + EXTI_IMR2_IM38 | EXTI_IMR2_IM39 | EXTI_IMR2_IM40 | \ + EXTI_IMR2_IM41 | EXTI_IMR2_IM42 | EXTI_IMR2_IM43 | \ + EXTI_IMR2_IM44 | EXTI_IMR2_IM45 | EXTI_IMR2_IM46) /*!< All Extended line not reserved*/ +#else +#define LL_EXTI_LINE_ALL_32_63 (EXTI_IMR2_IM34 | EXTI_IMR2_IM38 | EXTI_IMR2_IM42 | \ + EXTI_IMR2_IM43 | EXTI_IMR2_IM44 | EXTI_IMR2_IM45 | \ + EXTI_IMR2_IM46) /*!< All Extended line not reserved*/ +#endif /* DUAL_CORE */ + +#if defined(USE_FULL_LL_DRIVER) +#define LL_EXTI_LINE_NONE (0x00000000U) /*!< None Extended line */ +#endif /*USE_FULL_LL_DRIVER*/ + +/** + * @} + */ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup EXTI_LL_EC_MODE Mode + * @{ + */ +#define LL_EXTI_MODE_IT ((uint8_t)0x00U) /*!< Interrupt Mode */ +#define LL_EXTI_MODE_EVENT ((uint8_t)0x01U) /*!< Event Mode */ +#define LL_EXTI_MODE_IT_EVENT ((uint8_t)0x02U) /*!< Interrupt & Event Mode */ +/** + * @} + */ + +/** @defgroup EXTI_LL_EC_TRIGGER Edge Trigger + * @{ + */ +#define LL_EXTI_TRIGGER_NONE ((uint8_t)0x00U) /*!< No Trigger Mode */ +#define LL_EXTI_TRIGGER_RISING ((uint8_t)0x01U) /*!< Trigger Rising Mode */ +#define LL_EXTI_TRIGGER_FALLING ((uint8_t)0x02U) /*!< Trigger Falling Mode */ +#define LL_EXTI_TRIGGER_RISING_FALLING ((uint8_t)0x03U) /*!< Trigger Rising & Falling Mode */ +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup EXTI_LL_Exported_Macros EXTI Exported Macros + * @{ + */ + +/** @defgroup EXTI_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in EXTI register + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_EXTI_WriteReg(__REG__, __VALUE__) WRITE_REG(EXTI->__REG__, (__VALUE__)) + +/** + * @brief Read a value in EXTI register + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_EXTI_ReadReg(__REG__) READ_REG(EXTI->__REG__) +/** + * @} + */ + + +/** + * @} + */ + + + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup EXTI_LL_Exported_Functions EXTI Exported Functions + * @{ + */ +/** @defgroup EXTI_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable ExtiLine Interrupt request for Lines in range 0 to 31 + * @rmtoll IMR1 IMx LL_EXTI_EnableIT_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableIT_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->IMR1, ExtiLine); +} + +#if defined(DUAL_CORE) +/** + * @brief Enable ExtiLine Interrupt request for Lines in range 0 to 31 for cpu2 + * @rmtoll C2IMR1 IMx LL_C2_EXTI_EnableIT_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @retval None + */ +__STATIC_INLINE void LL_C2_EXTI_EnableIT_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->C2IMR1, ExtiLine); +} +#endif /* DUAL_CORE */ + +/** + * @brief Enable ExtiLine Interrupt request for Lines in range 32 to 63 + * @rmtoll IMR2 IMx LL_EXTI_EnableIT_32_63 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_36 (*) + * @arg @ref LL_EXTI_LINE_37 (*) + * @arg @ref LL_EXTI_LINE_38 + * @arg @ref LL_EXTI_LINE_39 (*) + * @arg @ref LL_EXTI_LINE_40 (*) + * @arg @ref LL_EXTI_LINE_41 (*) + * @arg @ref LL_EXTI_LINE_42 + * @arg @ref LL_EXTI_LINE_43 + * @arg @ref LL_EXTI_LINE_44 + * @arg @ref LL_EXTI_LINE_45 + * @arg @ref LL_EXTI_LINE_46 + * @arg @ref LL_EXTI_LINE_ALL_32_63 + * (*) value not defined in all devices + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableIT_32_63(uint32_t ExtiLine) +{ + SET_BIT(EXTI->IMR2, ExtiLine); +} + +#if defined(DUAL_CORE) +/** + * @brief Enable ExtiLine Interrupt request for Lines in range 32 to 63 for cpu2 + * @rmtoll C2IMR2 IMx LL_C2_EXTI_EnableIT_32_63 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_36 (*) + * @arg @ref LL_EXTI_LINE_37 (*) + * @arg @ref LL_EXTI_LINE_38 + * @arg @ref LL_EXTI_LINE_39 (*) + * @arg @ref LL_EXTI_LINE_40 (*) + * @arg @ref LL_EXTI_LINE_41 (*) + * @arg @ref LL_EXTI_LINE_42 + * @arg @ref LL_EXTI_LINE_43 + * @arg @ref LL_EXTI_LINE_44 + * @arg @ref LL_EXTI_LINE_45 + * @arg @ref LL_EXTI_LINE_46 + * @arg @ref LL_EXTI_LINE_ALL_32_63 + * (*) value not defined in all devices + * @retval None + */ +__STATIC_INLINE void LL_C2_EXTI_EnableIT_32_63(uint32_t ExtiLine) +{ + SET_BIT(EXTI->C2IMR2, ExtiLine); +} +#endif /* DUAL_CORE */ + +/** + * @brief Disable ExtiLine Interrupt request for Lines in range 0 to 31 + * @rmtoll IMR1 IMx LL_EXTI_DisableIT_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableIT_0_31(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->IMR1, ExtiLine); +} + +#if defined(DUAL_CORE) +/** + * @brief Disable ExtiLine Interrupt request for Lines in range 0 to 31 for cpu2 + * @rmtoll C2IMR1 IMx LL_C2_EXTI_DisableIT_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @retval None + */ +__STATIC_INLINE void LL_C2_EXTI_DisableIT_0_31(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->C2IMR1, ExtiLine); +} +#endif /* DUAL_CORE */ + +/** + * @brief Disable ExtiLine Interrupt request for Lines in range 32 to 63 + * @rmtoll IMR2 IMx LL_EXTI_DisableIT_32_63 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_36 (*) + * @arg @ref LL_EXTI_LINE_37 (*) + * @arg @ref LL_EXTI_LINE_38 + * @arg @ref LL_EXTI_LINE_39 (*) + * @arg @ref LL_EXTI_LINE_40 (*) + * @arg @ref LL_EXTI_LINE_41 (*) + * @arg @ref LL_EXTI_LINE_42 + * @arg @ref LL_EXTI_LINE_43 + * @arg @ref LL_EXTI_LINE_44 + * @arg @ref LL_EXTI_LINE_45 + * @arg @ref LL_EXTI_LINE_46 + * @arg @ref LL_EXTI_LINE_ALL_32_63 + * (*) value not defined in all devices + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableIT_32_63(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->IMR2, ExtiLine); +} + +#if defined(DUAL_CORE) +/** + * @brief Disable ExtiLine Interrupt request for Lines in range 32 to 63 for cpu2 + * @rmtoll C2IMR2 IMx LL_C2_EXTI_DisableIT_32_63 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_36 (*) + * @arg @ref LL_EXTI_LINE_37 (*) + * @arg @ref LL_EXTI_LINE_38 + * @arg @ref LL_EXTI_LINE_39 (*) + * @arg @ref LL_EXTI_LINE_40 (*) + * @arg @ref LL_EXTI_LINE_41 (*) + * @arg @ref LL_EXTI_LINE_42 + * @arg @ref LL_EXTI_LINE_43 + * @arg @ref LL_EXTI_LINE_44 + * @arg @ref LL_EXTI_LINE_45 + * @arg @ref LL_EXTI_LINE_46 + * @arg @ref LL_EXTI_LINE_ALL_32_63 + * (*) value not defined in all devices + * @retval None + */ +__STATIC_INLINE void LL_C2_EXTI_DisableIT_32_63(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->C2IMR2, ExtiLine); +} +#endif /* DUAL_CORE */ + +/** + * @brief Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31 + * @rmtoll IMR1 IMx LL_EXTI_IsEnabledIT_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->IMR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); +} + +#if defined(DUAL_CORE) +/** + * @brief Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31 for cpu2 + * @rmtoll C2IMR1 IMx LL_C2_EXTI_IsEnabledIT_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C2_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->C2IMR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); +} +#endif /* DUAL_CORE */ + +/** + * @brief Indicate if ExtiLine Interrupt request is enabled for Lines in range 32 to 63 + * @rmtoll IMR2 IMx LL_EXTI_IsEnabledIT_32_63 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_36 (*) + * @arg @ref LL_EXTI_LINE_37 (*) + * @arg @ref LL_EXTI_LINE_38 + * @arg @ref LL_EXTI_LINE_39 (*) + * @arg @ref LL_EXTI_LINE_40 (*) + * @arg @ref LL_EXTI_LINE_41 (*) + * @arg @ref LL_EXTI_LINE_42 + * @arg @ref LL_EXTI_LINE_43 + * @arg @ref LL_EXTI_LINE_44 + * @arg @ref LL_EXTI_LINE_45 + * @arg @ref LL_EXTI_LINE_46 + * @arg @ref LL_EXTI_LINE_ALL_32_63 + * (*) value not defined in all devices + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_32_63(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->IMR2, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); +} + +#if defined(DUAL_CORE) +/** + * @brief Indicate if ExtiLine Interrupt request is enabled for Lines in range 32 to 63 for cpu2 + * @rmtoll C2IMR2 IMx LL_C2_EXTI_IsEnabledIT_32_63 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_36 (*) + * @arg @ref LL_EXTI_LINE_37 (*) + * @arg @ref LL_EXTI_LINE_38 + * @arg @ref LL_EXTI_LINE_39 (*) + * @arg @ref LL_EXTI_LINE_40 (*) + * @arg @ref LL_EXTI_LINE_41 (*) + * @arg @ref LL_EXTI_LINE_42 + * @arg @ref LL_EXTI_LINE_43 + * @arg @ref LL_EXTI_LINE_44 + * @arg @ref LL_EXTI_LINE_45 + * @arg @ref LL_EXTI_LINE_46 + * @arg @ref LL_EXTI_LINE_ALL_32_63 + * (*) value not defined in all devices + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C2_EXTI_IsEnabledIT_32_63(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->C2IMR2, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); +} +#endif /* DUAL_CORE */ + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Event_Management Event_Management + * @{ + */ + +/** + * @brief Enable ExtiLine Event request for Lines in range 0 to 31 + * @rmtoll EMR1 EMx LL_EXTI_EnableEvent_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableEvent_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->EMR1, ExtiLine); +} + +#if defined(DUAL_CORE) +/** + * @brief Enable ExtiLine Event request for Lines in range 0 to 31 for cpu2 + * @rmtoll C2EMR1 EMx LL_C2_EXTI_EnableEvent_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @retval None + */ +__STATIC_INLINE void LL_C2_EXTI_EnableEvent_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->C2EMR1, ExtiLine); +} +#endif /* DUAL_CORE */ + +/** + * @brief Enable ExtiLine Event request for Lines in range 32 to 63 + * @rmtoll EMR2 EMx LL_EXTI_EnableEvent_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_40 (*) + * @arg @ref LL_EXTI_LINE_41 (*) + * (*) value not defined in all devices + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableEvent_32_63(uint32_t ExtiLine) +{ + SET_BIT(EXTI->EMR2, ExtiLine); +} + +#if defined(DUAL_CORE) +/** + * @brief Enable ExtiLine Event request for Lines in range 32 to 63 for cpu2 + * @rmtoll C2EMR2 EMx LL_C2_EXTI_EnableEvent_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_40 (*) + * @arg @ref LL_EXTI_LINE_41 (*) + * (*) value not defined in all devices + * @retval None + */ +__STATIC_INLINE void LL_C2_EXTI_EnableEvent_32_63(uint32_t ExtiLine) +{ + SET_BIT(EXTI->C2EMR2, ExtiLine); +} +#endif /* DUAL_CORE */ + +/** + * @brief Disable ExtiLine Event request for Lines in range 0 to 31 + * @rmtoll EMR1 EMx LL_EXTI_DisableEvent_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableEvent_0_31(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->EMR1, ExtiLine); +} + +#if defined(DUAL_CORE) +/** + * @brief Disable ExtiLine Event request for Lines in range 0 to 31 for cpu2 + * @rmtoll C2EMR1 EMx LL_C2_EXTI_DisableEvent_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @retval None + */ +__STATIC_INLINE void LL_C2_EXTI_DisableEvent_0_31(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->C2EMR1, ExtiLine); +} +#endif /* DUAL_CORE */ + +/** + * @brief Disable ExtiLine Event request for Lines in range 32 to 63 + * @rmtoll EMR2 EMx LL_EXTI_DisableEvent_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_40 (*) + * @arg @ref LL_EXTI_LINE_41 (*) + * (*) value not defined in all devices + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableEvent_32_63(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->EMR2, ExtiLine); +} + +#if defined(DUAL_CORE) +/** + * @brief Disable ExtiLine Event request for Lines in range 32 to 63 for cpu2 + * @rmtoll C2EMR2 EMx LL_C2_EXTI_DisableEvent_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_40 (*) + * @arg @ref LL_EXTI_LINE_41 (*) + * (*) value not defined in all devices + * @retval None + */ +__STATIC_INLINE void LL_C2_EXTI_DisableEvent_32_63(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->C2EMR2, ExtiLine); +} +#endif /* DUAL_CORE */ + +/** + * @brief Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31 + * @rmtoll EMR1 EMx LL_EXTI_IsEnabledEvent_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_0_31(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->EMR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); +} + +#if defined(DUAL_CORE) +/** + * @brief Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31 for cpu2 + * @rmtoll C2EMR1 EMx LL_C2_EXTI_IsEnabledEvent_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C2_EXTI_IsEnabledEvent_0_31(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->C2EMR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); +} +#endif /* DUAL_CORE */ + +/** + * @brief Indicate if ExtiLine Event request is enabled for Lines in range 32 to 63 + * @rmtoll EMR2 EMx LL_EXTI_IsEnabledEvent_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_40 (*) + * @arg @ref LL_EXTI_LINE_41 (*) + * (*) value not defined in all devices + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_32_63(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->EMR2, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); +} + +#if defined(DUAL_CORE) +/** + * @brief Indicate if ExtiLine Event request is enabled for Lines in range 32 to 63 for cpu2 + * @rmtoll EMR2 EMx LL_C2_EXTI_IsEnabledEvent_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_40 (*) + * @arg @ref LL_EXTI_LINE_41 (*) + * (*) value not defined in all devices + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C2_EXTI_IsEnabledEvent_32_63(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->C2EMR2, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); +} +#endif /* DUAL_CORE */ + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Rising_Trigger_Management Rising_Trigger_Management + * @{ + */ + +/** + * @brief Enable ExtiLine Rising Edge Trigger for Lines in range 0 to 31 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a rising edge on a configurable interrupt + * line occurs during a write operation in the EXTI_RTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @rmtoll RTSR1 RTx LL_EXTI_EnableRisingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableRisingTrig_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->RTSR1, ExtiLine); + +} + +/** + * @brief Enable ExtiLine Rising Edge Trigger for Lines in range 32 to 63 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a rising edge on a configurable interrupt + * line occurs during a write operation in the EXTI_RTSR register, the + * pending bit is not set.Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @rmtoll RTSR2 RTx LL_EXTI_EnableRisingTrig_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_40 + * @arg @ref LL_EXTI_LINE_41 + * @arg @ref LL_EXTI_LINE_45 + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableRisingTrig_32_63(uint32_t ExtiLine) +{ + SET_BIT(EXTI->RTSR2, ExtiLine); +} + +/** + * @brief Disable ExtiLine Rising Edge Trigger for Lines in range 0 to 31 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a rising edge on a configurable interrupt + * line occurs during a write operation in the EXTI_RTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @rmtoll RTSR1 RTx LL_EXTI_DisableRisingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableRisingTrig_0_31(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->RTSR1, ExtiLine); + +} + +/** + * @brief Disable ExtiLine Rising Edge Trigger for Lines in range 32 to 63 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a rising edge on a configurable interrupt + * line occurs during a write operation in the EXTI_RTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @rmtoll RTSR2 RTx LL_EXTI_DisableRisingTrig_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_40 + * @arg @ref LL_EXTI_LINE_41 + * @arg @ref LL_EXTI_LINE_45 + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableRisingTrig_32_63(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->RTSR2, ExtiLine); +} + +/** + * @brief Check if rising edge trigger is enabled for Lines in range 0 to 31 + * @rmtoll RTSR1 RTx LL_EXTI_IsEnabledRisingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_0_31(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->RTSR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); +} + +/** + * @brief Check if rising edge trigger is enabled for Lines in range 32 to 63 + * @rmtoll RTSR2 RTx LL_EXTI_IsEnabledRisingTrig_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_40 + * @arg @ref LL_EXTI_LINE_41 + * @arg @ref LL_EXTI_LINE_45 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_32_63(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->RTSR2, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Falling_Trigger_Management Falling_Trigger_Management + * @{ + */ + +/** + * @brief Enable ExtiLine Falling Edge Trigger for Lines in range 0 to 31 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a falling edge on a configurable interrupt + * line occurs during a write operation in the EXTI_FTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @rmtoll FTSR1 FTx LL_EXTI_EnableFallingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableFallingTrig_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->FTSR1, ExtiLine); +} + +/** + * @brief Enable ExtiLine Falling Edge Trigger for Lines in range 32 to 63 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a Falling edge on a configurable interrupt + * line occurs during a write operation in the EXTI_FTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @rmtoll FTSR2 FTx LL_EXTI_EnableFallingTrig_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_40 + * @arg @ref LL_EXTI_LINE_41 + * @arg @ref LL_EXTI_LINE_45 + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableFallingTrig_32_63(uint32_t ExtiLine) +{ + SET_BIT(EXTI->FTSR2, ExtiLine); +} + +/** + * @brief Disable ExtiLine Falling Edge Trigger for Lines in range 0 to 31 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a Falling edge on a configurable interrupt + * line occurs during a write operation in the EXTI_FTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for the same interrupt line. + * In this case, both generate a trigger condition. + * @rmtoll FTSR1 FTx LL_EXTI_DisableFallingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableFallingTrig_0_31(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->FTSR1, ExtiLine); +} + +/** + * @brief Disable ExtiLine Falling Edge Trigger for Lines in range 32 to 63 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a Falling edge on a configurable interrupt + * line occurs during a write operation in the EXTI_FTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for the same interrupt line. + * In this case, both generate a trigger condition. + * @rmtoll FTSR2 FTx LL_EXTI_DisableFallingTrig_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_40 + * @arg @ref LL_EXTI_LINE_41 + * @arg @ref LL_EXTI_LINE_45 + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableFallingTrig_32_63(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->FTSR2, ExtiLine); +} + +/** + * @brief Check if falling edge trigger is enabled for Lines in range 0 to 31 + * @rmtoll FTSR1 FTx LL_EXTI_IsEnabledFallingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_0_31(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->FTSR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); +} + +/** + * @brief Check if falling edge trigger is enabled for Lines in range 32 to 63 + * @rmtoll FTSR2 FTx LL_EXTI_IsEnabledFallingTrig_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_40 + * @arg @ref LL_EXTI_LINE_41 + * @arg @ref LL_EXTI_LINE_45 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_32_63(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->FTSR2, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Software_Interrupt_Management Software_Interrupt_Management + * @{ + */ + +/** + * @brief Generate a software Interrupt Event for Lines in range 0 to 31 + * @note If the interrupt is enabled on this line in the EXTI_IMR1, writing a 1 to + * this bit when it is at '0' sets the corresponding pending bit in EXTI_PR1 + * resulting in an interrupt request generation. + * This bit is cleared by clearing the corresponding bit in the EXTI_PR1 + * register (by writing a 1 into the bit) + * @rmtoll SWIER1 SWIx LL_EXTI_GenerateSWI_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @retval None + */ +__STATIC_INLINE void LL_EXTI_GenerateSWI_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->SWIER1, ExtiLine); +} + +/** + * @brief Generate a software Interrupt Event for Lines in range 32 to 63 + * @note If the interrupt is enabled on this line in the EXTI_IMR2, writing a 1 to + * this bit when it is at '0' sets the corresponding pending bit in EXTI_PR2 + * resulting in an interrupt request generation. + * This bit is cleared by clearing the corresponding bit in the EXTI_PR2 + * register (by writing a 1 into the bit) + * @rmtoll SWIER2 SWIx LL_EXTI_GenerateSWI_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_40 + * @arg @ref LL_EXTI_LINE_41 + * @arg @ref LL_EXTI_LINE_45 + * @retval None + */ +__STATIC_INLINE void LL_EXTI_GenerateSWI_32_63(uint32_t ExtiLine) +{ + SET_BIT(EXTI->SWIER2, ExtiLine); +} + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Flag_Management Flag_Management + * @{ + */ + +/** + * @brief Check if the ExtLine Flag is set or not for Lines in range 0 to 31 + * @note This bit is set when the selected edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll PR1 PIFx LL_EXTI_IsActiveFlag_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_0_31(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->PR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); +} + +/** + * @brief Check if the ExtLine Flag is set or not for Lines in range 32 to 63 + * @note This bit is set when the selected edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll PR2 PIFx LL_EXTI_IsActiveFlag_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_40 + * @arg @ref LL_EXTI_LINE_41 + * @arg @ref LL_EXTI_LINE_45 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_32_63(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->PR2, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); +} + +/** + * @brief Read ExtLine Combination Flag for Lines in range 0 to 31 + * @note This bit is set when the selected edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll PR1 PIFx LL_EXTI_ReadFlag_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @retval @note This bit is set when the selected edge event arrives on the interrupt + */ +__STATIC_INLINE uint32_t LL_EXTI_ReadFlag_0_31(uint32_t ExtiLine) +{ + return (uint32_t)(READ_BIT(EXTI->PR1, ExtiLine)); +} + +/** + * @brief Read ExtLine Combination Flag for Lines in range 32 to 63 + * @note This bit is set when the selected edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll PR2 PIFx LL_EXTI_ReadFlag_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_40 + * @arg @ref LL_EXTI_LINE_41 + * @arg @ref LL_EXTI_LINE_45 + * @retval @note This bit is set when the selected edge event arrives on the interrupt + */ +__STATIC_INLINE uint32_t LL_EXTI_ReadFlag_32_63(uint32_t ExtiLine) +{ + return (uint32_t)(READ_BIT(EXTI->PR2, ExtiLine)); +} + +/** + * @brief Clear ExtLine Flags for Lines in range 0 to 31 + * @note This bit is set when the selected edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll PR1 PIFx LL_EXTI_ClearFlag_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @retval None + */ +__STATIC_INLINE void LL_EXTI_ClearFlag_0_31(uint32_t ExtiLine) +{ + WRITE_REG(EXTI->PR1, ExtiLine); +} + +/** + * @brief Clear ExtLine Flags for Lines in range 32 to 63 + * @note This bit is set when the selected edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll PR2 PIFx LL_EXTI_ClearFlag_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_40 + * @arg @ref LL_EXTI_LINE_41 + * @arg @ref LL_EXTI_LINE_45 + * @retval None + */ +__STATIC_INLINE void LL_EXTI_ClearFlag_32_63(uint32_t ExtiLine) +{ + WRITE_REG(EXTI->PR2, ExtiLine); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup EXTI_LL_EF_Init Initialization and de-initialization functions + * @{ + */ +ErrorStatus LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct); +ErrorStatus LL_EXTI_DeInit(void); +void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct); +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* EXTI */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32WLxx_LL_EXTI_H */ diff --git a/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_gpio.h b/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_gpio.h new file mode 100644 index 0000000..47e105f --- /dev/null +++ b/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_gpio.h @@ -0,0 +1,1035 @@ +/** + ****************************************************************************** + * @file stm32wlxx_ll_gpio.h + * @author MCD Application Team + * @brief Header file of GPIO LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32WLxx_LL_GPIO_H +#define STM32WLxx_LL_GPIO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wlxx.h" + +/** @addtogroup STM32WLxx_LL_Driver + * @{ + */ + +#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) ||defined (GPIOH) + +/** @defgroup GPIO_LL GPIO + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup GPIO_LL_Private_Macros GPIO Private Macros + * @{ + */ + +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup GPIO_LL_ES_INIT GPIO Exported Init structures + * @{ + */ + +/** + * @brief LL GPIO Init Structure definition + */ +typedef struct +{ + uint32_t Pin; /*!< Specifies the GPIO pins to be configured. + This parameter can be any value of @ref GPIO_LL_EC_PIN */ + + uint32_t Mode; /*!< Specifies the operating mode for the selected pins. + This parameter can be a value of @ref GPIO_LL_EC_MODE. + + GPIO HW configuration can be modified afterwards using + unitary function @ref LL_GPIO_SetPinMode().*/ + + uint32_t Speed; /*!< Specifies the speed for the selected pins. + This parameter can be a value of @ref GPIO_LL_EC_SPEED. + + GPIO HW configuration can be modified afterwards using + unitary function @ref LL_GPIO_SetPinSpeed().*/ + + uint32_t OutputType; /*!< Specifies the operating output type for the selected pins. + This parameter can be a value of @ref GPIO_LL_EC_OUTPUT. + + GPIO HW configuration can be modified afterwards using + unitary function @ref LL_GPIO_SetPinOutputType().*/ + + uint32_t Pull; /*!< Specifies the operating Pull-up/Pull down for the selected pins. + This parameter can be a value of @ref GPIO_LL_EC_PULL. + + GPIO HW configuration can be modified afterwards using + unitary function @ref LL_GPIO_SetPinPull().*/ + + uint32_t Alternate; /*!< Specifies the Peripheral to be connected to the selected pins. + This parameter can be a value of @ref GPIO_LL_EC_AF. + + GPIO HW configuration can be modified afterwards using + unitary function @ref LL_GPIO_SetAFPin_0_7() and LL_GPIO_SetAFPin_8_15().*/ +} LL_GPIO_InitTypeDef; + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup GPIO_LL_Exported_Constants GPIO Exported Constants + * @{ + */ + +/** @defgroup GPIO_LL_EC_PIN PIN + * @{ + */ +#define LL_GPIO_PIN_0 GPIO_BSRR_BS0 /*!< Select pin 0 */ +#define LL_GPIO_PIN_1 GPIO_BSRR_BS1 /*!< Select pin 1 */ +#define LL_GPIO_PIN_2 GPIO_BSRR_BS2 /*!< Select pin 2 */ +#define LL_GPIO_PIN_3 GPIO_BSRR_BS3 /*!< Select pin 3 */ +#define LL_GPIO_PIN_4 GPIO_BSRR_BS4 /*!< Select pin 4 */ +#define LL_GPIO_PIN_5 GPIO_BSRR_BS5 /*!< Select pin 5 */ +#define LL_GPIO_PIN_6 GPIO_BSRR_BS6 /*!< Select pin 6 */ +#define LL_GPIO_PIN_7 GPIO_BSRR_BS7 /*!< Select pin 7 */ +#define LL_GPIO_PIN_8 GPIO_BSRR_BS8 /*!< Select pin 8 */ +#define LL_GPIO_PIN_9 GPIO_BSRR_BS9 /*!< Select pin 9 */ +#define LL_GPIO_PIN_10 GPIO_BSRR_BS10 /*!< Select pin 10 */ +#define LL_GPIO_PIN_11 GPIO_BSRR_BS11 /*!< Select pin 11 */ +#define LL_GPIO_PIN_12 GPIO_BSRR_BS12 /*!< Select pin 12 */ +#define LL_GPIO_PIN_13 GPIO_BSRR_BS13 /*!< Select pin 13 */ +#define LL_GPIO_PIN_14 GPIO_BSRR_BS14 /*!< Select pin 14 */ +#define LL_GPIO_PIN_15 GPIO_BSRR_BS15 /*!< Select pin 15 */ +#define LL_GPIO_PIN_ALL (GPIO_BSRR_BS0 | GPIO_BSRR_BS1 | GPIO_BSRR_BS2 | \ + GPIO_BSRR_BS3 | GPIO_BSRR_BS4 | GPIO_BSRR_BS5 | \ + GPIO_BSRR_BS6 | GPIO_BSRR_BS7 | GPIO_BSRR_BS8 | \ + GPIO_BSRR_BS9 | GPIO_BSRR_BS10 | GPIO_BSRR_BS11 | \ + GPIO_BSRR_BS12 | GPIO_BSRR_BS13 | GPIO_BSRR_BS14 | \ + GPIO_BSRR_BS15) /*!< Select all pins */ +/** + * @} + */ + +/** @defgroup GPIO_LL_EC_MODE Mode + * @{ + */ +#define LL_GPIO_MODE_INPUT (0x00000000U) /*!< Select input mode */ +#define LL_GPIO_MODE_OUTPUT GPIO_MODER_MODE0_0 /*!< Select output mode */ +#define LL_GPIO_MODE_ALTERNATE GPIO_MODER_MODE0_1 /*!< Select alternate function mode */ +#define LL_GPIO_MODE_ANALOG GPIO_MODER_MODE0 /*!< Select analog mode */ +/** + * @} + */ + +/** @defgroup GPIO_LL_EC_OUTPUT Output Type + * @{ + */ +#define LL_GPIO_OUTPUT_PUSHPULL (0x00000000U) /*!< Select push-pull as output type */ +#define LL_GPIO_OUTPUT_OPENDRAIN GPIO_OTYPER_OT0 /*!< Select open-drain as output type */ +/** + * @} + */ + +/** @defgroup GPIO_LL_EC_SPEED Output Speed + * @{ + */ +#define LL_GPIO_SPEED_FREQ_LOW (0x00000000U) /*!< Select I/O low output speed */ +#define LL_GPIO_SPEED_FREQ_MEDIUM GPIO_OSPEEDR_OSPEED0_0 /*!< Select I/O medium output speed */ +#define LL_GPIO_SPEED_FREQ_HIGH GPIO_OSPEEDR_OSPEED0_1 /*!< Select I/O fast output speed */ +#define LL_GPIO_SPEED_FREQ_VERY_HIGH GPIO_OSPEEDR_OSPEED0 /*!< Select I/O high output speed */ +/** + * @} + */ + +/** @defgroup GPIO_LL_EC_PULL Pull Up Pull Down + * @{ + */ +#define LL_GPIO_PULL_NO (0x00000000U) /*!< Select I/O no pull */ +#define LL_GPIO_PULL_UP GPIO_PUPDR_PUPD0_0 /*!< Select I/O pull up */ +#define LL_GPIO_PULL_DOWN GPIO_PUPDR_PUPD0_1 /*!< Select I/O pull down */ +/** + * @} + */ + +/** @defgroup GPIO_LL_EC_AF Alternate Function + * @{ + */ +#define LL_GPIO_AF_0 (0x0000000U) /*!< Select alternate function 0 */ +#define LL_GPIO_AF_1 (0x0000001U) /*!< Select alternate function 1 */ +#define LL_GPIO_AF_2 (0x0000002U) /*!< Select alternate function 2 */ +#define LL_GPIO_AF_3 (0x0000003U) /*!< Select alternate function 3 */ +#define LL_GPIO_AF_4 (0x0000004U) /*!< Select alternate function 4 */ +#define LL_GPIO_AF_5 (0x0000005U) /*!< Select alternate function 5 */ +#define LL_GPIO_AF_6 (0x0000006U) /*!< Select alternate function 6 */ +#define LL_GPIO_AF_7 (0x0000007U) /*!< Select alternate function 7 */ +#define LL_GPIO_AF_8 (0x0000008U) /*!< Select alternate function 8 */ +#define LL_GPIO_AF_9 (0x0000009U) /*!< Select alternate function 9 */ +#define LL_GPIO_AF_10 (0x000000AU) /*!< Select alternate function 10 */ +#define LL_GPIO_AF_11 (0x000000BU) /*!< Select alternate function 11 */ +#define LL_GPIO_AF_12 (0x000000CU) /*!< Select alternate function 12 */ +#define LL_GPIO_AF_13 (0x000000DU) /*!< Select alternate function 13 */ +#define LL_GPIO_AF_14 (0x000000EU) /*!< Select alternate function 14 */ +#define LL_GPIO_AF_15 (0x000000FU) /*!< Select alternate function 15 */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup GPIO_LL_Exported_Macros GPIO Exported Macros + * @{ + */ + +/** @defgroup GPIO_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in GPIO register + * @param __INSTANCE__ GPIO Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_GPIO_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in GPIO register + * @param __INSTANCE__ GPIO Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_GPIO_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup GPIO_LL_Exported_Functions GPIO Exported Functions + * @{ + */ + +/** @defgroup GPIO_LL_EF_Port_Configuration Port Configuration + * @{ + */ + +/** + * @brief Configure gpio mode for a dedicated pin on dedicated port. + * @note I/O mode can be Input mode, General purpose output, Alternate function mode or Analog. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll MODER MODEy LL_GPIO_SetPinMode + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @param Mode This parameter can be one of the following values: + * @arg @ref LL_GPIO_MODE_INPUT + * @arg @ref LL_GPIO_MODE_OUTPUT + * @arg @ref LL_GPIO_MODE_ALTERNATE + * @arg @ref LL_GPIO_MODE_ANALOG + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode) +{ +#if defined(CORE_CM0PLUS) + MODIFY_REG(GPIOx->MODER, ((Pin * Pin) * GPIO_MODER_MODE0), ((Pin * Pin) * Mode)); +#else + MODIFY_REG(GPIOx->MODER, (GPIO_MODER_MODE0 << (POSITION_VAL(Pin) * 2U)), (Mode << (POSITION_VAL(Pin) * 2U))); +#endif /* CORE_CM0PLUS */ +} + +/** + * @brief Return gpio mode for a dedicated pin on dedicated port. + * @note I/O mode can be Input mode, General purpose output, Alternate function mode or Analog. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll MODER MODEy LL_GPIO_GetPinMode + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_MODE_INPUT + * @arg @ref LL_GPIO_MODE_OUTPUT + * @arg @ref LL_GPIO_MODE_ALTERNATE + * @arg @ref LL_GPIO_MODE_ANALOG + */ +__STATIC_INLINE uint32_t LL_GPIO_GetPinMode(const GPIO_TypeDef *GPIOx, uint32_t Pin) +{ +#if defined(CORE_CM0PLUS) + return (uint32_t)(READ_BIT(GPIOx->MODER, ((Pin * Pin) * GPIO_MODER_MODE0)) / (Pin * Pin)); +#else + return (uint32_t)(READ_BIT(GPIOx->MODER, + (GPIO_MODER_MODE0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U)); +#endif /* CORE_CM0PLUS */ +} + +/** + * @brief Configure gpio output type for several pins on dedicated port. + * @note Output type as to be set when gpio pin is in output or + * alternate modes. Possible type are Push-pull or Open-drain. + * @rmtoll OTYPER OTy LL_GPIO_SetPinOutputType + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @param OutputType This parameter can be one of the following values: + * @arg @ref LL_GPIO_OUTPUT_PUSHPULL + * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t PinMask, uint32_t OutputType) +{ + MODIFY_REG(GPIOx->OTYPER, PinMask, (PinMask * OutputType)); +} + +/** + * @brief Return gpio output type for several pins on dedicated port. + * @note Output type as to be set when gpio pin is in output or + * alternate modes. Possible type are Push-pull or Open-drain. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll OTYPER OTy LL_GPIO_GetPinOutputType + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_OUTPUT_PUSHPULL + * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN + */ +__STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType(const GPIO_TypeDef *GPIOx, uint32_t Pin) +{ +#if defined(CORE_CM0PLUS) + return (uint32_t)(READ_BIT(GPIOx->OTYPER, Pin) / Pin); +#else + return (uint32_t)(READ_BIT(GPIOx->OTYPER, Pin) >> POSITION_VAL(Pin)); +#endif /* CORE_CM0PLUS */ +} + +/** + * @brief Configure gpio speed for a dedicated pin on dedicated port. + * @note I/O speed can be Low, Medium, Fast or High speed. + * @note Warning: only one pin can be passed as parameter. + * @note Refer to datasheet for frequency specifications and the power + * supply and load conditions for each speed. + * @rmtoll OSPEEDR OSPEEDy LL_GPIO_SetPinSpeed + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @param Speed This parameter can be one of the following values: + * @arg @ref LL_GPIO_SPEED_FREQ_LOW + * @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM + * @arg @ref LL_GPIO_SPEED_FREQ_HIGH + * @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Speed) +{ +#if defined(CORE_CM0PLUS) + MODIFY_REG(GPIOx->OSPEEDR, ((Pin * Pin) * GPIO_OSPEEDR_OSPEED0), ((Pin * Pin) * Speed)); +#else + MODIFY_REG(GPIOx->OSPEEDR, (GPIO_OSPEEDR_OSPEED0 << (POSITION_VAL(Pin) * 2U)), + (Speed << (POSITION_VAL(Pin) * 2U))); +#endif /* CORE_CM0PLUS */ +} + +/** + * @brief Return gpio speed for a dedicated pin on dedicated port. + * @note I/O speed can be Low, Medium, Fast or High speed. + * @note Warning: only one pin can be passed as parameter. + * @note Refer to datasheet for frequency specifications and the power + * supply and load conditions for each speed. + * @rmtoll OSPEEDR OSPEEDy LL_GPIO_GetPinSpeed + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_SPEED_FREQ_LOW + * @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM + * @arg @ref LL_GPIO_SPEED_FREQ_HIGH + * @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH + */ +__STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(const GPIO_TypeDef *GPIOx, uint32_t Pin) +{ +#if defined(CORE_CM0PLUS) + return (uint32_t)(READ_BIT(GPIOx->OSPEEDR, ((Pin * Pin) * GPIO_OSPEEDR_OSPEED0)) / (Pin * Pin)); +#else + return (uint32_t)(READ_BIT(GPIOx->OSPEEDR, + (GPIO_OSPEEDR_OSPEED0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U)); +#endif /* CORE_CM0PLUS */ +} + +/** + * @brief Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll PUPDR PUPDy LL_GPIO_SetPinPull + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @param Pull This parameter can be one of the following values: + * @arg @ref LL_GPIO_PULL_NO + * @arg @ref LL_GPIO_PULL_UP + * @arg @ref LL_GPIO_PULL_DOWN + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Pull) +{ +#if defined(CORE_CM0PLUS) + MODIFY_REG(GPIOx->PUPDR, ((Pin * Pin) * GPIO_PUPDR_PUPD0), ((Pin * Pin) * Pull)); +#else + MODIFY_REG(GPIOx->PUPDR, (GPIO_PUPDR_PUPD0 << (POSITION_VAL(Pin) * 2U)), (Pull << (POSITION_VAL(Pin) * 2U))); +#endif /* CORE_CM0PLUS */ +} + +/** + * @brief Return gpio pull-up or pull-down for a dedicated pin on a dedicated port + * @note Warning: only one pin can be passed as parameter. + * @rmtoll PUPDR PUPDy LL_GPIO_GetPinPull + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_PULL_NO + * @arg @ref LL_GPIO_PULL_UP + * @arg @ref LL_GPIO_PULL_DOWN + */ +__STATIC_INLINE uint32_t LL_GPIO_GetPinPull(const GPIO_TypeDef *GPIOx, uint32_t Pin) +{ +#if defined(CORE_CM0PLUS) + return (uint32_t)(READ_BIT(GPIOx->PUPDR, ((Pin * Pin) * GPIO_PUPDR_PUPD0)) / (Pin * Pin)); +#else + return (uint32_t)(READ_BIT(GPIOx->PUPDR, + (GPIO_PUPDR_PUPD0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U)); +#endif /* CORE_CM0PLUS */ +} + +/** + * @brief Configure gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port. + * @note Possible values are from AF0 to AF15 depending on target. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll AFRL AFSELy LL_GPIO_SetAFPin_0_7 + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @param Alternate This parameter can be one of the following values: + * @arg @ref LL_GPIO_AF_0 + * @arg @ref LL_GPIO_AF_1 + * @arg @ref LL_GPIO_AF_2 + * @arg @ref LL_GPIO_AF_3 + * @arg @ref LL_GPIO_AF_4 + * @arg @ref LL_GPIO_AF_5 + * @arg @ref LL_GPIO_AF_6 + * @arg @ref LL_GPIO_AF_7 + * @arg @ref LL_GPIO_AF_8 + * @arg @ref LL_GPIO_AF_9 + * @arg @ref LL_GPIO_AF_10 + * @arg @ref LL_GPIO_AF_11 + * @arg @ref LL_GPIO_AF_12 + * @arg @ref LL_GPIO_AF_13 + * @arg @ref LL_GPIO_AF_14 + * @arg @ref LL_GPIO_AF_15 + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate) +{ +#if defined(CORE_CM0PLUS) + MODIFY_REG(GPIOx->AFR[0], ((((Pin * Pin) * Pin) * Pin) * GPIO_AFRL_AFSEL0), + ((((Pin * Pin) * Pin) * Pin) * Alternate)); +#else + MODIFY_REG(GPIOx->AFR[0], (GPIO_AFRL_AFSEL0 << (POSITION_VAL(Pin) * 4U)), + (Alternate << (POSITION_VAL(Pin) * 4U))); +#endif /* CORE_CM0PLUS */ +} + +/** + * @brief Return gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port. + * @rmtoll AFRL AFSELy LL_GPIO_GetAFPin_0_7 + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_AF_0 + * @arg @ref LL_GPIO_AF_1 + * @arg @ref LL_GPIO_AF_2 + * @arg @ref LL_GPIO_AF_3 + * @arg @ref LL_GPIO_AF_4 + * @arg @ref LL_GPIO_AF_5 + * @arg @ref LL_GPIO_AF_6 + * @arg @ref LL_GPIO_AF_7 + * @arg @ref LL_GPIO_AF_8 + * @arg @ref LL_GPIO_AF_9 + * @arg @ref LL_GPIO_AF_10 + * @arg @ref LL_GPIO_AF_11 + * @arg @ref LL_GPIO_AF_12 + * @arg @ref LL_GPIO_AF_13 + * @arg @ref LL_GPIO_AF_14 + * @arg @ref LL_GPIO_AF_15 + */ +__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_0_7(const GPIO_TypeDef *GPIOx, uint32_t Pin) +{ +#if defined(CORE_CM0PLUS) + return (uint32_t)(READ_BIT(GPIOx->AFR[0], + ((((Pin * Pin) * Pin) * Pin) * GPIO_AFRL_AFSEL0)) / (((Pin * Pin) * Pin) * Pin)); +#else + return (uint32_t)(READ_BIT(GPIOx->AFR[0], + (GPIO_AFRL_AFSEL0 << (POSITION_VAL(Pin) * 4U))) >> (POSITION_VAL(Pin) * 4U)); +#endif /* CORE_CM0PLUS */ +} + +/** + * @brief Configure gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port. + * @note Possible values are from AF0 to AF15 depending on target. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll AFRH AFSELy LL_GPIO_SetAFPin_8_15 + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @param Alternate This parameter can be one of the following values: + * @arg @ref LL_GPIO_AF_0 + * @arg @ref LL_GPIO_AF_1 + * @arg @ref LL_GPIO_AF_2 + * @arg @ref LL_GPIO_AF_3 + * @arg @ref LL_GPIO_AF_4 + * @arg @ref LL_GPIO_AF_5 + * @arg @ref LL_GPIO_AF_6 + * @arg @ref LL_GPIO_AF_7 + * @arg @ref LL_GPIO_AF_8 + * @arg @ref LL_GPIO_AF_9 + * @arg @ref LL_GPIO_AF_10 + * @arg @ref LL_GPIO_AF_11 + * @arg @ref LL_GPIO_AF_12 + * @arg @ref LL_GPIO_AF_13 + * @arg @ref LL_GPIO_AF_14 + * @arg @ref LL_GPIO_AF_15 + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate) +{ +#if defined(CORE_CM0PLUS) + MODIFY_REG(GPIOx->AFR[1], (((((Pin >> 8U) * (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)) * GPIO_AFRH_AFSEL8), + (((((Pin >> 8U) * (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)) * Alternate)); +#else + MODIFY_REG(GPIOx->AFR[1], (GPIO_AFRH_AFSEL8 << (POSITION_VAL(Pin >> 8U) * 4U)), + (Alternate << (POSITION_VAL(Pin >> 8U) * 4U))); +#endif /* CORE_CM0PLUS */ +} + +/** + * @brief Return gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port. + * @note Possible values are from AF0 to AF15 depending on target. + * @rmtoll AFRH AFSELy LL_GPIO_GetAFPin_8_15 + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_AF_0 + * @arg @ref LL_GPIO_AF_1 + * @arg @ref LL_GPIO_AF_2 + * @arg @ref LL_GPIO_AF_3 + * @arg @ref LL_GPIO_AF_4 + * @arg @ref LL_GPIO_AF_5 + * @arg @ref LL_GPIO_AF_6 + * @arg @ref LL_GPIO_AF_7 + * @arg @ref LL_GPIO_AF_8 + * @arg @ref LL_GPIO_AF_9 + * @arg @ref LL_GPIO_AF_10 + * @arg @ref LL_GPIO_AF_11 + * @arg @ref LL_GPIO_AF_12 + * @arg @ref LL_GPIO_AF_13 + * @arg @ref LL_GPIO_AF_14 + * @arg @ref LL_GPIO_AF_15 + */ +__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_8_15(const GPIO_TypeDef *GPIOx, uint32_t Pin) +{ +#if defined(CORE_CM0PLUS) + return (uint32_t)(READ_BIT(GPIOx->AFR[1], + (((((Pin >> 8U) * (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)) * GPIO_AFRH_AFSEL8)) / ((((Pin >> 8U) * + (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U))); +#else + return (uint32_t)(READ_BIT(GPIOx->AFR[1], + (GPIO_AFRH_AFSEL8 << (POSITION_VAL(Pin >> 8U) * 4U))) >> (POSITION_VAL(Pin >> 8U) * 4U)); +#endif /* CORE_CM0PLUS */ +} + + +/** + * @brief Lock configuration of several pins for a dedicated port. + * @note When the lock sequence has been applied on a port bit, the + * value of this port bit can no longer be modified until the + * next reset. + * @note Each lock bit freezes a specific configuration register + * (control and alternate function registers). + * @rmtoll LCKR LCKK LL_GPIO_LockPin + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void LL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + __IO uint32_t temp; + WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask); + WRITE_REG(GPIOx->LCKR, PinMask); + WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask); + /* Read LCKK register. This read is mandatory to complete key lock sequence */ + temp = READ_REG(GPIOx->LCKR); + (void) temp; +} + +/** + * @brief Return 1 if all pins passed as parameter, of a dedicated port, are locked. else Return 0. + * @rmtoll LCKR LCKy LL_GPIO_IsPinLocked + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_IsPinLocked(const GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + return ((READ_BIT(GPIOx->LCKR, PinMask) == (PinMask)) ? 1UL : 0UL); +} + +/** + * @brief Return 1 if one of the pin of a dedicated port is locked. else return 0. + * @rmtoll LCKR LCKK LL_GPIO_IsAnyPinLocked + * @param GPIOx GPIO Port + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked(const GPIO_TypeDef *GPIOx) +{ + return ((READ_BIT(GPIOx->LCKR, GPIO_LCKR_LCKK) == (GPIO_LCKR_LCKK)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup GPIO_LL_EF_Data_Access Data Access + * @{ + */ + +/** + * @brief Return full input data register value for a dedicated port. + * @rmtoll IDR IDy LL_GPIO_ReadInputPort + * @param GPIOx GPIO Port + * @retval Input data register value of port + */ +__STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(const GPIO_TypeDef *GPIOx) +{ + return (uint32_t)(READ_REG(GPIOx->IDR)); +} + +/** + * @brief Return if input data level for several pins of dedicated port is high or low. + * @rmtoll IDR IDy LL_GPIO_IsInputPinSet + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet(const GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + return ((READ_BIT(GPIOx->IDR, PinMask) == (PinMask)) ? 1UL : 0UL); +} + +/** + * @brief Write output data register for the port. + * @rmtoll ODR ODy LL_GPIO_WriteOutputPort + * @param GPIOx GPIO Port + * @param PortValue Level value for each pin of the port + * @retval None + */ +__STATIC_INLINE void LL_GPIO_WriteOutputPort(GPIO_TypeDef *GPIOx, uint32_t PortValue) +{ + WRITE_REG(GPIOx->ODR, PortValue); +} + +/** + * @brief Return full output data register value for a dedicated port. + * @rmtoll ODR ODy LL_GPIO_ReadOutputPort + * @param GPIOx GPIO Port + * @retval Output data register value of port + */ +__STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort(const GPIO_TypeDef *GPIOx) +{ + return (uint32_t)(READ_REG(GPIOx->ODR)); +} + +/** + * @brief Return if input data level for several pins of dedicated port is high or low. + * @rmtoll ODR ODy LL_GPIO_IsOutputPinSet + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_IsOutputPinSet(const GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + return ((READ_BIT(GPIOx->ODR, PinMask) == (PinMask)) ? 1UL : 0UL); +} + +/** + * @brief Set several pins to high level on dedicated gpio port. + * @rmtoll BSRR BSy LL_GPIO_SetOutputPin + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + WRITE_REG(GPIOx->BSRR, PinMask); +} + +/** + * @brief Set several pins to low level on dedicated gpio port. + * @rmtoll BRR BRy LL_GPIO_ResetOutputPin + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void LL_GPIO_ResetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + WRITE_REG(GPIOx->BRR, PinMask); +} + +/** + * @brief Toggle data value for several pin of dedicated port. + * @rmtoll ODR ODy LL_GPIO_TogglePin + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + uint32_t odr = READ_REG(GPIOx->ODR); + WRITE_REG(GPIOx->BSRR, ((odr & PinMask) << 16u) | (~odr & PinMask)); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup GPIO_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +ErrorStatus LL_GPIO_DeInit(const GPIO_TypeDef *GPIOx); +ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct); +void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct); + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOH) */ +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32WLxx_LL_GPIO_H */ diff --git a/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_lpuart.h b/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_lpuart.h new file mode 100644 index 0000000..c76640c --- /dev/null +++ b/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_lpuart.h @@ -0,0 +1,2662 @@ +/** + ****************************************************************************** + * @file stm32wlxx_ll_lpuart.h + * @author MCD Application Team + * @brief Header file of LPUART LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32WLxx_LL_LPUART_H +#define STM32WLxx_LL_LPUART_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wlxx.h" + +/** @addtogroup STM32WLxx_LL_Driver + * @{ + */ + +#if defined (LPUART1) + +/** @defgroup LPUART_LL LPUART + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @defgroup LPUART_LL_Private_Variables LPUART Private Variables + * @{ + */ +/* Array used to get the LPUART prescaler division decimal values versus @ref LPUART_LL_EC_PRESCALER values */ +static const uint16_t LPUART_PRESCALER_TAB[] = +{ + (uint16_t)1, + (uint16_t)2, + (uint16_t)4, + (uint16_t)6, + (uint16_t)8, + (uint16_t)10, + (uint16_t)12, + (uint16_t)16, + (uint16_t)32, + (uint16_t)64, + (uint16_t)128, + (uint16_t)256, + (uint16_t)256, + (uint16_t)256, + (uint16_t)256, + (uint16_t)256 +}; +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup LPUART_LL_Private_Constants LPUART Private Constants + * @{ + */ +/* Defines used in Baud Rate related macros and corresponding register setting computation */ +#define LPUART_LPUARTDIV_FREQ_MUL 256U +#define LPUART_BRR_MASK 0x000FFFFFU +#define LPUART_BRR_MIN_VALUE 0x00000300U +/** + * @} + */ + + +/* Private macros ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup LPUART_LL_Private_Macros LPUART Private Macros + * @{ + */ +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup LPUART_LL_ES_INIT LPUART Exported Init structures + * @{ + */ + +/** + * @brief LL LPUART Init Structure definition + */ +typedef struct +{ + uint32_t PrescalerValue; /*!< Specifies the Prescaler to compute the communication baud rate. + This parameter can be a value of @ref LPUART_LL_EC_PRESCALER. + + This feature can be modified afterwards using unitary + function @ref LL_LPUART_SetPrescaler().*/ + + uint32_t BaudRate; /*!< This field defines expected LPUART communication baud rate. + + This feature can be modified afterwards using unitary + function @ref LL_LPUART_SetBaudRate().*/ + + uint32_t DataWidth; /*!< Specifies the number of data bits transmitted or received in a frame. + This parameter can be a value of @ref LPUART_LL_EC_DATAWIDTH. + + This feature can be modified afterwards using unitary + function @ref LL_LPUART_SetDataWidth().*/ + + uint32_t StopBits; /*!< Specifies the number of stop bits transmitted. + This parameter can be a value of @ref LPUART_LL_EC_STOPBITS. + + This feature can be modified afterwards using unitary + function @ref LL_LPUART_SetStopBitsLength().*/ + + uint32_t Parity; /*!< Specifies the parity mode. + This parameter can be a value of @ref LPUART_LL_EC_PARITY. + + This feature can be modified afterwards using unitary + function @ref LL_LPUART_SetParity().*/ + + uint32_t TransferDirection; /*!< Specifies whether the Receive and/or Transmit mode is enabled or disabled. + This parameter can be a value of @ref LPUART_LL_EC_DIRECTION. + + This feature can be modified afterwards using unitary + function @ref LL_LPUART_SetTransferDirection().*/ + + uint32_t HardwareFlowControl; /*!< Specifies whether the hardware flow control mode is enabled or disabled. + This parameter can be a value of @ref LPUART_LL_EC_HWCONTROL. + + This feature can be modified afterwards using unitary + function @ref LL_LPUART_SetHWFlowCtrl().*/ + +} LL_LPUART_InitTypeDef; + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup LPUART_LL_Exported_Constants LPUART Exported Constants + * @{ + */ + +/** @defgroup LPUART_LL_EC_CLEAR_FLAG Clear Flags Defines + * @brief Flags defines which can be used with LL_LPUART_WriteReg function + * @{ + */ +#define LL_LPUART_ICR_PECF USART_ICR_PECF /*!< Parity error clear flag */ +#define LL_LPUART_ICR_FECF USART_ICR_FECF /*!< Framing error clear flag */ +#define LL_LPUART_ICR_NCF USART_ICR_NECF /*!< Noise error detected clear flag */ +#define LL_LPUART_ICR_ORECF USART_ICR_ORECF /*!< Overrun error clear flag */ +#define LL_LPUART_ICR_IDLECF USART_ICR_IDLECF /*!< Idle line detected clear flag */ +#define LL_LPUART_ICR_TCCF USART_ICR_TCCF /*!< Transmission complete clear flag */ +#define LL_LPUART_ICR_CTSCF USART_ICR_CTSCF /*!< CTS clear flag */ +#define LL_LPUART_ICR_CMCF USART_ICR_CMCF /*!< Character match clear flag */ +#define LL_LPUART_ICR_WUCF USART_ICR_WUCF /*!< Wakeup from Stop mode clear flag */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_LPUART_ReadReg function + * @{ + */ +#define LL_LPUART_ISR_PE USART_ISR_PE /*!< Parity error flag */ +#define LL_LPUART_ISR_FE USART_ISR_FE /*!< Framing error flag */ +#define LL_LPUART_ISR_NE USART_ISR_NE /*!< Noise detected flag */ +#define LL_LPUART_ISR_ORE USART_ISR_ORE /*!< Overrun error flag */ +#define LL_LPUART_ISR_IDLE USART_ISR_IDLE /*!< Idle line detected flag */ +#define LL_LPUART_ISR_RXNE_RXFNE USART_ISR_RXNE_RXFNE /*!< Read data register or RX FIFO not empty flag */ +#define LL_LPUART_ISR_TC USART_ISR_TC /*!< Transmission complete flag */ +#define LL_LPUART_ISR_TXE_TXFNF USART_ISR_TXE_TXFNF /*!< Transmit data register empty or TX FIFO Not Full flag*/ +#define LL_LPUART_ISR_CTSIF USART_ISR_CTSIF /*!< CTS interrupt flag */ +#define LL_LPUART_ISR_CTS USART_ISR_CTS /*!< CTS flag */ +#define LL_LPUART_ISR_BUSY USART_ISR_BUSY /*!< Busy flag */ +#define LL_LPUART_ISR_CMF USART_ISR_CMF /*!< Character match flag */ +#define LL_LPUART_ISR_SBKF USART_ISR_SBKF /*!< Send break flag */ +#define LL_LPUART_ISR_RWU USART_ISR_RWU /*!< Receiver wakeup from Mute mode flag */ +#define LL_LPUART_ISR_WUF USART_ISR_WUF /*!< Wakeup from Stop mode flag */ +#define LL_LPUART_ISR_TEACK USART_ISR_TEACK /*!< Transmit enable acknowledge flag */ +#define LL_LPUART_ISR_REACK USART_ISR_REACK /*!< Receive enable acknowledge flag */ +#define LL_LPUART_ISR_TXFE USART_ISR_TXFE /*!< TX FIFO empty flag */ +#define LL_LPUART_ISR_RXFF USART_ISR_RXFF /*!< RX FIFO full flag */ +#define LL_LPUART_ISR_RXFT USART_ISR_RXFT /*!< RX FIFO threshold flag */ +#define LL_LPUART_ISR_TXFT USART_ISR_TXFT /*!< TX FIFO threshold flag */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_LPUART_ReadReg and LL_LPUART_WriteReg functions + * @{ + */ +#define LL_LPUART_CR1_IDLEIE USART_CR1_IDLEIE /*!< IDLE interrupt enable */ +#define LL_LPUART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_RXFNEIE /*!< Read data register and RXFIFO not empty + interrupt enable */ +#define LL_LPUART_CR1_TCIE USART_CR1_TCIE /*!< Transmission complete interrupt enable */ +#define LL_LPUART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_TXFNFIE /*!< Transmit data register empty and TX FIFO + not full interrupt enable */ +#define LL_LPUART_CR1_PEIE USART_CR1_PEIE /*!< Parity error */ +#define LL_LPUART_CR1_CMIE USART_CR1_CMIE /*!< Character match interrupt enable */ +#define LL_LPUART_CR1_TXFEIE USART_CR1_TXFEIE /*!< TX FIFO empty interrupt enable */ +#define LL_LPUART_CR1_RXFFIE USART_CR1_RXFFIE /*!< RX FIFO full interrupt enable */ +#define LL_LPUART_CR3_EIE USART_CR3_EIE /*!< Error interrupt enable */ +#define LL_LPUART_CR3_CTSIE USART_CR3_CTSIE /*!< CTS interrupt enable */ +#define LL_LPUART_CR3_WUFIE USART_CR3_WUFIE /*!< Wakeup from Stop mode interrupt enable */ +#define LL_LPUART_CR3_TXFTIE USART_CR3_TXFTIE /*!< TX FIFO threshold interrupt enable */ +#define LL_LPUART_CR3_RXFTIE USART_CR3_RXFTIE /*!< RX FIFO threshold interrupt enable */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_FIFOTHRESHOLD FIFO Threshold + * @{ + */ +#define LL_LPUART_FIFOTHRESHOLD_1_8 0x00000000U /*!< FIFO reaches 1/8 of its depth */ +#define LL_LPUART_FIFOTHRESHOLD_1_4 0x00000001U /*!< FIFO reaches 1/4 of its depth */ +#define LL_LPUART_FIFOTHRESHOLD_1_2 0x00000002U /*!< FIFO reaches 1/2 of its depth */ +#define LL_LPUART_FIFOTHRESHOLD_3_4 0x00000003U /*!< FIFO reaches 3/4 of its depth */ +#define LL_LPUART_FIFOTHRESHOLD_7_8 0x00000004U /*!< FIFO reaches 7/8 of its depth */ +#define LL_LPUART_FIFOTHRESHOLD_8_8 0x00000005U /*!< FIFO becomes empty for TX and full for RX */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_DIRECTION Direction + * @{ + */ +#define LL_LPUART_DIRECTION_NONE 0x00000000U /*!< Transmitter and Receiver are disabled */ +#define LL_LPUART_DIRECTION_RX USART_CR1_RE /*!< Transmitter is disabled and Receiver is enabled */ +#define LL_LPUART_DIRECTION_TX USART_CR1_TE /*!< Transmitter is enabled and Receiver is disabled */ +#define LL_LPUART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< Transmitter and Receiver are enabled */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_PARITY Parity Control + * @{ + */ +#define LL_LPUART_PARITY_NONE 0x00000000U /*!< Parity control disabled */ +#define LL_LPUART_PARITY_EVEN USART_CR1_PCE /*!< Parity control enabled and Even Parity is selected */ +#define LL_LPUART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Parity control enabled and Odd Parity is selected */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_WAKEUP Wakeup + * @{ + */ +#define LL_LPUART_WAKEUP_IDLELINE 0x00000000U /*!< LPUART wake up from Mute mode on Idle Line */ +#define LL_LPUART_WAKEUP_ADDRESSMARK USART_CR1_WAKE /*!< LPUART wake up from Mute mode on Address Mark */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_DATAWIDTH Datawidth + * @{ + */ +#define LL_LPUART_DATAWIDTH_7B USART_CR1_M1 /*!< 7 bits word length : Start bit, 7 data bits, n stop bits */ +#define LL_LPUART_DATAWIDTH_8B 0x00000000U /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */ +#define LL_LPUART_DATAWIDTH_9B USART_CR1_M0 /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_PRESCALER Clock Source Prescaler + * @{ + */ +#define LL_LPUART_PRESCALER_DIV1 0x00000000U /*!< Input clock not divided */ +#define LL_LPUART_PRESCALER_DIV2 (USART_PRESC_PRESCALER_0) /*!< Input clock divided by 2 */ +#define LL_LPUART_PRESCALER_DIV4 (USART_PRESC_PRESCALER_1) /*!< Input clock divided by 4 */ +#define LL_LPUART_PRESCALER_DIV6 (USART_PRESC_PRESCALER_1 |\ + USART_PRESC_PRESCALER_0) /*!< Input clock divided by 6 */ +#define LL_LPUART_PRESCALER_DIV8 (USART_PRESC_PRESCALER_2) /*!< Input clock divided by 8 */ +#define LL_LPUART_PRESCALER_DIV10 (USART_PRESC_PRESCALER_2 |\ + USART_PRESC_PRESCALER_0) /*!< Input clock divided by 10 */ +#define LL_LPUART_PRESCALER_DIV12 (USART_PRESC_PRESCALER_2 |\ + USART_PRESC_PRESCALER_1) /*!< Input clock divided by 12 */ +#define LL_LPUART_PRESCALER_DIV16 (USART_PRESC_PRESCALER_2 |\ + USART_PRESC_PRESCALER_1 |\ + USART_PRESC_PRESCALER_0) /*!< Input clock divided by 16 */ +#define LL_LPUART_PRESCALER_DIV32 (USART_PRESC_PRESCALER_3) /*!< Input clock divided by 32 */ +#define LL_LPUART_PRESCALER_DIV64 (USART_PRESC_PRESCALER_3 |\ + USART_PRESC_PRESCALER_0) /*!< Input clock divided by 64 */ +#define LL_LPUART_PRESCALER_DIV128 (USART_PRESC_PRESCALER_3 |\ + USART_PRESC_PRESCALER_1) /*!< Input clock divided by 128 */ +#define LL_LPUART_PRESCALER_DIV256 (USART_PRESC_PRESCALER_3 |\ + USART_PRESC_PRESCALER_1 |\ + USART_PRESC_PRESCALER_0) /*!< Input clock divided by 256 */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_STOPBITS Stop Bits + * @{ + */ +#define LL_LPUART_STOPBITS_1 0x00000000U /*!< 1 stop bit */ +#define LL_LPUART_STOPBITS_2 USART_CR2_STOP_1 /*!< 2 stop bits */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_TXRX TX RX Pins Swap + * @{ + */ +#define LL_LPUART_TXRX_STANDARD 0x00000000U /*!< TX/RX pins are used as defined in standard pinout */ +#define LL_LPUART_TXRX_SWAPPED (USART_CR2_SWAP) /*!< TX and RX pins functions are swapped. */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_RXPIN_LEVEL RX Pin Active Level Inversion + * @{ + */ +#define LL_LPUART_RXPIN_LEVEL_STANDARD 0x00000000U /*!< RX pin signal works using the standard logic levels */ +#define LL_LPUART_RXPIN_LEVEL_INVERTED (USART_CR2_RXINV) /*!< RX pin signal values are inverted. */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_TXPIN_LEVEL TX Pin Active Level Inversion + * @{ + */ +#define LL_LPUART_TXPIN_LEVEL_STANDARD 0x00000000U /*!< TX pin signal works using the standard logic levels */ +#define LL_LPUART_TXPIN_LEVEL_INVERTED (USART_CR2_TXINV) /*!< TX pin signal values are inverted. */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_BINARY_LOGIC Binary Data Inversion + * @{ + */ +#define LL_LPUART_BINARY_LOGIC_POSITIVE 0x00000000U /*!< Logical data from the data register are send/received + in positive/direct logic. (1=H, 0=L) */ +#define LL_LPUART_BINARY_LOGIC_NEGATIVE USART_CR2_DATAINV /*!< Logical data from the data register are send/received + in negative/inverse logic. (1=L, 0=H). + The parity bit is also inverted. */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_BITORDER Bit Order + * @{ + */ +#define LL_LPUART_BITORDER_LSBFIRST 0x00000000U /*!< data is transmitted/received with data bit 0 first, + following the start bit */ +#define LL_LPUART_BITORDER_MSBFIRST USART_CR2_MSBFIRST /*!< data is transmitted/received with the MSB first, + following the start bit */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_ADDRESS_DETECT Address Length Detection + * @{ + */ +#define LL_LPUART_ADDRESS_DETECT_4B 0x00000000U /*!< 4-bit address detection method selected */ +#define LL_LPUART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit address detection (in 8-bit data mode) method selected */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_HWCONTROL Hardware Control + * @{ + */ +#define LL_LPUART_HWCONTROL_NONE 0x00000000U /*!< CTS and RTS hardware flow control disabled */ +#define LL_LPUART_HWCONTROL_RTS USART_CR3_RTSE /*!< RTS output enabled, data is only requested + when there is space in the receive buffer */ +#define LL_LPUART_HWCONTROL_CTS USART_CR3_CTSE /*!< CTS mode enabled, data is only transmitted + when the nCTS input is asserted (tied to 0)*/ +#define LL_LPUART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) /*!< CTS and RTS hardware flow control enabled */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_WAKEUP_ON Wakeup Activation + * @{ + */ +#define LL_LPUART_WAKEUP_ON_ADDRESS 0x00000000U /*!< Wake up active on address match */ +#define LL_LPUART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1 /*!< Wake up active on Start bit detection */ +#define LL_LPUART_WAKEUP_ON_RXNE (USART_CR3_WUS_0 | USART_CR3_WUS_1) /*!< Wake up active on RXNE */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_DE_POLARITY Driver Enable Polarity + * @{ + */ +#define LL_LPUART_DE_POLARITY_HIGH 0x00000000U /*!< DE signal is active high */ +#define LL_LPUART_DE_POLARITY_LOW USART_CR3_DEP /*!< DE signal is active low */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_DMA_REG_DATA DMA Register Data + * @{ + */ +#define LL_LPUART_DMA_REG_DATA_TRANSMIT 0x00000000U /*!< Get address of data register used for transmission */ +#define LL_LPUART_DMA_REG_DATA_RECEIVE 0x00000001U /*!< Get address of data register used for reception */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup LPUART_LL_Exported_Macros LPUART Exported Macros + * @{ + */ + +/** @defgroup LPUART_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in LPUART register + * @param __INSTANCE__ LPUART Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_LPUART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in LPUART register + * @param __INSTANCE__ LPUART Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_LPUART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** @defgroup LPUART_LL_EM_Exported_Macros_Helper Helper Macros + * @{ + */ + +/** + * @brief Compute LPUARTDIV value according to Peripheral Clock and + * expected Baud Rate (20-bit value of LPUARTDIV is returned) + * @param __PERIPHCLK__ Peripheral Clock frequency used for LPUART Instance + * @param __PRESCALER__ This parameter can be one of the following values: + * @arg @ref LL_LPUART_PRESCALER_DIV1 + * @arg @ref LL_LPUART_PRESCALER_DIV2 + * @arg @ref LL_LPUART_PRESCALER_DIV4 + * @arg @ref LL_LPUART_PRESCALER_DIV6 + * @arg @ref LL_LPUART_PRESCALER_DIV8 + * @arg @ref LL_LPUART_PRESCALER_DIV10 + * @arg @ref LL_LPUART_PRESCALER_DIV12 + * @arg @ref LL_LPUART_PRESCALER_DIV16 + * @arg @ref LL_LPUART_PRESCALER_DIV32 + * @arg @ref LL_LPUART_PRESCALER_DIV64 + * @arg @ref LL_LPUART_PRESCALER_DIV128 + * @arg @ref LL_LPUART_PRESCALER_DIV256 + * @param __BAUDRATE__ Baud Rate value to achieve + * @retval LPUARTDIV value to be used for BRR register filling + */ +#define __LL_LPUART_DIV(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) (uint32_t)\ + ((((((uint64_t)(__PERIPHCLK__)/(uint64_t)(LPUART_PRESCALER_TAB[(uint16_t)(__PRESCALER__)]))\ + * LPUART_LPUARTDIV_FREQ_MUL) + (uint32_t)((__BAUDRATE__)/2U))/(__BAUDRATE__)) & LPUART_BRR_MASK) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup LPUART_LL_Exported_Functions LPUART Exported Functions + * @{ + */ + +/** @defgroup LPUART_LL_EF_Configuration Configuration functions + * @{ + */ + +/** + * @brief LPUART Enable + * @rmtoll CR1 UE LL_LPUART_Enable + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_Enable(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->CR1, USART_CR1_UE); +} + +/** + * @brief LPUART Disable + * @note When LPUART is disabled, LPUART prescalers and outputs are stopped immediately, + * and current operations are discarded. The configuration of the LPUART is kept, but all the status + * flags, in the LPUARTx_ISR are set to their default values. + * @note In order to go into low-power mode without generating errors on the line, + * the TE bit must be reset before and the software must wait + * for the TC bit in the LPUART_ISR to be set before resetting the UE bit. + * The DMA requests are also reset when UE = 0 so the DMA channel must + * be disabled before resetting the UE bit. + * @rmtoll CR1 UE LL_LPUART_Disable + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_Disable(USART_TypeDef *LPUARTx) +{ + CLEAR_BIT(LPUARTx->CR1, USART_CR1_UE); +} + +/** + * @brief Indicate if LPUART is enabled + * @rmtoll CR1 UE LL_LPUART_IsEnabled + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabled(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)) ? 1UL : 0UL); +} + +/** + * @brief FIFO Mode Enable + * @rmtoll CR1 FIFOEN LL_LPUART_EnableFIFO + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableFIFO(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->CR1, USART_CR1_FIFOEN); +} + +/** + * @brief FIFO Mode Disable + * @rmtoll CR1 FIFOEN LL_LPUART_DisableFIFO + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableFIFO(USART_TypeDef *LPUARTx) +{ + CLEAR_BIT(LPUARTx->CR1, USART_CR1_FIFOEN); +} + +/** + * @brief Indicate if FIFO Mode is enabled + * @rmtoll CR1 FIFOEN LL_LPUART_IsEnabledFIFO + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledFIFO(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR1, USART_CR1_FIFOEN) == (USART_CR1_FIFOEN)) ? 1UL : 0UL); +} + +/** + * @brief Configure TX FIFO Threshold + * @rmtoll CR3 TXFTCFG LL_LPUART_SetTXFIFOThreshold + * @param LPUARTx LPUART Instance + * @param Threshold This parameter can be one of the following values: + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8 + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetTXFIFOThreshold(USART_TypeDef *LPUARTx, uint32_t Threshold) +{ + ATOMIC_MODIFY_REG(LPUARTx->CR3, USART_CR3_TXFTCFG, Threshold << USART_CR3_TXFTCFG_Pos); +} + +/** + * @brief Return TX FIFO Threshold Configuration + * @rmtoll CR3 TXFTCFG LL_LPUART_GetTXFIFOThreshold + * @param LPUARTx LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8 + */ +__STATIC_INLINE uint32_t LL_LPUART_GetTXFIFOThreshold(const USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos); +} + +/** + * @brief Configure RX FIFO Threshold + * @rmtoll CR3 RXFTCFG LL_LPUART_SetRXFIFOThreshold + * @param LPUARTx LPUART Instance + * @param Threshold This parameter can be one of the following values: + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8 + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetRXFIFOThreshold(USART_TypeDef *LPUARTx, uint32_t Threshold) +{ + ATOMIC_MODIFY_REG(LPUARTx->CR3, USART_CR3_RXFTCFG, Threshold << USART_CR3_RXFTCFG_Pos); +} + +/** + * @brief Return RX FIFO Threshold Configuration + * @rmtoll CR3 RXFTCFG LL_LPUART_GetRXFIFOThreshold + * @param LPUARTx LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8 + */ +__STATIC_INLINE uint32_t LL_LPUART_GetRXFIFOThreshold(const USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos); +} + +/** + * @brief Configure TX and RX FIFOs Threshold + * @rmtoll CR3 TXFTCFG LL_LPUART_ConfigFIFOsThreshold\n + * CR3 RXFTCFG LL_LPUART_ConfigFIFOsThreshold + * @param LPUARTx LPUART Instance + * @param TXThreshold This parameter can be one of the following values: + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8 + * @param RXThreshold This parameter can be one of the following values: + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8 + * @retval None + */ +__STATIC_INLINE void LL_LPUART_ConfigFIFOsThreshold(USART_TypeDef *LPUARTx, uint32_t TXThreshold, uint32_t RXThreshold) +{ + ATOMIC_MODIFY_REG(LPUARTx->CR3, USART_CR3_TXFTCFG | USART_CR3_RXFTCFG, (TXThreshold << USART_CR3_TXFTCFG_Pos) | \ + (RXThreshold << USART_CR3_RXFTCFG_Pos)); +} + +/** + * @brief LPUART enabled in STOP Mode + * @note When this function is enabled, LPUART is able to wake up the MCU from Stop mode, provided that + * LPUART clock selection is HSI or LSE in RCC. + * @rmtoll CR1 UESM LL_LPUART_EnableInStopMode + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableInStopMode(USART_TypeDef *LPUARTx) +{ + ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_UESM); +} + +/** + * @brief LPUART disabled in STOP Mode + * @note When this function is disabled, LPUART is not able to wake up the MCU from Stop mode + * @rmtoll CR1 UESM LL_LPUART_DisableInStopMode + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableInStopMode(USART_TypeDef *LPUARTx) +{ + ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_UESM); +} + +/** + * @brief Indicate if LPUART is enabled in STOP Mode + * (able to wake up MCU from Stop mode or not) + * @rmtoll CR1 UESM LL_LPUART_IsEnabledInStopMode + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledInStopMode(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM)) ? 1UL : 0UL); +} + +/** + * @brief Receiver Enable (Receiver is enabled and begins searching for a start bit) + * @rmtoll CR1 RE LL_LPUART_EnableDirectionRx + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableDirectionRx(USART_TypeDef *LPUARTx) +{ + ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_RE); +} + +/** + * @brief Receiver Disable + * @rmtoll CR1 RE LL_LPUART_DisableDirectionRx + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableDirectionRx(USART_TypeDef *LPUARTx) +{ + ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_RE); +} + +/** + * @brief Transmitter Enable + * @rmtoll CR1 TE LL_LPUART_EnableDirectionTx + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableDirectionTx(USART_TypeDef *LPUARTx) +{ + ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TE); +} + +/** + * @brief Transmitter Disable + * @rmtoll CR1 TE LL_LPUART_DisableDirectionTx + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableDirectionTx(USART_TypeDef *LPUARTx) +{ + ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TE); +} + +/** + * @brief Configure simultaneously enabled/disabled states + * of Transmitter and Receiver + * @rmtoll CR1 RE LL_LPUART_SetTransferDirection\n + * CR1 TE LL_LPUART_SetTransferDirection + * @param LPUARTx LPUART Instance + * @param TransferDirection This parameter can be one of the following values: + * @arg @ref LL_LPUART_DIRECTION_NONE + * @arg @ref LL_LPUART_DIRECTION_RX + * @arg @ref LL_LPUART_DIRECTION_TX + * @arg @ref LL_LPUART_DIRECTION_TX_RX + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetTransferDirection(USART_TypeDef *LPUARTx, uint32_t TransferDirection) +{ + ATOMIC_MODIFY_REG(LPUARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection); +} + +/** + * @brief Return enabled/disabled states of Transmitter and Receiver + * @rmtoll CR1 RE LL_LPUART_GetTransferDirection\n + * CR1 TE LL_LPUART_GetTransferDirection + * @param LPUARTx LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_DIRECTION_NONE + * @arg @ref LL_LPUART_DIRECTION_RX + * @arg @ref LL_LPUART_DIRECTION_TX + * @arg @ref LL_LPUART_DIRECTION_TX_RX + */ +__STATIC_INLINE uint32_t LL_LPUART_GetTransferDirection(const USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_RE | USART_CR1_TE)); +} + +/** + * @brief Configure Parity (enabled/disabled and parity mode if enabled) + * @note This function selects if hardware parity control (generation and detection) is enabled or disabled. + * When the parity control is enabled (Odd or Even), computed parity bit is inserted at the MSB position + * (depending on data width) and parity is checked on the received data. + * @rmtoll CR1 PS LL_LPUART_SetParity\n + * CR1 PCE LL_LPUART_SetParity + * @param LPUARTx LPUART Instance + * @param Parity This parameter can be one of the following values: + * @arg @ref LL_LPUART_PARITY_NONE + * @arg @ref LL_LPUART_PARITY_EVEN + * @arg @ref LL_LPUART_PARITY_ODD + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetParity(USART_TypeDef *LPUARTx, uint32_t Parity) +{ + MODIFY_REG(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE, Parity); +} + +/** + * @brief Return Parity configuration (enabled/disabled and parity mode if enabled) + * @rmtoll CR1 PS LL_LPUART_GetParity\n + * CR1 PCE LL_LPUART_GetParity + * @param LPUARTx LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_PARITY_NONE + * @arg @ref LL_LPUART_PARITY_EVEN + * @arg @ref LL_LPUART_PARITY_ODD + */ +__STATIC_INLINE uint32_t LL_LPUART_GetParity(const USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE)); +} + +/** + * @brief Set Receiver Wake Up method from Mute mode. + * @rmtoll CR1 WAKE LL_LPUART_SetWakeUpMethod + * @param LPUARTx LPUART Instance + * @param Method This parameter can be one of the following values: + * @arg @ref LL_LPUART_WAKEUP_IDLELINE + * @arg @ref LL_LPUART_WAKEUP_ADDRESSMARK + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetWakeUpMethod(USART_TypeDef *LPUARTx, uint32_t Method) +{ + MODIFY_REG(LPUARTx->CR1, USART_CR1_WAKE, Method); +} + +/** + * @brief Return Receiver Wake Up method from Mute mode + * @rmtoll CR1 WAKE LL_LPUART_GetWakeUpMethod + * @param LPUARTx LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_WAKEUP_IDLELINE + * @arg @ref LL_LPUART_WAKEUP_ADDRESSMARK + */ +__STATIC_INLINE uint32_t LL_LPUART_GetWakeUpMethod(const USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_WAKE)); +} + +/** + * @brief Set Word length (nb of data bits, excluding start and stop bits) + * @rmtoll CR1 M LL_LPUART_SetDataWidth + * @param LPUARTx LPUART Instance + * @param DataWidth This parameter can be one of the following values: + * @arg @ref LL_LPUART_DATAWIDTH_7B + * @arg @ref LL_LPUART_DATAWIDTH_8B + * @arg @ref LL_LPUART_DATAWIDTH_9B + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetDataWidth(USART_TypeDef *LPUARTx, uint32_t DataWidth) +{ + MODIFY_REG(LPUARTx->CR1, USART_CR1_M, DataWidth); +} + +/** + * @brief Return Word length (i.e. nb of data bits, excluding start and stop bits) + * @rmtoll CR1 M LL_LPUART_GetDataWidth + * @param LPUARTx LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_DATAWIDTH_7B + * @arg @ref LL_LPUART_DATAWIDTH_8B + * @arg @ref LL_LPUART_DATAWIDTH_9B + */ +__STATIC_INLINE uint32_t LL_LPUART_GetDataWidth(const USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_M)); +} + +/** + * @brief Allow switch between Mute Mode and Active mode + * @rmtoll CR1 MME LL_LPUART_EnableMuteMode + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableMuteMode(USART_TypeDef *LPUARTx) +{ + ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_MME); +} + +/** + * @brief Prevent Mute Mode use. Set Receiver in active mode permanently. + * @rmtoll CR1 MME LL_LPUART_DisableMuteMode + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableMuteMode(USART_TypeDef *LPUARTx) +{ + ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_MME); +} + +/** + * @brief Indicate if switch between Mute Mode and Active mode is allowed + * @rmtoll CR1 MME LL_LPUART_IsEnabledMuteMode + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledMuteMode(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR1, USART_CR1_MME) == (USART_CR1_MME)) ? 1UL : 0UL); +} + +/** + * @brief Configure Clock source prescaler for baudrate generator and oversampling + * @rmtoll PRESC PRESCALER LL_LPUART_SetPrescaler + * @param LPUARTx LPUART Instance + * @param PrescalerValue This parameter can be one of the following values: + * @arg @ref LL_LPUART_PRESCALER_DIV1 + * @arg @ref LL_LPUART_PRESCALER_DIV2 + * @arg @ref LL_LPUART_PRESCALER_DIV4 + * @arg @ref LL_LPUART_PRESCALER_DIV6 + * @arg @ref LL_LPUART_PRESCALER_DIV8 + * @arg @ref LL_LPUART_PRESCALER_DIV10 + * @arg @ref LL_LPUART_PRESCALER_DIV12 + * @arg @ref LL_LPUART_PRESCALER_DIV16 + * @arg @ref LL_LPUART_PRESCALER_DIV32 + * @arg @ref LL_LPUART_PRESCALER_DIV64 + * @arg @ref LL_LPUART_PRESCALER_DIV128 + * @arg @ref LL_LPUART_PRESCALER_DIV256 + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetPrescaler(USART_TypeDef *LPUARTx, uint32_t PrescalerValue) +{ + MODIFY_REG(LPUARTx->PRESC, USART_PRESC_PRESCALER, (uint16_t)PrescalerValue); +} + +/** + * @brief Retrieve the Clock source prescaler for baudrate generator and oversampling + * @rmtoll PRESC PRESCALER LL_LPUART_GetPrescaler + * @param LPUARTx LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_PRESCALER_DIV1 + * @arg @ref LL_LPUART_PRESCALER_DIV2 + * @arg @ref LL_LPUART_PRESCALER_DIV4 + * @arg @ref LL_LPUART_PRESCALER_DIV6 + * @arg @ref LL_LPUART_PRESCALER_DIV8 + * @arg @ref LL_LPUART_PRESCALER_DIV10 + * @arg @ref LL_LPUART_PRESCALER_DIV12 + * @arg @ref LL_LPUART_PRESCALER_DIV16 + * @arg @ref LL_LPUART_PRESCALER_DIV32 + * @arg @ref LL_LPUART_PRESCALER_DIV64 + * @arg @ref LL_LPUART_PRESCALER_DIV128 + * @arg @ref LL_LPUART_PRESCALER_DIV256 + */ +__STATIC_INLINE uint32_t LL_LPUART_GetPrescaler(const USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->PRESC, USART_PRESC_PRESCALER)); +} + +/** + * @brief Set the length of the stop bits + * @rmtoll CR2 STOP LL_LPUART_SetStopBitsLength + * @param LPUARTx LPUART Instance + * @param StopBits This parameter can be one of the following values: + * @arg @ref LL_LPUART_STOPBITS_1 + * @arg @ref LL_LPUART_STOPBITS_2 + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetStopBitsLength(USART_TypeDef *LPUARTx, uint32_t StopBits) +{ + MODIFY_REG(LPUARTx->CR2, USART_CR2_STOP, StopBits); +} + +/** + * @brief Retrieve the length of the stop bits + * @rmtoll CR2 STOP LL_LPUART_GetStopBitsLength + * @param LPUARTx LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_STOPBITS_1 + * @arg @ref LL_LPUART_STOPBITS_2 + */ +__STATIC_INLINE uint32_t LL_LPUART_GetStopBitsLength(const USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_STOP)); +} + +/** + * @brief Configure Character frame format (Datawidth, Parity control, Stop Bits) + * @note Call of this function is equivalent to following function call sequence : + * - Data Width configuration using @ref LL_LPUART_SetDataWidth() function + * - Parity Control and mode configuration using @ref LL_LPUART_SetParity() function + * - Stop bits configuration using @ref LL_LPUART_SetStopBitsLength() function + * @rmtoll CR1 PS LL_LPUART_ConfigCharacter\n + * CR1 PCE LL_LPUART_ConfigCharacter\n + * CR1 M LL_LPUART_ConfigCharacter\n + * CR2 STOP LL_LPUART_ConfigCharacter + * @param LPUARTx LPUART Instance + * @param DataWidth This parameter can be one of the following values: + * @arg @ref LL_LPUART_DATAWIDTH_7B + * @arg @ref LL_LPUART_DATAWIDTH_8B + * @arg @ref LL_LPUART_DATAWIDTH_9B + * @param Parity This parameter can be one of the following values: + * @arg @ref LL_LPUART_PARITY_NONE + * @arg @ref LL_LPUART_PARITY_EVEN + * @arg @ref LL_LPUART_PARITY_ODD + * @param StopBits This parameter can be one of the following values: + * @arg @ref LL_LPUART_STOPBITS_1 + * @arg @ref LL_LPUART_STOPBITS_2 + * @retval None + */ +__STATIC_INLINE void LL_LPUART_ConfigCharacter(USART_TypeDef *LPUARTx, uint32_t DataWidth, uint32_t Parity, + uint32_t StopBits) +{ + MODIFY_REG(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE | USART_CR1_M, Parity | DataWidth); + MODIFY_REG(LPUARTx->CR2, USART_CR2_STOP, StopBits); +} + +/** + * @brief Configure TX/RX pins swapping setting. + * @rmtoll CR2 SWAP LL_LPUART_SetTXRXSwap + * @param LPUARTx LPUART Instance + * @param SwapConfig This parameter can be one of the following values: + * @arg @ref LL_LPUART_TXRX_STANDARD + * @arg @ref LL_LPUART_TXRX_SWAPPED + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetTXRXSwap(USART_TypeDef *LPUARTx, uint32_t SwapConfig) +{ + MODIFY_REG(LPUARTx->CR2, USART_CR2_SWAP, SwapConfig); +} + +/** + * @brief Retrieve TX/RX pins swapping configuration. + * @rmtoll CR2 SWAP LL_LPUART_GetTXRXSwap + * @param LPUARTx LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_TXRX_STANDARD + * @arg @ref LL_LPUART_TXRX_SWAPPED + */ +__STATIC_INLINE uint32_t LL_LPUART_GetTXRXSwap(const USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_SWAP)); +} + +/** + * @brief Configure RX pin active level logic + * @rmtoll CR2 RXINV LL_LPUART_SetRXPinLevel + * @param LPUARTx LPUART Instance + * @param PinInvMethod This parameter can be one of the following values: + * @arg @ref LL_LPUART_RXPIN_LEVEL_STANDARD + * @arg @ref LL_LPUART_RXPIN_LEVEL_INVERTED + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetRXPinLevel(USART_TypeDef *LPUARTx, uint32_t PinInvMethod) +{ + MODIFY_REG(LPUARTx->CR2, USART_CR2_RXINV, PinInvMethod); +} + +/** + * @brief Retrieve RX pin active level logic configuration + * @rmtoll CR2 RXINV LL_LPUART_GetRXPinLevel + * @param LPUARTx LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_RXPIN_LEVEL_STANDARD + * @arg @ref LL_LPUART_RXPIN_LEVEL_INVERTED + */ +__STATIC_INLINE uint32_t LL_LPUART_GetRXPinLevel(const USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_RXINV)); +} + +/** + * @brief Configure TX pin active level logic + * @rmtoll CR2 TXINV LL_LPUART_SetTXPinLevel + * @param LPUARTx LPUART Instance + * @param PinInvMethod This parameter can be one of the following values: + * @arg @ref LL_LPUART_TXPIN_LEVEL_STANDARD + * @arg @ref LL_LPUART_TXPIN_LEVEL_INVERTED + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetTXPinLevel(USART_TypeDef *LPUARTx, uint32_t PinInvMethod) +{ + MODIFY_REG(LPUARTx->CR2, USART_CR2_TXINV, PinInvMethod); +} + +/** + * @brief Retrieve TX pin active level logic configuration + * @rmtoll CR2 TXINV LL_LPUART_GetTXPinLevel + * @param LPUARTx LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_TXPIN_LEVEL_STANDARD + * @arg @ref LL_LPUART_TXPIN_LEVEL_INVERTED + */ +__STATIC_INLINE uint32_t LL_LPUART_GetTXPinLevel(const USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_TXINV)); +} + +/** + * @brief Configure Binary data logic. + * + * @note Allow to define how Logical data from the data register are send/received : + * either in positive/direct logic (1=H, 0=L) or in negative/inverse logic (1=L, 0=H) + * @rmtoll CR2 DATAINV LL_LPUART_SetBinaryDataLogic + * @param LPUARTx LPUART Instance + * @param DataLogic This parameter can be one of the following values: + * @arg @ref LL_LPUART_BINARY_LOGIC_POSITIVE + * @arg @ref LL_LPUART_BINARY_LOGIC_NEGATIVE + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetBinaryDataLogic(USART_TypeDef *LPUARTx, uint32_t DataLogic) +{ + MODIFY_REG(LPUARTx->CR2, USART_CR2_DATAINV, DataLogic); +} + +/** + * @brief Retrieve Binary data configuration + * @rmtoll CR2 DATAINV LL_LPUART_GetBinaryDataLogic + * @param LPUARTx LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_BINARY_LOGIC_POSITIVE + * @arg @ref LL_LPUART_BINARY_LOGIC_NEGATIVE + */ +__STATIC_INLINE uint32_t LL_LPUART_GetBinaryDataLogic(const USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_DATAINV)); +} + +/** + * @brief Configure transfer bit order (either Less or Most Significant Bit First) + * @note MSB First means data is transmitted/received with the MSB first, following the start bit. + * LSB First means data is transmitted/received with data bit 0 first, following the start bit. + * @rmtoll CR2 MSBFIRST LL_LPUART_SetTransferBitOrder + * @param LPUARTx LPUART Instance + * @param BitOrder This parameter can be one of the following values: + * @arg @ref LL_LPUART_BITORDER_LSBFIRST + * @arg @ref LL_LPUART_BITORDER_MSBFIRST + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetTransferBitOrder(USART_TypeDef *LPUARTx, uint32_t BitOrder) +{ + MODIFY_REG(LPUARTx->CR2, USART_CR2_MSBFIRST, BitOrder); +} + +/** + * @brief Return transfer bit order (either Less or Most Significant Bit First) + * @note MSB First means data is transmitted/received with the MSB first, following the start bit. + * LSB First means data is transmitted/received with data bit 0 first, following the start bit. + * @rmtoll CR2 MSBFIRST LL_LPUART_GetTransferBitOrder + * @param LPUARTx LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_BITORDER_LSBFIRST + * @arg @ref LL_LPUART_BITORDER_MSBFIRST + */ +__STATIC_INLINE uint32_t LL_LPUART_GetTransferBitOrder(const USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_MSBFIRST)); +} + +/** + * @brief Set Address of the LPUART node. + * @note This is used in multiprocessor communication during Mute mode or Stop mode, + * for wake up with address mark detection. + * @note 4bits address node is used when 4-bit Address Detection is selected in ADDM7. + * (b7-b4 should be set to 0) + * 8bits address node is used when 7-bit Address Detection is selected in ADDM7. + * (This is used in multiprocessor communication during Mute mode or Stop mode, + * for wake up with 7-bit address mark detection. + * The MSB of the character sent by the transmitter should be equal to 1. + * It may also be used for character detection during normal reception, + * Mute mode inactive (for example, end of block detection in ModBus protocol). + * In this case, the whole received character (8-bit) is compared to the ADD[7:0] + * value and CMF flag is set on match) + * @rmtoll CR2 ADD LL_LPUART_ConfigNodeAddress\n + * CR2 ADDM7 LL_LPUART_ConfigNodeAddress + * @param LPUARTx LPUART Instance + * @param AddressLen This parameter can be one of the following values: + * @arg @ref LL_LPUART_ADDRESS_DETECT_4B + * @arg @ref LL_LPUART_ADDRESS_DETECT_7B + * @param NodeAddress 4 or 7 bit Address of the LPUART node. + * @retval None + */ +__STATIC_INLINE void LL_LPUART_ConfigNodeAddress(USART_TypeDef *LPUARTx, uint32_t AddressLen, uint32_t NodeAddress) +{ + MODIFY_REG(LPUARTx->CR2, USART_CR2_ADD | USART_CR2_ADDM7, + (uint32_t)(AddressLen | (NodeAddress << USART_CR2_ADD_Pos))); +} + +/** + * @brief Return 8 bit Address of the LPUART node as set in ADD field of CR2. + * @note If 4-bit Address Detection is selected in ADDM7, + * only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant) + * If 7-bit Address Detection is selected in ADDM7, + * only 8bits (b7-b0) of returned value are relevant (b31-b8 are not relevant) + * @rmtoll CR2 ADD LL_LPUART_GetNodeAddress + * @param LPUARTx LPUART Instance + * @retval Address of the LPUART node (Value between Min_Data=0 and Max_Data=255) + */ +__STATIC_INLINE uint32_t LL_LPUART_GetNodeAddress(const USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_ADD) >> USART_CR2_ADD_Pos); +} + +/** + * @brief Return Length of Node Address used in Address Detection mode (7-bit or 4-bit) + * @rmtoll CR2 ADDM7 LL_LPUART_GetNodeAddressLen + * @param LPUARTx LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_ADDRESS_DETECT_4B + * @arg @ref LL_LPUART_ADDRESS_DETECT_7B + */ +__STATIC_INLINE uint32_t LL_LPUART_GetNodeAddressLen(const USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_ADDM7)); +} + +/** + * @brief Enable RTS HW Flow Control + * @rmtoll CR3 RTSE LL_LPUART_EnableRTSHWFlowCtrl + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableRTSHWFlowCtrl(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->CR3, USART_CR3_RTSE); +} + +/** + * @brief Disable RTS HW Flow Control + * @rmtoll CR3 RTSE LL_LPUART_DisableRTSHWFlowCtrl + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableRTSHWFlowCtrl(USART_TypeDef *LPUARTx) +{ + CLEAR_BIT(LPUARTx->CR3, USART_CR3_RTSE); +} + +/** + * @brief Enable CTS HW Flow Control + * @rmtoll CR3 CTSE LL_LPUART_EnableCTSHWFlowCtrl + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableCTSHWFlowCtrl(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->CR3, USART_CR3_CTSE); +} + +/** + * @brief Disable CTS HW Flow Control + * @rmtoll CR3 CTSE LL_LPUART_DisableCTSHWFlowCtrl + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableCTSHWFlowCtrl(USART_TypeDef *LPUARTx) +{ + CLEAR_BIT(LPUARTx->CR3, USART_CR3_CTSE); +} + +/** + * @brief Configure HW Flow Control mode (both CTS and RTS) + * @rmtoll CR3 RTSE LL_LPUART_SetHWFlowCtrl\n + * CR3 CTSE LL_LPUART_SetHWFlowCtrl + * @param LPUARTx LPUART Instance + * @param HardwareFlowControl This parameter can be one of the following values: + * @arg @ref LL_LPUART_HWCONTROL_NONE + * @arg @ref LL_LPUART_HWCONTROL_RTS + * @arg @ref LL_LPUART_HWCONTROL_CTS + * @arg @ref LL_LPUART_HWCONTROL_RTS_CTS + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetHWFlowCtrl(USART_TypeDef *LPUARTx, uint32_t HardwareFlowControl) +{ + MODIFY_REG(LPUARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE, HardwareFlowControl); +} + +/** + * @brief Return HW Flow Control configuration (both CTS and RTS) + * @rmtoll CR3 RTSE LL_LPUART_GetHWFlowCtrl\n + * CR3 CTSE LL_LPUART_GetHWFlowCtrl + * @param LPUARTx LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_HWCONTROL_NONE + * @arg @ref LL_LPUART_HWCONTROL_RTS + * @arg @ref LL_LPUART_HWCONTROL_CTS + * @arg @ref LL_LPUART_HWCONTROL_RTS_CTS + */ +__STATIC_INLINE uint32_t LL_LPUART_GetHWFlowCtrl(const USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE)); +} + +/** + * @brief Enable Overrun detection + * @rmtoll CR3 OVRDIS LL_LPUART_EnableOverrunDetect + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableOverrunDetect(USART_TypeDef *LPUARTx) +{ + CLEAR_BIT(LPUARTx->CR3, USART_CR3_OVRDIS); +} + +/** + * @brief Disable Overrun detection + * @rmtoll CR3 OVRDIS LL_LPUART_DisableOverrunDetect + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableOverrunDetect(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->CR3, USART_CR3_OVRDIS); +} + +/** + * @brief Indicate if Overrun detection is enabled + * @rmtoll CR3 OVRDIS LL_LPUART_IsEnabledOverrunDetect + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledOverrunDetect(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS) ? 1UL : 0UL); +} + +/** + * @brief Select event type for Wake UP Interrupt Flag (WUS[1:0] bits) + * @rmtoll CR3 WUS LL_LPUART_SetWKUPType + * @param LPUARTx LPUART Instance + * @param Type This parameter can be one of the following values: + * @arg @ref LL_LPUART_WAKEUP_ON_ADDRESS + * @arg @ref LL_LPUART_WAKEUP_ON_STARTBIT + * @arg @ref LL_LPUART_WAKEUP_ON_RXNE + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetWKUPType(USART_TypeDef *LPUARTx, uint32_t Type) +{ + MODIFY_REG(LPUARTx->CR3, USART_CR3_WUS, Type); +} + +/** + * @brief Return event type for Wake UP Interrupt Flag (WUS[1:0] bits) + * @rmtoll CR3 WUS LL_LPUART_GetWKUPType + * @param LPUARTx LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_WAKEUP_ON_ADDRESS + * @arg @ref LL_LPUART_WAKEUP_ON_STARTBIT + * @arg @ref LL_LPUART_WAKEUP_ON_RXNE + */ +__STATIC_INLINE uint32_t LL_LPUART_GetWKUPType(const USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_WUS)); +} + +/** + * @brief Configure LPUART BRR register for achieving expected Baud Rate value. + * + * @note Compute and set LPUARTDIV value in BRR Register (full BRR content) + * according to used Peripheral Clock and expected Baud Rate values + * @note Peripheral clock and Baud Rate values provided as function parameters should be valid + * (Baud rate value != 0). + * @note Provided that LPUARTx_BRR must be > = 0x300 and LPUART_BRR is 20-bit, + * a care should be taken when generating high baud rates using high PeriphClk + * values. PeriphClk must be in the range [3 x BaudRate, 4096 x BaudRate]. + * @rmtoll BRR BRR LL_LPUART_SetBaudRate + * @param LPUARTx LPUART Instance + * @param PeriphClk Peripheral Clock + * @param PrescalerValue This parameter can be one of the following values: + * @arg @ref LL_LPUART_PRESCALER_DIV1 + * @arg @ref LL_LPUART_PRESCALER_DIV2 + * @arg @ref LL_LPUART_PRESCALER_DIV4 + * @arg @ref LL_LPUART_PRESCALER_DIV6 + * @arg @ref LL_LPUART_PRESCALER_DIV8 + * @arg @ref LL_LPUART_PRESCALER_DIV10 + * @arg @ref LL_LPUART_PRESCALER_DIV12 + * @arg @ref LL_LPUART_PRESCALER_DIV16 + * @arg @ref LL_LPUART_PRESCALER_DIV32 + * @arg @ref LL_LPUART_PRESCALER_DIV64 + * @arg @ref LL_LPUART_PRESCALER_DIV128 + * @arg @ref LL_LPUART_PRESCALER_DIV256 + * @param BaudRate Baud Rate + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetBaudRate(USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t PrescalerValue, + uint32_t BaudRate) +{ + if (BaudRate != 0U) + { + LPUARTx->BRR = __LL_LPUART_DIV(PeriphClk, PrescalerValue, BaudRate); + } +} + +/** + * @brief Return current Baud Rate value, according to LPUARTDIV present in BRR register + * (full BRR content), and to used Peripheral Clock values + * @note In case of non-initialized or invalid value stored in BRR register, value 0 will be returned. + * @rmtoll BRR BRR LL_LPUART_GetBaudRate + * @param LPUARTx LPUART Instance + * @param PeriphClk Peripheral Clock + * @param PrescalerValue This parameter can be one of the following values: + * @arg @ref LL_LPUART_PRESCALER_DIV1 + * @arg @ref LL_LPUART_PRESCALER_DIV2 + * @arg @ref LL_LPUART_PRESCALER_DIV4 + * @arg @ref LL_LPUART_PRESCALER_DIV6 + * @arg @ref LL_LPUART_PRESCALER_DIV8 + * @arg @ref LL_LPUART_PRESCALER_DIV10 + * @arg @ref LL_LPUART_PRESCALER_DIV12 + * @arg @ref LL_LPUART_PRESCALER_DIV16 + * @arg @ref LL_LPUART_PRESCALER_DIV32 + * @arg @ref LL_LPUART_PRESCALER_DIV64 + * @arg @ref LL_LPUART_PRESCALER_DIV128 + * @arg @ref LL_LPUART_PRESCALER_DIV256 + * @retval Baud Rate + */ +__STATIC_INLINE uint32_t LL_LPUART_GetBaudRate(const USART_TypeDef *LPUARTx, uint32_t PeriphClk, + uint32_t PrescalerValue) +{ + uint32_t lpuartdiv; + uint32_t brrresult; + uint32_t periphclkpresc = (uint32_t)(PeriphClk / (LPUART_PRESCALER_TAB[(uint16_t)PrescalerValue])); + + lpuartdiv = LPUARTx->BRR & LPUART_BRR_MASK; + + if (lpuartdiv >= LPUART_BRR_MIN_VALUE) + { + brrresult = (uint32_t)(((uint64_t)(periphclkpresc) * LPUART_LPUARTDIV_FREQ_MUL) / lpuartdiv); + } + else + { + brrresult = 0x0UL; + } + + return (brrresult); +} + +/** + * @} + */ + +/** @defgroup LPUART_LL_EF_Configuration_HalfDuplex Configuration functions related to Half Duplex feature + * @{ + */ + +/** + * @brief Enable Single Wire Half-Duplex mode + * @rmtoll CR3 HDSEL LL_LPUART_EnableHalfDuplex + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableHalfDuplex(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->CR3, USART_CR3_HDSEL); +} + +/** + * @brief Disable Single Wire Half-Duplex mode + * @rmtoll CR3 HDSEL LL_LPUART_DisableHalfDuplex + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableHalfDuplex(USART_TypeDef *LPUARTx) +{ + CLEAR_BIT(LPUARTx->CR3, USART_CR3_HDSEL); +} + +/** + * @brief Indicate if Single Wire Half-Duplex mode is enabled + * @rmtoll CR3 HDSEL LL_LPUART_IsEnabledHalfDuplex + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledHalfDuplex(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup LPUART_LL_EF_Configuration_DE Configuration functions related to Driver Enable feature + * @{ + */ + +/** + * @brief Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits). + * @rmtoll CR1 DEDT LL_LPUART_SetDEDeassertionTime + * @param LPUARTx LPUART Instance + * @param Time Value between Min_Data=0 and Max_Data=31 + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetDEDeassertionTime(USART_TypeDef *LPUARTx, uint32_t Time) +{ + MODIFY_REG(LPUARTx->CR1, USART_CR1_DEDT, Time << USART_CR1_DEDT_Pos); +} + +/** + * @brief Return DEDT (Driver Enable De-Assertion Time) + * @rmtoll CR1 DEDT LL_LPUART_GetDEDeassertionTime + * @param LPUARTx LPUART Instance + * @retval Time value expressed on 5 bits ([4:0] bits) : c + */ +__STATIC_INLINE uint32_t LL_LPUART_GetDEDeassertionTime(const USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_DEDT) >> USART_CR1_DEDT_Pos); +} + +/** + * @brief Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits). + * @rmtoll CR1 DEAT LL_LPUART_SetDEAssertionTime + * @param LPUARTx LPUART Instance + * @param Time Value between Min_Data=0 and Max_Data=31 + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetDEAssertionTime(USART_TypeDef *LPUARTx, uint32_t Time) +{ + MODIFY_REG(LPUARTx->CR1, USART_CR1_DEAT, Time << USART_CR1_DEAT_Pos); +} + +/** + * @brief Return DEAT (Driver Enable Assertion Time) + * @rmtoll CR1 DEAT LL_LPUART_GetDEAssertionTime + * @param LPUARTx LPUART Instance + * @retval Time value expressed on 5 bits ([4:0] bits) : Time Value between Min_Data=0 and Max_Data=31 + */ +__STATIC_INLINE uint32_t LL_LPUART_GetDEAssertionTime(const USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_DEAT) >> USART_CR1_DEAT_Pos); +} + +/** + * @brief Enable Driver Enable (DE) Mode + * @rmtoll CR3 DEM LL_LPUART_EnableDEMode + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableDEMode(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->CR3, USART_CR3_DEM); +} + +/** + * @brief Disable Driver Enable (DE) Mode + * @rmtoll CR3 DEM LL_LPUART_DisableDEMode + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableDEMode(USART_TypeDef *LPUARTx) +{ + CLEAR_BIT(LPUARTx->CR3, USART_CR3_DEM); +} + +/** + * @brief Indicate if Driver Enable (DE) Mode is enabled + * @rmtoll CR3 DEM LL_LPUART_IsEnabledDEMode + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDEMode(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR3, USART_CR3_DEM) == (USART_CR3_DEM)) ? 1UL : 0UL); +} + +/** + * @brief Select Driver Enable Polarity + * @rmtoll CR3 DEP LL_LPUART_SetDESignalPolarity + * @param LPUARTx LPUART Instance + * @param Polarity This parameter can be one of the following values: + * @arg @ref LL_LPUART_DE_POLARITY_HIGH + * @arg @ref LL_LPUART_DE_POLARITY_LOW + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetDESignalPolarity(USART_TypeDef *LPUARTx, uint32_t Polarity) +{ + MODIFY_REG(LPUARTx->CR3, USART_CR3_DEP, Polarity); +} + +/** + * @brief Return Driver Enable Polarity + * @rmtoll CR3 DEP LL_LPUART_GetDESignalPolarity + * @param LPUARTx LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_DE_POLARITY_HIGH + * @arg @ref LL_LPUART_DE_POLARITY_LOW + */ +__STATIC_INLINE uint32_t LL_LPUART_GetDESignalPolarity(const USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_DEP)); +} + +/** + * @} + */ + +/** @defgroup LPUART_LL_EF_FLAG_Management FLAG_Management + * @{ + */ + +/** + * @brief Check if the LPUART Parity Error Flag is set or not + * @rmtoll ISR PE LL_LPUART_IsActiveFlag_PE + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_PE(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_PE) == (USART_ISR_PE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART Framing Error Flag is set or not + * @rmtoll ISR FE LL_LPUART_IsActiveFlag_FE + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_FE(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_FE) == (USART_ISR_FE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART Noise error detected Flag is set or not + * @rmtoll ISR NE LL_LPUART_IsActiveFlag_NE + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_NE(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_NE) == (USART_ISR_NE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART OverRun Error Flag is set or not + * @rmtoll ISR ORE LL_LPUART_IsActiveFlag_ORE + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_ORE(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_ORE) == (USART_ISR_ORE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART IDLE line detected Flag is set or not + * @rmtoll ISR IDLE LL_LPUART_IsActiveFlag_IDLE + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_IDLE(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE)) ? 1UL : 0UL); +} + +#define LL_LPUART_IsActiveFlag_RXNE LL_LPUART_IsActiveFlag_RXNE_RXFNE /* Redefinition for legacy purpose */ + +/** + * @brief Check if the LPUART Read Data Register or LPUART RX FIFO Not Empty Flag is set or not + * @rmtoll ISR RXNE_RXFNE LL_LPUART_IsActiveFlag_RXNE_RXFNE + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXNE_RXFNE(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXNE_RXFNE) == (USART_ISR_RXNE_RXFNE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART Transmission Complete Flag is set or not + * @rmtoll ISR TC LL_LPUART_IsActiveFlag_TC + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TC(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_TC) == (USART_ISR_TC)) ? 1UL : 0UL); +} + +#define LL_LPUART_IsActiveFlag_TXE LL_LPUART_IsActiveFlag_TXE_TXFNF /* Redefinition for legacy purpose */ + +/** + * @brief Check if the LPUART Transmit Data Register Empty or LPUART TX FIFO Not Full Flag is set or not + * @rmtoll ISR TXE_TXFNF LL_LPUART_IsActiveFlag_TXE_TXFNF + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXE_TXFNF(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXE_TXFNF) == (USART_ISR_TXE_TXFNF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART CTS interrupt Flag is set or not + * @rmtoll ISR CTSIF LL_LPUART_IsActiveFlag_nCTS + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_nCTS(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART CTS Flag is set or not + * @rmtoll ISR CTS LL_LPUART_IsActiveFlag_CTS + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CTS(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_CTS) == (USART_ISR_CTS)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART Busy Flag is set or not + * @rmtoll ISR BUSY LL_LPUART_IsActiveFlag_BUSY + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_BUSY(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART Character Match Flag is set or not + * @rmtoll ISR CMF LL_LPUART_IsActiveFlag_CM + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CM(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_CMF) == (USART_ISR_CMF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART Send Break Flag is set or not + * @rmtoll ISR SBKF LL_LPUART_IsActiveFlag_SBK + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_SBK(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART Receive Wake Up from mute mode Flag is set or not + * @rmtoll ISR RWU LL_LPUART_IsActiveFlag_RWU + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RWU(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART Wake Up from stop mode Flag is set or not + * @rmtoll ISR WUF LL_LPUART_IsActiveFlag_WKUP + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_WKUP(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_WUF) == (USART_ISR_WUF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART Transmit Enable Acknowledge Flag is set or not + * @rmtoll ISR TEACK LL_LPUART_IsActiveFlag_TEACK + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TEACK(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART Receive Enable Acknowledge Flag is set or not + * @rmtoll ISR REACK LL_LPUART_IsActiveFlag_REACK + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_REACK(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART TX FIFO Empty Flag is set or not + * @rmtoll ISR TXFE LL_LPUART_IsActiveFlag_TXFE + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFE(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXFE) == (USART_ISR_TXFE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART RX FIFO Full Flag is set or not + * @rmtoll ISR RXFF LL_LPUART_IsActiveFlag_RXFF + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXFF(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXFF) == (USART_ISR_RXFF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART TX FIFO Threshold Flag is set or not + * @rmtoll ISR TXFT LL_LPUART_IsActiveFlag_TXFT + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFT(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXFT) == (USART_ISR_TXFT)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART RX FIFO Threshold Flag is set or not + * @rmtoll ISR RXFT LL_LPUART_IsActiveFlag_RXFT + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXFT(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXFT) == (USART_ISR_RXFT)) ? 1UL : 0UL); +} + +/** + * @brief Clear Parity Error Flag + * @rmtoll ICR PECF LL_LPUART_ClearFlag_PE + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_ClearFlag_PE(USART_TypeDef *LPUARTx) +{ + WRITE_REG(LPUARTx->ICR, USART_ICR_PECF); +} + +/** + * @brief Clear Framing Error Flag + * @rmtoll ICR FECF LL_LPUART_ClearFlag_FE + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_ClearFlag_FE(USART_TypeDef *LPUARTx) +{ + WRITE_REG(LPUARTx->ICR, USART_ICR_FECF); +} + +/** + * @brief Clear Noise detected Flag + * @rmtoll ICR NECF LL_LPUART_ClearFlag_NE + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_ClearFlag_NE(USART_TypeDef *LPUARTx) +{ + WRITE_REG(LPUARTx->ICR, USART_ICR_NECF); +} + +/** + * @brief Clear OverRun Error Flag + * @rmtoll ICR ORECF LL_LPUART_ClearFlag_ORE + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_ClearFlag_ORE(USART_TypeDef *LPUARTx) +{ + WRITE_REG(LPUARTx->ICR, USART_ICR_ORECF); +} + +/** + * @brief Clear IDLE line detected Flag + * @rmtoll ICR IDLECF LL_LPUART_ClearFlag_IDLE + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_ClearFlag_IDLE(USART_TypeDef *LPUARTx) +{ + WRITE_REG(LPUARTx->ICR, USART_ICR_IDLECF); +} + +/** + * @brief Clear Transmission Complete Flag + * @rmtoll ICR TCCF LL_LPUART_ClearFlag_TC + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_ClearFlag_TC(USART_TypeDef *LPUARTx) +{ + WRITE_REG(LPUARTx->ICR, USART_ICR_TCCF); +} + +/** + * @brief Clear CTS Interrupt Flag + * @rmtoll ICR CTSCF LL_LPUART_ClearFlag_nCTS + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_ClearFlag_nCTS(USART_TypeDef *LPUARTx) +{ + WRITE_REG(LPUARTx->ICR, USART_ICR_CTSCF); +} + +/** + * @brief Clear Character Match Flag + * @rmtoll ICR CMCF LL_LPUART_ClearFlag_CM + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_ClearFlag_CM(USART_TypeDef *LPUARTx) +{ + WRITE_REG(LPUARTx->ICR, USART_ICR_CMCF); +} + +/** + * @brief Clear Wake Up from stop mode Flag + * @rmtoll ICR WUCF LL_LPUART_ClearFlag_WKUP + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_ClearFlag_WKUP(USART_TypeDef *LPUARTx) +{ + WRITE_REG(LPUARTx->ICR, USART_ICR_WUCF); +} + +/** + * @} + */ + +/** @defgroup LPUART_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable IDLE Interrupt + * @rmtoll CR1 IDLEIE LL_LPUART_EnableIT_IDLE + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableIT_IDLE(USART_TypeDef *LPUARTx) +{ + ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_IDLEIE); +} + +#define LL_LPUART_EnableIT_RXNE LL_LPUART_EnableIT_RXNE_RXFNE /* Redefinition for legacy purpose */ + +/** + * @brief Enable RX Not Empty and RX FIFO Not Empty Interrupt + * @rmtoll CR1 RXNEIE_RXFNEIE LL_LPUART_EnableIT_RXNE_RXFNE + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableIT_RXNE_RXFNE(USART_TypeDef *LPUARTx) +{ + ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE); +} + +/** + * @brief Enable Transmission Complete Interrupt + * @rmtoll CR1 TCIE LL_LPUART_EnableIT_TC + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableIT_TC(USART_TypeDef *LPUARTx) +{ + ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TCIE); +} + +#define LL_LPUART_EnableIT_TXE LL_LPUART_EnableIT_TXE_TXFNF /* Redefinition for legacy purpose */ + +/** + * @brief Enable TX Empty and TX FIFO Not Full Interrupt + * @rmtoll CR1 TXEIE_TXFNFIE LL_LPUART_EnableIT_TXE_TXFNF + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableIT_TXE_TXFNF(USART_TypeDef *LPUARTx) +{ + ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE); +} + +/** + * @brief Enable Parity Error Interrupt + * @rmtoll CR1 PEIE LL_LPUART_EnableIT_PE + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableIT_PE(USART_TypeDef *LPUARTx) +{ + ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_PEIE); +} + +/** + * @brief Enable Character Match Interrupt + * @rmtoll CR1 CMIE LL_LPUART_EnableIT_CM + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableIT_CM(USART_TypeDef *LPUARTx) +{ + ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_CMIE); +} + +/** + * @brief Enable TX FIFO Empty Interrupt + * @rmtoll CR1 TXFEIE LL_LPUART_EnableIT_TXFE + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableIT_TXFE(USART_TypeDef *LPUARTx) +{ + ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TXFEIE); +} + +/** + * @brief Enable RX FIFO Full Interrupt + * @rmtoll CR1 RXFFIE LL_LPUART_EnableIT_RXFF + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableIT_RXFF(USART_TypeDef *LPUARTx) +{ + ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_RXFFIE); +} + +/** + * @brief Enable Error Interrupt + * @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing + * error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register). + * - 0: Interrupt is inhibited + * - 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register. + * @rmtoll CR3 EIE LL_LPUART_EnableIT_ERROR + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableIT_ERROR(USART_TypeDef *LPUARTx) +{ + ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_EIE); +} + +/** + * @brief Enable CTS Interrupt + * @rmtoll CR3 CTSIE LL_LPUART_EnableIT_CTS + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableIT_CTS(USART_TypeDef *LPUARTx) +{ + ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_CTSIE); +} + +/** + * @brief Enable Wake Up from Stop Mode Interrupt + * @rmtoll CR3 WUFIE LL_LPUART_EnableIT_WKUP + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableIT_WKUP(USART_TypeDef *LPUARTx) +{ + ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_WUFIE); +} + +/** + * @brief Enable TX FIFO Threshold Interrupt + * @rmtoll CR3 TXFTIE LL_LPUART_EnableIT_TXFT + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableIT_TXFT(USART_TypeDef *LPUARTx) +{ + ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_TXFTIE); +} + +/** + * @brief Enable RX FIFO Threshold Interrupt + * @rmtoll CR3 RXFTIE LL_LPUART_EnableIT_RXFT + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableIT_RXFT(USART_TypeDef *LPUARTx) +{ + ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_RXFTIE); +} + +/** + * @brief Disable IDLE Interrupt + * @rmtoll CR1 IDLEIE LL_LPUART_DisableIT_IDLE + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableIT_IDLE(USART_TypeDef *LPUARTx) +{ + ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_IDLEIE); +} + +#define LL_LPUART_DisableIT_RXNE LL_LPUART_DisableIT_RXNE_RXFNE /* Redefinition for legacy purpose */ + +/** + * @brief Disable RX Not Empty and RX FIFO Not Empty Interrupt + * @rmtoll CR1 RXNEIE_RXFNEIE LL_LPUART_DisableIT_RXNE_RXFNE + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableIT_RXNE_RXFNE(USART_TypeDef *LPUARTx) +{ + ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE); +} + +/** + * @brief Disable Transmission Complete Interrupt + * @rmtoll CR1 TCIE LL_LPUART_DisableIT_TC + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableIT_TC(USART_TypeDef *LPUARTx) +{ + ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TCIE); +} + +#define LL_LPUART_DisableIT_TXE LL_LPUART_DisableIT_TXE_TXFNF /* Redefinition for legacy purpose */ + +/** + * @brief Disable TX Empty and TX FIFO Not Full Interrupt + * @rmtoll CR1 TXEIE_TXFNFIE LL_LPUART_DisableIT_TXE_TXFNF + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableIT_TXE_TXFNF(USART_TypeDef *LPUARTx) +{ + ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE); +} + +/** + * @brief Disable Parity Error Interrupt + * @rmtoll CR1 PEIE LL_LPUART_DisableIT_PE + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableIT_PE(USART_TypeDef *LPUARTx) +{ + ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_PEIE); +} + +/** + * @brief Disable Character Match Interrupt + * @rmtoll CR1 CMIE LL_LPUART_DisableIT_CM + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableIT_CM(USART_TypeDef *LPUARTx) +{ + ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_CMIE); +} + +/** + * @brief Disable TX FIFO Empty Interrupt + * @rmtoll CR1 TXFEIE LL_LPUART_DisableIT_TXFE + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableIT_TXFE(USART_TypeDef *LPUARTx) +{ + ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXFEIE); +} + +/** + * @brief Disable RX FIFO Full Interrupt + * @rmtoll CR1 RXFFIE LL_LPUART_DisableIT_RXFF + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableIT_RXFF(USART_TypeDef *LPUARTx) +{ + ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXFFIE); +} + +/** + * @brief Disable Error Interrupt + * @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing + * error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register). + * - 0: Interrupt is inhibited + * - 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register. + * @rmtoll CR3 EIE LL_LPUART_DisableIT_ERROR + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableIT_ERROR(USART_TypeDef *LPUARTx) +{ + ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_EIE); +} + +/** + * @brief Disable CTS Interrupt + * @rmtoll CR3 CTSIE LL_LPUART_DisableIT_CTS + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableIT_CTS(USART_TypeDef *LPUARTx) +{ + ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_CTSIE); +} + +/** + * @brief Disable Wake Up from Stop Mode Interrupt + * @rmtoll CR3 WUFIE LL_LPUART_DisableIT_WKUP + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableIT_WKUP(USART_TypeDef *LPUARTx) +{ + ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_WUFIE); +} + +/** + * @brief Disable TX FIFO Threshold Interrupt + * @rmtoll CR3 TXFTIE LL_LPUART_DisableIT_TXFT + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableIT_TXFT(USART_TypeDef *LPUARTx) +{ + ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_TXFTIE); +} + +/** + * @brief Disable RX FIFO Threshold Interrupt + * @rmtoll CR3 RXFTIE LL_LPUART_DisableIT_RXFT + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableIT_RXFT(USART_TypeDef *LPUARTx) +{ + ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_RXFTIE); +} + +/** + * @brief Check if the LPUART IDLE Interrupt source is enabled or disabled. + * @rmtoll CR1 IDLEIE LL_LPUART_IsEnabledIT_IDLE + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_IDLE(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE)) ? 1UL : 0UL); +} + +#define LL_LPUART_IsEnabledIT_RXNE LL_LPUART_IsEnabledIT_RXNE_RXFNE /* Redefinition for legacy purpose */ + +/** + * @brief Check if the LPUART RX Not Empty and LPUART RX FIFO Not Empty Interrupt is enabled or disabled. + * @rmtoll CR1 RXNEIE_RXFNEIE LL_LPUART_IsEnabledIT_RXNE_RXFNE + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXNE_RXFNE(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE) == (USART_CR1_RXNEIE_RXFNEIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART Transmission Complete Interrupt is enabled or disabled. + * @rmtoll CR1 TCIE LL_LPUART_IsEnabledIT_TC + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TC(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)) ? 1UL : 0UL); +} + +#define LL_LPUART_IsEnabledIT_TXE LL_LPUART_IsEnabledIT_TXE_TXFNF /* Redefinition for legacy purpose */ + +/** + * @brief Check if the LPUART TX Empty and LPUART TX FIFO Not Full Interrupt is enabled or disabled + * @rmtoll CR1 TXEIE_TXFNFIE LL_LPUART_IsEnabledIT_TXE_TXFNF + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXE_TXFNF(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE) == (USART_CR1_TXEIE_TXFNFIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART Parity Error Interrupt is enabled or disabled. + * @rmtoll CR1 PEIE LL_LPUART_IsEnabledIT_PE + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_PE(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART Character Match Interrupt is enabled or disabled. + * @rmtoll CR1 CMIE LL_LPUART_IsEnabledIT_CM + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CM(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART TX FIFO Empty Interrupt is enabled or disabled + * @rmtoll CR1 TXFEIE LL_LPUART_IsEnabledIT_TXFE + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFE(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR1, USART_CR1_TXFEIE) == (USART_CR1_TXFEIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART RX FIFO Full Interrupt is enabled or disabled + * @rmtoll CR1 RXFFIE LL_LPUART_IsEnabledIT_RXFF + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXFF(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR1, USART_CR1_RXFFIE) == (USART_CR1_RXFFIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART Error Interrupt is enabled or disabled. + * @rmtoll CR3 EIE LL_LPUART_IsEnabledIT_ERROR + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_ERROR(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART CTS Interrupt is enabled or disabled. + * @rmtoll CR3 CTSIE LL_LPUART_IsEnabledIT_CTS + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CTS(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART Wake Up from Stop Mode Interrupt is enabled or disabled. + * @rmtoll CR3 WUFIE LL_LPUART_IsEnabledIT_WKUP + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_WKUP(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR3, USART_CR3_WUFIE) == (USART_CR3_WUFIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if LPUART TX FIFO Threshold Interrupt is enabled or disabled + * @rmtoll CR3 TXFTIE LL_LPUART_IsEnabledIT_TXFT + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFT(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR3, USART_CR3_TXFTIE) == (USART_CR3_TXFTIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if LPUART RX FIFO Threshold Interrupt is enabled or disabled + * @rmtoll CR3 RXFTIE LL_LPUART_IsEnabledIT_RXFT + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXFT(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR3, USART_CR3_RXFTIE) == (USART_CR3_RXFTIE)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup LPUART_LL_EF_DMA_Management DMA_Management + * @{ + */ + +/** + * @brief Enable DMA Mode for reception + * @rmtoll CR3 DMAR LL_LPUART_EnableDMAReq_RX + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableDMAReq_RX(USART_TypeDef *LPUARTx) +{ + ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_DMAR); +} + +/** + * @brief Disable DMA Mode for reception + * @rmtoll CR3 DMAR LL_LPUART_DisableDMAReq_RX + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableDMAReq_RX(USART_TypeDef *LPUARTx) +{ + ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_DMAR); +} + +/** + * @brief Check if DMA Mode is enabled for reception + * @rmtoll CR3 DMAR LL_LPUART_IsEnabledDMAReq_RX + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_RX(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR)) ? 1UL : 0UL); +} + +/** + * @brief Enable DMA Mode for transmission + * @rmtoll CR3 DMAT LL_LPUART_EnableDMAReq_TX + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableDMAReq_TX(USART_TypeDef *LPUARTx) +{ + ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_DMAT); +} + +/** + * @brief Disable DMA Mode for transmission + * @rmtoll CR3 DMAT LL_LPUART_DisableDMAReq_TX + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableDMAReq_TX(USART_TypeDef *LPUARTx) +{ + ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_DMAT); +} + +/** + * @brief Check if DMA Mode is enabled for transmission + * @rmtoll CR3 DMAT LL_LPUART_IsEnabledDMAReq_TX + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_TX(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT)) ? 1UL : 0UL); +} + +/** + * @brief Enable DMA Disabling on Reception Error + * @rmtoll CR3 DDRE LL_LPUART_EnableDMADeactOnRxErr + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableDMADeactOnRxErr(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->CR3, USART_CR3_DDRE); +} + +/** + * @brief Disable DMA Disabling on Reception Error + * @rmtoll CR3 DDRE LL_LPUART_DisableDMADeactOnRxErr + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableDMADeactOnRxErr(USART_TypeDef *LPUARTx) +{ + CLEAR_BIT(LPUARTx->CR3, USART_CR3_DDRE); +} + +/** + * @brief Indicate if DMA Disabling on Reception Error is disabled + * @rmtoll CR3 DDRE LL_LPUART_IsEnabledDMADeactOnRxErr + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMADeactOnRxErr(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE)) ? 1UL : 0UL); +} + +/** + * @brief Get the LPUART data register address used for DMA transfer + * @rmtoll RDR RDR LL_LPUART_DMA_GetRegAddr\n + * @rmtoll TDR TDR LL_LPUART_DMA_GetRegAddr + * @param LPUARTx LPUART Instance + * @param Direction This parameter can be one of the following values: + * @arg @ref LL_LPUART_DMA_REG_DATA_TRANSMIT + * @arg @ref LL_LPUART_DMA_REG_DATA_RECEIVE + * @retval Address of data register + */ +__STATIC_INLINE uint32_t LL_LPUART_DMA_GetRegAddr(const USART_TypeDef *LPUARTx, uint32_t Direction) +{ + uint32_t data_reg_addr; + + if (Direction == LL_LPUART_DMA_REG_DATA_TRANSMIT) + { + /* return address of TDR register */ + data_reg_addr = (uint32_t) &(LPUARTx->TDR); + } + else + { + /* return address of RDR register */ + data_reg_addr = (uint32_t) &(LPUARTx->RDR); + } + + return data_reg_addr; +} + +/** + * @} + */ + +/** @defgroup LPUART_LL_EF_Data_Management Data_Management + * @{ + */ + +/** + * @brief Read Receiver Data register (Receive Data value, 8 bits) + * @rmtoll RDR RDR LL_LPUART_ReceiveData8 + * @param LPUARTx LPUART Instance + * @retval Time Value between Min_Data=0x00 and Max_Data=0xFF + */ +__STATIC_INLINE uint8_t LL_LPUART_ReceiveData8(const USART_TypeDef *LPUARTx) +{ + return (uint8_t)(READ_BIT(LPUARTx->RDR, USART_RDR_RDR) & 0xFFU); +} + +/** + * @brief Read Receiver Data register (Receive Data value, 9 bits) + * @rmtoll RDR RDR LL_LPUART_ReceiveData9 + * @param LPUARTx LPUART Instance + * @retval Time Value between Min_Data=0x00 and Max_Data=0x1FF + */ +__STATIC_INLINE uint16_t LL_LPUART_ReceiveData9(const USART_TypeDef *LPUARTx) +{ + return (uint16_t)(READ_BIT(LPUARTx->RDR, USART_RDR_RDR)); +} + +/** + * @brief Write in Transmitter Data Register (Transmit Data value, 8 bits) + * @rmtoll TDR TDR LL_LPUART_TransmitData8 + * @param LPUARTx LPUART Instance + * @param Value between Min_Data=0x00 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_LPUART_TransmitData8(USART_TypeDef *LPUARTx, uint8_t Value) +{ + LPUARTx->TDR = Value; +} + +/** + * @brief Write in Transmitter Data Register (Transmit Data value, 9 bits) + * @rmtoll TDR TDR LL_LPUART_TransmitData9 + * @param LPUARTx LPUART Instance + * @param Value between Min_Data=0x00 and Max_Data=0x1FF + * @retval None + */ +__STATIC_INLINE void LL_LPUART_TransmitData9(USART_TypeDef *LPUARTx, uint16_t Value) +{ + LPUARTx->TDR = Value & 0x1FFUL; +} + +/** + * @} + */ + +/** @defgroup LPUART_LL_EF_Execution Execution + * @{ + */ + +/** + * @brief Request Break sending + * @rmtoll RQR SBKRQ LL_LPUART_RequestBreakSending + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_RequestBreakSending(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_SBKRQ); +} + +/** + * @brief Put LPUART in mute mode and set the RWU flag + * @rmtoll RQR MMRQ LL_LPUART_RequestEnterMuteMode + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_RequestEnterMuteMode(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_MMRQ); +} + +/** + * @brief Request a Receive Data and FIFO flush + * @note Allows to discard the received data without reading them, and avoid an overrun + * condition. + * @rmtoll RQR RXFRQ LL_LPUART_RequestRxDataFlush + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_RequestRxDataFlush(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_RXFRQ); +} + +/** + * @brief Request a Transmit data FIFO flush + * @note TXFRQ bit is set to flush the whole FIFO when FIFO mode is enabled. This + * also sets the flag TXFE (TXFIFO empty bit in the LPUART_ISR register). + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll RQR TXFRQ LL_LPUART_RequestTxDataFlush + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_RequestTxDataFlush(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_TXFRQ); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup LPUART_LL_EF_Init Initialization and de-initialization functions + * @{ + */ +ErrorStatus LL_LPUART_DeInit(const USART_TypeDef *LPUARTx); +ErrorStatus LL_LPUART_Init(USART_TypeDef *LPUARTx, const LL_LPUART_InitTypeDef *LPUART_InitStruct); +void LL_LPUART_StructInit(LL_LPUART_InitTypeDef *LPUART_InitStruct); +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* LPUART1 */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32WLxx_LL_LPUART_H */ + diff --git a/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h b/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h new file mode 100644 index 0000000..b21706e --- /dev/null +++ b/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h @@ -0,0 +1,2286 @@ +/** + ****************************************************************************** + * @file stm32wlxx_ll_pwr.h + * @author MCD Application Team + * @brief Header file of PWR LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32WLxx_LL_PWR_H +#define __STM32WLxx_LL_PWR_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wlxx.h" + +/** @addtogroup STM32WLxx_LL_Driver + * @{ + */ + +#if defined(PWR) + +/** @defgroup PWR_LL PWR + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup PWR_LL_Private_Constants PWR Private Constants + * @{ + */ +#define PWR_FLASH_POWER_MODE_UNLOCK_CODE (0x0000C1B0UL) +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup PWR_LL_Exported_Constants PWR Exported Constants + * @{ + */ + +/** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines + * @brief Flags defines which can be used with LL_PWR_WriteReg function + * @{ + */ +#define LL_PWR_SCR_CWUF PWR_SCR_CWUF +#define LL_PWR_SCR_CWUF3 PWR_SCR_CWUF3 +#define LL_PWR_SCR_CWUF2 PWR_SCR_CWUF2 +#define LL_PWR_SCR_CWUF1 PWR_SCR_CWUF1 +#define LL_PWR_SCR_CWPVDF PWR_SCR_CWPVDF +#define LL_PWR_SCR_CWRFBUSYF PWR_SCR_CWRFBUSYF +#define LL_PWR_SCR_CC2HF PWR_SCR_CC2HF +#define LL_PWR_EXTSCR_C2CSSF PWR_EXTSCR_C2CSSF +#define LL_PWR_EXTSCR_C1CSSF PWR_EXTSCR_C1CSSF +/** + * @} + */ + +/** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_PWR_ReadReg function + * @{ + */ +#define LL_PWR_SR1_WUFI PWR_SR1_WUFI +#define LL_PWR_SR1_WUF3 PWR_SR1_WUF3 +#define LL_PWR_SR1_WUF2 PWR_SR1_WUF2 +#define LL_PWR_SR1_WUF1 PWR_SR1_WUF1 +#define LL_PWR_SR1_WPVDF PWR_SR1_WPVDF + +#define LL_PWR_SR2_LDORDY PWR_SR2_LDORDY +#define LL_PWR_SR2_PVMO3 PWR_SR2_PVMO3 +#define LL_PWR_SR2_PVDO PWR_SR2_PVDO +#define LL_PWR_SR2_RFEOL PWR_SR2_RFEOLF +#define LL_PWR_SR2_VOSF PWR_SR2_VOSF +#define LL_PWR_SR2_REGLPF PWR_SR2_REGLPF +#define LL_PWR_SR2_REGLPS PWR_SR2_REGLPS +#define LL_PWR_SR2_REGMRS PWR_SR2_REGMRS + +/* SMPS flags */ +#define LL_PWR_SR2_SMPSRDY PWR_SR2_SMPSRDY + +/* Radio flags */ +#define LL_PWR_SR1_WRFBUSY PWR_SR1_WRFBUSYF /* Radio busy flag for wake-up and interruption (triggered status: wake-up event or interruption occurred at least once. Can be cleared by software) */ +#define LL_PWR_SR2_RFBUSYS PWR_SR2_RFBUSYS /* Radio busy signal flag (current status) */ +#define LL_PWR_SR2_RFBUSYMS PWR_SR2_RFBUSYMS /* Radio busy masked signal flag (current status) */ + +/* Multicore flags */ +#define LL_PWR_EXTSCR_C1SBF PWR_EXTSCR_C1SBF /* System Standby flag for CPU1 */ +#define LL_PWR_EXTSCR_C1STOP2F PWR_EXTSCR_C1STOP2F /* System Stop 2 flag for CPU1 */ +#define LL_PWR_EXTSCR_C1STOPF PWR_EXTSCR_C1STOPF /* System Stop 0 or stop 1 flag for CPU1 */ +#define LL_PWR_EXTSCR_C1DS PWR_EXTSCR_C1DS /* CPU1 deepsleep mode */ +#if defined(DUAL_CORE) +#define LL_PWR_EXTSCR_C2SBF PWR_EXTSCR_C2SBF /* System Standby flag for CPU2 */ +#define LL_PWR_EXTSCR_C2STOP2F PWR_EXTSCR_C2STOP2F /* System Stop 2 flag for CPU2 */ +#define LL_PWR_EXTSCR_C2STOPF PWR_EXTSCR_C2STOPF /* System Stop 0 or stop 1 flag for CPU2 */ +#define LL_PWR_EXTSCR_C2DS PWR_EXTSCR_C2DS /* CPU2 deepsleep mode */ +#define LL_PWR_SR2_C2BOOTS PWR_SR2_C2BOOTS /* CPU2 boot request source information flag */ +#define LL_PWR_SR1_C2HF PWR_SR1_C2HF /* CPU2 hold interrupt flag */ +#endif /* DUAL_CORE */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_REGU_VOLTAGE REGU VOLTAGE + * @{ + */ +#define LL_PWR_REGU_VOLTAGE_SCALE1 (PWR_CR1_VOS_0) /* Regulator voltage output range 1 mode, typical output voltage at 1.2 V, system frequency up to 64 MHz. */ +#define LL_PWR_REGU_VOLTAGE_SCALE2 (PWR_CR1_VOS_1) /* Regulator voltage output range 2 mode, typical output voltage at 1.0 V, system frequency up to 16 MHz. */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_MODE_PWR MODE PWR + * @{ + */ +#define LL_PWR_MODE_STOP0 (0x000000000UL) +#define LL_PWR_MODE_STOP1 (PWR_CR1_LPMS_0) +#define LL_PWR_MODE_STOP2 (PWR_CR1_LPMS_1) +#define LL_PWR_MODE_STANDBY (PWR_CR1_LPMS_1 | PWR_CR1_LPMS_0) +#define LL_PWR_MODE_SHUTDOWN (PWR_CR1_LPMS_2 | PWR_CR1_LPMS_1 | PWR_CR1_LPMS_0) +/** + * @} + */ + +/** @defgroup PWR_LL_EC_FLASH_LPRUN_POWER_DOWN_MODE Flash power-down mode during low-power run mode + * @{ + */ +#define LL_PWR_FLASH_LPRUN_MODE_IDLE (0x000000000UL) +#define LL_PWR_FLASH_LPRUN_MODE_POWER_DOWN (PWR_CR1_FPDR) +/** + * @} + */ + +/** @defgroup PWR_LL_EC_FLASH_SLEEP_POWER_DOWN_MODE Flash power-down mode during sleep mode + * @{ + */ +#define LL_PWR_FLASH_SLEEP_MODE_IDLE (0x000000000UL) +#define LL_PWR_FLASH_SLEEP_MODE_POWER_DOWN (PWR_CR1_FPDS) +/** + * @} + */ + +/** @defgroup PWR_LL_EC_PVM Peripheral voltage monitoring + * @{ + */ +#define LL_PWR_PVM_VDDA_1_62V (PWR_CR2_PVME3) /* Monitoring VDDA vs. 1.62V */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_PVDLEVEL PVDLEVEL + * @{ + */ +#define LL_PWR_PVDLEVEL_0 (0x00000000UL) /* VPVD0 around 2.0 V */ +#define LL_PWR_PVDLEVEL_1 (PWR_CR2_PLS_0) /* VPVD1 around 2.2 V */ +#define LL_PWR_PVDLEVEL_2 (PWR_CR2_PLS_1) /* VPVD2 around 2.4 V */ +#define LL_PWR_PVDLEVEL_3 (PWR_CR2_PLS_1 | PWR_CR2_PLS_0) /* VPVD3 around 2.5 V */ +#define LL_PWR_PVDLEVEL_4 (PWR_CR2_PLS_2) /* VPVD4 around 2.6 V */ +#define LL_PWR_PVDLEVEL_5 (PWR_CR2_PLS_2 | PWR_CR2_PLS_0) /* VPVD5 around 2.8 V */ +#define LL_PWR_PVDLEVEL_6 (PWR_CR2_PLS_2 | PWR_CR2_PLS_1) /* VPVD6 around 2.9 V */ +#define LL_PWR_PVDLEVEL_7 (PWR_CR2_PLS_2 | PWR_CR2_PLS_1 | PWR_CR2_PLS_0) /* External input analog voltage (Compare internally to VREFINT) */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_EOL_OPERATING_MODES Monitoring of supply voltage for radio operating level (radio End Of Life) + * @{ + */ +#define LL_PWR_RADIO_EOL_DISABLE (0x00000000UL) /*!< Monitoring of supply voltage for radio operating level (radio End Of Life) disable */ +#define LL_PWR_RADIO_EOL_ENABLE (PWR_CR5_RFEOLEN) /*!< Monitoring of supply voltage for radio operating level (radio End Of Life) enable */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_WAKEUP WAKEUP + * @{ + */ +#define LL_PWR_WAKEUP_PIN1 (PWR_CR3_EWUP1) +#define LL_PWR_WAKEUP_PIN2 (PWR_CR3_EWUP2) +#define LL_PWR_WAKEUP_PIN3 (PWR_CR3_EWUP3) +/** + * @} + */ + +/** @defgroup PWR_LL_EC_BATT_CHARG_RESISTOR BATT CHARG RESISTOR + * @{ + */ +#define LL_PWR_BATT_CHARG_RESISTOR_5K (0x00000000UL) +#define LL_PWR_BATT_CHARGRESISTOR_1_5K (PWR_CR4_VBRS) +/** + * @} + */ + +/** @defgroup PWR_LL_EC_GPIO GPIO + * @{ + */ +#define LL_PWR_GPIO_A ((uint32_t)(&(PWR->PUCRA))) +#define LL_PWR_GPIO_B ((uint32_t)(&(PWR->PUCRB))) +#define LL_PWR_GPIO_C ((uint32_t)(&(PWR->PUCRC))) +#define LL_PWR_GPIO_H ((uint32_t)(&(PWR->PUCRH))) +/** + * @} + */ + +/** @defgroup PWR_LL_EC_GPIO_BIT GPIO BIT + * @{ + */ +/* Note: LL_PWR_GPIO_BIT_x defined from port B because all pins are available */ +/* for PWR pull-up and pull-down. */ +#define LL_PWR_GPIO_BIT_0 (PWR_PUCRB_PB0) +#define LL_PWR_GPIO_BIT_1 (PWR_PUCRB_PB1) +#define LL_PWR_GPIO_BIT_2 (PWR_PUCRB_PB2) +#define LL_PWR_GPIO_BIT_3 (PWR_PUCRB_PB3) +#define LL_PWR_GPIO_BIT_4 (PWR_PUCRB_PB4) +#define LL_PWR_GPIO_BIT_5 (PWR_PUCRB_PB5) +#define LL_PWR_GPIO_BIT_6 (PWR_PUCRB_PB6) +#define LL_PWR_GPIO_BIT_7 (PWR_PUCRB_PB7) +#define LL_PWR_GPIO_BIT_8 (PWR_PUCRB_PB8) +#define LL_PWR_GPIO_BIT_9 (PWR_PUCRB_PB9) +#define LL_PWR_GPIO_BIT_10 (PWR_PUCRB_PB10) +#define LL_PWR_GPIO_BIT_11 (PWR_PUCRB_PB11) +#define LL_PWR_GPIO_BIT_12 (PWR_PUCRB_PB12) +#define LL_PWR_GPIO_BIT_13 (PWR_PUCRB_PB13) +#define LL_PWR_GPIO_BIT_14 (PWR_PUCRB_PB14) +#define LL_PWR_GPIO_BIT_15 (PWR_PUCRB_PB15) +/** + * @} + */ + +/** @defgroup PWR_LL_EC_SMPS_OPERATING_MODES SMPS step down converter operating modes + * @{ + */ +#define LL_PWR_SMPS_BYPASS (0x00000000UL) /*!< SMPS step down in bypass mode (disable). */ +#define LL_PWR_SMPS_STEP_DOWN (PWR_CR5_SMPSEN) /*!< SMPS step down in step down mode if system low power mode is run, LP run or Stop 0. If system low power mode is Stop 1, Stop 2, Standby, Shutdown, then SMPS is forced in mode open to preserve energy stored in decoupling capacitor as long as possible. Note: In case of a board without SMPS coil mounted, SMPS should not be activated. */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_RADIO_BUSY_POLARITY Radio busy signal polarity + * @{ + */ +#define LL_PWR_RADIO_BUSY_POLARITY_RISING (0x00000000UL) /*!< Radio busy signal polarity to rising edge (detection on high level). */ +#define LL_PWR_RADIO_BUSY_POLARITY_FALLING (PWR_CR4_WRFBUSYP) /*!< Radio busy signal polarity to falling edge (detection on low level). */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_RADIO_BUSY_TRIGGER Radio busy trigger + * @{ + */ +#define LL_PWR_RADIO_BUSY_TRIGGER_NONE (0x00000000UL) /*!< Radio busy trigger action: no wake-up from low-power mode and no interruption sent to the selected CPU. */ +#define LL_PWR_RADIO_BUSY_TRIGGER_WU_IT (PWR_CR3_EWRFBUSY) /*!< Radio busy trigger action: wake-up from low-power mode Standby and interruption sent to the selected CPU. */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_RADIO_IRQ_TRIGGER Radio IRQ trigger + * @{ + */ +#define LL_PWR_RADIO_IRQ_TRIGGER_NONE (0x00000000UL) /*!< Radio IRQ trigger action: no wake-up from low-power mode and no interruption sent to the selected CPU. */ +#define LL_PWR_RADIO_IRQ_TRIGGER_WU_IT (PWR_CR3_EWRFIRQ) /*!< Radio IRQ trigger action: wake-up from low-power mode Standby and interruption sent to the selected CPU. */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_RADIO_SPI_NSS_SRC Radio Sub-GHz radio SPI NSS source + * @{ + */ +#define LL_PWR_SUBGHZSPI_NSS_SRC_SW (0x00000000UL) /*!< Sub-GHz radio SPI NSS controlled by software. Refer to function @ref LL_PWR_UnselectSUBGHZSPI_NSS(). */ +#define LL_PWR_SUBGHZSPI_NSS_SRC_LPTIM3 (PWR_CR1_SUBGHZSPINSSSEL) /*!< Sub-GHz radio SPI NSS controlled by LPTIM3. */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup PWR_LL_Exported_Macros PWR Exported Macros + * @{ + */ + +/** @defgroup PWR_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in PWR register + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__)) + +/** + * @brief Read a value in PWR register + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__) +/** + * @} + */ + +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup PWR_LL_Exported_Functions PWR Exported Functions + * @{ + */ + +/** @defgroup PWR_LL_EF_Configuration Configuration + * @{ + */ + +/** + * @brief Switch from run main mode to run low-power mode. + * @rmtoll CR1 LPR LL_PWR_EnterLowPowerRunMode + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnterLowPowerRunMode(void) +{ + SET_BIT(PWR->CR1, PWR_CR1_LPR); +} + +/** + * @brief Switch from run main mode to low-power mode. + * @rmtoll CR1 LPR LL_PWR_ExitLowPowerRunMode + * @retval None + */ +__STATIC_INLINE void LL_PWR_ExitLowPowerRunMode(void) +{ + CLEAR_BIT(PWR->CR1, PWR_CR1_LPR); +} + +/** + * @brief Check if the regulator is in low-power mode + * @rmtoll CR1 LPR LL_PWR_IsEnabledLowPowerRunMode + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledLowPowerRunMode(void) +{ + return ((READ_BIT(PWR->CR1, PWR_CR1_LPR) == (PWR_CR1_LPR)) ? 1UL : 0UL); +} + +/** + * @brief Set the main internal regulator output voltage + * @note A delay is required for the internal regulator to be ready + * after the voltage scaling has been changed. + * Check whether regulator reached the selected voltage level + * can be done using function @ref LL_PWR_IsActiveFlag_VOS(). + * @rmtoll CR1 VOS LL_PWR_SetRegulVoltageScaling + * @param VoltageScaling This parameter can be one of the following values: + * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1 + * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2 + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling) +{ + MODIFY_REG(PWR->CR1, PWR_CR1_VOS, VoltageScaling); +} + +/** + * @brief Get the main internal regulator output voltage + * @rmtoll CR1 VOS LL_PWR_GetRegulVoltageScaling + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1 + * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2 + */ +__STATIC_INLINE uint32_t LL_PWR_GetRegulVoltageScaling(void) +{ + return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_VOS)); +} + +/** + * @brief Enable access to the backup domain + * @rmtoll CR1 DBP LL_PWR_EnableBkUpAccess + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableBkUpAccess(void) +{ + SET_BIT(PWR->CR1, PWR_CR1_DBP); +} + +/** + * @brief Disable access to the backup domain + * @rmtoll CR1 DBP LL_PWR_DisableBkUpAccess + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableBkUpAccess(void) +{ + CLEAR_BIT(PWR->CR1, PWR_CR1_DBP); +} + +/** + * @brief Check if the backup domain is enabled + * @rmtoll CR1 DBP LL_PWR_IsEnabledBkUpAccess + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void) +{ + return ((READ_BIT(PWR->CR1, PWR_CR1_DBP) == (PWR_CR1_DBP)) ? 1UL : 0UL); +} + +/** + * @brief Set Low-Power mode + * @rmtoll CR1 LPMS LL_PWR_SetPowerMode + * @param LowPowerMode This parameter can be one of the following values: + * @arg @ref LL_PWR_MODE_STOP0 + * @arg @ref LL_PWR_MODE_STOP1 + * @arg @ref LL_PWR_MODE_STOP2 + * @arg @ref LL_PWR_MODE_STANDBY + * @arg @ref LL_PWR_MODE_SHUTDOWN + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t LowPowerMode) +{ + MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, LowPowerMode); +} + +/** + * @brief Get Low-Power mode + * @rmtoll CR1 LPMS LL_PWR_GetPowerMode + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_MODE_STOP0 + * @arg @ref LL_PWR_MODE_STOP1 + * @arg @ref LL_PWR_MODE_STOP2 + * @arg @ref LL_PWR_MODE_STANDBY + * @arg @ref LL_PWR_MODE_SHUTDOWN + */ +__STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void) +{ + return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_LPMS)); +} + +/** + * @brief Set flash power-down mode during low-power run mode + * @rmtoll CR1 FPDR LL_PWR_SetFlashPowerModeLPRun + * @param FlashLowPowerMode This parameter can be one of the following values: + * @arg @ref LL_PWR_FLASH_LPRUN_MODE_IDLE + * @arg @ref LL_PWR_FLASH_LPRUN_MODE_POWER_DOWN + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetFlashPowerModeLPRun(uint32_t FlashLowPowerMode) +{ + /* Unlock bit FPDR */ + WRITE_REG(PWR->CR1, PWR_FLASH_POWER_MODE_UNLOCK_CODE); + + /* Update bit FPDR */ + MODIFY_REG(PWR->CR1, PWR_CR1_FPDR, FlashLowPowerMode); +} + +/** + * @brief Get flash power-down mode during low-power run mode + * @rmtoll CR1 FPDR LL_PWR_GetFlashPowerModeLPRun + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_FLASH_LPRUN_MODE_IDLE + * @arg @ref LL_PWR_FLASH_LPRUN_MODE_POWER_DOWN + */ +__STATIC_INLINE uint32_t LL_PWR_GetFlashPowerModeLPRun(void) +{ + return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_FPDR)); +} + +/** + * @brief Set flash power-down mode during sleep mode + * @rmtoll CR1 FPDS LL_PWR_SetFlashPowerModeSleep + * @param FlashLowPowerMode This parameter can be one of the following values: + * @arg @ref LL_PWR_FLASH_SLEEP_MODE_IDLE + * @arg @ref LL_PWR_FLASH_SLEEP_MODE_POWER_DOWN + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetFlashPowerModeSleep(uint32_t FlashLowPowerMode) +{ + MODIFY_REG(PWR->CR1, PWR_CR1_FPDS, FlashLowPowerMode); +} + +/** + * @brief Get flash power-down mode during sleep mode + * @rmtoll CR1 FPDS LL_PWR_GetFlashPowerModeSleep + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_FLASH_SLEEP_MODE_IDLE + * @arg @ref LL_PWR_FLASH_SLEEP_MODE_POWER_DOWN + */ +__STATIC_INLINE uint32_t LL_PWR_GetFlashPowerModeSleep(void) +{ + return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_FPDS)); +} + +/** + * @brief Enable the Power Voltage Monitoring on a peripheral + * @rmtoll CR2 PVME3 LL_PWR_EnablePVM + * @param PeriphVoltage This parameter can be one of the following values: + * @arg @ref LL_PWR_PVM_VDDA_1_62V + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnablePVM(uint32_t PeriphVoltage) +{ + SET_BIT(PWR->CR2, PeriphVoltage); +} + +/** + * @brief Disable the Power Voltage Monitoring on a peripheral + * @rmtoll CR2 PVME3 LL_PWR_DisablePVM + * @param PeriphVoltage This parameter can be one of the following values: + * @arg @ref LL_PWR_PVM_VDDA_1_62V + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisablePVM(uint32_t PeriphVoltage) +{ + CLEAR_BIT(PWR->CR2, PeriphVoltage); +} + +/** + * @brief Check if Power Voltage Monitoring is enabled on a peripheral + * @rmtoll CR2 PVME3 LL_PWR_IsEnabledPVM + * @param PeriphVoltage This parameter can be one of the following values: + * @arg @ref LL_PWR_PVM_VDDA_1_62V + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledPVM(uint32_t PeriphVoltage) +{ + return ((READ_BIT(PWR->CR2, PeriphVoltage) == (PeriphVoltage)) ? 1UL : 0UL); +} + +/** + * @brief Configure the voltage threshold detected by the Power Voltage Detector + * @rmtoll CR2 PLS LL_PWR_SetPVDLevel + * @param PVDLevel This parameter can be one of the following values: + * @arg @ref LL_PWR_PVDLEVEL_0 + * @arg @ref LL_PWR_PVDLEVEL_1 + * @arg @ref LL_PWR_PVDLEVEL_2 + * @arg @ref LL_PWR_PVDLEVEL_3 + * @arg @ref LL_PWR_PVDLEVEL_4 + * @arg @ref LL_PWR_PVDLEVEL_5 + * @arg @ref LL_PWR_PVDLEVEL_6 + * @arg @ref LL_PWR_PVDLEVEL_7 + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel) +{ + MODIFY_REG(PWR->CR2, PWR_CR2_PLS, PVDLevel); +} + +/** + * @brief Get the voltage threshold detection + * @rmtoll CR2 PLS LL_PWR_GetPVDLevel + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_PVDLEVEL_0 + * @arg @ref LL_PWR_PVDLEVEL_1 + * @arg @ref LL_PWR_PVDLEVEL_2 + * @arg @ref LL_PWR_PVDLEVEL_3 + * @arg @ref LL_PWR_PVDLEVEL_4 + * @arg @ref LL_PWR_PVDLEVEL_5 + * @arg @ref LL_PWR_PVDLEVEL_6 + * @arg @ref LL_PWR_PVDLEVEL_7 + */ +__STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void) +{ + return (uint32_t)(READ_BIT(PWR->CR2, PWR_CR2_PLS)); +} + +/** + * @brief Enable Power Voltage Detector + * @rmtoll CR2 PVDE LL_PWR_EnablePVD + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnablePVD(void) +{ + SET_BIT(PWR->CR2, PWR_CR2_PVDE); +} + +/** + * @brief Disable Power Voltage Detector + * @rmtoll CR2 PVDE LL_PWR_DisablePVD + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisablePVD(void) +{ + CLEAR_BIT(PWR->CR2, PWR_CR2_PVDE); +} + +/** + * @brief Check if Power Voltage Detector is enabled + * @rmtoll CR2 PVDE LL_PWR_IsEnabledPVD + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void) +{ + return ((READ_BIT(PWR->CR2, PWR_CR2_PVDE) == (PWR_CR2_PVDE)) ? 1UL : 0UL); +} + +/** + * @brief Set monitoring of supply voltage for radio operating level + * (radio End Of Life), radio must be in active mode. + * @rmtoll CR5 RFEOLEN LL_PWR_SetRadioEOL + * @param RadioEOL This parameter can be one of the following values: + * @arg @ref LL_PWR_RADIO_EOL_DISABLE + * @arg @ref LL_PWR_RADIO_EOL_ENABLE + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetRadioEOL(uint32_t RadioEOL) +{ + MODIFY_REG(PWR->CR5, PWR_CR5_RFEOLEN, RadioEOL); +} + +/** + * @brief Get monitoring of supply voltage for radio operating level (radio End Of Life) + * @rmtoll CR5 RFEOLEN LL_PWR_GetRadioEOL + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_RADIO_EOL_DISABLE + * @arg @ref LL_PWR_RADIO_EOL_ENABLE + */ +__STATIC_INLINE uint32_t LL_PWR_GetRadioEOL(void) +{ + return (uint32_t)(READ_BIT(PWR->CR5, PWR_CR5_RFEOLEN)); +} + +/** + * @brief Enable Internal Wake-up line + * @rmtoll CR3 EIWF LL_PWR_EnableInternWU + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableInternWU(void) +{ + SET_BIT(PWR->CR3, PWR_CR3_EIWUL); +} + +/** + * @brief Disable Internal Wake-up line + * @rmtoll CR3 EIWF LL_PWR_DisableInternWU + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableInternWU(void) +{ + CLEAR_BIT(PWR->CR3, PWR_CR3_EIWUL); +} + +/** + * @brief Check if Internal Wake-up line is enabled + * @rmtoll CR3 EIWF LL_PWR_IsEnabledInternWU + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledInternWU(void) +{ + return ((READ_BIT(PWR->CR3, PWR_CR3_EIWUL) == (PWR_CR3_EIWUL)) ? 1UL : 0UL); +} + +/** + * @brief Enable pull-up and pull-down configuration + * @rmtoll CR3 APC LL_PWR_EnablePUPDCfg + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnablePUPDCfg(void) +{ + SET_BIT(PWR->CR3, PWR_CR3_APC); +} + +/** + * @brief Disable pull-up and pull-down configuration + * @rmtoll CR3 APC LL_PWR_DisablePUPDCfg + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisablePUPDCfg(void) +{ + CLEAR_BIT(PWR->CR3, PWR_CR3_APC); +} + +/** + * @brief Check if pull-up and pull-down configuration is enabled + * @rmtoll CR3 APC LL_PWR_IsEnabledPUPDCfg + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledPUPDCfg(void) +{ + return ((READ_BIT(PWR->CR3, PWR_CR3_APC) == (PWR_CR3_APC)) ? 1UL : 0UL); +} + +/** + * @brief Enable SRAM2 content retention in Standby mode + * @rmtoll CR3 RRS LL_PWR_EnableSRAM2Retention + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableSRAM2Retention(void) +{ + SET_BIT(PWR->CR3, PWR_CR3_RRS); +} + +/** + * @brief Disable SRAM2 content retention in Standby mode + * @rmtoll CR3 RRS LL_PWR_DisableSRAM2Retention + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableSRAM2Retention(void) +{ + CLEAR_BIT(PWR->CR3, PWR_CR3_RRS); +} + +/** + * @brief Check if SRAM2 content retention in Standby mode is enabled + * @rmtoll CR3 RRS LL_PWR_IsEnabledSRAM2Retention + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledSRAM2Retention(void) +{ + return ((READ_BIT(PWR->CR3, PWR_CR3_RRS) == (PWR_CR3_RRS)) ? 1UL : 0UL); +} + +/** + * @brief Enable wake-up power voltage detection with trigger for CPU1 + * @note Wake-up power voltage detection status can be checked + * using function @ref LL_PWR_IsActiveFlag_WPVD(). + * @rmtoll CR3 EWPVD LL_PWR_EnableWPVD + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableWPVD(void) +{ + SET_BIT(PWR->CR3, PWR_CR3_EWPVD); +} + +/** + * @brief Disable wake-up power voltage detection with trigger for CPU1 + * @rmtoll CR3 EWPVD LL_PWR_DisableWPVD + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableWPVD(void) +{ + CLEAR_BIT(PWR->CR3, PWR_CR3_EWPVD); +} + +/** + * @brief Check if wake-up power voltage detection is enabled with trigger for CPU1 + * @rmtoll CR3 EWPVD LL_PWR_IsEnabledWPVD + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledWPVD(void) +{ + return ((READ_BIT(PWR->CR3, PWR_CR3_EWPVD) == (PWR_CR3_EWPVD)) ? 1UL : 0UL); +} + +/** + * @brief Enable periodical sampling of supply voltage in Stop and Standby + * modes for detecting condition of PDR and BOR reset. + * @note Caution: When enabled, and if the supply voltage drops below + * the minimum operating condition between two supply voltage samples, + * the reset condition is missed and no reset is generated. + * @rmtoll CR3 ULPEN LL_PWR_EnableBORPVD_ULP + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableBORPVD_ULP(void) +{ + SET_BIT(PWR->CR3, PWR_CR3_ULPEN); +} + +/** + * @brief Disable periodical sampling of supply voltage in Stop and Standby + * modes for detecting condition of PDR and BOR reset. + * @rmtoll CR3 ULPEN LL_PWR_DisableBORPVD_ULP + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableBORPVD_ULP(void) +{ + CLEAR_BIT(PWR->CR3, PWR_CR3_ULPEN); +} + +/** + * @brief Check if periodical sampling of supply voltage in Stop and Standby + * modes is enabled. + * @rmtoll CR3 ULPEN LL_PWR_IsEnabledBORPVD_ULP + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledBORPVD_ULP(void) +{ + return ((READ_BIT(PWR->CR3, PWR_CR3_ULPEN) == (PWR_CR3_ULPEN)) ? 1UL : 0UL); +} + +/** + * @brief Enable the WakeUp PINx functionality + * @rmtoll CR3 EWUP1 LL_PWR_EnableWakeUpPin\n + * CR3 EWUP2 LL_PWR_EnableWakeUpPin\n + * CR3 EWUP3 LL_PWR_EnableWakeUpPin + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin) +{ + SET_BIT(PWR->CR3, WakeUpPin); +} + +/** + * @brief Disable the WakeUp PINx functionality + * @rmtoll CR3 EWUP1 LL_PWR_DisableWakeUpPin\n + * CR3 EWUP2 LL_PWR_DisableWakeUpPin\n + * CR3 EWUP3 LL_PWR_DisableWakeUpPin + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin) +{ + CLEAR_BIT(PWR->CR3, WakeUpPin); +} + +/** + * @brief Check if the WakeUp PINx functionality is enabled + * @rmtoll CR3 EWUP1 LL_PWR_IsEnabledWakeUpPin\n + * CR3 EWUP2 LL_PWR_IsEnabledWakeUpPin\n + * CR3 EWUP3 LL_PWR_IsEnabledWakeUpPin + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin) +{ + return ((READ_BIT(PWR->CR3, WakeUpPin) == (WakeUpPin)) ? 1UL : 0UL); +} + +/** + * @brief Set the resistor impedance + * @rmtoll CR4 VBRS LL_PWR_SetBattChargResistor + * @param Resistor This parameter can be one of the following values: + * @arg @ref LL_PWR_BATT_CHARG_RESISTOR_5K + * @arg @ref LL_PWR_BATT_CHARGRESISTOR_1_5K + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetBattChargResistor(uint32_t Resistor) +{ + MODIFY_REG(PWR->CR4, PWR_CR4_VBRS, Resistor); +} + +/** + * @brief Get the resistor impedance + * @rmtoll CR4 VBRS LL_PWR_GetBattChargResistor + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_BATT_CHARG_RESISTOR_5K + * @arg @ref LL_PWR_BATT_CHARGRESISTOR_1_5K + */ +__STATIC_INLINE uint32_t LL_PWR_GetBattChargResistor(void) +{ + return (uint32_t)(READ_BIT(PWR->CR4, PWR_CR4_VBRS)); +} + +/** + * @brief Enable battery charging + * @rmtoll CR4 VBE LL_PWR_EnableBatteryCharging + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableBatteryCharging(void) +{ + SET_BIT(PWR->CR4, PWR_CR4_VBE); +} + +/** + * @brief Disable battery charging + * @rmtoll CR4 VBE LL_PWR_DisableBatteryCharging + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableBatteryCharging(void) +{ + CLEAR_BIT(PWR->CR4, PWR_CR4_VBE); +} + +/** + * @brief Check if battery charging is enabled + * @rmtoll CR4 VBE LL_PWR_IsEnabledBatteryCharging + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledBatteryCharging(void) +{ + return ((READ_BIT(PWR->CR4, PWR_CR4_VBE) == (PWR_CR4_VBE)) ? 1UL : 0UL); +} + +/** + * @brief Set the Wake-Up pin polarity low for the event detection + * @rmtoll CR4 WP1 LL_PWR_SetWakeUpPinPolarityLow\n + * CR4 WP2 LL_PWR_SetWakeUpPinPolarityLow\n + * CR4 WP3 LL_PWR_SetWakeUpPinPolarityLow + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityLow(uint32_t WakeUpPin) +{ + SET_BIT(PWR->CR4, WakeUpPin); +} + +/** + * @brief Set the Wake-Up pin polarity high for the event detection + * @rmtoll CR4 WP1 LL_PWR_SetWakeUpPinPolarityHigh\n + * CR4 WP2 LL_PWR_SetWakeUpPinPolarityHigh\n + * CR4 WP3 LL_PWR_SetWakeUpPinPolarityHigh + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityHigh(uint32_t WakeUpPin) +{ + CLEAR_BIT(PWR->CR4, WakeUpPin); +} + +/** + * @brief Get the Wake-Up pin polarity for the event detection + * @rmtoll CR4 WP1 LL_PWR_IsWakeUpPinPolarityLow\n + * CR4 WP2 LL_PWR_IsWakeUpPinPolarityLow\n + * CR4 WP3 LL_PWR_IsWakeUpPinPolarityLow + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsWakeUpPinPolarityLow(uint32_t WakeUpPin) +{ + return ((READ_BIT(PWR->CR4, WakeUpPin) == (WakeUpPin)) ? 1UL : 0UL); +} + +/** + * @brief Enable GPIO pull-up state in Standby and Shutdown modes + * @note Some pins are not configurable for pulling in Standby and Shutdown + * modes. Refer to reference manual for available pins and ports. + * @rmtoll PUCRA PU0-15 LL_PWR_EnableGPIOPullUp\n + * PUCRB PU0-15 LL_PWR_EnableGPIOPullUp\n + * PUCRC PU0-15 LL_PWR_EnableGPIOPullUp\n + * PUCRH PU0-15 LL_PWR_EnableGPIOPullUp + * @param GPIO This parameter can be one of the following values: + * @arg @ref LL_PWR_GPIO_A + * @arg @ref LL_PWR_GPIO_B + * @arg @ref LL_PWR_GPIO_C + * @arg @ref LL_PWR_GPIO_H + * @param GPIONumber This parameter can be one of the following values: + * @arg @ref LL_PWR_GPIO_BIT_0 + * @arg @ref LL_PWR_GPIO_BIT_1 + * @arg @ref LL_PWR_GPIO_BIT_2 + * @arg @ref LL_PWR_GPIO_BIT_3 + * @arg @ref LL_PWR_GPIO_BIT_4 + * @arg @ref LL_PWR_GPIO_BIT_5 + * @arg @ref LL_PWR_GPIO_BIT_6 + * @arg @ref LL_PWR_GPIO_BIT_7 + * @arg @ref LL_PWR_GPIO_BIT_8 + * @arg @ref LL_PWR_GPIO_BIT_9 + * @arg @ref LL_PWR_GPIO_BIT_10 + * @arg @ref LL_PWR_GPIO_BIT_11 + * @arg @ref LL_PWR_GPIO_BIT_12 + * @arg @ref LL_PWR_GPIO_BIT_13 + * @arg @ref LL_PWR_GPIO_BIT_14 + * @arg @ref LL_PWR_GPIO_BIT_15 + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber) +{ + SET_BIT(*((__IO uint32_t *)GPIO), GPIONumber); +} + +/** + * @brief Disable GPIO pull-up state in Standby and Shutdown modes + * @note Some pins are not configurable for pulling in Standby and Shutdown + * modes. Refer to reference manual for available pins and ports. + * @rmtoll PUCRA PU0-15 LL_PWR_DisableGPIOPullUp\n + * PUCRB PU0-15 LL_PWR_DisableGPIOPullUp\n + * PUCRC PU0-15 LL_PWR_DisableGPIOPullUp\n + * PUCRH PU0-15 LL_PWR_DisableGPIOPullUp + * @param GPIO This parameter can be one of the following values: + * @arg @ref LL_PWR_GPIO_A + * @arg @ref LL_PWR_GPIO_B + * @arg @ref LL_PWR_GPIO_C + * @arg @ref LL_PWR_GPIO_H + * @param GPIONumber This parameter can be one of the following values: + * @arg @ref LL_PWR_GPIO_BIT_0 + * @arg @ref LL_PWR_GPIO_BIT_1 + * @arg @ref LL_PWR_GPIO_BIT_2 + * @arg @ref LL_PWR_GPIO_BIT_3 + * @arg @ref LL_PWR_GPIO_BIT_4 + * @arg @ref LL_PWR_GPIO_BIT_5 + * @arg @ref LL_PWR_GPIO_BIT_6 + * @arg @ref LL_PWR_GPIO_BIT_7 + * @arg @ref LL_PWR_GPIO_BIT_8 + * @arg @ref LL_PWR_GPIO_BIT_9 + * @arg @ref LL_PWR_GPIO_BIT_10 + * @arg @ref LL_PWR_GPIO_BIT_11 + * @arg @ref LL_PWR_GPIO_BIT_12 + * @arg @ref LL_PWR_GPIO_BIT_13 + * @arg @ref LL_PWR_GPIO_BIT_14 + * @arg @ref LL_PWR_GPIO_BIT_15 + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber) +{ + CLEAR_BIT(*((__IO uint32_t *)GPIO), GPIONumber); +} + +/** + * @brief Check if GPIO pull-up state is enabled + * @rmtoll PUCRA PU0-15 LL_PWR_IsEnabledGPIOPullUp\n + * PUCRB PU0-15 LL_PWR_IsEnabledGPIOPullUp\n + * PUCRC PU0-15 LL_PWR_IsEnabledGPIOPullUp\n + * PUCRH PU0-15 LL_PWR_IsEnabledGPIOPullUp + * @param GPIO This parameter can be one of the following values: + * @arg @ref LL_PWR_GPIO_A + * @arg @ref LL_PWR_GPIO_B + * @arg @ref LL_PWR_GPIO_C + * @arg @ref LL_PWR_GPIO_H + * @param GPIONumber This parameter can be one of the following values: + * @arg @ref LL_PWR_GPIO_BIT_0 + * @arg @ref LL_PWR_GPIO_BIT_1 + * @arg @ref LL_PWR_GPIO_BIT_2 + * @arg @ref LL_PWR_GPIO_BIT_3 + * @arg @ref LL_PWR_GPIO_BIT_4 + * @arg @ref LL_PWR_GPIO_BIT_5 + * @arg @ref LL_PWR_GPIO_BIT_6 + * @arg @ref LL_PWR_GPIO_BIT_7 + * @arg @ref LL_PWR_GPIO_BIT_8 + * @arg @ref LL_PWR_GPIO_BIT_9 + * @arg @ref LL_PWR_GPIO_BIT_10 + * @arg @ref LL_PWR_GPIO_BIT_11 + * @arg @ref LL_PWR_GPIO_BIT_12 + * @arg @ref LL_PWR_GPIO_BIT_13 + * @arg @ref LL_PWR_GPIO_BIT_14 + * @arg @ref LL_PWR_GPIO_BIT_15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber) +{ + return ((READ_BIT(*((__IO uint32_t *)(GPIO)), GPIONumber) == (GPIONumber)) ? 1UL : 0UL); +} + +/** + * @brief Enable GPIO pull-down state in Standby and Shutdown modes + * @note Some pins are not configurable for pulling in Standby and Shutdown + * modes. Refer to reference manual for available pins and ports. + * @rmtoll PDCRA PD0-15 LL_PWR_EnableGPIOPullDown\n + * PDCRB PD0-15 LL_PWR_EnableGPIOPullDown\n + * PDCRC PD0-15 LL_PWR_EnableGPIOPullDown\n + * PDCRH PD0-15 LL_PWR_EnableGPIOPullDown + * @param GPIO This parameter can be one of the following values: + * @arg @ref LL_PWR_GPIO_A + * @arg @ref LL_PWR_GPIO_B + * @arg @ref LL_PWR_GPIO_C + * @arg @ref LL_PWR_GPIO_H + * @param GPIONumber This parameter can be one of the following values: + * @arg @ref LL_PWR_GPIO_BIT_0 + * @arg @ref LL_PWR_GPIO_BIT_1 + * @arg @ref LL_PWR_GPIO_BIT_2 + * @arg @ref LL_PWR_GPIO_BIT_3 + * @arg @ref LL_PWR_GPIO_BIT_4 + * @arg @ref LL_PWR_GPIO_BIT_5 + * @arg @ref LL_PWR_GPIO_BIT_6 + * @arg @ref LL_PWR_GPIO_BIT_7 + * @arg @ref LL_PWR_GPIO_BIT_8 + * @arg @ref LL_PWR_GPIO_BIT_9 + * @arg @ref LL_PWR_GPIO_BIT_10 + * @arg @ref LL_PWR_GPIO_BIT_11 + * @arg @ref LL_PWR_GPIO_BIT_12 + * @arg @ref LL_PWR_GPIO_BIT_13 + * @arg @ref LL_PWR_GPIO_BIT_14 + * @arg @ref LL_PWR_GPIO_BIT_15 + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber) +{ + SET_BIT(*((__IO uint32_t *)(GPIO + 4U)), GPIONumber); +} + +/** + * @brief Disable GPIO pull-down state in Standby and Shutdown modes + * @note Some pins are not configurable for pulling in Standby and Shutdown + * modes. Refer to reference manual for available pins and ports. + * @rmtoll PDCRA PD0-15 LL_PWR_DisableGPIOPullDown\n + * PDCRB PD0-15 LL_PWR_DisableGPIOPullDown\n + * PDCRC PD0-15 LL_PWR_DisableGPIOPullDown\n + * PDCRH PD0-15 LL_PWR_DisableGPIOPullDown + * @param GPIO This parameter can be one of the following values: + * @arg @ref LL_PWR_GPIO_A + * @arg @ref LL_PWR_GPIO_B + * @arg @ref LL_PWR_GPIO_C + * @arg @ref LL_PWR_GPIO_H + * @param GPIONumber This parameter can be one of the following values: + * @arg @ref LL_PWR_GPIO_BIT_0 + * @arg @ref LL_PWR_GPIO_BIT_1 + * @arg @ref LL_PWR_GPIO_BIT_2 + * @arg @ref LL_PWR_GPIO_BIT_3 + * @arg @ref LL_PWR_GPIO_BIT_4 + * @arg @ref LL_PWR_GPIO_BIT_5 + * @arg @ref LL_PWR_GPIO_BIT_6 + * @arg @ref LL_PWR_GPIO_BIT_7 + * @arg @ref LL_PWR_GPIO_BIT_8 + * @arg @ref LL_PWR_GPIO_BIT_9 + * @arg @ref LL_PWR_GPIO_BIT_10 + * @arg @ref LL_PWR_GPIO_BIT_11 + * @arg @ref LL_PWR_GPIO_BIT_12 + * @arg @ref LL_PWR_GPIO_BIT_13 + * @arg @ref LL_PWR_GPIO_BIT_14 + * @arg @ref LL_PWR_GPIO_BIT_15 + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber) +{ + CLEAR_BIT(*((__IO uint32_t *)(GPIO + 4U)), GPIONumber); +} + +/** + * @brief Check if GPIO pull-down state is enabled + * @rmtoll PDCRA PD0-15 LL_PWR_IsEnabledGPIOPullDown\n + * PDCRB PD0-15 LL_PWR_IsEnabledGPIOPullDown\n + * PDCRC PD0-15 LL_PWR_IsEnabledGPIOPullDown\n + * PDCRH PD0-15 LL_PWR_IsEnabledGPIOPullDown + * @param GPIO This parameter can be one of the following values: + * @arg @ref LL_PWR_GPIO_A + * @arg @ref LL_PWR_GPIO_B + * @arg @ref LL_PWR_GPIO_C + * @arg @ref LL_PWR_GPIO_H + * @param GPIONumber This parameter can be one of the following values: + * @arg @ref LL_PWR_GPIO_BIT_0 + * @arg @ref LL_PWR_GPIO_BIT_1 + * @arg @ref LL_PWR_GPIO_BIT_2 + * @arg @ref LL_PWR_GPIO_BIT_3 + * @arg @ref LL_PWR_GPIO_BIT_4 + * @arg @ref LL_PWR_GPIO_BIT_5 + * @arg @ref LL_PWR_GPIO_BIT_6 + * @arg @ref LL_PWR_GPIO_BIT_7 + * @arg @ref LL_PWR_GPIO_BIT_8 + * @arg @ref LL_PWR_GPIO_BIT_9 + * @arg @ref LL_PWR_GPIO_BIT_10 + * @arg @ref LL_PWR_GPIO_BIT_11 + * @arg @ref LL_PWR_GPIO_BIT_12 + * @arg @ref LL_PWR_GPIO_BIT_13 + * @arg @ref LL_PWR_GPIO_BIT_14 + * @arg @ref LL_PWR_GPIO_BIT_15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber) +{ + return ((READ_BIT(*((__IO uint32_t *)(GPIO + 4U)), GPIONumber) == (GPIONumber)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup PWR_LL_EF_Configuration_SMPS Configuration of SMPS + * @{ + */ + +/** + * @brief Set SMPS operating mode + * @note In case of a board without SMPS coil mounted, SMPS should not be activated. + * @rmtoll CR5 SMPSEN LL_PWR_SMPS_SetMode + * @param OperatingMode This parameter can be one of the following values: + * @arg @ref LL_PWR_SMPS_BYPASS + * @arg @ref LL_PWR_SMPS_STEP_DOWN + * @retval None + */ +__STATIC_INLINE void LL_PWR_SMPS_SetMode(uint32_t OperatingMode) +{ + MODIFY_REG(PWR->CR5, PWR_CR5_SMPSEN, OperatingMode); +} + +/** + * @brief Get SMPS operating mode + * @rmtoll CR5 SMPSEN LL_PWR_SMPS_GetMode + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_SMPS_BYPASS + * @arg @ref LL_PWR_SMPS_STEP_DOWN + */ +__STATIC_INLINE uint32_t LL_PWR_SMPS_GetMode(void) +{ + return (uint32_t)(READ_BIT(PWR->CR5, PWR_CR5_SMPSEN)); +} + +/** + * @brief Get SMPS effective operating mode + * @note SMPS operating mode can be changed by hardware, therefore + * requested operating mode can differ from effective low power mode. + * - dependency SubGhz Radio IP: can switch SMPS on for radio activity. + * @note In case of a board without SMPS coil mounted, SMPS should not be activated + * and this function is not relevant. + * @rmtoll SR2 SMPSRDY LL_PWR_SMPS_GetEffectiveMode + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_SMPS_BYPASS + * @arg @ref LL_PWR_SMPS_STEP_DOWN + */ +__STATIC_INLINE uint32_t LL_PWR_SMPS_GetEffectiveMode(void) +{ + /* Return a value corresponding to definition of literals */ + /* LL_PWR_SMPS_BYPASS or LL_PWR_SMPS_STEP_DOWN. */ + return (uint32_t)(READ_BIT(PWR->SR2, PWR_SR2_SMPSRDY) << (PWR_CR5_SMPSEN_Pos - PWR_SR2_SMPSRDY_Pos)); +} + +/** + * @brief SMPS step down converter enable + * @note This function can be used for specific usage of the SMPS, + * for general usage of the SMPS the function + * @ref LL_PWR_SMPS_SetMode() should be used instead. + * @rmtoll CR5 SMPSEN LL_PWR_SMPS_Enable + * @retval None + */ +__STATIC_INLINE void LL_PWR_SMPS_Enable(void) +{ + SET_BIT(PWR->CR5, PWR_CR5_SMPSEN); +} + +/** + * @brief SMPS step down converter enable + * @note This function can be used for specific usage of the SMPS, + * for general usage of the SMPS the function + * @ref LL_PWR_SMPS_SetMode() should be used instead. + * @rmtoll CR5 SMPSEN LL_PWR_SMPS_Disable + * @retval None + */ +__STATIC_INLINE void LL_PWR_SMPS_Disable(void) +{ + CLEAR_BIT(PWR->CR5, PWR_CR5_SMPSEN); +} + +/** + * @brief Check if the SMPS step down converter is enabled + * @rmtoll CR5 SMPSEN LL_PWR_SMPS_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_SMPS_IsEnabled(void) +{ + return ((READ_BIT(PWR->CR5, PWR_CR5_SMPSEN) == (PWR_CR5_SMPSEN)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup PWR_LL_EF_Configuration_Radio Configuration of radio + * @{ + */ + +/** + * @brief Set radio busy signal polarity + * @rmtoll CR4 RFBUSYP LL_PWR_SetRadioBusyPolarity + * @param RadioBusyPolarity This parameter can be one of the following values: + * @arg @ref LL_PWR_RADIO_BUSY_POLARITY_RISING + * @arg @ref LL_PWR_RADIO_BUSY_POLARITY_FALLING + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetRadioBusyPolarity(uint32_t RadioBusyPolarity) +{ + MODIFY_REG(PWR->CR4, PWR_CR4_WRFBUSYP, RadioBusyPolarity); +} + +/** + * @brief Get radio busy signal polarity + * @rmtoll CR4 RFBUSYP LL_PWR_GetRadioBusyPolarity + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_RADIO_BUSY_POLARITY_RISING + * @arg @ref LL_PWR_RADIO_BUSY_POLARITY_FALLING + */ +__STATIC_INLINE uint32_t LL_PWR_GetRadioBusyPolarity(void) +{ + return (uint32_t)(READ_BIT(PWR->CR4, PWR_CR4_WRFBUSYP)); +} + +/** + * @brief Set radio busy trigger action for CPU1: wake-up from low-power mode + * Standby. + * @note Signal polarity can be configured using function + * @ref LL_PWR_SetRadioBusyPolarity(). + * @rmtoll CR3 ERFBUSY LL_PWR_SetRadioBusyTrigger + * @param RadioBusyTrigger This parameter can be one of the following values: + * @arg @ref LL_PWR_RADIO_BUSY_TRIGGER_NONE + * @arg @ref LL_PWR_RADIO_BUSY_TRIGGER_WU_IT + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetRadioBusyTrigger(uint32_t RadioBusyTrigger) +{ + MODIFY_REG(PWR->CR3, PWR_CR3_EWRFBUSY, RadioBusyTrigger); +} + +/** + * @brief Get radio busy trigger action for CPU1: wake-up from low-power mode + * Standby. + * @rmtoll CR3 ERFBUSY LL_PWR_GetRadioBusyTrigger + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_RADIO_BUSY_TRIGGER_NONE + * @arg @ref LL_PWR_RADIO_BUSY_TRIGGER_WU_IT + */ +__STATIC_INLINE uint32_t LL_PWR_GetRadioBusyTrigger(void) +{ + return (uint32_t)(READ_BIT(PWR->CR3, PWR_CR3_EWRFBUSY)); +} + +/** + * @brief Set radio IRQ trigger action for CPU1: wake-up from low-power mode + * Standby. + * @rmtoll CR3 ERFIRQ LL_PWR_SetRadioIRQTrigger + * @param RadioIRQTrigger This parameter can be one of the following values: + * @arg @ref LL_PWR_RADIO_IRQ_TRIGGER_NONE + * @arg @ref LL_PWR_RADIO_IRQ_TRIGGER_WU_IT + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetRadioIRQTrigger(uint32_t RadioIRQTrigger) +{ + MODIFY_REG(PWR->CR3, PWR_CR3_EWRFIRQ, RadioIRQTrigger); +} + +/** + * @brief Get radio IRQ trigger action for CPU1: wake-up from low-power mode + * Standby. + * @rmtoll CR3 ERFIRQ LL_PWR_GetRadioIRQTrigger + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_RADIO_IRQ_TRIGGER_NONE + * @arg @ref LL_PWR_RADIO_IRQ_TRIGGER_WU_IT + */ +__STATIC_INLINE uint32_t LL_PWR_GetRadioIRQTrigger(void) +{ + return (uint32_t)(READ_BIT(PWR->CR3, PWR_CR3_EWRFIRQ)); +} + +/** + * @brief Set sub-GHz radio SPI NSS control source + * @rmtoll CR1 SUBGHZSPINSSSEL LL_PWR_SetSUBGHZSPI_NSSSource + * @param RadioSPI_NSSSource This parameter can be one of the following values: + * @arg @ref LL_PWR_SUBGHZSPI_NSS_SRC_SW + * @arg @ref LL_PWR_SUBGHZSPI_NSS_SRC_LPTIM3 + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetSUBGHZSPI_NSSSource(uint32_t RadioSPI_NSSSource) +{ + MODIFY_REG(PWR->CR1, PWR_CR1_SUBGHZSPINSSSEL, RadioSPI_NSSSource); +} + +/** + * @brief Get sub-GHz radio SPI NSS control source + * @rmtoll CR1 SUBGHZSPINSSSEL LL_PWR_GetSUBGHZSPI_NSSSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_SUBGHZSPI_NSS_SRC_SW + * @arg @ref LL_PWR_SUBGHZSPI_NSS_SRC_LPTIM3 + */ +__STATIC_INLINE uint32_t LL_PWR_GetSUBGHZSPI_NSSSource(void) +{ + return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_SUBGHZSPINSSSEL)); +} + +/** + * @brief Set sub-GHz radio SPI NSS at logical level high. + * @rmtoll SUBGHZSPICR NSS LL_PWR_UnselectSUBGHZSPI_NSS + * @retval None + */ +__STATIC_INLINE void LL_PWR_UnselectSUBGHZSPI_NSS(void) +{ + SET_BIT(PWR->SUBGHZSPICR, PWR_SUBGHZSPICR_NSS); +} + +/** + * @brief Set sub-GHz radio SPI NSS at logical level low. + * @rmtoll SUBGHZSPICR NSS LL_PWR_SelectSUBGHZSPI_NSS + * @retval None + */ +__STATIC_INLINE void LL_PWR_SelectSUBGHZSPI_NSS(void) +{ + CLEAR_BIT(PWR->SUBGHZSPICR, PWR_SUBGHZSPICR_NSS); +} + +/** + * @brief Check whether sub-GHz radio SPI NSS is at logical level high or low. + * @rmtoll SUBGHZSPICR NSS LL_PWR_IsSUBGHZSPI_NSS_Selected + * @retval State of bit (1 for SUBGHZSPI_NSS selected or 0 for SUBGHZSPI_NSS unselected). + */ +__STATIC_INLINE uint32_t LL_PWR_IsSUBGHZSPI_NSS_Selected(void) +{ + return ((READ_BIT(PWR->SUBGHZSPICR, PWR_SUBGHZSPICR_NSS) != (PWR_SUBGHZSPICR_NSS)) ? 1UL : 0UL); +} + +/** + * @} + */ + +#if defined(DUAL_CORE) +/** @defgroup PWR_LL_EF_Configuration_Radio_CPU2 Configuration of radio for CPU2 + * @{ + */ + +/** + * @brief Set radio busy trigger action for CPU2: wake-up from low-power mode, + * interruption. + * @note Signal polarity can be configured using function + * @ref LL_PWR_SetRadioBusyPolarity(). + * @rmtoll C2CR3 ERFBUSY LL_C2_PWR_SetRadioBusyTrigger + * @param RadioBusyTrigger This parameter can be one of the following values: + * @arg @ref LL_PWR_RADIO_BUSY_TRIGGER_NONE + * @arg @ref LL_PWR_RADIO_BUSY_TRIGGER_WU_IT + * @retval None + */ +__STATIC_INLINE void LL_C2_PWR_SetRadioBusyTrigger(uint32_t RadioBusyTrigger) +{ + MODIFY_REG(PWR->C2CR3, PWR_C2CR3_EWRFBUSY, RadioBusyTrigger); +} + +/** + * @brief Get radio busy trigger action for CPU2: wake-up from low-power mode, + * interruption. + * @rmtoll C2CR3 ERFBUSY LL_C2_PWR_GetRadioBusyTrigger + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_RADIO_BUSY_TRIGGER_NONE + * @arg @ref LL_PWR_RADIO_BUSY_TRIGGER_WU_IT + */ +__STATIC_INLINE uint32_t LL_C2_PWR_GetRadioBusyTrigger(void) +{ + /* Note: Bit shift performed for literals to be generic between CPU1 and CPU2 */ + return (uint32_t)(READ_BIT(PWR->C2CR3, PWR_C2CR3_EWRFBUSY)); +} + +/** + * @brief Set radio IRQ trigger action for CPU2: wake-up from low-power mode, + * interruption. + * @rmtoll C2CR3 ERFIRQ LL_C2_PWR_SetRadioIRQTrigger + * @param RadioIRQTrigger This parameter can be one of the following values: + * @arg @ref LL_PWR_RADIO_IRQ_TRIGGER_NONE + * @arg @ref LL_PWR_RADIO_IRQ_TRIGGER_WU_IT + * @retval None + */ +__STATIC_INLINE void LL_C2_PWR_SetRadioIRQTrigger(uint32_t RadioIRQTrigger) +{ + MODIFY_REG(PWR->C2CR3, PWR_C2CR3_EWRFIRQ, RadioIRQTrigger); +} + +/** + * @brief Get radio IRQ trigger action for CPU2: wake-up from low-power mode, + * interruption. + * @rmtoll C2CR3 ERFIRQ LL_C2_PWR_GetRadioIRQTrigger + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_RADIO_IRQ_TRIGGER_NONE + * @arg @ref LL_PWR_RADIO_IRQ_TRIGGER_WU_IT + */ +__STATIC_INLINE uint32_t LL_C2_PWR_GetRadioIRQTrigger(void) +{ + return (uint32_t)(READ_BIT(PWR->C2CR3, PWR_C2CR3_EWRFIRQ)); +} + +/** + * @} + */ + +/** @defgroup PWR_LL_EF_Configuration_Multicore Configuration of multicore, intended to be executed by CPU1 + * @{ + */ + +/** + * @brief Boot CPU2 after reset or wakeup from Stop or Standby modes. + * @note CPU2 can boot from configuration of this function or from + * an illegal access. For information of boot source, + * refer to function @ref LL_PWR_IsActiveFlag_C2BOOTS(). + * @rmtoll CR4 C2BOOT LL_PWR_EnableBootC2 + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableBootC2(void) +{ + SET_BIT(PWR->CR4, PWR_CR4_C2BOOT); +} + +/** + * @brief Do not allow CPU2 to boot after reset or wakeup from Stop or Standby + * modes. + * @rmtoll CR4 C2BOOT LL_PWR_DisableBootC2 + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableBootC2(void) +{ + CLEAR_BIT(PWR->CR4, PWR_CR4_C2BOOT); +} + +/** + * @brief Check if bit to boot CPU2 after reset or wakeup from Stop or Standby + * modes is set + * @note CPU2 can boot from configuration of this function or from + * an illegal access. For information of boot source, + * refer to function @ref LL_PWR_IsActiveFlag_C2BOOTS(). + * @rmtoll CR4 C2BOOT LL_PWR_IsEnabledBootC2 + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledBootC2(void) +{ + return ((READ_BIT(PWR->CR4, PWR_CR4_C2BOOT) == (PWR_CR4_C2BOOT)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup PWR_LL_EF_Configuration_CPU2 Configuration of CPU2, intended to be executed by CPU2 + * @{ + */ + +/** + * @brief Set Low-Power mode for CPU2 + * @rmtoll C2CR1 LPMS LL_C2_PWR_SetPowerMode + * @param LowPowerMode This parameter can be one of the following values: + * @arg @ref LL_PWR_MODE_STOP0 + * @arg @ref LL_PWR_MODE_STOP1 + * @arg @ref LL_PWR_MODE_STOP2 + * @arg @ref LL_PWR_MODE_STANDBY + * @arg @ref LL_PWR_MODE_SHUTDOWN + * @retval None + */ +__STATIC_INLINE void LL_C2_PWR_SetPowerMode(uint32_t LowPowerMode) +{ + MODIFY_REG(PWR->C2CR1, PWR_C2CR1_LPMS, LowPowerMode); +} + +/** + * @brief Get Low-Power mode for CPU2 + * @rmtoll C2CR1 LPMS LL_C2_PWR_GetPowerMode + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_MODE_STOP0 + * @arg @ref LL_PWR_MODE_STOP1 + * @arg @ref LL_PWR_MODE_STOP2 + * @arg @ref LL_PWR_MODE_STANDBY + * @arg @ref LL_PWR_MODE_SHUTDOWN + */ +__STATIC_INLINE uint32_t LL_C2_PWR_GetPowerMode(void) +{ + return (uint32_t)(READ_BIT(PWR->C2CR1, PWR_C2CR1_LPMS)); +} + +/** + * @brief Set flash power-down mode during low-power run mode for CPU2 + * @rmtoll C2CR1 FPDR LL_C2_PWR_SetFlashPowerModeLPRun + * @param FlashLowPowerMode This parameter can be one of the following values: + * @arg @ref LL_PWR_FLASH_LPRUN_MODE_IDLE + * @arg @ref LL_PWR_FLASH_LPRUN_MODE_POWER_DOWN + * @retval None + */ +__STATIC_INLINE void LL_C2_PWR_SetFlashPowerModeLPRun(uint32_t FlashLowPowerMode) +{ + /* Unlock bit FPDR */ + WRITE_REG(PWR->C2CR1, PWR_FLASH_POWER_MODE_UNLOCK_CODE); + + /* Update bit FPDR */ + MODIFY_REG(PWR->C2CR1, PWR_C2CR1_FPDR, FlashLowPowerMode); +} + +/** + * @brief Get flash power-down mode during low-power run mode for CPU2 + * @rmtoll C2CR1 FPDR LL_C2_PWR_GetFlashPowerModeLPRun + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_FLASH_LPRUN_MODE_IDLE + * @arg @ref LL_PWR_FLASH_LPRUN_MODE_POWER_DOWN + */ +__STATIC_INLINE uint32_t LL_C2_PWR_GetFlashPowerModeLPRun(void) +{ + return (uint32_t)(READ_BIT(PWR->C2CR1, PWR_C2CR1_FPDR)); +} + +/** + * @brief Set flash power-down mode during sleep mode for CPU2 + * @rmtoll C2CR1 FPDS LL_C2_PWR_SetFlashPowerModeSleep + * @param FlashLowPowerMode This parameter can be one of the following values: + * @arg @ref LL_PWR_FLASH_SLEEP_MODE_IDLE + * @arg @ref LL_PWR_FLASH_SLEEP_MODE_POWER_DOWN + * @retval None + */ +__STATIC_INLINE void LL_C2_PWR_SetFlashPowerModeSleep(uint32_t FlashLowPowerMode) +{ + MODIFY_REG(PWR->C2CR1, PWR_C2CR1_FPDS, FlashLowPowerMode); +} + +/** + * @brief Get flash power-down mode during sleep mode for CPU2 + * @rmtoll C2CR1 FPDS LL_C2_PWR_GetFlashPowerModeSleep + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_FLASH_SLEEP_MODE_IDLE + * @arg @ref LL_PWR_FLASH_SLEEP_MODE_POWER_DOWN + */ +__STATIC_INLINE uint32_t LL_C2_PWR_GetFlashPowerModeSleep(void) +{ + return (uint32_t)(READ_BIT(PWR->C2CR1, PWR_C2CR1_FPDS)); +} + + +/** + * @brief Enable Internal Wake-up line for CPU2 + * @rmtoll C2CR3 EIWUL LL_C2_PWR_EnableInternWU + * @retval None + */ +__STATIC_INLINE void LL_C2_PWR_EnableInternWU(void) +{ + SET_BIT(PWR->C2CR3, PWR_C2CR3_EIWUL); +} + +/** + * @brief Disable Internal Wake-up line for CPU2 + * @rmtoll C2CR3 EIWUL LL_C2_PWR_DisableInternWU + * @retval None + */ +__STATIC_INLINE void LL_C2_PWR_DisableInternWU(void) +{ + CLEAR_BIT(PWR->C2CR3, PWR_C2CR3_EIWUL); +} + +/** + * @brief Check if Internal Wake-up line is enabled for CPU2 + * @rmtoll C2CR3 EIWUL LL_C2_PWR_IsEnabledInternWU + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C2_PWR_IsEnabledInternWU(void) +{ + return ((READ_BIT(PWR->C2CR3, PWR_C2CR3_EIWUL) == (PWR_C2CR3_EIWUL)) ? 1UL : 0UL); +} + +/** + * @brief Enable the WakeUp PINx functionality + * @rmtoll C2CR3 EWUP1 LL_C2_PWR_EnableWakeUpPin\n + * C2CR3 EWUP2 LL_C2_PWR_EnableWakeUpPin\n + * C2CR3 EWUP3 LL_C2_PWR_EnableWakeUpPin + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 + * @retval None + */ +__STATIC_INLINE void LL_C2_PWR_EnableWakeUpPin(uint32_t WakeUpPin) +{ + SET_BIT(PWR->C2CR3, WakeUpPin); +} + +/** + * @brief Disable the WakeUp PINx functionality + * @rmtoll C2CR3 EWUP1 LL_C2_PWR_EnableWakeUpPin\n + * C2CR3 EWUP2 LL_C2_PWR_EnableWakeUpPin\n + * C2CR3 EWUP3 LL_C2_PWR_EnableWakeUpPin + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 + * @retval None + */ +__STATIC_INLINE void LL_C2_PWR_DisableWakeUpPin(uint32_t WakeUpPin) +{ + CLEAR_BIT(PWR->C2CR3, WakeUpPin); +} + +/** + * @brief Check if the WakeUp PINx functionality is enabled + * @rmtoll C2CR3 EWUP1 LL_C2_PWR_EnableWakeUpPin\n + * C2CR3 EWUP2 LL_C2_PWR_EnableWakeUpPin\n + * C2CR3 EWUP3 LL_C2_PWR_EnableWakeUpPin + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 + * @retval None + */ +__STATIC_INLINE uint32_t LL_C2_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin) +{ + return ((READ_BIT(PWR->C2CR3, WakeUpPin) == (WakeUpPin)) ? 1UL : 0UL); +} + +/** + * @brief Enable pull-up and pull-down configuration for CPU2 + * @rmtoll C2CR3 APC LL_C2_PWR_EnablePUPDCfg + * @retval None + */ +__STATIC_INLINE void LL_C2_PWR_EnablePUPDCfg(void) +{ + SET_BIT(PWR->C2CR3, PWR_C2CR3_APC); +} + +/** + * @brief Disable pull-up and pull-down configuration for CPU2 + * @rmtoll C2CR3 APC LL_C2_PWR_DisablePUPDCfg + * @retval None + */ +__STATIC_INLINE void LL_C2_PWR_DisablePUPDCfg(void) +{ + CLEAR_BIT(PWR->C2CR3, PWR_C2CR3_APC); +} + +/** + * @brief Check if pull-up and pull-down configuration is enabled for CPU2 + * @rmtoll C2CR3 APC LL_C2_PWR_IsEnabledPUPDCfg + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C2_PWR_IsEnabledPUPDCfg(void) +{ + return ((READ_BIT(PWR->C2CR3, PWR_C2CR3_APC) == (PWR_C2CR3_APC)) ? 1UL : 0UL); +} + +/** + * @brief Enable wake-up power voltage detection with trigger for CPU2 + * @note Wake-up power voltage detection status can be checked + * using function @ref LL_PWR_IsActiveFlag_WPVD(). + * @rmtoll C2CR3 EWPVD LL_C2_PWR_EnableWPVD + * @retval None + */ +__STATIC_INLINE void LL_C2_PWR_EnableWPVD(void) +{ + SET_BIT(PWR->C2CR3, PWR_C2CR3_EWPVD); +} + +/** + * @brief Disable wake-up power voltage detection with trigger for CPU2 + * @rmtoll C2CR3 EWPVD LL_C2_PWR_DisableWPVD + * @retval None + */ +__STATIC_INLINE void LL_C2_PWR_DisableWPVD(void) +{ + CLEAR_BIT(PWR->C2CR3, PWR_C2CR3_EWPVD); +} + +/** + * @brief Check if wake-up power voltage detection is enabled with trigger for CPU2 + * @rmtoll C2CR3 EWPVD LL_C2_PWR_IsEnabledWPVD + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C2_PWR_IsEnabledWPVD(void) +{ + return ((READ_BIT(PWR->C2CR3, PWR_C2CR3_EWPVD) == (PWR_C2CR3_EWPVD)) ? 1UL : 0UL); +} + +/** + * @brief Enable CPU2 wake-up from low-power mode on illegal access occurrence + * @note Can be configured from CPU2 only + * @rmtoll SECCFGR C2EWILA LL_PWR_C2_EnableWakeUp_ILAC + * @retval None + */ +__STATIC_INLINE void LL_PWR_C2_EnableWakeUp_ILAC(void) +{ + SET_BIT(PWR->SECCFGR, PWR_SECCFGR_C2EWILA); +} + +/** + * @brief Disable CPU2 wake-up from low-power mode on illegal access occurrence + * @note Can be configured from CPU2 only + * @rmtoll SECCFGR C2EWILA LL_PWR_C2_DisableWakeUp_ILAC + * @retval None + */ +__STATIC_INLINE void LL_PWR_C2_DisableWakeUp_ILAC(void) +{ + CLEAR_BIT(PWR->SECCFGR, PWR_SECCFGR_C2EWILA); +} + +/** + * @brief Check if bit to wake-up CPU2 from low-power mode on illegal access + * occurrence is set + * @note Can be used from CPU2 only + * @rmtoll SECCFGR C2EWILA LL_PWR_C2_IsEnabledWakeUp_ILAC + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_PWR_C2_IsEnabledWakeUp_ILAC(void) +{ + return ((READ_BIT(PWR->SECCFGR, PWR_SECCFGR_C2EWILA) == (PWR_SECCFGR_C2EWILA)) ? 1UL : 0UL); +} +#endif /* DUAL_CORE */ + +/** + * @} + */ + +/** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management + * @{ + */ + +/** + * @brief Get Internal Wake-up line Flag + * @rmtoll SR1 WUFI LL_PWR_IsActiveFlag_InternWU + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_InternWU(void) +{ + return ((READ_BIT(PWR->SR1, PWR_SR1_WUFI) == (PWR_SR1_WUFI)) ? 1UL : 0UL); +} + +/** + * @brief Get Wake-up Flag 3 + * @rmtoll SR1 WUF3 LL_PWR_IsActiveFlag_WU3 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU3(void) +{ + return ((READ_BIT(PWR->SR1, PWR_SR1_WUF3) == (PWR_SR1_WUF3)) ? 1UL : 0UL); +} + +/** + * @brief Get Wake-up Flag 2 + * @rmtoll SR1 WUF2 LL_PWR_IsActiveFlag_WU2 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU2(void) +{ + return ((READ_BIT(PWR->SR1, PWR_SR1_WUF2) == (PWR_SR1_WUF2)) ? 1UL : 0UL); +} + +/** + * @brief Get Wake-up Flag 1 + * @rmtoll SR1 WUF1 LL_PWR_IsActiveFlag_WU1 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU1(void) +{ + return ((READ_BIT(PWR->SR1, PWR_SR1_WUF1) == (PWR_SR1_WUF1)) ? 1UL : 0UL); +} + +/** + * @brief Clear Wake-up Flags + * @rmtoll SCR CWUF LL_PWR_ClearFlag_WU + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_WU(void) +{ + WRITE_REG(PWR->SCR, PWR_SCR_CWUF); +} + +/** + * @brief Clear Wake-up Flag 3 + * @rmtoll SCR CWUF3 LL_PWR_ClearFlag_WU3 + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_WU3(void) +{ + WRITE_REG(PWR->SCR, PWR_SCR_CWUF3); +} + +/** + * @brief Clear Wake-up Flag 2 + * @rmtoll SCR CWUF2 LL_PWR_ClearFlag_WU2 + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_WU2(void) +{ + WRITE_REG(PWR->SCR, PWR_SCR_CWUF2); +} + +/** + * @brief Clear Wake-up Flag 1 + * @rmtoll SCR CWUF1 LL_PWR_ClearFlag_WU1 + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_WU1(void) +{ + WRITE_REG(PWR->SCR, PWR_SCR_CWUF1); +} + +/** + * @brief Indicate whether VDDA voltage is below or above PVM3 threshold + * @rmtoll SR2 PVMO3 LL_PWR_IsActiveFlag_PVMO3 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO3(void) +{ + return ((READ_BIT(PWR->SR2, PWR_SR2_PVMO3) == (PWR_SR2_PVMO3)) ? 1UL : 0UL); +} + +/** + * @brief Indicate whether VDD voltage is below or above the selected PVD threshold + * @rmtoll SR2 PVDO LL_PWR_IsActiveFlag_PVDO + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void) +{ + return ((READ_BIT(PWR->SR2, PWR_SR2_PVDO) == (PWR_SR2_PVDO)) ? 1UL : 0UL); +} + +/** + * @brief Indicate whether supply voltage is below radio operating level. + * @rmtoll SR2 RFEOLF LL_PWR_IsActiveFlag_RFEOL + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_RFEOL(void) +{ + return ((READ_BIT(PWR->SR2, PWR_SR2_RFEOLF) == (PWR_SR2_RFEOLF)) ? 1UL : 0UL); +} + +/** + * @brief Indicate whether the regulator reached the selected voltage level + * @note Regulator voltage level is selected using function + * @ref LL_PWR_SetRegulVoltageScaling(). + * @rmtoll SR2 VOSF LL_PWR_IsActiveFlag_VOS + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VOS(void) +{ + return ((READ_BIT(PWR->SR2, PWR_SR2_VOSF) == (PWR_SR2_VOSF)) ? 1UL : 0UL); +} + +/** + * @brief Get wake-up power voltage detection flag + * @rmtoll SR1 WPVD LL_PWR_IsActiveFlag_WPVD + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WPVD(void) +{ + return ((READ_BIT(PWR->SR1, PWR_SR1_WPVDF) == (PWR_SR1_WPVDF)) ? 1UL : 0UL); +} + +/** + * @brief Clear wake-up power voltage detection flag + * @rmtoll SCR CWPVD LL_PWR_ClearFlag_WPVD + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_WPVD(void) +{ + WRITE_REG(PWR->SCR, PWR_SCR_CWPVDF); +} + +/** + * @brief Get main LDO ready flag + * @rmtoll SR2 LDORDY LL_PWR_IsActiveFlag_LDORDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_LDORDY(void) +{ + return ((READ_BIT(PWR->SR2, PWR_SR2_LDORDY) == (PWR_SR2_LDORDY)) ? 1UL : 0UL); +} + +/** + * @brief Indicate whether the regulator is ready in main mode or is in low-power mode + * @note Return value "0" means the main regulator is ready and used. Return value "1" means the low-power regulator is used. + * @rmtoll SR2 REGLPF LL_PWR_IsActiveFlag_REGLPF + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_REGLPF(void) +{ + return ((READ_BIT(PWR->SR2, PWR_SR2_REGLPF) == (PWR_SR2_REGLPF)) ? 1UL : 0UL); +} + +/** + * @brief Indicate whether the low-power regulator is ready after a power-on + * reset, Standby or Shutdown mode. + * @note If the Standby mode is entered while REGLPS bit is still + * cleared (i.e. backup SRAM2 disabled), the wakeup time + * from Standby mode may be increased. + * @note Take care, return value "0" means the regulator is ready. Return value "1" means the output voltage range is still changing. + * @rmtoll SR2 REGLPS LL_PWR_IsActiveFlag_REGLPS + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_REGLPS(void) +{ + return ((READ_BIT(PWR->SR2, PWR_SR2_REGLPS) == (PWR_SR2_REGLPS)) ? 1UL : 0UL); +} + +/** + * @brief Indicate whether the main regulator is supplied from the LDO or SMPS + * or directly supplied from VDD. + * @note Return value "0" for main regulator supplied directly from VDD, return value "1" for main regulator supplied directly from LDO or SMPS. + * @rmtoll SR2 REGMRS LL_PWR_IsActiveFlag_REGMRS + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_REGMRS(void) +{ + return ((READ_BIT(PWR->SR2, PWR_SR2_REGMRS) == (PWR_SR2_REGMRS)) ? 1UL : 0UL); +} + +/** + * @brief Indicate whether the flash memory is ready + * @rmtoll SR2 FLASHRDY LL_PWR_IsActiveFlag_FLASHRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_FLASHRDY(void) +{ + return ((READ_BIT(PWR->SR2, PWR_SR2_FLASHRDY) == (PWR_SR2_FLASHRDY)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup PWR_LL_EF_FLAG_Management_SMPS FLAG management for SMPS + * @{ + */ + +/** + * @brief Get SMPS ready flag + * @rmtoll SR1 SMPSRDY LL_PWR_IsActiveFlag_SMPSRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SMPSRDY(void) +{ + return ((READ_BIT(PWR->SR2, PWR_SR2_SMPSRDY) == (PWR_SR2_SMPSRDY)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup PWR_LL_EF_FLAG_Management_Radio FLAG management for radio + * @{ + */ + +/** + * @brief Get radio busy flag (triggered status: wake-up event + * or interruption occurred at least once. Can be cleared by software). + * @note This radio busy triggered status is based on radio busy masked + * signal. + * To get radio busy masked signal current status, use function + * @ref LL_PWR_IsActiveFlag_RFBUSYMS() + * @rmtoll SR1 RFBUSYF LL_PWR_IsActiveFlag_RFBUSY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_RFBUSY(void) +{ + return ((READ_BIT(PWR->SR1, PWR_SR1_WRFBUSYF) == (PWR_SR1_WRFBUSYF)) ? 1UL : 0UL); +} + +/** + * @brief Clear radio busy flag + * @rmtoll SCR CRFBUSYF LL_PWR_ClearFlag_RFBUSY + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_RFBUSY(void) +{ + WRITE_REG(PWR->SCR, PWR_SCR_CWRFBUSYF); +} + +/** + * @brief Get radio busy signal flag (current status: + * set and cleared by hardware reflecting the real time signal level). + * @note The get radio busy flag triggered status, use function + * @ref LL_PWR_IsActiveFlag_RFBUSY() + * @rmtoll SR2 RFBUSYS LL_PWR_IsActiveFlag_RFBUSYS + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_RFBUSYS(void) +{ + return ((READ_BIT(PWR->SR2, PWR_SR2_RFBUSYS) == (PWR_SR2_RFBUSYS)) ? 1UL : 0UL); +} + +/** + * @brief Get radio busy masked signal flag (current status: + * set and cleared by hardware reflecting the real time signal level). + * @note The get radio busy flag triggered status, use function + * @ref LL_PWR_IsActiveFlag_RFBUSY() + * @rmtoll SR2 RFBUSYMS LL_PWR_IsActiveFlag_RFBUSYMS + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_RFBUSYMS(void) +{ + return ((READ_BIT(PWR->SR2, PWR_SR2_RFBUSYMS) == (PWR_SR2_RFBUSYMS)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup PWR_LL_EF_FLAG_Management_Multicore FLAG management for multicore + * @{ + */ + +#if defined(DUAL_CORE) +/** + * @brief Get CPU2 hold interrupt flag + * @rmtoll SR1 C2HF LL_PWR_IsActiveFlag_C2H + * @retval State of bit: 0 or 1 (CPU2 wake-up request and C2BOOT disabled, + * (except for illegal access wake-up), + * refer to function @ref LL_PWR_EnableBootC2()). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_C2H(void) +{ + return ((READ_BIT(PWR->SR1, PWR_SR1_C2HF) == (PWR_SR1_C2HF)) ? 1UL : 0UL); +} + +/** + * @brief Get CPU2 boot or wake-up request source information + * @rmtoll SR2 C2BOOTS LL_PWR_IsActiveFlag_C2BOOTS + * @retval State of bit: 0 (boot from an illegal access event) + * or 1 (boot from a SW request from function @ref LL_PWR_EnableBootC2()). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_C2BOOTS(void) +{ + return ((READ_BIT(PWR->SR2, PWR_SR2_C2BOOTS) == (PWR_SR2_C2BOOTS)) ? 1UL : 0UL); +} +#endif /* DUAL_CORE */ + +/** + * @brief Get system Stop 0 or Stop 1 flag for CPU1 + * @rmtoll EXTSCR C1STOPF LL_PWR_IsActiveFlag_C1STOP + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_C1STOP(void) +{ + return ((READ_BIT(PWR->EXTSCR, PWR_EXTSCR_C1STOPF) == (PWR_EXTSCR_C1STOPF)) ? 1UL : 0UL); +} + +/** + * @brief Get system Stop 2 flag for CPU1 + * @rmtoll EXTSCR C1STOP2F LL_PWR_IsActiveFlag_C1STOP2 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_C1STOP2(void) +{ + return ((READ_BIT(PWR->EXTSCR, PWR_EXTSCR_C1STOP2F) == (PWR_EXTSCR_C1STOP2F)) ? 1UL : 0UL); +} + +/** + * @brief Get system Standby flag for CPU1 + * @rmtoll EXTSCR C1SBF LL_PWR_IsActiveFlag_C1SB + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_C1SB(void) +{ + return ((READ_BIT(PWR->EXTSCR, PWR_EXTSCR_C1SBF) == (PWR_EXTSCR_C1SBF)) ? 1UL : 0UL); +} + +/** + * @brief Get deepsleep mode for CPU1 + * @rmtoll EXTSCR C1DS LL_PWR_IsActiveFlag_C1DS + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_C1DS(void) +{ + return ((READ_BIT(PWR->EXTSCR, PWR_EXTSCR_C1DS) == (PWR_EXTSCR_C1DS)) ? 1UL : 0UL); +} + +#if defined(DUAL_CORE) +/** + * @brief System Stop 0 or Stop 1 flag for CPU2 + * @rmtoll EXTSCR C2STOPF LL_PWR_IsActiveFlag_C2STOP + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_C2STOP(void) +{ + return ((READ_BIT(PWR->EXTSCR, PWR_EXTSCR_C2STOPF) == (PWR_EXTSCR_C2STOPF)) ? 1UL : 0UL); +} + +/** + * @brief System Stop 2 flag for CPU2 + * @rmtoll EXTSCR C2STOP2F LL_PWR_IsActiveFlag_C2STOP2 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_C2STOP2(void) +{ + return ((READ_BIT(PWR->EXTSCR, PWR_EXTSCR_C2STOP2F) == (PWR_EXTSCR_C2STOP2F)) ? 1UL : 0UL); +} + +/** + * @brief System Standby flag for CPU2 + * @rmtoll EXTSCR C2SBF LL_PWR_IsActiveFlag_C2SB + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_C2SB(void) +{ + return ((READ_BIT(PWR->EXTSCR, PWR_EXTSCR_C2SBF) == (PWR_EXTSCR_C2SBF)) ? 1UL : 0UL); +} + +/** + * @brief Get deepsleep mode for CPU2 + * @rmtoll EXTSCR C2DS LL_PWR_IsActiveFlag_C2DS + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_C2DS(void) +{ + return ((READ_BIT(PWR->EXTSCR, PWR_EXTSCR_C2DS) == (PWR_EXTSCR_C2DS)) ? 1UL : 0UL); +} + +/** + * @brief Clear CPU2 hold interrupt flag + * @rmtoll SCR CC2HF LL_PWR_ClearFlag_C2H + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_C2H(void) +{ + WRITE_REG(PWR->SCR, PWR_SCR_CC2HF); +} +#endif /* DUAL_CORE */ + +/** + * @brief Clear standby and stop flags for CPU1 + * @rmtoll EXTSCR C1CSSF LL_PWR_ClearFlag_C1STOP_C1STB + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_C1STOP_C1STB(void) +{ + WRITE_REG(PWR->EXTSCR, PWR_EXTSCR_C1CSSF); +} + +#if defined(DUAL_CORE) +/** + * @brief Clear standby and stop flags for CPU2 + * @rmtoll EXTSCR C2CSSF LL_PWR_ClearFlag_C2STOP_C2STB + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_C2STOP_C2STB(void) +{ + WRITE_REG(PWR->EXTSCR, PWR_EXTSCR_C2CSSF); +} +#endif /* DUAL_CORE */ + +/** + * @} + */ + +#if defined(DUAL_CORE) +/** @defgroup PWR_LL_EF_IT_Management_Multicore PWR IT management for multicore + * @{ + */ + +/** + * @brief Enable CPU2 hold interrupt for CPU1 + * @rmtoll CR3 EC2H LL_PWR_EnableIT_HoldCPU2 + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableIT_HoldCPU2(void) +{ + SET_BIT(PWR->CR3, PWR_CR3_EC2H); +} + +/** + * @brief Disable CPU2 hold interrupt for CPU1 + * @rmtoll CR3 EC2H LL_PWR_DisableIT_HoldCPU2 + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableIT_HoldCPU2(void) +{ + CLEAR_BIT(PWR->CR3, PWR_CR3_EC2H); +} + +/** + * @brief Check if CPU2 hold interrupt is enabled for CPU2 + * @rmtoll CR3 EC2H LL_PWR_IsEnabledIT_HoldCPU2 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledIT_HoldCPU2(void) +{ + return ((READ_BIT(PWR->CR3, PWR_CR3_EC2H) == (PWR_CR3_EC2H)) ? 1UL : 0UL); +} + +/** + * @} + */ +#endif /* DUAL_CORE */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup PWR_LL_EF_Init De-initialization function + * @{ + */ +ErrorStatus LL_PWR_DeInit(void); +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* PWR */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32WLxx_LL_PWR_H */ + diff --git a/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h b/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h new file mode 100644 index 0000000..1febd50 --- /dev/null +++ b/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h @@ -0,0 +1,3440 @@ +/** + ****************************************************************************** + * @file stm32wlxx_ll_rcc.h + * @author MCD Application Team + * @brief Header file of RCC LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32WLxx_LL_RCC_H +#define __STM32WLxx_LL_RCC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wlxx.h" + +/** @addtogroup STM32WLxx_LL_Driver + * @{ + */ + +#if defined(RCC) + +/** @defgroup RCC_LL RCC + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @defgroup RCC_LL_Private_Variables RCC Private Variables + * @{ + */ + +#define HSE_CONTROL_UNLOCK_KEY 0xCAFECAFEU + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RCC_LL_Private_Macros RCC Private Macros + * @{ + */ +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RCC_LL_Exported_Types RCC Exported Types + * @{ + */ + +/** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure + * @{ + */ + +/** + * @brief RCC Clocks Frequency Structure + */ +typedef struct +{ + uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency */ + uint32_t HCLK1_Frequency; /*!< HCLK1 clock frequency */ +#if defined(DUAL_CORE) + uint32_t HCLK2_Frequency; /*!< HCLK2 clock frequency */ +#endif /* DUAL_CORE */ + uint32_t HCLK3_Frequency; /*!< HCLK3 clock frequency */ + uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency */ + uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency */ +} LL_RCC_ClocksTypeDef; + +/** + * @} + */ + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup RCC_LL_Exported_Constants RCC Exported Constants + * @{ + */ + +/** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation + * @brief Defines used to adapt values of different oscillators + * @note These values could be modified in the user environment according to + * HW set-up. + * @{ + */ +#if !defined (HSE_VALUE) +#define HSE_VALUE 32000000U /*!< Value of the HSE oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSI_VALUE) +#define HSI_VALUE 16000000U /*!< Value of the HSI oscillator in Hz */ +#endif /* HSI_VALUE */ + +#if !defined (LSE_VALUE) +#define LSE_VALUE 32768U /*!< Value of the LSE oscillator in Hz */ +#endif /* LSE_VALUE */ + +#if !defined (LSI_VALUE) +#define LSI_VALUE 32000U /*!< Value of the LSI oscillator in Hz */ +#endif /* LSI_VALUE */ + +#if !defined (EXTERNAL_CLOCK_VALUE) +#define EXTERNAL_CLOCK_VALUE 48000U /*!< Value of the I2S_CKIN external oscillator in Hz */ +#endif /* EXTERNAL_CLOCK_VALUE */ + +/** + * @} + */ + +/** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines + * @brief Flags defines which can be used with LL_RCC_WriteReg function + * @{ + */ +#define LL_RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC /*!< LSI Ready Interrupt Clear */ +#define LL_RCC_CICR_LSERDYC RCC_CICR_LSERDYC /*!< LSE Ready Interrupt Clear */ +#define LL_RCC_CICR_MSIRDYC RCC_CICR_MSIRDYC /*!< MSI Ready Interrupt Clear */ +#define LL_RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC /*!< HSI Ready Interrupt Clear */ +#define LL_RCC_CICR_HSERDYC RCC_CICR_HSERDYC /*!< HSE Ready Interrupt Clear */ +#define LL_RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC /*!< PLL Ready Interrupt Clear */ +#define LL_RCC_CICR_LSECSSC RCC_CICR_LSECSSC /*!< LSE Clock Security System Interrupt Clear */ +#define LL_RCC_CICR_CSSC RCC_CICR_CSSC /*!< Clock Security System Interrupt Clear */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_RCC_ReadReg function + * @{ + */ +#define LL_RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF /*!< LSI Ready Interrupt flag */ +#define LL_RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF /*!< LSE Ready Interrupt flag */ +#define LL_RCC_CIFR_MSIRDYF RCC_CIFR_MSIRDYF /*!< MSI Ready Interrupt flag */ +#define LL_RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF /*!< HSI Ready Interrupt flag */ +#define LL_RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF /*!< HSE Ready Interrupt flag */ +#define LL_RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF /*!< PLL Ready Interrupt flag */ +#define LL_RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF /*!< LSE Clock Security System Interrupt flag */ +#define LL_RCC_CIFR_CSSF RCC_CIFR_CSSF /*!< Clock Security System Interrupt flag */ +#define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF /*!< Low-Power reset flag */ +#define LL_RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF /*!< OBL reset flag */ +#define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF /*!< PIN reset flag */ +#define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /*!< Software Reset flag */ +#define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset flag */ +#define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag */ +#define LL_RCC_CSR_BORRSTF RCC_CSR_BORRSTF /*!< BOR reset flag */ +#define LL_RCC_CSR_RFILASTF RCC_CSR_RFILARSTF /*!< Radio illegal access flag */ + +/** + * @} + */ + +/** @defgroup RCC_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions + * @{ + */ +#define LL_RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE /*!< LSI Ready Interrupt Enable */ +#define LL_RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE /*!< LSE Ready Interrupt Enable */ +#define LL_RCC_CIER_MSIRDYIE RCC_CIER_MSIRDYIE /*!< MSI Ready Interrupt Enable */ +#define LL_RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE /*!< HSI Ready Interrupt Enable */ +#define LL_RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE /*!< HSE Ready Interrupt Enable */ +#define LL_RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE /*!< PLL Ready Interrupt Enable */ +#define LL_RCC_CIER_LSECSSIE RCC_CIER_LSECSSIE /*!< LSE CSS Interrupt Enable */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_LSEDRIVE LSE oscillator drive capability + * @{ + */ +#define LL_RCC_LSEDRIVE_LOW 0x00000000U /*!< Xtal mode lower driving capability */ +#define LL_RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0 /*!< Xtal mode medium low driving capability */ +#define LL_RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1 /*!< Xtal mode medium high driving capability */ +#define LL_RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< Xtal mode higher driving capability */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_MSIRANGE MSI clock ranges + * @{ + */ +#define LL_RCC_MSIRANGE_0 RCC_CR_MSIRANGE_0 /*!< MSI = 100 KHz */ +#define LL_RCC_MSIRANGE_1 RCC_CR_MSIRANGE_1 /*!< MSI = 200 KHz */ +#define LL_RCC_MSIRANGE_2 RCC_CR_MSIRANGE_2 /*!< MSI = 400 KHz */ +#define LL_RCC_MSIRANGE_3 RCC_CR_MSIRANGE_3 /*!< MSI = 800 KHz */ +#define LL_RCC_MSIRANGE_4 RCC_CR_MSIRANGE_4 /*!< MSI = 1 MHz */ +#define LL_RCC_MSIRANGE_5 RCC_CR_MSIRANGE_5 /*!< MSI = 2 MHz */ +#define LL_RCC_MSIRANGE_6 RCC_CR_MSIRANGE_6 /*!< MSI = 4 MHz */ +#define LL_RCC_MSIRANGE_7 RCC_CR_MSIRANGE_7 /*!< MSI = 8 MHz */ +#define LL_RCC_MSIRANGE_8 RCC_CR_MSIRANGE_8 /*!< MSI = 16 MHz */ +#define LL_RCC_MSIRANGE_9 RCC_CR_MSIRANGE_9 /*!< MSI = 24 MHz */ +#define LL_RCC_MSIRANGE_10 RCC_CR_MSIRANGE_10 /*!< MSI = 32 MHz */ +#define LL_RCC_MSIRANGE_11 RCC_CR_MSIRANGE_11 /*!< MSI = 48 MHz */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_MSISRANGE MSI range after Standby mode + * @{ + */ +#define LL_RCC_MSISRANGE_4 RCC_CSR_MSISRANGE_1 /*!< MSI = 1 MHz */ +#define LL_RCC_MSISRANGE_5 RCC_CSR_MSISRANGE_2 /*!< MSI = 2 MHz */ +#define LL_RCC_MSISRANGE_6 RCC_CSR_MSISRANGE_4 /*!< MSI = 4 MHz */ +#define LL_RCC_MSISRANGE_7 RCC_CSR_MSISRANGE_8 /*!< MSI = 8 MHz */ +/** + * @} + */ + + +/** @defgroup RCC_LL_EC_LSCO_CLKSOURCE LSCO Selection + * @{ + */ +#define LL_RCC_LSCO_CLKSOURCE_LSI 0x00000000U /*!< LSI selection for low speed clock */ +#define LL_RCC_LSCO_CLKSOURCE_LSE RCC_BDCR_LSCOSEL /*!< LSE selection for low speed clock */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch + * @{ + */ +#define LL_RCC_SYS_CLKSOURCE_MSI 0x00000000U /*!< MSI selection as system clock */ +#define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_0 /*!< HSI selection as system clock */ +#define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_1 /*!< HSE selection as system clock */ +#define LL_RCC_SYS_CLKSOURCE_PLL (RCC_CFGR_SW_1 | RCC_CFGR_SW_0) /*!< PLL selection as system clock */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status + * @{ + */ +#define LL_RCC_SYS_CLKSOURCE_STATUS_MSI 0x00000000U /*!< MSI used as system clock */ +#define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_0 /*!< HSI used as system clock */ +#define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_1 /*!< HSE used as system clock */ +#define LL_RCC_SYS_CLKSOURCE_STATUS_PLL (RCC_CFGR_SWS_1 | RCC_CFGR_SWS_0) /*!< PLL used as system clock */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler + * @{ + */ +#define LL_RCC_SYSCLK_DIV_1 0x00000000U /*!< SYSCLK not divided */ +#define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_3 /*!< SYSCLK divided by 2 */ +#define LL_RCC_SYSCLK_DIV_3 RCC_CFGR_HPRE_0 /*!< SYSCLK divided by 3 */ +#define LL_RCC_SYSCLK_DIV_4 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_0) /*!< SYSCLK divided by 4 */ +#define LL_RCC_SYSCLK_DIV_5 RCC_CFGR_HPRE_1 /*!< SYSCLK divided by 5 */ +#define LL_RCC_SYSCLK_DIV_6 (RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_0) /*!< SYSCLK divided by 6 */ +#define LL_RCC_SYSCLK_DIV_8 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_1) /*!< SYSCLK divided by 8 */ +#define LL_RCC_SYSCLK_DIV_10 (RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_1) /*!< SYSCLK divided by 10 */ +#define LL_RCC_SYSCLK_DIV_16 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_1 | RCC_CFGR_HPRE_0) /*!< SYSCLK divided by 16 */ +#define LL_RCC_SYSCLK_DIV_32 (RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_1 | RCC_CFGR_HPRE_0) /*!< SYSCLK divided by 32 */ +#define LL_RCC_SYSCLK_DIV_64 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2) /*!< SYSCLK divided by 64 */ +#define LL_RCC_SYSCLK_DIV_128 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_0) /*!< SYSCLK divided by 128 */ +#define LL_RCC_SYSCLK_DIV_256 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_1) /*!< SYSCLK divided by 256 */ +#define LL_RCC_SYSCLK_DIV_512 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_1 | RCC_CFGR_HPRE_0) /*!< SYSCLK divided by 512 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1) + * @{ + */ +#define LL_RCC_APB1_DIV_1 0x00000000U /*!< HCLK1 not divided */ +#define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE1_2 /*!< HCLK1 divided by 2 */ +#define LL_RCC_APB1_DIV_4 (RCC_CFGR_PPRE1_2 | RCC_CFGR_PPRE1_0) /*!< HCLK1 divided by 4 */ +#define LL_RCC_APB1_DIV_8 (RCC_CFGR_PPRE1_2 | RCC_CFGR_PPRE1_1) /*!< HCLK1 divided by 8 */ +#define LL_RCC_APB1_DIV_16 (RCC_CFGR_PPRE1_2 | RCC_CFGR_PPRE1_1 | RCC_CFGR_PPRE1_0) /*!< HCLK1 divided by 16 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_APB2_DIV APB high-speed prescaler (APB2) + * @{ + */ +#define LL_RCC_APB2_DIV_1 0x00000000U /*!< HCLK1 not divided */ +#define LL_RCC_APB2_DIV_2 RCC_CFGR_PPRE2_2 /*!< HCLK1 divided by 2 */ +#define LL_RCC_APB2_DIV_4 (RCC_CFGR_PPRE2_2 | RCC_CFGR_PPRE2_0) /*!< HCLK1 divided by 4 */ +#define LL_RCC_APB2_DIV_8 (RCC_CFGR_PPRE2_2 | RCC_CFGR_PPRE2_1) /*!< HCLK1 divided by 8 */ +#define LL_RCC_APB2_DIV_16 (RCC_CFGR_PPRE2_2 | RCC_CFGR_PPRE2_1 | RCC_CFGR_PPRE2_0) /*!< HCLK1 divided by 16 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_STOP_WAKEUPCLOCK Wakeup from Stop and CSS backup clock selection + * @{ + */ +#define LL_RCC_STOP_WAKEUPCLOCK_MSI 0x00000000U /*!< MSI selection after wake-up from STOP */ +#define LL_RCC_STOP_WAKEUPCLOCK_HSI RCC_CFGR_STOPWUCK /*!< HSI selection after wake-up from STOP */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_MCO1SOURCE MCO1 SOURCE selection + * @{ + */ +#define LL_RCC_MCO1SOURCE_NOCLOCK 0x00000000U /*!< MCO output disabled, no clock on MCO */ +#define LL_RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_0 /*!< SYSCLK selection as MCO1 source */ +#define LL_RCC_MCO1SOURCE_MSI RCC_CFGR_MCOSEL_1 /*!< MSI selection as MCO1 source */ +#define LL_RCC_MCO1SOURCE_HSI (RCC_CFGR_MCOSEL_0| RCC_CFGR_MCOSEL_1) /*!< HSI selection as MCO1 source */ +#define LL_RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_2 /*!< HSE after stabilization selection as MCO1 source */ +#define LL_RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_2) /*!< Main PLLR selection as MCO1 source */ +#define LL_RCC_MCO1SOURCE_LSI (RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSI selection as MCO1 source */ +#define LL_RCC_MCO1SOURCE_LSE RCC_CFGR_MCOSEL_3 /*!< LSE selection as MCO1 source */ +#define LL_RCC_MCO1SOURCE_PLLPCLK (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_2|RCC_CFGR_MCOSEL_3) /*!< Main PLLQ selection as MCO1 source */ +#define LL_RCC_MCO1SOURCE_PLLQCLK (RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2|RCC_CFGR_MCOSEL_3) /*!< Main PLLP selection as MCO1 source */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_MCO1_DIV MCO1 prescaler + * @{ + */ +#define LL_RCC_MCO1_DIV_1 0x00000000U /*!< MCO not divided */ +#define LL_RCC_MCO1_DIV_2 RCC_CFGR_MCOPRE_0 /*!< MCO divided by 2 */ +#define LL_RCC_MCO1_DIV_4 RCC_CFGR_MCOPRE_1 /*!< MCO divided by 4 */ +#define LL_RCC_MCO1_DIV_8 (RCC_CFGR_MCOPRE_1 | RCC_CFGR_MCOPRE_0) /*!< MCO divided by 8 */ +#define LL_RCC_MCO1_DIV_16 RCC_CFGR_MCOPRE_2 /*!< MCO divided by 16 */ +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency + * @{ + */ +#define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U /*!< No clock enabled for the peripheral */ +#define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /*!< Frequency cannot be provided as external clock */ +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** @defgroup RCC_LL_EC_USART1_CLKSOURCE USARTx CLKSOURCE + * @{ + */ +#define LL_RCC_USART1_CLKSOURCE_PCLK2 (RCC_CCIPR_USART1SEL << 16U) /*!< PCLK2 clock used as USART1 clock source */ +#define LL_RCC_USART1_CLKSOURCE_SYSCLK ((RCC_CCIPR_USART1SEL << 16U) | RCC_CCIPR_USART1SEL_0) /*!< SYSCLK clock used as USART1 clock source */ +#define LL_RCC_USART1_CLKSOURCE_HSI ((RCC_CCIPR_USART1SEL << 16U) | RCC_CCIPR_USART1SEL_1) /*!< HSI clock used as USART1 clock source */ +#define LL_RCC_USART1_CLKSOURCE_LSE ((RCC_CCIPR_USART1SEL << 16U) | RCC_CCIPR_USART1SEL) /*!< LSE clock used as USART1 clock source */ +#define LL_RCC_USART2_CLKSOURCE_PCLK1 (RCC_CCIPR_USART2SEL << 16U) /*!< PCLK1 clock used as USART2 clock source */ +#define LL_RCC_USART2_CLKSOURCE_SYSCLK ((RCC_CCIPR_USART2SEL << 16U) | RCC_CCIPR_USART2SEL_0) /*!< SYSCLK clock used as USART2 clock source */ +#define LL_RCC_USART2_CLKSOURCE_HSI ((RCC_CCIPR_USART2SEL << 16U) | RCC_CCIPR_USART2SEL_1) /*!< HSI clock used as USART2 clock source */ +#define LL_RCC_USART2_CLKSOURCE_LSE ((RCC_CCIPR_USART2SEL << 16U) | RCC_CCIPR_USART2SEL) /*!< LSE clock used as USART2 clock source */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_I2S2_CLKSOURCE Peripheral I2S clock source selection + * @{ + */ +#define LL_RCC_I2S2_CLKSOURCE_PLL RCC_CCIPR_I2S2SEL_0 /*!< PLL clock used as I2S2 clock source */ +#define LL_RCC_I2S2_CLKSOURCE_HSI RCC_CCIPR_I2S2SEL_1 /*!< HSI clock used as I2S2 clock source */ +#define LL_RCC_I2S2_CLKSOURCE_PIN RCC_CCIPR_I2S2SEL /*!< External clock used as I2S2 clock source */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_LPUART1_CLKSOURCE LPUART1 CLKSOURCE + * @{ + */ +#define LL_RCC_LPUART1_CLKSOURCE_PCLK1 0x00000000U /*!< PCLK1 selected as LPUART1 clock */ +#define LL_RCC_LPUART1_CLKSOURCE_SYSCLK RCC_CCIPR_LPUART1SEL_0 /*!< SYCLK selected as LPUART1 clock */ +#define LL_RCC_LPUART1_CLKSOURCE_HSI RCC_CCIPR_LPUART1SEL_1 /*!< HSI selected as LPUART1 clock */ +#define LL_RCC_LPUART1_CLKSOURCE_LSE RCC_CCIPR_LPUART1SEL /*!< LSE selected as LPUART1 clock */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_I2Cx_CLKSOURCE I2Cx CLKSOURCE + * @{ + */ +#define LL_RCC_I2C1_CLKSOURCE_PCLK1 (uint32_t)((RCC_CCIPR_I2C1SEL << 4) | (0x00000000U >> 4)) /*!< PCLK1 selected as I2C1 clock */ +#define LL_RCC_I2C1_CLKSOURCE_SYSCLK (uint32_t)((RCC_CCIPR_I2C1SEL << 4) | (RCC_CCIPR_I2C1SEL_0 >> 4)) /*!< SYSCLK selected as I2C1 clock */ +#define LL_RCC_I2C1_CLKSOURCE_HSI (uint32_t)((RCC_CCIPR_I2C1SEL << 4) | (RCC_CCIPR_I2C1SEL_1 >> 4)) /*!< HSI selected as I2C1 clock */ +#define LL_RCC_I2C2_CLKSOURCE_PCLK1 (uint32_t)((RCC_CCIPR_I2C2SEL << 4) | (0x00000000U >> 4)) /*!< PCLK1 selected as I2C2 clock */ +#define LL_RCC_I2C2_CLKSOURCE_SYSCLK (uint32_t)((RCC_CCIPR_I2C2SEL << 4) | (RCC_CCIPR_I2C2SEL_0 >> 4)) /*!< SYSCLK selected as I2C2 clock */ +#define LL_RCC_I2C2_CLKSOURCE_HSI (uint32_t)((RCC_CCIPR_I2C2SEL << 4) | (RCC_CCIPR_I2C2SEL_1 >> 4)) /*!< HSI selected as I2C2 clock */ +#define LL_RCC_I2C3_CLKSOURCE_PCLK1 (uint32_t)((RCC_CCIPR_I2C3SEL << 4) | (0x00000000U >> 4)) /*!< PCLK1 selected as I2C3 clock */ +#define LL_RCC_I2C3_CLKSOURCE_SYSCLK (uint32_t)((RCC_CCIPR_I2C3SEL << 4) | (RCC_CCIPR_I2C3SEL_0 >> 4)) /*!< SYSCLK selected as I2C3 clock */ +#define LL_RCC_I2C3_CLKSOURCE_HSI (uint32_t)((RCC_CCIPR_I2C3SEL << 4) | (RCC_CCIPR_I2C3SEL_1 >> 4)) /*!< HSI selected as I2C3 clock */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_LPTIMx_CLKSOURCE LPTIMx CLKSOURCE + * @{ + */ +#define LL_RCC_LPTIM1_CLKSOURCE_PCLK1 (uint32_t)(RCC_CCIPR_LPTIM1SEL | (0x00000000U >> 16)) /*!< PCLK1 selected as LPTIM1 clock */ +#define LL_RCC_LPTIM1_CLKSOURCE_LSI (uint32_t)(RCC_CCIPR_LPTIM1SEL | (RCC_CCIPR_LPTIM1SEL_0 >> 16)) /*!< LSI selected as LPTIM1 clock */ +#define LL_RCC_LPTIM1_CLKSOURCE_HSI (uint32_t)(RCC_CCIPR_LPTIM1SEL | (RCC_CCIPR_LPTIM1SEL_1 >> 16)) /*!< HSI selected as LPTIM1 clock */ +#define LL_RCC_LPTIM1_CLKSOURCE_LSE (uint32_t)(RCC_CCIPR_LPTIM1SEL | (RCC_CCIPR_LPTIM1SEL >> 16)) /*!< LSE selected as LPTIM1 clock */ +#define LL_RCC_LPTIM2_CLKSOURCE_PCLK1 (uint32_t)(RCC_CCIPR_LPTIM2SEL | (0x00000000U >> 16)) /*!< PCLK1 selected as LPTIM2 clock */ +#define LL_RCC_LPTIM2_CLKSOURCE_LSI (uint32_t)(RCC_CCIPR_LPTIM2SEL | (RCC_CCIPR_LPTIM2SEL_0 >> 16)) /*!< LSI selected as LPTIM2 clock */ +#define LL_RCC_LPTIM2_CLKSOURCE_HSI (uint32_t)(RCC_CCIPR_LPTIM2SEL | (RCC_CCIPR_LPTIM2SEL_1 >> 16)) /*!< HSI selected as LPTIM2 clock */ +#define LL_RCC_LPTIM2_CLKSOURCE_LSE (uint32_t)(RCC_CCIPR_LPTIM2SEL | (RCC_CCIPR_LPTIM2SEL >> 16)) /*!< LSE selected as LPTIM2 clock */ +#define LL_RCC_LPTIM3_CLKSOURCE_PCLK1 (uint32_t)(RCC_CCIPR_LPTIM3SEL | (0x00000000U >> 16)) /*!< PCLK1 selected as LPTIM3 clock */ +#define LL_RCC_LPTIM3_CLKSOURCE_LSI (uint32_t)(RCC_CCIPR_LPTIM3SEL | (RCC_CCIPR_LPTIM3SEL_0 >> 16)) /*!< LSI selected as LPTIM3 clock */ +#define LL_RCC_LPTIM3_CLKSOURCE_HSI (uint32_t)(RCC_CCIPR_LPTIM3SEL | (RCC_CCIPR_LPTIM3SEL_1 >> 16)) /*!< HSI selected as LPTIM3 clock */ +#define LL_RCC_LPTIM3_CLKSOURCE_LSE (uint32_t)(RCC_CCIPR_LPTIM3SEL | (RCC_CCIPR_LPTIM3SEL >> 16)) /*!< LSE selected as LPTIM3 clock */ + +/** + * @} + */ + +/** @defgroup RCC_LL_EC_ADC_CLKSRC ADC CLKSRC + * @{ + */ +#define LL_RCC_ADC_CLKSOURCE_NONE 0x00000000U /*!< no Clock used as ADC clock */ +#define LL_RCC_ADC_CLKSOURCE_HSI RCC_CCIPR_ADCSEL_0 /*!< HSI selected as ADC clock */ +#define LL_RCC_ADC_CLKSOURCE_PLL RCC_CCIPR_ADCSEL_1 /*!< PLL selected as ADC clock */ +#define LL_RCC_ADC_CLKSOURCE_SYSCLK RCC_CCIPR_ADCSEL /*!< SYSCLK selected as ADC clock */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_RNG_CLKSRC RNG CLKSRC + * @{ + */ +#define LL_RCC_RNG_CLKSOURCE_PLL 0x00000000U /*!< PLL selected as RNG Clock */ +#define LL_RCC_RNG_CLKSOURCE_LSI RCC_CCIPR_RNGSEL_0 /*!< LSI selected as RNG clock */ +#define LL_RCC_RNG_CLKSOURCE_LSE RCC_CCIPR_RNGSEL_1 /*!< LSE selected as RNG clock */ +#define LL_RCC_RNG_CLKSOURCE_MSI (RCC_CCIPR_RNGSEL_1 | RCC_CCIPR_RNGSEL_0) /*!< MSI selected as RNG clock */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_USARTx USARTx + * @{ + */ +#define LL_RCC_USART1_CLKSOURCE RCC_CCIPR_USART1SEL /*!< USART1 clock source selection bits */ +#define LL_RCC_USART2_CLKSOURCE RCC_CCIPR_USART2SEL /*!< USART2 clock source selection bits */ + +/** + * @} + */ + +/** @defgroup RCC_LL_EC_I2S2 Peripheral I2S get clock source + * @{ + */ +#define LL_RCC_I2S2_CLKSOURCE RCC_CCIPR_I2S2SEL /*!< I2S2 Clock source selection */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_LPUART1 LPUART1 + * @{ + */ +#define LL_RCC_LPUART1_CLKSOURCE RCC_CCIPR_LPUART1SEL /*!< LPUART1 clock source selection bits */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_I2Cx I2Cx + * @{ + */ +#define LL_RCC_I2C1_CLKSOURCE RCC_CCIPR_I2C1SEL /*!< I2C1 clock source selection bits */ +#define LL_RCC_I2C2_CLKSOURCE RCC_CCIPR_I2C2SEL /*!< I2C2 clock source selection bits */ +#define LL_RCC_I2C3_CLKSOURCE RCC_CCIPR_I2C3SEL /*!< I2C3 clock source selection bits */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_LPTIMx LPTIMx + * @{ + */ +#define LL_RCC_LPTIM1_CLKSOURCE RCC_CCIPR_LPTIM1SEL /*!< LPTIM1 clock source selection bits */ +#define LL_RCC_LPTIM2_CLKSOURCE RCC_CCIPR_LPTIM2SEL /*!< LPTIM2 clock source selection bits */ +#define LL_RCC_LPTIM3_CLKSOURCE RCC_CCIPR_LPTIM3SEL /*!< LPTIM2 clock source selection bits */ + +/** + * @} + */ + +/** @defgroup RCC_LL_EC_RNG RNG + * @{ + */ +#define LL_RCC_RNG_CLKSOURCE RCC_CCIPR_RNGSEL /*!< RNG clock source selection bits */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_ADC ADC + * @{ + */ +#define LL_RCC_ADC_CLKSOURCE RCC_CCIPR_ADCSEL /*!< ADC clock source selection bits */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection + * @{ + */ +#define LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U /*!< No clock used as RTC clock */ +#define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */ +#define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */ +#define LL_RCC_RTC_CLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by 32 used as RTC clock */ + +/** + * @} + */ + +/** @defgroup RCC_LL_EC_PLLSOURCE PLL entry clock source + * @{ + */ +#define LL_RCC_PLLSOURCE_NONE 0x00000000U /*!< No clock */ +#define LL_RCC_PLLSOURCE_MSI RCC_PLLCFGR_PLLSRC_0 /*!< MSI clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_1 /*!< HSI clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_HSE (RCC_PLLCFGR_PLLSRC_1 | RCC_PLLCFGR_PLLSRC_0) /*!< HSE clock selected as PLL entry clock source */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_PLLM_DIV PLL.division factor + * @{ + */ +#define LL_RCC_PLLM_DIV_1 0x00000000U /*!< PLL division factor by 1 */ +#define LL_RCC_PLLM_DIV_2 (RCC_PLLCFGR_PLLM_0) /*!< PLL division factor by 2 */ +#define LL_RCC_PLLM_DIV_3 (RCC_PLLCFGR_PLLM_1) /*!< PLL division factor by 3 */ +#define LL_RCC_PLLM_DIV_4 ((RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0)) /*!< PLL division factor by 4 */ +#define LL_RCC_PLLM_DIV_5 (RCC_PLLCFGR_PLLM_2) /*!< PLL division factor by 5 */ +#define LL_RCC_PLLM_DIV_6 ((RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0)) /*!< PLL division factor by 6 */ +#define LL_RCC_PLLM_DIV_7 ((RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1)) /*!< PLL division factor by 7 */ +#define LL_RCC_PLLM_DIV_8 (RCC_PLLCFGR_PLLM) /*!< PLL division factor by 8 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_PLLR_DIV PLL division factor (PLLR) + * @{ + */ +#define LL_RCC_PLLR_DIV_2 (RCC_PLLCFGR_PLLR_0) /*!< Main PLL division factor for PLLCLK (system clock) by 2 */ +#define LL_RCC_PLLR_DIV_3 (RCC_PLLCFGR_PLLR_1) /*!< Main PLL division factor for PLLCLK (system clock) by 3 */ +#define LL_RCC_PLLR_DIV_4 (RCC_PLLCFGR_PLLR_1|RCC_PLLCFGR_PLLR_0) /*!< Main PLL division factor for PLLCLK (system clock) by 4 */ +#define LL_RCC_PLLR_DIV_5 (RCC_PLLCFGR_PLLR_2) /*!< Main PLL division factor for PLLCLK (system clock) by 5 */ +#define LL_RCC_PLLR_DIV_6 (RCC_PLLCFGR_PLLR_2|RCC_PLLCFGR_PLLR_0) /*!< Main PLL division factor for PLLCLK (system clock) by 6 */ +#define LL_RCC_PLLR_DIV_7 (RCC_PLLCFGR_PLLR_2|RCC_PLLCFGR_PLLR_1) /*!< Main PLL division factor for PLLCLK (system clock) by 7 */ +#define LL_RCC_PLLR_DIV_8 (RCC_PLLCFGR_PLLR) /*!< Main PLL division factor for PLLCLK (system clock) by 8 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_PLLP_DIV PLL division factor (PLLP) + * @{ + */ +#define LL_RCC_PLLP_DIV_2 (RCC_PLLCFGR_PLLP_0) /*!< Main PLL division factor for PLLP output by 2 */ +#define LL_RCC_PLLP_DIV_3 (RCC_PLLCFGR_PLLP_1) /*!< Main PLL division factor for PLLP output by 3 */ +#define LL_RCC_PLLP_DIV_4 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1) /*!< Main PLL division factor for PLLP output by 4 */ +#define LL_RCC_PLLP_DIV_5 (RCC_PLLCFGR_PLLP_2) /*!< Main PLL division factor for PLLP output by 5 */ +#define LL_RCC_PLLP_DIV_6 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_2) /*!< Main PLL division factor for PLLP output by 6 */ +#define LL_RCC_PLLP_DIV_7 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2) /*!< Main PLL division factor for PLLP output by 7 */ +#define LL_RCC_PLLP_DIV_8 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2) /*!< Main PLL division factor for PLLP output by 8 */ +#define LL_RCC_PLLP_DIV_9 (RCC_PLLCFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 9 */ +#define LL_RCC_PLLP_DIV_10 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 10 */ +#define LL_RCC_PLLP_DIV_11 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 11 */ +#define LL_RCC_PLLP_DIV_12 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 12 */ +#define LL_RCC_PLLP_DIV_13 (RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 13 */ +#define LL_RCC_PLLP_DIV_14 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 14 */ +#define LL_RCC_PLLP_DIV_15 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 15 */ +#define LL_RCC_PLLP_DIV_16 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3)/*!< Main PLL division factor for PLLP output by 16 */ +#define LL_RCC_PLLP_DIV_17 (RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 17 */ +#define LL_RCC_PLLP_DIV_18 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 18 */ +#define LL_RCC_PLLP_DIV_19 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 19 */ +#define LL_RCC_PLLP_DIV_20 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 20 */ +#define LL_RCC_PLLP_DIV_21 (RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 21 */ +#define LL_RCC_PLLP_DIV_22 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 22 */ +#define LL_RCC_PLLP_DIV_23 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 23 */ +#define LL_RCC_PLLP_DIV_24 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_4)/*!< Main PLL division factor for PLLP output by 24 */ +#define LL_RCC_PLLP_DIV_25 (RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 25 */ +#define LL_RCC_PLLP_DIV_26 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 26 */ +#define LL_RCC_PLLP_DIV_27 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 27*/ +#define LL_RCC_PLLP_DIV_28 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4)/*!< Main PLL division factor for PLLP output by 28 */ +#define LL_RCC_PLLP_DIV_29 (RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 29 */ +#define LL_RCC_PLLP_DIV_30 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4)/*!< Main PLL division factor for PLLP output by 30 */ +#define LL_RCC_PLLP_DIV_31 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4)/*!< Main PLL division factor for PLLP output by 31 */ +#define LL_RCC_PLLP_DIV_32 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4)/*!< Main PLL division factor for PLLP output by 32 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_PLLQ_DIV PLL division factor (PLLQ) + * @{ + */ +#define LL_RCC_PLLQ_DIV_2 (RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 2 */ +#define LL_RCC_PLLQ_DIV_3 (RCC_PLLCFGR_PLLQ_1) /*!< Main PLL division factor for PLLQ output by 3 */ +#define LL_RCC_PLLQ_DIV_4 (RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 4 */ +#define LL_RCC_PLLQ_DIV_5 (RCC_PLLCFGR_PLLQ_2) /*!< Main PLL division factor for PLLQ output by 5 */ +#define LL_RCC_PLLQ_DIV_6 (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 6 */ +#define LL_RCC_PLLQ_DIV_7 (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1) /*!< Main PLL division factor for PLLQ output by 7 */ +#define LL_RCC_PLLQ_DIV_8 (RCC_PLLCFGR_PLLQ) /*!< Main PLL division factor for PLLQ output by 8 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_MSIRANGESEL MSI clock range selection + * @{ + */ +#define LL_RCC_MSIRANGESEL_STANDBY 0U /*!< MSI Range is provided by MSISRANGE */ +#define LL_RCC_MSIRANGESEL_RUN 1U /*!< MSI Range is provided by MSIRANGE */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_LSIPRE LSI division factor + * @{ + */ +#define LL_RCC_LSI_PREDIV_1 0x00000000U /*!< LSI division factor by 1 */ +#define LL_RCC_LSI_PREDIV_128 RCC_CSR_LSIPRE /*!< LSI division factor by 128 */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup RCC_LL_Exported_Macros RCC Exported Macros + * @{ + */ + +/** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in RCC register + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__)) + +/** + * @brief Read a value in RCC register + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__) +/** + * @} + */ + +/** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies + * @{ + */ + +/** + * @brief Helper macro to calculate the PLLRCLK frequency on system domain + * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), + * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ()); + * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI) + * @param __PLLM__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_1 + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @param __PLLN__ Between Min_Data = 6 and Max_Data = 127 + * @param __PLLR__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLR_DIV_2 + * @arg @ref LL_RCC_PLLR_DIV_3 + * @arg @ref LL_RCC_PLLR_DIV_4 + * @arg @ref LL_RCC_PLLR_DIV_5 + * @arg @ref LL_RCC_PLLR_DIV_6 + * @arg @ref LL_RCC_PLLR_DIV_7 + * @arg @ref LL_RCC_PLLR_DIV_8 + * @retval PLL clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) \ + ((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \ + (((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos) + 1U)) + +/** + * @brief Helper macro to calculate the PLLPCLK frequency used on ADC domain + * @note ex: @ref __LL_RCC_CALC_PLLCLK_ADC_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), + * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetP ()); + * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI) + * @param __PLLM__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_1 + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @param __PLLN__ Between Min_Data = 6 and Max_Data = 127 + * @param __PLLP__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLP_DIV_2 + * @arg @ref LL_RCC_PLLP_DIV_3 + * @arg @ref LL_RCC_PLLP_DIV_4 + * @arg @ref LL_RCC_PLLP_DIV_5 + * @arg @ref LL_RCC_PLLP_DIV_6 + * @arg @ref LL_RCC_PLLP_DIV_7 + * @arg @ref LL_RCC_PLLP_DIV_8 + * @arg @ref LL_RCC_PLLP_DIV_9 + * @arg @ref LL_RCC_PLLP_DIV_10 + * @arg @ref LL_RCC_PLLP_DIV_11 + * @arg @ref LL_RCC_PLLP_DIV_12 + * @arg @ref LL_RCC_PLLP_DIV_13 + * @arg @ref LL_RCC_PLLP_DIV_14 + * @arg @ref LL_RCC_PLLP_DIV_15 + * @arg @ref LL_RCC_PLLP_DIV_16 + * @arg @ref LL_RCC_PLLP_DIV_17 + * @arg @ref LL_RCC_PLLP_DIV_18 + * @arg @ref LL_RCC_PLLP_DIV_19 + * @arg @ref LL_RCC_PLLP_DIV_20 + * @arg @ref LL_RCC_PLLP_DIV_21 + * @arg @ref LL_RCC_PLLP_DIV_22 + * @arg @ref LL_RCC_PLLP_DIV_23 + * @arg @ref LL_RCC_PLLP_DIV_24 + * @arg @ref LL_RCC_PLLP_DIV_25 + * @arg @ref LL_RCC_PLLP_DIV_26 + * @arg @ref LL_RCC_PLLP_DIV_27 + * @arg @ref LL_RCC_PLLP_DIV_28 + * @arg @ref LL_RCC_PLLP_DIV_29 + * @arg @ref LL_RCC_PLLP_DIV_30 + * @arg @ref LL_RCC_PLLP_DIV_31 + * @arg @ref LL_RCC_PLLP_DIV_32 + * @retval PLL clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLLCLK_ADC_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) \ + ((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \ + (((__PLLP__) >> RCC_PLLCFGR_PLLP_Pos) + 1U)) + +/** + * @brief Helper macro to calculate the PLLQCLK frequency used on RNG domain + * @note ex: @ref __LL_RCC_CALC_PLLCLK_RNG_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), + * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetQ ()); + * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI) + * @param __PLLM__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_1 + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @param __PLLN__ Between Min_Data = 6 and Max_Data = 127 + * @param __PLLQ__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLQ_DIV_2 + * @arg @ref LL_RCC_PLLQ_DIV_3 + * @arg @ref LL_RCC_PLLQ_DIV_4 + * @arg @ref LL_RCC_PLLQ_DIV_5 + * @arg @ref LL_RCC_PLLQ_DIV_6 + * @arg @ref LL_RCC_PLLQ_DIV_7 + * @arg @ref LL_RCC_PLLQ_DIV_8 + * @retval PLL clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLLCLK_RNG_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__) \ + ((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \ + (((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos) + 1U)) + +/** + * @brief Helper macro to calculate the PLLQCLK frequency used on I2S domain + * @note ex: @ref __LL_RCC_CALC_PLLCLK_I2S2_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), + * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetQ ()); + * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI) + * @param __PLLM__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_1 + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @param __PLLN__ Between Min_Data = 6 and Max_Data = 127 + * @param __PLLQ__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLQ_DIV_2 + * @arg @ref LL_RCC_PLLQ_DIV_3 + * @arg @ref LL_RCC_PLLQ_DIV_4 + * @arg @ref LL_RCC_PLLQ_DIV_5 + * @arg @ref LL_RCC_PLLQ_DIV_6 + * @arg @ref LL_RCC_PLLQ_DIV_7 + * @arg @ref LL_RCC_PLLQ_DIV_8 + * @retval PLL clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLLCLK_I2S2_FREQ __LL_RCC_CALC_PLLCLK_RNG_FREQ + +/** + * @brief Helper macro to calculate the HCLK1 frequency + * @param __SYSCLKFREQ__ SYSCLK frequency (based on MSI/HSE/HSI/PLLCLK) + * @param __CPU1PRESCALER__ This parameter can be one of the following values: + * @arg @ref LL_RCC_SYSCLK_DIV_1 + * @arg @ref LL_RCC_SYSCLK_DIV_2 + * @arg @ref LL_RCC_SYSCLK_DIV_3 + * @arg @ref LL_RCC_SYSCLK_DIV_4 + * @arg @ref LL_RCC_SYSCLK_DIV_5 + * @arg @ref LL_RCC_SYSCLK_DIV_6 + * @arg @ref LL_RCC_SYSCLK_DIV_8 + * @arg @ref LL_RCC_SYSCLK_DIV_10 + * @arg @ref LL_RCC_SYSCLK_DIV_16 + * @arg @ref LL_RCC_SYSCLK_DIV_32 + * @arg @ref LL_RCC_SYSCLK_DIV_64 + * @arg @ref LL_RCC_SYSCLK_DIV_128 + * @arg @ref LL_RCC_SYSCLK_DIV_256 + * @arg @ref LL_RCC_SYSCLK_DIV_512 + * @retval HCLK1 clock frequency (in Hz) + */ +#define __LL_RCC_CALC_HCLK1_FREQ(__SYSCLKFREQ__,__CPU1PRESCALER__) \ + ((__SYSCLKFREQ__) / AHBPrescTable[((__CPU1PRESCALER__) & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]) + +#if defined(DUAL_CORE) +/** + * @brief Helper macro to calculate the HCLK2 frequency + * @param __SYSCLKFREQ__ SYSCLK frequency (based on MSI/HSE/HSI/PLLCLK) + * @param __CPU2PRESCALER__ This parameter can be one of the following values: + * @arg @ref LL_RCC_SYSCLK_DIV_1 + * @arg @ref LL_RCC_SYSCLK_DIV_2 + * @arg @ref LL_RCC_SYSCLK_DIV_3 + * @arg @ref LL_RCC_SYSCLK_DIV_4 + * @arg @ref LL_RCC_SYSCLK_DIV_5 + * @arg @ref LL_RCC_SYSCLK_DIV_6 + * @arg @ref LL_RCC_SYSCLK_DIV_8 + * @arg @ref LL_RCC_SYSCLK_DIV_10 + * @arg @ref LL_RCC_SYSCLK_DIV_16 + * @arg @ref LL_RCC_SYSCLK_DIV_32 + * @arg @ref LL_RCC_SYSCLK_DIV_64 + * @arg @ref LL_RCC_SYSCLK_DIV_128 + * @arg @ref LL_RCC_SYSCLK_DIV_256 + * @arg @ref LL_RCC_SYSCLK_DIV_512 + * @retval HCLK2 clock frequency (in Hz) + */ +#define __LL_RCC_CALC_HCLK2_FREQ(__SYSCLKFREQ__, __CPU2PRESCALER__) \ + ((__SYSCLKFREQ__) / AHBPrescTable[((__CPU2PRESCALER__) & RCC_EXTCFGR_C2HPRE) >> RCC_EXTCFGR_C2HPRE_Pos]) +#endif /* DUAL_CORE */ + +/** + * @brief Helper macro to calculate the HCLK3 frequency + * @param __SYSCLKFREQ__ SYSCLK frequency (based on MSI/HSE/HSI/PLLCLK) + * @param __AHB3PRESCALER__ This parameter can be one of the following values: + * @arg @ref LL_RCC_SYSCLK_DIV_1 + * @arg @ref LL_RCC_SYSCLK_DIV_2 + * @arg @ref LL_RCC_SYSCLK_DIV_3 + * @arg @ref LL_RCC_SYSCLK_DIV_4 + * @arg @ref LL_RCC_SYSCLK_DIV_5 + * @arg @ref LL_RCC_SYSCLK_DIV_6 + * @arg @ref LL_RCC_SYSCLK_DIV_8 + * @arg @ref LL_RCC_SYSCLK_DIV_10 + * @arg @ref LL_RCC_SYSCLK_DIV_16 + * @arg @ref LL_RCC_SYSCLK_DIV_32 + * @arg @ref LL_RCC_SYSCLK_DIV_64 + * @arg @ref LL_RCC_SYSCLK_DIV_128 + * @arg @ref LL_RCC_SYSCLK_DIV_256 + * @arg @ref LL_RCC_SYSCLK_DIV_512 + * @retval HCLK3 clock frequency (in Hz) + */ +#define __LL_RCC_CALC_HCLK3_FREQ(__SYSCLKFREQ__, __AHB3PRESCALER__) \ + ((__SYSCLKFREQ__) / AHBPrescTable[(((__AHB3PRESCALER__) >> 4U) & RCC_EXTCFGR_SHDHPRE) >> RCC_EXTCFGR_SHDHPRE_Pos]) + + +/** + * @brief Helper macro to calculate the PCLK1 frequency (ABP1) + * @param __HCLKFREQ__ HCLK frequency + * @param __APB1PRESCALER__ This parameter can be one of the following values: + * @arg @ref LL_RCC_APB1_DIV_1 + * @arg @ref LL_RCC_APB1_DIV_2 + * @arg @ref LL_RCC_APB1_DIV_4 + * @arg @ref LL_RCC_APB1_DIV_8 + * @arg @ref LL_RCC_APB1_DIV_16 + * @retval PCLK1 clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) \ + ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE1_Pos]) + +/** + * @brief Helper macro to calculate the PCLK2 frequency (ABP2) + * @param __HCLKFREQ__ HCLK frequency + * @param __APB2PRESCALER__ This parameter can be one of the following values: + * @arg @ref LL_RCC_APB2_DIV_1 + * @arg @ref LL_RCC_APB2_DIV_2 + * @arg @ref LL_RCC_APB2_DIV_4 + * @arg @ref LL_RCC_APB2_DIV_8 + * @arg @ref LL_RCC_APB2_DIV_16 + * @retval PCLK2 clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) \ + ((__HCLKFREQ__) >> APBPrescTable[(__APB2PRESCALER__) >> RCC_CFGR_PPRE2_Pos]) + +/** + * @brief Helper macro to calculate the MSI frequency (in Hz) + * @note __MSISEL__ can be retrieved thanks to function LL_RCC_MSI_IsEnabledRangeSelect() + * @note if __MSISEL__ is equal to LL_RCC_MSIRANGESEL_STANDBY, + * __MSIRANGE__can be retrieved by LL_RCC_MSI_GetRangeAfterStandby() + * else by LL_RCC_MSI_GetRange() + * ex: __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), + * (LL_RCC_MSI_IsEnabledRangeSelect()? + * LL_RCC_MSI_GetRange(): + * LL_RCC_MSI_GetRangeAfterStandby())) + * @param __MSISEL__ This parameter can be one of the following values: + * @arg @ref LL_RCC_MSIRANGESEL_STANDBY + * @arg @ref LL_RCC_MSIRANGESEL_RUN + * @param __MSIRANGE__ This parameter can be one of the following values: + * @arg @ref LL_RCC_MSIRANGE_0 + * @arg @ref LL_RCC_MSIRANGE_1 + * @arg @ref LL_RCC_MSIRANGE_2 + * @arg @ref LL_RCC_MSIRANGE_3 + * @arg @ref LL_RCC_MSIRANGE_4 + * @arg @ref LL_RCC_MSIRANGE_5 + * @arg @ref LL_RCC_MSIRANGE_6 + * @arg @ref LL_RCC_MSIRANGE_7 + * @arg @ref LL_RCC_MSIRANGE_8 + * @arg @ref LL_RCC_MSIRANGE_9 + * @arg @ref LL_RCC_MSIRANGE_10 + * @arg @ref LL_RCC_MSIRANGE_11 + * @arg @ref LL_RCC_MSISRANGE_4 + * @arg @ref LL_RCC_MSISRANGE_5 + * @arg @ref LL_RCC_MSISRANGE_6 + * @arg @ref LL_RCC_MSISRANGE_7 + * @retval MSI clock frequency (in Hz) + */ +#define __LL_RCC_CALC_MSI_FREQ(__MSISEL__, __MSIRANGE__) \ + (((__MSISEL__) == LL_RCC_MSIRANGESEL_STANDBY) ? \ + (MSIRangeTable[((__MSIRANGE__) & RCC_CSR_MSISRANGE_Msk) >> RCC_CSR_MSISRANGE_Pos ]) : \ + (MSIRangeTable[((__MSIRANGE__) & RCC_CR_MSIRANGE_Msk) >> RCC_CR_MSIRANGE_Pos])) + +/** + * @} + */ + + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup RCC_LL_Exported_Functions RCC Exported Functions + * @{ + */ + +/** @defgroup RCC_LL_EF_HSE HSE + * @{ + */ + +/** + * @brief Enable HSE VDDTCXO output on package pin PB0-VDDTCXO + * @note PB0 must be configured in analog mode prior enabling VDDTCXO supply + * @rmtoll CR HSEBYPPWR LL_RCC_HSE_EnableTcxo + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_EnableTcxo(void) +{ + SET_BIT(RCC->CR, RCC_CR_HSEBYPPWR); +} + +/** + * @brief Disable HSE VDDTCXO output on package pin PB0-VDDTCXO + * @rmtoll CR HSEBYPPWR LL_RCC_HSE_DisableTcxo + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_DisableTcxo(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_HSEBYPPWR); +} + +/** + * @brief Get HSE VDDTCXO output on package pin PB0-VDDTCXO + * @rmtoll CR HSEBYPPWR LL_RCC_HSE_IsEnabledTcxo + * @retval None + */ +__STATIC_INLINE uint32_t LL_RCC_HSE_IsEnabledTcxo(void) +{ + return ((READ_BIT(RCC->CR, RCC_CR_HSEBYPPWR) == (RCC_CR_HSEBYPPWR)) ? 1UL : 0UL); +} + + +/** + * @brief Enable HSE sysclk and pll prescaler division by 2 + * @rmtoll CR HSEPRE LL_RCC_HSE_EnableDiv2 + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_EnableDiv2(void) +{ + SET_BIT(RCC->CR, RCC_CR_HSEPRE); +} + +/** + * @brief Disable HSE sysclk and pll prescaler division by 2 + * @rmtoll CR HSEPRE LL_RCC_HSE_DisableDiv2 + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_DisableDiv2(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_HSEPRE); +} + +/** + * @brief Get HSE sysclk and pll prescaler division by 2 + * @rmtoll CR HSEPRE LL_RCC_HSE_IsEnabledDiv2 + * @retval None + */ +__STATIC_INLINE uint32_t LL_RCC_HSE_IsEnabledDiv2(void) +{ + return ((READ_BIT(RCC->CR, RCC_CR_HSEPRE) == (RCC_CR_HSEPRE)) ? 1UL : 0UL); +} + +/** + * @brief Enable the Clock Security System. + * @rmtoll CR CSSON LL_RCC_HSE_EnableCSS + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_EnableCSS(void) +{ + SET_BIT(RCC->CR, RCC_CR_CSSON); +} + +/** + * @brief Enable HSE crystal oscillator (HSE ON) + * @rmtoll CR HSEON LL_RCC_HSE_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_Enable(void) +{ + SET_BIT(RCC->CR, RCC_CR_HSEON); +} + +/** + * @brief Disable HSE crystal oscillator (HSE ON) + * @rmtoll CR HSEON LL_RCC_HSE_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_Disable(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_HSEON); +} + +/** + * @brief Check if HSE oscillator Ready + * @rmtoll CR HSERDY LL_RCC_HSE_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void) +{ + return ((READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_HSI HSI + * @{ + */ + +/** + * @brief Enable HSI even in stop mode + * @note HSI oscillator is forced ON even in Stop mode + * @rmtoll CR HSIKERON LL_RCC_HSI_EnableInStopMode + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI_EnableInStopMode(void) +{ + SET_BIT(RCC->CR, RCC_CR_HSIKERON); +} + +/** + * @brief Disable HSI in stop mode + * @rmtoll CR HSIKERON LL_RCC_HSI_DisableInStopMode + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI_DisableInStopMode(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON); +} + +/** + * @brief Check if HSI in stop mode is ready + * @rmtoll CR HSIKERON LL_RCC_HSI_IsEnabledInStopMode + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_HSI_IsEnabledInStopMode(void) +{ + return ((READ_BIT(RCC->CR, RCC_CR_HSIKERON) == (RCC_CR_HSIKERON)) ? 1UL : 0UL); +} + +/** + * @brief Enable HSI oscillator + * @rmtoll CR HSION LL_RCC_HSI_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI_Enable(void) +{ + SET_BIT(RCC->CR, RCC_CR_HSION); +} + +/** + * @brief Disable HSI oscillator + * @rmtoll CR HSION LL_RCC_HSI_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI_Disable(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_HSION); +} + +/** + * @brief Check if HSI clock is ready + * @rmtoll CR HSIRDY LL_RCC_HSI_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void) +{ + return ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY)) ? 1UL : 0UL); +} + +/** + * @brief Enable HSI Automatic from stop mode + * @rmtoll CR HSIASFS LL_RCC_HSI_EnableAutoFromStop + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI_EnableAutoFromStop(void) +{ + SET_BIT(RCC->CR, RCC_CR_HSIASFS); +} + +/** + * @brief Disable HSI Automatic from stop mode + * @rmtoll CR HSIASFS LL_RCC_HSI_DisableAutoFromStop + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI_DisableAutoFromStop(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_HSIASFS); +} +/** + * @brief Get HSI Calibration value + * @note When HSITRIM is written, HSICAL is updated with the sum of + * HSITRIM and the factory trim value + * @rmtoll ICSCR HSICAL LL_RCC_HSI_GetCalibration + * @retval Between Min_Data = 0x00 and Max_Data = 0xFF + */ +__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void) +{ + return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSICAL) >> RCC_ICSCR_HSICAL_Pos); +} + +/** + * @brief Set HSI Calibration trimming + * @note user-programmable trimming value that is added to the HSICAL + * @note Default value is 64, which, when added to the HSICAL value, + * should trim the HSI to 16 MHz +/- 1 % + * @rmtoll ICSCR HSITRIM LL_RCC_HSI_SetCalibTrimming + * @param Value Between Min_Data = 0 and Max_Data = 127 + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value) +{ + MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, Value << RCC_ICSCR_HSITRIM_Pos); +} + +/** + * @brief Get HSI Calibration trimming + * @rmtoll ICSCR HSITRIM LL_RCC_HSI_GetCalibTrimming + * @retval Between Min_Data = 0 and Max_Data = 127 + */ +__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void) +{ + return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSITRIM) >> RCC_ICSCR_HSITRIM_Pos); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_LSE LSE + * @{ + */ + +/** + * @brief Enable Low Speed External (LSE) crystal. + * @rmtoll BDCR LSEON LL_RCC_LSE_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_Enable(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); +} + +/** + * @brief Disable Low Speed External (LSE) crystal. + * @rmtoll BDCR LSEON LL_RCC_LSE_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_Disable(void) +{ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); +} + +/** + * @brief Check if Low Speed External (LSE) crystal has been enabled or not + * @rmtoll BDCR LSEON LL_RCC_LSE_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_LSE_IsEnabled(void) +{ + return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSEON) == (RCC_BDCR_LSEON)) ? 1UL : 0UL); +} + +/** + * @brief Enable external clock source (LSE bypass). + * @rmtoll BDCR LSEBYP LL_RCC_LSE_EnableBypass + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_EnableBypass(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); +} + +/** + * @brief Disable external clock source (LSE bypass). + * @rmtoll BDCR LSEBYP LL_RCC_LSE_DisableBypass + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_DisableBypass(void) +{ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); +} + +/** + * @brief Set LSE oscillator drive capability + * @note The oscillator is in Xtal mode when it is not in bypass mode. + * @rmtoll BDCR LSEDRV LL_RCC_LSE_SetDriveCapability + * @param LSEDrive This parameter can be one of the following values: + * @arg @ref LL_RCC_LSEDRIVE_LOW + * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW + * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH + * @arg @ref LL_RCC_LSEDRIVE_HIGH + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive) +{ + MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, LSEDrive); +} + +/** + * @brief Get LSE oscillator drive capability + * @rmtoll BDCR LSEDRV LL_RCC_LSE_GetDriveCapability + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_LSEDRIVE_LOW + * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW + * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH + * @arg @ref LL_RCC_LSEDRIVE_HIGH + */ +__STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void) +{ + return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSEDRV)); +} + +/** + * @brief Enable Clock security system on LSE. + * @rmtoll BDCR LSECSSON LL_RCC_LSE_EnableCSS + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_EnableCSS(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON); +} + +/** + * @brief Disable Clock security system on LSE. + * @note Clock security system can be disabled only after a LSE + * failure detection. In that case it MUST be disabled by software. + * @rmtoll BDCR LSECSSON LL_RCC_LSE_DisableCSS + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_DisableCSS(void) +{ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSECSSON); +} + +/** + * @brief Enable LSE oscillator propagation for system clock + * @rmtoll BDCR LSESYSEN LL_RCC_LSE_EnablePropagation + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_EnablePropagation(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_LSESYSEN); +} + +/** + * @brief Disable LSE oscillator propagation for system clock + * @rmtoll BDCR LSESYSEN LL_RCC_LSE_DisablePropagation + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_DisablePropagation(void) +{ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSESYSEN); +} + +/** + * @brief Check if LSE oscillator propagation for system clock Ready + * @rmtoll BDCR LSEYSRDY LL_RCC_LSE_IsPropagationReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_LSE_IsPropagationReady(void) +{ + return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSESYSRDY) == (RCC_BDCR_LSESYSRDY)) ? 1UL : 0UL); +} + + +/** + * @brief Check if LSE oscillator Ready + * @rmtoll BDCR LSERDY LL_RCC_LSE_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void) +{ + return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY)) ? 1UL : 0UL); +} + +/** + * @brief Check if CSS on LSE failure Detection + * @rmtoll BDCR LSECSSD LL_RCC_LSE_IsCSSDetected + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_LSE_IsCSSDetected(void) +{ + return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSECSSD) == (RCC_BDCR_LSECSSD)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_LSI LSI + * @{ + */ + + +/** + * @brief Set LSI division factor + * @rmtoll CSR LSIPRE LL_RCC_LSI_SetPrediv + * @param LSI_PREDIV This parameter can be one of the following values: + * @arg @ref LL_RCC_LSI_PREDIV_1 + * @arg @ref LL_RCC_LSI_PREDIV_128 + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSI_SetPrediv(uint32_t LSI_PREDIV) +{ + MODIFY_REG(RCC->CSR, RCC_CSR_LSIPRE, LSI_PREDIV); +} + +/** + * @brief Get LSI division factor + * @rmtoll CSR LSIPRE LL_RCC_LSI_GetPrediv + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_LSI_PREDIV_1 + * @arg @ref LL_RCC_LSI_PREDIV_128 + */ +__STATIC_INLINE uint32_t LL_RCC_LSI_GetPrediv(void) +{ + return (READ_BIT(RCC->CSR, RCC_CSR_LSIPRE)); +} + + +/** + * @brief Enable LSI Oscillator + * @rmtoll CSR LSION LL_RCC_LSI_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSI_Enable(void) +{ + SET_BIT(RCC->CSR, RCC_CSR_LSION); +} + +/** + * @brief Disable LSI Oscillator + * @rmtoll CSR LSION LL_RCC_LSI_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSI_Disable(void) +{ + CLEAR_BIT(RCC->CSR, RCC_CSR_LSION); +} + +/** + * @brief Check if LSI is Ready + * @rmtoll CSR LSIRDY LL_RCC_LSI_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void) +{ + return ((READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_MSI MSI + * @{ + */ + +/** + * @brief Enable MSI oscillator + * @rmtoll CR MSION LL_RCC_MSI_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_MSI_Enable(void) +{ + SET_BIT(RCC->CR, RCC_CR_MSION); +} + +/** + * @brief Disable MSI oscillator + * @rmtoll CR MSION LL_RCC_MSI_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_MSI_Disable(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_MSION); +} + +/** + * @brief Check if MSI oscillator Ready + * @rmtoll CR MSIRDY LL_RCC_MSI_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_MSI_IsReady(void) +{ + return ((READ_BIT(RCC->CR, RCC_CR_MSIRDY) == (RCC_CR_MSIRDY)) ? 1UL : 0UL); +} + +/** + * @brief Enable MSI PLL-mode (Hardware auto calibration with LSE) + * @note MSIPLLEN must be enabled after LSE is enabled (LSEON enabled) + * and ready (LSERDY set by hardware) + * @note hardware protection to avoid enabling MSIPLLEN if LSE is not + * ready + * @rmtoll CR MSIPLLEN LL_RCC_MSI_EnablePLLMode + * @retval None + */ +__STATIC_INLINE void LL_RCC_MSI_EnablePLLMode(void) +{ + SET_BIT(RCC->CR, RCC_CR_MSIPLLEN); +} + +/** + * @brief Disable MSI-PLL mode + * @note cleared by hardware when LSE is disabled (LSEON = 0) or when + * the Clock Security System on LSE detects a LSE failure + * @rmtoll CR MSIPLLEN LL_RCC_MSI_DisablePLLMode + * @retval None + */ +__STATIC_INLINE void LL_RCC_MSI_DisablePLLMode(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_MSIPLLEN); +} + +/** + * @brief Enable MSI clock range selection with MSIRANGE register + * @note Write 0 has no effect. After a standby or a reset + * MSIRGSEL is at 0 and the MSI range value is provided by + * MSISRANGE + * @rmtoll CR MSIRGSEL LL_RCC_MSI_EnableRangeSelection + * @retval None + */ +__STATIC_INLINE void LL_RCC_MSI_EnableRangeSelection(void) +{ + SET_BIT(RCC->CR, RCC_CR_MSIRGSEL); +} + +/** + * @brief Check if MSI clock range is selected with MSIRANGE register + * @rmtoll CR MSIRGSEL LL_RCC_MSI_IsEnabledRangeSelect + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_MSI_IsEnabledRangeSelect(void) +{ + return ((READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) == (RCC_CR_MSIRGSEL)) ? 1UL : 0UL); +} + +/** + * @brief Configure the Internal Multi Speed oscillator (MSI) clock range in run mode. + * @rmtoll CR MSIRANGE LL_RCC_MSI_SetRange + * @param Range This parameter can be one of the following values: + * @arg @ref LL_RCC_MSIRANGE_0 + * @arg @ref LL_RCC_MSIRANGE_1 + * @arg @ref LL_RCC_MSIRANGE_2 + * @arg @ref LL_RCC_MSIRANGE_3 + * @arg @ref LL_RCC_MSIRANGE_4 + * @arg @ref LL_RCC_MSIRANGE_5 + * @arg @ref LL_RCC_MSIRANGE_6 + * @arg @ref LL_RCC_MSIRANGE_7 + * @arg @ref LL_RCC_MSIRANGE_8 + * @arg @ref LL_RCC_MSIRANGE_9 + * @arg @ref LL_RCC_MSIRANGE_10 + * @arg @ref LL_RCC_MSIRANGE_11 + * @retval None + */ +__STATIC_INLINE void LL_RCC_MSI_SetRange(uint32_t Range) +{ + MODIFY_REG(RCC->CR, RCC_CR_MSIRANGE, Range); +} + +/** + * @brief Get the Internal Multi Speed oscillator (MSI) clock range in run mode. + * @rmtoll CR MSIRANGE LL_RCC_MSI_GetRange + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_MSIRANGE_0 + * @arg @ref LL_RCC_MSIRANGE_1 + * @arg @ref LL_RCC_MSIRANGE_2 + * @arg @ref LL_RCC_MSIRANGE_3 + * @arg @ref LL_RCC_MSIRANGE_4 + * @arg @ref LL_RCC_MSIRANGE_5 + * @arg @ref LL_RCC_MSIRANGE_6 + * @arg @ref LL_RCC_MSIRANGE_7 + * @arg @ref LL_RCC_MSIRANGE_8 + * @arg @ref LL_RCC_MSIRANGE_9 + * @arg @ref LL_RCC_MSIRANGE_10 + * @arg @ref LL_RCC_MSIRANGE_11 + */ +__STATIC_INLINE uint32_t LL_RCC_MSI_GetRange(void) +{ + return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_MSIRANGE)); +} + +/** + * @brief Configure MSI range used after standby + * @rmtoll CSR MSISRANGE LL_RCC_MSI_SetRangeAfterStandby + * @param Range This parameter can be one of the following values: + * @arg @ref LL_RCC_MSISRANGE_4 + * @arg @ref LL_RCC_MSISRANGE_5 + * @arg @ref LL_RCC_MSISRANGE_6 + * @arg @ref LL_RCC_MSISRANGE_7 + * @retval None + */ +__STATIC_INLINE void LL_RCC_MSI_SetRangeAfterStandby(uint32_t Range) +{ + MODIFY_REG(RCC->CSR, RCC_CSR_MSISRANGE, Range); +} + +/** + * @brief Get MSI range used after standby + * @rmtoll CSR MSISRANGE LL_RCC_MSI_GetRangeAfterStandby + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_MSISRANGE_4 + * @arg @ref LL_RCC_MSISRANGE_5 + * @arg @ref LL_RCC_MSISRANGE_6 + * @arg @ref LL_RCC_MSISRANGE_7 + */ +__STATIC_INLINE uint32_t LL_RCC_MSI_GetRangeAfterStandby(void) +{ + return (uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_MSISRANGE)); +} + +/** + * @brief Get MSI Calibration value + * @note When MSITRIM is written, MSICAL is updated with the sum of + * MSITRIM and the factory trim value + * @rmtoll ICSCR MSICAL LL_RCC_MSI_GetCalibration + * @retval Between Min_Data = 0 and Max_Data = 255 + */ +__STATIC_INLINE uint32_t LL_RCC_MSI_GetCalibration(void) +{ + return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSICAL) >> RCC_ICSCR_MSICAL_Pos); +} + +/** + * @brief Set MSI Calibration trimming + * @note user-programmable trimming value that is added to the MSICAL + * @rmtoll ICSCR MSITRIM LL_RCC_MSI_SetCalibTrimming + * @param Value Between Min_Data = 0 and Max_Data = 255 + * @retval None + */ +__STATIC_INLINE void LL_RCC_MSI_SetCalibTrimming(uint32_t Value) +{ + MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, Value << RCC_ICSCR_MSITRIM_Pos); +} + +/** + * @brief Get MSI Calibration trimming + * @rmtoll ICSCR MSITRIM LL_RCC_MSI_GetCalibTrimming + * @retval Between 0 and 255 + */ +__STATIC_INLINE uint32_t LL_RCC_MSI_GetCalibTrimming(void) +{ + return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSITRIM) >> RCC_ICSCR_MSITRIM_Pos); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_LSCO LSCO + * @{ + */ + +/** + * @brief Enable Low speed clock + * @rmtoll BDCR LSCOEN LL_RCC_LSCO_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSCO_Enable(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_LSCOEN); +} + +/** + * @brief Disable Low speed clock + * @rmtoll BDCR LSCOEN LL_RCC_LSCO_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSCO_Disable(void) +{ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSCOEN); +} + +/** + * @brief Configure Low speed clock selection + * @rmtoll BDCR LSCOSEL LL_RCC_LSCO_SetSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSI + * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSE + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSCO_SetSource(uint32_t Source) +{ + MODIFY_REG(RCC->BDCR, RCC_BDCR_LSCOSEL, Source); +} + +/** + * @brief Get Low speed clock selection + * @rmtoll BDCR LSCOSEL LL_RCC_LSCO_GetSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSI + * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSE + */ +__STATIC_INLINE uint32_t LL_RCC_LSCO_GetSource(void) +{ + return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSCOSEL)); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_RF RF + * @{ + */ + +/** + * @brief Enable radio reset + * @rmtoll CSR RFRST LL_RCC_RF_EnableReset + * @retval None + */ +__STATIC_INLINE void LL_RCC_RF_EnableReset(void) +{ + SET_BIT(RCC->CSR, RCC_CSR_RFRST); +} + +/** + * @brief Disable radio reset + * @rmtoll CSR RFRST LL_RCC_RF_DisableReset + * @retval None + */ +__STATIC_INLINE void LL_RCC_RF_DisableReset(void) +{ + CLEAR_BIT(RCC->CSR, RCC_CSR_RFRST); +} + +/** + * @brief Get radio reset + * @rmtoll CSR RFRST LL_RCC_RF_IsEnabledReset + * @retval None + */ +__STATIC_INLINE uint32_t LL_RCC_RF_IsEnabledReset(void) +{ + return ((READ_BIT(RCC->CSR, RCC_CSR_RFRST) == (RCC_CSR_RFRST)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC flag Radio in reset is set or not. + * @rmtoll CSR RFRSTF LL_RCC_IsRFUnderReset + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsRFUnderReset(void) +{ + return ((READ_BIT(RCC->CSR, RCC_CSR_RFRSTF) == (RCC_CSR_RFRSTF)) ? 1UL : 0UL); +} + + +/** + * @} + */ + + +/** @defgroup RCC_LL_EF_System System + * @{ + */ + +/** + * @brief Configure the system clock source + * @rmtoll CFGR SW LL_RCC_SetSysClkSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_SYS_CLKSOURCE_MSI + * @arg @ref LL_RCC_SYS_CLKSOURCE_HSI + * @arg @ref LL_RCC_SYS_CLKSOURCE_HSE + * @arg @ref LL_RCC_SYS_CLKSOURCE_PLL + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source); +} + +/** + * @brief Get the system clock source + * @rmtoll CFGR SWS LL_RCC_GetSysClkSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_MSI + * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI + * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE + * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL + */ +__STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS)); +} + + +/** + * @brief Set AHB prescaler + * @rmtoll CFGR HPRE LL_RCC_SetAHBPrescaler + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_SYSCLK_DIV_1 + * @arg @ref LL_RCC_SYSCLK_DIV_2 + * @arg @ref LL_RCC_SYSCLK_DIV_3 + * @arg @ref LL_RCC_SYSCLK_DIV_4 + * @arg @ref LL_RCC_SYSCLK_DIV_5 + * @arg @ref LL_RCC_SYSCLK_DIV_6 + * @arg @ref LL_RCC_SYSCLK_DIV_8 + * @arg @ref LL_RCC_SYSCLK_DIV_10 + * @arg @ref LL_RCC_SYSCLK_DIV_16 + * @arg @ref LL_RCC_SYSCLK_DIV_32 + * @arg @ref LL_RCC_SYSCLK_DIV_64 + * @arg @ref LL_RCC_SYSCLK_DIV_128 + * @arg @ref LL_RCC_SYSCLK_DIV_256 + * @arg @ref LL_RCC_SYSCLK_DIV_512 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler); +} + +#if defined(DUAL_CORE) +/** + * @brief Set CPU2 AHB prescaler + * @rmtoll EXTCFGR C2HPRE LL_C2_RCC_SetAHBPrescaler + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_SYSCLK_DIV_1 + * @arg @ref LL_RCC_SYSCLK_DIV_2 + * @arg @ref LL_RCC_SYSCLK_DIV_3 + * @arg @ref LL_RCC_SYSCLK_DIV_4 + * @arg @ref LL_RCC_SYSCLK_DIV_5 + * @arg @ref LL_RCC_SYSCLK_DIV_6 + * @arg @ref LL_RCC_SYSCLK_DIV_8 + * @arg @ref LL_RCC_SYSCLK_DIV_10 + * @arg @ref LL_RCC_SYSCLK_DIV_16 + * @arg @ref LL_RCC_SYSCLK_DIV_32 + * @arg @ref LL_RCC_SYSCLK_DIV_64 + * @arg @ref LL_RCC_SYSCLK_DIV_128 + * @arg @ref LL_RCC_SYSCLK_DIV_256 + * @arg @ref LL_RCC_SYSCLK_DIV_512 + * @retval None + */ +__STATIC_INLINE void LL_C2_RCC_SetAHBPrescaler(uint32_t Prescaler) +{ + MODIFY_REG(RCC->EXTCFGR, RCC_EXTCFGR_C2HPRE, Prescaler); +} +#endif /* DUAL_CORE */ + +/** + * @brief Set AHB3 prescaler + * @rmtoll EXTCFGR SHDHPRE LL_RCC_SetAHB3Prescaler + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_SYSCLK_DIV_1 + * @arg @ref LL_RCC_SYSCLK_DIV_2 + * @arg @ref LL_RCC_SYSCLK_DIV_3 + * @arg @ref LL_RCC_SYSCLK_DIV_4 + * @arg @ref LL_RCC_SYSCLK_DIV_5 + * @arg @ref LL_RCC_SYSCLK_DIV_6 + * @arg @ref LL_RCC_SYSCLK_DIV_8 + * @arg @ref LL_RCC_SYSCLK_DIV_10 + * @arg @ref LL_RCC_SYSCLK_DIV_16 + * @arg @ref LL_RCC_SYSCLK_DIV_32 + * @arg @ref LL_RCC_SYSCLK_DIV_64 + * @arg @ref LL_RCC_SYSCLK_DIV_128 + * @arg @ref LL_RCC_SYSCLK_DIV_256 + * @arg @ref LL_RCC_SYSCLK_DIV_512 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetAHB3Prescaler(uint32_t Prescaler) +{ + MODIFY_REG(RCC->EXTCFGR, RCC_EXTCFGR_SHDHPRE, Prescaler >> 4); +} + +/** + * @brief Set APB1 prescaler + * @rmtoll CFGR PPRE1 LL_RCC_SetAPB1Prescaler + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_APB1_DIV_1 + * @arg @ref LL_RCC_APB1_DIV_2 + * @arg @ref LL_RCC_APB1_DIV_4 + * @arg @ref LL_RCC_APB1_DIV_8 + * @arg @ref LL_RCC_APB1_DIV_16 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler); +} + +/** + * @brief Set APB2 prescaler + * @rmtoll CFGR PPRE2 LL_RCC_SetAPB2Prescaler + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_APB2_DIV_1 + * @arg @ref LL_RCC_APB2_DIV_2 + * @arg @ref LL_RCC_APB2_DIV_4 + * @arg @ref LL_RCC_APB2_DIV_8 + * @arg @ref LL_RCC_APB2_DIV_16 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler); +} + +/** + * @brief Get AHB prescaler + * @rmtoll CFGR HPRE LL_RCC_GetAHBPrescaler + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_SYSCLK_DIV_1 + * @arg @ref LL_RCC_SYSCLK_DIV_2 + * @arg @ref LL_RCC_SYSCLK_DIV_3 + * @arg @ref LL_RCC_SYSCLK_DIV_4 + * @arg @ref LL_RCC_SYSCLK_DIV_5 + * @arg @ref LL_RCC_SYSCLK_DIV_6 + * @arg @ref LL_RCC_SYSCLK_DIV_8 + * @arg @ref LL_RCC_SYSCLK_DIV_10 + * @arg @ref LL_RCC_SYSCLK_DIV_16 + * @arg @ref LL_RCC_SYSCLK_DIV_32 + * @arg @ref LL_RCC_SYSCLK_DIV_64 + * @arg @ref LL_RCC_SYSCLK_DIV_128 + * @arg @ref LL_RCC_SYSCLK_DIV_256 + * @arg @ref LL_RCC_SYSCLK_DIV_512 + */ +__STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE)); +} + +#if defined(DUAL_CORE) +/** + * @brief Get C2 AHB prescaler + * @rmtoll EXTCFGR C2HPRE LL_C2_RCC_GetAHBPrescaler + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_SYSCLK_DIV_1 + * @arg @ref LL_RCC_SYSCLK_DIV_2 + * @arg @ref LL_RCC_SYSCLK_DIV_3 + * @arg @ref LL_RCC_SYSCLK_DIV_4 + * @arg @ref LL_RCC_SYSCLK_DIV_5 + * @arg @ref LL_RCC_SYSCLK_DIV_6 + * @arg @ref LL_RCC_SYSCLK_DIV_8 + * @arg @ref LL_RCC_SYSCLK_DIV_10 + * @arg @ref LL_RCC_SYSCLK_DIV_16 + * @arg @ref LL_RCC_SYSCLK_DIV_32 + * @arg @ref LL_RCC_SYSCLK_DIV_64 + * @arg @ref LL_RCC_SYSCLK_DIV_128 + * @arg @ref LL_RCC_SYSCLK_DIV_256 + * @arg @ref LL_RCC_SYSCLK_DIV_512 + */ +__STATIC_INLINE uint32_t LL_C2_RCC_GetAHBPrescaler(void) +{ + return (uint32_t)(READ_BIT(RCC->EXTCFGR, RCC_EXTCFGR_C2HPRE)); +} +#endif /* DUAL_CORE */ + +/** + * @brief Get AHB3 prescaler + * @rmtoll EXTCFGR SHDHPRE LL_RCC_GetAHB3Prescaler + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_SYSCLK_DIV_1 + * @arg @ref LL_RCC_SYSCLK_DIV_2 + * @arg @ref LL_RCC_SYSCLK_DIV_3 + * @arg @ref LL_RCC_SYSCLK_DIV_4 + * @arg @ref LL_RCC_SYSCLK_DIV_5 + * @arg @ref LL_RCC_SYSCLK_DIV_6 + * @arg @ref LL_RCC_SYSCLK_DIV_8 + * @arg @ref LL_RCC_SYSCLK_DIV_10 + * @arg @ref LL_RCC_SYSCLK_DIV_16 + * @arg @ref LL_RCC_SYSCLK_DIV_32 + * @arg @ref LL_RCC_SYSCLK_DIV_64 + * @arg @ref LL_RCC_SYSCLK_DIV_128 + * @arg @ref LL_RCC_SYSCLK_DIV_256 + * @arg @ref LL_RCC_SYSCLK_DIV_512 + */ +__STATIC_INLINE uint32_t LL_RCC_GetAHB3Prescaler(void) +{ + return (uint32_t)(READ_BIT(RCC->EXTCFGR, RCC_EXTCFGR_SHDHPRE) << 4); +} + +/** + * @brief Get APB1 prescaler + * @rmtoll CFGR PPRE1 LL_RCC_GetAPB1Prescaler + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_APB1_DIV_1 + * @arg @ref LL_RCC_APB1_DIV_2 + * @arg @ref LL_RCC_APB1_DIV_4 + * @arg @ref LL_RCC_APB1_DIV_8 + * @arg @ref LL_RCC_APB1_DIV_16 + */ +__STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1)); +} + +/** + * @brief Get APB2 prescaler + * @rmtoll CFGR PPRE2 LL_RCC_GetAPB2Prescaler + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_APB2_DIV_1 + * @arg @ref LL_RCC_APB2_DIV_2 + * @arg @ref LL_RCC_APB2_DIV_4 + * @arg @ref LL_RCC_APB2_DIV_8 + * @arg @ref LL_RCC_APB2_DIV_16 + */ +__STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2)); +} + +/** + * @brief Set Clock After Wake-Up From Stop mode + * @rmtoll CFGR STOPWUCK LL_RCC_SetClkAfterWakeFromStop + * @param Clock This parameter can be one of the following values: + * @arg @ref LL_RCC_STOP_WAKEUPCLOCK_MSI + * @arg @ref LL_RCC_STOP_WAKEUPCLOCK_HSI + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetClkAfterWakeFromStop(uint32_t Clock) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, Clock); +} + +/** + * @brief Get Clock After Wake-Up From Stop mode + * @rmtoll CFGR STOPWUCK LL_RCC_GetClkAfterWakeFromStop + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_STOP_WAKEUPCLOCK_MSI + * @arg @ref LL_RCC_STOP_WAKEUPCLOCK_HSI + */ +__STATIC_INLINE uint32_t LL_RCC_GetClkAfterWakeFromStop(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_STOPWUCK)); +} + +/** + * @} + */ + + +/** @defgroup RCC_LL_EF_MCO MCO + * @{ + */ + +/** + * @brief Configure MCOx + * @rmtoll CFGR MCOSEL LL_RCC_ConfigMCO\n + * CFGR MCOPRE LL_RCC_ConfigMCO + * @param MCOxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_MCO1SOURCE_NOCLOCK + * @arg @ref LL_RCC_MCO1SOURCE_SYSCLK + * @arg @ref LL_RCC_MCO1SOURCE_MSI + * @arg @ref LL_RCC_MCO1SOURCE_HSI + * @arg @ref LL_RCC_MCO1SOURCE_HSE + * @arg @ref LL_RCC_MCO1SOURCE_PLLCLK + * @arg @ref LL_RCC_MCO1SOURCE_LSI + * @arg @ref LL_RCC_MCO1SOURCE_LSE + * @arg @ref LL_RCC_MCO1SOURCE_PLLQCLK + * @arg @ref LL_RCC_MCO1SOURCE_PLLPCLK + * @param MCOxPrescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_MCO1_DIV_1 + * @arg @ref LL_RCC_MCO1_DIV_2 + * @arg @ref LL_RCC_MCO1_DIV_4 + * @arg @ref LL_RCC_MCO1_DIV_8 + * @arg @ref LL_RCC_MCO1_DIV_16 + * @retval None + */ +__STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE, MCOxSource | MCOxPrescaler); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source + * @{ + */ + +/** + * @brief Configure USARTx clock source + * @rmtoll CCIPR USART1SEL LL_RCC_SetUSARTClockSource + * @param USARTxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2 + * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI + * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE + * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI + * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t USARTxSource) +{ + MODIFY_REG(RCC->CCIPR, (USARTxSource >> 16), (USARTxSource & 0x0000FFFFU)); +} + +/** + * @brief Configure I2Sx clock source + * @rmtoll CCIPR I2S2SEL LL_RCC_SetI2SClockSource + * @param I2SxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_I2S2_CLKSOURCE_PLL + * @arg @ref LL_RCC_I2S2_CLKSOURCE_HSI + * @arg @ref LL_RCC_I2S2_CLKSOURCE_PIN + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetI2SClockSource(uint32_t I2SxSource) +{ + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2S2SEL, I2SxSource); +} + +/** + * @brief Configure LPUARTx clock source + * @rmtoll CCIPR LPUART1SEL LL_RCC_SetLPUARTClockSource + * @param LPUARTxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetLPUARTClockSource(uint32_t LPUARTxSource) +{ + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, LPUARTxSource); +} + +/** + * @brief Configure I2Cx clock source + * @rmtoll CCIPR I2CxSEL LL_RCC_SetI2CClockSource + * @param I2CxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI + * @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI + * @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t I2CxSource) +{ + MODIFY_REG(RCC->CCIPR, ((I2CxSource >> 4) & 0x000FF000U), ((I2CxSource << 4) & 0x000FF000U)); +} + +/** + * @brief Configure LPTIMx clock source + * @rmtoll CCIPR LPTIMxSEL LL_RCC_SetLPTIMClockSource + * @param LPTIMxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_HSI + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE + * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_LSI + * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_HSI + * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_LSE + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource) +{ + MODIFY_REG(RCC->CCIPR, (LPTIMxSource & 0xFFFF0000U), (LPTIMxSource << 16)); +} + +/** + * @brief Configure RNG clock source + * @rmtoll CCIPR RNGSEL LL_RCC_SetRNGClockSource + * @param RNGxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL + * @arg @ref LL_RCC_RNG_CLKSOURCE_LSI + * @arg @ref LL_RCC_RNG_CLKSOURCE_LSE + * @arg @ref LL_RCC_RNG_CLKSOURCE_MSI + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetRNGClockSource(uint32_t RNGxSource) +{ + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_RNGSEL, RNGxSource); +} + + +/** + * @brief Configure ADC clock source + * @rmtoll CCIPR ADCSEL LL_RCC_SetADCClockSource + * @param ADCxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_ADC_CLKSOURCE_NONE + * @arg @ref LL_RCC_ADC_CLKSOURCE_PLL + * @arg @ref LL_RCC_ADC_CLKSOURCE_SYSCLK + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ADCxSource) +{ + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADCSEL, ADCxSource); +} + +/** + * @brief Get USARTx clock source + * @rmtoll CCIPR USART1SEL LL_RCC_GetUSARTClockSource + * @param USARTx This parameter can be one of the following values: + * @arg @ref LL_RCC_USART1_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2 + * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI + * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE + * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI + * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE + */ +__STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t USARTx) +{ + return (uint32_t)(READ_BIT(RCC->CCIPR, USARTx) | (USARTx << 16)); +} + +/** + * @brief Get I2Sx clock source + * @rmtoll CCIPR I2S2SEL LL_RCC_GetI2SClockSource + * @param I2Sx This parameter can be one of the following values: + * @arg @ref LL_RCC_I2S2_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_I2S2_CLKSOURCE_PLL + * @arg @ref LL_RCC_I2S2_CLKSOURCE_HSI + * @arg @ref LL_RCC_I2S2_CLKSOURCE_PIN + */ +__STATIC_INLINE uint32_t LL_RCC_GetI2SClockSource(uint32_t I2Sx) +{ + return (uint32_t)(READ_BIT(RCC->CCIPR, I2Sx)); +} + +/** + * @brief Get LPUARTx clock source + * @rmtoll CCIPR LPUART1SEL LL_RCC_GetLPUARTClockSource + * @param LPUARTx This parameter can be one of the following values: + * @arg @ref LL_RCC_LPUART1_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE + */ +__STATIC_INLINE uint32_t LL_RCC_GetLPUARTClockSource(uint32_t LPUARTx) +{ + return (uint32_t)(READ_BIT(RCC->CCIPR, LPUARTx)); +} + +/** + * @brief Get I2Cx clock source + * @rmtoll CCIPR I2CxSEL LL_RCC_GetI2CClockSource + * @param I2Cx This parameter can be one of the following values: + * @arg @ref LL_RCC_I2C1_CLKSOURCE + * @arg @ref LL_RCC_I2C3_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI + * @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI + * @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI + */ +__STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t I2Cx) +{ + return (uint32_t)((READ_BIT(RCC->CCIPR, I2Cx) >> 4) | (I2Cx << 4)); +} + +/** + * @brief Get LPTIMx clock source + * @rmtoll CCIPR LPTIMxSEL LL_RCC_GetLPTIMClockSource + * @param LPTIMx This parameter can be one of the following values: + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE + * @arg @ref LL_RCC_LPTIM3_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_HSI + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE + * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_LSI + * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_HSI + * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_LSE + + */ +__STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx) +{ + return (uint32_t)((READ_BIT(RCC->CCIPR, LPTIMx) >> 16) | LPTIMx); +} + +/** + * @brief Get RNGx clock source + * @rmtoll CCIPR RNGSEL LL_RCC_GetRNGClockSource + * @param RNGx This parameter can be one of the following values: + * @arg @ref LL_RCC_RNG_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL + * @arg @ref LL_RCC_RNG_CLKSOURCE_LSI + * @arg @ref LL_RCC_RNG_CLKSOURCE_LSE + * @arg @ref LL_RCC_RNG_CLKSOURCE_MSI + */ +__STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource(uint32_t RNGx) +{ + return (uint32_t)(READ_BIT(RCC->CCIPR, RNGx)); +} + +/** + * @brief Get ADCx clock source + * @rmtoll CCIPR ADCSEL LL_RCC_GetADCClockSource + * @param ADCx This parameter can be one of the following values: + * @arg @ref LL_RCC_ADC_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_ADC_CLKSOURCE_NONE + * @arg @ref LL_RCC_ADC_CLKSOURCE_HSI + * @arg @ref LL_RCC_ADC_CLKSOURCE_PLL + * @arg @ref LL_RCC_ADC_CLKSOURCE_SYSCLK + */ +__STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t ADCx) +{ + return (uint32_t)(READ_BIT(RCC->CCIPR, ADCx)); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_RTC RTC + * @{ + */ + +/** + * @brief Set RTC Clock Source + * @note Once the RTC clock source has been selected, it cannot be changed anymore unless + * the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is + * set). The BDRST bit can be used to reset them. + * @rmtoll BDCR RTCSEL LL_RCC_SetRTCClockSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE + * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE + * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI + * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source) +{ + MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source); +} + +/** + * @brief Get RTC Clock Source + * @rmtoll BDCR RTCSEL LL_RCC_GetRTCClockSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE + * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE + * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI + * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32 + */ +__STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void) +{ + return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)); +} + +/** + * @brief Enable RTC + * @rmtoll BDCR RTCEN LL_RCC_EnableRTC + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableRTC(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN); +} + +/** + * @brief Disable RTC + * @rmtoll BDCR RTCEN LL_RCC_DisableRTC + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableRTC(void) +{ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN); +} + +/** + * @brief Check if RTC has been enabled or not + * @rmtoll BDCR RTCEN LL_RCC_IsEnabledRTC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void) +{ + return ((READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN)) ? 1UL : 0UL); +} + +/** + * @brief Force the Backup domain reset + * @rmtoll BDCR BDRST LL_RCC_ForceBackupDomainReset + * @retval None + */ +__STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_BDRST); +} + +/** + * @brief Release the Backup domain reset + * @rmtoll BDCR BDRST LL_RCC_ReleaseBackupDomainReset + * @retval None + */ +__STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void) +{ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST); +} + +/** + * @} + */ + + +/** @defgroup RCC_LL_EF_PLL PLL + * @{ + */ + +/** + * @brief Enable PLL + * @rmtoll CR PLLON LL_RCC_PLL_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_Enable(void) +{ + SET_BIT(RCC->CR, RCC_CR_PLLON); +} + +/** + * @brief Disable PLL + * @note Cannot be disabled if the PLL clock is used as the system clock + * @rmtoll CR PLLON LL_RCC_PLL_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_Disable(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_PLLON); +} + +/** + * @brief Check if PLL Ready + * @rmtoll CR PLLRDY LL_RCC_PLL_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void) +{ + return ((READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY)) ? 1UL : 0UL); +} + +/** + * @brief Configure PLL used for SYSCLK Domain + * @note PLL Source and PLLM Divider can be written only when PLL is disabled + * @note PLLN/PLLR can be written only when PLL is disabled + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n + * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SYS\n + * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SYS\n + * PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_SYS + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_NONE + * @arg @ref LL_RCC_PLLSOURCE_MSI + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @param PLLM This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_1 + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @param PLLN Between 6 and 127 + * @param PLLR This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLR_DIV_2 + * @arg @ref LL_RCC_PLLR_DIV_3 + * @arg @ref LL_RCC_PLLR_DIV_4 + * @arg @ref LL_RCC_PLLR_DIV_5 + * @arg @ref LL_RCC_PLLR_DIV_6 + * @arg @ref LL_RCC_PLLR_DIV_7 + * @arg @ref LL_RCC_PLLR_DIV_8 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLR, + Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLR); +} + +/** + * @brief Configure PLL used for ADC domain clock + * @note PLL Source and PLLM Divider can be written only when PLL is disabled + * @note PLLN/PLLP can be written only when PLL is disabled + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_ADC\n + * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_ADC\n + * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_ADC\n + * PLLCFGR PLLP LL_RCC_PLL_ConfigDomain_ADC + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_NONE + * @arg @ref LL_RCC_PLLSOURCE_MSI + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @param PLLM This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_1 + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @param PLLN Between 6 and 127 + * @param PLLP This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLP_DIV_2 + * @arg @ref LL_RCC_PLLP_DIV_3 + * @arg @ref LL_RCC_PLLP_DIV_4 + * @arg @ref LL_RCC_PLLP_DIV_5 + * @arg @ref LL_RCC_PLLP_DIV_6 + * @arg @ref LL_RCC_PLLP_DIV_7 + * @arg @ref LL_RCC_PLLP_DIV_8 + * @arg @ref LL_RCC_PLLP_DIV_9 + * @arg @ref LL_RCC_PLLP_DIV_10 + * @arg @ref LL_RCC_PLLP_DIV_11 + * @arg @ref LL_RCC_PLLP_DIV_12 + * @arg @ref LL_RCC_PLLP_DIV_13 + * @arg @ref LL_RCC_PLLP_DIV_14 + * @arg @ref LL_RCC_PLLP_DIV_15 + * @arg @ref LL_RCC_PLLP_DIV_16 + * @arg @ref LL_RCC_PLLP_DIV_17 + * @arg @ref LL_RCC_PLLP_DIV_18 + * @arg @ref LL_RCC_PLLP_DIV_19 + * @arg @ref LL_RCC_PLLP_DIV_20 + * @arg @ref LL_RCC_PLLP_DIV_21 + * @arg @ref LL_RCC_PLLP_DIV_22 + * @arg @ref LL_RCC_PLLP_DIV_23 + * @arg @ref LL_RCC_PLLP_DIV_24 + * @arg @ref LL_RCC_PLLP_DIV_25 + * @arg @ref LL_RCC_PLLP_DIV_26 + * @arg @ref LL_RCC_PLLP_DIV_27 + * @arg @ref LL_RCC_PLLP_DIV_28 + * @arg @ref LL_RCC_PLLP_DIV_29 + * @arg @ref LL_RCC_PLLP_DIV_30 + * @arg @ref LL_RCC_PLLP_DIV_31 + * @arg @ref LL_RCC_PLLP_DIV_32 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_ADC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLP, + Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLP); +} + +/** + * @brief Configure PLL used for RNG domain clock + * @note PLL Source and PLLM Divider can be written only when PLL is disabled + * @note PLLN/PLLQ can be written only when PLL is disabled + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_RNG\n + * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_RNG\n + * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_RNG\n + * PLLCFGR PLLQ LL_RCC_PLL_ConfigDomain_RNG + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_NONE + * @arg @ref LL_RCC_PLLSOURCE_MSI + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @param PLLM This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_1 + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @param PLLN Between 6 and 127 + * @param PLLQ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLQ_DIV_2 + * @arg @ref LL_RCC_PLLQ_DIV_3 + * @arg @ref LL_RCC_PLLQ_DIV_4 + * @arg @ref LL_RCC_PLLQ_DIV_5 + * @arg @ref LL_RCC_PLLQ_DIV_6 + * @arg @ref LL_RCC_PLLQ_DIV_7 + * @arg @ref LL_RCC_PLLQ_DIV_8 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_RNG(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLQ, + Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLQ); +} + +/** + * @brief Configure PLL used for I2S domain clock + * @note PLL Source and PLLM Divider can be written only when PLL is disabled + * @note PLLN/PLLQ can be written only when PLL is disabled + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_I2S\n + * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_I2S\n + * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_I2S\n + * PLLCFGR PLLQ LL_RCC_PLL_ConfigDomain_I2S + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_NONE + * @arg @ref LL_RCC_PLLSOURCE_MSI + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @param PLLM This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_1 + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @param PLLN Between 6 and 127 + * @param PLLQ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLQ_DIV_2 + * @arg @ref LL_RCC_PLLQ_DIV_3 + * @arg @ref LL_RCC_PLLQ_DIV_4 + * @arg @ref LL_RCC_PLLQ_DIV_5 + * @arg @ref LL_RCC_PLLQ_DIV_6 + * @arg @ref LL_RCC_PLLQ_DIV_7 + * @arg @ref LL_RCC_PLLQ_DIV_8 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_I2S(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLQ, + Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLQ); +} + +/** + * @brief Get Main PLL multiplication factor for VCO + * @rmtoll PLLCFGR PLLN LL_RCC_PLL_GetN + * @retval Between 6 and 127 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_GetN(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); +} + +/** + * @brief Get Main PLL division factor for PLLP + * @rmtoll PLLCFGR PLLP LL_RCC_PLL_GetP + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLP_DIV_2 + * @arg @ref LL_RCC_PLLP_DIV_3 + * @arg @ref LL_RCC_PLLP_DIV_4 + * @arg @ref LL_RCC_PLLP_DIV_5 + * @arg @ref LL_RCC_PLLP_DIV_6 + * @arg @ref LL_RCC_PLLP_DIV_7 + * @arg @ref LL_RCC_PLLP_DIV_8 + * @arg @ref LL_RCC_PLLP_DIV_9 + * @arg @ref LL_RCC_PLLP_DIV_10 + * @arg @ref LL_RCC_PLLP_DIV_11 + * @arg @ref LL_RCC_PLLP_DIV_12 + * @arg @ref LL_RCC_PLLP_DIV_13 + * @arg @ref LL_RCC_PLLP_DIV_14 + * @arg @ref LL_RCC_PLLP_DIV_15 + * @arg @ref LL_RCC_PLLP_DIV_16 + * @arg @ref LL_RCC_PLLP_DIV_17 + * @arg @ref LL_RCC_PLLP_DIV_18 + * @arg @ref LL_RCC_PLLP_DIV_19 + * @arg @ref LL_RCC_PLLP_DIV_20 + * @arg @ref LL_RCC_PLLP_DIV_21 + * @arg @ref LL_RCC_PLLP_DIV_22 + * @arg @ref LL_RCC_PLLP_DIV_23 + * @arg @ref LL_RCC_PLLP_DIV_24 + * @arg @ref LL_RCC_PLLP_DIV_25 + * @arg @ref LL_RCC_PLLP_DIV_26 + * @arg @ref LL_RCC_PLLP_DIV_27 + * @arg @ref LL_RCC_PLLP_DIV_28 + * @arg @ref LL_RCC_PLLP_DIV_29 + * @arg @ref LL_RCC_PLLP_DIV_30 + * @arg @ref LL_RCC_PLLP_DIV_31 + * @arg @ref LL_RCC_PLLP_DIV_32 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_GetP(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP)); +} + +/** + * @brief Get Main PLL division factor for PLLQ + * @note used for PLL48MCLK selected for USB, RNG (48 MHz clock) + * @rmtoll PLLCFGR PLLQ LL_RCC_PLL_GetQ + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLQ_DIV_2 + * @arg @ref LL_RCC_PLLQ_DIV_3 + * @arg @ref LL_RCC_PLLQ_DIV_4 + * @arg @ref LL_RCC_PLLQ_DIV_5 + * @arg @ref LL_RCC_PLLQ_DIV_6 + * @arg @ref LL_RCC_PLLQ_DIV_7 + * @arg @ref LL_RCC_PLLQ_DIV_8 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_GetQ(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ)); +} + +/** + * @brief Get Main PLL division factor for PLLR + * @note used for PLLCLK (system clock) + * @rmtoll PLLCFGR PLLR LL_RCC_PLL_GetR + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLR_DIV_2 + * @arg @ref LL_RCC_PLLR_DIV_3 + * @arg @ref LL_RCC_PLLR_DIV_4 + * @arg @ref LL_RCC_PLLR_DIV_5 + * @arg @ref LL_RCC_PLLR_DIV_6 + * @arg @ref LL_RCC_PLLR_DIV_7 + * @arg @ref LL_RCC_PLLR_DIV_8 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_GetR(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR)); +} + +/** + * @brief Get Division factor for the main PLL and other PLL + * @rmtoll PLLCFGR PLLM LL_RCC_PLL_GetDivider + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_1 + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_GetDivider(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM)); +} + +/** + * @brief Enable PLL output mapped on ADC domain clock + * @rmtoll PLLCFGR PLLPEN LL_RCC_PLL_EnableDomain_ADC + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_EnableDomain_ADC(void) +{ + SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN); +} + +/** + * @brief Disable PLL output mapped on ADC domain clock + * @note In order to save power, when the PLLCLK of the PLL is + * not used, should be 0 + * @rmtoll PLLCFGR PLLPEN LL_RCC_PLL_DisableDomain_ADC + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_DisableDomain_ADC(void) +{ + CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN); +} + +/** + * @brief Check if PLL output mapped on ADC domain clock is enabled + * @rmtoll PLLCFGR RCC_PLLCFGR_PLLPEN LL_RCC_PLL_IsEnabledDomain_ADC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_IsEnabledDomain_ADC(void) +{ + return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN) == (RCC_PLLCFGR_PLLPEN)) ? 1UL : 0UL); +} + +/** + * @brief Enable PLL output mapped on RNG domain clock + * @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_EnableDomain_RNG + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_EnableDomain_RNG(void) +{ + SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN); +} + +/** + * @brief Disable PLL output mapped on RNG domain clock + * @note In order to save power, when the PLLCLK of the PLL is + * not used, should be 0 + * @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_DisableDomain_RNG + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_DisableDomain_RNG(void) +{ + CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN); +} + +/** + * @brief Check if PLL output mapped on RNG domain clock is enabled + * @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_IsEnabledDomain_RNG + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_IsEnabledDomain_RNG(void) +{ + return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN) == (RCC_PLLCFGR_PLLQEN)) ? 1UL : 0UL); +} + +/** + * @brief Enable PLL output mapped on I2S domain clock + * @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_EnableDomain_I2S + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_EnableDomain_I2S(void) +{ + SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN); +} + +/** + * @brief Disable PLL output mapped on I2S domain clock + * @note In order to save power, when the PLLCLK of the PLL is + * not used, should be 0 + * @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_DisableDomain_I2S + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_DisableDomain_I2S(void) +{ + CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN); +} + +/** + * @brief Check if PLL output mapped on I2S domain clock is enabled + * @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_IsEnabledDomain_I2S + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_IsEnabledDomain_I2S(void) +{ + return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN) == (RCC_PLLCFGR_PLLQEN)) ? 1UL : 0UL); +} + +/** + * @brief Enable PLL output mapped on SYSCLK domain + * @rmtoll PLLCFGR PLLREN LL_RCC_PLL_EnableDomain_SYS + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_EnableDomain_SYS(void) +{ + SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLREN); +} + +/** + * @brief Disable PLL output mapped on SYSCLK domain + * @note Cannot be disabled if the PLL clock is used as the system clock + * @note In order to save power, when the PLLCLK of the PLL is + * not used, Main PLL should be 0 + * @rmtoll PLLCFGR PLLREN LL_RCC_PLL_DisableDomain_SYS + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_DisableDomain_SYS(void) +{ + CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLREN); +} + +/** + * @brief Check if PLL output mapped on SYS domain clock is enabled + * @rmtoll PLLCFGR PLLREN LL_RCC_PLL_IsEnabledDomain_SYS + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_IsEnabledDomain_SYS(void) +{ + return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLREN) == (RCC_PLLCFGR_PLLREN)) ? 1UL : 0UL); +} + +/** + * @brief Configure PLL clock source + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_SetMainSource + * @param PLLSource This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_MSI + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_SetMainSource(uint32_t PLLSource) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PLLSource); +} + +/** + * @brief Get the oscillator used as PLL clock source. + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_GetMainSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_NONE + * @arg @ref LL_RCC_PLLSOURCE_MSI + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC)); +} + +/** + * @} + */ + + + +/** @defgroup RCC_LL_EF_FLAG_Management FLAG Management + * @{ + */ + +/** + * @brief Clear LSI ready interrupt flag + * @rmtoll CICR LSIRDYC LL_RCC_ClearFlag_LSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_LSIRDYC); +} + +/** + * @brief Clear LSE ready interrupt flag + * @rmtoll CICR LSERDYC LL_RCC_ClearFlag_LSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_LSERDYC); +} + +/** + * @brief Clear MSI ready interrupt flag + * @rmtoll CICR MSIRDYC LL_RCC_ClearFlag_MSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_MSIRDY(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_MSIRDYC); +} + +/** + * @brief Clear HSI ready interrupt flag + * @rmtoll CICR HSIRDYC LL_RCC_ClearFlag_HSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_HSIRDYC); +} + +/** + * @brief Clear HSE ready interrupt flag + * @rmtoll CICR HSERDYC LL_RCC_ClearFlag_HSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_HSERDYC); +} + +/** + * @brief Clear PLL ready interrupt flag + * @rmtoll CICR PLLRDYC LL_RCC_ClearFlag_PLLRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_PLLRDYC); +} + +/** + * @brief Clear Clock security system interrupt flag + * @rmtoll CICR CSSC LL_RCC_ClearFlag_HSECSS + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_CSSC); +} + +/** + * @brief Clear LSE Clock security system interrupt flag + * @rmtoll CICR LSECSSC LL_RCC_ClearFlag_LSECSS + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_LSECSS(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_LSECSSC); +} + +/** + * @brief Check if LSI ready interrupt occurred or not + * @rmtoll CIFR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSIRDYF) == (RCC_CIFR_LSIRDYF)) ? 1UL : 0UL); + +} + +/** + * @brief Check if LSE ready interrupt occurred or not + * @rmtoll CIFR LSERDYF LL_RCC_IsActiveFlag_LSERDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSERDYF) == (RCC_CIFR_LSERDYF)) ? 1UL : 0UL); +} + +/** + * @brief Check if MSI ready interrupt occurred or not + * @rmtoll CIFR MSIRDYF LL_RCC_IsActiveFlag_MSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_MSIRDY(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_MSIRDYF) == (RCC_CIFR_MSIRDYF)) ? 1UL : 0UL); +} + +/** + * @brief Check if HSI ready interrupt occurred or not + * @rmtoll CIFR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSIRDYF) == (RCC_CIFR_HSIRDYF)) ? 1UL : 0UL); +} + +/** + * @brief Check if HSE ready interrupt occurred or not + * @rmtoll CIFR HSERDYF LL_RCC_IsActiveFlag_HSERDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSERDYF) == (RCC_CIFR_HSERDYF)) ? 1UL : 0UL); +} + +/** + * @brief Check if PLL ready interrupt occurred or not + * @rmtoll CIFR PLLRDYF LL_RCC_IsActiveFlag_PLLRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLLRDYF) == (RCC_CIFR_PLLRDYF)) ? 1UL : 0UL); + +} + +/** + * @brief Check if Clock security system interrupt occurred or not + * @rmtoll CIFR CSSF LL_RCC_IsActiveFlag_HSECSS + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_CSSF) == (RCC_CIFR_CSSF)) ? 1UL : 0UL); +} + +/** + * @brief Check if LSE Clock security system interrupt occurred or not + * @rmtoll CIFR LSECSSF LL_RCC_IsActiveFlag_LSECSS + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSECSS(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSECSSF) == (RCC_CIFR_LSECSSF)) ? 1UL : 0UL); +} + +/** + * @brief Check if HCLK1 prescaler flag value has been applied or not + * @rmtoll CFGR HPREF LL_RCC_IsActiveFlag_HPRE + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HPRE(void) +{ + return ((READ_BIT(RCC->CFGR, RCC_CFGR_HPREF) == (RCC_CFGR_HPREF)) ? 1UL : 0UL); +} + +#if defined(DUAL_CORE) +/** + * @brief Check if HCLK2 prescaler flag value has been applied or not + * @rmtoll EXTCFGR C2HPREF LL_RCC_IsActiveFlag_C2HPRE + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_C2HPRE(void) +{ + return ((READ_BIT(RCC->EXTCFGR, RCC_EXTCFGR_C2HPREF) == (RCC_EXTCFGR_C2HPREF)) ? 1UL : 0UL); +} +#endif /* DUAL_CORE */ + +/** + * @brief Check if HCLK3 prescaler flag value has been applied or not + * @rmtoll EXTCFGR SHDHPREF LL_RCC_IsActiveFlag_SHDHPRE + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SHDHPRE(void) +{ + return ((READ_BIT(RCC->EXTCFGR, RCC_EXTCFGR_SHDHPREF) == (RCC_EXTCFGR_SHDHPREF)) ? 1UL : 0UL); +} + + +/** + * @brief Check if PLCK1 prescaler flag value has been applied or not + * @rmtoll CFGR PPRE1F LL_RCC_IsActiveFlag_PPRE1 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PPRE1(void) +{ + return ((READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1F) == (RCC_CFGR_PPRE1F)) ? 1UL : 0UL); +} + +/** + * @brief Check if PLCK2 prescaler flag value has been applied or not + * @rmtoll CFGR PPRE2F LL_RCC_IsActiveFlag_PPRE2 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PPRE2(void) +{ + return ((READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2F) == (RCC_CFGR_PPRE2F)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC flag Independent Watchdog reset is set or not. + * @rmtoll CSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void) +{ + return ((READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == (RCC_CSR_IWDGRSTF)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC flag Radio illegal access is set or not. + * @rmtoll CSR RFILARSTF LL_RCC_IsActiveFlag_RFILARST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_RFILARST(void) +{ + return ((READ_BIT(RCC->CSR, RCC_CSR_RFILARSTF) == (RCC_CSR_RFILARSTF)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC flag Low Power reset is set or not. + * @rmtoll CSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void) +{ + return ((READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == (RCC_CSR_LPWRRSTF)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC flag Option byte reset is set or not. + * @rmtoll CSR OBLRSTF LL_RCC_IsActiveFlag_OBLRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_OBLRST(void) +{ + return ((READ_BIT(RCC->CSR, RCC_CSR_OBLRSTF) == (RCC_CSR_OBLRSTF)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC flag Pin reset is set or not. + * @rmtoll CSR PINRSTF LL_RCC_IsActiveFlag_PINRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void) +{ + return ((READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == (RCC_CSR_PINRSTF)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC flag Software reset is set or not. + * @rmtoll CSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void) +{ + return ((READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == (RCC_CSR_SFTRSTF)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC flag Window Watchdog reset is set or not. + * @rmtoll CSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void) +{ + return ((READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == (RCC_CSR_WWDGRSTF)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC flag BOR reset is set or not. + * @rmtoll CSR BORRSTF LL_RCC_IsActiveFlag_BORRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_BORRST(void) +{ + return ((READ_BIT(RCC->CSR, RCC_CSR_BORRSTF) == (RCC_CSR_BORRSTF)) ? 1UL : 0UL); +} + +/** + * @brief Set RMVF bit to clear the reset flags. + * @rmtoll CSR RMVF LL_RCC_ClearResetFlags + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearResetFlags(void) +{ + SET_BIT(RCC->CSR, RCC_CSR_RMVF); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_IT_Management IT Management + * @{ + */ + +/** + * @brief Enable LSI ready interrupt + * @rmtoll CIER LSIRDYIE LL_RCC_EnableIT_LSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void) +{ + SET_BIT(RCC->CIER, RCC_CIER_LSIRDYIE); +} + +/** + * @brief Enable LSE ready interrupt + * @rmtoll CIER LSERDYIE LL_RCC_EnableIT_LSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void) +{ + SET_BIT(RCC->CIER, RCC_CIER_LSERDYIE); +} + +/** + * @brief Enable MSI ready interrupt + * @rmtoll CIER MSIRDYIE LL_RCC_EnableIT_MSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_MSIRDY(void) +{ + SET_BIT(RCC->CIER, RCC_CIER_MSIRDYIE); +} + +/** + * @brief Enable HSI ready interrupt + * @rmtoll CIER HSIRDYIE LL_RCC_EnableIT_HSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void) +{ + SET_BIT(RCC->CIER, RCC_CIER_HSIRDYIE); +} + +/** + * @brief Enable HSE ready interrupt + * @rmtoll CIER HSERDYIE LL_RCC_EnableIT_HSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void) +{ + SET_BIT(RCC->CIER, RCC_CIER_HSERDYIE); +} + +/** + * @brief Enable PLL ready interrupt + * @rmtoll CIER PLLRDYIE LL_RCC_EnableIT_PLLRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void) +{ + SET_BIT(RCC->CIER, RCC_CIER_PLLRDYIE); +} + +/** + * @brief Enable LSE clock security system interrupt + * @rmtoll CIER LSECSSIE LL_RCC_EnableIT_LSECSS + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_LSECSS(void) +{ + SET_BIT(RCC->CIER, RCC_CIER_LSECSSIE); +} + +/** + * @brief Disable LSI ready interrupt + * @rmtoll CIER LSIRDYIE LL_RCC_DisableIT_LSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void) +{ + CLEAR_BIT(RCC->CIER, RCC_CIER_LSIRDYIE); +} + +/** + * @brief Disable LSE ready interrupt + * @rmtoll CIER LSERDYIE LL_RCC_DisableIT_LSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void) +{ + CLEAR_BIT(RCC->CIER, RCC_CIER_LSERDYIE); +} + +/** + * @brief Disable MSI ready interrupt + * @rmtoll CIER MSIRDYIE LL_RCC_DisableIT_MSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_MSIRDY(void) +{ + CLEAR_BIT(RCC->CIER, RCC_CIER_MSIRDYIE); +} + +/** + * @brief Disable HSI ready interrupt + * @rmtoll CIER HSIRDYIE LL_RCC_DisableIT_HSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void) +{ + CLEAR_BIT(RCC->CIER, RCC_CIER_HSIRDYIE); +} + +/** + * @brief Disable HSE ready interrupt + * @rmtoll CIER HSERDYIE LL_RCC_DisableIT_HSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void) +{ + CLEAR_BIT(RCC->CIER, RCC_CIER_HSERDYIE); +} + +/** + * @brief Disable PLL ready interrupt + * @rmtoll CIER PLLRDYIE LL_RCC_DisableIT_PLLRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void) +{ + CLEAR_BIT(RCC->CIER, RCC_CIER_PLLRDYIE); +} + +/** + * @brief Disable LSE clock security system interrupt + * @rmtoll CIER LSECSSIE LL_RCC_DisableIT_LSECSS + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_LSECSS(void) +{ + CLEAR_BIT(RCC->CIER, RCC_CIER_LSECSSIE); +} + +/** + * @brief Checks if LSI ready interrupt source is enabled or disabled. + * @rmtoll CIER LSIRDYIE LL_RCC_IsEnabledIT_LSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void) +{ + return ((READ_BIT(RCC->CIER, RCC_CIER_LSIRDYIE) == (RCC_CIER_LSIRDYIE)) ? 1UL : 0UL); +} + +/** + * @brief Checks if LSE ready interrupt source is enabled or disabled. + * @rmtoll CIER LSERDYIE LL_RCC_IsEnabledIT_LSERDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void) +{ + return ((READ_BIT(RCC->CIER, RCC_CIER_LSERDYIE) == (RCC_CIER_LSERDYIE)) ? 1UL : 0UL); +} + +/** + * @brief Checks if MSI ready interrupt source is enabled or disabled. + * @rmtoll CIER MSIRDYIE LL_RCC_IsEnabledIT_MSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_MSIRDY(void) +{ + return ((READ_BIT(RCC->CIER, RCC_CIER_MSIRDYIE) == (RCC_CIER_MSIRDYIE)) ? 1UL : 0UL); +} + +/** + * @brief Checks if HSI ready interrupt source is enabled or disabled. + * @rmtoll CIER HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void) +{ + return ((READ_BIT(RCC->CIER, RCC_CIER_HSIRDYIE) == (RCC_CIER_HSIRDYIE)) ? 1UL : 0UL); +} + +/** + * @brief Checks if HSE ready interrupt source is enabled or disabled. + * @rmtoll CIER HSERDYIE LL_RCC_IsEnabledIT_HSERDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void) +{ + return ((READ_BIT(RCC->CIER, RCC_CIER_HSERDYIE) == (RCC_CIER_HSERDYIE)) ? 1UL : 0UL); +} + +/** + * @brief Checks if PLL ready interrupt source is enabled or disabled. + * @rmtoll CIER PLLRDYIE LL_RCC_IsEnabledIT_PLLRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void) +{ + return ((READ_BIT(RCC->CIER, RCC_CIER_PLLRDYIE) == (RCC_CIER_PLLRDYIE)) ? 1UL : 0UL); + +} + +/** + * @brief Checks if LSECSS interrupt source is enabled or disabled. + * @rmtoll CIER LSECSSIE LL_RCC_IsEnabledIT_LSECSS + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSECSS(void) +{ + return ((READ_BIT(RCC->CIER, RCC_CIER_LSECSSIE) == (RCC_CIER_LSECSSIE)) ? 1UL : 0UL); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RCC_LL_EF_Init De-initialization function + * @{ + */ +ErrorStatus LL_RCC_DeInit(void); +/** + * @} + */ + +/** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions + * @{ + */ +void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks); +uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource); +uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource); +uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource); +uint32_t LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource); +uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource); +uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource); +uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource); +uint32_t LL_RCC_GetRTCClockFreq(void); +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(RCC) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32WLxx_LL_RCC_H */ diff --git a/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rtc.h b/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rtc.h new file mode 100644 index 0000000..a5157c3 --- /dev/null +++ b/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rtc.h @@ -0,0 +1,4608 @@ +/** + ****************************************************************************** + * @file stm32wlxx_ll_rtc.h + * @author MCD Application Team + * @brief Header file of RTC LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32WLxx_LL_RTC_H +#define STM32WLxx_LL_RTC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wlxx.h" + +/** @addtogroup STM32WLxx_LL_Driver + * @{ + */ + +#if defined(RTC) + +/** @defgroup RTC_LL RTC + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup RTC_LL_Private_Constants RTC Private Constants + * @{ + */ +/* Masks Definition */ +#define RTC_LL_INIT_MASK 0xFFFFFFFFU +#define RTC_LL_RSF_MASK 0xFFFFFF5FU + +/* Write protection defines */ +#define RTC_WRITE_PROTECTION_DISABLE (uint8_t)0xFF +#define RTC_WRITE_PROTECTION_ENABLE_1 (uint8_t)0xCA +#define RTC_WRITE_PROTECTION_ENABLE_2 (uint8_t)0x53 + +/* Defines used to combine date & time */ +#define RTC_OFFSET_WEEKDAY 24U +#define RTC_OFFSET_DAY 16U +#define RTC_OFFSET_MONTH 8U +#define RTC_OFFSET_HOUR 16U +#define RTC_OFFSET_MINUTE 8U + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RTC_LL_Private_Macros RTC Private Macros + * @{ + */ +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +#if !defined (UNUSED) +#define UNUSED(x) ((void)(x)) +#endif /* !UNUSED */ + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RTC_LL_ES_INIT RTC Exported Init structure + * @{ + */ + +/** + * @brief RTC Init structures definition + */ +typedef struct +{ + uint32_t HourFormat; /*!< Specifies the RTC Hours Format. + This parameter can be a value of @ref RTC_LL_EC_HOURFORMAT + + This feature can be modified afterwards using unitary function + @ref LL_RTC_SetHourFormat(). */ + + uint32_t AsynchPrescaler; /*!< Specifies the RTC Asynchronous Predivider value. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F + + This feature can be modified afterwards using unitary function + @ref LL_RTC_SetAsynchPrescaler(). */ + + uint32_t SynchPrescaler; /*!< Specifies the RTC Synchronous Predivider value. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FFF + + This feature can be modified afterwards using unitary function + @ref LL_RTC_SetSynchPrescaler(). */ +} LL_RTC_InitTypeDef; + +/** + * @brief RTC Time structure definition + */ +typedef struct +{ + uint32_t TimeFormat; /*!< Specifies the RTC AM/PM Time. + This parameter can be a value of @ref RTC_LL_EC_TIME_FORMAT + + This feature can be modified afterwards using unitary function @ref LL_RTC_TIME_SetFormat(). */ + + uint8_t Hours; /*!< Specifies the RTC Time Hours. + This parameter must be a number between Min_Data = 0 and Max_Data = 12 if the @ref LL_RTC_TIME_FORMAT_PM is selected. + This parameter must be a number between Min_Data = 0 and Max_Data = 23 if the @ref LL_RTC_TIME_FORMAT_AM_OR_24 is selected. + + This feature can be modified afterwards using unitary function @ref LL_RTC_TIME_SetHour(). */ + + uint8_t Minutes; /*!< Specifies the RTC Time Minutes. + This parameter must be a number between Min_Data = 0 and Max_Data = 59 + + This feature can be modified afterwards using unitary function @ref LL_RTC_TIME_SetMinute(). */ + + uint8_t Seconds; /*!< Specifies the RTC Time Seconds. + This parameter must be a number between Min_Data = 0 and Max_Data = 59 + + This feature can be modified afterwards using unitary function @ref LL_RTC_TIME_SetSecond(). */ +} LL_RTC_TimeTypeDef; + +/** + * @brief RTC Date structure definition + */ +typedef struct +{ + uint8_t WeekDay; /*!< Specifies the RTC Date WeekDay. + This parameter can be a value of @ref RTC_LL_EC_WEEKDAY + + This feature can be modified afterwards using unitary function @ref LL_RTC_DATE_SetWeekDay(). */ + + uint8_t Month; /*!< Specifies the RTC Date Month. + This parameter can be a value of @ref RTC_LL_EC_MONTH + + This feature can be modified afterwards using unitary function @ref LL_RTC_DATE_SetMonth(). */ + + uint8_t Day; /*!< Specifies the RTC Date Day. + This parameter must be a number between Min_Data = 1 and Max_Data = 31 + + This feature can be modified afterwards using unitary function @ref LL_RTC_DATE_SetDay(). */ + + uint8_t Year; /*!< Specifies the RTC Date Year. + This parameter must be a number between Min_Data = 0 and Max_Data = 99 + + This feature can be modified afterwards using unitary function @ref LL_RTC_DATE_SetYear(). */ +} LL_RTC_DateTypeDef; + +/** + * @brief RTC Alarm structure definition + */ +typedef struct +{ + LL_RTC_TimeTypeDef AlarmTime; /*!< Specifies the RTC Alarm Time members. */ + + uint32_t AlarmMask; /*!< Specifies the RTC Alarm Masks. + This parameter can be a value of @ref RTC_LL_EC_ALMA_MASK for ALARM A or @ref RTC_LL_EC_ALMB_MASK for ALARM B. + + This feature can be modified afterwards using unitary function @ref LL_RTC_ALMA_SetMask() for ALARM A + or @ref LL_RTC_ALMB_SetMask() for ALARM B + */ + + uint32_t AlarmDateWeekDaySel; /*!< Specifies the RTC Alarm is on day or WeekDay. + This parameter can be a value of @ref RTC_LL_EC_ALMA_WEEKDAY_SELECTION for ALARM A or @ref RTC_LL_EC_ALMB_WEEKDAY_SELECTION for ALARM B + + This feature can be modified afterwards using unitary function @ref LL_RTC_ALMA_EnableWeekday() or @ref LL_RTC_ALMA_DisableWeekday() + for ALARM A or @ref LL_RTC_ALMB_EnableWeekday() or @ref LL_RTC_ALMB_DisableWeekday() for ALARM B + */ + + uint8_t AlarmDateWeekDay; /*!< Specifies the RTC Alarm Day/WeekDay. + If AlarmDateWeekDaySel set to day, this parameter must be a number between Min_Data = 1 and Max_Data = 31. + + This feature can be modified afterwards using unitary function @ref LL_RTC_ALMA_SetDay() + for ALARM A or @ref LL_RTC_ALMB_SetDay() for ALARM B. + + If AlarmDateWeekDaySel set to Weekday, this parameter can be a value of @ref RTC_LL_EC_WEEKDAY. + + This feature can be modified afterwards using unitary function @ref LL_RTC_ALMA_SetWeekDay() + for ALARM A or @ref LL_RTC_ALMB_SetWeekDay() for ALARM B. + */ +} LL_RTC_AlarmTypeDef; + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup RTC_LL_Exported_Constants RTC Exported Constants + * @{ + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RTC_LL_EC_FORMAT FORMAT + * @{ + */ +#define LL_RTC_FORMAT_BIN 0x00000000U /*!< Binary data format */ +#define LL_RTC_FORMAT_BCD 0x00000001U /*!< BCD data format */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_ALMA_WEEKDAY_SELECTION RTC Alarm A Date WeekDay + * @{ + */ +#define LL_RTC_ALMA_DATEWEEKDAYSEL_DATE 0x00000000U /*!< Alarm A Date is selected */ +#define LL_RTC_ALMA_DATEWEEKDAYSEL_WEEKDAY RTC_ALRMAR_WDSEL /*!< Alarm A WeekDay is selected */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_ALMB_WEEKDAY_SELECTION RTC Alarm B Date WeekDay + * @{ + */ +#define LL_RTC_ALMB_DATEWEEKDAYSEL_DATE 0x00000000U /*!< Alarm B Date is selected */ +#define LL_RTC_ALMB_DATEWEEKDAYSEL_WEEKDAY RTC_ALRMBR_WDSEL /*!< Alarm B WeekDay is selected */ +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ + +/** @defgroup RTC_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_RTC_ReadReg function + * @{ + */ +#define LL_RTC_SCR_ITSF RTC_SCR_CITSF +#define LL_RTC_SCR_TSOVF RTC_SCR_CTSOVF +#define LL_RTC_SCR_TSF RTC_SCR_CTSF +#define LL_RTC_SCR_WUTF RTC_SCR_CWUTF +#define LL_RTC_SCR_ALRBF RTC_SCR_CALRBF +#define LL_RTC_SCR_ALRAF RTC_SCR_CALRAF + +#define LL_RTC_ICSR_RECALPF RTC_ICSR_RECALPF +#define LL_RTC_ICSR_INITF RTC_ICSR_INITF +#define LL_RTC_ICSR_RSF RTC_ICSR_RSF +#define LL_RTC_ICSR_INITS RTC_ICSR_INITS +#define LL_RTC_ICSR_SHPF RTC_ICSR_SHPF +#define LL_RTC_ICSR_WUTWF RTC_ICSR_WUTWF +/** + * @} + */ + +/** @defgroup RTC_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_RTC_ReadReg and LL_RTC_WriteReg functions + * @{ + */ +#define LL_RTC_CR_TSIE RTC_CR_TSIE +#define LL_RTC_CR_WUTIE RTC_CR_WUTIE +#define LL_RTC_CR_ALRBIE RTC_CR_ALRBIE +#define LL_RTC_CR_ALRAIE RTC_CR_ALRAIE +/** + * @} + */ + +/** @defgroup RTC_LL_EC_WEEKDAY WEEK DAY + * @{ + */ +#define LL_RTC_WEEKDAY_MONDAY (uint8_t)0x01 /*!< Monday */ +#define LL_RTC_WEEKDAY_TUESDAY (uint8_t)0x02 /*!< Tuesday */ +#define LL_RTC_WEEKDAY_WEDNESDAY (uint8_t)0x03 /*!< Wednesday */ +#define LL_RTC_WEEKDAY_THURSDAY (uint8_t)0x04 /*!< Thrusday */ +#define LL_RTC_WEEKDAY_FRIDAY (uint8_t)0x05 /*!< Friday */ +#define LL_RTC_WEEKDAY_SATURDAY (uint8_t)0x06 /*!< Saturday */ +#define LL_RTC_WEEKDAY_SUNDAY (uint8_t)0x07 /*!< Sunday */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_MONTH MONTH + * @{ + */ +#define LL_RTC_MONTH_JANUARY (uint8_t)0x01 /*!< January */ +#define LL_RTC_MONTH_FEBRUARY (uint8_t)0x02 /*!< February */ +#define LL_RTC_MONTH_MARCH (uint8_t)0x03 /*!< March */ +#define LL_RTC_MONTH_APRIL (uint8_t)0x04 /*!< April */ +#define LL_RTC_MONTH_MAY (uint8_t)0x05 /*!< May */ +#define LL_RTC_MONTH_JUNE (uint8_t)0x06 /*!< June */ +#define LL_RTC_MONTH_JULY (uint8_t)0x07 /*!< July */ +#define LL_RTC_MONTH_AUGUST (uint8_t)0x08 /*!< August */ +#define LL_RTC_MONTH_SEPTEMBER (uint8_t)0x09 /*!< September */ +#define LL_RTC_MONTH_OCTOBER (uint8_t)0x10 /*!< October */ +#define LL_RTC_MONTH_NOVEMBER (uint8_t)0x11 /*!< November */ +#define LL_RTC_MONTH_DECEMBER (uint8_t)0x12 /*!< December */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_HOURFORMAT HOUR FORMAT + * @{ + */ +#define LL_RTC_HOURFORMAT_24HOUR 0x00000000U /*!< 24 hour/day format */ +#define LL_RTC_HOURFORMAT_AMPM RTC_CR_FMT /*!< AM/PM hour format */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_ALARMOUT ALARM OUTPUT + * @{ + */ +#define LL_RTC_ALARMOUT_DISABLE 0x00000000U /*!< Output disabled */ +#define LL_RTC_ALARMOUT_ALMA RTC_CR_OSEL_0 /*!< Alarm A output enabled */ +#define LL_RTC_ALARMOUT_ALMB RTC_CR_OSEL_1 /*!< Alarm B output enabled */ +#define LL_RTC_ALARMOUT_WAKEUP RTC_CR_OSEL /*!< Wakeup output enabled */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_ALARM_OUTPUTTYPE ALARM OUTPUT TYPE + * @{ + */ +#define LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN RTC_CR_TAMPALRM_TYPE /*!< RTC_ALARM is open-drain output */ +#define LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL 0x00000000U /*!< RTC_ALARM is push-pull output */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_OUTPUTPOLARITY_PIN OUTPUT POLARITY PIN + * @{ + */ +#define LL_RTC_OUTPUTPOLARITY_PIN_HIGH 0x00000000U /*!< Pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL)*/ +#define LL_RTC_OUTPUTPOLARITY_PIN_LOW RTC_CR_POL /*!< Pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL) */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_TIME_FORMAT TIME FORMAT + * @{ + */ +#define LL_RTC_TIME_FORMAT_AM_OR_24 0x00000000U /*!< AM or 24-hour format */ +#define LL_RTC_TIME_FORMAT_PM RTC_TR_PM /*!< PM */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_SHIFT_SECOND SHIFT SECOND + * @{ + */ +#define LL_RTC_SHIFT_SECOND_DELAY 0x00000000U /* Delay (seconds) = SUBFS / (PREDIV_S + 1) */ +#define LL_RTC_SHIFT_SECOND_ADVANCE RTC_SHIFTR_ADD1S /* Advance (seconds) = (1 - (SUBFS / (PREDIV_S + 1))) */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_ALMA_MASK ALARMA MASK + * @{ + */ +#define LL_RTC_ALMA_MASK_NONE 0x00000000U /*!< No masks applied on Alarm A*/ +#define LL_RTC_ALMA_MASK_DATEWEEKDAY RTC_ALRMAR_MSK4 /*!< Date/day do not care in Alarm A comparison */ +#define LL_RTC_ALMA_MASK_HOURS RTC_ALRMAR_MSK3 /*!< Hours do not care in Alarm A comparison */ +#define LL_RTC_ALMA_MASK_MINUTES RTC_ALRMAR_MSK2 /*!< Minutes do not care in Alarm A comparison */ +#define LL_RTC_ALMA_MASK_SECONDS RTC_ALRMAR_MSK1 /*!< Seconds do not care in Alarm A comparison */ +#define LL_RTC_ALMA_MASK_ALL (RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK1) /*!< Masks all */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_ALMA_TIME_FORMAT ALARMA TIME FORMAT + * @{ + */ +#define LL_RTC_ALMA_TIME_FORMAT_AM 0x00000000U /*!< AM or 24-hour format */ +#define LL_RTC_ALMA_TIME_FORMAT_PM RTC_ALRMAR_PM /*!< PM */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_ALMA_SUBSECONDBIN_AUTOCLR RTC Alarm Sub Seconds with binary mode auto clear Definitions + * @{ + */ +#define LL_RTC_ALMA_SUBSECONDBIN_AUTOCLR_NO 0UL /*!< The synchronous binary counter (SS[31:0] in RTC_SSR) is free-running. */ +#define LL_RTC_ALMA_SUBSECONDBIN_AUTOCLR_YES RTC_ALRMASSR_SSCLR /*!< The synchronous binary counter (SS[31:0] in RTC_SSR) is running from 0xFFFF FFFF to + RTC_ALRMABINR -> SS[31:0] value and is automatically reloaded with 0xFFFF FFFF + when reaching RTC_ALRMABINR -> SS[31:0]. */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_ALMB_MASK ALARMB MASK + * @{ + */ +#define LL_RTC_ALMB_MASK_NONE 0x00000000U /*!< No masks applied on Alarm B*/ +#define LL_RTC_ALMB_MASK_DATEWEEKDAY RTC_ALRMBR_MSK4 /*!< Date/day do not care in Alarm B comparison */ +#define LL_RTC_ALMB_MASK_HOURS RTC_ALRMBR_MSK3 /*!< Hours do not care in Alarm B comparison */ +#define LL_RTC_ALMB_MASK_MINUTES RTC_ALRMBR_MSK2 /*!< Minutes do not care in Alarm B comparison */ +#define LL_RTC_ALMB_MASK_SECONDS RTC_ALRMBR_MSK1 /*!< Seconds do not care in Alarm B comparison */ +#define LL_RTC_ALMB_MASK_ALL (RTC_ALRMBR_MSK4 | RTC_ALRMBR_MSK3 | RTC_ALRMBR_MSK2 | RTC_ALRMBR_MSK1) /*!< Masks all */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_ALMB_TIME_FORMAT ALARMB TIME FORMAT + * @{ + */ +#define LL_RTC_ALMB_TIME_FORMAT_AM 0x00000000U /*!< AM or 24-hour format */ +#define LL_RTC_ALMB_TIME_FORMAT_PM RTC_ALRMBR_PM /*!< PM */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_ALMB_SUBSECONDBIN_AUTOCLR Alarm Sub Seconds with binary mode auto clear Definitions + * @{ + */ +#define LL_RTC_ALMB_SUBSECONDBIN_AUTOCLR_NO 0UL /*!< The synchronous binary counter (SS[31:0] in RTC_SSR) is free-running. */ +#define LL_RTC_ALMB_SUBSECONDBIN_AUTOCLR_YES RTC_ALRMBSSR_SSCLR /*!< The synchronous binary counter (SS[31:0] in RTC_SSR) is running from 0xFFFF FFFF to + RTC_ALRMABINR -> SS[31:0] value and is automatically reloaded with 0xFFFF FFFF + when reaching RTC_ALRMABINR -> SS[31:0]. */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_ALMB_FLAG_AUTOCLR RTC Alarm Flag auto clear Definitions + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @{ + */ +#define LL_RTC_ALMB_FLAG_AUTOCLR_NO 0UL /*!< */ +#define LL_RTC_ALMB_FLAG_AUTOCLR_YES RTC_CR_ALRBMSK /*!< */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_TIMESTAMP_EDGE TIMESTAMP EDGE + * @{ + */ +#define LL_RTC_TIMESTAMP_EDGE_RISING 0x00000000U /*!< RTC_TS input rising edge generates a time-stamp event */ +#define LL_RTC_TIMESTAMP_EDGE_FALLING RTC_CR_TSEDGE /*!< RTC_TS input falling edge generates a time-stamp even */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_TS_TIME_FORMAT TIMESTAMP TIME FORMAT + * @{ + */ +#define LL_RTC_TS_TIME_FORMAT_AM 0x00000000U /*!< AM or 24-hour format */ +#define LL_RTC_TS_TIME_FORMAT_PM RTC_TSTR_PM /*!< PM */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_TAMPER TAMPER + * @{ + */ +#define LL_RTC_TAMPER_1 TAMP_CR1_TAMP1E /*!< Tamper 1 input detection */ +#define LL_RTC_TAMPER_2 TAMP_CR1_TAMP2E /*!< Tamper 2 input detection */ +#define LL_RTC_TAMPER_3 TAMP_CR1_TAMP3E /*!< Tamper 3 input detection */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_TAMPER_MASK TAMPER MASK + * @{ + */ +#define LL_RTC_TAMPER_MASK_TAMPER1 TAMP_CR2_TAMP1MSK /*!< Tamper 1 event generates a trigger event. TAMP1F is masked and internally cleared by hardware.The backup registers are not erased */ +#define LL_RTC_TAMPER_MASK_TAMPER2 TAMP_CR2_TAMP2MSK /*!< Tamper 2 event generates a trigger event. TAMP2F is masked and internally cleared by hardware. The backup registers are not erased. */ +#define LL_RTC_TAMPER_MASK_TAMPER3 TAMP_CR2_TAMP3MSK /*!< Tamper 3 event generates a trigger event. TAMP2F is masked and internally cleared by hardware. The backup registers are not erased. */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_TAMPER_NOERASE TAMPER NO ERASE + * @{ + */ +#define LL_RTC_TAMPER_NOERASE_TAMPER1 TAMP_CR2_TAMP1NOERASE /*!< Tamper 1 event does not erase the backup registers. */ +#define LL_RTC_TAMPER_NOERASE_TAMPER2 TAMP_CR2_TAMP2NOERASE /*!< Tamper 2 event does not erase the backup registers. */ +#define LL_RTC_TAMPER_NOERASE_TAMPER3 TAMP_CR2_TAMP3NOERASE /*!< Tamper 3 event does not erase the backup registers. */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_TAMPER_DURATION TAMPER DURATION + * @{ + */ +#define LL_RTC_TAMPER_DURATION_1RTCCLK 0x00000000U /*!< Tamper pins are pre-charged before sampling during 1 RTCCLK cycle */ +#define LL_RTC_TAMPER_DURATION_2RTCCLK TAMP_FLTCR_TAMPPRCH_0 /*!< Tamper pins are pre-charged before sampling during 2 RTCCLK cycles */ +#define LL_RTC_TAMPER_DURATION_4RTCCLK TAMP_FLTCR_TAMPPRCH_1 /*!< Tamper pins are pre-charged before sampling during 4 RTCCLK cycles */ +#define LL_RTC_TAMPER_DURATION_8RTCCLK TAMP_FLTCR_TAMPPRCH /*!< Tamper pins are pre-charged before sampling during 8 RTCCLK cycles */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_TAMPER_FILTER TAMPER FILTER + * @{ + */ +#define LL_RTC_TAMPER_FILTER_DISABLE 0x00000000U /*!< Tamper filter is disabled */ +#define LL_RTC_TAMPER_FILTER_2SAMPLE TAMP_FLTCR_TAMPFLT_0 /*!< Tamper is activated after 2 consecutive samples at the active level */ +#define LL_RTC_TAMPER_FILTER_4SAMPLE TAMP_FLTCR_TAMPFLT_1 /*!< Tamper is activated after 4 consecutive samples at the active level */ +#define LL_RTC_TAMPER_FILTER_8SAMPLE TAMP_FLTCR_TAMPFLT /*!< Tamper is activated after 8 consecutive samples at the active level. */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_TAMPER_SAMPLFREQDIV TAMPER SAMPLING FREQUENCY DIVIDER + * @{ + */ +#define LL_RTC_TAMPER_SAMPLFREQDIV_32768 0x00000000U /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 32768 */ +#define LL_RTC_TAMPER_SAMPLFREQDIV_16384 TAMP_FLTCR_TAMPFREQ_0 /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 16384 */ +#define LL_RTC_TAMPER_SAMPLFREQDIV_8192 TAMP_FLTCR_TAMPFREQ_1 /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 8192 */ +#define LL_RTC_TAMPER_SAMPLFREQDIV_4096 (TAMP_FLTCR_TAMPFREQ_1 | TAMP_FLTCR_TAMPFREQ_0) /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 4096 */ +#define LL_RTC_TAMPER_SAMPLFREQDIV_2048 TAMP_FLTCR_TAMPFREQ_2 /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 2048 */ +#define LL_RTC_TAMPER_SAMPLFREQDIV_1024 (TAMP_FLTCR_TAMPFREQ_2 | TAMP_FLTCR_TAMPFREQ_0) /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 1024 */ +#define LL_RTC_TAMPER_SAMPLFREQDIV_512 (TAMP_FLTCR_TAMPFREQ_2 | TAMP_FLTCR_TAMPFREQ_1) /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 512 */ +#define LL_RTC_TAMPER_SAMPLFREQDIV_256 TAMP_FLTCR_TAMPFREQ /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 256 */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_TAMPER_ACTIVELEVEL TAMPER ACTIVE LEVEL + * @{ + */ +#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP1 TAMP_CR2_TAMP1TRG /*!< Tamper 1 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event */ +#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP2 TAMP_CR2_TAMP2TRG /*!< Tamper 2 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event */ +#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP3 TAMP_CR2_TAMP3TRG /*!< Tamper 3 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event */ +/** + * @} + */ + + +/** @defgroup RTC_LL_EC_INTERNAL INTERNAL TAMPER + * @{ + */ +#define LL_RTC_TAMPER_ITAMP3 TAMP_CR1_ITAMP3E /*!< Internal tamper 3: LSE monitoring */ +#define LL_RTC_TAMPER_ITAMP5 TAMP_CR1_ITAMP5E /*!< Internal tamper 5: RTC calendar overflow */ +#define LL_RTC_TAMPER_ITAMP6 TAMP_CR1_ITAMP6E /*!< Internal tamper 6: JTAG access in RDP level 1 */ +#define LL_RTC_TAMPER_ITAMP8 TAMP_CR1_ITAMP8E /*!< Internal tamper 8: Monotonic counter overflow */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_BKP BACKUP + * @{ + */ +#define LL_RTC_BKP_NUMBER RTC_BACKUP_NB +#define LL_RTC_BKP_DR0 0U +#define LL_RTC_BKP_DR1 1U +#define LL_RTC_BKP_DR2 2U +#define LL_RTC_BKP_DR3 3U +#define LL_RTC_BKP_DR4 4U +#define LL_RTC_BKP_DR5 5U +#define LL_RTC_BKP_DR6 6U +#define LL_RTC_BKP_DR7 7U +#define LL_RTC_BKP_DR8 8U +#define LL_RTC_BKP_DR9 9U +#define LL_RTC_BKP_DR10 10U +#define LL_RTC_BKP_DR11 11U +#define LL_RTC_BKP_DR12 12U +#define LL_RTC_BKP_DR13 13U +#define LL_RTC_BKP_DR14 14U +#define LL_RTC_BKP_DR15 15U +#define LL_RTC_BKP_DR16 16U +#define LL_RTC_BKP_DR17 17U +#define LL_RTC_BKP_DR18 18U +#define LL_RTC_BKP_DR19 19U +/** + * @} + */ + +/** @defgroup RTC_LL_EC_WAKEUPCLOCK_DIV WAKEUP CLOCK DIV + * @{ + */ +#define LL_RTC_WAKEUPCLOCK_DIV_16 0x00000000U /*!< RTC/16 clock is selected */ +#define LL_RTC_WAKEUPCLOCK_DIV_8 RTC_CR_WUCKSEL_0 /*!< RTC/8 clock is selected */ +#define LL_RTC_WAKEUPCLOCK_DIV_4 RTC_CR_WUCKSEL_1 /*!< RTC/4 clock is selected */ +#define LL_RTC_WAKEUPCLOCK_DIV_2 (RTC_CR_WUCKSEL_1 | RTC_CR_WUCKSEL_0) /*!< RTC/2 clock is selected */ +#define LL_RTC_WAKEUPCLOCK_CKSPRE RTC_CR_WUCKSEL_2 /*!< ck_spre (usually 1 Hz) clock is selected */ +#define LL_RTC_WAKEUPCLOCK_CKSPRE_WUT (RTC_CR_WUCKSEL_2 | RTC_CR_WUCKSEL_1) /*!< ck_spre (usually 1 Hz) clock is selected and 2exp16 is added to the WUT counter value*/ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_CALIB_OUTPUT Calibration output + * @{ + */ +#define LL_RTC_CALIB_OUTPUT_NONE 0x00000000U /*!< Calibration output disabled */ +#define LL_RTC_CALIB_OUTPUT_1HZ (RTC_CR_COE | RTC_CR_COSEL) /*!< Calibration output is 1 Hz */ +#define LL_RTC_CALIB_OUTPUT_512HZ RTC_CR_COE /*!< Calibration output is 512 Hz */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_CALIB_INSERTPULSE Calibration pulse insertion + * @{ + */ +#define LL_RTC_CALIB_INSERTPULSE_NONE 0x00000000U /*!< No RTCCLK pulses are added */ +#define LL_RTC_CALIB_INSERTPULSE_SET RTC_CALR_CALP /*!< One RTCCLK pulse is effectively inserted every 2exp11 pulses (frequency increased by 488.5 ppm) */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_CALIB_PERIOD Calibration period + * @{ + */ +#define LL_RTC_CALIB_PERIOD_32SEC 0x00000000U /*!< Use a 32-second calibration cycle period */ +#define LL_RTC_CALIB_PERIOD_16SEC RTC_CALR_CALW16 /*!< Use a 16-second calibration cycle period */ +#define LL_RTC_CALIB_PERIOD_8SEC RTC_CALR_CALW8 /*!< Use a 8-second calibration cycle period */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_CALIB_LOWPOWER Calibration low power + * @{ + */ +#define LL_RTC_CALIB_LOWPOWER_NONE 0x00000000U /*!< High conso mode */ +#define LL_RTC_CALIB_LOWPOWER_SET RTC_CALR_LPCAL /*!< low power mode */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_BINARY_MODE Binary mode (Sub Second Register) + * @{ + */ +#define LL_RTC_BINARY_NONE 0x00000000U /*!< Free running BCD calendar mode (Binary mode disabled). */ +#define LL_RTC_BINARY_ONLY RTC_ICSR_BIN_0 /*!< Free running Binary mode (BCD mode disabled) */ +#define LL_RTC_BINARY_MIX RTC_ICSR_BIN_1 /*!< Free running BCD calendar and Binary mode enable */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_BINARY_MIX_BCDU Calendar second incrementation in Binary mix mode + * @{ + */ +#define LL_RTC_BINARY_MIX_BCDU_0 0x00000000u /*!< 1s calendar increment is generated each time SS[7:0] = 0 */ +#define LL_RTC_BINARY_MIX_BCDU_1 (0x1UL << RTC_ICSR_BCDU_Pos) /*!< 1s calendar increment is generated each time SS[8:0] = 0 */ +#define LL_RTC_BINARY_MIX_BCDU_2 (0x2UL << RTC_ICSR_BCDU_Pos) /*!< 1s calendar increment is generated each time SS[9:0] = 0 */ +#define LL_RTC_BINARY_MIX_BCDU_3 (0x3UL << RTC_ICSR_BCDU_Pos) /*!< 1s calendar increment is generated each time SS[10:0] = 0 */ +#define LL_RTC_BINARY_MIX_BCDU_4 (0x4UL << RTC_ICSR_BCDU_Pos) /*!< 1s calendar increment is generated each time SS[11:0] = 0 */ +#define LL_RTC_BINARY_MIX_BCDU_5 (0x5UL << RTC_ICSR_BCDU_Pos) /*!< 1s calendar increment is generated each time SS[12:0] = 0 */ +#define LL_RTC_BINARY_MIX_BCDU_6 (0x6UL << RTC_ICSR_BCDU_Pos) /*!< 1s calendar increment is generated each time SS[13:0] = 0 */ +#define LL_RTC_BINARY_MIX_BCDU_7 (0x7UL << RTC_ICSR_BCDU_Pos) /*!< 1s calendar increment is generated each time SS[14:0] = 0 */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup RTC_LL_Exported_Macros RTC Exported Macros + * @{ + */ + +/** @defgroup RTC_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in RTC register + * @param __INSTANCE__ RTC Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_RTC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in RTC register + * @param __INSTANCE__ RTC Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_RTC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** @defgroup RTC_LL_EM_Convert Convert helper Macros + * @{ + */ + +/** + * @brief Helper macro to convert a value from 2 digit decimal format to BCD format + * @param __VALUE__ Byte to be converted + * @retval Converted byte + */ +#define __LL_RTC_CONVERT_BIN2BCD(__VALUE__) ((uint8_t)((((__VALUE__) / 10U) << 4U) | ((__VALUE__) % 10U))) + +/** + * @brief Helper macro to convert a value from BCD format to 2 digit decimal format + * @param __VALUE__ BCD value to be converted + * @retval Converted byte + */ +#define __LL_RTC_CONVERT_BCD2BIN(__VALUE__) ((uint8_t)((((uint8_t)((__VALUE__) &\ + (uint8_t)0xF0U) >> (uint8_t)0x4U) * 10U) + ((__VALUE__) & (uint8_t)0x0FU))) + +/** + * @} + */ + +/** @defgroup RTC_LL_EM_Date Date helper Macros + * @{ + */ + +/** + * @brief Helper macro to retrieve weekday. + * @param __RTC_DATE__ Date returned by @ref LL_RTC_DATE_Get function. + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_WEEKDAY_MONDAY + * @arg @ref LL_RTC_WEEKDAY_TUESDAY + * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY + * @arg @ref LL_RTC_WEEKDAY_THURSDAY + * @arg @ref LL_RTC_WEEKDAY_FRIDAY + * @arg @ref LL_RTC_WEEKDAY_SATURDAY + * @arg @ref LL_RTC_WEEKDAY_SUNDAY + */ +#define __LL_RTC_GET_WEEKDAY(__RTC_DATE__) (((__RTC_DATE__) >> RTC_OFFSET_WEEKDAY) & 0x000000FFU) + +/** + * @brief Helper macro to retrieve Year in BCD format + * @param __RTC_DATE__ Value returned by @ref LL_RTC_DATE_Get + * @retval Year in BCD format (0x00 . . . 0x99) + */ +#define __LL_RTC_GET_YEAR(__RTC_DATE__) ((__RTC_DATE__) & 0x000000FFU) + +/** + * @brief Helper macro to retrieve Month in BCD format + * @param __RTC_DATE__ Value returned by @ref LL_RTC_DATE_Get + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_MONTH_JANUARY + * @arg @ref LL_RTC_MONTH_FEBRUARY + * @arg @ref LL_RTC_MONTH_MARCH + * @arg @ref LL_RTC_MONTH_APRIL + * @arg @ref LL_RTC_MONTH_MAY + * @arg @ref LL_RTC_MONTH_JUNE + * @arg @ref LL_RTC_MONTH_JULY + * @arg @ref LL_RTC_MONTH_AUGUST + * @arg @ref LL_RTC_MONTH_SEPTEMBER + * @arg @ref LL_RTC_MONTH_OCTOBER + * @arg @ref LL_RTC_MONTH_NOVEMBER + * @arg @ref LL_RTC_MONTH_DECEMBER + */ +#define __LL_RTC_GET_MONTH(__RTC_DATE__) (((__RTC_DATE__) >>RTC_OFFSET_MONTH) & 0x000000FFU) + +/** + * @brief Helper macro to retrieve Day in BCD format + * @param __RTC_DATE__ Value returned by @ref LL_RTC_DATE_Get + * @retval Day in BCD format (0x01 . . . 0x31) + */ +#define __LL_RTC_GET_DAY(__RTC_DATE__) (((__RTC_DATE__) >>RTC_OFFSET_DAY) & 0x000000FFU) + +/** + * @} + */ + +/** @defgroup RTC_LL_EM_Time Time helper Macros + * @{ + */ + +/** + * @brief Helper macro to retrieve hour in BCD format + * @param __RTC_TIME__ RTC time returned by @ref LL_RTC_TIME_Get function + * @retval Hours in BCD format (0x01. . .0x12 or between Min_Data=0x00 and Max_Data=0x23) + */ +#define __LL_RTC_GET_HOUR(__RTC_TIME__) (((__RTC_TIME__) >> RTC_OFFSET_HOUR) & 0x000000FFU) + +/** + * @brief Helper macro to retrieve minute in BCD format + * @param __RTC_TIME__ RTC time returned by @ref LL_RTC_TIME_Get function + * @retval Minutes in BCD format (0x00. . .0x59) + */ +#define __LL_RTC_GET_MINUTE(__RTC_TIME__) (((__RTC_TIME__) >> RTC_OFFSET_MINUTE) & 0x000000FFU) + +/** + * @brief Helper macro to retrieve second in BCD format + * @param __RTC_TIME__ RTC time returned by @ref LL_RTC_TIME_Get function + * @retval Seconds in format (0x00. . .0x59) + */ +#define __LL_RTC_GET_SECOND(__RTC_TIME__) ((__RTC_TIME__) & 0x000000FFU) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup RTC_LL_Exported_Functions RTC Exported Functions + * @{ + */ + +/** @defgroup RTC_LL_EF_Configuration Configuration + * @{ + */ + +/** + * @brief Set Hours format (24 hour/day or AM/PM hour format) + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function) + * @rmtoll RTC_CR FMT LL_RTC_SetHourFormat + * @param RTCx RTC Instance + * @param HourFormat This parameter can be one of the following values: + * @arg @ref LL_RTC_HOURFORMAT_24HOUR + * @arg @ref LL_RTC_HOURFORMAT_AMPM + * @retval None + */ +__STATIC_INLINE void LL_RTC_SetHourFormat(RTC_TypeDef *RTCx, uint32_t HourFormat) +{ + MODIFY_REG(RTCx->CR, RTC_CR_FMT, HourFormat); +} + +/** + * @brief Get Hours format (24 hour/day or AM/PM hour format) + * @rmtoll RTC_CR FMT LL_RTC_GetHourFormat + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_HOURFORMAT_24HOUR + * @arg @ref LL_RTC_HOURFORMAT_AMPM + */ +__STATIC_INLINE uint32_t LL_RTC_GetHourFormat(const RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_FMT)); +} + +/** + * @brief Select the flag to be routed to RTC_ALARM output + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR OSEL LL_RTC_SetAlarmOutEvent + * @param RTCx RTC Instance + * @param AlarmOutput This parameter can be one of the following values: + * @arg @ref LL_RTC_ALARMOUT_DISABLE + * @arg @ref LL_RTC_ALARMOUT_ALMA + * @arg @ref LL_RTC_ALARMOUT_ALMB + * @arg @ref LL_RTC_ALARMOUT_WAKEUP + * @retval None + */ +__STATIC_INLINE void LL_RTC_SetAlarmOutEvent(RTC_TypeDef *RTCx, uint32_t AlarmOutput) +{ + MODIFY_REG(RTCx->CR, RTC_CR_OSEL, AlarmOutput); +} + +/** + * @brief Get the flag to be routed to RTC_ALARM output + * @rmtoll RTC_CR OSEL LL_RTC_GetAlarmOutEvent + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_ALARMOUT_DISABLE + * @arg @ref LL_RTC_ALARMOUT_ALMA + * @arg @ref LL_RTC_ALARMOUT_ALMB + * @arg @ref LL_RTC_ALARMOUT_WAKEUP + */ +__STATIC_INLINE uint32_t LL_RTC_GetAlarmOutEvent(const RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_OSEL)); +} + +/** + * @brief Set RTC_ALARM output type (ALARM in push-pull or open-drain output) + * @rmtoll RTC_CR TAMPALRM_TYPE LL_RTC_SetAlarmOutputType + * @param RTCx RTC Instance + * @param Output This parameter can be one of the following values: + * @arg @ref LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN + * @arg @ref LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL + * @retval None + */ +__STATIC_INLINE void LL_RTC_SetAlarmOutputType(RTC_TypeDef *RTCx, uint32_t Output) +{ + MODIFY_REG(RTCx->CR, RTC_CR_TAMPALRM_TYPE, Output); +} + +/** + * @brief Get RTC_ALARM output type (ALARM in push-pull or open-drain output) + * @rmtoll RTC_CR TAMPALRM_TYPE LL_RTC_SetAlarmOutputType + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN + * @arg @ref LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL + */ +__STATIC_INLINE uint32_t LL_RTC_GetAlarmOutputType(const RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_TAMPALRM_TYPE)); +} + +/** + * @brief Enable initialization mode + * @note Initialization mode is used to program time and date register (RTC_TR and RTC_DR) + * and prescaler register (RTC_PRER), plus BIN and BCDU fields. + * Counters are stopped and start counting from the new value when INIT is reset. + * @rmtoll RTC_ICSR INIT LL_RTC_EnableInitMode + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableInitMode(RTC_TypeDef *RTCx) +{ + /* Set the Initialization mode */ + SET_BIT(RTCx->ICSR, RTC_ICSR_INIT); +} + +/** + * @brief Disable initialization mode (Free running mode) + * @rmtoll RTC_ICSR INIT LL_RTC_DisableInitMode + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableInitMode(RTC_TypeDef *RTCx) +{ + /* Exit Initialization mode */ + CLEAR_BIT(RTCx->ICSR, RTC_ICSR_INIT); +} + +/** + * @brief Set Binary mode (Sub Second Register) + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function). + * @rmtoll RTC_ICSR BIN LL_RTC_SetBinaryMode + * @param RTCx RTC Instance + * @param BinaryMode can be one of the following values: + * @arg @ref LL_RTC_BINARY_NONE + * @arg @ref LL_RTC_BINARY_ONLY + * @arg @ref LL_RTC_BINARY_MIX + * @retval None + */ +__STATIC_INLINE void LL_RTC_SetBinaryMode(RTC_TypeDef *RTCx, uint32_t BinaryMode) +{ + MODIFY_REG(RTCx->ICSR, RTC_ICSR_BIN, BinaryMode); +} + +/** + * @brief Get Binary mode (Sub Second Register) + * @rmtoll RTC_ICSR BIN LL_RTC_GetBinaryMode + * @param RTCx RTC Instance + * @retval This parameter can be one of the following values: + * @arg @ref LL_RTC_BINARY_NONE + * @arg @ref LL_RTC_BINARY_ONLY + * @arg @ref LL_RTC_BINARY_MIX + * @retval None + */ +__STATIC_INLINE uint32_t LL_RTC_GetBinaryMode(const RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->ICSR, RTC_ICSR_BIN)); +} + +/** + * @brief Set Binary Mix mode BCDU + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function). + * @rmtoll RTC_ICSR BCDU LL_RTC_SetBinMixBCDU + * @param RTCx RTC Instance + * @param BinMixBcdU can be one of the following values: + * @arg @ref LL_RTC_BINARY_MIX_BCDU_0 + * @arg @ref LL_RTC_BINARY_MIX_BCDU_1 + * @arg @ref LL_RTC_BINARY_MIX_BCDU_2 + * @arg @ref LL_RTC_BINARY_MIX_BCDU_3 + * @arg @ref LL_RTC_BINARY_MIX_BCDU_4 + * @arg @ref LL_RTC_BINARY_MIX_BCDU_5 + * @arg @ref LL_RTC_BINARY_MIX_BCDU_6 + * @arg @ref LL_RTC_BINARY_MIX_BCDU_7 + * @retval None + */ +__STATIC_INLINE void LL_RTC_SetBinMixBCDU(RTC_TypeDef *RTCx, uint32_t BinMixBcdU) +{ + MODIFY_REG(RTCx->ICSR, RTC_ICSR_BCDU, BinMixBcdU); +} + +/** + * @brief Get Binary Mix mode BCDU + * @rmtoll RTC_ICSR BCDU LL_RTC_GetBinMixBCDU + * @param RTCx RTC Instance + * @retval This parameter can be one of the following values: + * @arg @ref LL_RTC_BINARY_MIX_BCDU_0 + * @arg @ref LL_RTC_BINARY_MIX_BCDU_1 + * @arg @ref LL_RTC_BINARY_MIX_BCDU_2 + * @arg @ref LL_RTC_BINARY_MIX_BCDU_3 + * @arg @ref LL_RTC_BINARY_MIX_BCDU_4 + * @arg @ref LL_RTC_BINARY_MIX_BCDU_5 + * @arg @ref LL_RTC_BINARY_MIX_BCDU_6 + * @arg @ref LL_RTC_BINARY_MIX_BCDU_7 + * @retval None + */ +__STATIC_INLINE uint32_t LL_RTC_GetBinMixBCDU(const RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->ICSR, RTC_ICSR_BCDU)); +} + +/** + * @brief Set Output polarity (pin is low when ALRAF/ALRBF/WUTF is asserted) + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR POL LL_RTC_SetOutputPolarity + * @param RTCx RTC Instance + * @param Polarity This parameter can be one of the following values: + * @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_HIGH + * @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_LOW + * @retval None + */ +__STATIC_INLINE void LL_RTC_SetOutputPolarity(RTC_TypeDef *RTCx, uint32_t Polarity) +{ + MODIFY_REG(RTCx->CR, RTC_CR_POL, Polarity); +} + +/** + * @brief Get Output polarity + * @rmtoll RTC_CR POL LL_RTC_GetOutputPolarity + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_HIGH + * @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_LOW + */ +__STATIC_INLINE uint32_t LL_RTC_GetOutputPolarity(const RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_POL)); +} + +/** + * @brief Enable Bypass the shadow registers + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR BYPSHAD LL_RTC_EnableShadowRegBypass + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableShadowRegBypass(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CR, RTC_CR_BYPSHAD); +} + +/** + * @brief Disable Bypass the shadow registers + * @rmtoll RTC_CR BYPSHAD LL_RTC_DisableShadowRegBypass + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableShadowRegBypass(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CR, RTC_CR_BYPSHAD); +} + +/** + * @brief Check if Shadow registers bypass is enabled or not. + * @rmtoll RTC_CR BYPSHAD LL_RTC_IsShadowRegBypassEnabled + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsShadowRegBypassEnabled(const RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->CR, RTC_CR_BYPSHAD) == (RTC_CR_BYPSHAD)) ? 1U : 0U); +} + +/** + * @brief Enable RTC_REFIN reference clock detection (50 or 60 Hz) + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function) + * @rmtoll RTC_CR REFCKON LL_RTC_EnableRefClock + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableRefClock(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CR, RTC_CR_REFCKON); +} + +/** + * @brief Disable RTC_REFIN reference clock detection (50 or 60 Hz) + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function) + * @rmtoll RTC_CR REFCKON LL_RTC_DisableRefClock + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableRefClock(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CR, RTC_CR_REFCKON); +} + +/** + * @brief Set Asynchronous prescaler factor + * @rmtoll RTC_PRER PREDIV_A LL_RTC_SetAsynchPrescaler + * @param RTCx RTC Instance + * @param AsynchPrescaler Value between Min_Data = 0 and Max_Data = 0x7F + * @retval None + */ +__STATIC_INLINE void LL_RTC_SetAsynchPrescaler(RTC_TypeDef *RTCx, uint32_t AsynchPrescaler) +{ + MODIFY_REG(RTCx->PRER, RTC_PRER_PREDIV_A, AsynchPrescaler << RTC_PRER_PREDIV_A_Pos); +} + +/** + * @brief Set Synchronous prescaler factor + * @rmtoll RTC_PRER PREDIV_S LL_RTC_SetSynchPrescaler + * @param RTCx RTC Instance + * @param SynchPrescaler Value between Min_Data = 0 and Max_Data = 0x7FFF + * @retval None + */ +__STATIC_INLINE void LL_RTC_SetSynchPrescaler(RTC_TypeDef *RTCx, uint32_t SynchPrescaler) +{ + MODIFY_REG(RTCx->PRER, RTC_PRER_PREDIV_S, SynchPrescaler); +} + +/** + * @brief Get Asynchronous prescaler factor + * @rmtoll RTC_PRER PREDIV_A LL_RTC_GetAsynchPrescaler + * @param RTCx RTC Instance + * @retval Value between Min_Data = 0 and Max_Data = 0x7F + */ +__STATIC_INLINE uint32_t LL_RTC_GetAsynchPrescaler(const RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->PRER, RTC_PRER_PREDIV_A) >> RTC_PRER_PREDIV_A_Pos); +} + +/** + * @brief Get Synchronous prescaler factor + * @rmtoll RTC_PRER PREDIV_S LL_RTC_GetSynchPrescaler + * @param RTCx RTC Instance + * @retval Value between Min_Data = 0 and Max_Data = 0x7FFF + */ +__STATIC_INLINE uint32_t LL_RTC_GetSynchPrescaler(const RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->PRER, RTC_PRER_PREDIV_S)); +} + +/** + * @brief Enable the write protection for RTC registers. + * @rmtoll RTC_WPR KEY LL_RTC_EnableWriteProtection + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableWriteProtection(RTC_TypeDef *RTCx) +{ + WRITE_REG(RTCx->WPR, RTC_WRITE_PROTECTION_DISABLE); +} + +/** + * @brief Disable the write protection for RTC registers. + * @rmtoll RTC_WPR KEY LL_RTC_DisableWriteProtection + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableWriteProtection(RTC_TypeDef *RTCx) +{ + WRITE_REG(RTCx->WPR, RTC_WRITE_PROTECTION_ENABLE_1); + WRITE_REG(RTCx->WPR, RTC_WRITE_PROTECTION_ENABLE_2); +} + +/** + * @brief Enable tamper output. + * @note When the tamper output is enabled, all external and internal tamper flags + * are ORed and routed to the TAMPALRM output. + * @rmtoll RTC_CR TAMPOE LL_RTC_EnableTamperOutput + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableTamperOutput(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CR, RTC_CR_TAMPOE); +} + +/** + * @brief Disable tamper output. + * @rmtoll RTC_CR TAMPOE LL_RTC_DisableTamperOutput + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableTamperOutput(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CR, RTC_CR_TAMPOE); +} + +/** + * @brief Check if tamper output is enabled or not. + * @rmtoll RTC_CR TAMPOE LL_RTC_IsTamperOutputEnabled + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsTamperOutputEnabled(const RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->CR, RTC_CR_TAMPOE) == (RTC_CR_TAMPOE)) ? 1U : 0U); +} + +/** + * @brief Enable internal pull-up in output mode. + * @rmtoll RTC_CR TAMPALRM_PU LL_RTC_EnableAlarmPullUp + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableAlarmPullUp(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CR, RTC_CR_TAMPALRM_PU); +} + +/** + * @brief Disable internal pull-up in output mode. + * @rmtoll RTC_CR TAMPALRM_PU LL_RTC_EnableAlarmPullUp + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableAlarmPullUp(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CR, RTC_CR_TAMPALRM_PU); +} + +/** + * @brief Check if internal pull-up in output mode is enabled or not. + * @rmtoll RTC_CR TAMPALRM_PU LL_RTC_IsAlarmPullUpEnabled + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsAlarmPullUpEnabled(const RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->CR, RTC_CR_TAMPALRM_PU) == (RTC_CR_TAMPALRM_PU)) ? 1U : 0U); +} + +/** + * @brief Enable RTC_OUT2 output + * @note RTC_OUT2 mapping depends on both OSEL (@ref LL_RTC_SetAlarmOutEvent) + * and COE (@ref LL_RTC_CAL_SetOutputFreq) settings. + * @note RTC_OUT2 is not available ins VBAT mode. + * @rmtoll RTC_CR OUT2EN LL_RTC_EnableOutput2 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableOutput2(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CR, RTC_CR_OUT2EN); +} + +/** + * @brief Disable RTC_OUT2 output + * @rmtoll RTC_CR OUT2EN LL_RTC_DisableOutput2 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableOutput2(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CR, RTC_CR_OUT2EN); +} + +/** + * @brief Check if RTC_OUT2 output is enabled or not. + * @rmtoll RTC_CR OUT2EN LL_RTC_IsOutput2Enabled + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsOutput2Enabled(const RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->CR, RTC_CR_OUT2EN) == (RTC_CR_OUT2EN)) ? 1U : 0U); +} + +/** + * @} + */ + +/** @defgroup RTC_LL_EF_Time Time + * @{ + */ + +/** + * @brief Set time format (AM/24-hour or PM notation) + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function) + * @rmtoll RTC_TR PM LL_RTC_TIME_SetFormat + * @param RTCx RTC Instance + * @param TimeFormat This parameter can be one of the following values: + * @arg @ref LL_RTC_TIME_FORMAT_AM_OR_24 + * @arg @ref LL_RTC_TIME_FORMAT_PM + * @retval None + */ +__STATIC_INLINE void LL_RTC_TIME_SetFormat(RTC_TypeDef *RTCx, uint32_t TimeFormat) +{ + MODIFY_REG(RTCx->TR, RTC_TR_PM, TimeFormat); +} + +/** + * @brief Get time format (AM or PM notation) + * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * before reading this bit + * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar + * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)). + * @rmtoll RTC_TR PM LL_RTC_TIME_GetFormat + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_TIME_FORMAT_AM_OR_24 + * @arg @ref LL_RTC_TIME_FORMAT_PM + */ +__STATIC_INLINE uint32_t LL_RTC_TIME_GetFormat(const RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->TR, RTC_TR_PM)); +} + +/** + * @brief Set Hours in BCD format + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function) + * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert hour from binary to BCD format + * @rmtoll RTC_TR HT LL_RTC_TIME_SetHour\n + * RTC_TR HU LL_RTC_TIME_SetHour + * @param RTCx RTC Instance + * @param Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 + * @retval None + */ +__STATIC_INLINE void LL_RTC_TIME_SetHour(RTC_TypeDef *RTCx, uint32_t Hours) +{ + MODIFY_REG(RTCx->TR, (RTC_TR_HT | RTC_TR_HU), + (((Hours & 0xF0U) << (RTC_TR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_TR_HU_Pos))); +} + +/** + * @brief Get Hours in BCD format + * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * before reading this bit + * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar + * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)). + * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert hour from BCD to + * Binary format + * @rmtoll RTC_TR HT LL_RTC_TIME_GetHour\n + * RTC_TR HU LL_RTC_TIME_GetHour + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 + */ +__STATIC_INLINE uint32_t LL_RTC_TIME_GetHour(const RTC_TypeDef *RTCx) +{ + return (uint32_t)((READ_BIT(RTCx->TR, (RTC_TR_HT | RTC_TR_HU))) >> RTC_TR_HU_Pos); +} + +/** + * @brief Set Minutes in BCD format + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function) + * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Minutes from binary to BCD format + * @rmtoll RTC_TR MNT LL_RTC_TIME_SetMinute\n + * RTC_TR MNU LL_RTC_TIME_SetMinute + * @param RTCx RTC Instance + * @param Minutes Value between Min_Data=0x00 and Max_Data=0x59 + * @retval None + */ +__STATIC_INLINE void LL_RTC_TIME_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes) +{ + MODIFY_REG(RTCx->TR, (RTC_TR_MNT | RTC_TR_MNU), + (((Minutes & 0xF0U) << (RTC_TR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_TR_MNU_Pos))); +} + +/** + * @brief Get Minutes in BCD format + * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * before reading this bit + * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar + * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)). + * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert minute from BCD + * to Binary format + * @rmtoll RTC_TR MNT LL_RTC_TIME_GetMinute\n + * RTC_TR MNU LL_RTC_TIME_GetMinute + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x00 and Max_Data=0x59 + */ +__STATIC_INLINE uint32_t LL_RTC_TIME_GetMinute(const RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->TR, (RTC_TR_MNT | RTC_TR_MNU)) >> RTC_TR_MNU_Pos); +} + +/** + * @brief Set Seconds in BCD format + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function) + * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Seconds from binary to BCD format + * @rmtoll RTC_TR ST LL_RTC_TIME_SetSecond\n + * RTC_TR SU LL_RTC_TIME_SetSecond + * @param RTCx RTC Instance + * @param Seconds Value between Min_Data=0x00 and Max_Data=0x59 + * @retval None + */ +__STATIC_INLINE void LL_RTC_TIME_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds) +{ + MODIFY_REG(RTCx->TR, (RTC_TR_ST | RTC_TR_SU), + (((Seconds & 0xF0U) << (RTC_TR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_TR_SU_Pos))); +} + +/** + * @brief Get Seconds in BCD format + * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * before reading this bit + * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar + * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)). + * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD + * to Binary format + * @rmtoll RTC_TR ST LL_RTC_TIME_GetSecond\n + * RTC_TR SU LL_RTC_TIME_GetSecond + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x00 and Max_Data=0x59 + */ +__STATIC_INLINE uint32_t LL_RTC_TIME_GetSecond(const RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->TR, (RTC_TR_ST | RTC_TR_SU)) >> RTC_TR_SU_Pos); +} + +/** + * @brief Set time (hour, minute and second) in BCD format + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function) + * @note TimeFormat and Hours should follow the same format + * @rmtoll RTC_TR PM LL_RTC_TIME_Config\n + * RTC_TR HT LL_RTC_TIME_Config\n + * RTC_TR HU LL_RTC_TIME_Config\n + * RTC_TR MNT LL_RTC_TIME_Config\n + * RTC_TR MNU LL_RTC_TIME_Config\n + * RTC_TR ST LL_RTC_TIME_Config\n + * RTC_TR SU LL_RTC_TIME_Config + * @param RTCx RTC Instance + * @param Format12_24 This parameter can be one of the following values: + * @arg @ref LL_RTC_TIME_FORMAT_AM_OR_24 + * @arg @ref LL_RTC_TIME_FORMAT_PM + * @param Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 + * @param Minutes Value between Min_Data=0x00 and Max_Data=0x59 + * @param Seconds Value between Min_Data=0x00 and Max_Data=0x59 + * @retval None + */ +__STATIC_INLINE void LL_RTC_TIME_Config(RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, + uint32_t Seconds) +{ + uint32_t temp; + + temp = Format12_24 | \ + (((Hours & 0xF0U) << (RTC_TR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_TR_HU_Pos)) | \ + (((Minutes & 0xF0U) << (RTC_TR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_TR_MNU_Pos)) | \ + (((Seconds & 0xF0U) << (RTC_TR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_TR_SU_Pos)); + MODIFY_REG(RTCx->TR, (RTC_TR_PM | RTC_TR_HT | RTC_TR_HU | RTC_TR_MNT | RTC_TR_MNU | RTC_TR_ST | RTC_TR_SU), temp); +} + +/** + * @brief Get time (hour, minute and second) in BCD format + * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * before reading this bit + * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar + * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)). + * @note helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND + * are available to get independently each parameter. + * @rmtoll RTC_TR HT LL_RTC_TIME_Get\n + * RTC_TR HU LL_RTC_TIME_Get\n + * RTC_TR MNT LL_RTC_TIME_Get\n + * RTC_TR MNU LL_RTC_TIME_Get\n + * RTC_TR ST LL_RTC_TIME_Get\n + * RTC_TR SU LL_RTC_TIME_Get + * @param RTCx RTC Instance + * @retval Combination of hours, minutes and seconds (Format: 0x00HHMMSS). + */ +__STATIC_INLINE uint32_t LL_RTC_TIME_Get(const RTC_TypeDef *RTCx) +{ + uint32_t temp; + + temp = READ_BIT(RTCx->TR, (RTC_TR_HT | RTC_TR_HU | RTC_TR_MNT | RTC_TR_MNU | RTC_TR_ST | RTC_TR_SU)); + return (uint32_t)((((((temp & RTC_TR_HT) >> RTC_TR_HT_Pos) << 4U) | ((temp & RTC_TR_HU) >> RTC_TR_HU_Pos)) << RTC_OFFSET_HOUR) | \ + (((((temp & RTC_TR_MNT) >> RTC_TR_MNT_Pos) << 4U) | ((temp & RTC_TR_MNU) >> RTC_TR_MNU_Pos)) << RTC_OFFSET_MINUTE) | \ + ((((temp & RTC_TR_ST) >> RTC_TR_ST_Pos) << 4U) | ((temp & RTC_TR_SU) >> RTC_TR_SU_Pos))); +} + +/** + * @brief Memorize whether the daylight saving time change has been performed + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR BKP LL_RTC_TIME_EnableDayLightStore + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_TIME_EnableDayLightStore(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CR, RTC_CR_BKP); +} + +/** + * @brief Disable memorization whether the daylight saving time change has been performed. + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR BKP LL_RTC_TIME_DisableDayLightStore + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_TIME_DisableDayLightStore(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CR, RTC_CR_BKP); +} + +/** + * @brief Check if RTC Day Light Saving stored operation has been enabled or not + * @rmtoll RTC_CR BKP LL_RTC_TIME_IsDayLightStoreEnabled + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_TIME_IsDayLightStoreEnabled(const RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->CR, RTC_CR_BKP) == (RTC_CR_BKP)) ? 1U : 0U); +} + +/** + * @brief Subtract 1 hour (winter time change) + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR SUB1H LL_RTC_TIME_DecHour + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_TIME_DecHour(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CR, RTC_CR_SUB1H); +} + +/** + * @brief Add 1 hour (summer time change) + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR ADD1H LL_RTC_TIME_IncHour + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_TIME_IncHour(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CR, RTC_CR_ADD1H); +} + +/** + * @brief Get Sub second value in the synchronous prescaler counter. + * @note You can use both SubSeconds value and SecondFraction (PREDIV_S through + * LL_RTC_GetSynchPrescaler function) terms returned to convert Calendar + * SubSeconds value in second fraction ratio with time unit following + * generic formula: + * ==> Seconds fraction ratio * time_unit= [(SecondFraction-SubSeconds)/(SecondFraction+1)] * time_unit + * This conversion can be performed only if no shift operation is pending + * (ie. SHFP=0) when PREDIV_S >= SS. + * @rmtoll RTC_SSR SS LL_RTC_TIME_GetSubSecond + * @param RTCx RTC Instance + * @retval If binary mode is none, Value between Min_Data=0x0 and Max_Data=0x7FFF + * else Value between Min_Data=0x0 and Max_Data=0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_RTC_TIME_GetSubSecond(const RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->SSR, RTC_SSR_SS)); +} + +/** + * @brief Synchronize to a remote clock with a high degree of precision. + * @note This operation effectively subtracts from (delays) or advance the clock of a fraction of a second. + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @note When REFCKON is set, firmware must not write to Shift control register. + * @rmtoll RTC_SHIFTR ADD1S LL_RTC_TIME_Synchronize\n + * RTC_SHIFTR SUBFS LL_RTC_TIME_Synchronize + * @param RTCx RTC Instance + * @param ShiftSecond This parameter can be one of the following values: + * @arg @ref LL_RTC_SHIFT_SECOND_DELAY + * @arg @ref LL_RTC_SHIFT_SECOND_ADVANCE + * @param Fraction Number of Seconds Fractions (any value from 0 to 0x7FFF) + * @retval None + */ +__STATIC_INLINE void LL_RTC_TIME_Synchronize(RTC_TypeDef *RTCx, uint32_t ShiftSecond, uint32_t Fraction) +{ + WRITE_REG(RTCx->SHIFTR, ShiftSecond | Fraction); +} + +/** + * @} + */ + +/** @defgroup RTC_LL_EF_Date Date + * @{ + */ + +/** + * @brief Set Year in BCD format + * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Year from binary to BCD format + * @rmtoll RTC_DR YT LL_RTC_DATE_SetYear\n + * RTC_DR YU LL_RTC_DATE_SetYear + * @param RTCx RTC Instance + * @param Year Value between Min_Data=0x00 and Max_Data=0x99 + * @retval None + */ +__STATIC_INLINE void LL_RTC_DATE_SetYear(RTC_TypeDef *RTCx, uint32_t Year) +{ + MODIFY_REG(RTCx->DR, (RTC_DR_YT | RTC_DR_YU), + (((Year & 0xF0U) << (RTC_DR_YT_Pos - 4U)) | ((Year & 0x0FU) << RTC_DR_YU_Pos))); +} + +/** + * @brief Get Year in BCD format + * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * before reading this bit + * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Year from BCD to Binary format + * @rmtoll RTC_DR YT LL_RTC_DATE_GetYear\n + * RTC_DR YU LL_RTC_DATE_GetYear + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x00 and Max_Data=0x99 + */ +__STATIC_INLINE uint32_t LL_RTC_DATE_GetYear(const RTC_TypeDef *RTCx) +{ + return (uint32_t)((READ_BIT(RTCx->DR, (RTC_DR_YT | RTC_DR_YU))) >> RTC_DR_YU_Pos); +} + +/** + * @brief Set Week day + * @rmtoll RTC_DR WDU LL_RTC_DATE_SetWeekDay + * @param RTCx RTC Instance + * @param WeekDay This parameter can be one of the following values: + * @arg @ref LL_RTC_WEEKDAY_MONDAY + * @arg @ref LL_RTC_WEEKDAY_TUESDAY + * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY + * @arg @ref LL_RTC_WEEKDAY_THURSDAY + * @arg @ref LL_RTC_WEEKDAY_FRIDAY + * @arg @ref LL_RTC_WEEKDAY_SATURDAY + * @arg @ref LL_RTC_WEEKDAY_SUNDAY + * @retval None + */ +__STATIC_INLINE void LL_RTC_DATE_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay) +{ + MODIFY_REG(RTCx->DR, RTC_DR_WDU, WeekDay << RTC_DR_WDU_Pos); +} + +/** + * @brief Get Week day + * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * before reading this bit + * @rmtoll RTC_DR WDU LL_RTC_DATE_GetWeekDay + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_WEEKDAY_MONDAY + * @arg @ref LL_RTC_WEEKDAY_TUESDAY + * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY + * @arg @ref LL_RTC_WEEKDAY_THURSDAY + * @arg @ref LL_RTC_WEEKDAY_FRIDAY + * @arg @ref LL_RTC_WEEKDAY_SATURDAY + * @arg @ref LL_RTC_WEEKDAY_SUNDAY + */ +__STATIC_INLINE uint32_t LL_RTC_DATE_GetWeekDay(const RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->DR, RTC_DR_WDU) >> RTC_DR_WDU_Pos); +} + +/** + * @brief Set Month in BCD format + * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Month from binary to BCD format + * @rmtoll RTC_DR MT LL_RTC_DATE_SetMonth\n + * RTC_DR MU LL_RTC_DATE_SetMonth + * @param RTCx RTC Instance + * @param Month This parameter can be one of the following values: + * @arg @ref LL_RTC_MONTH_JANUARY + * @arg @ref LL_RTC_MONTH_FEBRUARY + * @arg @ref LL_RTC_MONTH_MARCH + * @arg @ref LL_RTC_MONTH_APRIL + * @arg @ref LL_RTC_MONTH_MAY + * @arg @ref LL_RTC_MONTH_JUNE + * @arg @ref LL_RTC_MONTH_JULY + * @arg @ref LL_RTC_MONTH_AUGUST + * @arg @ref LL_RTC_MONTH_SEPTEMBER + * @arg @ref LL_RTC_MONTH_OCTOBER + * @arg @ref LL_RTC_MONTH_NOVEMBER + * @arg @ref LL_RTC_MONTH_DECEMBER + * @retval None + */ +__STATIC_INLINE void LL_RTC_DATE_SetMonth(RTC_TypeDef *RTCx, uint32_t Month) +{ + MODIFY_REG(RTCx->DR, (RTC_DR_MT | RTC_DR_MU), + (((Month & 0xF0U) << (RTC_DR_MT_Pos - 4U)) | ((Month & 0x0FU) << RTC_DR_MU_Pos))); +} + +/** + * @brief Get Month in BCD format + * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * before reading this bit + * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Month from BCD to Binary format + * @rmtoll RTC_DR MT LL_RTC_DATE_GetMonth\n + * RTC_DR MU LL_RTC_DATE_GetMonth + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_MONTH_JANUARY + * @arg @ref LL_RTC_MONTH_FEBRUARY + * @arg @ref LL_RTC_MONTH_MARCH + * @arg @ref LL_RTC_MONTH_APRIL + * @arg @ref LL_RTC_MONTH_MAY + * @arg @ref LL_RTC_MONTH_JUNE + * @arg @ref LL_RTC_MONTH_JULY + * @arg @ref LL_RTC_MONTH_AUGUST + * @arg @ref LL_RTC_MONTH_SEPTEMBER + * @arg @ref LL_RTC_MONTH_OCTOBER + * @arg @ref LL_RTC_MONTH_NOVEMBER + * @arg @ref LL_RTC_MONTH_DECEMBER + */ +__STATIC_INLINE uint32_t LL_RTC_DATE_GetMonth(const RTC_TypeDef *RTCx) +{ + return (uint32_t)((READ_BIT(RTCx->DR, (RTC_DR_MT | RTC_DR_MU))) >> RTC_DR_MU_Pos); +} + +/** + * @brief Set Day in BCD format + * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Day from binary to BCD format + * @rmtoll RTC_DR DT LL_RTC_DATE_SetDay\n + * RTC_DR DU LL_RTC_DATE_SetDay + * @param RTCx RTC Instance + * @param Day Value between Min_Data=0x01 and Max_Data=0x31 + * @retval None + */ +__STATIC_INLINE void LL_RTC_DATE_SetDay(RTC_TypeDef *RTCx, uint32_t Day) +{ + MODIFY_REG(RTCx->DR, (RTC_DR_DT | RTC_DR_DU), + (((Day & 0xF0U) << (RTC_DR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_DR_DU_Pos))); +} + +/** + * @brief Get Day in BCD format + * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * before reading this bit + * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format + * @rmtoll RTC_DR DT LL_RTC_DATE_GetDay\n + * RTC_DR DU LL_RTC_DATE_GetDay + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x01 and Max_Data=0x31 + */ +__STATIC_INLINE uint32_t LL_RTC_DATE_GetDay(const RTC_TypeDef *RTCx) +{ + return (uint32_t)((READ_BIT(RTCx->DR, (RTC_DR_DT | RTC_DR_DU))) >> RTC_DR_DU_Pos); +} + +/** + * @brief Set date (WeekDay, Day, Month and Year) in BCD format + * @rmtoll RTC_DR WDU LL_RTC_DATE_Config\n + * RTC_DR MT LL_RTC_DATE_Config\n + * RTC_DR MU LL_RTC_DATE_Config\n + * RTC_DR DT LL_RTC_DATE_Config\n + * RTC_DR DU LL_RTC_DATE_Config\n + * RTC_DR YT LL_RTC_DATE_Config\n + * RTC_DR YU LL_RTC_DATE_Config + * @param RTCx RTC Instance + * @param WeekDay This parameter can be one of the following values: + * @arg @ref LL_RTC_WEEKDAY_MONDAY + * @arg @ref LL_RTC_WEEKDAY_TUESDAY + * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY + * @arg @ref LL_RTC_WEEKDAY_THURSDAY + * @arg @ref LL_RTC_WEEKDAY_FRIDAY + * @arg @ref LL_RTC_WEEKDAY_SATURDAY + * @arg @ref LL_RTC_WEEKDAY_SUNDAY + * @param Day Value between Min_Data=0x01 and Max_Data=0x31 + * @param Month This parameter can be one of the following values: + * @arg @ref LL_RTC_MONTH_JANUARY + * @arg @ref LL_RTC_MONTH_FEBRUARY + * @arg @ref LL_RTC_MONTH_MARCH + * @arg @ref LL_RTC_MONTH_APRIL + * @arg @ref LL_RTC_MONTH_MAY + * @arg @ref LL_RTC_MONTH_JUNE + * @arg @ref LL_RTC_MONTH_JULY + * @arg @ref LL_RTC_MONTH_AUGUST + * @arg @ref LL_RTC_MONTH_SEPTEMBER + * @arg @ref LL_RTC_MONTH_OCTOBER + * @arg @ref LL_RTC_MONTH_NOVEMBER + * @arg @ref LL_RTC_MONTH_DECEMBER + * @param Year Value between Min_Data=0x00 and Max_Data=0x99 + * @retval None + */ +__STATIC_INLINE void LL_RTC_DATE_Config(RTC_TypeDef *RTCx, uint32_t WeekDay, uint32_t Day, uint32_t Month, + uint32_t Year) +{ + uint32_t temp; + + temp = (WeekDay << RTC_DR_WDU_Pos) | \ + (((Year & 0xF0U) << (RTC_DR_YT_Pos - 4U)) | ((Year & 0x0FU) << RTC_DR_YU_Pos)) | \ + (((Month & 0xF0U) << (RTC_DR_MT_Pos - 4U)) | ((Month & 0x0FU) << RTC_DR_MU_Pos)) | \ + (((Day & 0xF0U) << (RTC_DR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_DR_DU_Pos)); + + MODIFY_REG(RTCx->DR, (RTC_DR_WDU | RTC_DR_MT | RTC_DR_MU | RTC_DR_DT | RTC_DR_DU | RTC_DR_YT | RTC_DR_YU), temp); +} + +/** + * @brief Get date (WeekDay, Day, Month and Year) in BCD format + * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * before reading this bit + * @note helper macros __LL_RTC_GET_WEEKDAY, __LL_RTC_GET_YEAR, __LL_RTC_GET_MONTH, + * and __LL_RTC_GET_DAY are available to get independently each parameter. + * @rmtoll RTC_DR WDU LL_RTC_DATE_Get\n + * RTC_DR MT LL_RTC_DATE_Get\n + * RTC_DR MU LL_RTC_DATE_Get\n + * RTC_DR DT LL_RTC_DATE_Get\n + * RTC_DR DU LL_RTC_DATE_Get\n + * RTC_DR YT LL_RTC_DATE_Get\n + * RTC_DR YU LL_RTC_DATE_Get + * @param RTCx RTC Instance + * @retval Combination of WeekDay, Day, Month and Year (Format: 0xWWDDMMYY). + */ +__STATIC_INLINE uint32_t LL_RTC_DATE_Get(const RTC_TypeDef *RTCx) +{ + uint32_t temp; + + temp = READ_BIT(RTCx->DR, (RTC_DR_WDU | RTC_DR_MT | RTC_DR_MU | RTC_DR_DT | RTC_DR_DU | RTC_DR_YT | RTC_DR_YU)); + return (uint32_t)((((temp & RTC_DR_WDU) >> RTC_DR_WDU_Pos) << RTC_OFFSET_WEEKDAY) | \ + (((((temp & RTC_DR_DT) >> RTC_DR_DT_Pos) << 4U) | ((temp & RTC_DR_DU) >> RTC_DR_DU_Pos)) << RTC_OFFSET_DAY) | \ + (((((temp & RTC_DR_MT) >> RTC_DR_MT_Pos) << 4U) | ((temp & RTC_DR_MU) >> RTC_DR_MU_Pos)) << RTC_OFFSET_MONTH) | \ + ((((temp & RTC_DR_YT) >> RTC_DR_YT_Pos) << 4U) | ((temp & RTC_DR_YU) >> RTC_DR_YU_Pos))); +} + +/** + * @} + */ + +/** @defgroup RTC_LL_EF_ALARMA ALARMA + * @{ + */ + +/** + * @brief Enable Alarm A + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR ALRAE LL_RTC_ALMA_Enable + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMA_Enable(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CR, RTC_CR_ALRAE); +} + +/** + * @brief Disable Alarm A + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR ALRAE LL_RTC_ALMA_Disable + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMA_Disable(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CR, RTC_CR_ALRAE); +} + +/** + * @brief Specify the Alarm A masks. + * @rmtoll RTC_ALRMAR MSK4 LL_RTC_ALMA_SetMask\n + * RTC_ALRMAR MSK3 LL_RTC_ALMA_SetMask\n + * RTC_ALRMAR MSK2 LL_RTC_ALMA_SetMask\n + * RTC_ALRMAR MSK1 LL_RTC_ALMA_SetMask + * @param RTCx RTC Instance + * @param Mask This parameter can be a combination of the following values: + * @arg @ref LL_RTC_ALMA_MASK_NONE + * @arg @ref LL_RTC_ALMA_MASK_DATEWEEKDAY + * @arg @ref LL_RTC_ALMA_MASK_HOURS + * @arg @ref LL_RTC_ALMA_MASK_MINUTES + * @arg @ref LL_RTC_ALMA_MASK_SECONDS + * @arg @ref LL_RTC_ALMA_MASK_ALL + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMA_SetMask(RTC_TypeDef *RTCx, uint32_t Mask) +{ + MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK1, Mask); +} + +/** + * @brief Get the Alarm A masks. + * @rmtoll RTC_ALRMAR MSK4 LL_RTC_ALMA_GetMask\n + * RTC_ALRMAR MSK3 LL_RTC_ALMA_GetMask\n + * RTC_ALRMAR MSK2 LL_RTC_ALMA_GetMask\n + * RTC_ALRMAR MSK1 LL_RTC_ALMA_GetMask + * @param RTCx RTC Instance + * @retval Returned value can be can be a combination of the following values: + * @arg @ref LL_RTC_ALMA_MASK_NONE + * @arg @ref LL_RTC_ALMA_MASK_DATEWEEKDAY + * @arg @ref LL_RTC_ALMA_MASK_HOURS + * @arg @ref LL_RTC_ALMA_MASK_MINUTES + * @arg @ref LL_RTC_ALMA_MASK_SECONDS + * @arg @ref LL_RTC_ALMA_MASK_ALL + */ +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetMask(const RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->ALRMAR, RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK1)); +} + +/** + * @brief Enable AlarmA Week day selection (DU[3:0] represents the week day. DT[1:0] is do not care) + * @rmtoll RTC_ALRMAR WDSEL LL_RTC_ALMA_EnableWeekday + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMA_EnableWeekday(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->ALRMAR, RTC_ALRMAR_WDSEL); +} + +/** + * @brief Disable AlarmA Week day selection (DU[3:0] represents the date ) + * @rmtoll RTC_ALRMAR WDSEL LL_RTC_ALMA_DisableWeekday + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMA_DisableWeekday(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->ALRMAR, RTC_ALRMAR_WDSEL); +} + +/** + * @brief Set ALARM A Day in BCD format + * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Day from binary to BCD format + * @rmtoll RTC_ALRMAR DT LL_RTC_ALMA_SetDay\n + * RTC_ALRMAR DU LL_RTC_ALMA_SetDay + * @param RTCx RTC Instance + * @param Day Value between Min_Data=0x01 and Max_Data=0x31 + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMA_SetDay(RTC_TypeDef *RTCx, uint32_t Day) +{ + MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_DT | RTC_ALRMAR_DU), + (((Day & 0xF0U) << (RTC_ALRMAR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_ALRMAR_DU_Pos))); +} + +/** + * @brief Get ALARM A Day in BCD format + * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format + * @rmtoll RTC_ALRMAR DT LL_RTC_ALMA_GetDay\n + * RTC_ALRMAR DU LL_RTC_ALMA_GetDay + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x01 and Max_Data=0x31 + */ +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetDay(const RTC_TypeDef *RTCx) +{ + return (uint32_t)((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_DT | RTC_ALRMAR_DU))) >> RTC_ALRMAR_DU_Pos); +} + +/** + * @brief Set ALARM A Weekday + * @rmtoll RTC_ALRMAR DU LL_RTC_ALMA_SetWeekDay + * @param RTCx RTC Instance + * @param WeekDay This parameter can be one of the following values: + * @arg @ref LL_RTC_WEEKDAY_MONDAY + * @arg @ref LL_RTC_WEEKDAY_TUESDAY + * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY + * @arg @ref LL_RTC_WEEKDAY_THURSDAY + * @arg @ref LL_RTC_WEEKDAY_FRIDAY + * @arg @ref LL_RTC_WEEKDAY_SATURDAY + * @arg @ref LL_RTC_WEEKDAY_SUNDAY + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMA_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay) +{ + MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_DU, WeekDay << RTC_ALRMAR_DU_Pos); +} + +/** + * @brief Get ALARM A Weekday + * @rmtoll RTC_ALRMAR DU LL_RTC_ALMA_GetWeekDay + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_WEEKDAY_MONDAY + * @arg @ref LL_RTC_WEEKDAY_TUESDAY + * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY + * @arg @ref LL_RTC_WEEKDAY_THURSDAY + * @arg @ref LL_RTC_WEEKDAY_FRIDAY + * @arg @ref LL_RTC_WEEKDAY_SATURDAY + * @arg @ref LL_RTC_WEEKDAY_SUNDAY + */ +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetWeekDay(const RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->ALRMAR, RTC_ALRMAR_DU) >> RTC_ALRMAR_DU_Pos); +} + +/** + * @brief Set Alarm A time format (AM/24-hour or PM notation) + * @rmtoll RTC_ALRMAR PM LL_RTC_ALMA_SetTimeFormat + * @param RTCx RTC Instance + * @param TimeFormat This parameter can be one of the following values: + * @arg @ref LL_RTC_ALMA_TIME_FORMAT_AM + * @arg @ref LL_RTC_ALMA_TIME_FORMAT_PM + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMA_SetTimeFormat(RTC_TypeDef *RTCx, uint32_t TimeFormat) +{ + MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_PM, TimeFormat); +} + +/** + * @brief Get Alarm A time format (AM or PM notation) + * @rmtoll RTC_ALRMAR PM LL_RTC_ALMA_GetTimeFormat + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_ALMA_TIME_FORMAT_AM + * @arg @ref LL_RTC_ALMA_TIME_FORMAT_PM + */ +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetTimeFormat(const RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->ALRMAR, RTC_ALRMAR_PM)); +} + +/** + * @brief Set ALARM A Hours in BCD format + * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Hours from binary to BCD format + * @rmtoll RTC_ALRMAR HT LL_RTC_ALMA_SetHour\n + * RTC_ALRMAR HU LL_RTC_ALMA_SetHour + * @param RTCx RTC Instance + * @param Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMA_SetHour(RTC_TypeDef *RTCx, uint32_t Hours) +{ + MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_HT | RTC_ALRMAR_HU), + (((Hours & 0xF0U) << (RTC_ALRMAR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMAR_HU_Pos))); +} + +/** + * @brief Get ALARM A Hours in BCD format + * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Hours from BCD to Binary format + * @rmtoll RTC_ALRMAR HT LL_RTC_ALMA_GetHour\n + * RTC_ALRMAR HU LL_RTC_ALMA_GetHour + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 + */ +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetHour(const RTC_TypeDef *RTCx) +{ + return (uint32_t)((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_HT | RTC_ALRMAR_HU))) >> RTC_ALRMAR_HU_Pos); +} + +/** + * @brief Set ALARM A Minutes in BCD format + * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Minutes from binary to BCD format + * @rmtoll RTC_ALRMAR MNT LL_RTC_ALMA_SetMinute\n + * RTC_ALRMAR MNU LL_RTC_ALMA_SetMinute + * @param RTCx RTC Instance + * @param Minutes Value between Min_Data=0x00 and Max_Data=0x59 + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMA_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes) +{ + MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU), + (((Minutes & 0xF0U) << (RTC_ALRMAR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMAR_MNU_Pos))); +} + +/** + * @brief Get ALARM A Minutes in BCD format + * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Minutes from BCD to Binary format + * @rmtoll RTC_ALRMAR MNT LL_RTC_ALMA_GetMinute\n + * RTC_ALRMAR MNU LL_RTC_ALMA_GetMinute + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x00 and Max_Data=0x59 + */ +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetMinute(const RTC_TypeDef *RTCx) +{ + return (uint32_t)((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU))) >> RTC_ALRMAR_MNU_Pos); +} + +/** + * @brief Set ALARM A Seconds in BCD format + * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Seconds from binary to BCD format + * @rmtoll RTC_ALRMAR ST LL_RTC_ALMA_SetSecond\n + * RTC_ALRMAR SU LL_RTC_ALMA_SetSecond + * @param RTCx RTC Instance + * @param Seconds Value between Min_Data=0x00 and Max_Data=0x59 + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMA_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds) +{ + MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_ST | RTC_ALRMAR_SU), + (((Seconds & 0xF0U) << (RTC_ALRMAR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMAR_SU_Pos))); +} + +/** + * @brief Get ALARM A Seconds in BCD format + * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD to Binary format + * @rmtoll RTC_ALRMAR ST LL_RTC_ALMA_GetSecond\n + * RTC_ALRMAR SU LL_RTC_ALMA_GetSecond + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x00 and Max_Data=0x59 + */ +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSecond(const RTC_TypeDef *RTCx) +{ + return (uint32_t)((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_ST | RTC_ALRMAR_SU))) >> RTC_ALRMAR_SU_Pos); +} + +/** + * @brief Set Alarm A Time (hour, minute and second) in BCD format + * @rmtoll RTC_ALRMAR PM LL_RTC_ALMA_ConfigTime\n + * RTC_ALRMAR HT LL_RTC_ALMA_ConfigTime\n + * RTC_ALRMAR HU LL_RTC_ALMA_ConfigTime\n + * RTC_ALRMAR MNT LL_RTC_ALMA_ConfigTime\n + * RTC_ALRMAR MNU LL_RTC_ALMA_ConfigTime\n + * RTC_ALRMAR ST LL_RTC_ALMA_ConfigTime\n + * RTC_ALRMAR SU LL_RTC_ALMA_ConfigTime + * @param RTCx RTC Instance + * @param Format12_24 This parameter can be one of the following values: + * @arg @ref LL_RTC_ALMA_TIME_FORMAT_AM + * @arg @ref LL_RTC_ALMA_TIME_FORMAT_PM + * @param Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 + * @param Minutes Value between Min_Data=0x00 and Max_Data=0x59 + * @param Seconds Value between Min_Data=0x00 and Max_Data=0x59 + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMA_ConfigTime(RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, + uint32_t Seconds) +{ + uint32_t temp; + + temp = Format12_24 | (((Hours & 0xF0U) << (RTC_ALRMAR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMAR_HU_Pos)) | \ + (((Minutes & 0xF0U) << (RTC_ALRMAR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMAR_MNU_Pos)) | \ + (((Seconds & 0xF0U) << (RTC_ALRMAR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMAR_SU_Pos)); + + MODIFY_REG(RTCx->ALRMAR, + RTC_ALRMAR_PM | RTC_ALRMAR_HT | RTC_ALRMAR_HU | RTC_ALRMAR_MNT | RTC_ALRMAR_MNU | RTC_ALRMAR_ST | RTC_ALRMAR_SU, + temp); +} + +/** + * @brief Get Alarm B Time (hour, minute and second) in BCD format + * @note helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND + * are available to get independently each parameter. + * @rmtoll RTC_ALRMAR HT LL_RTC_ALMA_GetTime\n + * RTC_ALRMAR HU LL_RTC_ALMA_GetTime\n + * RTC_ALRMAR MNT LL_RTC_ALMA_GetTime\n + * RTC_ALRMAR MNU LL_RTC_ALMA_GetTime\n + * RTC_ALRMAR ST LL_RTC_ALMA_GetTime\n + * RTC_ALRMAR SU LL_RTC_ALMA_GetTime + * @param RTCx RTC Instance + * @retval Combination of hours, minutes and seconds. + */ +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetTime(RTC_TypeDef *RTCx) +{ + return (uint32_t)((LL_RTC_ALMA_GetHour(RTCx) << RTC_OFFSET_HOUR) | (LL_RTC_ALMA_GetMinute(RTCx) << RTC_OFFSET_MINUTE) | LL_RTC_ALMA_GetSecond(RTCx)); +} + +/** + * @brief Set Alarm A Mask the most-significant bits starting at this bit + * @note This register can be written only when ALRAE is reset in RTC_CR register, + * or in initialization mode. + * @rmtoll RTC_ALRMASSR MASKSS LL_RTC_ALMA_SetSubSecondMask + * @param RTCx RTC Instance + * @param Mask If binary mode is none, Value between Min_Data=0x0 and Max_Data=0xF + * else Value between Min_Data=0x0 and Max_Data=0x3F + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMA_SetSubSecondMask(RTC_TypeDef *RTCx, uint32_t Mask) +{ + MODIFY_REG(RTCx->ALRMASSR, RTC_ALRMASSR_MASKSS, Mask << RTC_ALRMASSR_MASKSS_Pos); +} + +/** + * @brief Get Alarm A Mask the most-significant bits starting at this bit + * @rmtoll RTC_ALRMASSR MASKSS LL_RTC_ALMA_GetSubSecondMask + * @param RTCx RTC Instance + * @retval If binary mode is none, Value between Min_Data=0x0 and Max_Data=0xF + * else Value between Min_Data=0x0 and Max_Data=0x3F + */ +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSubSecondMask(const RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->ALRMASSR, RTC_ALRMASSR_MASKSS) >> RTC_ALRMASSR_MASKSS_Pos); +} + +/** + * @brief Set Alarm A Binary mode auto clear + * @note This register can be written only when ALRAE is reset in RTC_CR register, + * or in initialization mode. + * @rmtoll RTC_ALRABINR SSCLR LL_RTC_ALMA_SetBinAutoClr + * @param RTCx RTC Instance + * @param BinaryAutoClr This parameter can be one of the following values: + * @arg @ref LL_RTC_ALMA_SUBSECONDBIN_AUTOCLR_NO + * @arg @ref LL_RTC_ALMA_SUBSECONDBIN_AUTOCLR_YES + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMA_SetBinAutoClr(RTC_TypeDef *RTCx, uint32_t BinaryAutoClr) +{ + MODIFY_REG(RTCx->ALRMASSR, RTC_ALRMASSR_SSCLR, BinaryAutoClr); +} + +/** + * @brief Get Alarm A Binary mode auto clear + * @rmtoll RTC_ALRABINR SSCLR LL_RTC_ALMA_GetBinAutoClr + * @param RTCx RTC Instance + * @retval It can be one of the following values: + * @arg @ref LL_RTC_ALMA_SUBSECONDBIN_AUTOCLR_NO + * @arg @ref LL_RTC_ALMA_SUBSECONDBIN_AUTOCLR_YES + */ +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetBinAutoClr(const RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->ALRMASSR, RTC_ALRMASSR_SSCLR)); +} + +/** + * @brief Set Alarm A Sub seconds value + * @rmtoll RTC_ALRMABINR SS LL_RTC_ALMA_SetSubSecond + * @param RTCx RTC Instance + * @param Subsecond If binary mode is none, Value between Min_Data=0x0 and Max_Data=0x7FFF + * else Value between Min_Data=0x0 and Max_Data=0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMA_SetSubSecond(RTC_TypeDef *RTCx, uint32_t Subsecond) +{ + MODIFY_REG(RTCx->ALRABINR, RTC_ALRABINR_SS, Subsecond); +} + +/** + * @brief Get Alarm A Sub seconds value + * @rmtoll RTC_ALRMABINR SS LL_RTC_ALMA_GetSubSecond + * @param RTCx RTC Instance + * @retval If binary mode is none, Value between Min_Data=0x0 and Max_Data=0x7FFF + * else Value between Min_Data=0x0 and Max_Data=0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSubSecond(const RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->ALRABINR, RTC_ALRABINR_SS)); +} + +/** + * @} + */ + +/** @defgroup RTC_LL_EF_ALARMB ALARMB + * @{ + */ + +/** + * @brief Enable Alarm B + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR ALRBE LL_RTC_ALMB_Enable + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMB_Enable(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CR, RTC_CR_ALRBE); +} + +/** + * @brief Disable Alarm B + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR ALRBE LL_RTC_ALMB_Disable + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMB_Disable(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CR, RTC_CR_ALRBE); +} + +/** + * @brief Specify the Alarm B masks. + * @rmtoll RTC_ALRMBR MSK4 LL_RTC_ALMB_SetMask\n + * RTC_ALRMBR MSK3 LL_RTC_ALMB_SetMask\n + * RTC_ALRMBR MSK2 LL_RTC_ALMB_SetMask\n + * RTC_ALRMBR MSK1 LL_RTC_ALMB_SetMask + * @param RTCx RTC Instance + * @param Mask This parameter can be a combination of the following values: + * @arg @ref LL_RTC_ALMB_MASK_NONE + * @arg @ref LL_RTC_ALMB_MASK_DATEWEEKDAY + * @arg @ref LL_RTC_ALMB_MASK_HOURS + * @arg @ref LL_RTC_ALMB_MASK_MINUTES + * @arg @ref LL_RTC_ALMB_MASK_SECONDS + * @arg @ref LL_RTC_ALMB_MASK_ALL + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMB_SetMask(RTC_TypeDef *RTCx, uint32_t Mask) +{ + MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_MSK4 | RTC_ALRMBR_MSK3 | RTC_ALRMBR_MSK2 | RTC_ALRMBR_MSK1, Mask); +} + +/** + * @brief Get the Alarm B masks. + * @rmtoll RTC_ALRMBR MSK4 LL_RTC_ALMB_GetMask\n + * RTC_ALRMBR MSK3 LL_RTC_ALMB_GetMask\n + * RTC_ALRMBR MSK2 LL_RTC_ALMB_GetMask\n + * RTC_ALRMBR MSK1 LL_RTC_ALMB_GetMask + * @param RTCx RTC Instance + * @retval Returned value can be can be a combination of the following values: + * @arg @ref LL_RTC_ALMB_MASK_NONE + * @arg @ref LL_RTC_ALMB_MASK_DATEWEEKDAY + * @arg @ref LL_RTC_ALMB_MASK_HOURS + * @arg @ref LL_RTC_ALMB_MASK_MINUTES + * @arg @ref LL_RTC_ALMB_MASK_SECONDS + * @arg @ref LL_RTC_ALMB_MASK_ALL + */ +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetMask(const RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->ALRMBR, RTC_ALRMBR_MSK4 | RTC_ALRMBR_MSK3 | RTC_ALRMBR_MSK2 | RTC_ALRMBR_MSK1)); +} + +/** + * @brief Enable AlarmB Week day selection (DU[3:0] represents the week day. DT[1:0] is do not care) + * @rmtoll RTC_ALRMBR WDSEL LL_RTC_ALMB_EnableWeekday + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMB_EnableWeekday(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->ALRMBR, RTC_ALRMBR_WDSEL); +} + +/** + * @brief Disable AlarmB Week day selection (DU[3:0] represents the date ) + * @rmtoll RTC_ALRMBR WDSEL LL_RTC_ALMB_DisableWeekday + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMB_DisableWeekday(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->ALRMBR, RTC_ALRMBR_WDSEL); +} + +/** + * @brief Set ALARM B Day in BCD format + * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Day from binary to BCD format + * @rmtoll RTC_ALRMBR DT LL_RTC_ALMB_SetDay\n + * RTC_ALRMBR DU LL_RTC_ALMB_SetDay + * @param RTCx RTC Instance + * @param Day Value between Min_Data=0x01 and Max_Data=0x31 + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMB_SetDay(RTC_TypeDef *RTCx, uint32_t Day) +{ + MODIFY_REG(RTCx->ALRMBR, (RTC_ALRMBR_DT | RTC_ALRMBR_DU), + (((Day & 0xF0U) << (RTC_ALRMBR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_ALRMBR_DU_Pos))); +} + +/** + * @brief Get ALARM B Day in BCD format + * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format + * @rmtoll RTC_ALRMBR DT LL_RTC_ALMB_GetDay\n + * RTC_ALRMBR DU LL_RTC_ALMB_GetDay + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x01 and Max_Data=0x31 + */ +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetDay(const RTC_TypeDef *RTCx) +{ + return (uint32_t)((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_DT | RTC_ALRMBR_DU))) >> RTC_ALRMBR_DU_Pos); +} + +/** + * @brief Set ALARM B Weekday + * @rmtoll RTC_ALRMBR DU LL_RTC_ALMB_SetWeekDay + * @param RTCx RTC Instance + * @param WeekDay This parameter can be one of the following values: + * @arg @ref LL_RTC_WEEKDAY_MONDAY + * @arg @ref LL_RTC_WEEKDAY_TUESDAY + * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY + * @arg @ref LL_RTC_WEEKDAY_THURSDAY + * @arg @ref LL_RTC_WEEKDAY_FRIDAY + * @arg @ref LL_RTC_WEEKDAY_SATURDAY + * @arg @ref LL_RTC_WEEKDAY_SUNDAY + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMB_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay) +{ + MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_DU, WeekDay << RTC_ALRMBR_DU_Pos); +} + +/** + * @brief Get ALARM B Weekday + * @rmtoll RTC_ALRMBR DU LL_RTC_ALMB_GetWeekDay + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_WEEKDAY_MONDAY + * @arg @ref LL_RTC_WEEKDAY_TUESDAY + * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY + * @arg @ref LL_RTC_WEEKDAY_THURSDAY + * @arg @ref LL_RTC_WEEKDAY_FRIDAY + * @arg @ref LL_RTC_WEEKDAY_SATURDAY + * @arg @ref LL_RTC_WEEKDAY_SUNDAY + */ +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetWeekDay(const RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->ALRMBR, RTC_ALRMBR_DU) >> RTC_ALRMBR_DU_Pos); +} + +/** + * @brief Set ALARM B time format (AM/24-hour or PM notation) + * @rmtoll RTC_ALRMBR PM LL_RTC_ALMB_SetTimeFormat + * @param RTCx RTC Instance + * @param TimeFormat This parameter can be one of the following values: + * @arg @ref LL_RTC_ALMB_TIME_FORMAT_AM + * @arg @ref LL_RTC_ALMB_TIME_FORMAT_PM + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMB_SetTimeFormat(RTC_TypeDef *RTCx, uint32_t TimeFormat) +{ + MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_PM, TimeFormat); +} + +/** + * @brief Get ALARM B time format (AM or PM notation) + * @rmtoll RTC_ALRMBR PM LL_RTC_ALMB_GetTimeFormat + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_ALMB_TIME_FORMAT_AM + * @arg @ref LL_RTC_ALMB_TIME_FORMAT_PM + */ +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetTimeFormat(const RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->ALRMBR, RTC_ALRMBR_PM)); +} + +/** + * @brief Set ALARM B Hours in BCD format + * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Hours from binary to BCD format + * @rmtoll RTC_ALRMBR HT LL_RTC_ALMB_SetHour\n + * RTC_ALRMBR HU LL_RTC_ALMB_SetHour + * @param RTCx RTC Instance + * @param Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMB_SetHour(RTC_TypeDef *RTCx, uint32_t Hours) +{ + MODIFY_REG(RTCx->ALRMBR, (RTC_ALRMBR_HT | RTC_ALRMBR_HU), + (((Hours & 0xF0U) << (RTC_ALRMBR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMBR_HU_Pos))); +} + +/** + * @brief Get ALARM B Hours in BCD format + * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Hours from BCD to Binary format + * @rmtoll RTC_ALRMBR HT LL_RTC_ALMB_GetHour\n + * RTC_ALRMBR HU LL_RTC_ALMB_GetHour + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 + */ +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetHour(const RTC_TypeDef *RTCx) +{ + return (uint32_t)((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_HT | RTC_ALRMBR_HU))) >> RTC_ALRMBR_HU_Pos); +} + +/** + * @brief Set ALARM B Minutes in BCD format + * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Minutes from binary to BCD format + * @rmtoll RTC_ALRMBR MNT LL_RTC_ALMB_SetMinute\n + * RTC_ALRMBR MNU LL_RTC_ALMB_SetMinute + * @param RTCx RTC Instance + * @param Minutes between Min_Data=0x00 and Max_Data=0x59 + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMB_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes) +{ + MODIFY_REG(RTCx->ALRMBR, (RTC_ALRMBR_MNT | RTC_ALRMBR_MNU), + (((Minutes & 0xF0U) << (RTC_ALRMBR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMBR_MNU_Pos))); +} + +/** + * @brief Get ALARM B Minutes in BCD format + * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Minutes from BCD to Binary format + * @rmtoll RTC_ALRMBR MNT LL_RTC_ALMB_GetMinute\n + * RTC_ALRMBR MNU LL_RTC_ALMB_GetMinute + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x00 and Max_Data=0x59 + */ +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetMinute(const RTC_TypeDef *RTCx) +{ + return (uint32_t)((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_MNT | RTC_ALRMBR_MNU))) >> RTC_ALRMBR_MNU_Pos); +} + +/** + * @brief Set ALARM B Seconds in BCD format + * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Seconds from binary to BCD format + * @rmtoll RTC_ALRMBR ST LL_RTC_ALMB_SetSecond\n + * RTC_ALRMBR SU LL_RTC_ALMB_SetSecond + * @param RTCx RTC Instance + * @param Seconds Value between Min_Data=0x00 and Max_Data=0x59 + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMB_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds) +{ + MODIFY_REG(RTCx->ALRMBR, (RTC_ALRMBR_ST | RTC_ALRMBR_SU), + (((Seconds & 0xF0U) << (RTC_ALRMBR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMBR_SU_Pos))); +} + +/** + * @brief Get ALARM B Seconds in BCD format + * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD to Binary format + * @rmtoll RTC_ALRMBR ST LL_RTC_ALMB_GetSecond\n + * RTC_ALRMBR SU LL_RTC_ALMB_GetSecond + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x00 and Max_Data=0x59 + */ +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSecond(const RTC_TypeDef *RTCx) +{ + return (uint32_t)((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_ST | RTC_ALRMBR_SU))) >> RTC_ALRMBR_SU_Pos); +} + +/** + * @brief Set Alarm B Time (hour, minute and second) in BCD format + * @rmtoll RTC_ALRMBR PM LL_RTC_ALMB_ConfigTime\n + * RTC_ALRMBR HT LL_RTC_ALMB_ConfigTime\n + * RTC_ALRMBR HU LL_RTC_ALMB_ConfigTime\n + * RTC_ALRMBR MNT LL_RTC_ALMB_ConfigTime\n + * RTC_ALRMBR MNU LL_RTC_ALMB_ConfigTime\n + * RTC_ALRMBR ST LL_RTC_ALMB_ConfigTime\n + * RTC_ALRMBR SU LL_RTC_ALMB_ConfigTime + * @param RTCx RTC Instance + * @param Format12_24 This parameter can be one of the following values: + * @arg @ref LL_RTC_ALMB_TIME_FORMAT_AM + * @arg @ref LL_RTC_ALMB_TIME_FORMAT_PM + * @param Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 + * @param Minutes Value between Min_Data=0x00 and Max_Data=0x59 + * @param Seconds Value between Min_Data=0x00 and Max_Data=0x59 + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMB_ConfigTime(RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, + uint32_t Seconds) +{ + uint32_t temp; + + temp = Format12_24 | (((Hours & 0xF0U) << (RTC_ALRMBR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMBR_HU_Pos)) | \ + (((Minutes & 0xF0U) << (RTC_ALRMBR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMBR_MNU_Pos)) | \ + (((Seconds & 0xF0U) << (RTC_ALRMBR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMBR_SU_Pos)); + + MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_PM | RTC_ALRMBR_HT | RTC_ALRMBR_HU | RTC_ALRMBR_MNT | RTC_ALRMBR_MNU | RTC_ALRMBR_ST + | RTC_ALRMBR_SU, temp); +} + +/** + * @brief Get Alarm B Time (hour, minute and second) in BCD format + * @note helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND + * are available to get independently each parameter. + * @rmtoll RTC_ALRMBR HT LL_RTC_ALMB_GetTime\n + * RTC_ALRMBR HU LL_RTC_ALMB_GetTime\n + * RTC_ALRMBR MNT LL_RTC_ALMB_GetTime\n + * RTC_ALRMBR MNU LL_RTC_ALMB_GetTime\n + * RTC_ALRMBR ST LL_RTC_ALMB_GetTime\n + * RTC_ALRMBR SU LL_RTC_ALMB_GetTime + * @param RTCx RTC Instance + * @retval Combination of hours, minutes and seconds. + */ +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetTime(RTC_TypeDef *RTCx) +{ + return (uint32_t)((LL_RTC_ALMB_GetHour(RTCx) << RTC_OFFSET_HOUR) | (LL_RTC_ALMB_GetMinute(RTCx) << RTC_OFFSET_MINUTE) | LL_RTC_ALMB_GetSecond(RTCx)); +} + +/** + * @brief Set Alarm B Mask the most-significant bits starting at this bit + * @note This register can be written only when ALRBE is reset in RTC_CR register, + * or in initialization mode. + * @rmtoll RTC_ALRMBSSR MASKSS LL_RTC_ALMB_SetSubSecondMask + * @param RTCx RTC Instance + * @param Mask If binary mode is none, Value between Min_Data=0x0 and Max_Data=0xF + * else Value between Min_Data=0x0 and Max_Data=0x3F + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMB_SetSubSecondMask(RTC_TypeDef *RTCx, uint32_t Mask) +{ + MODIFY_REG(RTCx->ALRMBSSR, RTC_ALRMBSSR_MASKSS, Mask << RTC_ALRMBSSR_MASKSS_Pos); +} + +/** + * @brief Get Alarm B Mask the most-significant bits starting at this bit + * @rmtoll RTC_ALRMBSSR MASKSS LL_RTC_ALMB_GetSubSecondMask + * @param RTCx RTC Instance + * @retval If binary mode is none, Value between Min_Data=0x0 and Max_Data=0xF + * else Value between Min_Data=0x0 and Max_Data=0x3F + */ +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSubSecondMask(const RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->ALRMBSSR, RTC_ALRMBSSR_MASKSS) >> RTC_ALRMBSSR_MASKSS_Pos); +} + +/** + * @brief Set Alarm B Binary mode auto clear + * @note This register can be written only when ALRBE is reset in RTC_CR register, + * or in initialization mode. + * @rmtoll RTC_ALRBBINR SSCLR LL_RTC_ALMB_SetBinAutoClr + * @param RTCx RTC Instance + * @param BinaryAutoClr This parameter can be one of the following values: + * @arg @ref LL_RTC_ALMB_SUBSECONDBIN_AUTOCLR_NO + * @arg @ref LL_RTC_ALMB_SUBSECONDBIN_AUTOCLR_YES + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMB_SetBinAutoClr(RTC_TypeDef *RTCx, uint32_t BinaryAutoClr) +{ + MODIFY_REG(RTCx->ALRMBSSR, RTC_ALRMBSSR_SSCLR, BinaryAutoClr); +} + +/** + * @brief Get Alarm B Binary mode auto clear + * @rmtoll RTC_ALRBBINR SSCLR LL_RTC_ALMB_GetBinAutoClr + * @param RTCx RTC Instance + * @retval It can be one of the following values: + * @arg @ref LL_RTC_ALMB_SUBSECONDBIN_AUTOCLR_NO + * @arg @ref LL_RTC_ALMB_SUBSECONDBIN_AUTOCLR_YES + */ +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetBinAutoClr(const RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->ALRMBSSR, RTC_ALRMBSSR_SSCLR)); +} + +/** + * @brief Set Alarm B Sub seconds value + * @rmtoll RTC_ALRMBBINR SS LL_RTC_ALMB_SetSubSecond + * @param RTCx RTC Instance + * @param Subsecond If binary mode is none, Value between Min_Data=0x0 and Max_Data=0x7FFF + * else Value between Min_Data=0x0 and Max_Data=0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMB_SetSubSecond(RTC_TypeDef *RTCx, uint32_t Subsecond) +{ + MODIFY_REG(RTCx->ALRBBINR, RTC_ALRBBINR_SS, Subsecond); +} + +/** + * @brief Get Alarm B Sub seconds value + * @rmtoll RTC_ALRMBBINR SS LL_RTC_ALMB_GetSubSecond + * @param RTCx RTC Instance + * @retval If binary mode is none, Value between Min_Data=0x0 and Max_Data=0x7FFF + * else Value between Min_Data=0x0 and Max_Data=0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSubSecond(const RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->ALRBBINR, RTC_ALRBBINR_SS)); +} + +/** + * @} + */ + +/** @defgroup RTC_LL_EF_Timestamp Timestamp + * @{ + */ + +/** + * @brief Enable internal event timestamp + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR ITSE LL_RTC_TS_EnableInternalEvent + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_TS_EnableInternalEvent(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CR, RTC_CR_ITSE); +} + +/** + * @brief Disable internal event timestamp + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR ITSE LL_RTC_TS_DisableInternalEvent + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_TS_DisableInternalEvent(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CR, RTC_CR_ITSE); +} + +/** + * @brief Enable Timestamp + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR TSE LL_RTC_TS_Enable + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_TS_Enable(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CR, RTC_CR_TSE); +} + +/** + * @brief Disable Timestamp + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR TSE LL_RTC_TS_Disable + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_TS_Disable(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CR, RTC_CR_TSE); +} + +/** + * @brief Set Time-stamp event active edge + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @note TSE must be reset when TSEDGE is changed to avoid unwanted TSF setting + * @rmtoll RTC_CR TSEDGE LL_RTC_TS_SetActiveEdge + * @param RTCx RTC Instance + * @param Edge This parameter can be one of the following values: + * @arg @ref LL_RTC_TIMESTAMP_EDGE_RISING + * @arg @ref LL_RTC_TIMESTAMP_EDGE_FALLING + * @retval None + */ +__STATIC_INLINE void LL_RTC_TS_SetActiveEdge(RTC_TypeDef *RTCx, uint32_t Edge) +{ + MODIFY_REG(RTCx->CR, RTC_CR_TSEDGE, Edge); +} + +/** + * @brief Get Time-stamp event active edge + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR TSEDGE LL_RTC_TS_GetActiveEdge + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_TIMESTAMP_EDGE_RISING + * @arg @ref LL_RTC_TIMESTAMP_EDGE_FALLING + */ +__STATIC_INLINE uint32_t LL_RTC_TS_GetActiveEdge(const RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_TSEDGE)); +} + +/** + * @brief Get Timestamp AM/PM notation (AM or 24-hour format) + * @rmtoll RTC_TSTR PM LL_RTC_TS_GetTimeFormat + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_TS_TIME_FORMAT_AM + * @arg @ref LL_RTC_TS_TIME_FORMAT_PM + */ +__STATIC_INLINE uint32_t LL_RTC_TS_GetTimeFormat(const RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_PM)); +} + +/** + * @brief Get Timestamp Hours in BCD format + * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Hours from BCD to Binary format + * @rmtoll RTC_TSTR HT LL_RTC_TS_GetHour\n + * RTC_TSTR HU LL_RTC_TS_GetHour + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 + */ +__STATIC_INLINE uint32_t LL_RTC_TS_GetHour(const RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_HT | RTC_TSTR_HU) >> RTC_TSTR_HU_Pos); +} + +/** + * @brief Get Timestamp Minutes in BCD format + * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Minutes from BCD to Binary format + * @rmtoll RTC_TSTR MNT LL_RTC_TS_GetMinute\n + * RTC_TSTR MNU LL_RTC_TS_GetMinute + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x00 and Max_Data=0x59 + */ +__STATIC_INLINE uint32_t LL_RTC_TS_GetMinute(const RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_MNT | RTC_TSTR_MNU) >> RTC_TSTR_MNU_Pos); +} + +/** + * @brief Get Timestamp Seconds in BCD format + * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD to Binary format + * @rmtoll RTC_TSTR ST LL_RTC_TS_GetSecond\n + * RTC_TSTR SU LL_RTC_TS_GetSecond + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x00 and Max_Data=0x59 + */ +__STATIC_INLINE uint32_t LL_RTC_TS_GetSecond(const RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_ST | RTC_TSTR_SU)); +} + +/** + * @brief Get Timestamp time (hour, minute and second) in BCD format + * @note helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND + * are available to get independently each parameter. + * @rmtoll RTC_TSTR HT LL_RTC_TS_GetTime\n + * RTC_TSTR HU LL_RTC_TS_GetTime\n + * RTC_TSTR MNT LL_RTC_TS_GetTime\n + * RTC_TSTR MNU LL_RTC_TS_GetTime\n + * RTC_TSTR ST LL_RTC_TS_GetTime\n + * RTC_TSTR SU LL_RTC_TS_GetTime + * @param RTCx RTC Instance + * @retval Combination of hours, minutes and seconds. + */ +__STATIC_INLINE uint32_t LL_RTC_TS_GetTime(const RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->TSTR, + RTC_TSTR_HT | RTC_TSTR_HU | RTC_TSTR_MNT | RTC_TSTR_MNU | RTC_TSTR_ST | RTC_TSTR_SU)); +} + +/** + * @brief Get Timestamp Week day + * @rmtoll RTC_TSDR WDU LL_RTC_TS_GetWeekDay + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_WEEKDAY_MONDAY + * @arg @ref LL_RTC_WEEKDAY_TUESDAY + * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY + * @arg @ref LL_RTC_WEEKDAY_THURSDAY + * @arg @ref LL_RTC_WEEKDAY_FRIDAY + * @arg @ref LL_RTC_WEEKDAY_SATURDAY + * @arg @ref LL_RTC_WEEKDAY_SUNDAY + */ +__STATIC_INLINE uint32_t LL_RTC_TS_GetWeekDay(const RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_WDU) >> RTC_TSDR_WDU_Pos); +} + +/** + * @brief Get Timestamp Month in BCD format + * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Month from BCD to Binary format + * @rmtoll RTC_TSDR MT LL_RTC_TS_GetMonth\n + * RTC_TSDR MU LL_RTC_TS_GetMonth + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_MONTH_JANUARY + * @arg @ref LL_RTC_MONTH_FEBRUARY + * @arg @ref LL_RTC_MONTH_MARCH + * @arg @ref LL_RTC_MONTH_APRIL + * @arg @ref LL_RTC_MONTH_MAY + * @arg @ref LL_RTC_MONTH_JUNE + * @arg @ref LL_RTC_MONTH_JULY + * @arg @ref LL_RTC_MONTH_AUGUST + * @arg @ref LL_RTC_MONTH_SEPTEMBER + * @arg @ref LL_RTC_MONTH_OCTOBER + * @arg @ref LL_RTC_MONTH_NOVEMBER + * @arg @ref LL_RTC_MONTH_DECEMBER + */ +__STATIC_INLINE uint32_t LL_RTC_TS_GetMonth(const RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_MT | RTC_TSDR_MU) >> RTC_TSDR_MU_Pos); +} + +/** + * @brief Get Timestamp Day in BCD format + * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format + * @rmtoll RTC_TSDR DT LL_RTC_TS_GetDay\n + * RTC_TSDR DU LL_RTC_TS_GetDay + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x01 and Max_Data=0x31 + */ +__STATIC_INLINE uint32_t LL_RTC_TS_GetDay(const RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_DT | RTC_TSDR_DU)); +} + +/** + * @brief Get Timestamp date (WeekDay, Day and Month) in BCD format + * @note helper macros __LL_RTC_GET_WEEKDAY, __LL_RTC_GET_MONTH, + * and __LL_RTC_GET_DAY are available to get independently each parameter. + * @rmtoll RTC_TSDR WDU LL_RTC_TS_GetDate\n + * RTC_TSDR MT LL_RTC_TS_GetDate\n + * RTC_TSDR MU LL_RTC_TS_GetDate\n + * RTC_TSDR DT LL_RTC_TS_GetDate\n + * RTC_TSDR DU LL_RTC_TS_GetDate + * @param RTCx RTC Instance + * @retval Combination of Weekday, Day and Month + */ +__STATIC_INLINE uint32_t LL_RTC_TS_GetDate(const RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_WDU | RTC_TSDR_MT | RTC_TSDR_MU | RTC_TSDR_DT | RTC_TSDR_DU)); +} + +/** + * @brief Get time-stamp sub second value + * @rmtoll RTC_TSSSR SS LL_RTC_TS_GetSubSecond + * @param RTCx RTC Instance + * @retval If binary mode is none, Value between Min_Data=0x0 and Max_Data=0x7FFF + * else Value between Min_Data=0x0 and Max_Data=0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_RTC_TS_GetSubSecond(const RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->TSSSR, RTC_TSSSR_SS)); +} + +/** + * @brief Activate timestamp on tamper detection event + * @rmtoll RTC_CR TAMPTS LL_RTC_TS_EnableOnTamper + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_TS_EnableOnTamper(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CR, RTC_CR_TAMPTS); +} + +/** + * @brief Disable timestamp on tamper detection event + * @rmtoll RTC_CR TAMPTS LL_RTC_TS_DisableOnTamper + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_TS_DisableOnTamper(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CR, RTC_CR_TAMPTS); +} + + +/** + * @} + */ + +/** @defgroup RTC_LL_EF_Tamper Tamper + * @{ + */ + +/** + * @brief Enable TAMPx input detection + * @rmtoll TAMP_CR1 TAMP1E LL_RTC_TAMPER_Enable\n + * TAMP_CR1 TAMP2E LL_RTC_TAMPER_Enable\n + * TAMP_CR1 TAMP3E LL_RTC_TAMPER_Enable\n + * @param RTCx RTC Instance + * @param Tamper This parameter can be a combination of the following values: + * @arg @ref RTC_LL_EC_TAMPER + * + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_Enable(const RTC_TypeDef *RTCx, uint32_t Tamper) +{ + UNUSED(RTCx); + SET_BIT(TAMP->CR1, Tamper); +} + +/** + * @brief Clear TAMPx input detection + * @rmtoll TAMP_CR1 TAMP1E LL_RTC_TAMPER_Disable\n + * TAMP_CR1 TAMP2E LL_RTC_TAMPER_Disable\n + * TAMP_CR1 TAMP3E LL_RTC_TAMPER_Disable\n + * @param RTCx RTC Instance + * @param Tamper This parameter can be a combination of the following values: + * @arg @ref RTC_LL_EC_TAMPER + * + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_Disable(const RTC_TypeDef *RTCx, uint32_t Tamper) +{ + UNUSED(RTCx); + CLEAR_BIT(TAMP->CR1, Tamper); +} + +/** + * @brief Enable Tamper mask flag + * @note Associated Tamper IT must not enabled when tamper mask is set. + * @rmtoll TAMP_CR2 TAMP1MSK LL_RTC_TAMPER_EnableMask\n + * TAMP_CR2 TAMP2MSK LL_RTC_TAMPER_EnableMask\n + * TAMP_CR2 TAMP3MSK LL_RTC_TAMPER_EnableMask + * @param RTCx RTC Instance + * @param Mask This parameter can be a combination of the following values: + * @arg @ref RTC_LL_EC_TAMPER_MASK + * + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_EnableMask(const RTC_TypeDef *RTCx, uint32_t Mask) +{ + UNUSED(RTCx); + SET_BIT(TAMP->CR2, Mask); +} + +/** + * @brief Disable Tamper mask flag + * @rmtoll TAMP_MISR TAMP1MF LL_RTC_TAMPER_DisableMask\n + * TAMP_MISR TAMP2MF LL_RTC_TAMPER_DisableMask\n + * TAMP_MISR TAMP3MF LL_RTC_TAMPER_DisableMask + * @param RTCx RTC Instance + * @param Mask This parameter can be a combination of the following values: + * @arg @ref RTC_LL_EC_TAMPER_MASK + * + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_DisableMask(const RTC_TypeDef *RTCx, uint32_t Mask) +{ + UNUSED(RTCx); + CLEAR_BIT(TAMP->CR2, Mask); +} + +/** + * @brief Enable backup register erase after Tamper event detection + * @rmtoll TAMP_CR2 TAMP1NOERASE LL_RTC_TAMPER_EnableEraseBKP\n + * TAMP_CR2 TAMP2NOERASE LL_RTC_TAMPER_EnableEraseBKP\n + * TAMP_CR2 TAMP3NOERASE LL_RTC_TAMPER_EnableEraseBKP\n + * @param RTCx RTC Instance + * @param Tamper This parameter can be a combination of the following values: + * @arg @ref RTC_LL_EC_TAMPER_NOERASE + * + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_EnableEraseBKP(const RTC_TypeDef *RTCx, uint32_t Tamper) +{ + UNUSED(RTCx); + CLEAR_BIT(TAMP->CR2, Tamper); +} + +/** + * @brief Disable backup register erase after Tamper event detection + * @rmtoll TAMP_CR2 TAMP1NOERASE LL_RTC_TAMPER_DisableEraseBKP\n + * TAMP_CR2 TAMP2NOERASE LL_RTC_TAMPER_DisableEraseBKP\n + * TAMP_CR2 TAMP3NOERASE LL_RTC_TAMPER_DisableEraseBKP\n + * @param RTCx RTC Instance + * @param Tamper This parameter can be a combination of the following values: + * @arg @ref RTC_LL_EC_TAMPER_NOERASE + * + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_DisableEraseBKP(const RTC_TypeDef *RTCx, uint32_t Tamper) +{ + UNUSED(RTCx); + SET_BIT(TAMP->CR2, Tamper); +} + +/** + * @brief Disable RTC_TAMPx pull-up disable (Disable precharge of RTC_TAMPx pins) + * @rmtoll TAMP_FLTCR TAMPPUDIS LL_RTC_TAMPER_DisablePullUp + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_DisablePullUp(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + SET_BIT(TAMP->FLTCR, TAMP_FLTCR_TAMPPUDIS); +} + +/** + * @brief Enable RTC_TAMPx pull-up disable ( Precharge RTC_TAMPx pins before sampling) + * @rmtoll TAMP_FLTCR TAMPPUDIS LL_RTC_TAMPER_EnablePullUp + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_EnablePullUp(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + CLEAR_BIT(TAMP->FLTCR, TAMP_FLTCR_TAMPPUDIS); +} + +/** + * @brief Set RTC_TAMPx precharge duration + * @rmtoll TAMP_FLTCR TAMPPRCH LL_RTC_TAMPER_SetPrecharge + * @param RTCx RTC Instance + * @param Duration This parameter can be one of the following values: + * @arg @ref LL_RTC_TAMPER_DURATION_1RTCCLK + * @arg @ref LL_RTC_TAMPER_DURATION_2RTCCLK + * @arg @ref LL_RTC_TAMPER_DURATION_4RTCCLK + * @arg @ref LL_RTC_TAMPER_DURATION_8RTCCLK + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_SetPrecharge(const RTC_TypeDef *RTCx, uint32_t Duration) +{ + UNUSED(RTCx); + MODIFY_REG(TAMP->FLTCR, TAMP_FLTCR_TAMPPRCH, Duration); +} + +/** + * @brief Get RTC_TAMPx precharge duration + * @rmtoll TAMP_FLTCR TAMPPRCH LL_RTC_TAMPER_GetPrecharge + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_TAMPER_DURATION_1RTCCLK + * @arg @ref LL_RTC_TAMPER_DURATION_2RTCCLK + * @arg @ref LL_RTC_TAMPER_DURATION_4RTCCLK + * @arg @ref LL_RTC_TAMPER_DURATION_8RTCCLK + */ +__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetPrecharge(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return (uint32_t)(READ_BIT(TAMP->FLTCR, TAMP_FLTCR_TAMPPRCH)); +} + +/** + * @brief Set RTC_TAMPx filter count + * @rmtoll TAMP_FLTCR TAMPFLT LL_RTC_TAMPER_SetFilterCount + * @param RTCx RTC Instance + * @param FilterCount This parameter can be one of the following values: + * @arg @ref LL_RTC_TAMPER_FILTER_DISABLE + * @arg @ref LL_RTC_TAMPER_FILTER_2SAMPLE + * @arg @ref LL_RTC_TAMPER_FILTER_4SAMPLE + * @arg @ref LL_RTC_TAMPER_FILTER_8SAMPLE + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_SetFilterCount(const RTC_TypeDef *RTCx, uint32_t FilterCount) +{ + UNUSED(RTCx); + MODIFY_REG(TAMP->FLTCR, TAMP_FLTCR_TAMPFLT, FilterCount); +} + +/** + * @brief Get RTC_TAMPx filter count + * @rmtoll TAMP_FLTCR TAMPFLT LL_RTC_TAMPER_GetFilterCount + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_TAMPER_FILTER_DISABLE + * @arg @ref LL_RTC_TAMPER_FILTER_2SAMPLE + * @arg @ref LL_RTC_TAMPER_FILTER_4SAMPLE + * @arg @ref LL_RTC_TAMPER_FILTER_8SAMPLE + */ +__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetFilterCount(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return (uint32_t)(READ_BIT(TAMP->FLTCR, TAMP_FLTCR_TAMPFLT)); +} + +/** + * @brief Set Tamper sampling frequency + * @rmtoll TAMP_FLTCR TAMPFREQ LL_RTC_TAMPER_SetSamplingFreq + * @param RTCx RTC Instance + * @param SamplingFreq This parameter can be one of the following values: + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_32768 + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_16384 + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_8192 + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_4096 + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_2048 + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_1024 + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_512 + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_256 + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_SetSamplingFreq(const RTC_TypeDef *RTCx, uint32_t SamplingFreq) +{ + UNUSED(RTCx); + MODIFY_REG(TAMP->FLTCR, TAMP_FLTCR_TAMPFREQ, SamplingFreq); +} + +/** + * @brief Get Tamper sampling frequency + * @rmtoll TAMP_FLTCR TAMPFREQ LL_RTC_TAMPER_GetSamplingFreq + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_32768 + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_16384 + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_8192 + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_4096 + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_2048 + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_1024 + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_512 + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_256 + */ +__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetSamplingFreq(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return (uint32_t)(READ_BIT(TAMP->FLTCR, TAMP_FLTCR_TAMPFREQ)); +} + +/** + * @brief Enable Active level for Tamper input + * @rmtoll TAMP_CR2 TAMP1TRG LL_RTC_TAMPER_EnableActiveLevel\n + * TAMP_CR2 TAMP2TRG LL_RTC_TAMPER_EnableActiveLevel\n + * TAMP_CR2 TAMP3TRG LL_RTC_TAMPER_EnableActiveLevel\n + * @param RTCx RTC Instance + * @param Tamper This parameter can be a combination of the following values: + * @arg @ref RTC_LL_EC_TAMPER_ACTIVELEVEL + * + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_EnableActiveLevel(const RTC_TypeDef *RTCx, uint32_t Tamper) +{ + UNUSED(RTCx); + SET_BIT(TAMP->CR2, Tamper); +} + +/** + * @brief Disable Active level for Tamper input + * @rmtoll TAMP_CR2 TAMP1TRG LL_RTC_TAMPER_DisableActiveLevel\n + * TAMP_CR2 TAMP2TRG LL_RTC_TAMPER_DisableActiveLevel\n + * TAMP_CR2 TAMP3TRG LL_RTC_TAMPER_DisableActiveLevel\n + * @param RTCx RTC Instance + * @param Tamper This parameter can be a combination of the following values: + * @arg @ref RTC_LL_EC_TAMPER_ACTIVELEVEL + * + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_DisableActiveLevel(const RTC_TypeDef *RTCx, uint32_t Tamper) +{ + UNUSED(RTCx); + CLEAR_BIT(TAMP->CR2, Tamper); +} + +/** + * @} + */ + +/** @defgroup RTC_LL_EF_Internal_Tamper Internal Tamper + * @{ + */ + +/** + * @brief Enable internal tamper detection. + * @rmtoll TAMP_CR1 ITAMP1E LL_RTC_TAMPER_ITAMP_Enable\n + * TAMP_CR1 ITAMP2E LL_RTC_TAMPER_ITAMP_Enable\n + * TAMP_CR1 ITAMP3E LL_RTC_TAMPER_ITAMP_Enable\n + * TAMP_CR1 ITAMP5E LL_RTC_TAMPER_ITAMP_Enable\n + * TAMP_CR1 ITAMP6E LL_RTC_TAMPER_ITAMP_Enable + * TAMP_CR1 ITAMP8E LL_RTC_TAMPER_ITAMP_Enable + * @param RTCx RTC Instance + * @param InternalTamper This parameter can be a combination of the following values: + * @arg @ref RTC_LL_EC_INTERNAL + * + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_ITAMP_Enable(const RTC_TypeDef *RTCx, uint32_t InternalTamper) +{ + UNUSED(RTCx); + SET_BIT(TAMP->CR1, InternalTamper); +} + +/** + * @brief Disable internal tamper detection. + * @rmtoll TAMP_CR1 ITAMP1E LL_RTC_TAMPER_ITAMP_Disable\n + * TAMP_CR1 ITAMP2E LL_RTC_TAMPER_ITAMP_Disable\n + * TAMP_CR1 ITAMP3E LL_RTC_TAMPER_ITAMP_Disable\n + * TAMP_CR1 ITAMP5E LL_RTC_TAMPER_ITAMP_Disable\n + * TAMP_CR1 ITAMP6E LL_RTC_TAMPER_ITAMP_Disable + * TAMP_CR1 ITAMP8E LL_RTC_TAMPER_ITAMP_Disable + * @param RTCx RTC Instance + * @param InternalTamper This parameter can be a combination of the following values: + * @arg @ref RTC_LL_EC_INTERNAL + * + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_ITAMP_Disable(const RTC_TypeDef *RTCx, uint32_t InternalTamper) +{ + UNUSED(RTCx); + CLEAR_BIT(TAMP->CR1, InternalTamper); +} + +/** + * @} + */ + +/** @defgroup RTC_LL_EF_Wakeup Wakeup + * @{ + */ + +/** + * @brief Enable Wakeup timer + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR WUTE LL_RTC_WAKEUP_Enable + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_WAKEUP_Enable(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CR, RTC_CR_WUTE); +} + +/** + * @brief Disable Wakeup timer + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR WUTE LL_RTC_WAKEUP_Disable + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_WAKEUP_Disable(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CR, RTC_CR_WUTE); +} + +/** + * @brief Check if Wakeup timer is enabled or not + * @rmtoll RTC_CR WUTE LL_RTC_WAKEUP_IsEnabled + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_WAKEUP_IsEnabled(const RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->CR, RTC_CR_WUTE) == (RTC_CR_WUTE)) ? 1U : 0U); +} + +/** + * @brief Select Wakeup clock + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @note Bit can be written only when RTC_CR WUTE bit = 0 and RTC_ICSR WUTWF bit = 1 + * @rmtoll RTC_CR WUCKSEL LL_RTC_WAKEUP_SetClock + * @param RTCx RTC Instance + * @param WakeupClock This parameter can be one of the following values: + * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_16 + * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_8 + * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_4 + * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_2 + * @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE + * @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE_WUT + * @retval None + */ +__STATIC_INLINE void LL_RTC_WAKEUP_SetClock(RTC_TypeDef *RTCx, uint32_t WakeupClock) +{ + MODIFY_REG(RTCx->CR, RTC_CR_WUCKSEL, WakeupClock); +} + +/** + * @brief Get Wakeup clock + * @rmtoll RTC_CR WUCKSEL LL_RTC_WAKEUP_GetClock + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_16 + * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_8 + * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_4 + * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_2 + * @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE + * @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE_WUT + */ +__STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetClock(const RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_WUCKSEL)); +} + +/** + * @brief Set Wakeup auto-reload value + * @note Bit can be written only when WUTWF is set to 1 in RTC_ICSR + * @rmtoll RTC_WUTR WUT LL_RTC_WAKEUP_SetAutoReload + * @param RTCx RTC Instance + * @param Value Value between Min_Data=0x00 and Max_Data=0xFFFF + * @retval None + */ +__STATIC_INLINE void LL_RTC_WAKEUP_SetAutoReload(RTC_TypeDef *RTCx, uint32_t Value) +{ + MODIFY_REG(RTCx->WUTR, RTC_WUTR_WUT, Value); +} + +/** + * @brief Get Wakeup auto-reload value + * @rmtoll RTC_WUTR WUT LL_RTC_WAKEUP_GetAutoReload + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x00 and Max_Data=0xFFFF + */ +__STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetAutoReload(const RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->WUTR, RTC_WUTR_WUT)); +} + +/** + * @} + */ + +/** @defgroup RTC_LL_EF_Backup_Registers Backup_Registers + * @{ + */ + +/** + * @brief Writes a data in a specified Backup data register. + * @rmtoll TAMP_BKPxR BKP LL_RTC_BKP_SetRegister + * @param RTCx RTC Instance + * @param BackupRegister This parameter can be one of the following values: + * @arg @ref LL_RTC_BKP_DR0 + * @arg @ref LL_RTC_BKP_DR1 + * @arg @ref LL_RTC_BKP_DR2 + * @arg @ref LL_RTC_BKP_DR3 + * @arg @ref LL_RTC_BKP_DR4 + * @arg @ref LL_RTC_BKP_DR5 + * @arg @ref LL_RTC_BKP_DR6 + * @arg @ref LL_RTC_BKP_DR7 + * @arg @ref LL_RTC_BKP_DR8 + * @arg @ref LL_RTC_BKP_DR9 + * @arg @ref LL_RTC_BKP_DR10 + * @arg @ref LL_RTC_BKP_DR11 + * @arg @ref LL_RTC_BKP_DR12 + * @arg @ref LL_RTC_BKP_DR13 + * @arg @ref LL_RTC_BKP_DR14 + * @arg @ref LL_RTC_BKP_DR15 + * @arg @ref LL_RTC_BKP_DR16 + * @arg @ref LL_RTC_BKP_DR17 + * @arg @ref LL_RTC_BKP_DR18 + * @arg @ref LL_RTC_BKP_DR19 + * @param Data Value between Min_Data=0x00 and Max_Data=0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_RTC_BKP_SetRegister(const RTC_TypeDef *RTCx, uint32_t BackupRegister, uint32_t Data) +{ + uint32_t tmp; + + UNUSED(RTCx); + + tmp = (uint32_t)(&(TAMP->BKP0R)); + tmp += (BackupRegister * 4U); + + /* Write the specified register */ + *(__IO uint32_t *)tmp = (uint32_t)Data; +} + +/** + * @brief Reads data from the specified RTC Backup data Register. + * @rmtoll TAMP_BKPxR BKP LL_RTC_BKP_GetRegister + * @param RTCx RTC Instance + * @param BackupRegister This parameter can be one of the following values: + * @arg @ref LL_RTC_BKP_DR0 + * @arg @ref LL_RTC_BKP_DR1 + * @arg @ref LL_RTC_BKP_DR2 + * @arg @ref LL_RTC_BKP_DR3 + * @arg @ref LL_RTC_BKP_DR4 + * @arg @ref LL_RTC_BKP_DR5 + * @arg @ref LL_RTC_BKP_DR6 + * @arg @ref LL_RTC_BKP_DR7 + * @arg @ref LL_RTC_BKP_DR8 + * @arg @ref LL_RTC_BKP_DR9 + * @arg @ref LL_RTC_BKP_DR10 + * @arg @ref LL_RTC_BKP_DR11 + * @arg @ref LL_RTC_BKP_DR12 + * @arg @ref LL_RTC_BKP_DR13 + * @arg @ref LL_RTC_BKP_DR14 + * @arg @ref LL_RTC_BKP_DR15 + * @arg @ref LL_RTC_BKP_DR16 + * @arg @ref LL_RTC_BKP_DR17 + * @arg @ref LL_RTC_BKP_DR18 + * @arg @ref LL_RTC_BKP_DR19 + * @retval Value between Min_Data=0x00 and Max_Data=0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_RTC_BKP_GetRegister(const RTC_TypeDef *RTCx, uint32_t BackupRegister) +{ + uint32_t tmp; + + UNUSED(RTCx); + + tmp = (uint32_t)(&(TAMP->BKP0R)); + tmp += (BackupRegister * 4U); + + /* Read the specified register */ + return (*(__IO uint32_t *)tmp); +} + +/** + * @} + */ + +/** @defgroup RTC_LL_EF_Calibration Calibration + * @{ + */ + +/** + * @brief Set Calibration output frequency (1 Hz or 512 Hz) + * @note Bits are write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR COE LL_RTC_CAL_SetOutputFreq\n + * RTC_CR COSEL LL_RTC_CAL_SetOutputFreq + * @param RTCx RTC Instance + * @param Frequency This parameter can be one of the following values: + * @arg @ref LL_RTC_CALIB_OUTPUT_NONE + * @arg @ref LL_RTC_CALIB_OUTPUT_1HZ + * @arg @ref LL_RTC_CALIB_OUTPUT_512HZ + * @retval None + */ +__STATIC_INLINE void LL_RTC_CAL_SetOutputFreq(RTC_TypeDef *RTCx, uint32_t Frequency) +{ + MODIFY_REG(RTCx->CR, RTC_CR_COE | RTC_CR_COSEL, Frequency); +} + +/** + * @brief Get Calibration output frequency (1 Hz or 512 Hz) + * @rmtoll RTC_CR COE LL_RTC_CAL_GetOutputFreq\n + * RTC_CR COSEL LL_RTC_CAL_GetOutputFreq + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_CALIB_OUTPUT_NONE + * @arg @ref LL_RTC_CALIB_OUTPUT_1HZ + * @arg @ref LL_RTC_CALIB_OUTPUT_512HZ + */ +__STATIC_INLINE uint32_t LL_RTC_CAL_GetOutputFreq(const RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_COE | RTC_CR_COSEL)); +} + +/** + * @brief Insert or not One RTCCLK pulse every 2exp11 pulses (frequency increased by 488.5 ppm) + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @note Bit can be written only when RECALPF is set to 0 in RTC_ICSR + * @rmtoll RTC_CALR CALP LL_RTC_CAL_SetPulse + * @param RTCx RTC Instance + * @param Pulse This parameter can be one of the following values: + * @arg @ref LL_RTC_CALIB_INSERTPULSE_NONE + * @arg @ref LL_RTC_CALIB_INSERTPULSE_SET + * @retval None + */ +__STATIC_INLINE void LL_RTC_CAL_SetPulse(RTC_TypeDef *RTCx, uint32_t Pulse) +{ + MODIFY_REG(RTCx->CALR, RTC_CALR_CALP, Pulse); +} + +/** + * @brief Check if one RTCCLK has been inserted or not every 2exp11 pulses (frequency increased by 488.5 ppm) + * @rmtoll RTC_CALR CALP LL_RTC_CAL_IsPulseInserted + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_CAL_IsPulseInserted(const RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->CALR, RTC_CALR_CALP) == (RTC_CALR_CALP)) ? 1U : 0U); +} + +/** + * @brief Set the calibration cycle period + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @note Bit can be written only when RECALPF is set to 0 in RTC_ICSR + * @rmtoll RTC_CALR CALW8 LL_RTC_CAL_SetPeriod\n + * RTC_CALR CALW16 LL_RTC_CAL_SetPeriod + * @param RTCx RTC Instance + * @param Period This parameter can be one of the following values: + * @arg @ref LL_RTC_CALIB_PERIOD_32SEC + * @arg @ref LL_RTC_CALIB_PERIOD_16SEC + * @arg @ref LL_RTC_CALIB_PERIOD_8SEC + * @retval None + */ +__STATIC_INLINE void LL_RTC_CAL_SetPeriod(RTC_TypeDef *RTCx, uint32_t Period) +{ + MODIFY_REG(RTCx->CALR, RTC_CALR_CALW8 | RTC_CALR_CALW16, Period); +} + +/** + * @brief Get the calibration cycle period + * @rmtoll RTC_CALR CALW8 LL_RTC_CAL_GetPeriod\n + * RTC_CALR CALW16 LL_RTC_CAL_GetPeriod + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_CALIB_PERIOD_32SEC + * @arg @ref LL_RTC_CALIB_PERIOD_16SEC + * @arg @ref LL_RTC_CALIB_PERIOD_8SEC + */ +__STATIC_INLINE uint32_t LL_RTC_CAL_GetPeriod(const RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->CALR, RTC_CALR_CALW8 | RTC_CALR_CALW16)); +} + +/** + * @brief Set Calibration minus + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @note Bit can be written only when RECALPF is set to 0 in RTC_ICSR + * @rmtoll RTC_CALR CALM LL_RTC_CAL_SetMinus + * @param RTCx RTC Instance + * @param CalibMinus Value between Min_Data=0x00 and Max_Data=0x1FF + * @retval None + */ +__STATIC_INLINE void LL_RTC_CAL_SetMinus(RTC_TypeDef *RTCx, uint32_t CalibMinus) +{ + MODIFY_REG(RTCx->CALR, RTC_CALR_CALM, CalibMinus); +} + +/** + * @brief Get Calibration minus + * @rmtoll RTC_CALR CALM LL_RTC_CAL_GetMinus + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x00 and Max_Data= 0x1FF + */ +__STATIC_INLINE uint32_t LL_RTC_CAL_GetMinus(const RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->CALR, RTC_CALR_CALM)); +} + +/** + * @brief Enable Calibration Low Power + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @note Bit can be written only when RECALPF is set to 0 + * @rmtoll RTC_CALR LPCAL LL_RTC_CAL_LowPower_Enable + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_CAL_LowPower_Enable(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CALR, RTC_CALR_LPCAL); +} + +/** + * @brief Disable Calibration Low Power + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @note Bit can be written only when RECALPF is set to 0 + * @rmtoll RTC_CALR LPCAL LL_RTC_CAL_LowPower_Disable + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_CAL_LowPower_Disable(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CALR, RTC_CALR_LPCAL); +} + +/** + * @brief Check if Calibration Low Power is enabled or not + * @rmtoll RTC_CALR LPCAL LL_RTC_CAL_LowPower_IsEnabled + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_CAL_LowPower_IsEnabled(const RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->CALR, RTC_CALR_LPCAL) == (RTC_CALR_LPCAL)) ? 1U : 0U); +} + +/** + * @} + */ + +/** @defgroup RTC_LL_EF_FLAG_Management FLAG_Management + * @{ + */ + +/** + * @brief Get Internal Time-stamp flag + * @rmtoll RTC_SR ITSF LL_RTC_IsActiveFlag_ITS + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITS(const RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->SR, RTC_SR_ITSF) == (RTC_SR_ITSF)) ? 1U : 0U); +} + +/** + * @brief Get Recalibration pending Flag + * @rmtoll RTC_ICSR RECALPF LL_RTC_IsActiveFlag_RECALP + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RECALP(const RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->ICSR, RTC_ICSR_RECALPF) == (RTC_ICSR_RECALPF)) ? 1U : 0U); +} + +/** + * @brief Get Time-stamp overflow flag + * @rmtoll RTC_SR TSOVF LL_RTC_IsActiveFlag_TSOV + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSOV(const RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->SR, RTC_SR_TSOVF) == (RTC_SR_TSOVF)) ? 1U : 0U); +} + +/** + * @brief Get Time-stamp flag + * @rmtoll RTC_SR TSF LL_RTC_IsActiveFlag_TS + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TS(const RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->SR, RTC_SR_TSF) == (RTC_SR_TSF)) ? 1U : 0U); +} + +/** + * @brief Get Wakeup timer flag + * @rmtoll RTC_SR WUTF LL_RTC_IsActiveFlag_WUT + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUT(const RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->SR, RTC_SR_WUTF) == (RTC_SR_WUTF)) ? 1U : 0U); +} + +/** + * @brief Get Alarm B flag + * @rmtoll RTC_SR ALRBF LL_RTC_IsActiveFlag_ALRB + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRB(const RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->SR, RTC_SR_ALRBF) == (RTC_SR_ALRBF)) ? 1U : 0U); +} + +/** + * @brief Get Alarm A flag + * @rmtoll RTC_SR ALRAF LL_RTC_IsActiveFlag_ALRA + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRA(const RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->SR, RTC_SR_ALRAF) == (RTC_SR_ALRAF)) ? 1U : 0U); +} + +/** + * @brief Get SSR Underflow flag + * @rmtoll RTC_SR SSRUF LL_RTC_IsActiveFlag_SSRU + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_SSRU(const RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->SR, RTC_SR_SSRUF) == (RTC_SR_SSRUF)) ? 1U : 0U); +} + +/** + * @brief Clear Internal Time-stamp flag + * @rmtoll RTC_SCR CITSF LL_RTC_ClearFlag_ITS + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_ITS(RTC_TypeDef *RTCx) +{ + WRITE_REG(RTCx->SCR, RTC_SCR_CITSF); +} + +/** + * @brief Clear Time-stamp overflow flag + * @rmtoll RTC_SCR CTSOVF LL_RTC_ClearFlag_TSOV + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_TSOV(RTC_TypeDef *RTCx) +{ + WRITE_REG(RTCx->SCR, RTC_SCR_CTSOVF); +} + +/** + * @brief Clear Time-stamp flag + * @rmtoll RTC_SCR CTSF LL_RTC_ClearFlag_TS + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_TS(RTC_TypeDef *RTCx) +{ + WRITE_REG(RTCx->SCR, RTC_SCR_CTSF); +} + +/** + * @brief Clear Wakeup timer flag + * @rmtoll RTC_SCR CWUTF LL_RTC_ClearFlag_WUT + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_WUT(RTC_TypeDef *RTCx) +{ + WRITE_REG(RTCx->SCR, RTC_SCR_CWUTF); +} + +/** + * @brief Clear Alarm B flag + * @rmtoll RTC_SCR CALRBF LL_RTC_ClearFlag_ALRB + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_ALRB(RTC_TypeDef *RTCx) +{ + WRITE_REG(RTCx->SCR, RTC_SCR_CALRBF); +} + +/** + * @brief Clear Alarm A flag + * @rmtoll RTC_SCR CALRAF LL_RTC_ClearFlag_ALRA + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_ALRA(RTC_TypeDef *RTCx) +{ + WRITE_REG(RTCx->SCR, RTC_SCR_CALRAF); +} + +/** + * @brief Clear SSR Underflow flag + * @rmtoll RTC_SCR CSSRUF LL_RTC_ClearFlag_SSRU + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_SSRU(RTC_TypeDef *RTCx) +{ + WRITE_REG(RTCx->SCR, RTC_SCR_CSSRUF); +} + +/** + * @brief Get Initialization flag + * @rmtoll RTC_ICSR INITF LL_RTC_IsActiveFlag_INIT + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INIT(const RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->ICSR, RTC_ICSR_INITF) == (RTC_ICSR_INITF)) ? 1U : 0U); +} + +/** + * @brief Get Registers synchronization flag + * @rmtoll RTC_ICSR RSF LL_RTC_IsActiveFlag_RS + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RS(const RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->ICSR, RTC_ICSR_RSF) == (RTC_ICSR_RSF)) ? 1U : 0U); +} + +/** + * @brief Clear Registers synchronization flag + * @rmtoll RTC_ICSR RSF LL_RTC_ClearFlag_RS + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_RS(RTC_TypeDef *RTCx) +{ + WRITE_REG(RTCx->ICSR, (~((RTC_ICSR_RSF | RTC_ICSR_INIT) & 0x000000FFU) | (RTCx->ICSR & RTC_ICSR_INIT))); +} + +/** + * @brief Get Initialization status flag + * @rmtoll RTC_ICSR INITS LL_RTC_IsActiveFlag_INITS + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INITS(const RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->ICSR, RTC_ICSR_INITS) == (RTC_ICSR_INITS)) ? 1U : 0U); +} + +/** + * @brief Get Shift operation pending flag + * @rmtoll RTC_ICSR SHPF LL_RTC_IsActiveFlag_SHP + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_SHP(const RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->ICSR, RTC_ICSR_SHPF) == (RTC_ICSR_SHPF)) ? 1U : 0U); +} + +/** + * @brief Get Wakeup timer write flag + * @rmtoll RTC_ICSR WUTWF LL_RTC_IsActiveFlag_WUTW + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUTW(const RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->ICSR, RTC_ICSR_WUTWF) == (RTC_ICSR_WUTWF)) ? 1U : 0U); +} + +/** + * @brief Get Alarm A masked flag. + * @rmtoll RTC_MISR ALRAMF LL_RTC_IsActiveFlag_ALRAM + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRAM(const RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->MISR, RTC_MISR_ALRAMF) == (RTC_MISR_ALRAMF)) ? 1U : 0U); +} + +/** + * @brief Get SSR Underflow masked flag. + * @rmtoll RTC_MISR SSRUMF LL_RTC_IsActiveFlag_SSRUM + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_SSRUM(const RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->MISR, RTC_MISR_SSRUMF) == (RTC_MISR_SSRUMF)) ? 1U : 0U); +} + +/** + * @brief Get Alarm B masked flag. + * @rmtoll RTC_MISR ALRBMF LL_RTC_IsActiveFlag_ALRBM + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRBM(const RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->MISR, RTC_MISR_ALRBMF) == (RTC_MISR_ALRBMF)) ? 1U : 0U); +} + +/** + * @brief Get Wakeup timer masked flag. + * @rmtoll RTC_MISR WUTMF LL_RTC_IsActiveFlag_WUTM + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUTM(const RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->MISR, RTC_MISR_WUTMF) == (RTC_MISR_WUTMF)) ? 1U : 0U); +} + +/** + * @brief Get Time-stamp masked flag. + * @rmtoll RTC_MISR TSMF LL_RTC_IsActiveFlag_TSM + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSM(const RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->MISR, RTC_MISR_TSMF) == (RTC_MISR_TSMF)) ? 1U : 0U); +} + +/** + * @brief Get Time-stamp overflow masked flag. + * @rmtoll RTC_MISR TSOVMF LL_RTC_IsActiveFlag_TSOVM + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSOVM(const RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->MISR, RTC_MISR_TSOVMF) == (RTC_MISR_TSOVMF)) ? 1U : 0U); +} + +/** + * @brief Get Internal Time-stamp masked flag. + * @rmtoll RTC_MISR ITSMF LL_RTC_IsActiveFlag_ITSM + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITSM(const RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->MISR, RTC_MISR_ITSMF) == (RTC_MISR_ITSMF)) ? 1U : 0U); +} + +/** + * @brief Get tamper 1 detection flag. + * @rmtoll TAMP_SR TAMP1F LL_RTC_IsActiveFlag_TAMP1 + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP1(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->SR, TAMP_SR_TAMP1F) == (TAMP_SR_TAMP1F)) ? 1U : 0U); +} + +/** + * @brief Get tamper 2 detection flag. + * @rmtoll TAMP_SR TAMP2F LL_RTC_IsActiveFlag_TAMP2 + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP2(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->SR, TAMP_SR_TAMP2F) == (TAMP_SR_TAMP2F)) ? 1U : 0U); +} + +/** + * @brief Get tamper 3 detection flag. + * @rmtoll TAMP_SR TAMP3F LL_RTC_IsActiveFlag_TAMP3 + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP3(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->SR, TAMP_SR_TAMP3F) == (TAMP_SR_TAMP3F)) ? 1U : 0U); +} +/** + * @brief Get internal tamper 3 detection flag. + * @rmtoll TAMP_SR ITAMP3F LL_RTC_IsActiveFlag_ITAMP3 + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP3(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->SR, TAMP_SR_ITAMP3F) == (TAMP_SR_ITAMP3F)) ? 1U : 0U); +} + + +/** + * @brief Get internal tamper 5 detection flag. + * @rmtoll TAMP_SR ITAMP5F LL_RTC_IsActiveFlag_ITAMP5 + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP5(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->SR, TAMP_SR_ITAMP5F) == (TAMP_SR_ITAMP5F)) ? 1U : 0U); +} + +/** + * @brief Get internal tamper 6 detection flag. + * @rmtoll TAMP_SR ITAMP6F LL_RTC_IsActiveFlag_ITAMP6 + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP6(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->SR, TAMP_SR_ITAMP6F) == (TAMP_SR_ITAMP6F)) ? 1U : 0U); +} + +/** + * @brief Get internal tamper 8 detection flag. + * @rmtoll TAMP_SR ITAMP8F LL_RTC_IsActiveFlag_ITAMP8 + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP8(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->SR, TAMP_SR_ITAMP8F) == (TAMP_SR_ITAMP8F)) ? 1U : 0U); +} + +/** + * @brief Get tamper 1 interrupt masked flag. + * @rmtoll TAMP_MISR TAMP1MF LL_RTC_IsActiveFlag_TAMP1M + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP1M(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->MISR, TAMP_MISR_TAMP1MF) == (TAMP_MISR_TAMP1MF)) ? 1U : 0U); +} + +/** + * @brief Get tamper 2 interrupt masked flag. + * @rmtoll TAMP_MISR TAMP2MF LL_RTC_IsActiveFlag_TAMP2M + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP2M(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->MISR, TAMP_MISR_TAMP2MF) == (TAMP_MISR_TAMP2MF)) ? 1U : 0U); +} + +/** + * @brief Get tamper 3 interrupt masked flag. + * @rmtoll TAMP_MISR TAMP3MF LL_RTC_IsActiveFlag_TAMP3M + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP3M(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->MISR, TAMP_MISR_TAMP3MF) == (TAMP_MISR_TAMP3MF)) ? 1U : 0U); +} + +/** + * @brief Get internal tamper 3 interrupt masked flag. + * @rmtoll TAMP_MISR ITAMP3MF LL_RTC_IsActiveFlag_ITAMP3M + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP3M(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->MISR, TAMP_MISR_ITAMP3MF) == (TAMP_MISR_ITAMP3MF)) ? 1U : 0U); +} + +/** + * @brief Get internal tamper 5 interrupt masked flag. + * @rmtoll TAMP_MISR ITAMP5MF LL_RTC_IsActiveFlag_ITAMP5M + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP5M(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->MISR, TAMP_MISR_ITAMP5MF) == (TAMP_MISR_ITAMP5MF)) ? 1U : 0U); +} + +/** + * @brief Get internal tamper 6 interrupt masked flag. + * @rmtoll TAMP_MISR ITAMP6MF LL_RTC_IsActiveFlag_ITAMP6M + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP6M(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->MISR, TAMP_MISR_ITAMP6MF) == (TAMP_MISR_ITAMP6MF)) ? 1U : 0U); +} + +/** + * @brief Get internal tamper 8 interrupt masked flag. + * @rmtoll TAMP_MISR ITAMP8MF LL_RTC_IsActiveFlag_ITAMP8M + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP8M(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->MISR, TAMP_MISR_ITAMP8MF) == (TAMP_MISR_ITAMP8MF)) ? 1U : 0U); +} + +/** + * @brief Clear tamper 1 detection flag. + * @rmtoll TAMP_SCR CTAMP1F LL_RTC_ClearFlag_TAMP1 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_TAMP1(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + WRITE_REG(TAMP->SCR, TAMP_SCR_CTAMP1F); +} + +/** + * @brief Clear tamper 2 detection flag. + * @rmtoll TAMP_SCR CTAMP2F LL_RTC_ClearFlag_TAMP2 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_TAMP2(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + WRITE_REG(TAMP->SCR, TAMP_SCR_CTAMP2F); +} + +/** + * @brief Clear tamper 3 detection flag. + * @rmtoll TAMP_SCR CTAMP3F LL_RTC_ClearFlag_TAMP3 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_TAMP3(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + WRITE_REG(TAMP->SCR, TAMP_SCR_CTAMP3F); +} + + +/** + * @brief Clear internal tamper 3 detection flag. + * @rmtoll TAMP_SCR CITAMP3F LL_RTC_ClearFlag_ITAMP3 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_ITAMP3(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + WRITE_REG(TAMP->SCR, TAMP_SCR_CITAMP3F); +} + +/** + * @brief Clear internal tamper 5 detection flag. + * @rmtoll TAMP_SCR CITAMP5F LL_RTC_ClearFlag_ITAMP5 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_ITAMP5(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + WRITE_REG(TAMP->SCR, TAMP_SCR_CITAMP5F); +} + +/** + * @brief Clear internal tamper 6 detection flag. + * @rmtoll TAMP_SCR CITAMP6F LL_RTC_ClearFlag_ITAMP6 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_ITAMP6(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + WRITE_REG(TAMP->SCR, TAMP_SCR_CITAMP6F); +} + +/** + * @brief Clear internal tamper 8 detection flag. + * @rmtoll TAMP_SCR CITAMP8F LL_RTC_ClearFlag_ITAMP8 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_ITAMP8(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + WRITE_REG(TAMP->SCR, TAMP_SCR_CITAMP8F); +} + +/** + * @} + */ + +/** @defgroup RTC_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable Time-stamp interrupt + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR TSIE LL_RTC_EnableIT_TS + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableIT_TS(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CR, RTC_CR_TSIE); +} + +/** + * @brief Disable Time-stamp interrupt + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR TSIE LL_RTC_DisableIT_TS + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableIT_TS(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CR, RTC_CR_TSIE); +} + +/** + * @brief Enable Wakeup timer interrupt + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR WUTIE LL_RTC_EnableIT_WUT + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableIT_WUT(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CR, RTC_CR_WUTIE); +} + +/** + * @brief Disable Wakeup timer interrupt + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR WUTIE LL_RTC_DisableIT_WUT + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableIT_WUT(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CR, RTC_CR_WUTIE); +} + +/** + * @brief Enable Alarm B interrupt + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR ALRBIE LL_RTC_EnableIT_ALRB + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableIT_ALRB(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CR, RTC_CR_ALRBIE); +} + +/** + * @brief Disable Alarm B interrupt + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR ALRBIE LL_RTC_DisableIT_ALRB + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableIT_ALRB(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CR, RTC_CR_ALRBIE); +} + +/** + * @brief Enable Alarm A interrupt + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR ALRAIE LL_RTC_EnableIT_ALRA + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableIT_ALRA(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CR, RTC_CR_ALRAIE); +} + +/** + * @brief Disable Alarm A interrupt + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR ALRAIE LL_RTC_DisableIT_ALRA + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableIT_ALRA(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CR, RTC_CR_ALRAIE); +} + +/** + * @brief Enable SSR Underflow interrupt + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR SSRUIE LL_RTC_EnableIT_SSRU + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableIT_SSRU(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CR, RTC_CR_SSRUIE); +} + +/** + * @brief Disable SSR Underflow interrupt + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR SSRUIE LL_RTC_DisableIT_SSRU + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableIT_SSRU(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CR, RTC_CR_SSRUIE); +} + +/** + * @brief Check if Time-stamp interrupt is enabled or not + * @rmtoll RTC_CR TSIE LL_RTC_IsEnabledIT_TS + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TS(const RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->CR, RTC_CR_TSIE) == (RTC_CR_TSIE)) ? 1U : 0U); +} + +/** + * @brief Check if Wakeup timer interrupt is enabled or not + * @rmtoll RTC_CR WUTIE LL_RTC_IsEnabledIT_WUT + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_WUT(const RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->CR, RTC_CR_WUTIE) == (RTC_CR_WUTIE)) ? 1U : 0U); +} + +/** + * @brief Check if Alarm B interrupt is enabled or not + * @rmtoll RTC_CR ALRBIE LL_RTC_IsEnabledIT_ALRB + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRB(const RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->CR, RTC_CR_ALRBIE) == (RTC_CR_ALRBIE)) ? 1U : 0U); +} + +/** + * @brief Check if Alarm A interrupt is enabled or not + * @rmtoll RTC_CR ALRAIE LL_RTC_IsEnabledIT_ALRA + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRA(const RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->CR, RTC_CR_ALRAIE) == (RTC_CR_ALRAIE)) ? 1U : 0U); +} + +/** + * @brief Check if SSR Underflow interrupt is enabled or not + * @rmtoll RTC_CR SSRUIE LL_RTC_IsEnabledIT_SSRU + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_SSRU(const RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->CR, RTC_CR_SSRUIE) == (RTC_CR_SSRUIE)) ? 1U : 0U); +} + +/** + * @brief Enable tamper 1 interrupt. + * @rmtoll TAMP_IER TAMP1IE LL_RTC_EnableIT_TAMP1 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableIT_TAMP1(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + SET_BIT(TAMP->IER, TAMP_IER_TAMP1IE); +} + +/** + * @brief Disable tamper 1 interrupt. + * @rmtoll TAMP_IER TAMP1IE LL_RTC_DisableIT_TAMP1 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableIT_TAMP1(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + CLEAR_BIT(TAMP->IER, TAMP_IER_TAMP1IE); +} + +/** + * @brief Enable tamper 2 interrupt. + * @rmtoll TAMP_IER TAMP2IE LL_RTC_EnableIT_TAMP2 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableIT_TAMP2(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + SET_BIT(TAMP->IER, TAMP_IER_TAMP2IE); +} + +/** + * @brief Disable tamper 2 interrupt. + * @rmtoll TAMP_IER TAMP2IE LL_RTC_DisableIT_TAMP2 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableIT_TAMP2(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + CLEAR_BIT(TAMP->IER, TAMP_IER_TAMP2IE); +} + +/** + * @brief Enable tamper 3 interrupt. + * @rmtoll TAMP_IER TAMP3IE LL_RTC_EnableIT_TAMP3 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableIT_TAMP3(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + SET_BIT(TAMP->IER, TAMP_IER_TAMP3IE); +} +/** + * @brief Disable tamper 3 interrupt. + * @rmtoll TAMP_IER TAMP3IE LL_RTC_DisableIT_TAMP3 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableIT_TAMP3(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + CLEAR_BIT(TAMP->IER, TAMP_IER_TAMP3IE); +} + +/** + * @brief Enable internal tamper 3 interrupt. + * @rmtoll TAMP_IER ITAMP3IE LL_RTC_EnableIT_ITAMP3 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableIT_ITAMP3(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + SET_BIT(TAMP->IER, TAMP_IER_ITAMP3IE); +} +/** + * @brief Disable internal tamper 3 interrupt. + * @rmtoll TAMP_IER ITAMP3IE LL_RTC_DisableIT_ITAMP3 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableIT_ITAMP3(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + CLEAR_BIT(TAMP->IER, TAMP_IER_ITAMP3IE); +} + +/** + * @brief Enable internal tamper 5 interrupt. + * @rmtoll TAMP_IER ITAMP5IE LL_RTC_EnableIT_ITAMP5 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableIT_ITAMP5(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + SET_BIT(TAMP->IER, TAMP_IER_ITAMP5IE); +} +/** + * @brief Disable internal tamper 5 interrupt. + * @rmtoll TAMP_IER ITAMP5IE LL_RTC_DisableIT_ITAMP5 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableIT_ITAMP5(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + CLEAR_BIT(TAMP->IER, TAMP_IER_ITAMP5IE); +} + +/** + * @brief Enable internal tamper 6 interrupt. + * @rmtoll TAMP_IER ITAMP6IE LL_RTC_EnableIT_ITAMP6 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableIT_ITAMP6(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + SET_BIT(TAMP->IER, TAMP_IER_ITAMP6IE); +} + +/** + * @brief Disable internal tamper 6 interrupt. + * @rmtoll TAMP_IER TAMP6IE LL_RTC_DisableIT_ITAMP6 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableIT_ITAMP6(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + CLEAR_BIT(TAMP->IER, TAMP_IER_ITAMP6IE); +} + +/** + * @brief Enable internal tamper 8 interrupt. + * @rmtoll TAMP_IER ITAMP8IE LL_RTC_EnableIT_ITAMP8 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableIT_ITAMP8(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + SET_BIT(TAMP->IER, TAMP_IER_ITAMP8IE); +} + +/** + * @brief Disable internal tamper 8 interrupt. + * @rmtoll TAMP_IER TAMP8IE LL_RTC_DisableIT_ITAMP8 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableIT_ITAMP8(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + CLEAR_BIT(TAMP->IER, TAMP_IER_ITAMP8IE); +} + +/** + * @brief Check if tamper 1 interrupt is enabled or not. + * @rmtoll TAMP_IER TAMP1IE LL_RTC_IsEnabledIT_TAMP1 + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP1(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->IER, TAMP_IER_TAMP1IE) == (TAMP_IER_TAMP1IE)) ? 1U : 0U); +} + +/** + * @brief Check if tamper 2 interrupt is enabled or not. + * @rmtoll TAMP_IER TAMP2IE LL_RTC_IsEnabledIT_TAMP2 + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP2(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->IER, TAMP_IER_TAMP2IE) == (TAMP_IER_TAMP2IE)) ? 1U : 0U); +} + +/** + * @brief Check if tamper 3 interrupt is enabled or not. + * @rmtoll TAMP_IER TAMP3IE LL_RTC_IsEnabledIT_TAMP3 + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP3(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->IER, TAMP_IER_TAMP3IE) == (TAMP_IER_TAMP3IE)) ? 1U : 0U); +} + +/** + * @brief Check if internal tamper 3 interrupt is enabled or not. + * @rmtoll TAMP_IER ITAMP3IE LL_RTC_IsEnabledIT_ITAMP3 + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP3(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->IER, TAMP_IER_ITAMP3IE) == (TAMP_IER_ITAMP3IE)) ? 1U : 0U); +} + +/** + * @brief Check if internal tamper 5 interrupt is enabled or not. + * @rmtoll TAMP_IER ITAMP5IE LL_RTC_IsEnabledIT_ITAMP5 + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP5(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->IER, TAMP_IER_ITAMP5IE) == (TAMP_IER_ITAMP5IE)) ? 1U : 0U); +} + +/** + * @brief Check if internal tamper 6 interrupt is enabled or not. + * @rmtoll TAMP_IER ITAMP6IE LL_RTC_IsEnabledIT_ITAMP6 + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP6(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->IER, TAMP_IER_ITAMP6IE) == (TAMP_IER_ITAMP6IE)) ? 1U : 0U); +} + +/** + * @brief Check if internal tamper 8 interrupt is enabled or not. + * @rmtoll TAMP_IER ITAMP8IE LL_RTC_IsEnabledIT_ITAMP8 + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP8(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->IER, TAMP_IER_ITAMP8IE) == (TAMP_IER_ITAMP8IE)) ? 1U : 0U); +} + + +/** + * @brief Increment Monotonic counter. + * @rmtoll TAMP_COUNTR COUNT LL_RTC_IncrementMonotonicCounter + * @param RTCx RTC Instance + * @retval None. + */ +__STATIC_INLINE void LL_RTC_IncrementMonotonicCounter(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + WRITE_REG(TAMP->COUNTR, 0u); +} + +/** + * @brief Increment Monotonic counter. + * @rmtoll TAMP_COUNTR COUNT LL_RTC_GetMonotonicCounter + * @param RTCx RTC Instance + * @retval Monotonic counter value. + */ +__STATIC_INLINE uint32_t LL_RTC_GetMonotonicCounter(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return READ_REG(TAMP->COUNTR); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RTC_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +ErrorStatus LL_RTC_DeInit(RTC_TypeDef *RTCx); +ErrorStatus LL_RTC_Init(RTC_TypeDef *RTCx, LL_RTC_InitTypeDef *RTC_InitStruct); +void LL_RTC_StructInit(LL_RTC_InitTypeDef *RTC_InitStruct); +ErrorStatus LL_RTC_TIME_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_TimeTypeDef *RTC_TimeStruct); +void LL_RTC_TIME_StructInit(LL_RTC_TimeTypeDef *RTC_TimeStruct); +ErrorStatus LL_RTC_DATE_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_DateTypeDef *RTC_DateStruct); +void LL_RTC_DATE_StructInit(LL_RTC_DateTypeDef *RTC_DateStruct); +ErrorStatus LL_RTC_ALMA_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct); +ErrorStatus LL_RTC_ALMB_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct); +void LL_RTC_ALMA_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct); +void LL_RTC_ALMB_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct); +ErrorStatus LL_RTC_EnterInitMode(RTC_TypeDef *RTCx); +ErrorStatus LL_RTC_ExitInitMode(RTC_TypeDef *RTCx); +ErrorStatus LL_RTC_WaitForSynchro(RTC_TypeDef *RTCx); + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(RTC) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32WLxx_LL_RTC_H */ diff --git a/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h b/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h new file mode 100644 index 0000000..f943cc0 --- /dev/null +++ b/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h @@ -0,0 +1,2297 @@ +/** + ****************************************************************************** + * @file stm32wlxx_ll_spi.h + * @author MCD Application Team + * @brief Header file of SPI LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32WLxx_LL_SPI_H +#define STM32WLxx_LL_SPI_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wlxx.h" + +/** @addtogroup STM32WLxx_LL_Driver + * @{ + */ + +#if defined (SPI1) || defined (SPI2) + +/** @defgroup SPI_LL SPI + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup SPI_LL_ES_INIT SPI Exported Init structure + * @{ + */ + +/** + * @brief SPI Init structures definition + */ +typedef struct +{ + uint32_t TransferDirection; /*!< Specifies the SPI unidirectional or bidirectional data mode. + This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE. + + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetTransferDirection().*/ + + uint32_t Mode; /*!< Specifies the SPI mode (Master/Slave). + This parameter can be a value of @ref SPI_LL_EC_MODE. + + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetMode().*/ + + uint32_t DataWidth; /*!< Specifies the SPI data width. + This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH. + + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetDataWidth().*/ + + uint32_t ClockPolarity; /*!< Specifies the serial clock steady state. + This parameter can be a value of @ref SPI_LL_EC_POLARITY. + + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetClockPolarity().*/ + + uint32_t ClockPhase; /*!< Specifies the clock active edge for the bit capture. + This parameter can be a value of @ref SPI_LL_EC_PHASE. + + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetClockPhase().*/ + + uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) + or by software using the SSI bit. + This parameter can be a value of @ref SPI_LL_EC_NSS_MODE. + + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetNSSMode().*/ + + uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used + to configure the transmit and receive SCK clock. + This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPRESCALER. + @note The communication clock is derived from the master clock. + The slave clock does not need to be set. + + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetBaudRatePrescaler().*/ + + uint32_t BitOrder; /*!< Specifies whether data transfers start from MSB or LSB bit. + This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER. + + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetTransferBitOrder().*/ + + uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not. + This parameter can be a value of @ref SPI_LL_EC_CRC_CALCULATION. + + This feature can be modified afterwards using unitary + functions @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/ + + uint32_t CRCPoly; /*!< Specifies the polynomial used for the CRC calculation. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF. + + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetCRCPolynomial().*/ + +} LL_SPI_InitTypeDef; + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup SPI_LL_Exported_Constants SPI Exported Constants + * @{ + */ + +/** @defgroup SPI_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_SPI_ReadReg function + * @{ + */ +#define LL_SPI_SR_RXNE SPI_SR_RXNE /*!< Rx buffer not empty flag */ +#define LL_SPI_SR_TXE SPI_SR_TXE /*!< Tx buffer empty flag */ +#define LL_SPI_SR_BSY SPI_SR_BSY /*!< Busy flag */ +#define LL_SPI_SR_CRCERR SPI_SR_CRCERR /*!< CRC error flag */ +#define LL_SPI_SR_MODF SPI_SR_MODF /*!< Mode fault flag */ +#define LL_SPI_SR_OVR SPI_SR_OVR /*!< Overrun flag */ +#define LL_SPI_SR_FRE SPI_SR_FRE /*!< TI mode frame format error flag */ +/** + * @} + */ + +/** @defgroup SPI_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions + * @{ + */ +#define LL_SPI_CR2_RXNEIE SPI_CR2_RXNEIE /*!< Rx buffer not empty interrupt enable */ +#define LL_SPI_CR2_TXEIE SPI_CR2_TXEIE /*!< Tx buffer empty interrupt enable */ +#define LL_SPI_CR2_ERRIE SPI_CR2_ERRIE /*!< Error interrupt enable */ +/** + * @} + */ + +/** @defgroup SPI_LL_EC_MODE Operation Mode + * @{ + */ +#define LL_SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI) /*!< Master configuration */ +#define LL_SPI_MODE_SLAVE 0x00000000U /*!< Slave configuration */ +/** + * @} + */ + +/** @defgroup SPI_LL_EC_PROTOCOL Serial Protocol + * @{ + */ +#define LL_SPI_PROTOCOL_MOTOROLA 0x00000000U /*!< Motorola mode. Used as default value */ +#define LL_SPI_PROTOCOL_TI (SPI_CR2_FRF) /*!< TI mode */ +/** + * @} + */ + +/** @defgroup SPI_LL_EC_PHASE Clock Phase + * @{ + */ +#define LL_SPI_PHASE_1EDGE 0x00000000U /*!< First clock transition is the first data capture edge */ +#define LL_SPI_PHASE_2EDGE (SPI_CR1_CPHA) /*!< Second clock transition is the first data capture edge */ +/** + * @} + */ + +/** @defgroup SPI_LL_EC_POLARITY Clock Polarity + * @{ + */ +#define LL_SPI_POLARITY_LOW 0x00000000U /*!< Clock to 0 when idle */ +#define LL_SPI_POLARITY_HIGH (SPI_CR1_CPOL) /*!< Clock to 1 when idle */ +/** + * @} + */ + +/** @defgroup SPI_LL_EC_BAUDRATEPRESCALER Baud Rate Prescaler + * @{ + */ +#define LL_SPI_BAUDRATEPRESCALER_DIV2 0x00000000U /*!< BaudRate control equal to fPCLK/2 */ +#define LL_SPI_BAUDRATEPRESCALER_DIV4 (SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/4 */ +#define LL_SPI_BAUDRATEPRESCALER_DIV8 (SPI_CR1_BR_1) /*!< BaudRate control equal to fPCLK/8 */ +#define LL_SPI_BAUDRATEPRESCALER_DIV16 (SPI_CR1_BR_1 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/16 */ +#define LL_SPI_BAUDRATEPRESCALER_DIV32 (SPI_CR1_BR_2) /*!< BaudRate control equal to fPCLK/32 */ +#define LL_SPI_BAUDRATEPRESCALER_DIV64 (SPI_CR1_BR_2 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/64 */ +#define LL_SPI_BAUDRATEPRESCALER_DIV128 (SPI_CR1_BR_2 | SPI_CR1_BR_1) /*!< BaudRate control equal to fPCLK/128 */ +#define LL_SPI_BAUDRATEPRESCALER_DIV256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/256 */ +/** + * @} + */ + +/** @defgroup SPI_LL_EC_BIT_ORDER Transmission Bit Order + * @{ + */ +#define LL_SPI_LSB_FIRST (SPI_CR1_LSBFIRST) /*!< Data is transmitted/received with the LSB first */ +#define LL_SPI_MSB_FIRST 0x00000000U /*!< Data is transmitted/received with the MSB first */ +/** + * @} + */ + +/** @defgroup SPI_LL_EC_TRANSFER_MODE Transfer Mode + * @{ + */ +#define LL_SPI_FULL_DUPLEX 0x00000000U /*!< Full-Duplex mode. Rx and Tx transfer on 2 lines */ +#define LL_SPI_SIMPLEX_RX (SPI_CR1_RXONLY) /*!< Simplex Rx mode. Rx transfer only on 1 line */ +#define LL_SPI_HALF_DUPLEX_RX (SPI_CR1_BIDIMODE) /*!< Half-Duplex Rx mode. Rx transfer on 1 line */ +#define LL_SPI_HALF_DUPLEX_TX (SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE) /*!< Half-Duplex Tx mode. Tx transfer on 1 line */ +/** + * @} + */ + +/** @defgroup SPI_LL_EC_NSS_MODE Slave Select Pin Mode + * @{ + */ +#define LL_SPI_NSS_SOFT (SPI_CR1_SSM) /*!< NSS managed internally. NSS pin not used and free */ +#define LL_SPI_NSS_HARD_INPUT 0x00000000U /*!< NSS pin used in Input. Only used in Master mode */ +#define LL_SPI_NSS_HARD_OUTPUT (((uint32_t)SPI_CR2_SSOE << 16U)) /*!< NSS pin used in Output. Only used in Slave mode as chip select */ +/** + * @} + */ + +/** @defgroup SPI_LL_EC_DATAWIDTH Datawidth + * @{ + */ +#define LL_SPI_DATAWIDTH_4BIT (SPI_CR2_DS_0 | SPI_CR2_DS_1) /*!< Data length for SPI transfer: 4 bits */ +#define LL_SPI_DATAWIDTH_5BIT (SPI_CR2_DS_2) /*!< Data length for SPI transfer: 5 bits */ +#define LL_SPI_DATAWIDTH_6BIT (SPI_CR2_DS_2 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 6 bits */ +#define LL_SPI_DATAWIDTH_7BIT (SPI_CR2_DS_2 | SPI_CR2_DS_1) /*!< Data length for SPI transfer: 7 bits */ +#define LL_SPI_DATAWIDTH_8BIT (SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 8 bits */ +#define LL_SPI_DATAWIDTH_9BIT (SPI_CR2_DS_3) /*!< Data length for SPI transfer: 9 bits */ +#define LL_SPI_DATAWIDTH_10BIT (SPI_CR2_DS_3 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 10 bits */ +#define LL_SPI_DATAWIDTH_11BIT (SPI_CR2_DS_3 | SPI_CR2_DS_1) /*!< Data length for SPI transfer: 11 bits */ +#define LL_SPI_DATAWIDTH_12BIT (SPI_CR2_DS_3 | SPI_CR2_DS_1 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 12 bits */ +#define LL_SPI_DATAWIDTH_13BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2) /*!< Data length for SPI transfer: 13 bits */ +#define LL_SPI_DATAWIDTH_14BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 14 bits */ +#define LL_SPI_DATAWIDTH_15BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_1) /*!< Data length for SPI transfer: 15 bits */ +#define LL_SPI_DATAWIDTH_16BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 16 bits */ +/** + * @} + */ +#if defined(USE_FULL_LL_DRIVER) + +/** @defgroup SPI_LL_EC_CRC_CALCULATION CRC Calculation + * @{ + */ +#define LL_SPI_CRCCALCULATION_DISABLE 0x00000000U /*!< CRC calculation disabled */ +#define LL_SPI_CRCCALCULATION_ENABLE (SPI_CR1_CRCEN) /*!< CRC calculation enabled */ +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** @defgroup SPI_LL_EC_CRC_LENGTH CRC Length + * @{ + */ +#define LL_SPI_CRC_8BIT 0x00000000U /*!< 8-bit CRC length */ +#define LL_SPI_CRC_16BIT (SPI_CR1_CRCL) /*!< 16-bit CRC length */ +/** + * @} + */ + +/** @defgroup SPI_LL_EC_RX_FIFO_TH RX FIFO Threshold + * @{ + */ +#define LL_SPI_RX_FIFO_TH_HALF 0x00000000U /*!< RXNE event is generated if FIFO level is greater than or equal to 1/2 (16-bit) */ +#define LL_SPI_RX_FIFO_TH_QUARTER (SPI_CR2_FRXTH) /*!< RXNE event is generated if FIFO level is greater than or equal to 1/4 (8-bit) */ +/** + * @} + */ + +/** @defgroup SPI_LL_EC_RX_FIFO RX FIFO Level + * @{ + */ +#define LL_SPI_RX_FIFO_EMPTY 0x00000000U /*!< FIFO reception empty */ +#define LL_SPI_RX_FIFO_QUARTER_FULL (SPI_SR_FRLVL_0) /*!< FIFO reception 1/4 */ +#define LL_SPI_RX_FIFO_HALF_FULL (SPI_SR_FRLVL_1) /*!< FIFO reception 1/2 */ +#define LL_SPI_RX_FIFO_FULL (SPI_SR_FRLVL_1 | SPI_SR_FRLVL_0) /*!< FIFO reception full */ +/** + * @} + */ + +/** @defgroup SPI_LL_EC_TX_FIFO TX FIFO Level + * @{ + */ +#define LL_SPI_TX_FIFO_EMPTY 0x00000000U /*!< FIFO transmission empty */ +#define LL_SPI_TX_FIFO_QUARTER_FULL (SPI_SR_FTLVL_0) /*!< FIFO transmission 1/4 */ +#define LL_SPI_TX_FIFO_HALF_FULL (SPI_SR_FTLVL_1) /*!< FIFO transmission 1/2 */ +#define LL_SPI_TX_FIFO_FULL (SPI_SR_FTLVL_1 | SPI_SR_FTLVL_0) /*!< FIFO transmission full */ +/** + * @} + */ + +/** @defgroup SPI_LL_EC_DMA_PARITY DMA Parity + * @{ + */ +#define LL_SPI_DMA_PARITY_EVEN 0x00000000U /*!< Select DMA parity Even */ +#define LL_SPI_DMA_PARITY_ODD 0x00000001U /*!< Select DMA parity Odd */ + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup SPI_LL_Exported_Macros SPI Exported Macros + * @{ + */ + +/** @defgroup SPI_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in SPI register + * @param __INSTANCE__ SPI Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in SPI register + * @param __INSTANCE__ SPI Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup SPI_LL_Exported_Functions SPI Exported Functions + * @{ + */ + +/** @defgroup SPI_LL_EF_Configuration Configuration + * @{ + */ + +/** + * @brief Enable SPI peripheral + * @rmtoll CR1 SPE LL_SPI_Enable + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_Enable(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CR1, SPI_CR1_SPE); +} + +/** + * @brief Disable SPI peripheral + * @note When disabling the SPI, follow the procedure described in the Reference Manual. + * @rmtoll CR1 SPE LL_SPI_Disable + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE); +} + +/** + * @brief Check if SPI peripheral is enabled + * @rmtoll CR1 SPE LL_SPI_IsEnabled + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabled(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE)) ? 1UL : 0UL); +} + +/** + * @brief Set SPI operation mode to Master or Slave + * @note This bit should not be changed when communication is ongoing. + * @rmtoll CR1 MSTR LL_SPI_SetMode\n + * CR1 SSI LL_SPI_SetMode + * @param SPIx SPI Instance + * @param Mode This parameter can be one of the following values: + * @arg @ref LL_SPI_MODE_MASTER + * @arg @ref LL_SPI_MODE_SLAVE + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode) +{ + MODIFY_REG(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI, Mode); +} + +/** + * @brief Get SPI operation mode (Master or Slave) + * @rmtoll CR1 MSTR LL_SPI_GetMode\n + * CR1 SSI LL_SPI_GetMode + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_MODE_MASTER + * @arg @ref LL_SPI_MODE_SLAVE + */ +__STATIC_INLINE uint32_t LL_SPI_GetMode(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI)); +} + +/** + * @brief Set serial protocol used + * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation. + * @rmtoll CR2 FRF LL_SPI_SetStandard + * @param SPIx SPI Instance + * @param Standard This parameter can be one of the following values: + * @arg @ref LL_SPI_PROTOCOL_MOTOROLA + * @arg @ref LL_SPI_PROTOCOL_TI + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard) +{ + MODIFY_REG(SPIx->CR2, SPI_CR2_FRF, Standard); +} + +/** + * @brief Get serial protocol used + * @rmtoll CR2 FRF LL_SPI_GetStandard + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_PROTOCOL_MOTOROLA + * @arg @ref LL_SPI_PROTOCOL_TI + */ +__STATIC_INLINE uint32_t LL_SPI_GetStandard(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRF)); +} + +/** + * @brief Set clock phase + * @note This bit should not be changed when communication is ongoing. + * This bit is not used in SPI TI mode. + * @rmtoll CR1 CPHA LL_SPI_SetClockPhase + * @param SPIx SPI Instance + * @param ClockPhase This parameter can be one of the following values: + * @arg @ref LL_SPI_PHASE_1EDGE + * @arg @ref LL_SPI_PHASE_2EDGE + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase) +{ + MODIFY_REG(SPIx->CR1, SPI_CR1_CPHA, ClockPhase); +} + +/** + * @brief Get clock phase + * @rmtoll CR1 CPHA LL_SPI_GetClockPhase + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_PHASE_1EDGE + * @arg @ref LL_SPI_PHASE_2EDGE + */ +__STATIC_INLINE uint32_t LL_SPI_GetClockPhase(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPHA)); +} + +/** + * @brief Set clock polarity + * @note This bit should not be changed when communication is ongoing. + * This bit is not used in SPI TI mode. + * @rmtoll CR1 CPOL LL_SPI_SetClockPolarity + * @param SPIx SPI Instance + * @param ClockPolarity This parameter can be one of the following values: + * @arg @ref LL_SPI_POLARITY_LOW + * @arg @ref LL_SPI_POLARITY_HIGH + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity) +{ + MODIFY_REG(SPIx->CR1, SPI_CR1_CPOL, ClockPolarity); +} + +/** + * @brief Get clock polarity + * @rmtoll CR1 CPOL LL_SPI_GetClockPolarity + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_POLARITY_LOW + * @arg @ref LL_SPI_POLARITY_HIGH + */ +__STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPOL)); +} + +/** + * @brief Set baud rate prescaler + * @note These bits should not be changed when communication is ongoing. SPI BaudRate = fPCLK/Prescaler. + * @rmtoll CR1 BR LL_SPI_SetBaudRatePrescaler + * @param SPIx SPI Instance + * @param BaudRate This parameter can be one of the following values: + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256 + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t BaudRate) +{ + MODIFY_REG(SPIx->CR1, SPI_CR1_BR, BaudRate); +} + +/** + * @brief Get baud rate prescaler + * @rmtoll CR1 BR LL_SPI_GetBaudRatePrescaler + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256 + */ +__STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_BR)); +} + +/** + * @brief Set transfer bit order + * @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode. + * @rmtoll CR1 LSBFIRST LL_SPI_SetTransferBitOrder + * @param SPIx SPI Instance + * @param BitOrder This parameter can be one of the following values: + * @arg @ref LL_SPI_LSB_FIRST + * @arg @ref LL_SPI_MSB_FIRST + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder) +{ + MODIFY_REG(SPIx->CR1, SPI_CR1_LSBFIRST, BitOrder); +} + +/** + * @brief Get transfer bit order + * @rmtoll CR1 LSBFIRST LL_SPI_GetTransferBitOrder + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_LSB_FIRST + * @arg @ref LL_SPI_MSB_FIRST + */ +__STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_LSBFIRST)); +} + +/** + * @brief Set transfer direction mode + * @note For Half-Duplex mode, Rx Direction is set by default. + * In master mode, the MOSI pin is used and in slave mode, the MISO pin is used for Half-Duplex. + * @rmtoll CR1 RXONLY LL_SPI_SetTransferDirection\n + * CR1 BIDIMODE LL_SPI_SetTransferDirection\n + * CR1 BIDIOE LL_SPI_SetTransferDirection + * @param SPIx SPI Instance + * @param TransferDirection This parameter can be one of the following values: + * @arg @ref LL_SPI_FULL_DUPLEX + * @arg @ref LL_SPI_SIMPLEX_RX + * @arg @ref LL_SPI_HALF_DUPLEX_RX + * @arg @ref LL_SPI_HALF_DUPLEX_TX + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t TransferDirection) +{ + MODIFY_REG(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE, TransferDirection); +} + +/** + * @brief Get transfer direction mode + * @rmtoll CR1 RXONLY LL_SPI_GetTransferDirection\n + * CR1 BIDIMODE LL_SPI_GetTransferDirection\n + * CR1 BIDIOE LL_SPI_GetTransferDirection + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_FULL_DUPLEX + * @arg @ref LL_SPI_SIMPLEX_RX + * @arg @ref LL_SPI_HALF_DUPLEX_RX + * @arg @ref LL_SPI_HALF_DUPLEX_TX + */ +__STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE)); +} + +/** + * @brief Set frame data width + * @rmtoll CR2 DS LL_SPI_SetDataWidth + * @param SPIx SPI Instance + * @param DataWidth This parameter can be one of the following values: + * @arg @ref LL_SPI_DATAWIDTH_4BIT + * @arg @ref LL_SPI_DATAWIDTH_5BIT + * @arg @ref LL_SPI_DATAWIDTH_6BIT + * @arg @ref LL_SPI_DATAWIDTH_7BIT + * @arg @ref LL_SPI_DATAWIDTH_8BIT + * @arg @ref LL_SPI_DATAWIDTH_9BIT + * @arg @ref LL_SPI_DATAWIDTH_10BIT + * @arg @ref LL_SPI_DATAWIDTH_11BIT + * @arg @ref LL_SPI_DATAWIDTH_12BIT + * @arg @ref LL_SPI_DATAWIDTH_13BIT + * @arg @ref LL_SPI_DATAWIDTH_14BIT + * @arg @ref LL_SPI_DATAWIDTH_15BIT + * @arg @ref LL_SPI_DATAWIDTH_16BIT + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth) +{ + MODIFY_REG(SPIx->CR2, SPI_CR2_DS, DataWidth); +} + +/** + * @brief Get frame data width + * @rmtoll CR2 DS LL_SPI_GetDataWidth + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_DATAWIDTH_4BIT + * @arg @ref LL_SPI_DATAWIDTH_5BIT + * @arg @ref LL_SPI_DATAWIDTH_6BIT + * @arg @ref LL_SPI_DATAWIDTH_7BIT + * @arg @ref LL_SPI_DATAWIDTH_8BIT + * @arg @ref LL_SPI_DATAWIDTH_9BIT + * @arg @ref LL_SPI_DATAWIDTH_10BIT + * @arg @ref LL_SPI_DATAWIDTH_11BIT + * @arg @ref LL_SPI_DATAWIDTH_12BIT + * @arg @ref LL_SPI_DATAWIDTH_13BIT + * @arg @ref LL_SPI_DATAWIDTH_14BIT + * @arg @ref LL_SPI_DATAWIDTH_15BIT + * @arg @ref LL_SPI_DATAWIDTH_16BIT + */ +__STATIC_INLINE uint32_t LL_SPI_GetDataWidth(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_DS)); +} + +/** + * @brief Set threshold of RXFIFO that triggers an RXNE event + * @rmtoll CR2 FRXTH LL_SPI_SetRxFIFOThreshold + * @param SPIx SPI Instance + * @param Threshold This parameter can be one of the following values: + * @arg @ref LL_SPI_RX_FIFO_TH_HALF + * @arg @ref LL_SPI_RX_FIFO_TH_QUARTER + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetRxFIFOThreshold(SPI_TypeDef *SPIx, uint32_t Threshold) +{ + MODIFY_REG(SPIx->CR2, SPI_CR2_FRXTH, Threshold); +} + +/** + * @brief Get threshold of RXFIFO that triggers an RXNE event + * @rmtoll CR2 FRXTH LL_SPI_GetRxFIFOThreshold + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_RX_FIFO_TH_HALF + * @arg @ref LL_SPI_RX_FIFO_TH_QUARTER + */ +__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOThreshold(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRXTH)); +} + +/** + * @} + */ + +/** @defgroup SPI_LL_EF_CRC_Management CRC Management + * @{ + */ + +/** + * @brief Enable CRC + * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation. + * @rmtoll CR1 CRCEN LL_SPI_EnableCRC + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableCRC(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CR1, SPI_CR1_CRCEN); +} + +/** + * @brief Disable CRC + * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation. + * @rmtoll CR1 CRCEN LL_SPI_DisableCRC + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CR1, SPI_CR1_CRCEN); +} + +/** + * @brief Check if CRC is enabled + * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation. + * @rmtoll CR1 CRCEN LL_SPI_IsEnabledCRC + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->CR1, SPI_CR1_CRCEN) == (SPI_CR1_CRCEN)) ? 1UL : 0UL); +} + +/** + * @brief Set CRC Length + * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation. + * @rmtoll CR1 CRCL LL_SPI_SetCRCWidth + * @param SPIx SPI Instance + * @param CRCLength This parameter can be one of the following values: + * @arg @ref LL_SPI_CRC_8BIT + * @arg @ref LL_SPI_CRC_16BIT + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetCRCWidth(SPI_TypeDef *SPIx, uint32_t CRCLength) +{ + MODIFY_REG(SPIx->CR1, SPI_CR1_CRCL, CRCLength); +} + +/** + * @brief Get CRC Length + * @rmtoll CR1 CRCL LL_SPI_GetCRCWidth + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_CRC_8BIT + * @arg @ref LL_SPI_CRC_16BIT + */ +__STATIC_INLINE uint32_t LL_SPI_GetCRCWidth(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CRCL)); +} + +/** + * @brief Set CRCNext to transfer CRC on the line + * @note This bit has to be written as soon as the last data is written in the SPIx_DR register. + * @rmtoll CR1 CRCNEXT LL_SPI_SetCRCNext + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetCRCNext(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CR1, SPI_CR1_CRCNEXT); +} + +/** + * @brief Set polynomial for CRC calculation + * @rmtoll CRCPR CRCPOLY LL_SPI_SetCRCPolynomial + * @param SPIx SPI Instance + * @param CRCPoly This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly) +{ + WRITE_REG(SPIx->CRCPR, (uint16_t)CRCPoly); +} + +/** + * @brief Get polynomial for CRC calculation + * @rmtoll CRCPR CRCPOLY LL_SPI_GetCRCPolynomial + * @param SPIx SPI Instance + * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF + */ +__STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_REG(SPIx->CRCPR)); +} + +/** + * @brief Get Rx CRC + * @rmtoll RXCRCR RXCRC LL_SPI_GetRxCRC + * @param SPIx SPI Instance + * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF + */ +__STATIC_INLINE uint32_t LL_SPI_GetRxCRC(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_REG(SPIx->RXCRCR)); +} + +/** + * @brief Get Tx CRC + * @rmtoll TXCRCR TXCRC LL_SPI_GetTxCRC + * @param SPIx SPI Instance + * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF + */ +__STATIC_INLINE uint32_t LL_SPI_GetTxCRC(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_REG(SPIx->TXCRCR)); +} + +/** + * @} + */ + +/** @defgroup SPI_LL_EF_NSS_Management Slave Select Pin Management + * @{ + */ + +/** + * @brief Set NSS mode + * @note LL_SPI_NSS_SOFT Mode is not used in SPI TI mode. + * @rmtoll CR1 SSM LL_SPI_SetNSSMode\n + * @rmtoll CR2 SSOE LL_SPI_SetNSSMode + * @param SPIx SPI Instance + * @param NSS This parameter can be one of the following values: + * @arg @ref LL_SPI_NSS_SOFT + * @arg @ref LL_SPI_NSS_HARD_INPUT + * @arg @ref LL_SPI_NSS_HARD_OUTPUT + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS) +{ + MODIFY_REG(SPIx->CR1, SPI_CR1_SSM, NSS); + MODIFY_REG(SPIx->CR2, SPI_CR2_SSOE, ((uint32_t)(NSS >> 16U))); +} + +/** + * @brief Get NSS mode + * @rmtoll CR1 SSM LL_SPI_GetNSSMode\n + * @rmtoll CR2 SSOE LL_SPI_GetNSSMode + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_NSS_SOFT + * @arg @ref LL_SPI_NSS_HARD_INPUT + * @arg @ref LL_SPI_NSS_HARD_OUTPUT + */ +__STATIC_INLINE uint32_t LL_SPI_GetNSSMode(const SPI_TypeDef *SPIx) +{ + uint32_t Ssm = (READ_BIT(SPIx->CR1, SPI_CR1_SSM)); + uint32_t Ssoe = (READ_BIT(SPIx->CR2, SPI_CR2_SSOE) << 16U); + return (Ssm | Ssoe); +} + +/** + * @brief Enable NSS pulse management + * @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode. + * @rmtoll CR2 NSSP LL_SPI_EnableNSSPulseMgt + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableNSSPulseMgt(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CR2, SPI_CR2_NSSP); +} + +/** + * @brief Disable NSS pulse management + * @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode. + * @rmtoll CR2 NSSP LL_SPI_DisableNSSPulseMgt + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_DisableNSSPulseMgt(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CR2, SPI_CR2_NSSP); +} + +/** + * @brief Check if NSS pulse is enabled + * @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode. + * @rmtoll CR2 NSSP LL_SPI_IsEnabledNSSPulse + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->CR2, SPI_CR2_NSSP) == (SPI_CR2_NSSP)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup SPI_LL_EF_FLAG_Management FLAG Management + * @{ + */ + +/** + * @brief Check if Rx buffer is not empty + * @rmtoll SR RXNE LL_SPI_IsActiveFlag_RXNE + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->SR, SPI_SR_RXNE) == (SPI_SR_RXNE)) ? 1UL : 0UL); +} + +/** + * @brief Check if Tx buffer is empty + * @rmtoll SR TXE LL_SPI_IsActiveFlag_TXE + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->SR, SPI_SR_TXE) == (SPI_SR_TXE)) ? 1UL : 0UL); +} + +/** + * @brief Get CRC error flag + * @rmtoll SR CRCERR LL_SPI_IsActiveFlag_CRCERR + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->SR, SPI_SR_CRCERR) == (SPI_SR_CRCERR)) ? 1UL : 0UL); +} + +/** + * @brief Get mode fault error flag + * @rmtoll SR MODF LL_SPI_IsActiveFlag_MODF + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF)) ? 1UL : 0UL); +} + +/** + * @brief Get overrun error flag + * @rmtoll SR OVR LL_SPI_IsActiveFlag_OVR + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR)) ? 1UL : 0UL); +} + +/** + * @brief Get busy flag + * @note The BSY flag is cleared under any one of the following conditions: + * -When the SPI is correctly disabled + * -When a fault is detected in Master mode (MODF bit set to 1) + * -In Master mode, when it finishes a data transmission and no new data is ready to be + * sent + * -In Slave mode, when the BSY flag is set to '0' for at least one SPI clock cycle between + * each data transfer. + * @rmtoll SR BSY LL_SPI_IsActiveFlag_BSY + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->SR, SPI_SR_BSY) == (SPI_SR_BSY)) ? 1UL : 0UL); +} + +/** + * @brief Get frame format error flag + * @rmtoll SR FRE LL_SPI_IsActiveFlag_FRE + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->SR, SPI_SR_FRE) == (SPI_SR_FRE)) ? 1UL : 0UL); +} + +/** + * @brief Get FIFO reception Level + * @rmtoll SR FRLVL LL_SPI_GetRxFIFOLevel + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_RX_FIFO_EMPTY + * @arg @ref LL_SPI_RX_FIFO_QUARTER_FULL + * @arg @ref LL_SPI_RX_FIFO_HALF_FULL + * @arg @ref LL_SPI_RX_FIFO_FULL + */ +__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOLevel(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FRLVL)); +} + +/** + * @brief Get FIFO Transmission Level + * @rmtoll SR FTLVL LL_SPI_GetTxFIFOLevel + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_TX_FIFO_EMPTY + * @arg @ref LL_SPI_TX_FIFO_QUARTER_FULL + * @arg @ref LL_SPI_TX_FIFO_HALF_FULL + * @arg @ref LL_SPI_TX_FIFO_FULL + */ +__STATIC_INLINE uint32_t LL_SPI_GetTxFIFOLevel(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FTLVL)); +} + +/** + * @brief Clear CRC error flag + * @rmtoll SR CRCERR LL_SPI_ClearFlag_CRCERR + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_ClearFlag_CRCERR(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->SR, SPI_SR_CRCERR); +} + +/** + * @brief Clear mode fault error flag + * @note Clearing this flag is done by a read access to the SPIx_SR + * register followed by a write access to the SPIx_CR1 register + * @rmtoll SR MODF LL_SPI_ClearFlag_MODF + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx) +{ + __IO uint32_t tmpreg_sr; + tmpreg_sr = SPIx->SR; + (void) tmpreg_sr; + CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE); +} + +/** + * @brief Clear overrun error flag + * @note Clearing this flag is done by a read access to the SPIx_DR + * register followed by a read access to the SPIx_SR register + * @rmtoll SR OVR LL_SPI_ClearFlag_OVR + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_ClearFlag_OVR(const SPI_TypeDef *SPIx) +{ + __IO uint32_t tmpreg; + tmpreg = SPIx->DR; + (void) tmpreg; + tmpreg = SPIx->SR; + (void) tmpreg; +} + +/** + * @brief Clear frame format error flag + * @note Clearing this flag is done by reading SPIx_SR register + * @rmtoll SR FRE LL_SPI_ClearFlag_FRE + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_ClearFlag_FRE(const SPI_TypeDef *SPIx) +{ + __IO uint32_t tmpreg; + tmpreg = SPIx->SR; + (void) tmpreg; +} + +/** + * @} + */ + +/** @defgroup SPI_LL_EF_IT_Management Interrupt Management + * @{ + */ + +/** + * @brief Enable error interrupt + * @note This bit controls the generation of an interrupt when an error condition + * occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode). + * @rmtoll CR2 ERRIE LL_SPI_EnableIT_ERR + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableIT_ERR(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CR2, SPI_CR2_ERRIE); +} + +/** + * @brief Enable Rx buffer not empty interrupt + * @rmtoll CR2 RXNEIE LL_SPI_EnableIT_RXNE + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableIT_RXNE(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CR2, SPI_CR2_RXNEIE); +} + +/** + * @brief Enable Tx buffer empty interrupt + * @rmtoll CR2 TXEIE LL_SPI_EnableIT_TXE + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableIT_TXE(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CR2, SPI_CR2_TXEIE); +} + +/** + * @brief Disable error interrupt + * @note This bit controls the generation of an interrupt when an error condition + * occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode). + * @rmtoll CR2 ERRIE LL_SPI_DisableIT_ERR + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_DisableIT_ERR(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CR2, SPI_CR2_ERRIE); +} + +/** + * @brief Disable Rx buffer not empty interrupt + * @rmtoll CR2 RXNEIE LL_SPI_DisableIT_RXNE + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_DisableIT_RXNE(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CR2, SPI_CR2_RXNEIE); +} + +/** + * @brief Disable Tx buffer empty interrupt + * @rmtoll CR2 TXEIE LL_SPI_DisableIT_TXE + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_DisableIT_TXE(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CR2, SPI_CR2_TXEIE); +} + +/** + * @brief Check if error interrupt is enabled + * @rmtoll CR2 ERRIE LL_SPI_IsEnabledIT_ERR + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if Rx buffer not empty interrupt is enabled + * @rmtoll CR2 RXNEIE LL_SPI_IsEnabledIT_RXNE + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->CR2, SPI_CR2_RXNEIE) == (SPI_CR2_RXNEIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if Tx buffer empty interrupt + * @rmtoll CR2 TXEIE LL_SPI_IsEnabledIT_TXE + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->CR2, SPI_CR2_TXEIE) == (SPI_CR2_TXEIE)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup SPI_LL_EF_DMA_Management DMA Management + * @{ + */ + +/** + * @brief Enable DMA Rx + * @rmtoll CR2 RXDMAEN LL_SPI_EnableDMAReq_RX + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableDMAReq_RX(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CR2, SPI_CR2_RXDMAEN); +} + +/** + * @brief Disable DMA Rx + * @rmtoll CR2 RXDMAEN LL_SPI_DisableDMAReq_RX + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CR2, SPI_CR2_RXDMAEN); +} + +/** + * @brief Check if DMA Rx is enabled + * @rmtoll CR2 RXDMAEN LL_SPI_IsEnabledDMAReq_RX + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->CR2, SPI_CR2_RXDMAEN) == (SPI_CR2_RXDMAEN)) ? 1UL : 0UL); +} + +/** + * @brief Enable DMA Tx + * @rmtoll CR2 TXDMAEN LL_SPI_EnableDMAReq_TX + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableDMAReq_TX(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CR2, SPI_CR2_TXDMAEN); +} + +/** + * @brief Disable DMA Tx + * @rmtoll CR2 TXDMAEN LL_SPI_DisableDMAReq_TX + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CR2, SPI_CR2_TXDMAEN); +} + +/** + * @brief Check if DMA Tx is enabled + * @rmtoll CR2 TXDMAEN LL_SPI_IsEnabledDMAReq_TX + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->CR2, SPI_CR2_TXDMAEN) == (SPI_CR2_TXDMAEN)) ? 1UL : 0UL); +} + +/** + * @brief Set parity of Last DMA reception + * @rmtoll CR2 LDMARX LL_SPI_SetDMAParity_RX + * @param SPIx SPI Instance + * @param Parity This parameter can be one of the following values: + * @arg @ref LL_SPI_DMA_PARITY_ODD + * @arg @ref LL_SPI_DMA_PARITY_EVEN + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetDMAParity_RX(SPI_TypeDef *SPIx, uint32_t Parity) +{ + MODIFY_REG(SPIx->CR2, SPI_CR2_LDMARX, (Parity << SPI_CR2_LDMARX_Pos)); +} + +/** + * @brief Get parity configuration for Last DMA reception + * @rmtoll CR2 LDMARX LL_SPI_GetDMAParity_RX + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_DMA_PARITY_ODD + * @arg @ref LL_SPI_DMA_PARITY_EVEN + */ +__STATIC_INLINE uint32_t LL_SPI_GetDMAParity_RX(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMARX) >> SPI_CR2_LDMARX_Pos); +} + +/** + * @brief Set parity of Last DMA transmission + * @rmtoll CR2 LDMATX LL_SPI_SetDMAParity_TX + * @param SPIx SPI Instance + * @param Parity This parameter can be one of the following values: + * @arg @ref LL_SPI_DMA_PARITY_ODD + * @arg @ref LL_SPI_DMA_PARITY_EVEN + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetDMAParity_TX(SPI_TypeDef *SPIx, uint32_t Parity) +{ + MODIFY_REG(SPIx->CR2, SPI_CR2_LDMATX, (Parity << SPI_CR2_LDMATX_Pos)); +} + +/** + * @brief Get parity configuration for Last DMA transmission + * @rmtoll CR2 LDMATX LL_SPI_GetDMAParity_TX + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_DMA_PARITY_ODD + * @arg @ref LL_SPI_DMA_PARITY_EVEN + */ +__STATIC_INLINE uint32_t LL_SPI_GetDMAParity_TX(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMATX) >> SPI_CR2_LDMATX_Pos); +} + +/** + * @brief Get the data register address used for DMA transfer + * @rmtoll DR DR LL_SPI_DMA_GetRegAddr + * @param SPIx SPI Instance + * @retval Address of data register + */ +__STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(const SPI_TypeDef *SPIx) +{ + return (uint32_t) &(SPIx->DR); +} + +/** + * @} + */ + +/** @defgroup SPI_LL_EF_DATA_Management DATA Management + * @{ + */ + +/** + * @brief Read 8-Bits in the data register + * @rmtoll DR DR LL_SPI_ReceiveData8 + * @param SPIx SPI Instance + * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFF + */ +__STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx) +{ + return (*((__IO uint8_t *)&SPIx->DR)); +} + +/** + * @brief Read 16-Bits in the data register + * @rmtoll DR DR LL_SPI_ReceiveData16 + * @param SPIx SPI Instance + * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFFFF + */ +__STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx) +{ + return (uint16_t)(READ_REG(SPIx->DR)); +} + +/** + * @brief Write 8-Bits in the data register + * @rmtoll DR DR LL_SPI_TransmitData8 + * @param SPIx SPI Instance + * @param TxData Value between Min_Data=0x00 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData) +{ +#if defined (__GNUC__) + __IO uint8_t *spidr = ((__IO uint8_t *)&SPIx->DR); + *spidr = TxData; +#else + *((__IO uint8_t *)&SPIx->DR) = TxData; +#endif /* __GNUC__ */ +} + +/** + * @brief Write 16-Bits in the data register + * @rmtoll DR DR LL_SPI_TransmitData16 + * @param SPIx SPI Instance + * @param TxData Value between Min_Data=0x00 and Max_Data=0xFFFF + * @retval None + */ +__STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData) +{ +#if defined (__GNUC__) + __IO uint16_t *spidr = ((__IO uint16_t *)&SPIx->DR); + *spidr = TxData; +#else + SPIx->DR = TxData; +#endif /* __GNUC__ */ +} + +/** + * @} + */ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup SPI_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +ErrorStatus LL_SPI_DeInit(const SPI_TypeDef *SPIx); +ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct); +void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct); + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup I2S_LL I2S + * @{ + */ + +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup I2S_LL_ES_INIT I2S Exported Init structure + * @{ + */ + +/** + * @brief I2S Init structure definition + */ + +typedef struct +{ + uint32_t Mode; /*!< Specifies the I2S operating mode. + This parameter can be a value of @ref I2S_LL_EC_MODE + + This feature can be modified afterwards using unitary function @ref LL_I2S_SetTransferMode().*/ + + uint32_t Standard; /*!< Specifies the standard used for the I2S communication. + This parameter can be a value of @ref I2S_LL_EC_STANDARD + + This feature can be modified afterwards using unitary function @ref LL_I2S_SetStandard().*/ + + + uint32_t DataFormat; /*!< Specifies the data format for the I2S communication. + This parameter can be a value of @ref I2S_LL_EC_DATA_FORMAT + + This feature can be modified afterwards using unitary function @ref LL_I2S_SetDataFormat().*/ + + + uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not. + This parameter can be a value of @ref I2S_LL_EC_MCLK_OUTPUT + + This feature can be modified afterwards using unitary functions @ref LL_I2S_EnableMasterClock() or @ref LL_I2S_DisableMasterClock.*/ + + + uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication. + This parameter can be a value of @ref I2S_LL_EC_AUDIO_FREQ + + Audio Frequency can be modified afterwards using Reference manual formulas to calculate Prescaler Linear, Parity + and unitary functions @ref LL_I2S_SetPrescalerLinear() and @ref LL_I2S_SetPrescalerParity() to set it.*/ + + + uint32_t ClockPolarity; /*!< Specifies the idle state of the I2S clock. + This parameter can be a value of @ref I2S_LL_EC_POLARITY + + This feature can be modified afterwards using unitary function @ref LL_I2S_SetClockPolarity().*/ + +} LL_I2S_InitTypeDef; + +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup I2S_LL_Exported_Constants I2S Exported Constants + * @{ + */ + +/** @defgroup I2S_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_I2S_ReadReg function + * @{ + */ +#define LL_I2S_SR_RXNE LL_SPI_SR_RXNE /*!< Rx buffer not empty flag */ +#define LL_I2S_SR_TXE LL_SPI_SR_TXE /*!< Tx buffer empty flag */ +#define LL_I2S_SR_BSY LL_SPI_SR_BSY /*!< Busy flag */ +#define LL_I2S_SR_UDR SPI_SR_UDR /*!< Underrun flag */ +#define LL_I2S_SR_OVR LL_SPI_SR_OVR /*!< Overrun flag */ +#define LL_I2S_SR_FRE LL_SPI_SR_FRE /*!< TI mode frame format error flag */ +/** + * @} + */ + +/** @defgroup SPI_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions + * @{ + */ +#define LL_I2S_CR2_RXNEIE LL_SPI_CR2_RXNEIE /*!< Rx buffer not empty interrupt enable */ +#define LL_I2S_CR2_TXEIE LL_SPI_CR2_TXEIE /*!< Tx buffer empty interrupt enable */ +#define LL_I2S_CR2_ERRIE LL_SPI_CR2_ERRIE /*!< Error interrupt enable */ +/** + * @} + */ + +/** @defgroup I2S_LL_EC_DATA_FORMAT Data format + * @{ + */ +#define LL_I2S_DATAFORMAT_16B 0x00000000U /*!< Data length 16 bits, Channel length 16bit */ +#define LL_I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN) /*!< Data length 16 bits, Channel length 32bit */ +#define LL_I2S_DATAFORMAT_24B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0) /*!< Data length 24 bits, Channel length 32bit */ +#define LL_I2S_DATAFORMAT_32B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1) /*!< Data length 16 bits, Channel length 32bit */ +/** + * @} + */ + +/** @defgroup I2S_LL_EC_POLARITY Clock Polarity + * @{ + */ +#define LL_I2S_POLARITY_LOW 0x00000000U /*!< Clock steady state is low level */ +#define LL_I2S_POLARITY_HIGH (SPI_I2SCFGR_CKPOL) /*!< Clock steady state is high level */ +/** + * @} + */ + +/** @defgroup I2S_LL_EC_STANDARD I2s Standard + * @{ + */ +#define LL_I2S_STANDARD_PHILIPS 0x00000000U /*!< I2S standard philips */ +#define LL_I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0) /*!< MSB justified standard (left justified) */ +#define LL_I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1) /*!< LSB justified standard (right justified) */ +#define LL_I2S_STANDARD_PCM_SHORT (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1) /*!< PCM standard, short frame synchronization */ +#define LL_I2S_STANDARD_PCM_LONG (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC) /*!< PCM standard, long frame synchronization */ +/** + * @} + */ + +/** @defgroup I2S_LL_EC_MODE Operation Mode + * @{ + */ +#define LL_I2S_MODE_SLAVE_TX 0x00000000U /*!< Slave Tx configuration */ +#define LL_I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0) /*!< Slave Rx configuration */ +#define LL_I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1) /*!< Master Tx configuration */ +#define LL_I2S_MODE_MASTER_RX (SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1) /*!< Master Rx configuration */ +/** + * @} + */ + +/** @defgroup I2S_LL_EC_PRESCALER_FACTOR Prescaler Factor + * @{ + */ +#define LL_I2S_PRESCALER_PARITY_EVEN 0x00000000U /*!< Odd factor: Real divider value is = I2SDIV * 2 */ +#define LL_I2S_PRESCALER_PARITY_ODD (SPI_I2SPR_ODD >> 8U) /*!< Odd factor: Real divider value is = (I2SDIV * 2)+1 */ +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) + +/** @defgroup I2S_LL_EC_MCLK_OUTPUT MCLK Output + * @{ + */ +#define LL_I2S_MCLK_OUTPUT_DISABLE 0x00000000U /*!< Master clock output is disabled */ +#define LL_I2S_MCLK_OUTPUT_ENABLE (SPI_I2SPR_MCKOE) /*!< Master clock output is enabled */ +/** + * @} + */ + +/** @defgroup I2S_LL_EC_AUDIO_FREQ Audio Frequency + * @{ + */ + +#define LL_I2S_AUDIOFREQ_192K 192000U /*!< Audio Frequency configuration 192000 Hz */ +#define LL_I2S_AUDIOFREQ_96K 96000U /*!< Audio Frequency configuration 96000 Hz */ +#define LL_I2S_AUDIOFREQ_48K 48000U /*!< Audio Frequency configuration 48000 Hz */ +#define LL_I2S_AUDIOFREQ_44K 44100U /*!< Audio Frequency configuration 44100 Hz */ +#define LL_I2S_AUDIOFREQ_32K 32000U /*!< Audio Frequency configuration 32000 Hz */ +#define LL_I2S_AUDIOFREQ_22K 22050U /*!< Audio Frequency configuration 22050 Hz */ +#define LL_I2S_AUDIOFREQ_16K 16000U /*!< Audio Frequency configuration 16000 Hz */ +#define LL_I2S_AUDIOFREQ_11K 11025U /*!< Audio Frequency configuration 11025 Hz */ +#define LL_I2S_AUDIOFREQ_8K 8000U /*!< Audio Frequency configuration 8000 Hz */ +#define LL_I2S_AUDIOFREQ_DEFAULT 2U /*!< Audio Freq not specified. Register I2SDIV = 2 */ +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup I2S_LL_Exported_Macros I2S Exported Macros + * @{ + */ + +/** @defgroup I2S_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in I2S register + * @param __INSTANCE__ I2S Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_I2S_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in I2S register + * @param __INSTANCE__ I2S Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_I2S_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup I2S_LL_Exported_Functions I2S Exported Functions + * @{ + */ + +/** @defgroup I2S_LL_EF_Configuration Configuration + * @{ + */ + +/** + * @brief Select I2S mode and Enable I2S peripheral + * @rmtoll I2SCFGR I2SMOD LL_I2S_Enable\n + * I2SCFGR I2SE LL_I2S_Enable + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_Enable(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SE); +} + +/** + * @brief Disable I2S peripheral + * @rmtoll I2SCFGR I2SE LL_I2S_Disable + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_Disable(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SE); +} + +/** + * @brief Check if I2S peripheral is enabled + * @rmtoll I2SCFGR I2SE LL_I2S_IsEnabled + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2S_IsEnabled(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SE) == (SPI_I2SCFGR_I2SE)) ? 1UL : 0UL); +} + +/** + * @brief Set I2S data frame length + * @rmtoll I2SCFGR DATLEN LL_I2S_SetDataFormat\n + * I2SCFGR CHLEN LL_I2S_SetDataFormat + * @param SPIx SPI Instance + * @param DataFormat This parameter can be one of the following values: + * @arg @ref LL_I2S_DATAFORMAT_16B + * @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED + * @arg @ref LL_I2S_DATAFORMAT_24B + * @arg @ref LL_I2S_DATAFORMAT_32B + * @retval None + */ +__STATIC_INLINE void LL_I2S_SetDataFormat(SPI_TypeDef *SPIx, uint32_t DataFormat) +{ + MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN, DataFormat); +} + +/** + * @brief Get I2S data frame length + * @rmtoll I2SCFGR DATLEN LL_I2S_GetDataFormat\n + * I2SCFGR CHLEN LL_I2S_GetDataFormat + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_I2S_DATAFORMAT_16B + * @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED + * @arg @ref LL_I2S_DATAFORMAT_24B + * @arg @ref LL_I2S_DATAFORMAT_32B + */ +__STATIC_INLINE uint32_t LL_I2S_GetDataFormat(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)); +} + +/** + * @brief Set I2S clock polarity + * @rmtoll I2SCFGR CKPOL LL_I2S_SetClockPolarity + * @param SPIx SPI Instance + * @param ClockPolarity This parameter can be one of the following values: + * @arg @ref LL_I2S_POLARITY_LOW + * @arg @ref LL_I2S_POLARITY_HIGH + * @retval None + */ +__STATIC_INLINE void LL_I2S_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity) +{ + SET_BIT(SPIx->I2SCFGR, ClockPolarity); +} + +/** + * @brief Get I2S clock polarity + * @rmtoll I2SCFGR CKPOL LL_I2S_GetClockPolarity + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_I2S_POLARITY_LOW + * @arg @ref LL_I2S_POLARITY_HIGH + */ +__STATIC_INLINE uint32_t LL_I2S_GetClockPolarity(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_CKPOL)); +} + +/** + * @brief Set I2S standard protocol + * @rmtoll I2SCFGR I2SSTD LL_I2S_SetStandard\n + * I2SCFGR PCMSYNC LL_I2S_SetStandard + * @param SPIx SPI Instance + * @param Standard This parameter can be one of the following values: + * @arg @ref LL_I2S_STANDARD_PHILIPS + * @arg @ref LL_I2S_STANDARD_MSB + * @arg @ref LL_I2S_STANDARD_LSB + * @arg @ref LL_I2S_STANDARD_PCM_SHORT + * @arg @ref LL_I2S_STANDARD_PCM_LONG + * @retval None + */ +__STATIC_INLINE void LL_I2S_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard) +{ + MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC, Standard); +} + +/** + * @brief Get I2S standard protocol + * @rmtoll I2SCFGR I2SSTD LL_I2S_GetStandard\n + * I2SCFGR PCMSYNC LL_I2S_GetStandard + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_I2S_STANDARD_PHILIPS + * @arg @ref LL_I2S_STANDARD_MSB + * @arg @ref LL_I2S_STANDARD_LSB + * @arg @ref LL_I2S_STANDARD_PCM_SHORT + * @arg @ref LL_I2S_STANDARD_PCM_LONG + */ +__STATIC_INLINE uint32_t LL_I2S_GetStandard(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC)); +} + +/** + * @brief Set I2S transfer mode + * @rmtoll I2SCFGR I2SCFG LL_I2S_SetTransferMode + * @param SPIx SPI Instance + * @param Mode This parameter can be one of the following values: + * @arg @ref LL_I2S_MODE_SLAVE_TX + * @arg @ref LL_I2S_MODE_SLAVE_RX + * @arg @ref LL_I2S_MODE_MASTER_TX + * @arg @ref LL_I2S_MODE_MASTER_RX + * @retval None + */ +__STATIC_INLINE void LL_I2S_SetTransferMode(SPI_TypeDef *SPIx, uint32_t Mode) +{ + MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG, Mode); +} + +/** + * @brief Get I2S transfer mode + * @rmtoll I2SCFGR I2SCFG LL_I2S_GetTransferMode + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_I2S_MODE_SLAVE_TX + * @arg @ref LL_I2S_MODE_SLAVE_RX + * @arg @ref LL_I2S_MODE_MASTER_TX + * @arg @ref LL_I2S_MODE_MASTER_RX + */ +__STATIC_INLINE uint32_t LL_I2S_GetTransferMode(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG)); +} + +/** + * @brief Set I2S linear prescaler + * @rmtoll I2SPR I2SDIV LL_I2S_SetPrescalerLinear + * @param SPIx SPI Instance + * @param PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_I2S_SetPrescalerLinear(SPI_TypeDef *SPIx, uint8_t PrescalerLinear) +{ + MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV, PrescalerLinear); +} + +/** + * @brief Get I2S linear prescaler + * @rmtoll I2SPR I2SDIV LL_I2S_GetPrescalerLinear + * @param SPIx SPI Instance + * @retval PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF + */ +__STATIC_INLINE uint32_t LL_I2S_GetPrescalerLinear(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_I2SDIV)); +} + +/** + * @brief Set I2S parity prescaler + * @rmtoll I2SPR ODD LL_I2S_SetPrescalerParity + * @param SPIx SPI Instance + * @param PrescalerParity This parameter can be one of the following values: + * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN + * @arg @ref LL_I2S_PRESCALER_PARITY_ODD + * @retval None + */ +__STATIC_INLINE void LL_I2S_SetPrescalerParity(SPI_TypeDef *SPIx, uint32_t PrescalerParity) +{ + MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_ODD, PrescalerParity << 8U); +} + +/** + * @brief Get I2S parity prescaler + * @rmtoll I2SPR ODD LL_I2S_GetPrescalerParity + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN + * @arg @ref LL_I2S_PRESCALER_PARITY_ODD + */ +__STATIC_INLINE uint32_t LL_I2S_GetPrescalerParity(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_ODD) >> 8U); +} + +/** + * @brief Enable the master clock output (Pin MCK) + * @rmtoll I2SPR MCKOE LL_I2S_EnableMasterClock + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_EnableMasterClock(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE); +} + +/** + * @brief Disable the master clock output (Pin MCK) + * @rmtoll I2SPR MCKOE LL_I2S_DisableMasterClock + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_DisableMasterClock(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE); +} + +/** + * @brief Check if the master clock output (Pin MCK) is enabled + * @rmtoll I2SPR MCKOE LL_I2S_IsEnabledMasterClock + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE) == (SPI_I2SPR_MCKOE)) ? 1UL : 0UL); +} + +#if defined(SPI_I2SCFGR_ASTRTEN) +/** + * @brief Enable asynchronous start + * @rmtoll I2SCFGR ASTRTEN LL_I2S_EnableAsyncStart + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_EnableAsyncStart(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN); +} + +/** + * @brief Disable asynchronous start + * @rmtoll I2SCFGR ASTRTEN LL_I2S_DisableAsyncStart + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_DisableAsyncStart(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN); +} + +/** + * @brief Check if asynchronous start is enabled + * @rmtoll I2SCFGR ASTRTEN LL_I2S_IsEnabledAsyncStart + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2S_IsEnabledAsyncStart(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN) == (SPI_I2SCFGR_ASTRTEN)) ? 1UL : 0UL); +} +#endif /* SPI_I2SCFGR_ASTRTEN */ + +/** + * @} + */ + +/** @defgroup I2S_LL_EF_FLAG FLAG Management + * @{ + */ + +/** + * @brief Check if Rx buffer is not empty + * @rmtoll SR RXNE LL_I2S_IsActiveFlag_RXNE + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXNE(const SPI_TypeDef *SPIx) +{ + return LL_SPI_IsActiveFlag_RXNE(SPIx); +} + +/** + * @brief Check if Tx buffer is empty + * @rmtoll SR TXE LL_I2S_IsActiveFlag_TXE + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXE(const SPI_TypeDef *SPIx) +{ + return LL_SPI_IsActiveFlag_TXE(SPIx); +} + +/** + * @brief Get busy flag + * @rmtoll SR BSY LL_I2S_IsActiveFlag_BSY + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_BSY(const SPI_TypeDef *SPIx) +{ + return LL_SPI_IsActiveFlag_BSY(SPIx); +} + +/** + * @brief Get overrun error flag + * @rmtoll SR OVR LL_I2S_IsActiveFlag_OVR + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR(const SPI_TypeDef *SPIx) +{ + return LL_SPI_IsActiveFlag_OVR(SPIx); +} + +/** + * @brief Get underrun error flag + * @rmtoll SR UDR LL_I2S_IsActiveFlag_UDR + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->SR, SPI_SR_UDR) == (SPI_SR_UDR)) ? 1UL : 0UL); +} + +/** + * @brief Get frame format error flag + * @rmtoll SR FRE LL_I2S_IsActiveFlag_FRE + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_FRE(const SPI_TypeDef *SPIx) +{ + return LL_SPI_IsActiveFlag_FRE(SPIx); +} + +/** + * @brief Get channel side flag. + * @note 0: Channel Left has to be transmitted or has been received\n + * 1: Channel Right has to be transmitted or has been received\n + * It has no significance in PCM mode. + * @rmtoll SR CHSIDE LL_I2S_IsActiveFlag_CHSIDE + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_CHSIDE(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->SR, SPI_SR_CHSIDE) == (SPI_SR_CHSIDE)) ? 1UL : 0UL); +} + +/** + * @brief Clear overrun error flag + * @rmtoll SR OVR LL_I2S_ClearFlag_OVR + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_ClearFlag_OVR(SPI_TypeDef *SPIx) +{ + LL_SPI_ClearFlag_OVR(SPIx); +} + +/** + * @brief Clear underrun error flag + * @rmtoll SR UDR LL_I2S_ClearFlag_UDR + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_ClearFlag_UDR(const SPI_TypeDef *SPIx) +{ + __IO uint32_t tmpreg; + tmpreg = SPIx->SR; + (void)tmpreg; +} + +/** + * @brief Clear frame format error flag + * @rmtoll SR FRE LL_I2S_ClearFlag_FRE + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_ClearFlag_FRE(const SPI_TypeDef *SPIx) +{ + LL_SPI_ClearFlag_FRE(SPIx); +} + +/** + * @} + */ + +/** @defgroup I2S_LL_EF_IT Interrupt Management + * @{ + */ + +/** + * @brief Enable error IT + * @note This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode). + * @rmtoll CR2 ERRIE LL_I2S_EnableIT_ERR + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_EnableIT_ERR(SPI_TypeDef *SPIx) +{ + LL_SPI_EnableIT_ERR(SPIx); +} + +/** + * @brief Enable Rx buffer not empty IT + * @rmtoll CR2 RXNEIE LL_I2S_EnableIT_RXNE + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_EnableIT_RXNE(SPI_TypeDef *SPIx) +{ + LL_SPI_EnableIT_RXNE(SPIx); +} + +/** + * @brief Enable Tx buffer empty IT + * @rmtoll CR2 TXEIE LL_I2S_EnableIT_TXE + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_EnableIT_TXE(SPI_TypeDef *SPIx) +{ + LL_SPI_EnableIT_TXE(SPIx); +} + +/** + * @brief Disable error IT + * @note This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode). + * @rmtoll CR2 ERRIE LL_I2S_DisableIT_ERR + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_DisableIT_ERR(SPI_TypeDef *SPIx) +{ + LL_SPI_DisableIT_ERR(SPIx); +} + +/** + * @brief Disable Rx buffer not empty IT + * @rmtoll CR2 RXNEIE LL_I2S_DisableIT_RXNE + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_DisableIT_RXNE(SPI_TypeDef *SPIx) +{ + LL_SPI_DisableIT_RXNE(SPIx); +} + +/** + * @brief Disable Tx buffer empty IT + * @rmtoll CR2 TXEIE LL_I2S_DisableIT_TXE + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_DisableIT_TXE(SPI_TypeDef *SPIx) +{ + LL_SPI_DisableIT_TXE(SPIx); +} + +/** + * @brief Check if ERR IT is enabled + * @rmtoll CR2 ERRIE LL_I2S_IsEnabledIT_ERR + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_ERR(const SPI_TypeDef *SPIx) +{ + return LL_SPI_IsEnabledIT_ERR(SPIx); +} + +/** + * @brief Check if RXNE IT is enabled + * @rmtoll CR2 RXNEIE LL_I2S_IsEnabledIT_RXNE + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXNE(const SPI_TypeDef *SPIx) +{ + return LL_SPI_IsEnabledIT_RXNE(SPIx); +} + +/** + * @brief Check if TXE IT is enabled + * @rmtoll CR2 TXEIE LL_I2S_IsEnabledIT_TXE + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_TXE(const SPI_TypeDef *SPIx) +{ + return LL_SPI_IsEnabledIT_TXE(SPIx); +} + +/** + * @} + */ + +/** @defgroup I2S_LL_EF_DMA DMA Management + * @{ + */ + +/** + * @brief Enable DMA Rx + * @rmtoll CR2 RXDMAEN LL_I2S_EnableDMAReq_RX + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_EnableDMAReq_RX(SPI_TypeDef *SPIx) +{ + LL_SPI_EnableDMAReq_RX(SPIx); +} + +/** + * @brief Disable DMA Rx + * @rmtoll CR2 RXDMAEN LL_I2S_DisableDMAReq_RX + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_DisableDMAReq_RX(SPI_TypeDef *SPIx) +{ + LL_SPI_DisableDMAReq_RX(SPIx); +} + +/** + * @brief Check if DMA Rx is enabled + * @rmtoll CR2 RXDMAEN LL_I2S_IsEnabledDMAReq_RX + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_RX(const SPI_TypeDef *SPIx) +{ + return LL_SPI_IsEnabledDMAReq_RX(SPIx); +} + +/** + * @brief Enable DMA Tx + * @rmtoll CR2 TXDMAEN LL_I2S_EnableDMAReq_TX + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_EnableDMAReq_TX(SPI_TypeDef *SPIx) +{ + LL_SPI_EnableDMAReq_TX(SPIx); +} + +/** + * @brief Disable DMA Tx + * @rmtoll CR2 TXDMAEN LL_I2S_DisableDMAReq_TX + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_DisableDMAReq_TX(SPI_TypeDef *SPIx) +{ + LL_SPI_DisableDMAReq_TX(SPIx); +} + +/** + * @brief Check if DMA Tx is enabled + * @rmtoll CR2 TXDMAEN LL_I2S_IsEnabledDMAReq_TX + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_TX(const SPI_TypeDef *SPIx) +{ + return LL_SPI_IsEnabledDMAReq_TX(SPIx); +} + +/** + * @} + */ + +/** @defgroup I2S_LL_EF_DATA DATA Management + * @{ + */ + +/** + * @brief Read 16-Bits in data register + * @rmtoll DR DR LL_I2S_ReceiveData16 + * @param SPIx SPI Instance + * @retval RxData Value between Min_Data=0x0000 and Max_Data=0xFFFF + */ +__STATIC_INLINE uint16_t LL_I2S_ReceiveData16(SPI_TypeDef *SPIx) +{ + return LL_SPI_ReceiveData16(SPIx); +} + +/** + * @brief Write 16-Bits in data register + * @rmtoll DR DR LL_I2S_TransmitData16 + * @param SPIx SPI Instance + * @param TxData Value between Min_Data=0x0000 and Max_Data=0xFFFF + * @retval None + */ +__STATIC_INLINE void LL_I2S_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData) +{ + LL_SPI_TransmitData16(SPIx, TxData); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup I2S_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +ErrorStatus LL_I2S_DeInit(const SPI_TypeDef *SPIx); +ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct); +void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct); +void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity); + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined (SPI1) || defined (SPI2) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32WLxx_LL_SPI_H */ + diff --git a/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h b/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h new file mode 100644 index 0000000..9fcd9a5 --- /dev/null +++ b/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h @@ -0,0 +1,1927 @@ +/** + ****************************************************************************** + * @file stm32wlxx_ll_system.h + * @author MCD Application Team + * @brief Header file of SYSTEM LL module. + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The LL SYSTEM driver contains a set of generic APIs that can be + used by user: + (+) Some of the FLASH features need to be handled in the SYSTEM file. + (+) Access to DBGCMU registers + (+) Access to SYSCFG registers + (+) Access to VREFBUF registers + + @endverbatim + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32WLxx_LL_SYSTEM_H +#define STM32WLxx_LL_SYSTEM_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wlxx.h" + +/** @addtogroup STM32WLxx_LL_Driver + * @{ + */ + +#if defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) || defined (VREFBUF) + +/** @defgroup SYSTEM_LL SYSTEM + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants + * @{ + */ +#define LL_SYSCFG_EXTI_REGISTER_PINPOS_SHFT 16U /*!< Define used to shift pin position in EXTICR register */ + +/** + * @brief VREFBUF VREF_SC0 & VREF_SC1 calibration values + */ +#define VREFBUF_SC0_CAL_ADDR ((uint8_t*) (0x1FFF75F0UL)) /*!< Address of VREFBUF trimming value for VRS=0, + VREF_SC0 in STM32WL datasheet */ +#define VREFBUF_SC1_CAL_ADDR ((uint8_t*) (0x1FFF7530UL)) /*!< Address of VREFBUF trimming value for VRS=1, + VREF_SC1 in STM32WL datasheet */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants + * @{ + */ + +/** @defgroup SYSTEM_LL_EC_REMAP SYSCFG REMAP + * @{ + */ +#define LL_SYSCFG_REMAP_FLASH 0x00000000U /*!< Main Flash memory mapped at 0x00000000 */ +#define LL_SYSCFG_REMAP_SYSTEMFLASH SYSCFG_MEMRMP_MEM_MODE_0 /*!< System Flash memory mapped at 0x00000000 */ +#define LL_SYSCFG_REMAP_SRAM (SYSCFG_MEMRMP_MEM_MODE_1 | SYSCFG_MEMRMP_MEM_MODE_0) /*!< SRAM1 mapped at 0x00000000 */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_I2C_FASTMODEPLUS SYSCFG I2C FASTMODEPLUS + * @{ + */ +#define LL_SYSCFG_I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP /*!< Enable Fast Mode Plus on PB6 */ +#define LL_SYSCFG_I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP /*!< Enable Fast Mode Plus on PB7 */ +#define LL_SYSCFG_I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP /*!< Enable Fast Mode Plus on PB8 */ +#define LL_SYSCFG_I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /*!< Enable Fast Mode Plus on PB9 */ +#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP /*!< Enable Fast Mode Plus on I2C1 pins */ +#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C2_FMP /*!< Enable Fast Mode Plus on I2C2 pins */ +#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 SYSCFG_CFGR1_I2C3_FMP /*!< Enable Fast Mode Plus on I2C3 pins */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_EXTI_PORT SYSCFG EXTI PORT + * @{ + */ +#define LL_SYSCFG_EXTI_PORTA 0U /*!< EXTI PORT A */ +#define LL_SYSCFG_EXTI_PORTB 1U /*!< EXTI PORT B */ +#define LL_SYSCFG_EXTI_PORTC 2U /*!< EXTI PORT C */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_EXTI_LINE SYSCFG EXTI LINE + * @{ + */ +#if defined(CORE_CM0PLUS) +#define LL_SYSCFG_EXTI_LINE0 (uint32_t)((0U << LL_SYSCFG_EXTI_REGISTER_PINPOS_SHFT) | 0U) /*!< EXTI_POSITION_0 | EXTICR[0] */ +#define LL_SYSCFG_EXTI_LINE1 (uint32_t)((4U << LL_SYSCFG_EXTI_REGISTER_PINPOS_SHFT) | 0U) /*!< EXTI_POSITION_4 | EXTICR[0] */ +#define LL_SYSCFG_EXTI_LINE2 (uint32_t)((8U << LL_SYSCFG_EXTI_REGISTER_PINPOS_SHFT) | 0U) /*!< EXTI_POSITION_8 | EXTICR[0] */ +#define LL_SYSCFG_EXTI_LINE3 (uint32_t)((12U << LL_SYSCFG_EXTI_REGISTER_PINPOS_SHFT) | 0U) /*!< EXTI_POSITION_12 | EXTICR[0] */ +#define LL_SYSCFG_EXTI_LINE4 (uint32_t)((0U << LL_SYSCFG_EXTI_REGISTER_PINPOS_SHFT) | 1U) /*!< EXTI_POSITION_0 | EXTICR[1] */ +#define LL_SYSCFG_EXTI_LINE5 (uint32_t)((4U << LL_SYSCFG_EXTI_REGISTER_PINPOS_SHFT) | 1U) /*!< EXTI_POSITION_4 | EXTICR[1] */ +#define LL_SYSCFG_EXTI_LINE6 (uint32_t)((8U << LL_SYSCFG_EXTI_REGISTER_PINPOS_SHFT) | 1U) /*!< EXTI_POSITION_8 | EXTICR[1] */ +#define LL_SYSCFG_EXTI_LINE7 (uint32_t)((12U << LL_SYSCFG_EXTI_REGISTER_PINPOS_SHFT) | 1U) /*!< EXTI_POSITION_12 | EXTICR[1] */ +#define LL_SYSCFG_EXTI_LINE8 (uint32_t)((0U << LL_SYSCFG_EXTI_REGISTER_PINPOS_SHFT) | 2U) /*!< EXTI_POSITION_0 | EXTICR[2] */ +#define LL_SYSCFG_EXTI_LINE9 (uint32_t)((4U << LL_SYSCFG_EXTI_REGISTER_PINPOS_SHFT) | 2U) /*!< EXTI_POSITION_4 | EXTICR[2] */ +#define LL_SYSCFG_EXTI_LINE10 (uint32_t)((8U << LL_SYSCFG_EXTI_REGISTER_PINPOS_SHFT) | 2U) /*!< EXTI_POSITION_8 | EXTICR[2] */ +#define LL_SYSCFG_EXTI_LINE11 (uint32_t)((12U << LL_SYSCFG_EXTI_REGISTER_PINPOS_SHFT) | 2U) /*!< EXTI_POSITION_12 | EXTICR[2] */ +#define LL_SYSCFG_EXTI_LINE12 (uint32_t)((0U << LL_SYSCFG_EXTI_REGISTER_PINPOS_SHFT) | 3U) /*!< EXTI_POSITION_0 | EXTICR[3] */ +#define LL_SYSCFG_EXTI_LINE13 (uint32_t)((4U << LL_SYSCFG_EXTI_REGISTER_PINPOS_SHFT) | 3U) /*!< EXTI_POSITION_4 | EXTICR[3] */ +#define LL_SYSCFG_EXTI_LINE14 (uint32_t)((8U << LL_SYSCFG_EXTI_REGISTER_PINPOS_SHFT) | 3U) /*!< EXTI_POSITION_8 | EXTICR[3] */ +#define LL_SYSCFG_EXTI_LINE15 (uint32_t)((12U << LL_SYSCFG_EXTI_REGISTER_PINPOS_SHFT) | 3U) /*!< EXTI_POSITION_12 | EXTICR[3] */ +#else +#define LL_SYSCFG_EXTI_LINE0 (uint32_t)((0x000FU << LL_SYSCFG_EXTI_REGISTER_PINPOS_SHFT) | 0U) /*!< EXTI_POSITION_0 | EXTICR[0] */ +#define LL_SYSCFG_EXTI_LINE1 (uint32_t)((0x00F0U << LL_SYSCFG_EXTI_REGISTER_PINPOS_SHFT) | 0U) /*!< EXTI_POSITION_4 | EXTICR[0] */ +#define LL_SYSCFG_EXTI_LINE2 (uint32_t)((0x0F00U << LL_SYSCFG_EXTI_REGISTER_PINPOS_SHFT) | 0U) /*!< EXTI_POSITION_8 | EXTICR[0] */ +#define LL_SYSCFG_EXTI_LINE3 (uint32_t)((0xF000U << LL_SYSCFG_EXTI_REGISTER_PINPOS_SHFT) | 0U) /*!< EXTI_POSITION_12 | EXTICR[0] */ +#define LL_SYSCFG_EXTI_LINE4 (uint32_t)((0x000FU << LL_SYSCFG_EXTI_REGISTER_PINPOS_SHFT) | 1U) /*!< EXTI_POSITION_0 | EXTICR[1] */ +#define LL_SYSCFG_EXTI_LINE5 (uint32_t)((0x00F0U << LL_SYSCFG_EXTI_REGISTER_PINPOS_SHFT) | 1U) /*!< EXTI_POSITION_4 | EXTICR[1] */ +#define LL_SYSCFG_EXTI_LINE6 (uint32_t)((0x0F00U << LL_SYSCFG_EXTI_REGISTER_PINPOS_SHFT) | 1U) /*!< EXTI_POSITION_8 | EXTICR[1] */ +#define LL_SYSCFG_EXTI_LINE7 (uint32_t)((0xF000U << LL_SYSCFG_EXTI_REGISTER_PINPOS_SHFT) | 1U) /*!< EXTI_POSITION_12 | EXTICR[1] */ +#define LL_SYSCFG_EXTI_LINE8 (uint32_t)((0x000FU << LL_SYSCFG_EXTI_REGISTER_PINPOS_SHFT) | 2U) /*!< EXTI_POSITION_0 | EXTICR[2] */ +#define LL_SYSCFG_EXTI_LINE9 (uint32_t)((0x00F0U << LL_SYSCFG_EXTI_REGISTER_PINPOS_SHFT) | 2U) /*!< EXTI_POSITION_4 | EXTICR[2] */ +#define LL_SYSCFG_EXTI_LINE10 (uint32_t)((0x0F00U << LL_SYSCFG_EXTI_REGISTER_PINPOS_SHFT) | 2U) /*!< EXTI_POSITION_8 | EXTICR[2] */ +#define LL_SYSCFG_EXTI_LINE11 (uint32_t)((0xF000U << LL_SYSCFG_EXTI_REGISTER_PINPOS_SHFT) | 2U) /*!< EXTI_POSITION_12 | EXTICR[2] */ +#define LL_SYSCFG_EXTI_LINE12 (uint32_t)((0x000FU << LL_SYSCFG_EXTI_REGISTER_PINPOS_SHFT) | 3U) /*!< EXTI_POSITION_0 | EXTICR[3] */ +#define LL_SYSCFG_EXTI_LINE13 (uint32_t)((0x00F0U << LL_SYSCFG_EXTI_REGISTER_PINPOS_SHFT) | 3U) /*!< EXTI_POSITION_4 | EXTICR[3] */ +#define LL_SYSCFG_EXTI_LINE14 (uint32_t)((0x0F00U << LL_SYSCFG_EXTI_REGISTER_PINPOS_SHFT) | 3U) /*!< EXTI_POSITION_8 | EXTICR[3] */ +#define LL_SYSCFG_EXTI_LINE15 (uint32_t)((0xF000U << LL_SYSCFG_EXTI_REGISTER_PINPOS_SHFT) | 3U) /*!< EXTI_POSITION_12 | EXTICR[3] */ +#endif +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_TIMBREAK SYSCFG TIMER BREAK + * @{ + */ +#define LL_SYSCFG_TIMBREAK_ECC SYSCFG_CFGR2_ECCL /*!< Enables and locks the ECC error signal + with Break Input of TIM1/16/17 */ +#define LL_SYSCFG_TIMBREAK_PVD SYSCFG_CFGR2_PVDL /*!< Enables and locks the PVD connection + with TIM1/16/17 Break Input + and also the PVDE and PLS bits of the Power Control Interface */ +#define LL_SYSCFG_TIMBREAK_SRAM2_PARITY SYSCFG_CFGR2_SPL /*!< Enables and locks the SRAM2_PARITY error signal + with Break Input of TIM1/16/17 */ +#define LL_SYSCFG_TIMBREAK_LOCKUP SYSCFG_CFGR2_CLL /*!< Enables and locks the LOCKUP output of CortexM4 + with Break Input of TIM1/16/17 */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_SRAM2WRP SYSCFG SRAM2 WRITE PROTECTION + * @{ + */ +#define LL_SYSCFG_SRAM2WRP_PAGE0 SYSCFG_SWPR_PAGE0 /*!< SRAM2 Write protection page 0 */ +#define LL_SYSCFG_SRAM2WRP_PAGE1 SYSCFG_SWPR_PAGE1 /*!< SRAM2 Write protection page 1 */ +#define LL_SYSCFG_SRAM2WRP_PAGE2 SYSCFG_SWPR_PAGE2 /*!< SRAM2 Write protection page 2 */ +#define LL_SYSCFG_SRAM2WRP_PAGE3 SYSCFG_SWPR_PAGE3 /*!< SRAM2 Write protection page 3 */ +#define LL_SYSCFG_SRAM2WRP_PAGE4 SYSCFG_SWPR_PAGE4 /*!< SRAM2 Write protection page 4 */ +#define LL_SYSCFG_SRAM2WRP_PAGE5 SYSCFG_SWPR_PAGE5 /*!< SRAM2 Write protection page 5 */ +#define LL_SYSCFG_SRAM2WRP_PAGE6 SYSCFG_SWPR_PAGE6 /*!< SRAM2 Write protection page 6 */ +#define LL_SYSCFG_SRAM2WRP_PAGE7 SYSCFG_SWPR_PAGE7 /*!< SRAM2 Write protection page 7 */ +#define LL_SYSCFG_SRAM2WRP_PAGE8 SYSCFG_SWPR_PAGE8 /*!< SRAM2 Write protection page 8 */ +#define LL_SYSCFG_SRAM2WRP_PAGE9 SYSCFG_SWPR_PAGE9 /*!< SRAM2 Write protection page 9 */ +#define LL_SYSCFG_SRAM2WRP_PAGE10 SYSCFG_SWPR_PAGE10 /*!< SRAM2 Write protection page 10 */ +#define LL_SYSCFG_SRAM2WRP_PAGE11 SYSCFG_SWPR_PAGE11 /*!< SRAM2 Write protection page 11 */ +#define LL_SYSCFG_SRAM2WRP_PAGE12 SYSCFG_SWPR_PAGE12 /*!< SRAM2 Write protection page 12 */ +#define LL_SYSCFG_SRAM2WRP_PAGE13 SYSCFG_SWPR_PAGE13 /*!< SRAM2 Write protection page 13 */ +#define LL_SYSCFG_SRAM2WRP_PAGE14 SYSCFG_SWPR_PAGE14 /*!< SRAM2 Write protection page 14 */ +#define LL_SYSCFG_SRAM2WRP_PAGE15 SYSCFG_SWPR_PAGE15 /*!< SRAM2 Write protection page 15 */ +#define LL_SYSCFG_SRAM2WRP_PAGE16 SYSCFG_SWPR_PAGE16 /*!< SRAM2 Write protection page 16 */ +#define LL_SYSCFG_SRAM2WRP_PAGE17 SYSCFG_SWPR_PAGE17 /*!< SRAM2 Write protection page 17 */ +#define LL_SYSCFG_SRAM2WRP_PAGE18 SYSCFG_SWPR_PAGE18 /*!< SRAM2 Write protection page 18 */ +#define LL_SYSCFG_SRAM2WRP_PAGE19 SYSCFG_SWPR_PAGE19 /*!< SRAM2 Write protection page 19 */ +#define LL_SYSCFG_SRAM2WRP_PAGE20 SYSCFG_SWPR_PAGE20 /*!< SRAM2 Write protection page 20 */ +#define LL_SYSCFG_SRAM2WRP_PAGE21 SYSCFG_SWPR_PAGE21 /*!< SRAM2 Write protection page 21 */ +#define LL_SYSCFG_SRAM2WRP_PAGE22 SYSCFG_SWPR_PAGE22 /*!< SRAM2 Write protection page 22 */ +#define LL_SYSCFG_SRAM2WRP_PAGE23 SYSCFG_SWPR_PAGE23 /*!< SRAM2 Write protection page 23 */ +#define LL_SYSCFG_SRAM2WRP_PAGE24 SYSCFG_SWPR_PAGE24 /*!< SRAM2 Write protection page 24 */ +#define LL_SYSCFG_SRAM2WRP_PAGE25 SYSCFG_SWPR_PAGE25 /*!< SRAM2 Write protection page 25 */ +#define LL_SYSCFG_SRAM2WRP_PAGE26 SYSCFG_SWPR_PAGE26 /*!< SRAM2 Write protection page 26 */ +#define LL_SYSCFG_SRAM2WRP_PAGE27 SYSCFG_SWPR_PAGE27 /*!< SRAM2 Write protection page 27 */ +#define LL_SYSCFG_SRAM2WRP_PAGE28 SYSCFG_SWPR_PAGE28 /*!< SRAM2 Write protection page 28 */ +#define LL_SYSCFG_SRAM2WRP_PAGE29 SYSCFG_SWPR_PAGE29 /*!< SRAM2 Write protection page 29 */ +#define LL_SYSCFG_SRAM2WRP_PAGE30 SYSCFG_SWPR_PAGE30 /*!< SRAM2 Write protection page 30 */ +#define LL_SYSCFG_SRAM2WRP_PAGE31 SYSCFG_SWPR_PAGE31 /*!< SRAM2 Write protection page 31 */ +/** + * @} + */ + +#if defined(DUAL_CORE) +/** @defgroup SYSTEM_LL_EC_IM SYSCFG CPU1 INTERRUPT MASK + * @{ + */ +#define LL_SYSCFG_GRP1_RTCSTAMPTAMPLSECSS SYSCFG_IMR1_RTCSTAMPTAMPLSECSSIM /*!< Enabling of interrupt from RTCSTAMPTAMPLSECSS to CPU1 */ +#define LL_SYSCFG_GRP1_RTCSSRU SYSCFG_IMR1_RTCSSRUIM /*!< Enabling of interrupt from RTC SSRU to CPU1 */ +#define LL_SYSCFG_GRP1_EXTI5 SYSCFG_IMR1_EXTI5IM /*!< Enabling of interrupt from External Interrupt Line 5 to CPU1 */ +#define LL_SYSCFG_GRP1_EXTI6 SYSCFG_IMR1_EXTI6IM /*!< Enabling of interrupt from External Interrupt Line 6 to CPU1 */ +#define LL_SYSCFG_GRP1_EXTI7 SYSCFG_IMR1_EXTI7IM /*!< Enabling of interrupt from External Interrupt Line 7 to CPU1 */ +#define LL_SYSCFG_GRP1_EXTI8 SYSCFG_IMR1_EXTI8IM /*!< Enabling of interrupt from External Interrupt Line 8 to CPU1 */ +#define LL_SYSCFG_GRP1_EXTI9 SYSCFG_IMR1_EXTI9IM /*!< Enabling of interrupt from External Interrupt Line 9 to CPU1 */ +#define LL_SYSCFG_GRP1_EXTI10 SYSCFG_IMR1_EXTI10IM /*!< Enabling of interrupt from External Interrupt Line 10 to CPU1 */ +#define LL_SYSCFG_GRP1_EXTI11 SYSCFG_IMR1_EXTI11IM /*!< Enabling of interrupt from External Interrupt Line 11 to CPU1 */ +#define LL_SYSCFG_GRP1_EXTI12 SYSCFG_IMR1_EXTI12IM /*!< Enabling of interrupt from External Interrupt Line 12 to CPU1 */ +#define LL_SYSCFG_GRP1_EXTI13 SYSCFG_IMR1_EXTI13IM /*!< Enabling of interrupt from External Interrupt Line 13 to CPU1 */ +#define LL_SYSCFG_GRP1_EXTI14 SYSCFG_IMR1_EXTI14IM /*!< Enabling of interrupt from External Interrupt Line 14 to CPU1 */ +#define LL_SYSCFG_GRP1_EXTI15 SYSCFG_IMR1_EXTI15IM /*!< Enabling of interrupt from External Interrupt Line 15 to CPU1 */ + +#define LL_SYSCFG_GRP2_PVM3 SYSCFG_IMR2_PVM3IM /*!< Enabling of interrupt from Power Voltage Monitoring 3 to CPU1 */ +#define LL_SYSCFG_GRP2_PVD SYSCFG_IMR2_PVDIM /*!< Enabling of interrupt from Power Voltage Detector to CPU1 */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_C2_IM SYSCFG CPU2 INTERRUPT MASK + * @{ + */ +#define LL_C2_SYSCFG_GRP1_RTCSTAMP_RTCTAMP_LSECSS SYSCFG_C2IMR1_RTCSTAMPTAMPLSECSSIM /*!< Enabling of interrupt from RTC TimeStamp, RTC Tampers + and LSE Clock Security System to CPU2 */ +#define LL_C2_SYSCFG_GRP1_RTCALARM SYSCFG_C2IMR1_RTCALARMIM /*!< Enabling of interrupt from RTC Alarms to CPU2 */ +#define LL_C2_SYSCFG_GRP1_RTCSSRU SYSCFG_C2IMR1_RTCSSRUIM /*!< Enabling of interrupt from RTC SSRU to CPU2 */ +#define LL_C2_SYSCFG_GRP1_RTCWKUP SYSCFG_C2IMR1_RTCWKUPIM /*!< Enabling of interrupt from RTC Wakeup to CPU2 */ +#define LL_C2_SYSCFG_GRP1_RCC SYSCFG_C2IMR1_RCCIM /*!< Enabling of interrupt from RCC to CPU2 */ +#define LL_C2_SYSCFG_GRP1_FLASH SYSCFG_C2IMR1_FLASHIM /*!< Enabling of interrupt from FLASH to CPU2 */ +#define LL_C2_SYSCFG_GRP1_PKA SYSCFG_C2IMR1_PKAIM /*!< Enabling of interrupt from PKA to CPU2 */ +#define LL_C2_SYSCFG_GRP1_AES SYSCFG_C2IMR1_AESIM /*!< Enabling of interrupt from AES to CPU2 */ +#define LL_C2_SYSCFG_GRP1_COMP SYSCFG_C2IMR1_COMPIM /*!< Enabling of interrupt from Comparator to CPU2 */ +#define LL_C2_SYSCFG_GRP1_ADC SYSCFG_C2IMR1_ADCIM /*!< Enabling of interrupt from Analog Digital Converter to CPU2 */ +#define LL_C2_SYSCFG_GRP1_DAC SYSCFG_C2IMR1_DACIM /*!< Enabling of interrupt from Digital Analog Converter to CPU2 */ + +#define LL_C2_SYSCFG_GRP1_EXTI0 SYSCFG_C2IMR1_EXTI0IM /*!< Enabling of interrupt from External Interrupt Line 0 to CPU2 */ +#define LL_C2_SYSCFG_GRP1_EXTI1 SYSCFG_C2IMR1_EXTI1IM /*!< Enabling of interrupt from External Interrupt Line 1 to CPU2 */ +#define LL_C2_SYSCFG_GRP1_EXTI2 SYSCFG_C2IMR1_EXTI2IM /*!< Enabling of interrupt from External Interrupt Line 2 to CPU2 */ +#define LL_C2_SYSCFG_GRP1_EXTI3 SYSCFG_C2IMR1_EXTI3IM /*!< Enabling of interrupt from External Interrupt Line 3 to CPU2 */ +#define LL_C2_SYSCFG_GRP1_EXTI4 SYSCFG_C2IMR1_EXTI4IM /*!< Enabling of interrupt from External Interrupt Line 4 to CPU2 */ +#define LL_C2_SYSCFG_GRP1_EXTI5 SYSCFG_C2IMR1_EXTI5IM /*!< Enabling of interrupt from External Interrupt Line 5 to CPU2 */ +#define LL_C2_SYSCFG_GRP1_EXTI6 SYSCFG_C2IMR1_EXTI6IM /*!< Enabling of interrupt from External Interrupt Line 6 to CPU2 */ +#define LL_C2_SYSCFG_GRP1_EXTI7 SYSCFG_C2IMR1_EXTI7IM /*!< Enabling of interrupt from External Interrupt Line 7 to CPU2 */ +#define LL_C2_SYSCFG_GRP1_EXTI8 SYSCFG_C2IMR1_EXTI8IM /*!< Enabling of interrupt from External Interrupt Line 8 to CPU2 */ +#define LL_C2_SYSCFG_GRP1_EXTI9 SYSCFG_C2IMR1_EXTI9IM /*!< Enabling of interrupt from External Interrupt Line 9 to CPU2 */ +#define LL_C2_SYSCFG_GRP1_EXTI10 SYSCFG_C2IMR1_EXTI10IM /*!< Enabling of interrupt from External Interrupt Line 10 to CPU2 */ +#define LL_C2_SYSCFG_GRP1_EXTI11 SYSCFG_C2IMR1_EXTI11IM /*!< Enabling of interrupt from External Interrupt Line 11 to CPU2 */ +#define LL_C2_SYSCFG_GRP1_EXTI12 SYSCFG_C2IMR1_EXTI12IM /*!< Enabling of interrupt from External Interrupt Line 12 to CPU2 */ +#define LL_C2_SYSCFG_GRP1_EXTI13 SYSCFG_C2IMR1_EXTI13IM /*!< Enabling of interrupt from External Interrupt Line 13 to CPU2 */ +#define LL_C2_SYSCFG_GRP1_EXTI14 SYSCFG_C2IMR1_EXTI14IM /*!< Enabling of interrupt from External Interrupt Line 14 to CPU2 */ +#define LL_C2_SYSCFG_GRP1_EXTI15 SYSCFG_C2IMR1_EXTI15IM /*!< Enabling of interrupt from External Interrupt Line 15 to CPU2 */ + +#define LL_C2_SYSCFG_GRP2_DMA1CH1 SYSCFG_C2IMR2_DMA1CH1IM /*!< Enabling of interrupt from DMA1 Channel 1 to CPU2 */ +#define LL_C2_SYSCFG_GRP2_DMA1CH2 SYSCFG_C2IMR2_DMA1CH2IM /*!< Enabling of interrupt from DMA1 Channel 2 to CPU2 */ +#define LL_C2_SYSCFG_GRP2_DMA1CH3 SYSCFG_C2IMR2_DMA1CH3IM /*!< Enabling of interrupt from DMA1 Channel 3 to CPU2 */ +#define LL_C2_SYSCFG_GRP2_DMA1CH4 SYSCFG_C2IMR2_DMA1CH4IM /*!< Enabling of interrupt from DMA1 Channel 4 to CPU2 */ +#define LL_C2_SYSCFG_GRP2_DMA1CH5 SYSCFG_C2IMR2_DMA1CH5IM /*!< Enabling of interrupt from DMA1 Channel 5 to CPU2 */ +#define LL_C2_SYSCFG_GRP2_DMA1CH6 SYSCFG_C2IMR2_DMA1CH6IM /*!< Enabling of interrupt from DMA1 Channel 6 to CPU2 */ +#define LL_C2_SYSCFG_GRP2_DMA1CH7 SYSCFG_C2IMR2_DMA1CH7IM /*!< Enabling of interrupt from DMA1 Channel 7 to CPU2 */ + +#define LL_C2_SYSCFG_GRP2_DMA2CH1 SYSCFG_C2IMR2_DMA2CH1IM /*!< Enabling of interrupt from DMA2 Channel 1 to CPU2 */ +#define LL_C2_SYSCFG_GRP2_DMA2CH2 SYSCFG_C2IMR2_DMA2CH2IM /*!< Enabling of interrupt from DMA2 Channel 2 to CPU2 */ +#define LL_C2_SYSCFG_GRP2_DMA2CH3 SYSCFG_C2IMR2_DMA2CH3IM /*!< Enabling of interrupt from DMA2 Channel 3 to CPU2 */ +#define LL_C2_SYSCFG_GRP2_DMA2CH4 SYSCFG_C2IMR2_DMA2CH4IM /*!< Enabling of interrupt from DMA2 Channel 4 to CPU2 */ +#define LL_C2_SYSCFG_GRP2_DMA2CH5 SYSCFG_C2IMR2_DMA2CH5IM /*!< Enabling of interrupt from DMA2 Channel 5 to CPU2 */ +#define LL_C2_SYSCFG_GRP2_DMA2CH6 SYSCFG_C2IMR2_DMA2CH6IM /*!< Enabling of interrupt from DMA2 Channel 6 to CPU2 */ +#define LL_C2_SYSCFG_GRP2_DMA2CH7 SYSCFG_C2IMR2_DMA2CH7IM /*!< Enabling of interrupt from DMA2 Channel 7 to CPU2 */ + +#define LL_C2_SYSCFG_GRP2_DMAMUX1 SYSCFG_C2IMR2_DMAMUX1IM /*!< Enabling of interrupt from DMAMUX1 to CPU2 */ + +#define LL_C2_SYSCFG_GRP2_PVM3 SYSCFG_C2IMR2_PVM3IM /*!< Enabling of interrupt from Power Voltage Monitoring 3 to CPU2 */ +#define LL_C2_SYSCFG_GRP2_PVD SYSCFG_C2IMR2_PVDIM /*!< Enabling of interrupt from Power Voltage Detector to CPU2 */ +/** + * @} + */ +#endif + +/** @defgroup SYSTEM_LL_EC_RF_TEST_BUS_TYPE SYSCFG RF TEST BUS TYPE + * @{ + */ +#define LL_SYSCFG_ANALOG_TEST_BUS SYSCFG_RFDCR_RFTBSEL /*!< Analog test bus selected on RF_ADTB[3:0] */ +#define LL_SYSCFG_DIGITAL_TEST_BUS 0x00000000U /*!< Digital test bus selected on RF_ADTB[3:0] */ +/** + * @} + */ + + +#if defined(CORE_CM0PLUS) +#else +/** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU CPU1 APB1 GRP1 STOP IP + * @{ + */ +#define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_APB1FZR1_DBG_TIM2_STOP /*!< The counter clock of TIM2 is stopped when the core is halted */ +#define LL_DBGMCU_APB1_GRP1_RTC_STOP DBGMCU_APB1FZR1_DBG_RTC_STOP /*!< The clock of the RTC counter is stopped when the core is halted */ +#define LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_APB1FZR1_DBG_WWDG_STOP /*!< The watchdog counter clock is stopped when the core is halted */ +#define LL_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_APB1FZR1_DBG_IWDG_STOP /*!< The independent watchdog counter clock is stopped when the core is halted */ +#define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_APB1FZR1_DBG_I2C1_STOP /*!< The I2C1 SMBus timeout is frozen */ +#define LL_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_APB1FZR1_DBG_I2C2_STOP /*!< The I2C2 SMBus timeout is frozen */ +#define LL_DBGMCU_APB1_GRP1_I2C3_STOP DBGMCU_APB1FZR1_DBG_I2C3_STOP /*!< The I2C3 SMBus timeout is frozen */ +#define LL_DBGMCU_APB1_GRP1_LPTIM1_STOP DBGMCU_APB1FZR1_DBG_LPTIM1_STOP /*!< The counter clock of LPTIM1 is stopped when the core is halted */ +/** + * @} + */ + +#if defined(DUAL_CORE) +/** @defgroup SYSTEM_LL_EC_C2_APB1_GRP1_STOP_IP DBGMCU CPU2 APB1 GRP1 STOP IP + * @{ + */ +#define LL_C2_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_C2APB1FZR1_DBG_TIM2_STOP /*!< The counter clock of TIM2 is stopped when the core is halted */ +#define LL_C2_DBGMCU_APB1_GRP1_RTC_STOP DBGMCU_C2APB1FZR1_DBG_RTC_STOP /*!< The clock of the RTC counter is stopped when the core is halted */ +#define LL_C2_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_C2APB1FZR1_DBG_IWDG_STOP /*!< The independent watchdog counter clock is stopped when the core is halted */ +#define LL_C2_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_C2APB1FZR1_DBG_I2C1_STOP /*!< The I2C1 SMBus timeout is frozen */ +#define LL_C2_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_C2APB1FZR1_DBG_I2C2_STOP /*!< The I2C2 SMBus timeout is frozen */ +#define LL_C2_DBGMCU_APB1_GRP1_I2C3_STOP DBGMCU_C2APB1FZR1_DBG_I2C3_STOP /*!< The I2C3 SMBus timeout is frozen */ +#define LL_C2_DBGMCU_APB1_GRP1_LPTIM1_STOP DBGMCU_C2APB1FZR1_DBG_LPTIM1_STOP /*!< The counter clock of LPTIM1 is stopped when the core is halted */ +/** + * @} + */ +#endif /* DUAL_CORE */ + +/** @defgroup SYSTEM_LL_EC_APB1_GRP2_STOP_IP DBGMCU CPU1 APB1 GRP2 STOP IP + * @{ + */ +#define LL_DBGMCU_APB1_GRP2_LPTIM2_STOP DBGMCU_APB1FZR2_DBG_LPTIM2_STOP /*!< The counter clock of LPTIM2 is stopped when the core is halted */ +#define LL_DBGMCU_APB1_GRP2_LPTIM3_STOP DBGMCU_APB1FZR2_DBG_LPTIM3_STOP /*!< The counter clock of LPTIM3 is stopped when the core is halted */ +/** + * @} + */ + +#if defined(DUAL_CORE) +/** @defgroup SYSTEM_LL_EC_C2_APB1_GRP2_STOP_IP DBGMCU CPU2 APB1 GRP2 STOP IP + * @{ + */ +#define LL_C2_DBGMCU_APB1_GRP2_LPTIM2_STOP DBGMCU_C2APB1FZR2_DBG_LPTIM2_STOP /*!< The counter clock of LPTIM2 is stopped when the core is halted */ +#define LL_C2_DBGMCU_APB1_GRP2_LPTIM3_STOP DBGMCU_C2APB1FZR2_DBG_LPTIM3_STOP /*!< The counter clock of LPTIM3 is stopped when the core is halted */ +/** + * @} + */ +#endif /* DUAL_CORE */ + +/** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU CPU1 APB2 GRP1 STOP IP + * @{ + */ +#define LL_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_APB2FZR_DBG_TIM1_STOP /*!< The counter clock of TIM1 is stopped when the core is halted */ +#define LL_DBGMCU_APB2_GRP1_TIM16_STOP DBGMCU_APB2FZR_DBG_TIM16_STOP /*!< The counter clock of TIM16 is stopped when the core is halted */ +#define LL_DBGMCU_APB2_GRP1_TIM17_STOP DBGMCU_APB2FZR_DBG_TIM17_STOP /*!< The counter clock of TIM17 is stopped when the core is halted */ +/** + * @} + */ + +#if defined(DUAL_CORE) +/** @defgroup SYSTEM_LL_EC_C2_APB2_GRP1_STOP_IP DBGMCU CPU2 APB2 GRP1 STOP IP + * @{ + */ +#define LL_C2_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_C2APB2FZR_DBG_TIM1_STOP /*!< The counter clock of TIM1 is stopped when the core is halted */ +#define LL_C2_DBGMCU_APB2_GRP1_TIM16_STOP DBGMCU_C2APB2FZR_DBG_TIM16_STOP /*!< The counter clock of TIM16 is stopped when the core is halted */ +#define LL_C2_DBGMCU_APB2_GRP1_TIM17_STOP DBGMCU_C2APB2FZR_DBG_TIM17_STOP /*!< The counter clock of TIM17 is stopped when the core is halted */ +/** + * @} + */ +#endif /* DUAL_CORE */ + +#endif + +#if defined(VREFBUF) +/** @defgroup SYSTEM_LL_EC_VOLTAGE VREFBUF VOLTAGE + * @{ + */ +#define LL_VREFBUF_VOLTAGE_SCALE0 0x00000000U /*!< Voltage reference scale 0 (VREF_OUT1) */ +#define LL_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS /*!< Voltage reference scale 1 (VREF_OUT2) */ +/** + * @} + */ +#endif /* VREFBUF */ + +/** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY + * @{ + */ +#define LL_FLASH_LATENCY_0 0x00000000U /*!< FLASH Zero wait state */ +#define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_0 /*!< FLASH One wait state */ +#define LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_1 /*!< FLASH Two wait states */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions + * @{ + */ + +/** @defgroup SYSTEM_LL_EF_SYSCFG SYSCFG + * @{ + */ + +/** + * @brief Set memory mapping at address 0x00000000 + * @rmtoll SYSCFG_MEMRMP MEM_MODE LL_SYSCFG_SetRemapMemory + * @param Memory This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_REMAP_FLASH + * @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH + * @arg @ref LL_SYSCFG_REMAP_SRAM + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetRemapMemory(uint32_t Memory) +{ + MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, Memory); +} + +/** + * @brief Get memory mapping at address 0x00000000 + * @rmtoll SYSCFG_MEMRMP MEM_MODE LL_SYSCFG_GetRemapMemory + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_REMAP_FLASH + * @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH + * @arg @ref LL_SYSCFG_REMAP_SRAM + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetRemapMemory(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE)); +} + +/** + * @brief Enable I/O analog switch voltage booster. + * @note When voltage booster is enabled, I/O analog switches are supplied + * by a dedicated voltage booster, from VDD power domain. This is + * the recommended configuration with low VDDA voltage operation. + * @note The I/O analog switch voltage booster is relevant for peripherals + * using I/O in analog input: ADC and COMP. + * However, COMP inputs have a high impedance and + * voltage booster do not impact performance significantly. + * Therefore, the voltage booster is mainly intended for + * usage with ADC. + * @rmtoll SYSCFG_CFGR1 BOOSTEN LL_SYSCFG_EnableAnalogBooster + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_EnableAnalogBooster(void) +{ + SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN); +} + +/** + * @brief Disable I/O analog switch voltage booster. + * @note When voltage booster is enabled, I/O analog switches are supplied + * by a dedicated voltage booster, from VDD power domain. This is + * the recommended configuration with low VDDA voltage operation. + * @note The I/O analog switch voltage booster is relevant for peripherals + * using I/O in analog input: ADC and COMP. + * However, COMP inputs have a high impedance and + * voltage booster do not impact performance significantly. + * Therefore, the voltage booster is mainly intended for + * usage with ADC. + * @rmtoll SYSCFG_CFGR1 BOOSTEN LL_SYSCFG_DisableAnalogBooster + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DisableAnalogBooster(void) +{ + CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN); +} + +/** + * @brief Enable the I2C fast mode plus driving capability. + * @rmtoll SYSCFG_CFGR1 I2C_PBx_FMP LL_SYSCFG_EnableFastModePlus\n + * SYSCFG_CFGR1 I2Cx_FMP LL_SYSCFG_EnableFastModePlus + * @param ConfigFastModePlus This parameter can be a combination of the following values: + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus) +{ + SET_BIT(SYSCFG->CFGR1, ConfigFastModePlus); +} + +/** + * @brief Disable the I2C fast mode plus driving capability. + * @rmtoll SYSCFG_CFGR1 I2C_PBx_FMP LL_SYSCFG_DisableFastModePlus\n + * SYSCFG_CFGR1 I2Cx_FMP LL_SYSCFG_DisableFastModePlus + * @param ConfigFastModePlus This parameter can be a combination of the following values: + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus) +{ + CLEAR_BIT(SYSCFG->CFGR1, ConfigFastModePlus); +} + +/** + * @brief Configure source input for the EXTI external interrupt. + * @rmtoll SYSCFG_EXTICR1 EXTIx LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR2 EXTIx LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR3 EXTIx LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR4 EXTIx LL_SYSCFG_SetEXTISource + * @param Port This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_EXTI_PORTA + * @arg @ref LL_SYSCFG_EXTI_PORTB + * @arg @ref LL_SYSCFG_EXTI_PORTC + * + * @param Line This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_EXTI_LINE0 + * @arg @ref LL_SYSCFG_EXTI_LINE1 + * @arg @ref LL_SYSCFG_EXTI_LINE2 + * @arg @ref LL_SYSCFG_EXTI_LINE3 + * @arg @ref LL_SYSCFG_EXTI_LINE4 + * @arg @ref LL_SYSCFG_EXTI_LINE5 + * @arg @ref LL_SYSCFG_EXTI_LINE6 + * @arg @ref LL_SYSCFG_EXTI_LINE7 + * @arg @ref LL_SYSCFG_EXTI_LINE8 + * @arg @ref LL_SYSCFG_EXTI_LINE9 + * @arg @ref LL_SYSCFG_EXTI_LINE10 + * @arg @ref LL_SYSCFG_EXTI_LINE11 + * @arg @ref LL_SYSCFG_EXTI_LINE12 + * @arg @ref LL_SYSCFG_EXTI_LINE13 + * @arg @ref LL_SYSCFG_EXTI_LINE14 + * @arg @ref LL_SYSCFG_EXTI_LINE15 + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetEXTISource(uint32_t Port, uint32_t Line) +{ +#if defined(CORE_CM0PLUS) + MODIFY_REG(SYSCFG->EXTICR[Line & 0x03U], SYSCFG_EXTICR1_EXTI0 << ((Line >> LL_SYSCFG_EXTI_REGISTER_PINPOS_SHFT) & 12UL), (Port << ((Line >> LL_SYSCFG_EXTI_REGISTER_PINPOS_SHFT) & 12UL))); +#else + MODIFY_REG(SYSCFG->EXTICR[Line & 0x03U], (Line >> LL_SYSCFG_EXTI_REGISTER_PINPOS_SHFT), (Port << ((POSITION_VAL((Line >> LL_SYSCFG_EXTI_REGISTER_PINPOS_SHFT))) & 0x0000000FUL))); +#endif +} + +/** + * @brief Get the configured defined for specific EXTI Line + * @rmtoll SYSCFG_EXTICR1 EXTIx LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR2 EXTIx LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR3 EXTIx LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR4 EXTIx LL_SYSCFG_GetEXTISource + * @param Line This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_EXTI_LINE0 + * @arg @ref LL_SYSCFG_EXTI_LINE1 + * @arg @ref LL_SYSCFG_EXTI_LINE2 + * @arg @ref LL_SYSCFG_EXTI_LINE3 + * @arg @ref LL_SYSCFG_EXTI_LINE4 + * @arg @ref LL_SYSCFG_EXTI_LINE5 + * @arg @ref LL_SYSCFG_EXTI_LINE6 + * @arg @ref LL_SYSCFG_EXTI_LINE7 + * @arg @ref LL_SYSCFG_EXTI_LINE8 + * @arg @ref LL_SYSCFG_EXTI_LINE9 + * @arg @ref LL_SYSCFG_EXTI_LINE10 + * @arg @ref LL_SYSCFG_EXTI_LINE11 + * @arg @ref LL_SYSCFG_EXTI_LINE12 + * @arg @ref LL_SYSCFG_EXTI_LINE13 + * @arg @ref LL_SYSCFG_EXTI_LINE14 + * @arg @ref LL_SYSCFG_EXTI_LINE15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_EXTI_PORTA + * @arg @ref LL_SYSCFG_EXTI_PORTB + * @arg @ref LL_SYSCFG_EXTI_PORTC + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource(uint32_t Line) +{ +#if defined(CORE_CM0PLUS) + return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0x03U], (SYSCFG_EXTICR1_EXTI0 << ((Line >> LL_SYSCFG_EXTI_REGISTER_PINPOS_SHFT) & 12UL))) >> ((Line >> LL_SYSCFG_EXTI_REGISTER_PINPOS_SHFT) & 12UL)); +#else + return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0x03U], + (Line >> LL_SYSCFG_EXTI_REGISTER_PINPOS_SHFT)) >> POSITION_VAL(Line >> LL_SYSCFG_EXTI_REGISTER_PINPOS_SHFT)); +#endif +} + +/** + * @brief Start a hardware SRAM2 erase operation. + * @rmtoll SYSCFG_SCSR SRAM2ER LL_SYSCFG_EnableSRAM2Erase\n + * @note This operation can be done only once SRAM2 page write protection unlocked + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_EnableSRAM2Erase(void) +{ + SET_BIT(SYSCFG->SCSR, SYSCFG_SCSR_SRAM2ER); +} + +/** + * @brief Check if SRAM1 or SRAM2 is busy by erase operation + * @rmtoll SYSCFG_SCSR SRAMBSY LL_SYSCFG_IsSRAMEraseOngoing + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsSRAMEraseOngoing(void) +{ + return ((READ_BIT(SYSCFG->SCSR, SYSCFG_SCSR_SRAMBSY) == (SYSCFG_SCSR_SRAMBSY)) ? 1UL : 0UL); +} + +/** + * @brief Check if PKA SRAMis busy by erase operation + * @rmtoll SYSCFG_SCSR PKASRAMBSY LL_SYSCFG_IsPKASRAMEraseOngoing + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsPKASRAMEraseOngoing(void) +{ + return ((READ_BIT(SYSCFG->SCSR, SYSCFG_SCSR_PKASRAMBSY) == (SYSCFG_SCSR_PKASRAMBSY)) ? 1UL : 0UL); +} + +/** + * @brief Set connections to TIM1/16/17 Break inputs + * @rmtoll SYSCFG_CFGR2 CLL LL_SYSCFG_SetTIMBreakInputs\n + * SYSCFG_CFGR2 SPL LL_SYSCFG_SetTIMBreakInputs\n + * SYSCFG_CFGR2 PVDL LL_SYSCFG_SetTIMBreakInputs\n + * SYSCFG_CFGR2 ECCL LL_SYSCFG_SetTIMBreakInputs + * @param Break This parameter can be a combination of the following values: + * @arg @ref LL_SYSCFG_TIMBREAK_ECC + * @arg @ref LL_SYSCFG_TIMBREAK_PVD + * @arg @ref LL_SYSCFG_TIMBREAK_SRAM2_PARITY + * @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs(uint32_t Break) +{ + MODIFY_REG(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL | SYSCFG_CFGR2_SPL | SYSCFG_CFGR2_PVDL | SYSCFG_CFGR2_ECCL, Break); +} + +/** + * @brief Get connections to TIM1/16/17 Break inputs + * @rmtoll SYSCFG_CFGR2 CLL LL_SYSCFG_GetTIMBreakInputs\n + * SYSCFG_CFGR2 SPL LL_SYSCFG_GetTIMBreakInputs\n + * SYSCFG_CFGR2 PVDL LL_SYSCFG_GetTIMBreakInputs\n + * SYSCFG_CFGR2 ECCL LL_SYSCFG_GetTIMBreakInputs + * @retval Returned value can be can be a combination of the following values: + * @arg @ref LL_SYSCFG_TIMBREAK_ECC + * @arg @ref LL_SYSCFG_TIMBREAK_PVD + * @arg @ref LL_SYSCFG_TIMBREAK_SRAM2_PARITY + * @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL | SYSCFG_CFGR2_SPL | SYSCFG_CFGR2_PVDL | SYSCFG_CFGR2_ECCL)); +} + +/** + * @brief Check if SRAM2 parity error detected + * @rmtoll SYSCFG_CFGR2 SPF LL_SYSCFG_IsActiveFlag_SP + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_SP(void) +{ + return ((READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF) == (SYSCFG_CFGR2_SPF)) ? 1UL : 0UL); +} + +/** + * @brief Clear SRAM2 parity error flag + * @rmtoll SYSCFG_CFGR2 SPF LL_SYSCFG_ClearFlag_SP + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_ClearFlag_SP(void) +{ + SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF); +} + +/** + * @brief Enable SRAM2 page write protection for Pages in range 0 to 31 + * @note Write protection is cleared only by a system reset + * @rmtoll SYSCFG_SWPR PxWP LL_SYSCFG_EnableSRAM2PageWRP_0_31 + * @param SRAM2WRP This parameter can be a combination of the following values: + * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE0 + * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE1 + * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE2 + * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE3 + * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE4 + * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE5 + * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE6 + * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE7 + * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE8 + * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE9 + * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE10 + * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE11 + * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE12 + * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE13 + * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE14 + * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE15 + * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE16 + * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE17 + * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE18 + * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE19 + * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE20 + * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE21 + * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE22 + * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE23 + * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE24 + * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE25 + * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE26 + * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE27 + * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE28 + * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE29 + * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE30 + * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE31 + * @retval None + */ +/* Legacy define */ +#define LL_SYSCFG_EnableSRAM2PageWRP LL_SYSCFG_EnableSRAM2PageWRP_0_31 +__STATIC_INLINE void LL_SYSCFG_EnableSRAM2PageWRP_0_31(uint32_t SRAM2WRP) +{ + SET_BIT(SYSCFG->SWPR, SRAM2WRP); +} + + +/** + * @brief SRAM2 page write protection lock prior to erase + * @rmtoll SYSCFG_SKR KEY LL_SYSCFG_LockSRAM2WRP + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_LockSRAM2WRP(void) +{ + /* Writing a wrong key reactivates the write protection */ + WRITE_REG(SYSCFG->SKR, 0x00U); +} + +/** + * @brief SRAM2 page write protection unlock prior to erase + * @rmtoll SYSCFG_SKR KEY LL_SYSCFG_UnlockSRAM2WRP + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_UnlockSRAM2WRP(void) +{ + /* unlock the write protection of the SRAM2ER bit */ + WRITE_REG(SYSCFG->SKR, 0xCAU); + WRITE_REG(SYSCFG->SKR, 0x53U); +} + +#if defined(DUAL_CORE) +/** + * @brief Enable CPU1 Interrupt Mask + * @rmtoll SYSCFG_IMR1 RTCSTAMPTAMPLSECSS1IM LL_SYSCFG_GRP1_EnableIT\n + * SYSCFG_IMR1 RTCSSRUIM LL_SYSCFG_GRP1_EnableIT\n + * SYSCFG_IMR1 EXTIxIM LL_SYSCFG_GRP1_EnableIT + * @param Interrupt This parameter can be a combination of the following values: + * @arg @ref LL_SYSCFG_GRP1_RTCSTAMPTAMPLSECSS + * @arg @ref LL_SYSCFG_GRP1_RTCSSRU + * @arg @ref LL_SYSCFG_GRP1_EXTI5 + * @arg @ref LL_SYSCFG_GRP1_EXTI6 + * @arg @ref LL_SYSCFG_GRP1_EXTI7 + * @arg @ref LL_SYSCFG_GRP1_EXTI8 + * @arg @ref LL_SYSCFG_GRP1_EXTI9 + * @arg @ref LL_SYSCFG_GRP1_EXTI10 + * @arg @ref LL_SYSCFG_GRP1_EXTI11 + * @arg @ref LL_SYSCFG_GRP1_EXTI12 + * @arg @ref LL_SYSCFG_GRP1_EXTI13 + * @arg @ref LL_SYSCFG_GRP1_EXTI14 + * @arg @ref LL_SYSCFG_GRP1_EXTI15 + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_GRP1_EnableIT(uint32_t Interrupt) +{ + CLEAR_BIT(SYSCFG->IMR1, Interrupt); +} + +/** + * @brief Enable CPU1 Interrupt Mask + * @rmtoll SYSCFG_IMR1 PVM3IM LL_SYSCFG_GRP2_EnableIT\n + * SYSCFG_IMR1 PVDIM LL_SYSCFG_GRP2_EnableIT + * @param Interrupt This parameter can be a combination of the following values: + * @arg @ref LL_SYSCFG_GRP2_PVM3 + * @arg @ref LL_SYSCFG_GRP2_PVD + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_GRP2_EnableIT(uint32_t Interrupt) +{ + CLEAR_BIT(SYSCFG->IMR2, Interrupt); +} + +/** + * @brief Disable CPU1 Interrupt Mask + * @rmtoll SYSCFG_IMR1 RTCSTAMPTAMPLSECSS1IM LL_SYSCFG_GRP1_DisableIT\n + * SYSCFG_IMR1 RTCSSRUIM LL_SYSCFG_GRP1_DisableIT\n + * SYSCFG_IMR1 EXTIxIM LL_SYSCFG_GRP1_DisableIT + * @param Interrupt This parameter can be a combination of the following values: + * @arg @ref LL_SYSCFG_GRP1_RTCSTAMPTAMPLSECSS + * @arg @ref LL_SYSCFG_GRP1_RTCSSRU + * @arg @ref LL_SYSCFG_GRP1_EXTI5 + * @arg @ref LL_SYSCFG_GRP1_EXTI6 + * @arg @ref LL_SYSCFG_GRP1_EXTI7 + * @arg @ref LL_SYSCFG_GRP1_EXTI8 + * @arg @ref LL_SYSCFG_GRP1_EXTI9 + * @arg @ref LL_SYSCFG_GRP1_EXTI10 + * @arg @ref LL_SYSCFG_GRP1_EXTI11 + * @arg @ref LL_SYSCFG_GRP1_EXTI12 + * @arg @ref LL_SYSCFG_GRP1_EXTI13 + * @arg @ref LL_SYSCFG_GRP1_EXTI14 + * @arg @ref LL_SYSCFG_GRP1_EXTI15 + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_GRP1_DisableIT(uint32_t Interrupt) +{ + SET_BIT(SYSCFG->IMR1, Interrupt); +} + +/** + * @brief Disable CPU1 Interrupt Mask + * @rmtoll SYSCFG_IMR2 PVM3IM LL_SYSCFG_GRP2_DisableIT\n + * SYSCFG_IMR2 PVDIM LL_SYSCFG_GRP2_DisableIT + * @param Interrupt This parameter can be a combination of the following values: + * @arg @ref LL_SYSCFG_GRP2_PVM3 + * @arg @ref LL_SYSCFG_GRP2_PVD + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_GRP2_DisableIT(uint32_t Interrupt) +{ + SET_BIT(SYSCFG->IMR2, Interrupt); +} + +/** + * @brief Indicate if CPU1 Interrupt Mask is enabled + * @rmtoll SYSCFG_IMR1 RTCSTAMPTAMPLSECSS1IM LL_SYSCFG_GRP1_IsEnabledIT\n + * SYSCFG_IMR1 RTCSSRUIM LL_SYSCFG_GRP1_IsEnabledIT\n + * SYSCFG_IMR1 EXTIxIM LL_SYSCFG_GRP1_IsEnabledIT + * @param Interrupt This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_GRP1_RTCSTAMPTAMPLSECSS + * @arg @ref LL_SYSCFG_GRP1_RTCSSRU + * @arg @ref LL_SYSCFG_GRP1_EXTI5 + * @arg @ref LL_SYSCFG_GRP1_EXTI6 + * @arg @ref LL_SYSCFG_GRP1_EXTI7 + * @arg @ref LL_SYSCFG_GRP1_EXTI8 + * @arg @ref LL_SYSCFG_GRP1_EXTI9 + * @arg @ref LL_SYSCFG_GRP1_EXTI10 + * @arg @ref LL_SYSCFG_GRP1_EXTI11 + * @arg @ref LL_SYSCFG_GRP1_EXTI12 + * @arg @ref LL_SYSCFG_GRP1_EXTI13 + * @arg @ref LL_SYSCFG_GRP1_EXTI14 + * @arg @ref LL_SYSCFG_GRP1_EXTI15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GRP1_IsEnabledIT(uint32_t Interrupt) +{ + return ((READ_BIT(SYSCFG->IMR1, Interrupt) != (Interrupt)) ? 1UL : 0UL); +} + +/** + * @brief Indicate if CPU1 Interrupt Mask is enabled + * @rmtoll SYSCFG_IMR2 PVM3IM LL_SYSCFG_GRP2_IsEnabledIT\n + * SYSCFG_IMR2 PVDIM LL_SYSCFG_GRP2_IsEnabledIT + * @param Interrupt This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_GRP2_PVM3 + * @arg @ref LL_SYSCFG_GRP2_PVD + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GRP2_IsEnabledIT(uint32_t Interrupt) +{ + return ((READ_BIT(SYSCFG->IMR2, Interrupt) != (Interrupt)) ? 1UL : 0UL); +} + +/** + * @brief Enable CPU2 Interrupt Mask + * @rmtoll SYSCFG_C2IMR1 RTCSTAMPTAMPLSECSSIM LL_C2_SYSCFG_GRP1_EnableIT\n + * SYSCFG_C2IMR1 RTCALARMIM LL_C2_SYSCFG_GRP1_EnableIT\n + * SYSCFG_C2IMR1 RTCSSRUIM LL_C2_SYSCFG_GRP1_EnableIT\n + * SYSCFG_C2IMR1 RTCWKUPIM LL_C2_SYSCFG_GRP1_EnableIT\n + * SYSCFG_C2IMR1 RCCIM LL_C2_SYSCFG_GRP1_EnableIT\n + * SYSCFG_C2IMR1 FLASHIM LL_C2_SYSCFG_GRP1_EnableIT\n + * SYSCFG_C2IMR1 PKAIM LL_C2_SYSCFG_GRP1_EnableIT\n + * SYSCFG_C2IMR1 RNGIM LL_C2_SYSCFG_GRP1_EnableIT\n + * SYSCFG_C2IMR1 AESIM LL_C2_SYSCFG_GRP1_EnableIT\n + * SYSCFG_C2IMR1 COMPIM LL_C2_SYSCFG_GRP1_EnableIT\n + * SYSCFG_C2IMR1 ADCIM LL_C2_SYSCFG_GRP1_EnableIT\n + * SYSCFG_C2IMR1 EXTIxIM LL_C2_SYSCFG_GRP1_EnableIT + * @param Interrupt This parameter can be a combination of the following values: + * @arg @ref LL_C2_SYSCFG_GRP1_RTCSTAMP_RTCTAMP_LSECSS + * @arg @ref LL_C2_SYSCFG_GRP1_RTCALARM + * @arg @ref LL_C2_SYSCFG_GRP1_RTCSSRU + * @arg @ref LL_C2_SYSCFG_GRP1_RTCWKUP + * @arg @ref LL_C2_SYSCFG_GRP1_RCC + * @arg @ref LL_C2_SYSCFG_GRP1_FLASH + * @arg @ref LL_C2_SYSCFG_GRP1_PKA + * @arg @ref LL_C2_SYSCFG_GRP1_AES + * @arg @ref LL_C2_SYSCFG_GRP1_COMP + * @arg @ref LL_C2_SYSCFG_GRP1_ADC + * @arg @ref LL_C2_SYSCFG_GRP1_DAC + * @arg @ref LL_C2_SYSCFG_GRP1_EXTI0 + * @arg @ref LL_C2_SYSCFG_GRP1_EXTI1 + * @arg @ref LL_C2_SYSCFG_GRP1_EXTI2 + * @arg @ref LL_C2_SYSCFG_GRP1_EXTI3 + * @arg @ref LL_C2_SYSCFG_GRP1_EXTI4 + * @arg @ref LL_C2_SYSCFG_GRP1_EXTI5 + * @arg @ref LL_C2_SYSCFG_GRP1_EXTI6 + * @arg @ref LL_C2_SYSCFG_GRP1_EXTI7 + * @arg @ref LL_C2_SYSCFG_GRP1_EXTI8 + * @arg @ref LL_C2_SYSCFG_GRP1_EXTI9 + * @arg @ref LL_C2_SYSCFG_GRP1_EXTI10 + * @arg @ref LL_C2_SYSCFG_GRP1_EXTI11 + * @arg @ref LL_C2_SYSCFG_GRP1_EXTI12 + * @arg @ref LL_C2_SYSCFG_GRP1_EXTI13 + * @arg @ref LL_C2_SYSCFG_GRP1_EXTI14 + * @arg @ref LL_C2_SYSCFG_GRP1_EXTI15 + * @retval None + */ +__STATIC_INLINE void LL_C2_SYSCFG_GRP1_EnableIT(uint32_t Interrupt) +{ + CLEAR_BIT(SYSCFG->C2IMR1, Interrupt); +} + +/** + * @brief Enable CPU2 Interrupt Mask + * @rmtoll SYSCFG_C2IMR2 DMA1CHxIM LL_C2_SYSCFG_GRP2_EnableIT\n + * SYSCFG_C2IMR2 DMA2CHxIM LL_C2_SYSCFG_GRP2_EnableIT\n + * SYSCFG_C2IMR2 DMAMUX1IM LL_C2_SYSCFG_GRP2_EnableIT\n + * SYSCFG_C2IMR2 PVM3IM LL_C2_SYSCFG_GRP2_EnableIT\n + * SYSCFG_C2IMR2 PVDIM LL_C2_SYSCFG_GRP2_EnableIT + * @param Interrupt This parameter can be a combination of the following values: + * @arg @ref LL_C2_SYSCFG_GRP2_DMA1CH1 + * @arg @ref LL_C2_SYSCFG_GRP2_DMA1CH2 + * @arg @ref LL_C2_SYSCFG_GRP2_DMA1CH3 + * @arg @ref LL_C2_SYSCFG_GRP2_DMA1CH4 + * @arg @ref LL_C2_SYSCFG_GRP2_DMA1CH5 + * @arg @ref LL_C2_SYSCFG_GRP2_DMA1CH6 + * @arg @ref LL_C2_SYSCFG_GRP2_DMA1CH7 + * @arg @ref LL_C2_SYSCFG_GRP2_DMA2CH1 + * @arg @ref LL_C2_SYSCFG_GRP2_DMA2CH2 + * @arg @ref LL_C2_SYSCFG_GRP2_DMA2CH3 + * @arg @ref LL_C2_SYSCFG_GRP2_DMA2CH4 + * @arg @ref LL_C2_SYSCFG_GRP2_DMA2CH5 + * @arg @ref LL_C2_SYSCFG_GRP2_DMA2CH6 + * @arg @ref LL_C2_SYSCFG_GRP2_DMA2CH7 + * @arg @ref LL_C2_SYSCFG_GRP2_DMAMUX1 + * @arg @ref LL_C2_SYSCFG_GRP2_PVM3 + * @arg @ref LL_C2_SYSCFG_GRP2_PVD + * @retval None + */ +__STATIC_INLINE void LL_C2_SYSCFG_GRP2_EnableIT(uint32_t Interrupt) +{ + CLEAR_BIT(SYSCFG->C2IMR2, Interrupt); +} + +/** + * @brief Disable CPU2 Interrupt Mask + * @rmtoll SYSCFG_C2IMR1 RTCSTAMPTAMPLSECSS LL_C2_SYSCFG_GRP1_DisableIT\n + * SYSCFG_C2IMR1 RTCALARMIM LL_C2_SYSCFG_GRP1_DisableIT\n + * SYSCFG_C2IMR1 RTCSSRUIM LL_C2_SYSCFG_GRP1_DisableIT\n + * SYSCFG_C2IMR1 RTCWKUPIM LL_C2_SYSCFG_GRP1_DisableIT\n + * SYSCFG_C2IMR1 RCCIM LL_C2_SYSCFG_GRP1_DisableIT\n + * SYSCFG_C2IMR1 FLASHIM LL_C2_SYSCFG_GRP1_DisableIT\n + * SYSCFG_C2IMR1 PKAIM LL_C2_SYSCFG_GRP1_DisableIT\n + * SYSCFG_C2IMR1 RNGIM LL_C2_SYSCFG_GRP1_DisableIT\n + * SYSCFG_C2IMR1 AESIM LL_C2_SYSCFG_GRP1_DisableIT\n + * SYSCFG_C2IMR1 COMPIM LL_C2_SYSCFG_GRP1_DisableIT\n + * SYSCFG_C2IMR1 ADCIM LL_C2_SYSCFG_GRP1_DisableIT\n + * SYSCFG_C2IMR1 EXTIxIM LL_C2_SYSCFG_GRP1_DisableIT + * @param Interrupt This parameter can be a combination of the following values: + * @arg @ref LL_C2_SYSCFG_GRP1_RTCSTAMP_RTCTAMP_LSECSS + * @arg @ref LL_C2_SYSCFG_GRP1_RTCALARM + * @arg @ref LL_C2_SYSCFG_GRP1_RTCSSRU + * @arg @ref LL_C2_SYSCFG_GRP1_RTCWKUP + * @arg @ref LL_C2_SYSCFG_GRP1_RCC + * @arg @ref LL_C2_SYSCFG_GRP1_FLASH + * @arg @ref LL_C2_SYSCFG_GRP1_AES + * @arg @ref LL_C2_SYSCFG_GRP1_COMP + * @arg @ref LL_C2_SYSCFG_GRP1_ADC + * @arg @ref LL_C2_SYSCFG_GRP1_DAC + * @arg @ref LL_C2_SYSCFG_GRP1_EXTI0 + * @arg @ref LL_C2_SYSCFG_GRP1_EXTI1 + * @arg @ref LL_C2_SYSCFG_GRP1_EXTI2 + * @arg @ref LL_C2_SYSCFG_GRP1_EXTI3 + * @arg @ref LL_C2_SYSCFG_GRP1_EXTI4 + * @arg @ref LL_C2_SYSCFG_GRP1_EXTI5 + * @arg @ref LL_C2_SYSCFG_GRP1_EXTI6 + * @arg @ref LL_C2_SYSCFG_GRP1_EXTI7 + * @arg @ref LL_C2_SYSCFG_GRP1_EXTI8 + * @arg @ref LL_C2_SYSCFG_GRP1_EXTI9 + * @arg @ref LL_C2_SYSCFG_GRP1_EXTI10 + * @arg @ref LL_C2_SYSCFG_GRP1_EXTI11 + * @arg @ref LL_C2_SYSCFG_GRP1_EXTI12 + * @arg @ref LL_C2_SYSCFG_GRP1_EXTI13 + * @arg @ref LL_C2_SYSCFG_GRP1_EXTI14 + * @arg @ref LL_C2_SYSCFG_GRP1_EXTI15 + * @retval None + */ +__STATIC_INLINE void LL_C2_SYSCFG_GRP1_DisableIT(uint32_t Interrupt) +{ + SET_BIT(SYSCFG->C2IMR1, Interrupt); +} + +/** + * @brief Disable CPU2 Interrupt Mask + * @rmtoll SYSCFG_C2IMR2 DMA1CHxIM LL_C2_SYSCFG_GRP2_DisableIT\n + * SYSCFG_C2IMR2 DMA2CHxIM LL_C2_SYSCFG_GRP2_DisableIT\n + * SYSCFG_C2IMR2 DMAMUX1IM LL_C2_SYSCFG_GRP2_DisableIT\n + * SYSCFG_C2IMR2 PVM3IM LL_C2_SYSCFG_GRP2_DisableIT\n + * SYSCFG_C2IMR2 PVDIM LL_C2_SYSCFG_GRP2_DisableIT + * @param Interrupt This parameter can be a combination of the following values: + * @arg @ref LL_C2_SYSCFG_GRP2_DMA1CH1 + * @arg @ref LL_C2_SYSCFG_GRP2_DMA1CH2 + * @arg @ref LL_C2_SYSCFG_GRP2_DMA1CH3 + * @arg @ref LL_C2_SYSCFG_GRP2_DMA1CH4 + * @arg @ref LL_C2_SYSCFG_GRP2_DMA1CH5 + * @arg @ref LL_C2_SYSCFG_GRP2_DMA1CH6 + * @arg @ref LL_C2_SYSCFG_GRP2_DMA1CH7 + * @arg @ref LL_C2_SYSCFG_GRP2_DMA2CH1 + * @arg @ref LL_C2_SYSCFG_GRP2_DMA2CH2 + * @arg @ref LL_C2_SYSCFG_GRP2_DMA2CH3 + * @arg @ref LL_C2_SYSCFG_GRP2_DMA2CH4 + * @arg @ref LL_C2_SYSCFG_GRP2_DMA2CH5 + * @arg @ref LL_C2_SYSCFG_GRP2_DMA2CH6 + * @arg @ref LL_C2_SYSCFG_GRP2_DMA2CH7 + * @arg @ref LL_C2_SYSCFG_GRP2_DMAMUX1 + * @arg @ref LL_C2_SYSCFG_GRP2_PVM3 + * @arg @ref LL_C2_SYSCFG_GRP2_PVD + * @retval None + */ +__STATIC_INLINE void LL_C2_SYSCFG_GRP2_DisableIT(uint32_t Interrupt) +{ + SET_BIT(SYSCFG->C2IMR2, Interrupt); +} + +/** + * @brief Indicate if CPU2 Interrupt Mask is enabled + * @rmtoll SYSCFG_C2IMR1 RTCSTAMPTAMPLSECSS LL_C2_SYSCFG_GRP1_IsEnabledIT\n + * SYSCFG_C2IMR1 RTCALARMIM LL_C2_SYSCFG_GRP1_IsEnabledIT\n + * SYSCFG_C2IMR1 RTCSSRUIM LL_C2_SYSCFG_GRP1_IsEnabledIT\n + * SYSCFG_C2IMR1 RTCWKUPIM LL_C2_SYSCFG_GRP1_IsEnabledIT\n + * SYSCFG_C2IMR1 RCCIM LL_C2_SYSCFG_GRP1_IsEnabledIT\n + * SYSCFG_C2IMR1 FLASHIM LL_C2_SYSCFG_GRP1_IsEnabledIT\n + * SYSCFG_C2IMR1 PKAIM LL_C2_SYSCFG_GRP1_IsEnabledIT\n + * SYSCFG_C2IMR1 RNGIM LL_C2_SYSCFG_GRP1_IsEnabledIT\n + * SYSCFG_C2IMR1 AESIM LL_C2_SYSCFG_GRP1_IsEnabledIT\n + * SYSCFG_C2IMR1 COMPIM LL_C2_SYSCFG_GRP1_IsEnabledIT\n + * SYSCFG_C2IMR1 ADCIM LL_C2_SYSCFG_GRP1_IsEnabledIT\n + * SYSCFG_C2IMR1 EXTIxIM LL_C2_SYSCFG_GRP1_IsEnabledIT + * @param Interrupt This parameter can be a combination of the following values: + * @arg @ref LL_C2_SYSCFG_GRP1_RTCSTAMP_RTCTAMP_LSECSS + * @arg @ref LL_C2_SYSCFG_GRP1_RTCALARM + * @arg @ref LL_C2_SYSCFG_GRP1_RTCSSRU + * @arg @ref LL_C2_SYSCFG_GRP1_RTCWKUP + * @arg @ref LL_C2_SYSCFG_GRP1_RCC + * @arg @ref LL_C2_SYSCFG_GRP1_FLASH + * @arg @ref LL_C2_SYSCFG_GRP1_PKA + * @arg @ref LL_C2_SYSCFG_GRP1_AES + * @arg @ref LL_C2_SYSCFG_GRP1_COMP + * @arg @ref LL_C2_SYSCFG_GRP1_ADC + * @arg @ref LL_C2_SYSCFG_GRP1_DAC + * @arg @ref LL_C2_SYSCFG_GRP1_EXTI0 + * @arg @ref LL_C2_SYSCFG_GRP1_EXTI1 + * @arg @ref LL_C2_SYSCFG_GRP1_EXTI2 + * @arg @ref LL_C2_SYSCFG_GRP1_EXTI3 + * @arg @ref LL_C2_SYSCFG_GRP1_EXTI4 + * @arg @ref LL_C2_SYSCFG_GRP1_EXTI5 + * @arg @ref LL_C2_SYSCFG_GRP1_EXTI6 + * @arg @ref LL_C2_SYSCFG_GRP1_EXTI7 + * @arg @ref LL_C2_SYSCFG_GRP1_EXTI8 + * @arg @ref LL_C2_SYSCFG_GRP1_EXTI9 + * @arg @ref LL_C2_SYSCFG_GRP1_EXTI10 + * @arg @ref LL_C2_SYSCFG_GRP1_EXTI11 + * @arg @ref LL_C2_SYSCFG_GRP1_EXTI12 + * @arg @ref LL_C2_SYSCFG_GRP1_EXTI13 + * @arg @ref LL_C2_SYSCFG_GRP1_EXTI14 + * @arg @ref LL_C2_SYSCFG_GRP1_EXTI15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C2_SYSCFG_GRP1_IsEnabledIT(uint32_t Interrupt) +{ + return ((READ_BIT(SYSCFG->C2IMR1, Interrupt) != (Interrupt)) ? 1UL : 0UL); +} + +/** + * @brief Indicate if CPU2 Interrupt Mask is enabled + * @rmtoll SYSCFG_C2IMR2 DMA1CHxIM LL_C2_SYSCFG_GRP2_IsEnabledIT\n + * SYSCFG_C2IMR2 DMA2CHxIM LL_C2_SYSCFG_GRP2_IsEnabledIT\n + * SYSCFG_C2IMR2 DMAMUX1IM LL_C2_SYSCFG_GRP2_IsEnabledIT\n + * SYSCFG_C2IMR2 PVM3IM LL_C2_SYSCFG_GRP2_IsEnabledIT\n + * SYSCFG_C2IMR2 PVDIM LL_C2_SYSCFG_GRP2_IsEnabledIT + * @param Interrupt This parameter can be a combination of the following values: + * @arg @ref LL_C2_SYSCFG_GRP2_DMA1CH1 + * @arg @ref LL_C2_SYSCFG_GRP2_DMA1CH2 + * @arg @ref LL_C2_SYSCFG_GRP2_DMA1CH3 + * @arg @ref LL_C2_SYSCFG_GRP2_DMA1CH4 + * @arg @ref LL_C2_SYSCFG_GRP2_DMA1CH5 + * @arg @ref LL_C2_SYSCFG_GRP2_DMA1CH6 + * @arg @ref LL_C2_SYSCFG_GRP2_DMA1CH7 + * @arg @ref LL_C2_SYSCFG_GRP2_DMA2CH1 + * @arg @ref LL_C2_SYSCFG_GRP2_DMA2CH2 + * @arg @ref LL_C2_SYSCFG_GRP2_DMA2CH3 + * @arg @ref LL_C2_SYSCFG_GRP2_DMA2CH4 + * @arg @ref LL_C2_SYSCFG_GRP2_DMA2CH5 + * @arg @ref LL_C2_SYSCFG_GRP2_DMA2CH6 + * @arg @ref LL_C2_SYSCFG_GRP2_DMA2CH7 + * @arg @ref LL_C2_SYSCFG_GRP2_DMAMUX1 + * @arg @ref LL_C2_SYSCFG_GRP2_PVM3 + * @arg @ref LL_C2_SYSCFG_GRP2_PVD + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C2_SYSCFG_GRP2_IsEnabledIT(uint32_t Interrupt) +{ + return ((READ_BIT(SYSCFG->C2IMR2, Interrupt) != (Interrupt)) ? 1UL : 0UL); +} +#endif /* DUAL_CORE */ + +/** + * @brief Set radio debug test bus type, analog or digital + * @rmtoll SYSCFG_RFDR RFTBSEL LL_SYSCFG_SetRadioDebugTestBus + * @param RadioDebugTestBus This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_ANALOG_TEST_BUS + * @arg @ref LL_SYSCFG_DIGITAL_TEST_BUS + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetRadioDebugTestBus(uint32_t RadioDebugTestBus) +{ + MODIFY_REG(SYSCFG->RFDCR, SYSCFG_RFDCR_RFTBSEL, RadioDebugTestBus); +} + +/** + * @brief Get radio debug test bus type, analog or digital + * @rmtoll SYSCFG_RFDR RFTBSEL LL_SYSCFG_GetRadioDebugTestBus + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_ANALOG_TEST_BUS + * @arg @ref LL_SYSCFG_DIGITAL_TEST_BUS + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetRadioDebugTestBus(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->RFDCR, SYSCFG_RFDCR_RFTBSEL)); +} +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU + * @note DBGMCU is only accessible by Cortex M4 + * To access on DBGMCU, Cortex M0+ need to request to the Cortex M4 + * the action. + * @{ + */ + +#if defined(CORE_CM0PLUS) +#else +/** + * @brief Return the device identifier + * @note For STM32WLxxxx devices, the device ID is 0x497 + * @rmtoll DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID + * @retval Values between Min_Data=0x00 and Max_Data=0xFFF (ex: device ID is 0x497) + */ +__STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void) +{ + return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID)); +} + +/** + * @brief Return the device revision identifier + * @note This field indicates the revision of the device. + * @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID + * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF + */ +__STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void) +{ + return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos); +} + +/** + * @brief Enable the CPU1 Debug Module during SLEEP mode + * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_EnableDBGSleepMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_EnableDBGSleepMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); +} + +/** + * @brief Disable the CPU1 Debug Module during SLEEP mode + * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_DisableDBGSleepMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_DisableDBGSleepMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); +} + +/** + * @brief Enable the Debug Module during STOP mode + * @note This bit does not influence CPU2 operation, CPU2 cannot be debugged + * in Stop mode even when this bit is enabled + * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); +} + +/** + * @brief Disable the Debug Module during STOP mode + * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_DisableDBGStopMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); +} + +/** + * @brief Enable the Debug Module during STANDBY mode + * @note This bit does not influence CPU2 operation, CPU2 cannot be debugged + * in Standby mode even when this bit is enabled + * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); +} + +/** + * @brief Disable the Debug Module during STANDBY mode + * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_DisableDBGStandbyMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); +} + +/** + * @brief Freeze CPU1 APB1 peripherals (group1 peripherals) + * @rmtoll DBGMCU_APB1FZR1 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs) +{ + SET_BIT(DBGMCU->APB1FZR1, Periphs); +} + +#if defined(DUAL_CORE) +/** + * @brief Freeze CPU2 APB1 peripherals (group1 peripherals) + * @rmtoll DBGMCU_C2APB1FZR1 DBG_xxxx_STOP LL_C2_DBGMCU_APB1_GRP1_FreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_C2_DBGMCU_APB1_GRP1_TIM2_STOP + * @arg @ref LL_C2_DBGMCU_APB1_GRP1_RTC_STOP + * @arg @ref LL_C2_DBGMCU_APB1_GRP1_IWDG_STOP + * @arg @ref LL_C2_DBGMCU_APB1_GRP1_I2C1_STOP + * @arg @ref LL_C2_DBGMCU_APB1_GRP1_I2C2_STOP + * @arg @ref LL_C2_DBGMCU_APB1_GRP1_I2C3_STOP + * @arg @ref LL_C2_DBGMCU_APB1_GRP1_LPTIM1_STOP + * @retval None + */ +__STATIC_INLINE void LL_C2_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs) +{ + SET_BIT(DBGMCU->C2APB1FZR1, Periphs); +} +#endif /* DUAL_CORE */ + +/** + * @brief Freeze CPU1 APB1 peripherals (group2 peripherals) + * @rmtoll DBGMCU_APB1FZR2 LL_DBGMCU_APB1_GRP2_LPTIM2_STOP LL_DBGMCU_APB1_GRP2_FreezePeriph + * DBGMCU_APB1FZR2 LL_DBGMCU_APB1_GRP2_LPTIM3_STOP LL_DBGMCU_APB1_GRP2_FreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB1_GRP2_LPTIM2_STOP + * @arg @ref LL_DBGMCU_APB1_GRP2_LPTIM3_STOP + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs) +{ + SET_BIT(DBGMCU->APB1FZR2, Periphs); +} + +#if defined(DUAL_CORE) +/** + * @brief Freeze CPU2 APB1 peripherals (group2 peripherals) + * @rmtoll DBGMCU_APB1FZR2 LL_C2_DBGMCU_APB1_GRP2_LPTIM2_STOP LL_C2_DBGMCU_APB1_GRP2_FreezePeriph + * DBGMCU_APB1FZR2 LL_C2_DBGMCU_APB1_GRP2_LPTIM3_STOP LL_C2_DBGMCU_APB1_GRP2_FreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_C2_DBGMCU_APB1_GRP2_LPTIM2_STOP + * @arg @ref LL_C2_DBGMCU_APB1_GRP2_LPTIM3_STOP + * @retval None + */ +__STATIC_INLINE void LL_C2_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs) +{ + SET_BIT(DBGMCU->C2APB1FZR2, Periphs); +} +#endif /* DUAL_CORE */ + +/** + * @brief Unfreeze CPU1 APB1 peripherals (group1 peripherals) + * @rmtoll DBGMCU_APB1FZR1 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs) +{ + CLEAR_BIT(DBGMCU->APB1FZR1, Periphs); +} + +#if defined(DUAL_CORE) +/** + * @brief Unfreeze CPU2 APB1 peripherals (group1 peripherals) + * @rmtoll DBGMCU_C2APB1FZR1 DBG_xxxx_STOP LL_C2_DBGMCU_APB1_GRP1_UnFreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_C2_DBGMCU_APB1_GRP1_TIM2_STOP + * @arg @ref LL_C2_DBGMCU_APB1_GRP1_RTC_STOP + * @arg @ref LL_C2_DBGMCU_APB1_GRP1_IWDG_STOP + * @arg @ref LL_C2_DBGMCU_APB1_GRP1_I2C1_STOP + * @arg @ref LL_C2_DBGMCU_APB1_GRP1_I2C3_STOP + * @arg @ref LL_C2_DBGMCU_APB1_GRP1_LPTIM1_STOP + * @retval None + */ +__STATIC_INLINE void LL_C2_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs) +{ + CLEAR_BIT(DBGMCU->C2APB1FZR1, Periphs); +} +#endif /* DUAL_CORE */ + +/** + * @brief Unfreeze CPU1 APB1 peripherals (group2 peripherals) + * @rmtoll DBGMCU_APB1FZR2 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP2_UnFreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB1_GRP2_LPTIM2_STOP + * @arg @ref LL_DBGMCU_APB1_GRP2_LPTIM3_STOP + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs) +{ + CLEAR_BIT(DBGMCU->APB1FZR2, Periphs); +} + +#if defined(DUAL_CORE) +/** + * @brief Unfreeze CPU2 APB1 peripherals (group2 peripherals) + * @rmtoll DBGMCU_C2APB1FZR2 DBG_xxxx_STOP LL_C2_DBGMCU_APB1_GRP2_UnFreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_C2_DBGMCU_APB1_GRP2_LPTIM2_STOP + * @arg @ref LL_C2_DBGMCU_APB1_GRP2_LPTIM3_STOP + * @retval None + */ +__STATIC_INLINE void LL_C2_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs) +{ + CLEAR_BIT(DBGMCU->C2APB1FZR2, Periphs); +} +#endif /* DUAL_CORE */ + +/** + * @brief Freeze CPU1 APB2 peripherals + * @rmtoll DBGMCU_APB2FZR DBG_TIMx_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs) +{ + SET_BIT(DBGMCU->APB2FZR, Periphs); +} + +#if defined(DUAL_CORE) +/** + * @brief Freeze CPU2 APB2 peripherals + * @rmtoll DBGMCU_C2APB2FZR DBG_TIMx_STOP LL_C2_DBGMCU_APB2_GRP1_FreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_C2_DBGMCU_APB2_GRP1_TIM1_STOP + * @arg @ref LL_C2_DBGMCU_APB2_GRP1_TIM16_STOP + * @arg @ref LL_C2_DBGMCU_APB2_GRP1_TIM17_STOP + * @retval None + */ +__STATIC_INLINE void LL_C2_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs) +{ + SET_BIT(DBGMCU->C2APB2FZR, Periphs); +} +#endif /* DUAL_CORE */ + +/** + * @brief Unfreeze CPU1 APB2 peripherals + * @rmtoll DBGMCU_APB2FZR DBG_TIMx_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs) +{ + CLEAR_BIT(DBGMCU->APB2FZR, Periphs); +} + +#if defined(DUAL_CORE) +/** + * @brief Unfreeze CPU2 APB2 peripherals + * @rmtoll DBGMCU_C2APB2FZR DBG_TIMx_STOP LL_C2_DBGMCU_APB2_GRP1_UnFreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_C2_DBGMCU_APB2_GRP1_TIM1_STOP + * @arg @ref LL_C2_DBGMCU_APB2_GRP1_TIM16_STOP + * @arg @ref LL_C2_DBGMCU_APB2_GRP1_TIM17_STOP + * @retval None + */ +__STATIC_INLINE void LL_C2_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs) +{ + CLEAR_BIT(DBGMCU->C2APB2FZR, Periphs); +} +#endif /* DUAL_CORE */ + +#endif +/** + * @} + */ + +#if defined(VREFBUF) +/** @defgroup SYSTEM_LL_EF_VREFBUF VREFBUF + * @{ + */ + +/** + * @brief Enable Internal voltage reference + * @rmtoll VREFBUF_CSR ENVR LL_VREFBUF_Enable + * @retval None + */ +__STATIC_INLINE void LL_VREFBUF_Enable(void) +{ + SET_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR); +} + +/** + * @brief Disable Internal voltage reference + * @rmtoll VREFBUF_CSR ENVR LL_VREFBUF_Disable + * @retval None + */ +__STATIC_INLINE void LL_VREFBUF_Disable(void) +{ + CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR); +} + +/** + * @brief Enable high impedance (VREF+pin is high impedance) + * @rmtoll VREFBUF_CSR HIZ LL_VREFBUF_EnableHIZ + * @retval None + */ +__STATIC_INLINE void LL_VREFBUF_EnableHIZ(void) +{ + SET_BIT(VREFBUF->CSR, VREFBUF_CSR_HIZ); +} + +/** + * @brief Disable high impedance (VREF+pin is internally connected to the voltage reference buffer output) + * @rmtoll VREFBUF_CSR HIZ LL_VREFBUF_DisableHIZ + * @retval None + */ +__STATIC_INLINE void LL_VREFBUF_DisableHIZ(void) +{ + CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_HIZ); +} + +/** + * @brief Set the Voltage reference scale + * @rmtoll VREFBUF_CSR VRS LL_VREFBUF_SetVoltageScaling + * @param Scale This parameter can be one of the following values: + * @arg @ref LL_VREFBUF_VOLTAGE_SCALE0 + * @arg @ref LL_VREFBUF_VOLTAGE_SCALE1 + * @retval None + */ +__STATIC_INLINE void LL_VREFBUF_SetVoltageScaling(uint32_t Scale) +{ + MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_VRS, Scale); +} + +/** + * @brief Get the Voltage reference scale + * @rmtoll VREFBUF_CSR VRS LL_VREFBUF_GetVoltageScaling + * @retval Returned value can be one of the following values: + * @arg @ref LL_VREFBUF_VOLTAGE_SCALE0 + * @arg @ref LL_VREFBUF_VOLTAGE_SCALE1 + */ +__STATIC_INLINE uint32_t LL_VREFBUF_GetVoltageScaling(void) +{ + return (uint32_t)(READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRS)); +} + +/** + * @brief Get the VREFBUF trimming value for VRS=0 (VREF_SC0) + * @retval Between 0 and 0x3F + */ +__STATIC_INLINE uint32_t LL_VREFBUF_SC0_GetCalibration(void) +{ + return (uint32_t)(*VREFBUF_SC0_CAL_ADDR); +} + +/** + * @brief Get the VREFBUF trimming value for VRS=1 (VREF_SC1) + * @retval Between 0 and 0x3F + */ +__STATIC_INLINE uint32_t LL_VREFBUF_SC1_GetCalibration(void) +{ + return (uint32_t)(*VREFBUF_SC1_CAL_ADDR); +} + +/** + * @brief Check if Voltage reference buffer is ready + * @rmtoll VREFBUF_CSR VRR LL_VREFBUF_IsVREFReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_VREFBUF_IsVREFReady(void) +{ + return ((READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRR) == (VREFBUF_CSR_VRR)) ? 1UL : 0UL); +} + +/** + * @brief Get the trimming code for VREFBUF calibration + * @rmtoll VREFBUF_CCR TRIM LL_VREFBUF_GetTrimming + * @retval Between 0 and 0x3F + */ +__STATIC_INLINE uint32_t LL_VREFBUF_GetTrimming(void) +{ + return (uint32_t)(READ_BIT(VREFBUF->CCR, VREFBUF_CCR_TRIM)); +} + +/** + * @brief Set the trimming code for VREFBUF calibration (Tune the internal reference buffer voltage) + * @note Each VrefBuf voltage scale is calibrated in production for each device, + * data stored in flash memory. + * Functions @ref LL_VREFBUF_SC0_GetCalibration and + * @ref LL_VREFBUF_SC0_GetCalibration can be used to retrieve + * these calibration data. + * @rmtoll VREFBUF_CCR TRIM LL_VREFBUF_SetTrimming + * @param Value Between 0 and 0x3F + * @retval None + */ +__STATIC_INLINE void LL_VREFBUF_SetTrimming(uint32_t Value) +{ + WRITE_REG(VREFBUF->CCR, Value); +} + +/** + * @} + */ +#endif /* VREFBUF */ + +/** @defgroup SYSTEM_LL_EF_FLASH FLASH + * @{ + */ + +/** + * @brief Set FLASH Latency + * @rmtoll FLASH_ACR LATENCY LL_FLASH_SetLatency + * @param Latency This parameter can be one of the following values: + * @arg @ref LL_FLASH_LATENCY_0 + * @arg @ref LL_FLASH_LATENCY_1 + * @arg @ref LL_FLASH_LATENCY_2 + * @retval None + */ +__STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency) +{ + MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency); +} + +/** + * @brief Get FLASH Latency + * @rmtoll FLASH_ACR LATENCY LL_FLASH_GetLatency + * @retval Returned value can be one of the following values: + * @arg @ref LL_FLASH_LATENCY_0 + * @arg @ref LL_FLASH_LATENCY_1 + * @arg @ref LL_FLASH_LATENCY_2 + */ +__STATIC_INLINE uint32_t LL_FLASH_GetLatency(void) +{ + return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY)); +} + +/** + * @brief Enable Prefetch + * @rmtoll FLASH_ACR PRFTEN LL_FLASH_EnablePrefetch + * @retval None + */ +__STATIC_INLINE void LL_FLASH_EnablePrefetch(void) +{ +#if defined(CORE_CM0PLUS) + SET_BIT(FLASH->C2ACR, FLASH_C2ACR_PRFTEN); +#else + SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN); +#endif +} + +/** + * @brief Disable Prefetch + * @rmtoll FLASH_ACR PRFTEN LL_FLASH_DisablePrefetch + * @rmtoll FLASH_C2ACR PRFTEN LL_FLASH_DisablePrefetch + * @retval None + */ +__STATIC_INLINE void LL_FLASH_DisablePrefetch(void) +{ +#if defined(CORE_CM0PLUS) + CLEAR_BIT(FLASH->C2ACR, FLASH_C2ACR_PRFTEN); +#else + CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN); +#endif +} + +/** + * @brief Check if Prefetch buffer is enabled + * @rmtoll FLASH_ACR PRFTEN LL_FLASH_IsPrefetchEnabled + * @rmtoll FLASH_C2ACR C2PRFTEN LL_FLASH_IsPrefetchEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_FLASH_IsPrefetchEnabled(void) +{ +#if defined(CORE_CM0PLUS) + return ((READ_BIT(FLASH->C2ACR, FLASH_C2ACR_PRFTEN) == (FLASH_C2ACR_PRFTEN)) ? 1UL : 0UL); +#else + return ((READ_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) == (FLASH_ACR_PRFTEN)) ? 1UL : 0UL); +#endif +} + +/** + * @brief Enable Instruction cache + * @rmtoll FLASH_ACR ICEN LL_FLASH_EnableInstCache + * @rmtoll FLASH_C2ACR ICEN LL_FLASH_EnableInstCache + * @retval None + */ +__STATIC_INLINE void LL_FLASH_EnableInstCache(void) +{ +#if defined(CORE_CM0PLUS) + SET_BIT(FLASH->C2ACR, FLASH_C2ACR_ICEN); +#else + SET_BIT(FLASH->ACR, FLASH_ACR_ICEN); +#endif +} + +/** + * @brief Disable Instruction cache + * @rmtoll FLASH_ACR ICEN LL_FLASH_DisableInstCache + * @rmtoll FLASH_C2ACR ICEN LL_FLASH_DisableInstCache + * @retval None + */ +__STATIC_INLINE void LL_FLASH_DisableInstCache(void) +{ +#if defined(CORE_CM0PLUS) + CLEAR_BIT(FLASH->C2ACR, FLASH_C2ACR_ICEN); +#else + CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICEN); +#endif +} + +#if defined(CORE_CM0PLUS) +#else +/** + * @brief Enable Data cache + * @rmtoll FLASH_ACR DCEN LL_FLASH_EnableDataCache + * @retval None + */ +__STATIC_INLINE void LL_FLASH_EnableDataCache(void) +{ + SET_BIT(FLASH->ACR, FLASH_ACR_DCEN); +} + +/** + * @brief Disable Data cache + * @rmtoll FLASH_ACR DCEN LL_FLASH_DisableDataCache + * @retval None + */ +__STATIC_INLINE void LL_FLASH_DisableDataCache(void) +{ + CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCEN); +} +#endif + +/** + * @brief Enable Instruction cache reset + * @note bit can be written only when the instruction cache is disabled + * @rmtoll FLASH_ACR ICRST LL_FLASH_EnableInstCacheReset + * @rmtoll FLASH_C2ACR ICRST LL_FLASH_EnableInstCacheReset + * @retval None + */ +__STATIC_INLINE void LL_FLASH_EnableInstCacheReset(void) +{ +#if defined(CORE_CM0PLUS) + SET_BIT(FLASH->C2ACR, FLASH_C2ACR_ICRST); +#else + SET_BIT(FLASH->ACR, FLASH_ACR_ICRST); +#endif +} + +/** + * @brief Disable Instruction cache reset + * @rmtoll FLASH_ACR ICRST LL_FLASH_DisableInstCacheReset + * @rmtoll FLASH_C2ACR ICRST LL_FLASH_DisableInstCacheReset + * @retval None + */ +__STATIC_INLINE void LL_FLASH_DisableInstCacheReset(void) +{ +#if defined(CORE_CM0PLUS) + CLEAR_BIT(FLASH->C2ACR, FLASH_C2ACR_ICRST); +#else + CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICRST); +#endif +} + +#if defined(CORE_CM0PLUS) +#else +/** + * @brief Enable Data cache reset + * @note bit can be written only when the data cache is disabled + * @rmtoll FLASH_ACR DCRST LL_FLASH_EnableDataCacheReset + * @retval None + */ +__STATIC_INLINE void LL_FLASH_EnableDataCacheReset(void) +{ + SET_BIT(FLASH->ACR, FLASH_ACR_DCRST); +} + +/** + * @brief Disable Data cache reset + * @rmtoll FLASH_ACR DCRST LL_FLASH_DisableDataCacheReset + * @retval None + */ +__STATIC_INLINE void LL_FLASH_DisableDataCacheReset(void) +{ + CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCRST); +} +#endif + +/** + * @brief Suspend new program or erase operation request + * @note Any new Flash program and erase operation on both CPU side will be suspended + * until this bit and the same bit in Flash CPU2 access control register (FLASH_C2ACR) are + * cleared. The PESD bit in both the Flash status register (FLASH_SR) and Flash + * CPU2 status register (FLASH_C2SR) register will be set when at least one PES + * bit in FLASH_ACR or FLASH_C2ACR is set. + * @rmtoll FLASH_ACR PES LL_FLASH_SuspendOperation + * @rmtoll FLASH_C2ACR PES LL_FLASH_SuspendOperation + * @retval None + */ +__STATIC_INLINE void LL_FLASH_SuspendOperation(void) +{ +#if defined(CORE_CM0PLUS) + SET_BIT(FLASH->C2ACR, FLASH_C2ACR_PES); +#else + SET_BIT(FLASH->ACR, FLASH_ACR_PES); +#endif +} + +/** + * @brief Allow new program or erase operation request + * @note Any new Flash program and erase operation on both CPU side will be allowed + * until one of this bit or the same bit in Flash CPU2 access control register (FLASH_C2ACR) is + * set. The PESD bit in both the Flash status register (FLASH_SR) and Flash + * CPU2 status register (FLASH_C2SR) register will be clear when both PES + * bit in FLASH_ACR or FLASH_C2ACR is cleared. + * @rmtoll FLASH_ACR PES LL_FLASH_AllowOperation + * @rmtoll FLASH_C2ACR PES LL_FLASH_AllowOperation + * @retval None + */ +__STATIC_INLINE void LL_FLASH_AllowOperation(void) +{ +#if defined(CORE_CM0PLUS) + CLEAR_BIT(FLASH->C2ACR, FLASH_C2ACR_PES); +#else + CLEAR_BIT(FLASH->ACR, FLASH_ACR_PES); +#endif +} + +/** + * @brief Check if new program or erase operation request from CPU2 is suspended + * @rmtoll FLASH_ACR PES LL_FLASH_IsOperationSuspended + * @rmtoll FLASH_C2ACR PES LL_FLASH_IsOperationSuspended + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_FLASH_IsOperationSuspended(void) +{ +#if defined(CORE_CM0PLUS) + return ((READ_BIT(FLASH->C2ACR, FLASH_C2ACR_PES) == (FLASH_C2ACR_PES)) ? 1UL : 0UL); +#else + return ((READ_BIT(FLASH->ACR, FLASH_ACR_PES) == (FLASH_ACR_PES)) ? 1UL : 0UL); +#endif +} + +/** + * @brief Check if new program or erase operation request from CPU1 or CPU2 is suspended + * @rmtoll FLASH_SR PESD LL_FLASH_IsActiveFlag_OperationSuspended + * @rmtoll FLASH_C2SR PESD LL_FLASH_IsActiveFlag_OperationSuspended + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_FLASH_IsActiveFlag_OperationSuspended(void) +{ +#if defined(CORE_CM0PLUS) + return ((READ_BIT(FLASH->C2SR, FLASH_C2SR_PESD) == (FLASH_C2SR_PESD)) ? 1UL : 0UL); +#else + return ((READ_BIT(FLASH->SR, FLASH_SR_PESD) == (FLASH_SR_PESD)) ? 1UL : 0UL); +#endif +} + +/** + * @brief Set EMPTY flag information as Flash User area empty + * @rmtoll FLASH_ACR EMPTY LL_FLASH_SetEmptyFlag + * @retval None + */ +__STATIC_INLINE void LL_FLASH_SetEmptyFlag(void) +{ + SET_BIT(FLASH->ACR, FLASH_ACR_EMPTY); +} + +/** + * @brief Clear EMPTY flag information as Flash User area programmed + * @rmtoll FLASH_ACR EMPTY LL_FLASH_ClearEmptyFlag + * @retval None + */ +__STATIC_INLINE void LL_FLASH_ClearEmptyFlag(void) +{ + CLEAR_BIT(FLASH->ACR, FLASH_ACR_EMPTY); +} + +/** + * @brief Check if the EMPTY flag is set or reset + * @rmtoll FLASH_ACR EMPTY LL_FLASH_IsEmptyFlag + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_FLASH_IsEmptyFlag(void) +{ + return ((READ_BIT(FLASH->ACR, FLASH_ACR_EMPTY) == FLASH_ACR_EMPTY) ? 1UL : 0UL); +} + +#if defined(DUAL_CORE) +/** + * @brief Get IPCC buffer base address + * @rmtoll FLASH_IPCCBR IPCCDBA LL_FLASH_GetIPCCBufferAddr + * @retval IPCC data buffer base address offset + */ +__STATIC_INLINE uint32_t LL_FLASH_GetIPCCBufferAddr(void) +{ + return (uint32_t)(READ_BIT(FLASH->IPCCBR, FLASH_IPCCBR_IPCCDBA)); +} +#endif /* DUAL_CORE */ + +#if defined(DUAL_CORE) +/** + * @brief Get CPU2 boot reset vector + * @rmtoll FLASH_SRRVR SBRV LL_FLASH_GetC2BootResetVect + * @retval CPU2 boot reset vector + */ +__STATIC_INLINE uint32_t LL_FLASH_GetC2BootResetVect(void) +{ + return (uint32_t)(READ_BIT(FLASH->SRRVR, FLASH_SRRVR_SBRV)); +} +#endif /* DUAL_CORE */ + +/** + * @brief Return the Unique Device Number + * @retval Values between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_FLASH_GetUDN(void) +{ + return (READ_REG(*((uint32_t *)UID64_BASE))); +} + +/** + * @brief Return the Device ID + * For STM32WLxxxx devices, the device ID is 0x15 + * @retval Values between Min_Data=0x00 and Max_Data=0xFF (ex: Device ID is 0x15) + */ +__STATIC_INLINE uint32_t LL_FLASH_GetDeviceID(void) +{ + return ((READ_REG(*((uint32_t *)UID64_BASE + 1U))) & 0x000000FFU); +} + +/** + * @brief Return the ST Company ID + * @note For STM32WLxxxx devices, the ST Company ID is 0x0080E1 + * @retval Values between Min_Data=0x00 and Max_Data=0xFFFFFF (ex: ST Company ID is 0x0080E1) + */ +__STATIC_INLINE uint32_t LL_FLASH_GetSTCompanyID(void) +{ + return (((READ_REG(*((uint32_t *)UID64_BASE + 1U))) >> 8U) & 0x00FFFFFFU); +} +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) || defined (VREFBUF) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32WLxx_LL_SYSTEM_H */ diff --git a/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_usart.h b/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_usart.h new file mode 100644 index 0000000..766dad6 --- /dev/null +++ b/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_usart.h @@ -0,0 +1,4399 @@ +/** + ****************************************************************************** + * @file stm32wlxx_ll_usart.h + * @author MCD Application Team + * @brief Header file of USART LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32WLxx_LL_USART_H +#define STM32WLxx_LL_USART_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wlxx.h" + +/** @addtogroup STM32WLxx_LL_Driver + * @{ + */ + +#if defined(USART1) || defined(USART2) + +/** @defgroup USART_LL USART + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @defgroup USART_LL_Private_Variables USART Private Variables + * @{ + */ +/* Array used to get the USART prescaler division decimal values versus @ref USART_LL_EC_PRESCALER values */ +static const uint32_t USART_PRESCALER_TAB[] = +{ + 1UL, + 2UL, + 4UL, + 6UL, + 8UL, + 10UL, + 12UL, + 16UL, + 32UL, + 64UL, + 128UL, + 256UL +}; +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup USART_LL_Private_Constants USART Private Constants + * @{ + */ +/** + * @} + */ +/* Private macros ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup USART_LL_Private_Macros USART Private Macros + * @{ + */ +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup USART_LL_ES_INIT USART Exported Init structures + * @{ + */ + +/** + * @brief LL USART Init Structure definition + */ +typedef struct +{ + uint32_t PrescalerValue; /*!< Specifies the Prescaler to compute the communication baud rate. + This parameter can be a value of @ref USART_LL_EC_PRESCALER. + + This feature can be modified afterwards using unitary + function @ref LL_USART_SetPrescaler().*/ + + uint32_t BaudRate; /*!< This field defines expected Usart communication baud rate. + + This feature can be modified afterwards using unitary + function @ref LL_USART_SetBaudRate().*/ + + uint32_t DataWidth; /*!< Specifies the number of data bits transmitted or received in a frame. + This parameter can be a value of @ref USART_LL_EC_DATAWIDTH. + + This feature can be modified afterwards using unitary + function @ref LL_USART_SetDataWidth().*/ + + uint32_t StopBits; /*!< Specifies the number of stop bits transmitted. + This parameter can be a value of @ref USART_LL_EC_STOPBITS. + + This feature can be modified afterwards using unitary + function @ref LL_USART_SetStopBitsLength().*/ + + uint32_t Parity; /*!< Specifies the parity mode. + This parameter can be a value of @ref USART_LL_EC_PARITY. + + This feature can be modified afterwards using unitary + function @ref LL_USART_SetParity().*/ + + uint32_t TransferDirection; /*!< Specifies whether the Receive and/or Transmit mode is enabled or disabled. + This parameter can be a value of @ref USART_LL_EC_DIRECTION. + + This feature can be modified afterwards using unitary + function @ref LL_USART_SetTransferDirection().*/ + + uint32_t HardwareFlowControl; /*!< Specifies whether the hardware flow control mode is enabled or disabled. + This parameter can be a value of @ref USART_LL_EC_HWCONTROL. + + This feature can be modified afterwards using unitary + function @ref LL_USART_SetHWFlowCtrl().*/ + + uint32_t OverSampling; /*!< Specifies whether USART oversampling mode is 16 or 8. + This parameter can be a value of @ref USART_LL_EC_OVERSAMPLING. + + This feature can be modified afterwards using unitary + function @ref LL_USART_SetOverSampling().*/ + +} LL_USART_InitTypeDef; + +/** + * @brief LL USART Clock Init Structure definition + */ +typedef struct +{ + uint32_t ClockOutput; /*!< Specifies whether the USART clock is enabled or disabled. + This parameter can be a value of @ref USART_LL_EC_CLOCK. + + USART HW configuration can be modified afterwards using unitary functions + @ref LL_USART_EnableSCLKOutput() or @ref LL_USART_DisableSCLKOutput(). + For more details, refer to description of this function. */ + + uint32_t ClockPolarity; /*!< Specifies the steady state of the serial clock. + This parameter can be a value of @ref USART_LL_EC_POLARITY. + + USART HW configuration can be modified afterwards using unitary + functions @ref LL_USART_SetClockPolarity(). + For more details, refer to description of this function. */ + + uint32_t ClockPhase; /*!< Specifies the clock transition on which the bit capture is made. + This parameter can be a value of @ref USART_LL_EC_PHASE. + + USART HW configuration can be modified afterwards using unitary + functions @ref LL_USART_SetClockPhase(). + For more details, refer to description of this function. */ + + uint32_t LastBitClockPulse; /*!< Specifies whether the clock pulse corresponding to the last transmitted + data bit (MSB) has to be output on the SCLK pin in synchronous mode. + This parameter can be a value of @ref USART_LL_EC_LASTCLKPULSE. + + USART HW configuration can be modified afterwards using unitary + functions @ref LL_USART_SetLastClkPulseOutput(). + For more details, refer to description of this function. */ + +} LL_USART_ClockInitTypeDef; + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup USART_LL_Exported_Constants USART Exported Constants + * @{ + */ + +/** @defgroup USART_LL_EC_CLEAR_FLAG Clear Flags Defines + * @brief Flags defines which can be used with LL_USART_WriteReg function + * @{ + */ +#define LL_USART_ICR_PECF USART_ICR_PECF /*!< Parity error clear flag */ +#define LL_USART_ICR_FECF USART_ICR_FECF /*!< Framing error clear flag */ +#define LL_USART_ICR_NECF USART_ICR_NECF /*!< Noise error detected clear flag */ +#define LL_USART_ICR_ORECF USART_ICR_ORECF /*!< Overrun error clear flag */ +#define LL_USART_ICR_IDLECF USART_ICR_IDLECF /*!< Idle line detected clear flag */ +#define LL_USART_ICR_TXFECF USART_ICR_TXFECF /*!< TX FIFO Empty clear flag */ +#define LL_USART_ICR_TCCF USART_ICR_TCCF /*!< Transmission complete clear flag */ +#define LL_USART_ICR_TCBGTCF USART_ICR_TCBGTCF /*!< Transmission completed before guard time clear flag */ +#define LL_USART_ICR_LBDCF USART_ICR_LBDCF /*!< LIN break detection clear flag */ +#define LL_USART_ICR_CTSCF USART_ICR_CTSCF /*!< CTS clear flag */ +#define LL_USART_ICR_RTOCF USART_ICR_RTOCF /*!< Receiver timeout clear flag */ +#define LL_USART_ICR_EOBCF USART_ICR_EOBCF /*!< End of block clear flag */ +#define LL_USART_ICR_UDRCF USART_ICR_UDRCF /*!< SPI Slave Underrun clear flag */ +#define LL_USART_ICR_CMCF USART_ICR_CMCF /*!< Character match clear flag */ +#define LL_USART_ICR_WUCF USART_ICR_WUCF /*!< Wakeup from Stop mode clear flag */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_USART_ReadReg function + * @{ + */ +#define LL_USART_ISR_PE USART_ISR_PE /*!< Parity error flag */ +#define LL_USART_ISR_FE USART_ISR_FE /*!< Framing error flag */ +#define LL_USART_ISR_NE USART_ISR_NE /*!< Noise detected flag */ +#define LL_USART_ISR_ORE USART_ISR_ORE /*!< Overrun error flag */ +#define LL_USART_ISR_IDLE USART_ISR_IDLE /*!< Idle line detected flag */ +#define LL_USART_ISR_RXNE_RXFNE USART_ISR_RXNE_RXFNE /*!< Read data register or RX FIFO not empty flag */ +#define LL_USART_ISR_TC USART_ISR_TC /*!< Transmission complete flag */ +#define LL_USART_ISR_TXE_TXFNF USART_ISR_TXE_TXFNF /*!< Transmit data register empty or TX FIFO Not Full flag*/ +#define LL_USART_ISR_LBDF USART_ISR_LBDF /*!< LIN break detection flag */ +#define LL_USART_ISR_CTSIF USART_ISR_CTSIF /*!< CTS interrupt flag */ +#define LL_USART_ISR_CTS USART_ISR_CTS /*!< CTS flag */ +#define LL_USART_ISR_RTOF USART_ISR_RTOF /*!< Receiver timeout flag */ +#define LL_USART_ISR_EOBF USART_ISR_EOBF /*!< End of block flag */ +#define LL_USART_ISR_UDR USART_ISR_UDR /*!< SPI Slave underrun error flag */ +#define LL_USART_ISR_ABRE USART_ISR_ABRE /*!< Auto baud rate error flag */ +#define LL_USART_ISR_ABRF USART_ISR_ABRF /*!< Auto baud rate flag */ +#define LL_USART_ISR_BUSY USART_ISR_BUSY /*!< Busy flag */ +#define LL_USART_ISR_CMF USART_ISR_CMF /*!< Character match flag */ +#define LL_USART_ISR_SBKF USART_ISR_SBKF /*!< Send break flag */ +#define LL_USART_ISR_RWU USART_ISR_RWU /*!< Receiver wakeup from Mute mode flag */ +#define LL_USART_ISR_WUF USART_ISR_WUF /*!< Wakeup from Stop mode flag */ +#define LL_USART_ISR_TEACK USART_ISR_TEACK /*!< Transmit enable acknowledge flag */ +#define LL_USART_ISR_REACK USART_ISR_REACK /*!< Receive enable acknowledge flag */ +#define LL_USART_ISR_TXFE USART_ISR_TXFE /*!< TX FIFO empty flag */ +#define LL_USART_ISR_RXFF USART_ISR_RXFF /*!< RX FIFO full flag */ +#define LL_USART_ISR_TCBGT USART_ISR_TCBGT /*!< Transmission complete before guard time completion flag */ +#define LL_USART_ISR_RXFT USART_ISR_RXFT /*!< RX FIFO threshold flag */ +#define LL_USART_ISR_TXFT USART_ISR_TXFT /*!< TX FIFO threshold flag */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_USART_ReadReg and LL_USART_WriteReg functions + * @{ + */ +#define LL_USART_CR1_IDLEIE USART_CR1_IDLEIE /*!< IDLE interrupt enable */ +#define LL_USART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_RXFNEIE /*!< Read data register and RXFIFO not empty interrupt enable */ +#define LL_USART_CR1_TCIE USART_CR1_TCIE /*!< Transmission complete interrupt enable */ +#define LL_USART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_TXFNFIE /*!< Transmit data register empty and TX FIFO not full interrupt enable */ +#define LL_USART_CR1_PEIE USART_CR1_PEIE /*!< Parity error */ +#define LL_USART_CR1_CMIE USART_CR1_CMIE /*!< Character match interrupt enable */ +#define LL_USART_CR1_RTOIE USART_CR1_RTOIE /*!< Receiver timeout interrupt enable */ +#define LL_USART_CR1_EOBIE USART_CR1_EOBIE /*!< End of Block interrupt enable */ +#define LL_USART_CR1_TXFEIE USART_CR1_TXFEIE /*!< TX FIFO empty interrupt enable */ +#define LL_USART_CR1_RXFFIE USART_CR1_RXFFIE /*!< RX FIFO full interrupt enable */ +#define LL_USART_CR2_LBDIE USART_CR2_LBDIE /*!< LIN break detection interrupt enable */ +#define LL_USART_CR3_EIE USART_CR3_EIE /*!< Error interrupt enable */ +#define LL_USART_CR3_CTSIE USART_CR3_CTSIE /*!< CTS interrupt enable */ +#define LL_USART_CR3_WUFIE USART_CR3_WUFIE /*!< Wakeup from Stop mode interrupt enable */ +#define LL_USART_CR3_TXFTIE USART_CR3_TXFTIE /*!< TX FIFO threshold interrupt enable */ +#define LL_USART_CR3_TCBGTIE USART_CR3_TCBGTIE /*!< Transmission complete before guard time interrupt enable */ +#define LL_USART_CR3_RXFTIE USART_CR3_RXFTIE /*!< RX FIFO threshold interrupt enable */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_FIFOTHRESHOLD FIFO Threshold + * @{ + */ +#define LL_USART_FIFOTHRESHOLD_1_8 0x00000000U /*!< FIFO reaches 1/8 of its depth */ +#define LL_USART_FIFOTHRESHOLD_1_4 0x00000001U /*!< FIFO reaches 1/4 of its depth */ +#define LL_USART_FIFOTHRESHOLD_1_2 0x00000002U /*!< FIFO reaches 1/2 of its depth */ +#define LL_USART_FIFOTHRESHOLD_3_4 0x00000003U /*!< FIFO reaches 3/4 of its depth */ +#define LL_USART_FIFOTHRESHOLD_7_8 0x00000004U /*!< FIFO reaches 7/8 of its depth */ +#define LL_USART_FIFOTHRESHOLD_8_8 0x00000005U /*!< FIFO becomes empty for TX and full for RX */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_DIRECTION Communication Direction + * @{ + */ +#define LL_USART_DIRECTION_NONE 0x00000000U /*!< Transmitter and Receiver are disabled */ +#define LL_USART_DIRECTION_RX USART_CR1_RE /*!< Transmitter is disabled and Receiver is enabled */ +#define LL_USART_DIRECTION_TX USART_CR1_TE /*!< Transmitter is enabled and Receiver is disabled */ +#define LL_USART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< Transmitter and Receiver are enabled */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_PARITY Parity Control + * @{ + */ +#define LL_USART_PARITY_NONE 0x00000000U /*!< Parity control disabled */ +#define LL_USART_PARITY_EVEN USART_CR1_PCE /*!< Parity control enabled and Even Parity is selected */ +#define LL_USART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Parity control enabled and Odd Parity is selected */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_WAKEUP Wakeup + * @{ + */ +#define LL_USART_WAKEUP_IDLELINE 0x00000000U /*!< USART wake up from Mute mode on Idle Line */ +#define LL_USART_WAKEUP_ADDRESSMARK USART_CR1_WAKE /*!< USART wake up from Mute mode on Address Mark */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_DATAWIDTH Datawidth + * @{ + */ +#define LL_USART_DATAWIDTH_7B USART_CR1_M1 /*!< 7 bits word length : Start bit, 7 data bits, n stop bits */ +#define LL_USART_DATAWIDTH_8B 0x00000000U /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */ +#define LL_USART_DATAWIDTH_9B USART_CR1_M0 /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_OVERSAMPLING Oversampling + * @{ + */ +#define LL_USART_OVERSAMPLING_16 0x00000000U /*!< Oversampling by 16 */ +#define LL_USART_OVERSAMPLING_8 USART_CR1_OVER8 /*!< Oversampling by 8 */ +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup USART_LL_EC_CLOCK Clock Signal + * @{ + */ + +#define LL_USART_CLOCK_DISABLE 0x00000000U /*!< Clock signal not provided */ +#define LL_USART_CLOCK_ENABLE USART_CR2_CLKEN /*!< Clock signal provided */ +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/** @defgroup USART_LL_EC_LASTCLKPULSE Last Clock Pulse + * @{ + */ +#define LL_USART_LASTCLKPULSE_NO_OUTPUT 0x00000000U /*!< The clock pulse of the last data bit is not output to the SCLK pin */ +#define LL_USART_LASTCLKPULSE_OUTPUT USART_CR2_LBCL /*!< The clock pulse of the last data bit is output to the SCLK pin */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_PHASE Clock Phase + * @{ + */ +#define LL_USART_PHASE_1EDGE 0x00000000U /*!< The first clock transition is the first data capture edge */ +#define LL_USART_PHASE_2EDGE USART_CR2_CPHA /*!< The second clock transition is the first data capture edge */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_POLARITY Clock Polarity + * @{ + */ +#define LL_USART_POLARITY_LOW 0x00000000U /*!< Steady low value on SCLK pin outside transmission window*/ +#define LL_USART_POLARITY_HIGH USART_CR2_CPOL /*!< Steady high value on SCLK pin outside transmission window */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_PRESCALER Clock Source Prescaler + * @{ + */ +#define LL_USART_PRESCALER_DIV1 0x00000000U /*!< Input clock not divided */ +#define LL_USART_PRESCALER_DIV2 (USART_PRESC_PRESCALER_0) /*!< Input clock divided by 2 */ +#define LL_USART_PRESCALER_DIV4 (USART_PRESC_PRESCALER_1) /*!< Input clock divided by 4 */ +#define LL_USART_PRESCALER_DIV6 (USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 6 */ +#define LL_USART_PRESCALER_DIV8 (USART_PRESC_PRESCALER_2) /*!< Input clock divided by 8 */ +#define LL_USART_PRESCALER_DIV10 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 10 */ +#define LL_USART_PRESCALER_DIV12 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1) /*!< Input clock divided by 12 */ +#define LL_USART_PRESCALER_DIV16 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 16 */ +#define LL_USART_PRESCALER_DIV32 (USART_PRESC_PRESCALER_3) /*!< Input clock divided by 32 */ +#define LL_USART_PRESCALER_DIV64 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 64 */ +#define LL_USART_PRESCALER_DIV128 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1) /*!< Input clock divided by 128 */ +#define LL_USART_PRESCALER_DIV256 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 256 */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_STOPBITS Stop Bits + * @{ + */ +#define LL_USART_STOPBITS_0_5 USART_CR2_STOP_0 /*!< 0.5 stop bit */ +#define LL_USART_STOPBITS_1 0x00000000U /*!< 1 stop bit */ +#define LL_USART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1) /*!< 1.5 stop bits */ +#define LL_USART_STOPBITS_2 USART_CR2_STOP_1 /*!< 2 stop bits */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_TXRX TX RX Pins Swap + * @{ + */ +#define LL_USART_TXRX_STANDARD 0x00000000U /*!< TX/RX pins are used as defined in standard pinout */ +#define LL_USART_TXRX_SWAPPED (USART_CR2_SWAP) /*!< TX and RX pins functions are swapped. */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_RXPIN_LEVEL RX Pin Active Level Inversion + * @{ + */ +#define LL_USART_RXPIN_LEVEL_STANDARD 0x00000000U /*!< RX pin signal works using the standard logic levels */ +#define LL_USART_RXPIN_LEVEL_INVERTED (USART_CR2_RXINV) /*!< RX pin signal values are inverted. */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_TXPIN_LEVEL TX Pin Active Level Inversion + * @{ + */ +#define LL_USART_TXPIN_LEVEL_STANDARD 0x00000000U /*!< TX pin signal works using the standard logic levels */ +#define LL_USART_TXPIN_LEVEL_INVERTED (USART_CR2_TXINV) /*!< TX pin signal values are inverted. */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_BINARY_LOGIC Binary Data Inversion + * @{ + */ +#define LL_USART_BINARY_LOGIC_POSITIVE 0x00000000U /*!< Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L) */ +#define LL_USART_BINARY_LOGIC_NEGATIVE USART_CR2_DATAINV /*!< Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted. */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_BITORDER Bit Order + * @{ + */ +#define LL_USART_BITORDER_LSBFIRST 0x00000000U /*!< data is transmitted/received with data bit 0 first, following the start bit */ +#define LL_USART_BITORDER_MSBFIRST USART_CR2_MSBFIRST /*!< data is transmitted/received with the MSB first, following the start bit */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_AUTOBAUD_DETECT_ON Autobaud Detection + * @{ + */ +#define LL_USART_AUTOBAUD_DETECT_ON_STARTBIT 0x00000000U /*!< Measurement of the start bit is used to detect the baud rate */ +#define LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE USART_CR2_ABRMODE_0 /*!< Falling edge to falling edge measurement. Received frame must start with a single bit = 1 -> Frame = Start10xxxxxx */ +#define LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME USART_CR2_ABRMODE_1 /*!< 0x7F frame detection */ +#define LL_USART_AUTOBAUD_DETECT_ON_55_FRAME (USART_CR2_ABRMODE_1 | USART_CR2_ABRMODE_0) /*!< 0x55 frame detection */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_ADDRESS_DETECT Address Length Detection + * @{ + */ +#define LL_USART_ADDRESS_DETECT_4B 0x00000000U /*!< 4-bit address detection method selected */ +#define LL_USART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit address detection (in 8-bit data mode) method selected */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_HWCONTROL Hardware Control + * @{ + */ +#define LL_USART_HWCONTROL_NONE 0x00000000U /*!< CTS and RTS hardware flow control disabled */ +#define LL_USART_HWCONTROL_RTS USART_CR3_RTSE /*!< RTS output enabled, data is only requested when there is space in the receive buffer */ +#define LL_USART_HWCONTROL_CTS USART_CR3_CTSE /*!< CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0) */ +#define LL_USART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) /*!< CTS and RTS hardware flow control enabled */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_WAKEUP_ON Wakeup Activation + * @{ + */ +#define LL_USART_WAKEUP_ON_ADDRESS 0x00000000U /*!< Wake up active on address match */ +#define LL_USART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1 /*!< Wake up active on Start bit detection */ +#define LL_USART_WAKEUP_ON_RXNE (USART_CR3_WUS_0 | USART_CR3_WUS_1) /*!< Wake up active on RXNE */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_IRDA_POWER IrDA Power + * @{ + */ +#define LL_USART_IRDA_POWER_NORMAL 0x00000000U /*!< IrDA normal power mode */ +#define LL_USART_IRDA_POWER_LOW USART_CR3_IRLP /*!< IrDA low power mode */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_LINBREAK_DETECT LIN Break Detection Length + * @{ + */ +#define LL_USART_LINBREAK_DETECT_10B 0x00000000U /*!< 10-bit break detection method selected */ +#define LL_USART_LINBREAK_DETECT_11B USART_CR2_LBDL /*!< 11-bit break detection method selected */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_DE_POLARITY Driver Enable Polarity + * @{ + */ +#define LL_USART_DE_POLARITY_HIGH 0x00000000U /*!< DE signal is active high */ +#define LL_USART_DE_POLARITY_LOW USART_CR3_DEP /*!< DE signal is active low */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_DMA_REG_DATA DMA Register Data + * @{ + */ +#define LL_USART_DMA_REG_DATA_TRANSMIT 0x00000000U /*!< Get address of data register used for transmission */ +#define LL_USART_DMA_REG_DATA_RECEIVE 0x00000001U /*!< Get address of data register used for reception */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup USART_LL_Exported_Macros USART Exported Macros + * @{ + */ + +/** @defgroup USART_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in USART register + * @param __INSTANCE__ USART Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_USART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in USART register + * @param __INSTANCE__ USART Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_USART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** @defgroup USART_LL_EM_Exported_Macros_Helper Exported_Macros_Helper + * @{ + */ + +/** + * @brief Compute USARTDIV value according to Peripheral Clock and + * expected Baud Rate in 8 bits sampling mode (32 bits value of USARTDIV is returned) + * @param __PERIPHCLK__ Peripheral Clock frequency used for USART instance + * @param __PRESCALER__ This parameter can be one of the following values: + * @arg @ref LL_USART_PRESCALER_DIV1 + * @arg @ref LL_USART_PRESCALER_DIV2 + * @arg @ref LL_USART_PRESCALER_DIV4 + * @arg @ref LL_USART_PRESCALER_DIV6 + * @arg @ref LL_USART_PRESCALER_DIV8 + * @arg @ref LL_USART_PRESCALER_DIV10 + * @arg @ref LL_USART_PRESCALER_DIV12 + * @arg @ref LL_USART_PRESCALER_DIV16 + * @arg @ref LL_USART_PRESCALER_DIV32 + * @arg @ref LL_USART_PRESCALER_DIV64 + * @arg @ref LL_USART_PRESCALER_DIV128 + * @arg @ref LL_USART_PRESCALER_DIV256 + * @param __BAUDRATE__ Baud rate value to achieve + * @retval USARTDIV value to be used for BRR register filling in OverSampling_8 case + */ +#define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) \ + (((((__PERIPHCLK__)/(USART_PRESCALER_TAB[(__PRESCALER__)]))*2U)\ + + ((__BAUDRATE__)/2U))/(__BAUDRATE__)) + +/** + * @brief Compute USARTDIV value according to Peripheral Clock and + * expected Baud Rate in 16 bits sampling mode (32 bits value of USARTDIV is returned) + * @param __PERIPHCLK__ Peripheral Clock frequency used for USART instance + * @param __PRESCALER__ This parameter can be one of the following values: + * @arg @ref LL_USART_PRESCALER_DIV1 + * @arg @ref LL_USART_PRESCALER_DIV2 + * @arg @ref LL_USART_PRESCALER_DIV4 + * @arg @ref LL_USART_PRESCALER_DIV6 + * @arg @ref LL_USART_PRESCALER_DIV8 + * @arg @ref LL_USART_PRESCALER_DIV10 + * @arg @ref LL_USART_PRESCALER_DIV12 + * @arg @ref LL_USART_PRESCALER_DIV16 + * @arg @ref LL_USART_PRESCALER_DIV32 + * @arg @ref LL_USART_PRESCALER_DIV64 + * @arg @ref LL_USART_PRESCALER_DIV128 + * @arg @ref LL_USART_PRESCALER_DIV256 + * @param __BAUDRATE__ Baud rate value to achieve + * @retval USARTDIV value to be used for BRR register filling in OverSampling_16 case + */ +#define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) \ + ((((__PERIPHCLK__)/(USART_PRESCALER_TAB[(__PRESCALER__)]))\ + + ((__BAUDRATE__)/2U))/(__BAUDRATE__)) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup USART_LL_Exported_Functions USART Exported Functions + * @{ + */ + +/** @defgroup USART_LL_EF_Configuration Configuration functions + * @{ + */ + +/** + * @brief USART Enable + * @rmtoll CR1 UE LL_USART_Enable + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_Enable(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR1, USART_CR1_UE); +} + +/** + * @brief USART Disable (all USART prescalers and outputs are disabled) + * @note When USART is disabled, USART prescalers and outputs are stopped immediately, + * and current operations are discarded. The configuration of the USART is kept, but all the status + * flags, in the USARTx_ISR are set to their default values. + * @rmtoll CR1 UE LL_USART_Disable + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_Disable(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR1, USART_CR1_UE); +} + +/** + * @brief Indicate if USART is enabled + * @rmtoll CR1 UE LL_USART_IsEnabled + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabled(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)) ? 1UL : 0UL); +} + +/** + * @brief FIFO Mode Enable + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR1 FIFOEN LL_USART_EnableFIFO + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableFIFO(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR1, USART_CR1_FIFOEN); +} + +/** + * @brief FIFO Mode Disable + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR1 FIFOEN LL_USART_DisableFIFO + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableFIFO(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR1, USART_CR1_FIFOEN); +} + +/** + * @brief Indicate if FIFO Mode is enabled + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR1 FIFOEN LL_USART_IsEnabledFIFO + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledFIFO(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR1, USART_CR1_FIFOEN) == (USART_CR1_FIFOEN)) ? 1UL : 0UL); +} + +/** + * @brief Configure TX FIFO Threshold + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR3 TXFTCFG LL_USART_SetTXFIFOThreshold + * @param USARTx USART Instance + * @param Threshold This parameter can be one of the following values: + * @arg @ref LL_USART_FIFOTHRESHOLD_1_8 + * @arg @ref LL_USART_FIFOTHRESHOLD_1_4 + * @arg @ref LL_USART_FIFOTHRESHOLD_1_2 + * @arg @ref LL_USART_FIFOTHRESHOLD_3_4 + * @arg @ref LL_USART_FIFOTHRESHOLD_7_8 + * @arg @ref LL_USART_FIFOTHRESHOLD_8_8 + * @retval None + */ +__STATIC_INLINE void LL_USART_SetTXFIFOThreshold(USART_TypeDef *USARTx, uint32_t Threshold) +{ + ATOMIC_MODIFY_REG(USARTx->CR3, USART_CR3_TXFTCFG, Threshold << USART_CR3_TXFTCFG_Pos); +} + +/** + * @brief Return TX FIFO Threshold Configuration + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR3 TXFTCFG LL_USART_GetTXFIFOThreshold + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_FIFOTHRESHOLD_1_8 + * @arg @ref LL_USART_FIFOTHRESHOLD_1_4 + * @arg @ref LL_USART_FIFOTHRESHOLD_1_2 + * @arg @ref LL_USART_FIFOTHRESHOLD_3_4 + * @arg @ref LL_USART_FIFOTHRESHOLD_7_8 + * @arg @ref LL_USART_FIFOTHRESHOLD_8_8 + */ +__STATIC_INLINE uint32_t LL_USART_GetTXFIFOThreshold(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos); +} + +/** + * @brief Configure RX FIFO Threshold + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR3 RXFTCFG LL_USART_SetRXFIFOThreshold + * @param USARTx USART Instance + * @param Threshold This parameter can be one of the following values: + * @arg @ref LL_USART_FIFOTHRESHOLD_1_8 + * @arg @ref LL_USART_FIFOTHRESHOLD_1_4 + * @arg @ref LL_USART_FIFOTHRESHOLD_1_2 + * @arg @ref LL_USART_FIFOTHRESHOLD_3_4 + * @arg @ref LL_USART_FIFOTHRESHOLD_7_8 + * @arg @ref LL_USART_FIFOTHRESHOLD_8_8 + * @retval None + */ +__STATIC_INLINE void LL_USART_SetRXFIFOThreshold(USART_TypeDef *USARTx, uint32_t Threshold) +{ + ATOMIC_MODIFY_REG(USARTx->CR3, USART_CR3_RXFTCFG, Threshold << USART_CR3_RXFTCFG_Pos); +} + +/** + * @brief Return RX FIFO Threshold Configuration + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR3 RXFTCFG LL_USART_GetRXFIFOThreshold + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_FIFOTHRESHOLD_1_8 + * @arg @ref LL_USART_FIFOTHRESHOLD_1_4 + * @arg @ref LL_USART_FIFOTHRESHOLD_1_2 + * @arg @ref LL_USART_FIFOTHRESHOLD_3_4 + * @arg @ref LL_USART_FIFOTHRESHOLD_7_8 + * @arg @ref LL_USART_FIFOTHRESHOLD_8_8 + */ +__STATIC_INLINE uint32_t LL_USART_GetRXFIFOThreshold(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos); +} + +/** + * @brief Configure TX and RX FIFOs Threshold + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR3 TXFTCFG LL_USART_ConfigFIFOsThreshold\n + * CR3 RXFTCFG LL_USART_ConfigFIFOsThreshold + * @param USARTx USART Instance + * @param TXThreshold This parameter can be one of the following values: + * @arg @ref LL_USART_FIFOTHRESHOLD_1_8 + * @arg @ref LL_USART_FIFOTHRESHOLD_1_4 + * @arg @ref LL_USART_FIFOTHRESHOLD_1_2 + * @arg @ref LL_USART_FIFOTHRESHOLD_3_4 + * @arg @ref LL_USART_FIFOTHRESHOLD_7_8 + * @arg @ref LL_USART_FIFOTHRESHOLD_8_8 + * @param RXThreshold This parameter can be one of the following values: + * @arg @ref LL_USART_FIFOTHRESHOLD_1_8 + * @arg @ref LL_USART_FIFOTHRESHOLD_1_4 + * @arg @ref LL_USART_FIFOTHRESHOLD_1_2 + * @arg @ref LL_USART_FIFOTHRESHOLD_3_4 + * @arg @ref LL_USART_FIFOTHRESHOLD_7_8 + * @arg @ref LL_USART_FIFOTHRESHOLD_8_8 + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigFIFOsThreshold(USART_TypeDef *USARTx, uint32_t TXThreshold, uint32_t RXThreshold) +{ + ATOMIC_MODIFY_REG(USARTx->CR3, USART_CR3_TXFTCFG | USART_CR3_RXFTCFG, (TXThreshold << USART_CR3_TXFTCFG_Pos) | + (RXThreshold << USART_CR3_RXFTCFG_Pos)); +} + +/** + * @brief USART enabled in STOP Mode. + * @note When this function is enabled, USART is able to wake up the MCU from Stop mode, provided that + * USART clock selection is HSI or LSE in RCC. + * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + * Wake-up from Stop mode feature is supported by the USARTx instance. + * @rmtoll CR1 UESM LL_USART_EnableInStopMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableInStopMode(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_UESM); +} + +/** + * @brief USART disabled in STOP Mode. + * @note When this function is disabled, USART is not able to wake up the MCU from Stop mode + * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + * Wake-up from Stop mode feature is supported by the USARTx instance. + * @rmtoll CR1 UESM LL_USART_DisableInStopMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableInStopMode(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_UESM); +} + +/** + * @brief Indicate if USART is enabled in STOP Mode (able to wake up MCU from Stop mode or not) + * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + * Wake-up from Stop mode feature is supported by the USARTx instance. + * @rmtoll CR1 UESM LL_USART_IsEnabledInStopMode + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledInStopMode(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM)) ? 1UL : 0UL); +} + +/** + * @brief Receiver Enable (Receiver is enabled and begins searching for a start bit) + * @rmtoll CR1 RE LL_USART_EnableDirectionRx + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableDirectionRx(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RE); +} + +/** + * @brief Receiver Disable + * @rmtoll CR1 RE LL_USART_DisableDirectionRx + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableDirectionRx(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RE); +} + +/** + * @brief Transmitter Enable + * @rmtoll CR1 TE LL_USART_EnableDirectionTx + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableDirectionTx(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TE); +} + +/** + * @brief Transmitter Disable + * @rmtoll CR1 TE LL_USART_DisableDirectionTx + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableDirectionTx(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TE); +} + +/** + * @brief Configure simultaneously enabled/disabled states + * of Transmitter and Receiver + * @rmtoll CR1 RE LL_USART_SetTransferDirection\n + * CR1 TE LL_USART_SetTransferDirection + * @param USARTx USART Instance + * @param TransferDirection This parameter can be one of the following values: + * @arg @ref LL_USART_DIRECTION_NONE + * @arg @ref LL_USART_DIRECTION_RX + * @arg @ref LL_USART_DIRECTION_TX + * @arg @ref LL_USART_DIRECTION_TX_RX + * @retval None + */ +__STATIC_INLINE void LL_USART_SetTransferDirection(USART_TypeDef *USARTx, uint32_t TransferDirection) +{ + ATOMIC_MODIFY_REG(USARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection); +} + +/** + * @brief Return enabled/disabled states of Transmitter and Receiver + * @rmtoll CR1 RE LL_USART_GetTransferDirection\n + * CR1 TE LL_USART_GetTransferDirection + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_DIRECTION_NONE + * @arg @ref LL_USART_DIRECTION_RX + * @arg @ref LL_USART_DIRECTION_TX + * @arg @ref LL_USART_DIRECTION_TX_RX + */ +__STATIC_INLINE uint32_t LL_USART_GetTransferDirection(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_RE | USART_CR1_TE)); +} + +/** + * @brief Configure Parity (enabled/disabled and parity mode if enabled). + * @note This function selects if hardware parity control (generation and detection) is enabled or disabled. + * When the parity control is enabled (Odd or Even), computed parity bit is inserted at the MSB position + * (9th or 8th bit depending on data width) and parity is checked on the received data. + * @rmtoll CR1 PS LL_USART_SetParity\n + * CR1 PCE LL_USART_SetParity + * @param USARTx USART Instance + * @param Parity This parameter can be one of the following values: + * @arg @ref LL_USART_PARITY_NONE + * @arg @ref LL_USART_PARITY_EVEN + * @arg @ref LL_USART_PARITY_ODD + * @retval None + */ +__STATIC_INLINE void LL_USART_SetParity(USART_TypeDef *USARTx, uint32_t Parity) +{ + MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE, Parity); +} + +/** + * @brief Return Parity configuration (enabled/disabled and parity mode if enabled) + * @rmtoll CR1 PS LL_USART_GetParity\n + * CR1 PCE LL_USART_GetParity + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_PARITY_NONE + * @arg @ref LL_USART_PARITY_EVEN + * @arg @ref LL_USART_PARITY_ODD + */ +__STATIC_INLINE uint32_t LL_USART_GetParity(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE)); +} + +/** + * @brief Set Receiver Wake Up method from Mute mode. + * @rmtoll CR1 WAKE LL_USART_SetWakeUpMethod + * @param USARTx USART Instance + * @param Method This parameter can be one of the following values: + * @arg @ref LL_USART_WAKEUP_IDLELINE + * @arg @ref LL_USART_WAKEUP_ADDRESSMARK + * @retval None + */ +__STATIC_INLINE void LL_USART_SetWakeUpMethod(USART_TypeDef *USARTx, uint32_t Method) +{ + MODIFY_REG(USARTx->CR1, USART_CR1_WAKE, Method); +} + +/** + * @brief Return Receiver Wake Up method from Mute mode + * @rmtoll CR1 WAKE LL_USART_GetWakeUpMethod + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_WAKEUP_IDLELINE + * @arg @ref LL_USART_WAKEUP_ADDRESSMARK + */ +__STATIC_INLINE uint32_t LL_USART_GetWakeUpMethod(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_WAKE)); +} + +/** + * @brief Set Word length (i.e. nb of data bits, excluding start and stop bits) + * @rmtoll CR1 M0 LL_USART_SetDataWidth\n + * CR1 M1 LL_USART_SetDataWidth + * @param USARTx USART Instance + * @param DataWidth This parameter can be one of the following values: + * @arg @ref LL_USART_DATAWIDTH_7B + * @arg @ref LL_USART_DATAWIDTH_8B + * @arg @ref LL_USART_DATAWIDTH_9B + * @retval None + */ +__STATIC_INLINE void LL_USART_SetDataWidth(USART_TypeDef *USARTx, uint32_t DataWidth) +{ + MODIFY_REG(USARTx->CR1, USART_CR1_M, DataWidth); +} + +/** + * @brief Return Word length (i.e. nb of data bits, excluding start and stop bits) + * @rmtoll CR1 M0 LL_USART_GetDataWidth\n + * CR1 M1 LL_USART_GetDataWidth + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_DATAWIDTH_7B + * @arg @ref LL_USART_DATAWIDTH_8B + * @arg @ref LL_USART_DATAWIDTH_9B + */ +__STATIC_INLINE uint32_t LL_USART_GetDataWidth(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_M)); +} + +/** + * @brief Allow switch between Mute Mode and Active mode + * @rmtoll CR1 MME LL_USART_EnableMuteMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableMuteMode(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_MME); +} + +/** + * @brief Prevent Mute Mode use. Set Receiver in active mode permanently. + * @rmtoll CR1 MME LL_USART_DisableMuteMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableMuteMode(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_MME); +} + +/** + * @brief Indicate if switch between Mute Mode and Active mode is allowed + * @rmtoll CR1 MME LL_USART_IsEnabledMuteMode + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledMuteMode(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR1, USART_CR1_MME) == (USART_CR1_MME)) ? 1UL : 0UL); +} + +/** + * @brief Set Oversampling to 8-bit or 16-bit mode + * @rmtoll CR1 OVER8 LL_USART_SetOverSampling + * @param USARTx USART Instance + * @param OverSampling This parameter can be one of the following values: + * @arg @ref LL_USART_OVERSAMPLING_16 + * @arg @ref LL_USART_OVERSAMPLING_8 + * @retval None + */ +__STATIC_INLINE void LL_USART_SetOverSampling(USART_TypeDef *USARTx, uint32_t OverSampling) +{ + MODIFY_REG(USARTx->CR1, USART_CR1_OVER8, OverSampling); +} + +/** + * @brief Return Oversampling mode + * @rmtoll CR1 OVER8 LL_USART_GetOverSampling + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_OVERSAMPLING_16 + * @arg @ref LL_USART_OVERSAMPLING_8 + */ +__STATIC_INLINE uint32_t LL_USART_GetOverSampling(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_OVER8)); +} + +/** + * @brief Configure if Clock pulse of the last data bit is output to the SCLK pin or not + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @rmtoll CR2 LBCL LL_USART_SetLastClkPulseOutput + * @param USARTx USART Instance + * @param LastBitClockPulse This parameter can be one of the following values: + * @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT + * @arg @ref LL_USART_LASTCLKPULSE_OUTPUT + * @retval None + */ +__STATIC_INLINE void LL_USART_SetLastClkPulseOutput(USART_TypeDef *USARTx, uint32_t LastBitClockPulse) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_LBCL, LastBitClockPulse); +} + +/** + * @brief Retrieve Clock pulse of the last data bit output configuration + * (Last bit Clock pulse output to the SCLK pin or not) + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @rmtoll CR2 LBCL LL_USART_GetLastClkPulseOutput + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT + * @arg @ref LL_USART_LASTCLKPULSE_OUTPUT + */ +__STATIC_INLINE uint32_t LL_USART_GetLastClkPulseOutput(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBCL)); +} + +/** + * @brief Select the phase of the clock output on the SCLK pin in synchronous mode + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @rmtoll CR2 CPHA LL_USART_SetClockPhase + * @param USARTx USART Instance + * @param ClockPhase This parameter can be one of the following values: + * @arg @ref LL_USART_PHASE_1EDGE + * @arg @ref LL_USART_PHASE_2EDGE + * @retval None + */ +__STATIC_INLINE void LL_USART_SetClockPhase(USART_TypeDef *USARTx, uint32_t ClockPhase) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_CPHA, ClockPhase); +} + +/** + * @brief Return phase of the clock output on the SCLK pin in synchronous mode + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @rmtoll CR2 CPHA LL_USART_GetClockPhase + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_PHASE_1EDGE + * @arg @ref LL_USART_PHASE_2EDGE + */ +__STATIC_INLINE uint32_t LL_USART_GetClockPhase(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPHA)); +} + +/** + * @brief Select the polarity of the clock output on the SCLK pin in synchronous mode + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @rmtoll CR2 CPOL LL_USART_SetClockPolarity + * @param USARTx USART Instance + * @param ClockPolarity This parameter can be one of the following values: + * @arg @ref LL_USART_POLARITY_LOW + * @arg @ref LL_USART_POLARITY_HIGH + * @retval None + */ +__STATIC_INLINE void LL_USART_SetClockPolarity(USART_TypeDef *USARTx, uint32_t ClockPolarity) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_CPOL, ClockPolarity); +} + +/** + * @brief Return polarity of the clock output on the SCLK pin in synchronous mode + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @rmtoll CR2 CPOL LL_USART_GetClockPolarity + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_POLARITY_LOW + * @arg @ref LL_USART_POLARITY_HIGH + */ +__STATIC_INLINE uint32_t LL_USART_GetClockPolarity(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPOL)); +} + +/** + * @brief Configure Clock signal format (Phase Polarity and choice about output of last bit clock pulse) + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @note Call of this function is equivalent to following function call sequence : + * - Clock Phase configuration using @ref LL_USART_SetClockPhase() function + * - Clock Polarity configuration using @ref LL_USART_SetClockPolarity() function + * - Output of Last bit Clock pulse configuration using @ref LL_USART_SetLastClkPulseOutput() function + * @rmtoll CR2 CPHA LL_USART_ConfigClock\n + * CR2 CPOL LL_USART_ConfigClock\n + * CR2 LBCL LL_USART_ConfigClock + * @param USARTx USART Instance + * @param Phase This parameter can be one of the following values: + * @arg @ref LL_USART_PHASE_1EDGE + * @arg @ref LL_USART_PHASE_2EDGE + * @param Polarity This parameter can be one of the following values: + * @arg @ref LL_USART_POLARITY_LOW + * @arg @ref LL_USART_POLARITY_HIGH + * @param LBCPOutput This parameter can be one of the following values: + * @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT + * @arg @ref LL_USART_LASTCLKPULSE_OUTPUT + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigClock(USART_TypeDef *USARTx, uint32_t Phase, uint32_t Polarity, uint32_t LBCPOutput) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL, Phase | Polarity | LBCPOutput); +} + +/** + * @brief Configure Clock source prescaler for baudrate generator and oversampling + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll PRESC PRESCALER LL_USART_SetPrescaler + * @param USARTx USART Instance + * @param PrescalerValue This parameter can be one of the following values: + * @arg @ref LL_USART_PRESCALER_DIV1 + * @arg @ref LL_USART_PRESCALER_DIV2 + * @arg @ref LL_USART_PRESCALER_DIV4 + * @arg @ref LL_USART_PRESCALER_DIV6 + * @arg @ref LL_USART_PRESCALER_DIV8 + * @arg @ref LL_USART_PRESCALER_DIV10 + * @arg @ref LL_USART_PRESCALER_DIV12 + * @arg @ref LL_USART_PRESCALER_DIV16 + * @arg @ref LL_USART_PRESCALER_DIV32 + * @arg @ref LL_USART_PRESCALER_DIV64 + * @arg @ref LL_USART_PRESCALER_DIV128 + * @arg @ref LL_USART_PRESCALER_DIV256 + * @retval None + */ +__STATIC_INLINE void LL_USART_SetPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue) +{ + MODIFY_REG(USARTx->PRESC, USART_PRESC_PRESCALER, (uint16_t)PrescalerValue); +} + +/** + * @brief Retrieve the Clock source prescaler for baudrate generator and oversampling + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll PRESC PRESCALER LL_USART_GetPrescaler + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_PRESCALER_DIV1 + * @arg @ref LL_USART_PRESCALER_DIV2 + * @arg @ref LL_USART_PRESCALER_DIV4 + * @arg @ref LL_USART_PRESCALER_DIV6 + * @arg @ref LL_USART_PRESCALER_DIV8 + * @arg @ref LL_USART_PRESCALER_DIV10 + * @arg @ref LL_USART_PRESCALER_DIV12 + * @arg @ref LL_USART_PRESCALER_DIV16 + * @arg @ref LL_USART_PRESCALER_DIV32 + * @arg @ref LL_USART_PRESCALER_DIV64 + * @arg @ref LL_USART_PRESCALER_DIV128 + * @arg @ref LL_USART_PRESCALER_DIV256 + */ +__STATIC_INLINE uint32_t LL_USART_GetPrescaler(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->PRESC, USART_PRESC_PRESCALER)); +} + +/** + * @brief Enable Clock output on SCLK pin + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @rmtoll CR2 CLKEN LL_USART_EnableSCLKOutput + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableSCLKOutput(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR2, USART_CR2_CLKEN); +} + +/** + * @brief Disable Clock output on SCLK pin + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @rmtoll CR2 CLKEN LL_USART_DisableSCLKOutput + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableSCLKOutput(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR2, USART_CR2_CLKEN); +} + +/** + * @brief Indicate if Clock output on SCLK pin is enabled + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @rmtoll CR2 CLKEN LL_USART_IsEnabledSCLKOutput + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledSCLKOutput(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR2, USART_CR2_CLKEN) == (USART_CR2_CLKEN)) ? 1UL : 0UL); +} + +/** + * @brief Set the length of the stop bits + * @rmtoll CR2 STOP LL_USART_SetStopBitsLength + * @param USARTx USART Instance + * @param StopBits This parameter can be one of the following values: + * @arg @ref LL_USART_STOPBITS_0_5 + * @arg @ref LL_USART_STOPBITS_1 + * @arg @ref LL_USART_STOPBITS_1_5 + * @arg @ref LL_USART_STOPBITS_2 + * @retval None + */ +__STATIC_INLINE void LL_USART_SetStopBitsLength(USART_TypeDef *USARTx, uint32_t StopBits) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits); +} + +/** + * @brief Retrieve the length of the stop bits + * @rmtoll CR2 STOP LL_USART_GetStopBitsLength + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_STOPBITS_0_5 + * @arg @ref LL_USART_STOPBITS_1 + * @arg @ref LL_USART_STOPBITS_1_5 + * @arg @ref LL_USART_STOPBITS_2 + */ +__STATIC_INLINE uint32_t LL_USART_GetStopBitsLength(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_STOP)); +} + +/** + * @brief Configure Character frame format (Datawidth, Parity control, Stop Bits) + * @note Call of this function is equivalent to following function call sequence : + * - Data Width configuration using @ref LL_USART_SetDataWidth() function + * - Parity Control and mode configuration using @ref LL_USART_SetParity() function + * - Stop bits configuration using @ref LL_USART_SetStopBitsLength() function + * @rmtoll CR1 PS LL_USART_ConfigCharacter\n + * CR1 PCE LL_USART_ConfigCharacter\n + * CR1 M0 LL_USART_ConfigCharacter\n + * CR1 M1 LL_USART_ConfigCharacter\n + * CR2 STOP LL_USART_ConfigCharacter + * @param USARTx USART Instance + * @param DataWidth This parameter can be one of the following values: + * @arg @ref LL_USART_DATAWIDTH_7B + * @arg @ref LL_USART_DATAWIDTH_8B + * @arg @ref LL_USART_DATAWIDTH_9B + * @param Parity This parameter can be one of the following values: + * @arg @ref LL_USART_PARITY_NONE + * @arg @ref LL_USART_PARITY_EVEN + * @arg @ref LL_USART_PARITY_ODD + * @param StopBits This parameter can be one of the following values: + * @arg @ref LL_USART_STOPBITS_0_5 + * @arg @ref LL_USART_STOPBITS_1 + * @arg @ref LL_USART_STOPBITS_1_5 + * @arg @ref LL_USART_STOPBITS_2 + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigCharacter(USART_TypeDef *USARTx, uint32_t DataWidth, uint32_t Parity, + uint32_t StopBits) +{ + MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE | USART_CR1_M, Parity | DataWidth); + MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits); +} + +/** + * @brief Configure TX/RX pins swapping setting. + * @rmtoll CR2 SWAP LL_USART_SetTXRXSwap + * @param USARTx USART Instance + * @param SwapConfig This parameter can be one of the following values: + * @arg @ref LL_USART_TXRX_STANDARD + * @arg @ref LL_USART_TXRX_SWAPPED + * @retval None + */ +__STATIC_INLINE void LL_USART_SetTXRXSwap(USART_TypeDef *USARTx, uint32_t SwapConfig) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_SWAP, SwapConfig); +} + +/** + * @brief Retrieve TX/RX pins swapping configuration. + * @rmtoll CR2 SWAP LL_USART_GetTXRXSwap + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_TXRX_STANDARD + * @arg @ref LL_USART_TXRX_SWAPPED + */ +__STATIC_INLINE uint32_t LL_USART_GetTXRXSwap(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_SWAP)); +} + +/** + * @brief Configure RX pin active level logic + * @rmtoll CR2 RXINV LL_USART_SetRXPinLevel + * @param USARTx USART Instance + * @param PinInvMethod This parameter can be one of the following values: + * @arg @ref LL_USART_RXPIN_LEVEL_STANDARD + * @arg @ref LL_USART_RXPIN_LEVEL_INVERTED + * @retval None + */ +__STATIC_INLINE void LL_USART_SetRXPinLevel(USART_TypeDef *USARTx, uint32_t PinInvMethod) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_RXINV, PinInvMethod); +} + +/** + * @brief Retrieve RX pin active level logic configuration + * @rmtoll CR2 RXINV LL_USART_GetRXPinLevel + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_RXPIN_LEVEL_STANDARD + * @arg @ref LL_USART_RXPIN_LEVEL_INVERTED + */ +__STATIC_INLINE uint32_t LL_USART_GetRXPinLevel(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_RXINV)); +} + +/** + * @brief Configure TX pin active level logic + * @rmtoll CR2 TXINV LL_USART_SetTXPinLevel + * @param USARTx USART Instance + * @param PinInvMethod This parameter can be one of the following values: + * @arg @ref LL_USART_TXPIN_LEVEL_STANDARD + * @arg @ref LL_USART_TXPIN_LEVEL_INVERTED + * @retval None + */ +__STATIC_INLINE void LL_USART_SetTXPinLevel(USART_TypeDef *USARTx, uint32_t PinInvMethod) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_TXINV, PinInvMethod); +} + +/** + * @brief Retrieve TX pin active level logic configuration + * @rmtoll CR2 TXINV LL_USART_GetTXPinLevel + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_TXPIN_LEVEL_STANDARD + * @arg @ref LL_USART_TXPIN_LEVEL_INVERTED + */ +__STATIC_INLINE uint32_t LL_USART_GetTXPinLevel(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_TXINV)); +} + +/** + * @brief Configure Binary data logic. + * @note Allow to define how Logical data from the data register are send/received : + * either in positive/direct logic (1=H, 0=L) or in negative/inverse logic (1=L, 0=H) + * @rmtoll CR2 DATAINV LL_USART_SetBinaryDataLogic + * @param USARTx USART Instance + * @param DataLogic This parameter can be one of the following values: + * @arg @ref LL_USART_BINARY_LOGIC_POSITIVE + * @arg @ref LL_USART_BINARY_LOGIC_NEGATIVE + * @retval None + */ +__STATIC_INLINE void LL_USART_SetBinaryDataLogic(USART_TypeDef *USARTx, uint32_t DataLogic) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_DATAINV, DataLogic); +} + +/** + * @brief Retrieve Binary data configuration + * @rmtoll CR2 DATAINV LL_USART_GetBinaryDataLogic + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_BINARY_LOGIC_POSITIVE + * @arg @ref LL_USART_BINARY_LOGIC_NEGATIVE + */ +__STATIC_INLINE uint32_t LL_USART_GetBinaryDataLogic(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_DATAINV)); +} + +/** + * @brief Configure transfer bit order (either Less or Most Significant Bit First) + * @note MSB First means data is transmitted/received with the MSB first, following the start bit. + * LSB First means data is transmitted/received with data bit 0 first, following the start bit. + * @rmtoll CR2 MSBFIRST LL_USART_SetTransferBitOrder + * @param USARTx USART Instance + * @param BitOrder This parameter can be one of the following values: + * @arg @ref LL_USART_BITORDER_LSBFIRST + * @arg @ref LL_USART_BITORDER_MSBFIRST + * @retval None + */ +__STATIC_INLINE void LL_USART_SetTransferBitOrder(USART_TypeDef *USARTx, uint32_t BitOrder) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_MSBFIRST, BitOrder); +} + +/** + * @brief Return transfer bit order (either Less or Most Significant Bit First) + * @note MSB First means data is transmitted/received with the MSB first, following the start bit. + * LSB First means data is transmitted/received with data bit 0 first, following the start bit. + * @rmtoll CR2 MSBFIRST LL_USART_GetTransferBitOrder + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_BITORDER_LSBFIRST + * @arg @ref LL_USART_BITORDER_MSBFIRST + */ +__STATIC_INLINE uint32_t LL_USART_GetTransferBitOrder(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_MSBFIRST)); +} + +/** + * @brief Enable Auto Baud-Rate Detection + * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not + * Auto Baud Rate detection feature is supported by the USARTx instance. + * @rmtoll CR2 ABREN LL_USART_EnableAutoBaudRate + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableAutoBaudRate(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR2, USART_CR2_ABREN); +} + +/** + * @brief Disable Auto Baud-Rate Detection + * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not + * Auto Baud Rate detection feature is supported by the USARTx instance. + * @rmtoll CR2 ABREN LL_USART_DisableAutoBaudRate + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableAutoBaudRate(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR2, USART_CR2_ABREN); +} + +/** + * @brief Indicate if Auto Baud-Rate Detection mechanism is enabled + * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not + * Auto Baud Rate detection feature is supported by the USARTx instance. + * @rmtoll CR2 ABREN LL_USART_IsEnabledAutoBaud + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledAutoBaud(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR2, USART_CR2_ABREN) == (USART_CR2_ABREN)) ? 1UL : 0UL); +} + +/** + * @brief Set Auto Baud-Rate mode bits + * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not + * Auto Baud Rate detection feature is supported by the USARTx instance. + * @rmtoll CR2 ABRMODE LL_USART_SetAutoBaudRateMode + * @param USARTx USART Instance + * @param AutoBaudRateMode This parameter can be one of the following values: + * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_STARTBIT + * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE + * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME + * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_55_FRAME + * @retval None + */ +__STATIC_INLINE void LL_USART_SetAutoBaudRateMode(USART_TypeDef *USARTx, uint32_t AutoBaudRateMode) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_ABRMODE, AutoBaudRateMode); +} + +/** + * @brief Return Auto Baud-Rate mode + * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not + * Auto Baud Rate detection feature is supported by the USARTx instance. + * @rmtoll CR2 ABRMODE LL_USART_GetAutoBaudRateMode + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_STARTBIT + * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE + * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME + * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_55_FRAME + */ +__STATIC_INLINE uint32_t LL_USART_GetAutoBaudRateMode(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ABRMODE)); +} + +/** + * @brief Enable Receiver Timeout + * @rmtoll CR2 RTOEN LL_USART_EnableRxTimeout + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableRxTimeout(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR2, USART_CR2_RTOEN); +} + +/** + * @brief Disable Receiver Timeout + * @rmtoll CR2 RTOEN LL_USART_DisableRxTimeout + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableRxTimeout(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR2, USART_CR2_RTOEN); +} + +/** + * @brief Indicate if Receiver Timeout feature is enabled + * @rmtoll CR2 RTOEN LL_USART_IsEnabledRxTimeout + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledRxTimeout(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR2, USART_CR2_RTOEN) == (USART_CR2_RTOEN)) ? 1UL : 0UL); +} + +/** + * @brief Set Address of the USART node. + * @note This is used in multiprocessor communication during Mute mode or Stop mode, + * for wake up with address mark detection. + * @note 4bits address node is used when 4-bit Address Detection is selected in ADDM7. + * (b7-b4 should be set to 0) + * 8bits address node is used when 7-bit Address Detection is selected in ADDM7. + * (This is used in multiprocessor communication during Mute mode or Stop mode, + * for wake up with 7-bit address mark detection. + * The MSB of the character sent by the transmitter should be equal to 1. + * It may also be used for character detection during normal reception, + * Mute mode inactive (for example, end of block detection in ModBus protocol). + * In this case, the whole received character (8-bit) is compared to the ADD[7:0] + * value and CMF flag is set on match) + * @rmtoll CR2 ADD LL_USART_ConfigNodeAddress\n + * CR2 ADDM7 LL_USART_ConfigNodeAddress + * @param USARTx USART Instance + * @param AddressLen This parameter can be one of the following values: + * @arg @ref LL_USART_ADDRESS_DETECT_4B + * @arg @ref LL_USART_ADDRESS_DETECT_7B + * @param NodeAddress 4 or 7 bit Address of the USART node. + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigNodeAddress(USART_TypeDef *USARTx, uint32_t AddressLen, uint32_t NodeAddress) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_ADD | USART_CR2_ADDM7, + (uint32_t)(AddressLen | (NodeAddress << USART_CR2_ADD_Pos))); +} + +/** + * @brief Return 8 bit Address of the USART node as set in ADD field of CR2. + * @note If 4-bit Address Detection is selected in ADDM7, + * only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant) + * If 7-bit Address Detection is selected in ADDM7, + * only 8bits (b7-b0) of returned value are relevant (b31-b8 are not relevant) + * @rmtoll CR2 ADD LL_USART_GetNodeAddress + * @param USARTx USART Instance + * @retval Address of the USART node (Value between Min_Data=0 and Max_Data=255) + */ +__STATIC_INLINE uint32_t LL_USART_GetNodeAddress(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADD) >> USART_CR2_ADD_Pos); +} + +/** + * @brief Return Length of Node Address used in Address Detection mode (7-bit or 4-bit) + * @rmtoll CR2 ADDM7 LL_USART_GetNodeAddressLen + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_ADDRESS_DETECT_4B + * @arg @ref LL_USART_ADDRESS_DETECT_7B + */ +__STATIC_INLINE uint32_t LL_USART_GetNodeAddressLen(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADDM7)); +} + +/** + * @brief Enable RTS HW Flow Control + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll CR3 RTSE LL_USART_EnableRTSHWFlowCtrl + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableRTSHWFlowCtrl(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_RTSE); +} + +/** + * @brief Disable RTS HW Flow Control + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll CR3 RTSE LL_USART_DisableRTSHWFlowCtrl + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableRTSHWFlowCtrl(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_RTSE); +} + +/** + * @brief Enable CTS HW Flow Control + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll CR3 CTSE LL_USART_EnableCTSHWFlowCtrl + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableCTSHWFlowCtrl(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_CTSE); +} + +/** + * @brief Disable CTS HW Flow Control + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll CR3 CTSE LL_USART_DisableCTSHWFlowCtrl + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableCTSHWFlowCtrl(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_CTSE); +} + +/** + * @brief Configure HW Flow Control mode (both CTS and RTS) + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll CR3 RTSE LL_USART_SetHWFlowCtrl\n + * CR3 CTSE LL_USART_SetHWFlowCtrl + * @param USARTx USART Instance + * @param HardwareFlowControl This parameter can be one of the following values: + * @arg @ref LL_USART_HWCONTROL_NONE + * @arg @ref LL_USART_HWCONTROL_RTS + * @arg @ref LL_USART_HWCONTROL_CTS + * @arg @ref LL_USART_HWCONTROL_RTS_CTS + * @retval None + */ +__STATIC_INLINE void LL_USART_SetHWFlowCtrl(USART_TypeDef *USARTx, uint32_t HardwareFlowControl) +{ + MODIFY_REG(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE, HardwareFlowControl); +} + +/** + * @brief Return HW Flow Control configuration (both CTS and RTS) + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll CR3 RTSE LL_USART_GetHWFlowCtrl\n + * CR3 CTSE LL_USART_GetHWFlowCtrl + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_HWCONTROL_NONE + * @arg @ref LL_USART_HWCONTROL_RTS + * @arg @ref LL_USART_HWCONTROL_CTS + * @arg @ref LL_USART_HWCONTROL_RTS_CTS + */ +__STATIC_INLINE uint32_t LL_USART_GetHWFlowCtrl(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE)); +} + +/** + * @brief Enable One bit sampling method + * @rmtoll CR3 ONEBIT LL_USART_EnableOneBitSamp + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableOneBitSamp(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_ONEBIT); +} + +/** + * @brief Disable One bit sampling method + * @rmtoll CR3 ONEBIT LL_USART_DisableOneBitSamp + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableOneBitSamp(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_ONEBIT); +} + +/** + * @brief Indicate if One bit sampling method is enabled + * @rmtoll CR3 ONEBIT LL_USART_IsEnabledOneBitSamp + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledOneBitSamp(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR3, USART_CR3_ONEBIT) == (USART_CR3_ONEBIT)) ? 1UL : 0UL); +} + +/** + * @brief Enable Overrun detection + * @rmtoll CR3 OVRDIS LL_USART_EnableOverrunDetect + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableOverrunDetect(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_OVRDIS); +} + +/** + * @brief Disable Overrun detection + * @rmtoll CR3 OVRDIS LL_USART_DisableOverrunDetect + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableOverrunDetect(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_OVRDIS); +} + +/** + * @brief Indicate if Overrun detection is enabled + * @rmtoll CR3 OVRDIS LL_USART_IsEnabledOverrunDetect + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledOverrunDetect(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS) ? 1UL : 0UL); +} + +/** + * @brief Select event type for Wake UP Interrupt Flag (WUS[1:0] bits) + * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + * Wake-up from Stop mode feature is supported by the USARTx instance. + * @rmtoll CR3 WUS LL_USART_SetWKUPType + * @param USARTx USART Instance + * @param Type This parameter can be one of the following values: + * @arg @ref LL_USART_WAKEUP_ON_ADDRESS + * @arg @ref LL_USART_WAKEUP_ON_STARTBIT + * @arg @ref LL_USART_WAKEUP_ON_RXNE + * @retval None + */ +__STATIC_INLINE void LL_USART_SetWKUPType(USART_TypeDef *USARTx, uint32_t Type) +{ + MODIFY_REG(USARTx->CR3, USART_CR3_WUS, Type); +} + +/** + * @brief Return event type for Wake UP Interrupt Flag (WUS[1:0] bits) + * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + * Wake-up from Stop mode feature is supported by the USARTx instance. + * @rmtoll CR3 WUS LL_USART_GetWKUPType + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_WAKEUP_ON_ADDRESS + * @arg @ref LL_USART_WAKEUP_ON_STARTBIT + * @arg @ref LL_USART_WAKEUP_ON_RXNE + */ +__STATIC_INLINE uint32_t LL_USART_GetWKUPType(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_WUS)); +} + +/** + * @brief Configure USART BRR register for achieving expected Baud Rate value. + * @note Compute and set USARTDIV value in BRR Register (full BRR content) + * according to used Peripheral Clock, Oversampling mode, and expected Baud Rate values + * @note Peripheral clock and Baud rate values provided as function parameters should be valid + * (Baud rate value != 0) + * @note In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d. + * @rmtoll BRR BRR LL_USART_SetBaudRate + * @param USARTx USART Instance + * @param PeriphClk Peripheral Clock + * @param PrescalerValue This parameter can be one of the following values: + * @arg @ref LL_USART_PRESCALER_DIV1 + * @arg @ref LL_USART_PRESCALER_DIV2 + * @arg @ref LL_USART_PRESCALER_DIV4 + * @arg @ref LL_USART_PRESCALER_DIV6 + * @arg @ref LL_USART_PRESCALER_DIV8 + * @arg @ref LL_USART_PRESCALER_DIV10 + * @arg @ref LL_USART_PRESCALER_DIV12 + * @arg @ref LL_USART_PRESCALER_DIV16 + * @arg @ref LL_USART_PRESCALER_DIV32 + * @arg @ref LL_USART_PRESCALER_DIV64 + * @arg @ref LL_USART_PRESCALER_DIV128 + * @arg @ref LL_USART_PRESCALER_DIV256 + * @param OverSampling This parameter can be one of the following values: + * @arg @ref LL_USART_OVERSAMPLING_16 + * @arg @ref LL_USART_OVERSAMPLING_8 + * @param BaudRate Baud Rate + * @retval None + */ +__STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t PrescalerValue, + uint32_t OverSampling, + uint32_t BaudRate) +{ + uint32_t usartdiv; + uint32_t brrtemp; + + if (PrescalerValue > LL_USART_PRESCALER_DIV256) + { + /* Do not overstep the size of USART_PRESCALER_TAB */ + } + else if (BaudRate == 0U) + { + /* Can Not divide per 0 */ + } + else if (OverSampling == LL_USART_OVERSAMPLING_8) + { + usartdiv = (uint16_t)(__LL_USART_DIV_SAMPLING8(PeriphClk, (uint8_t)PrescalerValue, BaudRate)); + brrtemp = usartdiv & 0xFFF0U; + brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); + USARTx->BRR = brrtemp; + } + else + { + USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING16(PeriphClk, (uint8_t)PrescalerValue, BaudRate)); + } +} + +/** + * @brief Return current Baud Rate value, according to USARTDIV present in BRR register + * (full BRR content), and to used Peripheral Clock and Oversampling mode values + * @note In case of non-initialized or invalid value stored in BRR register, value 0 will be returned. + * @note In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d. + * @rmtoll BRR BRR LL_USART_GetBaudRate + * @param USARTx USART Instance + * @param PeriphClk Peripheral Clock + * @param PrescalerValue This parameter can be one of the following values: + * @arg @ref LL_USART_PRESCALER_DIV1 + * @arg @ref LL_USART_PRESCALER_DIV2 + * @arg @ref LL_USART_PRESCALER_DIV4 + * @arg @ref LL_USART_PRESCALER_DIV6 + * @arg @ref LL_USART_PRESCALER_DIV8 + * @arg @ref LL_USART_PRESCALER_DIV10 + * @arg @ref LL_USART_PRESCALER_DIV12 + * @arg @ref LL_USART_PRESCALER_DIV16 + * @arg @ref LL_USART_PRESCALER_DIV32 + * @arg @ref LL_USART_PRESCALER_DIV64 + * @arg @ref LL_USART_PRESCALER_DIV128 + * @arg @ref LL_USART_PRESCALER_DIV256 + * @param OverSampling This parameter can be one of the following values: + * @arg @ref LL_USART_OVERSAMPLING_16 + * @arg @ref LL_USART_OVERSAMPLING_8 + * @retval Baud Rate + */ +__STATIC_INLINE uint32_t LL_USART_GetBaudRate(const USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t PrescalerValue, + uint32_t OverSampling) +{ + uint32_t usartdiv; + uint32_t brrresult = 0x0U; + uint32_t periphclkpresc = (uint32_t)(PeriphClk / (USART_PRESCALER_TAB[(uint8_t)PrescalerValue])); + + usartdiv = USARTx->BRR; + + if (usartdiv == 0U) + { + /* Do not perform a division by 0 */ + } + else if (OverSampling == LL_USART_OVERSAMPLING_8) + { + usartdiv = (uint16_t)((usartdiv & 0xFFF0U) | ((usartdiv & 0x0007U) << 1U)) ; + if (usartdiv != 0U) + { + brrresult = (periphclkpresc * 2U) / usartdiv; + } + } + else + { + if ((usartdiv & 0xFFFFU) != 0U) + { + brrresult = periphclkpresc / usartdiv; + } + } + return (brrresult); +} + +/** + * @brief Set Receiver Time Out Value (expressed in nb of bits duration) + * @rmtoll RTOR RTO LL_USART_SetRxTimeout + * @param USARTx USART Instance + * @param Timeout Value between Min_Data=0x00 and Max_Data=0x00FFFFFF + * @retval None + */ +__STATIC_INLINE void LL_USART_SetRxTimeout(USART_TypeDef *USARTx, uint32_t Timeout) +{ + MODIFY_REG(USARTx->RTOR, USART_RTOR_RTO, Timeout); +} + +/** + * @brief Get Receiver Time Out Value (expressed in nb of bits duration) + * @rmtoll RTOR RTO LL_USART_GetRxTimeout + * @param USARTx USART Instance + * @retval Value between Min_Data=0x00 and Max_Data=0x00FFFFFF + */ +__STATIC_INLINE uint32_t LL_USART_GetRxTimeout(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_RTO)); +} + +/** + * @brief Set Block Length value in reception + * @rmtoll RTOR BLEN LL_USART_SetBlockLength + * @param USARTx USART Instance + * @param BlockLength Value between Min_Data=0x00 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_USART_SetBlockLength(USART_TypeDef *USARTx, uint32_t BlockLength) +{ + MODIFY_REG(USARTx->RTOR, USART_RTOR_BLEN, BlockLength << USART_RTOR_BLEN_Pos); +} + +/** + * @brief Get Block Length value in reception + * @rmtoll RTOR BLEN LL_USART_GetBlockLength + * @param USARTx USART Instance + * @retval Value between Min_Data=0x00 and Max_Data=0xFF + */ +__STATIC_INLINE uint32_t LL_USART_GetBlockLength(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_BLEN) >> USART_RTOR_BLEN_Pos); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_Configuration_IRDA Configuration functions related to Irda feature + * @{ + */ + +/** + * @brief Enable IrDA mode + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * IrDA feature is supported by the USARTx instance. + * @rmtoll CR3 IREN LL_USART_EnableIrda + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIrda(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_IREN); +} + +/** + * @brief Disable IrDA mode + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * IrDA feature is supported by the USARTx instance. + * @rmtoll CR3 IREN LL_USART_DisableIrda + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIrda(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_IREN); +} + +/** + * @brief Indicate if IrDA mode is enabled + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * IrDA feature is supported by the USARTx instance. + * @rmtoll CR3 IREN LL_USART_IsEnabledIrda + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIrda(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR3, USART_CR3_IREN) == (USART_CR3_IREN)) ? 1UL : 0UL); +} + +/** + * @brief Configure IrDA Power Mode (Normal or Low Power) + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * IrDA feature is supported by the USARTx instance. + * @rmtoll CR3 IRLP LL_USART_SetIrdaPowerMode + * @param USARTx USART Instance + * @param PowerMode This parameter can be one of the following values: + * @arg @ref LL_USART_IRDA_POWER_NORMAL + * @arg @ref LL_USART_IRDA_POWER_LOW + * @retval None + */ +__STATIC_INLINE void LL_USART_SetIrdaPowerMode(USART_TypeDef *USARTx, uint32_t PowerMode) +{ + MODIFY_REG(USARTx->CR3, USART_CR3_IRLP, PowerMode); +} + +/** + * @brief Retrieve IrDA Power Mode configuration (Normal or Low Power) + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * IrDA feature is supported by the USARTx instance. + * @rmtoll CR3 IRLP LL_USART_GetIrdaPowerMode + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_IRDA_POWER_NORMAL + * @arg @ref LL_USART_PHASE_2EDGE + */ +__STATIC_INLINE uint32_t LL_USART_GetIrdaPowerMode(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_IRLP)); +} + +/** + * @brief Set Irda prescaler value, used for dividing the USART clock source + * to achieve the Irda Low Power frequency (8 bits value) + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * IrDA feature is supported by the USARTx instance. + * @rmtoll GTPR PSC LL_USART_SetIrdaPrescaler + * @param USARTx USART Instance + * @param PrescalerValue Value between Min_Data=0x00 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_USART_SetIrdaPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue) +{ + MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, (uint16_t)PrescalerValue); +} + +/** + * @brief Return Irda prescaler value, used for dividing the USART clock source + * to achieve the Irda Low Power frequency (8 bits value) + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * IrDA feature is supported by the USARTx instance. + * @rmtoll GTPR PSC LL_USART_GetIrdaPrescaler + * @param USARTx USART Instance + * @retval Irda prescaler value (Value between Min_Data=0x00 and Max_Data=0xFF) + */ +__STATIC_INLINE uint32_t LL_USART_GetIrdaPrescaler(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC)); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_Configuration_Smartcard Configuration functions related to Smartcard feature + * @{ + */ + +/** + * @brief Enable Smartcard NACK transmission + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR3 NACK LL_USART_EnableSmartcardNACK + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableSmartcardNACK(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_NACK); +} + +/** + * @brief Disable Smartcard NACK transmission + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR3 NACK LL_USART_DisableSmartcardNACK + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableSmartcardNACK(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_NACK); +} + +/** + * @brief Indicate if Smartcard NACK transmission is enabled + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR3 NACK LL_USART_IsEnabledSmartcardNACK + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcardNACK(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR3, USART_CR3_NACK) == (USART_CR3_NACK)) ? 1UL : 0UL); +} + +/** + * @brief Enable Smartcard mode + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR3 SCEN LL_USART_EnableSmartcard + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableSmartcard(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_SCEN); +} + +/** + * @brief Disable Smartcard mode + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR3 SCEN LL_USART_DisableSmartcard + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableSmartcard(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_SCEN); +} + +/** + * @brief Indicate if Smartcard mode is enabled + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR3 SCEN LL_USART_IsEnabledSmartcard + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcard(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR3, USART_CR3_SCEN) == (USART_CR3_SCEN)) ? 1UL : 0UL); +} + +/** + * @brief Set Smartcard Auto-Retry Count value (SCARCNT[2:0] bits) + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @note This bit-field specifies the number of retries in transmit and receive, in Smartcard mode. + * In transmission mode, it specifies the number of automatic retransmission retries, before + * generating a transmission error (FE bit set). + * In reception mode, it specifies the number or erroneous reception trials, before generating a + * reception error (RXNE and PE bits set) + * @rmtoll CR3 SCARCNT LL_USART_SetSmartcardAutoRetryCount + * @param USARTx USART Instance + * @param AutoRetryCount Value between Min_Data=0 and Max_Data=7 + * @retval None + */ +__STATIC_INLINE void LL_USART_SetSmartcardAutoRetryCount(USART_TypeDef *USARTx, uint32_t AutoRetryCount) +{ + MODIFY_REG(USARTx->CR3, USART_CR3_SCARCNT, AutoRetryCount << USART_CR3_SCARCNT_Pos); +} + +/** + * @brief Return Smartcard Auto-Retry Count value (SCARCNT[2:0] bits) + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR3 SCARCNT LL_USART_GetSmartcardAutoRetryCount + * @param USARTx USART Instance + * @retval Smartcard Auto-Retry Count value (Value between Min_Data=0 and Max_Data=7) + */ +__STATIC_INLINE uint32_t LL_USART_GetSmartcardAutoRetryCount(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_SCARCNT) >> USART_CR3_SCARCNT_Pos); +} + +/** + * @brief Set Smartcard prescaler value, used for dividing the USART clock + * source to provide the SMARTCARD Clock (5 bits value) + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll GTPR PSC LL_USART_SetSmartcardPrescaler + * @param USARTx USART Instance + * @param PrescalerValue Value between Min_Data=0 and Max_Data=31 + * @retval None + */ +__STATIC_INLINE void LL_USART_SetSmartcardPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue) +{ + MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, (uint16_t)PrescalerValue); +} + +/** + * @brief Return Smartcard prescaler value, used for dividing the USART clock + * source to provide the SMARTCARD Clock (5 bits value) + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll GTPR PSC LL_USART_GetSmartcardPrescaler + * @param USARTx USART Instance + * @retval Smartcard prescaler value (Value between Min_Data=0 and Max_Data=31) + */ +__STATIC_INLINE uint32_t LL_USART_GetSmartcardPrescaler(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC)); +} + +/** + * @brief Set Smartcard Guard time value, expressed in nb of baud clocks periods + * (GT[7:0] bits : Guard time value) + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll GTPR GT LL_USART_SetSmartcardGuardTime + * @param USARTx USART Instance + * @param GuardTime Value between Min_Data=0x00 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_USART_SetSmartcardGuardTime(USART_TypeDef *USARTx, uint32_t GuardTime) +{ + MODIFY_REG(USARTx->GTPR, USART_GTPR_GT, (uint16_t)(GuardTime << USART_GTPR_GT_Pos)); +} + +/** + * @brief Return Smartcard Guard time value, expressed in nb of baud clocks periods + * (GT[7:0] bits : Guard time value) + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll GTPR GT LL_USART_GetSmartcardGuardTime + * @param USARTx USART Instance + * @retval Smartcard Guard time value (Value between Min_Data=0x00 and Max_Data=0xFF) + */ +__STATIC_INLINE uint32_t LL_USART_GetSmartcardGuardTime(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_GT) >> USART_GTPR_GT_Pos); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_Configuration_HalfDuplex Configuration functions related to Half Duplex feature + * @{ + */ + +/** + * @brief Enable Single Wire Half-Duplex mode + * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not + * Half-Duplex mode is supported by the USARTx instance. + * @rmtoll CR3 HDSEL LL_USART_EnableHalfDuplex + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableHalfDuplex(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_HDSEL); +} + +/** + * @brief Disable Single Wire Half-Duplex mode + * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not + * Half-Duplex mode is supported by the USARTx instance. + * @rmtoll CR3 HDSEL LL_USART_DisableHalfDuplex + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableHalfDuplex(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_HDSEL); +} + +/** + * @brief Indicate if Single Wire Half-Duplex mode is enabled + * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not + * Half-Duplex mode is supported by the USARTx instance. + * @rmtoll CR3 HDSEL LL_USART_IsEnabledHalfDuplex + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledHalfDuplex(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_Configuration_SPI_SLAVE Configuration functions related to SPI Slave feature + * @{ + */ +/** + * @brief Enable SPI Synchronous Slave mode + * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not + * SPI Slave mode feature is supported by the USARTx instance. + * @rmtoll CR2 SLVEN LL_USART_EnableSPISlave + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableSPISlave(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR2, USART_CR2_SLVEN); +} + +/** + * @brief Disable SPI Synchronous Slave mode + * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not + * SPI Slave mode feature is supported by the USARTx instance. + * @rmtoll CR2 SLVEN LL_USART_DisableSPISlave + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableSPISlave(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR2, USART_CR2_SLVEN); +} + +/** + * @brief Indicate if SPI Synchronous Slave mode is enabled + * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not + * SPI Slave mode feature is supported by the USARTx instance. + * @rmtoll CR2 SLVEN LL_USART_IsEnabledSPISlave + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledSPISlave(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR2, USART_CR2_SLVEN) == (USART_CR2_SLVEN)) ? 1UL : 0UL); +} + +/** + * @brief Enable SPI Slave Selection using NSS input pin + * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not + * SPI Slave mode feature is supported by the USARTx instance. + * @note SPI Slave Selection depends on NSS input pin + * (The slave is selected when NSS is low and deselected when NSS is high). + * @rmtoll CR2 DIS_NSS LL_USART_EnableSPISlaveSelect + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableSPISlaveSelect(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR2, USART_CR2_DIS_NSS); +} + +/** + * @brief Disable SPI Slave Selection using NSS input pin + * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not + * SPI Slave mode feature is supported by the USARTx instance. + * @note SPI Slave will be always selected and NSS input pin will be ignored. + * @rmtoll CR2 DIS_NSS LL_USART_DisableSPISlaveSelect + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableSPISlaveSelect(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR2, USART_CR2_DIS_NSS); +} + +/** + * @brief Indicate if SPI Slave Selection depends on NSS input pin + * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not + * SPI Slave mode feature is supported by the USARTx instance. + * @rmtoll CR2 DIS_NSS LL_USART_IsEnabledSPISlaveSelect + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledSPISlaveSelect(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR2, USART_CR2_DIS_NSS) != (USART_CR2_DIS_NSS)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_Configuration_LIN Configuration functions related to LIN feature + * @{ + */ + +/** + * @brief Set LIN Break Detection Length + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll CR2 LBDL LL_USART_SetLINBrkDetectionLen + * @param USARTx USART Instance + * @param LINBDLength This parameter can be one of the following values: + * @arg @ref LL_USART_LINBREAK_DETECT_10B + * @arg @ref LL_USART_LINBREAK_DETECT_11B + * @retval None + */ +__STATIC_INLINE void LL_USART_SetLINBrkDetectionLen(USART_TypeDef *USARTx, uint32_t LINBDLength) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_LBDL, LINBDLength); +} + +/** + * @brief Return LIN Break Detection Length + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll CR2 LBDL LL_USART_GetLINBrkDetectionLen + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_LINBREAK_DETECT_10B + * @arg @ref LL_USART_LINBREAK_DETECT_11B + */ +__STATIC_INLINE uint32_t LL_USART_GetLINBrkDetectionLen(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBDL)); +} + +/** + * @brief Enable LIN mode + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll CR2 LINEN LL_USART_EnableLIN + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableLIN(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR2, USART_CR2_LINEN); +} + +/** + * @brief Disable LIN mode + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll CR2 LINEN LL_USART_DisableLIN + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableLIN(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR2, USART_CR2_LINEN); +} + +/** + * @brief Indicate if LIN mode is enabled + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll CR2 LINEN LL_USART_IsEnabledLIN + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledLIN(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR2, USART_CR2_LINEN) == (USART_CR2_LINEN)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_Configuration_DE Configuration functions related to Driver Enable feature + * @{ + */ + +/** + * @brief Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits). + * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not + * Driver Enable feature is supported by the USARTx instance. + * @rmtoll CR1 DEDT LL_USART_SetDEDeassertionTime + * @param USARTx USART Instance + * @param Time Value between Min_Data=0 and Max_Data=31 + * @retval None + */ +__STATIC_INLINE void LL_USART_SetDEDeassertionTime(USART_TypeDef *USARTx, uint32_t Time) +{ + MODIFY_REG(USARTx->CR1, USART_CR1_DEDT, Time << USART_CR1_DEDT_Pos); +} + +/** + * @brief Return DEDT (Driver Enable De-Assertion Time) + * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not + * Driver Enable feature is supported by the USARTx instance. + * @rmtoll CR1 DEDT LL_USART_GetDEDeassertionTime + * @param USARTx USART Instance + * @retval Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31 + */ +__STATIC_INLINE uint32_t LL_USART_GetDEDeassertionTime(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEDT) >> USART_CR1_DEDT_Pos); +} + +/** + * @brief Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits). + * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not + * Driver Enable feature is supported by the USARTx instance. + * @rmtoll CR1 DEAT LL_USART_SetDEAssertionTime + * @param USARTx USART Instance + * @param Time Value between Min_Data=0 and Max_Data=31 + * @retval None + */ +__STATIC_INLINE void LL_USART_SetDEAssertionTime(USART_TypeDef *USARTx, uint32_t Time) +{ + MODIFY_REG(USARTx->CR1, USART_CR1_DEAT, Time << USART_CR1_DEAT_Pos); +} + +/** + * @brief Return DEAT (Driver Enable Assertion Time) + * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not + * Driver Enable feature is supported by the USARTx instance. + * @rmtoll CR1 DEAT LL_USART_GetDEAssertionTime + * @param USARTx USART Instance + * @retval Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31 + */ +__STATIC_INLINE uint32_t LL_USART_GetDEAssertionTime(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEAT) >> USART_CR1_DEAT_Pos); +} + +/** + * @brief Enable Driver Enable (DE) Mode + * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not + * Driver Enable feature is supported by the USARTx instance. + * @rmtoll CR3 DEM LL_USART_EnableDEMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableDEMode(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_DEM); +} + +/** + * @brief Disable Driver Enable (DE) Mode + * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not + * Driver Enable feature is supported by the USARTx instance. + * @rmtoll CR3 DEM LL_USART_DisableDEMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableDEMode(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_DEM); +} + +/** + * @brief Indicate if Driver Enable (DE) Mode is enabled + * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not + * Driver Enable feature is supported by the USARTx instance. + * @rmtoll CR3 DEM LL_USART_IsEnabledDEMode + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledDEMode(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR3, USART_CR3_DEM) == (USART_CR3_DEM)) ? 1UL : 0UL); +} + +/** + * @brief Select Driver Enable Polarity + * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not + * Driver Enable feature is supported by the USARTx instance. + * @rmtoll CR3 DEP LL_USART_SetDESignalPolarity + * @param USARTx USART Instance + * @param Polarity This parameter can be one of the following values: + * @arg @ref LL_USART_DE_POLARITY_HIGH + * @arg @ref LL_USART_DE_POLARITY_LOW + * @retval None + */ +__STATIC_INLINE void LL_USART_SetDESignalPolarity(USART_TypeDef *USARTx, uint32_t Polarity) +{ + MODIFY_REG(USARTx->CR3, USART_CR3_DEP, Polarity); +} + +/** + * @brief Return Driver Enable Polarity + * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not + * Driver Enable feature is supported by the USARTx instance. + * @rmtoll CR3 DEP LL_USART_GetDESignalPolarity + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_DE_POLARITY_HIGH + * @arg @ref LL_USART_DE_POLARITY_LOW + */ +__STATIC_INLINE uint32_t LL_USART_GetDESignalPolarity(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_DEP)); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_AdvancedConfiguration Advanced Configurations services + * @{ + */ + +/** + * @brief Perform basic configuration of USART for enabling use in Asynchronous Mode (UART) + * @note In UART mode, the following bits must be kept cleared: + * - LINEN bit in the USART_CR2 register, + * - CLKEN bit in the USART_CR2 register, + * - SCEN bit in the USART_CR3 register, + * - IREN bit in the USART_CR3 register, + * - HDSEL bit in the USART_CR3 register. + * @note Call of this function is equivalent to following function call sequence : + * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function + * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function + * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function + * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function + * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function + * @note Other remaining configurations items related to Asynchronous Mode + * (as Baud Rate, Word length, Parity, ...) should be set using + * dedicated functions + * @rmtoll CR2 LINEN LL_USART_ConfigAsyncMode\n + * CR2 CLKEN LL_USART_ConfigAsyncMode\n + * CR3 SCEN LL_USART_ConfigAsyncMode\n + * CR3 IREN LL_USART_ConfigAsyncMode\n + * CR3 HDSEL LL_USART_ConfigAsyncMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigAsyncMode(USART_TypeDef *USARTx) +{ + /* In Asynchronous mode, the following bits must be kept cleared: + - LINEN, CLKEN bits in the USART_CR2 register, + - SCEN, IREN and HDSEL bits in the USART_CR3 register. + */ + CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL)); +} + +/** + * @brief Perform basic configuration of USART for enabling use in Synchronous Mode + * @note In Synchronous mode, the following bits must be kept cleared: + * - LINEN bit in the USART_CR2 register, + * - SCEN bit in the USART_CR3 register, + * - IREN bit in the USART_CR3 register, + * - HDSEL bit in the USART_CR3 register. + * This function also sets the USART in Synchronous mode. + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @note Call of this function is equivalent to following function call sequence : + * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function + * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function + * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function + * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function + * - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function + * @note Other remaining configurations items related to Synchronous Mode + * (as Baud Rate, Word length, Parity, Clock Polarity, ...) should be set using + * dedicated functions + * @rmtoll CR2 LINEN LL_USART_ConfigSyncMode\n + * CR2 CLKEN LL_USART_ConfigSyncMode\n + * CR3 SCEN LL_USART_ConfigSyncMode\n + * CR3 IREN LL_USART_ConfigSyncMode\n + * CR3 HDSEL LL_USART_ConfigSyncMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigSyncMode(USART_TypeDef *USARTx) +{ + /* In Synchronous mode, the following bits must be kept cleared: + - LINEN bit in the USART_CR2 register, + - SCEN, IREN and HDSEL bits in the USART_CR3 register. + */ + CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN)); + CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL)); + /* set the UART/USART in Synchronous mode */ + SET_BIT(USARTx->CR2, USART_CR2_CLKEN); +} + +/** + * @brief Perform basic configuration of USART for enabling use in LIN Mode + * @note In LIN mode, the following bits must be kept cleared: + * - STOP and CLKEN bits in the USART_CR2 register, + * - SCEN bit in the USART_CR3 register, + * - IREN bit in the USART_CR3 register, + * - HDSEL bit in the USART_CR3 register. + * This function also set the UART/USART in LIN mode. + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @note Call of this function is equivalent to following function call sequence : + * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function + * - Clear STOP in CR2 using @ref LL_USART_SetStopBitsLength() function + * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function + * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function + * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function + * - Set LINEN in CR2 using @ref LL_USART_EnableLIN() function + * @note Other remaining configurations items related to LIN Mode + * (as Baud Rate, Word length, LIN Break Detection Length, ...) should be set using + * dedicated functions + * @rmtoll CR2 CLKEN LL_USART_ConfigLINMode\n + * CR2 STOP LL_USART_ConfigLINMode\n + * CR2 LINEN LL_USART_ConfigLINMode\n + * CR3 IREN LL_USART_ConfigLINMode\n + * CR3 SCEN LL_USART_ConfigLINMode\n + * CR3 HDSEL LL_USART_ConfigLINMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigLINMode(USART_TypeDef *USARTx) +{ + /* In LIN mode, the following bits must be kept cleared: + - STOP and CLKEN bits in the USART_CR2 register, + - IREN, SCEN and HDSEL bits in the USART_CR3 register. + */ + CLEAR_BIT(USARTx->CR2, (USART_CR2_CLKEN | USART_CR2_STOP)); + CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_SCEN | USART_CR3_HDSEL)); + /* Set the UART/USART in LIN mode */ + SET_BIT(USARTx->CR2, USART_CR2_LINEN); +} + +/** + * @brief Perform basic configuration of USART for enabling use in Half Duplex Mode + * @note In Half Duplex mode, the following bits must be kept cleared: + * - LINEN bit in the USART_CR2 register, + * - CLKEN bit in the USART_CR2 register, + * - SCEN bit in the USART_CR3 register, + * - IREN bit in the USART_CR3 register, + * This function also sets the UART/USART in Half Duplex mode. + * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not + * Half-Duplex mode is supported by the USARTx instance. + * @note Call of this function is equivalent to following function call sequence : + * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function + * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function + * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function + * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function + * - Set HDSEL in CR3 using @ref LL_USART_EnableHalfDuplex() function + * @note Other remaining configurations items related to Half Duplex Mode + * (as Baud Rate, Word length, Parity, ...) should be set using + * dedicated functions + * @rmtoll CR2 LINEN LL_USART_ConfigHalfDuplexMode\n + * CR2 CLKEN LL_USART_ConfigHalfDuplexMode\n + * CR3 HDSEL LL_USART_ConfigHalfDuplexMode\n + * CR3 SCEN LL_USART_ConfigHalfDuplexMode\n + * CR3 IREN LL_USART_ConfigHalfDuplexMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigHalfDuplexMode(USART_TypeDef *USARTx) +{ + /* In Half Duplex mode, the following bits must be kept cleared: + - LINEN and CLKEN bits in the USART_CR2 register, + - SCEN and IREN bits in the USART_CR3 register. + */ + CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN)); + /* set the UART/USART in Half Duplex mode */ + SET_BIT(USARTx->CR3, USART_CR3_HDSEL); +} + +/** + * @brief Perform basic configuration of USART for enabling use in Smartcard Mode + * @note In Smartcard mode, the following bits must be kept cleared: + * - LINEN bit in the USART_CR2 register, + * - IREN bit in the USART_CR3 register, + * - HDSEL bit in the USART_CR3 register. + * This function also configures Stop bits to 1.5 bits and + * sets the USART in Smartcard mode (SCEN bit). + * Clock Output is also enabled (CLKEN). + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @note Call of this function is equivalent to following function call sequence : + * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function + * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function + * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function + * - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function + * - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function + * - Set SCEN in CR3 using @ref LL_USART_EnableSmartcard() function + * @note Other remaining configurations items related to Smartcard Mode + * (as Baud Rate, Word length, Parity, ...) should be set using + * dedicated functions + * @rmtoll CR2 LINEN LL_USART_ConfigSmartcardMode\n + * CR2 STOP LL_USART_ConfigSmartcardMode\n + * CR2 CLKEN LL_USART_ConfigSmartcardMode\n + * CR3 HDSEL LL_USART_ConfigSmartcardMode\n + * CR3 SCEN LL_USART_ConfigSmartcardMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigSmartcardMode(USART_TypeDef *USARTx) +{ + /* In Smartcard mode, the following bits must be kept cleared: + - LINEN bit in the USART_CR2 register, + - IREN and HDSEL bits in the USART_CR3 register. + */ + CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN)); + CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_HDSEL)); + /* Configure Stop bits to 1.5 bits */ + /* Synchronous mode is activated by default */ + SET_BIT(USARTx->CR2, (USART_CR2_STOP_0 | USART_CR2_STOP_1 | USART_CR2_CLKEN)); + /* set the UART/USART in Smartcard mode */ + SET_BIT(USARTx->CR3, USART_CR3_SCEN); +} + +/** + * @brief Perform basic configuration of USART for enabling use in Irda Mode + * @note In IRDA mode, the following bits must be kept cleared: + * - LINEN bit in the USART_CR2 register, + * - STOP and CLKEN bits in the USART_CR2 register, + * - SCEN bit in the USART_CR3 register, + * - HDSEL bit in the USART_CR3 register. + * This function also sets the UART/USART in IRDA mode (IREN bit). + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * IrDA feature is supported by the USARTx instance. + * @note Call of this function is equivalent to following function call sequence : + * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function + * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function + * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function + * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function + * - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function + * - Set IREN in CR3 using @ref LL_USART_EnableIrda() function + * @note Other remaining configurations items related to Irda Mode + * (as Baud Rate, Word length, Power mode, ...) should be set using + * dedicated functions + * @rmtoll CR2 LINEN LL_USART_ConfigIrdaMode\n + * CR2 CLKEN LL_USART_ConfigIrdaMode\n + * CR2 STOP LL_USART_ConfigIrdaMode\n + * CR3 SCEN LL_USART_ConfigIrdaMode\n + * CR3 HDSEL LL_USART_ConfigIrdaMode\n + * CR3 IREN LL_USART_ConfigIrdaMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigIrdaMode(USART_TypeDef *USARTx) +{ + /* In IRDA mode, the following bits must be kept cleared: + - LINEN, STOP and CLKEN bits in the USART_CR2 register, + - SCEN and HDSEL bits in the USART_CR3 register. + */ + CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP)); + CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL)); + /* set the UART/USART in IRDA mode */ + SET_BIT(USARTx->CR3, USART_CR3_IREN); +} + +/** + * @brief Perform basic configuration of USART for enabling use in Multi processor Mode + * (several USARTs connected in a network, one of the USARTs can be the master, + * its TX output connected to the RX inputs of the other slaves USARTs). + * @note In MultiProcessor mode, the following bits must be kept cleared: + * - LINEN bit in the USART_CR2 register, + * - CLKEN bit in the USART_CR2 register, + * - SCEN bit in the USART_CR3 register, + * - IREN bit in the USART_CR3 register, + * - HDSEL bit in the USART_CR3 register. + * @note Call of this function is equivalent to following function call sequence : + * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function + * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function + * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function + * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function + * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function + * @note Other remaining configurations items related to Multi processor Mode + * (as Baud Rate, Wake Up Method, Node address, ...) should be set using + * dedicated functions + * @rmtoll CR2 LINEN LL_USART_ConfigMultiProcessMode\n + * CR2 CLKEN LL_USART_ConfigMultiProcessMode\n + * CR3 SCEN LL_USART_ConfigMultiProcessMode\n + * CR3 HDSEL LL_USART_ConfigMultiProcessMode\n + * CR3 IREN LL_USART_ConfigMultiProcessMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigMultiProcessMode(USART_TypeDef *USARTx) +{ + /* In Multi Processor mode, the following bits must be kept cleared: + - LINEN and CLKEN bits in the USART_CR2 register, + - IREN, SCEN and HDSEL bits in the USART_CR3 register. + */ + CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_FLAG_Management FLAG_Management + * @{ + */ + +/** + * @brief Check if the USART Parity Error Flag is set or not + * @rmtoll ISR PE LL_USART_IsActiveFlag_PE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_PE(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_PE) == (USART_ISR_PE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Framing Error Flag is set or not + * @rmtoll ISR FE LL_USART_IsActiveFlag_FE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_FE(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_FE) == (USART_ISR_FE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Noise error detected Flag is set or not + * @rmtoll ISR NE LL_USART_IsActiveFlag_NE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_NE(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_NE) == (USART_ISR_NE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART OverRun Error Flag is set or not + * @rmtoll ISR ORE LL_USART_IsActiveFlag_ORE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ORE(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_ORE) == (USART_ISR_ORE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART IDLE line detected Flag is set or not + * @rmtoll ISR IDLE LL_USART_IsActiveFlag_IDLE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_IDLE(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE)) ? 1UL : 0UL); +} + +#define LL_USART_IsActiveFlag_RXNE LL_USART_IsActiveFlag_RXNE_RXFNE /* Redefinition for legacy purpose */ + +/** + * @brief Check if the USART Read Data Register or USART RX FIFO Not Empty Flag is set or not + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll ISR RXNE_RXFNE LL_USART_IsActiveFlag_RXNE_RXFNE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE_RXFNE(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_RXNE_RXFNE) == (USART_ISR_RXNE_RXFNE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Transmission Complete Flag is set or not + * @rmtoll ISR TC LL_USART_IsActiveFlag_TC + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_TC) == (USART_ISR_TC)) ? 1UL : 0UL); +} + +#define LL_USART_IsActiveFlag_TXE LL_USART_IsActiveFlag_TXE_TXFNF /* Redefinition for legacy purpose */ + +/** + * @brief Check if the USART Transmit Data Register Empty or USART TX FIFO Not Full Flag is set or not + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll ISR TXE_TXFNF LL_USART_IsActiveFlag_TXE_TXFNF + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE_TXFNF(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_TXE_TXFNF) == (USART_ISR_TXE_TXFNF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART LIN Break Detection Flag is set or not + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll ISR LBDF LL_USART_IsActiveFlag_LBD + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_LBD(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_LBDF) == (USART_ISR_LBDF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART CTS interrupt Flag is set or not + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll ISR CTSIF LL_USART_IsActiveFlag_nCTS + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_nCTS(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART CTS Flag is set or not + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll ISR CTS LL_USART_IsActiveFlag_CTS + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CTS(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_CTS) == (USART_ISR_CTS)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Receiver Time Out Flag is set or not + * @rmtoll ISR RTOF LL_USART_IsActiveFlag_RTO + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RTO(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_RTOF) == (USART_ISR_RTOF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART End Of Block Flag is set or not + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll ISR EOBF LL_USART_IsActiveFlag_EOB + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_EOB(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_EOBF) == (USART_ISR_EOBF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the SPI Slave Underrun error flag is set or not + * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not + * SPI Slave mode feature is supported by the USARTx instance. + * @rmtoll ISR UDR LL_USART_IsActiveFlag_UDR + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_UDR(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_UDR) == (USART_ISR_UDR)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Auto-Baud Rate Error Flag is set or not + * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not + * Auto Baud Rate detection feature is supported by the USARTx instance. + * @rmtoll ISR ABRE LL_USART_IsActiveFlag_ABRE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABRE(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_ABRE) == (USART_ISR_ABRE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Auto-Baud Rate Flag is set or not + * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not + * Auto Baud Rate detection feature is supported by the USARTx instance. + * @rmtoll ISR ABRF LL_USART_IsActiveFlag_ABR + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABR(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_ABRF) == (USART_ISR_ABRF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Busy Flag is set or not + * @rmtoll ISR BUSY LL_USART_IsActiveFlag_BUSY + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_BUSY(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Character Match Flag is set or not + * @rmtoll ISR CMF LL_USART_IsActiveFlag_CM + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CM(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_CMF) == (USART_ISR_CMF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Send Break Flag is set or not + * @rmtoll ISR SBKF LL_USART_IsActiveFlag_SBK + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_SBK(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Receive Wake Up from mute mode Flag is set or not + * @rmtoll ISR RWU LL_USART_IsActiveFlag_RWU + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RWU(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Wake Up from stop mode Flag is set or not + * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + * Wake-up from Stop mode feature is supported by the USARTx instance. + * @rmtoll ISR WUF LL_USART_IsActiveFlag_WKUP + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_WKUP(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_WUF) == (USART_ISR_WUF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Transmit Enable Acknowledge Flag is set or not + * @rmtoll ISR TEACK LL_USART_IsActiveFlag_TEACK + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TEACK(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Receive Enable Acknowledge Flag is set or not + * @rmtoll ISR REACK LL_USART_IsActiveFlag_REACK + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_REACK(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART TX FIFO Empty Flag is set or not + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll ISR TXFE LL_USART_IsActiveFlag_TXFE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXFE(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_TXFE) == (USART_ISR_TXFE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART RX FIFO Full Flag is set or not + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll ISR RXFF LL_USART_IsActiveFlag_RXFF + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXFF(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_RXFF) == (USART_ISR_RXFF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the Smartcard Transmission Complete Before Guard Time Flag is set or not + * @rmtoll ISR TCBGT LL_USART_IsActiveFlag_TCBGT + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TCBGT(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_TCBGT) == (USART_ISR_TCBGT)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART TX FIFO Threshold Flag is set or not + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll ISR TXFT LL_USART_IsActiveFlag_TXFT + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXFT(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_TXFT) == (USART_ISR_TXFT)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART RX FIFO Threshold Flag is set or not + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll ISR RXFT LL_USART_IsActiveFlag_RXFT + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXFT(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_RXFT) == (USART_ISR_RXFT)) ? 1UL : 0UL); +} + +/** + * @brief Clear Parity Error Flag + * @rmtoll ICR PECF LL_USART_ClearFlag_PE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_PE(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_PECF); +} + +/** + * @brief Clear Framing Error Flag + * @rmtoll ICR FECF LL_USART_ClearFlag_FE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_FE(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_FECF); +} + +/** + * @brief Clear Noise Error detected Flag + * @rmtoll ICR NECF LL_USART_ClearFlag_NE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_NE(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_NECF); +} + +/** + * @brief Clear OverRun Error Flag + * @rmtoll ICR ORECF LL_USART_ClearFlag_ORE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_ORE(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_ORECF); +} + +/** + * @brief Clear IDLE line detected Flag + * @rmtoll ICR IDLECF LL_USART_ClearFlag_IDLE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_IDLE(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_IDLECF); +} + +/** + * @brief Clear TX FIFO Empty Flag + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll ICR TXFECF LL_USART_ClearFlag_TXFE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_TXFE(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_TXFECF); +} + +/** + * @brief Clear Transmission Complete Flag + * @rmtoll ICR TCCF LL_USART_ClearFlag_TC + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_TC(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_TCCF); +} + +/** + * @brief Clear Smartcard Transmission Complete Before Guard Time Flag + * @rmtoll ICR TCBGTCF LL_USART_ClearFlag_TCBGT + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_TCBGT(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_TCBGTCF); +} + +/** + * @brief Clear LIN Break Detection Flag + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll ICR LBDCF LL_USART_ClearFlag_LBD + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_LBD(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_LBDCF); +} + +/** + * @brief Clear CTS Interrupt Flag + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll ICR CTSCF LL_USART_ClearFlag_nCTS + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_nCTS(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_CTSCF); +} + +/** + * @brief Clear Receiver Time Out Flag + * @rmtoll ICR RTOCF LL_USART_ClearFlag_RTO + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_RTO(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_RTOCF); +} + +/** + * @brief Clear End Of Block Flag + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll ICR EOBCF LL_USART_ClearFlag_EOB + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_EOB(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_EOBCF); +} + +/** + * @brief Clear SPI Slave Underrun Flag + * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not + * SPI Slave mode feature is supported by the USARTx instance. + * @rmtoll ICR UDRCF LL_USART_ClearFlag_UDR + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_UDR(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_UDRCF); +} + +/** + * @brief Clear Character Match Flag + * @rmtoll ICR CMCF LL_USART_ClearFlag_CM + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_CM(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_CMCF); +} + +/** + * @brief Clear Wake Up from stop mode Flag + * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + * Wake-up from Stop mode feature is supported by the USARTx instance. + * @rmtoll ICR WUCF LL_USART_ClearFlag_WKUP + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_WKUP(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_WUCF); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable IDLE Interrupt + * @rmtoll CR1 IDLEIE LL_USART_EnableIT_IDLE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_IDLE(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_IDLEIE); +} + +#define LL_USART_EnableIT_RXNE LL_USART_EnableIT_RXNE_RXFNE /* Redefinition for legacy purpose */ + +/** + * @brief Enable RX Not Empty and RX FIFO Not Empty Interrupt + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR1 RXNEIE_RXFNEIE LL_USART_EnableIT_RXNE_RXFNE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_RXNE_RXFNE(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE); +} + +/** + * @brief Enable Transmission Complete Interrupt + * @rmtoll CR1 TCIE LL_USART_EnableIT_TC + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_TC(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TCIE); +} + +#define LL_USART_EnableIT_TXE LL_USART_EnableIT_TXE_TXFNF /* Redefinition for legacy purpose */ + +/** + * @brief Enable TX Empty and TX FIFO Not Full Interrupt + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR1 TXEIE_TXFNFIE LL_USART_EnableIT_TXE_TXFNF + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_TXE_TXFNF(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE); +} + +/** + * @brief Enable Parity Error Interrupt + * @rmtoll CR1 PEIE LL_USART_EnableIT_PE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_PE(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_PEIE); +} + +/** + * @brief Enable Character Match Interrupt + * @rmtoll CR1 CMIE LL_USART_EnableIT_CM + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_CM(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_CMIE); +} + +/** + * @brief Enable Receiver Timeout Interrupt + * @rmtoll CR1 RTOIE LL_USART_EnableIT_RTO + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_RTO(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RTOIE); +} + +/** + * @brief Enable End Of Block Interrupt + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR1 EOBIE LL_USART_EnableIT_EOB + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_EOB(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_EOBIE); +} + +/** + * @brief Enable TX FIFO Empty Interrupt + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR1 TXFEIE LL_USART_EnableIT_TXFE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_TXFE(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TXFEIE); +} + +/** + * @brief Enable RX FIFO Full Interrupt + * @rmtoll CR1 RXFFIE LL_USART_EnableIT_RXFF + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_RXFF(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RXFFIE); +} + +/** + * @brief Enable LIN Break Detection Interrupt + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll CR2 LBDIE LL_USART_EnableIT_LBD + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_LBD(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR2, USART_CR2_LBDIE); +} + +/** + * @brief Enable Error Interrupt + * @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing + * error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_ISR register). + * 0: Interrupt is inhibited + * 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_ISR register. + * @rmtoll CR3 EIE LL_USART_EnableIT_ERROR + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_ERROR(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_EIE); +} + +/** + * @brief Enable CTS Interrupt + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll CR3 CTSIE LL_USART_EnableIT_CTS + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_CTS(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_CTSIE); +} + +/** + * @brief Enable Wake Up from Stop Mode Interrupt + * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + * Wake-up from Stop mode feature is supported by the USARTx instance. + * @rmtoll CR3 WUFIE LL_USART_EnableIT_WKUP + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_WKUP(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_WUFIE); +} + +/** + * @brief Enable TX FIFO Threshold Interrupt + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR3 TXFTIE LL_USART_EnableIT_TXFT + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_TXFT(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_TXFTIE); +} + +/** + * @brief Enable Smartcard Transmission Complete Before Guard Time Interrupt + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR3 TCBGTIE LL_USART_EnableIT_TCBGT + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_TCBGT(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_TCBGTIE); +} + +/** + * @brief Enable RX FIFO Threshold Interrupt + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR3 RXFTIE LL_USART_EnableIT_RXFT + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_RXFT(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_RXFTIE); +} + +/** + * @brief Disable IDLE Interrupt + * @rmtoll CR1 IDLEIE LL_USART_DisableIT_IDLE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_IDLE(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_IDLEIE); +} + +#define LL_USART_DisableIT_RXNE LL_USART_DisableIT_RXNE_RXFNE /* Redefinition for legacy purpose */ + +/** + * @brief Disable RX Not Empty and RX FIFO Not Empty Interrupt + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR1 RXNEIE_RXFNEIE LL_USART_DisableIT_RXNE_RXFNE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_RXNE_RXFNE(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE); +} + +/** + * @brief Disable Transmission Complete Interrupt + * @rmtoll CR1 TCIE LL_USART_DisableIT_TC + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_TC(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TCIE); +} + +#define LL_USART_DisableIT_TXE LL_USART_DisableIT_TXE_TXFNF /* Redefinition for legacy purpose */ + +/** + * @brief Disable TX Empty and TX FIFO Not Full Interrupt + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR1 TXEIE_TXFNFIE LL_USART_DisableIT_TXE_TXFNF + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_TXE_TXFNF(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE); +} + +/** + * @brief Disable Parity Error Interrupt + * @rmtoll CR1 PEIE LL_USART_DisableIT_PE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_PE(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_PEIE); +} + +/** + * @brief Disable Character Match Interrupt + * @rmtoll CR1 CMIE LL_USART_DisableIT_CM + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_CM(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_CMIE); +} + +/** + * @brief Disable Receiver Timeout Interrupt + * @rmtoll CR1 RTOIE LL_USART_DisableIT_RTO + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_RTO(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RTOIE); +} + +/** + * @brief Disable End Of Block Interrupt + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR1 EOBIE LL_USART_DisableIT_EOB + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_EOB(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_EOBIE); +} + +/** + * @brief Disable TX FIFO Empty Interrupt + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR1 TXFEIE LL_USART_DisableIT_TXFE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_TXFE(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TXFEIE); +} + +/** + * @brief Disable RX FIFO Full Interrupt + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR1 RXFFIE LL_USART_DisableIT_RXFF + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_RXFF(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RXFFIE); +} + +/** + * @brief Disable LIN Break Detection Interrupt + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll CR2 LBDIE LL_USART_DisableIT_LBD + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_LBD(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR2, USART_CR2_LBDIE); +} + +/** + * @brief Disable Error Interrupt + * @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing + * error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_ISR register). + * 0: Interrupt is inhibited + * 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_ISR register. + * @rmtoll CR3 EIE LL_USART_DisableIT_ERROR + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_ERROR(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_EIE); +} + +/** + * @brief Disable CTS Interrupt + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll CR3 CTSIE LL_USART_DisableIT_CTS + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_CTS(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_CTSIE); +} + +/** + * @brief Disable Wake Up from Stop Mode Interrupt + * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + * Wake-up from Stop mode feature is supported by the USARTx instance. + * @rmtoll CR3 WUFIE LL_USART_DisableIT_WKUP + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_WKUP(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_WUFIE); +} + +/** + * @brief Disable TX FIFO Threshold Interrupt + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR3 TXFTIE LL_USART_DisableIT_TXFT + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_TXFT(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_TXFTIE); +} + +/** + * @brief Disable Smartcard Transmission Complete Before Guard Time Interrupt + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR3 TCBGTIE LL_USART_DisableIT_TCBGT + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_TCBGT(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_TCBGTIE); +} + +/** + * @brief Disable RX FIFO Threshold Interrupt + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR3 RXFTIE LL_USART_DisableIT_RXFT + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_RXFT(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_RXFTIE); +} + +/** + * @brief Check if the USART IDLE Interrupt source is enabled or disabled. + * @rmtoll CR1 IDLEIE LL_USART_IsEnabledIT_IDLE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_IDLE(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE)) ? 1UL : 0UL); +} + +#define LL_USART_IsEnabledIT_RXNE LL_USART_IsEnabledIT_RXNE_RXFNE /* Redefinition for legacy purpose */ + +/** + * @brief Check if the USART RX Not Empty and USART RX FIFO Not Empty Interrupt is enabled or disabled. + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR1 RXNEIE_RXFNEIE LL_USART_IsEnabledIT_RXNE_RXFNE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE_RXFNE(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE) == (USART_CR1_RXNEIE_RXFNEIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Transmission Complete Interrupt is enabled or disabled. + * @rmtoll CR1 TCIE LL_USART_IsEnabledIT_TC + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)) ? 1UL : 0UL); +} + +#define LL_USART_IsEnabledIT_TXE LL_USART_IsEnabledIT_TXE_TXFNF /* Redefinition for legacy purpose */ + +/** + * @brief Check if the USART TX Empty and USART TX FIFO Not Full Interrupt is enabled or disabled + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR1 TXEIE_TXFNFIE LL_USART_IsEnabledIT_TXE_TXFNF + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE_TXFNF(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE) == (USART_CR1_TXEIE_TXFNFIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Parity Error Interrupt is enabled or disabled. + * @rmtoll CR1 PEIE LL_USART_IsEnabledIT_PE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_PE(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Character Match Interrupt is enabled or disabled. + * @rmtoll CR1 CMIE LL_USART_IsEnabledIT_CM + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CM(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Receiver Timeout Interrupt is enabled or disabled. + * @rmtoll CR1 RTOIE LL_USART_IsEnabledIT_RTO + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RTO(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR1, USART_CR1_RTOIE) == (USART_CR1_RTOIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART End Of Block Interrupt is enabled or disabled. + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR1 EOBIE LL_USART_IsEnabledIT_EOB + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_EOB(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR1, USART_CR1_EOBIE) == (USART_CR1_EOBIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART TX FIFO Empty Interrupt is enabled or disabled + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR1 TXFEIE LL_USART_IsEnabledIT_TXFE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXFE(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR1, USART_CR1_TXFEIE) == (USART_CR1_TXFEIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART RX FIFO Full Interrupt is enabled or disabled + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR1 RXFFIE LL_USART_IsEnabledIT_RXFF + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXFF(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR1, USART_CR1_RXFFIE) == (USART_CR1_RXFFIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART LIN Break Detection Interrupt is enabled or disabled. + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll CR2 LBDIE LL_USART_IsEnabledIT_LBD + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_LBD(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR2, USART_CR2_LBDIE) == (USART_CR2_LBDIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Error Interrupt is enabled or disabled. + * @rmtoll CR3 EIE LL_USART_IsEnabledIT_ERROR + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_ERROR(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART CTS Interrupt is enabled or disabled. + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll CR3 CTSIE LL_USART_IsEnabledIT_CTS + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CTS(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Wake Up from Stop Mode Interrupt is enabled or disabled. + * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + * Wake-up from Stop mode feature is supported by the USARTx instance. + * @rmtoll CR3 WUFIE LL_USART_IsEnabledIT_WKUP + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_WKUP(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR3, USART_CR3_WUFIE) == (USART_CR3_WUFIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if USART TX FIFO Threshold Interrupt is enabled or disabled + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR3 TXFTIE LL_USART_IsEnabledIT_TXFT + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXFT(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR3, USART_CR3_TXFTIE) == (USART_CR3_TXFTIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the Smartcard Transmission Complete Before Guard Time Interrupt is enabled or disabled. + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR3 TCBGTIE LL_USART_IsEnabledIT_TCBGT + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TCBGT(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR3, USART_CR3_TCBGTIE) == (USART_CR3_TCBGTIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if USART RX FIFO Threshold Interrupt is enabled or disabled + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR3 RXFTIE LL_USART_IsEnabledIT_RXFT + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXFT(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR3, USART_CR3_RXFTIE) == (USART_CR3_RXFTIE)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_DMA_Management DMA_Management + * @{ + */ + +/** + * @brief Enable DMA Mode for reception + * @rmtoll CR3 DMAR LL_USART_EnableDMAReq_RX + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableDMAReq_RX(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_DMAR); +} + +/** + * @brief Disable DMA Mode for reception + * @rmtoll CR3 DMAR LL_USART_DisableDMAReq_RX + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableDMAReq_RX(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_DMAR); +} + +/** + * @brief Check if DMA Mode is enabled for reception + * @rmtoll CR3 DMAR LL_USART_IsEnabledDMAReq_RX + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_RX(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR)) ? 1UL : 0UL); +} + +/** + * @brief Enable DMA Mode for transmission + * @rmtoll CR3 DMAT LL_USART_EnableDMAReq_TX + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableDMAReq_TX(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_DMAT); +} + +/** + * @brief Disable DMA Mode for transmission + * @rmtoll CR3 DMAT LL_USART_DisableDMAReq_TX + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableDMAReq_TX(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_DMAT); +} + +/** + * @brief Check if DMA Mode is enabled for transmission + * @rmtoll CR3 DMAT LL_USART_IsEnabledDMAReq_TX + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_TX(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT)) ? 1UL : 0UL); +} + +/** + * @brief Enable DMA Disabling on Reception Error + * @rmtoll CR3 DDRE LL_USART_EnableDMADeactOnRxErr + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableDMADeactOnRxErr(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_DDRE); +} + +/** + * @brief Disable DMA Disabling on Reception Error + * @rmtoll CR3 DDRE LL_USART_DisableDMADeactOnRxErr + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableDMADeactOnRxErr(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_DDRE); +} + +/** + * @brief Indicate if DMA Disabling on Reception Error is disabled + * @rmtoll CR3 DDRE LL_USART_IsEnabledDMADeactOnRxErr + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledDMADeactOnRxErr(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE)) ? 1UL : 0UL); +} + +/** + * @brief Get the data register address used for DMA transfer + * @rmtoll RDR RDR LL_USART_DMA_GetRegAddr\n + * @rmtoll TDR TDR LL_USART_DMA_GetRegAddr + * @param USARTx USART Instance + * @param Direction This parameter can be one of the following values: + * @arg @ref LL_USART_DMA_REG_DATA_TRANSMIT + * @arg @ref LL_USART_DMA_REG_DATA_RECEIVE + * @retval Address of data register + */ +__STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(const USART_TypeDef *USARTx, uint32_t Direction) +{ + uint32_t data_reg_addr; + + if (Direction == LL_USART_DMA_REG_DATA_TRANSMIT) + { + /* return address of TDR register */ + data_reg_addr = (uint32_t) &(USARTx->TDR); + } + else + { + /* return address of RDR register */ + data_reg_addr = (uint32_t) &(USARTx->RDR); + } + + return data_reg_addr; +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_Data_Management Data_Management + * @{ + */ + +/** + * @brief Read Receiver Data register (Receive Data value, 8 bits) + * @rmtoll RDR RDR LL_USART_ReceiveData8 + * @param USARTx USART Instance + * @retval Value between Min_Data=0x00 and Max_Data=0xFF + */ +__STATIC_INLINE uint8_t LL_USART_ReceiveData8(const USART_TypeDef *USARTx) +{ + return (uint8_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR) & 0xFFU); +} + +/** + * @brief Read Receiver Data register (Receive Data value, 9 bits) + * @rmtoll RDR RDR LL_USART_ReceiveData9 + * @param USARTx USART Instance + * @retval Value between Min_Data=0x00 and Max_Data=0x1FF + */ +__STATIC_INLINE uint16_t LL_USART_ReceiveData9(const USART_TypeDef *USARTx) +{ + return (uint16_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR)); +} + +/** + * @brief Write in Transmitter Data Register (Transmit Data value, 8 bits) + * @rmtoll TDR TDR LL_USART_TransmitData8 + * @param USARTx USART Instance + * @param Value between Min_Data=0x00 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_USART_TransmitData8(USART_TypeDef *USARTx, uint8_t Value) +{ + USARTx->TDR = Value; +} + +/** + * @brief Write in Transmitter Data Register (Transmit Data value, 9 bits) + * @rmtoll TDR TDR LL_USART_TransmitData9 + * @param USARTx USART Instance + * @param Value between Min_Data=0x00 and Max_Data=0x1FF + * @retval None + */ +__STATIC_INLINE void LL_USART_TransmitData9(USART_TypeDef *USARTx, uint16_t Value) +{ + USARTx->TDR = (uint16_t)(Value & 0x1FFUL); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_Execution Execution + * @{ + */ + +/** + * @brief Request an Automatic Baud Rate measurement on next received data frame + * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not + * Auto Baud Rate detection feature is supported by the USARTx instance. + * @rmtoll RQR ABRRQ LL_USART_RequestAutoBaudRate + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_RequestAutoBaudRate(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_ABRRQ); +} + +/** + * @brief Request Break sending + * @rmtoll RQR SBKRQ LL_USART_RequestBreakSending + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_RequestBreakSending(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_SBKRQ); +} + +/** + * @brief Put USART in mute mode and set the RWU flag + * @rmtoll RQR MMRQ LL_USART_RequestEnterMuteMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_RequestEnterMuteMode(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_MMRQ); +} + +/** + * @brief Request a Receive Data and FIFO flush + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @note Allows to discard the received data without reading them, and avoid an overrun + * condition. + * @rmtoll RQR RXFRQ LL_USART_RequestRxDataFlush + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_RequestRxDataFlush(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_RXFRQ); +} + +/** + * @brief Request a Transmit data and FIFO flush + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll RQR TXFRQ LL_USART_RequestTxDataFlush + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_RequestTxDataFlush(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_TXFRQ); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup USART_LL_EF_Init Initialization and de-initialization functions + * @{ + */ +ErrorStatus LL_USART_DeInit(const USART_TypeDef *USARTx); +ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, const LL_USART_InitTypeDef *USART_InitStruct); +void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct); +ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, const LL_USART_ClockInitTypeDef *USART_ClockInitStruct); +void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct); +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* USART1 || USART2 */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32WLxx_LL_USART_H */ + diff --git a/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_utils.h b/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_utils.h new file mode 100644 index 0000000..6e4f59b --- /dev/null +++ b/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_utils.h @@ -0,0 +1,333 @@ +/** + ****************************************************************************** + * @file stm32wlxx_ll_utils.h + * @author MCD Application Team + * @brief Header file of UTILS LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The LL UTILS driver contains a set of generic APIs that can be + used by user: + (+) Device electronic signature + (+) Timing functions + (+) PLL configuration functions + + @endverbatim + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32WLxx_LL_UTILS_H +#define __STM32WLxx_LL_UTILS_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wlxx.h" + +/** @addtogroup STM32WLxx_LL_Driver + * @{ + */ + +/** @defgroup UTILS_LL UTILS + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup UTILS_LL_Private_Constants UTILS Private Constants + * @{ + */ + +/* Max delay can be used in LL_mDelay */ +#define LL_MAX_DELAY 0xFFFFFFFFU + +/** + * @brief Unique device ID register base address + */ +#define UID_BASE_ADDRESS UID_BASE + +/** + * @brief Flash size data register base address + */ +#define FLASHSIZE_BASE_ADDRESS FLASHSIZE_BASE + +/** + * @brief Package data register base address + */ +#define PACKAGE_BASE_ADDRESS PACKAGE_BASE + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup UTILS_LL_Private_Macros UTILS Private Macros + * @{ + */ +/** + * @} + */ +/* Exported types ------------------------------------------------------------*/ +/** @defgroup UTILS_LL_ES_INIT UTILS Exported structures + * @{ + */ +/** + * @brief UTILS PLL structure definition + */ +typedef struct +{ + uint32_t PLLM; /*!< Division factor for PLL VCO input clock. + This parameter can be a value of @ref RCC_LL_EC_PLLM_DIV + + This feature can be modified afterwards using unitary function + @ref LL_RCC_PLL_ConfigDomain_SYS(). */ + + uint32_t PLLN; /*!< Multiplication factor for PLL VCO output clock. + This parameter must be a number between Min_Data = 6 and Max_Data = 127 + + This feature can be modified afterwards using unitary function + @ref LL_RCC_PLL_ConfigDomain_SYS(). */ + + uint32_t PLLR; /*!< Division for the main system clock. + This parameter can be a value of @ref RCC_LL_EC_PLLR_DIV + + This feature can be modified afterwards using unitary function + @ref LL_RCC_PLL_ConfigDomain_SYS(). */ +} LL_UTILS_PLLInitTypeDef; + +/** + * @brief UTILS System, AHB and APB buses clock configuration structure definition + */ +typedef struct +{ + uint32_t CPU1CLKDivider; /*!< The CPU1 clock (HCLK1) divider. This clock is derived from the system clock + (SYSCLK). + This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV + + This feature can be modified afterwards using unitary function + @ref LL_RCC_SetAHBPrescaler(). */ + +#if defined(DUAL_CORE) + uint32_t CPU2CLKDivider; /*!< The CPU2 clock (HCLK2) divider. This clock is derived from the system clock + (SYSCLK). + This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV + + This feature can be modified afterwards using unitary function + @ref LL_C2_RCC_SetAHBPrescaler(). */ +#endif /* DUAL_CORE */ + + uint32_t AHB3CLKDivider; /*!< The AHBS clock (HCLK3) divider. This clock is derived from the system clock + (SYSCLK). + This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV + + This feature can be modified afterwards using unitary function + @ref LL_RCC_SetAHB3Prescaler(). */ + + uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK1). + This parameter can be a value of @ref RCC_LL_EC_APB1_DIV + + This feature can be modified afterwards using unitary function + @ref LL_RCC_SetAPB1Prescaler(). */ + + uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK1). + This parameter can be a value of @ref RCC_LL_EC_APB2_DIV + + This feature can be modified afterwards using unitary function + @ref LL_RCC_SetAPB2Prescaler(). */ + +} LL_UTILS_ClkInitTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup UTILS_LL_Exported_Constants UTILS Exported Constants + * @{ + */ + +/** @defgroup UTILS_EC_HSE_BYPASS HSE Bypass activation + * @{ + */ +#define LL_UTILS_HSEBYPASS_OFF 0x00000000U /*!< HSE Bypass is not enabled */ +#define LL_UTILS_HSEBYPASS_ON 0x00000001U /*!< HSE Bypass is enabled */ +/** + * @} + */ + +/** @defgroup UTILS_EC_PACKAGETYPE PACKAGE TYPE + * @{ + */ +#define LL_UTILS_PACKAGETYPE_UFBGA73 0x00000000U /*!< UFBGA73 package type */ +#define LL_UTILS_PACKAGETYPE_WLCSP59 0x00000002U /*!< WLSCSP59 package type */ +#define LL_UTILS_PACKAGETYPE_UFQFPN48 0x0000000AU /*!< UFQPFN48 package type */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup UTILS_LL_Exported_Functions UTILS Exported Functions + * @{ + */ + +/** @defgroup UTILS_EF_DEVICE_ELECTRONIC_SIGNATURE DEVICE ELECTRONIC SIGNATURE + * @{ + */ +/** + * @brief Get Word0 of the unique device identifier (UID based on 96 bits) + * @retval UID[31:0]: X and Y coordinates on the wafer expressed in BCD format + */ +__STATIC_INLINE uint32_t LL_GetUID_Word0(void) +{ + return (uint32_t)(READ_REG(*((uint32_t *)UID_BASE_ADDRESS))); +} + +/** + * @brief Get Word1 of the unique device identifier (UID based on 96 bits) + * @retval UID[63:32]: Wafer number (UID[39:32]) & LOT_NUM[23:0] (UID[63:40]) + */ +__STATIC_INLINE uint32_t LL_GetUID_Word1(void) +{ + return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 4U)))); +} + +/** + * @brief Get Word2 of the unique device identifier (UID based on 96 bits) + * @retval UID[95:64]: Lot number (ASCII encoded) - LOT_NUM[55:24] + */ +__STATIC_INLINE uint32_t LL_GetUID_Word2(void) +{ + return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 8U)))); +} + +/** + * @brief Get Flash memory size + * @note This bitfield indicates the size of the device Flash memory expressed in + * Kbytes. As an example, 0x040 corresponds to 64 Kbytes. + * @retval FLASH_SIZE[15:0]: Flash memory size + */ +__STATIC_INLINE uint32_t LL_GetFlashSize(void) +{ + return (uint32_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS)) & 0xFFFFUL); +} + +/** + * @brief Get Package type + * @retval Returned value can be one of the following values: + * @arg @ref LL_UTILS_PACKAGETYPE_UFBGA73 + * @arg @ref LL_UTILS_PACKAGETYPE_UFQFPN48 + * @arg @ref LL_UTILS_PACKAGETYPE_WLCSP59 + * + */ +__STATIC_INLINE uint32_t LL_GetPackageType(void) +{ + return (uint32_t)(READ_REG(*((uint32_t *)PACKAGE_BASE_ADDRESS)) & 0x1FU); +} + +/** + * @} + */ + +/** @defgroup UTILS_LL_EF_DELAY DELAY + * @{ + */ +#if defined(CORE_CM0PLUS) +/** + * @brief This function configures the Cortex-M SysTick source of the time base. + * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro or function + * @ref LL_RCC_GetSystemClocksFreq (HCLK2_Frequency field)) + * @note When a RTOS is used, it is recommended to avoid changing the SysTick + * configuration by calling this function, for a delay use rather osDelay RTOS service. + * @param Ticks Frequency of Ticks (Hz) + * @retval None + */ +#else +/** + * @brief This function configures the Cortex-M SysTick source of the time base. + * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro or function + * @ref LL_RCC_GetSystemClocksFreq (HCLK1_Frequency field)) + * @note When a RTOS is used, it is recommended to avoid changing the SysTick + * configuration by calling this function, for a delay use rather osDelay RTOS service. + * @param Ticks Frequency of Ticks (Hz) + * @retval None + */ +#endif /* CORE_CM0PLUS */ +__STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks) +{ + if (Ticks > 0U) + { + /* Configure the SysTick to have interrupt in 1ms time base */ + SysTick->LOAD = (uint32_t)((HCLKFrequency / Ticks) - 1UL); /* set reload register */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable the Systick Timer */ + } +} + +void LL_Init1msTick(uint32_t HCLKFrequency); + +void LL_mDelay(uint32_t Delay); + +/** + * @} + */ + +/** @defgroup UTILS_EF_SYSTEM SYSTEM + * @{ + */ + +void LL_SetSystemCoreClock(uint32_t HCLKFrequency); +ErrorStatus LL_SetFlashLatency(uint32_t HCLK3_Frequency); +ErrorStatus LL_PLL_ConfigSystemClock_MSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, + LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); +ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, + LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); +ErrorStatus LL_PLL_ConfigSystemClock_HSE(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, + LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32WLxx_LL_UTILS_H */ diff --git a/Drivers/STM32WLxx_HAL_Driver/LICENSE.txt b/Drivers/STM32WLxx_HAL_Driver/LICENSE.txt new file mode 100644 index 0000000..3edc4d1 --- /dev/null +++ b/Drivers/STM32WLxx_HAL_Driver/LICENSE.txt @@ -0,0 +1,6 @@ +This software component is provided to you as part of a software package and +applicable license terms are in the Package_license file. If you received this +software component outside of a package or without applicable license terms, +the terms of the BSD-3-Clause license shall apply. +You may obtain a copy of the BSD-3-Clause at: +https://opensource.org/licenses/BSD-3-Clause diff --git a/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c b/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c new file mode 100644 index 0000000..7ebe990 --- /dev/null +++ b/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c @@ -0,0 +1,1017 @@ +/** + ****************************************************************************** + * @file stm32wlxx_hal.c + * @author MCD Application Team + * @brief HAL module driver. + * This is the common part of the HAL initialization + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The common HAL driver contains a set of generic and common APIs that can be + used by the PPP peripheral drivers and the user to start using the HAL. + [..] + The HAL contains two APIs' categories: + (+) Common HAL APIs + (+) Services HAL APIs + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wlxx_hal.h" + +/** @addtogroup STM32WLxx_HAL_Driver + * @{ + */ + +/** @addtogroup HAL + * @brief HAL module driver + * @{ + */ + +#ifdef HAL_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/** @defgroup HAL_Private_Constants HAL Private Constants + * @{ + */ +/** + * @brief STM32WLxx HAL Driver version number + */ +#define __STM32WLxx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ +#define __STM32WLxx_HAL_VERSION_SUB1 (0x04U) /*!< [23:16] sub1 version */ +#define __STM32WLxx_HAL_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */ +#define __STM32WLxx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ +#define __STM32WLxx_HAL_VERSION ((__STM32WLxx_HAL_VERSION_MAIN << 24U)\ + |(__STM32WLxx_HAL_VERSION_SUB1 << 16U)\ + |(__STM32WLxx_HAL_VERSION_SUB2 << 8U )\ + |(__STM32WLxx_HAL_VERSION_RC)) + +#define VREFBUF_TIMEOUT_VALUE 10U /* 10 ms */ + +#if defined(STM32WL5Mxx) +#define RADIO_SWITCH_CTRL_GPIO_PORT GPIOC +#define RADIO_SWITCH_CTRL_GPIO_CLK_ENABLE() __HAL_RCC_GPIOC_CLK_ENABLE() +#define RADIO_SWITCH_CTRL_GPIO_CLK_DISABLE() __HAL_RCC_GPIOC_CLK_DISABLE() + +#define RADIO_SWITCH_CTRL3_PIN GPIO_PIN_3 +#define RADIO_SWITCH_CTRL1_PIN GPIO_PIN_4 +#define RADIO_SWITCH_CTRL2_PIN GPIO_PIN_5 + +#endif /* STM32WL5Mxx */ + +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Exported variables ---------------------------------------------------------*/ +/** @defgroup HAL_Exported_Variables HAL Exported Variables + * @{ + */ +__IO uint32_t uwTick; +uint32_t uwTickPrio = (1UL << __NVIC_PRIO_BITS); /* Invalid PRIO */ +HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */ +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup HAL_Exported_Functions + * @{ + */ + +/** @addtogroup HAL_Exported_Functions_Group1 + * @brief HAL Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### HAL Initialization and Configuration functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Initialize the Flash interface the NVIC allocation and initial time base + clock configuration. + (+) De-initialize common part of the HAL. + (+) Configure the time base source to have 1ms time base with a dedicated + Tick interrupt priority. + (++) SysTick timer is used by default as source of time base, but user + can eventually implement his proper time base source (a general purpose + timer for example or other time source), keeping in mind that Time base + duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and + handled in milliseconds basis. + (++) Time base configuration function (HAL_InitTick ()) is called automatically + at the beginning of the program after reset by HAL_Init() or at any time + when clock is configured, by HAL_RCC_ClockConfig(). + (++) Source of time base is configured to generate interrupts at regular + time intervals. Care must be taken if HAL_Delay() is called from a + peripheral ISR process, the Tick interrupt line must have higher priority + (numerically lower) than the peripheral interrupt. Otherwise the caller + ISR process will be blocked. + (++) functions affecting time base configurations are declared as __weak + to make override possible in case of other implementations in user file. +@endverbatim + * @{ + */ + +/** + * @brief This function is used to initialize the HAL Library; it must be the first + * instruction to be executed in the main program (before to call any other + * HAL function), it performs the following: + * Configure the Flash prefetch, instruction and Data caches. + * Configures the SysTick to generate an interrupt each 1 millisecond, + * which is clocked by the MSI (at this stage, the clock is not yet + * configured and thus the system is running from the internal MSI at 4 MHz). + * Set NVIC Group Priority to 4. + * Calls the HAL_MspInit() callback function defined in user file + * "stm32wlxx_hal_msp.c" to do the global low level hardware initialization + * + * @note SysTick is used as time base for the HAL_Delay() function, the application + * need to ensure that the SysTick time base is always set to 1 millisecond + * to have correct HAL operation. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_Init(void) +{ + HAL_StatusTypeDef status = HAL_OK; + /* Configure Flash prefetch, Instruction cache, Data cache */ + /* Default configuration at reset is: */ + /* - Prefetch disabled */ + /* - Instruction cache enabled */ + /* - Data cache enabled */ +#if (INSTRUCTION_CACHE_ENABLE == 0U) + __HAL_FLASH_INSTRUCTION_CACHE_DISABLE(); +#endif /* INSTRUCTION_CACHE_ENABLE */ + +#ifdef CORE_CM0PLUS +#else +#if (DATA_CACHE_ENABLE == 0U) + __HAL_FLASH_DATA_CACHE_DISABLE(); +#endif /* DATA_CACHE_ENABLE */ +#endif + +#if (PREFETCH_ENABLE != 0U) + __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); +#endif /* PREFETCH_ENABLE */ + +#ifdef CORE_CM0PLUS +#else + /* Set Interrupt Group Priority */ + HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); +#endif + + /* Update the SystemCoreClock global variable */ +#if defined(DUAL_CORE) && defined(CORE_CM0PLUS) + SystemCoreClock = HAL_RCC_GetHCLK2Freq(); +#else + SystemCoreClock = HAL_RCC_GetHCLKFreq(); +#endif + + /* Use SysTick as time base source and configure 1ms tick (default clock after Reset is MSI) */ + if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) + { + status = HAL_ERROR; + } + else + { + /* Init the low level hardware */ + HAL_MspInit(); + } + + /* Return function status */ + return status; +} + +/** + * @brief This function de-Initializes common part of the HAL and stops the source of time base. + * @note This function is optional. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DeInit(void) +{ + /* Reset of all peripherals */ + __HAL_RCC_APB1_FORCE_RESET(); + __HAL_RCC_APB1_RELEASE_RESET(); + + __HAL_RCC_APB2_FORCE_RESET(); + __HAL_RCC_APB2_RELEASE_RESET(); + + __HAL_RCC_APB3_FORCE_RESET(); + __HAL_RCC_APB3_RELEASE_RESET(); + + __HAL_RCC_AHB1_FORCE_RESET(); + __HAL_RCC_AHB1_RELEASE_RESET(); + + __HAL_RCC_AHB2_FORCE_RESET(); + __HAL_RCC_AHB2_RELEASE_RESET(); + + __HAL_RCC_AHB3_FORCE_RESET(); + __HAL_RCC_AHB3_RELEASE_RESET(); + + /* De-Init the low level hardware */ + HAL_MspDeInit(); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Initialize the MSP. + * @retval None + */ +__weak void HAL_MspInit(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes the MSP. + * @retval None + */ +__weak void HAL_MspDeInit(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief This function configures the source of the time base: + * The time source is configured to have 1ms time base with a dedicated + * Tick interrupt priority. + * @note This function is called automatically at the beginning of program after + * reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig(). + * @note In the default implementation, SysTick timer is the source of time base. + * It is used to generate interrupts at regular time intervals. + * Care must be taken if HAL_Delay() is called from a peripheral ISR process, + * The SysTick interrupt must have higher priority (numerically lower) + * than the peripheral interrupt. Otherwise the caller ISR process will be blocked. + * The function is declared as __weak to be overwritten in case of other + * implementation in user file. + * @param TickPriority Tick interrupt priority. + * @retval HAL status + */ +__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check uwTickFreq for MisraC 2012 (even if uwTickFreq is a enum type that don't take the value zero)*/ + if ((uint32_t)uwTickFreq != 0U) + { + /*Configure the SysTick to have interrupt in 1ms time basis*/ +#ifdef CORE_CM0PLUS + if (HAL_SYSTICK_Config(HAL_RCC_GetHCLK2Freq() / (1000U / (uint32_t)uwTickFreq)) == 0U) +#else + if (HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq() / (1000U / (uint32_t)uwTickFreq)) == 0U) +#endif + { + /* Configure the SysTick IRQ priority */ + if (TickPriority < (1UL << __NVIC_PRIO_BITS)) + { + HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); + uwTickPrio = TickPriority; + } + else + { + status = HAL_ERROR; + } + } + else + { + status = HAL_ERROR; + } + } + else + { + status = HAL_ERROR; + } + + /* Return function status */ + return status; +} + +/** + * @} + */ + +/** @addtogroup HAL_Exported_Functions_Group2 + * @brief HAL Control functions + * +@verbatim + =============================================================================== + ##### HAL Control functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Provide a tick value in millisecond + (+) Provide a blocking delay in millisecond + (+) Suspend the time base source interrupt + (+) Resume the time base source interrupt + (+) Get the HAL API driver version + (+) Get the device revision identifier + (+) Get the device identifier + (+) Get the unique device identifier + +@endverbatim + * @{ + */ + +/** + * @brief This function is called to increment a global variable "uwTick" + * used as application time base. + * @note In the default implementation, this variable is incremented each 1ms + * in SysTick ISR. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void HAL_IncTick(void) +{ + uwTick += (uint32_t)uwTickFreq; +} + +/** + * @brief Provides a tick value in millisecond. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval tick value + */ +__weak uint32_t HAL_GetTick(void) +{ + return uwTick; +} + +/** + * @brief This function returns a tick priority. + * @retval tick priority + */ +uint32_t HAL_GetTickPrio(void) +{ + return uwTickPrio; +} + +/** + * @brief Set new tick Freq. + * @retval Status + */ +HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq) +{ + HAL_StatusTypeDef status = HAL_OK; + HAL_TickFreqTypeDef prevTickFreq; + assert_param(IS_TICKFREQ(Freq)); + + if (uwTickFreq != Freq) + { + /* Back up uwTickFreq frequency */ + prevTickFreq = uwTickFreq; + + /* Update uwTickFreq global variable used by HAL_InitTick() */ + uwTickFreq = Freq; + + /* Apply the new tick Freq */ + status = HAL_InitTick(uwTickPrio); + + if (status != HAL_OK) + { + /* Restore previous tick frequency */ + uwTickFreq = prevTickFreq; + } + } + + return status; +} + +/** + * @brief Return tick frequency. + * @retval Tick frequency. + * Value of @ref HAL_TickFreqTypeDef. + */ +HAL_TickFreqTypeDef HAL_GetTickFreq(void) +{ + return uwTickFreq; +} + +/** + * @brief This function provides minimum delay (in milliseconds) based + * on variable incremented. + * @note In the default implementation , SysTick timer is the source of time base. + * It is used to generate interrupts at regular time intervals where uwTick + * is incremented. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @param Delay specifies the delay time length, in milliseconds. + * @retval None + */ +__weak void HAL_Delay(uint32_t Delay) +{ + uint32_t tickstart = HAL_GetTick(); + uint32_t wait = Delay; + + /* Add a freq to guarantee minimum wait */ + if (wait < HAL_MAX_DELAY) + { + wait += (uint32_t)(uwTickFreq); + } + + while ((HAL_GetTick() - tickstart) < wait) + { + } +} + + +/** + * @brief Suspend Tick increment. + * @note In the default implementation , SysTick timer is the source of time base. It is + * used to generate interrupts at regular time intervals. Once HAL_SuspendTick() + * is called, the SysTick interrupt will be disabled and so Tick increment + * is suspended. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void HAL_SuspendTick(void) +{ + /* Disable SysTick Interrupt */ + CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); +} + +/** + * @brief Resume Tick increment. + * @note In the default implementation , SysTick timer is the source of time base. It is + * used to generate interrupts at regular time intervals. Once HAL_ResumeTick() + * is called, the SysTick interrupt will be enabled and so Tick increment + * is resumed. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void HAL_ResumeTick(void) +{ + /* Enable SysTick Interrupt */ + SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); +} + +/** + * @brief Returns the HAL revision + * @retval version : 0xXYZR (8bits for each decimal, R for RC) + */ +uint32_t HAL_GetHalVersion(void) +{ + return __STM32WLxx_HAL_VERSION; +} + +#if defined(CORE_CM0PLUS) +#else +/** + * @brief Returns the device revision identifier. + * @retval Device revision identifier + */ +uint32_t HAL_GetREVID(void) +{ + return (LL_DBGMCU_GetRevisionID()); +} + +/** + * @brief Returns the device identifier. + * @retval Device identifier + */ +uint32_t HAL_GetDEVID(void) +{ + return (LL_DBGMCU_GetDeviceID()); +} +#endif + +/** + * @brief Return the first word of the unique device identifier (UID based on 96 bits) + * @retval Device identifier + */ +uint32_t HAL_GetUIDw0(void) +{ + return (READ_REG(*((uint32_t *)UID_BASE))); +} + +/** + * @brief Return the second word of the unique device identifier (UID based on 96 bits) + * @retval Device identifier + */ +uint32_t HAL_GetUIDw1(void) +{ + return (READ_REG(*((uint32_t *)(UID_BASE + 4U)))); +} + +/** + * @brief Return the third word of the unique device identifier (UID based on 96 bits) + * @retval Device identifier + */ +uint32_t HAL_GetUIDw2(void) +{ + return (READ_REG(*((uint32_t *)(UID_BASE + 8U)))); +} + +/** + * @} + */ + +/** @addtogroup HAL_Exported_Functions_Group3 + * @brief HAL Debug functions + * +@verbatim + =============================================================================== + ##### HAL Debug functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Enable/Disable Debug module during SLEEP mode + (+) Enable/Disable Debug module during STOP mode + (+) Enable/Disable Debug module during STANDBY mode + +@endverbatim + * @{ + */ + +#if defined(CORE_CM0PLUS) +#else +/** + * @brief Enable the CPU1 Debug Module during SLEEP mode + * @retval None + */ +void HAL_DBGMCU_EnableDBGSleepMode(void) +{ + LL_DBGMCU_EnableDBGSleepMode(); +} + +/** + * @brief Disable the CPU1 Debug Module during SLEEP mode + * @retval None + */ +void HAL_DBGMCU_DisableDBGSleepMode(void) +{ + LL_DBGMCU_DisableDBGSleepMode(); +} + +/** + * @brief Enable the Debug Module during STOP mode + * @note This functionality does not influence CPU2 operation, CPU2 cannot be debugged + * in Stop mode even when this bit is enabled + * @retval None + */ +void HAL_DBGMCU_EnableDBGStopMode(void) +{ + LL_DBGMCU_EnableDBGStopMode(); +} + +/** + * @brief Disable the CPU1 Debug Module during STOP mode + * @retval None + */ +void HAL_DBGMCU_DisableDBGStopMode(void) +{ + LL_DBGMCU_DisableDBGStopMode(); +} + +/** + * @brief Enable the Debug Module during STANDBY mode + * @note This functionality does not influence CPU2 operation, CPU2 cannot be debugged + * in Standby mode even when this bit is enabled + * @retval None + */ +void HAL_DBGMCU_EnableDBGStandbyMode(void) +{ + LL_DBGMCU_EnableDBGStandbyMode(); +} + +/** + * @brief Disable the CPU1 Debug Module during STANDBY mode + * @retval None + */ +void HAL_DBGMCU_DisableDBGStandbyMode(void) +{ + LL_DBGMCU_DisableDBGStandbyMode(); +} +#endif + +/** + * @} + */ + +/** @defgroup HAL_Exported_Functions_Group4 HAL System Configuration functions + * @brief HAL System Configuration functions + * +@verbatim + =============================================================================== + ##### HAL system configuration functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Start a hardware SRAM2 erase operation + (+) Configure the Voltage reference buffer + (+) Enable/Disable the Voltage reference buffer + (+) Enable/Disable the I/O analog switch voltage booster + +@endverbatim + * @{ + */ + +/** + * @brief Start a hardware SRAM2 erase operation. + * @note As long as SRAM2 is not erased the SRAM2ER bit will be set. + * This bit is automatically reset at the end of the SRAM2 erase operation. + * @retval None + */ +void HAL_SYSCFG_SRAM2Erase(void) +{ + /* unlock the write protection of the SRAM2ER bit */ + __HAL_SYSCFG_SRAM2_WRP_UNLOCK(); + /* Starts a hardware SRAM2 erase operation*/ + __HAL_SYSCFG_SRAM2_ERASE(); +} + +/** + * @brief Configure the internal voltage reference buffer voltage scale. + * @param VoltageScaling specifies the output voltage to achieve + * This parameter can be one of the following values: + * @arg @ref SYSCFG_VREFBUF_VOLTAGE_SCALE0 : VREF_OUT1 around 2.048 V. + * This requires VDDA equal to or higher than 2.4 V. + * @arg @ref SYSCFG_VREFBUF_VOLTAGE_SCALE1 : VREF_OUT1 around 2.5 V. + * This requires VDDA equal to or higher than 2.8 V. + * @note Retrieve the TrimmingValue from factory located at + * VREFBUF_SC0_CAL_ADDR or VREFBUF_SC1_CAL_ADDR addresses. + * @retval None + */ +void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling) +{ + uint32_t TrimmingValue; + + /* Check the parameters */ + assert_param(IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(VoltageScaling)); + + LL_VREFBUF_SetVoltageScaling(VoltageScaling); + + /* Restrieve Calibration data and store them into trimming field */ + if (VoltageScaling == SYSCFG_VREFBUF_VOLTAGE_SCALE0) + { + TrimmingValue = ((uint32_t) * VREFBUF_SC0_CAL_ADDR) & 0x3FU; + } + else + { + TrimmingValue = ((uint32_t) * VREFBUF_SC1_CAL_ADDR) & 0x3FU; + } + assert_param(IS_SYSCFG_VREFBUF_TRIMMING(TrimmingValue)); + + HAL_SYSCFG_VREFBUF_TrimmingConfig(TrimmingValue); +} + +/** + * @brief Configure the internal voltage reference buffer high impedance mode. + * @param Mode specifies the high impedance mode + * This parameter can be one of the following values: + * @arg @ref SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE : VREF+ pin is internally connect to VREFINT output. + * @arg @ref SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE : VREF+ pin is high impedance. + * @retval HAL_OK/HAL_TIMEOUT + */ +void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode) +{ + + /* Check the parameters */ + assert_param(IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(Mode)); + + MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_HIZ, Mode); +} + +/** + * @brief Tune the Internal Voltage Reference buffer (VREFBUF). + * @note Each VrefBuf voltage scale is calibrated in production for each device, + * data stored in flash memory. + * Function @ref HAL_SYSCFG_VREFBUF_VoltageScalingConfig retrieves and + * applies this calibration data as trimming value at each scale change. + * Therefore, optionally, function @ref HAL_SYSCFG_VREFBUF_TrimmingConfig + * can be used in a second time to fine tune the trimming. + * @param TrimmingValue specifies trimming code for VREFBUF calibration + * This parameter can be a number between Min_Data = 0x00 and Max_Data = 0x3F + * @retval None + */ +void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue) +{ + /* Check the parameters */ + assert_param(IS_SYSCFG_VREFBUF_TRIMMING(TrimmingValue)); + + LL_VREFBUF_SetTrimming(TrimmingValue); + +} + +/** + * @brief Enable the Internal Voltage Reference buffer (VREFBUF). + * @retval HAL_OK/HAL_TIMEOUT + */ +HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void) +{ + uint32_t tickstart; + + LL_VREFBUF_Enable(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait for VRR bit */ + while (READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRR) == 0U) + { + if ((HAL_GetTick() - tickstart) > VREFBUF_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + return HAL_OK; +} + +/** + * @brief Disable the Internal Voltage Reference buffer (VREFBUF). + * + * @retval None + */ +void HAL_SYSCFG_DisableVREFBUF(void) +{ + LL_VREFBUF_Disable(); +} + +/** + * @brief Enable the I/O analog switch voltage booster + * + * @retval None + */ +void HAL_SYSCFG_EnableIOAnalogSwitchBooster(void) +{ + LL_SYSCFG_EnableAnalogBooster(); +} + +/** + * @brief Disable the I/O analog switch voltage booster + * + * @retval None + */ +void HAL_SYSCFG_DisableIOAnalogSwitchBooster(void) +{ + LL_SYSCFG_DisableAnalogBooster(); +} + +#if defined(DUAL_CORE) +/** + * @brief Enable Additional Interrupt Mask + * @note This interface is an additional interrupt masking interface + * up to the EXTI interface + * @param Interrupt Pointer to a SYSCFG_InterruptTypeDef structure that contains + * the Interrupt Mask configuration + * @retval None + */ +void HAL_SYSCFG_EnableIT(const SYSCFG_InterruptTypeDef *Interrupt) +{ + uint32_t InterruptMask1 = (Interrupt->InterruptMask1 & ~HAL_SYSCFG_GRP1_RESERVED); + uint32_t InterruptMask2 = (Interrupt->InterruptMask2 & ~HAL_SYSCFG_GRP2_RESERVED); + + /* Check the parameters */ + assert_param(IS_SYSCFG_IM_GRP1(Interrupt->InterruptMask1)); + assert_param(IS_SYSCFG_IM_GRP2(Interrupt->InterruptMask2)); + +#if defined(CORE_CM0PLUS) + LL_C2_SYSCFG_GRP1_EnableIT(InterruptMask1); + LL_C2_SYSCFG_GRP2_EnableIT(InterruptMask2); +#else + LL_SYSCFG_GRP1_EnableIT(InterruptMask1); + LL_SYSCFG_GRP2_EnableIT(InterruptMask2); +#endif +} + +/** + * @brief Disable Additional Interrupt Mask + * @note This interface is an additional interrupt masking interface + * up to the EXTI interface + * @param Interrupt Pointer to a SYSCFG_InterruptTypeDef structure that contains + * the Interrupt Mask configuration + * @retval None + */ +void HAL_SYSCFG_DisableIT(const SYSCFG_InterruptTypeDef *Interrupt) +{ + uint32_t InterruptMask1 = (Interrupt->InterruptMask1 & ~HAL_SYSCFG_GRP1_RESERVED); + uint32_t InterruptMask2 = (Interrupt->InterruptMask2 & ~HAL_SYSCFG_GRP2_RESERVED); + + /* Check the parameters */ + assert_param(IS_SYSCFG_IM_GRP1(Interrupt->InterruptMask1)); + assert_param(IS_SYSCFG_IM_GRP2(Interrupt->InterruptMask2)); + +#if defined(CORE_CM0PLUS) + LL_C2_SYSCFG_GRP1_DisableIT(InterruptMask1); + LL_C2_SYSCFG_GRP2_DisableIT(InterruptMask2); +#else + LL_SYSCFG_GRP1_DisableIT(InterruptMask1); + LL_SYSCFG_GRP2_DisableIT(InterruptMask2); +#endif +} +#endif /* DUAL_CORE */ +/** + * @} + */ + +#if defined(STM32WL5Mxx) +/** @defgroup HAL_Exported_Functions_Group5 HAL Radio Configuration functions + * @brief HAL Radio Configuration functions + * +@verbatim + =============================================================================== + ##### HAL Radio configuration functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Enable/Disable the Radio + (+) Configure the Radio to Rx, Tx Low Power or Tx High Power + +@endverbatim + * @{ + */ + +/* RADIO Control functions ****************************************************/ +/** + * @brief Init Radio Switch + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RADIO_Init(void) +{ + HAL_StatusTypeDef status; + GPIO_InitTypeDef gpio_init_structure; + + /* Enable the Radio Switch Clock */ + RADIO_SWITCH_CTRL_GPIO_CLK_ENABLE(); + + /* Configure the Radio Switch pin */ + gpio_init_structure.Pin = (RADIO_SWITCH_CTRL1_PIN | RADIO_SWITCH_CTRL2_PIN | RADIO_SWITCH_CTRL3_PIN); + gpio_init_structure.Mode = GPIO_MODE_OUTPUT_PP; + gpio_init_structure.Pull = GPIO_NOPULL; + gpio_init_structure.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + + HAL_GPIO_Init(RADIO_SWITCH_CTRL_GPIO_PORT, &gpio_init_structure); + + /* Lock RF Switch GPIOs configuration to avoid any user change */ + /* Only a MCU reset will unlock this configuration */ + status = HAL_GPIO_LockPin(RADIO_SWITCH_CTRL_GPIO_PORT, (RADIO_SWITCH_CTRL1_PIN | RADIO_SWITCH_CTRL2_PIN | RADIO_SWITCH_CTRL3_PIN)); + if (status == HAL_OK) + { + /* By default, the RF Switch is off */ + HAL_GPIO_WritePin(RADIO_SWITCH_CTRL_GPIO_PORT, + (RADIO_SWITCH_CTRL1_PIN | RADIO_SWITCH_CTRL2_PIN | RADIO_SWITCH_CTRL3_PIN), GPIO_PIN_RESET); + } + + return status; +} + +/** + * @brief DeInit Radio Switch + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RADIO_DeInit(void) +{ + /* Enable the Radio Switch Clock */ + RADIO_SWITCH_CTRL_GPIO_CLK_ENABLE(); + + /* Turn off switch */ + HAL_GPIO_WritePin(RADIO_SWITCH_CTRL_GPIO_PORT, + (RADIO_SWITCH_CTRL1_PIN | RADIO_SWITCH_CTRL2_PIN | RADIO_SWITCH_CTRL3_PIN), GPIO_PIN_RESET); + + /* Disable the Radio Switch Clock */ + RADIO_SWITCH_CTRL_GPIO_CLK_DISABLE(); + + return HAL_OK; +} + +/** + * @brief Configure Radio Switch. + * @param Config: Specifies the Radio RF switch path to be set. + * This parameter can be one of following parameters: + * @arg RADIO_SWITCH_OFF + * @arg RADIO_SWITCH_RX + * @arg RADIO_SWITCH_RFO_LP + * @arg RADIO_SWITCH_RFO_HP + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RADIO_SetSwitchConfig(HAL_RADIO_SwitchConfig_TypeDef Config) +{ + HAL_StatusTypeDef status = HAL_OK; + + switch (Config) + { + case RADIO_SWITCH_OFF: + { + /* Turn off switch */ + HAL_GPIO_WritePin(RADIO_SWITCH_CTRL_GPIO_PORT, + (RADIO_SWITCH_CTRL1_PIN | RADIO_SWITCH_CTRL2_PIN | RADIO_SWITCH_CTRL3_PIN), GPIO_PIN_RESET); + break; + } + case RADIO_SWITCH_RX: + { + /* Turns On in Rx Mode the RF Switch */ + HAL_GPIO_WritePin(RADIO_SWITCH_CTRL_GPIO_PORT, + (RADIO_SWITCH_CTRL1_PIN | RADIO_SWITCH_CTRL2_PIN | RADIO_SWITCH_CTRL3_PIN), GPIO_PIN_SET); + + break; + } + case RADIO_SWITCH_RFO_LP: + { + /* Turns On in Tx Low Power the RF Switch */ + HAL_GPIO_WriteMultipleStatePin(RADIO_SWITCH_CTRL_GPIO_PORT, RADIO_SWITCH_CTRL2_PIN, + (RADIO_SWITCH_CTRL1_PIN | RADIO_SWITCH_CTRL3_PIN)); + break; + } + case RADIO_SWITCH_RFO_HP: + { + /* Turns On in Tx High Power the RF Switch */ + HAL_GPIO_WriteMultipleStatePin(RADIO_SWITCH_CTRL_GPIO_PORT, RADIO_SWITCH_CTRL1_PIN, + (RADIO_SWITCH_CTRL2_PIN | RADIO_SWITCH_CTRL3_PIN)); + break; + } + default: + { + status = HAL_ERROR; + break; + } + } + + return status; +} + +/** + * @brief Get If TCXO is to be present on board + * @note never remove called by MW, + * @retval + * RADIO_CONF_TCXO_NOT_SUPPORTED + * RADIO_CONF_TCXO_SUPPORTED + */ +uint8_t HAL_RADIO_IsTCXO(void) +{ + return RADIO_CONF_TCXO_SUPPORTED; +} + +/** + * @brief Get If DCDC is to be present on board + * @note never remove called by MW, + * @retval + * RADIO_CONF_DCDC_NOT_SUPPORTED + * RADIO_CONF_DCDC_SUPPORTED + */ +uint8_t HAL_RADIO_IsDCDC(void) +{ + return RADIO_CONF_DCDC_SUPPORTED; +} + +/** + * @brief Return RF Output Max Power Configuration + * @retval + * RADIO_CONF_RFO_LP_MAX_15_dBm for LP mode + * RADIO_CONF_RFO_HP_MAX_22_dBm for HP mode + */ +int32_t HAL_RADIO_GetRFOMaxPowerConfig(HAL_RADIO_RFOMaxPowerConfig_TypeDef Config) +{ + int32_t ret; + + if (Config == RADIO_RFO_LP_MAXPOWER) + { + ret = RADIO_CONF_RFO_LP_MAX_15_dBm; + } + else + { + ret = RADIO_CONF_RFO_HP_MAX_22_dBm; + } + + return ret; +} + +/** + * @} + */ +#endif /* STM32WL5Mxx */ + +/** + * @} + */ + +#endif /* HAL_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ diff --git a/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.c b/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.c new file mode 100644 index 0000000..165797a --- /dev/null +++ b/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.c @@ -0,0 +1,597 @@ +/** + ****************************************************************************** + * @file stm32wlxx_hal_cortex.c + * @author MCD Application Team + * @brief CORTEX HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the CORTEX: + * + Initialization and Configuration functions + * + Peripheral Control functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + + [..] + *** How to configure Interrupts using CORTEX HAL driver *** + =========================================================== + [..] + This section provides functions allowing to configure the NVIC interrupts (IRQ). + The Cortex-M4 exceptions are managed by CMSIS functions. + + (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping() function. + (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority(). + (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ(). + + -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ pre-emption is no more possible. + The pending IRQ priority will be managed only by the sub priority. + + -@- IRQ priority order (sorted by highest to lowest priority): + (+@) Lowest pre-emption priority + (+@) Lowest sub priority + (+@) Lowest hardware priority (IRQ number) + + [..] + *** How to configure Systick using CORTEX HAL driver *** + ======================================================== + [..] + Setup SysTick Timer for time base. + + (+) The HAL_SYSTICK_Config() function calls the SysTick_Config() function which + is a CMSIS function that: + (++) Configures the SysTick Reload register with value passed as function parameter. + (++) Configures the SysTick IRQ priority to the lowest value (0x0F). + (++) Resets the SysTick Counter register. + (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK). + (++) Enables the SysTick Interrupt. + (++) Starts the SysTick Counter. + + (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro + __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the + HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined + inside the stm32wlxx_hal_cortex.h file. + + (+) You can change the SysTick IRQ priority by calling the + HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function + call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function. + + (+) To adjust the SysTick time base, use the following formula: + + Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s) + (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function + (++) Reload Value should not exceed 0xFFFFFF + + @endverbatim + ****************************************************************************** + + The table below gives the allowed values of the pre-emption priority and subpriority according + to the Priority Grouping configuration performed by HAL_NVIC_SetPriorityGrouping() function. + + ========================================================================================================================== + NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description + ========================================================================================================================== + NVIC_PRIORITYGROUP_0 | 0 | 0-15 | 0 bit for pre-emption priority + | | | 4 bits for subpriority + -------------------------------------------------------------------------------------------------------------------------- + NVIC_PRIORITYGROUP_1 | 0-1 | 0-7 | 1 bit for pre-emption priority + | | | 3 bits for subpriority + -------------------------------------------------------------------------------------------------------------------------- + NVIC_PRIORITYGROUP_2 | 0-3 | 0-3 | 2 bits for pre-emption priority + | | | 2 bits for subpriority + -------------------------------------------------------------------------------------------------------------------------- + NVIC_PRIORITYGROUP_3 | 0-7 | 0-1 | 3 bits for pre-emption priority + | | | 1 bit for subpriority + -------------------------------------------------------------------------------------------------------------------------- + NVIC_PRIORITYGROUP_4 | 0-15 | 0 | 4 bits for pre-emption priority + | | | 0 bit for subpriority + ========================================================================================================================== + + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wlxx_hal.h" + +/** @addtogroup STM32WLxx_HAL_Driver + * @{ + */ + +/** @addtogroup CORTEX + * @{ + */ + +#ifdef HAL_CORTEX_MODULE_ENABLED + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup CORTEX_Exported_Functions + * @{ + */ + + +/** @addtogroup CORTEX_Exported_Functions_Group1 + * @brief Initialization and Configuration functions + * +@verbatim + ============================================================================== + ##### Initialization and Configuration functions ##### + ============================================================================== + [..] + This section provides the CORTEX HAL driver functions allowing to configure Interrupts + SysTick functionalities + +@endverbatim + * @{ + */ + +#ifdef CORE_CM0PLUS +/** + * @brief Sets the priority of an interrupt. + * @param IRQn External interrupt number . + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to stm32wlxx.h file) + * @param PreemptPriority The preemption priority for the IRQn channel. + * This parameter can be a value between 0 and 3. + * A lower priority value indicates a higher priority + * @param SubPriority the subpriority level for the IRQ channel. + * with stm32wlxx devices, this parameter is a dummy value and it is ignored, because + * no subpriority supported in Cortex M0+ based products. + * @retval None + */ +void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) +{ + /* Check the parameters */ + assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); + NVIC_SetPriority(IRQn, PreemptPriority); +} +#else +/** + * @brief Set the priority grouping field (pre-emption priority and subpriority) + * using the required unlock sequence. + * @param PriorityGroup The priority grouping bits length. + * This parameter can be one of the following values: + * @arg NVIC_PRIORITYGROUP_0: 0 bit for pre-emption priority, + * 4 bits for subpriority + * @arg NVIC_PRIORITYGROUP_1: 1 bit for pre-emption priority, + * 3 bits for subpriority + * @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority, + * 2 bits for subpriority + * @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority, + * 1 bit for subpriority + * @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority, + * 0 bit for subpriority + * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. + * The pending IRQ priority will be managed only by the subpriority. + * @retval None + */ +void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + /* Check the parameters */ + assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); + + /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ + NVIC_SetPriorityGrouping(PriorityGroup); +} + +/** + * @brief Set the priority of an interrupt. + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer + * to the appropriate CMSIS device file (stm32wlxxxx.h)) + * @param PreemptPriority The pre-emption priority for the IRQn channel. + * This parameter can be a value between 0 and 15 + * A lower priority value indicates a higher priority + * @param SubPriority the subpriority level for the IRQ channel. + * This parameter can be a value between 0 and 15 + * A lower priority value indicates a higher priority. + * @retval None + */ +void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t prioritygroup; + + /* Check the parameters */ + assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); + assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); + + prioritygroup = NVIC_GetPriorityGrouping(); + + NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); +} +#endif /* CORE_CM0PLUS */ + +/** + * @brief Enable a device specific interrupt in the NVIC interrupt controller. + * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig() + * function should be called before. + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer + * to the appropriate CMSIS device file (stm32wlxxxx.h)) + * @retval None + */ +void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Enable interrupt */ + NVIC_EnableIRQ(IRQn); +} + +/** + * @brief Disable a device specific interrupt in the NVIC interrupt controller. + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer + * to the appropriate CMSIS device file (stm32wlxxxx.h)) + * @retval None + */ +void HAL_NVIC_DisableIRQ(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Disable interrupt */ + NVIC_DisableIRQ(IRQn); +} + +/** + * @brief Initiate a system reset request to reset the MCU. + * @retval None + */ +void HAL_NVIC_SystemReset(void) +{ + /* System Reset */ + NVIC_SystemReset(); +} + +/** + * @brief Initialize the System Timer with interrupt enabled and start the System Tick Timer (SysTick): + * Counter is in free running mode to generate periodic interrupts. + * @param TicksNumb Specifies the ticks Number of ticks between two interrupts. + * @retval status: - 0 Function succeeded. + * - 1 Function failed. + */ +uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) +{ + return SysTick_Config(TicksNumb); +} +/** + * @} + */ + +/** @addtogroup CORTEX_Exported_Functions_Group2 + * @brief Cortex control functions + * +@verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to control the CORTEX + (NVIC, SYSTICK, MPU) functionalities. + + +@endverbatim + * @{ + */ + +#ifdef CORE_CM0PLUS +/** + * @brief Get the priority of an interrupt. + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer + * to the appropriate CMSIS device file (stm32wlxxxx.h)) + * @retval None + */ +uint32_t HAL_NVIC_GetPriority(IRQn_Type IRQn) +{ + /* Get priority for Cortex-M system or device specific interrupts */ + return NVIC_GetPriority(IRQn); +} +#else + +/** + * @brief Get the priority grouping field from the NVIC Interrupt Controller. + * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field) + */ +uint32_t HAL_NVIC_GetPriorityGrouping(void) +{ + /* Get the PRIGROUP[10:8] field value */ + return NVIC_GetPriorityGrouping(); +} + +/** + * @brief Get the priority of an interrupt. + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer + * to the appropriate CMSIS device file (stm32wlxxxx.h)) + * @param PriorityGroup the priority grouping bits length. + * This parameter can be one of the following values: + * @arg NVIC_PRIORITYGROUP_0: 0 bit for pre-emption priority, + * 4 bits for subpriority + * @arg NVIC_PRIORITYGROUP_1: 1 bit for pre-emption priority, + * 3 bits for subpriority + * @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority, + * 2 bits for subpriority + * @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority, + * 1 bit for subpriority + * @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority, + * 0 bit for subpriority + * @param pPreemptPriority Pointer on the Preemptive priority value (starting from 0). + * @param pSubPriority Pointer on the Subpriority value (starting from 0). + * @retval None + */ +void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority) +{ + /* Check the parameters */ + assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); + /* Get priority for Cortex-M system or device specific interrupts */ + NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority); +} + +/** + * @brief Get active interrupt (read the active register in NVIC and return the active bit). + * @param IRQn External interrupt number + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer + * to the appropriate CMSIS device file (stm32wlxxxx.h)) + * @retval status: - 0 Interrupt status is not pending. + * - 1 Interrupt status is pending. + */ +uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn) +{ + /* Return 1 if active else 0 */ + return NVIC_GetActive(IRQn); +} + +#endif /* CORE_CM0PLUS */ + +/** + * @brief Set Pending bit of an external interrupt. + * @param IRQn External interrupt number + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer + * to the appropriate CMSIS device file (stm32wlxxxx.h)) + * @retval None + */ +void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Set interrupt pending */ + NVIC_SetPendingIRQ(IRQn); +} + +/** + * @brief Get Pending Interrupt (read the pending register in the NVIC + * and return the pending bit for the specified interrupt). + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer + * to the appropriate CMSIS device file (stm32wlxxxx.h)) + * @retval status: - 0 Interrupt status is not pending. + * - 1 Interrupt status is pending. + */ +uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Return 1 if pending else 0 */ + return NVIC_GetPendingIRQ(IRQn); +} + +/** + * @brief Clear the pending bit of an external interrupt. + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer + * to the appropriate CMSIS device file (stm32wlxxxx.h)) + * @retval None + */ +void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Clear pending interrupt */ + NVIC_ClearPendingIRQ(IRQn); +} + +/** + * @brief Configure the SysTick clock source. + * @param CLKSource specifies the SysTick clock source. + * This parameter can be one of the following values: + * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source. + * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source. + * @retval None + */ +void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource) +{ + /* Check the parameters */ + assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource)); + if (CLKSource == SYSTICK_CLKSOURCE_HCLK) + { + SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK; + } + else + { + SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK; + } +} + +/** + * @brief Handle SYSTICK interrupt request. + * @retval None + */ +void HAL_SYSTICK_IRQHandler(void) +{ + HAL_SYSTICK_Callback(); +} + +/** + * @brief SYSTICK callback. + * @retval None + */ +__weak void HAL_SYSTICK_Callback(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SYSTICK_Callback could be implemented in the user file + */ +} + +#if (__MPU_PRESENT == 1U) + +/** + * @brief Enable the MPU. + * @param MPU_Control: Specifies the control mode of the MPU during hard fault, + * NMI, FAULTMASK and privileged access to the default memory + * This parameter can be one of the following values: + * @arg MPU_HFNMI_PRIVDEF_NONE + * @arg MPU_HARDFAULT_NMI + * @arg MPU_PRIVILEGED_DEFAULT + * @arg MPU_HFNMI_PRIVDEF + * @retval None + */ +void HAL_MPU_Enable(uint32_t MPU_Control) +{ + /* Enable the MPU */ + MPU->CTRL = (MPU_Control | MPU_CTRL_ENABLE_Msk); + + /* Ensure MPU setting take effects */ + __DSB(); + __ISB(); +} + + +/** + * @brief Disable the MPU. + * @retval None + */ +void HAL_MPU_Disable(void) +{ + /* Make sure outstanding transfers are done */ + __DMB(); + + /* Disable the MPU and clear the control register*/ + MPU->CTRL = 0; +} + +/** + * @brief Enable the MPU Region. + * @retval None + */ +void HAL_MPU_EnableRegion(uint32_t RegionNumber) +{ + /* Check the parameters */ + assert_param(IS_MPU_REGION_NUMBER(RegionNumber)); + + /* Set the Region number */ + MPU->RNR = RegionNumber; + + /* Enable the Region */ + SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); +} + +/** + * @brief Disable the MPU Region. + * @retval None + */ +void HAL_MPU_DisableRegion(uint32_t RegionNumber) +{ + /* Check the parameters */ + assert_param(IS_MPU_REGION_NUMBER(RegionNumber)); + + /* Set the Region number */ + MPU->RNR = RegionNumber; + + /* Disable the Region */ + CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); +} + +/** + * @brief Initialize and configure the Region and the memory to be protected. + * @param MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains + * the initialization and configuration information. + * @retval None + */ +void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init) +{ + /* Check the parameters */ + assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number)); + assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable)); + assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec)); + assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission)); +#if defined(CORE_CM0PLUS) +#else + assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField)); +#endif /* CORE_CM0PLUS */ + assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable)); + assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable)); + assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable)); + assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable)); + assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size)); + + /* Set the Region number */ + MPU->RNR = MPU_Init->Number; + + /* Disable the Region */ + CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); + + /* Apply configuration */ + MPU->RBAR = MPU_Init->BaseAddress; + MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | + ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) | +#if defined(CORE_CM0PLUS) +#else + ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) | +#endif /* CORE_CM0PLUS */ + ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) | + ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) | + ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) | + ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) | + ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) | + ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos); +} +#endif /* __MPU_PRESENT */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_CORTEX_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + diff --git a/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.c b/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.c new file mode 100644 index 0000000..91f1315 --- /dev/null +++ b/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.c @@ -0,0 +1,1321 @@ +/** + ****************************************************************************** + * @file stm32wlxx_hal_dma.c + * @author MCD Application Team + * @brief DMA HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Direct Memory Access (DMA) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral State and errors functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Enable and configure the peripheral to be connected to the DMA Channel + (except for internal SRAM / FLASH memories: no initialization is + necessary). Please refer to the Reference manual for connection between peripherals + and DMA requests. + + (#) For a given Channel, program the required configuration through the following parameters: + Channel request, Transfer Direction, Source and Destination data formats, + Circular or Normal mode, Channel Priority level, Source and Destination Increment mode + using HAL_DMA_Init() function. + + Prior to HAL_DMA_Init the peripheral clock shall be enabled for both DMA & DMAMUX + thanks to: + (##) DMA1 or DMA2: __HAL_RCC_DMA1_CLK_ENABLE() or __HAL_RCC_DMA2_CLK_ENABLE(); + (##) DMAMUX1: __HAL_RCC_DMAMUX1_CLK_ENABLE(); + + (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error + detection. + + (#) Use HAL_DMA_Abort() function to abort the current transfer + + -@- In Memory-to-Memory transfer mode, Circular mode is not allowed. + + *** Polling mode IO operation *** + ================================= + [..] + (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source + address and destination address and the Length of data to be transferred + (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this + case a fixed Timeout can be configured by User depending from his application. + + *** Interrupt mode IO operation *** + =================================== + [..] + (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority() + (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ() + (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of + Source address and destination address and the Length of data to be transferred. + In this case the DMA interrupt is configured + (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine + (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can + add his own function to register callbacks with HAL_DMA_RegisterCallback(). + + *** DMA HAL driver macros list *** + ============================================= + [..] + Below the list of macros in DMA HAL driver. + + (+) __HAL_DMA_ENABLE: Enable the specified DMA Channel. + (+) __HAL_DMA_DISABLE: Disable the specified DMA Channel. + (+) __HAL_DMA_GET_FLAG: Get the DMA Channel pending flags. + (+) __HAL_DMA_CLEAR_FLAG: Clear the DMA Channel pending flags. + (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Channel interrupts. + (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Channel interrupts. + (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Channel interrupt is enabled or not. + + [..] + (@) You can refer to the DMA HAL driver header file for more useful macros + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wlxx_hal.h" + +/** @addtogroup STM32WLxx_HAL_Driver + * @{ + */ + +/** @defgroup DMA DMA + * @brief DMA HAL module driver + * @{ + */ + +#ifdef HAL_DMA_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ + +/** @defgroup DMA_Private_Functions DMA Private Functions + * @{ + */ +static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); +static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma); +static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma); + +/** + * @} + */ + +/* Exported functions ---------------------------------------------------------*/ + +/** @defgroup DMA_Exported_Functions DMA Exported Functions + * @{ + */ + +/** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and de-initialization functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] + This section provides functions allowing to initialize the DMA Channel source + and destination addresses, incrementation and data sizes, transfer direction, + circular/normal mode selection, memory-to-memory mode selection and Channel priority value. + [..] + The HAL_DMA_Init() function follows the DMA configuration procedures as described in + reference manual. + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the DMA according to the specified + * parameters in the DMA_InitTypeDef and initialize the associated handle. + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) +{ + /* Check the DMA handle allocation */ + if (hdma == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); + assert_param(IS_DMA_DIRECTION(hdma->Init.Direction)); + assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc)); + assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc)); + assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment)); + assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment)); + assert_param(IS_DMA_MODE(hdma->Init.Mode)); + assert_param(IS_DMA_PRIORITY(hdma->Init.Priority)); + + assert_param(IS_DMA_ALL_REQUEST(hdma->Init.Request)); + + /* Compute the channel index */ + if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1)) + { + /* DMA1 */ + hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U; + hdma->DmaBaseAddress = DMA1; + } + else + { + /* DMA2 */ + hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2U; + hdma->DmaBaseAddress = DMA2; + } + + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_BUSY; + + /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR and MEM2MEM bits */ + CLEAR_BIT(hdma->Instance->CCR, (DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | \ + DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | \ + DMA_CCR_DIR | DMA_CCR_MEM2MEM)); + + /* Set the DMA Channel configuration */ + SET_BIT(hdma->Instance->CCR, (hdma->Init.Direction | \ + hdma->Init.PeriphInc | hdma->Init.MemInc | \ + hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | \ + hdma->Init.Mode | hdma->Init.Priority)); + + /* Initialize parameters for DMAMUX channel : + DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask + */ + DMA_CalcDMAMUXChannelBaseAndMask(hdma); + + if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY) + { + /* if memory to memory force the request to 0*/ + hdma->Init.Request = DMA_REQUEST_MEM2MEM; + } + + /* Set peripheral request to DMAMUX channel */ + hdma->DMAmuxChannel->CCR = (hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID); + + /* Clear the DMAMUX synchro overrun flag */ + hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; + + if (((hdma->Init.Request > 0UL) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR3))) + { + /* Initialize parameters for DMAMUX request generator : + DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask + */ + DMA_CalcDMAMUXRequestGenBaseAndMask(hdma); + + /* Reset the DMAMUX request generator register*/ + hdma->DMAmuxRequestGen->RGCR = 0U; + + /* Clear the DMAMUX request generator overrun flag */ + hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; + } + else + { + hdma->DMAmuxRequestGen = NULL; + hdma->DMAmuxRequestGenStatus = NULL; + hdma->DMAmuxRequestGenStatusMask = 0U; + } + + /* Initialize the error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Initialize the DMA state*/ + hdma->State = HAL_DMA_STATE_READY; + + /* Release Lock */ + __HAL_UNLOCK(hdma); + + return HAL_OK; +} + +/** + * @brief DeInitialize the DMA peripheral. + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) +{ + /* Check the DMA handle allocation */ + if (NULL == hdma) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); + + /* Disable the selected DMA Channelx */ + __HAL_DMA_DISABLE(hdma); + + /* Compute the channel index */ + if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1)) + { + /* DMA1 */ + hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U; + hdma->DmaBaseAddress = DMA1; + } + else + { + /* DMA2 */ + hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2U; + hdma->DmaBaseAddress = DMA2; + } + + /* Reset DMA Channel control register */ + hdma->Instance->CCR = 0U; + + /* Clear all flags */ + hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU)); + + /* Initialize parameters for DMAMUX channel : + DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask */ + + DMA_CalcDMAMUXChannelBaseAndMask(hdma); + + /* Reset the DMAMUX channel that corresponds to the DMA channel */ + hdma->DMAmuxChannel->CCR = 0U; + + /* Clear the DMAMUX synchro overrun flag */ + hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; + + /* Reset Request generator parameters if any */ + if (((hdma->Init.Request > 0UL) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR3))) + { + /* Initialize parameters for DMAMUX request generator : + DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask + */ + DMA_CalcDMAMUXRequestGenBaseAndMask(hdma); + + /* Reset the DMAMUX request generator register*/ + hdma->DMAmuxRequestGen->RGCR = 0U; + + /* Clear the DMAMUX request generator overrun flag */ + hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; + } + + hdma->DMAmuxRequestGen = NULL; + hdma->DMAmuxRequestGenStatus = NULL; + hdma->DMAmuxRequestGenStatusMask = 0U; + + /* Clean callbacks */ + hdma->XferCpltCallback = NULL; + hdma->XferHalfCpltCallback = NULL; + hdma->XferErrorCallback = NULL; + hdma->XferAbortCallback = NULL; + + /* Initialize the error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Initialize the DMA state */ + hdma->State = HAL_DMA_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hdma); + + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup DMA_Exported_Functions_Group2 Input and Output operation functions + * @brief Input and Output operation functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure the source, destination address and data length and Start DMA transfer + (+) Configure the source, destination address and data length and + Start DMA transfer with interrupt + (+) Abort DMA transfer + (+) Poll for transfer complete + (+) Handle DMA interrupt request + (+) Register and Unregister DMA callbacks + +@endverbatim + * @{ + */ + +/** + * @brief Start the DMA Transfer. + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @param SrcAddress The source memory Buffer address + * @param DstAddress The destination memory Buffer address + * @param DataLength The length of data to be transferred from source to destination + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_DMA_BUFFER_SIZE(DataLength)); + + /* Process locked */ + __HAL_LOCK(hdma); + + if (hdma->State == HAL_DMA_STATE_READY) + { + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_BUSY; + + /* Initialize the error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Disable the peripheral */ + __HAL_DMA_DISABLE(hdma); + + /* Configure the source, destination address and the data length & clear flags*/ + DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); + + /* Enable the Peripheral */ + __HAL_DMA_ENABLE(hdma); + } + else + { + /* Change the error code */ + hdma->ErrorCode = HAL_DMA_ERROR_BUSY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Start the DMA Transfer with interrupt enabled. + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @param SrcAddress The source memory Buffer address + * @param DstAddress The destination memory Buffer address + * @param DataLength The length of data to be transferred from source to destination + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, + uint32_t DataLength) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_DMA_BUFFER_SIZE(DataLength)); + + /* Process locked */ + __HAL_LOCK(hdma); + + if (hdma->State == HAL_DMA_STATE_READY) + { + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_BUSY; + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Disable the peripheral */ + __HAL_DMA_DISABLE(hdma); + + /* Configure the source, destination address and the data length & clear flags*/ + DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); + + /* Enable the transfer complete interrupt */ + /* Enable the transfer Error interrupt */ + if (NULL != hdma->XferHalfCpltCallback) + { + /* Enable the Half transfer complete interrupt as well */ + __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); + } + else + { + __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); + __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE)); + } + + /* Check if DMAMUX Synchronization is enabled*/ + if ((hdma->DMAmuxChannel->CCR & DMAMUX_CxCR_SE) != 0U) + { + /* Enable DMAMUX sync overrun IT*/ + hdma->DMAmuxChannel->CCR |= DMAMUX_CxCR_SOIE; + } + + if (hdma->DMAmuxRequestGen != NULL) + { + /* if using DMAMUX request generator, enable the DMAMUX request generator overrun IT*/ + /* enable the request gen overrun IT*/ + hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE; + } + + /* Enable the Peripheral */ + __HAL_DMA_ENABLE(hdma); + } + else + { + /* Change the error code */ + hdma->ErrorCode = HAL_DMA_ERROR_BUSY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Abort the DMA Transfer. + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) +{ + /* Check the DMA peripheral handle */ + if (NULL == hdma) + { + return HAL_ERROR; + } + + /* Check the DMA peripheral state */ + if (hdma->State != HAL_DMA_STATE_BUSY) + { + hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + else + { + /* Disable the channel */ + __HAL_DMA_DISABLE(hdma); + + /* Disable DMA IT */ + __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); + + /* disable the DMAMUX sync overrun IT*/ + hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; + + /* Clear all flags */ + hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU)); + + /* Clear the DMAMUX synchro overrun flag */ + hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; + + if (hdma->DMAmuxRequestGen != NULL) + { + /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/ + /* disable the request gen overrun IT*/ + hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE; + + /* Clear the DMAMUX request generator overrun flag */ + hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; + } + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + } + + return HAL_OK; +} + +/** + * @brief Aborts the DMA Transfer in Interrupt mode. + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (hdma->State != HAL_DMA_STATE_BUSY) + { + /* no transfer ongoing */ + hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + + status = HAL_ERROR; + } + else + { + /* Disable the channel */ + __HAL_DMA_DISABLE(hdma); + + /* Disable DMA IT */ + __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); + + /* disable the DMAMUX sync overrun IT*/ + hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; + + /* Clear all flags */ + hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU)); + + /* Clear the DMAMUX synchro overrun flag */ + hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; + + if (hdma->DMAmuxRequestGen != NULL) + { + /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/ + /* disable the request gen overrun IT*/ + hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE; + + /* Clear the DMAMUX request generator overrun flag */ + hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; + } + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + /* Call User Abort callback */ + if (hdma->XferAbortCallback != NULL) + { + hdma->XferAbortCallback(hdma); + } + } + return status; +} + +/** + * @brief Polling for transfer complete. + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @param CompleteLevel Specifies the DMA level complete. + * @param Timeout Timeout duration. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, + uint32_t Timeout) +{ + uint32_t temp; + uint32_t tickstart; + + if (hdma->State != HAL_DMA_STATE_BUSY) + { + /* no transfer ongoing */ + hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + __HAL_UNLOCK(hdma); + return HAL_ERROR; + } + + /* Polling mode not supported in circular mode */ + if ((hdma->Instance->CCR & DMA_CCR_CIRC) != 0U) + { + hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED; + return HAL_ERROR; + } + + /* Get the level transfer complete flag */ + if (HAL_DMA_FULL_TRANSFER == CompleteLevel) + { + /* Transfer Complete flag */ + temp = DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1CU); + } + else + { + /* Half Transfer Complete flag */ + temp = DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1CU); + } + + /* Get tick */ + tickstart = HAL_GetTick(); + + while ((hdma->DmaBaseAddress->ISR & temp) == 0U) + { + if ((hdma->DmaBaseAddress->ISR & (DMA_FLAG_TE1 << (hdma->ChannelIndex & 0x1CU))) != 0U) + { + /* When a DMA transfer error occurs */ + /* A hardware clear of its EN bits is performed */ + /* Clear all flags */ + hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU)); + + /* Update error code */ + hdma->ErrorCode = HAL_DMA_ERROR_TE; + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + /* Update error code */ + hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + } + } + + /*Check for DMAMUX Request generator (if used) overrun status */ + if (hdma->DMAmuxRequestGen != NULL) + { + /* if using DMAMUX request generator Check for DMAMUX request generator overrun */ + if ((hdma->DMAmuxRequestGenStatus->RGSR & hdma->DMAmuxRequestGenStatusMask) != 0U) + { + /* Disable the request gen overrun interrupt */ + hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE; + + /* Clear the DMAMUX request generator overrun flag */ + hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; + + /* Update error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_REQGEN; + } + } + + /* Check for DMAMUX Synchronization overrun */ + if ((hdma->DMAmuxChannelStatus->CSR & hdma->DMAmuxChannelStatusMask) != 0U) + { + /* Clear the DMAMUX synchro overrun flag */ + hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; + + /* Update error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_SYNC; + } + + if (HAL_DMA_FULL_TRANSFER == CompleteLevel) + { + /* Clear the transfer complete flag */ + hdma->DmaBaseAddress->IFCR = (DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1CU)); + + /* Process unlocked */ + __HAL_UNLOCK(hdma); + + /* The selected Channelx EN bit is cleared (DMA is disabled and + all transfers are complete) */ + hdma->State = HAL_DMA_STATE_READY; + } + else + { + /* Clear the half transfer complete flag */ + hdma->DmaBaseAddress->IFCR = (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1CU)); + } + + return HAL_OK; +} + +/** + * @brief Handle DMA interrupt request. + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @retval None + */ +void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) +{ + uint32_t flag_it = hdma->DmaBaseAddress->ISR; + uint32_t source_it = hdma->Instance->CCR; + + /* Half Transfer Complete Interrupt management ******************************/ + if (((flag_it & (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1CU))) != 0U) && ((source_it & DMA_IT_HT) != 0U)) + { + /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */ + if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) + { + /* Disable the half transfer interrupt */ + __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); + } + /* Clear the half transfer complete flag */ + hdma->DmaBaseAddress->IFCR = DMA_ISR_HTIF1 << (hdma->ChannelIndex & 0x1CU); + + /* DMA peripheral state is not updated in Half Transfer */ + /* but in Transfer Complete case */ + + if (hdma->XferHalfCpltCallback != NULL) + { + /* Half transfer callback */ + hdma->XferHalfCpltCallback(hdma); + } + } + + /* Transfer Complete Interrupt management ***********************************/ + else if ((0U != (flag_it & (DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1CU)))) && (0U != (source_it & DMA_IT_TC))) + { + if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) + { + /* Disable the transfer complete and error interrupt */ + __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC); + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + } + /* Clear the transfer complete flag */ + __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1CU))); + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + if (hdma->XferCpltCallback != NULL) + { + /* Transfer complete callback */ + hdma->XferCpltCallback(hdma); + } + } + + /* Transfer Error Interrupt management **************************************/ + else if (((flag_it & (DMA_FLAG_TE1 << (hdma->ChannelIndex & 0x1CU))) != 0U) && ((source_it & DMA_IT_TE) != 0U)) + { + /* When a DMA transfer error occurs */ + /* A hardware clear of its EN bits is performed */ + /* Disable ALL DMA IT */ + __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); + + /* Clear all flags */ + hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU)); + + /* Update error code */ + hdma->ErrorCode = HAL_DMA_ERROR_TE; + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + if (hdma->XferErrorCallback != NULL) + { + /* Transfer error callback */ + hdma->XferErrorCallback(hdma); + } + } + else + { + /* Nothing To Do */ + } + return; +} + +/** + * @brief Register callbacks + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @param CallbackID User Callback identifier + * a HAL_DMA_CallbackIDTypeDef ENUM as parameter. + * @param pCallback Pointer to private callback function which has pointer to + * a DMA_HandleTypeDef structure as parameter. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma)) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hdma); + + if (hdma->State == HAL_DMA_STATE_READY) + { + switch (CallbackID) + { + case HAL_DMA_XFER_CPLT_CB_ID: + hdma->XferCpltCallback = pCallback; + break; + + case HAL_DMA_XFER_HALFCPLT_CB_ID: + hdma->XferHalfCpltCallback = pCallback; + break; + + case HAL_DMA_XFER_ERROR_CB_ID: + hdma->XferErrorCallback = pCallback; + break; + + case HAL_DMA_XFER_ABORT_CB_ID: + hdma->XferAbortCallback = pCallback; + break; + + default: + status = HAL_ERROR; + break; + } + } + else + { + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hdma); + + return status; +} + +/** + * @brief UnRegister callbacks + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @param CallbackID User Callback identifier + * a HAL_DMA_CallbackIDTypeDef ENUM as parameter. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hdma); + + if (hdma->State == HAL_DMA_STATE_READY) + { + switch (CallbackID) + { + case HAL_DMA_XFER_CPLT_CB_ID: + hdma->XferCpltCallback = NULL; + break; + + case HAL_DMA_XFER_HALFCPLT_CB_ID: + hdma->XferHalfCpltCallback = NULL; + break; + + case HAL_DMA_XFER_ERROR_CB_ID: + hdma->XferErrorCallback = NULL; + break; + + case HAL_DMA_XFER_ABORT_CB_ID: + hdma->XferAbortCallback = NULL; + break; + + case HAL_DMA_XFER_ALL_CB_ID: + hdma->XferCpltCallback = NULL; + hdma->XferHalfCpltCallback = NULL; + hdma->XferErrorCallback = NULL; + hdma->XferAbortCallback = NULL; + break; + + default: + status = HAL_ERROR; + break; + } + } + else + { + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hdma); + + return status; +} + +/** + * @} + */ + + +/** @defgroup DMA_Exported_Functions_Group3 Peripheral State and Errors functions + * @brief Peripheral State and Errors functions + * +@verbatim + =============================================================================== + ##### Peripheral State and Errors functions ##### + =============================================================================== + [..] + This subsection provides functions allowing to + (+) Check the DMA state + (+) Get error code + +@endverbatim + * @{ + */ + +/** + * @brief Return the DMA handle state. + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @retval HAL state + */ +HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma) +{ + /* Return DMA handle state */ + return hdma->State; +} + +/** + * @brief Return the DMA error code. + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @retval DMA Error Code + */ +uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma) +{ + /* Return the DMA error code */ + return hdma->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +#if defined(DMA_CCR_SECM) && defined(DMA_CCR_PRIV) +/** @defgroup DMA_Exported_Functions_Group4 Attributes management functions + * @brief Attributes management functions + * +@verbatim + =============================================================================== + ##### Attributes management functions ##### + =============================================================================== + [..] + This subsection provides functions allowing to + (+) Configure the DMA channel(s) privilege and non-privilege attributes + (+) Configure the DMA channel(s) secure and non-secure attributes from + secure world when the system implements the security (ESE=1) + (+) Get the DMA channel(s) attributes + +@endverbatim + * @{ + */ + +/** + * @brief Configure the DMA channel attribute(s). + * @note Available attributes are security and privilege protection. + * Each field can be set independently. Not allowed configurations + * are not taken into account & HAL_ERROR returned. + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @param ChannelAttributes specifies the DMA channel secure/privilege attributes. + * This parameter can be a one or a combination of @ref DMA_Channel_Attributes + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_DMA_ConfigChannelAttributes(DMA_HandleTypeDef *hdma, uint32_t ChannelAttributes) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t ccr; + +#if defined (CORE_CM0PLUS) + uint32_t ccr_SECM; +#endif /* CORE_CM0PLUS */ + + /* Check the DMA peripheral handle */ + if (hdma == NULL) + { + status = HAL_ERROR; + return status; + } + + /* Check the parameters */ + assert_param(IS_DMA_ATTRIBUTES(ChannelAttributes)); + + /* Read CCR register */ + ccr = READ_REG(hdma->Instance->CCR); + + /* Apply any requested privilege/non-privilege attributes */ + if ((ChannelAttributes & DMA_CHANNEL_ATTR_PRIV_MASK) != 0U) + { + if ((ChannelAttributes & DMA_CCR_PRIV) != 0U) + { + SET_BIT(ccr, DMA_CCR_PRIV); + } + else + { + CLEAR_BIT(ccr, DMA_CCR_PRIV); + } + } + +#if defined (CORE_CM0PLUS) + /* Channel */ + /* Check what is the current SECM status */ + if ((hdma->Instance->CCR & DMA_CCR_SECM) == DMA_CCR_SECM) + { + /* Channel is currently secure */ + ccr_SECM = DMA_CCR_SECM; + } + else + { + /* Channel is currently non-secure */ + ccr_SECM = 0U; + } + + if ((ChannelAttributes & DMA_CHANNEL_ATTR_SEC_MASK) != 0U) + { + if ((ChannelAttributes & DMA_CCR_SECM) != 0U) + { + SET_BIT(ccr, DMA_CCR_SECM); + /* Channel changed to secure */ + ccr_SECM = DMA_CCR_SECM; + } + else + { + CLEAR_BIT(ccr, DMA_CCR_SECM); + /* Channel changed to non-secure */ + ccr_SECM = 0U; + } + } + + /* Channel source */ + if ((ChannelAttributes & DMA_CHANNEL_ATTR_SEC_SRC_MASK) != 0U) + { + /* Configure Source security attributes */ + if ((ChannelAttributes & DMA_CCR_SSEC) != 0x0U) + { + /* SSEC can only be set if channel is secure */ + /* Otherwise configuration is not taken into account */ + if (ccr_SECM == 0U) + { + status = HAL_ERROR; + } + else + { + SET_BIT(ccr, DMA_CCR_SSEC); + } + } + else + { + CLEAR_BIT(ccr, DMA_CCR_SSEC); + } + } + + /* Channel destination */ + if ((ChannelAttributes & DMA_CHANNEL_ATTR_SEC_DEST_MASK) != 0U) + { + /* Configure Destination security attributes */ + if ((ChannelAttributes & DMA_CCR_DSEC) != 0U) + { + if (ccr_SECM == 0U) + { + /* DSEC can only be set if channel is secure */ + /* Destination channel is non secure */ + status = HAL_ERROR; + } + else + { + SET_BIT(ccr, DMA_CCR_DSEC); + } + } + else + { + CLEAR_BIT(ccr, DMA_CCR_DSEC); + } + } + +#endif /* CORE_CM0PLUS */ + + /* Update CCR Register: PRIV, SECM, SCEC, DSEC bits */ + WRITE_REG(hdma->Instance->CCR, ccr); + + return status; +} + +/** + * @brief Get the attribute of a DMA channel. + * @note Secure and non-secure attributes are only available from secure state + * when the system implements the security (ESE=1) + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @param ChannelAttributes pointer to return the attributes. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_DMA_GetConfigChannelAttributes(DMA_HandleTypeDef *hdma, uint32_t *ChannelAttributes) +{ + uint32_t read_attributes; + uint32_t attributes; + + /* Check the DMA peripheral handle and pointer to returned value */ + if ((hdma == NULL) || (ChannelAttributes == NULL)) + { + return HAL_ERROR; + } + +#if defined (CORE_CM0PLUS) + /* Get secure or non-secure attributes */ + read_attributes = READ_BIT(hdma->Instance->CCR, DMA_CCR_PRIV | DMA_CCR_SECM | DMA_CCR_SSEC | DMA_CCR_DSEC); + + /* Get privilege attributes */ + attributes = ((read_attributes & DMA_CCR_PRIV) == 0U) ? DMA_CHANNEL_NPRIV : DMA_CHANNEL_PRIV; + + /* Get security attributes */ + attributes |= ((read_attributes & DMA_CCR_SECM) == 0U) ? DMA_CHANNEL_NSEC : DMA_CHANNEL_SEC; + + /* Get security attributes of the source */ + attributes |= ((read_attributes & DMA_CCR_SSEC) == 0U) ? DMA_CHANNEL_SRC_NSEC : DMA_CHANNEL_SRC_SEC; + + /* Get security attributes of the destination */ + attributes |= ((read_attributes & DMA_CCR_DSEC) == 0U) ? DMA_CHANNEL_DEST_NSEC : DMA_CHANNEL_DEST_SEC; + +#else + + /* Get secure or non-secure attributes */ + read_attributes = READ_BIT(hdma->Instance->CCR, DMA_CCR_PRIV | DMA_CCR_SECM); + + /* Get privilege attributes */ + attributes = ((read_attributes & DMA_CCR_PRIV) == 0U) ? DMA_CHANNEL_NPRIV : DMA_CHANNEL_PRIV; + + /* Get security attributes */ + attributes |= ((read_attributes & DMA_CCR_SECM) == 0U) ? DMA_CHANNEL_NSEC : DMA_CHANNEL_SEC; +#endif /* CORE_CM0PLUS */ + + /* return value */ + *ChannelAttributes = attributes; + + return HAL_OK; +} +#endif /* DMA_SECURE_SWITCH */ +/** @addtogroup DMA_Private_Functions + * @{ + */ + +/** + * @brief Sets the DMA Transfer parameter. + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @param SrcAddress The source memory Buffer address + * @param DstAddress The destination memory Buffer address + * @param DataLength The length of data to be transferred from source to destination + * @retval HAL status + */ +static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) +{ + /* Clear the DMAMUX synchro overrun flag */ + hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; + + if (hdma->DMAmuxRequestGen != NULL) + { + /* Clear the DMAMUX request generator overrun flag */ + hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; + } + + /* Clear all flags */ + hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU)); + + /* Configure DMA Channel data length */ + hdma->Instance->CNDTR = DataLength; + + /* Memory to Peripheral */ + if ((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) + { + /* Configure DMA Channel destination address */ + hdma->Instance->CPAR = DstAddress; + + /* Configure DMA Channel source address */ + hdma->Instance->CMAR = SrcAddress; + } + /* Peripheral to Memory */ + else + { + /* Configure DMA Channel source address */ + hdma->Instance->CPAR = SrcAddress; + + /* Configure DMA Channel destination address */ + hdma->Instance->CMAR = DstAddress; + } +} + +/** + * @brief Updates the DMA handle with the DMAMUX channel and status mask depending on channel number + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @retval None + */ +static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma) +{ + uint32_t channel_number; + + /* check if instance is not outside the DMA channel range */ + if ((uint32_t)hdma->Instance < (uint32_t)DMA2_Channel1) + { + /* DMA1 */ + /* Associate a DMA Channel to a DMAMUX channel */ + hdma->DMAmuxChannel = (DMAMUX1_Channel0 + (hdma->ChannelIndex >> 2U)); + + /* Prepare channel_number used for DMAmuxChannelStatusMask computation */ + channel_number = (((uint32_t)hdma->Instance & 0xFFU) - 8U) / 20U; + } + else + { + /* DMA2 */ + /* Associate a DMA Channel to a DMAMUX channel */ + hdma->DMAmuxChannel = (DMAMUX1_Channel7 + (hdma->ChannelIndex >> 2U)); + + /* Prepare channel_number used for DMAmuxChannelStatusMask computation */ + channel_number = (((((uint32_t)hdma->Instance & 0xFFU) - 8U) / 20U) + 7U); + } + + /* Initialize the field DMAmuxChannelStatus to DMAMUX1_ChannelStatus base */ + hdma->DMAmuxChannelStatus = DMAMUX1_ChannelStatus; + + /* Initialize the field DMAmuxChannelStatusMask with the corresponding index of the DMAMUX channel selected for the current ChannelIndex */ + hdma->DMAmuxChannelStatusMask = 1UL << (channel_number & 0x1FU); +} + +/** + * @brief Updates the DMA handle with the DMAMUX request generator params + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @retval None + */ + +static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma) +{ + uint32_t request = hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID; + + /* DMA Channels are connected to DMAMUX1 request generator blocks*/ + hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_RequestGenerator0) + ((request - 1U) * 4U))); + + hdma->DMAmuxRequestGenStatus = DMAMUX1_RequestGenStatus; + + /* here "Request" is either DMA_REQUEST_GENERATOR0 to DMA_REQUEST_GENERATOR3, i.e. <= 4*/ + hdma->DMAmuxRequestGenStatusMask = 1UL << ((request - 1U) & 0x3U); +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_DMA_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + diff --git a/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma_ex.c b/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma_ex.c new file mode 100644 index 0000000..d7abb4a --- /dev/null +++ b/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma_ex.c @@ -0,0 +1,320 @@ +/** + ****************************************************************************** + * @file stm32wlxx_hal_dma_ex.c + * @author MCD Application Team + * @brief DMA Extension HAL module driver + * This file provides firmware functions to manage the following + * functionalities of the DMA Extension peripheral: + * + Extended features functions + * + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The DMA Extension HAL driver can be used as follows: + (+) Configure the DMAMUX Synchronization Block using HAL_DMAEx_ConfigMuxSync function. + (+) Configure the DMAMUX Request Generator Block using HAL_DMAEx_ConfigMuxRequestGenerator function. + Functions HAL_DMAEx_EnableMuxRequestGenerator and HAL_DMAEx_DisableMuxRequestGenerator can then be used + to respectively enable/disable the request generator. + + (+) To handle the DMAMUX Interrupts, the function HAL_DMAEx_MUX_IRQHandler should be called from + the DMAMUX IRQ handler i.e DMAMUX1_OVR_IRQHandler. + As only one interrupt line is available for all DMAMUX channels and request generators , HAL_DMAEx_MUX_IRQHandler should be + called with, as parameter, the appropriate DMA handle as many as used DMAs in the user project + (exception done if a given DMA is not using the DMAMUX SYNC block neither a request generator) + + @endverbatim + ****************************************************************************** + * @attention + * + * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wlxx_hal.h" + +/** @addtogroup STM32WLxx_HAL_Driver + * @{ + */ + +/** @defgroup DMAEx DMAEx + * @brief DMA Extended HAL module driver + * @{ + */ + +#ifdef HAL_DMA_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private Constants ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + + +/** @defgroup DMAEx_Exported_Functions DMAEx Exported Functions + * @{ + */ + +/** @defgroup DMAEx_Exported_Functions_Group1 DMAEx Extended features functions + * @brief Extended features functions + * +@verbatim + =============================================================================== + ##### Extended features functions ##### + =============================================================================== + [..] This section provides functions allowing to: + + (+) Configure the DMAMUX Synchronization Block using HAL_DMAEx_ConfigMuxSync function. + (+) Configure the DMAMUX Request Generator Block using HAL_DMAEx_ConfigMuxRequestGenerator function. + Functions HAL_DMAEx_EnableMuxRequestGenerator and HAL_DMAEx_DisableMuxRequestGenerator can then be used + to respectively enable/disable the request generator. + (+) Handle DMAMUX interrupts using HAL_DMAEx_MUX_IRQHandler : should be called from + the DMAMUX IRQ handler + +@endverbatim + * @{ + */ + +/** + * @brief Configure the DMAMUX synchronization parameters for a given DMA channel (instance). + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA channel. + * @param pSyncConfig Pointer to HAL_DMA_MuxSyncConfigTypeDef contains the DMAMUX synchronization parameters + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(DMA_HandleTypeDef *hdma, HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); + + assert_param(IS_DMAMUX_SYNC_SIGNAL_ID(pSyncConfig->SyncSignalID)); + + assert_param(IS_DMAMUX_SYNC_POLARITY(pSyncConfig-> SyncPolarity)); + assert_param(IS_DMAMUX_SYNC_STATE(pSyncConfig->SyncEnable)); + assert_param(IS_DMAMUX_SYNC_EVENT(pSyncConfig->EventEnable)); + assert_param(IS_DMAMUX_SYNC_REQUEST_NUMBER(pSyncConfig->RequestNumber)); + + /*Check if the DMA state is ready */ + if (hdma->State == HAL_DMA_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hdma); + + /* Set the new synchronization parameters (and keep the request ID filled during the Init)*/ + MODIFY_REG(hdma->DMAmuxChannel->CCR, \ + (~DMAMUX_CxCR_DMAREQ_ID), \ + (pSyncConfig->SyncSignalID | ((pSyncConfig->RequestNumber - 1U) << DMAMUX_CxCR_NBREQ_Pos) | \ + pSyncConfig->SyncPolarity | ((uint32_t)pSyncConfig->SyncEnable << DMAMUX_CxCR_SE_Pos) | \ + ((uint32_t)pSyncConfig->EventEnable << DMAMUX_CxCR_EGE_Pos))); + + /* Process UnLocked */ + __HAL_UNLOCK(hdma); + + return HAL_OK; + } + else + { + /* Set the error code to busy */ + hdma->ErrorCode = HAL_DMA_ERROR_BUSY; + + /* Return error status */ + return HAL_ERROR; + } +} + +/** + * @brief Configure the DMAMUX request generator block used by the given DMA channel (instance). + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA channel. + * @param pRequestGeneratorConfig Pointer to HAL_DMA_MuxRequestGeneratorConfigTypeDef + * contains the request generator parameters. + * + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator(DMA_HandleTypeDef *hdma, + HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig) +{ + HAL_StatusTypeDef status; + HAL_DMA_StateTypeDef temp_state = hdma->State; + + /* Check the parameters */ + assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); + + assert_param(IS_DMAMUX_REQUEST_GEN_SIGNAL_ID(pRequestGeneratorConfig->SignalID)); + + assert_param(IS_DMAMUX_REQUEST_GEN_POLARITY(pRequestGeneratorConfig->Polarity)); + assert_param(IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER(pRequestGeneratorConfig->RequestNumber)); + + /* check if the DMA state is ready + and DMA is using a DMAMUX request generator block + */ + if (hdma->DMAmuxRequestGen == NULL) + { + /* Set the error code to busy */ + hdma->ErrorCode = HAL_DMA_ERROR_PARAM; + + /* error status */ + status = HAL_ERROR; + } + else if (((hdma->DMAmuxRequestGen->RGCR & DMAMUX_RGxCR_GE) == 0U) && (temp_state == HAL_DMA_STATE_READY)) + { + /* RequestGenerator must be disable prior to the configuration i.e GE bit is 0 */ + + /* Process Locked */ + __HAL_LOCK(hdma); + + /* Set the request generator new parameters*/ + hdma->DMAmuxRequestGen->RGCR = pRequestGeneratorConfig->SignalID | \ + ((pRequestGeneratorConfig->RequestNumber - 1U) << DMAMUX_RGxCR_GNBREQ_Pos) | \ + pRequestGeneratorConfig->Polarity; + /* Process UnLocked */ + __HAL_UNLOCK(hdma); + + return HAL_OK; + } + else + { + /* Set the error code to busy */ + hdma->ErrorCode = HAL_DMA_ERROR_BUSY; + + /* error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Enable the DMAMUX request generator block used by the given DMA channel (instance). + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA channel. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator(DMA_HandleTypeDef *hdma) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); + + /* check if the DMA state is ready + and DMA is using a DMAMUX request generator block + */ + if ((hdma->State != HAL_DMA_STATE_RESET) && (hdma->DMAmuxRequestGen != 0)) + { + + /* Enable the request generator*/ + hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_GE; + + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Disable the DMAMUX request generator block used by the given DMA channel (instance). + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA channel. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator(DMA_HandleTypeDef *hdma) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); + + /* check if the DMA state is ready + and DMA is using a DMAMUX request generator block + */ + if ((hdma->State != HAL_DMA_STATE_RESET) && (hdma->DMAmuxRequestGen != 0)) + { + + /* Disable the request generator*/ + hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_GE; + + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Handles DMAMUX interrupt request. + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA channel. + * @retval None + */ +void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma) +{ + /* Check for DMAMUX Synchronization overrun */ + if ((hdma->DMAmuxChannelStatus->CSR & hdma->DMAmuxChannelStatusMask) != 0U) + { + /* Disable the synchro overrun interrupt */ + hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; + + /* Clear the DMAMUX synchro overrun flag */ + hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; + + /* Update error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_SYNC; + + if (hdma->XferErrorCallback != NULL) + { + /* Transfer error callback */ + hdma->XferErrorCallback(hdma); + } + } + + if (hdma->DMAmuxRequestGen != 0) + { + /* if using a DMAMUX request generator block Check for DMAMUX request generator overrun */ + if ((hdma->DMAmuxRequestGenStatus->RGSR & hdma->DMAmuxRequestGenStatusMask) != 0U) + { + /* Disable the request gen overrun interrupt */ + hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE; + + /* Clear the DMAMUX request generator overrun flag */ + hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; + + /* Update error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_REQGEN; + + if (hdma->XferErrorCallback != NULL) + { + /* Transfer error callback */ + hdma->XferErrorCallback(hdma); + } + } + } +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_DMA_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_exti.c b/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_exti.c new file mode 100644 index 0000000..6a636fe --- /dev/null +++ b/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_exti.c @@ -0,0 +1,649 @@ +/** + ****************************************************************************** + * @file stm32wlxx_hal_exti.c + * @author MCD Application Team + * @brief EXTI HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the General Purpose Input/Output (EXTI) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + ****************************************************************************** + * @attention + * + * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### EXTI Peripheral features ##### + ============================================================================== + [..] + (+) Each Exti line can be configured within this driver. + + (+) Exti line can be configured in 3 different modes + (++) Interrupt + (++) Event + (++) Both of them + + (+) Configurable Exti lines can be configured with 3 different triggers + (++) Rising + (++) Falling + (++) Both of them + + (+) When set in interrupt mode, configurable Exti lines have two diffenrents + interrupt pending registers which allow to distinguish which transition + occurs: + (++) Rising edge pending interrupt + (++) Falling + + (+) Exti lines 0 to 15 are linked to gpio pin number 0 to 15. Gpio port can + be selected through multiplexer. + + ##### How to use this driver ##### + ============================================================================== + [..] + + (#) Configure the EXTI line using HAL_EXTI_SetConfigLine(). + (++) Choose the interrupt line number by setting "Line" member from + EXTI_ConfigTypeDef structure. + (++) Configure the interrupt and/or event mode using "Mode" member from + EXTI_ConfigTypeDef structure. + (++) For configurable lines, configure rising and/or falling trigger + "Trigger" member from EXTI_ConfigTypeDef structure. + (++) For Exti lines linked to gpio, choose gpio port using "GPIOSel" + member from GPIO_InitTypeDef structure. + + (#) Get current Exti configuration of a dedicated line using + HAL_EXTI_GetConfigLine(). + (++) Provide exiting handle as parameter. + (++) Provide pointer on EXTI_ConfigTypeDef structure as second parameter. + + (#) Clear Exti configuration of a dedicated line using HAL_EXTI_GetConfigLine(). + (++) Provide exiting handle as parameter. + + (#) Register callback to treat Exti interrupts using HAL_EXTI_RegisterCallback(). + (++) Provide exiting handle as first parameter. + (++) Provide which callback will be registered using one value from + EXTI_CallbackIDTypeDef. + (++) Provide callback function pointer. + + (#) Get interrupt pending bit using HAL_EXTI_GetPending(). + + (#) Clear interrupt pending bit using HAL_EXTI_GetPending(). + + (#) Generate software interrupt using HAL_EXTI_GenerateSWI(). + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wlxx_hal.h" + +/** @addtogroup STM32WLxx_HAL_Driver + * @{ + */ + +/** @addtogroup EXTI + * @{ + */ +/** MISRA C:2012 deviation rule has been granted for following rule: + * Rule-18.1_b - Medium: Array `EXTICR' 1st subscript interval [0,7] may be out + * of bounds [0,3] in following API : + * HAL_EXTI_SetConfigLine + * HAL_EXTI_GetConfigLine + * HAL_EXTI_ClearConfigLine + */ + +#ifdef HAL_EXTI_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private defines ------------------------------------------------------------*/ +/** @defgroup EXTI_Private_Constants EXTI Private Constants + * @{ + */ +#define EXTI_MODE_OFFSET 0x04u /* 0x10: offset between CPU IMR/EMR registers */ +#define EXTI_CONFIG_OFFSET 0x08u /* 0x20: offset between CPU Rising/Falling configuration registers */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup EXTI_Exported_Functions + * @{ + */ + +/** @addtogroup EXTI_Exported_Functions_Group1 + * @brief Configuration functions + * +@verbatim + =============================================================================== + ##### Configuration functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Set configuration of a dedicated Exti line. + * @param hexti Exti handle. + * @param pExtiConfig Pointer on EXTI configuration to be set. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig) +{ + __IO uint32_t *regaddr; + uint32_t regval; + uint32_t linepos; + uint32_t maskline; + uint32_t offset; + + /* Check null pointer */ + if ((hexti == NULL) || (pExtiConfig == NULL)) + { + return HAL_ERROR; + } + + /* Check parameters */ + assert_param(IS_EXTI_LINE(pExtiConfig->Line)); + assert_param(IS_EXTI_MODE(pExtiConfig->Mode)); + + /* Assign line number to handle */ + hexti->Line = pExtiConfig->Line; + + /* compute line register offset and line mask */ + offset = ((pExtiConfig->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + linepos = (pExtiConfig->Line & EXTI_PIN_MASK); + maskline = (1uL << linepos); + + /* Configure triggers for configurable lines */ + if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u) + { + assert_param(IS_EXTI_TRIGGER(pExtiConfig->Trigger)); + + /* Configure rising trigger */ + regaddr = (&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset)); + regval = *regaddr; + + /* Mask or set line */ + if ((pExtiConfig->Trigger & EXTI_TRIGGER_RISING) != 0x00u) + { + regval |= maskline; + } + else + { + regval &= ~maskline; + } + + /* Store rising trigger mode */ + *regaddr = regval; + + /* Configure falling trigger */ + regaddr = (&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset)); + regval = *regaddr; + + /* Mask or set line */ + if ((pExtiConfig->Trigger & EXTI_TRIGGER_FALLING) != 0x00u) + { + regval |= maskline; + } + else + { + regval &= ~maskline; + } + + /* Store falling trigger mode */ + *regaddr = regval; + + /* Configure gpio port selection in case of gpio exti line */ + if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO) + { + assert_param(IS_EXTI_GPIO_PORT(pExtiConfig->GPIOSel)); + assert_param(IS_EXTI_GPIO_PIN(linepos)); + + regval = SYSCFG->EXTICR[linepos >> 2u]; + regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); + regval |= (pExtiConfig->GPIOSel << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); + SYSCFG->EXTICR[linepos >> 2u] = regval; + } + } + + /* Configure interrupt mode : read current mode */ +#if defined(DUAL_CORE) && defined(CORE_CM0PLUS) + regaddr = (&EXTI->C2IMR1 + (EXTI_MODE_OFFSET * offset)); +#else + regaddr = (&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset)); +#endif /* DUAL_CORE && CORE_CM0PLUS */ + regval = *regaddr; + + /* Mask or set line */ + if ((pExtiConfig->Mode & EXTI_MODE_INTERRUPT) != 0x00u) + { + regval |= maskline; + } + else + { + regval &= ~maskline; + } + + /* Store interrupt mode */ + *regaddr = regval; + + /* Configure event mode : read current mode */ +#if defined(DUAL_CORE) && defined(CORE_CM0PLUS) + regaddr = (&EXTI->C2EMR1 + (EXTI_MODE_OFFSET * offset)); +#else + regaddr = (&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset)); +#endif /* DUAL_CORE && CORE_CM0PLUS */ + regval = *regaddr; + + /* Mask or set line */ + if ((pExtiConfig->Mode & EXTI_MODE_EVENT) != 0x00u) + { + /* The event mode cannot be configured if the line does not support it */ + assert_param(IS_EXTI_EVENT_PRESENT(pExtiConfig->Line)); + regval |= maskline; + } + else + { + regval &= ~maskline; + } + + /* Store event mode */ + *regaddr = regval; + + return HAL_OK; +} + + +/** + * @brief Get configuration of a dedicated Exti line. + * @param hexti Exti handle. + * @param pExtiConfig Pointer on structure to store Exti configuration. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig) +{ + const __IO uint32_t *regaddr; + uint32_t regval; + uint32_t linepos; + uint32_t maskline; + uint32_t offset; + + /* Check null pointer */ + if ((hexti == NULL) || (pExtiConfig == NULL)) + { + return HAL_ERROR; + } + + /* Check the parameter */ + assert_param(IS_EXTI_LINE(hexti->Line)); + + /* Store handle line number to configuration structure */ + pExtiConfig->Line = hexti->Line; + + /* compute line register offset and line mask */ + offset = ((pExtiConfig->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + linepos = (pExtiConfig->Line & EXTI_PIN_MASK); + maskline = (1uL << linepos); + + /* 1] Get core mode : interrupt */ +#if defined(DUAL_CORE) && defined(CORE_CM0PLUS) + regaddr = (&EXTI->C2IMR1 + (EXTI_MODE_OFFSET * offset)); +#else + regaddr = (&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset)); +#endif /* DUAL_CORE && CORE_CM0PLUS */ + regval = *regaddr; + + /* Check if selected line is enable */ + if ((regval & maskline) != 0x00u) + { + pExtiConfig->Mode = EXTI_MODE_INTERRUPT; + } + else + { + pExtiConfig->Mode = EXTI_MODE_NONE; + } + + /* Get event mode */ +#if defined(DUAL_CORE) && defined(CORE_CM0PLUS) + regaddr = (&EXTI->C2EMR1 + (EXTI_MODE_OFFSET * offset)); +#else + regaddr = (&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset)); +#endif /* DUAL_CORE && CORE_CM0PLUS */ + regval = *regaddr; + + /* Check if selected line is enable */ + if ((regval & maskline) != 0x00u) + { + pExtiConfig->Mode |= EXTI_MODE_EVENT; + } + + /* Get default Trigger and GPIOSel configuration */ + pExtiConfig->Trigger = EXTI_TRIGGER_NONE; + pExtiConfig->GPIOSel = 0x00u; + + /* 2] Get trigger for configurable lines : rising */ + if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u) + { + regaddr = (&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset)); + regval = *regaddr; + + /* Check if configuration of selected line is enable */ + if ((regval & maskline) != 0x00u) + { + pExtiConfig->Trigger = EXTI_TRIGGER_RISING; + } + + /* Get falling configuration */ + regaddr = (&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset)); + regval = *regaddr; + + /* Check if configuration of selected line is enable */ + if ((regval & maskline) != 0x00u) + { + pExtiConfig->Trigger |= EXTI_TRIGGER_FALLING; + } + + /* Get Gpio port selection for gpio lines */ + if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO) + { + regval = SYSCFG->EXTICR[linepos >> 2u]; + pExtiConfig->GPIOSel = (regval >> (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))) & SYSCFG_EXTICR1_EXTI0; + } + } + + return HAL_OK; +} + + +/** + * @brief Clear whole configuration of a dedicated Exti line. + * @param hexti Exti handle. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(const EXTI_HandleTypeDef *hexti) +{ + __IO uint32_t *regaddr; + uint32_t regval; + uint32_t linepos; + uint32_t maskline; + uint32_t offset; + + /* Check null pointer */ + if (hexti == NULL) + { + return HAL_ERROR; + } + + /* Check the parameter */ + assert_param(IS_EXTI_LINE(hexti->Line)); + + /* compute line register offset and line mask */ + offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + linepos = (hexti->Line & EXTI_PIN_MASK); + maskline = (1uL << linepos); + + /* 1] Clear interrupt mode */ +#if defined(DUAL_CORE) && defined(CORE_CM0PLUS) + regaddr = (&EXTI->C2IMR1 + (EXTI_MODE_OFFSET * offset)); +#else + regaddr = (&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset)); +#endif /* DUAL_CORE && CORE_CM0PLUS */ + regval = (*regaddr & ~maskline); + *regaddr = regval; + + /* 2] Clear event mode */ +#if defined(DUAL_CORE) && defined(CORE_CM0PLUS) + regaddr = (&EXTI->C2EMR1 + (EXTI_MODE_OFFSET * offset)); +#else + regaddr = (&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset)); +#endif /* DUAL_CORE && CORE_CM0PLUS */ + regval = (*regaddr & ~maskline); + *regaddr = regval; + + /* 3] Clear triggers in case of configurable lines */ + if ((hexti->Line & EXTI_CONFIG) != 0x00u) + { + regaddr = (&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset)); + regval = (*regaddr & ~maskline); + *regaddr = regval; + + regaddr = (&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset)); + regval = (*regaddr & ~maskline); + *regaddr = regval; + + /* Get Gpio port selection for gpio lines */ + if ((hexti->Line & EXTI_GPIO) == EXTI_GPIO) + { + regval = SYSCFG->EXTICR[linepos >> 2u]; + regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); + SYSCFG->EXTICR[linepos >> 2u] = regval; + } + } + + return HAL_OK; +} + + +/** + * @brief Register callback for a dedicaated Exti line. + * @param hexti Exti handle. + * @param CallbackID User callback identifier. + * This parameter can be one of @arg @ref EXTI_CallbackIDTypeDef values. + * @param pPendingCbfn function pointer to be stored as callback. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void)) +{ + HAL_StatusTypeDef status = HAL_OK; + + switch (CallbackID) + { + case HAL_EXTI_COMMON_CB_ID: + hexti->PendingCallback = pPendingCbfn; + break; + + default: + status = HAL_ERROR; + break; + } + + return status; +} + + +/** + * @brief Store line number as handle private field. + * @param hexti Exti handle. + * @param ExtiLine Exti line number. + * This parameter can be from 0 to @ref EXTI_LINE_NB. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine) +{ + /* Check the parameters */ + assert_param(IS_EXTI_LINE(ExtiLine)); + + /* Check null pointer */ + if (hexti == NULL) + { + return HAL_ERROR; + } + else + { + /* Store line number as handle private field */ + hexti->Line = ExtiLine; + + return HAL_OK; + } +} + + +/** + * @} + */ + +/** @addtogroup EXTI_Exported_Functions_Group2 + * @brief EXTI IO functions. + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Handle EXTI interrupt request. + * @param hexti Exti handle. + * @retval none. + */ +void HAL_EXTI_IRQHandler(const EXTI_HandleTypeDef *hexti) +{ + __IO uint32_t *regaddr; + uint32_t regval; + uint32_t maskline; + uint32_t offset; + + /* Compute line register offset and line mask */ + offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + maskline = (1uL << (hexti->Line & EXTI_PIN_MASK)); + + /* Get pending bit */ + regaddr = (&EXTI->PR1 + (EXTI_CONFIG_OFFSET * offset)); + regval = (*regaddr & maskline); + + if (regval != 0x00u) + { + /* Clear pending bit */ + *regaddr = maskline; + + /* Call callback */ + if (hexti->PendingCallback != NULL) + { + hexti->PendingCallback(); + } + } +} + + +/** + * @brief Get interrupt pending bit of a dedicated line. + * @param hexti Exti handle. + * @param Edge Specify which pending edge as to be checked. + * This parameter can be one of the following values: + * @arg @ref EXTI_TRIGGER_RISING_FALLING + * This parameter is kept for compatibility with other series. + * @retval 1 if interrupt is pending else 0. + */ +uint32_t HAL_EXTI_GetPending(const EXTI_HandleTypeDef *hexti, uint32_t Edge) +{ + const __IO uint32_t *regaddr; + uint32_t regval; + uint32_t linepos; + uint32_t maskline; + uint32_t offset; + + /* Check parameters */ + assert_param(IS_EXTI_LINE(hexti->Line)); + assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); + assert_param(IS_EXTI_PENDING_EDGE(Edge)); + + /* compute line register offset and line mask */ + offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + linepos = (hexti->Line & EXTI_PIN_MASK); + maskline = (1uL << linepos); + + /* Get pending bit */ + regaddr = (&EXTI->PR1 + (EXTI_CONFIG_OFFSET * offset)); + + /* return 1 if bit is set else 0 */ + regval = ((*regaddr & maskline) >> linepos); + return regval; +} + + +/** + * @brief Clear interrupt pending bit of a dedicated line. + * @param hexti Exti handle. + * @param Edge Specify which pending edge as to be clear. + * This parameter can be one of the following values: + * @arg @ref EXTI_TRIGGER_RISING_FALLING + * This parameter is kept for compatibility with other series. + * @retval None. + */ +void HAL_EXTI_ClearPending(const EXTI_HandleTypeDef *hexti, uint32_t Edge) +{ + __IO uint32_t *regaddr; + uint32_t maskline; + uint32_t offset; + + /* Check parameters */ + assert_param(IS_EXTI_LINE(hexti->Line)); + assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); + assert_param(IS_EXTI_PENDING_EDGE(Edge)); + + /* compute line register offset and line mask */ + offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + maskline = (1uL << (hexti->Line & EXTI_PIN_MASK)); + + /* Get pending register address */ + regaddr = (&EXTI->PR1 + (EXTI_CONFIG_OFFSET * offset)); + + /* Clear Pending bit */ + *regaddr = maskline; +} + +/** + * @brief Generate a software interrupt for a dedicated line. + * @param hexti Exti handle. + * @retval None. + */ +void HAL_EXTI_GenerateSWI(const EXTI_HandleTypeDef *hexti) +{ + __IO uint32_t *regaddr; + uint32_t maskline; + uint32_t offset; + + /* Check parameters */ + assert_param(IS_EXTI_LINE(hexti->Line)); + assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); + + /* compute line register offset and line mask */ + offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + maskline = (1uL << (hexti->Line & EXTI_PIN_MASK)); + + regaddr = (&EXTI->SWIER1 + (EXTI_CONFIG_OFFSET * offset)); + *regaddr = maskline; +} + + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_EXTI_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ diff --git a/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash.c b/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash.c new file mode 100644 index 0000000..73a2914 --- /dev/null +++ b/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash.c @@ -0,0 +1,764 @@ +/** + ****************************************************************************** + * @file stm32wlxx_hal_flash.c + * @author MCD Application Team + * @brief FLASH HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the internal FLASH memory: + * + Program operations functions + * + Memory Control functions + * + Peripheral Errors functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### FLASH peripheral features ##### + ============================================================================== + + [..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses + to the Flash memory. It implements the erase and program Flash memory operations + and the read and write protection mechanisms. + + [..] The Flash memory interface accelerates code execution with a system of instruction + prefetch and cache lines. + + [..] The FLASH main features are: + (+) Flash memory read operations + (+) Flash memory program/erase operations + (+) Program and Erase suspension + (+) Read / write protections (2 areas per features) + (+) CPU2 Security area + (+) Option bytes programming + (+) Prefetch on CPU1 I-Code and CPU2 S-bus + (+) 32 instruction cache lines of 4*64 bits on I-Code for CPU1 + (+) 8 data cache lines of 4*64 bits on D-Code for CPU1 + (+) 4 instruction cache lines of 1*64 bits on S-bus for CPU2 + (+) 4 data cache lines of 1*64 bits on S-Bus for CPU2 + (+) Error code correction (ECC) : Data in flash are 72-bits word + (8 bits added per double word) + + ##### How to use this driver ##### + ============================================================================== + [..] + This driver provides functions and macros to configure and program the FLASH + memory of all STM32WLxx devices. + + (#) Flash Memory IO Programming functions: + (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and + HAL_FLASH_Lock() functions + (++) Program functions: double word and fast program (full row programming) + (++) There are two modes of programming: + (+++) Polling mode using HAL_FLASH_Program() function + (+++) Interrupt mode using HAL_FLASH_Program_IT() function + + (#) Interrupts and flags management functions: + (++) Handle FLASH interrupts by calling HAL_FLASH_IRQHandler() + (++) Callback functions are called when the flash operations are finished : + HAL_FLASH_EndOfOperationCallback() when everything is ok, otherwise + HAL_FLASH_OperationErrorCallback() + (++) Get error flag status by calling HAL_GetError() + + (#) Option bytes management functions : + (++) Lock and Unlock the option bytes using HAL_FLASH_OB_Unlock() and + HAL_FLASH_OB_Lock() functions + (++) Launch the reload of the option bytes using HAL_FLASH_OB_Launch() function. + In this case, a reset is generated + + [..] + In addition to these functions, this driver includes a set of macros allowing + to handle the following operations: + (+) Set the latency + (+) Enable/Disable the prefetch buffer + (+) Enable/Disable the suspend program or erase request + (+) Enable/Disable the Instruction cache and the Data cache + (+) Reset the Instruction cache and the Data cache + (+) Enable/Disable the Flash interrupts + (+) Monitor the Flash flags status + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wlxx_hal.h" + +/** @addtogroup STM32WLxx_HAL_Driver + * @{ + */ + +/** @defgroup FLASH FLASH + * @brief FLASH HAL module driver + * @{ + */ + +#ifdef HAL_FLASH_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private defines -----------------------------------------------------------*/ +/** @addtogroup FLASH_Private_Constants + * @{ + */ +#define FLASH_NB_DOUBLE_WORDS_IN_ROW 32 +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @defgroup FLASH_Private_Variables FLASH Private Variables + * @{ + */ +/** + * @brief Variable used for Program/Erase sectors under interruption + */ +FLASH_ProcessTypeDef pFlash = {.Lock = HAL_UNLOCKED, \ + .ErrorCode = HAL_FLASH_ERROR_NONE, \ + .ProcedureOnGoing = 0U, \ + .Address = 0U, \ + .Page = 0U, \ + .NbPagesToErase = 0U + }; +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup FLASH_Private_Functions FLASH Private Functions + * @{ + */ +static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data); +static void FLASH_Program_Fast(uint32_t Address, uint32_t DataAddress); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup FLASH_Exported_Functions FLASH Exported Functions + * @{ + */ + +/** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions + * @brief Programming operation functions + * +@verbatim + =============================================================================== + ##### Programming operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the FLASH + program operations. + +@endverbatim + * @{ + */ + +/** + * @brief Program double word or fast program of a row at a specified address. + * @note Before any operation, it is possible to check there is no operation suspended + * by call HAL_FLASHEx_IsOperationSuspended() + * @param TypeProgram Indicate the way to program at a specified address + * This parameter can be a value of @ref FLASH_TYPE_PROGRAM + * @param Address Specifies the address to be programmed. + * @param Data Specifies the data to be programmed + * This parameter is the data for the double word program and the address where + * are stored the data for the row fast program. + * + * @retval HAL_StatusTypeDef HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data) +{ + HAL_StatusTypeDef status; + + /* Check the parameters */ + assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram)); + assert_param(IS_ADDR_ALIGNED_64BITS(Address)); + assert_param(IS_FLASH_PROGRAM_ADDRESS(Address)); + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + /* Reset error code */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* Verify that next operation can be proceed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + if (status == HAL_OK) + { + if (TypeProgram == FLASH_TYPEPROGRAM_DOUBLEWORD) + { + /* Check the parameters */ + assert_param(IS_FLASH_PROGRAM_ADDRESS(Address)); + + /* Program double-word (64-bit) at a specified address */ + FLASH_Program_DoubleWord(Address, Data); + } + else + { + /* Check the parameters */ + assert_param(IS_FLASH_FAST_PROGRAM_ADDRESS(Address)); + + /* Fast program a 32 double-word (64-bit) row at a specified address */ + FLASH_Program_Fast(Address, (uint32_t)Data); + } + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + /* If the program operation is completed, disable the PG or FSTPG Bit */ +#ifdef CORE_CM0PLUS + CLEAR_BIT(FLASH->C2CR, TypeProgram); +#else + CLEAR_BIT(FLASH->CR, TypeProgram); +#endif + } + + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + + /* return status */ + return status; +} + +/** + * @brief Program double word or fast program of a row at a specified address with interrupt enabled. + * @note Before any operation, it is possible to check there is no operation suspended + * by call HAL_FLASHEx_IsOperationSuspended() + * @param TypeProgram Indicate the way to program at a specified address. + * This parameter can be a value of @ref FLASH_TYPE_PROGRAM + * @param Address Specifies the address to be programmed. + * @param Data Specifies the data to be programmed + * This parameter is the data for the double word program and the address where + * are stored the data for the row fast program. + * + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data) +{ + HAL_StatusTypeDef status; + + /* Check the parameters */ + assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram)); + assert_param(IS_ADDR_ALIGNED_64BITS(Address)); + assert_param(IS_FLASH_PROGRAM_ADDRESS(Address)); + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + /* Reset error code */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* Verify that next operation can be proceed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + if (status != HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + } + else + { + /* Set internal variables used by the IRQ handler */ + pFlash.ProcedureOnGoing = TypeProgram; + pFlash.Address = Address; + + /* Enable End of Operation and Error interrupts */ + __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_OPERR | FLASH_IT_ECCC); + + if (TypeProgram == FLASH_TYPEPROGRAM_DOUBLEWORD) + { + /* Check the parameters */ + assert_param(IS_FLASH_PROGRAM_ADDRESS(Address)); + + /* Program double-word (64-bit) at a specified address */ + FLASH_Program_DoubleWord(Address, Data); + } + else + { + /* Check the parameters */ + assert_param(IS_FLASH_FAST_PROGRAM_ADDRESS(Address)); + + /* Fast program a 32 double-word (64-bit) row at a specified address */ + FLASH_Program_Fast(Address, (uint32_t)Data); + } + } + + /* return status */ + return status; +} + +/** + * @brief Handle FLASH interrupt request. + * @retval None + */ +void HAL_FLASH_IRQHandler(void) +{ + uint32_t param = 0xFFFFFFFFU; + uint32_t error; + + /* Save flash errors. Only ECC detection can be checked here as ECCC + generates NMI */ +#ifdef CORE_CM0PLUS + error = (FLASH->C2SR & FLASH_FLAG_SR_ERRORS); + + /* Clear Current operation */ + CLEAR_BIT(FLASH->C2CR, pFlash.ProcedureOnGoing); +#else + error = (FLASH->SR & FLASH_FLAG_SR_ERRORS); + + /* Clear Current operation */ + CLEAR_BIT(FLASH->CR, pFlash.ProcedureOnGoing); +#endif + + /* A] Set parameter for user or error callbacks */ + /* check operation was a program or erase */ + if ((pFlash.ProcedureOnGoing & (FLASH_TYPEPROGRAM_DOUBLEWORD | FLASH_TYPEPROGRAM_FAST)) != 0U) + { + /* return address being programmed */ + param = pFlash.Address; + } + else if ((pFlash.ProcedureOnGoing & (FLASH_TYPEERASE_MASSERASE | FLASH_TYPEERASE_PAGES)) != 0U) + { + /* return page number being erased (0 for mass erase) */ + param = pFlash.Page; + } + else + { + /* No Procedure on-going */ + /* Nothing to do, but check error if any */ + } + + /* B] Check errors */ + if (error != 0U) + { + /*Save the error code*/ + pFlash.ErrorCode |= error; + + /* clear error flags */ + __HAL_FLASH_CLEAR_FLAG(error); + + /*Stop the procedure ongoing*/ + pFlash.ProcedureOnGoing = FLASH_TYPENONE; + + /* Error callback */ + HAL_FLASH_OperationErrorCallback(param); + } + + /* C] Check FLASH End of Operation flag */ + if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP)) + { + /* Clear FLASH End of Operation pending bit */ + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); + + if (pFlash.ProcedureOnGoing == FLASH_TYPEERASE_PAGES) + { + /* Nb of pages to erased can be decreased */ + pFlash.NbPagesToErase--; + + /* Check if there are still pages to erase*/ + if (pFlash.NbPagesToErase != 0U) + { + /* Increment page number */ + pFlash.Page++; + FLASH_PageErase(pFlash.Page); + } + else + { + /* No more pages to erase: stop erase pages procedure */ + pFlash.ProcedureOnGoing = FLASH_TYPENONE; + } + } + else + { + /*Stop the ongoing procedure */ + pFlash.ProcedureOnGoing = FLASH_TYPENONE; + } + + /* User callback */ + HAL_FLASH_EndOfOperationCallback(param); + } + + if (pFlash.ProcedureOnGoing == FLASH_TYPENONE) + { + /* Disable End of Operation and Error interrupts */ + __HAL_FLASH_DISABLE_IT(FLASH_IT_EOP | FLASH_IT_OPERR | FLASH_IT_ECCC); + + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + } +} + +/** + * @brief FLASH end of operation interrupt callback. + * @param ReturnValue The value saved in this parameter depends on the ongoing procedure + * Mass Erase: 0 + * Page Erase: Page which has been erased + * Program: Address which was selected for data program + * @retval None + */ +__weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(ReturnValue); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_FLASH_EndOfOperationCallback could be implemented in the user file + */ +} + +/** + * @brief FLASH operation error interrupt callback. + * @param ReturnValue The value saved in this parameter depends on the ongoing procedure + * Mass Erase: 0 + * Page Erase: Page number which returned an error + * Program: Address which was selected for data program + * @retval None + */ +__weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(ReturnValue); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_FLASH_OperationErrorCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions + * @brief Management functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the FLASH + memory operations. + +@endverbatim + * @{ + */ + +/** + * @brief Unlock the FLASH control register access. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_Unlock(void) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (READ_BIT(FLASH->CR, FLASH_CR_LOCK) != 0U) + { + /* Authorize the FLASH Registers access */ + WRITE_REG(FLASH->KEYR, FLASH_KEY1); + WRITE_REG(FLASH->KEYR, FLASH_KEY2); + + /* verify Flash is unlock */ + if (READ_BIT(FLASH->CR, FLASH_CR_LOCK) != 0U) + { + status = HAL_ERROR; + } + } + + return status; +} + +/** + * @brief Lock the FLASH control register access. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_Lock(void) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Set the LOCK Bit to lock the FLASH Registers access */ + /* @Note The lock and unlock procedure is done only using CR registers even from CPU2 */ + SET_BIT(FLASH->CR, FLASH_CR_LOCK); + + /* verify Flash is locked */ + if (READ_BIT(FLASH->CR, FLASH_CR_LOCK) == 0U) + { + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Unlock the FLASH Option Bytes Registers access. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void) +{ + HAL_StatusTypeDef status = HAL_ERROR; + + /* @Note The lock and unlock procedure is done only using CR registers even from CPU2 */ + if (READ_BIT(FLASH->CR, FLASH_CR_OPTLOCK) != 0U) + { + /* Authorizes the Option Byte register programming */ + WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY1); + WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY2); + + /* verify option bytes are unlocked */ + if (READ_BIT(FLASH->CR, FLASH_CR_OPTLOCK) == 0U) + { + status = HAL_OK; + } + } + + return status; +} + +/** + * @brief Lock the FLASH Option Bytes Registers access. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_OB_Lock(void) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Set the OPTLOCK Bit to lock the FLASH Option Byte Registers access */ + /* @Note The lock and unlock procedure is done only using CR registers even from CPU2 */ + SET_BIT(FLASH->CR, FLASH_CR_OPTLOCK); + + /* verify option bytes are lock */ + if (READ_BIT(FLASH->CR, FLASH_CR_OPTLOCK) == 0U) + { + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Launch the option byte loading. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_OB_Launch(void) +{ + /* Set the bit to force the option byte reloading */ + /* The OB launch is done from the same register either from CPU1 or CPU2 */ + SET_BIT(FLASH->CR, FLASH_CR_OBL_LAUNCH); + + /* We should not reach here : Option byte launch generates Option byte reset + so return error */ + return HAL_ERROR; +} + +/** + * @} + */ + +/** @defgroup FLASH_Exported_Functions_Group3 Peripheral State and Errors functions + * @brief Peripheral Errors functions + * +@verbatim + =============================================================================== + ##### Peripheral Errors functions ##### + =============================================================================== + [..] + This subsection permits to get in run-time Errors of the FLASH peripheral. + +@endverbatim + * @{ + */ + +/** + * @brief Get the specific FLASH error flag. + * @retval FLASH_ErrorCode The returned value can be + * @arg @ref HAL_FLASH_ERROR_NONE No error set + * @arg @ref HAL_FLASH_ERROR_OP FLASH Operation error + * @arg @ref HAL_FLASH_ERROR_PROG FLASH Programming error + * @arg @ref HAL_FLASH_ERROR_WRP FLASH Write protection error + * @arg @ref HAL_FLASH_ERROR_PGA FLASH Programming alignment error + * @arg @ref HAL_FLASH_ERROR_SIZ FLASH Size error + * @arg @ref HAL_FLASH_ERROR_PGS FLASH Programming sequence error + * @arg @ref HAL_FLASH_ERROR_MIS FLASH Fast programming data miss error + * @arg @ref HAL_FLASH_ERROR_FAST FLASH Fast programming error + * @arg @ref HAL_FLASH_ERROR_RD FLASH Read Protection error (PCROP) + * @arg @ref HAL_FLASH_ERROR_OPTV FLASH Option validity error + */ +uint32_t HAL_FLASH_GetError(void) +{ + return pFlash.ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ + +/** @addtogroup FLASH_Private_Functions + * @{ + */ + +/** + * @brief Wait for a FLASH operation to complete. + * @param Timeout Maximum flash operation timeout + * @retval HAL_StatusTypeDef HAL Status + */ +HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout) +{ + uint32_t error; + uint32_t tickstart = HAL_GetTick(); + + /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset. + Even if the FLASH operation fails, the BUSY flag will be reset and an error + flag will be set */ + while (__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY)) + { + if ((HAL_GetTick() - tickstart) >= Timeout) + { + return HAL_TIMEOUT; + } + } + + /* check flash errors. Only ECC correction can be checked here as ECCD + generates NMI */ +#ifdef CORE_CM0PLUS + error = FLASH->C2SR; +#else + error = FLASH->SR; +#endif + + /* Check FLASH End of Operation flag */ + if ((error & FLASH_FLAG_EOP) != 0U) + { + /* Clear FLASH End of Operation pending bit */ + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); + } + + /* Now update error variable to only error value */ + error &= FLASH_FLAG_SR_ERRORS; + + /* clear error flags */ + __HAL_FLASH_CLEAR_FLAG(error); + + if (error != 0U) + { + /*Save the error code*/ + pFlash.ErrorCode = error; + + return HAL_ERROR; + } + + /* Wait for control register to be written */ + while (__HAL_FLASH_GET_FLAG(FLASH_FLAG_CFGBSY)) + { + if ((HAL_GetTick() - tickstart) >= Timeout) + { + return HAL_TIMEOUT; + } + } + + return HAL_OK; +} + +/** + * @brief Program double-word (64-bit) at a specified address. + * @param Address Specifies the address to be programmed. + * @param Data Specifies the data to be programmed. + * @retval None + */ +static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data) +{ +#ifdef CORE_CM0PLUS + /* Set PG bit */ + SET_BIT(FLASH->C2CR, FLASH_CR_PG); +#else + /* Set PG bit */ + SET_BIT(FLASH->CR, FLASH_CR_PG); +#endif + + /* Program first word */ + *(uint32_t *)Address = (uint32_t)Data; + + /* Barrier to ensure programming is performed in 2 steps, in right order + (independently of compiler optimization behavior) */ + __ISB(); + + /* Program second word */ + *(uint32_t *)(Address + 4U) = (uint32_t)(Data >> 32U); +} + +/** + * @brief Fast program a 32 row double-word (64-bit) at a specified address. + * @param Address Specifies the address to be programmed. + * @param DataAddress Specifies the address where the data are stored. + * @retval None + */ +#ifdef CORE_CM0PLUS +static __RAM_FUNC void FLASH_Program_Fast(uint32_t Address, uint32_t DataAddress) +#else +static void FLASH_Program_Fast(uint32_t Address, uint32_t DataAddress) +#endif +{ + uint8_t row_index = (2 * FLASH_NB_DOUBLE_WORDS_IN_ROW); + __IO uint32_t *dest_addr = (__IO uint32_t *)Address; + __IO uint32_t *src_addr = (__IO uint32_t *)DataAddress; + uint32_t primask_bit; + + /* Set FSTPG bit */ +#ifdef CORE_CM0PLUS + SET_BIT(FLASH->C2CR, FLASH_CR_FSTPG); +#else + SET_BIT(FLASH->CR, FLASH_CR_FSTPG); +#endif + + /* Enter critical section: row programming should not be longer than 7 ms */ + primask_bit = __get_PRIMASK(); + __disable_irq(); + + /* Program the double word of the row */ + do + { + *dest_addr = *src_addr; + dest_addr++; + src_addr++; + row_index--; + } while (row_index != 0U); + + /* wait for BSY in order to be sure that flash operation is ended before + allowing prefetch in flash. Timeout does not return status, as it will + be anyway done later */ + while (__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY) != 0U) + { + } + + /* Exit critical section: restore previous priority mask */ + __set_PRIMASK(primask_bit); +} + +/** + * @} + */ + +#endif /* HAL_FLASH_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ + diff --git a/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c b/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c new file mode 100644 index 0000000..babb0b4 --- /dev/null +++ b/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c @@ -0,0 +1,1388 @@ +/** + ****************************************************************************** + * @file stm32wlxx_hal_flash_ex.c + * @author MCD Application Team + * @brief Extended FLASH HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the FLASH extended peripheral: + * + Extended programming operations functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### Flash Extended features ##### + ============================================================================== + + [..] Comparing to other previous devices, the FLASH interface for STM32WLxx + devices contains the following additional features + + (+) Capacity up to 256kB with single bank architecture supporting read-while-write + capability (RWW) + (+) Single bank memory organization + (+) PCROP protection + (+) WRP protection + (+) CPU2 Security area + (+) Program Erase Suspend feature + + ##### How to use this driver ##### + ============================================================================== + [..] This driver provides functions to configure and program the FLASH memory + of all STM32WLxx devices. It includes + (#) Flash Memory Erase functions: + (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and + HAL_FLASH_Lock() functions + (++) Erase function: Erase page, erase all sectors + (++) There are two modes of erase : + (+++) Polling Mode using HAL_FLASHEx_Erase() + (+++) Interrupt Mode using HAL_FLASHEx_Erase_IT() + + (#) Option Bytes Programming function: Use HAL_FLASHEx_OBProgram() to : + (++) Set/Reset the write protection (per 4 KByte) + (++) Set the Read protection Level + (++) Program the user Option Bytes + (++) Configure the PCROP protection (per 2 KByte) + (++) Configure the IPCC Buffer start Address + (++) Configure the CPU2 boot region and reset vector start Address + (++) Configure the Flash and SRAM2 secure area + + (#) Get Option Bytes Configuration function: Use HAL_FLASHEx_OBGetConfig() to : + (++) Get the value of a write protection area + (++) Know if the read protection is activated + (++) Get the value of the user Option Bytes + (++) Get the value of a PCROP area + (++) Get the IPCC Buffer start Address + (++) Get the CPU2 boot region and reset vector start Address + (++) Get the Flash and SRAM2 secure area + + (#) Flash Suspend, Allow functions: + (++) Suspend or Allow new program or erase operation request using HAL_FLASHEx_SuspendOperation() and + HAL_FLASHEx_AllowOperation() functions + + (#) Check is flash content is empty or not using HAL_FLASHEx_FlashEmptyCheck(). + and modify this setting (for flash loader purpose e.g.) using + HAL_FLASHEx_ForceFlashEmpty(). + + (#) Enable, Disable CPU2 debug access using HAL_FLASHEx_EnableC2Debug() or + HAL_FLASHEx_DisableC2Debug() + + (#) Enable Secure Hide Protection area access using HAL_FLASHEx_EnableSecHideProtection() + (++) Enable Secure Hide Protection area access done by hardware on a system reset + + (#) Privilege mode configuration function: Use HAL_FLASHEx_ConfigPrivMode() + (++) FLASH register can be protected against non-privilege accesses + + (#) Get the privilege mode configuration function: Use HAL_FLASHEx_GetPrivMode() + (++) Returns if the FLASH registers are protected against non-privilege accesses + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wlxx_hal.h" + +/** @addtogroup STM32WLxx_HAL_Driver + * @{ + */ + +/** @defgroup FLASHEx FLASHEx + * @brief FLASH Extended HAL module driver + * @{ + */ + +#ifdef HAL_FLASH_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions + * @{ + */ +static void FLASH_MassErase(void); +static void FLASH_AcknowledgePageErase(void); +static void FLASH_FlushCaches(void); +static void FLASH_OB_WRPConfig(uint32_t WRPArea, uint32_t WRPStartOffset, uint32_t WRDPEndOffset); +static void FLASH_OB_OptrConfig(uint32_t UserType, uint32_t UserConfig, uint32_t RDPLevel); +static void FLASH_OB_PCROP1AConfig(uint32_t PCROPConfig, uint32_t PCROP1AStartAddr, + uint32_t PCROP1AEndAddr); +static void FLASH_OB_PCROP1BConfig(uint32_t PCROP1BStartAddr, uint32_t PCROP1BEndAddr); +#if defined(DUAL_CORE) +static void FLASH_OB_IPCCBufferAddrConfig(uint32_t IPCCDataBufAddr); +static void FLASH_OB_SecureConfig(FLASH_OBProgramInitTypeDef *pOBParam); +#endif /* DUAL_CORE */ +static void FLASH_OB_GetWRP(uint32_t WRPArea, uint32_t *WRPStartOffset, uint32_t *WRDPEndOffset); +static uint32_t FLASH_OB_GetRDP(void); +static uint32_t FLASH_OB_GetUser(void); +static void FLASH_OB_GetPCROP(uint32_t *PCROPConfig, uint32_t *PCROP1AStartAddr, uint32_t *PCROP1AEndAddr, + uint32_t *PCROP1BStartAddr, uint32_t *PCROP1BEndAddr); +#if defined(DUAL_CORE) +static uint32_t FLASH_OB_GetIPCCBufferAddr(void); +static void FLASH_OB_GetSecureMemoryConfig(uint32_t *SecureFlashStartAddr, + uint32_t *HideProtectionStartAddr, uint32_t *SecureSRAM2StartAddr, uint32_t *SecureSRAM1StartAddr, + uint32_t *SecureMode); +static void FLASH_OB_GetC2BootResetConfig(uint32_t *C2BootResetVectAddr, uint32_t *C2BootResetRegion); +#endif /* DUAL_CORE */ +static HAL_StatusTypeDef FLASH_OB_ProceedWriteOperation(void); +#if defined(DUAL_CORE) +static uint32_t FLASH_OB_GetSUBGHZSPISecureAccess(void); +static uint32_t FLASH_OB_GetC2DebugAccessMode(void); +static void FLASH_OB_ConfigSecureMode(uint32_t SecureMode, uint32_t *Reg, uint32_t Bit, + uint32_t ValueEnable); +static uint32_t FLASH_OB_GetSecureMode(uint32_t Reg, uint32_t Bit, uint32_t ValueEnable, + uint32_t ValueDisable); +#endif /* DUAL_CORE */ +/** + * @} + */ + +/* Exported functions -------------------------------------------------------*/ +/** @defgroup FLASHEx_Exported_Functions FLASH Extended Exported Functions + * @{ + */ + +/** @defgroup FLASHEx_Exported_Functions_Group1 Extended IO operation functions + * @brief Extended IO operation functions + * +@verbatim + =============================================================================== + ##### Extended programming operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the Extended FLASH + programming operations Operations. + +@endverbatim + * @{ + */ +/** + * @brief Perform a mass erase or erase the specified FLASH memory pages. + * @note Before any operation, it is possible to check there is no operation suspended + * by call HAL_FLASHEx_IsOperationSuspended() + * @param[in] pEraseInit Pointer to an @ref FLASH_EraseInitTypeDef structure that + * contains the configuration information for the erasing. + * @param[out] PageError Pointer to variable that contains the configuration + * information on faulty page in case of error (0xFFFFFFFF means that all + * the pages have been correctly erased) + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_Erase(const FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError) +{ + HAL_StatusTypeDef status; + uint32_t index; + + /* Check the parameters */ + assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase)); + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + /* Reset error code */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* Verify that next operation can be proceed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + if (status == HAL_OK) + { + if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE) + { + /* Mass erase to be done */ + FLASH_MassErase(); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + /* If operation is completed or interrupted, no need to clear the Mass Erase Bit */ + } + else + { + /*Initialization of PageError variable*/ + *PageError = 0xFFFFFFFFU; + + for (index = pEraseInit->Page; index < (pEraseInit->Page + pEraseInit->NbPages); index++) + { + /* Start erase page */ + FLASH_PageErase(index); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + if (status != HAL_OK) + { + /* In case of error, stop erase procedure and return the faulty address */ + *PageError = index; + break; + } + } + + /* If operation is completed or interrupted, disable the Page Erase Bit */ + FLASH_AcknowledgePageErase(); + } + + /* Flush the caches to be sure of the data consistency */ + FLASH_FlushCaches(); + } + + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + + return status; +} + +/** + * @brief Perform a mass erase or erase the specified FLASH memory pages with interrupt enabled. + * @note Before any operation, it is possible to check there is no operation suspended + * by call HAL_FLASHEx_IsOperationSuspended() + * @param pEraseInit Pointer to an @ref FLASH_EraseInitTypeDef structure that + * contains the configuration information for the erasing. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit) +{ + HAL_StatusTypeDef status; + + /* Check the parameters */ + assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase)); + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + /* Reset error code */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* save procedure for interrupt treatment */ + pFlash.ProcedureOnGoing = pEraseInit->TypeErase; + + /* Verify that next operation can be proceed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + if (status != HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + } + else + { + /* Enable End of Operation and Error interrupts */ + __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_OPERR); + + if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE) + { + /* Set Page to 0 for Interrupt callback management */ + pFlash.Page = 0; + + /* Proceed to Mass Erase */ + FLASH_MassErase(); + } + else + { + /* Erase by page to be done */ + pFlash.NbPagesToErase = pEraseInit->NbPages; + pFlash.Page = pEraseInit->Page; + + /*Erase 1st page and wait for IT */ + FLASH_PageErase(pEraseInit->Page); + } + } + + /* return status */ + return status; +} + +/** + * @brief Program Option bytes. + * @param pOBInit Pointer to an @ref FLASH_OBProgramInitTypeDef structure that + * contains the configuration information for the programming. + * @note To configure any option bytes, the option lock bit OPTLOCK must be + * cleared with the call of @ref HAL_FLASH_OB_Unlock() function. + * @note New option bytes configuration will be taken into account only + * - after an option bytes launch through the call of @ref HAL_FLASH_OB_Launch() + * - a Power On Reset + * - an exit from Standby or Shutdown mode. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit) +{ + uint32_t optr; + HAL_StatusTypeDef status; + + /* Check the parameters */ + assert_param(IS_OPTIONBYTE(pOBInit->OptionType)); + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* Write protection configuration */ + if ((pOBInit->OptionType & OPTIONBYTE_WRP) != 0U) + { + /* Configure of Write protection on the selected area */ + FLASH_OB_WRPConfig(pOBInit->WRPArea, pOBInit->WRPStartOffset, pOBInit->WRPEndOffset); + } + + /* Option register */ + if ((pOBInit->OptionType & (OPTIONBYTE_RDP | OPTIONBYTE_USER)) == (OPTIONBYTE_RDP | OPTIONBYTE_USER)) + { + /* Fully modify OPTR register with RDP & user data */ + FLASH_OB_OptrConfig(pOBInit->UserType, pOBInit->UserConfig, pOBInit->RDPLevel); + } + else if ((pOBInit->OptionType & OPTIONBYTE_RDP) != 0U) + { + /* Only modify RDP so get current user data */ + optr = FLASH_OB_GetUser(); + + /* Remove BOR LEVEL User Type*/ + optr &= ~OB_USER_BOR_LEV; + + FLASH_OB_OptrConfig(optr, optr, pOBInit->RDPLevel); + } + else if ((pOBInit->OptionType & OPTIONBYTE_USER) != 0U) + { + /* Only modify user so get current RDP level */ + optr = FLASH_OB_GetRDP(); + FLASH_OB_OptrConfig(pOBInit->UserType, pOBInit->UserConfig, optr); + } + else + { + /* Do Nothing */ + } + + /* PCROP Configuration */ + if ((pOBInit->OptionType & OPTIONBYTE_PCROP) != 0U) + { + /* Check the parameters */ + assert_param(IS_OB_PCROP_CONFIG(pOBInit->PCROPConfig)); + + if ((pOBInit->PCROPConfig & (OB_PCROP_ZONE_A | OB_PCROP_RDP_ERASE)) != 0U) + { + /* Configure the Zone 1A Proprietary code readout protection */ + FLASH_OB_PCROP1AConfig(pOBInit->PCROPConfig, pOBInit->PCROP1AStartAddr, pOBInit->PCROP1AEndAddr); + } + + if ((pOBInit->PCROPConfig & OB_PCROP_ZONE_B) != 0U) + { + /* Configure the Zone 1B Proprietary code readout protection */ + FLASH_OB_PCROP1BConfig(pOBInit->PCROP1BStartAddr, pOBInit->PCROP1BEndAddr); + } + } + +#if defined(DUAL_CORE) + /* Secure mode and CPU2 Boot Vector */ + if ((pOBInit->OptionType & (OPTIONBYTE_SECURE_MODE | OPTIONBYTE_C2_BOOT_VECT | OPTIONBYTE_C2_DEBUG_ACCESS | + OPTIONBYTE_SUBGHZSPI_SECURE_ACCESS)) != 0U) + { + /* Set the secure flash, SRAM memory start address, CPU2 boot reset vector or CPU2 debug access */ + FLASH_OB_SecureConfig(pOBInit); + } + + /* IPCC mailbox data buffer address */ + if ((pOBInit->OptionType & OPTIONBYTE_IPCC_BUF_ADDR) != 0U) + { + /* Configure the IPCC data buffer address */ + FLASH_OB_IPCCBufferAddrConfig(pOBInit->IPCCdataBufAddr); + } +#endif /* DUAL_CORE */ + + /* Proceed the OB Write Operation */ + status = FLASH_OB_ProceedWriteOperation(); + + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + + /* return status */ + return status; +} + +/** + * @brief Get the Option bytes configuration. + * @note warning: this API only read flash register, it does not reflect any + * change that would have been programmed between previous Option byte + * loading and current call. + * @param pOBInit Pointer to an @ref FLASH_OBProgramInitTypeDef structure that contains the + * configuration information. The fields pOBInit->WRPArea and + * pOBInit->PCROPConfig should indicate which area is requested + * for the WRP and PCROP. + * @retval None + */ +void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit) +{ + pOBInit->OptionType = OPTIONBYTE_ALL; + + if ((pOBInit->WRPArea == OB_WRPAREA_BANK1_AREAA) || (pOBInit->WRPArea == OB_WRPAREA_BANK1_AREAB)) + { + /* Get write protection on the selected area */ + FLASH_OB_GetWRP(pOBInit->WRPArea, &(pOBInit->WRPStartOffset), &(pOBInit->WRPEndOffset)); + } + + /* Get Read protection level */ + pOBInit->RDPLevel = FLASH_OB_GetRDP(); + + /* Get the user option bytes */ + pOBInit->UserConfig = FLASH_OB_GetUser(); + pOBInit->UserType = OB_USER_ALL; + + /* Get the Zone 1A and 1B Proprietary code readout protection */ + FLASH_OB_GetPCROP(&(pOBInit->PCROPConfig), &(pOBInit->PCROP1AStartAddr), &(pOBInit->PCROP1AEndAddr), + &(pOBInit->PCROP1BStartAddr), &(pOBInit->PCROP1BEndAddr)); + pOBInit->PCROPConfig |= (OB_PCROP_ZONE_A | OB_PCROP_ZONE_B); + +#if defined(DUAL_CORE) + /* Get the IPCC start Address */ + pOBInit->IPCCdataBufAddr = FLASH_OB_GetIPCCBufferAddr(); + + /* Get the Secure Flash start address, Secure Hide Protection start address Secure Backup SRAM2 start address, Secure non-Backup SRAM1 start address and the Security Mode, */ + FLASH_OB_GetSecureMemoryConfig(&(pOBInit->SecureFlashStartAddr), &(pOBInit->HideProtectionStartAddr), + &(pOBInit->SecureSRAM2StartAddr), &(pOBInit->SecureSRAM1StartAddr), &(pOBInit->SecureMode)); + + /* Get the M0+ Secure Boot reset vector address and Secure Boot memory selection */ + FLASH_OB_GetC2BootResetConfig(&(pOBInit->C2SecureBootVectAddr), &(pOBInit->C2BootRegion)); + + /* Get the Sub-GHz radio SPI Secure Access */ + pOBInit->SUBGHZSPISecureAccess = FLASH_OB_GetSUBGHZSPISecureAccess(); + + /* Get the CPU2 Debug Access Mode */ + pOBInit->C2DebugAccessMode = FLASH_OB_GetC2DebugAccessMode(); +#endif /* DUAL_CORE */ +} + +/** + * @brief Flash Empty check + * @note This API checks if first location in Flash is programmed or not. + * This check is done once by Option Byte Loader. + * @retval Returned value can be one of the following values: + * @arg @ref FLASH_PROG_NOT_EMPTY 1st location in Flash is programmed + * @arg @ref FLASH_PROG_EMPTY 1st location in Flash is empty + */ +uint32_t HAL_FLASHEx_FlashEmptyCheck(void) +{ + return (READ_BIT(FLASH->ACR, FLASH_ACR_EMPTY)); +} + + +/** + * @brief Force Empty check value. + * @note Allows to modify program empty check value in order to force this + * information in Flash Interface, for all next reset that do not launch + * Option Byte Loader. + * @param FlashEmpty Specifies the empty check value + * This parameter can be one of the following values: + * @arg @ref FLASH_PROG_NOT_EMPTY 1st location in Flash is programmed + * @arg @ref FLASH_PROG_EMPTY 1st location in Flash is empty + * @retval None + */ +void HAL_FLASHEx_ForceFlashEmpty(uint32_t FlashEmpty) +{ + assert_param(IS_FLASH_EMPTY_CHECK(FlashEmpty)); + + MODIFY_REG(FLASH->ACR, FLASH_ACR_EMPTY, FlashEmpty); +} + +/** + * @brief Suspend new program or erase operation request. + * @note Any new Flash program and erase operation on both CPU side will be suspended + * until this bit and the same bit in Flash CPU2 access control register (FLASH_C2ACR) are + * cleared. The PESD bit in both the Flash status register (FLASH_SR) and Flash + * CPU2 status register (FLASH_C2SR) register will be set when at least one PES + * bit in FLASH_ACR or FLASH_C2ACR is set. + * @retval None + */ +void HAL_FLASHEx_SuspendOperation(void) +{ +#if defined(CORE_CM0PLUS) + SET_BIT(FLASH->C2ACR, FLASH_C2ACR_PES); +#else + SET_BIT(FLASH->ACR, FLASH_ACR_PES); +#endif +} + +/** + * @brief Allow new program or erase operation request. + * @note Any new Flash program and erase operation on both CPU side will be allowed + * until one of this bit or the same bit in Flash CPU2 access control register (FLASH_C2ACR) is + * set. The PESD bit in both the Flash status register (FLASH_SR) and Flash + * CPU2 status register (FLASH_C2SR) register will be clear when both PES + * bit in FLASH_ACR or FLASH_C2ACR is cleared. + * @retval None + */ +void HAL_FLASHEx_AllowOperation(void) +{ +#if defined(CORE_CM0PLUS) + CLEAR_BIT(FLASH->C2ACR, FLASH_C2ACR_PES); +#else + CLEAR_BIT(FLASH->ACR, FLASH_ACR_PES); +#endif +} + +/** + * @brief Check if new program or erase operation request from CPU1 or CPU2 is suspended + * @note Any new Flash program and erase operation on both CPU side will be allowed + * until one of this bit or the same bit in Flash CPU2 access control register (FLASH_C2ACR) is + * set. The PESD bit in both the Flash status register (FLASH_SR) and Flash + * CPU2 status register (FLASH_C2SR) register will be cleared when both PES + * bit in FLASH_ACR and FLASH_C2ACR are cleared. + * @retval Status + * - 0 : No suspended flash operation + * - 1 : Flash operation is suspended + */ +uint32_t HAL_FLASHEx_IsOperationSuspended(void) +{ + uint32_t status = 0U; + +#if defined(CORE_CM0PLUS) + if (READ_BIT(FLASH->C2SR, FLASH_C2SR_PESD) == FLASH_C2SR_PESD) +#else + if (READ_BIT(FLASH->SR, FLASH_SR_PESD) == FLASH_SR_PESD) +#endif + { + status = 1U; + } + + return status; +} + +#if defined(DUAL_CORE) +/** + * @brief Disable CPU2 debug access. + * @note This feature can only be accessed by a secure privileged CPU2 + * When FLASH_SFR_HDPAD = 0 (Secure Hide Protection area enabled) the CPU2 software debug is disabled after a system reset. + * When FLASH_SFR_HDPAD = 1 (Secure Hide Protection area disabled) the CPU2 software debug is enabled, after a system reset. + * @retval None + */ +void HAL_FLASHEx_DisableC2Debug(void) +{ + CLEAR_BIT(FLASH->ACR2, FLASH_ACR2_C2SWDBGEN); +} + +/** + * @brief Enable CPU2 debug access (When also enabled in FLASH_SFR_DDS). + * @note This feature can only be accessed by a secure privileged CPU2 + * When FLASH_SFR_HDPAD = 0 (Secure Hide Protection area enabled) the CPU2 software debug is disabled after a system reset. + * When FLASH_SFR_HDPAD = 1 (Secure Hide Protection area disabled) the CPU2 software debug is enabled, after a system reset. + * @retval None + */ +void HAL_FLASHEx_EnableC2Debug(void) +{ + SET_BIT(FLASH->ACR2, FLASH_ACR2_C2SWDBGEN); +} + +/** + * @brief Enable Secure Hide Protection Area access. + * @note This feature can only be accessed by a secure privileged CPU2 + * This bit is set by software and will only be reset by hardware on a system reset. + * @retval None + */ +void HAL_FLASHEx_EnableSecHideProtection(void) +{ + SET_BIT(FLASH->ACR2, FLASH_ACR2_HDPADIS); +} + +/** + * @brief Configuration of the privilege attribute. + * @note This feature can only be accessed by a secure privileged CPU2 + * @param PrivMode indicate privilege mode configuration + * This parameter can be one of the following values: + * @arg @ref FLASH_PRIV_GRANTED Access to Flash registers is granted + * @arg @ref FLASH_PRIV_DENIED Access to Flash registers is denied to non-privilege access + * @retval None + */ +void HAL_FLASHEx_ConfigPrivMode(uint32_t PrivMode) +{ + /* Check the parameters */ + assert_param(IS_FLASH_CFGPRIVMODE(PrivMode)); + + MODIFY_REG(FLASH->ACR2, FLASH_ACR2_PRIVMODE, PrivMode); +} + +/** + * @brief Return the value of the privilege attribute. + * @note This feature can only be accessed by a secure privileged CPU2 + * @retval It indicates privilege mode configuration. + * This return value can be one of the following values: + * @arg @ref FLASH_PRIV_GRANTED Access to Flash registers is granted + * @arg @ref FLASH_PRIV_DENIED Access to Flash registers is denied to non-privilege access + */ +uint32_t HAL_FLASHEx_GetPrivMode(void) +{ + return (FLASH->ACR2 & FLASH_ACR2_PRIVMODE); +} +#endif /* DUAL_CORE */ + +/** + * @} + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @addtogroup FLASHEx_Private_Functions + * @{ + */ + +/** + * @brief Mass erase of FLASH memory. + * @retval None + */ +static void FLASH_MassErase(void) +{ + /* Set the Mass Erase Bit and start bit */ +#ifdef CORE_CM0PLUS + SET_BIT(FLASH->C2CR, (FLASH_CR_MER | FLASH_CR_STRT)); +#else + SET_BIT(FLASH->CR, (FLASH_CR_MER | FLASH_CR_STRT)); +#endif +} + +/** + * @brief Erase the specified FLASH memory page. + * @param Page FLASH page to erase + * This parameter must be a value between 0 and (max number of pages in Flash - 1) + * @retval None + */ +void FLASH_PageErase(uint32_t Page) +{ + /* Check the parameters */ + assert_param(IS_FLASH_PAGE(Page)); + + /* Proceed to erase the page */ +#ifdef CORE_CM0PLUS + MODIFY_REG(FLASH->C2CR, FLASH_CR_PNB, ((Page << FLASH_CR_PNB_Pos) | FLASH_CR_PER | FLASH_CR_STRT)); +#else + MODIFY_REG(FLASH->CR, FLASH_CR_PNB, ((Page << FLASH_CR_PNB_Pos) | FLASH_CR_PER | FLASH_CR_STRT)); +#endif +} + +/** + * @brief Flush the instruction and data caches. + * @retval None + */ +void FLASH_FlushCaches(void) +{ + /* Flush instruction cache */ + if (READ_BIT(FLASH->ACR, FLASH_ACR_ICEN) == FLASH_ACR_ICEN) + { + /* Disable instruction cache */ + __HAL_FLASH_INSTRUCTION_CACHE_DISABLE(); + /* Reset instruction cache */ + __HAL_FLASH_INSTRUCTION_CACHE_RESET(); + /* Enable instruction cache */ + __HAL_FLASH_INSTRUCTION_CACHE_ENABLE(); + } + +#ifdef CORE_CM0PLUS +#else + /* Flush data cache */ + if (READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) == FLASH_ACR_DCEN) + { + /* Disable data cache */ + __HAL_FLASH_DATA_CACHE_DISABLE(); + /* Reset data cache */ + __HAL_FLASH_DATA_CACHE_RESET(); + /* Enable data cache */ + __HAL_FLASH_DATA_CACHE_ENABLE(); + } +#endif +} + +/** + * @brief Acknlowldge the page erase operation. + * @retval None + */ +static void FLASH_AcknowledgePageErase(void) +{ +#ifdef CORE_CM0PLUS + CLEAR_BIT(FLASH->C2CR, (FLASH_CR_PER | FLASH_CR_PNB)); +#else + CLEAR_BIT(FLASH->CR, (FLASH_CR_PER | FLASH_CR_PNB)); +#endif +} + +/** + * @brief Configure the write protection of the desired pages. + * @note When WRP is active in a zone, it cannot be erased or programmed. + * Consequently, a software mass erase cannot be performed if one zone + * is write-protected. + * @note When the memory read protection level is selected (RDP level = 1), + * it is not possible to program or erase Flash memory if the CPU debug + * features are connected (JTAG or single wire) or boot code is being + * executed from RAM or System flash, even if WRP is not activated. + * @note To configure the WRP options, the option lock bit OPTLOCK must be + * cleared with the call of the @ref HAL_FLASH_OB_Unlock() function. + * @note To validate the WRP options, the option bytes must be reloaded + * through the call of the @ref HAL_FLASH_OB_Launch() function. + * @param WRPArea Specifies the area to be configured. + * This parameter can be one of the following values: + * @arg @ref OB_WRPAREA_BANK1_AREAA Flash Bank 1 Area A + * @arg @ref OB_WRPAREA_BANK1_AREAB Flash Bank 1 Area B + * @param WRPStartOffset Specifies the start page of the write protected area + * This parameter can be page number between 0 and (max number of pages in the Flash - 1) + * @param WRDPEndOffset Specifies the end page of the write protected area + * This parameter can be page number between WRPStartOffset and (max number of pages in the Flash - 1) + * @retval None + */ +static void FLASH_OB_WRPConfig(uint32_t WRPArea, uint32_t WRPStartOffset, uint32_t WRDPEndOffset) +{ + /* Check the parameters */ + assert_param(IS_OB_WRPAREA(WRPArea)); + assert_param(IS_FLASH_PAGE(WRPStartOffset)); + assert_param(IS_FLASH_PAGE(WRDPEndOffset)); + + /* Configure the write protected area */ + if (WRPArea == OB_WRPAREA_BANK1_AREAA) + { + MODIFY_REG(FLASH->WRP1AR, (FLASH_WRP1AR_WRP1A_STRT | FLASH_WRP1AR_WRP1A_END), + (WRPStartOffset | (WRDPEndOffset << FLASH_WRP1AR_WRP1A_END_Pos))); + } + else /* OB_WRPAREA_BANK1_AREAB */ + { + MODIFY_REG(FLASH->WRP1BR, (FLASH_WRP1BR_WRP1B_STRT | FLASH_WRP1BR_WRP1B_END), + (WRPStartOffset | (WRDPEndOffset << FLASH_WRP1AR_WRP1A_END_Pos))); + } +} + +#if defined(DUAL_CORE) /* Comment duplicated for Document generation */ +/** + * @brief Set user & RDP configuration + * @note !!! Warning : When enabling OB_RDP level 2 it's no more possible + * to go back to level 1 or 0 !!! + * @param UserType The FLASH User Option Bytes to be modified + * This parameter can be a combination of all the following values: + * @arg @ref OB_USER_BOR_LEV or @ref OB_USER_nRST_STOP or @ref OB_USER_nRST_STDBY or + * @arg @ref OB_USER_nRST_SHDW or @ref OB_USER_IWDG_SW or @ref OB_USER_IWDG_STOP or + * @arg @ref OB_USER_IWDG_STDBY or @ref OB_USER_WWDG_SW or @ref OB_USER_nBOOT1 or + * @arg @ref OB_USER_SRAM2_PE or @ref OB_USER_SRAM_RST or @ref OB_USER_nSWBOOT0 or + * @arg @ref OB_USER_nBOOT0 or @ref OB_USER_BOOT_LOCK or @ref OB_USER_BOOT_LOCK or @ref OB_USER_ALL + * @param UserConfig The FLASH User Option Bytes values. + * This parameter can be a combination of all the following values: + * @arg @ref OB_BOR_LEVEL_0 or @ref OB_BOR_LEVEL_1 or ... or @ref OB_BOR_LEVEL_4 + * @arg @ref OB_STOP_RST or @ref OB_STOP_NORST + * @arg @ref OB_STANDBY_RST or @ref OB_STANDBY_NORST + * @arg @ref OB_SHUTDOWN_RST or @ref OB_SHUTDOWN_NORST + * @arg @ref OB_IWDG_SW or @ref OB_IWDG_HW + * @arg @ref OB_IWDG_STOP_FREEZE or @ref OB_IWDG_STOP_RUN + * @arg @ref OB_IWDG_STDBY_FREEZE or @ref OB_IWDG_STDBY_RUN + * @arg @ref OB_WWDG_SW or @ref OB_WWDG_HW + * @arg @ref OB_BOOT1_RESET or @ref OB_BOOT1_SET + * @arg @ref OB_SRAM2_PARITY_ENABLE or @ref OB_SRAM2_PARITY_DISABLE + * @arg @ref OB_SRAM_RST_ERASE or @ref OB_SRAM_RST_NOT_ERASE + * @arg @ref OB_BOOT0_FROM_OB or @ref OB_BOOT0_FROM_PIN + * @arg @ref OB_BOOT0_RESET or @ref OB_BOOT0_SET + * @arg @ref OB_BOOT_LOCK_DISABLE or @ref OB_BOOT_LOCK_ENABLE + * @arg @ref OB_C2BOOT_LOCK_DISABLE or @ref OB_C2BOOT_LOCK_ENABLE + * @param RDPLevel: specifies the read protection level. + * This parameter can be one of the following values: + * @arg @ref OB_RDP_LEVEL_0 No protection + * @arg @ref OB_RDP_LEVEL_1 Read protection of the memory + * @arg @ref OB_RDP_LEVEL_2 Full chip protection + * @retval None + */ +#else +/** + * @brief Set user & RDP configuration + * @note !!! Warning : When enabling OB_RDP level 2 it's no more possible + * to go back to level 1 or 0 !!! + * @param UserType The FLASH User Option Bytes to be modified + * This parameter can be a combination of all the following values: + * @arg @ref OB_USER_BOR_LEV or @ref OB_USER_nRST_STOP or @ref OB_USER_nRST_STDBY or + * @arg @ref OB_USER_nRST_SHDW or @ref OB_USER_IWDG_SW or @ref OB_USER_IWDG_STOP or + * @arg @ref OB_USER_IWDG_STDBY or @ref OB_USER_WWDG_SW or @ref OB_USER_nBOOT1 or + * @arg @ref OB_USER_SRAM2_PE or @ref OB_USER_SRAM_RST or @ref OB_USER_nSWBOOT0 or + * @arg @ref OB_USER_nBOOT0 or @ref OB_USER_BOOT_LOCK or @ref OB_USER_BOOT_LOCK or @ref OB_USER_ALL + * @param UserConfig The FLASH User Option Bytes values. + * This parameter can be a combination of all the following values: + * @arg @ref OB_BOR_LEVEL_0 or @ref OB_BOR_LEVEL_1 or ... or @ref OB_BOR_LEVEL_4 + * @arg @ref OB_STOP_RST or @ref OB_STOP_NORST + * @arg @ref OB_STANDBY_RST or @ref OB_STANDBY_NORST + * @arg @ref OB_SHUTDOWN_RST or @ref OB_SHUTDOWN_NORST + * @arg @ref OB_IWDG_SW or @ref OB_IWDG_HW + * @arg @ref OB_IWDG_STOP_FREEZE or @ref OB_IWDG_STOP_RUN + * @arg @ref OB_IWDG_STDBY_FREEZE or @ref OB_IWDG_STDBY_RUN + * @arg @ref OB_WWDG_SW or @ref OB_WWDG_HW + * @arg @ref OB_BOOT1_RESET or @ref OB_BOOT1_SET + * @arg @ref OB_SRAM2_PARITY_ENABLE or @ref OB_SRAM2_PARITY_DISABLE + * @arg @ref OB_SRAM_RST_ERASE or @ref OB_SRAM_RST_NOT_ERASE + * @arg @ref OB_BOOT0_FROM_OB or @ref OB_BOOT0_FROM_PIN + * @arg @ref OB_BOOT0_RESET or @ref OB_BOOT0_SET + * @arg @ref OB_BOOT_LOCK_DISABLE or @ref OB_BOOT_LOCK_ENABLE + * @param RDPLevel: specifies the read protection level. + * This parameter can be one of the following values: + * @arg @ref OB_RDP_LEVEL_0 No protection + * @arg @ref OB_RDP_LEVEL_1 Read protection of the memory + * @arg @ref OB_RDP_LEVEL_2 Full chip protection + * @retval None + */ +#endif +static void FLASH_OB_OptrConfig(uint32_t UserType, uint32_t UserConfig, uint32_t RDPLevel) +{ + uint32_t optr; + + /* Check the parameters */ + assert_param(IS_OB_USER_TYPE(UserType)); + assert_param(IS_OB_USER_CONFIG(UserType, UserConfig)); + assert_param(IS_OB_RDP_LEVEL(RDPLevel)); + + /* Configure the RDP level in the option bytes register */ + optr = FLASH->OPTR; + optr &= ~(UserType | FLASH_OPTR_RDP); + FLASH->OPTR = (optr | UserConfig | RDPLevel); +} + +/** + * @brief Configure the Zone 1A Proprietary code readout protection of the desired addresses, + * and erase configuration on RDP regression. + * @note To configure the PCROP options, the option lock bit OPTLOCK must be + * cleared with the call of the @ref HAL_FLASH_OB_Unlock() function. + * @note To validate the PCROP options, the option bytes must be reloaded + * through the call of the @ref HAL_FLASH_OB_Launch() function. + * @param PCROPConfig: specifies the erase configuration (OB_PCROP_RDP_NOT_ERASE or OB_PCROP_RDP_ERASE) + * on RDP level 1 regression. + * @param PCROP1AStartAddr Specifies the Zone 1A Start address of the Proprietary code readout protection + * This parameter can be an address between begin and end of the flash + * @param PCROP1AEndAddr Specifies the Zone 1A end address of the Proprietary code readout protection + * This parameter can be an address between PCROP1AStartAddr and end of the flash + * @retval None + */ +static void FLASH_OB_PCROP1AConfig(uint32_t PCROPConfig, uint32_t PCROP1AStartAddr, uint32_t PCROP1AEndAddr) +{ + uint32_t startoffset; + uint32_t endoffset; + uint32_t pcrop1aend; + + /* Check the parameters */ + assert_param(IS_OB_PCROP_CONFIG(PCROPConfig)); + assert_param(IS_FLASH_MAIN_MEM_ADDRESS(PCROP1AStartAddr)); + assert_param(IS_FLASH_MAIN_MEM_ADDRESS(PCROP1AEndAddr)); + + /* get pcrop 1A end register */ + pcrop1aend = FLASH->PCROP1AER; + + /* Configure the Proprietary code readout protection offset */ + if ((PCROPConfig & OB_PCROP_ZONE_A) != 0U) + { + /* Compute offset depending on pcrop granularity */ + startoffset = ((PCROP1AStartAddr - FLASH_BASE) >> FLASH_PCROP_GRANULARITY_OFFSET); /* 2K pages */ + endoffset = ((PCROP1AEndAddr - FLASH_BASE) >> FLASH_PCROP_GRANULARITY_OFFSET); /* 2K pages */ + + /* Set Zone A start offset */ + WRITE_REG(FLASH->PCROP1ASR, startoffset); + + /* Set Zone A end offset */ + pcrop1aend &= ~FLASH_PCROP1AER_PCROP1A_END; + pcrop1aend |= endoffset; + } + + /* Set RDP erase protection if needed. This bit is only set & will be reset by mass erase */ + if ((PCROPConfig & OB_PCROP_RDP_ERASE) != 0U) + { + pcrop1aend |= FLASH_PCROP1AER_PCROP_RDP; + } + + /* set 1A End register */ + WRITE_REG(FLASH->PCROP1AER, pcrop1aend); +} + +/** + * @brief Configure the Zone 1B Proprietary code readout protection of the desired addresses. + * @note To configure the PCROP options, the option lock bit OPTLOCK must be + * cleared with the call of the @ref HAL_FLASH_OB_Unlock() function. + * @note To validate the PCROP options, the option bytes must be reloaded + * through the call of the @ref HAL_FLASH_OB_Launch() function. + * @param PCROP1BStartAddr Specifies the Zone 1B Start address of the Proprietary code readout protection + * This parameter can be an address between begin and end of the flash + * @param PCROP1BEndAddr Specifies the Zone 1B end address of the Proprietary code readout protection + * This parameter can be an address between PCROP1BStartAddr and end of the flash + * @retval None + */ +static void FLASH_OB_PCROP1BConfig(uint32_t PCROP1BStartAddr, uint32_t PCROP1BEndAddr) +{ + uint32_t startoffset; + uint32_t endoffset; + + /* Check the parameters */ + assert_param(IS_FLASH_MAIN_MEM_ADDRESS(PCROP1BStartAddr)); + assert_param(IS_FLASH_MAIN_MEM_ADDRESS(PCROP1BEndAddr)); + + /* Compute offset depending on pcrop granularity */ + startoffset = ((PCROP1BStartAddr - FLASH_BASE) >> FLASH_PCROP_GRANULARITY_OFFSET); /* 2K pages */ + endoffset = ((PCROP1BEndAddr - FLASH_BASE) >> FLASH_PCROP_GRANULARITY_OFFSET); /* 2K pages */ + + /* Configure the Proprietary code readout protection start address */ + WRITE_REG(FLASH->PCROP1BSR, startoffset); + + /* Configure the Proprietary code readout protection end address */ + WRITE_REG(FLASH->PCROP1BER, endoffset); +} + +#if defined(DUAL_CORE) +/** + * @brief Program the FLASH IPCC data buffer address. + * @note To configure the extra user option bytes, the option lock bit OPTLOCK must + * be cleared with the call of the @ref HAL_FLASH_OB_Unlock() function. + * @note To validate the extra user option bytes, the option bytes must be reloaded + * through the call of the @ref HAL_FLASH_OB_Launch() function. + * @param IPCCDataBufAddr IPCC data buffer start address area in SRAM1 or SRAM2 + * This parameter must be the double-word aligned + * @retval None + */ +static void FLASH_OB_IPCCBufferAddrConfig(uint32_t IPCCDataBufAddr) +{ + assert_param(IS_OB_IPCC_BUF_ADDR(IPCCDataBufAddr)); + + /* Configure the option bytes register */ + WRITE_REG(FLASH->IPCCBR, (uint32_t)((IPCCDataBufAddr - SRAM1_BASE) >> 4)); +} + +/** + * @brief Configure the secure start address of the different memories, + * the secure mode, the CPU2 Secure Boot reset vector and the CPU2 debug access + * @note To configure the PCROP options, the option lock bit OPTLOCK must be + * cleared with the call of the @ref HAL_FLASH_OB_Unlock() function. + * @param pOBParam Pointer to an @ref FLASH_OBProgramInitTypeDef structure that + * contains the configuration information for the programming + * @retval void + */ +static void FLASH_OB_SecureConfig(FLASH_OBProgramInitTypeDef *pOBParam) +{ + uint32_t sfr_reg_val = READ_REG(FLASH->SFR); + uint32_t srrvr_reg_val = READ_REG(FLASH->SRRVR); + + if ((pOBParam->OptionType & OPTIONBYTE_SECURE_MODE) != 0U) + { + assert_param(IS_OB_SFSA_START_ADDR(pOBParam->SecureFlashStartAddr)); + assert_param(IS_OB_SBRSA_START_ADDR(pOBParam->SecureSRAM2StartAddr)); + assert_param(IS_OB_SNBRSA_START_ADDR(pOBParam->SecureSRAM1StartAddr)); + assert_param(IS_OB_HDPSA_START_ADDR(pOBParam->HideProtectionStartAddr)); + assert_param(IS_OB_SECURE_MODE(pOBParam->SecureMode)); + + /* Configure SFR register content with start FLASH PAGE index to secure and start FLASH PAGE index for hide protection area */ + MODIFY_REG(sfr_reg_val, (FLASH_SFR_SFSA | FLASH_SFR_HDPSA), \ + ((((pOBParam->SecureFlashStartAddr - FLASH_BASE) / FLASH_PAGE_SIZE) << FLASH_SFR_SFSA_Pos) | \ + (((pOBParam->HideProtectionStartAddr - FLASH_BASE) / FLASH_PAGE_SIZE) << FLASH_SFR_HDPSA_Pos))); + + /* Configure SRRVR register */ + MODIFY_REG(srrvr_reg_val, (FLASH_SRRVR_SBRSA | FLASH_SRRVR_SNBRSA), \ + (((((pOBParam->SecureSRAM2StartAddr - SRAM2_BASE) >> SRAM_SECURE_PAGE_GRANULARITY_OFFSET) << FLASH_SRRVR_SBRSA_Pos)) | \ + ((((pOBParam->SecureSRAM1StartAddr - SRAM1_BASE) >> SRAM_SECURE_PAGE_GRANULARITY_OFFSET) << FLASH_SRRVR_SNBRSA_Pos)))); + + /* If Full System Secure mode is requested, clear all the corresponding bit */ + /* Else set the corresponding bit */ + if (pOBParam->SecureMode == OB_SECURE_SYSTEM_AND_ALL_AREAS_ENABLE) + { + CLEAR_BIT(sfr_reg_val, (FLASH_SFR_FSD | FLASH_SFR_HDPAD)); + CLEAR_BIT(srrvr_reg_val, (FLASH_SRRVR_BRSD | FLASH_SRRVR_NBRSD)); + } + else if (pOBParam->SecureMode == OB_SECURE_SYSTEM_AND_ALL_AREAS_DISABLE) + { + SET_BIT(sfr_reg_val, (FLASH_SFR_FSD | FLASH_SFR_HDPAD)); + SET_BIT(srrvr_reg_val, (FLASH_SRRVR_BRSD | FLASH_SRRVR_NBRSD)); + } + else /* Enable Secure Area bit per bit */ + { + /* Set Flash Area in secure if requested */ + FLASH_OB_ConfigSecureMode(pOBParam->SecureMode, &sfr_reg_val, FLASH_SFR_FSD, OB_SECURE_SYSTEM_AND_FLASH_ENABLE); + + /* Set Hide Protection Area in secure if requested */ + FLASH_OB_ConfigSecureMode(pOBParam->SecureMode, &sfr_reg_val, FLASH_SFR_HDPAD, OB_SECURE_HIDE_PROTECTION_ENABLE); + + /* Set SRAM1 Area in secure if requested */ + FLASH_OB_ConfigSecureMode(pOBParam->SecureMode, &srrvr_reg_val, FLASH_SRRVR_NBRSD, OB_SECURE_SRAM1_ENABLE); + + /* Set SRAM2 Area in secure if requested */ + FLASH_OB_ConfigSecureMode(pOBParam->SecureMode, &srrvr_reg_val, FLASH_SRRVR_BRSD, OB_SECURE_SRAM2_ENABLE); + } + } + + /* Boot vector */ + if ((pOBParam->OptionType & OPTIONBYTE_C2_BOOT_VECT) != 0U) + { + /* Check the parameters */ + assert_param(IS_OB_BOOT_VECTOR_ADDR(pOBParam->C2SecureBootVectAddr)); + assert_param(IS_OB_BOOT_REGION(pOBParam->C2BootRegion)); + + /* Set the boot vector */ + if (pOBParam->C2BootRegion == OB_C2_BOOT_FROM_FLASH) + { + MODIFY_REG(srrvr_reg_val, (FLASH_SRRVR_SBRV | FLASH_SRRVR_C2OPT), + (((pOBParam->C2SecureBootVectAddr - FLASH_BASE) >> 2) | pOBParam->C2BootRegion)); + } + else + { + MODIFY_REG(srrvr_reg_val, (FLASH_SRRVR_SBRV | FLASH_SRRVR_C2OPT), + (((pOBParam->C2SecureBootVectAddr - SRAM1_BASE) >> 2) | pOBParam->C2BootRegion)); + } + } + + /* CPU2 Debug Access */ + if ((pOBParam->OptionType & OPTIONBYTE_C2_DEBUG_ACCESS) != 0U) + { + /* Check the parameters */ + assert_param(IS_OB_C2_DEBUG_MODE(pOBParam->C2DebugAccessMode)); + + /* Set the CPU2 Debug Access */ + MODIFY_REG(sfr_reg_val, FLASH_SFR_DDS, (uint32_t)pOBParam->C2DebugAccessMode); + } + + /* Sub-GHz radio SPI Access */ + if ((pOBParam->OptionType & OPTIONBYTE_SUBGHZSPI_SECURE_ACCESS) != 0U) + { + /* Check the parameters */ + assert_param(IS_OB_SUBGHZSPI_SECURE_ACCESS(pOBParam->SUBGHZSPISecureAccess)); + + /* Set the Sub-GHz radio SPI Secure Access */ + MODIFY_REG(sfr_reg_val, FLASH_SFR_SUBGHZSPISD, (uint32_t)pOBParam->SUBGHZSPISecureAccess); + } + + /* Update Flash registers */ + WRITE_REG(FLASH->SFR, sfr_reg_val); + WRITE_REG(FLASH->SRRVR, srrvr_reg_val); +} +#endif /* DUAL_CORE */ + +/** + * @brief Return the FLASH Write Protection Option Bytes value. + * @param[in] WRPArea Specifies the area to be returned. + * This parameter can be one of the following values: + * @arg @ref OB_WRPAREA_BANK1_AREAA Flash Bank 1 Area A + * @arg @ref OB_WRPAREA_BANK1_AREAB Flash Bank 1 Area B + * @param[out] WRPStartOffset Specifies the address where to copied the start page + * of the write protected area + * @param[out] WRDPEndOffset Specifies the address where to copied the end page of + * the write protected area + * @retval None + */ +static void FLASH_OB_GetWRP(uint32_t WRPArea, uint32_t *WRPStartOffset, uint32_t *WRDPEndOffset) +{ + /* Check the parameters */ + assert_param(IS_OB_WRPAREA(WRPArea)); + + /* Get the configuration of the write protected area */ + if (WRPArea == OB_WRPAREA_BANK1_AREAA) + { + *WRPStartOffset = READ_BIT(FLASH->WRP1AR, FLASH_WRP1AR_WRP1A_STRT); + *WRDPEndOffset = (READ_BIT(FLASH->WRP1AR, FLASH_WRP1AR_WRP1A_END) >> FLASH_WRP1AR_WRP1A_END_Pos); + } + else /* OB_WRPAREA_BANK1_AREAB */ + { + *WRPStartOffset = READ_BIT(FLASH->WRP1BR, FLASH_WRP1BR_WRP1B_STRT); + *WRDPEndOffset = (READ_BIT(FLASH->WRP1BR, FLASH_WRP1BR_WRP1B_END) >> FLASH_WRP1BR_WRP1B_END_Pos); + } +} + +/** + * @brief Return the FLASH Read Protection level. + * @retval FLASH ReadOut Protection Status: + * This return value can be one of the following values: + * @arg @ref OB_RDP_LEVEL_0 No protection + * @arg @ref OB_RDP_LEVEL_1 Read protection of the memory + * @arg @ref OB_RDP_LEVEL_2 Full chip protection + */ +static uint32_t FLASH_OB_GetRDP(void) +{ + uint32_t rdplvl = READ_BIT(FLASH->OPTR, FLASH_OPTR_RDP); + + if ((rdplvl != OB_RDP_LEVEL_0) && (rdplvl != OB_RDP_LEVEL_2)) + { + return (OB_RDP_LEVEL_1); + } + else + { + return rdplvl; + } +} + +#if defined(DUAL_CORE) /* Comment duplicated for Document generation */ +/** + * @brief Return the FLASH User Option Byte value. + * @retval This return value can be a combination of all the following values: + * @arg @ref OB_BOR_LEVEL_0 or @ref OB_BOR_LEVEL_1 or ... or @ref OB_BOR_LEVEL_4 + * @arg @ref OB_STOP_RST or @ref OB_STOP_RST + * @arg @ref OB_STANDBY_RST or @ref OB_STANDBY_NORST + * @arg @ref OB_SHUTDOWN_RST or @ref OB_SHUTDOWN_NORST + * @arg @ref OB_IWDG_SW or @ref OB_IWDG_HW + * @arg @ref OB_IWDG_STOP_FREEZE or @ref OB_IWDG_STOP_RUN + * @arg @ref OB_IWDG_STDBY_FREEZE or @ref OB_IWDG_STDBY_RUN + * @arg @ref OB_WWDG_SW or @ref OB_WWDG_HW + * @arg @ref OB_BOOT1_RESET or @ref OB_BOOT1_SET + * @arg @ref OB_SRAM2_PARITY_ENABLE or @ref OB_SRAM2_PARITY_DISABLE + * @arg @ref OB_SRAM_RST_ERASE or @ref OB_SRAM_RST_NOT_ERASE + * @arg @ref OB_BOOT0_FROM_OB or @ref OB_BOOT0_FROM_PIN + * @arg @ref OB_BOOT0_RESET or @ref OB_BOOT0_SET + * @arg @ref OB_BOOT_LOCK_DISABLE or @ref OB_BOOT_LOCK_ENABLE + * @arg @ref OB_C2BOOT_LOCK_DISABLE or @ref OB_C2BOOT_LOCK_ENABLE + */ +#else +/** + * @brief Return the FLASH User Option Byte value. + * @retval This return value can be a combination of all the following values: + * @arg @ref OB_BOR_LEVEL_0 or @ref OB_BOR_LEVEL_1 or ... or @ref OB_BOR_LEVEL_4 + * @arg @ref OB_STOP_RST or @ref OB_STOP_RST + * @arg @ref OB_STANDBY_RST or @ref OB_STANDBY_NORST + * @arg @ref OB_SHUTDOWN_RST or @ref OB_SHUTDOWN_NORST + * @arg @ref OB_IWDG_SW or @ref OB_IWDG_HW + * @arg @ref OB_IWDG_STOP_FREEZE or @ref OB_IWDG_STOP_RUN + * @arg @ref OB_IWDG_STDBY_FREEZE or @ref OB_IWDG_STDBY_RUN + * @arg @ref OB_WWDG_SW or @ref OB_WWDG_HW + * @arg @ref OB_BOOT1_RESET or @ref OB_BOOT1_SET + * @arg @ref OB_SRAM2_PARITY_ENABLE or @ref OB_SRAM2_PARITY_DISABLE + * @arg @ref OB_SRAM_RST_ERASE or @ref OB_SRAM_RST_NOT_ERASE + * @arg @ref OB_BOOT0_FROM_OB or @ref OB_BOOT0_FROM_PIN + * @arg @ref OB_BOOT0_RESET or @ref OB_BOOT0_SET + * @arg @ref OB_BOOT_LOCK_DISABLE or @ref OB_BOOT_LOCK_ENABLE + */ +#endif +static uint32_t FLASH_OB_GetUser(void) +{ + uint32_t user_config = (READ_REG(FLASH->OPTR) & OB_USER_ALL); + CLEAR_BIT(user_config, (FLASH_OPTR_RDP | FLASH_OPTR_ESE)); + + return user_config; +} + +/** + * @brief Return the FLASH Write Protection Option Bytes value. + * @param PCROPConfig [out] Specifies the address where to copied the configuration of PCROP_RDP option + * @param PCROP1AStartAddr [out] Specifies the address where to copied the start address + * of the Zone 1A Proprietary code readout protection + * @param PCROP1AEndAddr [out] Specifies the address where to copied the end address of + * the Zone 1A Proprietary code readout protection + * @param PCROP1BStartAddr [out] Specifies the address where to copied the start address + * of the Zone 1B Proprietary code readout protection + * @param PCROP1BEndAddr [out] Specifies the address where to copied the end address of + * the Zone 1B Proprietary code readout protection + * @retval None + */ +static void FLASH_OB_GetPCROP(uint32_t *PCROPConfig, uint32_t *PCROP1AStartAddr, uint32_t *PCROP1AEndAddr, + uint32_t *PCROP1BStartAddr, uint32_t *PCROP1BEndAddr) +{ + uint32_t pcrop; + + pcrop = (READ_BIT(FLASH->PCROP1BSR, FLASH_PCROP1BSR_PCROP1B_STRT)); + *PCROP1BStartAddr = ((pcrop << FLASH_PCROP_GRANULARITY_OFFSET) + FLASH_BASE); + + pcrop = (READ_BIT(FLASH->PCROP1BER, FLASH_PCROP1BER_PCROP1B_END)); + *PCROP1BEndAddr = ((pcrop << FLASH_PCROP_GRANULARITY_OFFSET) + FLASH_BASE); + + pcrop = (READ_BIT(FLASH->PCROP1ASR, FLASH_PCROP1ASR_PCROP1A_STRT)); + *PCROP1AStartAddr = ((pcrop << FLASH_PCROP_GRANULARITY_OFFSET) + FLASH_BASE); + + pcrop = (READ_BIT(FLASH->PCROP1AER, FLASH_PCROP1AER_PCROP1A_END)); + *PCROP1AEndAddr = ((pcrop << FLASH_PCROP_GRANULARITY_OFFSET) + FLASH_BASE); + + *PCROPConfig = (READ_REG(FLASH->PCROP1AER) & FLASH_PCROP1AER_PCROP_RDP); +} + +#if defined(DUAL_CORE) +/** + * @brief Return the FLASH IPCC data buffer base address Option Byte value. + * @retval Returned value is the address where to copied the IPCC data buffer address. + * Value return between Min_Data = 0x0 and Max_Data = 0x3FFF + * This value correspond to the first double-word of the IPCC mailbox data buffer area + * in SRAM starting from 0x20000000 (SRAM1 start address to SRAM2 end address). + */ +static uint32_t FLASH_OB_GetIPCCBufferAddr(void) +{ + return (uint32_t)((READ_BIT(FLASH->IPCCBR, FLASH_IPCCBR_IPCCDBA) << 4) + SRAM1_BASE); +} + +/** + * @brief Return the Secure Flash start address, Secure Hide Protection Area start address, Secure Backup SRAM2 start address, + * Secure non-Backup SRAM1 start address and the SecureMode + * @param SecureFlashStartAddr Specifies the address where to copied the Secure Flash start address + * @param HideProtectionStartAddr Specifies the address where to copied the Secure Hide Protection Area start address + * @param SecureSRAM2StartAddr Specifies the address where to copied the Secure Backup SRAM2 start address + * @param SecureSRAM1StartAddr Specifies the address where to copied the Secure non-Backup SRAM1 start address + * @param SecureMode Specifies the Secure area enabled or disabled. + * This return value can be one of the following values: + * @arg @ref OB_SECURE_SYSTEM_AND_ALL_AREAS_DISABLE : All System Security disabled + * @arg @ref OB_SECURE_SYSTEM_AND_FLASH_ENABLE : Flash Security enabled + * @arg @ref OB_SECURE_HIDE_PROTECTION_ENABLE : Hide Protection Security enabled + * @arg @ref OB_SECURE_SRAM1_ENABLE : SRAM1 Security enabled + * @arg @ref OB_SECURE_SRAM2_ENABLE : SRAM2 Security enabled + * @arg @ref OB_SECURE_SYSTEM_AND_FLASH_DISABLE : Flash Security disabled + * @arg @ref OB_SECURE_HIDE_PROTECTION_DISABLE : Hide Protection Security disabled + * @arg @ref OB_SECURE_SRAM1_DISABLE : SRAM1 Security disabled + * @arg @ref OB_SECURE_SRAM2_DISABLE : SRAM2 Security disabled + * @arg @ref OB_SECURE_SYSTEM_AND_ALL_AREAS_ENABLE : All System Security enabled + * @retval None + */ +static void FLASH_OB_GetSecureMemoryConfig(uint32_t *SecureFlashStartAddr, uint32_t *HideProtectionStartAddr, + uint32_t *SecureSRAM2StartAddr, uint32_t *SecureSRAM1StartAddr, uint32_t *SecureMode) +{ + uint32_t sfr_reg_val = READ_REG(FLASH->SFR); + uint32_t srrvr_reg_val = READ_REG(FLASH->SRRVR); + + /* Get Secure Flash start address */ + uint32_t user_config = (READ_BIT(sfr_reg_val, FLASH_SFR_SFSA) >> FLASH_SFR_SFSA_Pos); + + *SecureFlashStartAddr = ((user_config * FLASH_PAGE_SIZE) + FLASH_BASE); + + /* Get Hide Protection Area start address */ + user_config = (READ_BIT(sfr_reg_val, FLASH_SFR_HDPSA) >> FLASH_SFR_HDPSA_Pos); + + *HideProtectionStartAddr = ((user_config * FLASH_PAGE_SIZE) + FLASH_BASE); + + /* Get Secure SRAM2 start address */ + user_config = (READ_BIT(srrvr_reg_val, FLASH_SRRVR_SBRSA) >> FLASH_SRRVR_SBRSA_Pos); + + *SecureSRAM2StartAddr = ((user_config << SRAM_SECURE_PAGE_GRANULARITY_OFFSET) + SRAM2_BASE); + + /* Get Secure SRAM1 start address */ + user_config = (READ_BIT(srrvr_reg_val, FLASH_SRRVR_SNBRSA) >> FLASH_SRRVR_SNBRSA_Pos); + + *SecureSRAM1StartAddr = ((user_config << SRAM_SECURE_PAGE_GRANULARITY_OFFSET) + SRAM1_BASE); + + /* Get Secure Area mode */ + *SecureMode = (FLASH_OB_GetSecureMode(sfr_reg_val, FLASH_SFR_FSD, OB_SECURE_SYSTEM_AND_FLASH_ENABLE, OB_SECURE_SYSTEM_AND_FLASH_DISABLE) | \ + FLASH_OB_GetSecureMode(sfr_reg_val, FLASH_SFR_HDPAD, OB_SECURE_HIDE_PROTECTION_ENABLE, + OB_SECURE_HIDE_PROTECTION_DISABLE) | \ + FLASH_OB_GetSecureMode(srrvr_reg_val, FLASH_SRRVR_NBRSD, OB_SECURE_SRAM1_ENABLE, + OB_SECURE_SRAM1_DISABLE) | \ + FLASH_OB_GetSecureMode(srrvr_reg_val, FLASH_SRRVR_BRSD, OB_SECURE_SRAM2_ENABLE, OB_SECURE_SRAM2_DISABLE)); +} + +/** + * @brief Return the CPU2 Secure Boot reset vector address and the CPU2 Secure Boot Region + * @param C2BootResetVectAddr Specifies the address where to copied the CPU2 Secure Boot reset vector address + * @param C2BootResetRegion Specifies the Secure Boot reset memory region + * @retval None + */ +static void FLASH_OB_GetC2BootResetConfig(uint32_t *C2BootResetVectAddr, uint32_t *C2BootResetRegion) +{ + *C2BootResetRegion = (READ_BIT(FLASH->SRRVR, FLASH_SRRVR_C2OPT)); + + if (*C2BootResetRegion == OB_C2_BOOT_FROM_FLASH) + { + *C2BootResetVectAddr = (uint32_t)((READ_BIT(FLASH->SRRVR, FLASH_SRRVR_SBRV) << 2) + FLASH_BASE); + } + else + { + *C2BootResetVectAddr = (uint32_t)((READ_BIT(FLASH->SRRVR, FLASH_SRRVR_SBRV) << 2) + SRAM1_BASE); + } +} + +/** + * @brief Return the Sub-GHz radio SPI Secure Access mode + * @retval Returned value can be one of the following values: + * @arg @ref OB_SUBGHZSPI_SECURE_ACCESS_DISABLE : Sub-GHz radio SPI Secure access disabled + * @arg @ref OB_SUBGHZSPI_SECURE_ACCESS_ENABLE : Sub-GHz radio SPI Secure access enabled + */ +static uint32_t FLASH_OB_GetSUBGHZSPISecureAccess(void) +{ + return (READ_BIT(FLASH->SFR, FLASH_SFR_SUBGHZSPISD)); +} + +/** + * @brief Return the CPU2 Debug Access mode + * @retval Returned value can be one of the following values: + * @arg @ref OB_C2_DEBUG_ACCESS_DISABLE : CPU2 debug access disabled + * @arg @ref OB_C2_DEBUG_ACCESS_ENABLE : CPU2 debug access enabled + */ +static uint32_t FLASH_OB_GetC2DebugAccessMode(void) +{ + return (READ_BIT(FLASH->SFR, FLASH_SFR_DDS)); +} +#endif /* DUAL_CORE */ + +/** + * @brief Proceed the OB Write Operation. + * @retval HAL Status + */ +static HAL_StatusTypeDef FLASH_OB_ProceedWriteOperation(void) +{ + HAL_StatusTypeDef status; + + /* Verify that next operation can be proceed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + if (status == HAL_OK) + { + /* Set OPTSTRT Bit */ + SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + } + + return status; +} + +#if defined(DUAL_CORE) +/** + * @brief Update the security bit in a FLASH register. + * @param SecureMode Parameter to check as disabled or enabled + * @param Reg FLASH register to update + * @param Bit Bit in FLASH register to update + * @param ValueEnable Constant to check in comparison with SecureMode as enabled + * @retval None + */ +static void FLASH_OB_ConfigSecureMode(uint32_t SecureMode, uint32_t *Reg, uint32_t Bit, uint32_t ValueEnable) +{ + /* Check if SecureMode is requested */ + if ((SecureMode & ValueEnable) == ValueEnable) + { + CLEAR_BIT(*Reg, Bit); + } + else + { + SET_BIT(*Reg, Bit); + } +} + +/** + * @brief Get the security bit in a FLASH register. + * @param Reg FLASH register to check + * @param Bit Bit in FLASH register to check + * @param ValueEnable Constant to check in comparison with SecureMode as enabled + * @param ValueDisable Constant to check in comparison with SecureMode as disabled + * @retval SecureMode Specifies the Secure area enabled or disabled. + * This return value can be one of the following values: + * ValueEnable + * ValueDisable + * Null + */ +static uint32_t FLASH_OB_GetSecureMode(uint32_t Reg, uint32_t Bit, uint32_t ValueEnable, uint32_t ValueDisable) +{ + /* Return status of bit (set as enable, set as disable) */ + if (READ_BIT(Reg, Bit) == 0U) + { + return ValueEnable; + } + else + { + return ValueDisable; + } +} +#endif /* DUAL_CORE */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_FLASH_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ + diff --git a/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_gpio.c b/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_gpio.c new file mode 100644 index 0000000..d9ab50e --- /dev/null +++ b/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_gpio.c @@ -0,0 +1,569 @@ +/** + ****************************************************************************** + * @file stm32wlxx_hal_gpio.c + * @author MCD Application Team + * @brief GPIO HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the General Purpose Input/Output (GPIO) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + ****************************************************************************** + * @attention + * + * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### GPIO Peripheral features ##### + ============================================================================== + [..] + (+) Each port bit of the general-purpose I/O (GPIO) ports can be individually + configured by software in several modes: + (++) Input mode + (++) Analog mode + (++) Output mode + (++) Alternate function mode + (++) External interrupt/event lines + + (+) During and just after reset, the alternate functions and external interrupt + lines are not active and the I/O ports are configured in input floating mode. + + (+) All GPIO pins have weak internal pull-up and pull-down resistors, which can be + activated or not. + + (+) In Output or Alternate mode, each IO can be configured on open-drain or push-pull + type and the IO speed can be selected depending on the VDD value. + + (+) The microcontroller IO pins are connected to onboard peripherals/modules through a + multiplexer that allows only one peripheral alternate function (AF) connected + to an IO pin at a time. In this way, there can be no conflict between peripherals + sharing the same IO pin. + + (+) All ports have external interrupt/event capability. To use external interrupt + lines, the port must be configured in input mode. All available GPIO pins are + connected to the 16 external interrupt/event lines from EXTI0 to EXTI15. + + (+) The external interrupt/event controller consists of up to 28 edge detectors + (16 lines are connected to GPIO) for generating event/interrupt requests (each + input line can be independently configured to select the type (interrupt or event) + and the corresponding trigger event (rising or falling or both). Each line can + also be masked independently. + + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Enable the GPIO AHB clock using the following function: __HAL_RCC_GPIOx_CLK_ENABLE(). + + (#) Configure the GPIO pin(s) using HAL_GPIO_Init(). + (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure + (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef + structure. + (++) In case of Output or alternate function mode selection: the speed is + configured through "Speed" member from GPIO_InitTypeDef structure. + (++) In alternate mode is selection, the alternate function connected to the IO + is configured through "Alternate" member from GPIO_InitTypeDef structure. + (++) Analog mode is required when a pin is to be used as ADC channel + or DAC output. + (++) In case of external interrupt/event selection the "Mode" member from + GPIO_InitTypeDef structure select the type (interrupt or event) and + the corresponding trigger event (rising or falling or both). + + (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority + mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using + HAL_NVIC_EnableIRQ(). + + (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin(). + + (#) To set/reset the level of a pin configured in output mode use + HAL_GPIO_WritePin()/HAL_GPIO_TogglePin(). + + (#) To set the level of several pins and reset level of several other pins in + same cycle, use HAL_GPIO_WriteMultipleStatePin(). + + + (#) To lock pin configuration until next reset use HAL_GPIO_LockPin(). + + (#) During and just after reset, the alternate functions are not + active and the GPIO pins are configured in input floating mode (except JTAG + pins). + + (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose + (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has + priority over the GPIO function. + + (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as + general purpose PH0 and PH1, respectively, when the HSE oscillator is off. + The HSE has priority over the GPIO function. + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wlxx_hal.h" + +/** @addtogroup STM32WLxx_HAL_Driver + * @{ + */ + +/** @addtogroup GPIO + * @{ + */ + +#ifdef HAL_GPIO_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private defines ------------------------------------------------------------*/ +/** @addtogroup GPIO_Private_Constants GPIO Private Constants + * @{ + */ +#define GPIO_NUMBER (16U) +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup GPIO_Exported_Functions + * @{ + */ + +/** @addtogroup GPIO_Exported_Functions_Group1 + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the GPIOx peripheral according to the specified parameters in the GPIO_Init. + * @param GPIOx where x can be (A..H) to select the GPIO peripheral for STM32WLxx family + * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains + * the configuration information for the specified GPIO peripheral. + * @retval None + */ +void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, const GPIO_InitTypeDef *GPIO_Init) +{ + uint32_t position = 0x00u; + uint32_t iocurrent; + uint32_t temp; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); + assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); + assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); + + /* Configure the port pins */ + while (((GPIO_Init->Pin) >> position) != 0x00u) + { + /* Get current io position */ + iocurrent = (GPIO_Init->Pin) & (1uL << position); + + if (iocurrent != 0x00u) + { + /*--------------------- GPIO Mode Configuration ------------------------*/ + /* In case of Output or Alternate function mode selection */ + if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)) + { + /* Check the Speed parameter */ + assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); + /* Configure the IO Speed */ + temp = GPIOx->OSPEEDR; + temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U)); + temp |= (GPIO_Init->Speed << (position * 2U)); + GPIOx->OSPEEDR = temp; + + /* Configure the IO Output Type */ + temp = GPIOx->OTYPER; + temp &= ~(GPIO_OTYPER_OT0 << position) ; + temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position); + GPIOx->OTYPER = temp; + } + + /* Activate the Pull-up or Pull down resistor for the current IO */ + if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) + { + temp = GPIOx->PUPDR; + temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U)); + temp |= ((GPIO_Init->Pull) << (position * 2U)); + GPIOx->PUPDR = temp; + } + + /* In case of Alternate function mode selection */ + if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF) + { + /* Check the Alternate function parameters */ + assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); + assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); + + /* Configure Alternate function mapped with the current IO */ + temp = GPIOx->AFR[position >> 3U]; + temp &= ~(0xFU << ((position & 0x07U) * 4U)); + temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * 4U)); + GPIOx->AFR[position >> 3u] = temp; + } + + /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ + temp = GPIOx->MODER; + temp &= ~(GPIO_MODER_MODE0 << (position * 2U)); + temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U)); + GPIOx->MODER = temp; + + /*--------------------- EXTI Mode Configuration ------------------------*/ + /* Configure the External Interrupt or event for the current IO */ + if ((GPIO_Init->Mode & EXTI_MODE) != 0x00u) + { + temp = SYSCFG->EXTICR[position >> 2u]; + temp &= ~(0x07uL << (4U * (position & 0x03U))); + temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U))); + SYSCFG->EXTICR[position >> 2u] = temp; + + /* Clear Rising Falling edge configuration */ + temp = EXTI->RTSR1; + temp &= ~(iocurrent); + if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00u) + { + temp |= iocurrent; + } + EXTI->RTSR1 = temp; + + temp = EXTI->FTSR1; + temp &= ~(iocurrent); + if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00u) + { + temp |= iocurrent; + } + EXTI->FTSR1 = temp; + + /* Clear EXTI line configuration */ +#ifdef CORE_CM0PLUS + temp = EXTI->C2IMR1; +#else + temp = EXTI->IMR1; +#endif /* CORE_CM0PLUS */ + temp &= ~(iocurrent); + if ((GPIO_Init->Mode & EXTI_IT) != 0x00u) + { + temp |= iocurrent; + } +#ifdef CORE_CM0PLUS + EXTI->C2IMR1 = temp; +#else + EXTI->IMR1 = temp; +#endif /* CORE_CM0PLUS */ + +#ifdef CORE_CM0PLUS + temp = EXTI->C2EMR1; +#else + temp = EXTI->EMR1; +#endif /* CORE_CM0PLUS */ + temp &= ~(iocurrent); + if ((GPIO_Init->Mode & EXTI_EVT) != 0x00u) + { + temp |= iocurrent; + } +#ifdef CORE_CM0PLUS + EXTI->C2EMR1 = temp; +#else + EXTI->EMR1 = temp; +#endif /* CORE_CM0PLUS */ + } + } + + position++; + } +} + +/** + * @brief De-initialize the GPIOx peripheral registers to their default reset values. + * @param GPIOx where x can be (A..H) to select the GPIO peripheral for STM32WLxx family + * @param GPIO_Pin specifies the port bit to be written. + * This parameter can be any combination of GPIO_PIN_x where x can be (0..15). + * @retval None + */ +void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) +{ + uint32_t position = 0x00u; + uint32_t iocurrent; + uint32_t tmp; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + /* Configure the port pins */ + while ((GPIO_Pin >> position) != 0x00u) + { + /* Get current io position */ + iocurrent = (GPIO_Pin) & (1uL << position); + + if (iocurrent != 0x00u) + { + /*------------------------- EXTI Mode Configuration --------------------*/ + /* Clear the External Interrupt or Event for the current IO */ + + tmp = SYSCFG->EXTICR[position >> 2u]; + tmp &= (0x07uL << (4U * (position & 0x03U))); + if (tmp == (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U)))) + { + /* Clear EXTI line configuration */ +#ifdef CORE_CM0PLUS + EXTI->C2IMR1 &= ~(iocurrent); + EXTI->C2EMR1 &= ~(iocurrent); +#else + EXTI->IMR1 &= ~(iocurrent); + EXTI->EMR1 &= ~(iocurrent); +#endif /* CORE_CM0PLUS */ + + /* Clear Rising Falling edge configuration */ + EXTI->RTSR1 &= ~(iocurrent); + EXTI->FTSR1 &= ~(iocurrent); + + /* Clear EXTICR configuration */ + tmp = 0x07uL << (4u * (position & 0x03U)); + SYSCFG->EXTICR[position >> 2u] &= ~tmp; + } + + /*------------------------- GPIO Mode Configuration --------------------*/ + /* Configure IO in Analog Mode */ + GPIOx->MODER |= (GPIO_MODER_MODE0 << (position * 2U)); + + /* Configure the default Alternate Function in current IO */ + GPIOx->AFR[position >> 3U] &= ~(0xFU << ((position & 0x07U) * 4U)) ; + + /* Configure the default value for IO Speed */ + GPIOx->OSPEEDR &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U)); + + /* Configure the default value IO Output Type */ + GPIOx->OTYPER &= ~(GPIO_OTYPER_OT0 << position) ; + + /* Deactivate the Pull-up and Pull-down resistor for the current IO */ + GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPD0 << (position * 2U)); + } + + position++; + } +} + +/** + * @} + */ + +/** @addtogroup GPIO_Exported_Functions_Group2 + * @brief GPIO Read, Write, Toggle, Lock and EXTI management functions. + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Read the specified input port pin. + * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32WLxx family + * @param GPIO_Pin specifies the port bit to read. + * This parameter can be any combination of GPIO_PIN_x where x can be (0..15). + * @retval The input port pin value. + */ +GPIO_PinState HAL_GPIO_ReadPin(const GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + GPIO_PinState bitstatus; + + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + if ((GPIOx->IDR & GPIO_Pin) != 0x00u) + { + bitstatus = GPIO_PIN_SET; + } + else + { + bitstatus = GPIO_PIN_RESET; + } + return bitstatus; +} + +/** + * @brief Set or clear the selected data port bit. + * @note This function uses GPIOx_BSRR and GPIOx_BRR registers to allow atomic read/modify + * accesses. In this way, there is no risk of an IRQ occurring between + * the read and the modify access. + * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32WLxx family + * @param GPIO_Pin specifies the port bit to be written. + * This parameter can be any combination of GPIO_PIN_x where x can be (0..15). + * @param PinState specifies the value to be written to the selected bit. + * This parameter can be one of the GPIO_PinState enum values: + * @arg GPIO_PIN_RESET: to clear the port pin + * @arg GPIO_PIN_SET: to set the port pin + * @retval None + */ +void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) +{ + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + assert_param(IS_GPIO_PIN_ACTION(PinState)); + + if (PinState != GPIO_PIN_RESET) + { + GPIOx->BSRR = (uint32_t)GPIO_Pin; + } + else + { + GPIOx->BRR = (uint32_t)GPIO_Pin; + } +} + +/** + * @brief Set and clear several pins of a dedicated port in same cycle. + * @note This function uses GPIOx_BSRR and GPIOx_BRR registers to allow atomic read/modify + * accesses. + * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32WLxx family + * @param PinReset specifies the port bits to be reset + * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) or zero. + * @param PinSet specifies the port bits to be set + * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) or zero. + * @note Both PinReset and PinSet combinations shall not get any common bit, else + * assert would be triggered. + * @note At least one of the two parameters used to set or reset shall be different from zero. + * @retval None + */ +void HAL_GPIO_WriteMultipleStatePin(GPIO_TypeDef *GPIOx, uint16_t PinReset, uint16_t PinSet) +{ + uint32_t tmp; + + /* Check the parameters */ + /* Make sure at least one parameter is different from zero and that there is no common pin */ + assert_param(IS_GPIO_PIN((uint32_t)PinReset | (uint32_t)PinSet)); + assert_param(IS_GPIO_COMMON_PIN(PinReset, PinSet)); + + tmp = (((uint32_t)PinReset << 16) | PinSet); + GPIOx->BSRR = tmp; +} + +/** + * @brief Toggle the specified GPIO pin. + * @param GPIOx where x can be (A..H) to select the GPIO peripheral for STM32WLxx family + * @param GPIO_Pin specifies the pin to be toggled. + * This parameter can be any combination of GPIO_PIN_x where x can be (0..15). + * @retval None + */ +void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + uint32_t odr; + + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + /* get current Output Data Register value */ + odr = GPIOx->ODR; + + /* Set selected pins that were at low level, and reset ones that were high */ + GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin); +} + +/** + * @brief Lock GPIO Pins configuration registers. + * @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, + * GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH. + * @note The configuration of the locked GPIO pins can no longer be modified + * until the next reset. + * @param GPIOx where x can be (A..H) to select the GPIO peripheral for STM32WLxx family + * @param GPIO_Pin specifies the port bits to be locked. + * This parameter can be any combination of GPIO_PIN_x where x can be (0..15). + * @retval None + */ +HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + __IO uint32_t tmp = GPIO_LCKR_LCKK; + + /* Check the parameters */ + assert_param(IS_GPIO_LOCK_INSTANCE(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + /* Apply lock key write sequence */ + tmp |= GPIO_Pin; + /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */ + GPIOx->LCKR = tmp; + /* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */ + GPIOx->LCKR = GPIO_Pin; + /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */ + GPIOx->LCKR = tmp; + /* Read LCKK register. This read is mandatory to complete key lock sequence */ + tmp = GPIOx->LCKR; + + /* read again in order to confirm lock is active */ + if ((GPIOx->LCKR & GPIO_LCKR_LCKK) != 0x00u) + { + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Handle EXTI interrupt request. + * @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line. + * @retval None + */ +void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) +{ + /* EXTI line interrupt detected */ + if (__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != 0x00u) + { + __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin); + HAL_GPIO_EXTI_Callback(GPIO_Pin); + } +} + +/** + * @brief EXTI line detection callback. + * @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line. + * @retval None + */ +__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(GPIO_Pin); + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_GPIO_EXTI_Callback could be implemented in the user file + */ +} + +/** + * @} + */ + + +/** + * @} + */ + +#endif /* HAL_GPIO_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ diff --git a/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.c b/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.c new file mode 100644 index 0000000..ef05782 --- /dev/null +++ b/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.c @@ -0,0 +1,705 @@ +/** + ****************************************************************************** + * @file stm32wlxx_hal_pwr.c + * @author MCD Application Team + * @brief PWR HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Power Controller (PWR) peripheral: + * + Initialization/de-initialization functions + * + Peripheral Control functions + ****************************************************************************** + * @attention + * + * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wlxx_hal.h" + +/** @addtogroup STM32WLxx_HAL_Driver + * @{ + */ + +/** @addtogroup PWR + * @{ + */ + +#ifdef HAL_PWR_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ + +/** @addtogroup PWR_Private_Constants PWR Private Constants + * @{ + */ +/* Definitions of PWR registers reset value */ +#define PWR_CR1_RESET_VALUE (0x00000200) +#define PWR_CR2_RESET_VALUE (0x00000000) +#define PWR_CR3_RESET_VALUE (PWR_CR3_EIWUL) +#define PWR_CR4_RESET_VALUE (0x00000000) +#define PWR_CR5_RESET_VALUE (0x00000000) +#define PWR_PUCRA_RESET_VALUE (0x00000000) +#define PWR_PDCRA_RESET_VALUE (0x00000000) +#define PWR_PUCRB_RESET_VALUE (0x00000000) +#define PWR_PDCRB_RESET_VALUE (0x00000000) +#define PWR_PUCRC_RESET_VALUE (0x00000000) +#define PWR_PDCRC_RESET_VALUE (0x00000000) +#define PWR_PUCRH_RESET_VALUE (0x00000000) +#define PWR_PDCRH_RESET_VALUE (0x00000000) +#if defined(DUAL_CORE) +#define PWR_C2CR1_RESET_VALUE (PWR_C2CR1_LPMS_2 | PWR_C2CR1_LPMS_1 | PWR_C2CR1_LPMS_0) +#define PWR_C2CR3_RESET_VALUE (0x00000000) +#endif /* DUAL_CORE */ +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup PWR_Exported_Functions PWR Exported Functions + * @{ + */ + +/** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and de-initialization functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] + +@endverbatim + * @{ + */ + +/** + * @brief Deinitialize the HAL PWR peripheral registers to their default reset values. + * @retval None + */ +void HAL_PWR_DeInit(void) +{ + /* Apply reset values to all PWR registers */ + /* Note: Update of each register required since PWR global reset is not */ + /* available at RCC level on this STM32 series. */ + LL_PWR_WriteReg(CR1, PWR_CR1_RESET_VALUE); + LL_PWR_WriteReg(CR2, PWR_CR2_RESET_VALUE); + LL_PWR_WriteReg(CR3, PWR_CR3_RESET_VALUE); + LL_PWR_WriteReg(CR4, PWR_CR4_RESET_VALUE); + LL_PWR_WriteReg(CR5, PWR_CR5_RESET_VALUE); + LL_PWR_WriteReg(PUCRA, PWR_PUCRA_RESET_VALUE); + LL_PWR_WriteReg(PDCRA, PWR_PDCRA_RESET_VALUE); + LL_PWR_WriteReg(PUCRB, PWR_PUCRB_RESET_VALUE); + LL_PWR_WriteReg(PDCRB, PWR_PDCRB_RESET_VALUE); + LL_PWR_WriteReg(PUCRC, PWR_PUCRC_RESET_VALUE); + LL_PWR_WriteReg(PDCRC, PWR_PDCRC_RESET_VALUE); + LL_PWR_WriteReg(PUCRH, PWR_PUCRH_RESET_VALUE); + LL_PWR_WriteReg(PDCRH, PWR_PDCRH_RESET_VALUE); +#ifdef CORE_CM0PLUS + LL_PWR_WriteReg(C2CR1, PWR_C2CR1_RESET_VALUE); + LL_PWR_WriteReg(C2CR3, PWR_C2CR3_RESET_VALUE); +#endif /* CORE_CM0PLUS */ + + /* Clear all flags */ +#if defined(DUAL_CORE) + LL_PWR_WriteReg(SCR, + LL_PWR_SCR_CWUF + | LL_PWR_SCR_CWRFBUSYF + | LL_PWR_SCR_CWPVDF + | LL_PWR_SCR_CC2HF + ); +#else + LL_PWR_WriteReg(SCR, + LL_PWR_SCR_CWUF + | LL_PWR_SCR_CWRFBUSYF + | LL_PWR_SCR_CWPVDF + ); +#endif /* DUAL_CORE */ + +#ifdef CORE_CM0PLUS + LL_PWR_WriteReg(EXTSCR, LL_PWR_EXTSCR_C2CSSF); +#else + LL_PWR_WriteReg(EXTSCR, LL_PWR_EXTSCR_C1CSSF); +#endif /* CORE_CM0PLUS */ +} + + +/** + * @brief Enable access to the backup domain + * (RTC registers, RTC backup data registers). + * @note After reset, the backup domain is protected against + * possible unwanted write accesses. + * @note RTCSEL that sets the RTC clock source selection is in the RTC backup domain. + * In order to set or modify the RTC clock, the backup domain access must be + * disabled. + * @note LSEON bit that switches on and off the LSE crystal belongs as well to the + * backup domain. + * @retval None + */ +void HAL_PWR_EnableBkUpAccess(void) +{ + SET_BIT(PWR->CR1, PWR_CR1_DBP); +} + +/** + * @brief Disable access to the backup domain + * (RTC registers, RTC backup data registers). + * @retval None + */ +void HAL_PWR_DisableBkUpAccess(void) +{ + CLEAR_BIT(PWR->CR1, PWR_CR1_DBP); +} + +/** + * @} + */ + + +/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions + * @brief Low Power modes configuration functions + * +@verbatim + + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + + [..] + *** PVD configuration *** + ========================= + [..] + (+) The PVD is used to monitor the VDD power supply by comparing it to a + threshold selected by the PVD Level (PLS[2:0] bits in PWR_CR2 register). + (+) PVDO flag is available to indicate if VDD/VDDA is higher or lower + than the PVD threshold. This event is internally connected to the EXTI + line16 and can generate an interrupt if enabled. This is done through + __HAL_PVD_EXTI_ENABLE_IT() macro. + (+) The PVD is stopped in Standby mode. + + *** WakeUp pin configuration *** + ================================ + [..] + (+) WakeUp pins are used to wakeup the system from Standby mode or Shutdown mode. + The polarity of these pins can be set to configure event detection on high + level (rising edge) or low level (falling edge). + + *** Low Power modes configuration *** + ===================================== + [..] + The devices feature 8 low-power modes: + + (+) Low-power Run mode: core and peripherals are running, main regulator off, low power regulator on. + + (+) Sleep mode: Cortex-M4 core stopped, peripherals kept running, main and low power regulators on. + (+) Low-power Sleep mode: Cortex-M4 core stopped, peripherals kept running, main regulator off, low power regulator on. + + (+) Stop 0 mode: all clocks are stopped except LSI and LSE, main and low power regulators on. + (+) Stop 1 mode: all clocks are stopped except LSI and LSE, main regulator off, low power regulator on. + (+) Stop 2 mode: all clocks are stopped except LSI and LSE, main regulator off, low power regulator on, reduced set of waking up IPs compared to Stop 1 mode. + + (+) Standby mode with SRAM2: all clocks are stopped except LSI and LSE, SRAM2 content preserved, main regulator off, low power regulator on. + (+) Standby mode without SRAM2: all clocks are stopped except LSI and LSE, main and low power regulators off. + + (+) Shutdown mode: all clocks are stopped except LSE, main and low power regulators off. + + (+) Note: system power mode depends on each sub-system (CPU1, CPU2, radio) power modes. + Each CPU request to enter in a low-power mode will make system enter in the equivalent low-power mode + if all other sub-systems are aligned. + + *** Low-power run mode *** + ========================== + [..] + (+) Entry: (from main run mode) + (++) set LPR bit with HAL_PWREx_EnableLowPowerRunMode() API after having decreased the system clock below 2 MHz. + (+) Exit: + (++) clear LPR bit then wait for REGLP bit to be reset with HAL_PWREx_DisableLowPowerRunMode() API. Only + then can the system clock frequency be increased above 2 MHz. + + *** Sleep mode / Low-power sleep mode *** + ========================================= + [..] + (+) Entry: + The Sleep mode / Low-power Sleep mode is entered through HAL_PWR_EnterSLEEPMode() API + in specifying whether or not the regulator is forced to low-power mode and if exit is interrupt or event-triggered. + (++) PWR_MAINREGULATOR_ON: Sleep mode (regulator in main mode). + (++) PWR_LOWPOWERREGULATOR_ON: Low-power sleep (regulator in low power mode). + In the latter case, the system clock frequency must have been decreased below 2 MHz beforehand. + (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction + (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction + + (+) WFI Exit: + (++) Any peripheral interrupt acknowledged by the nested vectored interrupt + controller (NVIC) or any wake-up event. + + (+) WFE Exit: + (++) Any wake-up event such as an EXTI line configured in event mode. + + [..] When exiting the Low-power sleep mode by issuing an interrupt or a wakeup event, + the MCU is in Low-power Run mode. + + *** Stop 0, Stop 1 and Stop 2 modes *** + =============================== + [..] + (+) Entry: + The Stop 0, Stop 1 or Stop 2 modes are entered through the following API's: + (++) HAL_PWREx_EnterSTOP0Mode() for mode 0, HAL_PWREx_EnterSTOP1Mode() for mode 1, HAL_PWREx_EnterSTOP2Mode() for mode 2 + or for porting reasons HAL_PWR_EnterSTOPMode(). + + (+) Regulator setting (applicable to HAL_PWR_EnterSTOPMode() only): + (++) PWR_MAINREGULATOR_ON: Regulator in main mode (STOP0 mode) + (++) PWR_LOWPOWERREGULATOR_ON: Regulator in low-power mode (STOP1 mode) + (+) Exit (interrupt or event-triggered, specified when entering STOP mode): + (++) PWR_STOPENTRY_WFI: enter Stop mode with WFI instruction + (++) PWR_STOPENTRY_WFE: enter Stop mode with WFE instruction + (+) WFI Exit: + (++) Any EXTI Line (Internal or External) configured in Interrupt mode. + (++) Some specific communication peripherals (USART, LPUART, I2C) interrupts + when programmed in wakeup mode. + (+) WFE Exit: + (++) Any EXTI Line (Internal or External) configured in Event mode. + + [..] + When exiting Stop 0 and Stop 1 modes, the MCU is either in Run mode or in Low-power Run mode + depending on the LPR bit setting. + When exiting Stop 2 mode, the MCU is in Run mode. + + *** Standby mode *** + ==================== + [..] The Standby mode offers two options: + (+) option a) all clocks off except LSI and LSE, RRS bit set (keeps voltage regulator in low power mode). + SRAM and registers contents are lost except for the SRAM2 content, the RTC registers, RTC backup registers + and Standby circuitry. + (+) option b) all clocks off except LSI and LSE, RRS bit cleared (voltage regulator then disabled). + SRAM and register contents are lost except for the RTC registers, RTC backup registers + and Standby circuitry. + + (++) Entry: + (+++) The Standby mode is entered through HAL_PWR_EnterSTANDBYMode() API. + SRAM1 and register contents are lost except for registers in the Backup domain and + Standby circuitry. SRAM2 content can be preserved if the bit RRS is set in PWR_CR3 register. + To enable this feature, the user can resort to HAL_PWREx_EnableSRAMRetention() API + to set RRS bit. + (++) Exit: + (+++) WKUP pin rising edge, RTC alarm or wakeup, tamper event, time-stamp event, + external reset in NRST pin, IWDG reset. + [..] After waking up from Standby mode, program execution restarts in the same way as after a Reset. + + + *** Shutdown mode *** + ====================== + [..] + In Shutdown mode, + voltage regulator is disabled, all clocks are off except LSE, RRS bit is cleared. + SRAM and registers contents are lost except for backup domain registers. + (+) Entry: + The Shutdown mode is entered through HAL_PWREx_EnterSHUTDOWNMode() API. + (+) Exit: + (++) WKUP pin rising edge, RTC alarm or wakeup, tamper event, time-stamp event, + external reset in NRST pin. + [..] After waking up from Shutdown mode, program execution restarts in the same way as after a Reset. + + + *** Auto-wakeup (AWU) from low-power mode *** + ============================================= + [..] + The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC + Wakeup event, a tamper event or a time-stamp event, without depending on + an external interrupt (Auto-wakeup mode). + + (+) RTC auto-wakeup (AWU) from the Stop, Standby and Shutdown modes + + + (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to + configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function. + + (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it + is necessary to configure the RTC to detect the tamper or time stamp event using the + HAL_RTCEx_SetTimeStamp_IT() or HAL_RTCEx_SetTamper_IT() functions. + + (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to + configure the RTC to generate the RTC WakeUp event using the HAL_RTCEx_SetWakeUpTimer_IT() function. + +@endverbatim + * @{ + */ + +/** + * @brief Configure the voltage threshold detected by the Power Voltage Detector (PVD). + * @param sConfigPVD pointer to a PWR_PVDTypeDef structure that contains the PVD + * configuration information. + * @note Refer to the electrical characteristics of your device datasheet for + * more details about the voltage thresholds corresponding to each + * detection level. + * @note For devices dual core: if "sConfigPVD->Mode" is set to PVD_MODE_IT, + * wake-up target is set to wake-up the selected CPU. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_PWR_ConfigPVD(const PWR_PVDTypeDef *sConfigPVD) +{ + /* Check the parameters */ + assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel)); + assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode)); + + /* Set PLS bits according to PVDLevel value */ + MODIFY_REG(PWR->CR2, PWR_CR2_PLS, sConfigPVD->PVDLevel); + + /* Clear any previous config. Keep it clear if no event or IT mode is selected */ + + /* Note: On STM32WL series, power PVD event is not available on EXTI lines */ + /* (only interruption is available through EXTI line 16). */ + __HAL_PWR_PVD_EXTI_DISABLE_IT(); + __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); + __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); + + /* Configure interrupt mode */ + if ((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT) + { + __HAL_PWR_PVD_EXTI_ENABLE_IT(); + } + + /* Configure the edge */ + if ((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE) + { + __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); + } + + if ((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE) + { + __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); + } + + return HAL_OK; +} + +/** + * @brief Enable the Power Voltage Detector(PVD). + * @retval None + */ +void HAL_PWR_EnablePVD(void) +{ + /* Enable the power voltage detector */ + SET_BIT(PWR->CR2, PWR_CR2_PVDE); +} + +/** + * @brief Disable the Power Voltage Detector(PVD). + * @retval None + */ +void HAL_PWR_DisablePVD(void) +{ + /* Disable the power voltage detector */ + CLEAR_BIT(PWR->CR2, PWR_CR2_PVDE); +} + +/** + * @brief Enable the WakeUp PINx functionality. + * @param WakeUpPinPolarity Specifies which Wake-Up pin to enable. + * This parameter can be one of the following legacy values which set the default polarity + * i.e. detection on high level (rising edge): + * @arg PWR_WAKEUP_PIN1 Pin wake-up the system from Standby mode. + * @arg PWR_WAKEUP_PIN2 Pin wake-up the system from Standby mode. + * @arg PWR_WAKEUP_PIN3 Pin wake-up the system from Standby mode. + * or one of the following value where the user can explicitly specify the enabled pin and + * the chosen polarity: + * @arg @ref PWR_WAKEUP_PIN1_HIGH or @arg @ref PWR_WAKEUP_PIN1_LOW + * @arg @ref PWR_WAKEUP_PIN2_HIGH or @arg @ref PWR_WAKEUP_PIN2_LOW + * @arg @ref PWR_WAKEUP_PIN3_HIGH or @arg @ref PWR_WAKEUP_PIN3_LOW + * @note PWR_WAKEUP_PINx and PWR_WAKEUP_PINx_HIGH are equivalent. + * @retval None + */ +void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity) +{ + assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinPolarity)); + + /* Specifies the Wake-Up pin polarity for the event detection + (rising or falling edge) */ + MODIFY_REG(PWR->CR4, ((PWR_CR4_WP1 | PWR_CR4_WP2 | PWR_CR4_WP3) & WakeUpPinPolarity), + (WakeUpPinPolarity >> PWR_WUP_POLARITY_SHIFT)); + + /* Enable wake-up pin */ +#ifdef CORE_CM0PLUS + SET_BIT(PWR->C2CR3, (PWR_C2CR3_EWUP & WakeUpPinPolarity)); +#else + SET_BIT(PWR->CR3, (PWR_CR3_EWUP & WakeUpPinPolarity)); +#endif /* CORE_CM0PLUS */ +} + +/** + * @brief Disable the WakeUp PINx functionality. + * @param WakeUpPinx Specifies the Power Wake-Up pin to disable. + * This parameter can be one of the following values: + * @arg @ref PWR_WAKEUP_PIN1 Pin wake-up the system from Standby mode. + * @arg @ref PWR_WAKEUP_PIN2 Pin wake-up the system from Standby mode. + * @arg @ref PWR_WAKEUP_PIN3 Pin wake-up the system from Standby mode. + * @retval None + */ +void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx) +{ + assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx)); + + /* Disable wake-up pin */ +#ifdef CORE_CM0PLUS + CLEAR_BIT(PWR->C2CR3, (PWR_C2CR3_EWUP & WakeUpPinx)); +#else + CLEAR_BIT(PWR->CR3, (PWR_CR3_EWUP & WakeUpPinx)); +#endif /* CORE_CM0PLUS */ +} + +/** + * @brief Enter Sleep or Low-power Sleep mode. + * @note In Sleep/Low-power Sleep mode, all I/O pins keep the same state as in Run mode. + * @param Regulator Specifies the regulator state in Sleep/Low-power Sleep mode. + * This parameter can be one of the following values: + * @arg @ref PWR_MAINREGULATOR_ON Sleep mode (regulator in main mode) + * @arg @ref PWR_LOWPOWERREGULATOR_ON Low-power Sleep mode (regulator in low-power mode) + * @note Low-power Sleep mode is entered from Low-power Run mode (low-power regulator used + * and clock frequency below 2 MHz) and by calling HAL_PWR_EnterSLEEPMode() with Regulator set + * to PWR_LOWPOWERREGULATOR_ON. + * Additionally, the clock frequency must be reduced below 2 MHz. + * @note When exiting Low-power Sleep mode, the MCU is in Low-power Run mode. To move in + * Run mode, the user must resort to HAL_PWREx_DisableLowPowerRunMode() API. + * @param SLEEPEntry Specifies if Sleep mode is entered with WFI or WFE instruction. + * This parameter can be one of the following values: + * @arg @ref PWR_SLEEPENTRY_WFI enter Sleep or Low-power Sleep mode with WFI instruction + * @arg @ref PWR_SLEEPENTRY_WFE enter Sleep or Low-power Sleep mode with WFE instruction + * @note When WFI entry is used, tick interrupt have to be disabled if not desired as + * the interrupt wake up source. + * @retval None + */ +void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry) +{ + /* Check the parameters */ + assert_param(IS_PWR_REGULATOR(Regulator)); + assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry)); + + /* Set Regulator parameter */ + if (Regulator == PWR_MAINREGULATOR_ON) + { + /* If in low-power run mode at this point, exit it */ + if (HAL_IS_BIT_SET(PWR->SR2, (PWR_SR2_REGLPF))) + { + if (HAL_PWREx_DisableLowPowerRunMode() != HAL_OK) + { + return ; + } + } + /* Regulator now in main mode. */ + } + else + { + /* If in run mode, first move to low-power run mode. + The system clock frequency must be below 2 MHz at this point. */ + if (HAL_IS_BIT_CLR(PWR->SR2, (PWR_SR2_REGLPF))) + { + HAL_PWREx_EnableLowPowerRunMode(); + } + } + + /* Clear SLEEPDEEP bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); + + /* Select SLEEP mode entry -------------------------------------------------*/ + if (SLEEPEntry == PWR_SLEEPENTRY_WFI) + { + /* Request Wait For Interrupt */ + __WFI(); + } + else + { + /* Request Wait For Event */ + __SEV(); + __WFE(); + __WFE(); + } +} + +/** + * @brief Enter Stop mode + * @note This API is named HAL_PWR_EnterSTOPMode to ensure compatibility with legacy STM32 series + * where only "Stop mode" is mentioned with main or low power regulator ON. + * It is recommended to use functions: + * @arg @ref HAL_PWREx_EnterSTOP0Mode + * @arg @ref HAL_PWREx_EnterSTOP1Mode + * @arg @ref HAL_PWREx_EnterSTOP2Mode + * @note In Stop mode, all I/O pins keep the same state as in Run mode. + * @note All clocks in the VCORE domain are stopped; the PLL, the MSI, + * the HSI and the HSE oscillators are disabled. Some peripherals with the wakeup capability + * (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the HSI + * after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is propagated + * only to the peripheral requesting it. + * SRAM1, SRAM2 and register contents are preserved. + * The BOR is available. + * The voltage regulator can be configured either in normal (Stop 0) or low-power mode (Stop 1). + * @note When exiting Stop 0 or Stop 1 mode by issuing an interrupt or a wakeup event, + * the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register + * is set; the MSI oscillator is selected if STOPWUCK is cleared. + * @note When the voltage regulator operates in low power mode (Stop 1), an additional + * startup delay is incurred when waking up. + * By keeping the internal regulator ON during Stop mode (Stop 0), the consumption + * is higher although the startup time is reduced. + * @note According to system power policy, system entering in Stop mode + * is depending on other CPU power mode. + * @param Regulator Specifies the regulator state in Stop mode. + * This parameter can be one of the following values: + * @arg @ref PWR_MAINREGULATOR_ON Stop 0 mode (main regulator ON) + * @arg @ref PWR_LOWPOWERREGULATOR_ON Stop 1 mode (low power regulator ON) + * @param STOPEntry Specifies Stop 0, Stop 1 mode is entered with WFI or WFE instruction. + * This parameter can be one of the following values: + * @arg @ref PWR_STOPENTRY_WFI Enter Stop 0 or Stop 1 mode with WFI instruction. + * @arg @ref PWR_STOPENTRY_WFE Enter Stop 0 or Stop 1 mode with WFE instruction. + * @retval None + */ +void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry) +{ + /* Check the parameters */ + assert_param(IS_PWR_REGULATOR(Regulator)); + + if (Regulator == PWR_LOWPOWERREGULATOR_ON) + { + HAL_PWREx_EnterSTOP1Mode(STOPEntry); + } + else + { + HAL_PWREx_EnterSTOP0Mode(STOPEntry); + } +} + +/** + * @brief Enter Standby mode. + * @note In Standby mode, the PLL, the HSI, the MSI and the HSE oscillators are switched + * off. The voltage regulator is disabled, except when SRAM2 content is preserved + * in which case the regulator is in low-power mode. + * SRAM and register contents are lost except for registers in the Backup domain and + * Standby circuitry. SRAM2 content can be preserved if the bit RRS is set in PWR_CR3 register. + * To enable this feature, the user can resort to HAL_PWREx_EnableSRAMRetention() API + * to set RRS bit. + * The BOR is available. + * @note The I/Os can be configured either with a pull-up or pull-down or can be kept in analog state. + * HAL_PWREx_EnableGPIOPullUp() and HAL_PWREx_EnableGPIOPullDown() respectively enable Pull Up and + * Pull Down state, HAL_PWREx_DisableGPIOPullUp() and HAL_PWREx_DisableGPIOPullDown() disable the + * same. + * These states are effective in Standby mode only if APC bit is set through + * HAL_PWREx_EnablePullUpPullDownConfig() API. + * @note According to system power policy, system entering in Standby mode + * is depending on other CPU power mode. + * @retval None + */ +void HAL_PWR_EnterSTANDBYMode(void) +{ +#ifdef CORE_CM0PLUS + /* Set Stand-by mode */ + MODIFY_REG(PWR->C2CR1, PWR_C2CR1_LPMS, PWR_LOWPOWERMODE_STANDBY); +#else + /* Set Stand-by mode */ + MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_LOWPOWERMODE_STANDBY); +#endif /* CORE_CM0PLUS */ + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); + + /* This option is used to ensure that store operations are completed */ +#if defined (__CC_ARM) + __force_stores(); +#endif /* __CC_ARM */ + + /* Request Wait For Interrupt */ + __WFI(); + + /* Note: After this request to enter in Standby mode, at wake-up, program + execution depends on system low-power mode: + - If system was in Standby mode (other CPU in Standby or Shutdown), + then at wake-up program restarts at reset state + - If system was in Run or Stop mode (other CPU in Run, Sleep, Stop), + then at wake-up program continues from this point + */ +} + +/** + * @brief Indicate Sleep-On-Exit when returning from Handler mode to Thread mode. + * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor + * re-enters SLEEP mode when an interruption handling is over. + * Setting this bit is useful when the processor is expected to run only on + * interruptions handling. + * @retval None + */ +void HAL_PWR_EnableSleepOnExit(void) +{ + /* Set SLEEPONEXIT bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); +} + +/** + * @brief Disable Sleep-On-Exit feature when returning from Handler mode to Thread mode. + * @note Clear SLEEPONEXIT bit of SCR register. When this bit is set, the processor + * re-enters SLEEP mode when an interruption handling is over. + * @retval None + */ +void HAL_PWR_DisableSleepOnExit(void) +{ + /* Clear SLEEPONEXIT bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); +} + +/** + * @brief Enable CPU SEVONPEND bit. + * @note Set SEVONPEND bit of SCR register. When this bit is set, this causes + * WFE to wake up when an interrupt moves from inactive to pended. + * @retval None + */ +void HAL_PWR_EnableSEVOnPend(void) +{ + /* Set SEVONPEND bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); +} + +/** + * @brief Disable CPU SEVONPEND bit. + * @note Clear SEVONPEND bit of SCR register. When this bit is set, this causes + * WFE to wake up when an interrupt moves from inactive to pended. + * @retval None + */ +void HAL_PWR_DisableSEVOnPend(void) +{ + /* Clear SEVONPEND bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); +} + +/** + * @brief PWR PVD interrupt callback + * @retval None + */ +__weak void HAL_PWR_PVDCallback(void) +{ + /* NOTE : This function should not be modified; when the callback is needed, + the HAL_PWR_PVDCallback can be implemented in the user file + */ +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_PWR_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + diff --git a/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c b/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c new file mode 100644 index 0000000..983fe52 --- /dev/null +++ b/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c @@ -0,0 +1,1165 @@ +/** + ****************************************************************************** + * @file stm32wlxx_hal_pwr_ex.c + * @author MCD Application Team + * @brief Extended PWR HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Power Controller (PWR) peripheral: + * + Extended Initialization and de-initialization functions + * + Extended Peripheral Control functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wlxx_hal.h" + +/** @addtogroup STM32WLxx_HAL_Driver + * @{ + */ + +/** @addtogroup PWREx + * @{ + */ + +#ifdef HAL_PWR_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @addtogroup PWREx_Private_Constants PWR Extended Private Constants + * @{ + */ +#define PWR_PORTC_AVAILABLE_PINS (PWR_GPIO_BIT_15 |\ + PWR_GPIO_BIT_14 |\ + PWR_GPIO_BIT_13 |\ + PWR_GPIO_BIT_6 | PWR_GPIO_BIT_5 | PWR_GPIO_BIT_4 | PWR_GPIO_BIT_3 | PWR_GPIO_BIT_2 | PWR_GPIO_BIT_1 | PWR_GPIO_BIT_0) +#define PWR_PORTH_AVAILABLE_PINS (PWR_GPIO_BIT_3) + +/** @defgroup PWREx_TimeOut_Value PWR Extended Flag Setting Time Out Value + * @{ + */ +#define PWR_FLAG_SETTING_DELAY_US 50UL /*!< Time out value for REGLPF and VOSF flags setting */ +/** + * @} + */ + +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup PWREx_Exported_Functions PWR Extended Exported Functions + * @{ + */ + +/** @addtogroup PWREx_Exported_Functions_Group1 Extended Peripheral Control functions + * @brief Extended Peripheral Control functions + * +@verbatim + =============================================================================== + ##### Extended Peripheral Initialization and de-initialization functions ##### + =============================================================================== + [..] + +@endverbatim + * @{ + */ + + +/** + * @brief Return Voltage Scaling Range. + * @retval VOS bit field (PWR_REGULATOR_VOLTAGE_SCALE1 or PWPWR_REGULATOR_VOLTAGE_SCALE2) + */ +uint32_t HAL_PWREx_GetVoltageRange(void) +{ + return (PWR->CR1 & PWR_CR1_VOS); +} + +/** + * @brief Configure the main internal regulator output voltage. + * @param VoltageScaling specifies the regulator output voltage to achieve + * a trade-off between performance and power consumption. + * This parameter can be one of the following values: + * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1 Regulator voltage output range 1 mode, + * typical output voltage at 1.2 V, + * system frequency up to 48 MHz. + * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE2 Regulator voltage output range 2 mode, + * typical output voltage at 1.0 V, + * system frequency up to 16 MHz. + * @note When moving from Range 1 to Range 2, the system frequency must be decreased to + * a value below 16 MHz before calling HAL_PWREx_ControlVoltageScaling() API. + * When moving from Range 2 to Range 1, the system frequency can be increased to + * a value up to 48 MHz after calling HAL_PWREx_ControlVoltageScaling() API. + * @note When moving from Range 2 to Range 1, the API waits for VOSF flag to be + * cleared before returning the status. If the flag is not cleared within + * 50 microseconds, HAL_TIMEOUT status is reported. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling) +{ + uint32_t wait_loop_index; + + assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling)); + + /* If Set Range 1 */ + if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1) + { + if (READ_BIT(PWR->CR1, PWR_CR1_VOS) != PWR_REGULATOR_VOLTAGE_SCALE1) + { + /* Set Range 1 */ + MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1); + + /* Wait until VOSF is cleared */ + wait_loop_index = ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000UL); + while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U)) + { + wait_loop_index--; + } + if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) + { + return HAL_TIMEOUT; + } + } + } + else + { + if (READ_BIT(PWR->CR1, PWR_CR1_VOS) != PWR_REGULATOR_VOLTAGE_SCALE2) + { + /* Set Range 2 */ + MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE2); + /* No need to wait for VOSF to be cleared for this transition */ + } + } + + return HAL_OK; +} + +/****************************************************************************/ + +/** + * @brief Enable battery charging. + * When VDD is present, charge the external battery on VBAT through an internal resistor. + * @param ResistorSelection specifies the resistor impedance. + * This parameter can be one of the following values: + * @arg @ref PWR_BATTERY_CHARGING_RESISTOR_5 5 kOhms resistor + * @arg @ref PWR_BATTERY_CHARGING_RESISTOR_1_5 1.5 kOhms resistor + * @retval None + */ +void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorSelection) +{ + assert_param(IS_PWR_BATTERY_RESISTOR_SELECT(ResistorSelection)); + + /* Specify resistor selection */ + MODIFY_REG(PWR->CR4, PWR_CR4_VBRS, ResistorSelection); + + /* Enable battery charging */ + SET_BIT(PWR->CR4, PWR_CR4_VBE); +} + +/** + * @brief Disable battery charging. + * @retval None + */ +void HAL_PWREx_DisableBatteryCharging(void) +{ + CLEAR_BIT(PWR->CR4, PWR_CR4_VBE); +} + +/****************************************************************************/ + +/** + * @brief Enable Internal Wake-up Line. + * @retval None + */ +void HAL_PWREx_EnableInternalWakeUpLine(void) +{ +#ifdef CORE_CM0PLUS + SET_BIT(PWR->C2CR3, PWR_C2CR3_EIWUL); +#else + SET_BIT(PWR->CR3, PWR_CR3_EIWUL); +#endif /* CORE_CM0PLUS */ +} + +/** + * @brief Disable Internal Wake-up Line. + * @retval None + */ +void HAL_PWREx_DisableInternalWakeUpLine(void) +{ +#ifdef CORE_CM0PLUS + CLEAR_BIT(PWR->C2CR3, PWR_C2CR3_EIWUL); +#else + CLEAR_BIT(PWR->CR3, PWR_CR3_EIWUL); +#endif /* CORE_CM0PLUS */ +} + +/** + * @brief Set radio busy trigger polarity. + * @param RadioBusyPolarity This parameter can be one of the following values: + * @arg @ref PWR_RADIO_BUSY_POLARITY_RISING + * @arg @ref PWR_RADIO_BUSY_POLARITY_FALLING + * @retval HAL Status + */ +void HAL_PWREx_SetRadioBusyPolarity(uint32_t RadioBusyPolarity) +{ + /* Check the parameters */ + assert_param(IS_RADIO_BUSY_POLARITY(RadioBusyPolarity)); + + LL_PWR_SetRadioBusyPolarity(RadioBusyPolarity); +} + +/** + * @brief Set radio busy trigger action: wake-up from low-power mode Standby, + * interruption. + * @note Signal polarity can be configured using function + * @ref HAL_PWREx_SetRadioBusyPolarity(). + * @param RadioBusyTrigger This parameter can be one of the following values: + * @arg @ref PWR_RADIO_BUSY_TRIGGER_NONE + * @arg @ref PWR_RADIO_BUSY_TRIGGER_WU_IT + * @retval None + */ +void HAL_PWREx_SetRadioBusyTrigger(uint32_t RadioBusyTrigger) +{ + /* Check the parameters */ + assert_param(IS_PWR_RADIO_BUSY_TRIGGER(RadioBusyTrigger)); + +#ifdef CORE_CM0PLUS + LL_C2_PWR_SetRadioBusyTrigger(RadioBusyTrigger); +#else + LL_PWR_SetRadioBusyTrigger(RadioBusyTrigger); +#endif /* CORE_CM0PLUS */ +} + +/** + * @brief Set radio IRQ trigger action: wake-up from low-power mode Standby, + * interruption. + * @param RadioIRQTrigger This parameter can be one of the following values: + * @arg @ref PWR_RADIO_IRQ_TRIGGER_NONE + * @arg @ref PWR_RADIO_IRQ_TRIGGER_WU_IT + * @retval None + */ +void HAL_PWREx_SetRadioIRQTrigger(uint32_t RadioIRQTrigger) +{ + /* Check the parameters */ + assert_param(IS_RADIO_IRQ_TRIGGER(RadioIRQTrigger)); + +#ifdef CORE_CM0PLUS + LL_C2_PWR_SetRadioIRQTrigger(RadioIRQTrigger); +#else + LL_PWR_SetRadioIRQTrigger(RadioIRQTrigger); +#endif /* CORE_CM0PLUS */ +} + +#if defined(DUAL_CORE) +/** + * @brief Enable CPU2 on-Hold interrupt. + * @retval None + */ +void HAL_PWREx_EnableHOLDC2IT(void) +{ + SET_BIT(PWR->CR3, PWR_CR3_EC2H); +} + +/** + * @brief Disable CPU2 on-Hold interrupt. + * @retval None + */ +void HAL_PWREx_DisableHOLDC2IT(void) +{ + CLEAR_BIT(PWR->CR3, PWR_CR3_EC2H); +} +#endif /* DUAL_CORE */ + +/****************************************************************************/ + +/** + * @brief Enable GPIO pull-up state in Standby and Shutdown modes. + * @note Set the relevant PUy bits of PWR_PUCRx register to configure the I/O in + * pull-up state in Standby and Shutdown modes. + * @note This state is effective in Standby and Shutdown modes only if APC bit + * is set through HAL_PWREx_EnablePullUpPullDownConfig() API. + * @note The configuration is lost when exiting the Shutdown mode due to the + * power-on reset, maintained when exiting the Standby mode. + * @note To avoid any conflict at Standby and Shutdown modes exits, the corresponding + * PDy bit of PWR_PDCRx register is cleared unless it is reserved. + * @note Even if a PUy bit to set is reserved, the other PUy bits entered as input + * parameter at the same time are set. + * @param GPIO Specify the IO port. This parameter can be PWR_GPIO_A, ..., PWR_GPIO_H + * to select the GPIO peripheral. + * @param GPIONumber Specify the I/O pins numbers. + * This parameter can be one of the following values: + * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for PORTH where less + * I/O pins are available) or the logical OR of several of them to set + * several bits for a given port in a single API call. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber) +{ + HAL_StatusTypeDef status = HAL_OK; + + assert_param(IS_PWR_GPIO(GPIO)); + assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber)); + + switch (GPIO) + { + case PWR_GPIO_A: + SET_BIT(PWR->PUCRA, GPIONumber); + CLEAR_BIT(PWR->PDCRA, GPIONumber); + break; + case PWR_GPIO_B: + SET_BIT(PWR->PUCRB, GPIONumber); + CLEAR_BIT(PWR->PDCRB, GPIONumber); + break; + case PWR_GPIO_C: + SET_BIT(PWR->PUCRC, (GPIONumber & PWR_PORTC_AVAILABLE_PINS)); + CLEAR_BIT(PWR->PDCRC, (GPIONumber & PWR_PORTC_AVAILABLE_PINS)); + break; + case PWR_GPIO_H: + SET_BIT(PWR->PUCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS)); + CLEAR_BIT(PWR->PDCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS)); + break; + default: + status = HAL_ERROR; + break; + } + + return status; +} + +/** + * @brief Disable GPIO pull-up state in Standby mode and Shutdown modes. + * @note Reset the relevant PUy bits of PWR_PUCRx register used to configure the I/O + * in pull-up state in Standby and Shutdown modes. + * @note Even if a PUy bit to reset is reserved, the other PUy bits entered as input + * parameter at the same time are reset. + * @param GPIO Specifies the IO port. This parameter can be PWR_GPIO_A, ..., PWR_GPIO_H + * to select the GPIO peripheral. + * @param GPIONumber Specify the I/O pins numbers. + * This parameter can be one of the following values: + * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for PORTH where less + * I/O pins are available) or the logical OR of several of them to reset + * several bits for a given port in a single API call. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber) +{ + HAL_StatusTypeDef status = HAL_OK; + + assert_param(IS_PWR_GPIO(GPIO)); + assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber)); + + switch (GPIO) + { + case PWR_GPIO_A: + CLEAR_BIT(PWR->PUCRA, GPIONumber); + break; + case PWR_GPIO_B: + CLEAR_BIT(PWR->PUCRB, GPIONumber); + break; + case PWR_GPIO_C: + CLEAR_BIT(PWR->PUCRC, (GPIONumber & PWR_PORTC_AVAILABLE_PINS)); + break; + case PWR_GPIO_H: + CLEAR_BIT(PWR->PUCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS)); + break; + default: + status = HAL_ERROR; + break; + } + + return status; +} + +/** + * @brief Enable GPIO pull-down state in Standby and Shutdown modes. + * @note Set the relevant PDy bits of PWR_PDCRx register to configure the I/O in + * pull-down state in Standby and Shutdown modes. + * @note This state is effective in Standby and Shutdown modes only if APC bit + * is set through HAL_PWREx_EnablePullUpPullDownConfig() API. + * @note The configuration is lost when exiting the Shutdown mode due to the + * power-on reset, maintained when exiting the Standby mode. + * @note To avoid any conflict at Standby and Shutdown modes exits, the corresponding + * PUy bit of PWR_PUCRx register is cleared unless it is reserved. + * @note Even if a PDy bit to set is reserved, the other PDy bits entered as input + * parameter at the same time are set. + * @param GPIO Specify the IO port. This parameter can be PWR_GPIO_A..PWR_GPIO_H + * to select the GPIO peripheral. + * @param GPIONumber Specify the I/O pins numbers. + * This parameter can be one of the following values: + * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for PORTH where less + * I/O pins are available) or the logical OR of several of them to set + * several bits for a given port in a single API call. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber) +{ + HAL_StatusTypeDef status = HAL_OK; + + assert_param(IS_PWR_GPIO(GPIO)); + assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber)); + + switch (GPIO) + { + case PWR_GPIO_A: + SET_BIT(PWR->PDCRA, GPIONumber); + CLEAR_BIT(PWR->PUCRA, GPIONumber); + break; + case PWR_GPIO_B: + SET_BIT(PWR->PDCRB, GPIONumber); + CLEAR_BIT(PWR->PUCRB, GPIONumber); + break; + case PWR_GPIO_C: + SET_BIT(PWR->PDCRC, (GPIONumber & PWR_PORTC_AVAILABLE_PINS)); + CLEAR_BIT(PWR->PUCRC, (GPIONumber & PWR_PORTC_AVAILABLE_PINS)); + break; + case PWR_GPIO_H: + SET_BIT(PWR->PDCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS)); + CLEAR_BIT(PWR->PUCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS)); + break; + default: + status = HAL_ERROR; + break; + } + + return status; +} + +/** + * @brief Disable GPIO pull-down state in Standby and Shutdown modes. + * @note Reset the relevant PDy bits of PWR_PDCRx register used to configure the I/O + * in pull-down state in Standby and Shutdown modes. + * @note Even if a PDy bit to reset is reserved, the other PDy bits entered as input + * parameter at the same time are reset. + * @param GPIO Specifies the IO port. This parameter can be PWR_GPIO_A..PWR_GPIO_H + * to select the GPIO peripheral. + * @param GPIONumber Specify the I/O pins numbers. + * This parameter can be one of the following values: + * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for PORTH where less + * I/O pins are available) or the logical OR of several of them to reset + * several bits for a given port in a single API call. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber) +{ + HAL_StatusTypeDef status = HAL_OK; + + assert_param(IS_PWR_GPIO(GPIO)); + assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber)); + + switch (GPIO) + { + case PWR_GPIO_A: + CLEAR_BIT(PWR->PDCRA, GPIONumber); + break; + case PWR_GPIO_B: + CLEAR_BIT(PWR->PDCRB, GPIONumber); + break; + case PWR_GPIO_C: + CLEAR_BIT(PWR->PDCRC, (GPIONumber & PWR_PORTC_AVAILABLE_PINS)); + break; + case PWR_GPIO_H: + CLEAR_BIT(PWR->PDCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS)); + break; + default: + status = HAL_ERROR; + break; + } + + return status; +} + +/** + * @brief Enable pull-up and pull-down configuration. + * @note When APC bit is set, the I/O pull-up and pull-down configurations defined in + * PWR_PUCRx and PWR_PDCRx registers are applied in Standby and Shutdown modes. + * @note Pull-up set by PUy bit of PWR_PUCRx register is not activated if the corresponding + * PDy bit of PWR_PDCRx register is also set (pull-down configuration priority is higher). + * HAL_PWREx_EnableGPIOPullUp() and HAL_PWREx_EnableGPIOPullDown() API's ensure there + * is no conflict when setting PUy or PDy bit. + * @retval None + */ +void HAL_PWREx_EnablePullUpPullDownConfig(void) +{ +#ifdef CORE_CM0PLUS + SET_BIT(PWR->C2CR3, PWR_C2CR3_APC); +#else + SET_BIT(PWR->CR3, PWR_CR3_APC); +#endif /* CORE_CM0PLUS */ +} + +/** + * @brief Disable pull-up and pull-down configuration. + * @note When APC bit is cleared, the I/O pull-up and pull-down configurations defined in + * PWR_PUCRx and PWR_PDCRx registers are not applied in Standby and Shutdown modes. + * @retval None + */ +void HAL_PWREx_DisablePullUpPullDownConfig(void) +{ +#ifdef CORE_CM0PLUS + CLEAR_BIT(PWR->C2CR3, PWR_C2CR3_APC); +#else + CLEAR_BIT(PWR->CR3, PWR_CR3_APC); +#endif /* CORE_CM0PLUS */ +} + +/****************************************************************************/ + +#if defined(DUAL_CORE) +/** + * @brief Hold CPU and allocated peripherals after reset or wakeup from Stop or Standby. + * @param CPU Specifies the core to be held. + * This parameter can be one of the following values: + * @arg PWR_CORE_CPU2: Hold CPU2. + * @note Hold CPU2 with CPU1 as master by default. + * @retval None + */ +void HAL_PWREx_HoldCore(uint32_t CPU) +{ + /* Check the parameters */ + assert_param(IS_PWR_CORE_HOLD_RELEASE(CPU)); + + LL_PWR_DisableBootC2(); +} + +/** + * @brief Release CPU and allocated peripherals after reset or wakeup from Stop or Standby. + * @param CPU Specifies the core to be released. + * This parameter can be one of the following values: + * @arg PWR_CORE_CPU2: Release the CPU2 from holding. + * @retval None + */ +void HAL_PWREx_ReleaseCore(uint32_t CPU) +{ + /* Check the parameters */ + assert_param(IS_PWR_CORE_HOLD_RELEASE(CPU)); + + LL_PWR_EnableBootC2(); +} + +/****************************************************************************/ +#ifdef CORE_CM0PLUS +/** + * @brief Enable CPU2 wake-up from low-power mode on illegal access occurrence + * @note Can be configured from CPU2 only + * @retval None + */ +void HAL_PWREx_EnableWakeUp_ILAC(void) +{ + LL_PWR_C2_EnableWakeUp_ILAC(); +} + +/** + * @brief Disable CPU2 wake-up from low-power mode on illegal access occurrence + * @note Can be configured from CPU2 only + * @retval None + */ +void HAL_PWREx_DisableWakeUp_ILAC(void) +{ + LL_PWR_C2_DisableWakeUp_ILAC(); +} + +/** + * @brief Check if bit to wake-up CPU2 from low-power mode on illegal access + * occurrence is set + * @note Can be used from CPU2 only + * @retval State of bit (1 or 0) + */ +uint32_t HAL_PWREx_IsEnabledWakeUp_ILAC(void) +{ + return LL_PWR_C2_IsEnabledWakeUp_ILAC(); +} +#endif /* CORE_CM0PLUS */ +#endif /* DUAL_CORE */ + +/****************************************************************************/ +/** + * @brief Enable SRAM2 content retention in Standby mode. + * @note When RRS bit is set, SRAM is powered by the low-power regulator in + * Standby mode and its content is kept. + * @retval None + */ +void HAL_PWREx_EnableSRAMRetention(void) +{ + LL_PWR_EnableSRAM2Retention(); +} + +/** + * @brief Disable SRAM2 content retention in Standby mode. + * @note When RRS bit is reset, SRAM is powered off in Standby mode + * and its content is lost. + * @retval None + */ +void HAL_PWREx_DisableSRAMRetention(void) +{ + LL_PWR_DisableSRAM2Retention(); +} + +/****************************************************************************/ +/** + * @brief Enable Flash Power Down. + * @note This API allows to enable flash power down capabilities in low power + * run and low power sleep modes. + * @note This configuration is effective when both CPU have selected it. + * @param PowerMode this can be a combination of following values: + * @arg @ref PWR_FLASHPD_LPRUN + * @arg @ref PWR_FLASHPD_LPSLEEP + * @retval None + */ +void HAL_PWREx_EnableFlashPowerDown(uint32_t PowerMode) +{ + assert_param(IS_PWR_FLASH_POWERDOWN(PowerMode)); + +#ifdef CORE_CM0PLUS + if ((PowerMode & PWR_FLASHPD_LPRUN) != 0U) + { + /* Unlock bit FPDR */ + WRITE_REG(PWR->C2CR1, PWR_FLASH_POWER_MODE_UNLOCK_CODE); + } + + /* Set flash power down mode */ + SET_BIT(PWR->C2CR1, PowerMode); +#else + if ((PowerMode & PWR_FLASHPD_LPRUN) != 0U) + { + /* Unlock bit FPDR */ + WRITE_REG(PWR->CR1, PWR_FLASH_POWER_MODE_UNLOCK_CODE); + } + + /* Set flash power down mode */ + SET_BIT(PWR->CR1, PowerMode); +#endif /* CORE_CM0PLUS */ +} + +/** + * @brief Disable Flash Power Down. + * @note This API allows to disable flash power down capabilities in low power + * run and low power sleep modes. + * @note This configuration is effective when both CPU have selected it. + * @param PowerMode this can be a combination of following values: + * @arg @ref PWR_FLASHPD_LPRUN + * @arg @ref PWR_FLASHPD_LPSLEEP + * @retval None + */ +void HAL_PWREx_DisableFlashPowerDown(uint32_t PowerMode) +{ + assert_param(IS_PWR_FLASH_POWERDOWN(PowerMode)); + +#ifdef CORE_CM0PLUS + /* Set flash power down mode */ + CLEAR_BIT(PWR->C2CR1, PowerMode); +#else + /* Set flash power down mode */ + CLEAR_BIT(PWR->CR1, PowerMode); +#endif /* CORE_CM0PLUS */ +} + +/****************************************************************************/ +/** + * @brief Enable wake-up power voltage detection + * @note Wake-up power voltage detection status can be checked + * using flag @ref PWR_FLAG_WPVD. + * @retval None + */ +void HAL_PWREx_EnableWPVD(void) +{ +#ifdef CORE_CM0PLUS + LL_C2_PWR_EnableWPVD(); +#else + LL_PWR_EnableWPVD(); +#endif /* CORE_CM0PLUS */ +} + +/** + * @brief Disable wake-up power voltage detection + * @retval None + */ +void HAL_PWREx_DisableWPVD(void) +{ +#ifdef CORE_CM0PLUS + LL_C2_PWR_DisableWPVD(); +#else + LL_PWR_DisableWPVD(); +#endif /* CORE_CM0PLUS */ +} + +/** + * @brief Enable periodical sampling of supply voltage in Stop and Standby + * modes for detecting condition of PDR and BOR reset. + * @note Caution: When enabled, and if the supply voltage drops below + * the minimum operating condition between two supply voltage samples, + * the reset condition is missed and no reset is generated. + * @retval None + */ +void HAL_PWREx_EnableBORPVD_ULP(void) +{ + SET_BIT(PWR->CR3, PWR_CR3_ULPEN); +} + + +/** + * @brief Disable periodical sampling of supply voltage in Stop and Standby + * modes for detecting condition of PDR and BOR reset. + * @note All the other modes are not affected by this bit + * @retval None + */ +void HAL_PWREx_DisableBORPVD_ULP(void) +{ + CLEAR_BIT(PWR->CR3, PWR_CR3_ULPEN); +} + +/****************************************************************************/ + +/** + * @brief Enable the Power Voltage Monitoring 3: VDDA versus 1.62V. + * @retval None + */ +void HAL_PWREx_EnablePVM3(void) +{ + SET_BIT(PWR->CR2, PWR_PVM_3); +} + +/** + * @brief Disable the Power Voltage Monitoring 3: VDDA versus 1.62V. + * @retval None + */ +void HAL_PWREx_DisablePVM3(void) +{ + CLEAR_BIT(PWR->CR2, PWR_PVM_3); +} + +/** + * @brief Configure the Peripheral Voltage Monitoring (PVM). + * @param sConfigPVM pointer to a PWR_PVMTypeDef structure that contains the + * PVM configuration information. + * @note The API configures a single PVM according to the information contained + * in the input structure. To configure several PVMs, the API must be singly + * called for each PVM used. + * @note Refer to the electrical characteristics of your device datasheet for + * more details about the voltage thresholds corresponding to each + * detection level and to each monitored supply. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PWREx_ConfigPVM(const PWR_PVMTypeDef *sConfigPVM) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_PWR_PVM_TYPE(sConfigPVM->PVMType)); + assert_param(IS_PWR_PVM_MODE(sConfigPVM->Mode)); + + /* Configure EXTI lines if so required: + scan through PVMType to detect which PVMx is set and + configure the corresponding EXTI line accordingly. */ + switch (sConfigPVM->PVMType) + { + case PWR_PVM_3: + /* Clear any previous config. Keep it clear if no event or IT mode is selected */ + __HAL_PWR_PVM3_EXTI_DISABLE_EVENT(); + __HAL_PWR_PVM3_EXTI_DISABLE_IT(); + + __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE(); + __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE(); + + /* Configure interrupt mode */ + if ((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT) + { + __HAL_PWR_PVM3_EXTI_ENABLE_IT(); + } + + /* Configure the edge */ + if ((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE) + { + __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE(); + } + + if ((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE) + { + __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE(); + } + break; + + default: + status = HAL_ERROR; + break; + + } + + return status; +} + +/** + * @brief Set monitoring of supply voltage for radio operating level + * (radio End Of Life), radio must be in active mode. + * @param RadioEOL This parameter can be one of the following values: + * @arg @ref PWR_RADIO_EOL_ENABLE + * @arg @ref PWR_RADIO_EOL_DISABLE + * @retval None + */ +void HAL_PWREx_SetRadioEOL(uint32_t RadioEOL) +{ + MODIFY_REG(PWR->CR5, PWR_CR5_RFEOLEN, RadioEOL); +} + +/****************************************************************************/ + +/** + * @brief Set SMPS operating mode. + * @note In case of a board without SMPS coil mounted, SMPS should not be activated. + * @param OperatingMode This parameter can be one of the following values: + * @arg @ref PWR_SMPS_BYPASS + * @arg @ref PWR_SMPS_STEP_DOWN + * @retval None + */ +void HAL_PWREx_SMPS_SetMode(uint32_t OperatingMode) +{ + MODIFY_REG(PWR->CR5, PWR_CR5_SMPSEN, OperatingMode); +} + +/** + * @brief Get SMPS effective operating mode + * @note SMPS operating mode can be changed by hardware, therefore + * requested operating mode can differ from effective low power mode. + * - dependency SubGhz Radio IP: can switch SMPS on for radio activity. + * @note In case of a board without SMPS coil mounted, SMPS should not be activated + * and this function is not relevant. + * @retval Returned value can be one of the following values: + * @arg @ref PWR_SMPS_BYPASS + * @arg @ref PWR_SMPS_STEP_DOWN + */ +uint32_t HAL_PWREx_SMPS_GetEffectiveMode(void) +{ + /* Return a value corresponding to definition of literals */ + /* PWR_SMPS_BYPASS or PWR_SMPS_STEP_DOWN. */ + return (uint32_t)(READ_BIT(PWR->SR2, PWR_SR2_SMPSRDY) << (PWR_CR5_SMPSEN_Pos - PWR_SR2_SMPSRDY_Pos)); +} + +/****************************************************************************/ + +/** + * @brief Enter Low-power Run mode + * @note In Low-power Run mode, all I/O pins keep the same state as in Run mode. + * @note Clock frequency must be reduced below 2 MHz. + * @retval None + */ +void HAL_PWREx_EnableLowPowerRunMode(void) +{ + /* Set Regulator parameter */ + SET_BIT(PWR->CR1, PWR_CR1_LPR); +} + +/** + * @brief Exit Low-power Run mode. + * @note Before HAL_PWREx_DisableLowPowerRunMode() completion, the function checks that + * REGLPF has been properly reset (otherwise, HAL_PWREx_DisableLowPowerRunMode + * returns HAL_TIMEOUT status). The system clock frequency can then be + * increased above 2 MHz. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void) +{ + uint32_t wait_loop_index; + + /* Clear LPR bit */ + CLEAR_BIT(PWR->CR1, PWR_CR1_LPR); + + /* Wait until REGLPF is reset */ + wait_loop_index = ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000UL); + while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF)) && (wait_loop_index != 0U)) + { + wait_loop_index--; + } + if (HAL_IS_BIT_SET(PWR->SR2, (PWR_SR2_REGLPF))) + { + return HAL_TIMEOUT; + } + + return HAL_OK; +} + +/****************************************************************************/ + +/** + * @brief Enter Stop 0 mode. + * @note In Stop 0 mode, main and low voltage regulators are ON. + * @note In Stop 0 mode, all I/O pins keep the same state as in Run mode. + * @note All clocks in the VCORE domain are stopped; the PLL, the MSI, + * the HSI and the HSE oscillators are disabled. Some peripherals with the wakeup capability + * (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the HSI + * after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is propagated + * only to the peripheral requesting it. + * SRAM1, SRAM2 and register contents are preserved. + * The BOR is available. + * @note When exiting Stop 0 mode by issuing an interrupt or a wakeup event, + * the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register + * is set; the MSI oscillator is selected if STOPWUCK is cleared. + * @note By keeping the internal regulator ON during Stop 0 mode, the consumption + * is higher although the startup time is reduced. + * @note According to system power policy, system entering in Stop mode + * is depending on other CPU power mode. + * @param STOPEntry specifies if Stop mode in entered with WFI or WFE instruction. + * This parameter can be one of the following values: + * @arg @ref PWR_STOPENTRY_WFI Enter Stop mode with WFI instruction + * @arg @ref PWR_STOPENTRY_WFE Enter Stop mode with WFE instruction + * @retval None + */ +void HAL_PWREx_EnterSTOP0Mode(uint8_t STOPEntry) +{ + /* Check the parameters */ + assert_param(IS_PWR_STOP_ENTRY(STOPEntry)); + +#ifdef CORE_CM0PLUS + /* Stop 0 mode with Main Regulator */ + MODIFY_REG(PWR->C2CR1, PWR_C2CR1_LPMS, PWR_LOWPOWERMODE_STOP0); + +#else + /* Stop 0 mode with Main Regulator */ + MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_LOWPOWERMODE_STOP0); + +#endif /* CORE_CM0PLUS */ + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); + + /* Select Stop mode entry --------------------------------------------------*/ + if (STOPEntry == PWR_STOPENTRY_WFI) + { + /* Request Wait For Interrupt */ + __WFI(); + } + else + { + /* Request Wait For Event */ + __SEV(); + __WFE(); + __WFE(); + } + + /* Reset SLEEPDEEP bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); +} + +/** + * @brief Enter Stop 1 mode. + * @note In Stop 1 mode, only low power voltage regulator is ON. + * @note In Stop 1 mode, all I/O pins keep the same state as in Run mode. + * @note All clocks in the VCORE domain are stopped; the PLL, the MSI, + * the HSI and the HSE oscillators are disabled. Some peripherals with the wakeup capability + * (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the HSI + * after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is propagated + * only to the peripheral requesting it. + * SRAM1, SRAM2 and register contents are preserved. + * The BOR is available. + * @note When exiting Stop 1 mode by issuing an interrupt or a wakeup event, + * the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register + * is set; the MSI oscillator is selected if STOPWUCK is cleared. + * @note Due to low power mode, an additional startup delay is incurred when waking up from Stop 1 mode. + * @note According to system power policy, system entering in Stop mode + * is depending on other CPU power mode. + * @param STOPEntry specifies if Stop mode in entered with WFI or WFE instruction. + * This parameter can be one of the following values: + * @arg @ref PWR_STOPENTRY_WFI Enter Stop mode with WFI instruction + * @arg @ref PWR_STOPENTRY_WFE Enter Stop mode with WFE instruction + * @retval None + */ +void HAL_PWREx_EnterSTOP1Mode(uint8_t STOPEntry) +{ + /* Check the parameters */ + assert_param(IS_PWR_STOP_ENTRY(STOPEntry)); + +#ifdef CORE_CM0PLUS + /* Stop 1 mode with Low-Power Regulator */ + MODIFY_REG(PWR->C2CR1, PWR_C2CR1_LPMS, PWR_LOWPOWERMODE_STOP1); +#else + /* Stop 1 mode with Low-Power Regulator */ + MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_LOWPOWERMODE_STOP1); +#endif /* CORE_CM0PLUS */ + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); + + /* Select Stop mode entry --------------------------------------------------*/ + if (STOPEntry == PWR_STOPENTRY_WFI) + { + /* Request Wait For Interrupt */ + __WFI(); + } + else + { + /* Request Wait For Event */ + __SEV(); + __WFE(); + __WFE(); + } + + /* Reset SLEEPDEEP bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); +} + + +/** + * @brief Enter Stop 2 mode. + * @note In Stop 2 mode, only low power voltage regulator is ON. + * @note In Stop 2 mode, all I/O pins keep the same state as in Run mode. + * @note All clocks in the VCORE domain are stopped, the PLL, the MSI, + * the HSI and the HSE oscillators are disabled. Some peripherals with wakeup capability + * (LCD, LPTIM1, I2C3 and LPUART) can switch on the HSI to receive a frame, and switch off the HSI after + * receiving the frame if it is not a wakeup frame. In this case the HSI clock is propagated only + * to the peripheral requesting it. + * SRAM1, SRAM2 and register contents are preserved. + * The BOR is available. + * The voltage regulator is set in low-power mode but LPR bit must be cleared to enter stop 2 mode. + * Otherwise, Stop 1 mode is entered. + * @note When exiting Stop 2 mode by issuing an interrupt or a wakeup event, + * the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register + * is set; the MSI oscillator is selected if STOPWUCK is cleared. + * @note According to system power policy, system entering in Stop mode + * is depending on other CPU power mode. + * @param STOPEntry specifies if Stop mode in entered with WFI or WFE instruction. + * This parameter can be one of the following values: + * @arg @ref PWR_STOPENTRY_WFI Enter Stop mode with WFI instruction + * @arg @ref PWR_STOPENTRY_WFE Enter Stop mode with WFE instruction + * @retval None + */ +void HAL_PWREx_EnterSTOP2Mode(uint8_t STOPEntry) +{ + /* Check the parameter */ + assert_param(IS_PWR_STOP_ENTRY(STOPEntry)); + +#ifdef CORE_CM0PLUS + /* Set Stop mode 2 */ + MODIFY_REG(PWR->C2CR1, PWR_C2CR1_LPMS, PWR_LOWPOWERMODE_STOP2); +#else + /* Set Stop mode 2 */ + MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_LOWPOWERMODE_STOP2); +#endif /* CORE_CM0PLUS */ + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); + + /* Select Stop mode entry --------------------------------------------------*/ + if (STOPEntry == PWR_STOPENTRY_WFI) + { + /* Request Wait For Interrupt */ + __WFI(); + } + else + { + /* Request Wait For Event */ + __SEV(); + __WFE(); + __WFE(); + } + + /* Reset SLEEPDEEP bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); +} + +/** + * @brief Enter Shutdown mode. + * @note In Shutdown mode, the PLL, the HSI, the MSI, the LSI and the HSE oscillators are switched + * off. The voltage regulator is disabled and Vcore domain is powered off. + * SRAM1, SRAM2 and registers contents are lost except for registers in the Backup domain. + * The BOR is not available. + * @note The I/Os can be configured either with a pull-up or pull-down or can be kept in analog state. + * @note According to system power policy, system entering in Shutdown mode + * is depending on other CPU power mode. + * @retval None + */ +void HAL_PWREx_EnterSHUTDOWNMode(void) +{ +#ifdef CORE_CM0PLUS + /* Set Shutdown mode */ + MODIFY_REG(PWR->C2CR1, PWR_C2CR1_LPMS, PWR_LOWPOWERMODE_SHUTDOWN); +#else + /* Set Shutdown mode */ + MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_LOWPOWERMODE_SHUTDOWN); +#endif /* CORE_CM0PLUS */ + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); + + /* This option is used to ensure that store operations are completed */ +#if defined (__CC_ARM) + __force_stores(); +#endif /* __CC_ARM */ + + /* Request Wait For Interrupt */ + __WFI(); + + /* Note: After this request to enter in Shutdown mode, at wake-up, program + execution depends on system low-power mode: + - If system was in Shutdown mode (other CPU in Shutdown), + then at wake-up program restarts at reset state + - If system was in Run or Stop mode (other CPU in Run, Sleep, Stop), + then at wake-up program continues from this point + */ +} + +/** + * @brief This function handles the PWR PVD/PVMx interrupt request. + * @note This API should be called under the PVD_PVM_IRQHandler(). + * @retval None + */ +void HAL_PWREx_PVD_PVM_IRQHandler(void) +{ + /* Check PWR exti flag */ + if (__HAL_PWR_PVD_EXTI_GET_FLAG() != 0UL) + { + /* Clear PVD exti pending bit */ + __HAL_PWR_PVD_EXTI_CLEAR_FLAG(); + + /* PWR PVD interrupt user callback */ + HAL_PWR_PVDCallback(); + } + + if (__HAL_PWR_PVM3_EXTI_GET_FLAG() != 0UL) + { + /* Clear PVM3 exti pending bit */ + __HAL_PWR_PVM3_EXTI_CLEAR_FLAG(); + + /* PWR PVM3 interrupt user callback */ + HAL_PWREx_PVM3Callback(); + } +} + +/** + * @brief PWR PVM3 interrupt callback + * @retval None + */ +__weak void HAL_PWREx_PVM3Callback(void) +{ + /* NOTE : This function should not be modified; when the callback is needed, + HAL_PWREx_PVM3Callback() API can be implemented in the user file + */ +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_PWR_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + diff --git a/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.c b/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.c new file mode 100644 index 0000000..45162e5 --- /dev/null +++ b/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.c @@ -0,0 +1,1670 @@ +/** + ****************************************************************************** + * @file stm32wlxx_hal_rcc.c + * @author MCD Application Team + * @brief RCC HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Reset and Clock Control (RCC) peripheral: + * + Initialization and de-initialization functions + * + Peripheral Control functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### RCC specific features ##### + ============================================================================== + [..] + After reset the device is running from Multiple Speed Internal oscillator + (4 MHz) with Flash 0 wait state. Flash prefetch buffer, D-Cache + and I-Cache are disabled, and all peripherals are off except internal + SRAM, Flash and JTAG. + + (+) There is no prescaler on High speed (AHBs) and Low speed (APBs) buses: + all peripherals mapped on these buses are running at MSI speed. + (+) The clock for all peripherals is switched off, except the SRAM and FLASH. + (+) All GPIOs are in analog mode, except the JTAG pins which + are assigned to be used for debug purpose. + + [..] + Once the device started from reset, the user application has to: + (+) Configure clock source to be used to drive the System clock + (if the application needs higher frequency/performance) + (+) Configure the System clock frequency and Flash settings + (+) Configure the AHB and APB buses prescalers + (+) Enable the clock for the peripheral(s) to be used + (+) Configure the clock source(s) for peripherals which clocks are not + derived from the System clock (RTC, ADC, RNG, I2S2, USARTx, LPUART1, LPTIMx, I2Cx) + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wlxx_hal.h" + +/** @addtogroup STM32WLxx_HAL_Driver + * @{ + */ + +/** @defgroup RCC RCC + * @brief RCC HAL module driver + * @{ + */ + +#ifdef HAL_RCC_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup RCC_Private_Constants RCC Private Constants + * @{ + */ +#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT +#define HSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */ +#define MSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */ +#define LSI_TIMEOUT_VALUE (17U) /* 17 ms (16 ms starting time + 1) */ +#define PRESCALER_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */ +#define LATENCY_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */ +#define CLOCKSWITCH_TIMEOUT_VALUE (5000U) /* 5 s */ + +#define PLLSOURCE_NONE (0U) +#define MEGA_HZ (1000000U) /* Division factor to convert Hz in Mhz */ + +#define RCC_PLLCFR_RESET_VALUE (RCC_PLLCFGR_PLLR_0 | RCC_PLLCFGR_PLLQ_0 | RCC_PLLCFGR_PLLP_1 | RCC_PLLCFGR_PLLN_0) +#define RCC_EXTCFGR_RESET_VALUE (0x00030000U) +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/** @defgroup RCC_Private_Macros RCC Private Macros + * @{ + */ +#define RCC_GET_MCO_GPIO_PIN(__RCC_MCOx__) ((__RCC_MCOx__) & GPIO_PIN_MASK) + +#define RCC_GET_MCO_GPIO_AF(__RCC_MCOx__) (((__RCC_MCOx__) & RCC_MCO_GPIOAF_MASK) >> RCC_MCO_GPIOAF_POS) + +#define RCC_GET_MCO_GPIO_INDEX(__RCC_MCOx__) (((__RCC_MCOx__) & RCC_MCO_GPIOPORT_MASK) >> RCC_MCO_GPIOPORT_POS) + +#define RCC_GET_MCO_GPIO_PORT(__RCC_MCOx__) (IOPORT_BASE + ((0x00000400UL) * RCC_GET_MCO_GPIO_INDEX((__RCC_MCOx__)))) + +#define __COUNTOF(_A_) (sizeof(_A_) / sizeof(*(_A_))) +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup RCC_Private_Functions RCC Private Functions + * @{ + */ +static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t MSI_Range); +static HAL_StatusTypeDef RCC_SetFlashLatency(uint32_t Flash_ClkSrcFreq, uint32_t VCORE_Voltage); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup RCC_Exported_Functions RCC Exported Functions + * @{ + */ + +/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * + @verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] + This section provides functions allowing to configure the internal and external oscillators + (HSE, HSI, LSE, MSI, LSI, PLL, CSS and MCO) and the System buses clocks (SYSCLK, HCLK1, HCLK2, HCLK3, PCLK1 + and PCLK2). + + [..] Internal/external clock and PLL configuration + (+) HSI (high-speed internal): 16 MHz factory-trimmed RC used directly or through + the PLL as System clock source. + + (+) MSI (Multiple Speed Internal): Its frequency is software trimmable from 100KHZ to 48MHZ. + The number of flash wait states is automatically adjusted when MSI range is updated with + HAL_RCC_OscConfig() and the MSI is used as System clock source. + + (+) LSI (low-speed internal): 32 KHz low consumption RC used as IWDG and/or RTC + clock source. + + (+) HSE (high-speed external): 32 MHz crystal oscillator used directly or + through the PLL as System clock source. It is used also as RF clock source + Can be used also optionally as RTC clock source. + + (+) LSE (low-speed external): 32.768 KHz oscillator used optionally to drive RTC used for + Auto-wakeup from Stop and Standby modes, or the real-time clock (RTCCLK). + + (+) PLL (clocked by HSI, HSE or MSI) providing up to three independent output clocks: + (++) The first output is used to generate the high speed system clock (up to 48MHz). + (++) The second output is used to generate the clock for I2S2 and the random analog generator (<=48 MHz) + (++) The third output is used to generate a clock on ADC interface. + + (+) CSS (Clock security system): once enabled, if a HSE clock failure occurs + (HSE used directly or through PLL as System clock source), the System clock + is automatically switched to MSI or the HSI oscillator (depending on the + STOPWUCK configuration) and an interrupt is generated if enabled. + The interrupt is linked to the CPU1 and CPU2 NMI (Non-Maskable Interrupt) exception vector. + + (+) LSECSS: once enabled, if a LSE clock failure occurs, the LSE + clock is no longer supplied to the RTC but no hardware action is made to the registers. If the + MSI was in PLL-mode, this mode is disabled. + In Standby mode a wakeup is generated. In other modes an interrupt can be sent to wakeup + the software + + (+) MCO (microcontroller clock output): used to output MSI, LSI, HSI, LSE, HSE (before and + after stabilization), SYSCLK, or main PLL clocks (through a configurable prescaler) on PA8 pin. + + [..] System, AHB and APB buses clocks configuration + (+) Several clock sources can be used to drive the System clock (SYSCLK): MSI, HSI, + HSE and main PLL. + The AHB clock (HCLK1) is derived from System clock through configurable + prescaler and used to clock the CPU1, memory and peripherals mapped + on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived + from AHB clock through configurable prescalers and used to clock + the peripherals mapped on these buses. You can use + "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks. + The AHB3 clock (HCLK3) is derived from System clock through configurable + prescaler and used to clock the FLASH. APB3 (PCLK3) is derived from AHB3 clock. + + -@- All the peripheral clocks are derived from the System clock (SYSCLK) except: + + (+@) RTC: the RTC clock can be derived either from the LSI, LSE or HSE clock divided by 32. + You have to use __HAL_RCC_RTC_ENABLE() and HAL_RCCEx_PeriphCLKConfig() function + to configure this clock. + + (+@) IWDG clock which is always the LSI clock. + + (+) The maximum frequency of the SYSCLK, HCLK1, HCLK2, HCLK3, PCLK1 and PCLK2 is 48 MHz. + The clock source frequency should be adapted depending on the device voltage range + as listed in the Reference Manual "Clock source frequency versus voltage scaling" chapter. + + @endverbatim + + Table 1. HCLK3 clock frequency. + +--------------------------------------------------------+ + | Latency | HCLK3 clock frequency (MHz) | + | |-------------------------------------| + | | voltage range 1 | voltage range 2 | + | | 1.2 V | 1.0 V | + |------------------|------------------|------------------| + |0WS(1 HCLK cycles | HCLK3 <= 18 | HCLK3 <= 6 | + |------------------|------------------|------------------| + |1WS(2 HCLK cycles)| HCLK3 <= 36 | HCLK3 <= 12 | + |------------------|------------------|------------------| + |2WS(3 HCLK cycles)| HCLK3 <= 48 | HCLK3 <= 16 | + |------------------|------------------|------------------| + + * @{ + */ + +/** + * @brief Reset the RCC clock configuration to the default reset state. + * @note The default reset state of the clock configuration is given below: + * - MSI ON and used as system clock source + * - HSE, HSI, PLL OFF + * - HCLK1, HCLK2, HCLK3, PCLK1 and PCLK2 prescalers set to 1. + * - CSS, MCO OFF + * - All interrupts disabled + * @note This function doesn't modify the configuration of the + * - Peripheral clocks + * - LSI, LSE and RTC clocks + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCC_DeInit(void) +{ + uint32_t tickstart; + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Set MSION bit */ + LL_RCC_MSI_Enable(); + + /* Wait till MSI is ready */ + while (LL_RCC_MSI_IsReady() == 0U) + { + if ((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Set MSIRANGE default value */ + LL_RCC_MSI_SetRange(LL_RCC_MSIRANGE_6); + + /* Set MSITRIM bits to the reset value*/ + LL_RCC_MSI_SetCalibTrimming(RCC_MSICALIBRATION_DEFAULT); + + /* Set HSITRIM bits to the reset value*/ + LL_RCC_HSI_SetCalibTrimming(RCC_HSICALIBRATION_DEFAULT); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Reset CFGR register (MSI is selected as system clock source) */ + CLEAR_REG(RCC->CFGR); + + /* Wait till MSI oscillator used as system clock */ + while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_MSI) + { + if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Reset HSION, HSIKERON, HSIASFS, HSEON, PLLON, HSEPRE bits */ + CLEAR_BIT(RCC->CR, RCC_CR_HSION | RCC_CR_HSIKERON | RCC_CR_HSIASFS | RCC_CR_HSEON | RCC_CR_HSEPRE | RCC_CR_PLLON); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till HSE is disabled */ + while (LL_RCC_HSE_IsReady() != 0U) + { + if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Reset HSEBYPPWR bit once HSE is OFF */ + LL_RCC_HSE_DisableTcxo(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLL is fully stopped */ + while (LL_RCC_PLL_IsReady() != 0U) + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* once PLL is OFF, reset PLLCFGR register to default value */ + WRITE_REG(RCC->PLLCFGR, RCC_PLLCFR_RESET_VALUE); + + /* Disable all interrupts */ + CLEAR_REG(RCC->CIER); + + /* Clear all flags */ + WRITE_REG(RCC->CICR, 0xFFFFFFFFU); + + /* EXTCFGR reset*/ + WRITE_REG(RCC->EXTCFGR, RCC_EXTCFGR_RESET_VALUE); + + /* Update the SystemCoreClock global variable */ + SystemCoreClock = MSI_VALUE; + + /* Adapt Systick interrupt period */ + if (HAL_InitTick(uwTickPrio) != HAL_OK) + { + return HAL_ERROR; + } + else + { + return HAL_OK; + } +} + +/** + * @brief Initialize the RCC Oscillators according to the specified parameters in the + * @ref RCC_OscInitTypeDef. + * @param RCC_OscInitStruct pointer to a @ref RCC_OscInitTypeDef structure that + * contains the configuration information for the RCC Oscillators. + * @note The PLL is not disabled when used as system clock. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) +{ + uint32_t tickstart; + uint32_t sysclk_source; + uint32_t pll_config; + HAL_StatusTypeDef status; + + /* Check Null pointer */ + if (RCC_OscInitStruct == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); + + sysclk_source = __HAL_RCC_GET_SYSCLK_SOURCE(); + pll_config = __HAL_RCC_GET_PLL_OSCSOURCE(); + + /*----------------------------- MSI Configuration --------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI) + { + /* Check the parameters */ + assert_param(IS_RCC_MSI(RCC_OscInitStruct->MSIState)); + assert_param(IS_RCC_MSI_CALIBRATION_VALUE(RCC_OscInitStruct->MSICalibrationValue)); + assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange)); + + /* When the MSI is used as system clock it will not be disabled */ + if ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_MSI) || + ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_MSI))) + { + if (RCC_OscInitStruct->MSIState == RCC_MSI_OFF) + { + return HAL_ERROR; + } + /* Otherwise, just the calibration and MSI range change are allowed */ + else + { + /* To correctly read data from FLASH memory, the number of wait states (LATENCY) + must be correctly programmed according to the frequency of the AHB3 clock + and the supply voltage of the device. */ + if (RCC_OscInitStruct->MSIClockRange > __HAL_RCC_GET_MSI_RANGE()) + { + /* First increase number of wait states update if necessary */ + if (RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK) + { + return HAL_ERROR; + } + + /* Selects the Multiple Speed oscillator (MSI) clock range .*/ + __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange); + /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/ + __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue); + } + else + { + /* Else, keep current flash latency while decreasing applies */ + /* Selects the Multiple Speed oscillator (MSI) clock range. */ + __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange); + /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/ + __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue); + + /* Decrease number of wait states update if necessary */ + if (RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK) + { + return HAL_ERROR; + } + } + + /* Update the SystemCoreClock global variable */ + SystemCoreClock = HAL_RCC_GetHCLKFreq(); + + /* Configure the source of time base considering new system clocks settings */ + status = HAL_InitTick(uwTickPrio); + if (status != HAL_OK) + { + return status; + } + } + } + else + { + /* Check the MSI State */ + if (RCC_OscInitStruct->MSIState != RCC_MSI_OFF) + { + /* Enable the Internal High Speed oscillator (MSI). */ + __HAL_RCC_MSI_ENABLE(); + + /* Get timeout */ + tickstart = HAL_GetTick(); + + /* Wait till MSI is ready */ + while (LL_RCC_MSI_IsReady() == 0U) + { + if ((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Selects the Multiple Speed oscillator (MSI) clock range. */ + __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange); + /* Adjusts the Multiple Speed oscillator (MSI) calibration value. */ + __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue); + + } + else + { + /* Disable the Internal High Speed oscillator (MSI). */ + __HAL_RCC_MSI_DISABLE(); + + /* Get timeout */ + tickstart = HAL_GetTick(); + + /* Wait till MSI is disabled */ + while (LL_RCC_MSI_IsReady() != 0U) + { + if ((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + } + + /*------------------------------- HSE Configuration ------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) + { + /* Check the parameters */ + assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); + + /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ + if ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSE) || + ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_HSE))) + { + if (RCC_OscInitStruct->HSEState == RCC_HSE_OFF) + { + return HAL_ERROR; + } + } + else + { + /* Set the new HSE configuration ---------------------------------------*/ + /* Check HSE division factor */ + assert_param(IS_RCC_HSEDIV(RCC_OscInitStruct->HSEDiv)); + + /* Set HSE division factor */ + MODIFY_REG(RCC->CR, RCC_CR_HSEPRE, RCC_OscInitStruct->HSEDiv); + + __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); + + /* Check the HSE State */ + if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF) + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till HSE is ready */ + while (LL_RCC_HSE_IsReady() == 0U) + { + if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till HSE is disabled */ + while (LL_RCC_HSE_IsReady() != 0U) + { + if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + } + + /*----------------------------- HSI Configuration --------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) + { + /* Check the parameters */ + assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); + assert_param(IS_RCC_HSI_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); + + /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ + if ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSI) || + ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_HSI))) + { + /* When HSI is used as system clock it will not be disabled */ + if (RCC_OscInitStruct->HSIState == RCC_HSI_OFF) + { + return HAL_ERROR; + } + /* Otherwise, just the calibration is allowed */ + else + { + /* Adjusts the Internal High Speed oscillator (HSI) calibration value. */ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + } + } + else + { + /* Check the HSI State */ + if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF) + { + /* Enable the Internal High Speed oscillator (HSI). */ + __HAL_RCC_HSI_ENABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till HSI is ready */ + while (LL_RCC_HSI_IsReady() == 0U) + { + if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Adjusts the Internal High Speed oscillator (HSI) calibration value. */ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + } + else + { + /* Disable the Internal High Speed oscillator (HSI). */ + __HAL_RCC_HSI_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till HSI is disabled */ + while (LL_RCC_HSI_IsReady() != 0U) + { + if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + } + + /*------------------------------ LSI Configuration -------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) + { + /* Check the parameters */ + assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); + + /* Check the LSI State */ + if (RCC_OscInitStruct->LSIState != RCC_LSI_OFF) + { + uint32_t csr_temp = RCC->CSR; + + /* Check LSI division factor */ + assert_param(IS_RCC_LSIDIV(RCC_OscInitStruct->LSIDiv)); + + if (RCC_OscInitStruct->LSIDiv != (csr_temp & RCC_CSR_LSIPRE)) + { + if (((csr_temp & RCC_CSR_LSIRDY) == RCC_CSR_LSIRDY) && \ + ((csr_temp & RCC_CSR_LSION) != RCC_CSR_LSION)) + { + /* If LSIRDY is set while LSION is not enabled, + LSIPRE can't be updated */ + return HAL_ERROR; + } + + /* Turn off LSI before changing RCC_CSR_LSIPRE */ + if ((csr_temp & RCC_CSR_LSION) == RCC_CSR_LSION) + { + __HAL_RCC_LSI_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till LSI is disabled */ + while (LL_RCC_LSI_IsReady() != 0U) + { + if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + + /* Set LSI division factor */ + MODIFY_REG(RCC->CSR, RCC_CSR_LSIPRE, RCC_OscInitStruct->LSIDiv); + } + + /* Enable the Internal Low Speed oscillator (LSI). */ + __HAL_RCC_LSI_ENABLE(); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till LSI is ready */ + while (LL_RCC_LSI_IsReady() == 0U) + { + if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Disable the Internal Low Speed oscillator (LSI). */ + __HAL_RCC_LSI_DISABLE(); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till LSI is disabled */ + while (LL_RCC_LSI_IsReady() != 0U) + { + if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + + /*------------------------------ LSE Configuration -------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) + { + /* Check the parameters */ + assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); + + /* Update LSE configuration in Backup Domain control register */ + /* Requires to enable write access to Backup Domain of necessary */ + + if (LL_PWR_IsEnabledBkUpAccess() == 0U) + { + /* Enable write access to Backup domain */ + HAL_PWR_EnableBkUpAccess(); + + /* Wait for Backup domain Write protection disable */ + tickstart = HAL_GetTick(); + + while (LL_PWR_IsEnabledBkUpAccess() == 0U) + { + if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + + /* Set the new LSE configuration -----------------------------------------*/ + if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF) + { + /* Enable LSE bypasss (if requested) */ + if ((RCC_OscInitStruct->LSEState == RCC_LSE_BYPASS) + || (RCC_OscInitStruct->LSEState == RCC_LSE_BYPASS_RTC_ONLY)) + { + /* LSE oscillator bypass enable */ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); + } + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* LSE oscillator enable */ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); + + /* Wait till LSE is ready */ + while (LL_RCC_LSE_IsReady() == 0U) + { + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Enable LSE system clock (if requested) */ + if ((RCC_OscInitStruct->LSEState == RCC_LSE_ON) + || (RCC_OscInitStruct->LSEState == RCC_LSE_BYPASS)) + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + SET_BIT(RCC->BDCR, RCC_BDCR_LSESYSEN); + + /* Wait till LSESYS is ready */ + while (READ_BIT(RCC->BDCR, RCC_BDCR_LSESYSRDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSESYSEN); + + /* Wait till LSESYSRDY is cleared */ + while (READ_BIT(RCC->BDCR, RCC_BDCR_LSESYSRDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + else + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSESYSEN); + + /* Wait till LSESYSRDY is cleared */ + while (READ_BIT(RCC->BDCR, RCC_BDCR_LSESYSRDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* LSE oscillator disable */ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); + + /* Wait till LSE is disabled */ + while (LL_RCC_LSE_IsReady() != 0U) + { + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + + /*-------------------------------- PLL Configuration -----------------------*/ + /* Check the parameters */ + assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); + + if (RCC_OscInitStruct->PLL.PLLState != RCC_PLL_NONE) + { + /* Check if the PLL is used as system clock or not */ + if (sysclk_source != RCC_SYSCLKSOURCE_STATUS_PLLCLK) + { + if (RCC_OscInitStruct->PLL.PLLState == RCC_PLL_ON) + { + /* Check the parameters */ + assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); + assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM)); + assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN)); + assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP)); + assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ)); + assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR)); + + /* Disable the main PLL. */ + __HAL_RCC_PLL_DISABLE(); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till PLL is ready */ + while (LL_RCC_PLL_IsReady() != 0U) + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Configure the main PLL clock source, multiplication and division factors. */ + __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, + RCC_OscInitStruct->PLL.PLLM, + RCC_OscInitStruct->PLL.PLLN, + RCC_OscInitStruct->PLL.PLLP, + RCC_OscInitStruct->PLL.PLLQ, + RCC_OscInitStruct->PLL.PLLR); + + /* Enable the main PLL. */ + __HAL_RCC_PLL_ENABLE(); + + /* Enable PLL System Clock output. */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SYSCLK); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till PLL is ready */ + while (LL_RCC_PLL_IsReady() == 0U) + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Disable the main PLL. */ + __HAL_RCC_PLL_DISABLE(); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till PLL is disabled */ + while (LL_RCC_PLL_IsReady() != 0U) + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Disable the PLL source and outputs to save power when PLL is off */ + CLEAR_BIT(RCC->PLLCFGR, (RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLPEN | RCC_PLLCFGR_PLLQEN | RCC_PLLCFGR_PLLREN)); + } + } + else + { + /* Check if there is a request to disable the PLL used as System clock source */ + if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) + { + return HAL_ERROR; + } + else + { + /* Do not return HAL_ERROR if request repeats the current configuration */ + pll_config = RCC->PLLCFGR; + if ((READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) + || (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) + || (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) + || (READ_BIT(pll_config, RCC_PLLCFGR_PLLR) != RCC_OscInitStruct->PLL.PLLR)) + { + return HAL_ERROR; + } + } + } + } + return HAL_OK; +} + + +/** + * @brief Initialize the CPU, AHB and APB buses clocks according to the specified + * parameters in the RCC_ClkInitStruct. + * @param RCC_ClkInitStruct pointer to a @ref RCC_ClkInitTypeDef structure that + * contains the configuration information for the RCC peripheral. + * @param FLatency FLASH Latency + * This parameter can be one of the following values: + * @arg FLASH_LATENCY_0 FLASH 0 Latency cycle + * @arg FLASH_LATENCY_1 FLASH 1 Latency cycle + * @arg FLASH_LATENCY_2 FLASH 2 Latency cycle + * + * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency + * + * @note The MSI is used by default as system clock source after + * wake-up from Reset, wake-up from STANDBY mode. After restart from Reset, + * the MSI frequency is set to its default value 4 MHz. + * + * @note The HSI can be selected as system clock source after + * from STOP modes or in case of failure of the HSE used directly or indirectly + * as system clock (if the Clock Security System CSS is enabled). + * + * @note A switch from one clock source to another occurs only if the target + * clock source is ready (clock stable after startup delay or PLL locked). + * If a clock source which is not yet ready is selected, the switch will + * occur when the clock source is ready. + * + * @note You can use @ref HAL_RCC_GetClockConfig() function to know which clock is + * currently used as system clock source. + * + * @note Depending on the device voltage range, the software has to set correctly + * HPRE[3:0] bits to ensure that HCLK1 not exceed the maximum allowed frequency + * (for more details refer to section above "Initialization/de-initialization functions") + * @retval None + */ +HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) +{ + uint32_t tickstart; + + /* Check Null pointer */ + if (RCC_ClkInitStruct == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType)); + assert_param(IS_FLASH_LATENCY(FLatency)); + + /* To correctly read data from FLASH memory, the number of wait states (LATENCY) + must be correctly programmed according to the frequency of the FLASH clock + (HCLK3) and the supply voltage of the device. */ + + /* Increasing the number of wait states because of higher CPU frequency */ + if (FLatency > __HAL_FLASH_GET_LATENCY()) + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLatency); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + while (__HAL_FLASH_GET_LATENCY() != FLatency) + { + if ((HAL_GetTick() - tickstart) > LATENCY_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + + /*-------------------------- HCLK1 Configuration ---------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) + { + assert_param(IS_RCC_HCLKx(RCC_ClkInitStruct->AHBCLKDivider)); + LL_RCC_SetAHBPrescaler(RCC_ClkInitStruct->AHBCLKDivider); + + /* HCLK1 prescaler flag when value applied */ + tickstart = HAL_GetTick(); + while (LL_RCC_IsActiveFlag_HPRE() == 0U) + { + if ((HAL_GetTick() - tickstart) > PRESCALER_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + +#if defined(DUAL_CORE) + /*-------------------------- HCLK2 Configuration ---------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK2) == RCC_CLOCKTYPE_HCLK2) + { + assert_param(IS_RCC_HCLKx(RCC_ClkInitStruct->AHBCLK2Divider)); + LL_C2_RCC_SetAHBPrescaler(RCC_ClkInitStruct->AHBCLK2Divider); + + /* HCLK2 prescaler flag when value applied */ + tickstart = HAL_GetTick(); + while (LL_RCC_IsActiveFlag_C2HPRE() == 0U) + { + if ((HAL_GetTick() - tickstart) > PRESCALER_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } +#endif /* DUAL_CORE */ + + /*-------------------------- HCLK3 Configuration ---------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK3) == RCC_CLOCKTYPE_HCLK3) + { + assert_param(IS_RCC_HCLKx(RCC_ClkInitStruct->AHBCLK3Divider)); + LL_RCC_SetAHB3Prescaler(RCC_ClkInitStruct->AHBCLK3Divider); + + /* AHB shared prescaler flag when value applied */ + tickstart = HAL_GetTick(); + while (LL_RCC_IsActiveFlag_SHDHPRE() == 0U) + { + if ((HAL_GetTick() - tickstart) > PRESCALER_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + + /*-------------------------- PCLK1 Configuration ---------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) + { + assert_param(IS_RCC_PCLKx(RCC_ClkInitStruct->APB1CLKDivider)); + LL_RCC_SetAPB1Prescaler(RCC_ClkInitStruct->APB1CLKDivider); + + /* APB1 prescaler flag when value applied */ + tickstart = HAL_GetTick(); + while (LL_RCC_IsActiveFlag_PPRE1() == 0U) + { + if ((HAL_GetTick() - tickstart) > PRESCALER_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + + /*-------------------------- PCLK2 Configuration ---------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) + { + assert_param(IS_RCC_PCLKx(RCC_ClkInitStruct->APB2CLKDivider)); + LL_RCC_SetAPB2Prescaler((RCC_ClkInitStruct->APB2CLKDivider) << 3U); + + /* APB2 prescaler flag when value applied */ + tickstart = HAL_GetTick(); + while (LL_RCC_IsActiveFlag_PPRE2() == 0U) + { + if ((HAL_GetTick() - tickstart) > PRESCALER_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + + /*------------------------- SYSCLK Configuration ---------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) + { + assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); + + /* HSE is selected as System Clock Source */ + if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) + { + /* Check the HSE ready flag */ + if (LL_RCC_HSE_IsReady() == 0U) + { + return HAL_ERROR; + } + } + /* PLL is selected as System Clock Source */ + else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) + { + /* Check the PLL ready flag */ + if (LL_RCC_PLL_IsReady() == 0U) + { + return HAL_ERROR; + } + } + /* MSI is selected as System Clock Source */ + else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_MSI) + { + /* Check the MSI ready flag */ + if (LL_RCC_MSI_IsReady() == 0U) + { + return HAL_ERROR; + } + } + /* HSI is selected as System Clock Source */ + else + { + /* Check the HSI ready flag */ + if (LL_RCC_HSI_IsReady() == 0U) + { + return HAL_ERROR; + } + + } + + /* apply system clock switch */ + LL_RCC_SetSysClkSource(RCC_ClkInitStruct->SYSCLKSource); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* check system clock source switch status */ + while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) + { + if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + + /* Decreasing the number of wait states because of lower CPU frequency */ + if (FLatency < __HAL_FLASH_GET_LATENCY()) + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLatency); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + while (__HAL_FLASH_GET_LATENCY() != FLatency) + { + if ((HAL_GetTick() - tickstart) > LATENCY_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + + /*--------------------------------------------------------------------------*/ + + /* Update the SystemCoreClock global variable */ + SystemCoreClock = HAL_RCC_GetHCLKFreq(); + + /* Configure the source of time base considering new system clocks settings */ + return HAL_InitTick(uwTickPrio); +} + +/** + * @} + */ + +/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions + * @brief RCC clocks control functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to: + + (+) Output clock to MCO pin. + (+) Retrieve current clock frequencies. + (+) Enable the Clock Security System. + (+) HSE CSS Interrupt handler. + (+) Default HSE CSS callback function. + +@endverbatim + * @{ + */ + +/** + * @brief Select the clock source to output on MCO1 pin(PA8). + * @note PA8 should be configured in alternate function mode. + * @param RCC_MCOx specifies the output direction for the clock source. + * @arg @ref RCC_MCO1_PA8 Clock source to output on MCO1 pin(PA8). + * @param RCC_MCOSource specifies the clock source to output. + * This parameter can be one of the following values: + * @arg @ref RCC_MCO1SOURCE_NOCLOCK MCO output disabled, no clock on MCO + * @arg @ref RCC_MCO1SOURCE_SYSCLK system clock selected as MCO source + * @arg @ref RCC_MCO1SOURCE_MSI MSI clock selected as MCO source + * @arg @ref RCC_MCO1SOURCE_HSI HSI clock selected as MCO source + * @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO source + * @arg @ref RCC_MCO1SOURCE_PLLCLK main PLLR clock selected as MCO source + * @arg @ref RCC_MCO1SOURCE_LSI LSI clock selected as MCO source + * @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO source + * @arg @ref RCC_MCO1SOURCE_PLLPCLK main PLLP clock selected as MCO source + * @arg @ref RCC_MCO1SOURCE_PLLQCLK main PLLQ clock selected as MCO source + * @param RCC_MCODiv specifies the MCO prescaler. + * This parameter can be one of the following values: + * @arg @ref RCC_MCODIV_1 no division applied to MCO clock + * @arg @ref RCC_MCODIV_2 division by 2 applied to MCO clock + * @arg @ref RCC_MCODIV_4 division by 4 applied to MCO clock + * @arg @ref RCC_MCODIV_8 division by 8 applied to MCO clock + * @arg @ref RCC_MCODIV_16 division by 16 applied to MCO clock + * @retval None + */ +void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv) +{ + GPIO_InitTypeDef gpio_initstruct; + uint32_t mco_gpio_index; + GPIO_TypeDef *mco_gpio_port; + + /* Check the parameters */ + assert_param(IS_RCC_MCO(RCC_MCOx)); + assert_param(IS_RCC_MCODIV(RCC_MCODiv)); + assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource)); + + /* Configure the MCO1 pin in alternate function mode */ + gpio_initstruct.Mode = GPIO_MODE_AF_PP; + gpio_initstruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + gpio_initstruct.Pull = GPIO_NOPULL; + + /* Get MCOx GPIO Port */ + mco_gpio_port = (GPIO_TypeDef *) RCC_GET_MCO_GPIO_PORT(RCC_MCOx); + + /* MCOx Clock Enable */ + mco_gpio_index = RCC_GET_MCO_GPIO_INDEX(RCC_MCOx); + SET_BIT(RCC->AHB2ENR, (1UL << mco_gpio_index)); + + /* Configure the MCOx pin in alternate function mode */ + gpio_initstruct.Pin = RCC_GET_MCO_GPIO_PIN(RCC_MCOx); + gpio_initstruct.Alternate = RCC_GET_MCO_GPIO_AF(RCC_MCOx); + HAL_GPIO_Init(mco_gpio_port, &gpio_initstruct); + + /* Configure the microcontroller clock output (MCO) */ + LL_RCC_ConfigMCO(RCC_MCOSource, RCC_MCODiv); +} + +/** + * @brief Return the SYSCLK frequency. + * + * @note The system computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * @note If SYSCLK source is MSI, function returns values based on MSI range + * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*) + * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**) + * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(**), + * HSI_VALUE(*) or MSI Value multiplied/divided by the PLL factors. + * @note (*) HSI_VALUE is a constant defined in stm32wlxx_hal_conf.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * @note (**) HSE_VALUE is a constant defined in stm32wlxx_hal_conf.h file (default value + * 32 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * @note The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @note This function can be used by the user application to compute the + * baudrate for the communication peripherals or configure other parameters. + * + * @note Each time SYSCLK changes, this function must be called to update the + * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect. + * + * + * @retval SYSCLK frequency + */ +uint32_t HAL_RCC_GetSysClockFreq(void) +{ + uint32_t sysclk_source; + uint32_t pllsource; + uint32_t sysclockfreq = 0U; + uint32_t msifreq = 0U; + uint32_t pllinputfreq; + + sysclk_source = __HAL_RCC_GET_SYSCLK_SOURCE(); + pllsource = __HAL_RCC_GET_PLL_OSCSOURCE(); + + if ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_MSI) || + ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pllsource == RCC_PLLSOURCE_MSI))) + { + /* MSI or PLL with MSI source used as system clock source */ + /* Retrieve MSI frequency range in Hz */ + msifreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), + ((LL_RCC_MSI_IsEnabledRangeSelect() == 1U) ? + LL_RCC_MSI_GetRange() : + LL_RCC_MSI_GetRangeAfterStandby())); + + /* Get SYSCLK source */ + if (sysclk_source == RCC_SYSCLKSOURCE_STATUS_MSI) + { + /* MSI used as system clock source */ + sysclockfreq = msifreq; + } + } + else if (sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSI) + { + /* HSI used as system clock source */ + sysclockfreq = HSI_VALUE; + } + else if (sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSE) + { + /* HSE used as system clock source */ + if (LL_RCC_HSE_IsEnabledDiv2() == 1U) + { + sysclockfreq = HSE_VALUE / 2U; + } + else + { + sysclockfreq = HSE_VALUE; + } + } + else + { + /* Nothing to do */ + } + + if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) + { + /* PLL used as system clock source */ + pllsource = LL_RCC_PLL_GetMainSource(); + + switch (pllsource) + { + case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ + pllinputfreq = HSI_VALUE; + break; + case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ + if (LL_RCC_HSE_IsEnabledDiv2() == 1U) + { + pllinputfreq = HSE_VALUE / 2U; + } + else + { + pllinputfreq = HSE_VALUE; + } + break; + case RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */ + default: + pllinputfreq = msifreq; + break; + } + sysclockfreq = __LL_RCC_CALC_PLLCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(), + LL_RCC_PLL_GetN(), LL_RCC_PLL_GetR()); + } + + return sysclockfreq; +} + +/** + * @brief Return the HCLK frequency. + * @retval HCLK frequency in Hz + */ +uint32_t HAL_RCC_GetHCLKFreq(void) +{ + /* Get SysClock and Compute HCLK1 frequency --------------------------------*/ + return ((uint32_t)(__LL_RCC_CALC_HCLK1_FREQ(HAL_RCC_GetSysClockFreq(), LL_RCC_GetAHBPrescaler()))); +} + +#if defined(DUAL_CORE) +/** + * @brief Return the HCLK2 frequency. + * @retval HCLK2 frequency in Hz + */ +uint32_t HAL_RCC_GetHCLK2Freq(void) +{ + /* Get SysClock and Compute HCLK2 frequency --------------------------------*/ + return ((uint32_t)(__LL_RCC_CALC_HCLK2_FREQ(HAL_RCC_GetSysClockFreq(), LL_C2_RCC_GetAHBPrescaler()))); +} +#endif /* DUAL_CORE */ + +/** + * @brief Return the HCLK3 frequency. + * @retval HCLK3 frequency in Hz + */ +uint32_t HAL_RCC_GetHCLK3Freq(void) +{ + /* Get SysClock and Compute AHB3 frequency ---------------------------------*/ + return ((uint32_t)(__LL_RCC_CALC_HCLK3_FREQ(HAL_RCC_GetSysClockFreq(), LL_RCC_GetAHB3Prescaler()))); +} + +/** + * @brief Return the PCLK1 frequency. + * @retval PCLK1 frequency in Hz + */ +uint32_t HAL_RCC_GetPCLK1Freq(void) +{ + /* Get HCLK source and Compute PCLK1 frequency -----------------------------*/ + return ((uint32_t)(__LL_RCC_CALC_PCLK1_FREQ(HAL_RCC_GetHCLKFreq(), LL_RCC_GetAPB1Prescaler()))); +} + +/** + * @brief Return the PCLK2 frequency. + * @retval PCLK2 frequency in Hz + */ +uint32_t HAL_RCC_GetPCLK2Freq(void) +{ + /* Get HCLK source and Compute PCLK2 frequency -----------------------------*/ + return ((uint32_t)(__LL_RCC_CALC_PCLK2_FREQ(HAL_RCC_GetHCLKFreq(), LL_RCC_GetAPB2Prescaler()))); +} + +/** + * @brief Configure the RCC_OscInitStruct according to the internal + * RCC configuration registers. + * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that + * will be configured. + * @retval None + */ +void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) +{ + uint32_t regvalue; + uint32_t regICSRvalue; + uint32_t regPLLCFGRvalue; + + /* Check the parameters */ + if (RCC_OscInitStruct != NULL) + { + /* Set all possible values for the Oscillator type parameter ---------------*/ + RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_MSI | \ + RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI; + + /* Get register values */ + regvalue = RCC->CR; /* Control register */ + regICSRvalue = RCC->ICSCR; /* Get Internal Clock Sources Calibration register */ + regPLLCFGRvalue = RCC->PLLCFGR; /* Get PLL Configuration register */ + + /* Get the HSE configuration -----------------------------------------------*/ + RCC_OscInitStruct->HSEState = (regvalue & RCC_HSE_BYPASS_PWR); + RCC_OscInitStruct->HSEDiv = (regvalue & RCC_CR_HSEPRE); + + /* Get the MSI configuration -----------------------------------------------*/ + RCC_OscInitStruct->MSIState = (regvalue & RCC_CR_MSION); + RCC_OscInitStruct->MSICalibrationValue = ((regICSRvalue & RCC_ICSCR_MSITRIM) >> RCC_ICSCR_MSITRIM_Pos); + RCC_OscInitStruct->MSIClockRange = (regvalue & RCC_CR_MSIRANGE); + + /* Get the HSI configuration -----------------------------------------------*/ + RCC_OscInitStruct->HSIState = (regvalue & RCC_CR_HSION); + RCC_OscInitStruct->HSICalibrationValue = ((regICSRvalue & RCC_ICSCR_HSITRIM) >> RCC_ICSCR_HSITRIM_Pos); + + /* Get the PLL configuration -----------------------------------------------*/ + RCC_OscInitStruct->PLL.PLLState = ((regvalue & RCC_CR_PLLON) >> RCC_CR_PLLON_Pos) + 1U; + RCC_OscInitStruct->PLL.PLLSource = (regPLLCFGRvalue & RCC_PLLCFGR_PLLSRC); + RCC_OscInitStruct->PLL.PLLM = (regPLLCFGRvalue & RCC_PLLCFGR_PLLM); + RCC_OscInitStruct->PLL.PLLN = ((regPLLCFGRvalue & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); + RCC_OscInitStruct->PLL.PLLP = (regPLLCFGRvalue & RCC_PLLCFGR_PLLP); + RCC_OscInitStruct->PLL.PLLQ = (regPLLCFGRvalue & RCC_PLLCFGR_PLLQ); + RCC_OscInitStruct->PLL.PLLR = (regPLLCFGRvalue & RCC_PLLCFGR_PLLR); + + /* Get Backup Domain register */ + regvalue = RCC->BDCR; + + /* Get the LSE configuration -----------------------------------------------*/ + RCC_OscInitStruct->LSEState = (regvalue & RCC_LSE_BYPASS); + + /* Get Control/Status register */ + regvalue = RCC->CSR; + + /* Get the LSI configuration -----------------------------------------------*/ + RCC_OscInitStruct->LSIState = (regvalue & RCC_LSI_ON); + RCC_OscInitStruct->LSIDiv = (regvalue & RCC_CSR_LSIPRE); + } +} + +/** + * @brief Configure the RCC_ClkInitStruct according to the internal + * RCC configuration registers. + * @param RCC_ClkInitStruct Pointer to a @ref RCC_ClkInitTypeDef structure that + * will be configured. + * @param pFLatency Pointer to the Flash Latency variable. + * @retval None + */ +void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency) +{ + uint32_t regvalue; + + /* Check the parameters */ + if ((RCC_ClkInitStruct != NULL) && (pFLatency != NULL)) + { + /* Set all possible values for the Clock type parameter --------------------*/ + RCC_ClkInitStruct->ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 \ + | RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_HCLK3); +#if defined(DUAL_CORE) + RCC_ClkInitStruct->ClockType |= RCC_CLOCKTYPE_HCLK2; +#endif /* DUAL_CORE */ + + /* Get Clock Configuration Register */ + regvalue = RCC->CFGR; + + /* Get the SYSCLK configuration --------------------------------------------*/ + RCC_ClkInitStruct->SYSCLKSource = (regvalue & RCC_CFGR_SWS); + + /* Get the HCLK configuration ----------------------------------------------*/ + RCC_ClkInitStruct->AHBCLKDivider = (regvalue & RCC_CFGR_HPRE); + + /* Get the APB1 configuration ----------------------------------------------*/ + RCC_ClkInitStruct->APB1CLKDivider = (regvalue & RCC_CFGR_PPRE1); + + /* Get the APB2 configuration ----------------------------------------------*/ + RCC_ClkInitStruct->APB2CLKDivider = (regvalue & RCC_CFGR_PPRE2); + + /* Get Extended Clock Recovery Register */ + regvalue = RCC->EXTCFGR; + +#if defined(DUAL_CORE) + /* Get the AHBCLK2Divider configuration ------------------------------------*/ + RCC_ClkInitStruct->AHBCLK2Divider = (regvalue & RCC_EXTCFGR_C2HPRE); +#endif /* DUAL_CORE */ + + /* Get the AHBCLK3Divider configuration ------------------------------------*/ + RCC_ClkInitStruct->AHBCLK3Divider = ((regvalue & RCC_EXTCFGR_SHDHPRE) << 4); + + /* Get the Flash Wait State (Latency) configuration ------------------------*/ + *pFLatency = __HAL_FLASH_GET_LATENCY(); + } +} + +/** + * @brief Enable the Clock Security System. + * @note If a failure is detected on the HSE oscillator clock, this oscillator + * is automatically disabled and an interrupt is generated to inform the + * software about the failure (Clock Security System Interrupt, CSSI), + * allowing the MCU to perform rescue operations. The CSSI is linked to + * CPU1 and CPU2 NMI (Non-Maskable Interrupt) exception vector. + * @note The Clock Security System can only be cleared by reset. + * @retval None + */ +void HAL_RCC_EnableCSS(void) +{ + LL_RCC_HSE_EnableCSS(); +} + +/** + * @brief Handle the RCC HSE Clock Security System interrupt request. + * @note This API should be called under the NMI_Handler(). + * @retval None + */ +void HAL_RCC_NMI_IRQHandler(void) +{ + /* Check RCC CSSF interrupt flag */ + if (__HAL_RCC_GET_IT(RCC_IT_HSECSS)) + { + /* RCC Clock Security System interrupt user callback */ + HAL_RCC_CSSCallback(); + + /* Clear RCC CSS pending bit */ + __HAL_RCC_CLEAR_IT(RCC_IT_HSECSS); + } +} + +/** + * @brief Handle the RCC HSE Clock Security System interrupt callback. + * @retval none + */ +__weak void HAL_RCC_CSSCallback(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the @ref HAL_RCC_CSSCallback should be implemented in the user file + */ +} + +/** + * @brief Get and clear reset flags + * @note Once reset flags are retrieved, this API is clearing them in order + * to isolate next reset reason. + * @retval can be a combination of @ref RCC_Reset_Flag + */ +uint32_t HAL_RCC_GetResetSource(void) +{ + uint32_t reset; + + /* Get all reset flags */ + reset = RCC->CSR & RCC_RESET_FLAG_ALL; + + /* Clear Reset flags */ + RCC->CSR |= RCC_CSR_RMVF; + + return reset; +} + +/** + * @} + */ + +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ +/** @addtogroup RCC_Private_Functions + * @{ + */ + + +/** + * @brief Update number of Flash wait states in line with MSI range and current + voltage range. + * @param MSI_Range MSI range value from @ref RCC_MSIRANGE_0 to @ref RCC_MSIRANGE_11 + * @retval HAL status + */ +static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t MSI_Range) +{ + uint32_t flash_clksrcfreq; + uint32_t msifreq; + + /* MSI frequency range in Hz */ + msifreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSIRANGESEL_RUN, MSI_Range); + flash_clksrcfreq = __LL_RCC_CALC_HCLK3_FREQ(msifreq, LL_RCC_GetAHB3Prescaler()); + + return RCC_SetFlashLatency((flash_clksrcfreq / MEGA_HZ), HAL_PWREx_GetVoltageRange()); +} + + +/** + * @brief Update number of Flash wait states. + * @param Flash_ClkSrcFreq Flash Clock Source (in MHz) + * @param VCORE_Voltage Current Vcore voltage + * This parameter can be one of the following values: + * @arg PWR_REGULATOR_VOLTAGE_SCALE1 Regulator voltage output range 1 mode + * @arg PWR_REGULATOR_VOLTAGE_SCALE2 Regulator voltage output range 2 mode + * @retval HAL status + */ +static HAL_StatusTypeDef RCC_SetFlashLatency(uint32_t Flash_ClkSrcFreq, uint32_t VCORE_Voltage) +{ + /* Flash Clock source (HCLK3) range in MHz for VCORE range1 */ + const uint16_t FLASH_CLK_SRC_RANGE_VOS1[] = {18, 36, 48}; + + /* Flash Clock source (HCLK3) range in MHz for VCORE range2 */ + const uint16_t FLASH_CLK_SRC_RANGE_VOS2[] = {6, 12, 16}; + + /* Flash Latency range */ + const uint32_t FLASH_LATENCY_RANGE[] = {FLASH_LATENCY_0, FLASH_LATENCY_1, FLASH_LATENCY_2}; + + uint32_t latency = FLASH_LATENCY_0; /* default value 0WS */ + uint32_t tickstart; + + if (VCORE_Voltage == PWR_REGULATOR_VOLTAGE_SCALE1) + { + for (uint32_t index = 0; index < __COUNTOF(FLASH_CLK_SRC_RANGE_VOS1); index++) + { + if (Flash_ClkSrcFreq <= FLASH_CLK_SRC_RANGE_VOS1[index]) + { + latency = FLASH_LATENCY_RANGE[index]; + break; + } + } + } + else /* PWR_REGULATOR_VOLTAGE_SCALE2 */ + { + for (uint32_t index = 0; index < __COUNTOF(FLASH_CLK_SRC_RANGE_VOS2); index++) + { + if (Flash_ClkSrcFreq <= FLASH_CLK_SRC_RANGE_VOS2[index]) + { + latency = FLASH_LATENCY_RANGE[index]; + break; + } + } + } + + __HAL_FLASH_SET_LATENCY(latency); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + while (__HAL_FLASH_GET_LATENCY() != latency) + { + if ((HAL_GetTick() - tickstart) > LATENCY_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + return HAL_OK; +} + +/** + * @} + */ + +#endif /* HAL_RCC_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ diff --git a/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.c b/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.c new file mode 100644 index 0000000..c1aa0f3 --- /dev/null +++ b/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.c @@ -0,0 +1,1182 @@ +/** + ****************************************************************************** + * @file stm32wlxx_hal_rcc_ex.c + * @author MCD Application Team + * @brief Extended RCC HAL module driver. + * This file provides firmware functions to manage the following + * functionalities RCC extended peripheral: + * + Extended Peripheral Control functions + * + Extended Clock management functions + * + Extended Clock Recovery System Control functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wlxx_hal.h" + +/** @addtogroup STM32WLxx_HAL_Driver + * @{ + */ + +/** @defgroup RCCEx RCCEx + * @brief RCC Extended HAL module driver + * @{ + */ + +#ifdef HAL_RCC_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private defines -----------------------------------------------------------*/ +/** @defgroup RCCEx_Private_Constants RCCEx Private Constants + * @{ + */ +#define __LSCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE() +#define LSCO1_GPIO_PORT GPIOA +#define LSCO1_PIN GPIO_PIN_2 +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup RCCEx_Private_Functions RCCEx Private Functions + * @{ + */ +static uint32_t RCC_PLL_GetFreqDomain_P(void); +static uint32_t RCC_PLL_GetFreqDomain_Q(void); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions + * @{ + */ + +/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions + * @brief Extended Peripheral Control functions + * +@verbatim + =============================================================================== + ##### Extended Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the RCC Clocks + frequencies. + [..] + (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to + select the RTC clock source; in this case the Backup domain will be reset in + order to modify the RTC Clock source, as consequence RTC registers (including + the backup registers) and RCC_BDCR register are set to their reset values. + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the RCC extended peripherals clocks according to the specified + * parameters in the @ref RCC_PeriphCLKInitTypeDef. + * @param PeriphClkInit pointer to a @ref RCC_PeriphCLKInitTypeDef structure that + * contains a field PeriphClockSelection which can be a combination of the following values: + * @arg @ref RCC_PERIPHCLK_USART1 USART1 peripheral clock + * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock + * @arg @ref RCC_PERIPHCLK_LPUART1 LPUART1 peripheral clock + * @arg @ref RCC_PERIPHCLK_I2C1 I2C1 peripheral clock + * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock + * @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock + * @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock + * @arg @ref RCC_PERIPHCLK_LPTIM1 LPTIM1 peripheral clock + * @arg @ref RCC_PERIPHCLK_LPTIM2 LPTIM2 peripheral clock + * @arg @ref RCC_PERIPHCLK_LPTIM3 LPTIM3 peripheral clock + * @arg @ref RCC_PERIPHCLK_RNG RNG peripheral clock + * @arg @ref RCC_PERIPHCLK_ADC ADC peripheral clock + * @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock + * + * @note Care must be taken when @ref HAL_RCCEx_PeriphCLKConfig() is used to select + * the RTC clock source: in this case the access to Backup domain is enabled. + * + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) +{ + uint32_t tmpregister = 0; + uint32_t tickstart; + HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */ + HAL_StatusTypeDef status = HAL_OK; /* Final status */ + + /* Check the parameters */ + assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); + + /*-------------------------- RTC clock source configuration ----------------------*/ + if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) + { + + /* Check for RTC Parameters used to output RTCCLK */ + assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); + + + /* Enable write access to Backup domain */ + HAL_PWR_EnableBkUpAccess(); + + /* Wait for Backup domain Write protection disable */ + tickstart = HAL_GetTick(); + + while (!(READ_BIT(PWR->CR1, PWR_CR1_DBP) == (PWR_CR1_DBP))) + { + if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + { + ret = HAL_TIMEOUT; + break; + } + } + + if (ret == HAL_OK) + { + /* Reset the Backup domain only if the RTC Clock source selection is modified */ + if (LL_RCC_GetRTCClockSource() != PeriphClkInit->RTCClockSelection) + { + /* Store the content of BDCR register before the reset of Backup Domain */ + tmpregister = READ_BIT(RCC->BDCR, ~(RCC_BDCR_RTCSEL)); + + /* RTC Clock selection can be changed only if the Backup Domain is reset */ + __HAL_RCC_BACKUPRESET_FORCE(); + __HAL_RCC_BACKUPRESET_RELEASE(); + + /* Restore the Content of BDCR register */ + RCC->BDCR = tmpregister; + } + + /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */ + if (HAL_IS_BIT_SET(tmpregister, RCC_BDCR_LSERDY)) + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till LSE is ready */ + while (LL_RCC_LSE_IsReady() != 1U) + { + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + { + ret = HAL_TIMEOUT; + break; + } + } + } + + if (ret == HAL_OK) + { + /* Apply new RTC clock source selection */ + __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + else + { + /* set overall return value */ + status = ret; + } + + } + + /*-------------------- USART1 clock source configuration -------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) + { + /* Check the parameters */ + assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection)); + + /* Configure the USART1 clock source */ + __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection); + } + + /*-------------------- USART2 clock source configuration -------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) + { + /* Check the parameters */ + assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection)); + + /* Configure the USART2 clock source */ + __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection); + } + + /*-------------------- LPUART1 clock source configuration ------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) + { + /* Check the parameters */ + assert_param(IS_RCC_LPUART1CLKSOURCE(PeriphClkInit->Lpuart1ClockSelection)); + + /* Configure the LPUAR1 clock source */ + __HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection); + } + + /*-------------------- LPTIM1 clock source configuration -------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == (RCC_PERIPHCLK_LPTIM1)) + { + /* Check the parameters */ + assert_param(IS_RCC_LPTIM1CLKSOURCE(PeriphClkInit->Lptim1ClockSelection)); + + /* Configure the LPTIM1 clock source */ + __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection); + } + + /*-------------------- LPTIM2 clock source configuration -------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM2) == (RCC_PERIPHCLK_LPTIM2)) + { + /* Check the parameters */ + assert_param(IS_RCC_LPTIM2CLKSOURCE(PeriphClkInit->Lptim2ClockSelection)); + + /* Configure the LPTIM2 clock source */ + __HAL_RCC_LPTIM2_CONFIG(PeriphClkInit->Lptim2ClockSelection); + } + + /*-------------------- LPTIM3 clock source configuration -------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM3) == (RCC_PERIPHCLK_LPTIM3)) + { + /* Check the parameters */ + assert_param(IS_RCC_LPTIM3CLKSOURCE(PeriphClkInit->Lptim3ClockSelection)); + + /* Configure the LPTIM3 clock source */ + __HAL_RCC_LPTIM3_CONFIG(PeriphClkInit->Lptim3ClockSelection); + } + + /*-------------------- I2C1 clock source configuration ---------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) + { + /* Check the parameters */ + assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection)); + + /* Configure the I2C1 clock source */ + __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection); + } + + /*-------------------- I2C2 clock source configuration ---------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) + { + /* Check the parameters */ + assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection)); + + /* Configure the I2C2 clock source */ + __HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection); + } + + /*-------------------- I2C3 clock source configuration ---------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) + { + /* Check the parameters */ + assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection)); + + /* Configure the I2C3 clock source */ + __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection); + } + + /*-------------------- I2S2 clock source configuration ---------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S2) == (RCC_PERIPHCLK_I2S2)) + { + /* Check the parameters */ + assert_param(IS_RCC_I2S2CLKSOURCE(PeriphClkInit->I2s2ClockSelection)); + + /* Configure the I2S2 clock source */ + __HAL_RCC_I2S2_CONFIG(PeriphClkInit->I2s2ClockSelection); + + if (PeriphClkInit->I2s2ClockSelection == RCC_I2S2CLKSOURCE_PLL) + { + /* Enable RCC_PLL_I2S2CLK output */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_I2S2CLK); + } + } + + /*-------------------- RNG clock source configuration ----------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == (RCC_PERIPHCLK_RNG)) + { + assert_param(IS_RCC_RNGCLKSOURCE(PeriphClkInit->RngClockSelection)); + __HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection); + + if (PeriphClkInit->RngClockSelection == RCC_RNGCLKSOURCE_PLL) + { + /* Enable RCC_PLL_RNGCLK output */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_RNGCLK); + } + } + + /*-------------------- ADC clock source configuration ----------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) + { + /* Check the parameters */ + assert_param(IS_RCC_ADCCLKSOURCE(PeriphClkInit->AdcClockSelection)); + + /* Configure the ADC interface clock source */ + __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection); + + if (PeriphClkInit->AdcClockSelection == RCC_ADCCLKSOURCE_PLL) + { + /* Enable RCC_PLL_RNGCLK output */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_ADCCLK); + } + } + + return status; +} + + +/** + * @brief Get the RCC_ClkInitStruct according to the internal RCC configuration registers. + * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that + * returns the configuration information for the Extended Peripherals + * clocks(LPTIM1, LPTIM2, LPTIM3, I2C1, I2C2, I2C3, I2S2, LPUART1, + * USART1, USART2, RTC, ADC, RNG). + * @retval None + */ +void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) +{ + /* Set all possible values for the extended clock type parameter------------*/ + PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_I2S2 | \ + RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | \ + RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_LPTIM3 | \ + RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_RTC | \ + RCC_PERIPHCLK_LPUART1; + + /* Get the USART1 clock source ---------------------------------------------*/ + PeriphClkInit->Usart1ClockSelection = __HAL_RCC_GET_USART1_SOURCE(); + + /* Get the USART2 clock source ---------------------------------------------*/ + PeriphClkInit->Usart2ClockSelection = __HAL_RCC_GET_USART2_SOURCE(); + + /* Get the I2S2 clock source -----------------------------------------------*/ + PeriphClkInit->I2s2ClockSelection = __HAL_RCC_GET_I2S2_SOURCE(); + + /* Get the LPUART1 clock source --------------------------------------------*/ + PeriphClkInit->Lpuart1ClockSelection = __HAL_RCC_GET_LPUART1_SOURCE(); + + /* Get the I2C1 clock source -----------------------------------------------*/ + PeriphClkInit->I2c1ClockSelection = __HAL_RCC_GET_I2C1_SOURCE(); + + /* Get the I2C2 clock source -----------------------------------------------*/ + PeriphClkInit->I2c2ClockSelection = __HAL_RCC_GET_I2C2_SOURCE(); + + /* Get the I2C3 clock source -----------------------------------------------*/ + PeriphClkInit->I2c3ClockSelection = __HAL_RCC_GET_I2C3_SOURCE(); + + /* Get the LPTIM1 clock source ---------------------------------------------*/ + PeriphClkInit->Lptim1ClockSelection = __HAL_RCC_GET_LPTIM1_SOURCE(); + + /* Get the LPTIM2 clock source ---------------------------------------------*/ + PeriphClkInit->Lptim2ClockSelection = __HAL_RCC_GET_LPTIM2_SOURCE(); + + /* Get the LPTIM3 clock source ---------------------------------------------*/ + PeriphClkInit->Lptim3ClockSelection = __HAL_RCC_GET_LPTIM3_SOURCE(); + + /* Get the RTC clock source ------------------------------------------------*/ + PeriphClkInit->RTCClockSelection = __HAL_RCC_GET_RTC_SOURCE(); + + /* Get the RNG clock source ------------------------------------------------*/ + PeriphClkInit->RngClockSelection = __HAL_RCC_GET_RNG_SOURCE(); + + /* Get the ADC clock source ------------------------------------------------*/ + PeriphClkInit->AdcClockSelection = __HAL_RCC_GET_ADC_SOURCE(); + +} + +/** + * @brief Return the peripheral clock frequency for peripherals with clock source + * @note Return 0 if peripheral clock identifier not managed by this API + * @param PeriphClk Peripheral clock identifier + * This parameter can be one of the following values: + * @arg @ref RCC_PERIPHCLK_USART1 USART1 peripheral clock + * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock + * @arg @ref RCC_PERIPHCLK_LPUART1 LPUART1 peripheral clock + * @arg @ref RCC_PERIPHCLK_I2C1 I2C1 peripheral clock + * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock + * @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock + * @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock + * @arg @ref RCC_PERIPHCLK_LPTIM1 LPTIM1 peripheral clock + * @arg @ref RCC_PERIPHCLK_LPTIM2 LPTIM2 peripheral clock + * @arg @ref RCC_PERIPHCLK_LPTIM3 LPTIM3 peripheral clock + * @arg @ref RCC_PERIPHCLK_RNG RNG peripheral clock + * @arg @ref RCC_PERIPHCLK_ADC ADC peripheral clock + * @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock + * + * @retval Frequency in Hz + */ +uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) +{ + uint32_t frequency = 0U; + uint32_t srcclk; + + /* Check the parameters */ + assert_param(IS_RCC_PERIPHCLOCK(PeriphClk)); + + switch (PeriphClk) + { + case RCC_PERIPHCLK_RTC: + + /* Get the current RTC source */ + srcclk = LL_RCC_GetRTCClockSource(); + + switch (srcclk) + { + case LL_RCC_RTC_CLKSOURCE_LSE: /* LSE clock used as RTC clock source */ + if (LL_RCC_LSE_IsReady() == 1U) + { + frequency = LSE_VALUE; + } + break; + + case LL_RCC_RTC_CLKSOURCE_LSI: /* LSI clock used as RTC clock source */ + if (LL_RCC_LSI_IsReady() == 1U) + { + if (LL_RCC_LSI_GetPrediv() == LL_RCC_LSI_PREDIV_128) + { + frequency = LSI_VALUE / 128U; + } + else + { + frequency = LSI_VALUE; + } + } + break; + + case LL_RCC_RTC_CLKSOURCE_HSE_DIV32: /* HSE/32 clock used as RTC clock source */ + frequency = HSE_VALUE / 32U; + break; + + case LL_RCC_RTC_CLKSOURCE_NONE: /* No clock used as RTC clock source */ + default: + /* No clock source, frequency default init at 0 */ + break; + } + break; + + case RCC_PERIPHCLK_RNG: + + /* Get the current RTC source */ + srcclk = LL_RCC_GetRNGClockSource(LL_RCC_RNG_CLKSOURCE); + + switch (srcclk) + { + case LL_RCC_RNG_CLKSOURCE_PLL: /* PLL clock used as RNG clock source */ + if (LL_RCC_PLL_IsReady() == 1U) + { + frequency = RCC_PLL_GetFreqDomain_Q(); + } + break; + + case LL_RCC_RNG_CLKSOURCE_LSI: /* LSI clock used as RNG clock source */ + if (LL_RCC_LSI_IsReady() == 1U) + { + if (LL_RCC_LSI_GetPrediv() == LL_RCC_LSI_PREDIV_128) + { + frequency = LSI_VALUE / 128U; + } + else + { + frequency = LSI_VALUE; + } + } + break; + + case LL_RCC_RNG_CLKSOURCE_LSE: /* LSE clock used as RNG clock source */ + if (LL_RCC_LSE_IsReady() == 1U) + { + frequency = LSE_VALUE; + } + break; + + case LL_RCC_RNG_CLKSOURCE_MSI: /* MSI clock used as RNG clock source */ + default: + if (LL_RCC_MSI_IsReady() == 1U) + { + frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), + ((LL_RCC_MSI_IsEnabledRangeSelect() == 1U) ? + LL_RCC_MSI_GetRange() : + LL_RCC_MSI_GetRangeAfterStandby())); + } + break; + } + break; + + case RCC_PERIPHCLK_USART1: + + /* Get the current USART1 source */ + srcclk = LL_RCC_GetUSARTClockSource(LL_RCC_USART1_CLKSOURCE); + + switch (srcclk) + { + case LL_RCC_USART1_CLKSOURCE_SYSCLK: /* USART1 Clock is System Clock */ + frequency = HAL_RCC_GetSysClockFreq(); + break; + + case LL_RCC_USART1_CLKSOURCE_HSI: /* USART1 Clock is HSI Osc. */ + if (LL_RCC_HSI_IsReady() == 1U) + { + frequency = HSI_VALUE; + } + break; + + case LL_RCC_USART1_CLKSOURCE_LSE: /* USART1 Clock is LSE Osc. */ + if (LL_RCC_LSE_IsReady() == 1U) + { + frequency = LSE_VALUE; + } + break; + + case LL_RCC_USART1_CLKSOURCE_PCLK2: /* USART1 Clock is PCLK2 */ + default: + frequency = __LL_RCC_CALC_PCLK2_FREQ(__LL_RCC_CALC_HCLK1_FREQ(HAL_RCC_GetSysClockFreq(), \ + LL_RCC_GetAHBPrescaler()), \ + LL_RCC_GetAPB2Prescaler()); + break; + } + break; + + case RCC_PERIPHCLK_USART2: + + /* Get the current USART2 source */ + srcclk = LL_RCC_GetUSARTClockSource(LL_RCC_USART2_CLKSOURCE); + + switch (srcclk) + { + case LL_RCC_USART2_CLKSOURCE_SYSCLK: /* USART2 Clock is System Clock */ + frequency = HAL_RCC_GetSysClockFreq(); + break; + + case LL_RCC_USART2_CLKSOURCE_HSI: /* USART2 Clock is HSI Osc. */ + if (LL_RCC_HSI_IsReady() == 1U) + { + frequency = HSI_VALUE; + } + break; + + case LL_RCC_USART2_CLKSOURCE_LSE: /* USART2 Clock is LSE Osc. */ + if (LL_RCC_LSE_IsReady() == 1U) + { + frequency = LSE_VALUE; + } + break; + + case LL_RCC_USART2_CLKSOURCE_PCLK1: /* USART2 Clock is PCLK1 */ + default: + frequency = __LL_RCC_CALC_PCLK1_FREQ(__LL_RCC_CALC_HCLK1_FREQ(HAL_RCC_GetSysClockFreq(), \ + LL_RCC_GetAHBPrescaler()), \ + LL_RCC_GetAPB1Prescaler()); + break; + } + break; + + case RCC_PERIPHCLK_LPUART1: + + /* Get the current LPUART1 source */ + srcclk = LL_RCC_GetLPUARTClockSource(LL_RCC_LPUART1_CLKSOURCE); + + switch (srcclk) + { + case LL_RCC_LPUART1_CLKSOURCE_SYSCLK: /* LPUART1 Clock is System Clock */ + frequency = HAL_RCC_GetSysClockFreq(); + break; + + case LL_RCC_LPUART1_CLKSOURCE_HSI: /* LPUART1 Clock is HSI Osc. */ + if (LL_RCC_HSI_IsReady() == 1U) + { + frequency = HSI_VALUE; + } + break; + + case LL_RCC_LPUART1_CLKSOURCE_LSE: /* LPUART1 Clock is LSE Osc. */ + if (LL_RCC_LSE_IsReady() == 1U) + { + frequency = LSE_VALUE; + } + break; + + case LL_RCC_LPUART1_CLKSOURCE_PCLK1: /* LPUART1 Clock is PCLK1 */ + default: + frequency = __LL_RCC_CALC_PCLK1_FREQ(__LL_RCC_CALC_HCLK1_FREQ(HAL_RCC_GetSysClockFreq(), \ + LL_RCC_GetAHBPrescaler()), \ + LL_RCC_GetAPB1Prescaler()); + break; + } + + break; + + case RCC_PERIPHCLK_ADC: + + /* Get the current ADC source */ + srcclk = LL_RCC_GetADCClockSource(LL_RCC_ADC_CLKSOURCE); + + switch (srcclk) + { + case LL_RCC_ADC_CLKSOURCE_HSI: /* HSI Osc. used as ADC clock source */ + if (LL_RCC_HSI_IsReady() == 1U) + { + frequency = HSI_VALUE; + } + break; + + + case LL_RCC_ADC_CLKSOURCE_SYSCLK: /* SYSCLK clock used as ADC clock source */ + frequency = HAL_RCC_GetSysClockFreq(); + break; + + case LL_RCC_ADC_CLKSOURCE_PLL: /* PLL clock used as ADC clock source */ + if (LL_RCC_PLL_IsReady() == 1U) + { + frequency = RCC_PLL_GetFreqDomain_P(); + } + break; + + case LL_RCC_ADC_CLKSOURCE_NONE: /* No clock used as ADC clock source */ + default: + /* No clock source, frequency default init at 0 */ + break; + } + break; + + case RCC_PERIPHCLK_I2C1: + + /* Get the current I2C1 source */ + srcclk = LL_RCC_GetI2CClockSource(LL_RCC_I2C1_CLKSOURCE); + + switch (srcclk) + { + case LL_RCC_I2C1_CLKSOURCE_SYSCLK: /* I2C1 Clock is System Clock */ + frequency = HAL_RCC_GetSysClockFreq(); + break; + + case LL_RCC_I2C1_CLKSOURCE_HSI: /* I2C1 Clock is HSI Osc. */ + if (LL_RCC_HSI_IsReady() == 1U) + { + frequency = HSI_VALUE; + } + break; + + case LL_RCC_I2C1_CLKSOURCE_PCLK1: /* I2C1 Clock is PCLK1 */ + default: + frequency = __LL_RCC_CALC_PCLK1_FREQ(__LL_RCC_CALC_HCLK1_FREQ(HAL_RCC_GetSysClockFreq(), \ + LL_RCC_GetAHBPrescaler()), \ + LL_RCC_GetAPB1Prescaler()); + break; + } + break; + + case RCC_PERIPHCLK_I2C2: + + /* Get the current I2C2 source */ + srcclk = LL_RCC_GetI2CClockSource(LL_RCC_I2C2_CLKSOURCE); + + switch (srcclk) + { + case LL_RCC_I2C2_CLKSOURCE_SYSCLK: /* I2C2 Clock is System Clock */ + frequency = HAL_RCC_GetSysClockFreq(); + break; + + case LL_RCC_I2C2_CLKSOURCE_HSI: /* I2C2 Clock is HSI Osc. */ + if (LL_RCC_HSI_IsReady() == 1U) + { + frequency = HSI_VALUE; + } + break; + + case LL_RCC_I2C2_CLKSOURCE_PCLK1: /* I2C2 Clock is PCLK1 */ + default: + frequency = __LL_RCC_CALC_PCLK1_FREQ(__LL_RCC_CALC_HCLK1_FREQ(HAL_RCC_GetSysClockFreq(), \ + LL_RCC_GetAHBPrescaler()), \ + LL_RCC_GetAPB1Prescaler()); + break; + } + break; + + case RCC_PERIPHCLK_I2C3: + + /* Get the current I2C3 source */ + srcclk = LL_RCC_GetI2CClockSource(LL_RCC_I2C3_CLKSOURCE); + + switch (srcclk) + { + case LL_RCC_I2C3_CLKSOURCE_SYSCLK: /* I2C3 Clock is System Clock */ + frequency = HAL_RCC_GetSysClockFreq(); + break; + + case LL_RCC_I2C3_CLKSOURCE_HSI: /* I2C3 Clock is HSI Osc. */ + if (LL_RCC_HSI_IsReady() == 1U) + { + frequency = HSI_VALUE; + } + break; + + case LL_RCC_I2C3_CLKSOURCE_PCLK1: /* I2C3 Clock is PCLK1 */ + default: + frequency = __LL_RCC_CALC_PCLK1_FREQ(__LL_RCC_CALC_HCLK1_FREQ(HAL_RCC_GetSysClockFreq(), \ + LL_RCC_GetAHBPrescaler()), \ + LL_RCC_GetAPB1Prescaler()); + break; + } + break; + + case RCC_PERIPHCLK_I2S2: + + /* Get the current I2S2 source */ + srcclk = LL_RCC_GetI2SClockSource(LL_RCC_I2S2_CLKSOURCE); + + switch (srcclk) + { + case LL_RCC_I2S2_CLKSOURCE_PIN: /* I2S2 Clock is External clock */ + frequency = EXTERNAL_CLOCK_VALUE; + break; + + case LL_RCC_I2S2_CLKSOURCE_HSI: /* I2S2 Clock is HSI Osc. */ + if (LL_RCC_HSI_IsReady() == 1U) + { + frequency = HSI_VALUE; + } + break; + + case LL_RCC_I2S2_CLKSOURCE_PLL: /* I2S2 Clock is PLL */ + default: + frequency = RCC_PLL_GetFreqDomain_Q(); + break; + } + break; + + case RCC_PERIPHCLK_LPTIM1: + + /* Get the current LPTIM1 source */ + srcclk = LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM1_CLKSOURCE); + + switch (srcclk) + { + case LL_RCC_LPTIM1_CLKSOURCE_LSI: /* LPTIM1 Clock is LSI Osc. */ + if (LL_RCC_LSI_IsReady() == 1U) + { + if (LL_RCC_LSI_GetPrediv() == LL_RCC_LSI_PREDIV_128) + { + frequency = LSI_VALUE / 128U; + } + else + { + frequency = LSI_VALUE; + } + } + break; + + case LL_RCC_LPTIM1_CLKSOURCE_HSI: /* LPTIM1 Clock is HSI Osc. */ + if (LL_RCC_HSI_IsReady() == 1U) + { + frequency = HSI_VALUE; + } + break; + + case LL_RCC_LPTIM1_CLKSOURCE_LSE: /* LPTIM1 Clock is LSE Osc. */ + if (LL_RCC_LSE_IsReady() == 1U) + { + frequency = LSE_VALUE; + } + break; + + case LL_RCC_LPTIM1_CLKSOURCE_PCLK1: /* LPTIM1 Clock is PCLK1 */ + default: + frequency = __LL_RCC_CALC_PCLK1_FREQ(__LL_RCC_CALC_HCLK1_FREQ(HAL_RCC_GetSysClockFreq(), \ + LL_RCC_GetAHBPrescaler()), \ + LL_RCC_GetAPB1Prescaler()); + break; + } + break; + + case RCC_PERIPHCLK_LPTIM2: + + /* Get the current LPTIM2 source */ + srcclk = LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM2_CLKSOURCE); + + switch (srcclk) + { + case LL_RCC_LPTIM2_CLKSOURCE_LSI: /* LPTIM2 Clock is LSI Osc. */ + if (LL_RCC_LSI_IsReady() == 1U) + { + if (LL_RCC_LSI_GetPrediv() == LL_RCC_LSI_PREDIV_128) + { + frequency = LSI_VALUE / 128U; + } + else + { + frequency = LSI_VALUE; + } + } + break; + + case LL_RCC_LPTIM2_CLKSOURCE_HSI: /* LPTIM2 Clock is HSI Osc. */ + if (LL_RCC_HSI_IsReady() == 1U) + { + frequency = HSI_VALUE; + } + break; + + case LL_RCC_LPTIM2_CLKSOURCE_LSE: /* LPTIM2 Clock is LSE Osc. */ + if (LL_RCC_LSE_IsReady() == 1U) + { + frequency = LSE_VALUE; + } + break; + + case LL_RCC_LPTIM2_CLKSOURCE_PCLK1: /* LPTIM2 Clock is PCLK1 */ + default: + frequency = __LL_RCC_CALC_PCLK1_FREQ(__LL_RCC_CALC_HCLK1_FREQ(HAL_RCC_GetSysClockFreq(), \ + LL_RCC_GetAHBPrescaler()), \ + LL_RCC_GetAPB1Prescaler()); + break; + } + + break; + + case RCC_PERIPHCLK_LPTIM3: + + /* Get the current LPTIM3 source */ + srcclk = LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM3_CLKSOURCE); + + switch (srcclk) + { + case LL_RCC_LPTIM3_CLKSOURCE_LSI: /* LPTIM3 Clock is LSI Osc. */ + if (LL_RCC_LSI_IsReady() == 1U) + { + if (LL_RCC_LSI_GetPrediv() == LL_RCC_LSI_PREDIV_128) + { + frequency = LSI_VALUE / 128U; + } + else + { + frequency = LSI_VALUE; + } + } + break; + + case LL_RCC_LPTIM3_CLKSOURCE_HSI: /* LPTIM3 Clock is HSI Osc. */ + if (LL_RCC_HSI_IsReady() == 1U) + { + frequency = HSI_VALUE; + } + break; + + case LL_RCC_LPTIM3_CLKSOURCE_LSE: /* LPTIM3 Clock is LSE Osc. */ + if (LL_RCC_LSE_IsReady() == 1U) + { + frequency = LSE_VALUE; + } + break; + + case LL_RCC_LPTIM3_CLKSOURCE_PCLK1: /* LPTIM3 Clock is PCLK1 */ + default: + frequency = __LL_RCC_CALC_PCLK1_FREQ(__LL_RCC_CALC_HCLK1_FREQ(HAL_RCC_GetSysClockFreq(), \ + LL_RCC_GetAHBPrescaler()), \ + LL_RCC_GetAPB1Prescaler()); + break; + } + + break; + + default: + /* Unknown periphclk, frequency default init at 0 */ + break; + } + + return (frequency); +} + +/** + * @} + */ + +/** @defgroup RCCEx_Exported_Functions_Group2 Extended Clock management functions + * @brief Extended Clock management functions + * +@verbatim + =============================================================================== + ##### Extended clock management functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the + activation or deactivation of MSI PLL-mode, LSE CSS, + Low speed clock output and clock after wake-up from STOP mode. +@endverbatim + * @{ + */ + +/******************************************************************************/ + +/** + * @brief Configure the oscillator clock source for wakeup from Stop and CSS backup clock. + * @param WakeUpClk Wakeup clock + * This parameter can be one of the following values: + * @arg @ref RCC_STOP_WAKEUPCLOCK_MSI MSI oscillator selection + * @arg @ref RCC_STOP_WAKEUPCLOCK_HSI HSI oscillator selection + * @note This function shall not be called after the Clock Security System on HSE has been + * enabled. + * @retval None + */ +void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk) +{ + assert_param(IS_RCC_STOP_WAKEUPCLOCK(WakeUpClk)); + + __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(WakeUpClk); +} + +/** + * @brief Enable the LSE Clock Security System. + * @note Prior to enable the LSE Clock Security System, LSE oscillator has to be enabled + * with HAL_RCC_OscConfig() and the LSE oscillator clock has to be selected as RTC + * clock with HAL_RCCEx_PeriphCLKConfig(). + * @retval None + */ +void HAL_RCCEx_EnableLSECSS(void) +{ + LL_RCC_LSE_EnableCSS(); +} + +/** + * @brief Disable the LSE Clock Security System. + * @note LSE Clock Security System can only be disabled after a LSE failure detection. + * @retval None + */ +void HAL_RCCEx_DisableLSECSS(void) +{ + LL_RCC_LSE_DisableCSS(); + + /* Disable LSE CSS IT if any */ + __HAL_RCC_DISABLE_IT(RCC_IT_LSECSS); +} + +/** + * @brief Enable the LSE Clock Security System Interrupt & corresponding EXTI line. + * @note Prior to enable the LSE Clock Security System, LSE oscillator has to be enabled + * with HAL_RCC_OscConfig() and the LSE oscillator clock has to be selected as RTC + * clock with HAL_RCCEx_PeriphCLKConfig(). + * @note LSE Clock Security System Interrupt is mapped on RTC EXTI line 19 + * @retval None + */ +void HAL_RCCEx_EnableLSECSS_IT(void) +{ + /* Enable LSE CSS */ + LL_RCC_LSE_EnableCSS(); + + /* Enable LSE CSS IT */ + __HAL_RCC_ENABLE_IT(RCC_IT_LSECSS); + + /* Enable IT on EXTI Line 19 */ + __HAL_RCC_LSECSS_EXTI_ENABLE_IT(); + +} + +/** + * @brief Handle the RCC LSE Clock Security System interrupt request. + * @note Clearing the interrupt flag is under aplication's responsibility. + * This should be part of clock recovery strategy when waking up the + * system. + * @retval None + */ +void HAL_RCCEx_LSECSS_IRQHandler(void) +{ + /* Check RCC LSE CSSF flag */ + if (__HAL_RCC_GET_IT(RCC_IT_LSECSS)) + { + + /* RCC LSE Clock Security System interrupt user callback */ + HAL_RCCEx_LSECSS_Callback(); + } +} + +/** + * @brief RCCEx LSE Clock Security System interrupt callback. + * @retval none + */ +__weak void HAL_RCCEx_LSECSS_Callback(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the @ref HAL_RCCEx_LSECSS_Callback should be implemented in the user file + */ +} + +/** + * @brief Select the Low Speed clock source to output on LSCO pin (PA2). + * @param LSCOSource specifies the Low Speed clock source to output. + * This parameter can be one of the following values: + * @arg @ref RCC_LSCOSOURCE_LSI LSI clock selected as LSCO source + * @arg @ref RCC_LSCOSOURCE_LSE LSE clock selected as LSCO source + * @retval None + */ +void HAL_RCCEx_EnableLSCO(uint32_t LSCOSource) +{ + /* Check the parameters */ + assert_param(IS_RCC_LSCOSOURCE(LSCOSource)); + + /* Update LSCO selection according to parameter and enable LSCO */ + MODIFY_REG(RCC->BDCR, RCC_BDCR_LSCOSEL | RCC_BDCR_LSCOEN, LSCOSource | RCC_BDCR_LSCOEN); +} + +/** + * @brief Disable the Low Speed clock output. + * @retval None + */ +void HAL_RCCEx_DisableLSCO(void) +{ + /* Clear LSCOEN in BDCR register */ + LL_RCC_LSCO_Disable(); +} + +/** + * @brief Enable the PLL-mode of the MSI. + * @note Prior to enable the PLL-mode of the MSI for automatic hardware + * calibration LSE oscillator has to be enabled with @ref HAL_RCC_OscConfig(). + * @retval None + */ +void HAL_RCCEx_EnableMSIPLLMode(void) +{ + LL_RCC_MSI_EnablePLLMode() ; +} + +/** + * @brief Disable the PLL-mode of the MSI. + * @note PLL-mode of the MSI is automatically reset when LSE oscillator is disabled. + * @retval None + */ +void HAL_RCCEx_DisableMSIPLLMode(void) +{ + LL_RCC_MSI_DisablePLLMode() ; +} + +/** + * @} + */ + + +/** + * @} + */ + +/** @addtogroup RCCEx_Private_Functions + * @{ + */ + +/** + * @brief Return PLL clock (PLLPCLK) frequency used for ADC domain + * @retval PLLPCLK clock frequency (in Hz) + */ +static uint32_t RCC_PLL_GetFreqDomain_P(void) +{ + uint32_t pllinputfreq; + uint32_t pllsource; + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI Value / PLLM) * PLLN + * ADC Domain clock = PLL_VCO / PLLP + */ + pllsource = LL_RCC_PLL_GetMainSource(); + + switch (pllsource) + { + case LL_RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */ + pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), + ((LL_RCC_MSI_IsEnabledRangeSelect() == 1U) ? + LL_RCC_MSI_GetRange() : + LL_RCC_MSI_GetRangeAfterStandby())); + break; + + case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ + pllinputfreq = HSI_VALUE; + break; + + case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ + if (LL_RCC_HSE_IsEnabledDiv2() == 1U) + { + pllinputfreq = HSE_VALUE / 2U; + } + else + { + pllinputfreq = HSE_VALUE; + } + break; + + default: + pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), + ((LL_RCC_MSI_IsEnabledRangeSelect() == 1U) ? + LL_RCC_MSI_GetRange() : + LL_RCC_MSI_GetRangeAfterStandby())); + break; + } + return __LL_RCC_CALC_PLLCLK_ADC_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(), + LL_RCC_PLL_GetN(), LL_RCC_PLL_GetP()); +} + + +/** + * @brief Return PLL clock (PLLQCLK) frequency used for 48 MHz domain + * @retval PLLQCLK clock frequency (in Hz) + */ +static uint32_t RCC_PLL_GetFreqDomain_Q(void) +{ + uint32_t pllinputfreq; + uint32_t pllsource; + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI Value/ PLLM) * PLLN + * 48M Domain clock = PLL_VCO / PLLQ + */ + pllsource = LL_RCC_PLL_GetMainSource(); + + switch (pllsource) + { + case LL_RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */ + pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), + ((LL_RCC_MSI_IsEnabledRangeSelect() == 1U) ? + LL_RCC_MSI_GetRange() : + LL_RCC_MSI_GetRangeAfterStandby())); + break; + + case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ + pllinputfreq = HSI_VALUE; + break; + + case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ + if (LL_RCC_HSE_IsEnabledDiv2() == 1U) + { + pllinputfreq = HSE_VALUE / 2U; + } + else + { + pllinputfreq = HSE_VALUE; + } + break; + + default: + pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), + ((LL_RCC_MSI_IsEnabledRangeSelect() == 1U) ? + LL_RCC_MSI_GetRange() : + LL_RCC_MSI_GetRangeAfterStandby())); + break; + } + return __LL_RCC_CALC_PLLCLK_RNG_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(), + LL_RCC_PLL_GetN(), LL_RCC_PLL_GetQ()); +} + + +/** + * @} + */ + +#endif /* HAL_RCC_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ diff --git a/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.c b/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.c new file mode 100644 index 0000000..939c08f --- /dev/null +++ b/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.c @@ -0,0 +1,1988 @@ +/** + ****************************************************************************** + * @file stm32wlxx_hal_rtc.c + * @author MCD Application Team + * @brief RTC HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Real-Time Clock (RTC) peripheral: + * + Initialization/de-initialization functions + * + Calendar (Time and Date) configuration + * + Alarms (Alarm A and Alarm B) configuration + * + WakeUp Timer configuration + * + TimeStamp configuration + * + Tampers configuration + * + Backup Data Registers configuration + * + RTC Tamper and TimeStamp Pins Selection + * + Interrupts and flags management + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + =============================================================================== + ##### RTC Operating Condition ##### + =============================================================================== + [..] The real-time clock (RTC) and the RTC backup registers can be powered + from the VBAT voltage when the main VDD supply is powered off. + To retain the content of the RTC backup registers and supply the RTC + when VDD is turned off, VBAT pin can be connected to an optional + standby voltage supplied by a battery or by another source. + + ##### Backup Domain Reset ##### + =============================================================================== + [..] The backup domain reset sets all RTC registers and the RCC_BDCR register + to their reset values. + A backup domain reset is generated when one of the following events occurs: + (#) Software reset, triggered by setting the BDRST bit in the + RCC Backup domain control register (RCC_BDCR). + (#) VDD or VBAT power on, if both supplies have previously been powered off. + (#) Tamper detection event resets all data backup registers. + + ##### Backup Domain Access ##### + ================================================================== + [..] After reset, the backup domain (RTC registers and RTC backup data registers) + is protected against possible unwanted write accesses. + [..] To enable access to the RTC Domain and RTC registers, proceed as follows: + (+) Enable the Power Controller (PWR) APB1 interface clock using the + __HAL_RCC_PWR_CLK_ENABLE() function. + (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function. + (+) Select the RTC clock source using the __HAL_RCC_RTC_CONFIG() function. + (+) Enable RTC Clock using the __HAL_RCC_RTC_ENABLE() function. + + [..] To enable access to the RTC Domain and RTC registers, proceed as follows: + (#) Call the function HAL_RCCEx_PeriphCLKConfig with RCC_PERIPHCLK_RTC for + PeriphClockSelection and select RTCClockSelection (LSE, LSI or HSEdiv32) + (#) Enable RTC Clock using the __HAL_RCC_RTC_ENABLE() macro. + + ##### How to use RTC Driver ##### + =================================================================== + [..] + (+) Enable the RTC domain access (see description in the section above). + (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour + format using the HAL_RTC_Init() function. + + *** Time and Date configuration *** + =================================== + [..] + (+) To configure the RTC Calendar (Time and Date) use the HAL_RTC_SetTime() + and HAL_RTC_SetDate() functions. + (+) To read the RTC Calendar, use the HAL_RTC_GetTime() and HAL_RTC_GetDate() functions. + + *** Alarm configuration *** + =========================== + [..] + (+) To configure the RTC Alarm use the HAL_RTC_SetAlarm() function. + You can also configure the RTC Alarm with interrupt mode using the + HAL_RTC_SetAlarm_IT() function. + (+) To read the RTC Alarm, use the HAL_RTC_GetAlarm() function. + + ##### RTC and low power modes ##### + ================================================================== + [..] The MCU can be woken up from a low power mode by an RTC alternate + function. + [..] The RTC alternate functions are the RTC alarms (Alarm A and Alarm B), + RTC wakeup, RTC tamper event detection and RTC time stamp event detection. + These RTC alternate functions can wake up the system from the Stop and + Standby low power modes. + [..] The system can also wake up from low power modes without depending + on an external interrupt (Auto-wakeup mode), by using the RTC alarm + or the RTC wakeup events. + [..] The RTC provides a programmable time base for waking up from the + Stop or Standby mode at regular intervals. + Wakeup from STOP and STANDBY modes is possible only when the RTC clock source + is LSE or LSI. + + *** Callback registration *** + ============================================= + When The compilation define USE_HAL_RTC_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. This is the recommended configuration + in order to optimize memory/code consumption footprint/performances. + + The compilation define USE_RTC_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + Use Function HAL_RTC_RegisterCallback() to register an interrupt callback. + + Function HAL_RTC_RegisterCallback() allows to register following callbacks: + (+) AlarmAEventCallback : RTC Alarm A Event callback. + (+) AlarmBEventCallback : RTC Alarm B Event callback. + (+) TimeStampEventCallback : RTC TimeStamp Event callback. + (+) WakeUpTimerEventCallback : RTC WakeUpTimer Event callback. + (+) SSRUEventCallback : RTC SSRU Event callback. + (+) Tamper1EventCallback : RTC Tamper 1 Event callback. + (+) Tamper2EventCallback : RTC Tamper 2 Event callback. + (+) Tamper3EventCallback : RTC Tamper 3 Event callback. + (+) InternalTamper3EventCallback : RTC InternalTamper 3 Event callback. + (+) InternalTamper5EventCallback : RTC InternalTamper 5 Event callback. + (+) InternalTamper8EventCallback : RTC InternalTamper 6 Event callback. + (+) InternalTamper8EventCallback : RTC InternalTamper 8 Event callback. + (+) MspInitCallback : RTC MspInit callback. + (+) MspDeInitCallback : RTC MspDeInit callback. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + Use function HAL_RTC_UnRegisterCallback() to reset a callback to the default + weak function. + HAL_RTC_UnRegisterCallback() takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) AlarmAEventCallback : RTC Alarm A Event callback. + (+) AlarmBEventCallback : RTC Alarm B Event callback. + (+) TimeStampEventCallback : RTC TimeStamp Event callback. + (+) WakeUpTimerEventCallback : RTC WakeUpTimer Event callback. + (+) SSRUEventCallback : RTC SSRU Event callback. + (+) Tamper1EventCallback : RTC Tamper 1 Event callback. + (+) Tamper2EventCallback : RTC Tamper 2 Event callback. + (+) Tamper3EventCallback : RTC Tamper 3 Event callback. + (+) InternalTamper3EventCallback : RTC Internal Tamper 3 Event callback. + (+) InternalTamper5EventCallback : RTC Internal Tamper 5 Event callback. + (+) InternalTamper8EventCallback : RTC Internal Tamper 6 Event callback. + (+) InternalTamper8EventCallback : RTC Internal Tamper 8 Event callback. + (+) MspInitCallback : RTC MspInit callback. + (+) MspDeInitCallback : RTC MspDeInit callback. + + By default, after the HAL_RTC_Init() and when the state is HAL_RTC_STATE_RESET, + all callbacks are set to the corresponding weak functions : + examples AlarmAEventCallback(), TimeStampEventCallback(). + Exception done for MspInit and MspDeInit callbacks that are reset to the legacy weak function + in the HAL_RTC_Init()/HAL_RTC_DeInit() only when these callbacks are null + (not registered beforehand). + If not, MspInit or MspDeInit are not null, HAL_RTC_Init()/HAL_RTC_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) + + Callbacks can be registered/unregistered in HAL_RTC_STATE_READY state only. + Exception done MspInit/MspDeInit that can be registered/unregistered + in HAL_RTC_STATE_READY or HAL_RTC_STATE_RESET state, + thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using HAL_RTC_RegisterCallback() before calling HAL_RTC_DeInit() + or HAL_RTC_Init() function. + + When The compilation define USE_HAL_RTC_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wlxx_hal.h" + +/** @addtogroup STM32WLxx_HAL_Driver + * @{ + */ + + +/** @addtogroup RTC + * @brief RTC HAL module driver + * @{ + */ + +#ifdef HAL_RTC_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup RTC_Exported_Functions + * @{ + */ + +/** @addtogroup RTC_Exported_Functions_Group1 + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This section provides functions allowing to initialize and configure the + RTC Prescaler (Synchronous and Asynchronous), RTC Hour format, disable + RTC registers Write protection, enter and exit the RTC initialization mode, + RTC registers synchronization check and reference clock detection enable. + (#) The RTC Prescaler is programmed to generate the RTC 1Hz time base. + It is split into 2 programmable prescalers to minimize power consumption. + (++) A 7-bit asynchronous prescaler and a 15-bit synchronous prescaler. + (++) When both prescalers are used, it is recommended to configure the + asynchronous prescaler to a high value to minimize power consumption. + (#) All RTC registers are Write protected. Writing to the RTC registers + is enabled by writing a key into the Write Protection register, RTC_WPR. + (#) To configure the RTC Calendar, user application should enter + initialization mode. In this mode, the calendar counter is stopped + and its value can be updated. When the initialization sequence is + complete, the calendar restarts counting after 4 RTCCLK cycles. + (#) To read the calendar through the shadow registers after Calendar + initialization, calendar update or after wakeup from low power modes + the software must first clear the RSF flag. The software must then + wait until it is set again before reading the calendar, which means + that the calendar registers have been correctly copied into the + RTC_TR and RTC_DR shadow registers.The HAL_RTC_WaitForSynchro() function + implements the above software sequence (RSF clear and RSF check). + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the RTC peripheral + * @param hrtc RTC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc) +{ + HAL_StatusTypeDef status = HAL_ERROR; + + /* Check the RTC peripheral state */ + if (hrtc != NULL) + { + /* Check the parameters */ + assert_param(IS_RTC_HOUR_FORMAT(hrtc->Init.HourFormat)); + assert_param(IS_RTC_ASYNCH_PREDIV(hrtc->Init.AsynchPrediv)); + assert_param(IS_RTC_SYNCH_PREDIV(hrtc->Init.SynchPrediv)); + assert_param(IS_RTC_OUTPUT(hrtc->Init.OutPut)); + assert_param(IS_RTC_OUTPUT_REMAP(hrtc->Init.OutPutRemap)); + assert_param(IS_RTC_OUTPUT_POL(hrtc->Init.OutPutPolarity)); + assert_param(IS_RTC_OUTPUT_TYPE(hrtc->Init.OutPutType)); + assert_param(IS_RTC_OUTPUT_PULLUP(hrtc->Init.OutPutPullUp)); + assert_param(IS_RTC_BINARY_MODE(hrtc->Init.BinMode)); + assert_param(IS_RTC_BINARY_MIX_BCDU(hrtc->Init.BinMixBcdU)); + +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + if (hrtc->State == HAL_RTC_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hrtc->Lock = HAL_UNLOCKED; + + hrtc->AlarmAEventCallback = HAL_RTC_AlarmAEventCallback; /* Legacy weak AlarmAEventCallback */ + hrtc->AlarmBEventCallback = HAL_RTCEx_AlarmBEventCallback; /* Legacy weak AlarmBEventCallback */ + hrtc->TimeStampEventCallback = HAL_RTCEx_TimeStampEventCallback; /* Legacy weak TimeStampEventCallback */ + hrtc->WakeUpTimerEventCallback = HAL_RTCEx_WakeUpTimerEventCallback; /* Legacy weak WakeUpTimerEventCallback */ + hrtc->SSRUEventCallback = HAL_RTCEx_SSRUEventCallback; /* Legacy weak SSRUEventCallback */ + hrtc->Tamper1EventCallback = HAL_RTCEx_Tamper1EventCallback; /* Legacy weak Tamper1EventCallback */ + hrtc->Tamper2EventCallback = HAL_RTCEx_Tamper2EventCallback; /* Legacy weak Tamper2EventCallback */ + hrtc->Tamper3EventCallback = HAL_RTCEx_Tamper3EventCallback; /* Legacy weak Tamper3EventCallback */ + hrtc->InternalTamper3EventCallback = HAL_RTCEx_InternalTamper3EventCallback; /* Legacy weak InternalTamper3EventCallback */ + hrtc->InternalTamper5EventCallback = HAL_RTCEx_InternalTamper5EventCallback; /* Legacy weak InternalTamper5EventCallback */ + hrtc->InternalTamper6EventCallback = HAL_RTCEx_InternalTamper6EventCallback; /* Legacy weak InternalTamper6EventCallback */ + hrtc->InternalTamper8EventCallback = HAL_RTCEx_InternalTamper8EventCallback; /* Legacy weak InternalTamper8EventCallback */ + + if (hrtc->MspInitCallback == NULL) + { + hrtc->MspInitCallback = HAL_RTC_MspInit; + } + /* Init the low level hardware */ + hrtc->MspInitCallback(hrtc); + + if (hrtc->MspDeInitCallback == NULL) + { + hrtc->MspDeInitCallback = HAL_RTC_MspDeInit; + } + } +#else + if (hrtc->State == HAL_RTC_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hrtc->Lock = HAL_UNLOCKED; + + /* Initialize RTC MSP */ + HAL_RTC_MspInit(hrtc); + } +#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */ + + /* Set RTC state */ + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Check whether the calendar needs to be initialized */ + if (__HAL_RTC_IS_CALENDAR_INITIALIZED(hrtc) == 0U) + { + /* Check that the RTC mode is not 'binary only' */ + if (__HAL_RTC_GET_BINARY_MODE(hrtc) != RTC_BINARY_ONLY) + { + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /* Enter Initialization mode */ + status = RTC_EnterInitMode(hrtc); + + if (status == HAL_OK) + { + /* Clear RTC_CR FMT, OSEL and POL Bits */ + CLEAR_BIT(RTC->CR, (RTC_CR_FMT | RTC_CR_POL | RTC_CR_OSEL | RTC_CR_TAMPOE)); + /* Set RTC_CR register */ + SET_BIT(RTC->CR, (hrtc->Init.HourFormat | hrtc->Init.OutPut | hrtc->Init.OutPutPolarity)); + + /* Configure the RTC PRER */ + WRITE_REG(RTC->PRER, ((hrtc->Init.SynchPrediv) | (hrtc->Init.AsynchPrediv << RTC_PRER_PREDIV_A_Pos))); + + /* Configure the Binary mode */ + MODIFY_REG(RTC->ICSR, RTC_ICSR_BIN | RTC_ICSR_BCDU, hrtc->Init.BinMode | hrtc->Init.BinMixBcdU); + + /* Exit Initialization mode */ + status = RTC_ExitInitMode(hrtc); + + if (status == HAL_OK) + { + MODIFY_REG(RTC->CR, \ + RTC_CR_TAMPALRM_PU | RTC_CR_TAMPALRM_TYPE | RTC_CR_OUT2EN, \ + hrtc->Init.OutPutPullUp | hrtc->Init.OutPutType | hrtc->Init.OutPutRemap); + } + } + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + } + else + { + /* The calendar does not need to be initialized as the 'binary only' mode is selected */ + status = HAL_OK; + } + } + else + { + /* The calendar is already initialized */ + status = HAL_OK; + } + + if (status == HAL_OK) + { + hrtc->State = HAL_RTC_STATE_READY; + } + } + + return status; +} + +/** + * @brief DeInitialize the RTC peripheral. + * @note This function does not reset the RTC Backup Data registers. + * @param hrtc RTC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc) +{ + HAL_StatusTypeDef status; + + /* Set RTC state */ + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /* Enter Initialization mode */ + status = RTC_EnterInitMode(hrtc); + if (status == HAL_OK) + { + /* Reset all RTC CR register bits */ + CLEAR_REG(RTC->CR); + WRITE_REG(RTC->DR, (uint32_t)(RTC_DR_WDU_0 | RTC_DR_MU_0 | RTC_DR_DU_0)); + CLEAR_REG(RTC->TR); + WRITE_REG(RTC->WUTR, RTC_WUTR_WUT); + WRITE_REG(RTC->PRER, ((uint32_t)(RTC_PRER_PREDIV_A | 0xFFU))); + CLEAR_REG(RTC->ALRMAR); + CLEAR_REG(RTC->ALRMBR); + CLEAR_REG(RTC->SHIFTR); + CLEAR_REG(RTC->CALR); + CLEAR_REG(RTC->ALRMASSR); + CLEAR_REG(RTC->ALRMBSSR); + WRITE_REG(RTC->SCR, RTC_SCR_CITSF | RTC_SCR_CTSOVF | RTC_SCR_CTSF | RTC_SCR_CWUTF | RTC_SCR_CALRBF | RTC_SCR_CALRAF); + + /* Exit initialization mode */ + status = RTC_ExitInitMode(hrtc); + if (status == HAL_OK) + { + /* Reset TAMP registers */ + WRITE_REG(TAMP->CR1, RTC_INT_TAMPER_ALL); + CLEAR_REG(TAMP->CR2); + CLEAR_REG(TAMP->CR3); + CLEAR_REG(TAMP->FLTCR); + } + } + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + if (status == HAL_OK) + { +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + if (hrtc->MspDeInitCallback == NULL) + { + hrtc->MspDeInitCallback = HAL_RTC_MspDeInit; + } + + /* DeInit the low level hardware: CLOCK, NVIC.*/ + hrtc->MspDeInitCallback(hrtc); + +#else + /* De-Initialize RTC MSP */ + HAL_RTC_MspDeInit(hrtc); +#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */ + + hrtc->State = HAL_RTC_STATE_RESET; + } + + /* Release Lock */ + __HAL_UNLOCK(hrtc); + + return status; +} + +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User RTC Callback + * To be used instead of the weak predefined callback + * @param hrtc RTC handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_RTC_ALARM_A_EVENT_CB_ID Alarm A Event Callback ID + * @arg @ref HAL_RTC_ALARM_B_EVENT_CB_ID Alarm B Event Callback ID + * @arg @ref HAL_RTC_TIMESTAMP_EVENT_CB_ID TimeStamp Event Callback ID + * @arg @ref HAL_RTC_SSRU_EVENT_CB_ID SSRU Callback ID + * @arg @ref HAL_RTC_WAKEUPTIMER_EVENT_CB_ID WakeUp Timer Event Callback ID + * @arg @ref HAL_RTC_TAMPER1_EVENT_CB_ID Tamper 1 Callback ID + * @arg @ref HAL_RTC_TAMPER2_EVENT_CB_ID Tamper 2 Callback ID + * @arg @ref HAL_RTC_TAMPER3_EVENT_CB_ID Tamper 3 Callback ID + * @arg @ref HAL_RTC_INTERNAL_TAMPER3_EVENT_CB_ID Internal Tamper 3 Callback ID + * @arg @ref HAL_RTC_INTERNAL_TAMPER5_EVENT_CB_ID Internal Tamper 5 Callback ID + * @arg @ref HAL_RTC_INTERNAL_TAMPER6_EVENT_CB_ID Internal Tamper 6 Callback ID + * @arg @ref HAL_RTC_INTERNAL_TAMPER8_EVENT_CB_ID Internal Tamper 8 Callback ID + * @arg @ref HAL_RTC_MSPINIT_CB_ID Msp Init callback ID + * @arg @ref HAL_RTC_MSPDEINIT_CB_ID Msp DeInit callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_RegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID, + pRTC_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hrtc); + + if (HAL_RTC_STATE_READY == hrtc->State) + { + switch (CallbackID) + { + case HAL_RTC_ALARM_A_EVENT_CB_ID : + hrtc->AlarmAEventCallback = pCallback; + break; + + case HAL_RTC_ALARM_B_EVENT_CB_ID : + hrtc->AlarmBEventCallback = pCallback; + break; + + case HAL_RTC_TIMESTAMP_EVENT_CB_ID : + hrtc->TimeStampEventCallback = pCallback; + break; + + case HAL_RTC_WAKEUPTIMER_EVENT_CB_ID : + hrtc->WakeUpTimerEventCallback = pCallback; + break; + + case HAL_RTC_SSRU_EVENT_CB_ID : + hrtc->SSRUEventCallback = pCallback; + break; + + case HAL_RTC_TAMPER1_EVENT_CB_ID : + hrtc->Tamper1EventCallback = pCallback; + break; + + case HAL_RTC_TAMPER2_EVENT_CB_ID : + hrtc->Tamper2EventCallback = pCallback; + break; + + case HAL_RTC_TAMPER3_EVENT_CB_ID : + hrtc->Tamper3EventCallback = pCallback; + break; + + case HAL_RTC_INTERNAL_TAMPER3_EVENT_CB_ID : + hrtc->InternalTamper3EventCallback = pCallback; + break; + + case HAL_RTC_INTERNAL_TAMPER5_EVENT_CB_ID : + hrtc->InternalTamper5EventCallback = pCallback; + break; + + case HAL_RTC_INTERNAL_TAMPER6_EVENT_CB_ID : + hrtc->InternalTamper6EventCallback = pCallback; + break; + + case HAL_RTC_INTERNAL_TAMPER8_EVENT_CB_ID : + hrtc->InternalTamper8EventCallback = pCallback; + break; + + case HAL_RTC_MSPINIT_CB_ID : + hrtc->MspInitCallback = pCallback; + break; + + case HAL_RTC_MSPDEINIT_CB_ID : + hrtc->MspDeInitCallback = pCallback; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_RTC_STATE_RESET == hrtc->State) + { + switch (CallbackID) + { + case HAL_RTC_MSPINIT_CB_ID : + hrtc->MspInitCallback = pCallback; + break; + + case HAL_RTC_MSPDEINIT_CB_ID : + hrtc->MspDeInitCallback = pCallback; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hrtc); + + return status; +} + +/** + * @brief Unregister an RTC Callback + * RTC callback is redirected to the weak predefined callback + * @param hrtc RTC handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_RTC_ALARM_A_EVENT_CB_ID Alarm A Event Callback ID + * @arg @ref HAL_RTC_ALARM_B_EVENT_CB_ID Alarm B Event Callback ID + * @arg @ref HAL_RTC_TIMESTAMP_EVENT_CB_ID TimeStamp Event Callback ID + * @arg @ref HAL_RTC_SSRU_EVENT_CB_ID SSRU Callback ID + * @arg @ref HAL_RTC_WAKEUPTIMER_EVENT_CB_ID WakeUp Timer Event Callback ID + * @arg @ref HAL_RTC_TAMPER1_EVENT_CB_ID Tamper 1 Callback ID + * @arg @ref HAL_RTC_TAMPER2_EVENT_CB_ID Tamper 2 Callback ID + * @arg @ref HAL_RTC_TAMPER3_EVENT_CB_ID Tamper 3 Callback ID + * @arg @ref HAL_RTC_INTERNAL_TAMPER3_EVENT_CB_ID Internal Tamper 3 Callback ID + * @arg @ref HAL_RTC_INTERNAL_TAMPER5_EVENT_CB_ID Internal Tamper 5 Callback ID + * @arg @ref HAL_RTC_INTERNAL_TAMPER6_EVENT_CB_ID Internal Tamper 6 Callback ID + * @arg @ref HAL_RTC_INTERNAL_TAMPER8_EVENT_CB_ID Internal Tamper 8 Callback ID + * @arg @ref HAL_RTC_MSPINIT_CB_ID Msp Init callback ID + * @arg @ref HAL_RTC_MSPDEINIT_CB_ID Msp DeInit callback ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_UnRegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hrtc); + + if (HAL_RTC_STATE_READY == hrtc->State) + { + switch (CallbackID) + { + case HAL_RTC_ALARM_A_EVENT_CB_ID : + hrtc->AlarmAEventCallback = HAL_RTC_AlarmAEventCallback; /* Legacy weak AlarmAEventCallback */ + break; + + case HAL_RTC_ALARM_B_EVENT_CB_ID : + hrtc->AlarmBEventCallback = HAL_RTCEx_AlarmBEventCallback; /* Legacy weak AlarmBEventCallback */ + break; + + case HAL_RTC_TIMESTAMP_EVENT_CB_ID : + hrtc->TimeStampEventCallback = HAL_RTCEx_TimeStampEventCallback; /* Legacy weak TimeStampEventCallback */ + break; + + case HAL_RTC_WAKEUPTIMER_EVENT_CB_ID : + hrtc->WakeUpTimerEventCallback = HAL_RTCEx_WakeUpTimerEventCallback; /* Legacy weak WakeUpTimerEventCallback */ + break; + + case HAL_RTC_SSRU_EVENT_CB_ID : + hrtc->SSRUEventCallback = HAL_RTCEx_SSRUEventCallback; /* Legacy weak SSRUEventCallback */ + break; + + case HAL_RTC_TAMPER1_EVENT_CB_ID : + hrtc->Tamper1EventCallback = HAL_RTCEx_Tamper1EventCallback; /* Legacy weak Tamper1EventCallback */ + break; + + case HAL_RTC_TAMPER2_EVENT_CB_ID : + hrtc->Tamper2EventCallback = HAL_RTCEx_Tamper2EventCallback; /* Legacy weak Tamper2EventCallback */ + break; + + case HAL_RTC_TAMPER3_EVENT_CB_ID : + hrtc->Tamper3EventCallback = HAL_RTCEx_Tamper3EventCallback; /* Legacy weak Tamper3EventCallback */ + break; + + case HAL_RTC_INTERNAL_TAMPER3_EVENT_CB_ID : + hrtc->InternalTamper3EventCallback = HAL_RTCEx_InternalTamper3EventCallback; /* Legacy weak InternalTamper3EventCallback */ + break; + + case HAL_RTC_INTERNAL_TAMPER5_EVENT_CB_ID : + hrtc->InternalTamper5EventCallback = HAL_RTCEx_InternalTamper5EventCallback; /* Legacy weak InternalTamper5EventCallback */ + break; + + case HAL_RTC_INTERNAL_TAMPER6_EVENT_CB_ID : + hrtc->InternalTamper6EventCallback = HAL_RTCEx_InternalTamper6EventCallback; /* Legacy weak InternalTamper6EventCallback */ + break; + + case HAL_RTC_INTERNAL_TAMPER8_EVENT_CB_ID : + hrtc->InternalTamper8EventCallback = HAL_RTCEx_InternalTamper8EventCallback; /* Legacy weak InternalTamper8EventCallback */ + break; + + case HAL_RTC_MSPINIT_CB_ID : + hrtc->MspInitCallback = HAL_RTC_MspInit; + break; + + case HAL_RTC_MSPDEINIT_CB_ID : + hrtc->MspDeInitCallback = HAL_RTC_MspDeInit; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_RTC_STATE_RESET == hrtc->State) + { + switch (CallbackID) + { + case HAL_RTC_MSPINIT_CB_ID : + hrtc->MspInitCallback = HAL_RTC_MspInit; + break; + + case HAL_RTC_MSPDEINIT_CB_ID : + hrtc->MspDeInitCallback = HAL_RTC_MspDeInit; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hrtc); + + return status; +} +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ + +/** + * @brief Initialize the RTC MSP. + * @param hrtc RTC handle + * @retval None + */ +__weak void HAL_RTC_MspInit(RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_RTC_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitialize the RTC MSP. + * @param hrtc RTC handle + * @retval None + */ +__weak void HAL_RTC_MspDeInit(RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_RTC_MspDeInit could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @addtogroup RTC_Exported_Functions_Group2 + * @brief RTC Time and Date functions + * +@verbatim + =============================================================================== + ##### RTC Time and Date functions ##### + =============================================================================== + + [..] This section provides functions allowing to configure Time and Date features + +@endverbatim + * @{ + */ + +/** + * @brief Set RTC current time. + * @param hrtc RTC handle + * @param sTime Pointer to Time structure + * if Binary mode is RTC_BINARY_ONLY, this parameter is not used and RTC_SSR will be automatically reset to 0xFFFFFFFF + else sTime->SubSeconds is not used and RTC_SSR will be automatically reset to the A 7-bit async prescaler (RTC_PRER_PREDIV_A) + * @param Format Format of sTime->Hours, sTime->Minutes and sTime->Seconds. + * if Binary mode is RTC_BINARY_ONLY, this parameter is not used + * else this parameter can be one of the following values + * @arg RTC_FORMAT_BIN: Binary format + * @arg RTC_FORMAT_BCD: BCD format + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format) +{ + uint32_t tmpreg; + HAL_StatusTypeDef status; + +#ifdef USE_FULL_ASSERT + /* Check the parameters depending of the Binary mode with 32-bit free-running counter configuration. */ + if (READ_BIT(RTC->ICSR, RTC_ICSR_BIN) == RTC_BINARY_NONE) + { + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(Format)); + } +#endif /* USE_FULL_ASSERT */ + + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /* Enter Initialization mode */ + status = RTC_EnterInitMode(hrtc); + if (status == HAL_OK) + { + /* Check Binary mode ((32-bit free-running counter) */ + if (READ_BIT(RTC->ICSR, RTC_ICSR_BIN) != RTC_BINARY_ONLY) + { + if (Format == RTC_FORMAT_BIN) + { + if (READ_BIT(RTC->CR, RTC_CR_FMT) != 0U) + { + assert_param(IS_RTC_HOUR12(sTime->Hours)); + assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat)); + } + else + { + sTime->TimeFormat = 0x00U; + assert_param(IS_RTC_HOUR24(sTime->Hours)); + } + assert_param(IS_RTC_MINUTES(sTime->Minutes)); + assert_param(IS_RTC_SECONDS(sTime->Seconds)); + + tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(sTime->Hours) << RTC_TR_HU_Pos) | \ + ((uint32_t)RTC_ByteToBcd2(sTime->Minutes) << RTC_TR_MNU_Pos) | \ + ((uint32_t)RTC_ByteToBcd2(sTime->Seconds) << RTC_TR_SU_Pos) | \ + (((uint32_t)sTime->TimeFormat) << RTC_TR_PM_Pos)); + + } + else + { + if (READ_BIT(RTC->CR, RTC_CR_FMT) != 0U) + { + assert_param(IS_RTC_HOUR12(RTC_Bcd2ToByte(sTime->Hours))); + assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat)); + } + else + { + sTime->TimeFormat = 0x00U; + assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sTime->Hours))); + } + assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sTime->Minutes))); + assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sTime->Seconds))); + tmpreg = (((uint32_t)(sTime->Hours) << RTC_TR_HU_Pos) | \ + ((uint32_t)(sTime->Minutes) << RTC_TR_MNU_Pos) | \ + ((uint32_t)(sTime->Seconds) << RTC_TR_SU_Pos) | \ + ((uint32_t)(sTime->TimeFormat) << RTC_TR_PM_Pos)); + } + + /* Set the RTC_TR register */ + WRITE_REG(RTC->TR, (tmpreg & RTC_TR_RESERVED_MASK)); + + /* This interface is deprecated. To manage Daylight Saving Time, please use HAL_RTC_DST_xxx functions */ + CLEAR_BIT(RTC->CR, RTC_CR_BKP); + + /* This interface is deprecated. To manage Daylight Saving Time, please use HAL_RTC_DST_xxx functions */ + SET_BIT(RTC->CR, (sTime->DayLightSaving | sTime->StoreOperation)); + } + } + + /* Exit Initialization mode */ + status = RTC_ExitInitMode(hrtc); + + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + if (status == HAL_OK) + { + hrtc->State = HAL_RTC_STATE_READY; + } + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return status; +} + +/** + * @brief Get RTC current time. + * @note You can use SubSeconds and SecondFraction (sTime structure fields returned) to convert SubSeconds + * value in second fraction ratio with time unit following generic formula: + * Second fraction ratio * time_unit= [(SecondFraction-SubSeconds)/(SecondFraction+1)] * time_unit + * This conversion can be performed only if no shift operation is pending (ie. SHFP=0) when PREDIV_S >= SS + * @note You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values + * in the higher-order calendar shadow registers to ensure consistency between the time and date values. + * Reading RTC current time locks the values in calendar shadow registers until Current date is read + * to ensure consistency between the time and date values. + * @param hrtc RTC handle + * @param sTime + * if Binary mode is RTC_BINARY_ONLY, sTime->SubSeconds only is updated + * else + * Pointer to Time structure with Hours, Minutes and Seconds fields returned + * with input format (BIN or BCD), also SubSeconds field returning the + * RTC_SSR register content and SecondFraction field the Synchronous pre-scaler + * factor to be used for second fraction ratio computation. + * @param Format Format of sTime->Hours, sTime->Minutes and sTime->Seconds. + * if Binary mode is RTC_BINARY_ONLY, this parameter is not used + * else this parameter can be one of the following values: + * @arg RTC_FORMAT_BIN: Binary format + * @arg RTC_FORMAT_BCD: BCD format + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_GetTime(const RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format) +{ + uint32_t tmpreg; + + UNUSED(hrtc); + /* Get subseconds structure field from the corresponding register*/ + sTime->SubSeconds = READ_REG(RTC->SSR); + + if (READ_BIT(RTC->ICSR, RTC_ICSR_BIN) != RTC_BINARY_ONLY) + { + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(Format)); + + /* Get SecondFraction structure field from the corresponding register field*/ + sTime->SecondFraction = (uint32_t)(READ_REG(RTC->PRER) & RTC_PRER_PREDIV_S); + + /* Get the TR register */ + tmpreg = (uint32_t)(READ_REG(RTC->TR) & RTC_TR_RESERVED_MASK); + + /* Fill the structure fields with the read parameters */ + sTime->Hours = (uint8_t)((tmpreg & (RTC_TR_HT | RTC_TR_HU)) >> RTC_TR_HU_Pos); + sTime->Minutes = (uint8_t)((tmpreg & (RTC_TR_MNT | RTC_TR_MNU)) >> RTC_TR_MNU_Pos); + sTime->Seconds = (uint8_t)((tmpreg & (RTC_TR_ST | RTC_TR_SU)) >> RTC_TR_SU_Pos); + sTime->TimeFormat = (uint8_t)((tmpreg & (RTC_TR_PM)) >> RTC_TR_PM_Pos); + + /* Check the input parameters format */ + if (Format == RTC_FORMAT_BIN) + { + /* Convert the time structure parameters to Binary format */ + sTime->Hours = (uint8_t)RTC_Bcd2ToByte(sTime->Hours); + sTime->Minutes = (uint8_t)RTC_Bcd2ToByte(sTime->Minutes); + sTime->Seconds = (uint8_t)RTC_Bcd2ToByte(sTime->Seconds); + } + } + + return HAL_OK; +} + +/** + * @brief Set RTC current date. + * @param hrtc RTC handle + * @param sDate Pointer to date structure + * @param Format Format of sDate->Year, sDate->Month and sDate->Weekday. + * This parameter can be one of the following values: + * @arg RTC_FORMAT_BIN: Binary format + * @arg RTC_FORMAT_BCD: BCD format + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format) +{ + uint32_t datetmpreg; + HAL_StatusTypeDef status; + + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(Format)); + + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + if ((Format == RTC_FORMAT_BIN) && ((sDate->Month & 0x10U) == 0x10U)) + { + sDate->Month = (uint8_t)((sDate->Month & (uint8_t)~(0x10U)) + (uint8_t)0x0AU); + } + + assert_param(IS_RTC_WEEKDAY(sDate->WeekDay)); + + if (Format == RTC_FORMAT_BIN) + { + assert_param(IS_RTC_YEAR(sDate->Year)); + assert_param(IS_RTC_MONTH(sDate->Month)); + assert_param(IS_RTC_DATE(sDate->Date)); + + datetmpreg = (((uint32_t)RTC_ByteToBcd2(sDate->Year) << RTC_DR_YU_Pos) | \ + ((uint32_t)RTC_ByteToBcd2(sDate->Month) << RTC_DR_MU_Pos) | \ + ((uint32_t)RTC_ByteToBcd2(sDate->Date) << RTC_DR_DU_Pos) | \ + ((uint32_t)sDate->WeekDay << RTC_DR_WDU_Pos)); + } + else + { + assert_param(IS_RTC_YEAR(RTC_Bcd2ToByte(sDate->Year))); + assert_param(IS_RTC_MONTH(RTC_Bcd2ToByte(sDate->Month))); + assert_param(IS_RTC_DATE(RTC_Bcd2ToByte(sDate->Date))); + + datetmpreg = ((((uint32_t)sDate->Year) << RTC_DR_YU_Pos) | \ + (((uint32_t)sDate->Month) << RTC_DR_MU_Pos) | \ + (((uint32_t)sDate->Date) << RTC_DR_DU_Pos) | \ + (((uint32_t)sDate->WeekDay) << RTC_DR_WDU_Pos)); + } + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /* Enter Initialization mode */ + status = RTC_EnterInitMode(hrtc); + if (status == HAL_OK) + { + /* Set the RTC_DR register */ + WRITE_REG(RTC->DR, (uint32_t)(datetmpreg & RTC_DR_RESERVED_MASK)); + + /* Exit Initialization mode */ + status = RTC_ExitInitMode(hrtc); + } + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + if (status == HAL_OK) + { + hrtc->State = HAL_RTC_STATE_READY ; + } + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return status; +} + +/** + * @brief Get RTC current date. + * @note You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values + * in the higher-order calendar shadow registers to ensure consistency between the time and date values. + * Reading RTC current time locks the values in calendar shadow registers until Current date is read. + * @param hrtc RTC handle + * @param sDate Pointer to Date structure + * @param Format Format of sDate->Year, sDate->Month and sDate->Weekday. + * This parameter can be one of the following values: + * @arg RTC_FORMAT_BIN: Binary format + * @arg RTC_FORMAT_BCD: BCD format + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_GetDate(const RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format) +{ + uint32_t datetmpreg; + + UNUSED(hrtc); + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(Format)); + + /* Get the DR register */ + datetmpreg = (uint32_t)(READ_REG(RTC->DR) & RTC_DR_RESERVED_MASK); + + /* Fill the structure fields with the read parameters */ + sDate->Year = (uint8_t)((datetmpreg & (RTC_DR_YT | RTC_DR_YU)) >> RTC_DR_YU_Pos); + sDate->Month = (uint8_t)((datetmpreg & (RTC_DR_MT | RTC_DR_MU)) >> RTC_DR_MU_Pos); + sDate->Date = (uint8_t)((datetmpreg & (RTC_DR_DT | RTC_DR_DU)) >> RTC_DR_DU_Pos); + sDate->WeekDay = (uint8_t)((datetmpreg & (RTC_DR_WDU)) >> RTC_DR_WDU_Pos); + + /* Check the input parameters format */ + if (Format == RTC_FORMAT_BIN) + { + /* Convert the date structure parameters to Binary format */ + sDate->Year = (uint8_t)RTC_Bcd2ToByte(sDate->Year); + sDate->Month = (uint8_t)RTC_Bcd2ToByte(sDate->Month); + sDate->Date = (uint8_t)RTC_Bcd2ToByte(sDate->Date); + } + return HAL_OK; +} + +/** + * @brief Daylight Saving Time, Add one hour to the calendar in one single operation + * without going through the initialization procedure. + * @param hrtc RTC handle + * @retval None + */ +void HAL_RTC_DST_Add1Hour(const RTC_HandleTypeDef *hrtc) +{ + UNUSED(hrtc); + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + SET_BIT(RTC->CR, RTC_CR_ADD1H); + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); +} + +/** + * @brief Daylight Saving Time, Subtract one hour from the calendar in one + * single operation without going through the initialization procedure. + * @param hrtc RTC handle + * @retval None + */ +void HAL_RTC_DST_Sub1Hour(const RTC_HandleTypeDef *hrtc) +{ + UNUSED(hrtc); + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + SET_BIT(RTC->CR, RTC_CR_SUB1H); + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); +} + +/** + * @brief Daylight Saving Time, Set the store operation bit. + * @note It can be used by the software in order to memorize the DST status. + * @param hrtc RTC handle + * @retval None + */ +void HAL_RTC_DST_SetStoreOperation(const RTC_HandleTypeDef *hrtc) +{ + UNUSED(hrtc); + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + SET_BIT(RTC->CR, RTC_CR_BKP); + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); +} + +/** + * @brief Daylight Saving Time, Clear the store operation bit. + * @param hrtc RTC handle + * @retval None + */ +void HAL_RTC_DST_ClearStoreOperation(const RTC_HandleTypeDef *hrtc) +{ + UNUSED(hrtc); + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + CLEAR_BIT(RTC->CR, RTC_CR_BKP); + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); +} + +/** + * @brief Daylight Saving Time, Read the store operation bit. + * @param hrtc RTC handle + * @retval operation see RTC_StoreOperation_Definitions + */ +uint32_t HAL_RTC_DST_ReadStoreOperation(const RTC_HandleTypeDef *hrtc) +{ + UNUSED(hrtc); + return READ_BIT(RTC->CR, RTC_CR_BKP); +} + + +/** + * @} + */ + +/** @addtogroup RTC_Exported_Functions_Group3 + * @brief RTC Alarm functions + * +@verbatim + =============================================================================== + ##### RTC Alarm functions ##### + =============================================================================== + + [..] This section provides functions allowing to configure Alarm feature + +@endverbatim + * @{ + */ +/** + * @brief Set the specified RTC Alarm. + * @param hrtc RTC handle + * @param sAlarm Pointer to Alarm structure + * if Binary mode is RTC_BINARY_ONLY, 3 fields only are used + * sAlarm->AlarmTime.SubSeconds + * sAlarm->AlarmSubSecondMask + * sAlarm->BinaryAutoClr + * @param Format of the entered parameters. + * if Binary mode is RTC_BINARY_ONLY, this parameter is not used + * else this parameter can be one of the following values + * @arg RTC_FORMAT_BIN: Binary format + * @arg RTC_FORMAT_BCD: BCD format + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format) +{ + uint32_t tmpreg = 0; + uint32_t binaryMode; + + __HAL_LOCK(hrtc); + hrtc->State = HAL_RTC_STATE_BUSY; + +#ifdef USE_FULL_ASSERT + /* Check the parameters depending of the Binary mode (32-bit free-running counter configuration). */ + if (READ_BIT(RTC->ICSR, RTC_ICSR_BIN) == RTC_BINARY_NONE) + { + assert_param(IS_RTC_FORMAT(Format)); + assert_param(IS_RTC_ALARM(sAlarm->Alarm)); + assert_param(IS_RTC_ALARM_MASK(sAlarm->AlarmMask)); + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel)); + assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(sAlarm->AlarmTime.SubSeconds)); + assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(sAlarm->AlarmSubSecondMask)); + } + else if (READ_BIT(RTC->ICSR, RTC_ICSR_BIN) == RTC_BINARY_ONLY) + { + assert_param(IS_RTC_ALARM_SUB_SECOND_BINARY_MASK(sAlarm->AlarmSubSecondMask)); + assert_param(IS_RTC_ALARMSUBSECONDBIN_AUTOCLR(sAlarm->BinaryAutoClr)); + } + else /* RTC_BINARY_MIX */ + { + assert_param(IS_RTC_FORMAT(Format)); + assert_param(IS_RTC_ALARM(sAlarm->Alarm)); + assert_param(IS_RTC_ALARM_MASK(sAlarm->AlarmMask)); + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel)); + /* In Binary Mix Mode, the RTC can not generate an alarm on a match involving all calendar items + the upper SSR bits */ + assert_param((sAlarm->AlarmSubSecondMask >> RTC_ALRMASSR_MASKSS_Pos) <= (8U + (READ_BIT(RTC->ICSR, + RTC_ICSR_BCDU) >> RTC_ICSR_BCDU_Pos))); + } +#endif /* USE_FULL_ASSERT */ + + /* Get Binary mode (32-bit free-running counter configuration) */ + binaryMode = READ_BIT(RTC->ICSR, RTC_ICSR_BIN); + + if (binaryMode != RTC_BINARY_ONLY) + { + if (Format == RTC_FORMAT_BIN) + { + if (READ_BIT(RTC->CR, RTC_CR_FMT) != 0U) + { + assert_param(IS_RTC_HOUR12(sAlarm->AlarmTime.Hours)); + assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat)); + } + else + { + sAlarm->AlarmTime.TimeFormat = 0x00U; + assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours)); + } + assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes)); + assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds)); + + if (sAlarm->AlarmMask != RTC_ALARMMASK_DATEWEEKDAY) + { + if (sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE) + { + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(sAlarm->AlarmDateWeekDay)); + } + else + { + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay)); + } + } + + tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << RTC_ALRMAR_HU_Pos) | \ + ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << RTC_ALRMAR_MNU_Pos) | \ + ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds) << RTC_ALRMAR_SU_Pos) | \ + ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_ALRMAR_PM_Pos) | \ + ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << RTC_ALRMAR_DU_Pos) | \ + ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \ + ((uint32_t)sAlarm->AlarmMask)); + } + else /* format BCD */ + { + if (sAlarm->AlarmMask != RTC_ALARMMASK_ALL) + { + if (sAlarm->AlarmMask != RTC_ALARMMASK_HOURS) + { + if (READ_BIT(RTC->CR, RTC_CR_FMT) != 0U) + { + assert_param(IS_RTC_HOUR12(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours))); + assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat)); + } + else + { + sAlarm->AlarmTime.TimeFormat = 0x00U; + assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours))); + } + } + + assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes))); + assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds))); + } +#ifdef USE_FULL_ASSERT + if ((sAlarm->AlarmMask != RTC_ALARMMASK_ALL) && (sAlarm->AlarmMask != RTC_ALARMMASK_DATEWEEKDAY)) + { + if (sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE) + { + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay))); + } + else + { + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay))); + } + } +#endif /* USE_FULL_ASSERT */ + tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << RTC_ALRMAR_HU_Pos) | \ + ((uint32_t)(sAlarm->AlarmTime.Minutes) << RTC_ALRMAR_MNU_Pos) | \ + ((uint32_t)(sAlarm->AlarmTime.Seconds) << RTC_ALRMAR_SU_Pos) | \ + ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_ALRMAR_PM_Pos) | \ + ((uint32_t)(sAlarm->AlarmDateWeekDay) << RTC_ALRMAR_DU_Pos) | \ + ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \ + ((uint32_t)sAlarm->AlarmMask)); + } + } + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /* Configure the Alarm register */ + if (sAlarm->Alarm == RTC_ALARM_A) + { + /* Disable the Alarm A interrupt */ + /* In case of interrupt mode is used, the interrupt source must disabled */ + CLEAR_BIT(RTC->CR, (RTC_CR_ALRAE | RTC_CR_ALRAIE)); + + /* Clear flag alarm A */ + WRITE_REG(RTC->SCR, RTC_SCR_CALRAF); + + if (binaryMode == RTC_BINARY_ONLY) + { + WRITE_REG(RTC->ALRMASSR, sAlarm->AlarmSubSecondMask | sAlarm->BinaryAutoClr); + } + else + { + WRITE_REG(RTC->ALRMAR, tmpreg); + WRITE_REG(RTC->ALRMASSR, sAlarm->AlarmSubSecondMask); + } + + WRITE_REG(RTC->ALRABINR, sAlarm->AlarmTime.SubSeconds); + + /* Store in the handle the Alarm A enabled */ + SET_BIT(hrtc->IsEnabled.RtcFeatures, RTC_MISR_ALRAMF); + + /* Configure the Alarm state: Enable Alarm */ + SET_BIT(RTC->CR, RTC_CR_ALRAE); + } + else + { + /* Disable the Alarm B interrupt */ + /* In case of interrupt mode is used, the interrupt source must disabled */ + CLEAR_BIT(RTC->CR, (RTC_CR_ALRBE | RTC_CR_ALRBIE)); + + /* Clear flag alarm B */ + WRITE_REG(RTC->SCR, RTC_SCR_CALRBF); + + if (binaryMode == RTC_BINARY_ONLY) + { + WRITE_REG(RTC->ALRMBSSR, sAlarm->AlarmSubSecondMask | sAlarm->BinaryAutoClr); + } + else + { + WRITE_REG(RTC->ALRMBR, tmpreg); + WRITE_REG(RTC->ALRMBSSR, sAlarm->AlarmSubSecondMask); + } + + WRITE_REG(RTC->ALRBBINR, sAlarm->AlarmTime.SubSeconds); + + /* Store in the handle the Alarm B enabled */ + SET_BIT(hrtc->IsEnabled.RtcFeatures, RTC_MISR_ALRBMF); + + /* Configure the Alarm state: Enable Alarm */ + SET_BIT(RTC->CR, RTC_CR_ALRBE); + } + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Set the specified RTC Alarm with Interrupt. + * @param hrtc RTC handle + * @param sAlarm Pointer to Alarm structure + * if Binary mode is RTC_BINARY_ONLY, 3 fields only are used + * sAlarm->AlarmTime.SubSeconds + * sAlarm->AlarmSubSecondMask + * sAlarm->BinaryAutoClr + * @param Format Specifies the format of the entered parameters. + * if Binary mode is RTC_BINARY_ONLY, this parameter is not used + * else this parameter can be one of the following values + * @arg RTC_FORMAT_BIN: Binary format + * @arg RTC_FORMAT_BCD: BCD format + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format) +{ + uint32_t tmpreg = 0; + uint32_t binaryMode; + + /* Process Locked */ + __HAL_LOCK(hrtc); + hrtc->State = HAL_RTC_STATE_BUSY; + +#ifdef USE_FULL_ASSERT + /* Check the parameters depending of the Binary mode (32-bit free-running counter configuration). */ + if (READ_BIT(RTC->ICSR, RTC_ICSR_BIN) == RTC_BINARY_NONE) + { + assert_param(IS_RTC_FORMAT(Format)); + assert_param(IS_RTC_ALARM(sAlarm->Alarm)); + assert_param(IS_RTC_ALARM_MASK(sAlarm->AlarmMask)); + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel)); + assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(sAlarm->AlarmTime.SubSeconds)); + assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(sAlarm->AlarmSubSecondMask)); + } + else if (READ_BIT(RTC->ICSR, RTC_ICSR_BIN) == RTC_BINARY_ONLY) + { + assert_param(IS_RTC_ALARM_SUB_SECOND_BINARY_MASK(sAlarm->AlarmSubSecondMask)); + assert_param(IS_RTC_ALARMSUBSECONDBIN_AUTOCLR(sAlarm->BinaryAutoClr)); + } + else /* RTC_BINARY_MIX */ + { + assert_param(IS_RTC_FORMAT(Format)); + assert_param(IS_RTC_ALARM(sAlarm->Alarm)); + assert_param(IS_RTC_ALARM_MASK(sAlarm->AlarmMask)); + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel)); + /* In Binary Mix Mode, the RTC can not generate an alarm on a match involving all calendar items + the upper SSR bits */ + assert_param((sAlarm->AlarmSubSecondMask >> RTC_ALRMASSR_MASKSS_Pos) <= (8U + (READ_BIT(RTC->ICSR, + RTC_ICSR_BCDU) >> RTC_ICSR_BCDU_Pos))); + } +#endif /* USE_FULL_ASSERT */ + + /* Get Binary mode (32-bit free-running counter configuration) */ + binaryMode = READ_BIT(RTC->ICSR, RTC_ICSR_BIN); + + if (binaryMode != RTC_BINARY_ONLY) + { + if (Format == RTC_FORMAT_BIN) + { + if (READ_BIT(RTC->CR, RTC_CR_FMT) != 0U) + { + assert_param(IS_RTC_HOUR12(sAlarm->AlarmTime.Hours)); + assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat)); + } + else + { + sAlarm->AlarmTime.TimeFormat = 0x00U; + assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours)); + } + assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes)); + assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds)); + + if (sAlarm->AlarmMask != RTC_ALARMMASK_DATEWEEKDAY) + { + if (sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE) + { + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(sAlarm->AlarmDateWeekDay)); + } + else + { + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay)); + } + } + + tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << RTC_ALRMAR_HU_Pos) | \ + ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << RTC_ALRMAR_MNU_Pos) | \ + ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds) << RTC_ALRMAR_SU_Pos) | \ + ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_ALRMAR_PM_Pos) | \ + ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << RTC_ALRMAR_DU_Pos) | \ + ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \ + ((uint32_t)sAlarm->AlarmMask)); + } + else /* Format BCD */ + { + if (sAlarm->AlarmMask != RTC_ALARMMASK_ALL) + { + if (sAlarm->AlarmMask != RTC_ALARMMASK_HOURS) + { + if (READ_BIT(RTC->CR, RTC_CR_FMT) != 0U) + { + assert_param(IS_RTC_HOUR12(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours))); + assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat)); + } + else + { + sAlarm->AlarmTime.TimeFormat = 0x00U; + assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours))); + } + } + + assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes))); + assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds))); + } + +#ifdef USE_FULL_ASSERT + if ((sAlarm->AlarmMask != RTC_ALARMMASK_ALL) && (sAlarm->AlarmMask != RTC_ALARMMASK_DATEWEEKDAY)) + { + if (sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE) + { + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay))); + } + else + { + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay))); + } + } +#endif /* USE_FULL_ASSERT */ + tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << RTC_ALRMAR_HU_Pos) | \ + ((uint32_t)(sAlarm->AlarmTime.Minutes) << RTC_ALRMAR_MNU_Pos) | \ + ((uint32_t)(sAlarm->AlarmTime.Seconds) << RTC_ALRMAR_SU_Pos) | \ + ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_ALRMAR_PM_Pos) | \ + ((uint32_t)(sAlarm->AlarmDateWeekDay) << RTC_ALRMAR_DU_Pos) | \ + ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \ + ((uint32_t)sAlarm->AlarmMask)); + + } + } + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /* Configure the Alarm register */ + if (sAlarm->Alarm == RTC_ALARM_A) + { + /* Disable the Alarm A interrupt */ + CLEAR_BIT(RTC->CR, RTC_CR_ALRAE | RTC_CR_ALRAIE); + /* Clear flag alarm A */ + WRITE_REG(RTC->SCR, RTC_SCR_CALRAF); + + if (binaryMode == RTC_BINARY_ONLY) + { + RTC->ALRMASSR = sAlarm->AlarmSubSecondMask | sAlarm->BinaryAutoClr; + } + else + { + WRITE_REG(RTC->ALRMAR, tmpreg); + WRITE_REG(RTC->ALRMASSR, sAlarm->AlarmSubSecondMask); + } + + WRITE_REG(RTC->ALRABINR, sAlarm->AlarmTime.SubSeconds); + + /* Store in the handle the Alarm A enabled */ + SET_BIT(hrtc->IsEnabled.RtcFeatures, RTC_MISR_ALRAMF); + + /* Configure the Alarm interrupt */ + SET_BIT(RTC->CR, RTC_CR_ALRAE | RTC_CR_ALRAIE); + } + else + { + /* Disable the Alarm B interrupt */ + CLEAR_BIT(RTC->CR, RTC_CR_ALRBE | RTC_CR_ALRBIE); + /* Clear flag alarm B */ + WRITE_REG(RTC->SCR, RTC_SCR_CALRBF); + + if (binaryMode == RTC_BINARY_ONLY) + { + WRITE_REG(RTC->ALRMBSSR, sAlarm->AlarmSubSecondMask | sAlarm->BinaryAutoClr); + } + else + { + WRITE_REG(RTC->ALRMBR, tmpreg); + WRITE_REG(RTC->ALRMBSSR, sAlarm->AlarmSubSecondMask); + } + + WRITE_REG(RTC->ALRBBINR, sAlarm->AlarmTime.SubSeconds); + + /* Store in the handle the Alarm B enabled */ + SET_BIT(hrtc->IsEnabled.RtcFeatures, RTC_MISR_ALRBMF); + + /* Configure the Alarm interrupt */ + SET_BIT(RTC->CR, RTC_CR_ALRBE | RTC_CR_ALRBIE); + } + + /* RTC Alarm Interrupt Configuration: EXTI configuration */ + __HAL_RTC_ALARM_EXTI_ENABLE_IT(); + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Deactivate the specified RTC Alarm. + * @param hrtc RTC handle + * @param Alarm Specifies the Alarm. + * This parameter can be one of the following values: + * @arg RTC_ALARM_A: AlarmA + * @arg RTC_ALARM_B: AlarmB + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm) +{ + /* Check the parameters */ + assert_param(IS_RTC_ALARM(Alarm)); + + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + if (Alarm == RTC_ALARM_A) + { + /* AlarmA, In case of interrupt mode is used, the interrupt source must disabled */ + CLEAR_BIT(RTC->CR, RTC_CR_ALRAE | RTC_CR_ALRAIE); + + /* AlarmA, Clear SSCLR */ + CLEAR_BIT(RTC->ALRMASSR, RTC_ALRMASSR_SSCLR); + + /* Store in the handle the Alarm A disabled */ + CLEAR_BIT(hrtc->IsEnabled.RtcFeatures, RTC_MISR_ALRAMF); + + /* Clear AlarmA flag */ + WRITE_REG(RTC->SCR, RTC_SCR_CALRAF); + } + else + { + /* AlarmB, In case of interrupt mode is used, the interrupt source must disabled */ + CLEAR_BIT(RTC->CR, RTC_CR_ALRBE | RTC_CR_ALRBIE); + + /* AlarmB, Clear SSCLR */ + CLEAR_BIT(RTC->ALRMBSSR, RTC_ALRMBSSR_SSCLR); + + /* Store in the handle the Alarm B disabled */ + CLEAR_BIT(hrtc->IsEnabled.RtcFeatures, RTC_MISR_ALRBMF); + + /* Clear AlarmB flag */ + WRITE_REG(RTC->SCR, RTC_SCR_CALRBF); + } + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Get the RTC Alarm value and masks. + * @param hrtc RTC handle + * @param sAlarm Pointer to Date structure + * @param Alarm Specifies the Alarm. + * This parameter can be one of the following values: + * @arg RTC_ALARM_A: AlarmA + * @arg RTC_ALARM_B: AlarmB + * @param Format Specifies the format of the entered parameters. + * This parameter can be one of the following values: + * @arg RTC_FORMAT_BIN: Binary format + * @arg RTC_FORMAT_BCD: BCD format + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_GetAlarm(const RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format) +{ + uint32_t tmpreg; + uint32_t subsecondtmpreg; + uint32_t binaryMode; + + UNUSED(hrtc); + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(Format)); + assert_param(IS_RTC_ALARM(Alarm)); + + /* Get Binary mode (32-bit free-running counter configuration) */ + binaryMode = READ_BIT(RTC->ICSR, RTC_ICSR_BIN); + + if (binaryMode != RTC_BINARY_ONLY) + { + if (Alarm == RTC_ALARM_A) + { + /* AlarmA */ + sAlarm->Alarm = RTC_ALARM_A; + + tmpreg = READ_REG(RTC->ALRMAR); + subsecondtmpreg = (uint32_t)(READ_REG(RTC->ALRMASSR) & RTC_ALRMASSR_SS); + + /* Fill the structure with the read parameters */ + sAlarm->AlarmTime.Hours = (uint8_t)((tmpreg & (RTC_ALRMAR_HT | RTC_ALRMAR_HU)) >> RTC_ALRMAR_HU_Pos); + sAlarm->AlarmTime.Minutes = (uint8_t)((tmpreg & (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU)) >> RTC_ALRMAR_MNU_Pos); + sAlarm->AlarmTime.Seconds = (uint8_t)((tmpreg & (RTC_ALRMAR_ST | RTC_ALRMAR_SU)) >> RTC_ALRMAR_SU_Pos); + sAlarm->AlarmTime.TimeFormat = (uint8_t)((tmpreg & RTC_ALRMAR_PM) >> RTC_ALRMAR_PM_Pos); + sAlarm->AlarmTime.SubSeconds = (uint32_t) subsecondtmpreg; + sAlarm->AlarmDateWeekDay = (uint8_t)((tmpreg & (RTC_ALRMAR_DT | RTC_ALRMAR_DU)) >> RTC_ALRMAR_DU_Pos); + sAlarm->AlarmDateWeekDaySel = (uint32_t)(tmpreg & RTC_ALRMAR_WDSEL); + sAlarm->AlarmMask = (uint32_t)(tmpreg & RTC_ALARMMASK_ALL); + } + else + { + sAlarm->Alarm = RTC_ALARM_B; + + tmpreg = READ_REG(RTC->ALRMBR); + subsecondtmpreg = (uint32_t)(READ_REG(RTC->ALRMBSSR) & RTC_ALRMBSSR_SS); + + /* Fill the structure with the read parameters */ + sAlarm->AlarmTime.Hours = (uint8_t)((tmpreg & (RTC_ALRMBR_HT | RTC_ALRMBR_HU)) >> RTC_ALRMBR_HU_Pos); + sAlarm->AlarmTime.Minutes = (uint8_t)((tmpreg & (RTC_ALRMBR_MNT | RTC_ALRMBR_MNU)) >> RTC_ALRMBR_MNU_Pos); + sAlarm->AlarmTime.Seconds = (uint8_t)((tmpreg & (RTC_ALRMBR_ST | RTC_ALRMBR_SU)) >> RTC_ALRMBR_SU_Pos); + sAlarm->AlarmTime.TimeFormat = (uint8_t)((tmpreg & RTC_ALRMBR_PM) >> RTC_ALRMBR_PM_Pos); + sAlarm->AlarmTime.SubSeconds = (uint32_t) subsecondtmpreg; + sAlarm->AlarmDateWeekDay = (uint8_t)((tmpreg & (RTC_ALRMBR_DT | RTC_ALRMBR_DU)) >> RTC_ALRMBR_DU_Pos); + sAlarm->AlarmDateWeekDaySel = (uint32_t)(tmpreg & RTC_ALRMBR_WDSEL); + sAlarm->AlarmMask = (uint32_t)(tmpreg & RTC_ALARMMASK_ALL); + } + + if (Format == RTC_FORMAT_BIN) + { + sAlarm->AlarmTime.Hours = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours); + sAlarm->AlarmTime.Minutes = RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes); + sAlarm->AlarmTime.Seconds = RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds); + sAlarm->AlarmDateWeekDay = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay); + } + } + else + { + if (Alarm == RTC_ALARM_A) + { + sAlarm->Alarm = RTC_ALARM_A; + subsecondtmpreg = (uint32_t)(READ_REG(RTC->ALRABINR) & ((0x1UL << (sAlarm->AlarmSubSecondMask >> RTC_ALRMASSR_MASKSS_Pos)) - 1UL)); + } + else + { + sAlarm->Alarm = RTC_ALARM_B; + subsecondtmpreg = (uint32_t)(READ_REG(RTC->ALRBBINR) & ((0x1UL << (sAlarm->AlarmSubSecondMask >> RTC_ALRMBSSR_MASKSS_Pos)) - 1UL)); + } + + sAlarm->AlarmTime.SubSeconds = (uint32_t) subsecondtmpreg; + } + + return HAL_OK; +} + +/** + * @brief Handle Alarm interrupt request. + * @param hrtc RTC handle + * @retval None + */ +void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc) +{ + uint32_t tmp = READ_REG(RTC->MISR) & READ_REG(hrtc->IsEnabled.RtcFeatures); + + if ((tmp & RTC_MISR_ALRAMF) != 0U) + { + /* Clear the AlarmA interrupt pending bit */ + WRITE_REG(RTC->SCR, RTC_SCR_CALRAF); + +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + /* Call Compare Match registered Callback */ + hrtc->AlarmAEventCallback(hrtc); +#else + HAL_RTC_AlarmAEventCallback(hrtc); +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ + } + + if ((tmp & RTC_MISR_ALRBMF) != 0U) + { + /* Clear the AlarmB interrupt pending bit */ + WRITE_REG(RTC->SCR, RTC_SCR_CALRBF); + +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + /* Call Compare Match registered Callback */ + hrtc->AlarmBEventCallback(hrtc); +#else + HAL_RTCEx_AlarmBEventCallback(hrtc); +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ + } + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; +} + +/** + * @brief Alarm A callback. + * @param hrtc RTC handle + * @retval None + */ +__weak void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_RTC_AlarmAEventCallback could be implemented in the user file + */ +} + +/** + * @brief Handle AlarmA Polling request. + * @param hrtc RTC handle + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout) +{ + uint32_t tickstart = HAL_GetTick(); + + while (READ_BIT(RTC->SR, RTC_SR_ALRAF) == 0U) + { + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + hrtc->State = HAL_RTC_STATE_TIMEOUT; + return HAL_TIMEOUT; + } + } + } + + /* Clear the Alarm interrupt pending bit */ + WRITE_REG(RTC->SCR, RTC_SCR_CALRAF); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + return HAL_OK; +} + +/** + * @} + */ + +/** @addtogroup RTC_Exported_Functions_Group4 + * @brief Peripheral Control functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides functions allowing to + (+) Wait for RTC Time and Date Synchronization + +@endverbatim + * @{ + */ + +/** + * @brief Wait until the RTC Time and Date registers (RTC_TR and RTC_DR) are + * synchronized with RTC APB clock. + * @note The RTC Resynchronization mode is write protected, use the + * __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function. + * @note To read the calendar through the shadow registers after Calendar + * initialization, calendar update or after wakeup from low power modes + * the software must first clear the RSF flag. + * The software must then wait until it is set again before reading + * the calendar, which means that the calendar registers have been + * correctly copied into the RTC_TR and RTC_DR shadow registers. + * @param hrtc RTC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_WaitForSynchro(const RTC_HandleTypeDef *hrtc) +{ + uint32_t tickstart; + + UNUSED(hrtc); + /* Clear RSF flag */ + CLEAR_BIT(RTC->ICSR, RTC_ICSR_RSF); + + tickstart = HAL_GetTick(); + + /* Wait the registers to be synchronised */ + while (READ_BIT(RTC->ICSR, RTC_ICSR_RSF) == 0U) + { + if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + return HAL_OK; +} + +/** + * @} + */ + +/** @addtogroup RTC_Exported_Functions_Group5 + * @brief Peripheral State functions + * +@verbatim + =============================================================================== + ##### Peripheral State functions ##### + =============================================================================== + [..] + This subsection provides functions allowing to + (+) Get RTC state + +@endverbatim + * @{ + */ +/** + * @brief Return the RTC handle state. + * @param hrtc RTC handle + * @retval HAL state + */ +HAL_RTCStateTypeDef HAL_RTC_GetState(const RTC_HandleTypeDef *hrtc) +{ + /* Return RTC handle state */ + return hrtc->State; +} + +/** + * @} + */ +/** + * @} + */ + +/** @addtogroup RTC_Private_Functions + * @{ + */ +/** + * @brief Enter the RTC Initialization mode. + * @note The RTC Initialization mode is write protected, use the + * __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function. + * @param hrtc RTC handle + * @retval HAL status + */ +HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef *hrtc) +{ + uint32_t tickstart; + HAL_StatusTypeDef status = HAL_OK; + + UNUSED(hrtc); + /* Check if the Initialization mode is set */ + if (READ_BIT(RTC->ICSR, RTC_ICSR_INITF) == 0U) + { + /* Set the Initialization mode */ + SET_BIT(RTC->ICSR, RTC_ICSR_INIT); + + tickstart = HAL_GetTick(); + /* Wait till RTC is in INIT state and if Time out is reached exit */ + while ((READ_BIT(RTC->ICSR, RTC_ICSR_INITF) == 0U) && (status != HAL_TIMEOUT)) + { + if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) + { + status = HAL_TIMEOUT; + hrtc->State = HAL_RTC_STATE_TIMEOUT; + } + } + } + + return status; +} + +/** + * @brief Exit the RTC Initialization mode. + * @param hrtc RTC handle + * @retval HAL status + */ +HAL_StatusTypeDef RTC_ExitInitMode(RTC_HandleTypeDef *hrtc) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Exit Initialization mode */ + CLEAR_BIT(RTC->ICSR, RTC_ICSR_INIT); + + /* If CR_BYPSHAD bit = 0, wait for synchro */ + if (READ_BIT(RTC->CR, RTC_CR_BYPSHAD) == 0U) + { + if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) + { + hrtc->State = HAL_RTC_STATE_TIMEOUT; + status = HAL_TIMEOUT; + } + } + else /* WA 2.9.6 Calendar initialization may fail in case of consecutive INIT mode entry. */ + { + /* Clear BYPSHAD bit */ + CLEAR_BIT(RTC->CR, RTC_CR_BYPSHAD); + if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) + { + hrtc->State = HAL_RTC_STATE_TIMEOUT; + status = HAL_TIMEOUT; + } + /* Restore BYPSHAD bit */ + SET_BIT(RTC->CR, RTC_CR_BYPSHAD); + } + + return status; +} + +/** + * @brief Convert a 2 digit decimal to BCD format. + * @param Value Byte to be converted + * @retval Converted byte + */ +uint8_t RTC_ByteToBcd2(uint8_t Value) +{ + uint32_t bcdhigh = 0U; + uint8_t tmp_Value = Value; + + while (tmp_Value >= 10U) + { + bcdhigh++; + tmp_Value -= 10U; + } + + return ((uint8_t)(bcdhigh << 4U) | tmp_Value); +} + +/** + * @brief Convert from 2 digit BCD to Binary. + * @param Value BCD value to be converted + * @retval Converted word + */ +uint8_t RTC_Bcd2ToByte(uint8_t Value) +{ + uint32_t tmp; + tmp = (((uint32_t)Value & 0xF0U) >> 4) * 10U; + return (uint8_t)(tmp + ((uint32_t)Value & 0x0FU)); +} + +/** + * @} + */ + +#endif /* HAL_RTC_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ diff --git a/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c b/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c new file mode 100644 index 0000000..42f311f --- /dev/null +++ b/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c @@ -0,0 +1,2177 @@ +/** + ****************************************************************************** + * @file stm32wlxx_hal_rtc_ex.c + * @author MCD Application Team + * @brief Extended RTC HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Real Time Clock (RTC) Extended peripheral: + * + RTC Time Stamp functions + * + RTC Tamper functions + * + RTC Wake-up functions + * + Extended Control functions + * + Extended RTC features functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (+) Enable the RTC domain access. + (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour + format using the HAL_RTC_Init() function. + + *** RTC Wakeup configuration *** + ================================ + [..] + (+) To configure the RTC Wakeup Clock source and Counter use the HAL_RTCEx_SetWakeUpTimer() + function. You can also configure the RTC Wakeup timer with interrupt mode + using the HAL_RTCEx_SetWakeUpTimer_IT() function. + (+) To read the RTC WakeUp Counter register, use the HAL_RTCEx_GetWakeUpTimer() + function. + + *** Outputs configuration *** + ============================= + [..] The RTC has 2 different outputs: + (+) RTC_ALARM: this output is used to manage the RTC Alarm A, Alarm B + and WaKeUp signals. + To output the selected RTC signal, use the HAL_RTC_Init() function. + (+) RTC_CALIB: this output is 512Hz signal or 1Hz. + To enable the RTC_CALIB, use the HAL_RTCEx_SetCalibrationOutPut() function. + (+) Two pins can be used as RTC_ALARM or RTC_CALIB (PC13, PB2) managed on + the RTC_OR register. + (+) When the RTC_CALIB or RTC_ALARM output is selected, the RTC_OUT pin is + automatically configured in output alternate function. + + *** Smooth digital Calibration configuration *** + ================================================ + [..] + (+) Configure the RTC Original Digital Calibration Value and the corresponding + calibration cycle period (32s,16s and 8s) using the HAL_RTCEx_SetSmoothCalib() + function. + + *** TimeStamp configuration *** + =============================== + [..] + (+) Enable the RTC TimeStamp using the HAL_RTCEx_SetTimeStamp() function. + You can also configure the RTC TimeStamp with interrupt mode using the + HAL_RTCEx_SetTimeStamp_IT() function. + (+) To read the RTC TimeStamp Time and Date register, use the HAL_RTCEx_GetTimeStamp() + function. + + *** Internal TimeStamp configuration *** + =============================== + [..] + (+) Enable the RTC internal TimeStamp using the HAL_RTCEx_SetInternalTimeStamp() function. + User has to check internal timestamp occurrence using __HAL_RTC_INTERNAL_TIMESTAMP_GET_FLAG. + (+) To read the RTC TimeStamp Time and Date register, use the HAL_RTCEx_GetTimeStamp() + function. + + *** Tamper configuration *** + ============================ + [..] + (+) Enable the RTC Tamper and configure the Tamper filter count, trigger Edge + or Level according to the Tamper filter (if equal to 0 Edge else Level) + value, sampling frequency, NoErase, MaskFlag, precharge or discharge and + Pull-UP using the HAL_RTCEx_SetTamper() function. You can configure RTC Tamper + with interrupt mode using HAL_RTCEx_SetTamper_IT() function. + (+) The default configuration of the Tamper erases the backup registers. To avoid + erase, enable the NoErase field on the RTC_TAMPCR register. + (+) With new RTC tamper configuration, you have to call HAL_RTC_Init() in order to + perform TAMP base address offset calculation. + (+) If you do not intend to have tamper using RTC clock, you can bypass its initialization + by setting ClockEnable inti field to RTC_CLOCK_DISABLE. + (+) Enable Internal tamper using HAL_RTCEx_SetInternalTamper. IT mode can be chosen using + setting Interrupt field. + + *** Backup Data Registers configuration *** + =========================================== + [..] + (+) To write to the RTC Backup Data registers, use the HAL_RTCEx_BKUPWrite() + function. + (+) To read the RTC Backup Data registers, use the HAL_RTCEx_BKUPRead() + function. + (+) Before calling these functions you have to call HAL_RTC_Init() in order to + perform TAMP base address offset calculation. + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wlxx_hal.h" + +/** @addtogroup STM32WLxx_HAL_Driver + * @{ + */ + +/** @addtogroup RTCEx + * @brief RTC Extended HAL module driver + * @{ + */ + +#ifdef HAL_RTC_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @addtogroup RTCEx_Private_Defines + * @{ + */ +#define TAMP_ALL (TAMP_CR1_TAMP1E | TAMP_CR1_TAMP2E | TAMP_CR1_TAMP3E) +/** + * @} + */ + + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup RTCEx_Exported_Functions + * @{ + */ + + +/** @addtogroup RTCEx_Exported_Functions_Group1 + * @brief RTC TimeStamp and Tamper functions + * +@verbatim + =============================================================================== + ##### RTC TimeStamp and Tamper functions ##### + =============================================================================== + + [..] This section provides functions allowing to configure TimeStamp feature + +@endverbatim + * @{ + */ + +/** + * @brief Set TimeStamp. + * @note This API must be called before enabling the TimeStamp feature. + * @param hrtc RTC handle + * @param TimeStampEdge Specifies the pin edge on which the TimeStamp is + * activated. + * This parameter can be one of the following values: + * @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the + * rising edge of the related pin. + * @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the + * falling edge of the related pin. + * @param RTC_TimeStampPin specifies the RTC TimeStamp Pin. + * This parameter can be one of the following values: + * @arg RTC_TIMESTAMPPIN_DEFAULT: PC13 is selected as RTC TimeStamp Pin. + * The RTC TimeStamp Pin is per default PC13, but for reasons of + * compatibility, this parameter is required. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin) +{ + /* Check the parameters */ + assert_param(IS_TIMESTAMP_EDGE(TimeStampEdge)); + assert_param(IS_RTC_TIMESTAMP_PIN(RTC_TimeStampPin)); + UNUSED(RTC_TimeStampPin); + + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Get the RTC_CR register and clear the bits to be configured */ + CLEAR_BIT(RTC->CR, (RTC_CR_TSEDGE | RTC_CR_TSE)); + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /* Configure the Time Stamp TSEDGE and Enable bits */ + SET_BIT(RTC->CR, (uint32_t)TimeStampEdge | RTC_CR_TSE); + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Set TimeStamp with Interrupt. + * @note This API must be called before enabling the TimeStamp feature. + * @param hrtc RTC handle + * @param TimeStampEdge Specifies the pin edge on which the TimeStamp is + * activated. + * This parameter can be one of the following values: + * @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the + * rising edge of the related pin. + * @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the + * falling edge of the related pin. + * @param RTC_TimeStampPin Specifies the RTC TimeStamp Pin. + * This parameter can be one of the following values: + * @arg RTC_TIMESTAMPPIN_DEFAULT: PC13 is selected as RTC TimeStamp Pin. + * The RTC TimeStamp Pin is per default PC13, but for reasons of + * compatibility, this parameter is required. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin) +{ + /* Check the parameters */ + assert_param(IS_TIMESTAMP_EDGE(TimeStampEdge)); + assert_param(IS_RTC_TIMESTAMP_PIN(RTC_TimeStampPin)); + UNUSED(RTC_TimeStampPin); + + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /* Get the RTC_CR register and clear the bits to be configured */ + CLEAR_BIT(RTC->CR, (RTC_CR_TSEDGE | RTC_CR_TSE | RTC_CR_TSIE)); + + /* Configure the Time Stamp TSEDGE before Enable bit to avoid unwanted TSF setting. */ + SET_BIT(RTC->CR, (uint32_t)TimeStampEdge); + + /* Enable timestamp and IT */ + SET_BIT(RTC->CR, RTC_CR_TSE | RTC_CR_TSIE); + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + /* RTC timestamp Interrupt Configuration: EXTI configuration */ + __HAL_RTC_TIMESTAMP_EXTI_ENABLE_IT(); + + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Deactivate TimeStamp. + * @param hrtc RTC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc) +{ + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /* In case of interrupt mode is used, the interrupt source must disabled */ + CLEAR_BIT(RTC->CR, (RTC_CR_TSEDGE | RTC_CR_TSE | RTC_CR_TSIE)); + + /* Clear timestamp flag only if internal timestamp flag not set */ + if (READ_BIT(RTC->SR, RTC_SR_ITSF) == 0U) + { + WRITE_REG(RTC->SCR, RTC_SCR_CTSF); + } + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Set Internal TimeStamp. + * @note This API must be called before enabling the internal TimeStamp feature. + * @param hrtc RTC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_SetInternalTimeStamp(RTC_HandleTypeDef *hrtc) +{ + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /* Configure the internal Time Stamp Enable bits */ + SET_BIT(RTC->CR, RTC_CR_ITSE); + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Deactivate Internal TimeStamp. + * @param hrtc RTC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_DeactivateInternalTimeStamp(RTC_HandleTypeDef *hrtc) +{ + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /* Configure the internal Time Stamp Enable bits */ + CLEAR_BIT(RTC->CR, RTC_CR_ITSE); + + /* Clear internal timestamp flag if Timestamp not enabled and TSOVF not set */ + WRITE_REG(RTC->SCR, RTC_SCR_CITSF); + if (READ_BIT(RTC->SR, RTC_SR_TSOVF) == 0U) + { + if (READ_BIT(RTC->CR, RTC_CR_TSE) == 0U) + { + WRITE_REG(RTC->SCR, RTC_SCR_CTSF); + } + } + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Get the RTC TimeStamp value. + * @param hrtc RTC handle + * @param sTimeStamp Pointer to Time structure + * if BinMode = RTC_BINARY_ONLY, sTimeStamp->SubSeconds only is used + * @param sTimeStampDate Pointer to Date structure + * if BinMode = RTC_BINARY_ONLY, this parameter is not used. + * @param Format specifies the format of the entered parameters. + * if BinMode = RTC_BINARY_ONLY, this parameter is not used + * else this parameter can be one of the following values + * @arg RTC_FORMAT_BIN: Binary data format + * @arg RTC_FORMAT_BCD: BCD data format + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTimeStamp, + RTC_DateTypeDef *sTimeStampDate, uint32_t Format) +{ + uint32_t tmptime; + uint32_t tmpdate; + UNUSED(hrtc); + + sTimeStamp->SubSeconds = READ_REG(RTC->TSSSR); + if (READ_BIT(RTC->ICSR, RTC_ICSR_BIN) != RTC_BINARY_ONLY) + { + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(Format)); + + /* Get the TimeStamp time and date registers values */ + tmptime = READ_BIT(RTC->TSTR, RTC_TR_RESERVED_MASK); + tmpdate = READ_BIT(RTC->TSDR, RTC_DR_RESERVED_MASK); + + /* Fill the Time structure fields with the read parameters */ + sTimeStamp->Hours = (uint8_t)((tmptime & (RTC_TSTR_HT | RTC_TSTR_HU)) >> RTC_TSTR_HU_Pos); + sTimeStamp->Minutes = (uint8_t)((tmptime & (RTC_TSTR_MNT | RTC_TSTR_MNU)) >> RTC_TSTR_MNU_Pos); + sTimeStamp->Seconds = (uint8_t)((tmptime & (RTC_TSTR_ST | RTC_TSTR_SU)) >> RTC_TSTR_SU_Pos); + sTimeStamp->TimeFormat = (uint8_t)((tmptime & (RTC_TSTR_PM)) >> RTC_TSTR_PM_Pos); + sTimeStamp->SubSeconds = READ_BIT(RTC->TSSSR, RTC_TSSSR_SS); + + /* Fill the Date structure fields with the read parameters */ + sTimeStampDate->Year = 0U; + sTimeStampDate->Month = (uint8_t)((tmpdate & (RTC_TSDR_MT | RTC_TSDR_MU)) >> RTC_TSDR_MU_Pos); + sTimeStampDate->Date = (uint8_t)(tmpdate & (RTC_TSDR_DT | RTC_TSDR_DU)); + sTimeStampDate->WeekDay = (uint8_t)((tmpdate & (RTC_TSDR_WDU)) >> RTC_TSDR_WDU_Pos); + + /* Check the input parameters format */ + if (Format == RTC_FORMAT_BIN) + { + /* Convert the TimeStamp structure parameters to Binary format */ + sTimeStamp->Hours = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Hours); + sTimeStamp->Minutes = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Minutes); + sTimeStamp->Seconds = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Seconds); + + /* Convert the DateTimeStamp structure parameters to Binary format */ + sTimeStampDate->Month = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->Month); + sTimeStampDate->Date = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->Date); + sTimeStampDate->WeekDay = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->WeekDay); + } + } + + /* Clear the TIMESTAMP Flags */ + WRITE_REG(RTC->SCR, (RTC_SCR_CITSF | RTC_SCR_CTSF)); + + return HAL_OK; +} + +/** + * @brief Handle TimeStamp interrupt request. + * @param hrtc RTC handle + * @retval None + */ +void HAL_RTCEx_TimeStampIRQHandler(RTC_HandleTypeDef *hrtc) +{ + if (READ_BIT(RTC->MISR, RTC_MISR_TSMF) != 0U) + { +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + /* Call TimeStampEvent registered Callback */ + hrtc->TimeStampEventCallback(hrtc); +#else + HAL_RTCEx_TimeStampEventCallback(hrtc); +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ + /* Clearing flags after the Callback because the content of RTC_TSTR and RTC_TSDR are cleared when TSF bit is reset.*/ + WRITE_REG(RTC->SCR, RTC_SCR_CITSF | RTC_SCR_CTSF); + } + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; +} + +/** + * @brief TimeStamp callback. + * @param hrtc RTC handle + * @retval None + */ +__weak void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_RTCEx_TimeStampEventCallback could be implemented in the user file + */ +} + +/** + * @brief Handle TimeStamp polling request. + * @param hrtc RTC handle + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout) +{ + uint32_t tickstart = HAL_GetTick(); + + while (READ_BIT(RTC->SR, RTC_SR_TSF) == 0U) + { + if (READ_BIT(RTC->SR, RTC_SR_TSOVF) != 0U) + { + /* Clear the TIMESTAMP OverRun Flag */ + WRITE_REG(RTC->SCR, RTC_SCR_CTSOVF); + + /* Change TIMESTAMP state */ + hrtc->State = HAL_RTC_STATE_ERROR; + + return HAL_ERROR; + } + + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + hrtc->State = HAL_RTC_STATE_TIMEOUT; + return HAL_TIMEOUT; + } + } + } + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + return HAL_OK; +} + +/** + * @} + */ + +/** @addtogroup RTCEx_Exported_Functions_Group2 + * @brief RTC Wake-up functions + * +@verbatim + =============================================================================== + ##### RTC Wake-up functions ##### + =============================================================================== + + [..] This section provides functions allowing to configure Wake-up feature + +@endverbatim + * @{ + */ + +/** + * @brief Set wake up timer. + * @param hrtc RTC handle + * @param WakeUpCounter Wake up counter + * @param WakeUpClock Wake up clock + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock) +{ + uint32_t tickstart; + + /* Check the parameters */ + assert_param(IS_RTC_WAKEUP_CLOCK(WakeUpClock)); + assert_param(IS_RTC_WAKEUP_COUNTER(WakeUpCounter)); + + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /* Clear WUTE in RTC_CR to disable the wakeup timer */ + CLEAR_BIT(RTC->CR, RTC_CR_WUTE); + + /* Poll WUTWF until it is set in RTC_ICSR to make sure the access to wakeup autoreload + counter and to WUCKSEL[2:0] bits is allowed. This step must be skipped in + calendar initialization mode. */ + if (READ_BIT(RTC->ICSR, RTC_ICSR_INITF) == 0U) + { + tickstart = HAL_GetTick(); + while (READ_BIT(RTC->ICSR, RTC_ICSR_WUTWF) == 0U) + { + if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + hrtc->State = HAL_RTC_STATE_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_TIMEOUT; + } + } + } + + /* Configure the clock source */ + MODIFY_REG(RTC->CR, RTC_CR_WUCKSEL, (uint32_t)WakeUpClock); + + /* Configure the Wakeup Timer counter */ + WRITE_REG(RTC->WUTR, (uint32_t)WakeUpCounter); + + /* Enable the Wakeup Timer */ + SET_BIT(RTC->CR, RTC_CR_WUTE); + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Set wake up timer with interrupt. + * @param hrtc RTC handle + * @param WakeUpCounter Wake up counter + * @param WakeUpClock Wake up clock + * @param WakeUpAutoClr Wake up auto clear value (look at WUTOCLR in reference manual) + * - No effect if WakeUpAutoClr is set to zero + * - This feature is meaningful in case of Low power mode to avoid any RTC software execution after Wake Up. + * That is why when WakeUpAutoClr is set, EXTI is configured as EVENT instead of Interrupt to avoid useless IRQ handler execution. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock, + uint32_t WakeUpAutoClr) +{ + uint32_t tickstart; + + /* Check the parameters */ + assert_param(IS_RTC_WAKEUP_CLOCK(WakeUpClock)); + assert_param(IS_RTC_WAKEUP_COUNTER(WakeUpCounter)); + /* (0x0000<=WUTOCLR<=WUT) */ + assert_param(WakeUpAutoClr <= WakeUpCounter); + + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /* Clear WUTE in RTC_CR to disable the wakeup timer */ + CLEAR_BIT(RTC->CR, RTC_CR_WUTE); + + /* Clear flag Wake-Up */ + WRITE_REG(RTC->SCR, RTC_SCR_CWUTF); + + /* Poll WUTWF until it is set in RTC_ICSR to make sure the access to wakeup autoreload + counter and to WUCKSEL[2:0] bits is allowed. This step must be skipped in + calendar initialization mode. */ + if (READ_BIT(RTC->ICSR, RTC_ICSR_INITF) == 0U) + { + tickstart = HAL_GetTick(); + while (READ_BIT(RTC->ICSR, RTC_ICSR_WUTWF) == 0U) + { + if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + hrtc->State = HAL_RTC_STATE_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_TIMEOUT; + } + } + } + + /* Configure the Wakeup Timer counter and auto clear value */ + WRITE_REG(RTC->WUTR, (uint32_t)(WakeUpCounter | (WakeUpAutoClr << RTC_WUTR_WUTOCLR_Pos))); + + /* Configure the clock source */ + MODIFY_REG(RTC->CR, RTC_CR_WUCKSEL, (uint32_t)WakeUpClock); + + /* In case of WUT autoclr, the IRQ handler should not be called */ + if (WakeUpAutoClr != 0U) + { + /* RTC WakeUpTimer EXTI Configuration: Event configuration */ + __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_EVENT(); + } + else + { + /* RTC WakeUpTimer EXTI Configuration: Interrupt configuration */ + __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT(); + } + + /* Configure the Interrupt in the RTC_CR register and Enable the Wakeup Timer*/ + SET_BIT(RTC->CR, (RTC_CR_WUTIE | RTC_CR_WUTE)); + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Deactivate wake up timer counter. + * @param hrtc RTC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc) +{ + uint32_t tickstart; + + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /* Disable the Wakeup Timer */ + /* In case of interrupt mode is used, the interrupt source must disabled */ + CLEAR_BIT(RTC->CR, (RTC_CR_WUTE | RTC_CR_WUTIE)); + + tickstart = HAL_GetTick(); + /* Wait till RTC WUTWF flag is set and if Time out is reached exit */ + while (READ_BIT(RTC->ICSR, RTC_ICSR_WUTWF) == 0U) + { + if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + hrtc->State = HAL_RTC_STATE_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_TIMEOUT; + } + } + + /* Clear wakeup timer flag */ + WRITE_REG(RTC->SCR, RTC_SCR_CWUTF); + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Get wake up timer counter. + * @param hrtc RTC handle + * @retval Counter value + */ +uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc) +{ + UNUSED(hrtc); + /* Get the counter value */ + return (uint32_t)(READ_BIT(RTC->WUTR, RTC_WUTR_WUT)); +} + +/** + * @brief Handle Wake Up Timer interrupt request. + * @param hrtc RTC handle + * @retval None + */ +void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc) +{ + if (READ_BIT(RTC->MISR, RTC_MISR_WUTMF) != 0U) + { + /* Clear the WAKEUPTIMER interrupt pending bit */ + WRITE_REG(RTC->SCR, RTC_SCR_CWUTF); + +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + /* Call WakeUpTimerEvent registered Callback */ + hrtc->WakeUpTimerEventCallback(hrtc); +#else + /* WAKEUPTIMER callback */ + HAL_RTCEx_WakeUpTimerEventCallback(hrtc); +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ + } + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; +} + +/** + * @brief Wake Up Timer callback. + * @param hrtc RTC handle + * @retval None + */ +__weak void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_RTCEx_WakeUpTimerEventCallback could be implemented in the user file + */ +} + + +/** + * @brief Handle Wake Up Timer Polling. + * @param hrtc RTC handle + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout) +{ + uint32_t tickstart = HAL_GetTick(); + + while (READ_BIT(RTC->SR, RTC_SR_WUTF) == 0U) + { + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + hrtc->State = HAL_RTC_STATE_TIMEOUT; + return HAL_TIMEOUT; + } + } + } + + /* Clear the WAKEUPTIMER Flag */ + WRITE_REG(RTC->SCR, RTC_SCR_CWUTF); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + return HAL_OK; +} + +/** + * @} + */ + + +/** @addtogroup RTCEx_Exported_Functions_Group3 + * @brief Extended Peripheral Control functions + * +@verbatim + =============================================================================== + ##### Extended Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides functions allowing to + (+) Write a data in a specified RTC Backup data register + (+) Read a data in a specified RTC Backup data register + (+) Set the Coarse calibration parameters. + (+) Deactivate the Coarse calibration parameters + (+) Set the Smooth calibration parameters. + (+) Set Low Power calibration parameter. + (+) Configure the Synchronization Shift Control Settings. + (+) Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz). + (+) Deactivate the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz). + (+) Enable the RTC reference clock detection. + (+) Disable the RTC reference clock detection. + (+) Enable the Bypass Shadow feature. + (+) Disable the Bypass Shadow feature. + +@endverbatim + * @{ + */ + + + +/** + * @brief Set the Smooth calibration parameters. + * @note To deactivate the smooth calibration, the field SmoothCalibPlusPulses + * must be equal to SMOOTHCALIB_PLUSPULSES_RESET and the field + * SmoothCalibMinusPulsesValue must be equal to 0. + * @param hrtc RTC handle + * @param SmoothCalibPeriod Select the Smooth Calibration Period. + * This parameter can be can be one of the following values : + * @arg RTC_SMOOTHCALIB_PERIOD_32SEC: The smooth calibration period is 32s. + * @arg RTC_SMOOTHCALIB_PERIOD_16SEC: The smooth calibration period is 16s. + * @arg RTC_SMOOTHCALIB_PERIOD_8SEC: The smooth calibration period is 8s. + * @param SmoothCalibPlusPulses Select to Set or reset the CALP bit. + * This parameter can be one of the following values: + * @arg RTC_SMOOTHCALIB_PLUSPULSES_SET: Add one RTCCLK pulse every 2*11 pulses. + * @arg RTC_SMOOTHCALIB_PLUSPULSES_RESET: No RTCCLK pulses are added. + * @param SmoothCalibMinusPulsesValue Select the value of CALM[8:0] bits. + * This parameter can be one any value from 0 to 0x000001FF. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef *hrtc, uint32_t SmoothCalibPeriod, + uint32_t SmoothCalibPlusPulses, uint32_t SmoothCalibMinusPulsesValue) +{ + uint32_t tickstart; + + /* Check the parameters */ + assert_param(IS_RTC_SMOOTH_CALIB_PERIOD(SmoothCalibPeriod)); + assert_param(IS_RTC_SMOOTH_CALIB_PLUS(SmoothCalibPlusPulses)); + assert_param(IS_RTC_SMOOTH_CALIB_MINUS(SmoothCalibMinusPulsesValue)); + + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /* check if a calibration is pending*/ + if (READ_BIT(RTC->ICSR, RTC_ICSR_RECALPF) != 0U) + { + tickstart = HAL_GetTick(); + + /* check if a calibration is pending*/ + while (READ_BIT(RTC->ICSR, RTC_ICSR_RECALPF) != 0U) + { + if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_TIMEOUT; + } + } + } + + /* Configure the Smooth calibration settings */ + MODIFY_REG(RTC->CALR, (RTC_CALR_CALP | RTC_CALR_CALW8 | RTC_CALR_CALW16 | RTC_CALR_CALM), + (uint32_t)(SmoothCalibPeriod | SmoothCalibPlusPulses | SmoothCalibMinusPulsesValue)); + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Select the low power Calibration mode. + * @param hrtc: RTC handle + * @param LowPowerCalib: Low power Calibration mode. + * This parameter can be can be one of the following values : + * @arg RTC_LPCAL_SET: Low power mode. + * @arg RTC_LPCAL_RESET: High consumption mode. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_SetLowPowerCalib(RTC_HandleTypeDef *hrtc, uint32_t LowPowerCalib) +{ + /* Check the parameters */ + assert_param(IS_RTC_LOW_POWER_CALIB(LowPowerCalib)); + + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /* Configure the Smooth calibration settings */ + MODIFY_REG(RTC->CALR, RTC_CALR_LPCAL, LowPowerCalib); + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Configure the Synchronization Shift Control Settings. + * @note When REFCKON is set, firmware must not write to Shift control register. + * @param hrtc RTC handle + * @param ShiftAdd1S Select to add or not 1 second to the time calendar. + * This parameter can be one of the following values: + * @arg RTC_SHIFTADD1S_SET: Add one second to the clock calendar. + * @arg RTC_SHIFTADD1S_RESET: No effect. + * @param ShiftSubFS Select the number of Second Fractions to substitute. + * This parameter can be one any value from 0 to 0x7FFF. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef *hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS) +{ + uint32_t tickstart; + + /* Check the parameters */ + assert_param(IS_RTC_SHIFT_ADD1S(ShiftAdd1S)); + assert_param(IS_RTC_SHIFT_SUBFS(ShiftSubFS)); + + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + tickstart = HAL_GetTick(); + + /* Wait until the shift is completed*/ + while (READ_BIT(RTC->ICSR, RTC_ICSR_SHPF) != 0U) + { + if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + hrtc->State = HAL_RTC_STATE_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_TIMEOUT; + } + } + + /* Check if the reference clock detection is disabled */ + if (READ_BIT(RTC->CR, RTC_CR_REFCKON) == 0U) + { + /* Configure the Shift settings */ + MODIFY_REG(RTC->SHIFTR, RTC_SHIFTR_SUBFS, (uint32_t)(ShiftSubFS) | (uint32_t)(ShiftAdd1S)); + + /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ + if (READ_BIT(RTC->CR, RTC_CR_BYPSHAD) == 0U) + { + if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + hrtc->State = HAL_RTC_STATE_ERROR; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_ERROR; + } + } + } + else + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_ERROR; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_ERROR; + } + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz). + * @param hrtc RTC handle + * @param CalibOutput Select the Calibration output Selection . + * This parameter can be one of the following values: + * @arg RTC_CALIBOUTPUT_512HZ: A signal has a regular waveform at 512Hz. + * @arg RTC_CALIBOUTPUT_1HZ: A signal has a regular waveform at 1Hz. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef *hrtc, uint32_t CalibOutput) +{ + /* Check the parameters */ + assert_param(IS_RTC_CALIB_OUTPUT(CalibOutput)); + + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /* Configure the RTC_CR register */ + MODIFY_REG(RTC->CR, RTC_CR_COSEL, CalibOutput); + + /* Enable calibration output */ + SET_BIT(RTC->CR, RTC_CR_COE); + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Deactivate the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz). + * @param hrtc RTC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef *hrtc) +{ + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /* Disable calibration output */ + CLEAR_BIT(RTC->CR, RTC_CR_COE); + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Enable the RTC reference clock detection. + * @param hrtc RTC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef *hrtc) +{ + HAL_StatusTypeDef status; + + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /* Enter Initialization mode */ + status = RTC_EnterInitMode(hrtc); + if (status == HAL_OK) + { + /* Enable clockref detection */ + SET_BIT(RTC->CR, RTC_CR_REFCKON); + + /* Exit Initialization mode */ + status = RTC_ExitInitMode(hrtc); + } + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + if (status == HAL_OK) + { + hrtc->State = HAL_RTC_STATE_READY; + } + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return status; +} + +/** + * @brief Disable the RTC reference clock detection. + * @param hrtc RTC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef *hrtc) +{ + HAL_StatusTypeDef status; + + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /* Enter Initialization mode */ + status = RTC_EnterInitMode(hrtc); + if (status == HAL_OK) + { + /* Disable clockref detection */ + CLEAR_BIT(RTC->CR, RTC_CR_REFCKON); + + /* Exit Initialization mode */ + status = RTC_ExitInitMode(hrtc); + } + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + if (status == HAL_OK) + { + hrtc->State = HAL_RTC_STATE_READY; + } + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return status; +} + +/** + * @brief Enable the Bypass Shadow feature. + * @note When the Bypass Shadow is enabled the calendar value are taken + * directly from the Calendar counter. + * @param hrtc RTC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef *hrtc) +{ + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /* Set the BYPSHAD bit */ + SET_BIT(RTC->CR, RTC_CR_BYPSHAD); + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Disable the Bypass Shadow feature. + * @note When the Bypass Shadow is enabled the calendar value are taken + * directly from the Calendar counter. + * @param hrtc RTC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef *hrtc) +{ + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /* Reset the BYPSHAD bit */ + CLEAR_BIT(RTC->CR, RTC_CR_BYPSHAD); + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Increment Monotonic counter. + * @param hrtc RTC handle + * @param Instance Monotonic counter Instance + * This parameter can be can be one of the following values : + * @arg RTC_MONOTONIC_COUNTER_1 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_MonotonicCounterIncrement(RTC_HandleTypeDef *hrtc, uint32_t Instance) +{ + UNUSED(hrtc); + UNUSED(Instance); + /* This register is read-only only and is incremented by one when a write access is done to this + register. This register cannot roll-over and is frozen when reaching the maximum value. */ + CLEAR_REG(TAMP->COUNTR); + + return HAL_OK; +} + +/** + * @brief Monotonic counter incrementation. + * @param hrtc RTC handle + * @param Instance Monotonic counter Instance + * This parameter can be can be one of the following values : + * @arg RTC_MONOTONIC_COUNTER_1 + * @param Value Pointer to the counter monotonic counter value + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_MonotonicCounterGet(RTC_HandleTypeDef *hrtc, uint32_t Instance, uint32_t *Value) +{ + UNUSED(hrtc); + UNUSED(Instance); + + /* This register is read-only only and is incremented by one when a write access is done to this + register. This register cannot roll-over and is frozen when reaching the maximum value. */ + *Value = READ_REG(TAMP->COUNTR); + + return HAL_OK; +} + +/** + * @brief Set SSR Underflow detection with Interrupt. + * @param hrtc RTC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_SetSSRU_IT(RTC_HandleTypeDef *hrtc) +{ + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /* Enable IT SSRU */ + __HAL_RTC_SSRU_ENABLE_IT(hrtc, RTC_IT_SSRU); + + /* RTC SSRU Interrupt Configuration: EXTI configuration */ + __HAL_RTC_SSRU_EXTI_ENABLE_IT(); + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Deactivate SSR Underflow. + * @param hrtc RTC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_DeactivateSSRU(RTC_HandleTypeDef *hrtc) +{ + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /* In case of interrupt mode is used, the interrupt source must disabled */ + __HAL_RTC_SSRU_DISABLE_IT(hrtc, RTC_IT_TS); + + /* Clear SSR underflow flag */ + WRITE_REG(RTC->SCR, RTC_SCR_CSSRUF); + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Handle SSR underflow interrupt request. + * @param hrtc RTC handle + * @retval None + */ +void HAL_RTCEx_SSRUIRQHandler(RTC_HandleTypeDef *hrtc) +{ + if ((RTC->MISR & RTC_MISR_SSRUMF) != 0u) + { + /* Immediately clear flags */ + RTC->SCR = RTC_SCR_CSSRUF; + + /* SSRU callback */ +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + /* Call SSRUEvent registered Callback */ + hrtc->SSRUEventCallback(hrtc); +#else + HAL_RTCEx_SSRUEventCallback(hrtc); +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ + } + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; +} + +/** + * @brief SSR underflow callback. + * @param hrtc RTC handle + * @retval None + */ +__weak void HAL_RTCEx_SSRUEventCallback(RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_RTCEx_SSRUEventCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @addtogroup RTCEx_Exported_Functions_Group4 + * @brief Extended features functions + * +@verbatim + =============================================================================== + ##### Extended features functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) RTC Alarm B callback + (+) RTC Poll for Alarm B request + +@endverbatim + * @{ + */ + +/** + * @brief Alarm B callback. + * @param hrtc RTC handle + * @retval None + */ +__weak void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_RTCEx_AlarmBEventCallback could be implemented in the user file + */ +} + +/** + * @brief Handle Alarm B Polling request. + * @param hrtc RTC handle + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout) +{ + uint32_t tickstart = HAL_GetTick(); + + while (READ_BIT(RTC->SR, RTC_SR_ALRBF) == 0U) + { + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + hrtc->State = HAL_RTC_STATE_TIMEOUT; + return HAL_TIMEOUT; + } + } + } + + /* Clear the Alarm Flag */ + WRITE_REG(RTC->SCR, RTC_SCR_CALRBF); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + return HAL_OK; +} + +/** + * @} + */ + +/** @addtogroup RTCEx_Exported_Functions_Group5 + * @brief Extended RTC Tamper functions + * +@verbatim + ============================================================================== + ##### Tamper functions ##### + ============================================================================== + [..] + (+) Before calling any tamper or internal tamper function, you have to call first + HAL_RTC_Init() function. + (+) In that ine you can select to output tamper event on RTC pin. + [..] + (+) Enable the Tamper and configure the Tamper filter count, trigger Edge + or Level according to the Tamper filter (if equal to 0 Edge else Level) + value, sampling frequency, NoErase, MaskFlag, precharge or discharge and + Pull-UP, timestamp using the HAL_RTCEx_SetTamper() function. + You can configure Tamper with interrupt mode using HAL_RTCEx_SetTamper_IT() function. + (+) The default configuration of the Tamper erases the backup registers. To avoid + erase, enable the NoErase field on the TAMP_TAMPCR register. + [..] + (+) Enable Internal Tamper and configure it with interrupt, timestamp using + the HAL_RTCEx_SetInternalTamper() function. + +@endverbatim + * @{ + */ + + +/** + * @brief Set Tamper + * @param hrtc RTC handle + * @param sTamper Pointer to Tamper Structure. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper) +{ + uint32_t tmpreg; + + /* Check the parameters */ + assert_param(IS_RTC_TAMPER(sTamper->Tamper)); + assert_param(IS_RTC_TAMPER_TRIGGER(sTamper->Trigger)); + assert_param(IS_RTC_TAMPER_ERASE_MODE(sTamper->NoErase)); + assert_param(IS_RTC_TAMPER_MASKFLAG_STATE(sTamper->MaskFlag)); + assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection)); + assert_param(IS_RTC_TAMPER_FILTER(sTamper->Filter)); + assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency)); + assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration)); + assert_param(IS_RTC_TAMPER_PULLUP_STATE(sTamper->TamperPullUp)); + /* Trigger and Filter have exclusive configurations */ + assert_param(((sTamper->Filter != RTC_TAMPERFILTER_DISABLE) && ((sTamper->Trigger == RTC_TAMPERTRIGGER_LOWLEVEL) || (sTamper->Trigger == RTC_TAMPERTRIGGER_HIGHLEVEL))) + || ((sTamper->Filter == RTC_TAMPERFILTER_DISABLE) && ((sTamper->Trigger == RTC_TAMPERTRIGGER_RISINGEDGE) || (sTamper->Trigger == RTC_TAMPERTRIGGER_FALLINGEDGE)))); + + /* Configuration register 2 */ + tmpreg = READ_REG(TAMP->CR2); + tmpreg &= ~((sTamper->Tamper << TAMP_CR2_TAMP1TRG_Pos) | (sTamper->Tamper << TAMP_CR2_TAMP1MSK_Pos) | (sTamper->Tamper << TAMP_CR2_TAMP1NOERASE_Pos)); + + if ((sTamper->Trigger == RTC_TAMPERTRIGGER_HIGHLEVEL) || (sTamper->Trigger == RTC_TAMPERTRIGGER_FALLINGEDGE)) + { + tmpreg |= (sTamper->Tamper << TAMP_CR2_TAMP1TRG_Pos); + } + + if (sTamper->MaskFlag != RTC_TAMPERMASK_FLAG_DISABLE) + { + tmpreg |= (sTamper->Tamper << TAMP_CR2_TAMP1MSK_Pos); + } + + if (sTamper->NoErase != RTC_TAMPER_ERASE_BACKUP_ENABLE) + { + tmpreg |= (sTamper->Tamper << TAMP_CR2_TAMP1NOERASE_Pos); + } + WRITE_REG(TAMP->CR2, tmpreg); + + /* Filter control register */ + WRITE_REG(TAMP->FLTCR, sTamper->Filter | sTamper->SamplingFrequency | sTamper->PrechargeDuration | sTamper->TamperPullUp); + + /* Timestamp on tamper */ + if (READ_BIT(RTC->CR, RTC_CR_TAMPTS) != sTamper->TimeStampOnTamperDetection) + { + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + MODIFY_REG(RTC->CR, RTC_CR_TAMPTS, sTamper->TimeStampOnTamperDetection); + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + } + + /* Store in the handle the Tamper enabled */ + SET_BIT(hrtc->IsEnabled.TampFeatures, sTamper->Tamper); + + /* Control register 1 */ + SET_BIT(TAMP->CR1, sTamper->Tamper); + + return HAL_OK; +} + + +/** + * @brief Set Tamper in IT mode + * @param hrtc RTC handle + * @param sTamper Pointer to Tamper Structure. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper) +{ + uint32_t tmpreg; + + /* Check the parameters */ + assert_param(IS_RTC_TAMPER(sTamper->Tamper)); + assert_param(IS_RTC_TAMPER_TRIGGER(sTamper->Trigger)); + assert_param(IS_RTC_TAMPER_ERASE_MODE(sTamper->NoErase)); + assert_param(IS_RTC_TAMPER_MASKFLAG_STATE(sTamper->MaskFlag)); + assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection)); + assert_param(IS_RTC_TAMPER_FILTER(sTamper->Filter)); + assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency)); + assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration)); + assert_param(IS_RTC_TAMPER_PULLUP_STATE(sTamper->TamperPullUp)); + /* Trigger and Filter have exclusive configurations */ + assert_param(((sTamper->Filter != RTC_TAMPERFILTER_DISABLE) && ((sTamper->Trigger == RTC_TAMPERTRIGGER_LOWLEVEL) || (sTamper->Trigger == RTC_TAMPERTRIGGER_HIGHLEVEL))) + || ((sTamper->Filter == RTC_TAMPERFILTER_DISABLE) && ((sTamper->Trigger == RTC_TAMPERTRIGGER_RISINGEDGE) || (sTamper->Trigger == RTC_TAMPERTRIGGER_FALLINGEDGE)))); + + /* Configuration register 2 */ + tmpreg = READ_REG(TAMP->CR2); + tmpreg &= ~((sTamper->Tamper << TAMP_CR2_TAMP1TRG_Pos) | (sTamper->Tamper << TAMP_CR2_TAMP1MSK_Pos) | (sTamper->Tamper << TAMP_CR2_TAMP1NOERASE_Pos)); + + if ((sTamper->Trigger == RTC_TAMPERTRIGGER_HIGHLEVEL) || (sTamper->Trigger == RTC_TAMPERTRIGGER_FALLINGEDGE)) + { + tmpreg |= (sTamper->Tamper << TAMP_CR2_TAMP1TRG_Pos); + } + + if (sTamper->MaskFlag != RTC_TAMPERMASK_FLAG_DISABLE) + { + tmpreg |= (sTamper->Tamper << TAMP_CR2_TAMP1MSK_Pos); + } + + if (sTamper->NoErase != RTC_TAMPER_ERASE_BACKUP_ENABLE) + { + tmpreg |= (sTamper->Tamper << TAMP_CR2_TAMP1NOERASE_Pos); + } + WRITE_REG(TAMP->CR2, tmpreg); + + /* Filter control register */ + WRITE_REG(TAMP->FLTCR, sTamper->Filter | sTamper->SamplingFrequency | sTamper->PrechargeDuration | sTamper->TamperPullUp); + + /* Timestamp on tamper */ + if (READ_BIT(RTC->CR, RTC_CR_TAMPTS) != sTamper->TimeStampOnTamperDetection) + { + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + MODIFY_REG(RTC->CR, RTC_CR_TAMPTS, sTamper->TimeStampOnTamperDetection); + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + } + + /* RTC Tamper Interrupt Configuration: EXTI configuration */ + __HAL_RTC_TAMPER_EXTI_ENABLE_IT(); + + /* Interrupt enable register */ + SET_BIT(TAMP->IER, sTamper->Tamper); + + /* Store in the handle the Tamper enabled */ + SET_BIT(hrtc->IsEnabled.TampFeatures, sTamper->Tamper); + + /* Control register 1 */ + SET_BIT(TAMP->CR1, sTamper->Tamper); + + return HAL_OK; +} + +/** + * @brief Deactivate Tamper. + * @param hrtc RTC handle + * @param Tamper Selected tamper pin. + * This parameter can be a combination of the following values: + * @arg RTC_TAMPER_1 + * @arg RTC_TAMPER_2 + * @arg RTC_TAMPER_3 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper) +{ + UNUSED(hrtc); + assert_param(IS_RTC_TAMPER(Tamper)); + + /* Disable the selected Tamper pin */ + CLEAR_BIT(TAMP->CR1, Tamper); + + /* Clear tamper mask/noerase/trigger configuration */ + CLEAR_BIT(TAMP->CR2, (Tamper << TAMP_CR2_TAMP1TRG_Pos) | (Tamper << TAMP_CR2_TAMP1MSK_Pos) | (Tamper << TAMP_CR2_TAMP1NOERASE_Pos)); + + /* Clear tamper interrupt mode configuration */ + CLEAR_BIT(TAMP->IER, Tamper); + + /* Clear tamper interrupt and event flags (WO register) */ + WRITE_REG(TAMP->SCR, Tamper); + + /* Store in the handle the Tamper disabled */ + CLEAR_BIT(hrtc->IsEnabled.TampFeatures, Tamper); + + return HAL_OK; +} + + + +/** + * @brief Tamper event polling. + * @param hrtc RTC handle + * @param Tamper Selected tamper pin. + * This parameter can be a combination of the following values: + * @arg RTC_TAMPER_1 + * @arg RTC_TAMPER_2 + * @arg RTC_TAMPER_3 + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_PollForTamperEvent(RTC_HandleTypeDef *hrtc, uint32_t Tamper, uint32_t Timeout) +{ + UNUSED(hrtc); + assert_param(IS_RTC_TAMPER(Tamper)); + + uint32_t tickstart = HAL_GetTick(); + + /* Get the status of the Interrupt */ + while (READ_BIT(TAMP->SR, Tamper) != Tamper) + { + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + return HAL_TIMEOUT; + } + } + } + + /* Clear the Tamper Flag */ + WRITE_REG(TAMP->SCR, Tamper); + + return HAL_OK; +} + + +/** + * @brief Set Internal Tamper in interrupt mode + * @param hrtc RTC handle + * @param sIntTamper Pointer to Internal Tamper Structure. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_SetInternalTamper(RTC_HandleTypeDef *hrtc, RTC_InternalTamperTypeDef *sIntTamper) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* Check the parameters */ + assert_param(IS_RTC_INTERNAL_TAMPER(sIntTamper->IntTamper)); + assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sIntTamper->TimeStampOnTamperDetection)); + assert_param(IS_RTC_TAMPER_ERASE_MODE(sIntTamper->NoErase)); + + /* timestamp on internal tamper */ + if (READ_BIT(RTC->CR, RTC_CR_TAMPTS) != sIntTamper->TimeStampOnTamperDetection) + { + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + MODIFY_REG(RTC->CR, RTC_CR_TAMPTS, sIntTamper->TimeStampOnTamperDetection); + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + } + + if (sIntTamper->NoErase != RTC_TAMPER_ERASE_BACKUP_ENABLE) + { + /* Control register 3 */ + SET_BIT(TAMP->CR3, (sIntTamper->IntTamper >> 16U)); /* Shift of 16 bit to manage ITAMP on MSB part of CR3 */ + } + + /* Store in the handle the Internal Tamper enabled */ + SET_BIT(hrtc->IsEnabled.TampFeatures, sIntTamper->IntTamper); + + /* Control register 1 */ + SET_BIT(TAMP->CR1, sIntTamper->IntTamper); + + return HAL_OK; +} + + +/** + * @brief Set Internal Tamper + * @param hrtc RTC handle + * @param sIntTamper Pointer to Internal Tamper Structure. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_SetInternalTamper_IT(RTC_HandleTypeDef *hrtc, RTC_InternalTamperTypeDef *sIntTamper) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* Check the parameters */ + assert_param(IS_RTC_INTERNAL_TAMPER(sIntTamper->IntTamper)); + assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sIntTamper->TimeStampOnTamperDetection)); + assert_param(IS_RTC_TAMPER_ERASE_MODE(sIntTamper->NoErase)); + + /* timestamp on internal tamper */ + if (READ_BIT(RTC->CR, RTC_CR_TAMPTS) != sIntTamper->TimeStampOnTamperDetection) + { + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + MODIFY_REG(RTC->CR, RTC_CR_TAMPTS, sIntTamper->TimeStampOnTamperDetection); + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + } + + /* RTC Tamper Interrupt Configuration: EXTI configuration */ + __HAL_RTC_TAMPER_EXTI_ENABLE_IT(); + + /* Interrupt enable register */ + SET_BIT(TAMP->IER, sIntTamper->IntTamper); + + if (sIntTamper->NoErase != RTC_TAMPER_ERASE_BACKUP_ENABLE) + { + /* Control register 3 */ + SET_BIT(TAMP->CR3, (sIntTamper->IntTamper >> 16U)); /* Shift of 16 bit to manage ITAMP on MSB part of CR3 */ + } + + /* Store in the handle the Internal Tamper enabled */ + SET_BIT(hrtc->IsEnabled.TampFeatures, sIntTamper->IntTamper); + + /* Control register 1 */ + SET_BIT(TAMP->CR1, sIntTamper->IntTamper); + + return HAL_OK; +} + +/** + * @brief Deactivate Internal Tamper. + * @param hrtc RTC handle + * @param IntTamper Selected internal tamper event. + * This parameter can be any combination of existing internal tampers. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_DeactivateInternalTamper(RTC_HandleTypeDef *hrtc, uint32_t IntTamper) +{ + UNUSED(hrtc); + assert_param(IS_RTC_INTERNAL_TAMPER(IntTamper)); + + /* Disable the selected Tamper pin */ + CLEAR_BIT(TAMP->CR1, IntTamper); + + /* Clear internal tamper interrupt mode configuration */ + CLEAR_BIT(TAMP->IER, IntTamper); + + /* Clear internal tamper interrupt */ + WRITE_REG(TAMP->SCR, IntTamper); + + /* Store in the handle the internal Tamper disabled */ + CLEAR_BIT(hrtc->IsEnabled.TampFeatures, IntTamper); + + return HAL_OK; +} + + +/** + * @brief Internal Tamper event polling. + * @param hrtc RTC handle + * @param IntTamper selected tamper. + * This parameter can be any combination of existing internal tampers. + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_PollForInternalTamperEvent(RTC_HandleTypeDef *hrtc, uint32_t IntTamper, uint32_t Timeout) +{ + UNUSED(hrtc); + assert_param(IS_RTC_INTERNAL_TAMPER(IntTamper)); + + uint32_t tickstart = HAL_GetTick(); + + /* Get the status of the Interrupt */ + while (READ_BIT(TAMP->SR, IntTamper) != IntTamper) + { + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + return HAL_TIMEOUT; + } + } + } + + /* Clear the Tamper Flag */ + WRITE_REG(TAMP->SCR, IntTamper); + + return HAL_OK; +} + + +/** + * @brief Handle Tamper interrupt request. + * @param hrtc RTC handle + * @retval None + */ +void HAL_RTCEx_TamperIRQHandler(RTC_HandleTypeDef *hrtc) +{ + uint32_t tmp = READ_REG(TAMP->MISR) & READ_REG(hrtc->IsEnabled.TampFeatures); + + /* Immediately clear flags */ + WRITE_REG(TAMP->SCR, tmp); + + /* Check Tamper1 status */ + if ((tmp & RTC_TAMPER_1) == RTC_TAMPER_1) + { +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + /* Call Tamper 1 Event registered Callback */ + hrtc->Tamper1EventCallback(hrtc); +#else + /* Tamper1 callback */ + HAL_RTCEx_Tamper1EventCallback(hrtc); +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ + } + + /* Check Tamper2 status */ + if ((tmp & RTC_TAMPER_2) == RTC_TAMPER_2) + { +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + /* Call Tamper 2 Event registered Callback */ + hrtc->Tamper2EventCallback(hrtc); +#else + /* Tamper2 callback */ + HAL_RTCEx_Tamper2EventCallback(hrtc); +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ + } + + /* Check Tamper3 status */ + if ((tmp & RTC_TAMPER_3) == RTC_TAMPER_3) + { +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + /* Call Tamper 3 Event registered Callback */ + hrtc->Tamper3EventCallback(hrtc); +#else + /* Tamper3 callback */ + HAL_RTCEx_Tamper3EventCallback(hrtc); +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ + } + + /* Check Internal Tamper3 status */ + if ((tmp & RTC_INT_TAMPER_3) == RTC_INT_TAMPER_3) + { +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + /* Call Internal Tamper 3 Event registered Callback */ + hrtc->InternalTamper3EventCallback(hrtc); +#else + /* Internal Tamper3 callback */ + HAL_RTCEx_InternalTamper3EventCallback(hrtc); +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ + } + + /* Check Internal Tamper5 status */ + if ((tmp & RTC_INT_TAMPER_5) == RTC_INT_TAMPER_5) + { +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + /* Call Internal Tamper 5 Event registered Callback */ + hrtc->InternalTamper5EventCallback(hrtc); +#else + /* Internal Tamper5 callback */ + HAL_RTCEx_InternalTamper5EventCallback(hrtc); +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ + } + + /* Check Internal Tamper6 status */ + if ((tmp & RTC_INT_TAMPER_6) == RTC_INT_TAMPER_6) + { +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + /* Call Internal Tamper 6 Event registered Callback */ + hrtc->InternalTamper6EventCallback(hrtc); +#else + /* Internal Tamper6 callback */ + HAL_RTCEx_InternalTamper6EventCallback(hrtc); +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ + } + + /* Check Internal Tamper8 status */ + if ((tmp & RTC_INT_TAMPER_8) == RTC_INT_TAMPER_8) + { +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + /* Call Internal Tamper 8 Event registered Callback */ + hrtc->InternalTamper8EventCallback(hrtc); +#else + /* Internal Tamper8 callback */ + HAL_RTCEx_InternalTamper8EventCallback(hrtc); +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ + } +} + +/** + * @brief Tamper 1 callback. + * @param hrtc RTC handle + * @retval None + */ +__weak void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_RTCEx_Tamper1EventCallback could be implemented in the user file + */ +} + + +/** + * @brief Tamper 2 callback. + * @param hrtc RTC handle + * @retval None + */ +__weak void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_RTCEx_Tamper2EventCallback could be implemented in the user file + */ +} + +/** + * @brief Tamper 3 callback. + * @param hrtc RTC handle + * @retval None + */ +__weak void HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_RTCEx_Tamper3EventCallback could be implemented in the user file + */ +} + +/** + * @brief Internal Tamper 3 callback. + * @param hrtc RTC handle + * @retval None + */ +__weak void HAL_RTCEx_InternalTamper3EventCallback(RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_RTCEx_InternalTamper3EventCallback could be implemented in the user file + */ +} + + +/** + * @brief Internal Tamper 5 callback. + * @param hrtc RTC handle + * @retval None + */ +__weak void HAL_RTCEx_InternalTamper5EventCallback(RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_RTCEx_InternalTamper5EventCallback could be implemented in the user file + */ +} + +/** + * @brief Internal Tamper 6 callback. + * @param hrtc RTC handle + * @retval None + */ +__weak void HAL_RTCEx_InternalTamper6EventCallback(RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_RTCEx_InternalTamper6EventCallback could be implemented in the user file + */ +} + +/** + * @brief Internal Tamper 8 callback. + * @param hrtc RTC handle + * @retval None + */ +__weak void HAL_RTCEx_InternalTamper8EventCallback(RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_RTCEx_InternalTamper8EventCallback could be implemented in the user file + */ +} +/** + * @} + */ + + +/** @addtogroup RTCEx_Exported_Functions_Group6 + * @brief Extended RTC Backup register functions + * +@verbatim + =============================================================================== + ##### Extended RTC Backup register functions ##### + =============================================================================== + [..] + (+) Before calling any tamper or internal tamper function, you have to call first + HAL_RTC_Init() function. + (+) In that ine you can select to output tamper event on RTC pin. + [..] + This subsection provides functions allowing to + (+) Write a data in a specified RTC Backup data register + (+) Read a data in a specified RTC Backup data register +@endverbatim + * @{ + */ + + +/** + * @brief Write a data in a specified RTC Backup data register. + * @param hrtc RTC handle + * @param BackupRegister RTC Backup data Register number. + * This parameter can be RTC_BKP_DRx where x can be from 0 to RTC_BACKUP_NB + * @param Data Data to be written in the specified Backup data register. + * @retval None + */ +void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data) +{ + uint32_t tmp; + + UNUSED(hrtc); + /* Check the parameters */ + assert_param(IS_RTC_BKP(BackupRegister)); + + tmp = (uint32_t) &(TAMP->BKP0R); + tmp += (BackupRegister * 4U); + + /* Write the specified register */ + *(__IO uint32_t *)tmp = (uint32_t)Data; +} + + +/** + * @brief Reads data from the specified RTC Backup data Register. + * @param hrtc RTC handle + * @param BackupRegister RTC Backup data Register number. + * This parameter can be RTC_BKP_DRx where x can be from 0 to RTC_BACKUP_NB + * @retval Read value + */ +uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister) +{ + uint32_t tmp; + + UNUSED(hrtc); + /* Check the parameters */ + assert_param(IS_RTC_BKP(BackupRegister)); + + tmp = (uint32_t) &(TAMP->BKP0R); + tmp += (BackupRegister * 4U); + + /* Read the specified register */ + return (*(__IO uint32_t *)tmp); +} + + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_RTC_MODULE_ENABLED */ +/** + * @} + */ + + +/** + * @} + */ diff --git a/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c b/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c new file mode 100644 index 0000000..a0d1cc7 --- /dev/null +++ b/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c @@ -0,0 +1,1817 @@ +/******************************************************************************* + * @file stm32wlxx_hal_subghz.c + * @author MCD Application Team + * @brief SUBGHZ HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the SUBGHZ peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral State and Errors functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The SUBGHZ HAL driver can be used as follows: + + (#) Declare a SUBGHZ_HandleTypeDef handle structure, for example: + SUBGHZ_HandleTypeDef hUserSubghz; + + (#) Initialize the SUBGHZ low level resources by implementing the @ref HAL_SUBGHZ_MspInit() API: + (##) PWR configuration + (+++) Enable the SUBGHZSPI interface clock + (+++) Enable wakeup signal of the Radio peripheral + (##) NVIC configuration: + (+++) Enable the NVIC Radio IRQ ITs for CPU1 (EXTI 44) + (+++) Configure the Radio interrupt priority + + (#) Initialize the SUBGHZ handle and SUBGHZSPI SPI registers by calling the @ref HAL_SUBGHZ_Init(&hUserSubghz), + configures also the low level Hardware (GPIO, CLOCK, NVIC...etc) by calling + the customized @ref HAL_SUBGHZ_MspInit() API. + + (#) For SUBGHZ IO operations, polling operation modes is available within this driver : + + *** Polling mode IO operation *** + ===================================== + [..] + (+) Set and execute a command in blocking mode using @ref HAL_SUBGHZ_ExecSetCmd() + (+) Get a status blocking mode using @ref HAL_SUBGHZ_ExecGetCmd() + (+) Write a Data Buffer in blocking mode using @ref HAL_SUBGHZ_WriteBuffer() + (+) Read a Data Buffer in blocking mode using @ref HAL_SUBGHZ_ReadBuffer() + (+) Write Registers (more than 1 byte) in blocking mode using @ref HAL_SUBGHZ_WriteRegisters() + (+) Read Registers (more than 1 byte) in blocking mode using @ref HAL_SUBGHZ_ReadRegisters() + (+) Write Register (1 byte) in blocking mode using @ref HAL_SUBGHZ_WriteRegister() + (+) Read Register (1 byte) in blocking mode using @ref HAL_SUBGHZ_ReadRegister() + + *** SUBGHZ HAL driver macros list *** + ===================================== + [..] + (+) @ref __HAL_SUBGHZ_RESET_HANDLE_STATE: Reset the SUBGHZ handle state + +#if defined(GENERATOR_CALLBACK_REGISTERING_PRESENT) + *** SUBGHZ Callback registration *** + ===================================== + + [..] + The compilation flag USE_HAL_SUBGHZ_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + Use Functions @ref HAL_SUBGHZ_RegisterCallback() or @ref HAL_SUBGHZ_RegisterAddrCallback() + to register an interrupt callback. + + [..] + Function @ref HAL_SUBGHZ_RegisterCallback() allows to register following callbacks: + (+) TxCpltCallback : callback for Tx Completed. + (+) RxCpltCallback : callback for Rx Completed. + (+) PreambleDetectedCallback : callback for Preamble detected. + (+) SyncWordValidCallback : callback for Synchro word valid. + (+) HeaderValidCallback : callback for Header valid. + (+) HeaderErrorCallback : callback for Header error. + (+) CRCErrorCallback : callback for CRC Error. + (+) RxTxTimeoutCallback : callback for Rx Tx Timeout. + (+) MspInitCallback : callback for Msp Init. + (+) MspDeInitCallback : callback for Msp DeInit. + (+) LrFhssHopCallback : callback for LoRa Frequency Hopping Spread Spectrum Hopping. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + [..] + For specific callback CADStatusCallback use dedicated register callbacks : + @ref HAL_SUBGHZ_RegisterCadStatusCallback(). + [..] + Use function @ref HAL_SUBGHZ_UnRegisterCallback to reset a callback to the default + weak function. + @ref HAL_SUBGHZ_UnRegisterCallback takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) TxCpltCallback : callback for Tx Completed. + (+) RxCpltCallback : callback for Rx Completed. + (+) PreambleDetectedCallback : callback for Preamble detected. + (+) SyncWordValidCallback : callback for Synchro word valid. + (+) HeaderValidCallback : callback for Header valid. + (+) HeaderErrorCallback : callback for Header error. + (+) CRCErrorCallback : callback for CRC Error. + (+) RxTxTimeoutCallback : callback for Rx Tx Timeout. + (+) MspInitCallback : callback for Msp Init. + (+) MspDeInitCallback : callback for Msp DeInit. + (+) LrFhssHopCallback : callback for LoRa Frequency Hopping Spread Spectrum Hopping. + [..] + For specific callback CADStatusCallback use dedicated register callbacks : + @ref HAL_SUBGHZ_UnRegisterCadStatusCallback(). + [..] + MspInit and MspDeInit functions are reset to the legacy weak functions in the + @ref HAL_SUBGHZ_Init()/ @ref HAL_SUBGHZ_DeInit() only when these callbacks are null + (not registered beforehand). + If MspInit or MspDeInit are not null, the @ref HAL_SUBGHZ_Init()/ @ref HAL_SUBGHZ_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. + + [..] + Callbacks for MspInit/MspDeInit functions can be registered/unregistered + in @ref HAL_SUBGHZ_STATE_READY or @ref HAL_SUBGHZ_STATE_RESET state, + thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + Then, the user first registers the MspInit/MspDeInit user callbacks + using @ref HAL_SUBGHZ_RegisterCallback() before calling @ref HAL_SUBGHZ_DeInit() + or @ref HAL_SUBGHZ_Init() function. + + [..] + When the compilation flag USE_HAL_SUBGHZ_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. +#endif + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wlxx_hal.h" + +/** @addtogroup STM32WLxx_HAL_Driver + * @{ + */ + +/** @defgroup SUBGHZ SUBGHZ + * @brief SUBGHZ HAL module driver + * @{ + */ +#ifdef HAL_SUBGHZ_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private defines -----------------------------------------------------------*/ +/** @defgroup SUBGHZ_Private_Constants SUBGHZ Private Constants + * @{ + */ +#define SUBGHZ_DEFAULT_TIMEOUT 100U /* HAL Timeout in ms */ +#define SUBGHZ_DUMMY_DATA 0xFFU /* SUBGHZSPI Dummy Data use for Tx */ +#define SUBGHZ_DEEP_SLEEP_ENABLE 1U /* SUBGHZ Radio in Deep Sleep */ +#define SUBGHZ_DEEP_SLEEP_DISABLE 0U /* SUBGHZ Radio not in Deep Sleep */ + +/* SystemCoreClock dividers. Corresponding to time execution of while loop. */ +#define SUBGHZ_DEFAULT_LOOP_TIME ((SystemCoreClock*28U)>>19U) +#define SUBGHZ_RFBUSY_LOOP_TIME ((SystemCoreClock*24U)>>20U) + +/* ~150 us loop delay assuming 10 CPU cycles per iteration (> 20us as per Semtech spec) */ +#define SUBGHZ_NSS_LOOP_TIME ((SystemCoreClock)>>16U) +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup SUBGHZ_Private_Functions SUBGHZ Private Functions + * @{ + */ +void SUBGHZSPI_Init(uint32_t BaudratePrescaler); +void SUBGHZSPI_DeInit(void); +HAL_StatusTypeDef SUBGHZSPI_Transmit(SUBGHZ_HandleTypeDef *hsubghz, uint8_t Data); +HAL_StatusTypeDef SUBGHZSPI_Receive(SUBGHZ_HandleTypeDef *hsubghz, uint8_t *pData); +HAL_StatusTypeDef SUBGHZ_WaitOnBusy(SUBGHZ_HandleTypeDef *hsubghz); +HAL_StatusTypeDef SUBGHZ_CheckDeviceReady(SUBGHZ_HandleTypeDef *hsubghz); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup SUBGHZ_Exported_Functions SUBGHZ Exported Functions + * @{ + */ + +/** @defgroup SUBGHZ_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This subsection provides a set of functions allowing to initialize and + de-initialize the SUBGHZ peripheral: + + (+) User must implement HAL_SUBGHZ_MspInit() function in which he configures + all related peripherals resources (CLOCK, GPIO, IT and NVIC ). + + (+) Call the function HAL_SUBGHZ_Init() to configure SUBGHZSPI peripheral + and initialize SUBGHZ Handle. + + (+) Call the function HAL_SUBGHZ_DeInit() to restore the default configuration + of the SUBGHZ peripheral. + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the SUBGHZ according to the specified parameters + * in the SUBGHZ_HandleTypeDef and initialize the associated handle. + * @param hsubghz pointer to a SUBGHZ_HandleTypeDef structure that contains + * the handle information for SUBGHZ module. + * @note In case of exiting from Standby mode, before calling this function, + * set the state to HAL_SUBGHZ_STATE_RESET_RF_READY with __HAL_SUBGHZ_RESET_HANDLE_STATE_RF_READY + * to avoid the reset of Radio peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SUBGHZ_Init(SUBGHZ_HandleTypeDef *hsubghz) +{ + HAL_StatusTypeDef status; + __IO uint32_t count; + HAL_SUBGHZ_StateTypeDef subghz_state; + + /* Check the hsubghz handle allocation */ + if (hsubghz == NULL) + { + status = HAL_ERROR; + return status; + } + else + { + status = HAL_OK; + } + + assert_param(IS_SUBGHZSPI_BAUDRATE_PRESCALER(hsubghz->Init.BaudratePrescaler)); + + subghz_state = hsubghz->State; + if ((subghz_state == HAL_SUBGHZ_STATE_RESET) || + (subghz_state == HAL_SUBGHZ_STATE_RESET_RF_READY)) + { + /* Allocate lock resource and initialize it */ + hsubghz->Lock = HAL_UNLOCKED; + +#if (USE_HAL_SUBGHZ_REGISTER_CALLBACKS == 1) + /* Init the SUBGHZ Legacy weak Callback settings */ + hsubghz->TxCpltCallback = HAL_SUBGHZ_TxCpltCallback; + hsubghz->RxCpltCallback = HAL_SUBGHZ_RxCpltCallback; + hsubghz->PreambleDetectedCallback = HAL_SUBGHZ_PreambleDetectedCallback; + hsubghz->SyncWordValidCallback = HAL_SUBGHZ_SyncWordValidCallback; + hsubghz->HeaderValidCallback = HAL_SUBGHZ_HeaderValidCallback; + hsubghz->HeaderErrorCallback = HAL_SUBGHZ_HeaderErrorCallback; + hsubghz->CRCErrorCallback = HAL_SUBGHZ_CRCErrorCallback; + hsubghz->CADStatusCallback = HAL_SUBGHZ_CADStatusCallback; + hsubghz->RxTxTimeoutCallback = HAL_SUBGHZ_RxTxTimeoutCallback; + hsubghz->LrFhssHopCallback = HAL_SUBGHZ_LrFhssHopCallback; + + if (hsubghz->MspInitCallback == NULL) + { + hsubghz->MspInitCallback = HAL_SUBGHZ_MspInit; /* Legacy weak MspInit */ + } + + /* Init the low level hardware : GPIO, CLOCK, NVIC... */ + hsubghz->MspInitCallback(hsubghz); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC... */ + HAL_SUBGHZ_MspInit(hsubghz); +#endif /* USE_HAL_ SUBGHZ_REGISTER_CALLBACKS */ + +#if defined(CORE_CM0PLUS) + /* Enable EXTI 44 : Radio IRQ ITs for CPU2 */ + LL_C2_EXTI_EnableIT_32_63(LL_EXTI_LINE_44); +#else + /* Enable EXTI 44 : Radio IRQ ITs for CPU1 */ + LL_EXTI_EnableIT_32_63(LL_EXTI_LINE_44); +#endif /* CORE_CM0PLUS */ + } + + if (subghz_state == HAL_SUBGHZ_STATE_RESET) + { + /* Reinitialize Radio peripheral only if SUBGHZ is in full RESET state */ + hsubghz->State = HAL_SUBGHZ_STATE_BUSY; + + /* De-asserts the reset signal of the Radio peripheral */ + LL_RCC_RF_DisableReset(); + + /* Verify that Radio in reset status flag is set */ + count = SUBGHZ_DEFAULT_TIMEOUT * SUBGHZ_DEFAULT_LOOP_TIME; + + do + { + if (count == 0U) + { + status = HAL_ERROR; + hsubghz->ErrorCode = HAL_SUBGHZ_ERROR_TIMEOUT; + break; + } + count--; + } while (LL_RCC_IsRFUnderReset() != 0UL); + + /* Asserts the reset signal of the Radio peripheral */ + LL_PWR_UnselectSUBGHZSPI_NSS(); + +#if defined(CORE_CM0PLUS) + /* Enable wakeup signal of the Radio peripheral */ + LL_C2_PWR_SetRadioBusyTrigger(LL_PWR_RADIO_BUSY_TRIGGER_WU_IT); +#else + /* Enable wakeup signal of the Radio peripheral */ + LL_PWR_SetRadioBusyTrigger(LL_PWR_RADIO_BUSY_TRIGGER_WU_IT); +#endif /* CORE_CM0PLUS */ + } + + /* Clear Pending Flag */ + LL_PWR_ClearFlag_RFBUSY(); + + if (status == HAL_OK) + { + /* Initialize SUBGHZSPI Peripheral */ + SUBGHZSPI_Init(hsubghz->Init.BaudratePrescaler); + + hsubghz->DeepSleep = SUBGHZ_DEEP_SLEEP_ENABLE; + hsubghz->ErrorCode = HAL_SUBGHZ_ERROR_NONE; + } + + hsubghz->State = HAL_SUBGHZ_STATE_READY; + + return status; +} + +/** + * @brief De-Initialize the SUBGHZ peripheral. + * @param hsubghz pointer to a SUBGHZ_HandleTypeDef structure that contains + * the handle information for SUBGHZ module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SUBGHZ_DeInit(SUBGHZ_HandleTypeDef *hsubghz) +{ + HAL_StatusTypeDef status; + __IO uint32_t count; + + /* Check the SUBGHZ handle allocation */ + if (hsubghz == NULL) + { + status = HAL_ERROR; + return status; + } + else + { + status = HAL_OK; + } + + hsubghz->State = HAL_SUBGHZ_STATE_BUSY; + + /* DeInitialize SUBGHZSPI Peripheral */ + SUBGHZSPI_DeInit(); + +#if (USE_HAL_SUBGHZ_REGISTER_CALLBACKS == 1) + if (hsubghz->MspDeInitCallback == NULL) + { + hsubghz->MspDeInitCallback = HAL_SUBGHZ_MspDeInit; /* Legacy weak MspDeInit */ + } + + /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */ + hsubghz->MspDeInitCallback(hsubghz); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */ + HAL_SUBGHZ_MspDeInit(hsubghz); +#endif /* USE_HAL_SUBGHZ_REGISTER_CALLBACKS */ + +#if defined(CORE_CM0PLUS) + /* Disable EXTI 44 : Radio IRQ ITs for CPU2 */ + LL_C2_EXTI_DisableIT_32_63(LL_EXTI_LINE_44); + + /* Disable wakeup signal of the Radio peripheral */ + LL_C2_PWR_SetRadioBusyTrigger(LL_PWR_RADIO_BUSY_TRIGGER_NONE); +#else + /* Disable EXTI 44 : Radio IRQ ITs for CPU1 */ + LL_EXTI_DisableIT_32_63(LL_EXTI_LINE_44); + + /* Disable wakeup signal of the Radio peripheral */ + LL_PWR_SetRadioBusyTrigger(LL_PWR_RADIO_BUSY_TRIGGER_NONE); +#endif /* CORE_CM0PLUS */ + + /* Clear Pending Flag */ + LL_PWR_ClearFlag_RFBUSY(); + + /* Re-asserts the reset signal of the Radio peripheral */ + LL_RCC_RF_EnableReset(); + + /* Verify that Radio in reset status flag is set */ + count = SUBGHZ_DEFAULT_TIMEOUT * SUBGHZ_DEFAULT_LOOP_TIME; + + do + { + if (count == 0U) + { + status = HAL_ERROR; + hsubghz->ErrorCode = HAL_SUBGHZ_ERROR_TIMEOUT; + break; + } + count--; + } while (LL_RCC_IsRFUnderReset() != 1UL); + + hsubghz->ErrorCode = HAL_SUBGHZ_ERROR_NONE; + hsubghz->State = HAL_SUBGHZ_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hsubghz); + + return status; +} + +/** + * @brief Initialize the SUBGHZ MSP. + * @param hsubghz pointer to a SUBGHZ_HandleTypeDef structure that contains + * the handle information for SUBGHZ module. + * @retval None + */ +__weak void HAL_SUBGHZ_MspInit(SUBGHZ_HandleTypeDef *hsubghz) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SUBGHZ_MspInit should be implemented in the user file + */ + + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsubghz); +} + +/** + * @brief De-Initialize the SUBGHZ MSP. + * @param hsubghz pointer to a SUBGHZ_HandleTypeDef structure that contains + * the handle information for SUBGHZ module. + * @retval None + */ +__weak void HAL_SUBGHZ_MspDeInit(SUBGHZ_HandleTypeDef *hsubghz) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SUBGHZ_MspDeInit should be implemented in the user file + */ + + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsubghz); +} + +#if (USE_HAL_SUBGHZ_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User SUBGHZ Callback + * To be used instead of the weak predefined callback + * @param hsubghz pointer to a SUBGHZ_HandleTypeDef structure that contains + * the configuration information for the specified SUBGHZ. + * @param CallbackID ID of the callback to be registered + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SUBGHZ_RegisterCallback(SUBGHZ_HandleTypeDef *hsubghz, + HAL_SUBGHZ_CallbackIDTypeDef CallbackID, + pSUBGHZ_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hsubghz->ErrorCode |= HAL_SUBGHZ_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hsubghz); + + if (HAL_SUBGHZ_STATE_READY == hsubghz->State) + { + switch (CallbackID) + { + case HAL_SUBGHZ_TX_COMPLETE_CB_ID : + hsubghz->TxCpltCallback = pCallback; + break; + + case HAL_SUBGHZ_RX_COMPLETE_CB_ID : + hsubghz->RxCpltCallback = pCallback; + break; + + case HAL_SUBGHZ_PREAMBLE_DETECTED_CB_ID : + hsubghz->PreambleDetectedCallback = pCallback; + break; + + case HAL_SUBGHZ_SYNCWORD_VALID_CB_ID : + hsubghz->SyncWordValidCallback = pCallback; + break; + + case HAL_SUBGHZ_HEADER_VALID_CB_ID : + hsubghz->HeaderValidCallback = pCallback; + break; + + case HAL_SUBGHZ_HEADER_ERROR_CB_ID : + hsubghz->HeaderErrorCallback = pCallback; + break; + + case HAL_SUBGHZ_CRC_ERROR_CB_ID : + hsubghz->CRCErrorCallback = pCallback; + break; + + case HAL_SUBGHZ_RX_TX_TIMEOUT_CB_ID : + hsubghz->RxTxTimeoutCallback = pCallback; + break; + + case HAL_SUBGHZ_MSPINIT_CB_ID : + hsubghz->MspInitCallback = pCallback; + break; + + case HAL_SUBGHZ_MSPDEINIT_CB_ID : + hsubghz->MspDeInitCallback = pCallback; + break; + + case HAL_SUBGHZ_LR_FHSS_HOP_CB_ID : + hsubghz->LrFhssHopCallback = pCallback; + break; + + default : + /* Update the error code */ + hsubghz->ErrorCode = HAL_SUBGHZ_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_SUBGHZ_STATE_RESET == hsubghz->State) + { + switch (CallbackID) + { + case HAL_SUBGHZ_MSPINIT_CB_ID : + hsubghz->MspInitCallback = pCallback; + break; + + case HAL_SUBGHZ_MSPDEINIT_CB_ID : + hsubghz->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hsubghz->ErrorCode = HAL_SUBGHZ_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hsubghz->ErrorCode = HAL_SUBGHZ_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hsubghz); + + return status; +} + +/** + * @brief Unregister an SUBGHZ Callback + * SUBGHZ callback is redirected to the weak predefined callback + * @param hsubghz pointer to a SUBGHZ_HandleTypeDef structure that contains + * the configuration information for the specified SUBGHZ. + * @param CallbackID ID of the callback to be unregistered + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SUBGHZ_UnRegisterCallback(SUBGHZ_HandleTypeDef *hsubghz, + HAL_SUBGHZ_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hsubghz); + + if (HAL_SUBGHZ_STATE_READY == hsubghz->State) + { + /* call legacy weak callback function */ + switch (CallbackID) + { + case HAL_SUBGHZ_TX_COMPLETE_CB_ID : + hsubghz->TxCpltCallback = HAL_SUBGHZ_TxCpltCallback; + break; + + case HAL_SUBGHZ_RX_COMPLETE_CB_ID : + hsubghz->RxCpltCallback = HAL_SUBGHZ_RxCpltCallback; + break; + + case HAL_SUBGHZ_PREAMBLE_DETECTED_CB_ID : + hsubghz->PreambleDetectedCallback = HAL_SUBGHZ_PreambleDetectedCallback; + break; + + case HAL_SUBGHZ_SYNCWORD_VALID_CB_ID : + hsubghz->SyncWordValidCallback = HAL_SUBGHZ_SyncWordValidCallback; + break; + + case HAL_SUBGHZ_HEADER_VALID_CB_ID : + hsubghz->HeaderValidCallback = HAL_SUBGHZ_HeaderValidCallback; + break; + + case HAL_SUBGHZ_HEADER_ERROR_CB_ID : + hsubghz->HeaderErrorCallback = HAL_SUBGHZ_HeaderErrorCallback; + break; + + case HAL_SUBGHZ_CRC_ERROR_CB_ID : + hsubghz->CRCErrorCallback = HAL_SUBGHZ_CRCErrorCallback; + break; + + case HAL_SUBGHZ_RX_TX_TIMEOUT_CB_ID : + hsubghz->RxTxTimeoutCallback = HAL_SUBGHZ_RxTxTimeoutCallback; + break; + + case HAL_SUBGHZ_MSPINIT_CB_ID : + hsubghz->MspInitCallback = HAL_SUBGHZ_MspInit; + break; + + case HAL_SUBGHZ_MSPDEINIT_CB_ID : + hsubghz->MspDeInitCallback = HAL_SUBGHZ_MspDeInit; + break; + + case HAL_SUBGHZ_LR_FHSS_HOP_CB_ID : + hsubghz->LrFhssHopCallback = HAL_SUBGHZ_LrFhssHopCallback; + break; + + default : + /* Update the error code */ + hsubghz->ErrorCode = HAL_SUBGHZ_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_SUBGHZ_STATE_RESET == hsubghz->State) + { + switch (CallbackID) + { + case HAL_SUBGHZ_MSPINIT_CB_ID : + hsubghz->MspInitCallback = HAL_SUBGHZ_MspInit; + break; + + case HAL_SUBGHZ_MSPDEINIT_CB_ID : + hsubghz->MspDeInitCallback = HAL_SUBGHZ_MspDeInit; + break; + + default : + /* Update the error code */ + hsubghz->ErrorCode = HAL_SUBGHZ_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hsubghz->ErrorCode = HAL_SUBGHZ_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hsubghz); + + return status; +} + +/** + * @brief Register the channel activity detection status SUBGHZ Callback + * To be used instead of the weak HAL_SUBGHZ_AddrCallback() predefined callback + * @param hsubghz Pointer to a SUBGHZ_HandleTypeDef structure that contains + * the configuration information for the specified SUBGHZ. + * @param pCallback pointer to the CAD Status Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SUBGHZ_RegisterCadStatusCallback(SUBGHZ_HandleTypeDef *hsubghz, + pSUBGHZ_CadStatusCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hsubghz->ErrorCode = HAL_SUBGHZ_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + /* Process locked */ + __HAL_LOCK(hsubghz); + + if (HAL_SUBGHZ_STATE_READY == hsubghz->State) + { + hsubghz->CADStatusCallback = pCallback; + } + else + { + /* Update the error code */ + hsubghz->ErrorCode = HAL_SUBGHZ_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hsubghz); + return status; +} + +/** + * @brief UnRegister the channel activity detection status SUBGHZ Callback + * @param hsubghz Pointer to a SUBGHZ_HandleTypeDef structure that contains + * the configuration information for the specified SUBGHZ. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SUBGHZ_UnRegisterCadStatusCallback(SUBGHZ_HandleTypeDef *hsubghz) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hsubghz); + + if (HAL_SUBGHZ_STATE_READY == hsubghz->State) + { + hsubghz->CADStatusCallback = HAL_SUBGHZ_CADStatusCallback; /* Legacy weak AddrCallback */ + } + else + { + /* Update the error code */ + hsubghz->ErrorCode = HAL_SUBGHZ_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hsubghz); + return status; +} +#endif /* USE_HAL_SUBGHZ_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @defgroup SUBGHZ_Exported_Functions_Group2 IO operation functions + * @brief Data transfers functions + * +@verbatim + ============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the SUBGHZ + data transfers. + + [..] The SUBGHZ supports Read and Write operation: + + (#) There are four modes of transfer: + (++) Set operation: The Set Command operation is performed in polling mode. + The HAL status of command processing is returned by the same function + after finishing transfer. + (++) Get operation: The Get Status operation is performed using polling mode + These API update buffer in parameter to retrieve status of command. + These API return the HAL status + (++) Write operation: The write operation is performed in polling mode. + The HAL status of all data processing is returned by the same function + after finishing transfer. + (++) Read operation: The read operation is performed using polling mode + These APIs return the HAL status. + + (#) Blocking mode functions are : + (++) HAL_SUBGHZ_ExecSetCmd( + (++) HAL_SUBGHZ_ExecGetCmd() + (++) HAL_SUBGHZ_WriteBuffer() + (++) HAL_SUBGHZ_ReadBuffer() + (++) HAL_SUBGHZ_WriteRegisters() + (++) HAL_SUBGHZ_ReadRegisters() + (++) HAL_SUBGHZ_WriteRegister() + (++) HAL_SUBGHZ_ReadRegister() + +@endverbatim + * @{ + */ + +/** + * @brief Write data buffer at an Address to configurate the peripheral + * @param hsubghz pointer to a SUBGHZ_HandleTypeDef structure that contains + * the configuration information for the specified SUBGHZ. + * @param Address register to configurate + * @param pBuffer pointer to a data buffer + * @param Size amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SUBGHZ_WriteRegisters(SUBGHZ_HandleTypeDef *hsubghz, + uint16_t Address, + uint8_t *pBuffer, + uint16_t Size) +{ + HAL_StatusTypeDef status; + + if (hsubghz->State == HAL_SUBGHZ_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hsubghz); + + hsubghz->State = HAL_SUBGHZ_STATE_BUSY; + + (void)SUBGHZ_CheckDeviceReady(hsubghz); + + /* NSS = 0 */ + LL_PWR_SelectSUBGHZSPI_NSS(); + + (void)SUBGHZSPI_Transmit(hsubghz, SUBGHZ_RADIO_WRITE_REGISTER); + (void)SUBGHZSPI_Transmit(hsubghz, (uint8_t)((Address & 0xFF00U) >> 8U)); + (void)SUBGHZSPI_Transmit(hsubghz, (uint8_t)(Address & 0x00FFU)); + + for (uint16_t i = 0U; i < Size; i++) + { + (void)SUBGHZSPI_Transmit(hsubghz, pBuffer[i]); + } + + /* NSS = 1 */ + LL_PWR_UnselectSUBGHZSPI_NSS(); + + (void)SUBGHZ_WaitOnBusy(hsubghz); + + if (hsubghz->ErrorCode != HAL_SUBGHZ_ERROR_NONE) + { + status = HAL_ERROR; + } + else + { + status = HAL_OK; + } + + hsubghz->State = HAL_SUBGHZ_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsubghz); + + return status; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Read data register at an Address in the peripheral + * @param hsubghz pointer to a SUBGHZ_HandleTypeDef structure that contains + * the configuration information for the specified SUBGHZ. + * @param Address register to configurate + * @param pBuffer pointer to a data buffer + * @param Size amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SUBGHZ_ReadRegisters(SUBGHZ_HandleTypeDef *hsubghz, + uint16_t Address, + uint8_t *pBuffer, + uint16_t Size) +{ + HAL_StatusTypeDef status; + uint8_t *pData = pBuffer; + + if (hsubghz->State == HAL_SUBGHZ_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hsubghz); + + (void)SUBGHZ_CheckDeviceReady(hsubghz); + + /* NSS = 0 */ + LL_PWR_SelectSUBGHZSPI_NSS(); + + (void)SUBGHZSPI_Transmit(hsubghz, SUBGHZ_RADIO_READ_REGISTER); + (void)SUBGHZSPI_Transmit(hsubghz, (uint8_t)((Address & 0xFF00U) >> 8U)); + (void)SUBGHZSPI_Transmit(hsubghz, (uint8_t)(Address & 0x00FFU)); + (void)SUBGHZSPI_Transmit(hsubghz, 0U); + + for (uint16_t i = 0U; i < Size; i++) + { + (void)SUBGHZSPI_Receive(hsubghz, (pData)); + pData++; + } + + /* NSS = 1 */ + LL_PWR_UnselectSUBGHZSPI_NSS(); + + (void)SUBGHZ_WaitOnBusy(hsubghz); + + if (hsubghz->ErrorCode != HAL_SUBGHZ_ERROR_NONE) + { + status = HAL_ERROR; + } + else + { + status = HAL_OK; + } + + hsubghz->State = HAL_SUBGHZ_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsubghz); + + return status; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Write one data at an Address to configurate the peripheral + * @param hsubghz pointer to a SUBGHZ_HandleTypeDef structure that contains + * the configuration information for the specified SUBGHZ. + * @param Address register to configurate + * @param Value data + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SUBGHZ_WriteRegister(SUBGHZ_HandleTypeDef *hsubghz, + uint16_t Address, + uint8_t Value) +{ + return (HAL_SUBGHZ_WriteRegisters(hsubghz, Address, &Value, 1U)); +} + +/** + * @brief Read data register at an Address in the peripheral + * @param hsubghz pointer to a SUBGHZ_HandleTypeDef structure that contains + * the configuration information for the specified SUBGHZ. + * @param Address register to configurate + * @param pValue pointer to a data + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SUBGHZ_ReadRegister(SUBGHZ_HandleTypeDef *hsubghz, + uint16_t Address, + uint8_t *pValue) +{ + return (HAL_SUBGHZ_ReadRegisters(hsubghz, Address, pValue, 1U)); +} + +/** + * @brief Send a command to configure the peripheral + * @param hsubghz pointer to a SUBGHZ_HandleTypeDef structure that contains + * the configuration information for the specified SUBGHZ. + * @param Command configuration for peripheral + * @param pBuffer pointer to a data buffer + * @param Size amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SUBGHZ_ExecSetCmd(SUBGHZ_HandleTypeDef *hsubghz, + SUBGHZ_RadioSetCmd_t Command, + uint8_t *pBuffer, + uint16_t Size) +{ + HAL_StatusTypeDef status; + + /* LORA Modulation not available on STM32WLx4xx devices */ + assert_param(IS_SUBGHZ_MODULATION_SUPPORTED(Command, pBuffer[0U])); + + if (hsubghz->State == HAL_SUBGHZ_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hsubghz); + + /* Need to wakeup Radio if already in Sleep at startup */ + (void)SUBGHZ_CheckDeviceReady(hsubghz); + + if ((Command == RADIO_SET_SLEEP) || (Command == RADIO_SET_RXDUTYCYCLE)) + { + hsubghz->DeepSleep = SUBGHZ_DEEP_SLEEP_ENABLE; + } + else + { + hsubghz->DeepSleep = SUBGHZ_DEEP_SLEEP_DISABLE; + } + + /* NSS = 0 */ + LL_PWR_SelectSUBGHZSPI_NSS(); + + (void)SUBGHZSPI_Transmit(hsubghz, (uint8_t)Command); + + for (uint16_t i = 0U; i < Size; i++) + { + (void)SUBGHZSPI_Transmit(hsubghz, pBuffer[i]); + } + + /* NSS = 1 */ + LL_PWR_UnselectSUBGHZSPI_NSS(); + + if (Command != RADIO_SET_SLEEP) + { + (void)SUBGHZ_WaitOnBusy(hsubghz); + } + + if (hsubghz->ErrorCode != HAL_SUBGHZ_ERROR_NONE) + { + status = HAL_ERROR; + } + else + { + status = HAL_OK; + } + + hsubghz->State = HAL_SUBGHZ_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsubghz); + + return status; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Retrieve a status from the peripheral + * @param hsubghz pointer to a SUBGHZ_HandleTypeDef structure that contains + * the configuration information for the specified SUBGHZ. + * @param Command configuration for peripheral + * @param pBuffer pointer to a data buffer + * @param Size amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SUBGHZ_ExecGetCmd(SUBGHZ_HandleTypeDef *hsubghz, + SUBGHZ_RadioGetCmd_t Command, + uint8_t *pBuffer, + uint16_t Size) +{ + HAL_StatusTypeDef status; + uint8_t *pData = pBuffer; + + if (hsubghz->State == HAL_SUBGHZ_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hsubghz); + + (void)SUBGHZ_CheckDeviceReady(hsubghz); + + /* NSS = 0 */ + LL_PWR_SelectSUBGHZSPI_NSS(); + + (void)SUBGHZSPI_Transmit(hsubghz, (uint8_t)Command); + + /* Use to flush the Status (First byte) receive from SUBGHZ as not use */ + (void)SUBGHZSPI_Transmit(hsubghz, 0x00U); + + for (uint16_t i = 0U; i < Size; i++) + { + (void)SUBGHZSPI_Receive(hsubghz, (pData)); + pData++; + } + + /* NSS = 1 */ + LL_PWR_UnselectSUBGHZSPI_NSS(); + + (void)SUBGHZ_WaitOnBusy(hsubghz); + + if (hsubghz->ErrorCode != HAL_SUBGHZ_ERROR_NONE) + { + status = HAL_ERROR; + } + else + { + status = HAL_OK; + } + + hsubghz->State = HAL_SUBGHZ_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsubghz); + + return status; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Write data buffer inside payload of peripheral + * @param hsubghz pointer to a SUBGHZ_HandleTypeDef structure that contains + * the configuration information for the specified SUBGHZ. + * @param Offset Offset inside payload + * @param pBuffer pointer to a data buffer + * @param Size amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SUBGHZ_WriteBuffer(SUBGHZ_HandleTypeDef *hsubghz, + uint8_t Offset, + uint8_t *pBuffer, + uint16_t Size) +{ + HAL_StatusTypeDef status; + + if (hsubghz->State == HAL_SUBGHZ_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hsubghz); + + (void)SUBGHZ_CheckDeviceReady(hsubghz); + + /* NSS = 0 */ + LL_PWR_SelectSUBGHZSPI_NSS(); + + (void)SUBGHZSPI_Transmit(hsubghz, SUBGHZ_RADIO_WRITE_BUFFER); + (void)SUBGHZSPI_Transmit(hsubghz, Offset); + + for (uint16_t i = 0U; i < Size; i++) + { + (void)SUBGHZSPI_Transmit(hsubghz, pBuffer[i]); + } + /* NSS = 1 */ + LL_PWR_UnselectSUBGHZSPI_NSS(); + + (void)SUBGHZ_WaitOnBusy(hsubghz); + + if (hsubghz->ErrorCode != HAL_SUBGHZ_ERROR_NONE) + { + status = HAL_ERROR; + } + else + { + status = HAL_OK; + } + + hsubghz->State = HAL_SUBGHZ_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsubghz); + + return status; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Read data buffer inside payload of peripheral + * @param hsubghz pointer to a SUBGHZ_HandleTypeDef structure that contains + * the configuration information for the specified SUBGHZ. + * @param Offset Offset inside payload + * @param pBuffer pointer to a data buffer + * @param Size amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SUBGHZ_ReadBuffer(SUBGHZ_HandleTypeDef *hsubghz, + uint8_t Offset, + uint8_t *pBuffer, + uint16_t Size) +{ + HAL_StatusTypeDef status; + uint8_t *pData = pBuffer; + + if (hsubghz->State == HAL_SUBGHZ_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hsubghz); + + (void)SUBGHZ_CheckDeviceReady(hsubghz); + + /* NSS = 0 */ + LL_PWR_SelectSUBGHZSPI_NSS(); + + (void)SUBGHZSPI_Transmit(hsubghz, SUBGHZ_RADIO_READ_BUFFER); + (void)SUBGHZSPI_Transmit(hsubghz, Offset); + (void)SUBGHZSPI_Transmit(hsubghz, 0x00U); + + for (uint16_t i = 0U; i < Size; i++) + { + (void)SUBGHZSPI_Receive(hsubghz, (pData)); + pData++; + } + + /* NSS = 1 */ + LL_PWR_UnselectSUBGHZSPI_NSS(); + + (void)SUBGHZ_WaitOnBusy(hsubghz); + + if (hsubghz->ErrorCode != HAL_SUBGHZ_ERROR_NONE) + { + status = HAL_ERROR; + } + else + { + status = HAL_OK; + } + + hsubghz->State = HAL_SUBGHZ_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsubghz); + + return status; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Handle SUBGHZ interrupt request. + * @param hsubghz pointer to a SUBGHZ_HandleTypeDef structure that contains + * the configuration information for the specified SUBGHZ module. + * @retval None + */ +void HAL_SUBGHZ_IRQHandler(SUBGHZ_HandleTypeDef *hsubghz) +{ + uint8_t tmpisr[2U] = {0U}; + uint16_t itsource; + + /* Retrieve Interrupts from SUBGHZ Irq Register */ + (void)HAL_SUBGHZ_ExecGetCmd(hsubghz, RADIO_GET_IRQSTATUS, tmpisr, 2U); + itsource = tmpisr[0U]; + itsource = (itsource << 8U) | tmpisr[1U]; + + /* Clear SUBGHZ Irq Register */ + (void)HAL_SUBGHZ_ExecSetCmd(hsubghz, RADIO_CLR_IRQSTATUS, tmpisr, 2U); + + /* Packet transmission completed Interrupt */ + if (SUBGHZ_CHECK_IT_SOURCE(itsource, SUBGHZ_IT_TX_CPLT) != RESET) + { +#if (USE_HAL_SUBGHZ_REGISTER_CALLBACKS == 1U) + hsubghz->TxCpltCallback(hsubghz); +#else + HAL_SUBGHZ_TxCpltCallback(hsubghz); +#endif /* USE_HAL_SUBGHZ_REGISTER_CALLBACKS */ + } + + /* Packet received Interrupt */ + if ((SUBGHZ_CHECK_IT_SOURCE(itsource, SUBGHZ_IT_RX_CPLT) != RESET)) + { + if (SUBGHZ_CHECK_IT_SOURCE(itsource, SUBGHZ_IT_CRC_ERROR) != RESET) + { + hsubghz->ErrorCode |= HAL_SUBGHZ_ERROR_CRC_MISMATCH; + } +#if (USE_HAL_SUBGHZ_REGISTER_CALLBACKS == 1U) + hsubghz->RxCpltCallback(hsubghz); +#else + HAL_SUBGHZ_RxCpltCallback(hsubghz); +#endif /* USE_HAL_SUBGHZ_REGISTER_CALLBACKS */ + } + + /* Preamble Detected Interrupt */ + if (SUBGHZ_CHECK_IT_SOURCE(itsource, SUBGHZ_IT_PREAMBLE_DETECTED) != RESET) + { +#if (USE_HAL_SUBGHZ_REGISTER_CALLBACKS == 1U) + hsubghz->PreambleDetectedCallback(hsubghz); +#else + HAL_SUBGHZ_PreambleDetectedCallback(hsubghz); +#endif /* USE_HAL_SUBGHZ_REGISTER_CALLBACKS */ + } + + /* Valid sync word detected Interrupt */ + if (SUBGHZ_CHECK_IT_SOURCE(itsource, SUBGHZ_IT_SYNCWORD_VALID) != RESET) + { +#if (USE_HAL_SUBGHZ_REGISTER_CALLBACKS == 1U) + hsubghz->SyncWordValidCallback(hsubghz); +#else + HAL_SUBGHZ_SyncWordValidCallback(hsubghz); +#endif /* USE_HAL_SUBGHZ_REGISTER_CALLBACKS */ + } + + /* Valid LoRa header received Interrupt */ + if (SUBGHZ_CHECK_IT_SOURCE(itsource, SUBGHZ_IT_HEADER_VALID) != RESET) + { +#if (USE_HAL_SUBGHZ_REGISTER_CALLBACKS == 1U) + hsubghz->HeaderValidCallback(hsubghz); +#else + HAL_SUBGHZ_HeaderValidCallback(hsubghz); +#endif /* USE_HAL_SUBGHZ_REGISTER_CALLBACKS */ + } + + /* LoRa header CRC error Interrupt */ + if (SUBGHZ_CHECK_IT_SOURCE(itsource, SUBGHZ_IT_HEADER_ERROR) != RESET) + { +#if (USE_HAL_SUBGHZ_REGISTER_CALLBACKS == 1U) + hsubghz->HeaderErrorCallback(hsubghz); +#else + HAL_SUBGHZ_HeaderErrorCallback(hsubghz); +#endif /* USE_HAL_SUBGHZ_REGISTER_CALLBACKS */ + } + + /* Wrong CRC received Interrupt */ + if (SUBGHZ_CHECK_IT_SOURCE(itsource, SUBGHZ_IT_CRC_ERROR) != RESET) + { +#if (USE_HAL_SUBGHZ_REGISTER_CALLBACKS == 1U) + hsubghz->CRCErrorCallback(hsubghz); +#else + HAL_SUBGHZ_CRCErrorCallback(hsubghz); +#endif /* USE_HAL_SUBGHZ_REGISTER_CALLBACKS */ + } + + /* Channel activity detection finished Interrupt */ + if (SUBGHZ_CHECK_IT_SOURCE(itsource, SUBGHZ_IT_CAD_DONE) != RESET) + { +#if (USE_HAL_SUBGHZ_REGISTER_CALLBACKS == 1U) + /* Channel activity Detected Interrupt */ + if (SUBGHZ_CHECK_IT_SOURCE(itsource, SUBGHZ_IT_CAD_ACTIVITY_DETECTED) != RESET) + { + hsubghz->CADStatusCallback(hsubghz, HAL_SUBGHZ_CAD_DETECTED); + } + else + { + hsubghz->CADStatusCallback(hsubghz, HAL_SUBGHZ_CAD_CLEAR); + } +#else + /* Channel activity Detected Interrupt */ + if (SUBGHZ_CHECK_IT_SOURCE(itsource, SUBGHZ_IT_CAD_ACTIVITY_DETECTED) != RESET) + { + HAL_SUBGHZ_CADStatusCallback(hsubghz, HAL_SUBGHZ_CAD_DETECTED); + } + else + { + HAL_SUBGHZ_CADStatusCallback(hsubghz, HAL_SUBGHZ_CAD_CLEAR); + } +#endif /* USE_HAL_SUBGHZ_REGISTER_CALLBACKS */ + } + + /* Rx or Tx Timeout Interrupt */ + if (SUBGHZ_CHECK_IT_SOURCE(itsource, SUBGHZ_IT_RX_TX_TIMEOUT) != RESET) + { +#if (USE_HAL_SUBGHZ_REGISTER_CALLBACKS == 1U) + hsubghz->RxTxTimeoutCallback(hsubghz); +#else + HAL_SUBGHZ_RxTxTimeoutCallback(hsubghz); +#endif /* USE_HAL_SUBGHZ_REGISTER_CALLBACKS */ + } + + /* LR_FHSS Hop interrupt */ + if (SUBGHZ_CHECK_IT_SOURCE(itsource, SUBGHZ_IT_LR_FHSS_HOP) != RESET) + { +#if (USE_HAL_SUBGHZ_REGISTER_CALLBACKS == 1U) + hsubghz->LrFhssHopCallback(hsubghz); +#else + HAL_SUBGHZ_LrFhssHopCallback(hsubghz); +#endif /* USE_HAL_SUBGHZ_REGISTER_CALLBACKS */ + } +} + +/** + * @brief Packet transmission completed callback. + * @param hsubghz pointer to a SUBGHZ_HandleTypeDef structure that contains + * the configuration information for SUBGHZ module. + * @retval None + */ +__weak void HAL_SUBGHZ_TxCpltCallback(SUBGHZ_HandleTypeDef *hsubghz) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsubghz); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SUBGHZ_TxCpltCallback should be implemented in the user file + */ +} + +/** + * @brief Packet received callback. + * @param hsubghz pointer to a SUBGHZ_HandleTypeDef structure that contains + * the configuration information for SUBGHZ module. + * @retval None + */ +__weak void HAL_SUBGHZ_RxCpltCallback(SUBGHZ_HandleTypeDef *hsubghz) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsubghz); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SUBGHZ_RxCpltCallback should be implemented in the user file + */ +} + +/** + * @brief Preamble Detected callback. + * @param hsubghz pointer to a SUBGHZ_HandleTypeDef structure that contains + * the configuration information for SUBGHZ module. + * @retval None + */ +__weak void HAL_SUBGHZ_PreambleDetectedCallback(SUBGHZ_HandleTypeDef *hsubghz) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsubghz); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SUBGHZ_PreambleDetectedCallback should be implemented in the user file + */ +} + +/** + * @brief Valid sync word detected callback. + * @param hsubghz pointer to a SUBGHZ_HandleTypeDef structure that contains + * the configuration information for SUBGHZ module. + * @retval None + */ +__weak void HAL_SUBGHZ_SyncWordValidCallback(SUBGHZ_HandleTypeDef *hsubghz) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsubghz); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SUBGHZ_SyncWordValidCallback should be implemented in the user file + */ +} + +/** + * @brief Valid LoRa header received callback. + * @param hsubghz pointer to a SUBGHZ_HandleTypeDef structure that contains + * the configuration information for SUBGHZ module. + * @retval None + */ +__weak void HAL_SUBGHZ_HeaderValidCallback(SUBGHZ_HandleTypeDef *hsubghz) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsubghz); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SUBGHZ_HeaderValidCallback should be implemented in the user file + */ +} + +/** + * @brief LoRa header CRC error callback. + * @param hsubghz pointer to a SUBGHZ_HandleTypeDef structure that contains + * the configuration information for SUBGHZ module. + * @retval None + */ +__weak void HAL_SUBGHZ_HeaderErrorCallback(SUBGHZ_HandleTypeDef *hsubghz) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsubghz); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SUBGHZ_HeaderErrorCallback should be implemented in the user file + */ +} + +/** + * @brief Wrong CRC received callback. + * @param hsubghz pointer to a SUBGHZ_HandleTypeDef structure that contains + * the configuration information for SUBGHZ module. + * @retval None + */ +__weak void HAL_SUBGHZ_CRCErrorCallback(SUBGHZ_HandleTypeDef *hsubghz) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsubghz); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SUBGHZ_CRCErrorCallback should be implemented in the user file + */ +} + +/** + * @brief Channel activity detection status callback. + * @note Unified callback for CAD Done and CAD activity interrupts. + * @param hsubghz pointer to a SUBGHZ_HandleTypeDef structure that contains + * the configuration information for SUBGHZ module. + * @param cadstatus reports whether activity is detected or not + * @retval None + */ +__weak void HAL_SUBGHZ_CADStatusCallback(SUBGHZ_HandleTypeDef *hsubghz, + HAL_SUBGHZ_CadStatusTypeDef cadstatus) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsubghz); + + UNUSED(cadstatus); + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SUBGHZ_CADStatusCallback should be implemented in the user file + */ +} + +/** + * @brief Rx or Tx Timeout callback. + * @param hsubghz pointer to a SUBGHZ_HandleTypeDef structure that contains + * the configuration information for SUBGHZ module. + * @retval None + */ +__weak void HAL_SUBGHZ_RxTxTimeoutCallback(SUBGHZ_HandleTypeDef *hsubghz) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsubghz); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SUBGHZ_RxTxTimeoutCallback should be implemented in the user file + */ +} + +/** + * @brief LR FHSS Hop callback. + * @param hsubghz pointer to a SUBGHZ_HandleTypeDef structure that contains + * the configuration information for SUBGHZ module. + * @retval None + */ +__weak void HAL_SUBGHZ_LrFhssHopCallback(SUBGHZ_HandleTypeDef *hsubghz) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsubghz); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SUBGHZ_LrFhssHopCallback should be implemented in the user file + */ +} +/** + * @} + */ + +/** @defgroup SUBGHZ_Exported_Functions_Group3 Peripheral State and Errors functions + * @brief SUBGHZ control functions + * +@verbatim + =============================================================================== + ##### Peripheral State and Errors functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the SUBGHZ. + (+) HAL_SUBGHZ_GetState() API can be helpful to check in run-time the state of the SUBGHZ peripheral + (+) HAL_SUBGHZ_GetError() check in run-time Errors occurring during communication +@endverbatim + * @{ + */ + +/** + * @brief Return the SUBGHZ handle state. + * @param hsubghz pointer to a SUBGHZ_HandleTypeDef structure that contains + * the handle information for SUBGHZ module. + * @retval SUBGHZ state + */ +HAL_SUBGHZ_StateTypeDef HAL_SUBGHZ_GetState(const SUBGHZ_HandleTypeDef *hsubghz) +{ + /* Return SUBGHZ handle state */ + return hsubghz->State; +} + +/** + * @brief Return the SUBGHZ error code. + * @param hsubghz pointer to a SUBGHZ_HandleTypeDef structure that contains + * the handle information for SUBGHZ module. + * @retval SUBGHZ error code in bitmap format + */ +uint32_t HAL_SUBGHZ_GetError(const SUBGHZ_HandleTypeDef *hsubghz) +{ + /* Return SUBGHZ ErrorCode */ + return hsubghz->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup SUBGHZ_Private_Functions + * @brief Private functions + * @{ + */ + +/** + * @brief Initializes the SUBGHZSPI peripheral + * @param BaudratePrescaler SPI Baudrate prescaler + * @retval None + */ +void SUBGHZSPI_Init(uint32_t BaudratePrescaler) +{ + /* Check the parameters */ + assert_param(IS_SUBGHZ_ALL_INSTANCE(SUBGHZSPI)); + + /* Disable SUBGHZSPI Peripheral */ + CLEAR_BIT(SUBGHZSPI->CR1, SPI_CR1_SPE); + + /*----------------------- SPI CR1 Configuration ----------------------------* + * SPI Mode: Master * + * Communication Mode: 2 lines (Full-Duplex) * + * Clock polarity: Low * + * phase: 1st Edge * + * NSS management: Internal (Done with External bit inside PWR * + * Communication speed: BaudratePrescaler * + * First bit: MSB * + * CRC calculation: Disable * + *--------------------------------------------------------------------------*/ + WRITE_REG(SUBGHZSPI->CR1, (SPI_CR1_MSTR | SPI_CR1_SSI | BaudratePrescaler | SPI_CR1_SSM)); + + /*----------------------- SPI CR2 Configuration ----------------------------* + * Data Size: 8bits * + * TI Mode: Disable * + * NSS Pulse: Disable * + * Rx FIFO Threshold: 8bits * + *--------------------------------------------------------------------------*/ + WRITE_REG(SUBGHZSPI->CR2, (SPI_CR2_FRXTH | SPI_CR2_DS_0 | SPI_CR2_DS_1 | SPI_CR2_DS_2)); + + /* Enable SUBGHZSPI Peripheral */ + SET_BIT(SUBGHZSPI->CR1, SPI_CR1_SPE); +} + +/** + * @brief DeInitializes the SUBGHZSPI peripheral + * @retval None + */ +void SUBGHZSPI_DeInit(void) +{ + /* Check the parameters */ + assert_param(IS_SUBGHZ_ALL_INSTANCE(SUBGHZSPI)); + + /* Disable SUBGHZSPI Peripheral */ + CLEAR_BIT(SUBGHZSPI->CR1, SPI_CR1_SPE); +} + +/** + * @brief Transmit data through SUBGHZSPI peripheral + * @param hsubghz pointer to a SUBGHZ_HandleTypeDef structure that contains + * the handle information for SUBGHZ module. + * @param Data data to transmit + * @retval HAL status + */ +HAL_StatusTypeDef SUBGHZSPI_Transmit(SUBGHZ_HandleTypeDef *hsubghz, + uint8_t Data) +{ + HAL_StatusTypeDef status = HAL_OK; + __IO uint32_t count; + + /* Handle Tx transmission from SUBGHZSPI peripheral to Radio ****************/ + /* Initialize Timeout */ + count = SUBGHZ_DEFAULT_TIMEOUT * SUBGHZ_DEFAULT_LOOP_TIME; + + /* Wait until TXE flag is set */ + do + { + if (count == 0U) + { + status = HAL_ERROR; + hsubghz->ErrorCode = HAL_SUBGHZ_ERROR_TIMEOUT; + break; + } + count--; + } while (READ_BIT(SUBGHZSPI->SR, SPI_SR_TXE) != (SPI_SR_TXE)); + + /* Transmit Data*/ +#if defined (__GNUC__) + __IO uint8_t *spidr = ((__IO uint8_t *)&SUBGHZSPI->DR); + *spidr = Data; +#else + *((__IO uint8_t *)&SUBGHZSPI->DR) = Data; +#endif /* __GNUC__ */ + + /* Handle Rx transmission from SUBGHZSPI peripheral to Radio ****************/ + /* Initialize Timeout */ + count = SUBGHZ_DEFAULT_TIMEOUT * SUBGHZ_DEFAULT_LOOP_TIME; + + /* Wait until RXNE flag is set */ + do + { + if (count == 0U) + { + status = HAL_ERROR; + hsubghz->ErrorCode = HAL_SUBGHZ_ERROR_TIMEOUT; + break; + } + count--; + } while (READ_BIT(SUBGHZSPI->SR, SPI_SR_RXNE) != (SPI_SR_RXNE)); + + /* Flush Rx data */ + READ_REG(SUBGHZSPI->DR); + + return status; +} + +/** + * @brief Receive data through SUBGHZSPI peripheral + * @param hsubghz pointer to a SUBGHZ_HandleTypeDef structure that contains + * the handle information for SUBGHZ module. + * @param pData pointer on data to receive + * @retval HAL status + */ +HAL_StatusTypeDef SUBGHZSPI_Receive(SUBGHZ_HandleTypeDef *hsubghz, + uint8_t *pData) +{ + HAL_StatusTypeDef status = HAL_OK; + __IO uint32_t count; + + /* Handle Tx transmission from SUBGHZSPI peripheral to Radio ****************/ + /* Initialize Timeout */ + count = SUBGHZ_DEFAULT_TIMEOUT * SUBGHZ_DEFAULT_LOOP_TIME; + + /* Wait until TXE flag is set */ + do + { + if (count == 0U) + { + status = HAL_ERROR; + hsubghz->ErrorCode = HAL_SUBGHZ_ERROR_TIMEOUT; + break; + } + count--; + } while (READ_BIT(SUBGHZSPI->SR, SPI_SR_TXE) != (SPI_SR_TXE)); + + /* Transmit Data*/ +#if defined (__GNUC__) + __IO uint8_t *spidr = ((__IO uint8_t *)&SUBGHZSPI->DR); + *spidr = SUBGHZ_DUMMY_DATA; +#else + *((__IO uint8_t *)&SUBGHZSPI->DR) = SUBGHZ_DUMMY_DATA; +#endif /* __GNUC__ */ + + /* Handle Rx transmission from SUBGHZSPI peripheral to Radio ****************/ + /* Initialize Timeout */ + count = SUBGHZ_DEFAULT_TIMEOUT * SUBGHZ_DEFAULT_LOOP_TIME; + + /* Wait until RXNE flag is set */ + do + { + if (count == 0U) + { + status = HAL_ERROR; + hsubghz->ErrorCode = HAL_SUBGHZ_ERROR_TIMEOUT; + break; + } + count--; + } while (READ_BIT(SUBGHZSPI->SR, SPI_SR_RXNE) != (SPI_SR_RXNE)); + + /* Retrieve pData */ + *pData = (uint8_t)(READ_REG(SUBGHZSPI->DR)); + + return status; +} + +/** + * @brief Check if peripheral is ready + * @param hsubghz pointer to a SUBGHZ_HandleTypeDef structure that contains + * the handle information for SUBGHZ module. + * @retval HAL status + */ +HAL_StatusTypeDef SUBGHZ_CheckDeviceReady(SUBGHZ_HandleTypeDef *hsubghz) +{ + __IO uint32_t count; + + /* Wakeup radio in case of sleep mode: Select-Unselect radio */ + if (hsubghz->DeepSleep == SUBGHZ_DEEP_SLEEP_ENABLE) + { + /* Initialize NSS switch Delay */ + count = SUBGHZ_NSS_LOOP_TIME; + + /* NSS = 0; */ + LL_PWR_SelectSUBGHZSPI_NSS(); + + /* Wait Radio wakeup */ + do + { + count--; + } while (count != 0UL); + + /* NSS = 1 */ + LL_PWR_UnselectSUBGHZSPI_NSS(); + } + return (SUBGHZ_WaitOnBusy(hsubghz)); +} + +/** + * @brief Wait busy flag low from peripheral + * @param hsubghz pointer to a SUBGHZ_HandleTypeDef structure that contains + * the handle information for SUBGHZ module. + * @retval HAL status + */ +HAL_StatusTypeDef SUBGHZ_WaitOnBusy(SUBGHZ_HandleTypeDef *hsubghz) +{ + HAL_StatusTypeDef status; + __IO uint32_t count; + uint32_t mask; + + status = HAL_OK; + count = SUBGHZ_DEFAULT_TIMEOUT * SUBGHZ_RFBUSY_LOOP_TIME; + + /* Wait until Busy signal is set */ + do + { + mask = LL_PWR_IsActiveFlag_RFBUSYMS(); + + if (count == 0U) + { + status = HAL_ERROR; + hsubghz->ErrorCode = HAL_SUBGHZ_ERROR_RF_BUSY; + break; + } + count--; + } while ((LL_PWR_IsActiveFlag_RFBUSYS()& mask) == 1UL); + + return status; +} +/** + * @} + */ + +#endif /* HAL_SUBGHZ_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c b/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c new file mode 100644 index 0000000..a9ffee6 --- /dev/null +++ b/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c @@ -0,0 +1,4817 @@ +/** + ****************************************************************************** + * @file stm32wlxx_hal_uart.c + * @author MCD Application Team + * @brief UART HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART). + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral Control functions + * + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + =============================================================================== + ##### How to use this driver ##### + =============================================================================== + [..] + The UART HAL driver can be used as follows: + + (#) Declare a UART_HandleTypeDef handle structure (eg. UART_HandleTypeDef huart). + (#) Initialize the UART low level resources by implementing the HAL_UART_MspInit() API: + (++) Enable the USARTx interface clock. + (++) UART pins configuration: + (+++) Enable the clock for the UART GPIOs. + (+++) Configure these UART pins as alternate function pull-up. + (++) NVIC configuration if you need to use interrupt process (HAL_UART_Transmit_IT() + and HAL_UART_Receive_IT() APIs): + (+++) Configure the USARTx interrupt priority. + (+++) Enable the NVIC USART IRQ handle. + (++) UART interrupts handling: + -@@- The specific UART interrupts (Transmission complete interrupt, + RXNE interrupt, RX/TX FIFOs related interrupts and Error Interrupts) + are managed using the macros __HAL_UART_ENABLE_IT() and __HAL_UART_DISABLE_IT() + inside the transmit and receive processes. + (++) DMA Configuration if you need to use DMA process (HAL_UART_Transmit_DMA() + and HAL_UART_Receive_DMA() APIs): + (+++) Declare a DMA handle structure for the Tx/Rx channel. + (+++) Enable the DMAx interface clock. + (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters. + (+++) Configure the DMA Tx/Rx channel. + (+++) Associate the initialized DMA handle to the UART DMA Tx/Rx handle. + (+++) Configure the priority and enable the NVIC for the transfer complete + interrupt on the DMA Tx/Rx channel. + + (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Prescaler value , Hardware + flow control and Mode (Receiver/Transmitter) in the huart handle Init structure. + + (#) If required, program UART advanced features (TX/RX pins swap, auto Baud rate detection,...) + in the huart handle AdvancedInit structure. + + (#) For the UART asynchronous mode, initialize the UART registers by calling + the HAL_UART_Init() API. + + (#) For the UART Half duplex mode, initialize the UART registers by calling + the HAL_HalfDuplex_Init() API. + + (#) For the UART LIN (Local Interconnection Network) mode, initialize the UART registers + by calling the HAL_LIN_Init() API. + + (#) For the UART Multiprocessor mode, initialize the UART registers + by calling the HAL_MultiProcessor_Init() API. + + (#) For the UART RS485 Driver Enabled mode, initialize the UART registers + by calling the HAL_RS485Ex_Init() API. + + [..] + (@) These API's (HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(), + also configure the low level Hardware GPIO, CLOCK, CORTEX...etc) by + calling the customized HAL_UART_MspInit() API. + + ##### Callback registration ##### + ================================== + + [..] + The compilation define USE_HAL_UART_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + + [..] + Use Function HAL_UART_RegisterCallback() to register a user callback. + Function HAL_UART_RegisterCallback() allows to register following callbacks: + (+) TxHalfCpltCallback : Tx Half Complete Callback. + (+) TxCpltCallback : Tx Complete Callback. + (+) RxHalfCpltCallback : Rx Half Complete Callback. + (+) RxCpltCallback : Rx Complete Callback. + (+) ErrorCallback : Error Callback. + (+) AbortCpltCallback : Abort Complete Callback. + (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback. + (+) AbortReceiveCpltCallback : Abort Receive Complete Callback. + (+) WakeupCallback : Wakeup Callback. + (+) RxFifoFullCallback : Rx Fifo Full Callback. + (+) TxFifoEmptyCallback : Tx Fifo Empty Callback. + (+) MspInitCallback : UART MspInit. + (+) MspDeInitCallback : UART MspDeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + [..] + Use function HAL_UART_UnRegisterCallback() to reset a callback to the default + weak function. + HAL_UART_UnRegisterCallback() takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) TxHalfCpltCallback : Tx Half Complete Callback. + (+) TxCpltCallback : Tx Complete Callback. + (+) RxHalfCpltCallback : Rx Half Complete Callback. + (+) RxCpltCallback : Rx Complete Callback. + (+) ErrorCallback : Error Callback. + (+) AbortCpltCallback : Abort Complete Callback. + (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback. + (+) AbortReceiveCpltCallback : Abort Receive Complete Callback. + (+) WakeupCallback : Wakeup Callback. + (+) RxFifoFullCallback : Rx Fifo Full Callback. + (+) TxFifoEmptyCallback : Tx Fifo Empty Callback. + (+) MspInitCallback : UART MspInit. + (+) MspDeInitCallback : UART MspDeInit. + + [..] + For specific callback RxEventCallback, use dedicated registration/reset functions: + respectively HAL_UART_RegisterRxEventCallback() , HAL_UART_UnRegisterRxEventCallback(). + + [..] + By default, after the HAL_UART_Init() and when the state is HAL_UART_STATE_RESET + all callbacks are set to the corresponding weak functions: + examples HAL_UART_TxCpltCallback(), HAL_UART_RxHalfCpltCallback(). + Exception done for MspInit and MspDeInit functions that are respectively + reset to the legacy weak functions in the HAL_UART_Init() + and HAL_UART_DeInit() only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_UART_Init() and HAL_UART_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand). + + [..] + Callbacks can be registered/unregistered in HAL_UART_STATE_READY state only. + Exception done MspInit/MspDeInit that can be registered/unregistered + in HAL_UART_STATE_READY or HAL_UART_STATE_RESET state, thus registered (user) + MspInit/DeInit callbacks can be used during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using HAL_UART_RegisterCallback() before calling HAL_UART_DeInit() + or HAL_UART_Init() function. + + [..] + When The compilation define USE_HAL_UART_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available + and weak callbacks are used. + + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wlxx_hal.h" + +/** @addtogroup STM32WLxx_HAL_Driver + * @{ + */ + +/** @defgroup UART UART + * @brief HAL UART module driver + * @{ + */ + +#ifdef HAL_UART_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup UART_Private_Constants UART Private Constants + * @{ + */ +#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | \ + USART_CR1_OVER8 | USART_CR1_FIFOEN)) /*!< UART or USART CR1 fields of parameters set by UART_SetConfig API */ + +#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_ONEBIT | USART_CR3_TXFTCFG | \ + USART_CR3_RXFTCFG)) /*!< UART or USART CR3 fields of parameters set by UART_SetConfig API */ + +#define LPUART_BRR_MIN 0x00000300U /* LPUART BRR minimum authorized value */ +#define LPUART_BRR_MAX 0x000FFFFFU /* LPUART BRR maximum authorized value */ + +#define UART_BRR_MIN 0x10U /* UART BRR minimum authorized value */ +#define UART_BRR_MAX 0x0000FFFFU /* UART BRR maximum authorized value */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @addtogroup UART_Private_Functions + * @{ + */ +static void UART_EndRxTransfer(UART_HandleTypeDef *huart); +static void UART_EndTxTransfer(UART_HandleTypeDef *huart); +static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma); +static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma); +static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma); +static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma); +static void UART_DMAError(DMA_HandleTypeDef *hdma); +static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma); +static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma); +static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma); +static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma); +static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma); +static void UART_TxISR_8BIT(UART_HandleTypeDef *huart); +static void UART_TxISR_16BIT(UART_HandleTypeDef *huart); +static void UART_TxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart); +static void UART_TxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart); +static void UART_EndTransmit_IT(UART_HandleTypeDef *huart); +static void UART_RxISR_8BIT(UART_HandleTypeDef *huart); +static void UART_RxISR_16BIT(UART_HandleTypeDef *huart); +static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart); +static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart); +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/** @addtogroup UART_Private_variables + * @{ + */ +const uint16_t UARTPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U}; +/** + * @} + */ + +/* Exported Constants --------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup UART_Exported_Functions UART Exported Functions + * @{ + */ + +/** @defgroup UART_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim +=============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to initialize the USARTx or the UARTy + in asynchronous mode. + (+) For the asynchronous mode the parameters below can be configured: + (++) Baud Rate + (++) Word Length + (++) Stop Bit + (++) Parity: If the parity is enabled, then the MSB bit of the data written + in the data register is transmitted but is changed by the parity bit. + (++) Hardware flow control + (++) Receiver/transmitter modes + (++) Over Sampling Method + (++) One-Bit Sampling Method + (+) For the asynchronous mode, the following advanced features can be configured as well: + (++) TX and/or RX pin level inversion + (++) data logical level inversion + (++) RX and TX pins swap + (++) RX overrun detection disabling + (++) DMA disabling on RX error + (++) MSB first on communication line + (++) auto Baud rate detection + [..] + The HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init()and HAL_MultiProcessor_Init()API + follow respectively the UART asynchronous, UART Half duplex, UART LIN mode + and UART multiprocessor mode configuration procedures (details for the procedures + are available in reference manual). + +@endverbatim + + Depending on the frame length defined by the M1 and M0 bits (7-bit, + 8-bit or 9-bit), the possible UART formats are listed in the + following table. + + Table 1. UART frame format. + +-----------------------------------------------------------------------+ + | M1 bit | M0 bit | PCE bit | UART frame | + |---------|---------|-----------|---------------------------------------| + | 0 | 0 | 0 | | SB | 8 bit data | STB | | + |---------|---------|-----------|---------------------------------------| + | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | | + |---------|---------|-----------|---------------------------------------| + | 0 | 1 | 0 | | SB | 9 bit data | STB | | + |---------|---------|-----------|---------------------------------------| + | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | | + |---------|---------|-----------|---------------------------------------| + | 1 | 0 | 0 | | SB | 7 bit data | STB | | + |---------|---------|-----------|---------------------------------------| + | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | | + +-----------------------------------------------------------------------+ + + * @{ + */ + +/** + * @brief Initialize the UART mode according to the specified + * parameters in the UART_InitTypeDef and initialize the associated handle. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) +{ + /* Check the UART handle allocation */ + if (huart == NULL) + { + return HAL_ERROR; + } + + if (huart->Init.HwFlowCtl != UART_HWCONTROL_NONE) + { + /* Check the parameters */ + assert_param(IS_UART_HWFLOW_INSTANCE(huart->Instance)); + } + else + { + /* Check the parameters */ + assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance))); + } + + if (huart->gState == HAL_UART_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + huart->Lock = HAL_UNLOCKED; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + UART_InitCallbacksToDefault(huart); + + if (huart->MspInitCallback == NULL) + { + huart->MspInitCallback = HAL_UART_MspInit; + } + + /* Init the low level hardware */ + huart->MspInitCallback(huart); +#else + /* Init the low level hardware : GPIO, CLOCK */ + HAL_UART_MspInit(huart); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + + huart->gState = HAL_UART_STATE_BUSY; + + __HAL_UART_DISABLE(huart); + + /* Perform advanced settings configuration */ + /* For some items, configuration requires to be done prior TE and RE bits are set */ + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) + { + UART_AdvFeatureConfig(huart); + } + + /* Set the UART Communication parameters */ + if (UART_SetConfig(huart) == HAL_ERROR) + { + return HAL_ERROR; + } + + /* In asynchronous mode, the following bits must be kept cleared: + - LINEN and CLKEN bits in the USART_CR2 register, + - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ + CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); + + __HAL_UART_ENABLE(huart); + + /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ + return (UART_CheckIdleState(huart)); +} + +/** + * @brief Initialize the half-duplex mode according to the specified + * parameters in the UART_InitTypeDef and creates the associated handle. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart) +{ + /* Check the UART handle allocation */ + if (huart == NULL) + { + return HAL_ERROR; + } + + /* Check UART instance */ + assert_param(IS_UART_HALFDUPLEX_INSTANCE(huart->Instance)); + + if (huart->gState == HAL_UART_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + huart->Lock = HAL_UNLOCKED; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + UART_InitCallbacksToDefault(huart); + + if (huart->MspInitCallback == NULL) + { + huart->MspInitCallback = HAL_UART_MspInit; + } + + /* Init the low level hardware */ + huart->MspInitCallback(huart); +#else + /* Init the low level hardware : GPIO, CLOCK */ + HAL_UART_MspInit(huart); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + + huart->gState = HAL_UART_STATE_BUSY; + + __HAL_UART_DISABLE(huart); + + /* Perform advanced settings configuration */ + /* For some items, configuration requires to be done prior TE and RE bits are set */ + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) + { + UART_AdvFeatureConfig(huart); + } + + /* Set the UART Communication parameters */ + if (UART_SetConfig(huart) == HAL_ERROR) + { + return HAL_ERROR; + } + + /* In half-duplex mode, the following bits must be kept cleared: + - LINEN and CLKEN bits in the USART_CR2 register, + - SCEN and IREN bits in the USART_CR3 register.*/ + CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_IREN | USART_CR3_SCEN)); + + /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */ + SET_BIT(huart->Instance->CR3, USART_CR3_HDSEL); + + __HAL_UART_ENABLE(huart); + + /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ + return (UART_CheckIdleState(huart)); +} + + +/** + * @brief Initialize the LIN mode according to the specified + * parameters in the UART_InitTypeDef and creates the associated handle. + * @param huart UART handle. + * @param BreakDetectLength Specifies the LIN break detection length. + * This parameter can be one of the following values: + * @arg @ref UART_LINBREAKDETECTLENGTH_10B 10-bit break detection + * @arg @ref UART_LINBREAKDETECTLENGTH_11B 11-bit break detection + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength) +{ + /* Check the UART handle allocation */ + if (huart == NULL) + { + return HAL_ERROR; + } + + /* Check the LIN UART instance */ + assert_param(IS_UART_LIN_INSTANCE(huart->Instance)); + /* Check the Break detection length parameter */ + assert_param(IS_UART_LIN_BREAK_DETECT_LENGTH(BreakDetectLength)); + + /* LIN mode limited to 16-bit oversampling only */ + if (huart->Init.OverSampling == UART_OVERSAMPLING_8) + { + return HAL_ERROR; + } + /* LIN mode limited to 8-bit data length */ + if (huart->Init.WordLength != UART_WORDLENGTH_8B) + { + return HAL_ERROR; + } + + if (huart->gState == HAL_UART_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + huart->Lock = HAL_UNLOCKED; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + UART_InitCallbacksToDefault(huart); + + if (huart->MspInitCallback == NULL) + { + huart->MspInitCallback = HAL_UART_MspInit; + } + + /* Init the low level hardware */ + huart->MspInitCallback(huart); +#else + /* Init the low level hardware : GPIO, CLOCK */ + HAL_UART_MspInit(huart); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + + huart->gState = HAL_UART_STATE_BUSY; + + __HAL_UART_DISABLE(huart); + + /* Perform advanced settings configuration */ + /* For some items, configuration requires to be done prior TE and RE bits are set */ + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) + { + UART_AdvFeatureConfig(huart); + } + + /* Set the UART Communication parameters */ + if (UART_SetConfig(huart) == HAL_ERROR) + { + return HAL_ERROR; + } + + /* In LIN mode, the following bits must be kept cleared: + - LINEN and CLKEN bits in the USART_CR2 register, + - SCEN and IREN bits in the USART_CR3 register.*/ + CLEAR_BIT(huart->Instance->CR2, USART_CR2_CLKEN); + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_HDSEL | USART_CR3_IREN | USART_CR3_SCEN)); + + /* Enable the LIN mode by setting the LINEN bit in the CR2 register */ + SET_BIT(huart->Instance->CR2, USART_CR2_LINEN); + + /* Set the USART LIN Break detection length. */ + MODIFY_REG(huart->Instance->CR2, USART_CR2_LBDL, BreakDetectLength); + + __HAL_UART_ENABLE(huart); + + /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ + return (UART_CheckIdleState(huart)); +} + + +/** + * @brief Initialize the multiprocessor mode according to the specified + * parameters in the UART_InitTypeDef and initialize the associated handle. + * @param huart UART handle. + * @param Address UART node address (4-, 6-, 7- or 8-bit long). + * @param WakeUpMethod Specifies the UART wakeup method. + * This parameter can be one of the following values: + * @arg @ref UART_WAKEUPMETHOD_IDLELINE WakeUp by an idle line detection + * @arg @ref UART_WAKEUPMETHOD_ADDRESSMARK WakeUp by an address mark + * @note If the user resorts to idle line detection wake up, the Address parameter + * is useless and ignored by the initialization function. + * @note If the user resorts to address mark wake up, the address length detection + * is configured by default to 4 bits only. For the UART to be able to + * manage 6-, 7- or 8-bit long addresses detection, the API + * HAL_MultiProcessorEx_AddressLength_Set() must be called after + * HAL_MultiProcessor_Init(). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod) +{ + /* Check the UART handle allocation */ + if (huart == NULL) + { + return HAL_ERROR; + } + + /* Check the wake up method parameter */ + assert_param(IS_UART_WAKEUPMETHOD(WakeUpMethod)); + + if (huart->gState == HAL_UART_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + huart->Lock = HAL_UNLOCKED; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + UART_InitCallbacksToDefault(huart); + + if (huart->MspInitCallback == NULL) + { + huart->MspInitCallback = HAL_UART_MspInit; + } + + /* Init the low level hardware */ + huart->MspInitCallback(huart); +#else + /* Init the low level hardware : GPIO, CLOCK */ + HAL_UART_MspInit(huart); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + + huart->gState = HAL_UART_STATE_BUSY; + + __HAL_UART_DISABLE(huart); + + /* Perform advanced settings configuration */ + /* For some items, configuration requires to be done prior TE and RE bits are set */ + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) + { + UART_AdvFeatureConfig(huart); + } + + /* Set the UART Communication parameters */ + if (UART_SetConfig(huart) == HAL_ERROR) + { + return HAL_ERROR; + } + + /* In multiprocessor mode, the following bits must be kept cleared: + - LINEN and CLKEN bits in the USART_CR2 register, + - SCEN, HDSEL and IREN bits in the USART_CR3 register. */ + CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); + + if (WakeUpMethod == UART_WAKEUPMETHOD_ADDRESSMARK) + { + /* If address mark wake up method is chosen, set the USART address node */ + MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)Address << UART_CR2_ADDRESS_LSB_POS)); + } + + /* Set the wake up method by setting the WAKE bit in the CR1 register */ + MODIFY_REG(huart->Instance->CR1, USART_CR1_WAKE, WakeUpMethod); + + __HAL_UART_ENABLE(huart); + + /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ + return (UART_CheckIdleState(huart)); +} + + +/** + * @brief DeInitialize the UART peripheral. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) +{ + /* Check the UART handle allocation */ + if (huart == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance))); + + huart->gState = HAL_UART_STATE_BUSY; + + __HAL_UART_DISABLE(huart); + + huart->Instance->CR1 = 0x0U; + huart->Instance->CR2 = 0x0U; + huart->Instance->CR3 = 0x0U; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + if (huart->MspDeInitCallback == NULL) + { + huart->MspDeInitCallback = HAL_UART_MspDeInit; + } + /* DeInit the low level hardware */ + huart->MspDeInitCallback(huart); +#else + /* DeInit the low level hardware */ + HAL_UART_MspDeInit(huart); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->gState = HAL_UART_STATE_RESET; + huart->RxState = HAL_UART_STATE_RESET; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + huart->RxEventType = HAL_UART_RXEVENT_TC; + + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Initialize the UART MSP. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_MspInit(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_MspInit can be implemented in the user file + */ +} + +/** + * @brief DeInitialize the UART MSP. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_MspDeInit can be implemented in the user file + */ +} + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User UART Callback + * To be used to override the weak predefined callback + * @note The HAL_UART_RegisterCallback() may be called before HAL_UART_Init(), HAL_HalfDuplex_Init(), + * HAL_LIN_Init(), HAL_MultiProcessor_Init() or HAL_RS485Ex_Init() in HAL_UART_STATE_RESET to register + * callbacks for HAL_UART_MSPINIT_CB_ID and HAL_UART_MSPDEINIT_CB_ID + * @param huart uart handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_UART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID + * @arg @ref HAL_UART_TX_COMPLETE_CB_ID Tx Complete Callback ID + * @arg @ref HAL_UART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID + * @arg @ref HAL_UART_RX_COMPLETE_CB_ID Rx Complete Callback ID + * @arg @ref HAL_UART_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID + * @arg @ref HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID + * @arg @ref HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID + * @arg @ref HAL_UART_WAKEUP_CB_ID Wakeup Callback ID + * @arg @ref HAL_UART_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID + * @arg @ref HAL_UART_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID + * @arg @ref HAL_UART_MSPINIT_CB_ID MspInit Callback ID + * @arg @ref HAL_UART_MSPDEINIT_CB_ID MspDeInit Callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, + pUART_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + if (huart->gState == HAL_UART_STATE_READY) + { + switch (CallbackID) + { + case HAL_UART_TX_HALFCOMPLETE_CB_ID : + huart->TxHalfCpltCallback = pCallback; + break; + + case HAL_UART_TX_COMPLETE_CB_ID : + huart->TxCpltCallback = pCallback; + break; + + case HAL_UART_RX_HALFCOMPLETE_CB_ID : + huart->RxHalfCpltCallback = pCallback; + break; + + case HAL_UART_RX_COMPLETE_CB_ID : + huart->RxCpltCallback = pCallback; + break; + + case HAL_UART_ERROR_CB_ID : + huart->ErrorCallback = pCallback; + break; + + case HAL_UART_ABORT_COMPLETE_CB_ID : + huart->AbortCpltCallback = pCallback; + break; + + case HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID : + huart->AbortTransmitCpltCallback = pCallback; + break; + + case HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID : + huart->AbortReceiveCpltCallback = pCallback; + break; + + case HAL_UART_WAKEUP_CB_ID : + huart->WakeupCallback = pCallback; + break; + + case HAL_UART_RX_FIFO_FULL_CB_ID : + huart->RxFifoFullCallback = pCallback; + break; + + case HAL_UART_TX_FIFO_EMPTY_CB_ID : + huart->TxFifoEmptyCallback = pCallback; + break; + + case HAL_UART_MSPINIT_CB_ID : + huart->MspInitCallback = pCallback; + break; + + case HAL_UART_MSPDEINIT_CB_ID : + huart->MspDeInitCallback = pCallback; + break; + + default : + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + status = HAL_ERROR; + break; + } + } + else if (huart->gState == HAL_UART_STATE_RESET) + { + switch (CallbackID) + { + case HAL_UART_MSPINIT_CB_ID : + huart->MspInitCallback = pCallback; + break; + + case HAL_UART_MSPDEINIT_CB_ID : + huart->MspDeInitCallback = pCallback; + break; + + default : + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + status = HAL_ERROR; + break; + } + } + else + { + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Unregister an UART Callback + * UART callaback is redirected to the weak predefined callback + * @note The HAL_UART_UnRegisterCallback() may be called before HAL_UART_Init(), HAL_HalfDuplex_Init(), + * HAL_LIN_Init(), HAL_MultiProcessor_Init() or HAL_RS485Ex_Init() in HAL_UART_STATE_RESET to un-register + * callbacks for HAL_UART_MSPINIT_CB_ID and HAL_UART_MSPDEINIT_CB_ID + * @param huart uart handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_UART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID + * @arg @ref HAL_UART_TX_COMPLETE_CB_ID Tx Complete Callback ID + * @arg @ref HAL_UART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID + * @arg @ref HAL_UART_RX_COMPLETE_CB_ID Rx Complete Callback ID + * @arg @ref HAL_UART_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID + * @arg @ref HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID + * @arg @ref HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID + * @arg @ref HAL_UART_WAKEUP_CB_ID Wakeup Callback ID + * @arg @ref HAL_UART_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID + * @arg @ref HAL_UART_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID + * @arg @ref HAL_UART_MSPINIT_CB_ID MspInit Callback ID + * @arg @ref HAL_UART_MSPDEINIT_CB_ID MspDeInit Callback ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (HAL_UART_STATE_READY == huart->gState) + { + switch (CallbackID) + { + case HAL_UART_TX_HALFCOMPLETE_CB_ID : + huart->TxHalfCpltCallback = HAL_UART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ + break; + + case HAL_UART_TX_COMPLETE_CB_ID : + huart->TxCpltCallback = HAL_UART_TxCpltCallback; /* Legacy weak TxCpltCallback */ + break; + + case HAL_UART_RX_HALFCOMPLETE_CB_ID : + huart->RxHalfCpltCallback = HAL_UART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ + break; + + case HAL_UART_RX_COMPLETE_CB_ID : + huart->RxCpltCallback = HAL_UART_RxCpltCallback; /* Legacy weak RxCpltCallback */ + break; + + case HAL_UART_ERROR_CB_ID : + huart->ErrorCallback = HAL_UART_ErrorCallback; /* Legacy weak ErrorCallback */ + break; + + case HAL_UART_ABORT_COMPLETE_CB_ID : + huart->AbortCpltCallback = HAL_UART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + break; + + case HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID : + huart->AbortTransmitCpltCallback = HAL_UART_AbortTransmitCpltCallback; /* Legacy weak + AbortTransmitCpltCallback */ + break; + + case HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID : + huart->AbortReceiveCpltCallback = HAL_UART_AbortReceiveCpltCallback; /* Legacy weak + AbortReceiveCpltCallback */ + break; + + case HAL_UART_WAKEUP_CB_ID : + huart->WakeupCallback = HAL_UARTEx_WakeupCallback; /* Legacy weak WakeupCallback */ + break; + + case HAL_UART_RX_FIFO_FULL_CB_ID : + huart->RxFifoFullCallback = HAL_UARTEx_RxFifoFullCallback; /* Legacy weak RxFifoFullCallback */ + break; + + case HAL_UART_TX_FIFO_EMPTY_CB_ID : + huart->TxFifoEmptyCallback = HAL_UARTEx_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */ + break; + + case HAL_UART_MSPINIT_CB_ID : + huart->MspInitCallback = HAL_UART_MspInit; /* Legacy weak MspInitCallback */ + break; + + case HAL_UART_MSPDEINIT_CB_ID : + huart->MspDeInitCallback = HAL_UART_MspDeInit; /* Legacy weak MspDeInitCallback */ + break; + + default : + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + status = HAL_ERROR; + break; + } + } + else if (HAL_UART_STATE_RESET == huart->gState) + { + switch (CallbackID) + { + case HAL_UART_MSPINIT_CB_ID : + huart->MspInitCallback = HAL_UART_MspInit; + break; + + case HAL_UART_MSPDEINIT_CB_ID : + huart->MspDeInitCallback = HAL_UART_MspDeInit; + break; + + default : + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + status = HAL_ERROR; + break; + } + } + else + { + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Register a User UART Rx Event Callback + * To be used instead of the weak predefined callback + * @param huart Uart handle + * @param pCallback Pointer to the Rx Event Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(UART_HandleTypeDef *huart, pUART_RxEventCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + if (huart->RxState == HAL_UART_STATE_READY) + { + huart->RxEventCallback = pCallback; + } + else + { + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief UnRegister the UART Rx Event Callback + * UART Rx Event Callback is redirected to the weak HAL_UARTEx_RxEventCallback() predefined callback + * @param huart Uart handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (huart->RxState == HAL_UART_STATE_READY) + { + huart->RxEventCallback = HAL_UARTEx_RxEventCallback; /* Legacy weak UART Rx Event Callback */ + } + else + { + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + status = HAL_ERROR; + } + + return status; +} + +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup UART_Exported_Functions_Group2 IO operation functions + * @brief UART Transmit/Receive functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the UART asynchronous + and Half duplex data transfers. + + (#) There are two modes of transfer: + (++) Blocking mode: The communication is performed in polling mode. + The HAL status of all data processing is returned by the same function + after finishing transfer. + (++) Non-Blocking mode: The communication is performed using Interrupts + or DMA, These API's return the HAL status. + The end of the data processing will be indicated through the + dedicated UART IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks + will be executed respectively at the end of the transmit or Receive process + The HAL_UART_ErrorCallback()user callback will be executed when a communication error is detected + + (#) Blocking mode API's are : + (++) HAL_UART_Transmit() + (++) HAL_UART_Receive() + + (#) Non-Blocking mode API's with Interrupt are : + (++) HAL_UART_Transmit_IT() + (++) HAL_UART_Receive_IT() + (++) HAL_UART_IRQHandler() + + (#) Non-Blocking mode API's with DMA are : + (++) HAL_UART_Transmit_DMA() + (++) HAL_UART_Receive_DMA() + (++) HAL_UART_DMAPause() + (++) HAL_UART_DMAResume() + (++) HAL_UART_DMAStop() + + (#) A set of Transfer Complete Callbacks are provided in Non_Blocking mode: + (++) HAL_UART_TxHalfCpltCallback() + (++) HAL_UART_TxCpltCallback() + (++) HAL_UART_RxHalfCpltCallback() + (++) HAL_UART_RxCpltCallback() + (++) HAL_UART_ErrorCallback() + + (#) Non-Blocking mode transfers could be aborted using Abort API's : + (++) HAL_UART_Abort() + (++) HAL_UART_AbortTransmit() + (++) HAL_UART_AbortReceive() + (++) HAL_UART_Abort_IT() + (++) HAL_UART_AbortTransmit_IT() + (++) HAL_UART_AbortReceive_IT() + + (#) For Abort services based on interrupts (HAL_UART_Abortxxx_IT), a set of Abort Complete Callbacks are provided: + (++) HAL_UART_AbortCpltCallback() + (++) HAL_UART_AbortTransmitCpltCallback() + (++) HAL_UART_AbortReceiveCpltCallback() + + (#) A Rx Event Reception Callback (Rx event notification) is available for Non_Blocking modes of enhanced + reception services: + (++) HAL_UARTEx_RxEventCallback() + + (#) Wakeup from Stop mode Callback: + (++) HAL_UARTEx_WakeupCallback() + + (#) In Non-Blocking mode transfers, possible errors are split into 2 categories. + Errors are handled as follows : + (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is + to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error + in Interrupt mode reception . + Received character is then retrieved and stored in Rx buffer, Error code is set to allow user + to identify error type, and HAL_UART_ErrorCallback() user callback is executed. + Transfer is kept ongoing on UART side. + If user wants to abort it, Abort services should be called by user. + (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted. + This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode. + Error code is set to allow user to identify error type, and HAL_UART_ErrorCallback() + user callback is executed. + + -@- In the Half duplex communication, it is forbidden to run the transmit + and receive process in parallel, the UART state HAL_UART_STATE_BUSY_TX_RX can't be useful. + +@endverbatim + * @{ + */ + +/** + * @brief Send an amount of data in blocking mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data is handled as a set of u16. In this case, Size must indicate the number + * of u16 provided through pData. + * @note When FIFO mode is enabled, writing a data in the TDR register adds one + * data to the TXFIFO. Write operations to the TDR register are performed + * when TXFNF flag is set. From hardware perspective, TXFNF flag and + * TXE are mapped on the same bit-field. +#if defined(CORE_CM0PLUS) + * @note Dual core specific: there is no support for unaligned accesses on the Cortex-M0+ processor. + * When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits) + * (as sent data will be handled using u16 pointer cast). Depending on compilation chain, + * use of specific alignment compilation directives or pragmas might be required + * to ensure proper alignment for pData. +#endif + * @param huart UART handle. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be sent. + * @param Timeout Timeout duration. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + const uint8_t *pdata8bits; + const uint16_t *pdata16bits; + uint32_t tickstart; + + /* Check that a Tx process is not already ongoing */ + if (huart->gState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + +#if defined(CORE_CM0PLUS) + /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter + should be aligned on a u16 frontier, as data to be filled into TDR will be + handled through a u16 cast. */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + if ((((uint32_t)pData) & 1U) != 0U) + { + return HAL_ERROR; + } + } + +#endif /* CORE_CM0PLUS */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->gState = HAL_UART_STATE_BUSY_TX; + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + + huart->TxXferSize = Size; + huart->TxXferCount = Size; + + /* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + pdata8bits = NULL; + pdata16bits = (const uint16_t *) pData; + } + else + { + pdata8bits = pData; + pdata16bits = NULL; + } + + while (huart->TxXferCount > 0U) + { + if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) + { + + huart->gState = HAL_UART_STATE_READY; + + return HAL_TIMEOUT; + } + if (pdata8bits == NULL) + { + huart->Instance->TDR = (uint16_t)(*pdata16bits & 0x01FFU); + pdata16bits++; + } + else + { + huart->Instance->TDR = (uint8_t)(*pdata8bits & 0xFFU); + pdata8bits++; + } + if ((huart->gState & HAL_UART_STATE_BUSY_TX) == HAL_UART_STATE_BUSY_TX) + { + huart->TxXferCount--; + } + else + { + /* Process was aborted during the transmission */ + return HAL_ERROR; + } + } + + if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) + { + huart->gState = HAL_UART_STATE_READY; + + return HAL_TIMEOUT; + } + + /* At end of Tx process, restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in blocking mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of u16. In this case, Size must indicate the number + * of u16 available through pData. + * @note When FIFO mode is enabled, the RXFNE flag is set as long as the RXFIFO + * is not empty. Read operations from the RDR register are performed when + * RXFNE flag is set. From hardware perspective, RXFNE flag and + * RXNE are mapped on the same bit-field. +#if defined(CORE_CM0PLUS) + * @note Dual core specific: there is no support for unaligned accesses on the Cortex-M0+ processor. + * When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * address of user data buffer for storing data to be received, should be aligned on a half word frontier + * (16 bits) (as received data will be handled using u16 pointer cast). Depending on compilation chain, + * use of specific alignment compilation directives or pragmas might be required + * to ensure proper alignment for pData. +#endif + * @param huart UART handle. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. + * @param Timeout Timeout duration. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint8_t *pdata8bits; + uint16_t *pdata16bits; + uint16_t uhMask; + uint32_t tickstart; + + /* Check that a Rx process is not already ongoing */ + if (huart->RxState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + +#if defined(CORE_CM0PLUS) + /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter + should be aligned on a u16 frontier, as data to be received from RDR will be + handled through a u16 cast. */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + if ((((uint32_t)pData) & 1U) != 0U) + { + return HAL_ERROR; + } + } + +#endif /* CORE_CM0PLUS */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->RxState = HAL_UART_STATE_BUSY_RX; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + + huart->RxXferSize = Size; + huart->RxXferCount = Size; + + /* Computation of UART mask to apply to RDR register */ + UART_MASK_COMPUTATION(huart); + uhMask = huart->Mask; + + /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + pdata8bits = NULL; + pdata16bits = (uint16_t *) pData; + } + else + { + pdata8bits = pData; + pdata16bits = NULL; + } + + /* as long as data have to be received */ + while (huart->RxXferCount > 0U) + { + if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK) + { + huart->RxState = HAL_UART_STATE_READY; + + return HAL_TIMEOUT; + } + if (pdata8bits == NULL) + { + *pdata16bits = (uint16_t)(huart->Instance->RDR & uhMask); + pdata16bits++; + } + else + { + *pdata8bits = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask); + pdata8bits++; + } + if (huart->RxState == HAL_UART_STATE_BUSY_RX) + { + huart->RxXferCount--; + } + else + { + /* Process was aborted during the reception */ + return HAL_ERROR; + } + } + + /* At end of Rx process, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Send an amount of data in interrupt mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data is handled as a set of u16. In this case, Size must indicate the number + * of u16 provided through pData. +#if defined(CORE_CM0PLUS) + * @note Dual core specific: there is no support for unaligned accesses on the Cortex-M0+ processor. + * When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits) + * (as sent data will be handled using u16 pointer cast). Depending on compilation chain, + * use of specific alignment compilation directives or pragmas might be required + * to ensure proper alignment for pData. +#endif + * @param huart UART handle. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be sent. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size) +{ + /* Check that a Tx process is not already ongoing */ + if (huart->gState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + +#if defined(CORE_CM0PLUS) + /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter + should be aligned on a u16 frontier, as data to be filled into TDR will be + handled through a u16 cast. */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + if ((((uint32_t)pData) & 1U) != 0U) + { + return HAL_ERROR; + } + } + +#endif /* CORE_CM0PLUS */ + huart->pTxBuffPtr = pData; + huart->TxXferSize = Size; + huart->TxXferCount = Size; + huart->TxISR = NULL; + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->gState = HAL_UART_STATE_BUSY_TX; + + /* Configure Tx interrupt processing */ + if (huart->FifoMode == UART_FIFOMODE_ENABLE) + { + /* Set the Tx ISR function pointer according to the data word length */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + huart->TxISR = UART_TxISR_16BIT_FIFOEN; + } + else + { + huart->TxISR = UART_TxISR_8BIT_FIFOEN; + } + + /* Enable the TX FIFO threshold interrupt */ + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); + } + else + { + /* Set the Tx ISR function pointer according to the data word length */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + huart->TxISR = UART_TxISR_16BIT; + } + else + { + huart->TxISR = UART_TxISR_8BIT; + } + + /* Enable the Transmit Data Register Empty interrupt */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in interrupt mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of u16. In this case, Size must indicate the number + * of u16 available through pData. +#if defined(CORE_CM0PLUS) + * @note Dual core specific: there is no support for unaligned accesses on the Cortex-M0+ processor. + * When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * address of user data buffer for storing data to be received, should be aligned on a half word frontier + * (16 bits) (as received data will be handled using u16 pointer cast). Depending on compilation chain, + * use of specific alignment compilation directives or pragmas might be required + * to ensure proper alignment for pData. +#endif + * @param huart UART handle. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + /* Check that a Rx process is not already ongoing */ + if (huart->RxState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + +#if defined(CORE_CM0PLUS) + /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter + should be aligned on a u16 frontier, as data to be received from RDR will be + handled through a u16 cast. */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + if ((((uint32_t)pData) & 1U) != 0U) + { + return HAL_ERROR; + } + } + +#endif /* CORE_CM0PLUS */ + /* Set Reception type to Standard reception */ + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + if (!(IS_LPUART_INSTANCE(huart->Instance))) + { + /* Check that USART RTOEN bit is set */ + if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) + { + /* Enable the UART Receiver Timeout Interrupt */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RTOIE); + } + } + + return (UART_Start_Receive_IT(huart, pData, Size)); + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Send an amount of data in DMA mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data is handled as a set of u16. In this case, Size must indicate the number + * of u16 provided through pData. +#if defined(CORE_CM0PLUS) + * @note Dual core specific: there is no support for unaligned accesses on the Cortex-M0+ processor. + * When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits) + * (as sent data will be handled by DMA from halfword frontier). Depending on compilation chain, + * use of specific alignment compilation directives or pragmas might be required + * to ensure proper alignment for pData. +#endif + * @param huart UART handle. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be sent. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size) +{ + /* Check that a Tx process is not already ongoing */ + if (huart->gState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + +#if defined(CORE_CM0PLUS) + /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter + should be aligned on a u16 frontier, as data copy into TDR will be + handled by DMA from a u16 frontier. */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + if ((((uint32_t)pData) & 1U) != 0U) + { + return HAL_ERROR; + } + } + +#endif /* CORE_CM0PLUS */ + huart->pTxBuffPtr = pData; + huart->TxXferSize = Size; + huart->TxXferCount = Size; + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->gState = HAL_UART_STATE_BUSY_TX; + + if (huart->hdmatx != NULL) + { + /* Set the UART DMA transfer complete callback */ + huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt; + + /* Set the UART DMA Half transfer complete callback */ + huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt; + + /* Set the DMA error callback */ + huart->hdmatx->XferErrorCallback = UART_DMAError; + + /* Set the DMA abort callback */ + huart->hdmatx->XferAbortCallback = NULL; + + /* Enable the UART transmit DMA channel */ + if (HAL_DMA_Start_IT(huart->hdmatx, (uint32_t)huart->pTxBuffPtr, (uint32_t)&huart->Instance->TDR, Size) != HAL_OK) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + /* Restore huart->gState to ready */ + huart->gState = HAL_UART_STATE_READY; + + return HAL_ERROR; + } + } + /* Clear the TC flag in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF); + + /* Enable the DMA transfer for transmit request by setting the DMAT bit + in the UART CR3 register */ + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in DMA mode. + * @note When the UART parity is enabled (PCE = 1), the received data contain + * the parity bit (MSB position). + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of u16. In this case, Size must indicate the number + * of u16 available through pData. +#if defined(CORE_CM0PLUS) + * @note Dual core specific: there is no support for unaligned accesses on the Cortex-M0+ processor. + * When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * address of user data buffer for storing data to be received, should be aligned on a half word frontier + * (16 bits) (as received data will be handled by DMA from halfword frontier). Depending on compilation chain, + * use of specific alignment compilation directives or pragmas might be required + * to ensure proper alignment for pData. +#endif + * @param huart UART handle. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + /* Check that a Rx process is not already ongoing */ + if (huart->RxState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + +#if defined(CORE_CM0PLUS) + /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter + should be aligned on a u16 frontier, as data copy from RDR will be + handled by DMA from a u16 frontier. */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + if ((((uint32_t)pData) & 1U) != 0U) + { + return HAL_ERROR; + } + } + +#endif /* CORE_CM0PLUS */ + /* Set Reception type to Standard reception */ + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + if (!(IS_LPUART_INSTANCE(huart->Instance))) + { + /* Check that USART RTOEN bit is set */ + if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) + { + /* Enable the UART Receiver Timeout Interrupt */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RTOIE); + } + } + + return (UART_Start_Receive_DMA(huart, pData, Size)); + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Pause the DMA Transfer. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart) +{ + const HAL_UART_StateTypeDef gstate = huart->gState; + const HAL_UART_StateTypeDef rxstate = huart->RxState; + + if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) && + (gstate == HAL_UART_STATE_BUSY_TX)) + { + /* Disable the UART DMA Tx request */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + } + if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) && + (rxstate == HAL_UART_STATE_BUSY_RX)) + { + /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Disable the UART DMA Rx request */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + } + + return HAL_OK; +} + +/** + * @brief Resume the DMA Transfer. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart) +{ + if (huart->gState == HAL_UART_STATE_BUSY_TX) + { + /* Enable the UART DMA Tx request */ + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); + } + if (huart->RxState == HAL_UART_STATE_BUSY_RX) + { + /* Clear the Overrun flag before resuming the Rx transfer */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); + + /* Re-enable PE and ERR (Frame error, noise error, overrun error) interrupts */ + if (huart->Init.Parity != UART_PARITY_NONE) + { + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); + } + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Enable the UART DMA Rx request */ + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); + } + + return HAL_OK; +} + +/** + * @brief Stop the DMA Transfer. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart) +{ + /* The Lock is not implemented on this API to allow the user application + to call the HAL UART API under callbacks HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback() / + HAL_UART_TxHalfCpltCallback / HAL_UART_RxHalfCpltCallback: + indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete + interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of + the stream and the corresponding call back is executed. */ + + const HAL_UART_StateTypeDef gstate = huart->gState; + const HAL_UART_StateTypeDef rxstate = huart->RxState; + + /* Stop UART DMA Tx request if ongoing */ + if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) && + (gstate == HAL_UART_STATE_BUSY_TX)) + { + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + + /* Abort the UART DMA Tx channel */ + if (huart->hdmatx != NULL) + { + if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK) + { + if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + + UART_EndTxTransfer(huart); + } + + /* Stop UART DMA Rx request if ongoing */ + if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) && + (rxstate == HAL_UART_STATE_BUSY_RX)) + { + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* Abort the UART DMA Rx channel */ + if (huart->hdmarx != NULL) + { + if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK) + { + if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + + UART_EndRxTransfer(huart); + } + + return HAL_OK; +} + +/** + * @brief Abort ongoing transfers (blocking mode). + * @param huart UART handle. + * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable UART Interrupts (Tx and Rx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) + * - Set handle State to READY + * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart) +{ + /* Disable TXE, TC, RXNE, PE, RXFT, TXFT and ERR (Frame error, noise error, overrun error) interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | + USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE); + + /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); + } + + /* Abort the UART DMA Tx channel if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) + { + /* Disable the UART DMA Tx request if enabled */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + + /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */ + if (huart->hdmatx != NULL) + { + /* Set the UART DMA Abort callback to Null. + No call back execution at end of DMA abort procedure */ + huart->hdmatx->XferAbortCallback = NULL; + + if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK) + { + if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + } + + /* Abort the UART DMA Rx channel if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + /* Disable the UART DMA Rx request if enabled */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */ + if (huart->hdmarx != NULL) + { + /* Set the UART DMA Abort callback to Null. + No call back execution at end of DMA abort procedure */ + huart->hdmarx->XferAbortCallback = NULL; + + if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK) + { + if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + } + + /* Clear the Error flags in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); + + /* Flush the whole TX FIFO (if needed) */ + if (huart->FifoMode == UART_FIFOMODE_ENABLE) + { + __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST); + } + + /* Discard the received data */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + + /* Restore huart->gState and huart->RxState to Ready */ + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + huart->ErrorCode = HAL_UART_ERROR_NONE; + + return HAL_OK; +} + +/** + * @brief Abort ongoing Transmit transfer (blocking mode). + * @param huart UART handle. + * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable UART Interrupts (Tx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) + * - Set handle State to READY + * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart) +{ + /* Disable TCIE, TXEIE and TXFTIE interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TCIE | USART_CR1_TXEIE_TXFNFIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); + + /* Abort the UART DMA Tx channel if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) + { + /* Disable the UART DMA Tx request if enabled */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + + /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */ + if (huart->hdmatx != NULL) + { + /* Set the UART DMA Abort callback to Null. + No call back execution at end of DMA abort procedure */ + huart->hdmatx->XferAbortCallback = NULL; + + if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK) + { + if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + } + + /* Flush the whole TX FIFO (if needed) */ + if (huart->FifoMode == UART_FIFOMODE_ENABLE) + { + __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST); + } + + /* Restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + + return HAL_OK; +} + +/** + * @brief Abort ongoing Receive transfer (blocking mode). + * @param huart UART handle. + * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable UART Interrupts (Rx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) + * - Set handle State to READY + * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart) +{ + /* Disable PEIE, EIE, RXNEIE and RXFTIE interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE); + + /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); + } + + /* Abort the UART DMA Rx channel if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + /* Disable the UART DMA Rx request if enabled */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */ + if (huart->hdmarx != NULL) + { + /* Set the UART DMA Abort callback to Null. + No call back execution at end of DMA abort procedure */ + huart->hdmarx->XferAbortCallback = NULL; + + if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK) + { + if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + } + + /* Clear the Error flags in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); + + /* Discard the received data */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + + /* Restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + return HAL_OK; +} + +/** + * @brief Abort ongoing transfers (Interrupt mode). + * @param huart UART handle. + * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable UART Interrupts (Tx and Rx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) + * - Set handle State to READY + * - At abort completion, call user abort complete callback + * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be + * considered as completed only when user abort complete callback is executed (not when exiting function). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart) +{ + uint32_t abortcplt = 1U; + + /* Disable interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_TCIE | USART_CR1_RXNEIE_RXFNEIE | + USART_CR1_TXEIE_TXFNFIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE)); + + /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); + } + + /* If DMA Tx and/or DMA Rx Handles are associated to UART Handle, DMA Abort complete callbacks should be initialised + before any call to DMA Abort functions */ + /* DMA Tx Handle is valid */ + if (huart->hdmatx != NULL) + { + /* Set DMA Abort Complete callback if UART DMA Tx request if enabled. + Otherwise, set it to NULL */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) + { + huart->hdmatx->XferAbortCallback = UART_DMATxAbortCallback; + } + else + { + huart->hdmatx->XferAbortCallback = NULL; + } + } + /* DMA Rx Handle is valid */ + if (huart->hdmarx != NULL) + { + /* Set DMA Abort Complete callback if UART DMA Rx request if enabled. + Otherwise, set it to NULL */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + huart->hdmarx->XferAbortCallback = UART_DMARxAbortCallback; + } + else + { + huart->hdmarx->XferAbortCallback = NULL; + } + } + + /* Abort the UART DMA Tx channel if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) + { + /* Disable DMA Tx at UART level */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + + /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */ + if (huart->hdmatx != NULL) + { + /* UART Tx DMA Abort callback has already been initialised : + will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK) + { + huart->hdmatx->XferAbortCallback = NULL; + } + else + { + abortcplt = 0U; + } + } + } + + /* Abort the UART DMA Rx channel if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + /* Disable the UART DMA Rx request if enabled */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */ + if (huart->hdmarx != NULL) + { + /* UART Rx DMA Abort callback has already been initialised : + will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) + { + huart->hdmarx->XferAbortCallback = NULL; + abortcplt = 1U; + } + else + { + abortcplt = 0U; + } + } + } + + /* if no DMA abort complete callback execution is required => call user Abort Complete callback */ + if (abortcplt == 1U) + { + /* Clear ISR function pointers */ + huart->RxISR = NULL; + huart->TxISR = NULL; + + /* Reset errorCode */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + + /* Clear the Error flags in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); + + /* Flush the whole TX FIFO (if needed) */ + if (huart->FifoMode == UART_FIFOMODE_ENABLE) + { + __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST); + } + + /* Discard the received data */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + + /* Restore huart->gState and huart->RxState to Ready */ + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort complete callback */ + huart->AbortCpltCallback(huart); +#else + /* Call legacy weak Abort complete callback */ + HAL_UART_AbortCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + + return HAL_OK; +} + +/** + * @brief Abort ongoing Transmit transfer (Interrupt mode). + * @param huart UART handle. + * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable UART Interrupts (Tx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) + * - Set handle State to READY + * - At abort completion, call user abort complete callback + * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be + * considered as completed only when user abort complete callback is executed (not when exiting function). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart) +{ + /* Disable interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TCIE | USART_CR1_TXEIE_TXFNFIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); + + /* Abort the UART DMA Tx channel if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) + { + /* Disable the UART DMA Tx request if enabled */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + + /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */ + if (huart->hdmatx != NULL) + { + /* Set the UART DMA Abort callback : + will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ + huart->hdmatx->XferAbortCallback = UART_DMATxOnlyAbortCallback; + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK) + { + /* Call Directly huart->hdmatx->XferAbortCallback function in case of error */ + huart->hdmatx->XferAbortCallback(huart->hdmatx); + } + } + else + { + + /* Clear TxISR function pointers */ + huart->TxISR = NULL; + + /* Restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Transmit Complete Callback */ + huart->AbortTransmitCpltCallback(huart); +#else + /* Call legacy weak Abort Transmit Complete Callback */ + HAL_UART_AbortTransmitCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + } + else + { + /* Clear TxISR function pointers */ + huart->TxISR = NULL; + + /* Flush the whole TX FIFO (if needed) */ + if (huart->FifoMode == UART_FIFOMODE_ENABLE) + { + __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST); + } + + /* Restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Transmit Complete Callback */ + huart->AbortTransmitCpltCallback(huart); +#else + /* Call legacy weak Abort Transmit Complete Callback */ + HAL_UART_AbortTransmitCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + + return HAL_OK; +} + +/** + * @brief Abort ongoing Receive transfer (Interrupt mode). + * @param huart UART handle. + * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable UART Interrupts (Rx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) + * - Set handle State to READY + * - At abort completion, call user abort complete callback + * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be + * considered as completed only when user abort complete callback is executed (not when exiting function). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart) +{ + /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); + + /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); + } + + /* Abort the UART DMA Rx channel if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + /* Disable the UART DMA Rx request if enabled */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */ + if (huart->hdmarx != NULL) + { + /* Set the UART DMA Abort callback : + will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ + huart->hdmarx->XferAbortCallback = UART_DMARxOnlyAbortCallback; + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) + { + /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */ + huart->hdmarx->XferAbortCallback(huart->hdmarx); + } + } + else + { + /* Clear RxISR function pointer */ + huart->pRxBuffPtr = NULL; + + /* Clear the Error flags in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); + + /* Discard the received data */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + + /* Restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Receive Complete Callback */ + huart->AbortReceiveCpltCallback(huart); +#else + /* Call legacy weak Abort Receive Complete Callback */ + HAL_UART_AbortReceiveCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + } + else + { + /* Clear RxISR function pointer */ + huart->pRxBuffPtr = NULL; + + /* Clear the Error flags in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); + + /* Restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Receive Complete Callback */ + huart->AbortReceiveCpltCallback(huart); +#else + /* Call legacy weak Abort Receive Complete Callback */ + HAL_UART_AbortReceiveCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + + return HAL_OK; +} + +/** + * @brief Handle UART interrupt request. + * @param huart UART handle. + * @retval None + */ +void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) +{ + uint32_t isrflags = READ_REG(huart->Instance->ISR); + uint32_t cr1its = READ_REG(huart->Instance->CR1); + uint32_t cr3its = READ_REG(huart->Instance->CR3); + + uint32_t errorflags; + uint32_t errorcode; + + /* If no error occurs */ + errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF)); + if (errorflags == 0U) + { + /* UART in mode Receiver ---------------------------------------------------*/ + if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U) + && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) + || ((cr3its & USART_CR3_RXFTIE) != 0U))) + { + if (huart->RxISR != NULL) + { + huart->RxISR(huart); + } + return; + } + } + + /* If some errors occur */ + if ((errorflags != 0U) + && ((((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U) + || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE)) != 0U)))) + { + /* UART parity error interrupt occurred -------------------------------------*/ + if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF); + + huart->ErrorCode |= HAL_UART_ERROR_PE; + } + + /* UART frame error interrupt occurred --------------------------------------*/ + if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF); + + huart->ErrorCode |= HAL_UART_ERROR_FE; + } + + /* UART noise error interrupt occurred --------------------------------------*/ + if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF); + + huart->ErrorCode |= HAL_UART_ERROR_NE; + } + + /* UART Over-Run interrupt occurred -----------------------------------------*/ + if (((isrflags & USART_ISR_ORE) != 0U) + && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) || + ((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U))) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); + + huart->ErrorCode |= HAL_UART_ERROR_ORE; + } + + /* UART Receiver Timeout interrupt occurred ---------------------------------*/ + if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF); + + huart->ErrorCode |= HAL_UART_ERROR_RTO; + } + + /* Call UART Error Call back function if need be ----------------------------*/ + if (huart->ErrorCode != HAL_UART_ERROR_NONE) + { + /* UART in mode Receiver --------------------------------------------------*/ + if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U) + && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) + || ((cr3its & USART_CR3_RXFTIE) != 0U))) + { + if (huart->RxISR != NULL) + { + huart->RxISR(huart); + } + } + + /* If Error is to be considered as blocking : + - Receiver Timeout error in Reception + - Overrun error in Reception + - any error occurs in DMA mode reception + */ + errorcode = huart->ErrorCode; + if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) || + ((errorcode & (HAL_UART_ERROR_RTO | HAL_UART_ERROR_ORE)) != 0U)) + { + /* Blocking error : transfer is aborted + Set the UART state ready to be able to start again the process, + Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ + UART_EndRxTransfer(huart); + + /* Abort the UART DMA Rx channel if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + /* Disable the UART DMA Rx request if enabled */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* Abort the UART DMA Rx channel */ + if (huart->hdmarx != NULL) + { + /* Set the UART DMA Abort callback : + will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */ + huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError; + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) + { + /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */ + huart->hdmarx->XferAbortCallback(huart->hdmarx); + } + } + else + { + /* Call user error callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + + } + } + else + { + /* Call user error callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + } + else + { + /* Non Blocking error : transfer could go on. + Error is notified to user through user error callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + } + } + return; + + } /* End if some error occurs */ + + /* Check current reception Mode : + If Reception till IDLE event has been selected : */ + if ((huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + && ((isrflags & USART_ISR_IDLE) != 0U) + && ((cr1its & USART_ISR_IDLE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + + /* Check if DMA mode is enabled in UART */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + /* DMA mode enabled */ + /* Check received length : If all expected data are received, do nothing, + (DMA cplt callback will be called). + Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ + uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx); + if ((nb_remaining_rx_data > 0U) + && (nb_remaining_rx_data < huart->RxXferSize)) + { + /* Reception is not complete */ + huart->RxXferCount = nb_remaining_rx_data; + + /* In Normal mode, end DMA xfer and HAL UART Rx process*/ + if (HAL_IS_BIT_CLR(huart->hdmarx->Instance->CCR, DMA_CCR_CIRC)) + { + /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Disable the DMA transfer for the receiver request by resetting the DMAR bit + in the UART CR3 register */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* At end of Rx process, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + + /* Last bytes received, so no need as the abort is immediate */ + (void)HAL_DMA_Abort(huart->hdmarx); + } + + /* Initialize type of RxEvent that correspond to RxEvent callback execution; + In this case, Rx Event type is Idle Event */ + huart->RxEventType = HAL_UART_RXEVENT_IDLE; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + else + { + /* If DMA is in Circular mode, Idle event is to be reported to user + even if occurring after a Transfer Complete event from DMA */ + if (nb_remaining_rx_data == huart->RxXferSize) + { + if (HAL_IS_BIT_SET(huart->hdmarx->Instance->CCR, DMA_CCR_CIRC)) + { + /* Initialize type of RxEvent that correspond to RxEvent callback execution; + In this case, Rx Event type is Idle Event */ + huart->RxEventType = HAL_UART_RXEVENT_IDLE; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, huart->RxXferSize); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + } + } + return; + } + else + { + /* DMA mode not enabled */ + /* Check received length : If all expected data are received, do nothing. + Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ + uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount; + if ((huart->RxXferCount > 0U) + && (nb_rx_data > 0U)) + { + /* Disable the UART Parity Error Interrupt and RXNE interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); + + /* Disable the UART Error Interrupt:(Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); + + /* Rx process is completed, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* Clear RxISR function pointer */ + huart->RxISR = NULL; + + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + + /* Initialize type of RxEvent that correspond to RxEvent callback execution; + In this case, Rx Event type is Idle Event */ + huart->RxEventType = HAL_UART_RXEVENT_IDLE; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx complete callback*/ + huart->RxEventCallback(huart, nb_rx_data); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, nb_rx_data); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + return; + } + } + + /* UART wakeup from Stop mode interrupt occurred ---------------------------*/ + if (((isrflags & USART_ISR_WUF) != 0U) && ((cr3its & USART_CR3_WUFIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_WUF); + + /* UART Rx state is not reset as a reception process might be ongoing. + If UART handle state fields need to be reset to READY, this could be done in Wakeup callback */ + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Wakeup Callback */ + huart->WakeupCallback(huart); +#else + /* Call legacy weak Wakeup Callback */ + HAL_UARTEx_WakeupCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + return; + } + + /* UART in mode Transmitter ------------------------------------------------*/ + if (((isrflags & USART_ISR_TXE_TXFNF) != 0U) + && (((cr1its & USART_CR1_TXEIE_TXFNFIE) != 0U) + || ((cr3its & USART_CR3_TXFTIE) != 0U))) + { + if (huart->TxISR != NULL) + { + huart->TxISR(huart); + } + return; + } + + /* UART in mode Transmitter (transmission end) -----------------------------*/ + if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U)) + { + UART_EndTransmit_IT(huart); + return; + } + + /* UART TX Fifo Empty occurred ----------------------------------------------*/ + if (((isrflags & USART_ISR_TXFE) != 0U) && ((cr1its & USART_CR1_TXFEIE) != 0U)) + { +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Tx Fifo Empty Callback */ + huart->TxFifoEmptyCallback(huart); +#else + /* Call legacy weak Tx Fifo Empty Callback */ + HAL_UARTEx_TxFifoEmptyCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + return; + } + + /* UART RX Fifo Full occurred ----------------------------------------------*/ + if (((isrflags & USART_ISR_RXFF) != 0U) && ((cr1its & USART_CR1_RXFFIE) != 0U)) + { +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Rx Fifo Full Callback */ + huart->RxFifoFullCallback(huart); +#else + /* Call legacy weak Rx Fifo Full Callback */ + HAL_UARTEx_RxFifoFullCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + return; + } +} + +/** + * @brief Tx Transfer completed callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_TxCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief Tx Half Transfer completed callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_UART_TxHalfCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief Rx Transfer completed callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_RxCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief Rx Half Transfer completed callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_UART_RxHalfCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief UART error callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_ErrorCallback can be implemented in the user file. + */ +} + +/** + * @brief UART Abort Complete callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_AbortCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief UART Abort Complete callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_AbortTransmitCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief UART Abort Receive Complete callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_AbortReceiveCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief Reception Event Callback (Rx event notification called after use of advanced reception service). + * @param huart UART handle + * @param Size Number of data available in application reception buffer (indicates a position in + * reception buffer until which, data are available) + * @retval None + */ +__weak void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + UNUSED(Size); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UARTEx_RxEventCallback can be implemented in the user file. + */ +} + +/** + * @} + */ + +/** @defgroup UART_Exported_Functions_Group3 Peripheral Control functions + * @brief UART control functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the UART. + (+) HAL_UART_ReceiverTimeout_Config() API allows to configure the receiver timeout value on the fly + (+) HAL_UART_EnableReceiverTimeout() API enables the receiver timeout feature + (+) HAL_UART_DisableReceiverTimeout() API disables the receiver timeout feature + (+) HAL_MultiProcessor_EnableMuteMode() API enables mute mode + (+) HAL_MultiProcessor_DisableMuteMode() API disables mute mode + (+) HAL_MultiProcessor_EnterMuteMode() API enters mute mode + (+) UART_SetConfig() API configures the UART peripheral + (+) UART_AdvFeatureConfig() API optionally configures the UART advanced features + (+) UART_CheckIdleState() API ensures that TEACK and/or REACK are set after initialization + (+) HAL_HalfDuplex_EnableTransmitter() API disables receiver and enables transmitter + (+) HAL_HalfDuplex_EnableReceiver() API disables transmitter and enables receiver + (+) HAL_LIN_SendBreak() API transmits the break characters +@endverbatim + * @{ + */ + +/** + * @brief Update on the fly the receiver timeout value in RTOR register. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @param TimeoutValue receiver timeout value in number of baud blocks. The timeout + * value must be less or equal to 0x0FFFFFFFF. + * @retval None + */ +void HAL_UART_ReceiverTimeout_Config(UART_HandleTypeDef *huart, uint32_t TimeoutValue) +{ + if (!(IS_LPUART_INSTANCE(huart->Instance))) + { + assert_param(IS_UART_RECEIVER_TIMEOUT_VALUE(TimeoutValue)); + MODIFY_REG(huart->Instance->RTOR, USART_RTOR_RTO, TimeoutValue); + } +} + +/** + * @brief Enable the UART receiver timeout feature. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_EnableReceiverTimeout(UART_HandleTypeDef *huart) +{ + if (!(IS_LPUART_INSTANCE(huart->Instance))) + { + if (huart->gState == HAL_UART_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Set the USART RTOEN bit */ + SET_BIT(huart->Instance->CR2, USART_CR2_RTOEN); + + huart->gState = HAL_UART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Disable the UART receiver timeout feature. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_DisableReceiverTimeout(UART_HandleTypeDef *huart) +{ + if (!(IS_LPUART_INSTANCE(huart->Instance))) + { + if (huart->gState == HAL_UART_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Clear the USART RTOEN bit */ + CLEAR_BIT(huart->Instance->CR2, USART_CR2_RTOEN); + + huart->gState = HAL_UART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Enable UART in mute mode (does not mean UART enters mute mode; + * to enter mute mode, HAL_MultiProcessor_EnterMuteMode() API must be called). + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart) +{ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Enable USART mute mode by setting the MME bit in the CR1 register */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_MME); + + huart->gState = HAL_UART_STATE_READY; + + return (UART_CheckIdleState(huart)); +} + +/** + * @brief Disable UART mute mode (does not mean the UART actually exits mute mode + * as it may not have been in mute mode at this very moment). + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart) +{ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Disable USART mute mode by clearing the MME bit in the CR1 register */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_MME); + + huart->gState = HAL_UART_STATE_READY; + + return (UART_CheckIdleState(huart)); +} + +/** + * @brief Enter UART mute mode (means UART actually enters mute mode). + * @note To exit from mute mode, HAL_MultiProcessor_DisableMuteMode() API must be called. + * @param huart UART handle. + * @retval None + */ +void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart) +{ + __HAL_UART_SEND_REQ(huart, UART_MUTE_MODE_REQUEST); +} + +/** + * @brief Enable the UART transmitter and disable the UART receiver. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart) +{ + __HAL_LOCK(huart); + huart->gState = HAL_UART_STATE_BUSY; + + /* Clear TE and RE bits */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE)); + + /* Enable the USART's transmit interface by setting the TE bit in the USART CR1 register */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TE); + + huart->gState = HAL_UART_STATE_READY; + + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Enable the UART receiver and disable the UART transmitter. + * @param huart UART handle. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart) +{ + __HAL_LOCK(huart); + huart->gState = HAL_UART_STATE_BUSY; + + /* Clear TE and RE bits */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE)); + + /* Enable the USART's receive interface by setting the RE bit in the USART CR1 register */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RE); + + huart->gState = HAL_UART_STATE_READY; + + __HAL_UNLOCK(huart); + + return HAL_OK; +} + + +/** + * @brief Transmit break characters. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart) +{ + /* Check the parameters */ + assert_param(IS_UART_LIN_INSTANCE(huart->Instance)); + + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Send break characters */ + __HAL_UART_SEND_REQ(huart, UART_SENDBREAK_REQUEST); + + huart->gState = HAL_UART_STATE_READY; + + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup UART_Exported_Functions_Group4 Peripheral State and Error functions + * @brief UART Peripheral State functions + * +@verbatim + ============================================================================== + ##### Peripheral State and Error functions ##### + ============================================================================== + [..] + This subsection provides functions allowing to : + (+) Return the UART handle state. + (+) Return the UART handle error code + +@endverbatim + * @{ + */ + +/** + * @brief Return the UART handle state. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART. + * @retval HAL state + */ +HAL_UART_StateTypeDef HAL_UART_GetState(const UART_HandleTypeDef *huart) +{ + uint32_t temp1; + uint32_t temp2; + temp1 = huart->gState; + temp2 = huart->RxState; + + return (HAL_UART_StateTypeDef)(temp1 | temp2); +} + +/** + * @brief Return the UART handle error code. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART. + * @retval UART Error Code + */ +uint32_t HAL_UART_GetError(const UART_HandleTypeDef *huart) +{ + return huart->ErrorCode; +} +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup UART_Private_Functions UART Private Functions + * @{ + */ + +/** + * @brief Initialize the callbacks to their default values. + * @param huart UART handle. + * @retval none + */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart) +{ + /* Init the UART Callback settings */ + huart->TxHalfCpltCallback = HAL_UART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ + huart->TxCpltCallback = HAL_UART_TxCpltCallback; /* Legacy weak TxCpltCallback */ + huart->RxHalfCpltCallback = HAL_UART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ + huart->RxCpltCallback = HAL_UART_RxCpltCallback; /* Legacy weak RxCpltCallback */ + huart->ErrorCallback = HAL_UART_ErrorCallback; /* Legacy weak ErrorCallback */ + huart->AbortCpltCallback = HAL_UART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + huart->AbortTransmitCpltCallback = HAL_UART_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */ + huart->AbortReceiveCpltCallback = HAL_UART_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */ + huart->WakeupCallback = HAL_UARTEx_WakeupCallback; /* Legacy weak WakeupCallback */ + huart->RxFifoFullCallback = HAL_UARTEx_RxFifoFullCallback; /* Legacy weak RxFifoFullCallback */ + huart->TxFifoEmptyCallback = HAL_UARTEx_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */ + huart->RxEventCallback = HAL_UARTEx_RxEventCallback; /* Legacy weak RxEventCallback */ + +} +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + +/** + * @brief Configure the UART peripheral. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) +{ + uint32_t tmpreg; + uint16_t brrtemp; + UART_ClockSourceTypeDef clocksource; + uint32_t usartdiv; + HAL_StatusTypeDef ret = HAL_OK; + uint32_t lpuart_ker_ck_pres; + uint32_t pclk; + + /* Check the parameters */ + assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate)); + assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength)); + if (UART_INSTANCE_LOWPOWER(huart)) + { + assert_param(IS_LPUART_STOPBITS(huart->Init.StopBits)); + } + else + { + assert_param(IS_UART_STOPBITS(huart->Init.StopBits)); + assert_param(IS_UART_ONE_BIT_SAMPLE(huart->Init.OneBitSampling)); + } + + assert_param(IS_UART_PARITY(huart->Init.Parity)); + assert_param(IS_UART_MODE(huart->Init.Mode)); + assert_param(IS_UART_HARDWARE_FLOW_CONTROL(huart->Init.HwFlowCtl)); + assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling)); + assert_param(IS_UART_PRESCALER(huart->Init.ClockPrescaler)); + + /*-------------------------- USART CR1 Configuration -----------------------*/ + /* Clear M, PCE, PS, TE, RE and OVER8 bits and configure + * the UART Word Length, Parity, Mode and oversampling: + * set the M bits according to huart->Init.WordLength value + * set PCE and PS bits according to huart->Init.Parity value + * set TE and RE bits according to huart->Init.Mode value + * set OVER8 bit according to huart->Init.OverSampling value */ + tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ; + MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg); + + /*-------------------------- USART CR2 Configuration -----------------------*/ + /* Configure the UART Stop Bits: Set STOP[13:12] bits according + * to huart->Init.StopBits value */ + MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); + + /*-------------------------- USART CR3 Configuration -----------------------*/ + /* Configure + * - UART HardWare Flow Control: set CTSE and RTSE bits according + * to huart->Init.HwFlowCtl value + * - one-bit sampling method versus three samples' majority rule according + * to huart->Init.OneBitSampling (not applicable to LPUART) */ + tmpreg = (uint32_t)huart->Init.HwFlowCtl; + + if (!(UART_INSTANCE_LOWPOWER(huart))) + { + tmpreg |= huart->Init.OneBitSampling; + } + MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg); + + /*-------------------------- USART PRESC Configuration -----------------------*/ + /* Configure + * - UART Clock Prescaler : set PRESCALER according to huart->Init.ClockPrescaler value */ + MODIFY_REG(huart->Instance->PRESC, USART_PRESC_PRESCALER, huart->Init.ClockPrescaler); + + /*-------------------------- USART BRR Configuration -----------------------*/ + UART_GETCLOCKSOURCE(huart, clocksource); + + /* Check LPUART instance */ + if (UART_INSTANCE_LOWPOWER(huart)) + { + /* Retrieve frequency clock */ + switch (clocksource) + { + case UART_CLOCKSOURCE_PCLK1: + pclk = HAL_RCC_GetPCLK1Freq(); + break; + case UART_CLOCKSOURCE_HSI: + pclk = (uint32_t) HSI_VALUE; + break; + case UART_CLOCKSOURCE_SYSCLK: + pclk = HAL_RCC_GetSysClockFreq(); + break; + case UART_CLOCKSOURCE_LSE: + pclk = (uint32_t) LSE_VALUE; + break; + default: + pclk = 0U; + ret = HAL_ERROR; + break; + } + + /* If proper clock source reported */ + if (pclk != 0U) + { + /* Compute clock after Prescaler */ + lpuart_ker_ck_pres = (pclk / UARTPrescTable[huart->Init.ClockPrescaler]); + + /* Ensure that Frequency clock is in the range [3 * baudrate, 4096 * baudrate] */ + if ((lpuart_ker_ck_pres < (3U * huart->Init.BaudRate)) || + (lpuart_ker_ck_pres > (4096U * huart->Init.BaudRate))) + { + ret = HAL_ERROR; + } + else + { + /* Check computed UsartDiv value is in allocated range + (it is forbidden to write values lower than 0x300 in the LPUART_BRR register) */ + usartdiv = (uint32_t)(UART_DIV_LPUART(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); + if ((usartdiv >= LPUART_BRR_MIN) && (usartdiv <= LPUART_BRR_MAX)) + { + huart->Instance->BRR = usartdiv; + } + else + { + ret = HAL_ERROR; + } + } /* if ( (lpuart_ker_ck_pres < (3 * huart->Init.BaudRate) ) || + (lpuart_ker_ck_pres > (4096 * huart->Init.BaudRate) )) */ + } /* if (pclk != 0) */ + } + /* Check UART Over Sampling to set Baud Rate Register */ + else if (huart->Init.OverSampling == UART_OVERSAMPLING_8) + { + switch (clocksource) + { + case UART_CLOCKSOURCE_PCLK1: + pclk = HAL_RCC_GetPCLK1Freq(); + break; + case UART_CLOCKSOURCE_PCLK2: + pclk = HAL_RCC_GetPCLK2Freq(); + break; + case UART_CLOCKSOURCE_HSI: + pclk = (uint32_t) HSI_VALUE; + break; + case UART_CLOCKSOURCE_SYSCLK: + pclk = HAL_RCC_GetSysClockFreq(); + break; + case UART_CLOCKSOURCE_LSE: + pclk = (uint32_t) LSE_VALUE; + break; + default: + pclk = 0U; + ret = HAL_ERROR; + break; + } + + /* USARTDIV must be greater than or equal to 0d16 */ + if (pclk != 0U) + { + usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); + if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) + { + brrtemp = (uint16_t)(usartdiv & 0xFFF0U); + brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); + huart->Instance->BRR = brrtemp; + } + else + { + ret = HAL_ERROR; + } + } + } + else + { + switch (clocksource) + { + case UART_CLOCKSOURCE_PCLK1: + pclk = HAL_RCC_GetPCLK1Freq(); + break; + case UART_CLOCKSOURCE_PCLK2: + pclk = HAL_RCC_GetPCLK2Freq(); + break; + case UART_CLOCKSOURCE_HSI: + pclk = (uint32_t) HSI_VALUE; + break; + case UART_CLOCKSOURCE_SYSCLK: + pclk = HAL_RCC_GetSysClockFreq(); + break; + case UART_CLOCKSOURCE_LSE: + pclk = (uint32_t) LSE_VALUE; + break; + default: + pclk = 0U; + ret = HAL_ERROR; + break; + } + + if (pclk != 0U) + { + /* USARTDIV must be greater than or equal to 0d16 */ + usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); + if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) + { + huart->Instance->BRR = (uint16_t)usartdiv; + } + else + { + ret = HAL_ERROR; + } + } + } + + /* Initialize the number of data to process during RX/TX ISR execution */ + huart->NbTxDataToProcess = 1; + huart->NbRxDataToProcess = 1; + + /* Clear ISR function pointers */ + huart->RxISR = NULL; + huart->TxISR = NULL; + + return ret; +} + +/** + * @brief Configure the UART peripheral advanced features. + * @param huart UART handle. + * @retval None + */ +void UART_AdvFeatureConfig(UART_HandleTypeDef *huart) +{ + /* Check whether the set of advanced features to configure is properly set */ + assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit)); + + /* if required, configure RX/TX pins swap */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT)) + { + assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap); + } + + /* if required, configure TX pin active level inversion */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT)) + { + assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert); + } + + /* if required, configure RX pin active level inversion */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT)) + { + assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert); + } + + /* if required, configure data inversion */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT)) + { + assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert); + } + + /* if required, configure RX overrun detection disabling */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT)) + { + assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable)); + MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable); + } + + /* if required, configure DMA disabling on reception error */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT)) + { + assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError)); + MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError); + } + + /* if required, configure auto Baud rate detection scheme */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT)) + { + assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance)); + assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable); + /* set auto Baudrate detection parameters if detection is enabled */ + if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE) + { + assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode); + } + } + + /* if required, configure MSB first on communication line */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT)) + { + assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst); + } +} + +/** + * @brief Check the UART Idle State. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) +{ + uint32_t tickstart; + + /* Initialize the UART ErrorCode */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + + /* Check if the Transmitter is enabled */ + if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) + { + /* Wait until TEACK flag is set */ + if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) + { + /* Disable TXE interrupt for the interrupt process */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE)); + + huart->gState = HAL_UART_STATE_READY; + + __HAL_UNLOCK(huart); + + /* Timeout occurred */ + return HAL_TIMEOUT; + } + } + + /* Check if the Receiver is enabled */ + if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) + { + /* Wait until REACK flag is set */ + if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) + { + /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) + interrupts for the interrupt process */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + huart->RxState = HAL_UART_STATE_READY; + + __HAL_UNLOCK(huart); + + /* Timeout occurred */ + return HAL_TIMEOUT; + } + } + + /* Initialize the UART State */ + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + huart->RxEventType = HAL_UART_RXEVENT_TC; + + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief This function handles UART Communication Timeout. It waits + * until a flag is no longer in the specified status. + * @param huart UART handle. + * @param Flag Specifies the UART flag to check + * @param Status The actual Flag status (SET or RESET) + * @param Tickstart Tick start value + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, + uint32_t Tickstart, uint32_t Timeout) +{ + /* Wait until flag is set */ + while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) + { + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + { + + return HAL_TIMEOUT; + } + + if ((READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) && (Flag != UART_FLAG_TXE) && (Flag != UART_FLAG_TC)) + { + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET) + { + /* Clear Overrun Error flag*/ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); + + /* Blocking error : transfer is aborted + Set the UART state ready to be able to start again the process, + Disable Rx Interrupts if ongoing */ + UART_EndRxTransfer(huart); + + huart->ErrorCode = HAL_UART_ERROR_ORE; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_ERROR; + } + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET) + { + /* Clear Receiver Timeout flag*/ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF); + + /* Blocking error : transfer is aborted + Set the UART state ready to be able to start again the process, + Disable Rx Interrupts if ongoing */ + UART_EndRxTransfer(huart); + + huart->ErrorCode = HAL_UART_ERROR_RTO; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_TIMEOUT; + } + } + } + } + return HAL_OK; +} + +/** + * @brief Start Receive operation in interrupt mode. + * @note This function could be called by all HAL UART API providing reception in Interrupt mode. + * @note When calling this function, parameters validity is considered as already checked, + * i.e. Rx State, buffer address, ... + * UART Handle is assumed as Locked. + * @param huart UART handle. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. + * @retval HAL status + */ +HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + huart->pRxBuffPtr = pData; + huart->RxXferSize = Size; + huart->RxXferCount = Size; + huart->RxISR = NULL; + + /* Computation of UART mask to apply to RDR register */ + UART_MASK_COMPUTATION(huart); + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->RxState = HAL_UART_STATE_BUSY_RX; + + /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Configure Rx interrupt processing */ + if ((huart->FifoMode == UART_FIFOMODE_ENABLE) && (Size >= huart->NbRxDataToProcess)) + { + /* Set the Rx ISR function pointer according to the data word length */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + huart->RxISR = UART_RxISR_16BIT_FIFOEN; + } + else + { + huart->RxISR = UART_RxISR_8BIT_FIFOEN; + } + + /* Enable the UART Parity Error interrupt and RX FIFO Threshold interrupt */ + if (huart->Init.Parity != UART_PARITY_NONE) + { + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); + } + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); + } + else + { + /* Set the Rx ISR function pointer according to the data word length */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + huart->RxISR = UART_RxISR_16BIT; + } + else + { + huart->RxISR = UART_RxISR_8BIT; + } + + /* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */ + if (huart->Init.Parity != UART_PARITY_NONE) + { + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE); + } + else + { + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); + } + } + return HAL_OK; +} + +/** + * @brief Start Receive operation in DMA mode. + * @note This function could be called by all HAL UART API providing reception in DMA mode. + * @note When calling this function, parameters validity is considered as already checked, + * i.e. Rx State, buffer address, ... + * UART Handle is assumed as Locked. + * @param huart UART handle. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. + * @retval HAL status + */ +HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + huart->pRxBuffPtr = pData; + huart->RxXferSize = Size; + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->RxState = HAL_UART_STATE_BUSY_RX; + + if (huart->hdmarx != NULL) + { + /* Set the UART DMA transfer complete callback */ + huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt; + + /* Set the UART DMA Half transfer complete callback */ + huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt; + + /* Set the DMA error callback */ + huart->hdmarx->XferErrorCallback = UART_DMAError; + + /* Set the DMA abort callback */ + huart->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->RDR, (uint32_t)huart->pRxBuffPtr, Size) != HAL_OK) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + /* Restore huart->RxState to ready */ + huart->RxState = HAL_UART_STATE_READY; + + return HAL_ERROR; + } + } + + /* Enable the UART Parity Error Interrupt */ + if (huart->Init.Parity != UART_PARITY_NONE) + { + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); + } + + /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Enable the DMA transfer for the receiver request by setting the DMAR bit + in the UART CR3 register */ + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + return HAL_OK; +} + + +/** + * @brief End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion). + * @param huart UART handle. + * @retval None + */ +static void UART_EndTxTransfer(UART_HandleTypeDef *huart) +{ + /* Disable TXEIE, TCIE, TXFT interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_TXFTIE)); + + /* At end of Tx process, restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; +} + + +/** + * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion). + * @param huart UART handle. + * @retval None + */ +static void UART_EndRxTransfer(UART_HandleTypeDef *huart) +{ + /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); + + /* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + } + + /* At end of Rx process, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* Reset RxIsr function pointer */ + huart->RxISR = NULL; +} + + +/** + * @brief DMA UART transmit process complete callback. + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + + /* DMA Normal mode */ + if (HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC)) + { + /* Disable the DMA transfer for transmit request by resetting the DMAT bit + in the UART CR3 register */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + + /* Enable the UART Transmit Complete Interrupt */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); + } + /* DMA Circular mode */ + else + { +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Tx complete callback*/ + huart->TxCpltCallback(huart); +#else + /*Call legacy weak Tx complete callback*/ + HAL_UART_TxCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } +} + +/** + * @brief DMA UART transmit process half complete callback. + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Tx Half complete callback*/ + huart->TxHalfCpltCallback(huart); +#else + /*Call legacy weak Tx Half complete callback*/ + HAL_UART_TxHalfCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA UART receive process complete callback. + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + + /* DMA Normal mode */ + if (HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC)) + { + /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Disable the DMA transfer for the receiver request by resetting the DMAR bit + in the UART CR3 register */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* At end of Rx process, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + + /* If Reception till IDLE event has been selected, Disable IDLE Interrupt */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + } + } + + /* Initialize type of RxEvent that correspond to RxEvent callback execution; + In this case, Rx Event type is Transfer Complete */ + huart->RxEventType = HAL_UART_RXEVENT_TC; + + /* Check current reception Mode : + If Reception till IDLE event has been selected : use Rx Event callback */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + /* Check current nb of data still to be received on DMA side. + DMA Normal mode, remaining nb of data will be 0 + DMA Circular mode, remaining nb of data is reset to RxXferSize */ + uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(hdma); + if (nb_remaining_rx_data < huart->RxXferSize) + { + /* Update nb of remaining data */ + huart->RxXferCount = nb_remaining_rx_data; + } + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + else + { + /* In other cases : use Rx Complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx complete callback*/ + huart->RxCpltCallback(huart); +#else + /*Call legacy weak Rx complete callback*/ + HAL_UART_RxCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } +} + +/** + * @brief DMA UART receive process half complete callback. + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + + /* Initialize type of RxEvent that correspond to RxEvent callback execution; + In this case, Rx Event type is Half Transfer */ + huart->RxEventType = HAL_UART_RXEVENT_HT; + + /* Check current reception Mode : + If Reception till IDLE event has been selected : use Rx Event callback */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + huart->RxXferCount = huart->RxXferSize / 2U; + + /* Check current nb of data still to be received on DMA side. */ + uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(hdma); + if (nb_remaining_rx_data <= huart->RxXferSize) + { + /* Update nb of remaining data */ + huart->RxXferCount = nb_remaining_rx_data; + } + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + else + { + /* In other cases : use Rx Half Complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Half complete callback*/ + huart->RxHalfCpltCallback(huart); +#else + /*Call legacy weak Rx Half complete callback*/ + HAL_UART_RxHalfCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } +} + +/** + * @brief DMA UART communication error callback. + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMAError(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + + const HAL_UART_StateTypeDef gstate = huart->gState; + const HAL_UART_StateTypeDef rxstate = huart->RxState; + + /* Stop UART DMA Tx request if ongoing */ + if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) && + (gstate == HAL_UART_STATE_BUSY_TX)) + { + UART_EndTxTransfer(huart); + } + + /* Stop UART DMA Rx request if ongoing */ + if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) && + (rxstate == HAL_UART_STATE_BUSY_RX)) + { + UART_EndRxTransfer(huart); + } + + huart->ErrorCode |= HAL_UART_ERROR_DMA; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA UART communication abort callback, when initiated by HAL services on Error + * (To be called at end of DMA Abort procedure following error occurrence). + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA UART Tx communication abort callback, when initiated by user + * (To be called at end of DMA Tx Abort procedure following user abort request). + * @note When this callback is executed, User Abort complete call back is called only if no + * Abort still ongoing for Rx DMA Handle. + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + + huart->hdmatx->XferAbortCallback = NULL; + + /* Check if an Abort process is still ongoing */ + if (huart->hdmarx != NULL) + { + if (huart->hdmarx->XferAbortCallback != NULL) + { + return; + } + } + + /* Reset errorCode */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + + /* Clear the Error flags in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); + + /* Flush the whole TX FIFO (if needed) */ + if (huart->FifoMode == UART_FIFOMODE_ENABLE) + { + __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST); + } + + /* Restore huart->gState and huart->RxState to Ready */ + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* Call user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort complete callback */ + huart->AbortCpltCallback(huart); +#else + /* Call legacy weak Abort complete callback */ + HAL_UART_AbortCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + + +/** + * @brief DMA UART Rx communication abort callback, when initiated by user + * (To be called at end of DMA Rx Abort procedure following user abort request). + * @note When this callback is executed, User Abort complete call back is called only if no + * Abort still ongoing for Tx DMA Handle. + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + + huart->hdmarx->XferAbortCallback = NULL; + + /* Check if an Abort process is still ongoing */ + if (huart->hdmatx != NULL) + { + if (huart->hdmatx->XferAbortCallback != NULL) + { + return; + } + } + + /* Reset errorCode */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + + /* Clear the Error flags in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); + + /* Discard the received data */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + + /* Restore huart->gState and huart->RxState to Ready */ + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* Call user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort complete callback */ + huart->AbortCpltCallback(huart); +#else + /* Call legacy weak Abort complete callback */ + HAL_UART_AbortCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + + +/** + * @brief DMA UART Tx communication abort callback, when initiated by user by a call to + * HAL_UART_AbortTransmit_IT API (Abort only Tx transfer) + * (This callback is executed at end of DMA Tx Abort procedure following user abort request, + * and leads to user Tx Abort Complete callback execution). + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + + /* Flush the whole TX FIFO (if needed) */ + if (huart->FifoMode == UART_FIFOMODE_ENABLE) + { + __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST); + } + + /* Restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + + /* Call user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Transmit Complete Callback */ + huart->AbortTransmitCpltCallback(huart); +#else + /* Call legacy weak Abort Transmit Complete Callback */ + HAL_UART_AbortTransmitCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA UART Rx communication abort callback, when initiated by user by a call to + * HAL_UART_AbortReceive_IT API (Abort only Rx transfer) + * (This callback is executed at end of DMA Rx Abort procedure following user abort request, + * and leads to user Rx Abort Complete callback execution). + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + /* Clear the Error flags in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); + + /* Discard the received data */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + + /* Restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* Call user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Receive Complete Callback */ + huart->AbortReceiveCpltCallback(huart); +#else + /* Call legacy weak Abort Receive Complete Callback */ + HAL_UART_AbortReceiveCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + +/** + * @brief TX interrupt handler for 7 or 8 bits data word length . + * @note Function is called under interruption only, once + * interruptions have been enabled by HAL_UART_Transmit_IT(). + * @param huart UART handle. + * @retval None + */ +static void UART_TxISR_8BIT(UART_HandleTypeDef *huart) +{ + /* Check that a Tx process is ongoing */ + if (huart->gState == HAL_UART_STATE_BUSY_TX) + { + if (huart->TxXferCount == 0U) + { + /* Disable the UART Transmit Data Register Empty Interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); + + /* Enable the UART Transmit Complete Interrupt */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); + } + else + { + huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF); + huart->pTxBuffPtr++; + huart->TxXferCount--; + } + } +} + +/** + * @brief TX interrupt handler for 9 bits data word length. + * @note Function is called under interruption only, once + * interruptions have been enabled by HAL_UART_Transmit_IT(). + * @param huart UART handle. + * @retval None + */ +static void UART_TxISR_16BIT(UART_HandleTypeDef *huart) +{ + const uint16_t *tmp; + + /* Check that a Tx process is ongoing */ + if (huart->gState == HAL_UART_STATE_BUSY_TX) + { + if (huart->TxXferCount == 0U) + { + /* Disable the UART Transmit Data Register Empty Interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); + + /* Enable the UART Transmit Complete Interrupt */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); + } + else + { + tmp = (const uint16_t *) huart->pTxBuffPtr; + huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL); + huart->pTxBuffPtr += 2U; + huart->TxXferCount--; + } + } +} + +/** + * @brief TX interrupt handler for 7 or 8 bits data word length and FIFO mode is enabled. + * @note Function is called under interruption only, once + * interruptions have been enabled by HAL_UART_Transmit_IT(). + * @param huart UART handle. + * @retval None + */ +static void UART_TxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) +{ + uint16_t nb_tx_data; + + /* Check that a Tx process is ongoing */ + if (huart->gState == HAL_UART_STATE_BUSY_TX) + { + for (nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--) + { + if (huart->TxXferCount == 0U) + { + /* Disable the TX FIFO threshold interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); + + /* Enable the UART Transmit Complete Interrupt */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); + + break; /* force exit loop */ + } + else if (READ_BIT(huart->Instance->ISR, USART_ISR_TXE_TXFNF) != 0U) + { + huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF); + huart->pTxBuffPtr++; + huart->TxXferCount--; + } + else + { + /* Nothing to do */ + } + } + } +} + +/** + * @brief TX interrupt handler for 9 bits data word length and FIFO mode is enabled. + * @note Function is called under interruption only, once + * interruptions have been enabled by HAL_UART_Transmit_IT(). + * @param huart UART handle. + * @retval None + */ +static void UART_TxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) +{ + const uint16_t *tmp; + uint16_t nb_tx_data; + + /* Check that a Tx process is ongoing */ + if (huart->gState == HAL_UART_STATE_BUSY_TX) + { + for (nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--) + { + if (huart->TxXferCount == 0U) + { + /* Disable the TX FIFO threshold interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); + + /* Enable the UART Transmit Complete Interrupt */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); + + break; /* force exit loop */ + } + else if (READ_BIT(huart->Instance->ISR, USART_ISR_TXE_TXFNF) != 0U) + { + tmp = (const uint16_t *) huart->pTxBuffPtr; + huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL); + huart->pTxBuffPtr += 2U; + huart->TxXferCount--; + } + else + { + /* Nothing to do */ + } + } + } +} + +/** + * @brief Wrap up transmission in non-blocking mode. + * @param huart pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval None + */ +static void UART_EndTransmit_IT(UART_HandleTypeDef *huart) +{ + /* Disable the UART Transmit Complete Interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE); + + /* Tx process is ended, restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + + /* Cleat TxISR function pointer */ + huart->TxISR = NULL; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Tx complete callback*/ + huart->TxCpltCallback(huart); +#else + /*Call legacy weak Tx complete callback*/ + HAL_UART_TxCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + +/** + * @brief RX interrupt handler for 7 or 8 bits data word length . + * @param huart UART handle. + * @retval None + */ +static void UART_RxISR_8BIT(UART_HandleTypeDef *huart) +{ + uint16_t uhMask = huart->Mask; + uint16_t uhdata; + + /* Check that a Rx process is ongoing */ + if (huart->RxState == HAL_UART_STATE_BUSY_RX) + { + uhdata = (uint16_t) READ_REG(huart->Instance->RDR); + *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask); + huart->pRxBuffPtr++; + huart->RxXferCount--; + + if (huart->RxXferCount == 0U) + { + /* Disable the UART Parity Error Interrupt and RXNE interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); + + /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Rx process is completed, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + + /* Clear RxISR function pointer */ + huart->RxISR = NULL; + + /* Initialize type of RxEvent to Transfer Complete */ + huart->RxEventType = HAL_UART_RXEVENT_TC; + + if (!(IS_LPUART_INSTANCE(huart->Instance))) + { + /* Check that USART RTOEN bit is set */ + if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) + { + /* Enable the UART Receiver Timeout Interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); + } + } + + /* Check current reception Mode : + If Reception till IDLE event has been selected : */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + /* Set reception type to Standard */ + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* Disable IDLE interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) + { + /* Clear IDLE Flag */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + } + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, huart->RxXferSize); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + else + { + /* Standard reception API called */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx complete callback*/ + huart->RxCpltCallback(huart); +#else + /*Call legacy weak Rx complete callback*/ + HAL_UART_RxCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + } + } + else + { + /* Clear RXNE interrupt flag */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + } +} + +/** + * @brief RX interrupt handler for 9 bits data word length . + * @note Function is called under interruption only, once + * interruptions have been enabled by HAL_UART_Receive_IT() + * @param huart UART handle. + * @retval None + */ +static void UART_RxISR_16BIT(UART_HandleTypeDef *huart) +{ + uint16_t *tmp; + uint16_t uhMask = huart->Mask; + uint16_t uhdata; + + /* Check that a Rx process is ongoing */ + if (huart->RxState == HAL_UART_STATE_BUSY_RX) + { + uhdata = (uint16_t) READ_REG(huart->Instance->RDR); + tmp = (uint16_t *) huart->pRxBuffPtr ; + *tmp = (uint16_t)(uhdata & uhMask); + huart->pRxBuffPtr += 2U; + huart->RxXferCount--; + + if (huart->RxXferCount == 0U) + { + /* Disable the UART Parity Error Interrupt and RXNE interrupt*/ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); + + /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Rx process is completed, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + + /* Clear RxISR function pointer */ + huart->RxISR = NULL; + + /* Initialize type of RxEvent to Transfer Complete */ + huart->RxEventType = HAL_UART_RXEVENT_TC; + + if (!(IS_LPUART_INSTANCE(huart->Instance))) + { + /* Check that USART RTOEN bit is set */ + if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) + { + /* Enable the UART Receiver Timeout Interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); + } + } + + /* Check current reception Mode : + If Reception till IDLE event has been selected : */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + /* Set reception type to Standard */ + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* Disable IDLE interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) + { + /* Clear IDLE Flag */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + } + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, huart->RxXferSize); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + else + { + /* Standard reception API called */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx complete callback*/ + huart->RxCpltCallback(huart); +#else + /*Call legacy weak Rx complete callback*/ + HAL_UART_RxCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + } + } + else + { + /* Clear RXNE interrupt flag */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + } +} + +/** + * @brief RX interrupt handler for 7 or 8 bits data word length and FIFO mode is enabled. + * @note Function is called under interruption only, once + * interruptions have been enabled by HAL_UART_Receive_IT() + * @param huart UART handle. + * @retval None + */ +static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) +{ + uint16_t uhMask = huart->Mask; + uint16_t uhdata; + uint16_t nb_rx_data; + uint16_t rxdatacount; + uint32_t isrflags = READ_REG(huart->Instance->ISR); + uint32_t cr1its = READ_REG(huart->Instance->CR1); + uint32_t cr3its = READ_REG(huart->Instance->CR3); + + /* Check that a Rx process is ongoing */ + if (huart->RxState == HAL_UART_STATE_BUSY_RX) + { + nb_rx_data = huart->NbRxDataToProcess; + while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U)) + { + uhdata = (uint16_t) READ_REG(huart->Instance->RDR); + *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask); + huart->pRxBuffPtr++; + huart->RxXferCount--; + isrflags = READ_REG(huart->Instance->ISR); + + /* If some non blocking errors occurred */ + if ((isrflags & (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE)) != 0U) + { + /* UART parity error interrupt occurred -------------------------------------*/ + if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF); + + huart->ErrorCode |= HAL_UART_ERROR_PE; + } + + /* UART frame error interrupt occurred --------------------------------------*/ + if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF); + + huart->ErrorCode |= HAL_UART_ERROR_FE; + } + + /* UART noise error interrupt occurred --------------------------------------*/ + if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF); + + huart->ErrorCode |= HAL_UART_ERROR_NE; + } + + /* Call UART Error Call back function if need be ----------------------------*/ + if (huart->ErrorCode != HAL_UART_ERROR_NONE) + { + /* Non Blocking error : transfer could go on. + Error is notified to user through user error callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + } + } + + if (huart->RxXferCount == 0U) + { + /* Disable the UART Parity Error Interrupt and RXFT interrupt*/ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); + + /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) + and RX FIFO Threshold interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); + + /* Rx process is completed, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + + /* Clear RxISR function pointer */ + huart->RxISR = NULL; + + /* Initialize type of RxEvent to Transfer Complete */ + huart->RxEventType = HAL_UART_RXEVENT_TC; + + if (!(IS_LPUART_INSTANCE(huart->Instance))) + { + /* Check that USART RTOEN bit is set */ + if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) + { + /* Enable the UART Receiver Timeout Interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); + } + } + + /* Check current reception Mode : + If Reception till IDLE event has been selected : */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + /* Set reception type to Standard */ + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* Disable IDLE interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) + { + /* Clear IDLE Flag */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + } + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, huart->RxXferSize); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + else + { + /* Standard reception API called */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx complete callback*/ + huart->RxCpltCallback(huart); +#else + /*Call legacy weak Rx complete callback*/ + HAL_UART_RxCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + break; + } + } + + /* When remaining number of bytes to receive is less than the RX FIFO + threshold, next incoming frames are processed as if FIFO mode was + disabled (i.e. one interrupt per received frame). + */ + rxdatacount = huart->RxXferCount; + if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess)) + { + /* Disable the UART RXFT interrupt*/ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); + + /* Update the RxISR function pointer */ + huart->RxISR = UART_RxISR_8BIT; + + /* Enable the UART Data Register Not Empty interrupt */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); + } + } + else + { + /* Clear RXNE interrupt flag */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + } +} + +/** + * @brief RX interrupt handler for 9 bits data word length and FIFO mode is enabled. + * @note Function is called under interruption only, once + * interruptions have been enabled by HAL_UART_Receive_IT() + * @param huart UART handle. + * @retval None + */ +static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) +{ + uint16_t *tmp; + uint16_t uhMask = huart->Mask; + uint16_t uhdata; + uint16_t nb_rx_data; + uint16_t rxdatacount; + uint32_t isrflags = READ_REG(huart->Instance->ISR); + uint32_t cr1its = READ_REG(huart->Instance->CR1); + uint32_t cr3its = READ_REG(huart->Instance->CR3); + + /* Check that a Rx process is ongoing */ + if (huart->RxState == HAL_UART_STATE_BUSY_RX) + { + nb_rx_data = huart->NbRxDataToProcess; + while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U)) + { + uhdata = (uint16_t) READ_REG(huart->Instance->RDR); + tmp = (uint16_t *) huart->pRxBuffPtr ; + *tmp = (uint16_t)(uhdata & uhMask); + huart->pRxBuffPtr += 2U; + huart->RxXferCount--; + isrflags = READ_REG(huart->Instance->ISR); + + /* If some non blocking errors occurred */ + if ((isrflags & (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE)) != 0U) + { + /* UART parity error interrupt occurred -------------------------------------*/ + if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF); + + huart->ErrorCode |= HAL_UART_ERROR_PE; + } + + /* UART frame error interrupt occurred --------------------------------------*/ + if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF); + + huart->ErrorCode |= HAL_UART_ERROR_FE; + } + + /* UART noise error interrupt occurred --------------------------------------*/ + if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF); + + huart->ErrorCode |= HAL_UART_ERROR_NE; + } + + /* Call UART Error Call back function if need be ----------------------------*/ + if (huart->ErrorCode != HAL_UART_ERROR_NONE) + { + /* Non Blocking error : transfer could go on. + Error is notified to user through user error callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + } + } + + if (huart->RxXferCount == 0U) + { + /* Disable the UART Parity Error Interrupt and RXFT interrupt*/ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); + + /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) + and RX FIFO Threshold interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); + + /* Rx process is completed, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + + /* Clear RxISR function pointer */ + huart->RxISR = NULL; + + /* Initialize type of RxEvent to Transfer Complete */ + huart->RxEventType = HAL_UART_RXEVENT_TC; + + if (!(IS_LPUART_INSTANCE(huart->Instance))) + { + /* Check that USART RTOEN bit is set */ + if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) + { + /* Enable the UART Receiver Timeout Interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); + } + } + + /* Check current reception Mode : + If Reception till IDLE event has been selected : */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + /* Set reception type to Standard */ + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* Disable IDLE interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) + { + /* Clear IDLE Flag */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + } + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, huart->RxXferSize); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + else + { + /* Standard reception API called */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx complete callback*/ + huart->RxCpltCallback(huart); +#else + /*Call legacy weak Rx complete callback*/ + HAL_UART_RxCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + break; + } + } + + /* When remaining number of bytes to receive is less than the RX FIFO + threshold, next incoming frames are processed as if FIFO mode was + disabled (i.e. one interrupt per received frame). + */ + rxdatacount = huart->RxXferCount; + if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess)) + { + /* Disable the UART RXFT interrupt*/ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); + + /* Update the RxISR function pointer */ + huart->RxISR = UART_RxISR_16BIT; + + /* Enable the UART Data Register Not Empty interrupt */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); + } + } + else + { + /* Clear RXNE interrupt flag */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + } +} + +/** + * @} + */ + +#endif /* HAL_UART_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + diff --git a/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.c b/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.c new file mode 100644 index 0000000..47aca30 --- /dev/null +++ b/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.c @@ -0,0 +1,1101 @@ +/** + ****************************************************************************** + * @file stm32wlxx_hal_uart_ex.c + * @author MCD Application Team + * @brief Extended UART HAL module driver. + * This file provides firmware functions to manage the following extended + * functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART). + * + Initialization and de-initialization functions + * + Peripheral Control functions + * + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### UART peripheral extended features ##### + ============================================================================== + [..] + (#) Declare a UART_HandleTypeDef handle structure. + + (#) For the UART RS485 Driver Enable mode, initialize the UART registers + by calling the HAL_RS485Ex_Init() API. + + (#) FIFO mode enabling/disabling and RX/TX FIFO threshold programming. + + -@- When UART operates in FIFO mode, FIFO mode must be enabled prior + starting RX/TX transfers. Also RX/TX FIFO thresholds must be + configured prior starting RX/TX transfers. + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wlxx_hal.h" + +/** @addtogroup STM32WLxx_HAL_Driver + * @{ + */ + +/** @defgroup UARTEx UARTEx + * @brief UART Extended HAL module driver + * @{ + */ + +#ifdef HAL_UART_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup UARTEX_Private_Constants UARTEx Private Constants + * @{ + */ +/* UART RX FIFO depth */ +#define RX_FIFO_DEPTH 8U + +/* UART TX FIFO depth */ +#define TX_FIFO_DEPTH 8U +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup UARTEx_Private_Functions UARTEx Private Functions + * @{ + */ +static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection); +static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup UARTEx_Exported_Functions UARTEx Exported Functions + * @{ + */ + +/** @defgroup UARTEx_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Extended Initialization and Configuration Functions + * +@verbatim +=============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to initialize the USARTx or the UARTy + in asynchronous mode. + (+) For the asynchronous mode the parameters below can be configured: + (++) Baud Rate + (++) Word Length + (++) Stop Bit + (++) Parity: If the parity is enabled, then the MSB bit of the data written + in the data register is transmitted but is changed by the parity bit. + (++) Hardware flow control + (++) Receiver/transmitter modes + (++) Over Sampling Method + (++) One-Bit Sampling Method + (+) For the asynchronous mode, the following advanced features can be configured as well: + (++) TX and/or RX pin level inversion + (++) data logical level inversion + (++) RX and TX pins swap + (++) RX overrun detection disabling + (++) DMA disabling on RX error + (++) MSB first on communication line + (++) auto Baud rate detection + [..] + The HAL_RS485Ex_Init() API follows the UART RS485 mode configuration + procedures (details for the procedures are available in reference manual). + +@endverbatim + + Depending on the frame length defined by the M1 and M0 bits (7-bit, + 8-bit or 9-bit), the possible UART formats are listed in the + following table. + + Table 1. UART frame format. + +-----------------------------------------------------------------------+ + | M1 bit | M0 bit | PCE bit | UART frame | + |---------|---------|-----------|---------------------------------------| + | 0 | 0 | 0 | | SB | 8 bit data | STB | | + |---------|---------|-----------|---------------------------------------| + | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | | + |---------|---------|-----------|---------------------------------------| + | 0 | 1 | 0 | | SB | 9 bit data | STB | | + |---------|---------|-----------|---------------------------------------| + | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | | + |---------|---------|-----------|---------------------------------------| + | 1 | 0 | 0 | | SB | 7 bit data | STB | | + |---------|---------|-----------|---------------------------------------| + | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | | + +-----------------------------------------------------------------------+ + + * @{ + */ + +/** + * @brief Initialize the RS485 Driver enable feature according to the specified + * parameters in the UART_InitTypeDef and creates the associated handle. + * @param huart UART handle. + * @param Polarity Select the driver enable polarity. + * This parameter can be one of the following values: + * @arg @ref UART_DE_POLARITY_HIGH DE signal is active high + * @arg @ref UART_DE_POLARITY_LOW DE signal is active low + * @param AssertionTime Driver Enable assertion time: + * 5-bit value defining the time between the activation of the DE (Driver Enable) + * signal and the beginning of the start bit. It is expressed in sample time + * units (1/8 or 1/16 bit time, depending on the oversampling rate) + * @param DeassertionTime Driver Enable deassertion time: + * 5-bit value defining the time between the end of the last stop bit, in a + * transmitted message, and the de-activation of the DE (Driver Enable) signal. + * It is expressed in sample time units (1/8 or 1/16 bit time, depending on the + * oversampling rate). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, + uint32_t DeassertionTime) +{ + uint32_t temp; + + /* Check the UART handle allocation */ + if (huart == NULL) + { + return HAL_ERROR; + } + /* Check the Driver Enable UART instance */ + assert_param(IS_UART_DRIVER_ENABLE_INSTANCE(huart->Instance)); + + /* Check the Driver Enable polarity */ + assert_param(IS_UART_DE_POLARITY(Polarity)); + + /* Check the Driver Enable assertion time */ + assert_param(IS_UART_ASSERTIONTIME(AssertionTime)); + + /* Check the Driver Enable deassertion time */ + assert_param(IS_UART_DEASSERTIONTIME(DeassertionTime)); + + if (huart->gState == HAL_UART_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + huart->Lock = HAL_UNLOCKED; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + UART_InitCallbacksToDefault(huart); + + if (huart->MspInitCallback == NULL) + { + huart->MspInitCallback = HAL_UART_MspInit; + } + + /* Init the low level hardware */ + huart->MspInitCallback(huart); +#else + /* Init the low level hardware : GPIO, CLOCK, CORTEX */ + HAL_UART_MspInit(huart); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + + huart->gState = HAL_UART_STATE_BUSY; + + /* Disable the Peripheral */ + __HAL_UART_DISABLE(huart); + + /* Perform advanced settings configuration */ + /* For some items, configuration requires to be done prior TE and RE bits are set */ + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) + { + UART_AdvFeatureConfig(huart); + } + + /* Set the UART Communication parameters */ + if (UART_SetConfig(huart) == HAL_ERROR) + { + return HAL_ERROR; + } + + /* Enable the Driver Enable mode by setting the DEM bit in the CR3 register */ + SET_BIT(huart->Instance->CR3, USART_CR3_DEM); + + /* Set the Driver Enable polarity */ + MODIFY_REG(huart->Instance->CR3, USART_CR3_DEP, Polarity); + + /* Set the Driver Enable assertion and deassertion times */ + temp = (AssertionTime << UART_CR1_DEAT_ADDRESS_LSB_POS); + temp |= (DeassertionTime << UART_CR1_DEDT_ADDRESS_LSB_POS); + MODIFY_REG(huart->Instance->CR1, (USART_CR1_DEDT | USART_CR1_DEAT), temp); + + /* Enable the Peripheral */ + __HAL_UART_ENABLE(huart); + + /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ + return (UART_CheckIdleState(huart)); +} + +/** + * @} + */ + +/** @defgroup UARTEx_Exported_Functions_Group2 IO operation functions + * @brief Extended functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] + This subsection provides a set of Wakeup and FIFO mode related callback functions. + (#) Wakeup from Stop mode Callback: + (++) HAL_UARTEx_WakeupCallback() + (#) TX/RX Fifos Callbacks: + (++) HAL_UARTEx_RxFifoFullCallback() + (++) HAL_UARTEx_TxFifoEmptyCallback() +@endverbatim + * @{ + */ + +/** + * @brief UART wakeup from Stop mode callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UARTEx_WakeupCallback can be implemented in the user file. + */ +} + +/** + * @brief UART RX Fifo full callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UARTEx_RxFifoFullCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UARTEx_RxFifoFullCallback can be implemented in the user file. + */ +} + +/** + * @brief UART TX Fifo empty callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UARTEx_TxFifoEmptyCallback can be implemented in the user file. + */ +} + +/** + * @} + */ + +/** @defgroup UARTEx_Exported_Functions_Group3 Peripheral Control functions + * @brief Extended Peripheral Control functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] This section provides the following functions: + (+) HAL_MultiProcessorEx_AddressLength_Set() API optionally sets the UART node address + detection length to more than 4 bits for multiprocessor address mark wake up. + (+) HAL_UARTEx_StopModeWakeUpSourceConfig() API defines the wake-up from stop mode + trigger: address match, Start Bit detection or RXNE bit status. + (+) HAL_UARTEx_EnableStopMode() API enables the UART to wake up the MCU from stop mode + (+) HAL_UARTEx_DisableStopMode() API disables the above functionality + (+) HAL_UARTEx_EnableFifoMode() API enables the FIFO mode + (+) HAL_UARTEx_DisableFifoMode() API disables the FIFO mode + (+) HAL_UARTEx_SetTxFifoThreshold() API sets the TX FIFO threshold + (+) HAL_UARTEx_SetRxFifoThreshold() API sets the RX FIFO threshold + + [..] This subsection also provides a set of additional functions providing enhanced reception + services to user. (For example, these functions allow application to handle use cases + where number of data to be received is unknown). + + (#) Compared to standard reception services which only consider number of received + data elements as reception completion criteria, these functions also consider additional events + as triggers for updating reception status to caller : + (++) Detection of inactivity period (RX line has not been active for a given period). + (+++) RX inactivity detected by IDLE event, i.e. RX line has been in idle state (normally high state) + for 1 frame time, after last received byte. + (+++) RX inactivity detected by RTO, i.e. line has been in idle state + for a programmable time, after last received byte. + (++) Detection that a specific character has been received. + + (#) There are two modes of transfer: + (++) Blocking mode: The reception is performed in polling mode, until either expected number of data is received, + or till IDLE event occurs. Reception is handled only during function execution. + When function exits, no data reception could occur. HAL status and number of actually received data elements, + are returned by function after finishing transfer. + (++) Non-Blocking mode: The reception is performed using Interrupts or DMA. + These API's return the HAL status. + The end of the data processing will be indicated through the + dedicated UART IRQ when using Interrupt mode or the DMA IRQ when using DMA mode. + The HAL_UARTEx_RxEventCallback() user callback will be executed during Receive process + The HAL_UART_ErrorCallback()user callback will be executed when a reception error is detected. + + (#) Blocking mode API: + (++) HAL_UARTEx_ReceiveToIdle() + + (#) Non-Blocking mode API with Interrupt: + (++) HAL_UARTEx_ReceiveToIdle_IT() + + (#) Non-Blocking mode API with DMA: + (++) HAL_UARTEx_ReceiveToIdle_DMA() + +@endverbatim + * @{ + */ + +/** + * @brief By default in multiprocessor mode, when the wake up method is set + * to address mark, the UART handles only 4-bit long addresses detection; + * this API allows to enable longer addresses detection (6-, 7- or 8-bit + * long). + * @note Addresses detection lengths are: 6-bit address detection in 7-bit data mode, + * 7-bit address detection in 8-bit data mode, 8-bit address detection in 9-bit data mode. + * @param huart UART handle. + * @param AddressLength This parameter can be one of the following values: + * @arg @ref UART_ADDRESS_DETECT_4B 4-bit long address + * @arg @ref UART_ADDRESS_DETECT_7B 6-, 7- or 8-bit long address + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength) +{ + /* Check the UART handle allocation */ + if (huart == NULL) + { + return HAL_ERROR; + } + + /* Check the address length parameter */ + assert_param(IS_UART_ADDRESSLENGTH_DETECT(AddressLength)); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Disable the Peripheral */ + __HAL_UART_DISABLE(huart); + + /* Set the address length */ + MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, AddressLength); + + /* Enable the Peripheral */ + __HAL_UART_ENABLE(huart); + + /* TEACK and/or REACK to check before moving huart->gState to Ready */ + return (UART_CheckIdleState(huart)); +} + +/** + * @brief Set Wakeup from Stop mode interrupt flag selection. + * @note It is the application responsibility to enable the interrupt used as + * usart_wkup interrupt source before entering low-power mode. + * @param huart UART handle. + * @param WakeUpSelection Address match, Start Bit detection or RXNE/RXFNE bit status. + * This parameter can be one of the following values: + * @arg @ref UART_WAKEUP_ON_ADDRESS + * @arg @ref UART_WAKEUP_ON_STARTBIT + * @arg @ref UART_WAKEUP_ON_READDATA_NONEMPTY + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tickstart; + + /* check the wake-up from stop mode UART instance */ + assert_param(IS_UART_WAKEUP_FROMSTOP_INSTANCE(huart->Instance)); + /* check the wake-up selection parameter */ + assert_param(IS_UART_WAKEUP_SELECTION(WakeUpSelection.WakeUpEvent)); + + /* Process Locked */ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Disable the Peripheral */ + __HAL_UART_DISABLE(huart); + + /* Set the wake-up selection scheme */ + MODIFY_REG(huart->Instance->CR3, USART_CR3_WUS, WakeUpSelection.WakeUpEvent); + + if (WakeUpSelection.WakeUpEvent == UART_WAKEUP_ON_ADDRESS) + { + UARTEx_Wakeup_AddressConfig(huart, WakeUpSelection); + } + + /* Enable the Peripheral */ + __HAL_UART_ENABLE(huart); + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + + /* Wait until REACK flag is set */ + if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) + { + status = HAL_TIMEOUT; + } + else + { + /* Initialize the UART State */ + huart->gState = HAL_UART_STATE_READY; + } + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return status; +} + +/** + * @brief Enable UART Stop Mode. + * @note The UART is able to wake up the MCU from Stop 1 mode as long as UART clock is HSI or LSE. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart) +{ + /* Process Locked */ + __HAL_LOCK(huart); + + /* Set UESM bit */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_UESM); + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Disable UART Stop Mode. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart) +{ + /* Process Locked */ + __HAL_LOCK(huart); + + /* Clear UESM bit */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_UESM); + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Enable the FIFO mode. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_EnableFifoMode(UART_HandleTypeDef *huart) +{ + uint32_t tmpcr1; + + /* Check parameters */ + assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); + + /* Process Locked */ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Save actual UART configuration */ + tmpcr1 = READ_REG(huart->Instance->CR1); + + /* Disable UART */ + __HAL_UART_DISABLE(huart); + + /* Enable FIFO mode */ + SET_BIT(tmpcr1, USART_CR1_FIFOEN); + huart->FifoMode = UART_FIFOMODE_ENABLE; + + /* Restore UART configuration */ + WRITE_REG(huart->Instance->CR1, tmpcr1); + + /* Determine the number of data to process during RX/TX ISR execution */ + UARTEx_SetNbDataToProcess(huart); + + huart->gState = HAL_UART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Disable the FIFO mode. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart) +{ + uint32_t tmpcr1; + + /* Check parameters */ + assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); + + /* Process Locked */ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Save actual UART configuration */ + tmpcr1 = READ_REG(huart->Instance->CR1); + + /* Disable UART */ + __HAL_UART_DISABLE(huart); + + /* Disable FIFO mode */ + CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN); + huart->FifoMode = UART_FIFOMODE_DISABLE; + + /* Restore UART configuration */ + WRITE_REG(huart->Instance->CR1, tmpcr1); + + huart->gState = HAL_UART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Set the TXFIFO threshold. + * @param huart UART handle. + * @param Threshold TX FIFO threshold value + * This parameter can be one of the following values: + * @arg @ref UART_TXFIFO_THRESHOLD_1_8 + * @arg @ref UART_TXFIFO_THRESHOLD_1_4 + * @arg @ref UART_TXFIFO_THRESHOLD_1_2 + * @arg @ref UART_TXFIFO_THRESHOLD_3_4 + * @arg @ref UART_TXFIFO_THRESHOLD_7_8 + * @arg @ref UART_TXFIFO_THRESHOLD_8_8 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold) +{ + uint32_t tmpcr1; + + /* Check parameters */ + assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); + assert_param(IS_UART_TXFIFO_THRESHOLD(Threshold)); + + /* Process Locked */ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Save actual UART configuration */ + tmpcr1 = READ_REG(huart->Instance->CR1); + + /* Disable UART */ + __HAL_UART_DISABLE(huart); + + /* Update TX threshold configuration */ + MODIFY_REG(huart->Instance->CR3, USART_CR3_TXFTCFG, Threshold); + + /* Determine the number of data to process during RX/TX ISR execution */ + UARTEx_SetNbDataToProcess(huart); + + /* Restore UART configuration */ + WRITE_REG(huart->Instance->CR1, tmpcr1); + + huart->gState = HAL_UART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Set the RXFIFO threshold. + * @param huart UART handle. + * @param Threshold RX FIFO threshold value + * This parameter can be one of the following values: + * @arg @ref UART_RXFIFO_THRESHOLD_1_8 + * @arg @ref UART_RXFIFO_THRESHOLD_1_4 + * @arg @ref UART_RXFIFO_THRESHOLD_1_2 + * @arg @ref UART_RXFIFO_THRESHOLD_3_4 + * @arg @ref UART_RXFIFO_THRESHOLD_7_8 + * @arg @ref UART_RXFIFO_THRESHOLD_8_8 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold) +{ + uint32_t tmpcr1; + + /* Check the parameters */ + assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); + assert_param(IS_UART_RXFIFO_THRESHOLD(Threshold)); + + /* Process Locked */ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Save actual UART configuration */ + tmpcr1 = READ_REG(huart->Instance->CR1); + + /* Disable UART */ + __HAL_UART_DISABLE(huart); + + /* Update RX threshold configuration */ + MODIFY_REG(huart->Instance->CR3, USART_CR3_RXFTCFG, Threshold); + + /* Determine the number of data to process during RX/TX ISR execution */ + UARTEx_SetNbDataToProcess(huart); + + /* Restore UART configuration */ + WRITE_REG(huart->Instance->CR1, tmpcr1); + + huart->gState = HAL_UART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Receive an amount of data in blocking mode till either the expected number of data + * is received or an IDLE event occurs. + * @note HAL_OK is returned if reception is completed (expected number of data has been received) + * or if reception is stopped after IDLE event (less than the expected number of data has been received) + * In this case, RxLen output parameter indicates number of data available in reception buffer. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of uint16_t. In this case, Size must indicate the number + * of uint16_t available through pData. + * @note When FIFO mode is enabled, the RXFNE flag is set as long as the RXFIFO + * is not empty. Read operations from the RDR register are performed when + * RXFNE flag is set. From hardware perspective, RXFNE flag and + * RXNE are mapped on the same bit-field. +#if defined(CORE_CM0PLUS) + * @note Dual core specific: there is no support for unaligned accesses on the Cortex-M0+ processor. + * When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * (16 bits) address of user data buffer for storing data to be received, should be aligned on a half + * word frontier (as received data will be handled using uint16_t pointer cast). + * Depending on compilation chain, use of specific alignment compilation directives or pragmas + * might be required to ensure proper alignment for pData. +#endif + * @param huart UART handle. + * @param pData Pointer to data buffer (uint8_t or uint16_t data elements). + * @param Size Amount of data elements (uint8_t or uint16_t) to be received. + * @param RxLen Number of data elements finally received + * (could be lower than Size, in case reception ends on IDLE event) + * @param Timeout Timeout duration expressed in ms (covers the whole reception sequence). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen, + uint32_t Timeout) +{ + uint8_t *pdata8bits; + uint16_t *pdata16bits; + uint16_t uhMask; + uint32_t tickstart; + + /* Check that a Rx process is not already ongoing */ + if (huart->RxState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + +#if defined(CORE_CM0PLUS) + /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter + should be aligned on a uint16_t frontier, as data to be received from RDR will be + handled through a uint16_t cast. */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + if ((((uint32_t)pData) & 1U) != 0U) + { + return HAL_ERROR; + } + } + +#endif /* CORE_CM0PLUS */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->RxState = HAL_UART_STATE_BUSY_RX; + huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; + huart->RxEventType = HAL_UART_RXEVENT_TC; + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + + huart->RxXferSize = Size; + huart->RxXferCount = Size; + + /* Computation of UART mask to apply to RDR register */ + UART_MASK_COMPUTATION(huart); + uhMask = huart->Mask; + + /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + pdata8bits = NULL; + pdata16bits = (uint16_t *) pData; + } + else + { + pdata8bits = pData; + pdata16bits = NULL; + } + + /* Initialize output number of received elements */ + *RxLen = 0U; + + /* as long as data have to be received */ + while (huart->RxXferCount > 0U) + { + /* Check if IDLE flag is set */ + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE)) + { + /* Clear IDLE flag in ISR */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + + /* If Set, but no data ever received, clear flag without exiting loop */ + /* If Set, and data has already been received, this means Idle Event is valid : End reception */ + if (*RxLen > 0U) + { + huart->RxEventType = HAL_UART_RXEVENT_IDLE; + huart->RxState = HAL_UART_STATE_READY; + + return HAL_OK; + } + } + + /* Check if RXNE flag is set */ + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RXNE)) + { + if (pdata8bits == NULL) + { + *pdata16bits = (uint16_t)(huart->Instance->RDR & uhMask); + pdata16bits++; + } + else + { + *pdata8bits = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask); + pdata8bits++; + } + /* Increment number of received elements */ + *RxLen += 1U; + huart->RxXferCount--; + } + + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + huart->RxState = HAL_UART_STATE_READY; + + return HAL_TIMEOUT; + } + } + } + + /* Set number of received elements in output parameter : RxLen */ + *RxLen = huart->RxXferSize - huart->RxXferCount; + /* At end of Rx process, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in interrupt mode till either the expected number of data + * is received or an IDLE event occurs. + * @note Reception is initiated by this function call. Further progress of reception is achieved thanks + * to UART interrupts raised by RXNE and IDLE events. Callback is called at end of reception indicating + * number of received data elements. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of uint16_t. In this case, Size must indicate the number + * of uint16_t available through pData. +#if defined(CORE_CM0PLUS) + * @note Dual core specific: there is no support for unaligned accesses on the Cortex-M0+ processor. + * When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * address of user data buffer for storing data to be received, should be aligned on a half word frontier + * (16 bits) (as received data will be handled using uint16_t pointer cast). Depending on compilation chain, + * use of specific alignment compilation directives or pragmas might be required + * to ensure proper alignment for pData. +#endif + * @param huart UART handle. + * @param pData Pointer to data buffer (uint8_t or uint16_t data elements). + * @param Size Amount of data elements (uint8_t or uint16_t) to be received. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check that a Rx process is not already ongoing */ + if (huart->RxState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + +#if defined(CORE_CM0PLUS) + /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter + should be aligned on a uint16_t frontier, as data to be received from RDR will be + handled through a uint16_t cast. */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + if ((((uint32_t)pData) & 1U) != 0U) + { + return HAL_ERROR; + } + } + +#endif /* CORE_CM0PLUS */ + /* Set Reception type to reception till IDLE Event*/ + huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; + huart->RxEventType = HAL_UART_RXEVENT_TC; + + (void)UART_Start_Receive_IT(huart, pData, Size); + + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + } + else + { + /* In case of errors already pending when reception is started, + Interrupts may have already been raised and lead to reception abortion. + (Overrun error for instance). + In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */ + status = HAL_ERROR; + } + + return status; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in DMA mode till either the expected number + * of data is received or an IDLE event occurs. + * @note Reception is initiated by this function call. Further progress of reception is achieved thanks + * to DMA services, transferring automatically received data elements in user reception buffer and + * calling registered callbacks at half/end of reception. UART IDLE events are also used to consider + * reception phase as ended. In all cases, callback execution will indicate number of received data elements. + * @note When the UART parity is enabled (PCE = 1), the received data contain + * the parity bit (MSB position). + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of uint16_t. In this case, Size must indicate the number + * of uint16_t available through pData. +#if defined(CORE_CM0PLUS) + * @note Dual core specific: there is no support for unaligned accesses on the Cortex-M0+ processor. + * When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * address of user data buffer for storing data to be received, should be aligned on a half word frontier + * (16 bits) (as received data will be handled by DMA from halfword frontier). Depending on compilation chain, + * use of specific alignment compilation directives or pragmas might be required + * to ensure proper alignment for pData. +#endif + * @param huart UART handle. + * @param pData Pointer to data buffer (uint8_t or uint16_t data elements). + * @param Size Amount of data elements (uint8_t or uint16_t) to be received. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef status; + + /* Check that a Rx process is not already ongoing */ + if (huart->RxState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + +#if defined(CORE_CM0PLUS) + /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter + should be aligned on a uint16_t frontier, as data copy from RDR will be + handled by DMA from a uint16_t frontier. */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + if ((((uint32_t)pData) & 1U) != 0U) + { + return HAL_ERROR; + } + } + +#endif /* CORE_CM0PLUS */ + /* Set Reception type to reception till IDLE Event*/ + huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; + huart->RxEventType = HAL_UART_RXEVENT_TC; + + status = UART_Start_Receive_DMA(huart, pData, Size); + + /* Check Rx process has been successfully started */ + if (status == HAL_OK) + { + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + } + else + { + /* In case of errors already pending when reception is started, + Interrupts may have already been raised and lead to reception abortion. + (Overrun error for instance). + In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */ + status = HAL_ERROR; + } + } + + return status; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Provide Rx Event type that has lead to RxEvent callback execution. + * @note When HAL_UARTEx_ReceiveToIdle_IT() or HAL_UARTEx_ReceiveToIdle_DMA() API are called, progress + * of reception process is provided to application through calls of Rx Event callback (either default one + * HAL_UARTEx_RxEventCallback() or user registered one). As several types of events could occur (IDLE event, + * Half Transfer, or Transfer Complete), this function allows to retrieve the Rx Event type that has lead + * to Rx Event callback execution. + * @note This function is expected to be called within the user implementation of Rx Event Callback, + * in order to provide the accurate value. + * @note In Interrupt Mode: + * - HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has been received). + * - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed. + * @note In DMA Mode: + * - HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has been received). + * - HAL_UART_RXEVENT_HT : when half of expected nb of data has been received. + * - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed. + * @note In DMA mode, RxEvent callback could be called several times; + * When DMA is configured in Normal Mode, HT event does not stop Reception process; + * When DMA is configured in Circular Mode, HT, TC or IDLE events don't stop Reception process; + * @param huart UART handle. + * @retval Rx Event Type (return vale will be a value of @ref UART_RxEvent_Type_Values) + */ +HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(const UART_HandleTypeDef *huart) +{ + /* Return Rx Event type value, as stored in UART handle */ + return (huart->RxEventType); +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup UARTEx_Private_Functions + * @{ + */ + +/** + * @brief Initialize the UART wake-up from stop mode parameters when triggered by address detection. + * @param huart UART handle. + * @param WakeUpSelection UART wake up from stop mode parameters. + * @retval None + */ +static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection) +{ + assert_param(IS_UART_ADDRESSLENGTH_DETECT(WakeUpSelection.AddressLength)); + + /* Set the USART address length */ + MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, WakeUpSelection.AddressLength); + + /* Set the USART address node */ + MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)WakeUpSelection.Address << UART_CR2_ADDRESS_LSB_POS)); +} + +/** + * @brief Calculate the number of data to process in RX/TX ISR. + * @note The RX FIFO depth and the TX FIFO depth is extracted from + * the UART configuration registers. + * @param huart UART handle. + * @retval None + */ +static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart) +{ + uint8_t rx_fifo_depth; + uint8_t tx_fifo_depth; + uint8_t rx_fifo_threshold; + uint8_t tx_fifo_threshold; + static const uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U}; + static const uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U}; + + if (huart->FifoMode == UART_FIFOMODE_DISABLE) + { + huart->NbTxDataToProcess = 1U; + huart->NbRxDataToProcess = 1U; + } + else + { + rx_fifo_depth = RX_FIFO_DEPTH; + tx_fifo_depth = TX_FIFO_DEPTH; + rx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos); + tx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos); + huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / + (uint16_t)denominator[tx_fifo_threshold]; + huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / + (uint16_t)denominator[rx_fifo_threshold]; + } +} +/** + * @} + */ + +#endif /* HAL_UART_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ + diff --git a/EWARM/Project.eww b/EWARM/Project.eww new file mode 100644 index 0000000..91efaac --- /dev/null +++ b/EWARM/Project.eww @@ -0,0 +1,7 @@ + + + + $WS_DIR$\SubGHz_Phy_Per.ewp + + + diff --git a/EWARM/SubGHz_Phy_Per.ewd b/EWARM/SubGHz_Phy_Per.ewd new file mode 100644 index 0000000..4c89695 --- /dev/null +++ b/EWARM/SubGHz_Phy_Per.ewd @@ -0,0 +1,1534 @@ + + + 3 + + SubGHz_Phy_Per + + ARM + + 1 + + C-SPY + 2 + + 32 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 1 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 1 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + IJET_ID + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + JLINK_ID + 2 + + 16 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LMIFTDI_ID + 2 + + 3 + 1 + 1 + + + + + + + + + + + + + NULINK_ID + 2 + + 0 + 1 + 1 + + + + + + + PEMICRO_ID + 2 + + 3 + 1 + 1 + + + + + + + + STLINK_ID + 2 + + 7 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + THIRDPARTY_ID + 2 + + 0 + 1 + 1 + + + + + + + + TIFET_ID + 2 + + 1 + 1 + 1 + + + + + + + + + + + + + + + + + + + XDS100_ID + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\FreeRtos\FreeRtosArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin2.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm9.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm9BE.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + diff --git a/EWARM/SubGHz_Phy_Per.ewp b/EWARM/SubGHz_Phy_Per.ewp new file mode 100644 index 0000000..2c1fcc6 --- /dev/null +++ b/EWARM/SubGHz_Phy_Per.ewp @@ -0,0 +1,1286 @@ + + + 3 + + SubGHz_Phy_Per + + ARM + + 1 + + General + 3 + + 34 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 37 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 11 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + inputOutputBased + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 26 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + Coder + 0 + + + + + Application + + EWARM + + $PROJ_DIR$/startup_stm32wl55xx_cm4.s + + + + User + + Core + + $PROJ_DIR$/../Core/Src/dma.c + + + $PROJ_DIR$/../Core/Src/gpio.c + + + $PROJ_DIR$/../Core/Src/main.c + + + $PROJ_DIR$/../Core/Src/rtc.c + + + $PROJ_DIR$/../Core/Src/stm32_lpm_if.c + + + $PROJ_DIR$/../Core/Src/stm32wlxx_hal_msp.c + + + $PROJ_DIR$/../Core/Src/stm32wlxx_it.c + + + $PROJ_DIR$/../Core/Src/subghz.c + + + $PROJ_DIR$/../Core/Src/sys_app.c + + + $PROJ_DIR$/../Core/Src/sys_debug.c + + + $PROJ_DIR$/../Core/Src/timer_if.c + + + $PROJ_DIR$/../Core/Src/usart.c + + + $PROJ_DIR$/../Core/Src/usart_if.c + + + + SubGHz_Phy + + App + + $PROJ_DIR$/../SubGHz_Phy/App/app_subghz_phy.c + + + $PROJ_DIR$/../SubGHz_Phy/App/subghz_phy_app.c + + + + Target + + $PROJ_DIR$/../SubGHz_Phy/Target/radio_board_if.c + + + + + + + Doc + + $PROJ_DIR$/../readme.txt + + + + Drivers + + BSP + + STM32WLxx_Nucleo + + $PROJ_DIR$/../Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo.c + + + $PROJ_DIR$/../Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo_radio.c + + + + + CMSIS + + $PROJ_DIR$/../Core/Src/system_stm32wlxx.c + + + + STM32WLxx_HAL_Driver + + $PROJ_DIR$/../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c + + + $PROJ_DIR$/../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.c + + + $PROJ_DIR$/../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.c + + + $PROJ_DIR$/../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma_ex.c + + + $PROJ_DIR$/../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_exti.c + + + $PROJ_DIR$/../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash.c + + + $PROJ_DIR$/../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c + + + $PROJ_DIR$/../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_gpio.c + + + $PROJ_DIR$/../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.c + + + $PROJ_DIR$/../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c + + + $PROJ_DIR$/../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.c + + + $PROJ_DIR$/../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.c + + + $PROJ_DIR$/../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.c + + + $PROJ_DIR$/../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c + + + $PROJ_DIR$/../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c + + + $PROJ_DIR$/../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_tim.c + + + $PROJ_DIR$/../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_tim_ex.c + + + $PROJ_DIR$/../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c + + + $PROJ_DIR$/../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.c + + + + + Middlewares + + SubGHz_Phy + + $PROJ_DIR$/../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.c + + + $PROJ_DIR$/../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c + + + $PROJ_DIR$/../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c + + + $PROJ_DIR$/../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.c + + + $PROJ_DIR$/../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/wl_lr_fhss.c + + + + + Utilities + + $PROJ_DIR$/../Utilities/trace/adv_trace/stm32_adv_trace.c + + + $PROJ_DIR$/../Utilities/lpm/tiny_lpm/stm32_lpm.c + + + $PROJ_DIR$/../Utilities/misc/stm32_mem.c + + + $PROJ_DIR$/../Utilities/sequencer/stm32_seq.c + + + $PROJ_DIR$/../Utilities/misc/stm32_systime.c + + + $PROJ_DIR$/../Utilities/timer/stm32_timer.c + + + $PROJ_DIR$/../Utilities/misc/stm32_tiny_sscanf.c + + + $PROJ_DIR$/../Utilities/misc/stm32_tiny_vsnprintf.c + + + diff --git a/EWARM/startup_stm32wl55xx_cm4.s b/EWARM/startup_stm32wl55xx_cm4.s new file mode 100644 index 0000000..c2db9cb --- /dev/null +++ b/EWARM/startup_stm32wl55xx_cm4.s @@ -0,0 +1,508 @@ +;******************************************************************************** +;* File Name : startup_stm32wl55xx_cm4.s +;* Author : MCD Application Team +;* Description : M4 core vector table of the STM32WLxxxx devices for the +;* IAR (EWARM) toolchain. +;* +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == _iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address. +;* - Branches to main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* @attention +;* +;* Copyright (c) 2020-2021 STMicroelectronics. +;* All rights reserved. +;* +;* This software is licensed under terms that can be found in the LICENSE file +;* in the root directory of this software component. +;* If no LICENSE file comes with this software, it is provided AS-IS. +; +;******************************************************************************** +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_PVM_IRQHandler ; PVD and PVM Interrupt + DCD TAMP_STAMP_LSECSS_SSRU_IRQHandler ; RTC Tamper, RTC TimeStamp, LSECSS and RTC SSRU Interrupts + DCD RTC_WKUP_IRQHandler ; RTC Wakeup Interrupt + DCD FLASH_IRQHandler ; FLASH global Interrupt + DCD RCC_IRQHandler ; RCC Interrupt + DCD EXTI0_IRQHandler ; EXTI Line 0 Interrupt + DCD EXTI1_IRQHandler ; EXTI Line 1 Interrupt + DCD EXTI2_IRQHandler ; EXTI Line 2 Interrupt + DCD EXTI3_IRQHandler ; EXTI Line 3 Interrupt + DCD EXTI4_IRQHandler ; EXTI Line 4 Interrupt + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 Interrupt + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 Interrupt + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 Interrupt + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 Interrupt + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 Interrupt + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 Interrupt + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 Interrupt + DCD ADC_IRQHandler ; ADC Interrupt + DCD DAC_IRQHandler ; DAC Interrupt + DCD C2SEV_PWR_C2H_IRQHandler ; CPU M0+ SEV Interrupt + DCD COMP_IRQHandler ; COMP1 and COMP2 Interrupts + DCD EXTI9_5_IRQHandler ; EXTI Lines [9:5] Interrupt + DCD TIM1_BRK_IRQHandler ; TIM1 Break Interrupt + DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupt + DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Communication Interrupts + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare Interrupt + DCD TIM2_IRQHandler ; TIM2 Global Interrupt + DCD TIM16_IRQHandler ; TIM16 Global Interrupt + DCD TIM17_IRQHandler ; TIM17 Global Interrupt + DCD I2C1_EV_IRQHandler ; I2C1 Event Interrupt + DCD I2C1_ER_IRQHandler ; I2C1 Error Interrupt + DCD I2C2_EV_IRQHandler ; I2C2 Event Interrupt + DCD I2C2_ER_IRQHandler ; I2C2 Error Interrupt + DCD SPI1_IRQHandler ; SPI1 Interrupt + DCD SPI2_IRQHandler ; SPI2 Interrupt + DCD USART1_IRQHandler ; USART1 Interrupt + DCD USART2_IRQHandler ; USART2 Interrupt + DCD LPUART1_IRQHandler ; LPUART1 Interrupt + DCD LPTIM1_IRQHandler ; LPTIM1 Global Interrupt + DCD LPTIM2_IRQHandler ; LPTIM2 Global Interrupt + DCD EXTI15_10_IRQHandler ; EXTI Lines [15:10] Interrupt + DCD RTC_Alarm_IRQHandler ; RTC Alarms (A and B) Interrupt + DCD LPTIM3_IRQHandler ; LPTIM3 Global Interrupt + DCD SUBGHZSPI_IRQHandler ; SUBGHZSPI Interrupt + DCD IPCC_C1_RX_IRQHandler ; IPCC CPU1 RX occupied interrupt + DCD IPCC_C1_TX_IRQHandler ; IPCC CPU1 RX free interrupt + DCD HSEM_IRQHandler ; HSEM0 Interrupt + DCD I2C3_EV_IRQHandler ; I2C3 Event Interrupt + DCD I2C3_ER_IRQHandler ; I2C3 Error Interrupt + DCD SUBGHZ_Radio_IRQHandler ; SUBGHZ Radio Interrupt + DCD AES_IRQHandler ; AES Interrupt + DCD RNG_IRQHandler ; RNG1 Interrupt + DCD PKA_IRQHandler ; PKA Interrupt + DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 Interrupt + DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 Interrupt + DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 Interrupt + DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 Interrupt + DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 Interrupt + DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 Interrupt + DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 Interrupt + DCD DMAMUX1_OVR_IRQHandler ; DMAMUX overrun Interrupt + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + PUBWEAK PVD_PVM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PVD_PVM_IRQHandler + B PVD_PVM_IRQHandler + + PUBWEAK TAMP_STAMP_LSECSS_SSRU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TAMP_STAMP_LSECSS_SSRU_IRQHandler + B TAMP_STAMP_LSECSS_SSRU_IRQHandler + + PUBWEAK RTC_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_WKUP_IRQHandler + B RTC_WKUP_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RCC_IRQHandler + B RCC_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK DMA1_Channel1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel1_IRQHandler + B DMA1_Channel1_IRQHandler + + PUBWEAK DMA1_Channel2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel2_IRQHandler + B DMA1_Channel2_IRQHandler + + PUBWEAK DMA1_Channel3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel3_IRQHandler + B DMA1_Channel3_IRQHandler + + PUBWEAK DMA1_Channel4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel4_IRQHandler + B DMA1_Channel4_IRQHandler + + PUBWEAK DMA1_Channel5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel5_IRQHandler + B DMA1_Channel5_IRQHandler + + PUBWEAK DMA1_Channel6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel6_IRQHandler + B DMA1_Channel6_IRQHandler + + PUBWEAK DMA1_Channel7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel7_IRQHandler + B DMA1_Channel7_IRQHandler + + PUBWEAK ADC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC_IRQHandler + B ADC_IRQHandler + + PUBWEAK DAC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DAC_IRQHandler + B DAC_IRQHandler + + PUBWEAK C2SEV_PWR_C2H_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +C2SEV_PWR_C2H_IRQHandler + B C2SEV_PWR_C2H_IRQHandler + + PUBWEAK COMP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +COMP_IRQHandler + B COMP_IRQHandler + + PUBWEAK EXTI9_5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI9_5_IRQHandler + B EXTI9_5_IRQHandler + + PUBWEAK TIM1_BRK_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_BRK_IRQHandler + B TIM1_BRK_IRQHandler + + PUBWEAK TIM1_UP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_UP_IRQHandler + B TIM1_UP_IRQHandler + + PUBWEAK TIM1_TRG_COM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_TRG_COM_IRQHandler + B TIM1_TRG_COM_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + PUBWEAK TIM16_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM16_IRQHandler + B TIM16_IRQHandler + + PUBWEAK TIM17_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM17_IRQHandler + B TIM17_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK I2C2_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_EV_IRQHandler + B I2C2_EV_IRQHandler + + PUBWEAK I2C2_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_ER_IRQHandler + B I2C2_ER_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK LPUART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPUART1_IRQHandler + B LPUART1_IRQHandler + + PUBWEAK LPTIM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM1_IRQHandler + B LPTIM1_IRQHandler + + PUBWEAK LPTIM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM2_IRQHandler + B LPTIM2_IRQHandler + + PUBWEAK EXTI15_10_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI15_10_IRQHandler + B EXTI15_10_IRQHandler + + PUBWEAK RTC_Alarm_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_Alarm_IRQHandler + B RTC_Alarm_IRQHandler + + PUBWEAK LPTIM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM3_IRQHandler + B LPTIM3_IRQHandler + + PUBWEAK SUBGHZSPI_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SUBGHZSPI_IRQHandler + B SUBGHZSPI_IRQHandler + + PUBWEAK IPCC_C1_RX_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +IPCC_C1_RX_IRQHandler + B IPCC_C1_RX_IRQHandler + + PUBWEAK IPCC_C1_TX_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +IPCC_C1_TX_IRQHandler + B IPCC_C1_TX_IRQHandler + + PUBWEAK HSEM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HSEM_IRQHandler + B HSEM_IRQHandler + + PUBWEAK I2C3_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C3_EV_IRQHandler + B I2C3_EV_IRQHandler + + PUBWEAK I2C3_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C3_ER_IRQHandler + B I2C3_ER_IRQHandler + + PUBWEAK SUBGHZ_Radio_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SUBGHZ_Radio_IRQHandler + B SUBGHZ_Radio_IRQHandler + + PUBWEAK AES_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +AES_IRQHandler + B AES_IRQHandler + + PUBWEAK RNG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RNG_IRQHandler + B RNG_IRQHandler + + PUBWEAK PKA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PKA_IRQHandler + B PKA_IRQHandler + + PUBWEAK DMA2_Channel1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Channel1_IRQHandler + B DMA2_Channel1_IRQHandler + + PUBWEAK DMA2_Channel2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Channel2_IRQHandler + B DMA2_Channel2_IRQHandler + + PUBWEAK DMA2_Channel3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Channel3_IRQHandler + B DMA2_Channel3_IRQHandler + + PUBWEAK DMA2_Channel4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Channel4_IRQHandler + B DMA2_Channel4_IRQHandler + + PUBWEAK DMA2_Channel5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Channel5_IRQHandler + B DMA2_Channel5_IRQHandler + + PUBWEAK DMA2_Channel6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Channel6_IRQHandler + B DMA2_Channel6_IRQHandler + + PUBWEAK DMA2_Channel7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Channel7_IRQHandler + B DMA2_Channel7_IRQHandler + + PUBWEAK DMAMUX1_OVR_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMAMUX1_OVR_IRQHandler + B DMAMUX1_OVR_IRQHandler + + END diff --git a/EWARM/stm32wl55xx_flash_cm4.icf b/EWARM/stm32wl55xx_flash_cm4.icf new file mode 100644 index 0000000..9cf6f5a --- /dev/null +++ b/EWARM/stm32wl55xx_flash_cm4.icf @@ -0,0 +1,40 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x08000000; + +/*-Memory Regions-*/ +/***** FLASH *****/ +define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x0803FFFF; +/***** Non-backup SRAM1 *****/ +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x20007FFF; +/***** Backup SRAM2 *****/ +define symbol __ICFEDIT_region_RAM2_start__ = 0x20008000; +define symbol __ICFEDIT_region_RAM2_end__ = 0x2000FFFF; + +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x800; +define symbol __ICFEDIT_size_heap__ = 0x200; +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region RAM2_region = mem:[from __ICFEDIT_region_RAM2_start__ to __ICFEDIT_region_RAM2_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; +place in RAM2_region { }; diff --git a/MDK-ARM/SubGHz_Phy_Per.uvoptx b/MDK-ARM/SubGHz_Phy_Per.uvoptx new file mode 100644 index 0000000..15181b6 --- /dev/null +++ b/MDK-ARM/SubGHz_Phy_Per.uvoptx @@ -0,0 +1,921 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + SubGHz_Phy_Per + 0x4 + ARM-ADS + + 8000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 18 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 6 + + + + + + + + + + + STLink/ST-LINKIII-KEIL_SWO.dll + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + (105=-1,-1,-1,-1,0) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32WLxx_CM4 -FS08000000 -FL040000 -FP0($$Device:STM32WL55JCIx$CMSIS/Flash/STM32WLxx_CM4.FLM)) + + + 0 + ST-LINKIII-KEIL_SWO + -U-O142 -O2254 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -N00("ARM CoreSight SW-DP") -D00(6BA02477) -L00(0) -TO131090 -TC10000000 -TT10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32WLxx_CM4.FLM -FS08000000 -FL040000 -FP0($$Device:STM32WL55JCIx$CMSIS/Flash/STM32WLxx_CM4.FLM) + + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Application/MDK-ARM + 0 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + startup_stm32wl55xx_cm4.s + startup_stm32wl55xx_cm4.s + 0 + 0 + + + + + Application/User/Core + 0 + 0 + 0 + 0 + + 2 + 2 + 1 + 0 + 0 + 0 + ../Core/Src/main.c + main.c + 0 + 0 + + + 2 + 3 + 1 + 0 + 0 + 0 + ../Core/Src/gpio.c + gpio.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ../Core/Src/dma.c + dma.c + 0 + 0 + + + 2 + 5 + 1 + 0 + 0 + 0 + ../Core/Src/rtc.c + rtc.c + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + ../Core/Src/subghz.c + subghz.c + 0 + 0 + + + 2 + 7 + 1 + 0 + 0 + 0 + ../Core/Src/stm32_lpm_if.c + stm32_lpm_if.c + 0 + 0 + + + 2 + 8 + 1 + 0 + 0 + 0 + ../Core/Src/sys_app.c + sys_app.c + 0 + 0 + + + 2 + 9 + 1 + 0 + 0 + 0 + ../Core/Src/sys_debug.c + sys_debug.c + 0 + 0 + + + 2 + 10 + 1 + 0 + 0 + 0 + ../Core/Src/timer_if.c + timer_if.c + 0 + 0 + + + 2 + 11 + 1 + 0 + 0 + 0 + ../Core/Src/usart_if.c + usart_if.c + 0 + 0 + + + 2 + 12 + 1 + 0 + 0 + 0 + ../Core/Src/usart.c + usart.c + 0 + 0 + + + 2 + 13 + 1 + 0 + 0 + 0 + ../Core/Src/stm32wlxx_it.c + stm32wlxx_it.c + 0 + 0 + + + 2 + 14 + 1 + 0 + 0 + 0 + ../Core/Src/stm32wlxx_hal_msp.c + stm32wlxx_hal_msp.c + 0 + 0 + + + + + Application/User/SubGHz_Phy/App + 0 + 0 + 0 + 0 + + 3 + 15 + 1 + 0 + 0 + 0 + ../SubGHz_Phy/App/app_subghz_phy.c + app_subghz_phy.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + ../SubGHz_Phy/App/subghz_phy_app.c + subghz_phy_app.c + 0 + 0 + + + + + Application/User/SubGHz_Phy/Target + 0 + 0 + 0 + 0 + + 4 + 17 + 1 + 0 + 0 + 0 + ../SubGHz_Phy/Target/radio_board_if.c + radio_board_if.c + 0 + 0 + + + + + Doc + 0 + 0 + 0 + 0 + + 5 + 18 + 5 + 0 + 0 + 0 + ../readme.txt + readme.txt + 0 + 0 + + + + + Drivers/BSP/STM32WLxx_Nucleo + 0 + 0 + 0 + 0 + + 6 + 19 + 1 + 0 + 0 + 0 + ../Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo.c + stm32wlxx_nucleo.c + 0 + 0 + + + 6 + 20 + 1 + 0 + 0 + 0 + ../Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo_radio.c + stm32wlxx_nucleo_radio.c + 0 + 0 + + + + + Drivers/STM32WLxx_HAL_Driver + 0 + 0 + 0 + 0 + + 7 + 21 + 1 + 0 + 0 + 0 + ../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.c + stm32wlxx_hal_rcc.c + 0 + 0 + + + 7 + 22 + 1 + 0 + 0 + 0 + ../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.c + stm32wlxx_hal_rcc_ex.c + 0 + 0 + + + 7 + 23 + 1 + 0 + 0 + 0 + ../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash.c + stm32wlxx_hal_flash.c + 0 + 0 + + + 7 + 24 + 1 + 0 + 0 + 0 + ../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c + stm32wlxx_hal_flash_ex.c + 0 + 0 + + + 7 + 25 + 1 + 0 + 0 + 0 + ../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_gpio.c + stm32wlxx_hal_gpio.c + 0 + 0 + + + 7 + 26 + 1 + 0 + 0 + 0 + ../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.c + stm32wlxx_hal_dma.c + 0 + 0 + + + 7 + 27 + 1 + 0 + 0 + 0 + ../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma_ex.c + stm32wlxx_hal_dma_ex.c + 0 + 0 + + + 7 + 28 + 1 + 0 + 0 + 0 + ../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.c + stm32wlxx_hal_pwr.c + 0 + 0 + + + 7 + 29 + 1 + 0 + 0 + 0 + ../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c + stm32wlxx_hal_pwr_ex.c + 0 + 0 + + + 7 + 30 + 1 + 0 + 0 + 0 + ../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.c + stm32wlxx_hal_cortex.c + 0 + 0 + + + 7 + 31 + 1 + 0 + 0 + 0 + ../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c + stm32wlxx_hal.c + 0 + 0 + + + 7 + 32 + 1 + 0 + 0 + 0 + ../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_exti.c + stm32wlxx_hal_exti.c + 0 + 0 + + + 7 + 33 + 1 + 0 + 0 + 0 + ../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.c + stm32wlxx_hal_rtc.c + 0 + 0 + + + 7 + 34 + 1 + 0 + 0 + 0 + ../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c + stm32wlxx_hal_rtc_ex.c + 0 + 0 + + + 7 + 35 + 1 + 0 + 0 + 0 + ../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c + stm32wlxx_hal_subghz.c + 0 + 0 + + + 7 + 36 + 1 + 0 + 0 + 0 + ../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_tim.c + stm32wlxx_hal_tim.c + 0 + 0 + + + 7 + 37 + 1 + 0 + 0 + 0 + ../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_tim_ex.c + stm32wlxx_hal_tim_ex.c + 0 + 0 + + + 7 + 38 + 1 + 0 + 0 + 0 + ../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c + stm32wlxx_hal_uart.c + 0 + 0 + + + 7 + 39 + 1 + 0 + 0 + 0 + ../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.c + stm32wlxx_hal_uart_ex.c + 0 + 0 + + + + + Drivers/CMSIS + 0 + 0 + 0 + 0 + + 8 + 40 + 1 + 0 + 0 + 0 + ../Core/Src/system_stm32wlxx.c + system_stm32wlxx.c + 0 + 0 + + + + + Middlewares/SubGHz_Phy + 0 + 0 + 0 + 0 + + 9 + 41 + 1 + 0 + 0 + 0 + ../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.c + lr_fhss_mac.c + 0 + 0 + + + 9 + 42 + 1 + 0 + 0 + 0 + ../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c + radio.c + 0 + 0 + + + 9 + 43 + 1 + 0 + 0 + 0 + ../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c + radio_driver.c + 0 + 0 + + + 9 + 44 + 1 + 0 + 0 + 0 + ../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.c + radio_fw.c + 0 + 0 + + + 9 + 45 + 1 + 0 + 0 + 0 + ../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/wl_lr_fhss.c + wl_lr_fhss.c + 0 + 0 + + + + + Utilities + 0 + 0 + 0 + 0 + + 10 + 46 + 1 + 0 + 0 + 0 + ../Utilities/trace/adv_trace/stm32_adv_trace.c + stm32_adv_trace.c + 0 + 0 + + + 10 + 47 + 1 + 0 + 0 + 0 + ../Utilities/misc/stm32_mem.c + stm32_mem.c + 0 + 0 + + + 10 + 48 + 1 + 0 + 0 + 0 + ../Utilities/misc/stm32_systime.c + stm32_systime.c + 0 + 0 + + + 10 + 49 + 1 + 0 + 0 + 0 + ../Utilities/misc/stm32_tiny_sscanf.c + stm32_tiny_sscanf.c + 0 + 0 + + + 10 + 50 + 1 + 0 + 0 + 0 + ../Utilities/misc/stm32_tiny_vsnprintf.c + stm32_tiny_vsnprintf.c + 0 + 0 + + + 10 + 51 + 1 + 0 + 0 + 0 + ../Utilities/sequencer/stm32_seq.c + stm32_seq.c + 0 + 0 + + + 10 + 52 + 1 + 0 + 0 + 0 + ../Utilities/timer/stm32_timer.c + stm32_timer.c + 0 + 0 + + + 10 + 53 + 1 + 0 + 0 + 0 + ../Utilities/lpm/tiny_lpm/stm32_lpm.c + stm32_lpm.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/MDK-ARM/SubGHz_Phy_Per.uvprojx b/MDK-ARM/SubGHz_Phy_Per.uvprojx new file mode 100644 index 0000000..086f41e --- /dev/null +++ b/MDK-ARM/SubGHz_Phy_Per.uvprojx @@ -0,0 +1,718 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + SubGHz_Phy_Per + 0x4 + ARM-ADS + 6160000::V6.16::ARMCLANG + 1 + + + STM32WL55JCIx:CM4 + STMicroelectronics + Keil.STM32WLxx_DFP.1.1.1 + http://www.keil.com/pack/ + IRAM(0x20000000-0x20003FFF) IRAM2(0x20008000-0x2000BFFF) IROM(0x8000000-0x801FFFF) CLOCK(12000000) CPUTYPE("Cortex-M4") TZ + + + + 0 + + + + + + + + + + + $$Device:STM32WL55JCIx$CMSIS/SVD/STM32WL5x_CM4.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + SubGHz_Phy_Per\ + SubGHz_Phy_Per + 1 + 0 + 1 + 1 + 1 + + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 1 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 0 + + + SARMCM3.DLL + -REMAP -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4101 + + 1 + BIN/UL2V8M.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 1 + 1 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x4000 + + + 1 + 0x8000000 + 0x20000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x20000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x4000 + + + 0 + 0x20008000 + 0x4000 + + + + + + 1 + 7 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 3 + 0 + 0 + 1 + 0 + 0 + 5 + 3 + 0 + 0 + 0 + 0 + 0 + + -fshort-enums + CORE_CM4,USE_HAL_DRIVER,STM32WL55xx + + ../Core/Inc;../SubGHz_Phy/App;../SubGHz_Phy/Target;../Utilities/trace/adv_trace;../Drivers/STM32WLxx_HAL_Driver/Inc;../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy;../Utilities/misc;../Utilities/sequencer;../Utilities/timer;../Utilities/lpm/tiny_lpm;../Drivers/CMSIS/Device/ST/STM32WLxx/Include;../Middlewares/Third_Party/SubGHz_Phy;../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver;../Drivers/CMSIS/Include;../Drivers/BSP/STM32WLxx_Nucleo + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + + + + stm32wl55xx_flash_cm4.sct + + + + + + + + + + + Application/MDK-ARM + + + startup_stm32wl55xx_cm4.s + 2 + startup_stm32wl55xx_cm4.s + + + + + Application/User/Core + + + main.c + 1 + ../Core/Src/main.c + + + gpio.c + 1 + ../Core/Src/gpio.c + + + dma.c + 1 + ../Core/Src/dma.c + + + rtc.c + 1 + ../Core/Src/rtc.c + + + subghz.c + 1 + ../Core/Src/subghz.c + + + stm32_lpm_if.c + 1 + ../Core/Src/stm32_lpm_if.c + + + sys_app.c + 1 + ../Core/Src/sys_app.c + + + sys_debug.c + 1 + ../Core/Src/sys_debug.c + + + timer_if.c + 1 + ../Core/Src/timer_if.c + + + usart_if.c + 1 + ../Core/Src/usart_if.c + + + usart.c + 1 + ../Core/Src/usart.c + + + stm32wlxx_it.c + 1 + ../Core/Src/stm32wlxx_it.c + + + stm32wlxx_hal_msp.c + 1 + ../Core/Src/stm32wlxx_hal_msp.c + + + + + Application/User/SubGHz_Phy/App + + + app_subghz_phy.c + 1 + ../SubGHz_Phy/App/app_subghz_phy.c + + + subghz_phy_app.c + 1 + ../SubGHz_Phy/App/subghz_phy_app.c + + + + + Application/User/SubGHz_Phy/Target + + + radio_board_if.c + 1 + ../SubGHz_Phy/Target/radio_board_if.c + + + + + Doc + + + readme.txt + 5 + ../readme.txt + + + + + Drivers/BSP/STM32WLxx_Nucleo + + + stm32wlxx_nucleo.c + 1 + ../Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo.c + + + stm32wlxx_nucleo_radio.c + 1 + ../Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo_radio.c + + + + + Drivers/STM32WLxx_HAL_Driver + + + stm32wlxx_hal_rcc.c + 1 + ../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.c + + + stm32wlxx_hal_rcc_ex.c + 1 + ../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.c + + + stm32wlxx_hal_flash.c + 1 + ../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash.c + + + stm32wlxx_hal_flash_ex.c + 1 + ../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c + + + stm32wlxx_hal_gpio.c + 1 + ../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_gpio.c + + + stm32wlxx_hal_dma.c + 1 + ../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.c + + + stm32wlxx_hal_dma_ex.c + 1 + ../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma_ex.c + + + stm32wlxx_hal_pwr.c + 1 + ../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.c + + + stm32wlxx_hal_pwr_ex.c + 1 + ../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c + + + stm32wlxx_hal_cortex.c + 1 + ../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.c + + + stm32wlxx_hal.c + 1 + ../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c + + + stm32wlxx_hal_exti.c + 1 + ../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_exti.c + + + stm32wlxx_hal_rtc.c + 1 + ../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.c + + + stm32wlxx_hal_rtc_ex.c + 1 + ../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c + + + stm32wlxx_hal_subghz.c + 1 + ../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c + + + stm32wlxx_hal_tim.c + 1 + ../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_tim.c + + + stm32wlxx_hal_tim_ex.c + 1 + ../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_tim_ex.c + + + stm32wlxx_hal_uart.c + 1 + ../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c + + + stm32wlxx_hal_uart_ex.c + 1 + ../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.c + + + + + Drivers/CMSIS + + + system_stm32wlxx.c + 1 + ../Core/Src/system_stm32wlxx.c + + + + + Middlewares/SubGHz_Phy + + + lr_fhss_mac.c + 1 + ../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.c + + + radio.c + 1 + ../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c + + + radio_driver.c + 1 + ../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c + + + radio_fw.c + 1 + ../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.c + + + wl_lr_fhss.c + 1 + ../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/wl_lr_fhss.c + + + + + Utilities + + + stm32_adv_trace.c + 1 + ../Utilities/trace/adv_trace/stm32_adv_trace.c + + + stm32_mem.c + 1 + ../Utilities/misc/stm32_mem.c + + + stm32_systime.c + 1 + ../Utilities/misc/stm32_systime.c + + + stm32_tiny_sscanf.c + 1 + ../Utilities/misc/stm32_tiny_sscanf.c + + + stm32_tiny_vsnprintf.c + 1 + ../Utilities/misc/stm32_tiny_vsnprintf.c + + + stm32_seq.c + 1 + ../Utilities/sequencer/stm32_seq.c + + + stm32_timer.c + 1 + ../Utilities/timer/stm32_timer.c + + + stm32_lpm.c + 1 + ../Utilities/lpm/tiny_lpm/stm32_lpm.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/MDK-ARM/startup_stm32wl55xx_cm4.s b/MDK-ARM/startup_stm32wl55xx_cm4.s new file mode 100644 index 0000000..fc23aa2 --- /dev/null +++ b/MDK-ARM/startup_stm32wl55xx_cm4.s @@ -0,0 +1,363 @@ +;******************************************************************************** +;* File Name : startup_stm32wl55xx_cm4.s +;* Author : MCD Application Team +;* Description : STM32WL55xx devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************** +;* @attention +;* +;* Copyright (c) 2020-2021 STMicroelectronics. +;* All rights reserved. +;* +;* This software is licensed under terms that can be found in the LICENSE file +;* in the root directory of this software component. +;* If no LICENSE file comes with this software, it is provided AS-IS. +;* +;******************************************************************************** + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x800 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_PVM_IRQHandler ; PVD and PVM detector + DCD TAMP_STAMP_LSECSS_SSRU_IRQHandler ; RTC Tamper, RTC TimeStamp, LSECSS and RTC SSR Underflow Interrupts + DCD RTC_WKUP_IRQHandler ; RTC Wakeup Interrupt + DCD FLASH_IRQHandler ; FLASH global Interrupt + DCD RCC_IRQHandler ; RCC Interrupt + DCD EXTI0_IRQHandler ; EXTI Line 0 Interrupt + DCD EXTI1_IRQHandler ; EXTI Line 1 Interrupt + DCD EXTI2_IRQHandler ; EXTI Line 2 Interrupt + DCD EXTI3_IRQHandler ; EXTI Line 3 Interrupt + DCD EXTI4_IRQHandler ; EXTI Line 4 Interrupt + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 Interrupt + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 Interrupt + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 Interrupt + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 Interrupt + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 Interrupt + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 Interrupt + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 Interrupt + DCD ADC_IRQHandler ; ADC Interrupt + DCD DAC_IRQHandler ; DAC Interrupt + DCD C2SEV_PWR_C2H_IRQHandler ; CPU M0+ SEV and PWR CPU M0+ HOLD wakeup Interrupt + DCD COMP_IRQHandler ; COMP1 and COMP2 Interrupts + DCD EXTI9_5_IRQHandler ; EXTI Lines [9:5] Interrupt + DCD TIM1_BRK_IRQHandler ; TIM1 Break Interrupt + DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupts + DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Communication Interrupts + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare Interrupt + DCD TIM2_IRQHandler ; TIM2 Global Interrupt + DCD TIM16_IRQHandler ; TIM16 Global Interrupt + DCD TIM17_IRQHandler ; TIM17 Global Interrupt + DCD I2C1_EV_IRQHandler ; I2C1 Event Interrupt + DCD I2C1_ER_IRQHandler ; I2C1 Error Interrupt + DCD I2C2_EV_IRQHandler ; I2C2 Event Interrupt + DCD I2C2_ER_IRQHandler ; I2C2 Error Interrupt + DCD SPI1_IRQHandler ; SPI1 Interrupt + DCD SPI2_IRQHandler ; SPI2 Interrupt + DCD USART1_IRQHandler ; USART1 Interrupt + DCD USART2_IRQHandler ; USART2 Interrupt + DCD LPUART1_IRQHandler ; LPUART1 Interrupt + DCD LPTIM1_IRQHandler ; LPTIM1 Interrupt + DCD LPTIM2_IRQHandler ; LPTIM2 Interrupt + DCD EXTI15_10_IRQHandler ; EXTI Lines1[15:10 ]Interrupts + DCD RTC_Alarm_IRQHandler ; RTC Alarms (A and B) Interrupt + DCD LPTIM3_IRQHandler ; LPTIM3 Interrupt + DCD SUBGHZSPI_IRQHandler ; SUBGHZSPI Interrupt + DCD IPCC_C1_RX_IRQHandler ; IPCC CPU1 RX occupied interrupt + DCD IPCC_C1_TX_IRQHandler ; IPCC CPU1 RX free interrupt + DCD HSEM_IRQHandler ; HSEM0 Interrupt + DCD I2C3_EV_IRQHandler ; I2C3 Event Interrupt + DCD I2C3_ER_IRQHandler ; I2C3 Error Interrupt + DCD SUBGHZ_Radio_IRQHandler ; SUBGHZ Radio Interrupt + DCD AES_IRQHandler ; AES Interrupt + DCD RNG_IRQHandler ; RNG1 Interrupt + DCD PKA_IRQHandler ; PKA Interrupt + DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 Interrupt + DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 Interrupt + DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 Interrupt + DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 Interrupt + DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 Interrupt + DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 Interrupt + DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 Interrupt + DCD DMAMUX1_OVR_IRQHandler ; DMAMUX overrun Interrupt + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_PVM_IRQHandler [WEAK] + EXPORT TAMP_STAMP_LSECSS_SSRU_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT DMA1_Channel5_IRQHandler [WEAK] + EXPORT DMA1_Channel6_IRQHandler [WEAK] + EXPORT DMA1_Channel7_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT DAC_IRQHandler [WEAK] + EXPORT C2SEV_PWR_C2H_IRQHandler [WEAK] + EXPORT COMP_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_IRQHandler [WEAK] + EXPORT TIM1_UP_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM16_IRQHandler [WEAK] + EXPORT TIM17_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT LPUART1_IRQHandler [WEAK] + EXPORT LPTIM1_IRQHandler [WEAK] + EXPORT LPTIM2_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT LPTIM3_IRQHandler [WEAK] + EXPORT SUBGHZSPI_IRQHandler [WEAK] + EXPORT IPCC_C1_RX_IRQHandler [WEAK] + EXPORT IPCC_C1_TX_IRQHandler [WEAK] + EXPORT HSEM_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT SUBGHZ_Radio_IRQHandler [WEAK] + EXPORT AES_IRQHandler [WEAK] + EXPORT RNG_IRQHandler [WEAK] + EXPORT PKA_IRQHandler [WEAK] + EXPORT DMA2_Channel1_IRQHandler [WEAK] + EXPORT DMA2_Channel2_IRQHandler [WEAK] + EXPORT DMA2_Channel3_IRQHandler [WEAK] + EXPORT DMA2_Channel4_IRQHandler [WEAK] + EXPORT DMA2_Channel5_IRQHandler [WEAK] + EXPORT DMA2_Channel6_IRQHandler [WEAK] + EXPORT DMA2_Channel7_IRQHandler [WEAK] + EXPORT DMAMUX1_OVR_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_PVM_IRQHandler +TAMP_STAMP_LSECSS_SSRU_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +DMA1_Channel5_IRQHandler +DMA1_Channel6_IRQHandler +DMA1_Channel7_IRQHandler +ADC_IRQHandler +DAC_IRQHandler +C2SEV_PWR_C2H_IRQHandler +COMP_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_IRQHandler +TIM1_UP_IRQHandler +TIM1_TRG_COM_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM16_IRQHandler +TIM17_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +LPUART1_IRQHandler +LPTIM1_IRQHandler +LPTIM2_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +LPTIM3_IRQHandler +SUBGHZSPI_IRQHandler +IPCC_C1_RX_IRQHandler +IPCC_C1_TX_IRQHandler +HSEM_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +SUBGHZ_Radio_IRQHandler +AES_IRQHandler +RNG_IRQHandler +PKA_IRQHandler +DMA2_Channel1_IRQHandler +DMA2_Channel2_IRQHandler +DMA2_Channel3_IRQHandler +DMA2_Channel4_IRQHandler +DMA2_Channel5_IRQHandler +DMA2_Channel6_IRQHandler +DMA2_Channel7_IRQHandler +DMAMUX1_OVR_IRQHandler + + B . + + ENDP + + ALIGN + +;******************************************************************************** +; User Stack and Heap initialization +;******************************************************************************** + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/MDK-ARM/stm32wl55xx_flash_cm4.sct b/MDK-ARM/stm32wl55xx_flash_cm4.sct new file mode 100644 index 0000000..574c8f1 --- /dev/null +++ b/MDK-ARM/stm32wl55xx_flash_cm4.sct @@ -0,0 +1,19 @@ +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + +LR_IROM1 0x08000000 0x00040000 { ; load region size_region + ; FLASH + ER_IROM1 0x08000000 0x00040000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + ; Non-backup SRAM1 + RW_IRAM1 0x20000000 0x00008000 { ; RW data + .ANY (+RW +ZI) + } + ; Backup SRAM2 + RW_IRAM2 0x20008000 EMPTY 0x00008000 { ; to be modified accordingly to user project. Can be NoInit data for backup usage, RW, ZI region, etc... + } +} diff --git a/Middlewares/Third_Party/SubGHz_Phy/LICENSE b/Middlewares/Third_Party/SubGHz_Phy/LICENSE new file mode 100644 index 0000000..1a60a54 --- /dev/null +++ b/Middlewares/Third_Party/SubGHz_Phy/LICENSE @@ -0,0 +1,27 @@ +The Clear BSD License +Copyright Semtech Corporation 2021. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted (subject to the limitations in the disclaimer +below) provided that the following conditions are met: + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + * Neither the name of the Semtech corporation nor the + names of its contributors may be used to endorse or promote products + derived from this software without specific prior written permission. + +NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY +THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND +CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT +NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL SEMTECH CORPORATION BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. \ No newline at end of file diff --git a/Middlewares/Third_Party/SubGHz_Phy/Release_Notes.html b/Middlewares/Third_Party/SubGHz_Phy/Release_Notes.html new file mode 100644 index 0000000..3a3931c --- /dev/null +++ b/Middlewares/Third_Party/SubGHz_Phy/Release_Notes.html @@ -0,0 +1,141 @@ + + + + + + + Release Notes for STM32WLxx SubGHz Physical Layer Middleware + + + + + + +
+
+
+

Release Notes for

+

STM32WLxx SubGHz Physical Layer Middleware

+

Copyright © 2021 STMicroelectronics
+

+ +
+

Purpose

+

This Middleware provides the SubGHz Physical Layer for the stm32wlxx products. This covers

+
    +
  • STM32WLxx devices
    • +
+

This driver is composed of the radio driver and radio interface under “stm32_radio_driver” directory.

+
+
+

Update History

+
+ +
+

Main Changes

+
    +
  • Fix: Application hangs because MBMUXIF_LoraSendCmd() command stuck
    • +
  • Fix: typo in setting MaxPayloadLength for GENERIC_LORA in RadioSetRxGenericConfig
    • +
  • Release Notes update
    • +
+

Known limitations:

+

None

+
+
+
+ +
+

Main Changes

+
    +
  • Feature: 169MHz validation support
    • +
  • Feature: Add LoRa-E support (LR-FHSS)
    • +
  • Feature: RF output optimization
    • +
  • Chore: Sync Word register addresses not matching Semtech SX1261/2 datasheet
    • +
  • Fix: SUBGHz GCFO registers not in line with the RM
    • +
  • Fix: AGC of radio stuck when jammed
    • +
  • Release Notes update
    • +
+

Known limitations:

+

None

+
+
+
+ +
+

Main Changes

+
    +
  • Feature: Add defines RADIO_SIGFOX_ENABLE and RADIO_GENERIC_CONFIG_ENABLE to reduce code size when not needed
    • +
  • Feature: Add Tx GMSK support
    • +
  • Chore: Align register names with Reference Manual
    • +
  • Chore: Clarify node/broadcast address
    • +
  • Fix: Set_RxDutyCycle() function (Rx timeout Issue)
    • +
  • Licensing update: New way to declare licenses
    • +
  • Release Notes update
    • +
+

Known limitations:

+

None

+
+
+
+ +
+

Main Changes

+
    +
  • fix: SMPS drive level init
    • +
  • fix: GENERIC_BPSK in RadioSetTxGenericConfig function (test mode)
    • +
  • fix: MODEM_BPSK is not handled in RadioSetModem in radio.c
    • +
  • feature: add cfo calculation
    • +
  • fix: reduce interrupt scope to minimize privilege stack code execution
    • +
  • feature:add long packet in radio_fw
    • +
  • feature: Support IBM whitening by firmware radio_fw
    • +
  • fix: Channel Activity Detection: antenna switch set in rx mode
    • +
  • fix: Deadlock of WL RF driver
    • +
  • fix: PingPong RxErrors when SF12, BW500, CR 4/8
    • +
  • feature: move GetFskBandwidthRegValue in radio_driver
    • +
  • fix: Incorrect LoRa PER Results
    • +
  • feature: align to LoRaWAN Semtech stack v4.4.7 integration - Radio Part
    • +
+

Known limitations:

+

None

+
+
+
+ +
+

Main Changes

+
    +
  • First Release
    • +
+

Known limitations:

+

None

+
+
+
+
+
+
+
+

For complete documentation on STM32WLxx, visit: www.st.com/stm32wl

+

This release note uses up to date web standards and, for this reason, should not be opened with Internet Explorer but preferably with popular browsers such as Google Chrome, Mozilla Firefox, Opera or Microsoft Edge.

+
+

Info

+
+
+
+ + diff --git a/Middlewares/Third_Party/SubGHz_Phy/_htmresc/Add button.svg b/Middlewares/Third_Party/SubGHz_Phy/_htmresc/Add button.svg new file mode 100644 index 0000000..c211545 --- /dev/null +++ b/Middlewares/Third_Party/SubGHz_Phy/_htmresc/Add button.svg @@ -0,0 +1,2 @@ + + diff --git a/Middlewares/Third_Party/SubGHz_Phy/_htmresc/Update.svg b/Middlewares/Third_Party/SubGHz_Phy/_htmresc/Update.svg new file mode 100644 index 0000000..f88381f --- /dev/null +++ b/Middlewares/Third_Party/SubGHz_Phy/_htmresc/Update.svg @@ -0,0 +1,2 @@ + + diff --git a/Middlewares/Third_Party/SubGHz_Phy/_htmresc/favicon.png b/Middlewares/Third_Party/SubGHz_Phy/_htmresc/favicon.png new file mode 100644 index 0000000..06713ee Binary files /dev/null and b/Middlewares/Third_Party/SubGHz_Phy/_htmresc/favicon.png differ diff --git a/Middlewares/Third_Party/SubGHz_Phy/_htmresc/mini-st_2020.css b/Middlewares/Third_Party/SubGHz_Phy/_htmresc/mini-st_2020.css new file mode 100644 index 0000000..986f4d4 --- /dev/null +++ b/Middlewares/Third_Party/SubGHz_Phy/_htmresc/mini-st_2020.css @@ -0,0 +1,1711 @@ +@charset "UTF-8"; +/* + Flavor name: Custom (mini-custom) + Generated online - https://minicss.org/flavors + mini.css version: v3.0.1 +*/ +/* + Browsers resets and base typography. +*/ +/* Core module CSS variable definitions */ +:root { + --fore-color: #03234b; + --secondary-fore-color: #03234b; + --back-color: #ffffff; + --secondary-back-color: #ffffff; + --blockquote-color: #e6007e; + --pre-color: #e6007e; + --border-color: #3cb4e6; + --secondary-border-color: #3cb4e6; + --heading-ratio: 1.2; + --universal-margin: 0.5rem; + --universal-padding: 0.25rem; + --universal-border-radius: 0.075rem; + --background-margin: 1.5%; + --a-link-color: #3cb4e6; + --a-visited-color: #8c0078; } + +html { + font-size: 13.5px; } + +a, b, del, em, i, ins, q, span, strong, u { + font-size: 1em; } + +html, * { + font-family: -apple-system, BlinkMacSystemFont, Helvetica, arial, sans-serif; + line-height: 1.25; + -webkit-text-size-adjust: 100%; } + +* { + font-size: 1rem; } + +body { + margin: 0; + color: var(--fore-color); + @background: var(--back-color); + background: var(--back-color) linear-gradient(#ffd200, #ffd200) repeat-y left top; + background-size: var(--background-margin); + } + +details { + display: block; } + +summary { + display: list-item; } + +abbr[title] { + border-bottom: none; + text-decoration: underline dotted; } + +input { + overflow: visible; } + +img { + max-width: 100%; + height: auto; } + +h1, h2, h3, h4, h5, h6 { + line-height: 1.25; + margin: calc(1.5 * var(--universal-margin)) var(--universal-margin); + font-weight: 400; } + h1 small, h2 small, h3 small, h4 small, h5 small, h6 small { + color: var(--secondary-fore-color); + display: block; + margin-top: -0.25rem; } + +h1 { + font-size: calc(1rem * var(--heading-ratio) * var(--heading-ratio) * var(--heading-ratio)); } + +h2 { + font-size: calc(1rem * var(--heading-ratio) * var(--heading-ratio) ); + border-style: none none solid none ; + border-width: thin; + border-color: var(--border-color); } +h3 { + font-size: calc(1rem * var(--heading-ratio) ); } + +h4 { + font-size: calc(1rem * var(--heading-ratio)); } + +h5 { + font-size: 1rem; } + +h6 { + font-size: calc(1rem / var(--heading-ratio)); } + +p { + margin: var(--universal-margin); } + +ol, ul { + margin: var(--universal-margin); + padding-left: calc(3 * var(--universal-margin)); } + +b, strong { + font-weight: 700; } + +hr { + box-sizing: content-box; + border: 0; + line-height: 1.25em; + margin: var(--universal-margin); + height: 0.0714285714rem; + background: linear-gradient(to right, transparent, var(--border-color) 20%, var(--border-color) 80%, transparent); } + +blockquote { + display: block; + position: relative; + font-style: italic; + color: var(--secondary-fore-color); + margin: var(--universal-margin); + padding: calc(3 * var(--universal-padding)); + border: 0.0714285714rem solid var(--secondary-border-color); + border-left: 0.3rem solid var(--blockquote-color); + border-radius: 0 var(--universal-border-radius) var(--universal-border-radius) 0; } + blockquote:before { + position: absolute; + top: calc(0rem - var(--universal-padding)); + left: 0; + font-family: sans-serif; + font-size: 2rem; + font-weight: 800; + content: "\201c"; + color: var(--blockquote-color); } + blockquote[cite]:after { + font-style: normal; + font-size: 0.75em; + font-weight: 700; + content: "\a— " attr(cite); + white-space: pre; } + +code, kbd, pre, samp { + font-family: Menlo, Consolas, monospace; + font-size: 0.85em; } + +code { + background: var(--secondary-back-color); + border-radius: var(--universal-border-radius); + padding: calc(var(--universal-padding) / 4) calc(var(--universal-padding) / 2); } + +kbd { + background: var(--fore-color); + color: var(--back-color); + border-radius: var(--universal-border-radius); + padding: calc(var(--universal-padding) / 4) calc(var(--universal-padding) / 2); } + +pre { + overflow: auto; + background: var(--secondary-back-color); + padding: calc(1.5 * var(--universal-padding)); + margin: var(--universal-margin); + border: 0.0714285714rem solid var(--secondary-border-color); + border-left: 0.2857142857rem solid var(--pre-color); + border-radius: 0 var(--universal-border-radius) var(--universal-border-radius) 0; } + +sup, sub, code, kbd { + line-height: 0; + position: relative; + vertical-align: baseline; } + +small, sup, sub, figcaption { + font-size: 0.75em; } + +sup { + top: -0.5em; } + +sub { + bottom: -0.25em; } + +figure { + margin: var(--universal-margin); } + +figcaption { + color: var(--secondary-fore-color); } + +a { + text-decoration: none; } + a:link { + color: var(--a-link-color); } + a:visited { + color: var(--a-visited-color); } + a:hover, a:focus { + text-decoration: underline; } + +/* + Definitions for the grid system, cards and containers. +*/ +.container { + margin: 0 auto; + padding: 0 calc(1.5 * var(--universal-padding)); } + +.row { + box-sizing: border-box; + display: flex; + flex: 0 1 auto; + flex-flow: row wrap; + margin: 0 0 0 var(--background-margin); } + +.col-sm, +[class^='col-sm-'], +[class^='col-sm-offset-'], +.row[class*='cols-sm-'] > * { + box-sizing: border-box; + flex: 0 0 auto; + padding: 0 calc(var(--universal-padding) / 2); } + +.col-sm, +.row.cols-sm > * { + max-width: 100%; + flex-grow: 1; + flex-basis: 0; } + +.col-sm-1, +.row.cols-sm-1 > * { + max-width: 8.3333333333%; + flex-basis: 8.3333333333%; } + +.col-sm-offset-0 { + margin-left: 0; } + +.col-sm-2, +.row.cols-sm-2 > * { + max-width: 16.6666666667%; + flex-basis: 16.6666666667%; } + +.col-sm-offset-1 { + margin-left: 8.3333333333%; } + +.col-sm-3, +.row.cols-sm-3 > * { + max-width: 25%; + flex-basis: 25%; } + +.col-sm-offset-2 { + margin-left: 16.6666666667%; } + +.col-sm-4, +.row.cols-sm-4 > * { + max-width: 33.3333333333%; + flex-basis: 33.3333333333%; } + +.col-sm-offset-3 { + margin-left: 25%; } + +.col-sm-5, +.row.cols-sm-5 > * { + max-width: 41.6666666667%; + flex-basis: 41.6666666667%; } + +.col-sm-offset-4 { + margin-left: 33.3333333333%; } + +.col-sm-6, +.row.cols-sm-6 > * { + max-width: 50%; + flex-basis: 50%; } + +.col-sm-offset-5 { + margin-left: 41.6666666667%; } + +.col-sm-7, +.row.cols-sm-7 > * { + max-width: 58.3333333333%; + flex-basis: 58.3333333333%; } + +.col-sm-offset-6 { + margin-left: 50%; } + +.col-sm-8, +.row.cols-sm-8 > * { + max-width: 66.6666666667%; + flex-basis: 66.6666666667%; } + +.col-sm-offset-7 { + margin-left: 58.3333333333%; } + +.col-sm-9, +.row.cols-sm-9 > * { + max-width: 75%; + flex-basis: 75%; } + +.col-sm-offset-8 { + margin-left: 66.6666666667%; } + +.col-sm-10, +.row.cols-sm-10 > * { + max-width: 83.3333333333%; + flex-basis: 83.3333333333%; } + +.col-sm-offset-9 { + margin-left: 75%; } + +.col-sm-11, +.row.cols-sm-11 > * { + max-width: 91.6666666667%; + flex-basis: 91.6666666667%; } + +.col-sm-offset-10 { + margin-left: 83.3333333333%; } + +.col-sm-12, +.row.cols-sm-12 > * { + max-width: 100%; + flex-basis: 100%; } + +.col-sm-offset-11 { + margin-left: 91.6666666667%; } + +.col-sm-normal { + order: initial; } + +.col-sm-first { + order: -999; } + +.col-sm-last { + order: 999; } + +@media screen and (min-width: 500px) { + .col-md, + [class^='col-md-'], + [class^='col-md-offset-'], + .row[class*='cols-md-'] > * { + box-sizing: border-box; + flex: 0 0 auto; + padding: 0 calc(var(--universal-padding) / 2); } + + .col-md, + .row.cols-md > * { + max-width: 100%; + flex-grow: 1; + flex-basis: 0; } + + .col-md-1, + .row.cols-md-1 > * { + max-width: 8.3333333333%; + flex-basis: 8.3333333333%; } + + .col-md-offset-0 { + margin-left: 0; } + + .col-md-2, + .row.cols-md-2 > * { + max-width: 16.6666666667%; + flex-basis: 16.6666666667%; } + + .col-md-offset-1 { + margin-left: 8.3333333333%; } + + .col-md-3, + .row.cols-md-3 > * { + max-width: 25%; + flex-basis: 25%; } + + .col-md-offset-2 { + margin-left: 16.6666666667%; } + + .col-md-4, + .row.cols-md-4 > * { + max-width: 33.3333333333%; + flex-basis: 33.3333333333%; } + + .col-md-offset-3 { + margin-left: 25%; } + + .col-md-5, + .row.cols-md-5 > * { + max-width: 41.6666666667%; + flex-basis: 41.6666666667%; } + + .col-md-offset-4 { + margin-left: 33.3333333333%; } + + .col-md-6, + .row.cols-md-6 > * { + max-width: 50%; + flex-basis: 50%; } + + .col-md-offset-5 { + margin-left: 41.6666666667%; } + + .col-md-7, + .row.cols-md-7 > * { + max-width: 58.3333333333%; + flex-basis: 58.3333333333%; } + + .col-md-offset-6 { + margin-left: 50%; } + + .col-md-8, + .row.cols-md-8 > * { + max-width: 66.6666666667%; + flex-basis: 66.6666666667%; } + + .col-md-offset-7 { + margin-left: 58.3333333333%; } + + .col-md-9, + .row.cols-md-9 > * { + max-width: 75%; + flex-basis: 75%; } + + .col-md-offset-8 { + margin-left: 66.6666666667%; } + + .col-md-10, + .row.cols-md-10 > * { + max-width: 83.3333333333%; + flex-basis: 83.3333333333%; } + + .col-md-offset-9 { + margin-left: 75%; } + + .col-md-11, + .row.cols-md-11 > * { + max-width: 91.6666666667%; + flex-basis: 91.6666666667%; } + + .col-md-offset-10 { + margin-left: 83.3333333333%; } + + .col-md-12, + .row.cols-md-12 > * { + max-width: 100%; + flex-basis: 100%; } + + .col-md-offset-11 { + margin-left: 91.6666666667%; } + + .col-md-normal { + order: initial; } + + .col-md-first { + order: -999; } + + .col-md-last { + order: 999; } } +@media screen and (min-width: 1280px) { + .col-lg, + [class^='col-lg-'], + [class^='col-lg-offset-'], + .row[class*='cols-lg-'] > * { + box-sizing: border-box; + flex: 0 0 auto; + padding: 0 calc(var(--universal-padding) / 2); } + + .col-lg, + .row.cols-lg > * { + max-width: 100%; + flex-grow: 1; + flex-basis: 0; } + + .col-lg-1, + .row.cols-lg-1 > * { + max-width: 8.3333333333%; + flex-basis: 8.3333333333%; } + + .col-lg-offset-0 { + margin-left: 0; } + + .col-lg-2, + .row.cols-lg-2 > * { + max-width: 16.6666666667%; + flex-basis: 16.6666666667%; } + + .col-lg-offset-1 { + margin-left: 8.3333333333%; } + + .col-lg-3, + .row.cols-lg-3 > * { + max-width: 25%; + flex-basis: 25%; } + + .col-lg-offset-2 { + margin-left: 16.6666666667%; } + + .col-lg-4, + .row.cols-lg-4 > * { + max-width: 33.3333333333%; + flex-basis: 33.3333333333%; } + + .col-lg-offset-3 { + margin-left: 25%; } + + .col-lg-5, + .row.cols-lg-5 > * { + max-width: 41.6666666667%; + flex-basis: 41.6666666667%; } + + .col-lg-offset-4 { + margin-left: 33.3333333333%; } + + .col-lg-6, + .row.cols-lg-6 > * { + max-width: 50%; + flex-basis: 50%; } + + .col-lg-offset-5 { + margin-left: 41.6666666667%; } + + .col-lg-7, + .row.cols-lg-7 > * { + max-width: 58.3333333333%; + flex-basis: 58.3333333333%; } + + .col-lg-offset-6 { + margin-left: 50%; } + + .col-lg-8, + .row.cols-lg-8 > * { + max-width: 66.6666666667%; + flex-basis: 66.6666666667%; } + + .col-lg-offset-7 { + margin-left: 58.3333333333%; } + + .col-lg-9, + .row.cols-lg-9 > * { + max-width: 75%; + flex-basis: 75%; } + + .col-lg-offset-8 { + margin-left: 66.6666666667%; } + + .col-lg-10, + .row.cols-lg-10 > * { + max-width: 83.3333333333%; + flex-basis: 83.3333333333%; } + + .col-lg-offset-9 { + margin-left: 75%; } + + .col-lg-11, + .row.cols-lg-11 > * { + max-width: 91.6666666667%; + flex-basis: 91.6666666667%; } + + .col-lg-offset-10 { + margin-left: 83.3333333333%; } + + .col-lg-12, + .row.cols-lg-12 > * { + max-width: 100%; + flex-basis: 100%; } + + .col-lg-offset-11 { + margin-left: 91.6666666667%; } + + .col-lg-normal { + order: initial; } + + .col-lg-first { + order: -999; } + + .col-lg-last { + order: 999; } } +/* Card component CSS variable definitions */ +:root { + --card-back-color: #3cb4e6; + --card-fore-color: #03234b; + --card-border-color: #03234b; } + +.card { + display: flex; + flex-direction: column; + justify-content: space-between; + align-self: center; + position: relative; + width: 100%; + background: var(--card-back-color); + color: var(--card-fore-color); + border: 0.0714285714rem solid var(--card-border-color); + border-radius: var(--universal-border-radius); + margin: var(--universal-margin); + overflow: hidden; } + @media screen and (min-width: 320px) { + .card { + max-width: 320px; } } + .card > .sectione { + background: var(--card-back-color); + color: var(--card-fore-color); + box-sizing: border-box; + margin: 0; + border: 0; + border-radius: 0; + border-bottom: 0.0714285714rem solid var(--card-border-color); + padding: var(--universal-padding); + width: 100%; } + .card > .sectione.media { + height: 200px; + padding: 0; + -o-object-fit: cover; + object-fit: cover; } + .card > .sectione:last-child { + border-bottom: 0; } + +/* + Custom elements for card elements. +*/ +@media screen and (min-width: 240px) { + .card.small { + max-width: 240px; } } +@media screen and (min-width: 480px) { + .card.large { + max-width: 480px; } } +.card.fluid { + max-width: 100%; + width: auto; } + +.card.warning { + --card-back-color: #e5b8b7; + --card-fore-color: #3b234b; + --card-border-color: #8c0078; } + +.card.error { + --card-back-color: #464650; + --card-fore-color: #ffffff; + --card-border-color: #8c0078; } + +.card > .sectione.dark { + --card-back-color: #3b234b; + --card-fore-color: #ffffff; } + +.card > .sectione.double-padded { + padding: calc(1.5 * var(--universal-padding)); } + +/* + Definitions for forms and input elements. +*/ +/* Input_control module CSS variable definitions */ +:root { + --form-back-color: #ffe97f; + --form-fore-color: #03234b; + --form-border-color: #3cb4e6; + --input-back-color: #ffffff; + --input-fore-color: #03234b; + --input-border-color: #3cb4e6; + --input-focus-color: #0288d1; + --input-invalid-color: #d32f2f; + --button-back-color: #e2e2e2; + --button-hover-back-color: #dcdcdc; + --button-fore-color: #212121; + --button-border-color: transparent; + --button-hover-border-color: transparent; + --button-group-border-color: rgba(124, 124, 124, 0.54); } + +form { + background: var(--form-back-color); + color: var(--form-fore-color); + border: 0.0714285714rem solid var(--form-border-color); + border-radius: var(--universal-border-radius); + margin: var(--universal-margin); + padding: calc(2 * var(--universal-padding)) var(--universal-padding); } + +fieldset { + border: 0.0714285714rem solid var(--form-border-color); + border-radius: var(--universal-border-radius); + margin: calc(var(--universal-margin) / 4); + padding: var(--universal-padding); } + +legend { + box-sizing: border-box; + display: table; + max-width: 100%; + white-space: normal; + font-weight: 500; + padding: calc(var(--universal-padding) / 2); } + +label { + padding: calc(var(--universal-padding) / 2) var(--universal-padding); } + +.input-group { + display: inline-block; } + .input-group.fluid { + display: flex; + align-items: center; + justify-content: center; } + .input-group.fluid > input { + max-width: 100%; + flex-grow: 1; + flex-basis: 0px; } + @media screen and (max-width: 499px) { + .input-group.fluid { + align-items: stretch; + flex-direction: column; } } + .input-group.vertical { + display: flex; + align-items: stretch; + flex-direction: column; } + .input-group.vertical > input { + max-width: 100%; + flex-grow: 1; + flex-basis: 0px; } + +[type="number"]::-webkit-inner-spin-button, [type="number"]::-webkit-outer-spin-button { + height: auto; } + +[type="search"] { + -webkit-appearance: textfield; + outline-offset: -2px; } + +[type="search"]::-webkit-search-cancel-button, +[type="search"]::-webkit-search-decoration { + -webkit-appearance: none; } + +input:not([type]), [type="text"], [type="email"], [type="number"], [type="search"], +[type="password"], [type="url"], [type="tel"], [type="checkbox"], [type="radio"], textarea, select { + box-sizing: border-box; + background: var(--input-back-color); + color: var(--input-fore-color); + border: 0.0714285714rem solid var(--input-border-color); + border-radius: var(--universal-border-radius); + margin: calc(var(--universal-margin) / 2); + padding: var(--universal-padding) calc(1.5 * var(--universal-padding)); } + +input:not([type="button"]):not([type="submit"]):not([type="reset"]):hover, input:not([type="button"]):not([type="submit"]):not([type="reset"]):focus, textarea:hover, textarea:focus, select:hover, select:focus { + border-color: var(--input-focus-color); + box-shadow: none; } +input:not([type="button"]):not([type="submit"]):not([type="reset"]):invalid, input:not([type="button"]):not([type="submit"]):not([type="reset"]):focus:invalid, textarea:invalid, textarea:focus:invalid, select:invalid, select:focus:invalid { + border-color: var(--input-invalid-color); + box-shadow: none; } +input:not([type="button"]):not([type="submit"]):not([type="reset"])[readonly], textarea[readonly], select[readonly] { + background: var(--secondary-back-color); } + +select { + max-width: 100%; } + +option { + overflow: hidden; + text-overflow: ellipsis; } + +[type="checkbox"], [type="radio"] { + -webkit-appearance: none; + -moz-appearance: none; + appearance: none; + position: relative; + height: calc(1rem + var(--universal-padding) / 2); + width: calc(1rem + var(--universal-padding) / 2); + vertical-align: text-bottom; + padding: 0; + flex-basis: calc(1rem + var(--universal-padding) / 2) !important; + flex-grow: 0 !important; } + [type="checkbox"]:checked:before, [type="radio"]:checked:before { + position: absolute; } + +[type="checkbox"]:checked:before { + content: '\2713'; + font-family: sans-serif; + font-size: calc(1rem + var(--universal-padding) / 2); + top: calc(0rem - var(--universal-padding)); + left: calc(var(--universal-padding) / 4); } + +[type="radio"] { + border-radius: 100%; } + [type="radio"]:checked:before { + border-radius: 100%; + content: ''; + top: calc(0.0714285714rem + var(--universal-padding) / 2); + left: calc(0.0714285714rem + var(--universal-padding) / 2); + background: var(--input-fore-color); + width: 0.5rem; + height: 0.5rem; } + +:placeholder-shown { + color: var(--input-fore-color); } + +::-ms-placeholder { + color: var(--input-fore-color); + opacity: 0.54; } + +button::-moz-focus-inner, [type="button"]::-moz-focus-inner, [type="reset"]::-moz-focus-inner, [type="submit"]::-moz-focus-inner { + border-style: none; + padding: 0; } + +button, html [type="button"], [type="reset"], [type="submit"] { + -webkit-appearance: button; } + +button { + overflow: visible; + text-transform: none; } + +button, [type="button"], [type="submit"], [type="reset"], +a.button, label.button, .button, +a[role="button"], label[role="button"], [role="button"] { + display: inline-block; + background: var(--button-back-color); + color: var(--button-fore-color); + border: 0.0714285714rem solid var(--button-border-color); + border-radius: var(--universal-border-radius); + padding: var(--universal-padding) calc(1.5 * var(--universal-padding)); + margin: var(--universal-margin); + text-decoration: none; + cursor: pointer; + transition: background 0.3s; } + button:hover, button:focus, [type="button"]:hover, [type="button"]:focus, [type="submit"]:hover, [type="submit"]:focus, [type="reset"]:hover, [type="reset"]:focus, + a.button:hover, + a.button:focus, label.button:hover, label.button:focus, .button:hover, .button:focus, + a[role="button"]:hover, + a[role="button"]:focus, label[role="button"]:hover, label[role="button"]:focus, [role="button"]:hover, [role="button"]:focus { + background: var(--button-hover-back-color); + border-color: var(--button-hover-border-color); } + +input:disabled, input[disabled], textarea:disabled, textarea[disabled], select:disabled, select[disabled], button:disabled, button[disabled], .button:disabled, .button[disabled], [role="button"]:disabled, [role="button"][disabled] { + cursor: not-allowed; + opacity: 0.75; } + +.button-group { + display: flex; + border: 0.0714285714rem solid var(--button-group-border-color); + border-radius: var(--universal-border-radius); + margin: var(--universal-margin); } + .button-group > button, .button-group [type="button"], .button-group > [type="submit"], .button-group > [type="reset"], .button-group > .button, .button-group > [role="button"] { + margin: 0; + max-width: 100%; + flex: 1 1 auto; + text-align: center; + border: 0; + border-radius: 0; + box-shadow: none; } + .button-group > :not(:first-child) { + border-left: 0.0714285714rem solid var(--button-group-border-color); } + @media screen and (max-width: 499px) { + .button-group { + flex-direction: column; } + .button-group > :not(:first-child) { + border: 0; + border-top: 0.0714285714rem solid var(--button-group-border-color); } } + +/* + Custom elements for forms and input elements. +*/ +button.primary, [type="button"].primary, [type="submit"].primary, [type="reset"].primary, .button.primary, [role="button"].primary { + --button-back-color: #1976d2; + --button-fore-color: #f8f8f8; } + button.primary:hover, button.primary:focus, [type="button"].primary:hover, [type="button"].primary:focus, [type="submit"].primary:hover, [type="submit"].primary:focus, [type="reset"].primary:hover, [type="reset"].primary:focus, .button.primary:hover, .button.primary:focus, [role="button"].primary:hover, [role="button"].primary:focus { + --button-hover-back-color: #1565c0; } + +button.secondary, [type="button"].secondary, [type="submit"].secondary, [type="reset"].secondary, .button.secondary, [role="button"].secondary { + --button-back-color: #d32f2f; + --button-fore-color: #f8f8f8; } + button.secondary:hover, button.secondary:focus, [type="button"].secondary:hover, [type="button"].secondary:focus, [type="submit"].secondary:hover, [type="submit"].secondary:focus, [type="reset"].secondary:hover, [type="reset"].secondary:focus, .button.secondary:hover, .button.secondary:focus, [role="button"].secondary:hover, [role="button"].secondary:focus { + --button-hover-back-color: #c62828; } + +button.tertiary, [type="button"].tertiary, [type="submit"].tertiary, [type="reset"].tertiary, .button.tertiary, [role="button"].tertiary { + --button-back-color: #308732; + --button-fore-color: #f8f8f8; } + button.tertiary:hover, button.tertiary:focus, [type="button"].tertiary:hover, [type="button"].tertiary:focus, [type="submit"].tertiary:hover, [type="submit"].tertiary:focus, [type="reset"].tertiary:hover, [type="reset"].tertiary:focus, .button.tertiary:hover, .button.tertiary:focus, [role="button"].tertiary:hover, [role="button"].tertiary:focus { + --button-hover-back-color: #277529; } + +button.inverse, [type="button"].inverse, [type="submit"].inverse, [type="reset"].inverse, .button.inverse, [role="button"].inverse { + --button-back-color: #212121; + --button-fore-color: #f8f8f8; } + button.inverse:hover, button.inverse:focus, [type="button"].inverse:hover, [type="button"].inverse:focus, [type="submit"].inverse:hover, [type="submit"].inverse:focus, [type="reset"].inverse:hover, [type="reset"].inverse:focus, .button.inverse:hover, .button.inverse:focus, [role="button"].inverse:hover, [role="button"].inverse:focus { + --button-hover-back-color: #111; } + +button.small, [type="button"].small, [type="submit"].small, [type="reset"].small, .button.small, [role="button"].small { + padding: calc(0.5 * var(--universal-padding)) calc(0.75 * var(--universal-padding)); + margin: var(--universal-margin); } + +button.large, [type="button"].large, [type="submit"].large, [type="reset"].large, .button.large, [role="button"].large { + padding: calc(1.5 * var(--universal-padding)) calc(2 * var(--universal-padding)); + margin: var(--universal-margin); } + +/* + Definitions for navigation elements. +*/ +/* Navigation module CSS variable definitions */ +:root { + --header-back-color: #03234b; + --header-hover-back-color: #ffd200; + --header-fore-color: #ffffff; + --header-border-color: #3cb4e6; + --nav-back-color: #ffffff; + --nav-hover-back-color: #ffe97f; + --nav-fore-color: #e6007e; + --nav-border-color: #3cb4e6; + --nav-link-color: #3cb4e6; + --footer-fore-color: #ffffff; + --footer-back-color: #03234b; + --footer-border-color: #3cb4e6; + --footer-link-color: #3cb4e6; + --drawer-back-color: #ffffff; + --drawer-hover-back-color: #ffe97f; + --drawer-border-color: #3cb4e6; + --drawer-close-color: #e6007e; } + +header { + height: 2.75rem; + background: var(--header-back-color); + color: var(--header-fore-color); + border-bottom: 0.0714285714rem solid var(--header-border-color); + padding: calc(var(--universal-padding) / 4) 0; + white-space: nowrap; + overflow-x: auto; + overflow-y: hidden; } + header.row { + box-sizing: content-box; } + header .logo { + color: var(--header-fore-color); + font-size: 1.75rem; + padding: var(--universal-padding) calc(2 * var(--universal-padding)); + text-decoration: none; } + header button, header [type="button"], header .button, header [role="button"] { + box-sizing: border-box; + position: relative; + top: calc(0rem - var(--universal-padding) / 4); + height: calc(3.1875rem + var(--universal-padding) / 2); + background: var(--header-back-color); + line-height: calc(3.1875rem - var(--universal-padding) * 1.5); + text-align: center; + color: var(--header-fore-color); + border: 0; + border-radius: 0; + margin: 0; + text-transform: uppercase; } + header button:hover, header button:focus, header [type="button"]:hover, header [type="button"]:focus, header .button:hover, header .button:focus, header [role="button"]:hover, header [role="button"]:focus { + background: var(--header-hover-back-color); } + +nav { + background: var(--nav-back-color); + color: var(--nav-fore-color); + border: 0.0714285714rem solid var(--nav-border-color); + border-radius: var(--universal-border-radius); + margin: var(--universal-margin); } + nav * { + padding: var(--universal-padding) calc(1.5 * var(--universal-padding)); } + nav a, nav a:visited { + display: block; + color: var(--nav-link-color); + border-radius: var(--universal-border-radius); + transition: background 0.3s; } + nav a:hover, nav a:focus, nav a:visited:hover, nav a:visited:focus { + text-decoration: none; + background: var(--nav-hover-back-color); } + nav .sublink-1 { + position: relative; + margin-left: calc(2 * var(--universal-padding)); } + nav .sublink-1:before { + position: absolute; + left: calc(var(--universal-padding) - 1 * var(--universal-padding)); + top: -0.0714285714rem; + content: ''; + height: 100%; + border: 0.0714285714rem solid var(--nav-border-color); + border-left: 0; } + nav .sublink-2 { + position: relative; + margin-left: calc(4 * var(--universal-padding)); } + nav .sublink-2:before { + position: absolute; + left: calc(var(--universal-padding) - 3 * var(--universal-padding)); + top: -0.0714285714rem; + content: ''; + height: 100%; + border: 0.0714285714rem solid var(--nav-border-color); + border-left: 0; } + +footer { + background: var(--footer-back-color); + color: var(--footer-fore-color); + border-top: 0.0714285714rem solid var(--footer-border-color); + padding: calc(2 * var(--universal-padding)) var(--universal-padding); + font-size: 0.875rem; } + footer a, footer a:visited { + color: var(--footer-link-color); } + +header.sticky { + position: -webkit-sticky; + position: sticky; + z-index: 1101; + top: 0; } + +footer.sticky { + position: -webkit-sticky; + position: sticky; + z-index: 1101; + bottom: 0; } + +.drawer-toggle:before { + display: inline-block; + position: relative; + vertical-align: bottom; + content: '\00a0\2261\00a0'; + font-family: sans-serif; + font-size: 1.5em; } +@media screen and (min-width: 500px) { + .drawer-toggle:not(.persistent) { + display: none; } } + +[type="checkbox"].drawer { + height: 1px; + width: 1px; + margin: -1px; + overflow: hidden; + position: absolute; + clip: rect(0 0 0 0); + -webkit-clip-path: inset(100%); + clip-path: inset(100%); } + [type="checkbox"].drawer + * { + display: block; + box-sizing: border-box; + position: fixed; + top: 0; + width: 320px; + height: 100vh; + overflow-y: auto; + background: var(--drawer-back-color); + border: 0.0714285714rem solid var(--drawer-border-color); + border-radius: 0; + margin: 0; + z-index: 1110; + right: -320px; + transition: right 0.3s; } + [type="checkbox"].drawer + * .drawer-close { + position: absolute; + top: var(--universal-margin); + right: var(--universal-margin); + z-index: 1111; + width: 2rem; + height: 2rem; + border-radius: var(--universal-border-radius); + padding: var(--universal-padding); + margin: 0; + cursor: pointer; + transition: background 0.3s; } + [type="checkbox"].drawer + * .drawer-close:before { + display: block; + content: '\00D7'; + color: var(--drawer-close-color); + position: relative; + font-family: sans-serif; + font-size: 2rem; + line-height: 1; + text-align: center; } + [type="checkbox"].drawer + * .drawer-close:hover, [type="checkbox"].drawer + * .drawer-close:focus { + background: var(--drawer-hover-back-color); } + @media screen and (max-width: 320px) { + [type="checkbox"].drawer + * { + width: 100%; } } + [type="checkbox"].drawer:checked + * { + right: 0; } + @media screen and (min-width: 500px) { + [type="checkbox"].drawer:not(.persistent) + * { + position: static; + height: 100%; + z-index: 1100; } + [type="checkbox"].drawer:not(.persistent) + * .drawer-close { + display: none; } } + +/* + Definitions for the responsive table component. +*/ +/* Table module CSS variable definitions. */ +:root { + --table-border-color: #03234b; + --table-border-separator-color: #03234b; + --table-head-back-color: #03234b; + --table-head-fore-color: #ffffff; + --table-body-back-color: #ffffff; + --table-body-fore-color: #03234b; + --table-body-alt-back-color: #f4f4f4; } + +table { + border-collapse: separate; + border-spacing: 0; + margin: 0; + display: flex; + flex: 0 1 auto; + flex-flow: row wrap; + padding: var(--universal-padding); + padding-top: 0; } + table caption { + font-size: 1rem; + margin: calc(2 * var(--universal-margin)) 0; + max-width: 100%; + flex: 0 0 100%; } + table thead, table tbody { + display: flex; + flex-flow: row wrap; + border: 0.0714285714rem solid var(--table-border-color); } + table thead { + z-index: 999; + border-radius: var(--universal-border-radius) var(--universal-border-radius) 0 0; + border-bottom: 0.0714285714rem solid var(--table-border-separator-color); } + table tbody { + border-top: 0; + margin-top: calc(0 - var(--universal-margin)); + border-radius: 0 0 var(--universal-border-radius) var(--universal-border-radius); } + table tr { + display: flex; + padding: 0; } + table th, table td { + padding: calc(0.5 * var(--universal-padding)); + font-size: 0.9rem; } + table th { + text-align: left; + background: var(--table-head-back-color); + color: var(--table-head-fore-color); } + table td { + background: var(--table-body-back-color); + color: var(--table-body-fore-color); + border-top: 0.0714285714rem solid var(--table-border-color); } + +table:not(.horizontal) { + overflow: auto; + max-height: 100%; } + table:not(.horizontal) thead, table:not(.horizontal) tbody { + max-width: 100%; + flex: 0 0 100%; } + table:not(.horizontal) tr { + flex-flow: row wrap; + flex: 0 0 100%; } + table:not(.horizontal) th, table:not(.horizontal) td { + flex: 1 0 0%; + overflow: hidden; + text-overflow: ellipsis; } + table:not(.horizontal) thead { + position: sticky; + top: 0; } + table:not(.horizontal) tbody tr:first-child td { + border-top: 0; } + +table.horizontal { + border: 0; } + table.horizontal thead, table.horizontal tbody { + border: 0; + flex: .2 0 0; + flex-flow: row nowrap; } + table.horizontal tbody { + overflow: auto; + justify-content: space-between; + flex: .8 0 0; + margin-left: 0; + padding-bottom: calc(var(--universal-padding) / 4); } + table.horizontal tr { + flex-direction: column; + flex: 1 0 auto; } + table.horizontal th, table.horizontal td { + width: auto; + border: 0; + border-bottom: 0.0714285714rem solid var(--table-border-color); } + table.horizontal th:not(:first-child), table.horizontal td:not(:first-child) { + border-top: 0; } + table.horizontal th { + text-align: right; + border-left: 0.0714285714rem solid var(--table-border-color); + border-right: 0.0714285714rem solid var(--table-border-separator-color); } + table.horizontal thead tr:first-child { + padding-left: 0; } + table.horizontal th:first-child, table.horizontal td:first-child { + border-top: 0.0714285714rem solid var(--table-border-color); } + table.horizontal tbody tr:last-child td { + border-right: 0.0714285714rem solid var(--table-border-color); } + table.horizontal tbody tr:last-child td:first-child { + border-top-right-radius: 0.25rem; } + table.horizontal tbody tr:last-child td:last-child { + border-bottom-right-radius: 0.25rem; } + table.horizontal thead tr:first-child th:first-child { + border-top-left-radius: 0.25rem; } + table.horizontal thead tr:first-child th:last-child { + border-bottom-left-radius: 0.25rem; } + +@media screen and (max-width: 499px) { + table, table.horizontal { + border-collapse: collapse; + border: 0; + width: 100%; + display: table; } + table thead, table th, table.horizontal thead, table.horizontal th { + border: 0; + height: 1px; + width: 1px; + margin: -1px; + overflow: hidden; + padding: 0; + position: absolute; + clip: rect(0 0 0 0); + -webkit-clip-path: inset(100%); + clip-path: inset(100%); } + table tbody, table.horizontal tbody { + border: 0; + display: table-row-group; } + table tr, table.horizontal tr { + display: block; + border: 0.0714285714rem solid var(--table-border-color); + border-radius: var(--universal-border-radius); + background: #ffffff; + padding: var(--universal-padding); + margin: var(--universal-margin); + margin-bottom: calc(1 * var(--universal-margin)); } + table th, table td, table.horizontal th, table.horizontal td { + width: auto; } + table td, table.horizontal td { + display: block; + border: 0; + text-align: right; } + table td:before, table.horizontal td:before { + content: attr(data-label); + float: left; + font-weight: 600; } + table th:first-child, table td:first-child, table.horizontal th:first-child, table.horizontal td:first-child { + border-top: 0; } + table tbody tr:last-child td, table.horizontal tbody tr:last-child td { + border-right: 0; } } +table tr:nth-of-type(2n) > td { + background: var(--table-body-alt-back-color); } + +@media screen and (max-width: 500px) { + table tr:nth-of-type(2n) { + background: var(--table-body-alt-back-color); } } +:root { + --table-body-hover-back-color: #90caf9; } + +table.hoverable tr:hover, table.hoverable tr:hover > td, table.hoverable tr:focus, table.hoverable tr:focus > td { + background: var(--table-body-hover-back-color); } + +@media screen and (max-width: 500px) { + table.hoverable tr:hover, table.hoverable tr:hover > td, table.hoverable tr:focus, table.hoverable tr:focus > td { + background: var(--table-body-hover-back-color); } } +/* + Definitions for contextual background elements, toasts and tooltips. +*/ +/* Contextual module CSS variable definitions */ +:root { + --mark-back-color: #3cb4e6; + --mark-fore-color: #ffffff; } + +mark { + background: var(--mark-back-color); + color: var(--mark-fore-color); + font-size: 0.95em; + line-height: 1em; + border-radius: var(--universal-border-radius); + padding: calc(var(--universal-padding) / 4) var(--universal-padding); } + mark.inline-block { + display: inline-block; + font-size: 1em; + line-height: 1.4; + padding: calc(var(--universal-padding) / 2) var(--universal-padding); } + +:root { + --toast-back-color: #424242; + --toast-fore-color: #fafafa; } + +.toast { + position: fixed; + bottom: calc(var(--universal-margin) * 3); + left: 50%; + transform: translate(-50%, -50%); + z-index: 1111; + color: var(--toast-fore-color); + background: var(--toast-back-color); + border-radius: calc(var(--universal-border-radius) * 16); + padding: var(--universal-padding) calc(var(--universal-padding) * 3); } + +:root { + --tooltip-back-color: #212121; + --tooltip-fore-color: #fafafa; } + +.tooltip { + position: relative; + display: inline-block; } + .tooltip:before, .tooltip:after { + position: absolute; + opacity: 0; + clip: rect(0 0 0 0); + -webkit-clip-path: inset(100%); + clip-path: inset(100%); + transition: all 0.3s; + z-index: 1010; + left: 50%; } + .tooltip:not(.bottom):before, .tooltip:not(.bottom):after { + bottom: 75%; } + .tooltip.bottom:before, .tooltip.bottom:after { + top: 75%; } + .tooltip:hover:before, .tooltip:hover:after, .tooltip:focus:before, .tooltip:focus:after { + opacity: 1; + clip: auto; + -webkit-clip-path: inset(0%); + clip-path: inset(0%); } + .tooltip:before { + content: ''; + background: transparent; + border: var(--universal-margin) solid transparent; + left: calc(50% - var(--universal-margin)); } + .tooltip:not(.bottom):before { + border-top-color: #212121; } + .tooltip.bottom:before { + border-bottom-color: #212121; } + .tooltip:after { + content: attr(aria-label); + color: var(--tooltip-fore-color); + background: var(--tooltip-back-color); + border-radius: var(--universal-border-radius); + padding: var(--universal-padding); + white-space: nowrap; + transform: translateX(-50%); } + .tooltip:not(.bottom):after { + margin-bottom: calc(2 * var(--universal-margin)); } + .tooltip.bottom:after { + margin-top: calc(2 * var(--universal-margin)); } + +:root { + --modal-overlay-color: rgba(0, 0, 0, 0.45); + --modal-close-color: #e6007e; + --modal-close-hover-color: #ffe97f; } + +[type="checkbox"].modal { + height: 1px; + width: 1px; + margin: -1px; + overflow: hidden; + position: absolute; + clip: rect(0 0 0 0); + -webkit-clip-path: inset(100%); + clip-path: inset(100%); } + [type="checkbox"].modal + div { + position: fixed; + top: 0; + left: 0; + display: none; + width: 100vw; + height: 100vh; + background: var(--modal-overlay-color); } + [type="checkbox"].modal + div .card { + margin: 0 auto; + max-height: 50vh; + overflow: auto; } + [type="checkbox"].modal + div .card .modal-close { + position: absolute; + top: 0; + right: 0; + width: 1.75rem; + height: 1.75rem; + border-radius: var(--universal-border-radius); + padding: var(--universal-padding); + margin: 0; + cursor: pointer; + transition: background 0.3s; } + [type="checkbox"].modal + div .card .modal-close:before { + display: block; + content: '\00D7'; + color: var(--modal-close-color); + position: relative; + font-family: sans-serif; + font-size: 1.75rem; + line-height: 1; + text-align: center; } + [type="checkbox"].modal + div .card .modal-close:hover, [type="checkbox"].modal + div .card .modal-close:focus { + background: var(--modal-close-hover-color); } + [type="checkbox"].modal:checked + div { + display: flex; + flex: 0 1 auto; + z-index: 1200; } + [type="checkbox"].modal:checked + div .card .modal-close { + z-index: 1211; } + +:root { + --collapse-label-back-color: #03234b; + --collapse-label-fore-color: #ffffff; + --collapse-label-hover-back-color: #3cb4e6; + --collapse-selected-label-back-color: #3cb4e6; + --collapse-border-color: var(--collapse-label-back-color); + --collapse-selected-border-color: #ceecf8; + --collapse-content-back-color: #ffffff; + --collapse-selected-label-border-color: #3cb4e6; } + +.collapse { + width: calc(100% - 2 * var(--universal-margin)); + opacity: 1; + display: flex; + flex-direction: column; + margin: var(--universal-margin); + border-radius: var(--universal-border-radius); } + .collapse > [type="radio"], .collapse > [type="checkbox"] { + height: 1px; + width: 1px; + margin: -1px; + overflow: hidden; + position: absolute; + clip: rect(0 0 0 0); + -webkit-clip-path: inset(100%); + clip-path: inset(100%); } + .collapse > label { + flex-grow: 1; + display: inline-block; + height: 1.25rem; + cursor: pointer; + transition: background 0.2s; + color: var(--collapse-label-fore-color); + background: var(--collapse-label-back-color); + border: 0.0714285714rem solid var(--collapse-selected-border-color); + padding: calc(1.25 * var(--universal-padding)); } + .collapse > label:hover, .collapse > label:focus { + background: var(--collapse-label-hover-back-color); } + .collapse > label + div { + flex-basis: auto; + height: 1px; + width: 1px; + margin: -1px; + overflow: hidden; + position: absolute; + clip: rect(0 0 0 0); + -webkit-clip-path: inset(100%); + clip-path: inset(100%); + transition: max-height 0.3s; + max-height: 1px; } + .collapse > :checked + label { + background: var(--collapse-selected-label-back-color); + border-color: var(--collapse-selected-label-border-color); } + .collapse > :checked + label + div { + box-sizing: border-box; + position: relative; + width: 100%; + height: auto; + overflow: auto; + margin: 0; + background: var(--collapse-content-back-color); + border: 0.0714285714rem solid var(--collapse-selected-border-color); + border-top: 0; + padding: var(--universal-padding); + clip: auto; + -webkit-clip-path: inset(0%); + clip-path: inset(0%); + max-height: 100%; } + .collapse > label:not(:first-of-type) { + border-top: 0; } + .collapse > label:first-of-type { + border-radius: var(--universal-border-radius) var(--universal-border-radius) 0 0; } + .collapse > label:last-of-type:not(:first-of-type) { + border-radius: 0 0 var(--universal-border-radius) var(--universal-border-radius); } + .collapse > label:last-of-type:first-of-type { + border-radius: var(--universal-border-radius); } + .collapse > :checked:last-of-type:not(:first-of-type) + label { + border-radius: 0; } + .collapse > :checked:last-of-type + label + div { + border-radius: 0 0 var(--universal-border-radius) var(--universal-border-radius); } + +/* + Custom elements for contextual background elements, toasts and tooltips. +*/ +mark.tertiary { + --mark-back-color: #3cb4e6; } + +mark.tag { + padding: calc(var(--universal-padding)/2) var(--universal-padding); + border-radius: 1em; } + +/* + Definitions for progress elements and spinners. +*/ +/* Progress module CSS variable definitions */ +:root { + --progress-back-color: #3cb4e6; + --progress-fore-color: #555; } + +progress { + display: block; + vertical-align: baseline; + -webkit-appearance: none; + -moz-appearance: none; + appearance: none; + height: 0.75rem; + width: calc(100% - 2 * var(--universal-margin)); + margin: var(--universal-margin); + border: 0; + border-radius: calc(2 * var(--universal-border-radius)); + background: var(--progress-back-color); + color: var(--progress-fore-color); } + progress::-webkit-progress-value { + background: var(--progress-fore-color); + border-top-left-radius: calc(2 * var(--universal-border-radius)); + border-bottom-left-radius: calc(2 * var(--universal-border-radius)); } + progress::-webkit-progress-bar { + background: var(--progress-back-color); } + progress::-moz-progress-bar { + background: var(--progress-fore-color); + border-top-left-radius: calc(2 * var(--universal-border-radius)); + border-bottom-left-radius: calc(2 * var(--universal-border-radius)); } + progress[value="1000"]::-webkit-progress-value { + border-radius: calc(2 * var(--universal-border-radius)); } + progress[value="1000"]::-moz-progress-bar { + border-radius: calc(2 * var(--universal-border-radius)); } + progress.inline { + display: inline-block; + vertical-align: middle; + width: 60%; } + +:root { + --spinner-back-color: #ddd; + --spinner-fore-color: #555; } + +@keyframes spinner-donut-anim { + 0% { + transform: rotate(0deg); } + 100% { + transform: rotate(360deg); } } +.spinner { + display: inline-block; + margin: var(--universal-margin); + border: 0.25rem solid var(--spinner-back-color); + border-left: 0.25rem solid var(--spinner-fore-color); + border-radius: 50%; + width: 1.25rem; + height: 1.25rem; + animation: spinner-donut-anim 1.2s linear infinite; } + +/* + Custom elements for progress bars and spinners. +*/ +progress.primary { + --progress-fore-color: #1976d2; } + +progress.secondary { + --progress-fore-color: #d32f2f; } + +progress.tertiary { + --progress-fore-color: #308732; } + +.spinner.primary { + --spinner-fore-color: #1976d2; } + +.spinner.secondary { + --spinner-fore-color: #d32f2f; } + +.spinner.tertiary { + --spinner-fore-color: #308732; } + +/* + Definitions for icons - powered by Feather (https://feathericons.com/). +*/ +span[class^='icon-'] { + display: inline-block; + height: 1em; + width: 1em; + vertical-align: -0.125em; + background-size: contain; + margin: 0 calc(var(--universal-margin) / 4); } + span[class^='icon-'].secondary { + -webkit-filter: invert(25%); + filter: invert(25%); } + span[class^='icon-'].inverse { + -webkit-filter: invert(100%); + filter: invert(100%); } + +span.icon-alert { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='8' x2='12' y2='12'%3E%3C/line%3E%3Cline x1='12' y1='16' x2='12' y2='16'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-bookmark { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M19 21l-7-5-7 5V5a2 2 0 0 1 2-2h10a2 2 0 0 1 2 2z'%3E%3C/path%3E%3C/svg%3E"); } +span.icon-calendar { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='3' y='4' width='18' height='18' rx='2' ry='2'%3E%3C/rect%3E%3Cline x1='16' y1='2' x2='16' y2='6'%3E%3C/line%3E%3Cline x1='8' y1='2' x2='8' y2='6'%3E%3C/line%3E%3Cline x1='3' y1='10' x2='21' y2='10'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-credit { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='1' y='4' width='22' height='16' rx='2' ry='2'%3E%3C/rect%3E%3Cline x1='1' y1='10' x2='23' y2='10'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-edit { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M20 14.66V20a2 2 0 0 1-2 2H4a2 2 0 0 1-2-2V6a2 2 0 0 1 2-2h5.34'%3E%3C/path%3E%3Cpolygon points='18 2 22 6 12 16 8 16 8 12 18 2'%3E%3C/polygon%3E%3C/svg%3E"); } +span.icon-link { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M18 13v6a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2V8a2 2 0 0 1 2-2h6'%3E%3C/path%3E%3Cpolyline points='15 3 21 3 21 9'%3E%3C/polyline%3E%3Cline x1='10' y1='14' x2='21' y2='3'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-help { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M9.09 9a3 3 0 0 1 5.83 1c0 2-3 3-3 3'%3E%3C/path%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='17' x2='12' y2='17'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-home { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M3 9l9-7 9 7v11a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2z'%3E%3C/path%3E%3Cpolyline points='9 22 9 12 15 12 15 22'%3E%3C/polyline%3E%3C/svg%3E"); } +span.icon-info { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='16' x2='12' y2='12'%3E%3C/line%3E%3Cline x1='12' y1='8' x2='12' y2='8'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-lock { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='3' y='11' width='18' height='11' rx='2' ry='2'%3E%3C/rect%3E%3Cpath d='M7 11V7a5 5 0 0 1 10 0v4'%3E%3C/path%3E%3C/svg%3E"); } +span.icon-mail { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M4 4h16c1.1 0 2 .9 2 2v12c0 1.1-.9 2-2 2H4c-1.1 0-2-.9-2-2V6c0-1.1.9-2 2-2z'%3E%3C/path%3E%3Cpolyline points='22,6 12,13 2,6'%3E%3C/polyline%3E%3C/svg%3E"); } +span.icon-location { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M21 10c0 7-9 13-9 13s-9-6-9-13a9 9 0 0 1 18 0z'%3E%3C/path%3E%3Ccircle cx='12' cy='10' r='3'%3E%3C/circle%3E%3C/svg%3E"); } +span.icon-phone { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M22 16.92v3a2 2 0 0 1-2.18 2 19.79 19.79 0 0 1-8.63-3.07 19.5 19.5 0 0 1-6-6 19.79 19.79 0 0 1-3.07-8.67A2 2 0 0 1 4.11 2h3a2 2 0 0 1 2 1.72 12.84 12.84 0 0 0 .7 2.81 2 2 0 0 1-.45 2.11L8.09 9.91a16 16 0 0 0 6 6l1.27-1.27a2 2 0 0 1 2.11-.45 12.84 12.84 0 0 0 2.81.7A2 2 0 0 1 22 16.92z'%3E%3C/path%3E%3C/svg%3E"); } +span.icon-rss { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M4 11a9 9 0 0 1 9 9'%3E%3C/path%3E%3Cpath d='M4 4a16 16 0 0 1 16 16'%3E%3C/path%3E%3Ccircle cx='5' cy='19' r='1'%3E%3C/circle%3E%3C/svg%3E"); } +span.icon-search { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='11' cy='11' r='8'%3E%3C/circle%3E%3Cline x1='21' y1='21' x2='16.65' y2='16.65'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-settings { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='3'%3E%3C/circle%3E%3Cpath d='M19.4 15a1.65 1.65 0 0 0 .33 1.82l.06.06a2 2 0 0 1 0 2.83 2 2 0 0 1-2.83 0l-.06-.06a1.65 1.65 0 0 0-1.82-.33 1.65 1.65 0 0 0-1 1.51V21a2 2 0 0 1-2 2 2 2 0 0 1-2-2v-.09A1.65 1.65 0 0 0 9 19.4a1.65 1.65 0 0 0-1.82.33l-.06.06a2 2 0 0 1-2.83 0 2 2 0 0 1 0-2.83l.06-.06a1.65 1.65 0 0 0 .33-1.82 1.65 1.65 0 0 0-1.51-1H3a2 2 0 0 1-2-2 2 2 0 0 1 2-2h.09A1.65 1.65 0 0 0 4.6 9a1.65 1.65 0 0 0-.33-1.82l-.06-.06a2 2 0 0 1 0-2.83 2 2 0 0 1 2.83 0l.06.06a1.65 1.65 0 0 0 1.82.33H9a1.65 1.65 0 0 0 1-1.51V3a2 2 0 0 1 2-2 2 2 0 0 1 2 2v.09a1.65 1.65 0 0 0 1 1.51 1.65 1.65 0 0 0 1.82-.33l.06-.06a2 2 0 0 1 2.83 0 2 2 0 0 1 0 2.83l-.06.06a1.65 1.65 0 0 0-.33 1.82V9a1.65 1.65 0 0 0 1.51 1H21a2 2 0 0 1 2 2 2 2 0 0 1-2 2h-.09a1.65 1.65 0 0 0-1.51 1z'%3E%3C/path%3E%3C/svg%3E"); } +span.icon-share { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='18' cy='5' r='3'%3E%3C/circle%3E%3Ccircle cx='6' cy='12' r='3'%3E%3C/circle%3E%3Ccircle cx='18' cy='19' r='3'%3E%3C/circle%3E%3Cline x1='8.59' y1='13.51' x2='15.42' y2='17.49'%3E%3C/line%3E%3Cline x1='15.41' y1='6.51' x2='8.59' y2='10.49'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-cart { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='9' cy='21' r='1'%3E%3C/circle%3E%3Ccircle cx='20' cy='21' r='1'%3E%3C/circle%3E%3Cpath d='M1 1h4l2.68 13.39a2 2 0 0 0 2 1.61h9.72a2 2 0 0 0 2-1.61L23 6H6'%3E%3C/path%3E%3C/svg%3E"); } +span.icon-upload { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M21 15v4a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2v-4'%3E%3C/path%3E%3Cpolyline points='17 8 12 3 7 8'%3E%3C/polyline%3E%3Cline x1='12' y1='3' x2='12' y2='15'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-user { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M20 21v-2a4 4 0 0 0-4-4H8a4 4 0 0 0-4 4v2'%3E%3C/path%3E%3Ccircle cx='12' cy='7' r='4'%3E%3C/circle%3E%3C/svg%3E"); } + +/* + Definitions for STMicroelectronics icons (https://brandportal.st.com/document/26). +*/ +span.icon-st-update { + background-image: url("Update.svg"); } +span.icon-st-add { + background-image: url("Add button.svg"); } + +/* + Definitions for utilities and helper classes. +*/ +/* Utility module CSS variable definitions */ +:root { + --generic-border-color: rgba(0, 0, 0, 0.3); + --generic-box-shadow: 0 0.2857142857rem 0.2857142857rem 0 rgba(0, 0, 0, 0.125), 0 0.1428571429rem 0.1428571429rem -0.1428571429rem rgba(0, 0, 0, 0.125); } + +.hidden { + display: none !important; } + +.visually-hidden { + position: absolute !important; + width: 1px !important; + height: 1px !important; + margin: -1px !important; + border: 0 !important; + padding: 0 !important; + clip: rect(0 0 0 0) !important; + -webkit-clip-path: inset(100%) !important; + clip-path: inset(100%) !important; + overflow: hidden !important; } + +.bordered { + border: 0.0714285714rem solid var(--generic-border-color) !important; } + +.rounded { + border-radius: var(--universal-border-radius) !important; } + +.circular { + border-radius: 50% !important; } + +.shadowed { + box-shadow: var(--generic-box-shadow) !important; } + +.responsive-margin { + margin: calc(var(--universal-margin) / 4) !important; } + @media screen and (min-width: 500px) { + .responsive-margin { + margin: calc(var(--universal-margin) / 2) !important; } } + @media screen and (min-width: 1280px) { + .responsive-margin { + margin: var(--universal-margin) !important; } } + +.responsive-padding { + padding: calc(var(--universal-padding) / 4) !important; } + @media screen and (min-width: 500px) { + .responsive-padding { + padding: calc(var(--universal-padding) / 2) !important; } } + @media screen and (min-width: 1280px) { + .responsive-padding { + padding: var(--universal-padding) !important; } } + +@media screen and (max-width: 499px) { + .hidden-sm { + display: none !important; } } +@media screen and (min-width: 500px) and (max-width: 1279px) { + .hidden-md { + display: none !important; } } +@media screen and (min-width: 1280px) { + .hidden-lg { + display: none !important; } } +@media screen and (max-width: 499px) { + .visually-hidden-sm { + position: absolute !important; + width: 1px !important; + height: 1px !important; + margin: -1px !important; + border: 0 !important; + padding: 0 !important; + clip: rect(0 0 0 0) !important; + -webkit-clip-path: inset(100%) !important; + clip-path: inset(100%) !important; + overflow: hidden !important; } } +@media screen and (min-width: 500px) and (max-width: 1279px) { + .visually-hidden-md { + position: absolute !important; + width: 1px !important; + height: 1px !important; + margin: -1px !important; + border: 0 !important; + padding: 0 !important; + clip: rect(0 0 0 0) !important; + -webkit-clip-path: inset(100%) !important; + clip-path: inset(100%) !important; + overflow: hidden !important; } } +@media screen and (min-width: 1280px) { + .visually-hidden-lg { + position: absolute !important; + width: 1px !important; + height: 1px !important; + margin: -1px !important; + border: 0 !important; + padding: 0 !important; + clip: rect(0 0 0 0) !important; + -webkit-clip-path: inset(100%) !important; + clip-path: inset(100%) !important; + overflow: hidden !important; } } + +/*# sourceMappingURL=mini-custom.css.map */ + +img[alt="ST logo"] { display: block; margin: auto; width: 75%; max-width: 250px; min-width: 71px; } +img[alt="Cube logo"] { float: right; width: 30%; max-width: 10rem; min-width: 8rem; padding-right: 1rem;} + +.figure { + display: block; + margin-left: auto; + margin-right: auto; + text-align: center; +} \ No newline at end of file diff --git a/Middlewares/Third_Party/SubGHz_Phy/_htmresc/st_logo_2020.png b/Middlewares/Third_Party/SubGHz_Phy/_htmresc/st_logo_2020.png new file mode 100644 index 0000000..d6cebb5 Binary files /dev/null and b/Middlewares/Third_Party/SubGHz_Phy/_htmresc/st_logo_2020.png differ diff --git a/Middlewares/Third_Party/SubGHz_Phy/lr_fhss_v1_base_types.h b/Middlewares/Third_Party/SubGHz_Phy/lr_fhss_v1_base_types.h new file mode 100644 index 0000000..4266202 --- /dev/null +++ b/Middlewares/Third_Party/SubGHz_Phy/lr_fhss_v1_base_types.h @@ -0,0 +1,139 @@ +/*! + * @file lr_fhss_v1_base_types.h + * + * @brief Radio-independent LR-FHSS base type definitions, version 1 + * + * The Clear BSD License + * Copyright Semtech Corporation 2021. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted (subject to the limitations in the disclaimer + * below) provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of the Semtech corporation nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY + * THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT + * NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL SEMTECH CORPORATION BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef LR_FHSS_V1_BASE_TYPES_H__ +#define LR_FHSS_V1_BASE_TYPES_H__ + +/* + * ----------------------------------------------------------------------------- + * --- DEPENDENCIES ------------------------------------------------------------ + */ + +#include +#include + +/* + * ----------------------------------------------------------------------------- + * --- PUBLIC MACROS ----------------------------------------------------------- + */ + +/* + * ----------------------------------------------------------------------------- + * --- PUBLIC CONSTANTS -------------------------------------------------------- + */ + +#define LR_FHSS_HDR_BYTES ( 10 ) +#define LR_FHSS_HDR_BITS ( 8 * LR_FHSS_HDR_BYTES ) +#define LR_FHSS_HALF_HDR_BYTES ( 5 ) +#define LR_FHSS_HALF_HDR_BITS ( 8 * LR_FHSS_HALF_HDR_BYTES ) +#define LR_FHSS_SYNC_WORD_BYTES ( 4 ) +#define LR_FHSS_SYNC_WORD_BITS ( 8 * LR_FHSS_SYNC_WORD_BYTES ) +#define LR_FHSS_MAX_PHY_PAYLOAD_BYTES ( 255 ) +#define LR_FHSS_HEADER_BITS ( 114 ) +#define LR_FHSS_FRAG_BITS ( 48 ) +#define LR_FHSS_BLOCK_PREAMBLE_BITS ( 2 ) +#define LR_FHSS_BLOCK_BITS ( LR_FHSS_FRAG_BITS + LR_FHSS_BLOCK_PREAMBLE_BITS ) + +/* + * ----------------------------------------------------------------------------- + * --- PUBLIC TYPES ------------------------------------------------------------ + */ + +/*! + * @brief LR-FHSS modulation type + */ +typedef enum lr_fhss_v1_modulation_type_e +{ + LR_FHSS_V1_MODULATION_TYPE_GMSK_488 = 0, +} lr_fhss_v1_modulation_type_t; + +/*! + * @brief LR-FHSS coding rate + */ +typedef enum lr_fhss_v1_cr_e +{ + LR_FHSS_V1_CR_5_6 = 0x00, + LR_FHSS_V1_CR_2_3 = 0x01, + LR_FHSS_V1_CR_1_2 = 0x02, + LR_FHSS_V1_CR_1_3 = 0x03, +} lr_fhss_v1_cr_t; + +/*! + * @brief LR-FHSS grid + */ +typedef enum lr_fhss_v1_grid_e +{ + LR_FHSS_V1_GRID_25391_HZ = 0x00, + LR_FHSS_V1_GRID_3906_HZ = 0x01, +} lr_fhss_v1_grid_t; + +/*! + * @brief LR-FHSS bandwidth + */ +typedef enum lr_fhss_v1_bw_e +{ + LR_FHSS_V1_BW_39063_HZ = 0x00, + LR_FHSS_V1_BW_85938_HZ = 0x01, + LR_FHSS_V1_BW_136719_HZ = 0x02, + LR_FHSS_V1_BW_183594_HZ = 0x03, + LR_FHSS_V1_BW_335938_HZ = 0x04, + LR_FHSS_V1_BW_386719_HZ = 0x05, + LR_FHSS_V1_BW_722656_HZ = 0x06, + LR_FHSS_V1_BW_773438_HZ = 0x07, + LR_FHSS_V1_BW_1523438_HZ = 0x08, + LR_FHSS_V1_BW_1574219_HZ = 0x09, +} lr_fhss_v1_bw_t; + +/*! + * @brief LR-FHSS parameter structure + */ +typedef struct lr_fhss_v1_params_s +{ + const uint8_t* sync_word; /**< 4-byte sync word */ + lr_fhss_v1_modulation_type_t modulation_type; + lr_fhss_v1_cr_t cr; + lr_fhss_v1_grid_t grid; + lr_fhss_v1_bw_t bw; + bool enable_hopping; + uint8_t header_count; /**< Number of header blocks */ +} lr_fhss_v1_params_t; + +/* + * ----------------------------------------------------------------------------- + * --- PUBLIC FUNCTIONS PROTOTYPES --------------------------------------------- + */ + +#endif // LR_FHSS_V1_BASE_TYPES_H__ + +/* --- EOF ------------------------------------------------------------------ */ diff --git a/Middlewares/Third_Party/SubGHz_Phy/radio.h b/Middlewares/Third_Party/SubGHz_Phy/radio.h new file mode 100644 index 0000000..e8e0fd5 --- /dev/null +++ b/Middlewares/Third_Party/SubGHz_Phy/radio.h @@ -0,0 +1,474 @@ +/*! + * \file radio.h + * + * \brief Radio driver API definition + * + * \copyright Revised BSD License, see section \ref LICENSE. + * + * \code + * ______ _ + * / _____) _ | | + * ( (____ _____ ____ _| |_ _____ ____| |__ + * \____ \| ___ | (_ _) ___ |/ ___) _ \ + * _____) ) ____| | | || |_| ____( (___| | | | + * (______/|_____)_|_|_| \__)_____)\____)_| |_| + * (C)2013-2017 Semtech + * + * \endcode + * + * \author Miguel Luis ( Semtech ) + * + * \author Gregory Cristian ( Semtech ) + */ +/** + ****************************************************************************** + * + * Portions COPYRIGHT 2020 STMicroelectronics + * + * @file radio.h + * @author MCD Application Team + * @brief Radio driver API definition + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __RADIO_H__ +#define __RADIO_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif +/* Includes ------------------------------------------------------------------*/ + +#include +#include +#include "radio_def.h" +#include "radio_ex.h" +#include "lr_fhss_v1_base_types.h" + +/* Private typedef -----------------------------------------------------------*/ + +/*! + * Radio driver internal state machine states definition + */ +typedef enum +{ + RF_IDLE = 0, //!< The radio is idle + RF_RX_RUNNING, //!< The radio is in reception state + RF_TX_RUNNING, //!< The radio is in transmission state + RF_CAD, //!< The radio is doing channel activity detection +} RadioState_t; + + +typedef struct radio_lr_fhss_params_s +{ + lr_fhss_v1_params_t lr_fhss_params; + uint32_t center_frequency_in_hz; + int8_t device_offset; +} radio_lr_fhss_params_t; + +/*! + * Radio LR-FHSS configuration parameters + */ +typedef struct loramac_radio_lr_fhss_cfg_params_s +{ + int8_t tx_rf_pwr_in_dbm; //!< Radio RF output power + radio_lr_fhss_params_t radio_lr_fhss_params; //!< LR-FHSS parameters + uint32_t tx_timeout_in_ms; //!< Radio tx timeout +} radio_lr_fhss_cfg_params_t; + +/*! + * Radio LoRa time on air configuration parameters + */ +typedef struct loramac_radio_lr_fhss_time_on_air_params_s +{ + radio_lr_fhss_params_t radio_lr_fhss_params; //!< LR-FHSS parameters + uint8_t pld_len_in_bytes; //!< LoRa payload length in bytes +} radio_lr_fhss_time_on_air_params_t; + + +/* Function prototypes -----------------------------------------------------------*/ + +/*! + * \brief Radio driver definition + */ +struct Radio_s +{ + /*! + * \brief Initializes the radio + * + * \param [in] events Structure containing the driver callback functions + */ + void ( *Init )( RadioEvents_t *events ); + /*! + * Return current radio status + * + * \return status Radio status.[RF_IDLE, RF_RX_RUNNING, RF_TX_RUNNING] + */ + RadioState_t ( *GetStatus )( void ); + /*! + * \brief Configures the radio with the given modem + * + * \param [in] modem Modem to be used [0: FSK, 1: LoRa] + */ + void ( *SetModem )( RadioModems_t modem ); + /*! + * \brief Sets the channel frequency + * + * \param [in] freq Channel RF frequency + */ + void ( *SetChannel )( uint32_t freq ); + /*! + * \brief Checks if the channel is free for the given time + * + * \remark The FSK modem is always used for this task as we can select the Rx bandwidth at will. + * + * \param [in] freq Channel RF frequency in Hertz + * \param [in] rxBandwidth Rx bandwidth in Hertz + * \param [in] rssiThresh RSSI threshold in dBm + * \param [in] maxCarrierSenseTime Max time in milliseconds while the RSSI is measured + * + * \retval isFree [true: Channel is free, false: Channel is not free] + */ + bool ( *IsChannelFree )( uint32_t freq, uint32_t rxBandwidth, int16_t rssiThresh, uint32_t maxCarrierSenseTime ); + /*! + * \brief Generates a 32 bits random value based on the RSSI readings + * + * \remark This function sets the radio in LoRa modem mode and disables + * all interrupts. + * After calling this function either Radio.SetRxConfig or + * Radio.SetTxConfig functions must be called. + * + * \retval randomValue 32 bits random value + */ + uint32_t ( *Random )( void ); + /*! + * \brief Sets the reception parameters + * + * \param [in] modem Radio modem to be used [0: FSK, 1: LoRa] + * \param [in] bandwidth Sets the bandwidth + * FSK : >= 2600 and <= 250000 Hz + * LoRa: [0: 125 kHz, 1: 250 kHz, + * 2: 500 kHz, 3: Reserved] + * \param [in] datarate Sets the Datarate + * FSK : 600..300000 bits/s + * LoRa: [6: 64, 7: 128, 8: 256, 9: 512, + * 10: 1024, 11: 2048, 12: 4096 chips] + * \param [in] coderate Sets the coding rate (LoRa only) + * FSK : N/A ( set to 0 ) + * LoRa: [1: 4/5, 2: 4/6, 3: 4/7, 4: 4/8] + * \param [in] bandwidthAfc Sets the AFC Bandwidth (FSK only) + * FSK : >= 2600 and <= 250000 Hz + * LoRa: N/A ( set to 0 ) + * \param [in] preambleLen Sets the Preamble length + * FSK : Number of bytes + * LoRa: Length in symbols (the hardware adds 4 more symbols) + * \param [in] symbTimeout Sets the RxSingle timeout value + * FSK : timeout in number of bytes + * LoRa: timeout in symbols + * \param [in] fixLen Fixed length packets [0: variable, 1: fixed] + * \param [in] payloadLen Sets payload length when fixed length is used + * \param [in] crcOn Enables/Disables the CRC [0: OFF, 1: ON] + * \param [in] freqHopOn Enables disables the intra-packet frequency hopping + * FSK : N/A ( set to 0 ) + * LoRa: [0: OFF, 1: ON] + * \param [in] hopPeriod Number of symbols between each hop + * FSK : N/A ( set to 0 ) + * LoRa: Number of symbols + * \param [in] iqInverted Inverts IQ signals (LoRa only) + * FSK : N/A ( set to 0 ) + * LoRa: [0: not inverted, 1: inverted] + * \param [in] rxContinuous Sets the reception in continuous mode + * [false: single mode, true: continuous mode] + */ + void ( *SetRxConfig )( RadioModems_t modem, uint32_t bandwidth, + uint32_t datarate, uint8_t coderate, + uint32_t bandwidthAfc, uint16_t preambleLen, + uint16_t symbTimeout, bool fixLen, + uint8_t payloadLen, + bool crcOn, bool freqHopOn, uint8_t hopPeriod, + bool iqInverted, bool rxContinuous ); + /*! + * \brief Sets the transmission parameters + * + * \param [in] modem Radio modem to be used [0: FSK, 1: LoRa] + * \param [in] power Sets the output power [dBm] + * \param [in] fdev Sets the frequency deviation (FSK only) + * FSK : [Hz] + * LoRa: 0 + * \param [in] bandwidth Sets the bandwidth (LoRa only) + * FSK : 0 + * LoRa: [0: 125 kHz, 1: 250 kHz, + * 2: 500 kHz, 3: Reserved] + * \param [in] datarate Sets the Datarate + * FSK : 600..300000 bits/s + * LoRa: [6: 64, 7: 128, 8: 256, 9: 512, + * 10: 1024, 11: 2048, 12: 4096 chips] + * \param [in] coderate Sets the coding rate (LoRa only) + * FSK : N/A ( set to 0 ) + * LoRa: [1: 4/5, 2: 4/6, 3: 4/7, 4: 4/8] + * \param [in] preambleLen Sets the preamble length + * FSK : Number of bytes + * LoRa: Length in symbols (the hardware adds 4 more symbols) + * \param [in] fixLen Fixed length packets [0: variable, 1: fixed] + * \param [in] crcOn Enables disables the CRC [0: OFF, 1: ON] + * \param [in] freqHopOn Enables disables the intra-packet frequency hopping + * FSK : N/A ( set to 0 ) + * LoRa: [0: OFF, 1: ON] + * \param [in] hopPeriod Number of symbols between each hop + * FSK : N/A ( set to 0 ) + * LoRa: Number of symbols + * \param [in] iqInverted Inverts IQ signals (LoRa only) + * FSK : N/A ( set to 0 ) + * LoRa: [0: not inverted, 1: inverted] + * \param [in] timeout Transmission timeout [ms] + */ + void ( *SetTxConfig )( RadioModems_t modem, int8_t power, uint32_t fdev, + uint32_t bandwidth, uint32_t datarate, + uint8_t coderate, uint16_t preambleLen, + bool fixLen, bool crcOn, bool freqHopOn, + uint8_t hopPeriod, bool iqInverted, uint32_t timeout ); + /*! + * \brief Checks if the given RF frequency is supported by the hardware + * + * \param [in] frequency RF frequency to be checked + * \retval isSupported [true: supported, false: unsupported] + */ + bool ( *CheckRfFrequency )( uint32_t frequency ); + /*! + * \brief Computes the packet time on air in ms for the given payload + * + * \remark Can only be called once SetRxConfig or SetTxConfig have been called + * + * \param [in] modem Radio modem to be used [0: FSK, 1: LoRa] + * \param [in] bandwidth Sets the bandwidth + * FSK : >= 2600 and <= 250000 Hz + * LoRa: [0: 125 kHz, 1: 250 kHz, + * 2: 500 kHz, 3: Reserved] + * \param [in] datarate Sets the Datarate + * FSK : 600..300000 bits/s + * LoRa: [6: 64, 7: 128, 8: 256, 9: 512, + * 10: 1024, 11: 2048, 12: 4096 chips] + * \param [in] coderate Sets the coding rate (LoRa only) + * FSK : N/A ( set to 0 ) + * LoRa: [1: 4/5, 2: 4/6, 3: 4/7, 4: 4/8] + * \param [in] preambleLen Sets the Preamble length + * FSK : Number of bytes + * LoRa: Length in symbols (the hardware adds 4 more symbols) + * \param [in] fixLen Fixed length packets [0: variable, 1: fixed] + * \param [in] payloadLen Sets payload length when fixed length is used + * \param [in] crcOn Enables/Disables the CRC [0: OFF, 1: ON] + * + * \retval airTime Computed airTime (ms) for the given packet payload length + */ + uint32_t ( *TimeOnAir )( RadioModems_t modem, uint32_t bandwidth, + uint32_t datarate, uint8_t coderate, + uint16_t preambleLen, bool fixLen, uint8_t payloadLen, + bool crcOn ); + /*! + * \brief Sends the buffer of size. Prepares the packet to be sent and sets + * the radio in transmission + * + * \param [in] buffer Buffer pointer + * \param [in] size Buffer size + * + * \retval status (OK, ERROR, ...) + */ + radio_status_t ( *Send )( uint8_t *buffer, uint8_t size ); + /*! + * \brief Sets the radio in sleep mode + */ + void ( *Sleep )( void ); + /*! + * \brief Sets the radio in standby mode + */ + void ( *Standby )( void ); + /*! + * \brief Sets the radio in reception mode for the given time + * \param [in] timeout Reception timeout [ms] + * [0: continuous, others timeout] + */ + void ( *Rx )( uint32_t timeout ); + /*! + * \brief Start a Channel Activity Detection + */ + void ( *StartCad )( void ); + /*! + * \brief Sets the radio in continuous wave transmission mode + * + * \param [in] freq Channel RF frequency + * \param [in] power Sets the output power [dBm] + * \param [in] time Transmission mode timeout [s] + */ + void ( *SetTxContinuousWave )( uint32_t freq, int8_t power, uint16_t time ); + /*! + * \brief Reads the current RSSI value + * + * \retval rssiValue Current RSSI value in [dBm] + */ + int16_t ( *Rssi )( RadioModems_t modem ); + /*! + * \brief Writes the radio register at the specified address + * + * \param [in] addr Register address + * \param [in] data New register value + */ + void ( *Write )( uint16_t addr, uint8_t data ); + /*! + * \brief Reads the radio register at the specified address + * + * \param [in] addr Register address + * \retval data Register value + */ + uint8_t ( *Read )( uint16_t addr ); + /*! + * \brief Writes multiple radio registers starting at address + * + * \param [in] addr First Radio register address + * \param [in] buffer Buffer containing the new register's values + * \param [in] size Number of registers to be written + */ + void ( *WriteRegisters )( uint16_t addr, uint8_t *buffer, uint8_t size ); + /*! + * \brief Reads multiple radio registers starting at address + * + * \param [in] addr First Radio register address + * \param [out] buffer Buffer where to copy the registers data + * \param [in] size Number of registers to be read + */ + void ( *ReadRegisters )( uint16_t addr, uint8_t *buffer, uint8_t size ); + /*! + * \brief Sets the maximum payload length. + * + * \param [in] modem Radio modem to be used [0: FSK, 1: LoRa] + * \param [in] max Maximum payload length in bytes + */ + void ( *SetMaxPayloadLength )( RadioModems_t modem, uint8_t max ); + /*! + * \brief Sets the network to public or private. Updates the sync byte. + * + * \remark Applies to LoRa modem only + * + * \param [in] enable if true, it enables a public network + */ + void ( *SetPublicNetwork )( bool enable ); + /*! + * \brief Gets the time required for the board plus radio to get out of sleep.[ms] + * + * \retval time Radio plus board wakeup time in ms. + */ + uint32_t ( *GetWakeupTime )( void ); + /*! + * \brief Process radio irq + */ + void ( *IrqProcess )( void ); + /*! + * \brief Sets the radio in reception mode with Max LNA gain for the given time + * + * \param [in] timeout Reception timeout [ms] + * [0: continuous, others timeout] + */ + void ( *RxBoosted )( uint32_t timeout ); + /*! + * \brief Sets the Rx duty cycle management parameters + * + * \param [in] rxTime Structure describing reception timeout value + * \param [in] sleepTime Structure describing sleep timeout value + */ + void ( *SetRxDutyCycle )( uint32_t rxTime, uint32_t sleepTime ); + /*! + * @brief Sets the Transmitter in continuous PRBS mode + * + * \remark power and datarate shall be configured prior calling TxPrbs + */ + void ( *TxPrbs )( void ); + /*! + * \brief Sets the Transmitter in continuous un-modulated Carrier mode at power dBm + * + * \param [in] power Tx power in dBm + */ + void ( *TxCw )( int8_t power ); + /*! + * \brief Sets the reception parameters + * + * \param [in] modem Radio modem to be used [GENERIC_FSK or GENERIC_FSK] + * \param [in] config configuration of receiver + * fsk field to be used if modem =GENERIC_FSK + * lora field to be used if modem =GENERIC_LORA + * \param [in] rxContinuous Sets the reception in continuous mode + * [0: single mode, otherwise continuous mode] + * \param [in] symbTimeout Sets the RxSingle timeout value + * FSK : timeout in number of bytes + * LoRa: timeout in symbols + * \return 0 when no parameters error, -1 otherwise + */ + int32_t ( *RadioSetRxGenericConfig )( GenericModems_t modem, RxConfigGeneric_t* config, uint32_t rxContinuous, uint32_t symbTimeout ); + /*! + * \brief Sets the transmission parameters + * + * \param [in] modem Radio modem to be used [GENERIC_FSK or GENERIC_FSK or GENERIC_BPSK] + * \param [in] config configuration of receiver + * fsk field to be used if modem =GENERIC_FSK + * lora field to be used if modem =GENERIC_LORA + * bpsk field to be used if modem =GENERIC_BPSK + * \param [in] power Sets the output power [dBm] + * \param [in] timeout Reception timeout [ms] + * \return 0 when no parameters error, -1 otherwise + */ + int32_t ( *RadioSetTxGenericConfig )( GenericModems_t modem, TxConfigGeneric_t* config, int8_t power, uint32_t timeout ); + /*! + * \brief Starts sending long Packet, packet maybe short + * + * \param [in] payload_size total payload size to be sent + * \param [in] timeout in ms + * \param [in] TxLongPacketGetNextChunkCb callback to be implemented on user side to feed partial chunk + * buffer: source buffer allocated by the app + * size: size in bytes to feed + * \return 0 when no parameters error, -1 otherwise + */ + int32_t ( *TransmitLongPacket )( uint16_t payload_size, uint32_t timeout,void (*TxLongPacketGetNextChunkCb) ( uint8_t** buffer, uint8_t buffer_size ) ); + /*! + * \brief Starts receiving long Packet, packet maybe short + * + * \param [in] boosted_mode boosted_mode: 0 normal Rx, 1:improved sensitivity + * \param [in] timeout Reception timeout [ms] + * \param [in] RxLongStorePacketChunkCb callback to be implemented on user side to record partial chunk in the application + * buffer: source buffer allocated in the radio driver + * size: size in bytes to record + * \return 0 when no parameters error, -1 otherwise + */ + int32_t ( *ReceiveLongPacket )( uint8_t boosted_mode, uint32_t timeout, void (*RxLongStorePacketChunkCb) ( uint8_t* buffer, uint8_t chunk_size ) ); + /* LrFhss extended radio functions */ + /*! + * \brief Configure the radio LR-FHSS modem parameters + * + * \param [in] cfg_params LR-FHSS modem configuration parameters + * + * \returns Operation status + */ + radio_status_t ( *LrFhssSetCfg)( const radio_lr_fhss_cfg_params_t *cfg_params ); + /*! + * \brief Get the time on air in millisecond for LR-FHSS packet + * + * \param [in] params Pointer to LR-FHSS time on air parameters + * \param [out] time_on_air_in_ms time on air parameters results in ms + * + * \returns Time-on-air value in ms for LR-FHSS packet LrFhssGetTimeOnAirInMs + */ + radio_status_t ( *LrFhssGetTimeOnAirInMs)( const radio_lr_fhss_time_on_air_params_t *params, uint32_t *time_on_air_in_ms ); +}; + +/*! + * \brief Radio driver + * + * \remark This variable is defined and initialized in the specific radio + * board implementation + */ +extern const struct Radio_s Radio; + +#ifdef __cplusplus +} +#endif + +#endif // __RADIO_H__ diff --git a/Middlewares/Third_Party/SubGHz_Phy/radio_def.h b/Middlewares/Third_Party/SubGHz_Phy/radio_def.h new file mode 100644 index 0000000..154b126 --- /dev/null +++ b/Middlewares/Third_Party/SubGHz_Phy/radio_def.h @@ -0,0 +1,123 @@ +/*! + * \file radio_def.h + * + * \brief Radio driver API definition type definition + * + * \copyright Revised BSD License, see section \ref LICENSE. + * + * \code + * ______ _ + * / _____) _ | | + * ( (____ _____ ____ _| |_ _____ ____| |__ + * \____ \| ___ | (_ _) ___ |/ ___) _ \ + * _____) ) ____| | | || |_| ____( (___| | | | + * (______/|_____)_|_|_| \__)_____)\____)_| |_| + * (C)2013-2017 Semtech + * + * \endcode + * + * \author Miguel Luis ( Semtech ) + * + * \author Gregory Cristian ( Semtech ) + */ +/*! + ****************************************************************************** + * + * Portions COPYRIGHT 2020 STMicroelectronics + * + * @file radio_def.h + * @author MCD Application Team + * @brief Radio driver API definition + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __RADIO_DEF_H__ +#define __RADIO_DEF_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif +/* Includes ------------------------------------------------------------------*/ + +#include +#include + +/* Public typedef -----------------------------------------------------------*/ + +/*! + * API return status + */ +typedef enum radio_status_e +{ + RADIO_STATUS_OK, + RADIO_STATUS_UNSUPPORTED_FEATURE, + RADIO_STATUS_UNKNOWN_VALUE, + RADIO_STATUS_ERROR, +} radio_status_t; + +/*! + * Radio driver supported modems + */ +typedef enum +{ + MODEM_FSK = 0, + MODEM_LORA, + MODEM_MSK, + MODEM_BPSK, + MODEM_SIGFOX_TX, + MODEM_SIGFOX_RX, +}RadioModems_t; + +/*! + * \brief Radio driver callback functions + */ +typedef struct +{ + /*! + * \brief Tx Done callback prototype. + */ + void ( *TxDone )( void ); + /*! + * \brief Tx Timeout callback prototype. + */ + void ( *TxTimeout )( void ); + /*! + * \brief Rx Done callback prototype. + * + * \param [in] payload Received buffer pointer + * \param [in] size Received buffer size + * \param [in] rssi RSSI value computed while receiving the frame [dBm] + * \param [in] LoraSnr_FskCfo + * FSK : Carrier Frequency Offset in kHz + * LoRa: SNR value in dB + */ + void ( *RxDone )( uint8_t *payload, uint16_t size, int16_t rssi, int8_t LoraSnr_FskCfo ); + /*! + * \brief Rx Timeout callback prototype. + */ + void ( *RxTimeout )( void ); + /*! + * \brief Rx Error callback prototype. + */ + void ( *RxError )( void ); + /*! + * \brief FHSS Change Channel callback prototype. + * + * \param [in] currentChannel Index number of the current channel + */ + void ( *FhssChangeChannel )( uint8_t currentChannel ); + /*! + * \brief CAD Done callback prototype. + * + * \param [in] channelDetected Channel Activity detected during the CAD + */ + void ( *CadDone ) ( bool channelActivityDetected ); +}RadioEvents_t; + +#ifdef __cplusplus +} +#endif + +#endif // __RADIO_DEF_H__ diff --git a/Middlewares/Third_Party/SubGHz_Phy/radio_ex.h b/Middlewares/Third_Party/SubGHz_Phy/radio_ex.h new file mode 100644 index 0000000..440407d --- /dev/null +++ b/Middlewares/Third_Party/SubGHz_Phy/radio_ex.h @@ -0,0 +1,314 @@ +/** + ****************************************************************************** + * @file radio_ex.h + * @author MCD Application Team + * @brief Extends radio capabilities (whitening, long packet) + ****************************************************************************** + * @attention + * + * Copyright (c) 2020(-2021) STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __RADIO_EX_H__ +#define __RADIO_EX_H__ + +#ifdef __cplusplus +extern "C" { +#endif +/* Includes ------------------------------------------------------------------*/ +#include + +/*******************************************Radio LORA enum*****************************************/ +typedef enum +{ + GENERIC_FSK = 0, + GENERIC_LORA, + GENERIC_BPSK, /*Tx only. In this mode, only payload is generated at the antenna (e.g. preamble nor syncword is generated and must be placed into the payload*/ + GENERIC_MSK, /*Tx only. For Rx, FSK must be used*/ +}GenericModems_t; + +/*! + * @brief Represents the possible spreading factor values in LoRa packet types + */ +typedef enum +{ + RADIO_LORA_SF5 = 0x05, + RADIO_LORA_SF6 = 0x06, + RADIO_LORA_SF7 = 0x07, + RADIO_LORA_SF8 = 0x08, + RADIO_LORA_SF9 = 0x09, + RADIO_LORA_SF10 = 0x0A, + RADIO_LORA_SF11 = 0x0B, + RADIO_LORA_SF12 = 0x0C, +}RADIO_LoRaSpreadingFactors_t; + +/*! + * @brief Represents the coding rate values for LoRa packet type + */ +typedef enum +{ + RADIO_LORA_CR_4_5 = 0x01, + RADIO_LORA_CR_4_6 = 0x02, + RADIO_LORA_CR_4_7 = 0x03, + RADIO_LORA_CR_4_8 = 0x04, +}RADIO_LoRaCodingRates_t; + +/*! + * @brief Represents the bandwidth values for LoRa packet type + */ +typedef enum +{ + RADIO_LORA_BW_500 = 6, + RADIO_LORA_BW_250 = 5, + RADIO_LORA_BW_125 = 4, + RADIO_LORA_BW_062 = 3, + RADIO_LORA_BW_041 = 10, + RADIO_LORA_BW_031 = 2, + RADIO_LORA_BW_020 = 9, + RADIO_LORA_BW_015 = 1, + RADIO_LORA_BW_010 = 8, + RADIO_LORA_BW_007 = 0, +}RADIO_LoRaBandwidths_t; + +/*! + * @brief Holds the lengths mode of a LoRa packet type + */ +typedef enum +{ + RADIO_LORA_PACKET_VARIABLE_LENGTH = 0x00, //!< The packet is on variable size, header included + RADIO_LORA_PACKET_FIXED_LENGTH = 0x01, //!< The packet is known on both sides, no header included in the packet + RADIO_LORA_PACKET_EXPLICIT = RADIO_LORA_PACKET_VARIABLE_LENGTH, + RADIO_LORA_PACKET_IMPLICIT = RADIO_LORA_PACKET_FIXED_LENGTH, +}RADIO_LoRaPacketLengthsMode_t; + +/*! + * @brief Represents the CRC mode for LoRa packet type + */ +typedef enum +{ + RADIO_LORA_CRC_ON = 0x01, //!< CRC activated + RADIO_LORA_CRC_OFF = 0x00, //!< CRC not used +}RADIO_LoRaCrcModes_t; + +/*! + * @brief Represents the IQ mode for LoRa packet type + */ +typedef enum +{ + RADIO_LORA_IQ_NORMAL = 0x00, + RADIO_LORA_IQ_INVERTED = 0x01, +}RADIO_LoRaIQModes_t; + +/*! + * @brief Represents the IQ mode for LoRa packet type + */ +typedef enum +{ + RADIO_LORA_LOWDR_OPT_OFF = 0x00, /*Forced to 0*/ + RADIO_LORA_LOWDR_OPT_ON = 0x01, /*Forced to 1*/ + RADIO_LORA_LOWDR_OPT_AUTO = 0x02, /*Forced to 1 when SF11 or SF12, 0 otherwise*/ +}RADIO_Ld_Opt_t; + +/*******************************************Radio FSK enum*****************************************/ + +/*! + * @brief Represents the modulation shaping parameter + */ +typedef enum +{ + RADIO_FSK_MOD_SHAPING_OFF = 0x00, + RADIO_FSK_MOD_SHAPING_G_BT_03 = 0x08, + RADIO_FSK_MOD_SHAPING_G_BT_05 = 0x09, + RADIO_FSK_MOD_SHAPING_G_BT_07 = 0x0A, + RADIO_FSK_MOD_SHAPING_G_BT_1 = 0x0B, +}RADIO_FSK_ModShapings_t; + +/*! + * @brief Represents the preamble length used to detect the packet on Rx side + */ +typedef enum +{ + RADIO_FSK_PREAMBLE_DETECTOR_OFF = 0x00, //!< Preamble detection length off + RADIO_FSK_PREAMBLE_DETECTOR_08_BITS = 0x04, //!< Preamble detection length 8 bits + RADIO_FSK_PREAMBLE_DETECTOR_16_BITS = 0x05, //!< Preamble detection length 16 bits + RADIO_FSK_PREAMBLE_DETECTOR_24_BITS = 0x06, //!< Preamble detection length 24 bits + RADIO_FSK_PREAMBLE_DETECTOR_32_BITS = 0x07, //!< Preamble detection length 32 bit +}RADIO_FSK_PreambleDetection_t; + +/*! + * @brief Represents the possible combinations of SyncWord correlators activated + */ +typedef enum +{ + RADIO_FSK_ADDRESSCOMP_FILT_OFF = 0x00, //!< No correlator turned on, i.e. do not search for SyncWord + RADIO_FSK_ADDRESSCOMP_FILT_NODE = 0x01, + RADIO_FSK_ADDRESSCOMP_FILT_NODE_BROAD = 0x02, +}RADIO_FSK_AddressComp_t; + +/*! + * @brief Radio packet length mode + */ +typedef enum +{ + RADIO_FSK_PACKET_FIXED_LENGTH = 0x00, //!< The packet is known on both sides, no header included in the packet + RADIO_FSK_PACKET_VARIABLE_LENGTH = 0x01, //!< 1 byte packet length field inserted after the sync word*/ + RADIO_FSK_PACKET_2BYTES_LENGTH = 0x02 //!< 2 bytes packet length field inserted after the sync word, payload size greater than 255 bytes */ +}RADIO_FSK_PacketLengthModes_t; + +/*! + * @brief Represents the CRC length + */ +typedef enum +{ + RADIO_FSK_CRC_OFF = 0x01, //!< No CRC in use + RADIO_FSK_CRC_1_BYTES = 0x00, + RADIO_FSK_CRC_2_BYTES = 0x02, + RADIO_FSK_CRC_1_BYTES_INV = 0x04, + RADIO_FSK_CRC_2_BYTES_INV = 0x06, + RADIO_FSK_CRC_2_BYTES_IBM = 0xF1, + RADIO_FSK_CRC_2_BYTES_CCIT = 0xF2, +}RADIO_FSK_CrcTypes_t; + +/*! + * @brief Radio whitening mode Off, CCIT or ibm + */ +typedef enum +{ + RADIO_FSK_DC_FREE_OFF = 0x00, /*whitening Off*/ + RADIO_FSK_DC_FREEWHITENING = 0x01, /*whitening CCIT*/ + RADIO_FSK_DC_IBM_WHITENING = 0x02, /*whitening IBM*/ +}RADIO_FSK_DcFree_t; + +/*! + * @brief Radio Lora generic Rx parameters + */ +typedef struct +{ + uint32_t StopTimerOnPreambleDetect; /*0 inactive, otherwise active*/ + RADIO_LoRaSpreadingFactors_t SpreadingFactor; + RADIO_LoRaBandwidths_t Bandwidth; + RADIO_LoRaCodingRates_t Coderate; + RADIO_Ld_Opt_t LowDatarateOptimize;/*0 inactive, 1 active, otherwise auto (active for SF11 and SF12)*/ + uint16_t PreambleLen; + RADIO_LoRaPacketLengthsMode_t LengthMode; + uint8_t MaxPayloadLength; + RADIO_LoRaCrcModes_t CrcMode; + RADIO_LoRaIQModes_t IqInverted; +} generic_param_rx_lora_t; + +/*! + * @brief Radio FSK generic Rx parameters + */ +typedef struct +{ + uint32_t StopTimerOnPreambleDetect; + uint32_t Bandwidth; + uint32_t BitRate; /* BitRate */ + uint32_t PreambleLen; /* Preamble length in Byte */ + uint8_t* SyncWord; /* SyncWord Buffer, 8 bytes max */ + uint32_t MaxPayloadLength; /* maximum Payload length to listen */ + uint16_t CrcPolynomial; /* Polynomial of the Crc*/ + uint16_t CrcSeed; /* Seed of the Crc*/ + uint16_t whiteSeed; /* WhiteningSeed, whitening can also be disabled by setting this field to 0 */ + uint8_t SyncWordLength; /* SyncWord Buffer length in Byte*/ + RADIO_FSK_PreambleDetection_t PreambleMinDetect; + RADIO_FSK_ModShapings_t ModulationShaping; + RADIO_FSK_AddressComp_t AddrComp; + RADIO_FSK_PacketLengthModes_t LengthMode; /* If the header is explicit, it will be transmitted in the GFSK packet. If the header is implicit, it will not be transmitted */ + RADIO_FSK_CrcTypes_t CrcLength; /* Size of the CRC block in the GFSK packet */ + RADIO_FSK_DcFree_t Whitening; /* whitening type*/ +} generic_param_rx_fsk_t; + +/*! + * @brief Radio generic Rx Configuration + */ +typedef struct +{ + generic_param_rx_fsk_t fsk; + generic_param_rx_lora_t lora; +} RxConfigGeneric_t; + +/*! + * @brief Radio BPSK generic Tx parameters + */ +typedef struct +{ + uint32_t BitRate; /*BitRate*/ +} generic_param_tx_bpsk_t; + +/*! + * @brief Radio Lora generic Tx parameters + */ +typedef struct +{ + RADIO_LoRaSpreadingFactors_t SpreadingFactor; + RADIO_LoRaBandwidths_t Bandwidth; + RADIO_LoRaCodingRates_t Coderate; + RADIO_Ld_Opt_t LowDatarateOptimize; /*0 inactive, otherwise active*/ + uint16_t PreambleLen; + RADIO_LoRaPacketLengthsMode_t LengthMode; + RADIO_LoRaCrcModes_t CrcMode; + RADIO_LoRaIQModes_t IqInverted; +} generic_param_tx_lora_t; + +/*! + * @brief Radio FSK generic Tx parameters + */ +typedef struct +{ + uint32_t BitRate; /* BitRate */ + uint32_t PreambleLen; /* in Byte */ + uint8_t* SyncWord; /* SyncWord Buffer, 8 bytes max */ + uint16_t CrcPolynomial; + uint16_t CrcSeed; + uint16_t whiteSeed; /* Whitening seed, whitening can be disabled by setting this field to 0 */ + uint8_t SyncWordLength; /* in Byte */ + RADIO_FSK_ModShapings_t ModulationShaping; + RADIO_FSK_PacketLengthModes_t HeaderType; /* If the header is explicit, it will be transmitted in the GFSK packet. If the header is implicit, it will not be transmitted */ + RADIO_FSK_CrcTypes_t CrcLength; /* Size of the CRC block in the GFSK packet */ + RADIO_FSK_DcFree_t Whitening; + uint32_t FrequencyDeviation; /* FrequencyDeviation */ +} generic_param_tx_fsk_t; + +/*! + * @brief Radio MSK generic Tx parameters + */ +typedef struct +{ + uint32_t BitRate; /* BitRate */ + uint32_t PreambleLen; /* in Byte */ + uint8_t* SyncWord; /* SyncWord Buffer, 8 bytes max */ + uint16_t CrcPolynomial; + uint16_t CrcSeed; + uint16_t whiteSeed; /* Whitening seed, whitening can be disabled by setting this field to 0 */ + uint8_t SyncWordLength; /* in Byte */ + RADIO_FSK_ModShapings_t ModulationShaping; + RADIO_FSK_PacketLengthModes_t HeaderType; /* If the header is explicit, it will be transmitted in the GFSK packet. If the header is implicit, it will not be transmitted */ + RADIO_FSK_CrcTypes_t CrcLength; /* Size of the CRC block in the GFSK packet */ + RADIO_FSK_DcFree_t Whitening; +} generic_param_tx_msk_t; + +/*! + * @brief Radio generic Tx Configuration + */ +typedef union +{ + generic_param_tx_fsk_t fsk; + generic_param_tx_lora_t lora; + generic_param_tx_bpsk_t bpsk; + generic_param_tx_msk_t msk; +} TxConfigGeneric_t; + +#ifdef __cplusplus +} +#endif + +#endif // __RADIO_EX_H__ diff --git a/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.c b/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.c new file mode 100644 index 0000000..c3fa28b --- /dev/null +++ b/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.c @@ -0,0 +1,862 @@ +/*! + * @file lr_fhss_mac.c + * + * @brief Radio-independent LR-FHSS driver implementation + * + * The Clear BSD License + * Copyright Semtech Corporation 2021. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted (subject to the limitations in the disclaimer + * below) provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of the Semtech corporation nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY + * THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT + * NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL SEMTECH CORPORATION BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * ----------------------------------------------------------------------------- + * --- DEPENDENCIES ------------------------------------------------------------ + */ +#include "lr_fhss_mac.h" +#include + +/* + * ----------------------------------------------------------------------------- + * --- PRIVATE MACROS----------------------------------------------------------- + */ + +#ifdef TEST +#define STATIC +#else +#define STATIC static +#endif + +/* + * ----------------------------------------------------------------------------- + * --- PRIVATE CONSTANTS ------------------------------------------------------- + */ + +#define LR_FHSS_MAX_TMP_BUF_BYTES ( 608 ) + +/* + * ----------------------------------------------------------------------------- + * --- PRIVATE TYPES ----------------------------------------------------------- + */ + +/* + * ----------------------------------------------------------------------------- + * --- PRIVATE VARIABLES ------------------------------------------------------- + */ + +/** @brief Channel count as function of bandwidth index, from Table 9 specification v18 */ +STATIC const uint16_t lr_fhss_channel_count[] = { 80, 176, 280, 376, 688, 792, 1480, 1584, 3120, 3224 }; + +/** @brief Generating polynomial as function of polynomial index, n_grid in { 10, 22, 28, 30, 35, 47 } */ +STATIC const uint8_t lr_fhss_lfsr_poly1[] = { 33, 45, 48, 51, 54, 57 }; + +/** @brief Generating polynomial as function of polynomial index, n_grid in { 86, 99 } */ +STATIC const uint8_t lr_fhss_lfsr_poly2[] = { 65, 68, 71, 72 }; + +/** @brief Generating polynomial as function of polynomial index, n_grid in { 185, 198 } */ +STATIC const uint8_t lr_fhss_lfsr_poly3[] = { 142, 149 }; + +/** @brief used for 1/3 rate viterbi encoding */ +STATIC const uint8_t lr_fhss_viterbi_1_3_table[64][2] = +{ + { 0, 7 }, { 3, 4 }, { 7, 0 }, { 4, 3 }, { 6, 1 }, { 5, 2 }, { 1, 6 }, { 2, 5 }, { 1, 6 }, { 2, 5 }, { 6, 1 }, + { 5, 2 }, { 7, 0 }, { 4, 3 }, { 0, 7 }, { 3, 4 }, { 4, 3 }, { 7, 0 }, { 3, 4 }, { 0, 7 }, { 2, 5 }, { 1, 6 }, + { 5, 2 }, { 6, 1 }, { 5, 2 }, { 6, 1 }, { 2, 5 }, { 1, 6 }, { 3, 4 }, { 0, 7 }, { 4, 3 }, { 7, 0 }, { 7, 0 }, + { 4, 3 }, { 0, 7 }, { 3, 4 }, { 1, 6 }, { 2, 5 }, { 6, 1 }, { 5, 2 }, { 6, 1 }, { 5, 2 }, { 1, 6 }, { 2, 5 }, + { 0, 7 }, { 3, 4 }, { 7, 0 }, { 4, 3 }, { 3, 4 }, { 0, 7 }, { 4, 3 }, { 7, 0 }, { 5, 2 }, { 6, 1 }, { 2, 5 }, + { 1, 6 }, { 2, 5 }, { 1, 6 }, { 5, 2 }, { 6, 1 }, { 4, 3 }, { 7, 0 }, { 3, 4 }, { 0, 7 } +}; + +/** @brief used for 1/2 rate viterbi encoding */ +STATIC const uint8_t lr_fhss_viterbi_1_2_table[16][2] = +{ + { 0, 3 }, { 1, 2 }, { 2, 1 }, { 3, 0 }, { 2, 1 }, { 3, 0 }, + { 0, 3 }, { 1, 2 }, { 3, 0 }, { 2, 1 }, { 1, 2 }, { 0, 3 }, + { 1, 2 }, { 0, 3 }, { 3, 0 }, { 2, 1 } +}; + +/** @brief used header interleaving */ +STATIC const uint8_t lr_fhss_header_interleaver_minus_one[80] = +{ + 0, 18, 36, 54, 72, 4, 22, 40, // + 58, 76, 8, 26, 44, 62, 12, 30, // + 48, 66, 16, 34, 52, 70, 1, 19, // + 37, 55, 73, 5, 23, 41, 59, 77, // + 9, 27, 45, 63, 13, 31, 49, 67, // + 17, 35, 53, 71, 2, 20, 38, 56, // + 74, 6, 24, 42, 60, 78, 10, 28, // + 46, 64, 14, 32, 50, 68, 3, 21, // + 39, 57, 75, 7, 25, 43, 61, 79, // + 11, 29, 47, 65, 15, 33, 51, 69 // +}; + +/** @brief lookup table for lr_fhss_header_crc8 */ +const uint8_t lr_fhss_header_crc8_lut[256] = +{ + 0, 47, 94, 113, 188, 147, 226, 205, 87, 120, 9, 38, 235, 196, 181, 154, // + 174, 129, 240, 223, 18, 61, 76, 99, 249, 214, 167, 136, 69, 106, 27, 52, // + 115, 92, 45, 2, 207, 224, 145, 190, 36, 11, 122, 85, 152, 183, 198, 233, // + 221, 242, 131, 172, 97, 78, 63, 16, 138, 165, 212, 251, 54, 25, 104, 71, // + 230, 201, 184, 151, 90, 117, 4, 43, 177, 158, 239, 192, 13, 34, 83, 124, // + 72, 103, 22, 57, 244, 219, 170, 133, 31, 48, 65, 110, 163, 140, 253, 210, // + 149, 186, 203, 228, 41, 6, 119, 88, 194, 237, 156, 179, 126, 81, 32, 15, // + 59, 20, 101, 74, 135, 168, 217, 246, 108, 67, 50, 29, 208, 255, 142, 161, // + 227, 204, 189, 146, 95, 112, 1, 46, 180, 155, 234, 197, 8, 39, 86, 121, // + 77, 98, 19, 60, 241, 222, 175, 128, 26, 53, 68, 107, 166, 137, 248, 215, // + 144, 191, 206, 225, 44, 3, 114, 93, 199, 232, 153, 182, 123, 84, 37, 10, // + 62, 17, 96, 79, 130, 173, 220, 243, 105, 70, 55, 24, 213, 250, 139, 164, // + 5, 42, 91, 116, 185, 150, 231, 200, 82, 125, 12, 35, 238, 193, 176, 159, // + 171, 132, 245, 218, 23, 56, 73, 102, 252, 211, 162, 141, 64, 111, 30, 49, // + 118, 89, 40, 7, 202, 229, 148, 187, 33, 14, 127, 80, 157, 178, 195, 236, // + 216, 247, 134, 169, 100, 75, 58, 21, 143, 160, 209, 254, 51, 28, 109, 66 // +}; + +/** @brief lookup table for lr_fhss_payload_crc16 */ +const uint16_t lr_fhss_payload_crc16_lut[256] = +{ + 0, 30043, 60086, 40941, 41015, 54636, 19073, 16346, 13621, 16494, 57219, 43736, 38146, 57433, 32692, 2799, // + 27242, 7985, 32988, 62855, 51805, 48902, 8427, 21936, 24415, 10756, 46569, 49330, 65384, 35379, 5598, 24709, // + 54484, 41359, 15970, 19257, 29923, 440, 40533, 60174, 57825, 38074, 2903, 32268, 16854, 13453, 43872, 56891, // + 48830, 52197, 21512, 8531, 7817, 27602, 62527, 33124, 35723, 65232, 24893, 5222, 11196, 24295, 49418, 46161, // + 56563, 43432, 13893, 17182, 31940, 2463, 38514, 58153, 59846, 40093, 880, 30251, 18929, 15530, 41799, 54812, // + 46745, 50114, 23599, 10612, 5806, 25589, 64536, 35139, 33708, 63223, 26906, 7233, 9115, 22208, 51501, 48246, // + 2087, 32124, 58001, 38858, 43024, 56651, 17062, 14333, 15634, 18505, 55204, 41727, 40229, 59518, 30611, 712, // + 25165, 5910, 35067, 64928, 49786, 46881, 10444, 23959, 22392, 8739, 48590, 51349, 63311, 33300, 7673, 26786, // + 52413, 47590, 9739, 21328, 27786, 6609, 34364, 62311, 63880, 36051, 4926, 26213, 22975, 11492, 45833, 50770, // + 42711, 54156, 19553, 14650, 1760, 29627, 60502, 39181, 37858, 59065, 31060, 3087, 13269, 18062, 55651, 44088, // + 6249, 27954, 62175, 34692, 47198, 52485, 21224, 10163, 11612, 22535, 51178, 45745, 36203, 63536, 26589, 4742, // + 29187, 1880, 39093, 60910, 53812, 42863, 14466, 19929, 18230, 12909, 44416, 55515, 59137, 37466, 3511, 30956, // + 4174, 25877, 64248, 36771, 45177, 50466, 23247, 12180, 9595, 20512, 53197, 47766, 34124, 61463, 28666, 6817, // + 31268, 3967, 37010, 58825, 55827, 44872, 12453, 17918, 20241, 14922, 42407, 53500, 61222, 39549, 1424, 28875, // + 50330, 45505, 11820, 23415, 25773, 4598, 36379, 64320, 61871, 34036, 6937, 28226, 20888, 9411, 47918, 52853, // + 44784, 56235, 17478, 12573, 3783, 31644, 58481, 37162, 39877, 61086, 29043, 1064, 15346, 20137, 53572, 42015 +}; + +/*! + * @brief integral square root, rounded up + * + * @param [in] x argument + * + * @returns Square root of argument, rounded up to next integer + * + * @remark This function is only appropriate to use for reasonably small arguments + */ +STATIC uint16_t sqrt_uint16( uint16_t x ); + +/* + * ----------------------------------------------------------------------------- + * --- PRIVATE FUNCTION DECLARATIONS ------------------------------------------- + */ + +/*! + * @brief Compute 16-bit payload CRC + * + * @param [in] data_in Pointer to input buffer + * @param [in] data_in_bytecount Input buffer length, in bytes + * + * @returns 16-bit CRC + */ +STATIC uint16_t lr_fhss_payload_crc16( const uint8_t *data_in, uint16_t data_in_bytecount ); + +/*! + * @brief Compute 8-bit header CRC + * + * @param [in] data_in Pointer to input buffer + * @param [in] data_in_bytecount Input buffer length, in bytes + * + * @returns 8-bit CRC + */ +STATIC uint8_t lr_fhss_header_crc8( const uint8_t *data_in, uint16_t data_in_bytecount ); + +/*! + * @brief Whiten the payload + * + * @param [in] data_in Pointer to input buffer + * @param [in] data_in_bytecount Input buffer length, in bytes + * @param [out] data_out Pointer to output buffer, of same length as input buffer + */ +STATIC void lr_fhss_payload_whitening( const uint8_t *data_in, uint16_t data_in_bytecount, uint8_t *data_out ); + +/*! + * @brief Extract specific bit from array of bytes + * + * @param [in] data_in Array of bytes + * @param [in] bit_number Index of bit in array + * + * @returns Value of the bit + */ +STATIC uint8_t lr_fhss_extract_bit_in_byte_vector( const uint8_t *data_in, uint32_t bit_number ); + +/*! + * @brief Set specific bit in array of bytes + * + * @param [in] data_in Array of bytes + * @param [in] bit_number Index of bit in array + * @param [in] bit_value Value to be set + */ +STATIC void lr_fhss_set_bit_in_byte_vector( uint8_t *vector, uint32_t bit_number, uint8_t bit_value ); + +/*! + * @brief Compute 1/2 rate Viterbi encoding + * + * @param [in,out] encod_state Pointer to encoded state + * @param [in] data_in Pointer to input buffer + * @param [in] data_in_bitcount Length of input buffer, in bits + * @param [in] data_out Pointer to output buffer + * + * @returns Length of output buffer, in bits + */ +STATIC uint16_t lr_fhss_convolution_encode_viterbi_1_2_base( uint8_t *encod_state, const uint8_t *data_in, + uint16_t data_in_bitcount, uint8_t *data_out ); + +/*! + * @brief Compute 1/3 rate Viterbi encoding + * + * @param [in,out] encod_state Pointer to encoded state + * @param [in] data_in Pointer to input buffer + * @param [in] data_in_bitcount Length of input buffer, in bits + * @param [out] data_out Pointer to output buffer + * + * @returns Length of output buffer, in bits + */ +STATIC uint16_t lr_fhss_convolution_encode_viterbi_1_3_base( uint8_t *encod_state, const uint8_t *data_in, + uint16_t data_in_bitcount, uint8_t *data_out ); + +/*! + * @brief Convolute using lr_fhss_convolution_encode_viterbi_1_2_base with optional tail-biting + * + * @param [in] data_in Pointer to input buffer + * @param [in] data_in_bitcount Length of input buffer, in bits + * @param [in] tail_biting Set to true to activate tail-biting + * @param [out] data_out Pointer to output buffer + * + * @remark If tail-biting is activated, this function calls lr_fhss_convolution_encode_viterbi_1_2_base twice + * + * @returns Length of output buffer, in bits + */ +STATIC uint16_t lr_fhss_convolution_encode_viterbi_1_2( const uint8_t *data_in, uint16_t data_in_bitcount, + bool tail_biting, uint8_t *data_out ); + +/*! + * @brief Convolute using lr_fhss_convolution_encode_viterbi_1_3_base + * + * @param [in] data_in Pointer to input buffer + * @param [in] data_in_bitcount Length of input buffer, in bits + * @param [out] data_out Pointer to output buffer + * + * @returns Length of output buffer, in bits + */ +STATIC uint16_t lr_fhss_convolution_encode_viterbi_1_3( const uint8_t *data_in, uint16_t data_in_bitcount, + uint8_t *data_out ); + +/*! + * @brief Computes payload interleaving + * + * @param [in] data_in Pointer to input buffer + * @param [in] data_in_bitcount Length of input buffer, in bits + * @param [out] data_out Pointer to output buffer + * @param [in] output_offset Output offset indicating where data must be placed, in bits, relative to data_out bit 0 + * + * @returns Length of output buffer, in bits + */ +STATIC uint16_t lr_fhss_payload_interleaving( const uint8_t *data_in, uint16_t data_in_bitcount, uint8_t *data_out, + uint32_t output_offset ); + +/*! + * @brief Create the raw LR-FHSS header + * + * @param [in] params Parameter structure + * @param [in] hop_sequence_id The hop sequence ID that will be used to obtain hop-related data + * @param [in] payload_length Length of application payload, in bytes + * @param [out] data_out Pointer to output buffer + */ +STATIC void lr_fhss_raw_header( const lr_fhss_v1_params_t *params, uint16_t hop_sequence_id, uint16_t payload_length, + uint8_t *data_out ); + +/*! + * @brief Store sync word index inside provided header + * + * @param [in] sync_word_index The sync word index to store + * @param [out] data_out Pointer to output buffer + */ +STATIC void lr_fhss_store_header_sync_word_index( uint8_t sync_word_index, uint8_t *data_out ); + +/*! + * @brief Get the bit count and block count for a LR-FHSS frame + * + * @param [in] params Parameter structure + * @param [in] payload_length Length of physical payload, in bytes + * @param [out] nb_hops_out Number of LR-FHSS hops + * + * @returns Length of physical payload, in bits + */ +STATIC uint16_t lr_fhss_get_bit_and_hop_count( const lr_fhss_v1_params_t *params, uint16_t payload_length, + uint8_t *nb_hops_out ); + +/* + * ----------------------------------------------------------------------------- + * --- PUBLIC FUNCTION DEFINITIONS --------------------------------------------- + */ + +unsigned int lr_fhss_get_hop_sequence_count( const lr_fhss_v1_params_t *params ) +{ + if( ( params->grid == LR_FHSS_V1_GRID_25391_HZ ) || + ( ( params->grid == LR_FHSS_V1_GRID_3906_HZ ) && ( params->bw < LR_FHSS_V1_BW_335938_HZ ) ) ) + { + return 384; + } + return 512; +} + +void lr_fhss_process_parameters( const lr_fhss_v1_params_t *params, uint16_t payload_length, lr_fhss_digest_t *digest ) +{ + digest->nb_bits = lr_fhss_get_bit_and_hop_count( params, payload_length, &digest->nb_hops ); + + digest->nb_bytes = ( digest->nb_bits + 8 - 1 ) / 8; + if( params->enable_hopping ) + { + digest->nb_hops = digest->nb_hops; + } + else + { + digest->nb_hops = 1; + } +} + +radio_status_t lr_fhss_get_hop_params( const lr_fhss_v1_params_t *params, lr_fhss_hop_params_t *hop_params, + uint16_t *initial_state, uint16_t hop_sequence_id ) +{ + uint32_t channel_count = lr_fhss_channel_count[params->bw]; + + if( params->grid == LR_FHSS_V1_GRID_3906_HZ ) + { + hop_params->n_grid = channel_count / 8; + } + else + { + hop_params->n_grid = channel_count / 52; + } + + switch( hop_params->n_grid ) + { + case 10: + case 22: + case 28: + case 30: + case 35: + case 47: + { + *initial_state = 6; + hop_params->polynomial = lr_fhss_lfsr_poly1[hop_sequence_id >> 6]; + hop_params->xoring_seed = hop_sequence_id & 0x3F; + if( hop_sequence_id >= 384 ) + { + return RADIO_STATUS_ERROR; + } + break; + } + case 60: + case 62: + { + *initial_state = 56; + hop_params->polynomial = lr_fhss_lfsr_poly1[hop_sequence_id >> 6]; + hop_params->xoring_seed = hop_sequence_id & 0x3F; + if( hop_sequence_id >= 384 ) + { + return RADIO_STATUS_ERROR; + } + break; + } + case 86: + case 99: + { + *initial_state = 6; + hop_params->polynomial = lr_fhss_lfsr_poly2[hop_sequence_id >> 7]; + hop_params->xoring_seed = hop_sequence_id & 0x7F; + break; + } + case 185: + case 198: + { + *initial_state = 6; + hop_params->polynomial = lr_fhss_lfsr_poly3[hop_sequence_id >> 8]; + hop_params->xoring_seed = hop_sequence_id & 0xFF; + break; + } + case 390: + case 403: + { + *initial_state = 6; + hop_params->polynomial = 264; + hop_params->xoring_seed = hop_sequence_id; + break; + } + default: + return RADIO_STATUS_ERROR; + } + + hop_params->hop_sequence_id = hop_sequence_id; + + return RADIO_STATUS_OK; +} + +uint16_t lr_fhss_get_next_state( uint16_t *lfsr_state, const lr_fhss_hop_params_t *hop_params ) +{ + uint16_t hop; + + do + { + uint16_t lsb = *lfsr_state & 1; + *lfsr_state >>= 1; + if( lsb ) + { + *lfsr_state ^= hop_params->polynomial; + } + hop = hop_params->xoring_seed; + if( hop != *lfsr_state ) + { + hop ^= *lfsr_state; + } + } while( hop > hop_params->n_grid ); + + return hop - 1; +} + +int16_t lr_fhss_get_next_freq_in_grid( uint16_t *lfsr_state, const lr_fhss_hop_params_t *hop_params, + const lr_fhss_v1_params_t *params ) +{ + uint16_t n_i; + + if( params->enable_hopping ) + { + n_i = lr_fhss_get_next_state( lfsr_state, hop_params ); + } + else + { + n_i = hop_params->hop_sequence_id % hop_params->n_grid; + } + + if( n_i < ( hop_params->n_grid >> 1 ) ) + { + return n_i; + } + else + { + return n_i - hop_params->n_grid; + } +} + +/**************************** Build LR-FHSS Frame *********************************************************** + * Core of the LR-FHSS frame generator * + * * + * In |---------| |-----| |-----------------| |-------| |------------| |----------------------| Out * + **---|Whitening|--|CRC16|--|Outer Code + CRC8|--|Viterbi|--|Interleaving|--|Sync+header+crc Header|------ * + * |---------| |-----| |-----------------|--|-------| |------------| |----------------------| * + * * + **********************************************************************************************************/ +uint16_t lr_fhss_build_frame( const lr_fhss_v1_params_t *params, uint16_t hop_sequence_id, const uint8_t *data_in, + uint16_t data_in_bytecount, uint8_t *data_out ) +{ + uint8_t data_out_tmp[LR_FHSS_MAX_TMP_BUF_BYTES] = { 0 }; + + lr_fhss_payload_whitening( data_in, data_in_bytecount, data_out ); + uint16_t payload_crc = lr_fhss_payload_crc16( data_out, data_in_bytecount ); + + data_out[data_in_bytecount] = ( payload_crc >> 8 ) & 0xFF; + data_out[data_in_bytecount + 1] = payload_crc & 0xFF; + data_out[data_in_bytecount + 2] = 0; + + // the 1/3 encoded bytes can go up to LR_FHSS_MAX_TMP_BUF_BYTES temporarily, before puncturing it + uint16_t nb_bits = + lr_fhss_convolution_encode_viterbi_1_3( data_out, 8 * ( data_in_bytecount + 2 ) + 6, data_out_tmp ); + + // Avoid putting random stack data into payload + memset( data_out, 0, LR_FHSS_MAX_PHY_PAYLOAD_BYTES ); + + if( params->cr != LR_FHSS_V1_CR_1_3 ) + { + // this assumes first matrix values are always the same, which is the case + uint32_t matrix_index = 0; + uint8_t matrix[15] = { 1, 1, 0, 0, 1, 0, 1, 0, 0, 0, 1, 0, 1, 0, 0 }; + uint8_t matrix_len = 0; + switch( params->cr ) + { + case LR_FHSS_V1_CR_5_6: + matrix_len = 15; + break; + case LR_FHSS_V1_CR_2_3: + matrix_len = 6; + break; + case LR_FHSS_V1_CR_1_2: + matrix_len = 3; + break; + default: + // LR_FHSS_V1_CR_1_3 is excluded from this code block + break; + } + + uint32_t j = 0; + for( uint32_t i = 0; i < nb_bits; i++ ) + { + if( matrix[matrix_index] ) + { + lr_fhss_set_bit_in_byte_vector( data_out, j++, lr_fhss_extract_bit_in_byte_vector( data_out_tmp, i ) ); + } + if( ++matrix_index == matrix_len ) + { + matrix_index = 0; + } + } + nb_bits = j; + + memcpy( data_out_tmp, data_out, ( nb_bits + 7 ) / 8 ); + } + + // Interleave directly to data_out + nb_bits = + lr_fhss_payload_interleaving( data_out_tmp, nb_bits, data_out, LR_FHSS_HEADER_BITS * params->header_count ); + + // Build the header + uint8_t raw_header[LR_FHSS_HALF_HDR_BYTES]; + lr_fhss_raw_header( params, hop_sequence_id, data_in_bytecount, raw_header ); + + uint16_t header_offset = 0; + for( uint32_t i = 0; i < params->header_count; i++ ) + { + // Insert appropriate index into header + lr_fhss_store_header_sync_word_index( params->header_count - i - 1, raw_header ); + raw_header[4] = lr_fhss_header_crc8( raw_header, 4 ); + + // Convolutional encode + uint8_t coded_header[LR_FHSS_HDR_BYTES] = { 0 }; + lr_fhss_convolution_encode_viterbi_1_2( raw_header, LR_FHSS_HALF_HDR_BITS, 1, coded_header ); + + // Header guard bits + lr_fhss_set_bit_in_byte_vector( data_out, header_offset + 0, 0 ); + lr_fhss_set_bit_in_byte_vector( data_out, header_offset + 1, 0 ); + + // Interleave the header directly to the physical payload buffer + for( uint32_t j = 0; j < LR_FHSS_HALF_HDR_BITS; j++ ) + { + lr_fhss_set_bit_in_byte_vector( + data_out, header_offset + 2 + j, + lr_fhss_extract_bit_in_byte_vector( coded_header, lr_fhss_header_interleaver_minus_one[j] ) ); + } + for( uint32_t j = 0; j < LR_FHSS_HALF_HDR_BITS; j++ ) + { + lr_fhss_set_bit_in_byte_vector( + data_out, header_offset + 2 + LR_FHSS_HALF_HDR_BITS + LR_FHSS_SYNC_WORD_BITS + j, + lr_fhss_extract_bit_in_byte_vector( coded_header, + lr_fhss_header_interleaver_minus_one[LR_FHSS_HALF_HDR_BITS + j] ) ); + } + + // Copy the sync word to the physical payload buffer + for( uint32_t j = 0; j < LR_FHSS_SYNC_WORD_BITS; j++ ) + { + lr_fhss_set_bit_in_byte_vector( data_out, header_offset + 2 + LR_FHSS_HALF_HDR_BITS + j, + lr_fhss_extract_bit_in_byte_vector( params->sync_word, j ) ); + } + + header_offset += LR_FHSS_HEADER_BITS; + } + + return ( header_offset + nb_bits + 7 ) / 8; +} + +uint32_t lr_fhss_get_time_on_air_in_ms( const lr_fhss_v1_params_t *params, uint16_t payload_length ) +{ + // Multiply by 1000 / 488.28125, or equivalently 256/125, rounding up + return ( ( lr_fhss_get_time_on_air_numerator( params, payload_length ) << 8 ) + 124 ) / 125; +} + +/* + * ----------------------------------------------------------------------------- + * --- PRIVATE FUNCTION DEFINITIONS -------------------------------------------- + */ + +STATIC uint16_t lr_fhss_payload_crc16( const uint8_t *data_in, uint16_t data_in_bytecount ) +{ + uint16_t crc16 = 65535; + uint8_t pos = 0; + for( uint16_t k = 0; k < data_in_bytecount; k++ ) + { + pos = ( ( crc16 >> 8 ) ^ data_in[k] ); + crc16 = ( crc16 << 8 ) ^ lr_fhss_payload_crc16_lut[pos]; + } + return crc16; +} + +STATIC uint8_t lr_fhss_header_crc8( const uint8_t *data_in, uint16_t data_in_bytecount ) +{ + uint8_t crc8 = 255; + for( uint16_t k = 0; k < data_in_bytecount; k++ ) + { + uint8_t pos = ( crc8 ^ data_in[k] ); + crc8 = lr_fhss_header_crc8_lut[pos]; + } + + return crc8; +} + +STATIC void lr_fhss_payload_whitening( const uint8_t *data_in, uint16_t data_in_bytecount, uint8_t *data_out ) +{ + uint8_t lfsr = 0xFF; + + for( uint8_t index = 0; index < data_in_bytecount; index++ ) + { + uint8_t u = data_in[index] ^ lfsr; + data_out[index] = ( ( u & 0x0F ) << 4 ) | ( ( u & 0xF0 ) >> 4 ); + lfsr = + ( lfsr << 1 ) | ( ( ( lfsr & 0x80 ) >> 7 ) ^ + ( ( ( lfsr & 0x20 ) >> 5 ) ^ ( ( ( lfsr & 0x10 ) >> 4 ) ^ ( ( lfsr & 0x8 ) >> 3 ) ) ) ); + } +} + +STATIC uint8_t lr_fhss_extract_bit_in_byte_vector( const uint8_t *data_in, uint32_t bit_number ) +{ + uint32_t index = bit_number >> 3; + uint8_t bit_pos = 7 - ( bit_number % 8 ); + + if( data_in[index] & ( 1 << bit_pos ) ) + { + return 1; + } + return 0; +} + +STATIC void lr_fhss_set_bit_in_byte_vector( uint8_t *vector, uint32_t bit_number, uint8_t bit_value ) +{ + uint32_t index = bit_number >> 3; + uint8_t bit_pos = 7 - ( bit_number % 8 ); + + vector[index] = ( vector[index] & ( 0xff - ( 1 << bit_pos ) ) ) | ( bit_value << bit_pos ); +} + +STATIC uint16_t lr_fhss_convolution_encode_viterbi_1_2_base( uint8_t *encod_state, const uint8_t *data_in, + uint16_t data_in_bitcount, uint8_t *data_out ) +{ + uint8_t g1g0; + uint8_t cur_bit; + uint16_t ind_bit; + uint16_t data_out_bitcount = 0; + uint16_t bin_out_16 = 0; + + for( ind_bit = 0; ind_bit < data_in_bitcount; ind_bit++ ) + { + cur_bit = lr_fhss_extract_bit_in_byte_vector( data_in, ind_bit ); + g1g0 = lr_fhss_viterbi_1_2_table[*encod_state][cur_bit]; + *encod_state = ( *encod_state * 2 + cur_bit ) % 16; + bin_out_16 |= ( g1g0 << ( ( 7 - ( ind_bit % 8 ) ) << 1 ) ); + if( ind_bit % 8 == 7 ) + { + *data_out++ = ( uint8_t )( bin_out_16 >> 8 ); + *data_out++ = ( uint8_t ) bin_out_16; + bin_out_16 = 0; + } + data_out_bitcount += 2; + } + if( ind_bit % 8 ) + { + *data_out++ = ( uint8_t )( bin_out_16 >> 8 ); + *data_out++ = ( uint8_t ) bin_out_16; + bin_out_16 = 0; + } + + return data_out_bitcount; +} + +STATIC uint16_t lr_fhss_convolution_encode_viterbi_1_3_base( uint8_t *encod_state, const uint8_t *data_in, + uint16_t data_in_bitcount, uint8_t *data_out ) +{ + uint8_t g1g0; + uint8_t cur_bit; + uint16_t ind_bit; + uint16_t data_out_bitcount = 0; + uint32_t bin_out_32 = 0; + + for( ind_bit = 0; ind_bit < data_in_bitcount; ind_bit++ ) + { + cur_bit = lr_fhss_extract_bit_in_byte_vector( data_in, ind_bit ); + g1g0 = lr_fhss_viterbi_1_3_table[*encod_state][cur_bit]; + *encod_state = ( *encod_state * 2 + cur_bit ) % 64; + bin_out_32 |= ( g1g0 << ( ( 7 - ( ind_bit % 8 ) ) * 3 ) ); + if( ind_bit % 8 == 7 ) + { + *data_out++ = ( uint8_t )( bin_out_32 >> 16 ); + *data_out++ = ( uint8_t )( bin_out_32 >> 8 ); + *data_out++ = ( uint8_t ) bin_out_32; + bin_out_32 = 0; + } + data_out_bitcount += 3; + } + if( ind_bit % 8 ) + { + *data_out++ = ( uint8_t )( bin_out_32 >> 16 ); + *data_out++ = ( uint8_t )( bin_out_32 >> 8 ); + *data_out++ = ( uint8_t ) bin_out_32; + bin_out_32 = 0; + } + + return data_out_bitcount; +} + +STATIC uint16_t lr_fhss_convolution_encode_viterbi_1_2( const uint8_t *data_in, uint16_t data_in_bitcount, + bool tail_biting, uint8_t *data_out ) +{ + uint8_t encode_state = 0; + uint16_t data_out_bitcount; + + data_out_bitcount = + lr_fhss_convolution_encode_viterbi_1_2_base( &encode_state, data_in, data_in_bitcount, data_out ); + if( tail_biting ) + { + data_out_bitcount = + lr_fhss_convolution_encode_viterbi_1_2_base( &encode_state, data_in, data_in_bitcount, data_out ); + } + return data_out_bitcount; +} + +STATIC uint16_t lr_fhss_convolution_encode_viterbi_1_3( const uint8_t *data_in, uint16_t data_in_bitcount, + uint8_t *data_out ) +{ + uint8_t encode_state = 0; + return lr_fhss_convolution_encode_viterbi_1_3_base( &encode_state, data_in, data_in_bitcount, data_out ); +} + +STATIC uint16_t sqrt_uint16( uint16_t x ) +{ + uint16_t y = 0; + + while( y * y < x ) + { + y += 1; + } + + return y; +} + +STATIC uint16_t lr_fhss_payload_interleaving( const uint8_t *data_in, uint16_t data_in_bitcount, uint8_t *data_out, + uint32_t output_offset ) +{ + uint16_t step = sqrt_uint16( data_in_bitcount ); + const uint16_t step_v = step >> 1; + step = step << 1; + + uint16_t pos = 0; + uint16_t st_idx = 0; + uint16_t st_idx_init = 0; + int16_t bits_left = data_in_bitcount; + uint16_t out_row_index = output_offset; + + while( bits_left > 0 ) + { + int16_t in_row_width = bits_left; + if( in_row_width > LR_FHSS_FRAG_BITS ) + { + in_row_width = LR_FHSS_FRAG_BITS; + } + + lr_fhss_set_bit_in_byte_vector( data_out, 0 + out_row_index, 0 ); // guard bits + lr_fhss_set_bit_in_byte_vector( data_out, 1 + out_row_index, 0 ); // guard bits + for( uint32_t j = 0; j < in_row_width; j++ ) + { + lr_fhss_set_bit_in_byte_vector( data_out, j + 2 + out_row_index, + lr_fhss_extract_bit_in_byte_vector( data_in, pos ) ); // guard bit + + pos += step; + if( pos >= data_in_bitcount ) + { + st_idx += step_v; + if( st_idx >= step ) + { + st_idx_init++; + st_idx = st_idx_init; + } + pos = st_idx; + } + } + + bits_left -= LR_FHSS_FRAG_BITS; + out_row_index += 2 + in_row_width; + } + + return out_row_index - output_offset; +} + +STATIC void lr_fhss_raw_header( const lr_fhss_v1_params_t *params, uint16_t hop_sequence_id, uint16_t payload_length, + uint8_t *data_out ) +{ + data_out[0] = payload_length; + data_out[1] = ( params->modulation_type << 5 ) + ( params->cr << 3 ) + ( params->grid << 2 ) + + ( params->enable_hopping ? 2 : 0 ) + ( params->bw >> 3 ); + data_out[2] = ( ( params->bw & 0x07 ) << 5 ) + ( hop_sequence_id >> 4 ); + data_out[3] = ( ( hop_sequence_id & 0x000F ) << 4 ); +} + +STATIC void lr_fhss_store_header_sync_word_index( uint8_t sync_word_index, uint8_t *data_out ) +{ + data_out[3] = ( data_out[3] & ~0x0C ) | ( sync_word_index << 2 ); +} + +STATIC uint16_t lr_fhss_get_bit_and_hop_count( const lr_fhss_v1_params_t *params, uint16_t payload_length, + uint8_t *nb_hops_out ) +{ + // check length : payload + 16bit crc, encoded, padded to 48bits, adding 2 guard bit / 48bits + uint16_t length_bits = ( payload_length + 2 ) * 8 + 6; + switch( params->cr ) + { + case LR_FHSS_V1_CR_5_6: + length_bits = ( ( length_bits * 6 ) + 4 ) / 5; + break; + + case LR_FHSS_V1_CR_2_3: + length_bits = length_bits * 3 / 2; + break; + + case LR_FHSS_V1_CR_1_2: + length_bits = length_bits * 2; + break; + + case LR_FHSS_V1_CR_1_3: + length_bits = length_bits * 3; + break; + } + + *nb_hops_out = ( length_bits + 47 ) / 48 + params->header_count; + + // calculate total number of payload bits, after breaking into blocks + uint16_t payload_bits = length_bits / LR_FHSS_FRAG_BITS * LR_FHSS_BLOCK_BITS; + uint16_t last_block_bits = length_bits % LR_FHSS_FRAG_BITS; + if( last_block_bits > 0 ) + { + // add the 2 guard bits for the last block + the actual remaining payload bits + payload_bits += last_block_bits + 2; + } + + return ( LR_FHSS_HEADER_BITS * params->header_count ) + payload_bits; +} + +/* --- EOF ------------------------------------------------------------------ */ diff --git a/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.h b/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.h new file mode 100644 index 0000000..7fb6bf0 --- /dev/null +++ b/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.h @@ -0,0 +1,198 @@ +/*! + * @file lr_fhss_mac.h + * + * @brief Radio-independent LR-FHSS algorithms driver internal API + * + * The Clear BSD License + * Copyright Semtech Corporation 2021. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted (subject to the limitations in the disclaimer + * below) provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of the Semtech corporation nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY + * THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT + * NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL SEMTECH CORPORATION BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef LR_FHSS_MAC_H__ +#define LR_FHSS_MAC_H__ + +/* + * ----------------------------------------------------------------------------- + * --- DEPENDENCIES ------------------------------------------------------------ + */ + +#include +#include +#include "radio_def.h" +#include "lr_fhss_v1_base_types.h" + +/* + * ----------------------------------------------------------------------------- + * --- PUBLIC MACROS ----------------------------------------------------------- + */ + +/* + * ----------------------------------------------------------------------------- + * --- PUBLIC CONSTANTS -------------------------------------------------------- + */ + + +/* + * ----------------------------------------------------------------------------- + * --- PUBLIC TYPES ------------------------------------------------------------ + */ + +/*! + * Digest, holding physical payload length and hop information + */ +typedef struct lr_fhss_digest_s +{ + uint16_t nb_bytes; /**< Length of LR-FHSS frame, in bytes */ + uint16_t nb_bits; /**< Number of bits */ + uint8_t nb_hops; /**< Number of hops */ +} lr_fhss_digest_t; + +/*! + * Hopping configuration, created by @ref lr_fhss_get_hop_params, and used to generate hop sequence + */ +typedef struct lr_fhss_hop_params_s +{ + uint16_t n_grid; /**< Ngrid, as described in specification */ + uint16_t polynomial; /**< polynomial, as described in specification, used for hop sequence generation */ + uint16_t xoring_seed; /**< xoring seed, as described in specification, used for hop sequence generation */ + uint16_t hop_sequence_id; /**< Hopping sequence seed, as described in specification, determines which hop sequence + will be used */ +} lr_fhss_hop_params_t; + +/*! + * ----------------------------------------------------------------------------- + * --- PUBLIC FUNCTIONS PROTOTYPES --------------------------------------------- + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + * @brief Return the number of hop sequences available using the given parameters + * + * @param [in] params LR-FHSS parameter structure + * + * @returns Number of valid hop sequences (512 or 384) + */ +unsigned int lr_fhss_get_hop_sequence_count( const lr_fhss_v1_params_t *params ); + +/*! + * @brief Fill the digest structure with various size-related data for a LR-FHSS frame + * + * @param [in] params LR-FHSS parameter structure + * @param [in] payload_length Length of payload, in bytes + * @param [out] digest Contains block count byte count, and number of hops + */ +void lr_fhss_process_parameters( const lr_fhss_v1_params_t *params, uint16_t payload_length, lr_fhss_digest_t *digest ); + +/*! + * @brief Fill the hop structure with various hop-related data for a LR-FHSS frame, and provide initial state + * + * @param [in] params LR-FHSS parameter structure + * @param [out] hop_params Hop parameter structure + * @param [out] initial_state Initial LFSR state + * @param [in] hop_sequence_id The hop sequence ID that will be used to obtain hop-related data + * + * @returns Operation status + */ +radio_status_t lr_fhss_get_hop_params( const lr_fhss_v1_params_t *params, lr_fhss_hop_params_t *hop_params, + uint16_t *initial_state, uint16_t hop_sequence_id ); + +/*! + * @brief Update the LFSR state by performing a hop, and return the hop grid position + * + * @param [in,out] lfsr_state LFSR state + * @param [in] hop_params Hop parameter structure + * + * @returns Hop position in the grid + */ +uint16_t lr_fhss_get_next_state( uint16_t *lfsr_state, const lr_fhss_hop_params_t *hop_params ); + +/*! + * @brief Return the frequency in grid units for given LR-FHSS parameters and hop index + * + * @param [in,out] lfsr_state LFSR state + * @param [in] hop_params Hop parameter structure + * @param [in] params LR-FHSS parameter structure + * + * @returns Frequency, in grid units + */ +int16_t lr_fhss_get_next_freq_in_grid( uint16_t *lfsr_state, const lr_fhss_hop_params_t *hop_params, + const lr_fhss_v1_params_t *params ); + +/*! + * @brief Construct the LR-FHSS frame + * + * @param [in] params LR-FHSS parameter structure + * @param [in] hop_sequence_id The hop sequence ID that will be used to obtain hop-related data + * @param [in] data_in Pointer to input buffer + * @param [in] data_in_bytecount Length of input buffer, in bytes + * @param [out] data_out Pointer to a buffer into which the final LR-FHSS frame is stored, large enough to hold + * 255 bytes + * + * @returns Length of frame, in bytes + */ +uint16_t lr_fhss_build_frame( const lr_fhss_v1_params_t *params, uint16_t hop_sequence_id, const uint8_t *data_in, + uint16_t data_in_bytecount, uint8_t *data_out ); + +/*! + * @brief Compute the numerator for LR-FHSS time-on-air computation. + * + * @remark To get the actual time-on-air in seconds, this value must be divided by the LR-FHSS bitrate in bits per + * second, 488.28125. + * + * @param [in] params LR-FHSS parameter structure + * @param [in] payload_length Length of application payload, in bytes + * + * @returns LR-FHSS time-on-air numerator + */ +static inline uint32_t lr_fhss_get_time_on_air_numerator( const lr_fhss_v1_params_t *params, uint16_t payload_length ) +{ + lr_fhss_digest_t digest; + lr_fhss_process_parameters( params, payload_length, &digest ); + + return digest.nb_bits; +} + +/*! + * @brief Get the time on air in ms for LR-FHSS transmission + * + * @param [in] params LR-FHSS parameter structure + * @param [in] payload_length Length of application-layer payload + * + * @returns Time-on-air value in ms for LR-FHSS transmission + */ +uint32_t lr_fhss_get_time_on_air_in_ms( const lr_fhss_v1_params_t *params, uint16_t payload_length ); + +#ifdef __cplusplus +} +#endif + +#endif // LR_FHSS_MAC_H__ + +/* --- EOF ------------------------------------------------------------------ */ diff --git a/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c b/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c new file mode 100644 index 0000000..f945d17 --- /dev/null +++ b/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c @@ -0,0 +1,2390 @@ +/*! + * \file radio.c + * + * \brief Radio driver API implementation + * + * \copyright Revised BSD License, see section \ref LICENSE. + * + * \code + * ______ _ + * / _____) _ | | + * ( (____ _____ ____ _| |_ _____ ____| |__ + * \____ \| ___ | (_ _) ___ |/ ___) _ \ + * _____) ) ____| | | || |_| ____( (___| | | | + * (______/|_____)_|_|_| \__)_____)\____)_| |_| + * (C)2013-2017 Semtech + * + * \endcode + * + * \author Miguel Luis ( Semtech ) + * + * \author Gregory Cristian ( Semtech ) + */ +/** + ****************************************************************************** + * + * Portions COPYRIGHT 2020 STMicroelectronics + * + * @file radio.c + * @author MCD Application Team + * @brief Radio driver API definition + ****************************************************************************** + */ +/* Includes ------------------------------------------------------------------*/ +#include +#include "radio.h" +#include "wl_lr_fhss.h" +#include "timer.h" +#include "radio_fw.h" +#include "radio_driver.h" +#include "radio_conf.h" +#include "mw_log_conf.h" + +/* Private typedef -----------------------------------------------------------*/ +/*! + * Radio hardware and global parameters + */ +typedef struct SubgRf_s +{ + RadioModems_t Modem; + bool RxContinuous; + uint32_t TxTimeout; + uint32_t RxTimeout; + struct + { + bool Previous; + bool Current; + } PublicNetwork; + PacketParams_t PacketParams; + PacketStatus_t PacketStatus; + ModulationParams_t ModulationParams; + RadioIrqMasks_t RadioIrq; + uint8_t AntSwitchPaSelect; + uint32_t RxDcPreambleDetectTimeout; /* 0:RxDutyCycle is off, otherwise on with 2*rxTime + sleepTime (See STM32WL Errata: RadioSetRxDutyCycle)*/ +#if( RADIO_LR_FHSS_IS_ON == 1 ) + struct + { + uint32_t rf_freq_in_hz; + int8_t tx_rf_pwr_in_dbm; + bool is_lr_fhss_on; + uint16_t hop_sequence_id; + wl_lr_fhss_params_t lr_fhss_params; + wl_lr_fhss_state_t lr_fhss_state; + } lr_fhss; + +#endif /* RADIO_LR_FHSS_IS_ON == 1 */ +} SubgRf_t; + +/* Private macro -------------------------------------------------------------*/ +#define RADIO_BIT_MASK(__n) (~(1<<__n)) + +/** + * \brief Calculates ceiling division of ( X / N ) + * + * \param [in] X numerator + * \param [in] N denominator + * + */ +#ifndef DIVC +#define DIVC( X, N ) ( ( ( X ) + ( N ) - 1 ) / ( N ) ) +#endif + +/** + * \brief Calculates rounding division of ( X / N ) + * + * \param [in] X numerator + * \param [in] N denominator + * + */ +#ifndef DIVR +#define DIVR( X, N ) ( ( ( X ) + ( ((X)>0?(N):(N))>>1 ) ) / ( N ) ) +#endif + +/* Private define ------------------------------------------------------------*/ +/* */ +/*can be overridden in radio_conf.h*/ +#ifndef RADIO_LR_FHSS_IS_ON +#define RADIO_LR_FHSS_IS_ON 0 +#endif /* !RADIO_LR_FHSS_IS_ON */ +/*can be overridden in radio_conf.h*/ +#ifndef XTAL_FREQ +#define XTAL_FREQ 32000000UL +#endif +/*can be overridden in radio_conf.h*/ +#ifndef RADIO_IRQ_PROCESS_INIT +#define RADIO_IRQ_PROCESS_INIT() +#endif +/*can be overridden in radio_conf.h*/ +#ifndef RADIO_IRQ_PROCESS +#define RADIO_IRQ_PROCESS() RadioIrqProcess() +#endif +/*can be overridden in radio_conf.h*/ +#ifndef RADIO_RX_TIMEOUT_PROCESS +#define RADIO_RX_TIMEOUT_PROCESS() RadioOnRxTimeoutProcess() +#endif +/*can be overridden in radio_conf.h*/ +#ifndef RADIO_TX_TIMEOUT_PROCESS +#define RADIO_TX_TIMEOUT_PROCESS() RadioOnTxTimeoutProcess() +#endif +/*can be overridden in radio_conf.h*/ +#ifndef IRQ_TX_DBG +#define IRQ_TX_DBG ((uint16_t) 0) +#endif +/*can be overridden in radio_conf.h*/ +#ifndef IRQ_RX_DBG +#define IRQ_RX_DBG ((uint16_t) 0) +#endif +/*can be overridden in radio_conf.h*/ +#ifndef RADIO_SIGFOX_ENABLE +#define RADIO_SIGFOX_ENABLE 1 +#endif +/*can be overridden in radio_conf.h*/ +#ifndef RADIO_GENERIC_CONFIG_ENABLE +#define RADIO_GENERIC_CONFIG_ENABLE 1 +#endif + +/*can be overridden in radio_conf.h*/ +#ifndef DBG_GPIO_RADIO_RX +#define DBG_GPIO_RADIO_RX(set_rst) +#endif + +/*can be overridden in radio_conf.h*/ +#ifndef DBG_GPIO_RADIO_TX +#define DBG_GPIO_RADIO_TX(set_rst) +#endif + +#define RADIO_BUF_SIZE 255 + +/* Private function prototypes -----------------------------------------------*/ +/*! + * \brief Initializes the radio + * + * \param [in] events Structure containing the driver callback functions + */ +static void RadioInit( RadioEvents_t *events ); + +/*! + * Return current radio status + * + * \return status Radio status.[RF_IDLE, RF_RX_RUNNING, RF_TX_RUNNING] + */ +static RadioState_t RadioGetStatus( void ); + +/*! + * \brief Configures the radio with the given modem + * + * \param [in] modem Modem to be used [0: FSK, 1: LoRa] + */ +static void RadioSetModem( RadioModems_t modem ); + +/*! + * \brief Sets the channel frequency + * + * \param [in] freq Channel RF frequency + */ +static void RadioSetChannel( uint32_t freq ); + +/*! + * \brief Checks if the channel is free for the given time + * + * \remark The FSK modem is always used for this task as we can select the Rx bandwidth at will. + * + * \param [in] freq Channel RF frequency in Hertz + * \param [in] rxBandwidth Rx bandwidth in Hertz + * \param [in] rssiThresh RSSI threshold in dBm + * \param [in] maxCarrierSenseTime Max time in milliseconds while the RSSI is measured + * + * \retval isFree [true: Channel is free, false: Channel is not free] + */ +static bool RadioIsChannelFree( uint32_t freq, uint32_t rxBandwidth, int16_t rssiThresh, uint32_t maxCarrierSenseTime ); + +/*! + * \brief Generates a 32 bits random value based on the RSSI readings + * + * \remark This function sets the radio in LoRa modem mode and disables + * all interrupts. + * After calling this function either Radio.SetRxConfig or + * Radio.SetTxConfig functions must be called. + * + * \retval randomValue 32 bits random value + */ +static uint32_t RadioRandom( void ); + +/*! + * \brief Sets the reception parameters + * + * \param [in] modem Radio modem to be used [0: FSK, 1: LoRa] + * \param [in] bandwidth Sets the bandwidth + * FSK : >= 2600 and <= 250000 Hz + * LoRa: [0: 125 kHz, 1: 250 kHz, + * 2: 500 kHz, 3: Reserved] + * \param [in] datarate Sets the Datarate + * FSK : 600..300000 bits/s + * LoRa: [6: 64, 7: 128, 8: 256, 9: 512, + * 10: 1024, 11: 2048, 12: 4096 chips] + * \param [in] coderate Sets the coding rate (LoRa only) + * FSK : N/A ( set to 0 ) + * LoRa: [1: 4/5, 2: 4/6, 3: 4/7, 4: 4/8] + * \param [in] bandwidthAfc Sets the AFC Bandwidth (FSK only) + * FSK : >= 2600 and <= 250000 Hz + * LoRa: N/A ( set to 0 ) + * \param [in] preambleLen Sets the Preamble length + * FSK : Number of bytes + * LoRa: Length in symbols (the hardware adds 4 more symbols) + * \param [in] symbTimeout Sets the RxSingle timeout value + * FSK : timeout in number of bytes + * LoRa: timeout in symbols + * \param [in] fixLen Fixed length packets [0: variable, 1: fixed] + * \param [in] payloadLen Sets payload length when fixed length is used + * \param [in] crcOn Enables/Disables the CRC [0: OFF, 1: ON] + * \param [in] FreqHopOn Enables disables the intra-packet frequency hopping + * FSK : N/A ( set to 0 ) + * LoRa: [0: OFF, 1: ON] + * \param [in] HopPeriod Number of symbols between each hop + * FSK : N/A ( set to 0 ) + * LoRa: Number of symbols + * \param [in] iqInverted Inverts IQ signals (LoRa only) + * FSK : N/A ( set to 0 ) + * LoRa: [0: not inverted, 1: inverted] + * \param [in] rxContinuous Sets the reception in continuous mode + * [false: single mode, true: continuous mode] + */ +static void RadioSetRxConfig( RadioModems_t modem, uint32_t bandwidth, + uint32_t datarate, uint8_t coderate, + uint32_t bandwidthAfc, uint16_t preambleLen, + uint16_t symbTimeout, bool fixLen, + uint8_t payloadLen, + bool crcOn, bool FreqHopOn, uint8_t HopPeriod, + bool iqInverted, bool rxContinuous ); + +/*! + * \brief Sets the transmission parameters + * + * \param [in] modem Radio modem to be used [0: FSK, 1: LoRa] + * \param [in] power Sets the output power [dBm] + * \param [in] fdev Sets the frequency deviation (FSK only) + * FSK : [Hz] + * LoRa: 0 + * \param [in] bandwidth Sets the bandwidth (LoRa only) + * FSK : 0 + * LoRa: [0: 125 kHz, 1: 250 kHz, + * 2: 500 kHz, 3: Reserved] + * \param [in] datarate Sets the Datarate + * FSK : 600..300000 bits/s + * LoRa: [6: 64, 7: 128, 8: 256, 9: 512, + * 10: 1024, 11: 2048, 12: 4096 chips] + * \param [in] coderate Sets the coding rate (LoRa only) + * FSK : N/A ( set to 0 ) + * LoRa: [1: 4/5, 2: 4/6, 3: 4/7, 4: 4/8] + * \param [in] preambleLen Sets the preamble length + * FSK : Number of bytes + * LoRa: Length in symbols (the hardware adds 4 more symbols) + * \param [in] fixLen Fixed length packets [0: variable, 1: fixed] + * \param [in] crcOn Enables disables the CRC [0: OFF, 1: ON] + * \param [in] FreqHopOn Enables disables the intra-packet frequency hopping + * FSK : N/A ( set to 0 ) + * LoRa: [0: OFF, 1: ON] + * \param [in] HopPeriod Number of symbols between each hop + * FSK : N/A ( set to 0 ) + * LoRa: Number of symbols + * \param [in] iqInverted Inverts IQ signals (LoRa only) + * FSK : N/A ( set to 0 ) + * LoRa: [0: not inverted, 1: inverted] + * \param [in] timeout Transmission timeout [ms] + */ +static void RadioSetTxConfig( RadioModems_t modem, int8_t power, uint32_t fdev, + uint32_t bandwidth, uint32_t datarate, + uint8_t coderate, uint16_t preambleLen, + bool fixLen, bool crcOn, bool FreqHopOn, + uint8_t HopPeriod, bool iqInverted, uint32_t timeout ); + +/*! + * \brief Checks if the given RF frequency is supported by the hardware + * + * \param [in] frequency RF frequency to be checked + * \retval isSupported [true: supported, false: unsupported] + */ +static bool RadioCheckRfFrequency( uint32_t frequency ); + +/*! + * \brief Computes the packet time on air in ms for the given payload + * + * \remark Can only be called once SetRxConfig or SetTxConfig have been called + * + * \param [in] modem Radio modem to be used [0: FSK, 1: LoRa] + * \param [in] bandwidth Sets the bandwidth + * FSK : >= 2600 and <= 250000 Hz + * LoRa: [0: 125 kHz, 1: 250 kHz, + * 2: 500 kHz, 3: Reserved] + * \param [in] datarate Sets the Datarate + * FSK : 600..300000 bits/s + * LoRa: [6: 64, 7: 128, 8: 256, 9: 512, + * 10: 1024, 11: 2048, 12: 4096 chips] + * \param [in] coderate Sets the coding rate (LoRa only) + * FSK : N/A ( set to 0 ) + * LoRa: [1: 4/5, 2: 4/6, 3: 4/7, 4: 4/8] + * \param [in] preambleLen Sets the Preamble length + * FSK : Number of bytes + * LoRa: Length in symbols (the hardware adds 4 more symbols) + * \param [in] fixLen Fixed length packets [0: variable, 1: fixed] + * \param [in] payloadLen Sets payload length when fixed length is used + * \param [in] crcOn Enables/Disables the CRC [0: OFF, 1: ON] + * + * \retval airTime Computed airTime (ms) for the given packet payload length + */ +static uint32_t RadioTimeOnAir( RadioModems_t modem, uint32_t bandwidth, + uint32_t datarate, uint8_t coderate, + uint16_t preambleLen, bool fixLen, uint8_t payloadLen, + bool crcOn ); + +/*! + * \brief Sends the buffer of size. Prepares the packet to be sent and sets + * the radio in transmission + * + * \param [in] buffer Buffer pointer + * \param [in] size Buffer size + * + * \retval status (OK, ERROR, ...) + */ +static radio_status_t RadioSend( uint8_t *buffer, uint8_t size ); + +/*! + * \brief Sets the radio in sleep mode + */ +static void RadioSleep( void ); + +/*! + * \brief Sets the radio in standby mode + */ +static void RadioStandby( void ); + +/*! + * \brief Sets the radio in reception mode for the given time + * \param [in] timeout Reception timeout [ms] + * [0: continuous, others timeout] + */ +static void RadioRx( uint32_t timeout ); + +/*! + * \brief Start a Channel Activity Detection + */ +static void RadioStartCad( void ); + +/*! + * \brief Sets the radio in continuous wave transmission mode + * + * \param [in] freq Channel RF frequency + * \param [in] power Sets the output power [dBm] + * \param [in] time Transmission mode timeout [s] + */ +static void RadioSetTxContinuousWave( uint32_t freq, int8_t power, uint16_t time ); + +/*! + * \brief Reads the current RSSI value + * + * \retval rssiValue Current RSSI value in [dBm] + */ +static int16_t RadioRssi( RadioModems_t modem ); + +/*! + * \brief Writes the radio register at the specified address + * + * \param [in] addr Register address + * \param [in] data New register value + */ +static void RadioWrite( uint16_t addr, uint8_t data ); + +/*! + * \brief Reads the radio register at the specified address + * + * \param [in] addr Register address + * \retval data Register value + */ +static uint8_t RadioRead( uint16_t addr ); + +/*! + * \brief Writes multiple radio registers starting at address + * + * \param [in] addr First Radio register address + * \param [in] buffer Buffer containing the new register's values + * \param [in] size Number of registers to be written + */ +static void RadioWriteRegisters( uint16_t addr, uint8_t *buffer, uint8_t size ); + +/*! + * \brief Reads multiple radio registers starting at address + * + * \param [in] addr First Radio register address + * \param [out] buffer Buffer where to copy the registers data + * \param [in] size Number of registers to be read + */ +static void RadioReadRegisters( uint16_t addr, uint8_t *buffer, uint8_t size ); + +/*! + * \brief Sets the maximum payload length. + * + * \param [in] modem Radio modem to be used [0: FSK, 1: LoRa] + * \param [in] max Maximum payload length in bytes + */ +static void RadioSetMaxPayloadLength( RadioModems_t modem, uint8_t max ); + +/*! + * \brief Sets the network to public or private. Updates the sync byte. + * + * \remark Applies to LoRa modem only + * + * \param [in] enable if true, it enables a public network + */ +static void RadioSetPublicNetwork( bool enable ); + +/*! + * \brief Gets the time required for the board plus radio to get out of sleep.[ms] + * + * \retval time Radio plus board wakeup time in ms. + */ +static uint32_t RadioGetWakeupTime( void ); + +/*! + * \brief Process radio irq + */ +static void RadioIrqProcess( void ); + +/*! + * \brief Sets the radio in reception mode with Max LNA gain for the given time + * \param [in] timeout Reception timeout [ms] + * [0: continuous, others timeout] + */ +static void RadioRxBoosted( uint32_t timeout ); + +/*! + * \brief Sets the Rx duty cycle management parameters + * + * \param [in] rxTime Structure describing reception timeout value + * \param [in] sleepTime Structure describing sleep timeout value + */ +static void RadioSetRxDutyCycle( uint32_t rxTime, uint32_t sleepTime ); + +/*! + * \brief radio IRQ callback + * + * \param [in] radioIrq mask of radio irq + */ +static void RadioOnDioIrq( RadioIrqMasks_t radioIrq ); + +/*! + * \brief Tx timeout timer callback + * + * \param [in] context context of the interrupt + */ +static void RadioOnTxTimeoutIrq( void *context ); + +/*! + * \brief Rx timeout timer callback + * + * \param [in] context context of the interrupt + */ +static void RadioOnRxTimeoutIrq( void *context ); + +/*! + * \brief Rx timeout timer process + */ +static void RadioOnRxTimeoutProcess( void ); + +/*! + * \brief Tx timeout timer process + */ +static void RadioOnTxTimeoutProcess( void ); + +#if( RADIO_LR_FHSS_IS_ON == 1 ) +static uint32_t prbs31_val = 0xAA; +#endif /* RADIO_LR_FHSS_IS_ON == 1 */ + +#if (RADIO_SIGFOX_ENABLE == 1) +/*! + * @brief D-BPSK to BPSK + * + * @param [out] outBuffer buffer with frame encoded + * @param [in] inBuffer buffer with frame to encode + * @param [in] size size of the payload to encode + */ +static void payload_integration( uint8_t *outBuffer, uint8_t *inBuffer, uint8_t size ); +#endif /*RADIO_SIGFOX_ENABLE == 1*/ +/*! + * \brief Sets the Transmitter in continuous PRBS mode + */ +static void RadioTxPrbs( void ); + +/*! + * \brief Sets the Transmitter in continuous un-modulated Carrier mode at power dBm + * + * \param [in] power Tx power in dBm + */ +static void RadioTxCw( int8_t power ); + +/*! + * \brief Sets the reception parameters + * + * \param [in] modem Radio modem to be used [GENERIC_FSK or GENERIC_FSK] + * \param [in] config configuration of receiver + * fsk field to be used if modem =GENERIC_FSK +* lora field to be used if modem =GENERIC_LORA + * \param [in] rxContinuous Sets the reception in continuous mode + * [0: single mode, otherwise continuous mode] + * \param [in] symbTimeout Sets the RxSingle timeout value + * FSK : timeout in number of bytes + * LoRa: timeout in symbols + * \return 0 when no parameters error, -1 otherwise + */ +static int32_t RadioSetRxGenericConfig( GenericModems_t modem, RxConfigGeneric_t *config, + uint32_t rxContinuous, uint32_t symbTimeout ); + +/*! + * \brief Sets the transmission parameters + * + * \param [in] modem Radio modem to be used [GENERIC_FSK or GENERIC_FSK or GENERIC_BPSK] + * \param [in] config configuration of receiver + * fsk field to be used if modem =GENERIC_FSK +* lora field to be used if modem =GENERIC_LORA + bpsk field to be used if modem =GENERIC_BPSK + * \param [in] power Sets the output power [dBm] + * \param [in] timeout Transmission timeout [ms] + * \return 0 when no parameters error, -1 otherwise + */ +static int32_t RadioSetTxGenericConfig( GenericModems_t modem, TxConfigGeneric_t *config, + int8_t power, uint32_t timeout ); + +/*! + * \brief Configure the radio LR-FHSS modem parameters + * + * \param [in] cfg_params LR-FHSS modem configuration parameters + * + * \returns Operation status + */ +static radio_status_t RadioLrFhssSetCfg( const radio_lr_fhss_cfg_params_t *cfg_params ); + +/*! + * \brief Get the time on air in millisecond for LR-FHSS packet + * + * \param [in] params Pointer to LR-FHSS time on air parameters + * \param [out] time_on_air_in_ms time on air parameters results in ms + * + * \returns Time-on-air value in ms for LR-FHSS packet + */ +static radio_status_t RadioLrFhssGetTimeOnAirInMs( const radio_lr_fhss_time_on_air_params_t *params, uint32_t *time_on_air_in_ms ); + +/*! + * \brief Convert the bandwidth enum to Hz value + * + * \param [in] bw RF frequency to be checked + * \retval bandwidthInHz bandwidth value in Hertz + */ +static uint32_t RadioGetLoRaBandwidthInHz( RadioLoRaBandwidths_t bw ); + +/*! + * \brief Computes the time on air GFSK numerator + * + * \param [in] datarate Sets the Datarate + * FSK : 600..300000 bits/s + * LoRa: [6: 64, 7: 128, 8: 256, 9: 512, + * 10: 1024, 11: 2048, 12: 4096 chips] + * \param [in] coderate Sets the coding rate (LoRa only) + * FSK : N/A ( set to 0 ) + * LoRa: [1: 4/5, 2: 4/6, 3: 4/7, 4: 4/8] + * \param [in] preambleLen Sets the Preamble length + * FSK : Number of bytes + * LoRa: Length in symbols (the hardware adds 4 more symbols) + * \param [in] fixLen Fixed length packets [0: variable, 1: fixed] + * \param [in] payloadLen Sets payload length when fixed length is used + * \param [in] crcOn Enables/Disables the CRC [0: OFF, 1: ON] + * \retval numerator time on air GFSK numerator + */ +static uint32_t RadioGetGfskTimeOnAirNumerator( uint32_t datarate, uint8_t coderate, + uint16_t preambleLen, bool fixLen, uint8_t payloadLen, + bool crcOn ); + +/*! + * \brief Computes the time on air LoRa numerator + * + * \param [in] bandwidth Sets the bandwidth + * FSK : >= 2600 and <= 250000 Hz + * LoRa: [0: 125 kHz, 1: 250 kHz, + * 2: 500 kHz, 3: Reserved] + * \param [in] datarate Sets the Datarate + * FSK : 600..300000 bits/s + * LoRa: [6: 64, 7: 128, 8: 256, 9: 512, + * 10: 1024, 11: 2048, 12: 4096 chips] + * \param [in] coderate Sets the coding rate (LoRa only) + * FSK : N/A ( set to 0 ) + * LoRa: [1: 4/5, 2: 4/6, 3: 4/7, 4: 4/8] + * \param [in] preambleLen Sets the Preamble length + * FSK : Number of bytes + * LoRa: Length in symbols (the hardware adds 4 more symbols) + * \param [in] fixLen Fixed length packets [0: variable, 1: fixed] + * \param [in] payloadLen Sets payload length when fixed length is used + * \param [in] crcOn Enables/Disables the CRC [0: OFF, 1: ON] + * \retval numerator time on air LoRa numerator + */ +static uint32_t RadioGetLoRaTimeOnAirNumerator( uint32_t bandwidth, + uint32_t datarate, uint8_t coderate, + uint16_t preambleLen, bool fixLen, uint8_t payloadLen, + bool crcOn ); + +#if( RADIO_LR_FHSS_IS_ON == 1 ) +static uint32_t GetNextFreqIdx( uint32_t max ); +#endif /* RADIO_LR_FHSS_IS_ON == 1 */ + +/* Private variables ---------------------------------------------------------*/ +/*! + * Radio driver structure initialization + */ +const struct Radio_s Radio = +{ + RadioInit, + RadioGetStatus, + RadioSetModem, + RadioSetChannel, + RadioIsChannelFree, + RadioRandom, + RadioSetRxConfig, + RadioSetTxConfig, + RadioCheckRfFrequency, + RadioTimeOnAir, + RadioSend, + RadioSleep, + RadioStandby, + RadioRx, + RadioStartCad, + RadioSetTxContinuousWave, + RadioRssi, + RadioWrite, + RadioRead, + RadioWriteRegisters, + RadioReadRegisters, + RadioSetMaxPayloadLength, + RadioSetPublicNetwork, + RadioGetWakeupTime, + RadioIrqProcess, + RadioRxBoosted, + RadioSetRxDutyCycle, + RadioTxPrbs, + RadioTxCw, + RadioSetRxGenericConfig, + RadioSetTxGenericConfig, + RFW_TransmitLongPacket, + RFW_ReceiveLongPacket, + /* LrFhss extended radio functions */ + RadioLrFhssSetCfg, + RadioLrFhssGetTimeOnAirInMs +}; + +const RadioLoRaBandwidths_t Bandwidths[] = { LORA_BW_125, LORA_BW_250, LORA_BW_500 }; + +static uint8_t MaxPayloadLength = RADIO_BUF_SIZE; + +static uint8_t RadioBuffer[RADIO_BUF_SIZE]; + +/* + * Radio callbacks variable + */ +static RadioEvents_t *RadioEvents; + +/*! + * Radio hardware and global parameters + */ +SubgRf_t SubgRf; + +/*! + * Tx and Rx timers + */ +TimerEvent_t TxTimeoutTimer; +TimerEvent_t RxTimeoutTimer; + +/* Private functions ---------------------------------------------------------*/ + +static void RadioInit( RadioEvents_t *events ) +{ + RadioEvents = events; + + SubgRf.RxContinuous = false; + SubgRf.TxTimeout = 0; + SubgRf.RxTimeout = 0; + /*See STM32WL Errata: RadioSetRxDutyCycle*/ + SubgRf.RxDcPreambleDetectTimeout = 0; +#if( RADIO_LR_FHSS_IS_ON == 1 ) + SubgRf.lr_fhss.is_lr_fhss_on = false; +#endif /* RADIO_LR_FHSS_IS_ON == 1 */ + SUBGRF_Init( RadioOnDioIrq ); + /*SubgRf.publicNetwork set to false*/ + SubgRf.PublicNetwork.Current = false; + SubgRf.PublicNetwork.Previous = false; + + RADIO_IRQ_PROCESS_INIT(); + + SUBGRF_SetRegulatorMode( ); + + SUBGRF_SetBufferBaseAddress( 0x00, 0x00 ); + SUBGRF_SetTxParams( RFO_LP, 0, RADIO_RAMP_200_US ); + SUBGRF_SetDioIrqParams( IRQ_RADIO_ALL, IRQ_RADIO_ALL, IRQ_RADIO_NONE, IRQ_RADIO_NONE ); + + RadioSleep(); + // Initialize driver timeout timers + TimerInit( &TxTimeoutTimer, RadioOnTxTimeoutIrq ); + TimerInit( &RxTimeoutTimer, RadioOnRxTimeoutIrq ); + TimerStop( &TxTimeoutTimer ); + TimerStop( &RxTimeoutTimer ); +} + +static RadioState_t RadioGetStatus( void ) +{ + switch( SUBGRF_GetOperatingMode( ) ) + { + case MODE_TX: + return RF_TX_RUNNING; + case MODE_RX: + return RF_RX_RUNNING; + case MODE_CAD: + return RF_CAD; + default: + return RF_IDLE; + } +} + +static void RadioSetModem( RadioModems_t modem ) +{ + SubgRf.Modem = modem; + RFW_SetRadioModem( modem ); + switch( modem ) + { + default: + case MODEM_MSK: + SUBGRF_SetPacketType( PACKET_TYPE_GMSK ); + // When switching to GFSK mode the LoRa SyncWord register value is reset + // Thus, we also reset the RadioPublicNetwork variable + SubgRf.PublicNetwork.Current = false; + break; + case MODEM_FSK: + SUBGRF_SetPacketType( PACKET_TYPE_GFSK ); + // When switching to GFSK mode the LoRa SyncWord register value is reset + // Thus, we also reset the RadioPublicNetwork variable + SubgRf.PublicNetwork.Current = false; + break; + case MODEM_LORA: + SUBGRF_SetPacketType( PACKET_TYPE_LORA ); + // Public/Private network register is reset when switching modems + if( SubgRf.PublicNetwork.Current != SubgRf.PublicNetwork.Previous ) + { + SubgRf.PublicNetwork.Current = SubgRf.PublicNetwork.Previous; + RadioSetPublicNetwork( SubgRf.PublicNetwork.Current ); + } + break; + case MODEM_BPSK: + SUBGRF_SetPacketType( PACKET_TYPE_BPSK ); + // When switching to BPSK mode the LoRa SyncWord register value is reset + // Thus, we also reset the RadioPublicNetwork variable + SubgRf.PublicNetwork.Current = false; + break; +#if (RADIO_SIGFOX_ENABLE == 1) + case MODEM_SIGFOX_TX: + SUBGRF_SetPacketType( PACKET_TYPE_BPSK ); + // When switching to BPSK mode the LoRa SyncWord register value is reset + // Thus, we also reset the RadioPublicNetwork variable + SubgRf.PublicNetwork.Current = false; + break; + case MODEM_SIGFOX_RX: + SUBGRF_SetPacketType( PACKET_TYPE_GFSK ); + // When switching to GFSK mode the LoRa SyncWord register value is reset + // Thus, we also reset the RadioPublicNetwork variable + SubgRf.PublicNetwork.Current = false; + break; +#endif /*RADIO_SIGFOX_ENABLE == 1*/ + } +} + +static void RadioSetChannel( uint32_t freq ) +{ + SUBGRF_SetRfFrequency( freq ); +} + +static bool RadioIsChannelFree( uint32_t freq, uint32_t rxBandwidth, int16_t rssiThresh, uint32_t maxCarrierSenseTime ) +{ + bool status = true; + int16_t rssi = 0; + uint32_t carrierSenseTime = 0; + + RadioStandby( ); + + RadioSetModem( MODEM_FSK ); + + RadioSetChannel( freq ); + + // Set Rx bandwidth. Other parameters are not used. + RadioSetRxConfig( MODEM_FSK, rxBandwidth, 600, 0, rxBandwidth, 3, 0, false, + 0, false, 0, 0, false, true ); + RadioRx( 0 ); + + RADIO_DELAY_MS( RadioGetWakeupTime( ) ); + + carrierSenseTime = TimerGetCurrentTime( ); + + // Perform carrier sense for maxCarrierSenseTime + while( TimerGetElapsedTime( carrierSenseTime ) < maxCarrierSenseTime ) + { + rssi = RadioRssi( MODEM_FSK ); + + if( rssi > rssiThresh ) + { + status = false; + break; + } + } + RadioStandby( ); + + return status; +} + +static uint32_t RadioRandom( void ) +{ + uint32_t rnd = 0; + + /* + * Radio setup for random number generation + */ + // Disable modem interrupts + SUBGRF_SetDioIrqParams( IRQ_RADIO_NONE, IRQ_RADIO_NONE, IRQ_RADIO_NONE, IRQ_RADIO_NONE ); + + rnd = SUBGRF_GetRandom(); + + return rnd; +} + +static void RadioSetRxConfig( RadioModems_t modem, uint32_t bandwidth, + uint32_t datarate, uint8_t coderate, + uint32_t bandwidthAfc, uint16_t preambleLen, + uint16_t symbTimeout, bool fixLen, + uint8_t payloadLen, + bool crcOn, bool freqHopOn, uint8_t hopPeriod, + bool iqInverted, bool rxContinuous ) +{ +#if (RADIO_SIGFOX_ENABLE == 1) + uint8_t modReg; +#endif + SubgRf.RxContinuous = rxContinuous; + RFW_DeInit(); + if( rxContinuous == true ) + { + symbTimeout = 0; + } + if( fixLen == true ) + { + MaxPayloadLength = payloadLen; + } + else + { + MaxPayloadLength = 0xFF; + } + + switch( modem ) + { +#if (RADIO_SIGFOX_ENABLE == 1) + case MODEM_SIGFOX_RX: + SUBGRF_SetStopRxTimerOnPreambleDetect( true ); + SubgRf.ModulationParams.PacketType = PACKET_TYPE_GFSK; + + SubgRf.ModulationParams.Params.Gfsk.BitRate = datarate; + SubgRf.ModulationParams.Params.Gfsk.ModulationShaping = MOD_SHAPING_G_BT_05; + SubgRf.ModulationParams.Params.Gfsk.Fdev = 800; + SubgRf.ModulationParams.Params.Gfsk.Bandwidth = SUBGRF_GetFskBandwidthRegValue( bandwidth ); + + SubgRf.PacketParams.PacketType = PACKET_TYPE_GFSK; + SubgRf.PacketParams.Params.Gfsk.PreambleLength = ( preambleLen << 3 ); // convert byte into bit + SubgRf.PacketParams.Params.Gfsk.PreambleMinDetect = RADIO_PREAMBLE_DETECTOR_OFF; + SubgRf.PacketParams.Params.Gfsk.SyncWordLength = 2 << 3; // convert byte into bit + SubgRf.PacketParams.Params.Gfsk.AddrComp = RADIO_ADDRESSCOMP_FILT_OFF; + SubgRf.PacketParams.Params.Gfsk.HeaderType = RADIO_PACKET_FIXED_LENGTH; + SubgRf.PacketParams.Params.Gfsk.PayloadLength = MaxPayloadLength; + SubgRf.PacketParams.Params.Gfsk.CrcLength = RADIO_CRC_OFF; + + SubgRf.PacketParams.Params.Gfsk.DcFree = RADIO_DC_FREE_OFF; + + RadioSetModem( MODEM_SIGFOX_RX ); + SUBGRF_SetModulationParams( &SubgRf.ModulationParams ); + SUBGRF_SetPacketParams( &SubgRf.PacketParams ); + SUBGRF_SetSyncWord( ( uint8_t[] ){0xB2, 0x27, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 } ); + SUBGRF_SetWhiteningSeed( 0x01FF ); + + /* NO gfo reset (better sensitivity). Reg 0x8b8, bit4 = 0 */ + modReg= RadioRead(SUBGHZ_AGCGFORSTCFGR); + modReg&=RADIO_BIT_MASK(4); + RadioWrite(SUBGHZ_AGCGFORSTCFGR, modReg); + /* Lower the threshold of cfo_reset */ + RadioWrite(SUBGHZ_AGCGFORSTPOWTHR, 0x4 ); + + /* Bigger rssi_len (stability AGC). Reg 0x89b, bits[2 :4] = 0x1 */ + modReg= RadioRead(SUBGHZ_AGCRSSICTL0R); + modReg&=( RADIO_BIT_MASK(2) & RADIO_BIT_MASK(3) & RADIO_BIT_MASK(4) ); + RadioWrite(SUBGHZ_AGCRSSICTL0R, (modReg| (0x1<<3) ) ); + + /* Bigger afc_pbl_len (better frequency correction). Reg 0x6d1, bits[3 :4] = 0x3 */ + modReg= RadioRead(SUBGHZ_GAFCR); + modReg&=( RADIO_BIT_MASK(3) & RADIO_BIT_MASK(4) ); + RadioWrite(SUBGHZ_GAFCR, (modReg| (0x3<<3) )); + + /* Use of new bit synchronizer (to avoid CRC errors during PER for payloads with a small amount of transitions). Reg 0x6ac, bits[4 :6] = 0x5 */ + modReg= RadioRead(SUBGHZ_GBSYNCR); + modReg&=( RADIO_BIT_MASK(4) & RADIO_BIT_MASK(5) & RADIO_BIT_MASK(6) ); + RadioWrite(SUBGHZ_GBSYNCR, (modReg| (0x5<<4) )); + /*timeout unused when SubgRf.RxContinuous*/ + SubgRf.RxTimeout = ( uint32_t )(( symbTimeout * 8 * 1000 ) /datarate); + break; +#endif /*RADIO_SIGFOX_ENABLE == 1*/ + case MODEM_FSK: + SUBGRF_SetStopRxTimerOnPreambleDetect( false ); + SubgRf.ModulationParams.PacketType = PACKET_TYPE_GFSK; + + SubgRf.ModulationParams.Params.Gfsk.BitRate = datarate; + SubgRf.ModulationParams.Params.Gfsk.ModulationShaping = MOD_SHAPING_G_BT_1; + SubgRf.ModulationParams.Params.Gfsk.Bandwidth = SUBGRF_GetFskBandwidthRegValue( bandwidth ); + + SubgRf.PacketParams.PacketType = PACKET_TYPE_GFSK; + SubgRf.PacketParams.Params.Gfsk.PreambleLength = ( preambleLen << 3 ); // convert byte into bit + SubgRf.PacketParams.Params.Gfsk.PreambleMinDetect = RADIO_PREAMBLE_DETECTOR_08_BITS; + SubgRf.PacketParams.Params.Gfsk.SyncWordLength = 3 << 3; // convert byte into bit + SubgRf.PacketParams.Params.Gfsk.AddrComp = RADIO_ADDRESSCOMP_FILT_OFF; + SubgRf.PacketParams.Params.Gfsk.HeaderType = ( fixLen == true ) ? RADIO_PACKET_FIXED_LENGTH : RADIO_PACKET_VARIABLE_LENGTH; + SubgRf.PacketParams.Params.Gfsk.PayloadLength = MaxPayloadLength; + if( crcOn == true ) + { + SubgRf.PacketParams.Params.Gfsk.CrcLength = RADIO_CRC_2_BYTES_CCIT; + } + else + { + SubgRf.PacketParams.Params.Gfsk.CrcLength = RADIO_CRC_OFF; + } + SubgRf.PacketParams.Params.Gfsk.DcFree = RADIO_DC_FREEWHITENING; + + RadioStandby( ); + RadioSetModem( MODEM_FSK ); + SUBGRF_SetModulationParams( &SubgRf.ModulationParams ); + SUBGRF_SetPacketParams( &SubgRf.PacketParams ); + SUBGRF_SetSyncWord( ( uint8_t[] ){ 0xC1, 0x94, 0xC1, 0x00, 0x00, 0x00, 0x00, 0x00 } ); + SUBGRF_SetWhiteningSeed( 0x01FF ); + + /*timeout unused when SubgRf.RxContinuous*/ + SubgRf.RxTimeout = ( uint32_t )(( symbTimeout * 8 * 1000 ) /datarate); + break; + + case MODEM_LORA: + SUBGRF_SetStopRxTimerOnPreambleDetect( false ); + SubgRf.ModulationParams.PacketType = PACKET_TYPE_LORA; + SubgRf.ModulationParams.Params.LoRa.SpreadingFactor = ( RadioLoRaSpreadingFactors_t )datarate; + SubgRf.ModulationParams.Params.LoRa.Bandwidth = Bandwidths[bandwidth]; + SubgRf.ModulationParams.Params.LoRa.CodingRate = ( RadioLoRaCodingRates_t )coderate; + + if( ( ( bandwidth == 0 ) && ( ( datarate == 11 ) || ( datarate == 12 ) ) ) || + ( ( bandwidth == 1 ) && ( datarate == 12 ) ) ) + { + SubgRf.ModulationParams.Params.LoRa.LowDatarateOptimize = 0x01; + } + else + { + SubgRf.ModulationParams.Params.LoRa.LowDatarateOptimize = 0x00; + } + + SubgRf.PacketParams.PacketType = PACKET_TYPE_LORA; + + if( ( SubgRf.ModulationParams.Params.LoRa.SpreadingFactor == LORA_SF5 ) || + ( SubgRf.ModulationParams.Params.LoRa.SpreadingFactor == LORA_SF6 ) ) + { + if( preambleLen < 12 ) + { + SubgRf.PacketParams.Params.LoRa.PreambleLength = 12; + } + else + { + SubgRf.PacketParams.Params.LoRa.PreambleLength = preambleLen; + } + } + else + { + SubgRf.PacketParams.Params.LoRa.PreambleLength = preambleLen; + } + + SubgRf.PacketParams.Params.LoRa.HeaderType = ( RadioLoRaPacketLengthsMode_t )fixLen; + + SubgRf.PacketParams.Params.LoRa.PayloadLength = MaxPayloadLength; + SubgRf.PacketParams.Params.LoRa.CrcMode = ( RadioLoRaCrcModes_t )crcOn; + SubgRf.PacketParams.Params.LoRa.InvertIQ = ( RadioLoRaIQModes_t )iqInverted; + + RadioStandby( ); + RadioSetModem( MODEM_LORA ); + SUBGRF_SetModulationParams( &SubgRf.ModulationParams ); + SUBGRF_SetPacketParams( &SubgRf.PacketParams ); + SUBGRF_SetLoRaSymbNumTimeout( symbTimeout ); + + /* WORKAROUND - Set the step threshold value to 1 to avoid to miss low power signal after an interferer jam the chip in LoRa modulaltion */ + SUBGRF_WriteRegister(SUBGHZ_AGCCFG,SUBGRF_ReadRegister(SUBGHZ_AGCCFG)&0x1); + + /* WORKAROUND - Optimizing the Inverted IQ Operation, see STM32WL Erratasheet */ + if( SubgRf.PacketParams.Params.LoRa.InvertIQ == LORA_IQ_INVERTED ) + { + // RegIqPolaritySetup = @address 0x0736 + SUBGRF_WriteRegister( SUBGHZ_LIQPOLR, SUBGRF_ReadRegister( SUBGHZ_LIQPOLR ) & ~( 1 << 2 ) ); + } + else + { + // RegIqPolaritySetup @address 0x0736 + SUBGRF_WriteRegister( SUBGHZ_LIQPOLR, SUBGRF_ReadRegister( SUBGHZ_LIQPOLR ) | ( 1 << 2 ) ); + } + /* WORKAROUND END */ + + // Timeout Max, Timeout handled directly in SetRx function + SubgRf.RxTimeout = 0xFFFF; + + break; + default: + break; + } +} + +static void RadioSetTxConfig( RadioModems_t modem, int8_t power, uint32_t fdev, + uint32_t bandwidth, uint32_t datarate, + uint8_t coderate, uint16_t preambleLen, + bool fixLen, bool crcOn, bool freqHopOn, + uint8_t hopPeriod, bool iqInverted, uint32_t timeout ) +{ +#if( RADIO_LR_FHSS_IS_ON == 1 ) + /*disable LrFhss*/ + SubgRf.lr_fhss.is_lr_fhss_on = false; +#endif /* RADIO_LR_FHSS_IS_ON == 1 */ + RFW_DeInit(); + switch( modem ) + { + case MODEM_FSK: + SubgRf.ModulationParams.PacketType = PACKET_TYPE_GFSK; + SubgRf.ModulationParams.Params.Gfsk.BitRate = datarate; + + SubgRf.ModulationParams.Params.Gfsk.ModulationShaping = MOD_SHAPING_G_BT_1; + SubgRf.ModulationParams.Params.Gfsk.Bandwidth = SUBGRF_GetFskBandwidthRegValue( bandwidth ); + SubgRf.ModulationParams.Params.Gfsk.Fdev = fdev; + + SubgRf.PacketParams.PacketType = PACKET_TYPE_GFSK; + SubgRf.PacketParams.Params.Gfsk.PreambleLength = ( preambleLen << 3 ); // convert byte into bit + SubgRf.PacketParams.Params.Gfsk.PreambleMinDetect = RADIO_PREAMBLE_DETECTOR_08_BITS; + SubgRf.PacketParams.Params.Gfsk.SyncWordLength = 3 << 3 ; // convert byte into bit + SubgRf.PacketParams.Params.Gfsk.AddrComp = RADIO_ADDRESSCOMP_FILT_OFF; + SubgRf.PacketParams.Params.Gfsk.HeaderType = ( fixLen == true ) ? RADIO_PACKET_FIXED_LENGTH : RADIO_PACKET_VARIABLE_LENGTH; + + if( crcOn == true ) + { + SubgRf.PacketParams.Params.Gfsk.CrcLength = RADIO_CRC_2_BYTES_CCIT; + } + else + { + SubgRf.PacketParams.Params.Gfsk.CrcLength = RADIO_CRC_OFF; + } + SubgRf.PacketParams.Params.Gfsk.DcFree = RADIO_DC_FREEWHITENING; + + RadioStandby( ); + RadioSetModem( MODEM_FSK ); + SUBGRF_SetModulationParams( &SubgRf.ModulationParams ); + SUBGRF_SetPacketParams( &SubgRf.PacketParams ); + SUBGRF_SetSyncWord( ( uint8_t[] ){ 0xC1, 0x94, 0xC1, 0x00, 0x00, 0x00, 0x00, 0x00 } ); + SUBGRF_SetWhiteningSeed( 0x01FF ); + break; + + case MODEM_LORA: + SubgRf.ModulationParams.PacketType = PACKET_TYPE_LORA; + SubgRf.ModulationParams.Params.LoRa.SpreadingFactor = ( RadioLoRaSpreadingFactors_t ) datarate; + SubgRf.ModulationParams.Params.LoRa.Bandwidth = Bandwidths[bandwidth]; + SubgRf.ModulationParams.Params.LoRa.CodingRate= ( RadioLoRaCodingRates_t )coderate; + + if( ( ( bandwidth == 0 ) && ( ( datarate == 11 ) || ( datarate == 12 ) ) ) || + ( ( bandwidth == 1 ) && ( datarate == 12 ) ) ) + { + SubgRf.ModulationParams.Params.LoRa.LowDatarateOptimize = 0x01; + } + else + { + SubgRf.ModulationParams.Params.LoRa.LowDatarateOptimize = 0x00; + } + + SubgRf.PacketParams.PacketType = PACKET_TYPE_LORA; + + if( ( SubgRf.ModulationParams.Params.LoRa.SpreadingFactor == LORA_SF5 ) || + ( SubgRf.ModulationParams.Params.LoRa.SpreadingFactor == LORA_SF6 ) ) + { + if( preambleLen < 12 ) + { + SubgRf.PacketParams.Params.LoRa.PreambleLength = 12; + } + else + { + SubgRf.PacketParams.Params.LoRa.PreambleLength = preambleLen; + } + } + else + { + SubgRf.PacketParams.Params.LoRa.PreambleLength = preambleLen; + } + SubgRf.PacketParams.Params.LoRa.HeaderType = ( RadioLoRaPacketLengthsMode_t )fixLen; + SubgRf.PacketParams.Params.LoRa.PayloadLength = MaxPayloadLength; + SubgRf.PacketParams.Params.LoRa.CrcMode = ( RadioLoRaCrcModes_t )crcOn; + SubgRf.PacketParams.Params.LoRa.InvertIQ = ( RadioLoRaIQModes_t )iqInverted; + + RadioStandby( ); + RadioSetModem( MODEM_LORA ); + SUBGRF_SetModulationParams( &SubgRf.ModulationParams ); + SUBGRF_SetPacketParams( &SubgRf.PacketParams ); + break; +#if (RADIO_SIGFOX_ENABLE == 1) + case MODEM_SIGFOX_TX: + RadioSetModem(MODEM_SIGFOX_TX); + SubgRf.ModulationParams.PacketType = PACKET_TYPE_BPSK; + SubgRf.ModulationParams.Params.Bpsk.BitRate = datarate; + SubgRf.ModulationParams.Params.Bpsk.ModulationShaping = MOD_SHAPING_DBPSK; + SUBGRF_SetModulationParams( &SubgRf.ModulationParams ); + break; +#endif /*RADIO_SIGFOX_ENABLE == 1*/ + default: + break; + } + + SubgRf.AntSwitchPaSelect = SUBGRF_SetRfTxPower( power ); + /* WORKAROUND - Trimming the output voltage power_ldo to 3.3V */ + SUBGRF_WriteRegister(REG_DRV_CTRL, 0x7 << 1); + RFW_SetAntSwitch( SubgRf.AntSwitchPaSelect ); + SubgRf.TxTimeout = timeout; +} + +static bool RadioCheckRfFrequency( uint32_t frequency ) +{ + return true; +} + +static uint32_t RadioGetLoRaBandwidthInHz( RadioLoRaBandwidths_t bw ) +{ + uint32_t bandwidthInHz = 0; + + switch( bw ) + { + case LORA_BW_007: + bandwidthInHz = 7812UL; + break; + case LORA_BW_010: + bandwidthInHz = 10417UL; + break; + case LORA_BW_015: + bandwidthInHz = 15625UL; + break; + case LORA_BW_020: + bandwidthInHz = 20833UL; + break; + case LORA_BW_031: + bandwidthInHz = 31250UL; + break; + case LORA_BW_041: + bandwidthInHz = 41667UL; + break; + case LORA_BW_062: + bandwidthInHz = 62500UL; + break; + case LORA_BW_125: + bandwidthInHz = 125000UL; + break; + case LORA_BW_250: + bandwidthInHz = 250000UL; + break; + case LORA_BW_500: + bandwidthInHz = 500000UL; + break; + } + + return bandwidthInHz; +} + +static uint32_t RadioGetGfskTimeOnAirNumerator( uint32_t datarate, uint8_t coderate, + uint16_t preambleLen, bool fixLen, uint8_t payloadLen, + bool crcOn ) +{ + return ( preambleLen << 3 ) + + ( ( fixLen == false ) ? 8 : 0 ) + 24 + + ( ( payloadLen + ( ( crcOn == true ) ? 2 : 0 ) ) << 3 ); +} + +static uint32_t RadioGetLoRaTimeOnAirNumerator( uint32_t bandwidth, + uint32_t datarate, uint8_t coderate, + uint16_t preambleLen, bool fixLen, uint8_t payloadLen, + bool crcOn ) +{ + int32_t crDenom = coderate + 4; + bool lowDatareOptimize = false; + + // Ensure that the preamble length is at least 12 symbols when using SF5 or SF6 + if( ( datarate == 5 ) || ( datarate == 6 ) ) + { + if( preambleLen < 12 ) + { + preambleLen = 12; + } + } + + if( ( ( bandwidth == 0 ) && ( ( datarate == 11 ) || ( datarate == 12 ) ) ) || + ( ( bandwidth == 1 ) && ( datarate == 12 ) ) ) + { + lowDatareOptimize = true; + } + + int32_t ceilDenominator; + int32_t ceilNumerator = ( payloadLen << 3 ) + + ( crcOn ? 16 : 0 ) - + ( 4 * datarate ) + + ( fixLen ? 0 : 20 ); + + if( datarate <= 6 ) + { + ceilDenominator = 4 * datarate; + } + else + { + ceilNumerator += 8; + + if( lowDatareOptimize == true ) + { + ceilDenominator = 4 * ( datarate - 2 ); + } + else + { + ceilDenominator = 4 * datarate; + } + } + + if( ceilNumerator < 0 ) + { + ceilNumerator = 0; + } + + // Perform integral ceil() + int32_t intermediate = + ( ( ceilNumerator + ceilDenominator - 1 ) / ceilDenominator ) * crDenom + preambleLen + 12; + + if( datarate <= 6 ) + { + intermediate += 2; + } + + return ( uint32_t )( ( 4 * intermediate + 1 ) * ( 1 << ( datarate - 2 ) ) ); +} + +static uint32_t RadioTimeOnAir( RadioModems_t modem, uint32_t bandwidth, + uint32_t datarate, uint8_t coderate, + uint16_t preambleLen, bool fixLen, uint8_t payloadLen, + bool crcOn ) +{ + uint32_t numerator = 0; + uint32_t denominator = 1; + + switch( modem ) + { + case MODEM_FSK: + { + numerator = 1000U * RadioGetGfskTimeOnAirNumerator( datarate, coderate, + preambleLen, fixLen, + payloadLen, crcOn ); + denominator = datarate; + } + break; + case MODEM_LORA: + { + numerator = 1000U * RadioGetLoRaTimeOnAirNumerator( bandwidth, datarate, + coderate, preambleLen, + fixLen, payloadLen, crcOn ); + denominator = RadioGetLoRaBandwidthInHz( Bandwidths[bandwidth] ); + } + break; + default: + break; + } + // Perform integral ceil() + return DIVC( numerator, denominator ); +} + +static radio_status_t RadioSend( uint8_t *buffer, uint8_t size ) +{ + SUBGRF_SetDioIrqParams( IRQ_TX_DONE | IRQ_RX_TX_TIMEOUT | IRQ_TX_DBG, + IRQ_TX_DONE | IRQ_RX_TX_TIMEOUT | IRQ_TX_DBG, + IRQ_RADIO_NONE, + IRQ_RADIO_NONE ); + + /* Set DBG pin */ + DBG_GPIO_RADIO_TX( SET ); + + /* Set RF switch */ + SUBGRF_SetSwitch( SubgRf.AntSwitchPaSelect, RFSWITCH_TX ); + /* WORKAROUND - Modulation Quality with 500 kHz LoRaTM Bandwidth*/ + /* RegTxModulation = @address 0x0889 */ + if( ( SubgRf.Modem == MODEM_LORA ) && ( SubgRf.ModulationParams.Params.LoRa.Bandwidth == LORA_BW_500 ) ) + { + SUBGRF_WriteRegister( SUBGHZ_SDCFG0R, SUBGRF_ReadRegister( SUBGHZ_SDCFG0R ) & ~( 1 << 2 ) ); + } + else + { + SUBGRF_WriteRegister( SUBGHZ_SDCFG0R, SUBGRF_ReadRegister( SUBGHZ_SDCFG0R ) | ( 1 << 2 ) ); + } +#if( RADIO_LR_FHSS_IS_ON == 1 ) + //ral_lr_fhss_memory_state_t lr_fhss_state = radio_board_get_lr_fhss_state_reference( ); + + if( SubgRf.lr_fhss.is_lr_fhss_on == true ) + { + uint32_t hop_sequence_count = lr_fhss_get_hop_sequence_count( &SubgRf.lr_fhss.lr_fhss_params.lr_fhss_params ); + SubgRf.lr_fhss.hop_sequence_id = GetNextFreqIdx( hop_sequence_count ); + MW_LOG( TS_ON, VLEVEL_M, "LRFHSS HOPSEQ %d\r\n", SubgRf.lr_fhss.hop_sequence_id ); + if( RADIO_STATUS_OK != wl_lr_fhss_build_frame( &SubgRf.lr_fhss.lr_fhss_params, &SubgRf.lr_fhss.lr_fhss_state, + SubgRf.lr_fhss.hop_sequence_id, buffer, size, NULL ) ) + { + return RADIO_STATUS_ERROR; + } + + SUBGRF_SetDioIrqParams( IRQ_TX_DONE | IRQ_LR_FHSS_HOP | IRQ_RX_TX_TIMEOUT | IRQ_TX_DBG, + IRQ_TX_DONE | IRQ_LR_FHSS_HOP | IRQ_RX_TX_TIMEOUT | IRQ_TX_DBG, + IRQ_RADIO_NONE, + IRQ_RADIO_NONE ); + + SUBGRF_SetTx( SubgRf.TxTimeout << 6 ); + } + else +#endif /* RADIO_LR_FHSS_IS_ON == 1 */ + { + /* WORKAROUND END */ + switch( SubgRf.Modem ) + { + case MODEM_LORA: + { + SubgRf.PacketParams.Params.LoRa.PayloadLength = size; + SUBGRF_SetPacketParams( &SubgRf.PacketParams ); + SUBGRF_SendPayload( buffer, size, 0 ); + break; + } + case MODEM_MSK: + case MODEM_FSK: + { + if ( 1UL == RFW_Is_Init( ) ) + { + uint8_t outsize; + if ( 0UL == RFW_TransmitInit( buffer,size, &outsize ) ) + { + SubgRf.PacketParams.Params.Gfsk.PayloadLength = outsize; + SUBGRF_SetPacketParams( &SubgRf.PacketParams ); + SUBGRF_SendPayload( buffer, outsize, 0 ); + } + else + { + MW_LOG( TS_ON, VLEVEL_M, "RadioSend Oversize\r\n" ); + return RADIO_STATUS_ERROR; + } + } + else + { + SubgRf.PacketParams.Params.Gfsk.PayloadLength = size; + SUBGRF_SetPacketParams( &SubgRf.PacketParams ); + SUBGRF_SendPayload( buffer, size, 0 ); + } + break; + } + case MODEM_BPSK: + { + SubgRf.PacketParams.PacketType = PACKET_TYPE_BPSK; + SubgRf.PacketParams.Params.Bpsk.PayloadLength = size; + SUBGRF_SetPacketParams( &SubgRf.PacketParams ); + SUBGRF_SendPayload( buffer, size, 0 ); + break; + } +#if (RADIO_SIGFOX_ENABLE == 1) + case MODEM_SIGFOX_TX: + { + /* from bpsk to dbpsk */ + /* first 1 bit duplicated */ + /* RadioBuffer is 1 bytes more */ + payload_integration( RadioBuffer, buffer, size ); + + SubgRf.PacketParams.PacketType = PACKET_TYPE_BPSK; + SubgRf.PacketParams.Params.Bpsk.PayloadLength = size + 1; + SUBGRF_SetPacketParams( &SubgRf.PacketParams ); + + RadioWrite( SUBGHZ_RAM_RAMPUPL, 0 ); // clean start-up LSB + RadioWrite( SUBGHZ_RAM_RAMPUPH, 0 ); // clean start-up MSB + if( SubgRf.ModulationParams.Params.Bpsk.BitRate == 100 ) + { + RadioWrite( SUBGHZ_RAM_RAMPDNL, 0x70 ); // clean end of frame LSB + RadioWrite( SUBGHZ_RAM_RAMPDNH, 0x1D ); // clean end of frame MSB + } + else // 600 bps + { + RadioWrite( SUBGHZ_RAM_RAMPDNL, 0xE1 ); // clean end of frame LSB + RadioWrite( SUBGHZ_RAM_RAMPDNH, 0x04 ); // clean end of frame MSB + } + + uint16_t bitNum = ( size * 8 ) + 2; + RadioWrite( SUBGHZ_RAM_FRAMELIMH, ( bitNum >> 8 ) & 0x00FF ); // limit frame + RadioWrite( SUBGHZ_RAM_FRAMELIML, bitNum & 0x00FF ); // limit frame + SUBGRF_SendPayload( RadioBuffer, size + 1, 0xFFFFFF ); + break; + } +#endif /*RADIO_SIGFOX_ENABLE == 1*/ + default: + break; + } + + TimerSetValue( &TxTimeoutTimer, SubgRf.TxTimeout ); + TimerStart( &TxTimeoutTimer ); + } + + return RADIO_STATUS_OK; +} + +static void RadioSleep( void ) +{ + SleepParams_t params = { 0 }; + + params.Fields.WarmStart = 1; + SUBGRF_SetSleep( params ); + + RADIO_DELAY_MS( 2 ); +} + +static void RadioStandby( void ) +{ + SUBGRF_SetStandby( STDBY_RC ); +} + +static void RadioRx( uint32_t timeout ) +{ +#if( RADIO_LR_FHSS_IS_ON == 1 ) + if( SubgRf.lr_fhss.is_lr_fhss_on == true ) + { + //return LORAMAC_RADIO_STATUS_ERROR; + } +#endif /* RADIO_LR_FHSS_IS_ON == 1 */ + if( 1UL == RFW_Is_Init( ) ) + { + RFW_ReceiveInit( ); + } + else + { + SUBGRF_SetDioIrqParams( IRQ_RX_DONE | IRQ_RX_TX_TIMEOUT | IRQ_CRC_ERROR | IRQ_HEADER_ERROR | IRQ_RX_DBG, + IRQ_RX_DONE | IRQ_RX_TX_TIMEOUT | IRQ_CRC_ERROR | IRQ_HEADER_ERROR | IRQ_RX_DBG, + IRQ_RADIO_NONE, + IRQ_RADIO_NONE ); + } + + if( timeout != 0 ) + { + TimerSetValue( &RxTimeoutTimer, timeout ); + TimerStart( &RxTimeoutTimer ); + } + /* switch off RxDcPreambleDetect See STM32WL Errata: RadioSetRxDutyCycle*/ + SubgRf.RxDcPreambleDetectTimeout = 0; + /* Set DBG pin */ + DBG_GPIO_RADIO_RX( SET ); + /* RF switch configuration */ + SUBGRF_SetSwitch( SubgRf.AntSwitchPaSelect, RFSWITCH_RX ); + + if( SubgRf.RxContinuous == true ) + { + SUBGRF_SetRx( 0xFFFFFF ); // Rx Continuous + } + else + { + SUBGRF_SetRx( SubgRf.RxTimeout << 6 ); + } +} + +static void RadioRxBoosted( uint32_t timeout ) +{ +#if( RADIO_LR_FHSS_IS_ON == 1 ) + if( SubgRf.lr_fhss.is_lr_fhss_on == true ) + { + //return LORAMAC_RADIO_STATUS_ERROR; + } +#endif /* RADIO_LR_FHSS_IS_ON == 1 */ + if( 1UL == RFW_Is_Init() ) + { + RFW_ReceiveInit(); + } + else + { + SUBGRF_SetDioIrqParams( IRQ_RX_DONE | IRQ_RX_TX_TIMEOUT | IRQ_CRC_ERROR | IRQ_HEADER_ERROR | IRQ_RX_DBG, + IRQ_RX_DONE | IRQ_RX_TX_TIMEOUT | IRQ_CRC_ERROR | IRQ_HEADER_ERROR | IRQ_RX_DBG, + IRQ_RADIO_NONE, + IRQ_RADIO_NONE ); + } + if( timeout != 0 ) + { + TimerSetValue( &RxTimeoutTimer, timeout ); + TimerStart( &RxTimeoutTimer ); + } + /* switch off RxDcPreambleDetect See STM32WL Errata: RadioSetRxDutyCycle*/ + SubgRf.RxDcPreambleDetectTimeout = 0; + /* Set DBG pin */ + DBG_GPIO_RADIO_RX( SET ); + /* RF switch configuration */ + SUBGRF_SetSwitch( SubgRf.AntSwitchPaSelect, RFSWITCH_RX ); + + if( SubgRf.RxContinuous == true ) + { + SUBGRF_SetRxBoosted( 0xFFFFFF ); // Rx Continuous + } + else + { + SUBGRF_SetRxBoosted( SubgRf.RxTimeout << 6 ); + } +} + +static void RadioSetRxDutyCycle( uint32_t rxTime, uint32_t sleepTime ) +{ + /*See STM32WL Errata: RadioSetRxDutyCycle*/ + SubgRf.RxDcPreambleDetectTimeout = 2 * rxTime + sleepTime; + /*Enable also the IRQ_PREAMBLE_DETECTED*/ + SUBGRF_SetDioIrqParams( IRQ_RADIO_ALL, IRQ_RADIO_ALL, IRQ_RADIO_NONE, IRQ_RADIO_NONE ); + /* RF switch configuration */ + SUBGRF_SetSwitch( SubgRf.AntSwitchPaSelect, RFSWITCH_RX ); + /* Start Rx DutyCycle*/ + SUBGRF_SetRxDutyCycle( rxTime, sleepTime ); +} + +static void RadioStartCad( void ) +{ + /* RF switch configuration */ + SUBGRF_SetSwitch( SubgRf.AntSwitchPaSelect, RFSWITCH_RX ); + + SUBGRF_SetDioIrqParams( IRQ_CAD_CLEAR | IRQ_CAD_DETECTED, + IRQ_CAD_CLEAR | IRQ_CAD_DETECTED, + IRQ_RADIO_NONE, + IRQ_RADIO_NONE ); + SUBGRF_SetCad( ); +} + +static void RadioSetTxContinuousWave( uint32_t freq, int8_t power, uint16_t time ) +{ +#if( RADIO_LR_FHSS_IS_ON == 1 ) + if( SubgRf.lr_fhss.is_lr_fhss_on == true ) + { + //return LORAMAC_RADIO_STATUS_ERROR; + } +#endif /* RADIO_LR_FHSS_IS_ON == 1 */ + uint32_t timeout = ( uint32_t )time * 1000; + uint8_t antswitchpow; + + SUBGRF_SetRfFrequency( freq ); + + antswitchpow = SUBGRF_SetRfTxPower( power ); + + /* WORKAROUND - Trimming the output voltage power_ldo to 3.3V */ + SUBGRF_WriteRegister(REG_DRV_CTRL, 0x7 << 1); + + /* Set RF switch */ + SUBGRF_SetSwitch( antswitchpow, RFSWITCH_TX ); + + SUBGRF_SetTxContinuousWave( ); + + TimerSetValue( &TxTimeoutTimer, timeout ); + TimerStart( &TxTimeoutTimer ); +} + +static int16_t RadioRssi( RadioModems_t modem ) +{ + return SUBGRF_GetRssiInst( ); +} + +static void RadioWrite( uint16_t addr, uint8_t data ) +{ + SUBGRF_WriteRegister( addr, data ); +} + +static uint8_t RadioRead( uint16_t addr ) +{ + return SUBGRF_ReadRegister( addr ); +} + +static void RadioWriteRegisters( uint16_t addr, uint8_t *buffer, uint8_t size ) +{ + SUBGRF_WriteRegisters( addr, buffer, size ); +} + +static void RadioReadRegisters( uint16_t addr, uint8_t *buffer, uint8_t size ) +{ + SUBGRF_ReadRegisters( addr, buffer, size ); +} + +static void RadioSetMaxPayloadLength( RadioModems_t modem, uint8_t max ) +{ + if( modem == MODEM_LORA ) + { + SubgRf.PacketParams.Params.LoRa.PayloadLength = MaxPayloadLength = max; + SUBGRF_SetPacketParams( &SubgRf.PacketParams ); + } + else + { + if( SubgRf.PacketParams.Params.Gfsk.HeaderType == RADIO_PACKET_VARIABLE_LENGTH ) + { + SubgRf.PacketParams.Params.Gfsk.PayloadLength = MaxPayloadLength = max; + SUBGRF_SetPacketParams( &SubgRf.PacketParams ); + } + } +} + +static void RadioSetPublicNetwork( bool enable ) +{ + SubgRf.PublicNetwork.Current = SubgRf.PublicNetwork.Previous = enable; + + RadioSetModem( MODEM_LORA ); + if( enable == true ) + { + // Change LoRa modem SyncWord + SUBGRF_WriteRegister( REG_LR_SYNCWORD, ( LORA_MAC_PUBLIC_SYNCWORD >> 8 ) & 0xFF ); + SUBGRF_WriteRegister( REG_LR_SYNCWORD + 1, LORA_MAC_PUBLIC_SYNCWORD & 0xFF ); + } + else + { + // Change LoRa modem SyncWord + SUBGRF_WriteRegister( REG_LR_SYNCWORD, ( LORA_MAC_PRIVATE_SYNCWORD >> 8 ) & 0xFF ); + SUBGRF_WriteRegister( REG_LR_SYNCWORD + 1, LORA_MAC_PRIVATE_SYNCWORD & 0xFF ); + } +} + +static uint32_t RadioGetWakeupTime( void ) +{ + return SUBGRF_GetRadioWakeUpTime() + RADIO_WAKEUP_TIME; +} + +static void RadioOnTxTimeoutIrq( void *context ) +{ + RADIO_TX_TIMEOUT_PROCESS(); +} + +static void RadioOnRxTimeoutIrq( void *context ) +{ + RADIO_RX_TIMEOUT_PROCESS(); +} + +static void RadioOnTxTimeoutProcess( void ) +{ + DBG_GPIO_RADIO_TX( RST ); + + if( ( RadioEvents != NULL ) && ( RadioEvents->TxTimeout != NULL ) ) + { + RadioEvents->TxTimeout( ); + } +} + +static void RadioOnRxTimeoutProcess( void ) +{ + DBG_GPIO_RADIO_RX( RST ); + + if( ( RadioEvents != NULL ) && ( RadioEvents->RxTimeout != NULL ) ) + { + RadioEvents->RxTimeout( ); + } +} + +static void RadioOnDioIrq( RadioIrqMasks_t radioIrq ) +{ + SubgRf.RadioIrq = radioIrq; + + RADIO_IRQ_PROCESS(); +} + +static void RadioIrqProcess( void ) +{ + uint8_t size = 0; + int32_t cfo = 0; + + switch( SubgRf.RadioIrq ) + { + case IRQ_TX_DONE: + DBG_GPIO_RADIO_TX( RST ); + + TimerStop( &TxTimeoutTimer ); +#if( RADIO_LR_FHSS_IS_ON == 1 ) + if( SubgRf.lr_fhss.is_lr_fhss_on == true ) + { + wl_lr_fhss_handle_tx_done( &SubgRf.lr_fhss.lr_fhss_params, + &SubgRf.lr_fhss.lr_fhss_state ); + } +#endif /* RADIO_LR_FHSS_IS_ON == 1 */ + //!< Update operating mode state to a value lower than \ref MODE_STDBY_XOSC + SUBGRF_SetStandby( STDBY_RC ); + + if( RFW_Is_LongPacketModeEnabled() == 1 ) + { + RFW_DeInit_TxLongPacket( ); + } + + if( ( RadioEvents != NULL ) && ( RadioEvents->TxDone != NULL ) ) + { + RadioEvents->TxDone( ); + } + break; + + case IRQ_RX_DONE: + DBG_GPIO_RADIO_RX( RST ); + + TimerStop( &RxTimeoutTimer ); + if( SubgRf.RxContinuous == false ) + { + //!< Update operating mode state to a value lower than \ref MODE_STDBY_XOSC + SUBGRF_SetStandby( STDBY_RC ); + + /* WORKAROUND - Implicit Header Mode Timeout Behavior, see STM32WL Erratasheet */ + SUBGRF_WriteRegister( SUBGHZ_RTCCTLR, 0x00 ); + SUBGRF_WriteRegister( SUBGHZ_EVENTMASKR, SUBGRF_ReadRegister( SUBGHZ_EVENTMASKR ) | ( 1 << 1 ) ); + /* WORKAROUND END */ + } + SUBGRF_GetPayload( RadioBuffer, &size, 255 ); + SUBGRF_GetPacketStatus( &( SubgRf.PacketStatus ) ); + if( ( RadioEvents != NULL ) && ( RadioEvents->RxDone != NULL ) ) + { + switch( SubgRf.PacketStatus.packetType ) + { + case PACKET_TYPE_LORA: + RadioEvents->RxDone( RadioBuffer, size, SubgRf.PacketStatus.Params.LoRa.RssiPkt, + SubgRf.PacketStatus.Params.LoRa.SnrPkt ); + break; + default: + SUBGRF_GetCFO( SubgRf.ModulationParams.Params.Gfsk.BitRate, &cfo ); + RadioEvents->RxDone( RadioBuffer, size, SubgRf.PacketStatus.Params.Gfsk.RssiAvg, ( int8_t ) DIVR( cfo, 1000 ) ); + break; + } + } + break; + + case IRQ_CAD_CLEAR: + //!< Update operating mode state to a value lower than \ref MODE_STDBY_XOSC + SUBGRF_SetStandby( STDBY_RC ); + if( ( RadioEvents != NULL ) && ( RadioEvents->CadDone != NULL ) ) + { + RadioEvents->CadDone( false ); + } + break; + case IRQ_CAD_DETECTED: + //!< Update operating mode state to a value lower than \ref MODE_STDBY_XOSC + SUBGRF_SetStandby( STDBY_RC ); + if( ( RadioEvents != NULL ) && ( RadioEvents->CadDone != NULL ) ) + { + RadioEvents->CadDone( true ); + } + break; + + case IRQ_RX_TX_TIMEOUT: + MW_LOG( TS_ON, VLEVEL_M, "IRQ_RX_TX_TIMEOUT\r\n" ); + if( SUBGRF_GetOperatingMode( ) == MODE_TX ) + { + DBG_GPIO_RADIO_TX( RST ); + + TimerStop( &TxTimeoutTimer ); + //!< Update operating mode state to a value lower than \ref MODE_STDBY_XOSC + SUBGRF_SetStandby( STDBY_RC ); + if( ( RadioEvents != NULL ) && ( RadioEvents->TxTimeout != NULL ) ) + { + RadioEvents->TxTimeout( ); + } + } + else if( SUBGRF_GetOperatingMode( ) == MODE_RX ) + { + DBG_GPIO_RADIO_RX( RST ); + + TimerStop( &RxTimeoutTimer ); + //!< Update operating mode state to a value lower than \ref MODE_STDBY_XOSC + SUBGRF_SetStandby( STDBY_RC ); + if( ( RadioEvents != NULL ) && ( RadioEvents->RxTimeout != NULL ) ) + { + RadioEvents->RxTimeout( ); + } + } + break; + case IRQ_PREAMBLE_DETECTED: + MW_LOG( TS_ON, VLEVEL_M, "PRE OK\r\n" ); + /*See STM32WL Errata: RadioSetRxDutyCycle*/ + if( SubgRf.RxDcPreambleDetectTimeout != 0 ) + { + /* Update Radio RTC period */ + Radio.Write( SUBGHZ_RTCPRDR2, ( SubgRf.RxDcPreambleDetectTimeout >> 16 ) & 0xFF ); /*Update Radio RTC Period MSB*/ + Radio.Write( SUBGHZ_RTCPRDR1, ( SubgRf.RxDcPreambleDetectTimeout >> 8 ) & 0xFF ); /*Update Radio RTC Period MidByte*/ + Radio.Write( SUBGHZ_RTCPRDR0, ( SubgRf.RxDcPreambleDetectTimeout ) & 0xFF ); /*Update Radio RTC Period lsb*/ + Radio.Write( SUBGHZ_RTCCTLR, Radio.Read( SUBGHZ_RTCCTLR ) | 0x1 ); /*restart Radio RTC*/ + SubgRf.RxDcPreambleDetectTimeout = 0; + /*Clear IRQ_PREAMBLE_DETECTED mask*/ + SUBGRF_SetDioIrqParams( IRQ_RX_DONE | IRQ_RX_TX_TIMEOUT | IRQ_CRC_ERROR | IRQ_HEADER_ERROR | IRQ_RX_DBG, + IRQ_RX_DONE | IRQ_RX_TX_TIMEOUT | IRQ_CRC_ERROR | IRQ_HEADER_ERROR | IRQ_RX_DBG, + IRQ_RADIO_NONE, + IRQ_RADIO_NONE ); + + } + break; + + case IRQ_SYNCWORD_VALID: + MW_LOG( TS_ON, VLEVEL_M, "SYNC OK\r\n" ); + if( 1UL == RFW_Is_Init( ) ) + { + RFW_ReceivePayload( ); + } + break; + + case IRQ_HEADER_VALID: + MW_LOG( TS_ON, VLEVEL_M, "HDR OK\r\n" ); + break; + + case IRQ_HEADER_ERROR: + TimerStop( &RxTimeoutTimer ); + if( SubgRf.RxContinuous == false ) + { + //!< Update operating mode state to a value lower than \ref MODE_STDBY_XOSC + SUBGRF_SetStandby( STDBY_RC ); + } + if( ( RadioEvents != NULL ) && ( RadioEvents->RxTimeout != NULL ) ) + { + RadioEvents->RxTimeout( ); + MW_LOG( TS_ON, VLEVEL_M, "HDR KO\r\n" ); + } + break; + + case IRQ_CRC_ERROR: + MW_LOG( TS_ON, VLEVEL_M, "IRQ_CRC_ERROR\r\n" ); + + if( SubgRf.RxContinuous == false ) + { + //!< Update operating mode state to a value lower than \ref MODE_STDBY_XOSC + SUBGRF_SetStandby( STDBY_RC ); + } + if( ( RadioEvents != NULL ) && ( RadioEvents->RxError ) ) + { + RadioEvents->RxError( ); + } + break; +#if( RADIO_LR_FHSS_IS_ON == 1 ) + case IRQ_LR_FHSS_HOP: + { + ( void ) wl_lr_fhss_handle_hop( &SubgRf.lr_fhss.lr_fhss_params, &SubgRf.lr_fhss.lr_fhss_state ); + MW_LOG( TS_ON, VLEVEL_M, "HOP\r\n" ); + break; + } +#endif /* RADIO_LR_FHSS_IS_ON == 1 */ + default: + break; + } +} + +static void RadioTxPrbs( void ) +{ + SUBGRF_SetSwitch( SubgRf.AntSwitchPaSelect, RFSWITCH_TX ); + Radio.Write( SUBGHZ_GPKTCTL1AR, 0x2d ); // sel mode prbs9 instead of preamble + SUBGRF_SetTxInfinitePreamble( ); + SUBGRF_SetTx( 0x0fffff ); +} + +static void RadioTxCw( int8_t power ) +{ + uint8_t paselect = SUBGRF_SetRfTxPower( power ); + /* WORKAROUND - Trimming the output voltage power_ldo to 3.3V */ + SUBGRF_WriteRegister(REG_DRV_CTRL, 0x7 << 1); + SUBGRF_SetSwitch( paselect, RFSWITCH_TX ); + SUBGRF_SetTxContinuousWave( ); +} + +#if (RADIO_SIGFOX_ENABLE == 1) +static void payload_integration( uint8_t *outBuffer, uint8_t *inBuffer, uint8_t size ) +{ + uint8_t prevInt = 0; + uint8_t currBit; + uint8_t index_bit; + uint8_t index_byte; + uint8_t index_bit_out; + uint8_t index_byte_out; + int32_t i = 0; + + for( i = 0; i < size; i++ ) + { + /* reverse all inputs */ + inBuffer[i] = ~inBuffer[i]; + /* init outBuffer */ + outBuffer[i] = 0; + } + + for( i = 0; i < ( size * 8 ); i++ ) + { + /* index to take bit in inBuffer */ + index_bit = 7 - ( i % 8 ); + index_byte = i / 8; + /* index to place bit in outBuffer is shifted 1 bit right */ + index_bit_out = 7 - ( ( i + 1 ) % 8 ); + index_byte_out = ( i + 1 ) / 8; + /* extract current bit from input */ + currBit = ( inBuffer[index_byte] >> index_bit ) & 0x01; + /* integration */ + prevInt ^= currBit; + /* write result integration in output */ + outBuffer[index_byte_out] |= ( prevInt << index_bit_out ); + } + + outBuffer[size] = ( prevInt << 7 ) | ( prevInt << 6 ) | ( ( ( !prevInt ) & 0x01 ) << 5 ) ; +} +#endif /*RADIO_SIGFOX_ENABLE == 1*/ + +static int32_t RadioSetRxGenericConfig( GenericModems_t modem, RxConfigGeneric_t *config, uint32_t rxContinuous, + uint32_t symbTimeout ) +{ +#if (RADIO_GENERIC_CONFIG_ENABLE == 1) + int32_t status = 0; + uint8_t syncword[8] = {0}; + uint8_t MaxPayloadLength; + + RFW_DeInit( ); /* switch Off FwPacketDecoding by default */ + + if( rxContinuous != 0 ) + { + symbTimeout = 0; + } + SubgRf.RxContinuous = ( rxContinuous == 0 ) ? false : true; + + switch( modem ) + { + case GENERIC_FSK: + if( ( config->fsk.BitRate == 0 ) || ( config->fsk.PreambleLen == 0 ) ) + { + return -1; + } + if( config->fsk.SyncWordLength > 8 ) + { + return -1; + } + else + { + RADIO_MEMCPY8( syncword, config->fsk.SyncWord, config->fsk.SyncWordLength ); + } + + SUBGRF_SetStopRxTimerOnPreambleDetect( ( config->fsk.StopTimerOnPreambleDetect == 0 ) ? false : true ); + + SubgRf.ModulationParams.PacketType = PACKET_TYPE_GFSK; + SubgRf.ModulationParams.Params.Gfsk.BitRate = config->fsk.BitRate; + SubgRf.ModulationParams.Params.Gfsk.ModulationShaping = ( RadioModShapings_t ) config->fsk.ModulationShaping; + SubgRf.ModulationParams.Params.Gfsk.Bandwidth = SUBGRF_GetFskBandwidthRegValue( config->fsk.Bandwidth ); + + SubgRf.PacketParams.PacketType = PACKET_TYPE_GFSK; + SubgRf.PacketParams.Params.Gfsk.PreambleLength = ( config->fsk.PreambleLen ) << 3 ; // convert byte into bit + SubgRf.PacketParams.Params.Gfsk.PreambleMinDetect = ( RadioPreambleDetection_t ) config->fsk.PreambleMinDetect; + SubgRf.PacketParams.Params.Gfsk.SyncWordLength = ( config->fsk.SyncWordLength ) << 3; // convert byte into bit + SubgRf.PacketParams.Params.Gfsk.AddrComp = ( RadioAddressComp_t ) config->fsk.AddrComp; + + if( config->fsk.LengthMode == RADIO_FSK_PACKET_FIXED_LENGTH ) + { + SubgRf.PacketParams.Params.Gfsk.PayloadLength = config->fsk.MaxPayloadLength; + } + else if( config->fsk.LengthMode == RADIO_FSK_PACKET_2BYTES_LENGTH ) + { + /* Set max in the radio, in long packet mode will be tuned based dynamically on received chunk */ + SubgRf.PacketParams.Params.Gfsk.PayloadLength = 0xFF; + } + else + { + /* Set max in the radio */ + SubgRf.PacketParams.Params.Gfsk.PayloadLength = 0xFF; + } + + if( ( config->fsk.Whitening == RADIO_FSK_DC_IBM_WHITENING ) + || ( config->fsk.LengthMode == RADIO_FSK_PACKET_2BYTES_LENGTH ) ) + { + /* Supports only RADIO_FSK_CRC_2_BYTES_IBM or RADIO_FSK_CRC_2_BYTES_CCIT*/ + if( ( config->fsk.CrcLength != RADIO_FSK_CRC_2_BYTES_IBM ) && ( config->fsk.CrcLength != RADIO_FSK_CRC_2_BYTES_CCIT ) + && ( config->fsk.CrcLength != RADIO_FSK_CRC_OFF ) ) + { + return -1; + } + ConfigGeneric_t ConfigGeneric; + ConfigGeneric.rtx = CONFIG_RX; + ConfigGeneric.RxConfig = config; + if( 0UL != RFW_Init( &ConfigGeneric, RadioEvents, &RxTimeoutTimer ) ) + { + return -1; + } + /* Whitening off, will be processed by FW, switch off built-in radio whitening*/ + SubgRf.PacketParams.Params.Gfsk.DcFree = ( RadioDcFree_t ) RADIO_FSK_DC_FREE_OFF; + /* Crc off, Crc processed by FW, switch off built-in radio Crc*/ + SubgRf.PacketParams.Params.Gfsk.CrcLength = ( RadioCrcTypes_t ) RADIO_CRC_OFF; + /* Length contained in Tx, but will be processed by FW after de-whitening*/ + SubgRf.PacketParams.Params.Gfsk.HeaderType = ( RadioPacketLengthModes_t ) RADIO_PACKET_FIXED_LENGTH; + } + else + { + SubgRf.PacketParams.Params.Gfsk.CrcLength = ( RadioCrcTypes_t ) config->fsk.CrcLength; + SubgRf.PacketParams.Params.Gfsk.DcFree = ( RadioDcFree_t ) config->fsk.Whitening; + SubgRf.PacketParams.Params.Gfsk.HeaderType = ( RadioPacketLengthModes_t ) config->fsk.LengthMode; + } + + RadioStandby( ); + RadioSetModem( MODEM_FSK ); + SUBGRF_SetModulationParams( &SubgRf.ModulationParams ); + SUBGRF_SetPacketParams( &SubgRf.PacketParams ); + SUBGRF_SetSyncWord( syncword ); + SUBGRF_SetWhiteningSeed( config->fsk.whiteSeed ); + SUBGRF_SetCrcPolynomial( config->fsk.CrcPolynomial ); + /* timeout unused when SubgRf.RxContinuous */ + SubgRf.RxTimeout = ( uint32_t )( ( symbTimeout * 1000 * 8 ) / config->fsk.BitRate ); + break; + case GENERIC_LORA: + if( config->lora.PreambleLen == 0 ) + { + return -1; + } + + if( config->lora.LengthMode == RADIO_LORA_PACKET_FIXED_LENGTH ) + { + MaxPayloadLength = config->lora.MaxPayloadLength; + } + else + { + MaxPayloadLength = 0xFF; + } + SUBGRF_SetStopRxTimerOnPreambleDetect( ( config->lora.StopTimerOnPreambleDetect == 0 ) ? false : true ); + SUBGRF_SetLoRaSymbNumTimeout( symbTimeout ); + + SubgRf.ModulationParams.PacketType = PACKET_TYPE_LORA; + SubgRf.ModulationParams.Params.LoRa.SpreadingFactor = ( RadioLoRaSpreadingFactors_t ) config->lora.SpreadingFactor; + SubgRf.ModulationParams.Params.LoRa.Bandwidth = ( RadioLoRaBandwidths_t ) config->lora.Bandwidth; + SubgRf.ModulationParams.Params.LoRa.CodingRate = ( RadioLoRaCodingRates_t ) config->lora.Coderate; + switch( config->lora.LowDatarateOptimize ) + { + case RADIO_LORA_LOWDR_OPT_OFF: + SubgRf.ModulationParams.Params.LoRa.LowDatarateOptimize = 0; + break; + case RADIO_LORA_LOWDR_OPT_ON: + SubgRf.ModulationParams.Params.LoRa.LowDatarateOptimize = 1; + break; + case RADIO_LORA_LOWDR_OPT_AUTO: + if( ( config->lora.SpreadingFactor == RADIO_LORA_SF11 ) || ( config->lora.SpreadingFactor == RADIO_LORA_SF12 ) ) + { + SubgRf.ModulationParams.Params.LoRa.LowDatarateOptimize = 1; + } + else + { + SubgRf.ModulationParams.Params.LoRa.LowDatarateOptimize = 0; + } + break; + default: + break; + } + + SubgRf.PacketParams.PacketType = PACKET_TYPE_LORA; + SubgRf.PacketParams.Params.LoRa.PreambleLength = config->lora.PreambleLen; + SubgRf.PacketParams.Params.LoRa.HeaderType = ( RadioLoRaPacketLengthsMode_t ) config->lora.LengthMode; + SubgRf.PacketParams.Params.LoRa.PayloadLength = MaxPayloadLength; + SubgRf.PacketParams.Params.LoRa.CrcMode = ( RadioLoRaCrcModes_t ) config->lora.CrcMode; + SubgRf.PacketParams.Params.LoRa.InvertIQ = ( RadioLoRaIQModes_t ) config->lora.IqInverted; + + RadioStandby( ); + RadioSetModem( MODEM_LORA ); + SUBGRF_SetModulationParams( &SubgRf.ModulationParams ); + SUBGRF_SetPacketParams( &SubgRf.PacketParams ); + + /* WORKAROUND - Optimizing the Inverted IQ Operation, see STM32WL Erratasheet */ + if( SubgRf.PacketParams.Params.LoRa.InvertIQ == LORA_IQ_INVERTED ) + { + SUBGRF_WriteRegister( SUBGHZ_LIQPOLR, SUBGRF_ReadRegister( SUBGHZ_LIQPOLR ) & ~( 1 << 2 ) ); + } + else + { + SUBGRF_WriteRegister( SUBGHZ_LIQPOLR, SUBGRF_ReadRegister( SUBGHZ_LIQPOLR ) | ( 1 << 2 ) ); + } + /* WORKAROUND END */ + + // Timeout Max, Timeout handled directly in SetRx function + SubgRf.RxTimeout = 0xFFFF; + break; + default: + break; + } + return status; +#else /* RADIO_GENERIC_CONFIG_ENABLE == 1*/ + return -1; +#endif /* RADIO_GENERIC_CONFIG_ENABLE == 0*/ +} + +static int32_t RadioSetTxGenericConfig( GenericModems_t modem, TxConfigGeneric_t *config, int8_t power, + uint32_t timeout ) +{ +#if( RADIO_LR_FHSS_IS_ON == 1 ) + /*disable LrFhss*/ + SubgRf.lr_fhss.is_lr_fhss_on = false; +#endif /* RADIO_LR_FHSS_IS_ON == 1 */ +#if (RADIO_GENERIC_CONFIG_ENABLE == 1) + uint8_t syncword[8] = {0}; + RadioModems_t radio_modem; + RFW_DeInit( ); /* switch Off FwPacketDecoding by default */ + switch( modem ) + { + case GENERIC_MSK: + if( config->msk.SyncWordLength > 8 ) + { + return -1; + } + else + { + RADIO_MEMCPY8( syncword, config->msk.SyncWord, config->msk.SyncWordLength ); + } + if( ( config->msk.BitRate == 0 ) ) + { + return -1; + } + else if( config->msk.BitRate <= 10000 ) + { + /*max msk modulator datarate is 10kbps*/ + radio_modem = MODEM_MSK; + SubgRf.PacketParams.PacketType = PACKET_TYPE_GMSK; + SubgRf.ModulationParams.PacketType = PACKET_TYPE_GMSK; + SubgRf.ModulationParams.Params.Gfsk.BitRate = config->msk.BitRate; + SubgRf.ModulationParams.Params.Gfsk.ModulationShaping = ( RadioModShapings_t ) config->msk.ModulationShaping; + } + else + { + radio_modem = MODEM_FSK; + SubgRf.PacketParams.PacketType = PACKET_TYPE_GFSK; + SubgRf.ModulationParams.PacketType = PACKET_TYPE_GFSK; + SubgRf.ModulationParams.Params.Gfsk.BitRate = config->msk.BitRate; + SubgRf.ModulationParams.Params.Gfsk.ModulationShaping = ( RadioModShapings_t ) config->msk.ModulationShaping; + /*do msk with gfsk modulator*/ + SubgRf.ModulationParams.Params.Gfsk.Fdev = config->msk.BitRate / 4; + } + + SubgRf.PacketParams.Params.Gfsk.PreambleLength = ( config->msk.PreambleLen ) << 3; // convert byte into bit + SubgRf.PacketParams.Params.Gfsk.PreambleMinDetect = RADIO_PREAMBLE_DETECTOR_08_BITS; // don't care in tx + SubgRf.PacketParams.Params.Gfsk.SyncWordLength = ( config->msk.SyncWordLength ) << 3; // convert byte into bit + SubgRf.PacketParams.Params.Gfsk.AddrComp = RADIO_ADDRESSCOMP_FILT_OFF; // don't care in tx + + if( ( config->msk.Whitening == RADIO_FSK_DC_IBM_WHITENING ) + || ( config->msk.HeaderType == RADIO_FSK_PACKET_2BYTES_LENGTH ) ) + { + /* Supports only RADIO_FSK_CRC_2_BYTES_IBM or RADIO_FSK_CRC_2_BYTES_CCIT */ + if( ( config->msk.CrcLength != RADIO_FSK_CRC_2_BYTES_IBM ) && ( config->msk.CrcLength != RADIO_FSK_CRC_2_BYTES_CCIT ) + && ( config->msk.CrcLength != RADIO_FSK_CRC_OFF ) ) + { + return -1; + } + ConfigGeneric_t ConfigGeneric; + /*msk and fsk are union, no need for copy as fsk/msk struct are on same address*/ + ConfigGeneric.TxConfig = config; + ConfigGeneric.rtx = CONFIG_TX; + if( 0UL != RFW_Init( &ConfigGeneric, RadioEvents, &TxTimeoutTimer ) ) + { + return -1; + } + /* whitening off, will be processed by FW, switch off built-in radio whitening */ + SubgRf.PacketParams.Params.Gfsk.DcFree = ( RadioDcFree_t ) RADIO_FSK_DC_FREE_OFF; + /* Crc processed by FW, switch off built-in radio Crc */ + SubgRf.PacketParams.Params.Gfsk.CrcLength = ( RadioCrcTypes_t ) RADIO_CRC_OFF; + /* length contained in Tx, but will be processed by FW after de-whitening */ + SubgRf.PacketParams.Params.Gfsk.HeaderType = ( RadioPacketLengthModes_t ) RADIO_PACKET_FIXED_LENGTH; + } + else + { + SubgRf.PacketParams.Params.Gfsk.CrcLength = ( RadioCrcTypes_t ) config->msk.CrcLength; + SubgRf.PacketParams.Params.Gfsk.DcFree = ( RadioDcFree_t ) config->msk.Whitening; + SubgRf.PacketParams.Params.Gfsk.HeaderType = ( RadioPacketLengthModes_t ) config->msk.HeaderType; + } + + RadioStandby( ); + RadioSetModem( radio_modem ); + + SUBGRF_SetModulationParams( &SubgRf.ModulationParams ); + SUBGRF_SetPacketParams( &SubgRf.PacketParams ); + SUBGRF_SetSyncWord( syncword ); + SUBGRF_SetWhiteningSeed( config->msk.whiteSeed ); + SUBGRF_SetCrcPolynomial( config->msk.CrcPolynomial ); + break; + case GENERIC_FSK: + if( config->fsk.BitRate == 0 ) + { + return -1; + } + if( config->fsk.SyncWordLength > 8 ) + { + return -1; + } + else + { + RADIO_MEMCPY8( syncword, config->fsk.SyncWord, config->fsk.SyncWordLength ); + } + SubgRf.ModulationParams.PacketType = PACKET_TYPE_GFSK; + SubgRf.ModulationParams.Params.Gfsk.BitRate = config->fsk.BitRate; + SubgRf.ModulationParams.Params.Gfsk.ModulationShaping = ( RadioModShapings_t ) config->fsk.ModulationShaping; + SubgRf.ModulationParams.Params.Gfsk.Fdev = config->fsk.FrequencyDeviation; + + SubgRf.PacketParams.PacketType = PACKET_TYPE_GFSK; + SubgRf.PacketParams.Params.Gfsk.PreambleLength = ( config->fsk.PreambleLen ) << 3; // convert byte into bit + SubgRf.PacketParams.Params.Gfsk.PreambleMinDetect = RADIO_PREAMBLE_DETECTOR_08_BITS; // don't care in tx + SubgRf.PacketParams.Params.Gfsk.SyncWordLength = ( config->fsk.SyncWordLength ) << 3; // convert byte into bit + SubgRf.PacketParams.Params.Gfsk.AddrComp = RADIO_ADDRESSCOMP_FILT_OFF; // don't care in tx + + if( ( config->fsk.Whitening == RADIO_FSK_DC_IBM_WHITENING ) + || ( config->fsk.HeaderType == RADIO_FSK_PACKET_2BYTES_LENGTH ) ) + { + /* Supports only RADIO_FSK_CRC_2_BYTES_IBM or RADIO_FSK_CRC_2_BYTES_CCIT */ + if( ( config->fsk.CrcLength != RADIO_FSK_CRC_2_BYTES_IBM ) && ( config->fsk.CrcLength != RADIO_FSK_CRC_2_BYTES_CCIT ) + && ( config->fsk.CrcLength != RADIO_FSK_CRC_OFF ) ) + { + return -1; + } + ConfigGeneric_t ConfigGeneric; + ConfigGeneric.rtx = CONFIG_TX; + ConfigGeneric.TxConfig = config; + if( 0UL != RFW_Init( &ConfigGeneric, RadioEvents, &TxTimeoutTimer ) ) + { + return -1; + } + /* whitening off, will be processed by FW, switch off built-in radio whitening */ + SubgRf.PacketParams.Params.Gfsk.DcFree = ( RadioDcFree_t ) RADIO_FSK_DC_FREE_OFF; + /* Crc processed by FW, switch off built-in radio Crc */ + SubgRf.PacketParams.Params.Gfsk.CrcLength = ( RadioCrcTypes_t ) RADIO_CRC_OFF; + /* length contained in Tx, but will be processed by FW after de-whitening */ + SubgRf.PacketParams.Params.Gfsk.HeaderType = ( RadioPacketLengthModes_t ) RADIO_PACKET_FIXED_LENGTH; + } + else + { + SubgRf.PacketParams.Params.Gfsk.CrcLength = ( RadioCrcTypes_t ) config->fsk.CrcLength; + SubgRf.PacketParams.Params.Gfsk.DcFree = ( RadioDcFree_t ) config->fsk.Whitening; + SubgRf.PacketParams.Params.Gfsk.HeaderType = ( RadioPacketLengthModes_t ) config->fsk.HeaderType; + } + + RadioStandby( ); + RadioSetModem( MODEM_FSK ); + SUBGRF_SetModulationParams( &SubgRf.ModulationParams ); + SUBGRF_SetPacketParams( &SubgRf.PacketParams ); + SUBGRF_SetSyncWord( syncword ); + SUBGRF_SetWhiteningSeed( config->fsk.whiteSeed ); + SUBGRF_SetCrcPolynomial( config->fsk.CrcPolynomial ); + break; + case GENERIC_LORA: + SubgRf.ModulationParams.PacketType = PACKET_TYPE_LORA; + SubgRf.ModulationParams.Params.LoRa.SpreadingFactor = ( RadioLoRaSpreadingFactors_t ) config->lora.SpreadingFactor; + SubgRf.ModulationParams.Params.LoRa.Bandwidth = ( RadioLoRaBandwidths_t ) config->lora.Bandwidth; + SubgRf.ModulationParams.Params.LoRa.CodingRate = ( RadioLoRaCodingRates_t ) config->lora.Coderate; + switch( config->lora.LowDatarateOptimize ) + { + case RADIO_LORA_LOWDR_OPT_OFF: + SubgRf.ModulationParams.Params.LoRa.LowDatarateOptimize = 0; + break; + case RADIO_LORA_LOWDR_OPT_ON: + SubgRf.ModulationParams.Params.LoRa.LowDatarateOptimize = 1; + break; + case RADIO_LORA_LOWDR_OPT_AUTO: + if( ( config->lora.SpreadingFactor == RADIO_LORA_SF11 ) || ( config->lora.SpreadingFactor == RADIO_LORA_SF12 ) ) + { + SubgRf.ModulationParams.Params.LoRa.LowDatarateOptimize = 1; + } + else + { + SubgRf.ModulationParams.Params.LoRa.LowDatarateOptimize = 0; + } + break; + default: + break; + } + + SubgRf.PacketParams.PacketType = PACKET_TYPE_LORA; + SubgRf.PacketParams.Params.LoRa.PreambleLength = config->lora.PreambleLen; + SubgRf.PacketParams.Params.LoRa.HeaderType = ( RadioLoRaPacketLengthsMode_t ) config->lora.LengthMode; + SubgRf.PacketParams.Params.LoRa.CrcMode = ( RadioLoRaCrcModes_t ) config->lora.CrcMode; + SubgRf.PacketParams.Params.LoRa.InvertIQ = ( RadioLoRaIQModes_t ) config->lora.IqInverted; + + RadioStandby( ); + RadioSetModem( MODEM_LORA ); + SUBGRF_SetModulationParams( &SubgRf.ModulationParams ); + SUBGRF_SetPacketParams( &SubgRf.PacketParams ); + + /* WORKAROUND - Modulation Quality with 500 kHz LoRa Bandwidth, see STM32WL Erratasheet */ + if( SubgRf.ModulationParams.Params.LoRa.Bandwidth == LORA_BW_500 ) + { + // RegTxModulation = @address 0x0889 + SUBGRF_WriteRegister( SUBGHZ_SDCFG0R, SUBGRF_ReadRegister( SUBGHZ_SDCFG0R ) & ~( 1 << 2 ) ); + } + else + { + // RegTxModulation = @address 0x0889 + SUBGRF_WriteRegister( SUBGHZ_SDCFG0R, SUBGRF_ReadRegister( SUBGHZ_SDCFG0R ) | ( 1 << 2 ) ); + } + /* WORKAROUND END */ + break; + case GENERIC_BPSK: + if( ( config->bpsk.BitRate == 0 ) || ( config->bpsk.BitRate > 1000 ) ) + { + return -1; + } + RadioSetModem( MODEM_BPSK ); + SubgRf.ModulationParams.PacketType = PACKET_TYPE_BPSK; + SubgRf.ModulationParams.Params.Bpsk.BitRate = config->bpsk.BitRate; + SubgRf.ModulationParams.Params.Bpsk.ModulationShaping = MOD_SHAPING_DBPSK; + SUBGRF_SetModulationParams( &SubgRf.ModulationParams ); + break; + default: + break; + } + + SubgRf.AntSwitchPaSelect = SUBGRF_SetRfTxPower( power ); + RFW_SetAntSwitch( SubgRf.AntSwitchPaSelect ); + SubgRf.TxTimeout = timeout; + return 0; +#else /* RADIO_GENERIC_CONFIG_ENABLE == 1*/ + return -1; +#endif /* RADIO_GENERIC_CONFIG_ENABLE == 0*/ +} + +/* Lora Fhss Radio interface definitions*/ +#if( RADIO_LR_FHSS_IS_ON == 1 ) +static uint32_t GetNextFreqIdx( uint32_t max ) +{ + int32_t newbit = ( ( ( prbs31_val >> 30 ) ^ ( prbs31_val >> 27 ) ) & 1 ); + prbs31_val = ( ( prbs31_val << 1 ) | newbit ); + return ( prbs31_val - 1 ) % ( max ); +} +#endif /* RADIO_LR_FHSS_IS_ON == 1 */ + +static radio_status_t RadioLrFhssSetCfg( const radio_lr_fhss_cfg_params_t *cfg_params ) +{ + radio_status_t status = RADIO_STATUS_UNSUPPORTED_FEATURE; + +#if( RADIO_LR_FHSS_IS_ON == 1 ) + /* record config parameters in Subg structure*/ + SubgRf.lr_fhss.lr_fhss_params.lr_fhss_params = cfg_params->radio_lr_fhss_params.lr_fhss_params; + /* record tx timeout*/ + SubgRf.lr_fhss.tx_rf_pwr_in_dbm = cfg_params->tx_rf_pwr_in_dbm; + /* Convert Hz to pll steps*/ + SX_FREQ_TO_CHANNEL( SubgRf.lr_fhss.lr_fhss_params.center_freq_in_pll_steps, + cfg_params->radio_lr_fhss_params.center_frequency_in_hz ); + /**/ + SubgRf.lr_fhss.lr_fhss_params.device_offset = cfg_params->radio_lr_fhss_params.device_offset; + + SubgRf.TxTimeout = cfg_params->tx_timeout_in_ms; + /* set power and record RF switch config*/ + SubgRf.AntSwitchPaSelect = SUBGRF_SetRfTxPower( SubgRf.lr_fhss.tx_rf_pwr_in_dbm ); + + RadioStandby(); + + status = ( radio_status_t ) wl_lr_fhss_init( &SubgRf.lr_fhss.lr_fhss_params ); + if( status != RADIO_STATUS_OK ) + { + return status; + } + SubgRf.lr_fhss.is_lr_fhss_on = true; +#endif /* RADIO_LR_FHSS_IS_ON == 1 */ + return status; +} + +static radio_status_t RadioLrFhssGetTimeOnAirInMs( const radio_lr_fhss_time_on_air_params_t *params, + uint32_t *time_on_air_in_ms ) +{ +#if( RADIO_LR_FHSS_IS_ON == 1 ) + *time_on_air_in_ms = lr_fhss_get_time_on_air_in_ms( ¶ms->radio_lr_fhss_params.lr_fhss_params, + params->pld_len_in_bytes ); + + return RADIO_STATUS_OK; +#else + return RADIO_STATUS_UNSUPPORTED_FEATURE; +#endif /* RADIO_LR_FHSS_IS_ON */ +} \ No newline at end of file diff --git a/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c b/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c new file mode 100644 index 0000000..74cd43e --- /dev/null +++ b/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c @@ -0,0 +1,1205 @@ +/*! + * \file radio_driver.c + * + * \brief radio driver implementation + * + * \copyright Revised BSD License, see section \ref LICENSE. + * + * \code + * ______ _ + * / _____) _ | | + * ( (____ _____ ____ _| |_ _____ ____| |__ + * \____ \| ___ | (_ _) ___ |/ ___) _ \ + * _____) ) ____| | | || |_| ____( (___| | | | + * (______/|_____)_|_|_| \__)_____)\____)_| |_| + * (C)2013-2017 Semtech + * + * \endcode + * + * \author Miguel Luis ( Semtech ) + * + * \author Gregory Cristian ( Semtech ) + */ +/** + ****************************************************************************** + * + * Portions COPYRIGHT 2020 STMicroelectronics + * + * @file radio_driver.c + * @author MCD Application Team + * @brief radio driver implementation + ****************************************************************************** + */ +/* Includes ------------------------------------------------------------------*/ +#include "radio_driver.h" +#include "mw_log_conf.h" + +/* External variables ---------------------------------------------------------*/ +/*! + * \brief Sughz handler + */ +extern SUBGHZ_HandleTypeDef hsubghz; + +/* Private typedef -----------------------------------------------------------*/ +/*! + * FSK bandwidth definition + */ +typedef struct FskBandwidth_s +{ + uint32_t bandwidth; + uint8_t RegValue; +} FskBandwidth_t; +/* Private define ------------------------------------------------------------*/ +/** + * @brief drive value used anytime radio is NOT in TX low power mode + * @note SMPS_DRIVE_SETTING_DEFAULT can be redefined in radio_conf.h + */ +#ifndef SMPS_DRIVE_SETTING_DEFAULT +#define SMPS_DRIVE_SETTING_DEFAULT SMPS_DRV_40 +#endif /* SMPS_DRIVE_SETTING_DEFAULT */ + +/** + * @brief drive value used anytime radio is in TX low power mode + * TX low power mode is the worst case because the PA sinks from SMPS + * while in high power mode, current is sunk directly from the battery + * @note SMPS_DRIVE_SETTING_MAX can be redefined in radio_conf.h + */ +#ifndef SMPS_DRIVE_SETTING_MAX +#define SMPS_DRIVE_SETTING_MAX SMPS_DRV_60 +#endif /* SMPS_DRIVE_SETTING_MAX */ + +/** + * @brief Provides the frequency of the chip running on the radio and the frequency step + * @remark These defines are used for computing the frequency divider to set the RF frequency + * @note XTAL_FREQ can be redefined in radio_conf.h + */ +#ifndef XTAL_FREQ +#define XTAL_FREQ ( 32000000UL ) +#endif /* XTAL_FREQ */ + +/** + * @brief in XO mode, set internal capacitor (from 0x00 to 0x2F starting 11.2pF with 0.47pF steps) + * @note XTAL_DEFAULT_CAP_VALUE can be redefined in radio_conf.h + */ +#ifndef XTAL_DEFAULT_CAP_VALUE +#define XTAL_DEFAULT_CAP_VALUE ( 0x20UL ) +#endif /* XTAL_DEFAULT_CAP_VALUE */ + +/** + * @brief voltage of vdd tcxo. + * @note TCXO_CTRL_VOLTAGE can be redefined in radio_conf.h + */ +#ifndef TCXO_CTRL_VOLTAGE +#define TCXO_CTRL_VOLTAGE TCXO_CTRL_1_7V +#endif /* TCXO_CTRL_VOLTAGE */ + +/** + * @brief Radio maximum wakeup time (in ms) + * @note RF_WAKEUP_TIME can be redefined in radio_conf.h + */ +#ifndef RF_WAKEUP_TIME +#define RF_WAKEUP_TIME ( 10UL ) +#endif /* RF_WAKEUP_TIME */ + +/** + * @brief DCDC is present and enabled + * @remark this define is only used if the DCDC is present on the board + * @note DCDC_ENABLE can be redefined in radio_conf.h + */ +#ifndef DCDC_ENABLE +#define DCDC_ENABLE ( 1UL ) +#endif /* DCDC_ENABLE */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/*! + * \brief Holds the internal operating mode of the radio + */ +static RadioOperatingModes_t OperatingMode; + +/*! + * \brief Stores the current packet type set in the radio + */ +static RadioPacketTypes_t PacketType; + +/*! + * \brief Stores the current packet header type set in the radio + */ +static volatile RadioLoRaPacketLengthsMode_t LoRaHeaderType; + +/*! + * \brief Stores the last frequency error measured on LoRa received packet + */ +volatile uint32_t FrequencyError = 0; + +/*! + * \brief Hold the status of the Image calibration + */ +static bool ImageCalibrated = false; + +/*! + * Precomputed FSK bandwidth registers values + */ +static const FskBandwidth_t FskBandwidths[] = +{ + { 4800 , 0x1F }, + { 5800 , 0x17 }, + { 7300 , 0x0F }, + { 9700 , 0x1E }, + { 11700 , 0x16 }, + { 14600 , 0x0E }, + { 19500 , 0x1D }, + { 23400 , 0x15 }, + { 29300 , 0x0D }, + { 39000 , 0x1C }, + { 46900 , 0x14 }, + { 58600 , 0x0C }, + { 78200 , 0x1B }, + { 93800 , 0x13 }, + { 117300, 0x0B }, + { 156200, 0x1A }, + { 187200, 0x12 }, + { 234300, 0x0A }, + { 312000, 0x19 }, + { 373600, 0x11 }, + { 467000, 0x09 }, + { 500000, 0x00 }, // Invalid Bandwidth +}; + +/* Private function prototypes -----------------------------------------------*/ + +/*! + * \brief This set SMPS drive capability wrt. RF mode + * + * \param [in] level SMPS maximum drive capability level + */ +static void Radio_SMPS_Set( uint8_t level ); + +/*! + * \brief IRQ Callback radio function + */ +static DioIrqHandler RadioOnDioIrqCb; + +/* Exported functions ---------------------------------------------------------*/ +void SUBGRF_Init( DioIrqHandler dioIrq ) +{ + if ( dioIrq != NULL) + { + RadioOnDioIrqCb = dioIrq; + } + + RADIO_INIT(); + + /* set default SMPS current drive to default*/ + Radio_SMPS_Set(SMPS_DRIVE_SETTING_DEFAULT); + + ImageCalibrated = false; + + SUBGRF_SetStandby( STDBY_RC ); + + // Initialize TCXO control + if (1U == RBI_IsTCXO() ) + { + SUBGRF_SetTcxoMode( TCXO_CTRL_VOLTAGE, RF_WAKEUP_TIME << 6 );// 100 ms + SUBGRF_WriteRegister( REG_XTA_TRIM, 0x00 ); + + /*enable calibration for cut1.1 and later*/ + CalibrationParams_t calibParam; + calibParam.Value = 0x7F; + SUBGRF_Calibrate( calibParam ); + } + else + { + SUBGRF_WriteRegister( REG_XTA_TRIM, XTAL_DEFAULT_CAP_VALUE ); + SUBGRF_WriteRegister( REG_XTB_TRIM, XTAL_DEFAULT_CAP_VALUE ); + } + + /* WORKAROUND - Trimming the output voltage power_ldo to 3.3V */ + SUBGRF_WriteRegister(REG_DRV_CTRL, 0x7 << 1); + + /* Init RF Switch */ + RBI_Init(); + + OperatingMode = MODE_STDBY_RC; +} + +RadioOperatingModes_t SUBGRF_GetOperatingMode( void ) +{ + return OperatingMode; +} + +void SUBGRF_SetPayload( uint8_t *payload, uint8_t size ) +{ + SUBGRF_WriteBuffer( 0x00, payload, size ); +} + +uint8_t SUBGRF_GetPayload( uint8_t *buffer, uint8_t *size, uint8_t maxSize ) +{ + uint8_t offset = 0; + + SUBGRF_GetRxBufferStatus( size, &offset ); + if( *size > maxSize ) + { + return 1; + } + SUBGRF_ReadBuffer( offset, buffer, *size ); + + return 0; +} + +void SUBGRF_SendPayload( uint8_t *payload, uint8_t size, uint32_t timeout) +{ + SUBGRF_SetPayload( payload, size ); + SUBGRF_SetTx( timeout ); +} + +uint8_t SUBGRF_SetSyncWord( uint8_t *syncWord ) +{ + SUBGRF_WriteRegisters( REG_LR_SYNCWORDBASEADDRESS, syncWord, 8 ); + return 0; +} + +void SUBGRF_SetCrcSeed( uint16_t seed ) +{ + uint8_t buf[2]; + + buf[0] = ( uint8_t )( ( seed >> 8 ) & 0xFF ); + buf[1] = ( uint8_t )( seed & 0xFF ); + + switch( SUBGRF_GetPacketType( ) ) + { + case PACKET_TYPE_GFSK: + SUBGRF_WriteRegisters( REG_LR_CRCSEEDBASEADDR, buf, 2 ); + break; + + default: + break; + } +} + +void SUBGRF_SetCrcPolynomial( uint16_t polynomial ) +{ + uint8_t buf[2]; + + buf[0] = ( uint8_t )( ( polynomial >> 8 ) & 0xFF ); + buf[1] = ( uint8_t )( polynomial & 0xFF ); + + switch( SUBGRF_GetPacketType( ) ) + { + case PACKET_TYPE_GFSK: + SUBGRF_WriteRegisters( REG_LR_CRCPOLYBASEADDR, buf, 2 ); + break; + + default: + break; + } +} + +void SUBGRF_SetWhiteningSeed( uint16_t seed ) +{ + uint8_t regValue = 0; + + switch( SUBGRF_GetPacketType( ) ) + { + case PACKET_TYPE_GFSK: + regValue = SUBGRF_ReadRegister( REG_LR_WHITSEEDBASEADDR_MSB ) & 0xFE; + regValue = ( ( seed >> 8 ) & 0x01 ) | regValue; + SUBGRF_WriteRegister( REG_LR_WHITSEEDBASEADDR_MSB, regValue ); // only 1 bit. + SUBGRF_WriteRegister( REG_LR_WHITSEEDBASEADDR_LSB, (uint8_t)seed ); + break; + + default: + break; + } +} + +uint32_t SUBGRF_GetRandom( void ) +{ + uint32_t number = 0; + uint8_t regAnaLna = 0; + uint8_t regAnaMixer = 0; + + regAnaLna = SUBGRF_ReadRegister( REG_ANA_LNA ); + SUBGRF_WriteRegister( REG_ANA_LNA, regAnaLna & ~( 1 << 0 ) ); + + regAnaMixer = SUBGRF_ReadRegister( REG_ANA_MIXER ); + SUBGRF_WriteRegister( REG_ANA_MIXER, regAnaMixer & ~( 1 << 7 ) ); + + // Set radio in continuous reception + SUBGRF_SetRx( 0xFFFFFF ); // Rx Continuous + + SUBGRF_ReadRegisters( RANDOM_NUMBER_GENERATORBASEADDR, ( uint8_t* )&number, 4 ); + + SUBGRF_SetStandby( STDBY_RC ); + + SUBGRF_WriteRegister( REG_ANA_LNA, regAnaLna ); + SUBGRF_WriteRegister( REG_ANA_MIXER, regAnaMixer ); + + return number; +} + +void SUBGRF_SetSleep( SleepParams_t sleepConfig ) +{ + /* switch the antenna OFF by SW */ + RBI_ConfigRFSwitch(RBI_SWITCH_OFF); + + Radio_SMPS_Set(SMPS_DRIVE_SETTING_DEFAULT); + + uint8_t value = ( ( ( uint8_t )sleepConfig.Fields.WarmStart << 2 ) | + ( ( uint8_t )sleepConfig.Fields.Reset << 1 ) | + ( ( uint8_t )sleepConfig.Fields.WakeUpRTC ) ); + SUBGRF_WriteCommand( RADIO_SET_SLEEP, &value, 1 ); + OperatingMode = MODE_SLEEP; +} + +void SUBGRF_SetStandby( RadioStandbyModes_t standbyConfig ) +{ + SUBGRF_WriteCommand( RADIO_SET_STANDBY, ( uint8_t* )&standbyConfig, 1 ); + if( standbyConfig == STDBY_RC ) + { + OperatingMode = MODE_STDBY_RC; + } + else + { + OperatingMode = MODE_STDBY_XOSC; + } +} + +void SUBGRF_SetFs( void ) +{ + SUBGRF_WriteCommand( RADIO_SET_FS, 0, 0 ); + OperatingMode = MODE_FS; +} + +void SUBGRF_SetTx( uint32_t timeout ) +{ + uint8_t buf[3]; + + OperatingMode = MODE_TX; + + buf[0] = ( uint8_t )( ( timeout >> 16 ) & 0xFF ); + buf[1] = ( uint8_t )( ( timeout >> 8 ) & 0xFF ); + buf[2] = ( uint8_t )( timeout & 0xFF ); + SUBGRF_WriteCommand( RADIO_SET_TX, buf, 3 ); +} + +void SUBGRF_SetRx( uint32_t timeout ) +{ + uint8_t buf[3]; + + OperatingMode = MODE_RX; + + buf[0] = ( uint8_t )( ( timeout >> 16 ) & 0xFF ); + buf[1] = ( uint8_t )( ( timeout >> 8 ) & 0xFF ); + buf[2] = ( uint8_t )( timeout & 0xFF ); + SUBGRF_WriteCommand( RADIO_SET_RX, buf, 3 ); +} + +void SUBGRF_SetRxBoosted( uint32_t timeout ) +{ + uint8_t buf[3]; + + OperatingMode = MODE_RX; + + SUBGRF_WriteRegister( REG_RX_GAIN, 0x97 ); // max LNA gain, increase current by ~2mA for around ~3dB in sensitivity + + buf[0] = ( uint8_t )( ( timeout >> 16 ) & 0xFF ); + buf[1] = ( uint8_t )( ( timeout >> 8 ) & 0xFF ); + buf[2] = ( uint8_t )( timeout & 0xFF ); + SUBGRF_WriteCommand( RADIO_SET_RX, buf, 3 ); +} + +void SUBGRF_SetRxDutyCycle( uint32_t rxTime, uint32_t sleepTime ) +{ + uint8_t buf[6]; + + buf[0] = ( uint8_t )( ( rxTime >> 16 ) & 0xFF ); + buf[1] = ( uint8_t )( ( rxTime >> 8 ) & 0xFF ); + buf[2] = ( uint8_t )( rxTime & 0xFF ); + buf[3] = ( uint8_t )( ( sleepTime >> 16 ) & 0xFF ); + buf[4] = ( uint8_t )( ( sleepTime >> 8 ) & 0xFF ); + buf[5] = ( uint8_t )( sleepTime & 0xFF ); + SUBGRF_WriteCommand( RADIO_SET_RXDUTYCYCLE, buf, 6 ); + OperatingMode = MODE_RX_DC; +} + +void SUBGRF_SetCad( void ) +{ + SUBGRF_WriteCommand( RADIO_SET_CAD, 0, 0 ); + OperatingMode = MODE_CAD; +} + +void SUBGRF_SetTxContinuousWave( void ) +{ + SUBGRF_WriteCommand( RADIO_SET_TXCONTINUOUSWAVE, 0, 0 ); +} + +void SUBGRF_SetTxInfinitePreamble( void ) +{ + SUBGRF_WriteCommand( RADIO_SET_TXCONTINUOUSPREAMBLE, 0, 0 ); +} + +void SUBGRF_SetStopRxTimerOnPreambleDetect( bool enable ) +{ + SUBGRF_WriteCommand( RADIO_SET_STOPRXTIMERONPREAMBLE, ( uint8_t* )&enable, 1 ); +} + +void SUBGRF_SetLoRaSymbNumTimeout( uint8_t symbNum ) +{ + SUBGRF_WriteCommand( RADIO_SET_LORASYMBTIMEOUT, &symbNum, 1 ); + + if( symbNum >= 64 ) + { + uint8_t mant = symbNum >> 1; + uint8_t exp = 0; + uint8_t reg = 0; + + while( mant > 31 ) + { + mant >>= 2; + exp++; + } + + reg = exp + ( mant << 3 ); + SUBGRF_WriteRegister( REG_LR_SYNCH_TIMEOUT, reg ); + } +} + +void SUBGRF_SetRegulatorMode( void ) +{ + RadioRegulatorMode_t mode; + + if ( ( 1UL == RBI_IsDCDC() ) && ( 1UL == DCDC_ENABLE ) ) + { + mode = USE_DCDC ; + } + else + { + mode = USE_LDO ; + } + SUBGRF_WriteCommand( RADIO_SET_REGULATORMODE, ( uint8_t* )&mode, 1 ); +} + +void SUBGRF_Calibrate( CalibrationParams_t calibParam ) +{ + uint8_t value = ( ( ( uint8_t )calibParam.Fields.ImgEnable << 6 ) | + ( ( uint8_t )calibParam.Fields.ADCBulkPEnable << 5 ) | + ( ( uint8_t )calibParam.Fields.ADCBulkNEnable << 4 ) | + ( ( uint8_t )calibParam.Fields.ADCPulseEnable << 3 ) | + ( ( uint8_t )calibParam.Fields.PLLEnable << 2 ) | + ( ( uint8_t )calibParam.Fields.RC13MEnable << 1 ) | + ( ( uint8_t )calibParam.Fields.RC64KEnable ) ); + + SUBGRF_WriteCommand( RADIO_CALIBRATE, &value, 1 ); +} + +void SUBGRF_CalibrateImage( uint32_t freq ) +{ + uint8_t calFreq[2]; + + if( freq > 900000000 ) + { + calFreq[0] = 0xE1; + calFreq[1] = 0xE9; + } + else if( freq > 850000000 ) + { + calFreq[0] = 0xD7; + calFreq[1] = 0xDB; + } + else if( freq > 770000000 ) + { + calFreq[0] = 0xC1; + calFreq[1] = 0xC5; + } + else if( freq > 460000000 ) + { + calFreq[0] = 0x75; + calFreq[1] = 0x81; + } + else if( freq > 425000000 ) + { + calFreq[0] = 0x6B; + calFreq[1] = 0x6F; + } + else /* freq <= 425000000*/ + { + /* [ 156MHz - 171MHz ] */ + calFreq[0] = 0x29; + calFreq[1] = 0x2B ; + } + SUBGRF_WriteCommand( RADIO_CALIBRATEIMAGE, calFreq, 2 ); +} + +void SUBGRF_SetPaConfig( uint8_t paDutyCycle, uint8_t hpMax, uint8_t deviceSel, uint8_t paLut ) +{ + uint8_t buf[4]; + + buf[0] = paDutyCycle; + buf[1] = hpMax; + buf[2] = deviceSel; + buf[3] = paLut; + SUBGRF_WriteCommand( RADIO_SET_PACONFIG, buf, 4 ); +} + +void SUBGRF_SetRxTxFallbackMode( uint8_t fallbackMode ) +{ + SUBGRF_WriteCommand( RADIO_SET_TXFALLBACKMODE, &fallbackMode, 1 ); +} + +void SUBGRF_SetDioIrqParams( uint16_t irqMask, uint16_t dio1Mask, uint16_t dio2Mask, uint16_t dio3Mask ) +{ + uint8_t buf[8]; + + buf[0] = ( uint8_t )( ( irqMask >> 8 ) & 0x00FF ); + buf[1] = ( uint8_t )( irqMask & 0x00FF ); + buf[2] = ( uint8_t )( ( dio1Mask >> 8 ) & 0x00FF ); + buf[3] = ( uint8_t )( dio1Mask & 0x00FF ); + buf[4] = ( uint8_t )( ( dio2Mask >> 8 ) & 0x00FF ); + buf[5] = ( uint8_t )( dio2Mask & 0x00FF ); + buf[6] = ( uint8_t )( ( dio3Mask >> 8 ) & 0x00FF ); + buf[7] = ( uint8_t )( dio3Mask & 0x00FF ); + SUBGRF_WriteCommand( RADIO_CFG_DIOIRQ, buf, 8 ); +} + +uint16_t SUBGRF_GetIrqStatus( void ) +{ + uint8_t irqStatus[2]; + + SUBGRF_ReadCommand( RADIO_GET_IRQSTATUS, irqStatus, 2 ); + return ( irqStatus[0] << 8 ) | irqStatus[1]; +} + +void SUBGRF_SetTcxoMode (RadioTcxoCtrlVoltage_t tcxoVoltage, uint32_t timeout ) +{ + uint8_t buf[4]; + + buf[0] = tcxoVoltage & 0x07; + buf[1] = ( uint8_t )( ( timeout >> 16 ) & 0xFF ); + buf[2] = ( uint8_t )( ( timeout >> 8 ) & 0xFF ); + buf[3] = ( uint8_t )( timeout & 0xFF ); + + SUBGRF_WriteCommand( RADIO_SET_TCXOMODE, buf, 4 ); +} + +void SUBGRF_SetRfFrequency( uint32_t frequency ) +{ + uint8_t buf[4]; + uint32_t chan = 0; + + if( ImageCalibrated == false ) + { + SUBGRF_CalibrateImage( frequency ); + ImageCalibrated = true; + } + SX_FREQ_TO_CHANNEL(chan, frequency); + buf[0] = ( uint8_t )( ( chan >> 24 ) & 0xFF ); + buf[1] = ( uint8_t )( ( chan >> 16 ) & 0xFF ); + buf[2] = ( uint8_t )( ( chan >> 8 ) & 0xFF ); + buf[3] = ( uint8_t )( chan & 0xFF ); + SUBGRF_WriteCommand( RADIO_SET_RFFREQUENCY, buf, 4 ); +} + +void SUBGRF_SetPacketType( RadioPacketTypes_t packetType ) +{ + // Save packet type internally to avoid questioning the radio + PacketType = packetType; + + if( packetType == PACKET_TYPE_GFSK ) + { + SUBGRF_WriteRegister( REG_BIT_SYNC, 0x00 ); + } + SUBGRF_WriteCommand( RADIO_SET_PACKETTYPE, ( uint8_t* )&packetType, 1 ); +} + +RadioPacketTypes_t SUBGRF_GetPacketType( void ) +{ + return PacketType; +} + +void SUBGRF_SetTxParams( uint8_t paSelect, int8_t power, RadioRampTimes_t rampTime ) +{ + uint8_t buf[2]; + int32_t max_power; + + if (paSelect == RFO_LP) + { + max_power = RBI_GetRFOMaxPowerConfig(RBI_RFO_LP_MAXPOWER); + if (power > max_power) + { + power = max_power; + } + if (max_power == 14) + { + SUBGRF_SetPaConfig(0x04, 0x00, 0x01, 0x01); + power = 0x0E - (max_power - power); + } + else if (max_power == 10) + { + SUBGRF_SetPaConfig(0x01, 0x00, 0x01, 0x01); + power = 0x0D - (max_power - power); + } + else /*default 15dBm*/ + { + SUBGRF_SetPaConfig(0x07, 0x00, 0x01, 0x01); + power = 0x0E - (max_power - power); + } + if (power < -17) + { + power = -17; + } + SUBGRF_WriteRegister(REG_OCP, 0x18); /* current max is 80 mA for the whole device*/ + } + else /* rfo_hp*/ + { + /* WORKAROUND - Better Resistance of the RFO High Power Tx to Antenna Mismatch, see STM32WL Erratasheet*/ + SUBGRF_WriteRegister(REG_TX_CLAMP, SUBGRF_ReadRegister(REG_TX_CLAMP) | (0x0F << 1)); + /* WORKAROUND END*/ + max_power = RBI_GetRFOMaxPowerConfig(RBI_RFO_HP_MAXPOWER); + if (power > max_power) + { + power = max_power; + } + if (max_power == 20) + { + SUBGRF_SetPaConfig(0x03, 0x05, 0x00, 0x01); + power = 0x16 - (max_power - power); + } + else if (max_power == 17) + { + SUBGRF_SetPaConfig(0x02, 0x03, 0x00, 0x01); + power = 0x16 - (max_power - power); + } + else if (max_power == 14) + { + SUBGRF_SetPaConfig(0x02, 0x02, 0x00, 0x01); + power = 0x0E - (max_power - power); + } + else /*22dBm*/ + { + SUBGRF_SetPaConfig(0x04, 0x07, 0x00, 0x01); + power = 0x16 - (max_power - power); + } + if (power < -9) + { + power = -9; + } + SUBGRF_WriteRegister(REG_OCP, 0x38); /*current max 160mA for the whole device*/ + } + buf[0] = power; + buf[1] = (uint8_t)rampTime; + SUBGRF_WriteCommand(RADIO_SET_TXPARAMS, buf, 2); +} + +void SUBGRF_SetModulationParams( ModulationParams_t *modulationParams ) +{ + uint8_t n; + uint32_t tempVal = 0; + uint8_t buf[8] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; + + // Check if required configuration corresponds to the stored packet type + // If not, silently update radio packet type + if( PacketType != modulationParams->PacketType ) + { + SUBGRF_SetPacketType( modulationParams->PacketType ); + } + + switch( modulationParams->PacketType ) + { + case PACKET_TYPE_GFSK: + n = 8; + tempVal = ( uint32_t )(( 32 * XTAL_FREQ ) / modulationParams->Params.Gfsk.BitRate ); + buf[0] = ( tempVal >> 16 ) & 0xFF; + buf[1] = ( tempVal >> 8 ) & 0xFF; + buf[2] = tempVal & 0xFF; + buf[3] = modulationParams->Params.Gfsk.ModulationShaping; + buf[4] = modulationParams->Params.Gfsk.Bandwidth; + SX_FREQ_TO_CHANNEL(tempVal, modulationParams->Params.Gfsk.Fdev); + buf[5] = ( tempVal >> 16 ) & 0xFF; + buf[6] = ( tempVal >> 8 ) & 0xFF; + buf[7] = ( tempVal& 0xFF ); + SUBGRF_WriteCommand( RADIO_SET_MODULATIONPARAMS, buf, n ); + break; + case PACKET_TYPE_BPSK: + n = 4; + tempVal = ( uint32_t ) (( 32 * XTAL_FREQ) / modulationParams->Params.Bpsk.BitRate ); + buf[0] = ( tempVal >> 16 ) & 0xFF; + buf[1] = ( tempVal >> 8 ) & 0xFF; + buf[2] = tempVal & 0xFF; + buf[3] = modulationParams->Params.Bpsk.ModulationShaping; + SUBGRF_WriteCommand( RADIO_SET_MODULATIONPARAMS, buf, n ); + break; + case PACKET_TYPE_LORA: + n = 4; + buf[0] = modulationParams->Params.LoRa.SpreadingFactor; + buf[1] = modulationParams->Params.LoRa.Bandwidth; + buf[2] = modulationParams->Params.LoRa.CodingRate; + buf[3] = modulationParams->Params.LoRa.LowDatarateOptimize; + + SUBGRF_WriteCommand( RADIO_SET_MODULATIONPARAMS, buf, n ); + + break; + case PACKET_TYPE_GMSK: + n = 5; + tempVal = ( uint32_t )(( 32 *XTAL_FREQ) / modulationParams->Params.Gfsk.BitRate ); + buf[0] = ( tempVal >> 16 ) & 0xFF; + buf[1] = ( tempVal >> 8 ) & 0xFF; + buf[2] = tempVal & 0xFF; + buf[3] = modulationParams->Params.Gfsk.ModulationShaping; + buf[4] = modulationParams->Params.Gfsk.Bandwidth; + SUBGRF_WriteCommand( RADIO_SET_MODULATIONPARAMS, buf, n ); + break; + default: + case PACKET_TYPE_NONE: + break; + } +} + +void SUBGRF_SetPacketParams( PacketParams_t *packetParams ) +{ + uint8_t n; + uint8_t crcVal = 0; + uint8_t buf[9] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; + + // Check if required configuration corresponds to the stored packet type + // If not, silently update radio packet type + if( PacketType != packetParams->PacketType ) + { + SUBGRF_SetPacketType( packetParams->PacketType ); + } + + switch( packetParams->PacketType ) + { + case PACKET_TYPE_GMSK: + case PACKET_TYPE_GFSK: + if( packetParams->Params.Gfsk.CrcLength == RADIO_CRC_2_BYTES_IBM ) + { + SUBGRF_SetCrcSeed( CRC_IBM_SEED ); + SUBGRF_SetCrcPolynomial( CRC_POLYNOMIAL_IBM ); + crcVal = RADIO_CRC_2_BYTES; + } + else if( packetParams->Params.Gfsk.CrcLength == RADIO_CRC_2_BYTES_CCIT ) + { + SUBGRF_SetCrcSeed( CRC_CCITT_SEED ); + SUBGRF_SetCrcPolynomial( CRC_POLYNOMIAL_CCITT ); + crcVal = RADIO_CRC_2_BYTES_INV; + } + else + { + crcVal = packetParams->Params.Gfsk.CrcLength; + } + n = 9; + buf[0] = ( packetParams->Params.Gfsk.PreambleLength >> 8 ) & 0xFF; + buf[1] = packetParams->Params.Gfsk.PreambleLength; + buf[2] = packetParams->Params.Gfsk.PreambleMinDetect; + buf[3] = ( packetParams->Params.Gfsk.SyncWordLength /*<< 3*/ ); // convert from byte to bit + buf[4] = packetParams->Params.Gfsk.AddrComp; + buf[5] = packetParams->Params.Gfsk.HeaderType; + buf[6] = packetParams->Params.Gfsk.PayloadLength; + buf[7] = crcVal; + buf[8] = packetParams->Params.Gfsk.DcFree; + break; + case PACKET_TYPE_BPSK: + n = 1; + buf[0] = packetParams->Params.Bpsk.PayloadLength; + break; + case PACKET_TYPE_LORA: + n = 6; + buf[0] = ( packetParams->Params.LoRa.PreambleLength >> 8 ) & 0xFF; + buf[1] = packetParams->Params.LoRa.PreambleLength; + buf[2] = LoRaHeaderType = packetParams->Params.LoRa.HeaderType; + buf[3] = packetParams->Params.LoRa.PayloadLength; + buf[4] = packetParams->Params.LoRa.CrcMode; + buf[5] = packetParams->Params.LoRa.InvertIQ; + break; + default: + case PACKET_TYPE_NONE: + return; + } + SUBGRF_WriteCommand( RADIO_SET_PACKETPARAMS, buf, n ); +} + +void SUBGRF_SetCadParams( RadioLoRaCadSymbols_t cadSymbolNum, uint8_t cadDetPeak, uint8_t cadDetMin, RadioCadExitModes_t cadExitMode, uint32_t cadTimeout ) +{ + uint8_t buf[7]; + + buf[0] = ( uint8_t )cadSymbolNum; + buf[1] = cadDetPeak; + buf[2] = cadDetMin; + buf[3] = ( uint8_t )cadExitMode; + buf[4] = ( uint8_t )( ( cadTimeout >> 16 ) & 0xFF ); + buf[5] = ( uint8_t )( ( cadTimeout >> 8 ) & 0xFF ); + buf[6] = ( uint8_t )( cadTimeout & 0xFF ); + SUBGRF_WriteCommand( RADIO_SET_CADPARAMS, buf, 7 ); + OperatingMode = MODE_CAD; +} + +void SUBGRF_SetBufferBaseAddress( uint8_t txBaseAddress, uint8_t rxBaseAddress ) +{ + uint8_t buf[2]; + + buf[0] = txBaseAddress; + buf[1] = rxBaseAddress; + SUBGRF_WriteCommand( RADIO_SET_BUFFERBASEADDRESS, buf, 2 ); +} + +RadioPhyStatus_t SUBGRF_GetStatus( void ) +{ + uint8_t stat = 0; + RadioPhyStatus_t status = { .Value = 0 }; + + SUBGRF_ReadCommand( RADIO_GET_STATUS, &stat, 1 ); + status.Fields.CmdStatus = ( stat & ( 0x07 << 1 ) ) >> 1; + status.Fields.ChipMode = ( stat & ( 0x07 << 4 ) ) >> 4; + return status; +} + +int8_t SUBGRF_GetRssiInst( void ) +{ + uint8_t buf[1]; + int8_t rssi = 0; + + SUBGRF_ReadCommand( RADIO_GET_RSSIINST, buf, 1 ); + rssi = -buf[0] >> 1; + return rssi; +} + +void SUBGRF_GetRxBufferStatus( uint8_t *payloadLength, uint8_t *rxStartBufferPointer ) +{ + uint8_t status[2]; + + SUBGRF_ReadCommand( RADIO_GET_RXBUFFERSTATUS, status, 2 ); + + // In case of LORA fixed header, the payloadLength is obtained by reading + // the register REG_LR_PAYLOADLENGTH + if( ( SUBGRF_GetPacketType( ) == PACKET_TYPE_LORA ) && ( LoRaHeaderType == LORA_PACKET_FIXED_LENGTH ) ) + { + *payloadLength = SUBGRF_ReadRegister( REG_LR_PAYLOADLENGTH ); + } + else + { + *payloadLength = status[0]; + } + *rxStartBufferPointer = status[1]; +} + +void SUBGRF_GetPacketStatus( PacketStatus_t *pktStatus ) +{ + uint8_t status[3]; + + SUBGRF_ReadCommand( RADIO_GET_PACKETSTATUS, status, 3 ); + + pktStatus->packetType = SUBGRF_GetPacketType( ); + switch( pktStatus->packetType ) + { + case PACKET_TYPE_GFSK: + pktStatus->Params.Gfsk.RxStatus = status[0]; + pktStatus->Params.Gfsk.RssiSync = -status[1] >> 1; + pktStatus->Params.Gfsk.RssiAvg = -status[2] >> 1; + pktStatus->Params.Gfsk.FreqError = 0; + break; + + case PACKET_TYPE_LORA: + pktStatus->Params.LoRa.RssiPkt = -status[0] >> 1; + // Returns SNR value [dB] rounded to the nearest integer value + pktStatus->Params.LoRa.SnrPkt = ( ( ( int8_t )status[1] ) + 2 ) >> 2; + pktStatus->Params.LoRa.SignalRssiPkt = -status[2] >> 1; + pktStatus->Params.LoRa.FreqError = FrequencyError; + break; + + default: + case PACKET_TYPE_NONE: + // In that specific case, we set everything in the pktStatus to zeros + // and reset the packet type accordingly + RADIO_MEMSET8( pktStatus, 0, sizeof( PacketStatus_t ) ); + pktStatus->packetType = PACKET_TYPE_NONE; + break; + } +} + +RadioError_t SUBGRF_GetDeviceErrors( void ) +{ + uint8_t err[] = { 0, 0 }; + RadioError_t error = { .Value = 0 }; + + SUBGRF_ReadCommand( RADIO_GET_ERROR, ( uint8_t * )err, 2 ); + error.Fields.PaRamp = ( err[0] & ( 1 << 0 ) ) >> 0; + error.Fields.PllLock = ( err[1] & ( 1 << 6 ) ) >> 6; + error.Fields.XoscStart = ( err[1] & ( 1 << 5 ) ) >> 5; + error.Fields.ImgCalib = ( err[1] & ( 1 << 4 ) ) >> 4; + error.Fields.AdcCalib = ( err[1] & ( 1 << 3 ) ) >> 3; + error.Fields.PllCalib = ( err[1] & ( 1 << 2 ) ) >> 2; + error.Fields.Rc13mCalib = ( err[1] & ( 1 << 1 ) ) >> 1; + error.Fields.Rc64kCalib = ( err[1] & ( 1 << 0 ) ) >> 0; + return error; +} + +void SUBGRF_ClearDeviceErrors( void ) +{ + uint8_t buf[2] = { 0x00, 0x00 }; + SUBGRF_WriteCommand( RADIO_CLR_ERROR, buf, 2 ); +} + +void SUBGRF_ClearIrqStatus( uint16_t irq ) +{ + uint8_t buf[2]; + + buf[0] = ( uint8_t )( ( ( uint16_t )irq >> 8 ) & 0x00FF ); + buf[1] = ( uint8_t )( ( uint16_t )irq & 0x00FF ); + SUBGRF_WriteCommand( RADIO_CLR_IRQSTATUS, buf, 2 ); +} + +void SUBGRF_WriteRegister( uint16_t addr, uint8_t data ) +{ + CRITICAL_SECTION_BEGIN(); + HAL_SUBGHZ_WriteRegisters( &hsubghz, addr, (uint8_t*)&data, 1 ); + CRITICAL_SECTION_END(); +} + +uint8_t SUBGRF_ReadRegister( uint16_t addr ) +{ + uint8_t data; + CRITICAL_SECTION_BEGIN(); + HAL_SUBGHZ_ReadRegisters( &hsubghz, addr, &data, 1 ); + CRITICAL_SECTION_END(); + return data; +} + +void SUBGRF_WriteRegisters( uint16_t address, uint8_t *buffer, uint16_t size ) +{ + CRITICAL_SECTION_BEGIN(); + HAL_SUBGHZ_WriteRegisters( &hsubghz, address, buffer, size ); + CRITICAL_SECTION_END(); +} + +void SUBGRF_ReadRegisters( uint16_t address, uint8_t *buffer, uint16_t size ) +{ + CRITICAL_SECTION_BEGIN(); + HAL_SUBGHZ_ReadRegisters( &hsubghz, address, buffer, size ); + CRITICAL_SECTION_END(); +} + +void SUBGRF_WriteBuffer( uint8_t offset, uint8_t *buffer, uint8_t size ) +{ + CRITICAL_SECTION_BEGIN(); + HAL_SUBGHZ_WriteBuffer( &hsubghz, offset, buffer, size ); + CRITICAL_SECTION_END(); +} + +void SUBGRF_ReadBuffer( uint8_t offset, uint8_t *buffer, uint8_t size ) +{ + CRITICAL_SECTION_BEGIN(); + HAL_SUBGHZ_ReadBuffer( &hsubghz, offset, buffer, size ); + CRITICAL_SECTION_END(); +} + +void SUBGRF_WriteCommand( SUBGHZ_RadioSetCmd_t Command, uint8_t *pBuffer, + uint16_t Size ) +{ + CRITICAL_SECTION_BEGIN(); + HAL_SUBGHZ_ExecSetCmd( &hsubghz, Command, pBuffer, Size ); + CRITICAL_SECTION_END(); +} + +void SUBGRF_ReadCommand( SUBGHZ_RadioGetCmd_t Command, uint8_t *pBuffer, + uint16_t Size ) +{ + CRITICAL_SECTION_BEGIN(); + HAL_SUBGHZ_ExecGetCmd( &hsubghz, Command, pBuffer, Size ); + CRITICAL_SECTION_END(); +} + +void SUBGRF_SetSwitch( uint8_t paSelect, RFState_t rxtx ) +{ + RBI_Switch_TypeDef state = RBI_SWITCH_RX; + + if (rxtx == RFSWITCH_TX) + { + if (paSelect == RFO_LP) + { + state = RBI_SWITCH_RFO_LP; + Radio_SMPS_Set(SMPS_DRIVE_SETTING_MAX); + } + if (paSelect == RFO_HP) + { + state = RBI_SWITCH_RFO_HP; + } + } + else + { + if (rxtx == RFSWITCH_RX) + { + state = RBI_SWITCH_RX; + } + } + RBI_ConfigRFSwitch(state); +} + +uint8_t SUBGRF_SetRfTxPower( int8_t power ) +{ + uint8_t paSelect= RFO_LP; + + int32_t TxConfig = RBI_GetTxConfig(); + + switch (TxConfig) + { + case RBI_CONF_RFO_LP_HP: + { + if (power > 15) + { + paSelect = RFO_HP; + } + else + { + paSelect = RFO_LP; + } + break; + } + case RBI_CONF_RFO_LP: + { + paSelect = RFO_LP; + break; + } + case RBI_CONF_RFO_HP: + { + paSelect = RFO_HP; + break; + } + default: + break; + } + + SUBGRF_SetTxParams( paSelect, power, RADIO_RAMP_40_US ); + + return paSelect; +} + +uint32_t SUBGRF_GetRadioWakeUpTime( void ) +{ + return RF_WAKEUP_TIME; +} + +/* HAL_SUBGHz Callbacks definitions */ +void HAL_SUBGHZ_TxCpltCallback(SUBGHZ_HandleTypeDef *hsubghz) +{ + RadioOnDioIrqCb( IRQ_TX_DONE ); +} + +void HAL_SUBGHZ_RxCpltCallback(SUBGHZ_HandleTypeDef *hsubghz) +{ + RadioOnDioIrqCb( IRQ_RX_DONE ); +} + +void HAL_SUBGHZ_CRCErrorCallback (SUBGHZ_HandleTypeDef *hsubghz) +{ + RadioOnDioIrqCb( IRQ_CRC_ERROR); +} + +void HAL_SUBGHZ_CADStatusCallback(SUBGHZ_HandleTypeDef *hsubghz, HAL_SUBGHZ_CadStatusTypeDef cadstatus) +{ + switch (cadstatus) + { + case HAL_SUBGHZ_CAD_CLEAR: + RadioOnDioIrqCb( IRQ_CAD_CLEAR); + break; + case HAL_SUBGHZ_CAD_DETECTED: + RadioOnDioIrqCb( IRQ_CAD_DETECTED); + break; + default: + break; + } +} + +void HAL_SUBGHZ_RxTxTimeoutCallback(SUBGHZ_HandleTypeDef *hsubghz) +{ + RadioOnDioIrqCb( IRQ_RX_TX_TIMEOUT ); +} + +void HAL_SUBGHZ_HeaderErrorCallback(SUBGHZ_HandleTypeDef *hsubghz) +{ + RadioOnDioIrqCb( IRQ_HEADER_ERROR ); +} + +void HAL_SUBGHZ_PreambleDetectedCallback(SUBGHZ_HandleTypeDef *hsubghz) +{ + RadioOnDioIrqCb( IRQ_PREAMBLE_DETECTED ); +} + +void HAL_SUBGHZ_SyncWordValidCallback(SUBGHZ_HandleTypeDef *hsubghz) +{ + RadioOnDioIrqCb( IRQ_SYNCWORD_VALID ); +} + +void HAL_SUBGHZ_HeaderValidCallback(SUBGHZ_HandleTypeDef *hsubghz) +{ + RadioOnDioIrqCb( IRQ_HEADER_VALID ); +} + +void HAL_SUBGHZ_LrFhssHopCallback(SUBGHZ_HandleTypeDef *hsubghz) +{ + RadioOnDioIrqCb( IRQ_LR_FHSS_HOP ); +} + +static void Radio_SMPS_Set(uint8_t level) +{ + if ( 1U == RBI_IsDCDC() ) + { + uint8_t modReg; + modReg= SUBGRF_ReadRegister(SUBGHZ_SMPSC2R); + modReg&= (~SMPS_DRV_MASK); + SUBGRF_WriteRegister(SUBGHZ_SMPSC2R, modReg | level); + } +} + +uint8_t SUBGRF_GetFskBandwidthRegValue( uint32_t bandwidth ) +{ + uint8_t i; + + if( bandwidth == 0 ) + { + return( 0x1F ); + } + + for( i = 0; i < ( sizeof( FskBandwidths ) / sizeof( FskBandwidth_t ) ); i++ ) + { + if ( bandwidth < FskBandwidths[i].bandwidth ) + { + return FskBandwidths[i].RegValue; + } + } + // ERROR: Value not found + while( 1 ); +} +void SUBGRF_GetCFO( uint32_t bitRate, int32_t *cfo) +{ + uint8_t BwMant[] = {4, 8, 10, 12}; + /* read demod bandwidth: mant bit4:3, exp bits 2:0 */ + uint8_t reg = (SUBGRF_ReadRegister( SUBGHZ_BWSELR )); + uint8_t bandwidth_mant = BwMant[( reg >> 3 ) & 0x3]; + uint8_t bandwidth_exp = reg & 0x7; + uint32_t cf_fs = XTAL_FREQ / ( bandwidth_mant * ( 1 << ( bandwidth_exp + 1 ))); + uint32_t cf_osr = cf_fs / bitRate; + uint8_t interp = 1; + /* calculate demod interpolation factor */ + if (cf_osr * interp < 8) + { + interp = 2; + } + if (cf_osr * interp < 4) + { + interp = 4; + } + /* calculate demod sampling frequency */ + uint32_t fs = cf_fs* interp; + /* get the cfo registers */ + int32_t cfo_bin = ( SUBGRF_ReadRegister( SUBGHZ_GCFORH ) & 0xF ) << 8; + cfo_bin |= SUBGRF_ReadRegister( SUBGHZ_GCFORL ); + /* negate if 12 bits sign bit is 1 */ + if (( cfo_bin & 0x800 ) == 0x800 ) + { + cfo_bin |= 0xFFFFF000; + } + /* calculate cfo in Hz */ + /* shift by 5 first to not saturate, cfo_bin on 12bits */ + *cfo = ((int32_t)( cfo_bin * ( fs >> 5 ))) >> ( 12 - 5 ); +} diff --git a/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.h b/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.h new file mode 100644 index 0000000..07bb42e --- /dev/null +++ b/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.h @@ -0,0 +1,1307 @@ +/*! + * \file radio_driver.h + * + * \brief STM32WL_SubGHz_Phy driver implementation + * + * \copyright Revised BSD License, see section \ref LICENSE. + * + * \code + * ______ _ + * / _____) _ | | + * ( (____ _____ ____ _| |_ _____ ____| |__ + * \____ \| ___ | (_ _) ___ |/ ___) _ \ + * _____) ) ____| | | || |_| ____( (___| | | | + * (______/|_____)_|_|_| \__)_____)\____)_| |_| + * (C)2013-2017 Semtech + * + * \endcode + * + * \author Miguel Luis ( Semtech ) + * + * \author Gregory Cristian ( Semtech ) + */ +/** + ****************************************************************************** + * + * Portions COPYRIGHT 2020 STMicroelectronics + * + * @file radio_driver.h + * @author MCD Application Team + * @brief Header for driver radio interface + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __RADIO_DRIVER_H__ +#define __RADIO_DRIVER_H__ + +#ifdef __cplusplus +extern "C" { +#endif +/* Includes ------------------------------------------------------------------*/ + +#include +#include +#include "radio_conf.h" + +/* Exported constants --------------------------------------------------------*/ +#define RFO_LP 1 +#define RFO_HP 2 + +/* Exported macros --------------------------------------------------------*/ +#define SX_FREQ_TO_CHANNEL( channel, freq ) \ +do \ +{ \ + channel = (uint32_t) ((((uint64_t) freq)<<25)/(XTAL_FREQ) ); \ +}while( 0 ) + + +/*! + * \brief Radio complete Wake-up Time with margin for temperature compensation + */ +#define RADIO_WAKEUP_TIME 3 // [ms] + +/*! + * \brief Compensation delay for SetAutoTx/Rx functions in 15.625 microseconds + */ +#define AUTO_RX_TX_OFFSET 2 + +/*! + * \brief LFSR initial value to compute IBM type CRC + */ +#define CRC_IBM_SEED 0xFFFF + +/*! + * \brief LFSR initial value to compute CCIT type CRC + */ +#define CRC_CCITT_SEED 0x1D0F + +/*! + * \brief Polynomial used to compute IBM CRC + */ +#define CRC_POLYNOMIAL_IBM 0x8005 + +/*! + * \brief Polynomial used to compute CCIT CRC + */ +#define CRC_POLYNOMIAL_CCITT 0x1021 + +/*! + * \brief The address of the register holding the first byte defining the CRC seed + * + */ +#define REG_LR_CRCSEEDBASEADDR 0x06BC + +/*! + * \brief The address of the register holding the first byte defining the CRC polynomial + */ +#define REG_LR_CRCPOLYBASEADDR 0x06BE + +/*! + * \brief The address of the register holding the first byte defining the whitening seed + */ +#define REG_LR_WHITSEEDBASEADDR_MSB 0x06B8 +#define REG_LR_WHITSEEDBASEADDR_LSB 0x06B9 + +/*! + * \brief The address of the register holding the packet configuration + */ +#define REG_LR_PACKETPARAMS 0x0704 + +/*! + * \brief The address of the register holding the payload size + */ +#define REG_LR_PAYLOADLENGTH 0x0702 + +/*! + * \brief The address of the register holding the re-calculated number of symbols + */ +#define REG_LR_SYNCH_TIMEOUT 0x0706 + +/*! + * \brief The addresses of the registers holding SyncWords values + */ +#define REG_LR_SYNCWORDBASEADDRESS 0x06C0 + +/*! + * \brief The addresses of the register holding LoRa Modem SyncWord value + */ +#define REG_LR_SYNCWORD 0x0740 + +/*! + * \brief Syncword for Private LoRa networks + */ +#define LORA_MAC_PRIVATE_SYNCWORD 0x1424 + +/*! + * \brief Syncword for Public LoRa networks + */ +#define LORA_MAC_PUBLIC_SYNCWORD 0x3444 + +/*! + * \brief The address of the register giving a 32-bit random number + */ +#define RANDOM_NUMBER_GENERATORBASEADDR 0x0819 + +/*! + * \brief The address of the register used to disable the LNA + */ +#define REG_ANA_LNA 0x08E2 + +/*! + * The address of the register used to disable the mixer + */ +#define REG_ANA_MIXER 0x08E5 + +/*! + * \brief The address of the register holding RX Gain value (0x94: power saving, 0x96: rx boosted) + */ +#define REG_RX_GAIN 0x08AC + +/*! + * \brief The address of the register holding Bit Sync configuration + */ +#define REG_BIT_SYNC 0x06AC + +/*! + * \brief The address of the register holding the Tx boost value + */ +#define REG_DRV_CTRL 0x091F + +/*! + * \brief Change the value on the device internal trimming capacitor + */ +#define REG_XTA_TRIM 0x0911 + +/*! + * \brief Change the value on the device internal trimming capacitor + */ +#define REG_XTB_TRIM 0x0912 + +/*! + * \brief Set the current max value in the over current protection + */ +#define REG_OCP 0x08E7 + +/*! + * \brief PA Clamping threshold + */ +#define REG_TX_CLAMP 0x08D8 + +/** + * @brief Sub-GHz radio RAM definition + * @note The sub-GHz radio peripheral RAM address can be accessed by sub-GHz radio command + * SUBGRF_WriteRegisters() and SUBGRF_ReadRegisters() " + * @note These RAM addresses are used to control accurately ramp-up, ramp-down and length of a frame + */ +/*Sub-GHz radio Ramp Up High register*/ +#define SUBGHZ_RAM_RAMPUPH 0x00F0 +/*Sub-GHz radio Ramp Up Low register*/ +#define SUBGHZ_RAM_RAMPUPL 0x00F1 +/*Sub-GHz radio Ramp Down High register*/ +#define SUBGHZ_RAM_RAMPDNH 0x00F2 +/*Sub-GHz radio Ramp Down Low register*/ +#define SUBGHZ_RAM_RAMPDNL 0x00F3 +/*Sub-GHz radio frame limit High register*/ +#define SUBGHZ_RAM_FRAMELIMH 0x00F4 +/*Sub-GHz radio frame limit Low register*/ +#define SUBGHZ_RAM_FRAMELIML 0x00F5 + +/** + * @brief Sub-GHz radio register (re) definition + * @note The sub-GHz radio peripheral registers can be accessed by sub-GHz radio command + * SUBGRF_WriteRegisters() and SUBGRF_ReadRegisters() " + */ + +/*Sub-GHz radio generic bit synchronization register*/ +#define SUBGHZ_GBSYNCR REG_BIT_SYNC +/*Sub-GHz radio generic CFO High register */ +#define SUBGHZ_GCFORH 0x06B0 +/*Sub-GHz radio generic CFO Low register */ +#define SUBGHZ_GCFORL 0x06B1 +/*Sub-GHz radio generic pktCtl1 register*/ +#define SUBGHZ_GPKTCTL1R 0x06B4 +/*Sub-GHz radio generic packet control 1A register*/ +#define SUBGHZ_GPKTCTL1AR REG_LR_WHITSEEDBASEADDR_MSB +/*Sub-GHz radio generic whitening LSB register*/ +#define SUBGHZ_GWHITEINIRL REG_LR_WHITSEEDBASEADDR_LSB +/*Sub-GHz radio generic rtx register*/ +#define SUBGHZ_GRTXPLDLEN 0x06BB +/*Sub-GHz radio generic CRC initial MSB register*/ +#define SUBGHZ_GCRCINIRH REG_LR_CRCSEEDBASEADDR +/*Sub-GHz radio generic CRC initial LSB register*/ +#define SUBGHZ_GCRCINIRL 0x06BD +/*Sub-GHz radio generic CRC polynomial MSB register*/ +#define SUBGHZ_GCRCPOLRH REG_LR_CRCPOLYBASEADDR +/*Sub-GHz radio generic CRC polynomial LSB register*/ +#define SUBGHZ_GCRCPOLRL 0x06BF +/*Sub-GHz radio generic synchronization word control register 0*/ +#define SUBGHZ_GSYNCR0 REG_LR_SYNCWORDBASEADDRESS +/*Sub-GHz radio generic synchronization word control register 1*/ +#define SUBGHZ_GSYNCR1 0x06C1 +/*Sub-GHz radio generic synchronization word control register 2*/ +#define SUBGHZ_GSYNCR2 0x06C2 +/*Sub-GHz radio generic synchronization word control register 3*/ +#define SUBGHZ_GSYNCR3 0x06C3 +/*Sub-GHz radio generic synchronization word control register 4*/ +#define SUBGHZ_GSYNCR4 0x06C4 +/*Sub-GHz radio generic synchronization word control register 5*/ +#define SUBGHZ_GSYNCR5 0x06C5 +/*Sub-GHz radio generic synchronization word control register 6*/ +#define SUBGHZ_GSYNCR6 0x06C6 +/*Sub-GHz radio generic synchronization word control register 7*/ +#define SUBGHZ_GSYNCR7 0x06C7 +/*Sub-GHz radio generic node address register*/ +#define SUBGHZ_GNODEADDR 0x06CD +/*Sub-GHz radio generic broadacst address register*/ +#define SUBGHZ_GBCASTADDR 0x06CE +/*Sub-GHz radio generic Afc register*/ +#define SUBGHZ_GAFCR 0x06D1 +/*Sub-GHz radio Lora Payload Length */ +#define SUBGHZ_LPLDLENR REG_LR_PAYLOADLENGTH +/*Sub-GHz radio Lora synchro timeout */ +#define SUBGHZ_LSYNCTIMEOUTR REG_LR_SYNCH_TIMEOUT +/*Sub-GHz radio Lora IQ polarity register*/ +#define SUBGHZ_LIQPOLR 0x0736 +/*Sub-GHz radio LoRa synchronization word MSB register*/ +#define SUBGHZ_LSYNCRH REG_LR_SYNCWORD +/*Sub-GHz radio LoRa synchronization word LSB register*/ +#define SUBGHZ_LSYNCRL 0x0741 +/*Sub-GHz radio txAddrPtr register*/ +#define SUBGHZ_TXADRPTR 0x0802 +/*Sub-GHz radio rxAddrPtr register*/ +#define SUBGHZ_RXADRPTR 0x0803 +/*Sub-GHz radio Rx Bandwidth selector register */ +#define SUBGHZ_BWSELR 0x0807 +/*Sub-GHz radio random number register 3*/ +#define SUBGHZ_RNGR3 RANDOM_NUMBER_GENERATORBASEADDR +/*Sub-GHz radio random number register 2*/ +#define SUBGHZ_RNGR2 0x081A +/*Sub-GHz radio random number register 1*/ +#define SUBGHZ_RNGR1 0x081B +/*Sub-GHz radio random number register 0*/ +#define SUBGHZ_RNGR0 0x081C +/*Sub-GHz radio SD resolution*/ +#define SUBGHZ_SDCFG0R 0x0889 +/*Sub-GHz radio Agc Gfo Reset Rssi Control register*/ +#define SUBGHZ_AGCRSSICTL0R 0x089B +/*Sub-GHz radio Agc LoRa register*/ +#define SUBGHZ_AGCCFG 0x08A3 +/*Sub-GHz radio receiver gain control register*/ +#define SUBGHZ_RXGAINCR REG_RX_GAIN +/*Sub-GHz radio Agc Gfo Reset Config register*/ +#define SUBGHZ_AGCGFORSTCFGR 0x08B8 +/*Sub-GHz radio Agc Gfo Reset Power Threshold register*/ +#define SUBGHZ_AGCGFORSTPOWTHR 0x08B9 +/*Sub-GHz radio Tx clamp register*/ +#define SUBGHZ_TXCLAMPR REG_TX_CLAMP +/*Sub-GHz radio PA over current protection register*/ +#define SUBGHZ_PAOCPR REG_OCP +/*Sub-GHz radio rtc control register*/ +#define SUBGHZ_RTCCTLR 0x0902 +/*Sub-GHz radio rtc period register*/ +#define SUBGHZ_RTCPRDR2 0x0903 +#define SUBGHZ_RTCPRDR1 0x0904 +#define SUBGHZ_RTCPRDR0 0x0905 +/*Sub-GHz radio HSE32 OSC_IN capacitor trim register*/ +#define SUBGHZ_HSEINTRIMR REG_XTA_TRIM +/*Sub-GHz radio HSE32 OSC_OUT capacitor trim register*/ +#define SUBGHZ_HSEOUTTRIMR REG_XTB_TRIM +/*Sub-GHz radio SMPS control 0 register */ +#define SUBGHZ_SMPSC0R 0x0916 +/*Sub-GHz radio power control register*/ +#define SUBGHZ_PCR 0x091A +/*Sub-GHz radio SMPS control 2 register */ +#define SUBGHZ_SMPSC2R 0x0923 +/*Sub-GHz event mask register*/ +#define SUBGHZ_EVENTMASKR 0x0944 + +#define SMPS_CLK_DET_ENABLE ((uint8_t) (1<<6)) + +#define SMPS_DRV_20 ((uint8_t) ((0x0)<<1)) +#define SMPS_DRV_40 ((uint8_t) ((0x1)<<1)) +#define SMPS_DRV_60 ((uint8_t) ((0x2)<<1)) +#define SMPS_DRV_100 ((uint8_t) ((0x3)<<1)) +#define SMPS_DRV_MASK ((uint8_t) ((0x3)<<1)) + +/* Exported types ------------------------------------------------------------*/ +/*! + * \brief Structure describing the radio status + */ +typedef union RadioPhyStatus_u +{ + uint8_t Value; + struct + { //bit order is lsb -> msb + uint8_t Reserved : 1; //!< Reserved + uint8_t CmdStatus : 3; //!< Command status + uint8_t ChipMode : 3; //!< Chip mode + uint8_t CpuBusy : 1; //!< Flag for CPU radio busy + }Fields; +}RadioPhyStatus_t; + +/*! + * \brief Structure describing the error codes for callback functions + */ +typedef enum +{ + IRQ_HEADER_ERROR_CODE = 0x01, + IRQ_SYNCWORD_ERROR_CODE = 0x02, + IRQ_CRC_ERROR_CODE = 0x04, +}IrqErrorCode_t; + +enum IrqPblSyncHeaderCode_t +{ + IRQ_PBL_DETECT_CODE = 0x01, + IRQ_SYNCWORD_VALID_CODE = 0x02, + IRQ_HEADER_VALID_CODE = 0x04, +}; + +/*! + * \brief Declares the oscillator in use while in standby mode + * + * Using the STDBY_RC standby mode allow to reduce the energy consumption + * STDBY_XOSC should be used for time critical applications + */ +typedef enum +{ + STDBY_RC = 0x00, + STDBY_XOSC = 0x01, +}RadioStandbyModes_t; + +/*! + * \brief Declares the power regulation used to power the device + * + * This command allows the user to specify if DC-DC or LDO is used for power regulation. + * Using only LDO implies that the Rx or Tx current is doubled + */ +typedef enum +{ + USE_LDO = 0x00, // default + USE_DCDC = 0x01, +}RadioRegulatorMode_t; + +/*! + * \brief Represents the possible packet type (i.e. modem) used + */ +typedef enum +{ + PACKET_TYPE_GFSK = 0x00, + PACKET_TYPE_LORA = 0x01, + PACKET_TYPE_BPSK = 0x02, + PACKET_TYPE_GMSK = 0x03, + PACKET_TYPE_LR_FHSS = 0x03, + PACKET_TYPE_NONE = 0x0F, +}RadioPacketTypes_t; + +/*! + * \brief Represents the ramping time for power amplifier + */ +typedef enum +{ + RADIO_RAMP_10_US = 0x00, + RADIO_RAMP_20_US = 0x01, + RADIO_RAMP_40_US = 0x02, + RADIO_RAMP_80_US = 0x03, + RADIO_RAMP_200_US = 0x04, + RADIO_RAMP_800_US = 0x05, + RADIO_RAMP_1700_US = 0x06, + RADIO_RAMP_3400_US = 0x07, +}RadioRampTimes_t; + +/*! + * \brief Represents the number of symbols to be used for channel activity detection operation + */ +typedef enum +{ + LORA_CAD_01_SYMBOL = 0x00, + LORA_CAD_02_SYMBOL = 0x01, + LORA_CAD_04_SYMBOL = 0x02, + LORA_CAD_08_SYMBOL = 0x03, + LORA_CAD_16_SYMBOL = 0x04, +}RadioLoRaCadSymbols_t; + +/*! + * \brief Represents the Channel Activity Detection actions after the CAD operation is finished + */ +typedef enum +{ + LORA_CAD_ONLY = 0x00, + LORA_CAD_RX = 0x01, + LORA_CAD_LBT = 0x10, +}RadioCadExitModes_t; + +/*! + * \brief Represents the modulation shaping parameter + */ +typedef enum +{ + MOD_SHAPING_OFF = 0x00, + MOD_SHAPING_G_BT_03 = 0x08, + MOD_SHAPING_G_BT_05 = 0x09, + MOD_SHAPING_G_BT_07 = 0x0A, + MOD_SHAPING_G_BT_1 = 0x0B, + MOD_SHAPING_DBPSK = 0x16, +}RadioModShapings_t; + +/*! + * \brief Represents the modulation shaping parameter + */ +typedef enum +{ + RX_BW_4800 = 0x1F, + RX_BW_5800 = 0x17, + RX_BW_7300 = 0x0F, + RX_BW_9700 = 0x1E, + RX_BW_11700 = 0x16, + RX_BW_14600 = 0x0E, + RX_BW_19500 = 0x1D, + RX_BW_23400 = 0x15, + RX_BW_29300 = 0x0D, + RX_BW_39000 = 0x1C, + RX_BW_46900 = 0x14, + RX_BW_58600 = 0x0C, + RX_BW_78200 = 0x1B, + RX_BW_93800 = 0x13, + RX_BW_117300 = 0x0B, + RX_BW_156200 = 0x1A, + RX_BW_187200 = 0x12, + RX_BW_234300 = 0x0A, + RX_BW_312000 = 0x19, + RX_BW_373600 = 0x11, + RX_BW_467000 = 0x09, +}RadioRxBandwidth_t; + +/*! + * \brief Represents the possible spreading factor values in LoRa packet types + */ +typedef enum +{ + LORA_SF5 = 0x05, + LORA_SF6 = 0x06, + LORA_SF7 = 0x07, + LORA_SF8 = 0x08, + LORA_SF9 = 0x09, + LORA_SF10 = 0x0A, + LORA_SF11 = 0x0B, + LORA_SF12 = 0x0C, +}RadioLoRaSpreadingFactors_t; + +/*! + * \brief Represents the bandwidth values for LoRa packet type + */ +typedef enum +{ + LORA_BW_500 = 6, + LORA_BW_250 = 5, + LORA_BW_125 = 4, + LORA_BW_062 = 3, + LORA_BW_041 = 10, + LORA_BW_031 = 2, + LORA_BW_020 = 9, + LORA_BW_015 = 1, + LORA_BW_010 = 8, + LORA_BW_007 = 0, +}RadioLoRaBandwidths_t; + +/*! + * \brief Represents the coding rate values for LoRa packet type + */ +typedef enum +{ + LORA_CR_4_5 = 0x01, + LORA_CR_4_6 = 0x02, + LORA_CR_4_7 = 0x03, + LORA_CR_4_8 = 0x04, +}RadioLoRaCodingRates_t; + +/*! + * \brief Represents the preamble length used to detect the packet on Rx side + */ +typedef enum +{ + RADIO_PREAMBLE_DETECTOR_OFF = 0x00, //!< Preamble detection length off + RADIO_PREAMBLE_DETECTOR_08_BITS = 0x04, //!< Preamble detection length 8 bits + RADIO_PREAMBLE_DETECTOR_16_BITS = 0x05, //!< Preamble detection length 16 bits + RADIO_PREAMBLE_DETECTOR_24_BITS = 0x06, //!< Preamble detection length 24 bits + RADIO_PREAMBLE_DETECTOR_32_BITS = 0x07, //!< Preamble detection length 32 bit +}RadioPreambleDetection_t; + +/*! + * \brief Represents the possible combinations of SyncWord correlators activated + */ +typedef enum +{ + RADIO_ADDRESSCOMP_FILT_OFF = 0x00, //!< No correlator turned on, i.e. do not search for SyncWord + RADIO_ADDRESSCOMP_FILT_NODE = 0x01, + RADIO_ADDRESSCOMP_FILT_NODE_BROAD = 0x02, +}RadioAddressComp_t; + +/*! + * \brief Radio GFSK packet length mode + */ +typedef enum +{ + RADIO_PACKET_FIXED_LENGTH = 0x00, //!< The packet is known on both sides, no header included in the packet + RADIO_PACKET_VARIABLE_LENGTH = 0x01, //!< The packet is on variable size, header included +}RadioPacketLengthModes_t; + +/*! + * \brief Represents the CRC length + */ +typedef enum +{ + RADIO_CRC_OFF = 0x01, //!< No CRC in use + RADIO_CRC_1_BYTES = 0x00, + RADIO_CRC_2_BYTES = 0x02, + RADIO_CRC_1_BYTES_INV = 0x04, + RADIO_CRC_2_BYTES_INV = 0x06, + RADIO_CRC_2_BYTES_IBM = 0xF1, + RADIO_CRC_2_BYTES_CCIT = 0xF2, +}RadioCrcTypes_t; + +/*! + * \brief Radio whitening mode activated or deactivated + */ +typedef enum +{ + RADIO_DC_FREE_OFF = 0x00, + RADIO_DC_FREEWHITENING = 0x01, +}RadioDcFree_t; + +/*! + * \brief Holds the Radio lengths mode for the LoRa packet type + */ +typedef enum +{ + LORA_PACKET_VARIABLE_LENGTH = 0x00, //!< The packet is on variable size, header included + LORA_PACKET_FIXED_LENGTH = 0x01, //!< The packet is known on both sides, no header included in the packet + LORA_PACKET_EXPLICIT = LORA_PACKET_VARIABLE_LENGTH, + LORA_PACKET_IMPLICIT = LORA_PACKET_FIXED_LENGTH, +}RadioLoRaPacketLengthsMode_t; + +/*! + * \brief Represents the CRC mode for LoRa packet type + */ +typedef enum +{ + LORA_CRC_ON = 0x01, //!< CRC activated + LORA_CRC_OFF = 0x00, //!< CRC not used +}RadioLoRaCrcModes_t; + +/*! + * \brief Represents the IQ mode for LoRa packet type + */ +typedef enum +{ + LORA_IQ_NORMAL = 0x00, + LORA_IQ_INVERTED = 0x01, +}RadioLoRaIQModes_t; + +/*! + * \brief Represents the voltage used to control the TCXO on/off VDD_TCXO + */ +typedef enum +{ + TCXO_CTRL_1_6V = 0x00, + TCXO_CTRL_1_7V = 0x01, + TCXO_CTRL_1_8V = 0x02, + TCXO_CTRL_2_2V = 0x03, + TCXO_CTRL_2_4V = 0x04, + TCXO_CTRL_2_7V = 0x05, + TCXO_CTRL_3_0V = 0x06, + TCXO_CTRL_3_3V = 0x07, +}RadioTcxoCtrlVoltage_t; + +/*! + * \brief Represents the interruption masks available for the radio + * + * \remark Note that not all these interruptions are available for all packet types + */ +typedef enum +{ + IRQ_RADIO_NONE = 0x0000, + IRQ_TX_DONE = 0x0001, + IRQ_RX_DONE = 0x0002, + IRQ_PREAMBLE_DETECTED = 0x0004, + IRQ_SYNCWORD_VALID = 0x0008, + IRQ_HEADER_VALID = 0x0010, + IRQ_HEADER_ERROR = 0x0020, + IRQ_CRC_ERROR = 0x0040, + IRQ_CAD_CLEAR = 0x0080, + IRQ_CAD_DETECTED = 0x0100, + IRQ_RX_TX_TIMEOUT = 0x0200, + IRQ_LR_FHSS_HOP = 0x4000, + IRQ_RADIO_ALL = 0xFFFF, +}RadioIrqMasks_t; + +/*! + * \brief The type describing the modulation parameters for every packet types + */ +typedef struct +{ + RadioPacketTypes_t PacketType; //!< Packet to which the modulation parameters are referring to. + struct + { + struct + { + uint32_t BitRate; + uint32_t Fdev; + RadioModShapings_t ModulationShaping; + uint8_t Bandwidth; + }Gfsk; + struct + { + uint32_t BitRate; + RadioModShapings_t ModulationShaping; + }Bpsk; + struct + { + RadioLoRaSpreadingFactors_t SpreadingFactor; //!< Spreading Factor for the LoRa modulation + RadioLoRaBandwidths_t Bandwidth; //!< Bandwidth for the LoRa modulation + RadioLoRaCodingRates_t CodingRate; //!< Coding rate for the LoRa modulation + uint8_t LowDatarateOptimize; //!< Indicates if the modem uses the low datarate optimization + }LoRa; + }Params; //!< Holds the modulation parameters structure +}ModulationParams_t; + +/*! + * \brief The type describing the packet parameters for every packet types + */ +typedef struct +{ + RadioPacketTypes_t PacketType; //!< Packet to which the packet parameters are referring to. + struct + { + /*! + * \brief Holds the GFSK packet parameters + */ + struct + { + uint16_t PreambleLength; //!< The preamble Tx length for GFSK packet type in bit + RadioPreambleDetection_t PreambleMinDetect; //!< The preamble Rx length minimal for GFSK packet type + uint8_t SyncWordLength; //!< The synchronization word length for GFSK packet type + RadioAddressComp_t AddrComp; //!< Activated SyncWord correlators + RadioPacketLengthModes_t HeaderType; //!< If the header is explicit, it will be transmitted in the GFSK packet. If the header is implicit, it will not be transmitted + uint8_t PayloadLength; //!< Size of the payload in the GFSK packet + RadioCrcTypes_t CrcLength; //!< Size of the CRC block in the GFSK packet + RadioDcFree_t DcFree; + }Gfsk; + /*! + * \brief Holds the BPSK packet parameters + */ + struct + { + uint8_t PayloadLength; //!< Size of the payload in the BPSK packet + }Bpsk; + /*! + * \brief Holds the LoRa packet parameters + */ + struct + { + uint16_t PreambleLength; //!< The preamble length is the number of LoRa symbols in the preamble + RadioLoRaPacketLengthsMode_t HeaderType; //!< If the header is explicit, it will be transmitted in the LoRa packet. If the header is implicit, it will not be transmitted + uint8_t PayloadLength; //!< Size of the payload in the LoRa packet + RadioLoRaCrcModes_t CrcMode; //!< Size of CRC block in LoRa packet + RadioLoRaIQModes_t InvertIQ; //!< Allows to swap IQ for LoRa packet + }LoRa; + }Params; //!< Holds the packet parameters structure +}PacketParams_t; + +/*! + * \brief Represents the packet status for every packet type + */ +typedef struct +{ + RadioPacketTypes_t packetType; //!< Packet to which the packet status are referring to. + struct + { + struct + { + uint8_t RxStatus; + int8_t RssiAvg; //!< The averaged RSSI + int8_t RssiSync; //!< The RSSI measured on last packet + uint32_t FreqError; + }Gfsk; + struct + { + int8_t RssiPkt; //!< The RSSI of the last packet + int8_t SnrPkt; //!< The SNR of the last packet + int8_t SignalRssiPkt; + uint32_t FreqError; + }LoRa; + }Params; +}PacketStatus_t; + +/*! + * \brief Represents the Rx internal counters values when GFSK or LoRa packet type is used + */ +typedef struct +{ + RadioPacketTypes_t packetType; //!< Packet to which the packet status are referring to. + uint16_t PacketReceived; + uint16_t CrcOk; + uint16_t LengthError; +}RxCounter_t; + +/*! + * \brief Represents a calibration configuration + */ +typedef union +{ + struct + { + uint8_t RC64KEnable : 1; //!< Calibrate RC64K clock + uint8_t RC13MEnable : 1; //!< Calibrate RC13M clock + uint8_t PLLEnable : 1; //!< Calibrate PLL + uint8_t ADCPulseEnable : 1; //!< Calibrate ADC Pulse + uint8_t ADCBulkNEnable : 1; //!< Calibrate ADC bulkN + uint8_t ADCBulkPEnable : 1; //!< Calibrate ADC bulkP + uint8_t ImgEnable : 1; + uint8_t : 1; + }Fields; + uint8_t Value; +}CalibrationParams_t; + +/*! + * \brief Represents a sleep mode configuration + */ +typedef union +{ + struct + { + uint8_t WakeUpRTC : 1; //!< Get out of sleep mode if wakeup signal received from RTC + uint8_t Reset : 1; + uint8_t WarmStart : 1; + uint8_t Reserved : 5; + }Fields; + uint8_t Value; +}SleepParams_t; + +/*! + * \brief Represents the possible radio system error states + */ +typedef union +{ + struct + { + uint8_t Rc64kCalib : 1; //!< RC 64kHz oscillator calibration failed + uint8_t Rc13mCalib : 1; //!< RC 13MHz oscillator calibration failed + uint8_t PllCalib : 1; //!< PLL calibration failed + uint8_t AdcCalib : 1; //!< ADC calibration failed + uint8_t ImgCalib : 1; //!< Image calibration failed + uint8_t XoscStart : 1; //!< XOSC oscillator failed to start + uint8_t PllLock : 1; //!< PLL lock failed + uint8_t BuckStart : 1; //!< Buck converter failed to start + uint8_t PaRamp : 1; //!< PA ramp failed + uint8_t : 7; //!< Reserved + }Fields; + uint16_t Value; +}RadioError_t; + +/*! + * \brief Represents the operating mode the radio is actually running + */ +typedef enum +{ + MODE_SLEEP = 0x00, //! The radio is in sleep mode + MODE_STDBY_RC, //! The radio is in standby mode with RC oscillator + MODE_STDBY_XOSC, //! The radio is in standby mode with XOSC oscillator + MODE_FS, //! The radio is in frequency synthesis mode + MODE_TX, //! The radio is in transmit mode + MODE_RX, //! The radio is in receive mode + MODE_RX_DC, //! The radio is in receive duty cycle mode + MODE_CAD //! The radio is in channel activity detection mode +}RadioOperatingModes_t; + +/*! + * \brief Radio driver internal state machine states definition + */ +typedef enum +{ + RFSWITCH_RX = 0, //!< The radio is in RX + RFSWITCH_TX = 1 //!< The radio is in TX +}RFState_t; + +/*! + * Hardware IO IRQ callback function definition + */ +typedef void ( *DioIrqHandler )( RadioIrqMasks_t radioIrq ); + +#define RX_BUFFER_SIZE 256 + +/* External variables --------------------------------------------------------*/ +/* Exported macros -----------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +/*! + * ============================================================================ + * Public functions prototypes + * ============================================================================ + */ + +/*! + * \brief Initializes the bus for SUBG_RF driver communication + */ +void SUBGRF_Init( DioIrqHandler dioIrq ); + + /*! + * \brief Gets the current Operation Mode of the Radio + * + * \retval RadioOperatingModes_t last operating mode + */ +RadioOperatingModes_t SUBGRF_GetOperatingMode( void ); + +/*! + * \brief Saves the payload to be send in the radio buffer + * + * \param [in] payload A pointer to the payload + * \param [in] size The size of the payload + */ +void SUBGRF_SetPayload( uint8_t *payload, uint8_t size ); + +/*! + * \brief Reads the payload received. If the received payload is longer + * than maxSize, then the method returns 1 and do not set size and payload. + * + * \param [out] payload A pointer to a buffer into which the payload will be copied + * \param [out] size A pointer to the size of the payload received + * \param [in] maxSize The maximal size allowed to copy into the buffer + */ +uint8_t SUBGRF_GetPayload( uint8_t *payload, uint8_t *size, uint8_t maxSize ); + +/*! + * \brief Sends a payload + * + * \param [in] payload A pointer to the payload to send + * \param [in] size The size of the payload to send + * \param [in] timeout The timeout for Tx operation + */ +void SUBGRF_SendPayload( uint8_t *payload, uint8_t size, uint32_t timeout ); + +/*! + * \brief Sets the Sync Word given by index used in GFSK + * + * \param [in] syncWord SyncWord bytes ( 8 bytes ) + * + * \retval status [0: OK, 1: NOK] + */ +uint8_t SUBGRF_SetSyncWord( uint8_t *syncWord ); + +/*! + * \brief Sets the Initial value for the LFSR used for the CRC calculation + * + * \param [in] seed Initial LFSR value ( 2 bytes ) + * + */ +void SUBGRF_SetCrcSeed( uint16_t seed ); + +/*! + * \brief Sets the seed used for the CRC calculation + * + * \param [in] polynomial The polynomial value + * + */ +void SUBGRF_SetCrcPolynomial( uint16_t polynomial ); + +/*! + * \brief Sets the Initial value of the LFSR used for the whitening in GFSK protocols + * + * \param [in] seed Initial LFSR value + */ +void SUBGRF_SetWhiteningSeed( uint16_t seed ); + +/*! + * \brief Gets a 32-bit random value generated by the radio + * + * \remark A valid packet type must have been configured with \ref SUBGRF_SetPacketType + * before using this command. + * + * \remark The radio must be in reception mode before executing this function + * This code can potentially result in interrupt generation. It is the responsibility of + * the calling code to disable radio interrupts before calling this function, + * and re-enable them afterwards if necessary, or be certain that any interrupts + * generated during this process will not cause undesired side-effects in the software. + * + * Please note that the random numbers produced by the generator do not have a uniform or Gaussian distribution. If + * uniformity is needed, perform appropriate software post-processing. + * + * \retval randomValue 32 bits random value + */ +uint32_t SUBGRF_GetRandom( void ); + +/*! + * \brief Sets the radio in sleep mode + * + * \param [in] sleepConfig The sleep configuration describing data + * retention and RTC wake-up + */ +void SUBGRF_SetSleep( SleepParams_t sleepConfig ); + +/*! + * \brief Sets the radio in configuration mode + * + * \param [in] mode The standby mode to put the radio into + */ +void SUBGRF_SetStandby( RadioStandbyModes_t mode ); + +/*! + * \brief Sets the radio in FS mode + */ +void SUBGRF_SetFs( void ); + +/*! + * \brief Sets the radio in transmission mode + * + * \param [in] timeout Structure describing the transmission timeout value + */ +void SUBGRF_SetTx( uint32_t timeout ); + +/*! + * \brief Sets the radio in reception mode + * + * \param [in] timeout Structure describing the reception timeout value + */ +void SUBGRF_SetRx( uint32_t timeout ); + +/*! + * \brief Sets the radio in reception mode with Boosted LNA gain + * + * \param [in] timeout Structure describing the reception timeout value + */ +void SUBGRF_SetRxBoosted( uint32_t timeout ); + +/*! + * \brief Sets the Rx duty cycle management parameters + * + * \param [in] rxTime Structure describing reception timeout value + * \param [in] sleepTime Structure describing sleep timeout value + */ +void SUBGRF_SetRxDutyCycle( uint32_t rxTime, uint32_t sleepTime ); + +/*! + * \brief Sets the radio in CAD mode + */ +void SUBGRF_SetCad( void ); + +/*! + * \brief Sets the radio in continuous wave transmission mode + */ +void SUBGRF_SetTxContinuousWave( void ); + +/*! + * \brief Sets the radio in continuous preamble transmission mode + */ +void SUBGRF_SetTxInfinitePreamble( void ); + +/*! + * \brief Decide which interrupt will stop the internal radio rx timer. + * + * \param [in] enable [0: Timer stop after header/syncword detection + * 1: Timer stop after preamble detection] + */ +void SUBGRF_SetStopRxTimerOnPreambleDetect( bool enable ); + +/*! + * \brief Set the number of symbol the radio will wait to validate a reception + * + * \param [in] symbNum number of LoRa symbols + */ +void SUBGRF_SetLoRaSymbNumTimeout( uint8_t symbNum ); + +/*! + * \brief Sets the power regulators operating mode + */ +void SUBGRF_SetRegulatorMode( void ); + +/*! + * \brief Calibrates the given radio block + * + * \param [in] calibParam The description of blocks to be calibrated + */ +void SUBGRF_Calibrate( CalibrationParams_t calibParam ); + +/*! + * \brief Calibrates the Image rejection depending of the frequency + * + * \param [in] freq The operating frequency + */ +void SUBGRF_CalibrateImage( uint32_t freq ); + +/*! + * \brief Activate the extension of the timeout when long preamble is used + * + * \param [in] enable The radio will extend the timeout to cope with long preamble + */ +void SUBGRF_SetLongPreamble( uint8_t enable ); + +/*! + * \brief Sets the transmission parameters + * + * \param [in] paDutyCycle Duty Cycle for the PA + * \param [in] hpMax 0 for RFO_LP, 7 for RFO_HP + * \param [in] deviceSel 1 for RFO_LP, 0 for RFO_HP + * \param [in] paLut 0 for 14dBm LUT, 1 for 22dBm LUT + */ +void SUBGRF_SetPaConfig( uint8_t paDutyCycle, uint8_t hpMax, uint8_t deviceSel, uint8_t paLut ); + +/*! + * \brief Defines into which mode the chip goes after a TX / RX done + * + * \param [in] fallbackMode The mode in which the radio goes + */ +void SUBGRF_SetRxTxFallbackMode( uint8_t fallbackMode ); + +/*! + * \brief Write data to the radio memory + * + * \param [in] address The address of the first byte to write in the radio + * \param [in] buffer The data to be written in radio's memory + * \param [in] size The number of bytes to write in radio's memory + */ +void SUBGRF_WriteRegisters( uint16_t address, uint8_t *buffer, uint16_t size ); + +/*! + * \brief Read data from the radio memory + * + * \param [in] address The address of the first byte to read from the radio + * \param [out] buffer The buffer that holds data read from radio + * \param [in] size The number of bytes to read from radio's memory + */ +void SUBGRF_ReadRegisters( uint16_t address, uint8_t *buffer, uint16_t size ); + +/*! + * \brief Write data to the buffer holding the payload in the radio + * + * \param [in] offset The offset to start writing the payload + * \param [in] buffer The data to be written (the payload) + * \param [in] size The number of byte to be written + */ +void SUBGRF_WriteBuffer( uint8_t offset, uint8_t *buffer, uint8_t size ); + +/*! + * \brief Read data from the buffer holding the payload in the radio + * + * \param [in] offset The offset to start reading the payload + * \param [out] buffer A pointer to a buffer holding the data from the radio + * \param [in] size The number of byte to be read + */ +void SUBGRF_ReadBuffer( uint8_t offset, uint8_t *buffer, uint8_t size ); + +/*! + * \brief Write command to the radio + * + * \param [in] Command The Write Command + * \param [out] pBuffer A pointer command buffer + * \param [in] Size Size in byte of the command buffer + */ +void SUBGRF_WriteCommand( SUBGHZ_RadioSetCmd_t Command, uint8_t *pBuffer, + uint16_t Size ); + +/*! + * \brief Read command to the radio + * + * \param [in] Command The Read Command + * \param [out] pBuffer A pointer command buffer + * \param [in] Size Size in byte of the command buffer + */ +void SUBGRF_ReadCommand( SUBGHZ_RadioGetCmd_t Command, uint8_t *pBuffer, + uint16_t Size ); + +/*! + * \brief Sets the IRQ mask and DIO masks + * + * \param [in] irqMask General IRQ mask + * \param [in] dio1Mask DIO1 mask + * \param [in] dio2Mask DIO2 mask + * \param [in] dio3Mask DIO3 mask + */ +void SUBGRF_SetDioIrqParams( uint16_t irqMask, uint16_t dio1Mask, uint16_t dio2Mask, uint16_t dio3Mask ); + +/*! + * \brief Returns the current IRQ status + * + * \retval irqStatus IRQ status + */ +uint16_t SUBGRF_GetIrqStatus( void ); + +/*! + * \brief Indicates if the Radio main clock is supplied from a tcxo + * + * \param [in] tcxoVoltage voltage used to control the TCXO + * \param [in] timeout time given to the TCXO to go to 32MHz + */ +void SUBGRF_SetTcxoMode( RadioTcxoCtrlVoltage_t tcxoVoltage, uint32_t timeout ); + +/*! + * \brief Sets the RF frequency + * + * \param [in] frequency RF frequency [Hz] + */ +void SUBGRF_SetRfFrequency( uint32_t frequency ); + +/*! + * \brief Sets the radio for the given protocol + * + * \param [in] packetType [PACKET_TYPE_GFSK, PACKET_TYPE_LORA] + * + * \remark This method has to be called before SetRfFrequency, + * SetModulationParams and SetPacketParams + */ +void SUBGRF_SetPacketType( RadioPacketTypes_t packetType ); + +/*! + * \brief Gets the current radio protocol + * + * \retval packetType [PACKET_TYPE_GFSK, PACKET_TYPE_LORA] + */ +RadioPacketTypes_t SUBGRF_GetPacketType( void ); + +/*! + * \brief Sets the transmission parameters + * + * \param [in] paSelect RegPaConfig PaSelect value (RFO_LP, RFO_HP, etc) + * \param [in] power RF output power [-18..13] dBm + * \param [in] rampTime Transmission ramp up time + */ +void SUBGRF_SetTxParams( uint8_t paSelect, int8_t power, RadioRampTimes_t rampTime ); + +/*! + * \brief Set the modulation parameters + * + * \param [in] modParams A structure describing the modulation parameters + */ +void SUBGRF_SetModulationParams( ModulationParams_t *modParams ); + +/*! + * \brief Sets the packet parameters + * + * \param [in] packetParams A structure describing the packet parameters + */ +void SUBGRF_SetPacketParams( PacketParams_t *packetParams ); + +/*! + * \brief Sets the Channel Activity Detection (CAD) parameters + * + * \param [in] cadSymbolNum The number of symbol to use for CAD operations + * [LORA_CAD_01_SYMBOL, LORA_CAD_02_SYMBOL, + * LORA_CAD_04_SYMBOL, LORA_CAD_08_SYMBOL, + * LORA_CAD_16_SYMBOL] + * \param [in] cadDetPeak Limit for detection of SNR peak used in the CAD + * \param [in] cadDetMin Set the minimum symbol recognition for CAD + * \param [in] cadExitMode Operation to be done at the end of CAD action + * [LORA_CAD_ONLY, LORA_CAD_RX, LORA_CAD_LBT] + * \param [in] cadTimeout Defines the timeout value to abort the CAD activity + */ +void SUBGRF_SetCadParams( RadioLoRaCadSymbols_t cadSymbolNum, uint8_t cadDetPeak, uint8_t cadDetMin, RadioCadExitModes_t cadExitMode, uint32_t cadTimeout ); + +/*! + * \brief Sets the data buffer base address for transmission and reception + * + * \param [in] txBaseAddress Transmission base address + * \param [in] rxBaseAddress Reception base address + */ +void SUBGRF_SetBufferBaseAddress( uint8_t txBaseAddress, uint8_t rxBaseAddress ); + +/*! + * \brief Gets the current radio status + * + * \retval status Radio status + */ +RadioPhyStatus_t SUBGRF_GetStatus( void ); + +/*! + * \brief Returns the instantaneous RSSI value for the last packet received + * + * \retval rssiInst Instantaneous RSSI + */ +int8_t SUBGRF_GetRssiInst( void ); + +/*! + * \brief Gets the last received packet buffer status + * + * \param [out] payloadLength Last received packet payload length + * \param [out] rxStartBuffer Last received packet buffer address pointer + */ +void SUBGRF_GetRxBufferStatus( uint8_t *payloadLength, uint8_t *rxStartBuffer ); + +/*! + * \brief Gets the last received packet payload length + * + * \param [out] pktStatus A structure of packet status + */ +void SUBGRF_GetPacketStatus( PacketStatus_t *pktStatus ); + +/*! + * \brief Returns the possible system errors + * + * \retval sysErrors Value representing the possible sys failures + */ +RadioError_t SUBGRF_GetDeviceErrors( void ); + +/*! + * \brief Clear all the errors in the device + */ +void SUBGRF_ClearDeviceErrors( void ); + +/*! + * \brief Clears the IRQs + * + * \param [in] irq IRQ(s) to be cleared + */ +void SUBGRF_ClearIrqStatus( uint16_t irq ); + +/*! + * \brief Write radio register + * \param [in] address The address of the register + * \param [in] data data to write + */ +void SUBGRF_WriteRegister( uint16_t address, uint8_t data ); + +/*! + * \brief Read radio register + * \param [in] address The address of the register + * \retval Data read + */ +uint8_t SUBGRF_ReadRegister( uint16_t address ); + +/*! + * \brief Sets RF switch for TX & RX + * \param [in] paSelect Low Power or High Power board + * \param [in] rxtx RX/TX mode + */ +void SUBGRF_SetSwitch (uint8_t paSelect, RFState_t rxtx); + +/*! + * \brief Set the Tx End Device conducted power + * \param [in] power Tx power level [0..15] + * \retval paSelect [RFO_LP, RFO_HP] + */ +uint8_t SUBGRF_SetRfTxPower( int8_t power ); + +/*! + * \brief Service to get the radio wake-up time. + * \return Value of the radio wake-up time. + */ +uint32_t SUBGRF_GetRadioWakeUpTime( void ); + +/*! + * \brief Returns the known FSK bandwidth registers value + * + * \param [in] bandwidth Bandwidth value in Hz + * \retval regValue Bandwidth register value. + */ +uint8_t SUBGRF_GetFskBandwidthRegValue( uint32_t bandwidth ); +/*! + * \brief SUBGRF_GetCFO get the frequency offset between the remote transmitter and the radio receiver + * + * \param [in] bitrate gfsk bitrate + * \param [out] cfo carrier frequency offset in Hertz + */ +void SUBGRF_GetCFO( uint32_t bitrate, int32_t *cfo); + +#ifdef __cplusplus +} +#endif + +#endif // __RADIO_DRIVER_H__ diff --git a/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.c b/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.c new file mode 100644 index 0000000..5aa3d5b --- /dev/null +++ b/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.c @@ -0,0 +1,1112 @@ +/*! + ****************************************************************************** + * @file radio_fw.c + * @author MCD Application Team + * @brief extends the limited set of radio HW functionalities by FW algorithms + ****************************************************************************** + * @attention + * + * Copyright (c) 2020(-2021) STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include +#include "timer.h" +#include "radio_fw.h" +#include "radio_conf.h" +#include "radio_driver.h" +#include "mw_log_conf.h" + +/* External variables --------------------------------------------------------*/ +/* Private typedef -----------------------------------------------------------*/ + +/*! + * Radio RFWPacket and global parameters + * In RFWPacket mode, the packet is 'Fixed length' without Hw Crc check and without Hw (de-)whitening + */ +typedef struct +{ + uint8_t Enable; /* RFWPacket mode On: 1 or Off: 0*/ + uint8_t PayloadLengthFieldSize; /* Size of the packet length Field*/ + uint8_t CrcEnable; /* enable crc calculation and check*/ + uint8_t CrcFieldSize; /* size of the packet length Field*/ + uint16_t CrcPolynomial; /* Init Crc polynomial, to set before running RFW_CrcRun*/ + uint16_t CrcSeed; /* Init Crc seed to set before running RFW_CrcRun*/ + RADIO_FSK_CrcTypes_t CrcType; /* Init Crc types to set before running RFW_CrcRun*/ + uint16_t WhiteSeed; /* Init whitening seed, to set before running Radio_FwWhiteRun*/ + uint16_t LongPacketMaxRxLength; /* Maximum expected amount of bytes in payload*/ + RadioModems_t Modem; + RadioEvents_t *RadioEvents; +} RFwInit_t; + +typedef struct +{ + RFwInit_t Init; /* Init structure, set at Rx or Tx config*/ + uint16_t CrcLfsrState; /* State of LFSR crc, set from CrcSeed at beginning of each payload*/ + uint16_t WhiteLfsrState; /* State of LFSR whitening, set from WhiteSeed at beginning of each payload + use to save LFSR state after rx payload length de-whitening*/ + uint16_t PayloadLength; /* In Rx, Payload length is first byte(s) of the payload + excluding CrcFieldSize and PayloadLengthFieldSize*/ + uint8_t LongPacketModeEnable; /* set to one when RFW_TransmitLongPacket or RFW_ReceiveLongPacket. 0 otherwise*/ + TimerEvent_t Timer; /* Timer to get/Set Rx(Tx)Bytes*/ + uint16_t LongPacketRemainingBytes; /* Count remaining bytes to send receive (including crc)*/ + uint8_t RadioBufferOffset; /* Radio buffer offset*/ + uint16_t RxPayloadOffset; /* RxPayloadOffset buffer offset*/ + void ( *RxLongPacketStoreChunkCb )( uint8_t *buffer, uint8_t buffer_size ); + void ( *TxLongPacketGetNextChunkCb )( uint8_t **buffer, uint8_t buffer_size ); + uint8_t AntSwitchPaSelect; + uint32_t BitRate; + TimerEvent_t *RxTimeoutTimer; + TimerEvent_t *TxTimeoutTimer; +} RadioFw_t; + +/* Private define ------------------------------------------------------------*/ + +#define RADIO_BUF_SIZE 255 /* bytes SubG IP internal Buffer */ + +#define LONGPACKET_CHUNK_LENGTH_BYTES ((int32_t) 128) /* bytes (half Radio fifo) */ + +/* Private macro -------------------------------------------------------------*/ +/*! + * @brief Calculates ceiling division of ( X / N ) + * + * @param [in] X numerator + * @param [in] N denominator + * + */ +#ifndef DIVC +#define DIVC( X, N ) ( ( ( X ) + ( N ) - 1 ) / ( N ) ) +#endif /* DIVC */ + +/*! + * @brief Calculates rounding division of ( X / N ) + * + * @param [in] X numerator + * @param [in] N denominator + * + */ +#ifndef DIVR +#define DIVR( X, N ) ( ( ( X ) + ( ((X)>0?(N):(N))>>1 ) ) / ( N ) ) +#endif /* DIVR */ + +/*can be overridden in radio_conf.h*/ +#ifndef RFW_IT_INIT +#define RFW_IT_INIT() +#endif /* RFW_IT_INIT */ + +#ifndef RFW_GET_PAYLOAD_PROCESS +#define RFW_GET_PAYLOAD_PROCESS() RFW_GetPayloadProcess() +#endif /* RFW_GET_PAYLOAD_PROCESS */ + +/*can be overridden in radio_conf.h*/ +#ifndef RFW_TRANSMIT_LONGPACKET_TX_CHUNK_PROCESS +#define RFW_TRANSMIT_LONGPACKET_TX_CHUNK_PROCESS() RFW_TransmitLongPacket_TxChunkProcess() +#endif /* RFW_TRANSMIT_LONGPACKET_TX_CHUNK_PROCESS */ + +#ifndef RFW_MW_LOG_ENABLE +#define RFW_MW_LOG(...) +#else +#define RFW_MW_LOG MW_LOG +#endif /* RFW_MW_LOG_ENABLE */ + +#ifndef RFW_ENABLE +#define RFW_ENABLE 0 +#endif /* RFW_ENABLE */ + +#ifndef RFW_LONGPACKET_ENABLE +#define RFW_LONGPACKET_ENABLE 0 +#endif /* v */ + +#ifndef RADIO_MEMCPY8 +#define RADIO_MEMCPY8 memcpy +#endif /* RADIO_MEMCPY8 */ + +#ifndef RADIO_MEMSET8 +#define RADIO_MEMSET8 memset +#endif /* RADIO_MEMSET8 */ + +#if ((RFW_LONGPACKET_ENABLE==1)&&(RFW_ENABLE==0)) +#error RFW_ENABLE must be defined to 1 if RFW_LONGPACKET_ENABLE is defined to 1 +#endif /* RFW_LONGPACKET_ENABLE */ + +/* Private variables ---------------------------------------------------------*/ +#if (RFW_ENABLE == 1 ) +static RadioFw_t RFWPacket = {0}; +/*Radio buffer chunk*/ +static uint8_t ChunkBuffer[RADIO_BUF_SIZE]; +/*Radio buffer chunk for packet <=RADIO_BUF_SIZE and */ +static uint8_t RxBuffer[RADIO_BUF_SIZE]; +#endif /* RFW_ENABLE == 1 */ +/* Private function prototypes -----------------------------------------------*/ +#if (RFW_ENABLE == 1 ) +/*! + * @brief Record the seed of the (de-)Whitening algorithm + * + * @param [in] RFwInit_t the whitening Init structure + * @param [in] WhiteSeed the Initial seed of the Whitening algorithm + */ +static void RFW_WhiteInitState( RFwInit_t *Init, uint16_t WhiteSeed ); + +/*! + * @brief Set the state of the Whitening algorithm from the seed + * + * @param [in] RFWPacket the whitening structure + * @param [in] whiteSeed the Initial seed of the Whitening algorithm + */ +static void RFW_WhiteSetState( RadioFw_t *RFWPacket ); + +/*! + * @brief Initialize seed of the Crc algorithm + * + * @param [in] RFWPacket the whitening Init structure + * @param [in] CrcPolynomial the Initial seed of the Crc algorithm + * @param [in] CrcSeed the Initial seed of the Crc seed + * @param [in] CrcSeed the Initial seed of the Crc types (Ibm/CCITT) + */ +static void RFW_CrcInitState( RFwInit_t *Init, const uint16_t CrcPolynomial, const uint16_t CrcSeed, + const RADIO_FSK_CrcTypes_t CrcTypes ); + +/*! + * @brief Run the Crc algorithm + * @param [in] RFWPacket the whitening structure + */ +static void RFW_CrcSetState( RadioFw_t *RFWPacket ); +/*! + * @brief Run the Whitening algorithm + * + * @param [in] RFWPacket the whitening structure + * @param [in,out] Payload the Payload to (de-)Whiten and the payload result + * @param [in] Size the Payload size + */ +static void RFW_WhiteRun( RadioFw_t *RFWPacket, uint8_t *Payload, uint32_t Size ); + +/*! + * @brief Run the Crc algorithm + * + * @param [in] RFWPacket the whitening structure + * @param [in] Payload the Payload to calculate the Crc + * @param [in] Size the Payload size + * @param [out] CrcResult the result of the Crc calculation + */ +static int32_t RFW_CrcRun( RadioFw_t *const RFWPacket, const uint8_t *Payload, const uint32_t Size, + uint8_t CrcResult[2] ); + +/*! + * @brief Compute Crc Byte + * + * @param [in] crc Crc bytes + * @param [in] dataByte the data byte + * @param [out] polynomial the polynomial to use + * @return crc bytes out + */ +uint16_t RFW_CrcRun1Byte( uint16_t Crc, uint8_t DataByte, uint16_t Polynomial ); + +/*! + * @brief Get the payload length after sync + * + * @param [out] PayloadLength the length of PayloadOnly excluding CrcLengthField + * @return 0 when no parameters error, -1 otherwise + */ +static int32_t RFW_GetPacketLength( uint16_t *PayloadLength ); + +/*! + * @brief RFW_GetPayloadTimerEvent TimerEvent to get the payload data, de-whitening, and crc verification + * + * @Note calls RFW_GetPayloadProcess directly inside IRQ (default) or in background with sequencer or OS + * @param [in] context context of the timer + */ +static void RFW_GetPayloadTimerEvent( void *context ); + +/*! + * @brief RFW_GetPayloadProcess process to get the payload data, de-whitening, and crc verification + */ +static void RFW_GetPayloadProcess( void ); + +#if (RFW_LONGPACKET_ENABLE == 1 ) +/*! + * @brief RFW_TransmitLongPacket_NewTxChunkTimer: long packet Tx timer callback to process intermediate chunk of TxData + * @Note calls RFW_TransmitLongPacket_TxChunkProcess directly inside IRQ (default) or in background with sequencer or any Rtos + * + * @param [in] param unused + */ +static void RFW_TransmitLongPacket_NewTxChunkTimerEvent( void *param ); + +/*! + * @brief RFW_TransmitLongPacket_TxChunkProcess: tx long packet process intermediate chunk of TxData + */ +static void RFW_TransmitLongPacket_TxChunkProcess( void ); +#endif /* RFW_LONGPACKET_ENABLE == 1 */ + +/*! + * @brief RFW_GetPayload get the payload of + * + * @param [in] Offset Offset of the + * @param [in] Length carrier frequency offset in Hertz + */ +static void RFW_GetPayload( uint8_t Offset, uint8_t Length ); +#endif /* RFW_ENABLE == 1 */ + +/* Exported functions --------------------------------------------------------*/ +int32_t RFW_TransmitLongPacket( uint16_t payload_size, uint32_t timeout, + void ( *TxLongPacketGetNextChunkCb )( uint8_t **buffer, uint8_t buffer_size ) ) +{ + int32_t status = 0; +#if (RFW_LONGPACKET_ENABLE == 1 ) + uint32_t total_size = payload_size + RFWPacket.Init.PayloadLengthFieldSize + RFWPacket.Init.CrcFieldSize; + + RFW_MW_LOG( TS_ON, VLEVEL_M, "RevID=%04X\r\n", LL_DBGMCU_GetRevisionID() ); + + if( ( TxLongPacketGetNextChunkCb == NULL ) || + ( payload_size > ( 1 << ( 8 * RFWPacket.Init.PayloadLengthFieldSize ) ) - 1 ) || /*check that size fits inside the packetLengthField*/ + ( RFWPacket.Init.Enable == 0 ) || /* Can only be used when after RadioSetTxGenericConfig*/ + ( LL_DBGMCU_GetRevisionID() < 0x1003 ) ) /* Only available from stm32wl revision Y*/ + { + status = -1; + } + else + { + /*chunk buffer pointer fed by the application*/ + uint8_t *app_chunk_buffer_ptr = NULL; + /*size of the chunk to be sent*/ + uint8_t chunk_size; + uint8_t crc_size; + /*timeout for next chunk*/ + uint32_t chunk_timeout; + /*Records call back*/ + RFWPacket.TxLongPacketGetNextChunkCb = TxLongPacketGetNextChunkCb; + + /* Radio IRQ is set to DIO1 by default */ + SUBGRF_SetDioIrqParams( IRQ_TX_DONE | IRQ_RX_TX_TIMEOUT, + IRQ_TX_DONE | IRQ_RX_TX_TIMEOUT, + IRQ_RADIO_NONE, + IRQ_RADIO_NONE ); + + /* Set DBG pin */ + DBG_GPIO_RADIO_TX( SET ); + /* Set RF switch */ + SUBGRF_SetSwitch( RFWPacket.AntSwitchPaSelect, RFSWITCH_TX ); + + switch( RFWPacket.Init.Modem ) + { + case MODEM_FSK: + case MODEM_MSK: + { + if( RFWPacket.Init.Enable == 1 ) + { + /*crc will be calculated on the fly along with packet chunk transmission*/ + uint8_t crc_result[2]; + /*init radio buffer offset*/ + RFWPacket.RadioBufferOffset = 0; + /*long packet mode enable*/ + RFWPacket.LongPacketModeEnable = 1; + /*Remaining bytes to transmit*/ + RFWPacket.LongPacketRemainingBytes = total_size; + /*Records total payload bytes to transmit*/ + RFWPacket.PayloadLength = total_size; + if( total_size > RADIO_BUF_SIZE ) + { + /*cut in chunk*/ + if( total_size < RADIO_BUF_SIZE + RFWPacket.Init.CrcFieldSize ) + { + /*reduce chunk so that crc is treated in the next chunk*/ + chunk_size = RADIO_BUF_SIZE - RFWPacket.Init.PayloadLengthFieldSize - RFWPacket.Init.CrcFieldSize; + } + else + { + chunk_size = RADIO_BUF_SIZE - RFWPacket.Init.PayloadLengthFieldSize; + } + /*Set crc size for the crc calculation: no crc here because it is not the end of the packet*/ + crc_size = 0; + } + else + { + chunk_size = payload_size; + /*Set crc size for the crc calculation*/ + crc_size = RFWPacket.Init.CrcFieldSize; + } + /* Prepend payload size before Payload*/ + if( RFWPacket.Init.PayloadLengthFieldSize == 1 ) + { + ChunkBuffer[0] = payload_size; + } + else + { + ChunkBuffer[0] = ( uint8_t )( ( payload_size ) >> 8 ); + ChunkBuffer[1] = ( uint8_t )( ( payload_size ) & 0xFF ); + } + /* Get Tx chunk from app*/ + TxLongPacketGetNextChunkCb( &app_chunk_buffer_ptr, chunk_size ); + + /* Copy first chunk in ChunkBuffer Buffer*/ + RADIO_MEMCPY8( &ChunkBuffer[RFWPacket.Init.PayloadLengthFieldSize], app_chunk_buffer_ptr, chunk_size ); + + if( RFWPacket.Init.CrcEnable == 1 ) + { + /* Set the state of the Crc to crc_seed*/ + RFW_CrcSetState( &RFWPacket ); + /* Run the crc calculation on payload length and payload*/ + RFW_CrcRun( &RFWPacket, ChunkBuffer, RFWPacket.Init.PayloadLengthFieldSize + chunk_size, crc_result ); + /* Append the crc result after the payload if total_size<= RADIO_BUF_SIZE*/ + RADIO_MEMCPY8( &ChunkBuffer[RFWPacket.Init.PayloadLengthFieldSize + chunk_size], crc_result, crc_size ); + } + /* Init whitening at beginning of the packet*/ + RFW_WhiteSetState( &RFWPacket ); + /* Run the whitening calculation on payload length, payload and crc if crc fits inside 1st chunk*/ + RFW_WhiteRun( &RFWPacket, &ChunkBuffer[0], RFWPacket.Init.PayloadLengthFieldSize + chunk_size + crc_size ); + /* Configure the Transmitter to send all*/ + /* Init radio buffer */ + SUBGRF_WriteRegister( SUBGHZ_GRTXPLDLEN, RFWPacket.Init.PayloadLengthFieldSize + chunk_size + crc_size ); + SUBGRF_WriteRegister( SUBGHZ_TXADRPTR, 0 ); + /* Send*/ + SUBGRF_SendPayload( ChunkBuffer, RFWPacket.Init.PayloadLengthFieldSize + chunk_size + crc_size, 0 ); + if( total_size > RADIO_BUF_SIZE ) + { + /*in case total size is greater than RADIO_BUF_SIZE, need to program a timer to get next chunk*/ + /*RFWPacket.LongPacketRemainingBytes-= RFWPacket.Init.PayloadLengthFieldSize+ chunk_size+ crc_size;*/ + /*Initialize Timer to get new chunk and update radio ptr*/ + chunk_timeout = ( LONGPACKET_CHUNK_LENGTH_BYTES * 8 * 1000 ) / RFWPacket.BitRate; + RFW_MW_LOG( TS_ON, VLEVEL_M, "Timeout=%d,\r\n", chunk_timeout ); + TimerInit( &RFWPacket.Timer, RFW_TransmitLongPacket_NewTxChunkTimerEvent ); + TimerSetValue( &RFWPacket.Timer, chunk_timeout ); + TimerStart( &RFWPacket.Timer ); + /*Write bit infinite_sequence = 1, required for long packet*/ + uint8_t reg = SUBGRF_ReadRegister( SUBGHZ_GPKTCTL1AR ); + SUBGRF_WriteRegister( SUBGHZ_GPKTCTL1AR, reg | 0x02 ); + + TimerSetValue( RFWPacket.RxTimeoutTimer, timeout ); + TimerStart( RFWPacket.RxTimeoutTimer ); + } + } + else + { + /* error*/ + status = -1; + } + break; + } + case MODEM_LORA: + { + /* not supported by the radio Ip*/ + status = -2; + break; + } + case MODEM_BPSK: + { + /* not supported by the FW*/ + status = -2; + break; + } + case MODEM_SIGFOX_TX: + { + /* not supported by the FW*/ + status = -2; + break; + } + default: + break; + } + } +#else + status = -1; +#endif /* RFW_LONGPACKET_ENABLE == 1 */ + return status; +} + +int32_t RFW_ReceiveLongPacket( uint8_t boosted_mode, uint32_t timeout, + void ( *RxLongPacketStoreChunkCb )( uint8_t *buffer, uint8_t chunk_size ) ) +{ + int32_t status = 0; +#if (RFW_LONGPACKET_ENABLE == 1 ) + if( ( RxLongPacketStoreChunkCb == NULL ) || + ( RFWPacket.Init.Enable == 0 ) ) /* Can only be used when after RadioSetRxGenericConfig*/ + { + status = -1; + } + else + { + /*Records call back*/ + RFWPacket.RxLongPacketStoreChunkCb = RxLongPacketStoreChunkCb; + SUBGRF_SetDioIrqParams( IRQ_SYNCWORD_VALID | IRQ_RX_TX_TIMEOUT, + IRQ_SYNCWORD_VALID | IRQ_RX_TX_TIMEOUT, + IRQ_RADIO_NONE, + IRQ_RADIO_NONE ); + SUBGRF_SetSwitch( RFWPacket.AntSwitchPaSelect, RFSWITCH_RX ); + /*init radio buffer offset*/ + RFWPacket.RadioBufferOffset = 0; + /* Init whitening at beginning of the packet*/ + RFW_WhiteSetState( &RFWPacket ); + /* Set the state of the Crc to crc_seed*/ + RFW_CrcSetState( &RFWPacket ); + /* Init radio buffer */ + SUBGRF_WriteRegister( SUBGHZ_GRTXPLDLEN, 255 ); + SUBGRF_WriteRegister( SUBGHZ_RXADRPTR, 0 ); + /*enable long packet*/ + RFWPacket.LongPacketModeEnable = 1; + + if( timeout != 0 ) + { + TimerSetValue( RFWPacket.RxTimeoutTimer, timeout ); + TimerStart( RFWPacket.RxTimeoutTimer ); + } + DBG_GPIO_RADIO_RX( SET ); + if( boosted_mode == 1 ) + { + SUBGRF_SetRxBoosted( 0xFFFFFF ); /* Rx Continuous */ + } + else + { + SUBGRF_SetRx( 0xFFFFFF ); /* Rx Continuous */ + } + } +#else + status = -1; +#endif /* RFW_LONGPACKET_ENABLE == 1 */ + return status; +} + +int32_t RFW_Init( ConfigGeneric_t *config, RadioEvents_t *RadioEvents, TimerEvent_t *TimeoutTimerEvent ) +{ +#if (RFW_ENABLE == 1 ) + RADIO_FSK_PacketLengthModes_t HeaderType; + uint32_t RxMaxPayloadLength = 0; + RADIO_FSK_CrcTypes_t CrcLength; + uint16_t whiteSeed; + uint16_t CrcPolynomial; + uint16_t CrcSeed; + if( config->rtx == CONFIG_TX ) + { + HeaderType = config->TxConfig->fsk.HeaderType; + CrcLength = config->TxConfig->fsk.CrcLength; + whiteSeed = config->TxConfig->fsk.whiteSeed; + CrcPolynomial = config->TxConfig->fsk.CrcPolynomial; + CrcSeed = config->TxConfig->fsk.CrcSeed; + RFWPacket.BitRate = config->TxConfig->fsk.BitRate; + RFWPacket.TxTimeoutTimer = TimeoutTimerEvent; + } + else + { + HeaderType = config->RxConfig->fsk.LengthMode; + CrcLength = config->RxConfig->fsk.CrcLength; + RxMaxPayloadLength = config->RxConfig->fsk.MaxPayloadLength; + whiteSeed = config->RxConfig->fsk.whiteSeed; + CrcPolynomial = config->RxConfig->fsk.CrcPolynomial; + CrcSeed = config->RxConfig->fsk.CrcSeed; + RFWPacket.BitRate = config->RxConfig->fsk.BitRate; + RFWPacket.RxTimeoutTimer = TimeoutTimerEvent; + } + if( ( RadioEvents != NULL ) && ( RadioEvents->RxError ) ) + { + RFWPacket.Init.RadioEvents = RadioEvents; + } + else + { + return -1; + } + if( HeaderType == RADIO_FSK_PACKET_2BYTES_LENGTH ) + { +#if (RFW_LONGPACKET_ENABLE == 1 ) + RFWPacket.Init.PayloadLengthFieldSize = 2; +#else + return -1; +#endif /* RFW_LONGPACKET_ENABLE == 1 */ + } + else + { + RFWPacket.Init.PayloadLengthFieldSize = 1; + } + /*record, used to reject packet in length decoded at sync time out greater than LongPacketMaxRxLength*/ + RFWPacket.Init.LongPacketMaxRxLength = RxMaxPayloadLength; + if( CrcLength == RADIO_FSK_CRC_OFF ) + { + RFWPacket.Init.CrcEnable = 0; + RFWPacket.Init.CrcFieldSize = 0; + } + else + { + RFWPacket.Init.CrcEnable = 1; + RFWPacket.Init.CrcFieldSize = 2; + } + /*Macro can be used to init interrupt behaviour*/ + RFW_IT_INIT(); + /*Initialise whitening Seed*/ + RFW_WhiteInitState( &RFWPacket.Init, whiteSeed ); + /*Initialise Crc Seed*/ + RFW_CrcInitState( &RFWPacket.Init, CrcPolynomial, CrcSeed, CrcLength ); + /*Enable the RFWPacket decoding*/ + RFWPacket.Init.Enable = 1; + /* Initialize Timer for end of fixed packet, started at sync*/ + TimerInit( &RFWPacket.Timer, RFW_GetPayloadTimerEvent ); + return 0; +#else + return -1; +#endif /* RFW_ENABLE == 1 */ +} + +void RFW_DeInit( void ) +{ +#if (RFW_ENABLE == 1 ) + RFWPacket.Init.Enable = 0; /*Disable the RFWPacket decoding*/ +#endif /* RFW_ENABLE == 1 */ +} + +uint8_t RFW_Is_Init( void ) +{ +#if (RFW_ENABLE == 1 ) + return RFWPacket.Init.Enable; +#else + return 0; +#endif /* RFW_ENABLE == 1 */ +} + +uint8_t RFW_Is_LongPacketModeEnabled( void ) +{ +#if (RFW_ENABLE == 1 ) + return RFWPacket.LongPacketModeEnable; +#else + return 0; +#endif /* RFW_ENABLE == 1 */ +} + +void RFW_SetAntSwitch( uint8_t AntSwitch ) +{ +#if (RFW_ENABLE == 1 ) + RFWPacket.AntSwitchPaSelect = AntSwitch; +#endif /* RFW_ENABLE == 1 */ +} + +int32_t RFW_TransmitInit( uint8_t *inOutBuffer, uint8_t size, uint8_t *outSize ) +{ + int32_t status = -1; +#if (RFW_ENABLE == 1 ) + uint8_t crc_result[2]; + if( size + RFWPacket.Init.PayloadLengthFieldSize + RFWPacket.Init.CrcFieldSize > RADIO_BUF_SIZE ) + { + RFW_MW_LOG( TS_ON, VLEVEL_M, "RadioSend Oversize\r\n" ); + status = -1; + } + else + { + /* Copy tx buffer in payload*/ + RADIO_MEMCPY8( &ChunkBuffer[RFWPacket.Init.PayloadLengthFieldSize], inOutBuffer, size ); + /* Calculate the crc on */ + /* Payload Size without the packet length field nor the CRC */ + /* Prepend payload size before Payload*/ + if( RFWPacket.Init.PayloadLengthFieldSize == 1 ) + { + ChunkBuffer[0] = size; + } + else + { + ChunkBuffer[0] = 0; + ChunkBuffer[1] = size; + } + if( RFWPacket.Init.CrcEnable == 1 ) + { + /* Set the state of the Crc to crc_seed*/ + RFW_CrcSetState( &RFWPacket ); + /*Run the crc calculation on payload length and payload*/ + RFW_CrcRun( &RFWPacket, &ChunkBuffer[0], size + RFWPacket.Init.PayloadLengthFieldSize, crc_result ); + /*append the crc result after the payload*/ + RADIO_MEMCPY8( &ChunkBuffer[size + RFWPacket.Init.PayloadLengthFieldSize], crc_result, RFWPacket.Init.CrcFieldSize ); + } + /*init whitening at beginning of the packet*/ + RFW_WhiteSetState( &RFWPacket ); + /*Run the whitening calculation on payload length, payload and crc*/ + RFW_WhiteRun( &RFWPacket, &ChunkBuffer[0], size + RFWPacket.Init.PayloadLengthFieldSize + RFWPacket.Init.CrcFieldSize ); + /*Configure the Transmitter to send all*/ + *outSize = ( uint8_t ) size + RFWPacket.Init.PayloadLengthFieldSize + RFWPacket.Init.CrcFieldSize; + /*copy result*/ + RADIO_MEMCPY8( inOutBuffer, ChunkBuffer, *outSize ); + + RFWPacket.LongPacketModeEnable = 0; + + status = 0; + } +#endif /* RFW_ENABLE == 1 */ + return status; +} + +int32_t RFW_ReceiveInit( void ) +{ +#if (RFW_ENABLE == 1 ) + /* Radio IRQ is set to DIO1 by default */ + SUBGRF_SetDioIrqParams( IRQ_RADIO_ALL & ( ~IRQ_RX_DONE ), /* IRQ_RX_DONE | IRQ_RX_TX_TIMEOUT, */ + IRQ_RADIO_ALL & ( ~IRQ_RX_DONE ), /* IRQ_RX_DONE | IRQ_RX_TX_TIMEOUT, */ + IRQ_RADIO_NONE, + IRQ_RADIO_NONE ); + + /*init whitening at beginning of the packet*/ + RFW_WhiteSetState( &RFWPacket ); + /* Set the state of the Crc to crc_seed*/ + RFW_CrcSetState( &RFWPacket ); + + RFWPacket.RxPayloadOffset = 0; + + RFWPacket.LongPacketModeEnable = 0; + return 0; +#else + return -1; +#endif /* RFW_ENABLE == 1 */ +} + +void RFW_DeInit_TxLongPacket( void ) +{ +#if (RFW_LONGPACKET_ENABLE == 1 ) + /*long packet WA*/ + uint8_t reg = SUBGRF_ReadRegister( SUBGHZ_GPKTCTL1AR ); + SUBGRF_WriteRegister( SUBGHZ_GPKTCTL1AR, reg & ~0x02 ); /* clear infinite_sequence bit */ + SUBGRF_WriteRegister( SUBGHZ_GRTXPLDLEN, 0xFF ); /* RxTxPldLen: reset to 0xFF */ +#endif /* RFW_LONGPACKET_ENABLE == 1 */ +} + +void RFW_ReceivePayload( void ) +{ +#if (RFW_ENABLE == 1 ) + uint16_t PayloadLength = 0; + if( RFW_GetPacketLength( &PayloadLength ) == 0 ) + { + uint32_t timeout; + uint32_t packet_length = PayloadLength + RFWPacket.Init.CrcFieldSize; + /*record payload length*/ + RFWPacket.PayloadLength = PayloadLength; + /*record remaining payload length*/ + RFWPacket.LongPacketRemainingBytes = ( uint16_t ) packet_length; + /*record rx buffer offset*/ + RFWPacket.RadioBufferOffset = RFWPacket.Init.PayloadLengthFieldSize; + /*if decoded PayloadLength is longer than LongPacketMaxRxLength, reject packet*/ + if( PayloadLength > RFWPacket.Init.LongPacketMaxRxLength ) + { + SUBGRF_SetStandby( STDBY_RC ); + RFWPacket.Init.RadioEvents->RxError( ); + return; + } + if( packet_length < LONGPACKET_CHUNK_LENGTH_BYTES ) + { + /* all in one chunks*/ + /* calculate time to end of packet*/ + timeout = DIVC( ( packet_length ) * 8 * 1000, RFWPacket.BitRate ) + 2; + /**/ + /* start timer at the end of the packet*/ + RFW_MW_LOG( TS_ON, VLEVEL_M, "end packet in %dms\r\n", timeout ); + + } + else if( packet_length < ( 3 * LONGPACKET_CHUNK_LENGTH_BYTES / 2 ) ) + { + /* packet contained in 2 chunks*/ + /* make sure that crc not cut in chunk*/ + timeout = DIVR( ( packet_length * 8 * 1000 ) / 2, RFWPacket.BitRate ); + } + else + { + /* packet contained in multiple chunk*/ + /* program radio timer for first chunk*/ + timeout = DIVR( LONGPACKET_CHUNK_LENGTH_BYTES * 8 * 1000, RFWPacket.BitRate ); + } + TimerSetValue( &RFWPacket.Timer, timeout ); + TimerStart( &RFWPacket.Timer ); + } + else + { + /*timeout*/ + SUBGRF_SetStandby( STDBY_RC ); + RFWPacket.Init.RadioEvents->RxTimeout( ); + } +#endif /* RFW_ENABLE == 1 */ +} + +void RFW_SetRadioModem( RadioModems_t Modem ) +{ +#if (RFW_ENABLE == 1 ) + RFWPacket.Init.Modem = Modem; +#endif /* RFW_ENABLE == 1 */ +} + +/* Private Functions Definition -----------------------------------------------*/ +#if (RFW_LONGPACKET_ENABLE == 1 ) +static void RFW_TransmitLongPacket_NewTxChunkTimerEvent( void *param ) +{ + RFW_TRANSMIT_LONGPACKET_TX_CHUNK_PROCESS(); +} + +static void RFW_TransmitLongPacket_TxChunkProcess( void ) +{ + uint8_t *app_chunk_buffer_ptr = NULL; + uint8_t chunk_size = 0; + uint8_t crc_result[2] = {0}; + uint8_t crc_size; + uint32_t timeout;/*timeout for next chunk*/ + /*records how much has been sent*/ + uint8_t read_ptr = SUBGRF_ReadRegister( SUBGHZ_TXADRPTR ); /*radio has transmitted up to read_ptr*/ + uint8_t write_ptr = SUBGRF_ReadRegister( SUBGHZ_GRTXPLDLEN ); /*from read_ptr to write_ptr still to be transmitted*/ + /*calculates how much bytes were sent since previous radio loading*/ + uint8_t bytes_sent = read_ptr - RFWPacket.RadioBufferOffset; + /*bytes already loaded in the radio to send*/ + uint8_t bytes_loaded = write_ptr - read_ptr; + + /* Update offset tx, intentional wrap around*/ + RFWPacket.RadioBufferOffset += bytes_sent; + /*record payload remaining bytes to send*/ + RFWPacket.LongPacketRemainingBytes -= bytes_sent; + RFW_MW_LOG( TS_ON, VLEVEL_M, "read_ptr=%d, write_ptr=%d, bytes_sent=%d, bytes_loaded=%d,remaining to send=%d\r\n", + read_ptr, write_ptr, bytes_sent, bytes_loaded, RFWPacket.LongPacketRemainingBytes ); + if( RFWPacket.LongPacketRemainingBytes > 256 ) + { + /*get next chunk */ + /*make sure that at least full CrcFieldSize will be loaded for the last chunk*/ + if( RFWPacket.LongPacketRemainingBytes > 256 + RFWPacket.Init.CrcFieldSize ) + { + chunk_size = bytes_sent; + } + else + { + chunk_size = bytes_sent - RFWPacket.Init.CrcFieldSize; + } + /*no crc since it is not the last chunk*/ + crc_size = 0; + /*calculate timeout for next chunk*/ + timeout = DIVR( chunk_size * 8 * 1000, RFWPacket.BitRate ); + + TimerSetValue( &RFWPacket.Timer, timeout ); + TimerStart( &RFWPacket.Timer ); + } + else + { + /*last chunk to send*/ + + if( RFWPacket.LongPacketRemainingBytes > bytes_loaded ) + { + chunk_size = RFWPacket.LongPacketRemainingBytes - bytes_loaded; + } + else/* nothing to load anymore*/ + { + chunk_size = RFWPacket.Init.CrcFieldSize; + } + /* crc, since it is the last chunk*/ + crc_size = RFWPacket.Init.CrcFieldSize; + /*no more bytes to send*/ + RFWPacket.LongPacketRemainingBytes = 0; + /*no need to program another timer, Tx done will complete the Tx process*/ + } + /*get new chunk from the app*/ + RFWPacket.TxLongPacketGetNextChunkCb( &app_chunk_buffer_ptr, chunk_size - crc_size ); + /* Copy app_chunk_buffer_ptr in ChunkBuffer Buffer*/ + RADIO_MEMCPY8( ChunkBuffer, app_chunk_buffer_ptr, chunk_size - crc_size ); + if( RFWPacket.Init.CrcEnable == 1 ) + { + /* Run the crc calculation on payload length and payload*/ + RFW_CrcRun( &RFWPacket, ChunkBuffer, chunk_size - crc_size, crc_result ); + /* Append the crc result after the payload (if last chunk)*/ + RADIO_MEMCPY8( &ChunkBuffer[chunk_size - crc_size], crc_result, crc_size ); + } + /* Run the whitening calculation on payload length, payload and crc*/ + RFW_WhiteRun( &RFWPacket, ChunkBuffer, chunk_size ); + /*write next chunk*/ + SUBGRF_WriteBuffer( write_ptr, ChunkBuffer, chunk_size ); + + /*update end ptr*/ + SUBGRF_WriteRegister( SUBGHZ_GRTXPLDLEN, ( uint8_t )( chunk_size + write_ptr ) ); + + RFW_MW_LOG( TS_ON, VLEVEL_M, "next chunk size=%d, new write ptr=%d\n\r", chunk_size + crc_size, + ( uint8_t )( chunk_size + crc_size + write_ptr ) ); +} +#endif /* RFW_LONGPACKET_ENABLE == 1 */ + +#if (RFW_ENABLE == 1 ) +static void RFW_WhiteInitState( RFwInit_t *Init, uint16_t WhiteSeed ) +{ + Init->WhiteSeed = WhiteSeed; +} + +static void RFW_WhiteSetState( RadioFw_t *RFWPacket ) +{ + RFWPacket->WhiteLfsrState = RFWPacket->Init.WhiteSeed; +} + +static void RFW_CrcInitState( RFwInit_t *Init, const uint16_t CrcPolynomial, const uint16_t CrcSeed, + const RADIO_FSK_CrcTypes_t CrcType ) +{ + Init->CrcPolynomial = CrcPolynomial; + Init->CrcSeed = CrcSeed; + Init->CrcType = CrcType; +} + +static void RFW_CrcSetState( RadioFw_t *RFWPacket ) +{ + RFWPacket->CrcLfsrState = RFWPacket->Init.CrcSeed; +} + +static void RFW_WhiteRun( RadioFw_t *RFWPacket, uint8_t *Payload, uint32_t Size ) +{ + /*run the whitening algo on Size bytes*/ + uint16_t ibmwhite_state = RFWPacket->WhiteLfsrState; + for( int32_t i = 0; i < Size; i++ ) + { + Payload[i] ^= ibmwhite_state & 0xFF; + for( int32_t j = 0; j < 8; j++ ) + { + uint8_t msb = ( ( ibmwhite_state >> 5 ) & 0x1 ) ^ ( ( ibmwhite_state >> 0 ) & 0x1 ); + ibmwhite_state = ( ( msb << 8 ) | ( ibmwhite_state >> 1 ) ); + } + } + RFWPacket->WhiteLfsrState = ibmwhite_state; +} + +static int32_t RFW_CrcRun( RadioFw_t *const RFWPacket, const uint8_t *Payload, const uint32_t Size, + uint8_t CrcResult[2] ) +{ + int32_t status = 0; + int32_t i = 0; + uint16_t polynomial = RFWPacket->Init.CrcPolynomial; + /* Restore state from previous chunk*/ + uint16_t crc = RFWPacket->CrcLfsrState; + for( i = 0; i < Size; i++ ) + { + crc = RFW_CrcRun1Byte( crc, Payload[i], polynomial ); + } + /*Save state for next chunk*/ + RFWPacket->CrcLfsrState = crc; + + if( RFWPacket->Init.CrcType == RADIO_FSK_CRC_2_BYTES_IBM ) + { + CrcResult[1] = crc & 0xFF; + CrcResult[0] = crc >> 8; + } + else + { + crc = ~crc ; + CrcResult[1] = crc & 0xFF; + CrcResult[0] = crc >> 8; + } + return status; +} + +uint16_t RFW_CrcRun1Byte( uint16_t Crc, uint8_t DataByte, uint16_t Polynomial ) +{ + uint8_t i; + for( i = 0; i < 8; i++ ) + { + if( ( ( ( Crc & 0x8000 ) >> 8 ) ^ ( DataByte & 0x80 ) ) != 0 ) + { + Crc <<= 1; + Crc ^= Polynomial; + } + else + { + Crc <<= 1; + } + DataByte <<= 1; + } + return Crc; +} + +static int32_t RFW_PollRxBytes( uint32_t bytes ) +{ + uint32_t now = TimerGetCurrentTime( ); + uint8_t reg_buff_ptr_ref = SUBGRF_ReadRegister( SUBGHZ_RXADRPTR ); + uint8_t reg_buff_ptr = reg_buff_ptr_ref; + uint32_t timeout = DIVC( bytes * 8 * 1000, RFWPacket.BitRate ); + /* Wait that packet length is received */ + while( ( reg_buff_ptr - reg_buff_ptr_ref ) < bytes ) + { + /*reading rx address pointer*/ + reg_buff_ptr = SUBGRF_ReadRegister( SUBGHZ_RXADRPTR ); + if( TimerGetElapsedTime( now ) > timeout ) + { + /*timeout*/ + return -1; + } + } + return 0; +} + +static int32_t RFW_GetPacketLength( uint16_t *PayloadLength ) +{ + if( 0UL != RFW_PollRxBytes( RFWPacket.Init.PayloadLengthFieldSize ) ) + { + return -1; + } + /* Get buffer from Radio*/ + SUBGRF_ReadBuffer( 0, ChunkBuffer, RFWPacket.Init.PayloadLengthFieldSize ); + /* De-whiten packet length*/ + RFW_WhiteRun( &RFWPacket, ChunkBuffer, RFWPacket.Init.PayloadLengthFieldSize ); + /*do crc 1st calculation packetLengthField and store intermediate result */ + if( RFWPacket.Init.CrcEnable == 1 ) + { + /*run Crc algo on payloadLengthField*/ + uint8_t crc_dummy[2]; + RFW_CrcRun( &RFWPacket, ChunkBuffer, RFWPacket.Init.PayloadLengthFieldSize, crc_dummy ); + } + if( RFWPacket.Init.PayloadLengthFieldSize == 1 ) + { + *PayloadLength = ( uint16_t ) ChunkBuffer[0]; + } + else + { + /*packet length is 2 bytes*/ + *PayloadLength = ( ( ( uint16_t ) ChunkBuffer[0] ) << 8 ) | ChunkBuffer[1]; + } + RFW_MW_LOG( TS_ON, VLEVEL_M, "PayloadLength=%d,\r\n", *PayloadLength ); + return 0; +} + +static void RFW_GetPayloadTimerEvent( void *context ) +{ + RFW_GET_PAYLOAD_PROCESS(); +} + +static void RFW_GetPayloadProcess( void ) +{ + /*long packet mode*/ + uint8_t read_ptr = SUBGRF_ReadRegister( SUBGHZ_RXADRPTR ); + uint8_t size = read_ptr - RFWPacket.RadioBufferOffset; + uint32_t Timeout; + /*check remaining size*/ + if( RFWPacket.LongPacketRemainingBytes > size ) + { + /* update LongPacketRemainingBytes*/ + RFWPacket.LongPacketRemainingBytes -= size; + /*intermediate chunk*/ + RFW_MW_LOG( TS_ON, VLEVEL_M, "RxTxPldLen=0x%02X,\r\n", SUBGRF_ReadRegister( SUBGHZ_GRTXPLDLEN ) ); + RFW_MW_LOG( TS_ON, VLEVEL_M, "RxAddrPtr=0x%02X,\r\n", read_ptr ); + RFW_MW_LOG( TS_ON, VLEVEL_M, "offset= %d, size=%d, remaining=%d,\r\n", RFWPacket.RadioBufferOffset, size, + RFWPacket.LongPacketRemainingBytes ); + /*update pld length so that not reached*/ + SUBGRF_WriteRegister( SUBGHZ_GRTXPLDLEN, read_ptr - 1 ); + /* read data from radio*/ + SUBGRF_ReadBuffer( RFWPacket.RadioBufferOffset, ChunkBuffer, size ); + /* update buffer Offset, with intentional wrap around*/ + RFWPacket.RadioBufferOffset += size; + /*Run the de-whitening on current chunk*/ + RFW_WhiteRun( &RFWPacket, ChunkBuffer, size ); + if( RFWPacket.Init.CrcEnable == 1 ) + { + /*run Crc algo on partial chunk*/ + uint8_t crc_dummy[2]; + RFW_CrcRun( &RFWPacket, ChunkBuffer, size, crc_dummy ); + } + + if( RFWPacket.LongPacketModeEnable == 1 ) + { + /*report rx data chunk to application*/ + RFWPacket.RxLongPacketStoreChunkCb( ChunkBuffer, size ); + } + else + { + if( RFWPacket.RxPayloadOffset += size < RADIO_BUF_SIZE ) + { + RADIO_MEMCPY8( &RxBuffer[RFWPacket.RxPayloadOffset], ChunkBuffer, size ); + RFWPacket.RxPayloadOffset += size; + } + else + { + /*stop the radio*/ + SUBGRF_SetStandby( STDBY_RC ); + /*report CRC error*/ + RFWPacket.Init.RadioEvents->RxError( ); + return; + } + } + /*calculate next timer timeout*/ + if( RFWPacket.LongPacketRemainingBytes < LONGPACKET_CHUNK_LENGTH_BYTES ) + { + /*for the next and last chunk DIVC +1 to make sure crc is received.*/ + Timeout = DIVC( ( RFWPacket.LongPacketRemainingBytes ) * 8 * 1000, RFWPacket.BitRate ) + 2; + } + else if( RFWPacket.LongPacketRemainingBytes < ( 3 * LONGPACKET_CHUNK_LENGTH_BYTES ) / 2 ) + { + /*this is to make sure that last chunk will always be greater than LONGPACKET_CHUNK_LENGTH_BYTES/2 */ + Timeout = DIVR( ( RFWPacket.LongPacketRemainingBytes / 2 ) * 8 * 1000, RFWPacket.BitRate ); + } + else + { + /*size value is close to LONGPACKET_CHUNK_LENGTH_BYTES with +/- errors compensated in closed loop here*/ + Timeout = DIVR( ( LONGPACKET_CHUNK_LENGTH_BYTES ) * 8 * 1000, RFWPacket.BitRate ); + } + TimerSetValue( &RFWPacket.Timer, Timeout ); + TimerStart( &RFWPacket.Timer ); + } + else + { + if( RFWPacket.LongPacketRemainingBytes < RFWPacket.Init.CrcFieldSize ) + { + /* force LongPacketRemainingBytes to CrcFieldSize: this should never happen*/ + RFWPacket.LongPacketRemainingBytes = RFWPacket.Init.CrcFieldSize; + } + /*last chunk*/ + RFW_MW_LOG( TS_ON, VLEVEL_M, "LastChunk. offset= %d, size=%d, remaining=%d,\r\n", RFWPacket.RadioBufferOffset, size, + RFWPacket.LongPacketRemainingBytes ); + size = RFWPacket.LongPacketRemainingBytes; + /* update LongPacketRemainingBytes*/ + RFWPacket.LongPacketRemainingBytes = 0; + /*Process last chunk*/ + RFW_GetPayload( RFWPacket.RadioBufferOffset, size ); + } +} + +static void RFW_GetPayload( uint8_t Offset, uint8_t Length ) +{ + uint8_t crc_result[2]; + /*stop the radio*/ + SUBGRF_SetStandby( STDBY_RC ); + /*read data buffer*/ + SUBGRF_ReadBuffer( Offset, ChunkBuffer, Length ); + /*Run the de-whitening on all packet*/ + RFW_WhiteRun( &RFWPacket, ChunkBuffer, Length ); + if( RFWPacket.Init.CrcEnable == 1 ) + { + RFW_CrcRun( &RFWPacket, ChunkBuffer, Length - RFWPacket.Init.CrcFieldSize, crc_result ); + } + if( RFWPacket.LongPacketModeEnable == 1 ) + { + /*report rx data chunk to application*/ + + RFWPacket.RxLongPacketStoreChunkCb( ChunkBuffer, Length - RFWPacket.Init.CrcFieldSize ); + } + else + { + if( RFWPacket.RxPayloadOffset + Length - RFWPacket.Init.CrcFieldSize < RADIO_BUF_SIZE ) + { + RADIO_MEMCPY8( &RxBuffer[RFWPacket.RxPayloadOffset], ChunkBuffer, Length - RFWPacket.Init.CrcFieldSize ); + RFWPacket.RxPayloadOffset += Length - RFWPacket.Init.CrcFieldSize; + } + else + { + /*report CRC error*/ + RFWPacket.Init.RadioEvents->RxError( ); + return; + } + } + TimerStop( RFWPacket.RxTimeoutTimer ); + /* CRC check*/ + RFW_MW_LOG( TS_ON, VLEVEL_M, "crc_result= 0x%02X%02X, crc_payload=0x%02X%02X\r\n", crc_result[0], crc_result[1], + ChunkBuffer[Length - 2], ChunkBuffer[Length - 1] ); + if( ( ( crc_result[0] == ChunkBuffer[Length - 2] ) && + ( crc_result[1] == ChunkBuffer[Length - 1] ) ) || + ( RFWPacket.Init.CrcEnable == 0 ) ) + { + /*read Rssi sampled at Sync*/ + uint8_t rssi_sync = SUBGRF_ReadRegister( 0x06CA ); + /* Get Carrier Frequency Offset*/ + int32_t cfo; + SUBGRF_GetCFO( RFWPacket.BitRate, &cfo ); + /*ChunkBuffer[1] to remove packet Length*/ + RFWPacket.Init.RadioEvents->RxDone( RxBuffer, + RFWPacket.RxPayloadOffset, + -( rssi_sync >> 1 ), + ( int8_t ) DIVR( cfo, 1000 ) ); + } + else + { + /*report CRC error*/ + RFWPacket.Init.RadioEvents->RxError( ); + } + DBG_GPIO_RADIO_RX( RST ); +} +#endif /* RFW_ENABLE == 1 */ diff --git a/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.h b/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.h new file mode 100644 index 0000000..4de4cb6 --- /dev/null +++ b/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.h @@ -0,0 +1,154 @@ +/** + ****************************************************************************** + * @file radio_fw.h + * @author MCD Application Team + * @brief Extends radio capabilities (whitening, long packet) + ****************************************************************************** + * @attention + * + * Copyright (c) 2020(-2021) STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __RADIO_FW_H__ +#define __RADIO_FW_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "radio_def.h" +#include "radio_ex.h" + +/* Exported types ------------------------------------------------------------*/ + +/*reserved for SubGHz_Phy internal MW communication*/ +typedef enum +{ + CONFIG_RX = 0, + CONFIG_TX, +} ConfigGenericRTx_t; + +typedef struct +{ + TxConfigGeneric_t *TxConfig; + RxConfigGeneric_t *RxConfig; + ConfigGenericRTx_t rtx; +} ConfigGeneric_t; + +/* Exported constants --------------------------------------------------------*/ +/* External variables --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions prototypes ---------------------------------------------*/ + +/*! + * @brief Initialise the RFW module and enables custom whitening, optionally long packet feature + * + * @param [in] config rx or tx config from the application + * @param [in] RadioEvents from the radio + * @param [in] TimeoutTimerEvent Timer for Rx or Tx timeout event + * @return 0 when no parameters error, -1 otherwise + */ +int32_t RFW_Init( ConfigGeneric_t *config, RadioEvents_t *RadioEvents, TimerEvent_t *TimeoutTimerEvent ); + +/*! + * @brief Return whether the RFW module is enabled + * + * @return 0 when not initialised, -1 otherwise + */ +uint8_t RFW_Is_Init( void ); + +/*! + * @brief Return whether the RFW module long packet is enabled + * + * @return 0 when not initialised, -1 otherwise + */ +uint8_t RFW_Is_LongPacketModeEnabled( void ); + +/*! + * @brief Return whether the RFW module long packet is enabled + * + * @param [in] Modem set in the radio + */ +void RFW_SetRadioModem( RadioModems_t Modem ); + +/*! + * @brief DeInitialise the RFW module and enable custom whitening and optionally long packet feature + * + */ +void RFW_DeInit( void ); + +/*! + * @brief DeInitialise the TxLongPacket + * + */ +void RFW_DeInit_TxLongPacket( void ); + +/*! + * @brief Set antenna switch output to be used in Tx + * + * @param [in] AntSwitch RFO_LP or FRO_HP + * + */ +void RFW_SetAntSwitch( uint8_t AntSwitch ); + +/*! + * @brief Initialise reception for IBM whitening case + * + * @return 0 when RFW_ENABLE exists, -1 otherwise + */ +int32_t RFW_ReceiveInit( void ); + +/*! + * @brief Initialise transmission for IBM whitening case + * + * @param [in,out] inOutBuffer pointer of exchange buffer to send or receive data + * @param [in] size input buffer size + * @param [out] outSize output buffer size + * + */ +int32_t RFW_TransmitInit( uint8_t *inOutBuffer, uint8_t size, uint8_t *outSize ); + +/*! + * @brief Starts receiving payload. Called at Rx Sync IRQ + * + */ +void RFW_ReceivePayload( void ); + +/*! + * @brief Starts transmitting long Packet, note packet length may be on 1 bytes depending on config + * + * @param [in] payload_size total payload size to be sent + * @param [in] timeout Reception timeout [ms] + * @param [in] TxLongPacketGetNextChunkCb callback to be implemented on user side to feed partial chunk + * buffer: source buffer allocated by the app + * size: size in bytes to feed. User to implement the offset based on previous chunk request + * @return 0 when no parameters error, -1 otherwise + */ +int32_t RFW_TransmitLongPacket( uint16_t payload_size, uint32_t timeout, void ( *TxLongPacketGetNextChunkCb )( uint8_t **buffer, uint8_t buffer_size ) ); + +/*! + * @brief Starts receiving long Packet, packet maybe short + * + * @param [in] boosted_mode boosted_mode: 0 normal Rx, 1:improved sensitivity + * @param [in] timeout Reception timeout [ms] + * @param [in] RxLongStorePacketChunkCb callback to be implemented on user side to record partial chunk in the application + * buffer: source buffer allocated in the radio driver + * size: size in bytes to record + * @return 0 when no parameters error, -1 otherwise + */ +int32_t RFW_ReceiveLongPacket( uint8_t boosted_mode, uint32_t timeout, void ( *RxLongStorePacketChunkCb )( uint8_t *buffer, uint8_t chunk_size ) ); + +#ifdef __cplusplus +} +#endif + +#endif /*__RADIO_FW_H__*/ diff --git a/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/subghz_phy_version.h b/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/subghz_phy_version.h new file mode 100644 index 0000000..c369ed7 --- /dev/null +++ b/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/subghz_phy_version.h @@ -0,0 +1,53 @@ +/****************************************************************************** + * @file subghz_phy_version.h + * @author MCD Application Team + * @brief defines the radio driver version + ****************************************************************************** + * @attention + * + * Copyright (c) 2020(-2021) STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ + +#ifndef __SUBGHZ_PHY_VERSION_H__ +#define __SUBGHZ_PHY_VERSION_H__ + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* __SUBGHZ_PHY_TYPE: 0x01 STM32WL + 0x61 SX126X + 0x72 SX1272 + 0x76 SX1276 */ + +#define SUBGHZ_PHY_VERSION_MAIN (0x01U) /*!< [31:24] main version */ +#define SUBGHZ_PHY_VERSION_SUB1 (0x03U) /*!< [23:16] sub1 version */ +#define SUBGHZ_PHY_VERSION_SUB2 (0x01U) /*!< [15:8] sub2 version */ +#define SUBGHZ_PHY_TYPE (0x01U) /*!< [7:0] type version */ +#define SUBGHZ_PHY_VERSION ((SUBGHZ_PHY_VERSION_MAIN << 24) \ + |(SUBGHZ_PHY_VERSION_SUB1 << 16) \ + |(SUBGHZ_PHY_VERSION_SUB2 << 8) \ + |(SUBGHZ_PHY_TYPE)) + +/* Exported types ------------------------------------------------------------*/ +/* External variables --------------------------------------------------------*/ +/* Exported macros -----------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +#ifdef __cplusplus +} +#endif + +#endif /*__SUBGHZ_PHY_VERSION_H__*/ diff --git a/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/wl_lr_fhss.c b/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/wl_lr_fhss.c new file mode 100644 index 0000000..3bc785a --- /dev/null +++ b/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/wl_lr_fhss.c @@ -0,0 +1,425 @@ +/*! + * @file wl_lr_fhss.c + * + * @brief STM32WL LR-FHSS driver implementation + * + * The Clear BSD License + * Copyright Semtech Corporation 2021. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted (subject to the limitations in the disclaimer + * below) provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of the Semtech corporation nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY + * THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT + * NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL SEMTECH CORPORATION BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * ----------------------------------------------------------------------------- + * --- DEPENDENCIES ------------------------------------------------------------ + */ +#include "wl_lr_fhss.h" +#include "lr_fhss_mac.h" + +/* + * ----------------------------------------------------------------------------- + * --- PRIVATE MACROS----------------------------------------------------------- + */ + +/* + * ----------------------------------------------------------------------------- + * --- PRIVATE CONSTANTS ------------------------------------------------------- + */ + +/* \cond */ + +#define WL_SET_MODULATION_PARAMS ( 0x8B ) +#define WL_SET_PKT_PARAMS ( 0x8C ) + +#define WL_LR_FHSS_DISABLE_HOPPING ( 0 ) +#define WL_LR_FHSS_ENABLE_HOPPING ( 1 ) + +#define WL_LR_FHSS_HOP_TABLE_SIZE ( 16 ) +#define WL_LR_FHSS_HOP_ENTRY_SIZE ( 6 ) + +#define WL_LR_FHSS_GRID_3906_HZ_PLL_STEPS ( 4096 ) +#define WL_LR_FHSS_GRID_25391_HZ_PLL_STEPS ( 26624 ) + +#define WL_LR_FHSS_GRID_INDEX_TO_PLL_STEPS ( 512 ) + +/* \endcond */ + +/* + * ----------------------------------------------------------------------------- + * --- PRIVATE TYPES ----------------------------------------------------------- + */ + +/* + * ----------------------------------------------------------------------------- + * --- PRIVATE VARIABLES ------------------------------------------------------- + */ + +/* + * ----------------------------------------------------------------------------- + * --- PRIVATE FUNCTION DECLARATIONS ------------------------------------------- + */ + +/*! + * @brief Configure the radio to perform frequency hopping + * + * @param [in] context Chip implementation context + * @param [in] nb_bytes Total number of bytes + * @param [in] nb_hops Total number of hops + * + * @returns Operation status + */ +radio_status_t wl_lr_fhss_write_hop_config( const uint8_t nb_bytes, const uint8_t nb_hops ); + +/*! + * @brief Write a hop frequency/duration pair to the radio hop table + * + * @param [in] context Chip implementation context + * @param [in] index Index to chip hop table + * @param [in] nb_symbols Hop duration in symbols + * @param [in] freq_in_pll_steps Hop frequency, in PLL steps + * + * @returns Operation status + */ +radio_status_t wl_lr_fhss_write_hop( const uint8_t index, const uint16_t nb_symbols, + const uint32_t freq_in_pll_steps ); + +/*! + * @brief Get Frequency, in PLL steps, of the next hop + * + * @param [in] params stm32wl LR-FHSS parameter structure + * @param [out] state stm32wl LR-FHSS state structure that will be initialized by this function + * + * @returns Frequency, in PLL steps, of the next hop + */ +uint32_t wl_lr_fhss_get_next_freq_in_pll_steps( const wl_lr_fhss_params_t *params, + wl_lr_fhss_state_t *state ); + +/*! + * @brief Get grid frequency, in PLL steps + * + * @param [in] params stm32wl LR-FHSS parameter structure + * + * @returns Grid frequency, in PLL steps + */ +static inline unsigned int wl_lr_fhss_get_grid_in_pll_steps( const wl_lr_fhss_params_t *params ); + +/* + * ----------------------------------------------------------------------------- + * --- PUBLIC FUNCTIONS DEFINITION --------------------------------------------- + */ + +radio_status_t wl_lr_fhss_init( const wl_lr_fhss_params_t *params ) +{ + radio_status_t status = RADIO_STATUS_OK; + SUBGRF_SetPacketType( PACKET_TYPE_LR_FHSS ); + + uint8_t pkt_params_buffer[8] = {0}; + uint8_t mod_params_buffer[] = {32, 0, 0, MOD_SHAPING_G_BT_1, 0, 0, 0, 0}; + + SUBGRF_WriteCommand( RADIO_SET_PACKETPARAMS, pkt_params_buffer, sizeof( pkt_params_buffer ) ); + + SUBGRF_WriteCommand( RADIO_SET_MODULATIONPARAMS, mod_params_buffer, sizeof( mod_params_buffer ) ); + + SUBGRF_SetBufferBaseAddress( 0x00, 0x00 ); + return status; +} + +radio_status_t wl_lr_fhss_process_parameters( const wl_lr_fhss_params_t *params, uint16_t hop_sequence_id, + uint16_t payload_length, wl_lr_fhss_state_t *state ) +{ + lr_fhss_process_parameters( ¶ms->lr_fhss_params, payload_length, &state->digest ); + + if( state->digest.nb_bytes > LR_FHSS_MAX_PHY_PAYLOAD_BYTES ) + { + return RADIO_STATUS_UNKNOWN_VALUE; + } + if( params->lr_fhss_params.grid == LR_FHSS_V1_GRID_25391_HZ ) + { + if( params->device_offset > 25 || params->device_offset < -26 ) + { + return RADIO_STATUS_UNKNOWN_VALUE; + } + if( params->lr_fhss_params.bw < LR_FHSS_V1_BW_722656_HZ ) + { + return RADIO_STATUS_UNKNOWN_VALUE; + } + } + if( params->lr_fhss_params.grid == LR_FHSS_V1_GRID_3906_HZ ) + { + if( params->device_offset > 3 || params->device_offset < -4 ) + { + return RADIO_STATUS_UNKNOWN_VALUE; + } + } + + // Initialize hop index and params + state->current_hop = 0; + radio_status_t status = + lr_fhss_get_hop_params( ¶ms->lr_fhss_params, &state->hop_params, &state->lfsr_state, hop_sequence_id ); + if( status != RADIO_STATUS_OK ) + { + return ( radio_status_t ) status; + } + + // Skip the hop frequencies inside the set [0, 4 - header_count): + if( params->lr_fhss_params.enable_hopping != 0 ) + { + for( int i = 0; i < 4 - params->lr_fhss_params.header_count; ++i ) + { + lr_fhss_get_next_state( &state->lfsr_state, &state->hop_params ); + } + } + + state->next_freq_in_pll_steps = wl_lr_fhss_get_next_freq_in_pll_steps( params, state ); + return RADIO_STATUS_OK; +} + +radio_status_t wl_lr_fhss_write_hop_sequence_head( const wl_lr_fhss_params_t *params, + wl_lr_fhss_state_t *state ) +{ + radio_status_t status = wl_lr_fhss_write_hop_config( state->digest.nb_bytes, state->digest.nb_hops ); + if( status != RADIO_STATUS_OK ) + { + return status; + } + + const uint16_t pulse_shape_compensation = 1; + + if( params->lr_fhss_params.enable_hopping == 0 ) + { + // (LR_FHSS_HEADER_BITS + pulse_shape_compensation) symbols on first sync_word, LR_FHSS_HEADER_BITS on next + // sync_words, LR_FHSS_BLOCK_BITS on payload + const uint16_t nb_symbols = state->digest.nb_bits + pulse_shape_compensation; + + status = wl_lr_fhss_write_hop( state->current_hop, nb_symbols, state->next_freq_in_pll_steps ); + if( status != RADIO_STATUS_OK ) + { + return status; + } + state->current_hop++; + state->digest.nb_bits = 0; + } + else + { + // fill at most WL_LR_FHSS_HOP_TABLE_SIZE hops of the hardware hop table + uint8_t truncated_hops = state->digest.nb_hops; + if( truncated_hops > WL_LR_FHSS_HOP_TABLE_SIZE ) + { + truncated_hops = WL_LR_FHSS_HOP_TABLE_SIZE; + } + + while( state->current_hop < truncated_hops ) + { + uint16_t nb_symbols; + + // (LR_FHSS_HEADER_BITS + pulse_shape_compensation) symbols on first sync_word, LR_FHSS_HEADER_BITS on + // next sync_words, LR_FHSS_BLOCK_BITS on payload + if( state->current_hop >= params->lr_fhss_params.header_count ) + { + if( state->digest.nb_bits > LR_FHSS_BLOCK_BITS ) + { + nb_symbols = LR_FHSS_BLOCK_BITS; + } + else + { + nb_symbols = state->digest.nb_bits; + } + } + else if( state->current_hop > 0 ) + { + nb_symbols = LR_FHSS_HEADER_BITS; + } + else + { + nb_symbols = LR_FHSS_HEADER_BITS + pulse_shape_compensation; + } + + status = wl_lr_fhss_write_hop( state->current_hop, nb_symbols, state->next_freq_in_pll_steps ); + if( status != RADIO_STATUS_OK ) + { + return status; + } + + state->current_hop++; + state->digest.nb_bits -= nb_symbols; + + state->next_freq_in_pll_steps = wl_lr_fhss_get_next_freq_in_pll_steps( params, state ); + } + } + + return status; +} + +radio_status_t wl_lr_fhss_write_payload( const wl_lr_fhss_state_t *state, + const uint8_t *payload ) +{ + //return wl_write_buffer( context, 0x00, payload, state->digest.nb_bytes ); + SUBGRF_WriteBuffer( 0x00, ( uint8_t * ) payload, state->digest.nb_bytes ); + return RADIO_STATUS_OK; +} + +radio_status_t wl_lr_fhss_build_frame( const wl_lr_fhss_params_t *params, + wl_lr_fhss_state_t *state, uint16_t hop_sequence_id, + const uint8_t *payload, uint16_t payload_length, + uint32_t *first_frequency_in_pll_steps ) +{ + radio_status_t status = wl_lr_fhss_process_parameters( params, hop_sequence_id, payload_length, state ); + if( status != RADIO_STATUS_OK ) + { + return status; + } + + if( first_frequency_in_pll_steps != NULL ) + { + *first_frequency_in_pll_steps = state->next_freq_in_pll_steps; + } + + uint8_t tx_buffer[LR_FHSS_MAX_PHY_PAYLOAD_BYTES]; + lr_fhss_build_frame( ¶ms->lr_fhss_params, state->hop_params.hop_sequence_id, payload, payload_length, + tx_buffer ); + + status = wl_lr_fhss_write_payload( state, tx_buffer ); + if( status != RADIO_STATUS_OK ) + { + return status; + } + status = wl_lr_fhss_write_hop_sequence_head( params, state ); + + return status; +} + +radio_status_t wl_lr_fhss_handle_hop( const wl_lr_fhss_params_t *params, + wl_lr_fhss_state_t *state ) +{ + if( state->current_hop < state->digest.nb_hops ) + { + uint16_t nb_bits; + if( state->digest.nb_bits > LR_FHSS_BLOCK_BITS ) + { + nb_bits = LR_FHSS_BLOCK_BITS; + } + else + { + nb_bits = state->digest.nb_bits; + } + radio_status_t status = wl_lr_fhss_write_hop( state->current_hop % WL_LR_FHSS_HOP_TABLE_SIZE, + LR_FHSS_BLOCK_BITS, state->next_freq_in_pll_steps ); + if( status != RADIO_STATUS_OK ) + { + return status; + } + + state->current_hop++; + state->digest.nb_bits -= nb_bits; + state->next_freq_in_pll_steps = wl_lr_fhss_get_next_freq_in_pll_steps( params, state ); + } + return RADIO_STATUS_OK; +} + +radio_status_t wl_lr_fhss_handle_tx_done( const wl_lr_fhss_params_t *params, + wl_lr_fhss_state_t *state ) +{ + //const uint8_t ctrl = WL_LR_FHSS_DISABLE_HOPPING; + + //return wl_write_register( context, WL_LR_FHSS_REG_CTRL, &ctrl, 1 ); + SUBGRF_WriteRegister( WL_LR_FHSS_REG_CTRL, WL_LR_FHSS_DISABLE_HOPPING ); + return RADIO_STATUS_OK; +} + +/* + * ----------------------------------------------------------------------------- + * --- PRIVATE FUNCTIONS DEFINITION -------------------------------------------- + */ + +radio_status_t wl_lr_fhss_write_hop_config( const uint8_t nb_bytes, const uint8_t nb_hops ) +{ + uint8_t data[] = { WL_LR_FHSS_ENABLE_HOPPING, nb_bytes, nb_hops }; + + //return wl_write_register( context, WL_LR_FHSS_REG_CTRL, data, 3 ); + SUBGRF_WriteRegisters( WL_LR_FHSS_REG_CTRL, data, 3 ); + return RADIO_STATUS_OK; +} + +radio_status_t wl_lr_fhss_write_hop( const uint8_t index, const uint16_t nb_symbols, + const uint32_t freq_in_pll_steps ) +{ + if( index >= WL_LR_FHSS_HOP_TABLE_SIZE ) + { + return RADIO_STATUS_ERROR; + } + + uint8_t data[WL_LR_FHSS_HOP_ENTRY_SIZE] = + { + ( uint8_t )( nb_symbols >> 8 ), ( uint8_t ) nb_symbols, + ( uint8_t )( freq_in_pll_steps >> 24 ), ( uint8_t )( freq_in_pll_steps >> 16 ), + ( uint8_t )( freq_in_pll_steps >> 8 ), ( uint8_t ) freq_in_pll_steps, + }; + + //return wl_write_register( context, WL_LR_FHSS_REG_NUM_SYMBOLS_0 + ( WL_LR_FHSS_HOP_ENTRY_SIZE * index ), + // data, WL_LR_FHSS_HOP_ENTRY_SIZE ); + SUBGRF_WriteRegisters( WL_LR_FHSS_REG_NUM_SYMBOLS_0 + ( WL_LR_FHSS_HOP_ENTRY_SIZE * index ), + data, WL_LR_FHSS_HOP_ENTRY_SIZE ); + return RADIO_STATUS_OK; +} + +uint32_t wl_lr_fhss_get_next_freq_in_pll_steps( const wl_lr_fhss_params_t *params, + wl_lr_fhss_state_t *state ) +{ +#ifdef HOP_AT_CENTER_FREQ + const int16_t freq_table = 0; + uint32_t grid_offset = 0; +#else + const int16_t freq_table = + lr_fhss_get_next_freq_in_grid( &state->lfsr_state, &state->hop_params, ¶ms->lr_fhss_params ); + uint32_t nb_channel_in_grid = params->lr_fhss_params.grid ? 8 : 52; + uint32_t grid_offset = ( 1 + ( state->hop_params.n_grid % 2 ) ) * ( nb_channel_in_grid / 2 ); +#endif + + unsigned int grid_in_pll_steps = wl_lr_fhss_get_grid_in_pll_steps( params ); + uint32_t freq = params->center_freq_in_pll_steps - freq_table * grid_in_pll_steps - + ( params->device_offset + grid_offset ) * WL_LR_FHSS_GRID_INDEX_TO_PLL_STEPS; + +#ifndef HOP_AT_CENTER_FREQ + // Perform frequency correction for every other sync header + if( params->lr_fhss_params.enable_hopping && ( state->current_hop < params->lr_fhss_params.header_count ) ) + { + if( ( ( ( params->lr_fhss_params.header_count - state->current_hop ) % 2 ) == 0 ) ) + { + // OFFSET_SYNCWORD = 488.28125 / 2, and FREQ_STEP = 0.95367431640625, so + // OFFSET_SYNCWORD / FREQ_STEP = 256 + freq = freq + 256; + } + } +#endif + return freq; +} + +static inline unsigned int wl_lr_fhss_get_grid_in_pll_steps( const wl_lr_fhss_params_t *params ) +{ + return ( params->lr_fhss_params.grid == LR_FHSS_V1_GRID_3906_HZ ) ? WL_LR_FHSS_GRID_3906_HZ_PLL_STEPS : WL_LR_FHSS_GRID_25391_HZ_PLL_STEPS; +} + +/* --- EOF ------------------------------------------------------------------ */ diff --git a/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/wl_lr_fhss.h b/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/wl_lr_fhss.h new file mode 100644 index 0000000..d63fa98 --- /dev/null +++ b/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/wl_lr_fhss.h @@ -0,0 +1,238 @@ +/*! + * @file wl_lr_fhss.h + * + * @brief STM32WL LR-FHSS driver module API (internal to SubGHz_Phy middleware) + * + * The Clear BSD License + * Copyright Semtech Corporation 2021. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted (subject to the limitations in the disclaimer + * below) provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of the Semtech corporation nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY + * THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT + * NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL SEMTECH CORPORATION BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef WL_LR_FHSS_H__ +#define WL_LR_FHSS_H__ + +/* + * ----------------------------------------------------------------------------- + * --- DEPENDENCIES ------------------------------------------------------------ + */ + +#include +#include "radio_driver.h" +#include "lr_fhss_mac.h" + +/* + * ----------------------------------------------------------------------------- + * --- PUBLIC MACROS ----------------------------------------------------------- + */ + +/* + * ----------------------------------------------------------------------------- + * --- PUBLIC CONSTANTS -------------------------------------------------------- + */ + +#define WL_LR_FHSS_REG_CTRL ( 0x0385 ) +#define WL_LR_FHSS_REG_PACKET_LEN ( 0x0386 ) +#define WL_LR_FHSS_REG_NUM_HOPS ( 0x0387 ) +#define WL_LR_FHSS_REG_NUM_SYMBOLS_0 ( 0x0388 ) +#define WL_LR_FHSS_REG_FREQ_0 ( 0x038A ) + +/* + * ----------------------------------------------------------------------------- + * --- PUBLIC TYPES ------------------------------------------------------------ + */ + +/*! + * @brief STM32WL LR-FHSS LR-FHSS parameter definition + */ +typedef struct wl_lr_fhss_params_s +{ + lr_fhss_v1_params_t lr_fhss_params; + uint32_t center_freq_in_pll_steps; /**< Center frequency in transceiver units */ + int8_t device_offset; //lr_fhss_params, payload_length ); +} + +/*! + * @brief Return the number of hop sequences available using the given parameters + * + * @param [in] params stm32wl LR-FHSS parameter structure + * + * @return Returns the number of valid hop sequences (512 or 384) + */ +static inline unsigned int wl_lr_fhss_get_hop_sequence_count( const wl_lr_fhss_params_t *params ) +{ + return lr_fhss_get_hop_sequence_count( ¶ms->lr_fhss_params ); +} + +#ifdef __cplusplus +} +#endif + +#endif // WL_LR_FHSS_H__ + +/* --- EOF ------------------------------------------------------------------ */ diff --git a/STM32CubeIDE/.cproject b/STM32CubeIDE/.cproject new file mode 100644 index 0000000..f722791 --- /dev/null +++ b/STM32CubeIDE/.cproject @@ -0,0 +1,192 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/STM32CubeIDE/.project b/STM32CubeIDE/.project new file mode 100644 index 0000000..07ad1bd --- /dev/null +++ b/STM32CubeIDE/.project @@ -0,0 +1,301 @@ + + + SubGHz_Phy_Per + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + com.st.stm32cube.ide.mcu.MCUProjectNature + org.eclipse.cdt.core.cnature + com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAev2ProjectNature + com.st.stm32cube.ide.mcu.MCUNonUnderRootProjectNature + com.st.stm32cube.ide.mcu.MCUCubeProjectNature + com.st.stm32cube.ide.mcu.MCUAdvancedStructureProjectNature + com.st.stm32cube.ide.mcu.MCUEndUserDisabledMultiCpuProjectNature + com.st.stm32cube.ide.mcu.MCUMultiCpuProjectNature + com.st.stm32cube.ide.mcu.MCURootProjectNature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + SubGHz_Phy_Per.ioc + 1 + PARENT-1-PROJECT_LOC/SubGHz_Phy_Per.ioc + + + Doc/readme.txt + 1 + PARENT-1-PROJECT_LOC/readme.txt + + + Utilities/stm32_adv_trace.c + 1 + PARENT-1-PROJECT_LOC/Utilities/trace/adv_trace/stm32_adv_trace.c + + + Utilities/stm32_lpm.c + 1 + PARENT-1-PROJECT_LOC/Utilities/lpm/tiny_lpm/stm32_lpm.c + + + Utilities/stm32_mem.c + 1 + PARENT-1-PROJECT_LOC/Utilities/misc/stm32_mem.c + + + Utilities/stm32_seq.c + 1 + PARENT-1-PROJECT_LOC/Utilities/sequencer/stm32_seq.c + + + Utilities/stm32_systime.c + 1 + PARENT-1-PROJECT_LOC/Utilities/misc/stm32_systime.c + + + Utilities/stm32_timer.c + 1 + PARENT-1-PROJECT_LOC/Utilities/timer/stm32_timer.c + + + Utilities/stm32_tiny_sscanf.c + 1 + PARENT-1-PROJECT_LOC/Utilities/misc/stm32_tiny_sscanf.c + + + Utilities/stm32_tiny_vsnprintf.c + 1 + PARENT-1-PROJECT_LOC/Utilities/misc/stm32_tiny_vsnprintf.c + + + Drivers/CMSIS/system_stm32wlxx.c + 1 + PARENT-1-PROJECT_LOC/Core/Src/system_stm32wlxx.c + + + Drivers/STM32WLxx_HAL_Driver/stm32wlxx_hal.c + 1 + PARENT-1-PROJECT_LOC/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c + + + Drivers/STM32WLxx_HAL_Driver/stm32wlxx_hal_cortex.c + 1 + PARENT-1-PROJECT_LOC/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.c + + + Drivers/STM32WLxx_HAL_Driver/stm32wlxx_hal_dma.c + 1 + PARENT-1-PROJECT_LOC/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.c + + + Drivers/STM32WLxx_HAL_Driver/stm32wlxx_hal_dma_ex.c + 1 + PARENT-1-PROJECT_LOC/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma_ex.c + + + Drivers/STM32WLxx_HAL_Driver/stm32wlxx_hal_exti.c + 1 + PARENT-1-PROJECT_LOC/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_exti.c + + + Drivers/STM32WLxx_HAL_Driver/stm32wlxx_hal_flash.c + 1 + PARENT-1-PROJECT_LOC/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash.c + + + Drivers/STM32WLxx_HAL_Driver/stm32wlxx_hal_flash_ex.c + 1 + PARENT-1-PROJECT_LOC/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c + + + Drivers/STM32WLxx_HAL_Driver/stm32wlxx_hal_gpio.c + 1 + PARENT-1-PROJECT_LOC/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_gpio.c + + + Drivers/STM32WLxx_HAL_Driver/stm32wlxx_hal_pwr.c + 1 + PARENT-1-PROJECT_LOC/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.c + + + Drivers/STM32WLxx_HAL_Driver/stm32wlxx_hal_pwr_ex.c + 1 + PARENT-1-PROJECT_LOC/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c + + + Drivers/STM32WLxx_HAL_Driver/stm32wlxx_hal_rcc.c + 1 + PARENT-1-PROJECT_LOC/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.c + + + Drivers/STM32WLxx_HAL_Driver/stm32wlxx_hal_rcc_ex.c + 1 + PARENT-1-PROJECT_LOC/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.c + + + Drivers/STM32WLxx_HAL_Driver/stm32wlxx_hal_rtc.c + 1 + PARENT-1-PROJECT_LOC/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.c + + + Drivers/STM32WLxx_HAL_Driver/stm32wlxx_hal_rtc_ex.c + 1 + PARENT-1-PROJECT_LOC/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c + + + Drivers/STM32WLxx_HAL_Driver/stm32wlxx_hal_subghz.c + 1 + PARENT-1-PROJECT_LOC/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c + + + Drivers/STM32WLxx_HAL_Driver/stm32wlxx_hal_tim.c + 1 + PARENT-1-PROJECT_LOC/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_tim.c + + + Drivers/STM32WLxx_HAL_Driver/stm32wlxx_hal_tim_ex.c + 1 + PARENT-1-PROJECT_LOC/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_tim_ex.c + + + Drivers/STM32WLxx_HAL_Driver/stm32wlxx_hal_uart.c + 1 + PARENT-1-PROJECT_LOC/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c + + + Drivers/STM32WLxx_HAL_Driver/stm32wlxx_hal_uart_ex.c + 1 + PARENT-1-PROJECT_LOC/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.c + + + Middlewares/SubGHz_Phy/lr_fhss_mac.c + 1 + PARENT-1-PROJECT_LOC/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.c + + + Middlewares/SubGHz_Phy/radio.c + 1 + PARENT-1-PROJECT_LOC/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c + + + Middlewares/SubGHz_Phy/radio_driver.c + 1 + PARENT-1-PROJECT_LOC/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c + + + Middlewares/SubGHz_Phy/radio_fw.c + 1 + PARENT-1-PROJECT_LOC/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.c + + + Middlewares/SubGHz_Phy/wl_lr_fhss.c + 1 + PARENT-1-PROJECT_LOC/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/wl_lr_fhss.c + + + Application/User/Core/dma.c + 1 + PARENT-1-PROJECT_LOC/Core/Src/dma.c + + + Application/User/Core/gpio.c + 1 + PARENT-1-PROJECT_LOC/Core/Src/gpio.c + + + Application/User/Core/main.c + 1 + PARENT-1-PROJECT_LOC/Core/Src/main.c + + + Application/User/Core/rtc.c + 1 + PARENT-1-PROJECT_LOC/Core/Src/rtc.c + + + Application/User/Core/stm32_lpm_if.c + 1 + PARENT-1-PROJECT_LOC/Core/Src/stm32_lpm_if.c + + + Application/User/Core/stm32wlxx_hal_msp.c + 1 + PARENT-1-PROJECT_LOC/Core/Src/stm32wlxx_hal_msp.c + + + Application/User/Core/stm32wlxx_it.c + 1 + PARENT-1-PROJECT_LOC/Core/Src/stm32wlxx_it.c + + + Application/User/Core/subghz.c + 1 + PARENT-1-PROJECT_LOC/Core/Src/subghz.c + + + Application/User/Core/sys_app.c + 1 + PARENT-1-PROJECT_LOC/Core/Src/sys_app.c + + + Application/User/Core/sys_debug.c + 1 + PARENT-1-PROJECT_LOC/Core/Src/sys_debug.c + + + Application/User/Core/timer_if.c + 1 + PARENT-1-PROJECT_LOC/Core/Src/timer_if.c + + + Application/User/Core/usart.c + 1 + PARENT-1-PROJECT_LOC/Core/Src/usart.c + + + Application/User/Core/usart_if.c + 1 + PARENT-1-PROJECT_LOC/Core/Src/usart_if.c + + + Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo.c + 1 + PARENT-1-PROJECT_LOC/Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo.c + + + Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo_radio.c + 1 + PARENT-1-PROJECT_LOC/Drivers/BSP/STM32WLxx_Nucleo/stm32wlxx_nucleo_radio.c + + + Application/User/SubGHz_Phy/App/app_subghz_phy.c + 1 + PARENT-1-PROJECT_LOC/SubGHz_Phy/App/app_subghz_phy.c + + + Application/User/SubGHz_Phy/App/subghz_phy_app.c + 1 + PARENT-1-PROJECT_LOC/SubGHz_Phy/App/subghz_phy_app.c + + + Application/User/SubGHz_Phy/Target/radio_board_if.c + 1 + PARENT-1-PROJECT_LOC/SubGHz_Phy/Target/radio_board_if.c + + + diff --git a/STM32CubeIDE/Application/User/Core/syscalls.c b/STM32CubeIDE/Application/User/Core/syscalls.c new file mode 100644 index 0000000..2b47f84 --- /dev/null +++ b/STM32CubeIDE/Application/User/Core/syscalls.c @@ -0,0 +1,176 @@ +/** + ****************************************************************************** + * @file syscalls.c + * @author Auto-generated by STM32CubeIDE + * @brief STM32CubeIDE Minimal System calls file + * + * For more information about which c-functions + * need which of these lowlevel functions + * please consult the Newlib libc-manual + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes */ +#include +#include +#include +#include +#include +#include +#include +#include + + +/* Variables */ +extern int __io_putchar(int ch) __attribute__((weak)); +extern int __io_getchar(void) __attribute__((weak)); + + +char *__env[1] = { 0 }; +char **environ = __env; + + +/* Functions */ +void initialise_monitor_handles() +{ +} + +int _getpid(void) +{ + return 1; +} + +int _kill(int pid, int sig) +{ + (void)pid; + (void)sig; + errno = EINVAL; + return -1; +} + +void _exit (int status) +{ + _kill(status, -1); + while (1) {} /* Make sure we hang here */ +} + +__attribute__((weak)) int _read(int file, char *ptr, int len) +{ + (void)file; + int DataIdx; + + for (DataIdx = 0; DataIdx < len; DataIdx++) + { + *ptr++ = __io_getchar(); + } + + return len; +} + +__attribute__((weak)) int _write(int file, char *ptr, int len) +{ + (void)file; + int DataIdx; + + for (DataIdx = 0; DataIdx < len; DataIdx++) + { + __io_putchar(*ptr++); + } + return len; +} + +int _close(int file) +{ + (void)file; + return -1; +} + + +int _fstat(int file, struct stat *st) +{ + (void)file; + st->st_mode = S_IFCHR; + return 0; +} + +int _isatty(int file) +{ + (void)file; + return 1; +} + +int _lseek(int file, int ptr, int dir) +{ + (void)file; + (void)ptr; + (void)dir; + return 0; +} + +int _open(char *path, int flags, ...) +{ + (void)path; + (void)flags; + /* Pretend like we always fail */ + return -1; +} + +int _wait(int *status) +{ + (void)status; + errno = ECHILD; + return -1; +} + +int _unlink(char *name) +{ + (void)name; + errno = ENOENT; + return -1; +} + +int _times(struct tms *buf) +{ + (void)buf; + return -1; +} + +int _stat(char *file, struct stat *st) +{ + (void)file; + st->st_mode = S_IFCHR; + return 0; +} + +int _link(char *old, char *new) +{ + (void)old; + (void)new; + errno = EMLINK; + return -1; +} + +int _fork(void) +{ + errno = EAGAIN; + return -1; +} + +int _execve(char *name, char **argv, char **env) +{ + (void)name; + (void)argv; + (void)env; + errno = ENOMEM; + return -1; +} diff --git a/STM32CubeIDE/Application/User/Core/sysmem.c b/STM32CubeIDE/Application/User/Core/sysmem.c new file mode 100644 index 0000000..b425690 --- /dev/null +++ b/STM32CubeIDE/Application/User/Core/sysmem.c @@ -0,0 +1,79 @@ +/** + ****************************************************************************** + * @file sysmem.c + * @author Generated by STM32CubeIDE + * @brief STM32CubeIDE System Memory calls file + * + * For more information about which C functions + * need which of these lowlevel functions + * please consult the newlib libc manual + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes */ +#include +#include + +/** + * Pointer to the current high watermark of the heap usage + */ +static uint8_t *__sbrk_heap_end = NULL; + +/** + * @brief _sbrk() allocates memory to the newlib heap and is used by malloc + * and others from the C library + * + * @verbatim + * ############################################################################ + * # .data # .bss # newlib heap # MSP stack # + * # # # # Reserved by _Min_Stack_Size # + * ############################################################################ + * ^-- RAM start ^-- _end _estack, RAM end --^ + * @endverbatim + * + * This implementation starts allocating at the '_end' linker symbol + * The '_Min_Stack_Size' linker symbol reserves a memory for the MSP stack + * The implementation considers '_estack' linker symbol to be RAM end + * NOTE: If the MSP stack, at any point during execution, grows larger than the + * reserved size, please increase the '_Min_Stack_Size'. + * + * @param incr Memory size + * @return Pointer to allocated memory + */ +void *_sbrk(ptrdiff_t incr) +{ + extern uint8_t _end; /* Symbol defined in the linker script */ + extern uint8_t _estack; /* Symbol defined in the linker script */ + extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */ + const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size; + const uint8_t *max_heap = (uint8_t *)stack_limit; + uint8_t *prev_heap_end; + + /* Initialize heap end at first call */ + if (NULL == __sbrk_heap_end) + { + __sbrk_heap_end = &_end; + } + + /* Protect heap from growing into the reserved MSP stack */ + if (__sbrk_heap_end + incr > max_heap) + { + errno = ENOMEM; + return (void *)-1; + } + + prev_heap_end = __sbrk_heap_end; + __sbrk_heap_end += incr; + + return (void *)prev_heap_end; +} diff --git a/STM32CubeIDE/Application/User/Startup/startup_stm32wl55jcix.s b/STM32CubeIDE/Application/User/Startup/startup_stm32wl55jcix.s new file mode 100644 index 0000000..454561e --- /dev/null +++ b/STM32CubeIDE/Application/User/Startup/startup_stm32wl55jcix.s @@ -0,0 +1,434 @@ +/** + ****************************************************************************** + * @file startup_stm32wl55xx_cm4.s + * @author MCD Application Team + * @brief STM32WL55xx devices Cortex-M4 vector table for GCC toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address, + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M4 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + * Copyright (c) 2020-2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +.syntax unified +.cpu cortex-m4 +.fpu softvfp +.thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr r0, =_estack + mov sp, r0 /* set stack pointer */ + +/* Call the clock system initialization function.*/ + bl SystemInit + +/* Copy the data segment initializers from flash to SRAM */ + ldr r0, =_sdata + ldr r1, =_edata + ldr r2, =_sidata + movs r3, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r4, [r2, r3] + str r4, [r0, r3] + adds r3, r3, #4 + +LoopCopyDataInit: + adds r4, r0, r3 + cmp r4, r1 + bcc CopyDataInit + +/* Zero fill the bss segment. */ + ldr r2, =_sbss + ldr r4, =_ebss + movs r3, #0 + b LoopFillZerobss + +FillZerobss: + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + cmp r2, r4 + bcc FillZerobss + +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + + .size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler + +/****************************************************************************** +* +* The STM32WL55xx Cortex-M4 vector table. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler /* Window Watchdog interrupt */ + .word PVD_PVM_IRQHandler /* PVD and PVM interrupt through EXTI */ + .word TAMP_STAMP_LSECSS_SSRU_IRQHandler /* RTC Tamper, RTC TimeStamp, LSECSS and RTC SSRU int.*/ + .word RTC_WKUP_IRQHandler /* RTC wakeup interrupt through EXTI[19] */ + .word FLASH_IRQHandler /* Flash memory global interrupt and Flash memory ECC */ + .word RCC_IRQHandler /* RCC global interrupt */ + .word EXTI0_IRQHandler /* EXTI line 0 interrupt */ + .word EXTI1_IRQHandler /* EXTI line 1 interrupt */ + .word EXTI2_IRQHandler /* EXTI line 2 interrupt */ + .word EXTI3_IRQHandler /* EXTI line 3 interrupt */ + .word EXTI4_IRQHandler /* EXTI line 4 interrupt */ + .word DMA1_Channel1_IRQHandler /* DMA1 channel 1 interrupt */ + .word DMA1_Channel2_IRQHandler /* DMA1 channel 2 interrupt */ + .word DMA1_Channel3_IRQHandler /* DMA1 channel 3 interrupt */ + .word DMA1_Channel4_IRQHandler /* DMA1 channel 4 interrupt */ + .word DMA1_Channel5_IRQHandler /* DMA1 channel 5 interrupt */ + .word DMA1_Channel6_IRQHandler /* DMA1 channel 6 interrupt */ + .word DMA1_Channel7_IRQHandler /* DMA1 channel 7 interrupt */ + .word ADC_IRQHandler /* ADC interrupt */ + .word DAC_IRQHandler /* DAC interrupt */ + .word C2SEV_PWR_C2H_IRQHandler /* CPU M0+ SEV Interrupt */ + .word COMP_IRQHandler /* COMP1 and COMP2 interrupt through EXTI */ + .word EXTI9_5_IRQHandler /* EXTI line 9_5 interrupt */ + .word TIM1_BRK_IRQHandler /* Timer 1 break interrupt */ + .word TIM1_UP_IRQHandler /* Timer 1 Update */ + .word TIM1_TRG_COM_IRQHandler /* Timer 1 trigger and communication */ + .word TIM1_CC_IRQHandler /* Timer 1 capture compare interrupt */ + .word TIM2_IRQHandler /* TIM2 global interrupt */ + .word TIM16_IRQHandler /* Timer 16 global interrupt */ + .word TIM17_IRQHandler /* Timer 17 global interrupt */ + .word I2C1_EV_IRQHandler /* I2C1 event interrupt */ + .word I2C1_ER_IRQHandler /* I2C1 event interrupt */ + .word I2C2_EV_IRQHandler /* I2C2 error interrupt */ + .word I2C2_ER_IRQHandler /* I2C2 error interrupt */ + .word SPI1_IRQHandler /* SPI1 global interrupt */ + .word SPI2_IRQHandler /* SPI2 global interrupt */ + .word USART1_IRQHandler /* USART1 global interrupt */ + .word USART2_IRQHandler /* USART2 global interrupt */ + .word LPUART1_IRQHandler /* LPUART1 global interrupt */ + .word LPTIM1_IRQHandler /* LPtimer 1 global interrupt */ + .word LPTIM2_IRQHandler /* LPtimer 2 global interrupt */ + .word EXTI15_10_IRQHandler /* EXTI line 15_10] interrupt through EXTI */ + .word RTC_Alarm_IRQHandler /* RTC Alarms A & B interrupt */ + .word LPTIM3_IRQHandler /* LPtimer 3 global interrupt */ + .word SUBGHZSPI_IRQHandler /* SUBGHZSPI global interrupt */ + .word IPCC_C1_RX_IRQHandler /* IPCC CPU1 RX occupied interrupt */ + .word IPCC_C1_TX_IRQHandler /* IPCC CPU1 RX free interrupt */ + .word HSEM_IRQHandler /* Semaphore interrupt 0 to CPU1 */ + .word I2C3_EV_IRQHandler /* I2C3 event interrupt */ + .word I2C3_ER_IRQHandler /* I2C3 error interrupt */ + .word SUBGHZ_Radio_IRQHandler /* Radio IRQs RFBUSY interrupt through EXTI */ + .word AES_IRQHandler /* AES global interrupt */ + .word RNG_IRQHandler /* RNG interrupt */ + .word PKA_IRQHandler /* PKA interrupt */ + .word DMA2_Channel1_IRQHandler /* DMA2 channel 1 interrupt */ + .word DMA2_Channel2_IRQHandler /* DMA2 channel 2 interrupt */ + .word DMA2_Channel3_IRQHandler /* DMA2 channel 3 interrupt */ + .word DMA2_Channel4_IRQHandler /* DMA2 channel 4 interrupt */ + .word DMA2_Channel5_IRQHandler /* DMA2 channel 5 interrupt */ + .word DMA2_Channel6_IRQHandler /* DMA2 channel 6 interrupt */ + .word DMA2_Channel7_IRQHandler /* DMA2 channel 7 interrupt */ + .word DMAMUX1_OVR_IRQHandler /* DMAMUX overrun interrupt */ + + .size g_pfnVectors, .-g_pfnVectors + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_PVM_IRQHandler + .thumb_set PVD_PVM_IRQHandler,Default_Handler + + .weak TAMP_STAMP_LSECSS_SSRU_IRQHandler + .thumb_set TAMP_STAMP_LSECSS_SSRU_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC_IRQHandler + .thumb_set ADC_IRQHandler,Default_Handler + + .weak DAC_IRQHandler + .thumb_set DAC_IRQHandler,Default_Handler + + .weak C2SEV_PWR_C2H_IRQHandler + .thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler + + .weak COMP_IRQHandler + .thumb_set COMP_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_IRQHandler + .thumb_set TIM1_BRK_IRQHandler,Default_Handler + + .weak TIM1_UP_IRQHandler + .thumb_set TIM1_UP_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_IRQHandler + .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM16_IRQHandler + .thumb_set TIM16_IRQHandler,Default_Handler + + .weak TIM17_IRQHandler + .thumb_set TIM17_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak LPUART1_IRQHandler + .thumb_set LPUART1_IRQHandler,Default_Handler + + .weak LPTIM1_IRQHandler + .thumb_set LPTIM1_IRQHandler,Default_Handler + + .weak LPTIM2_IRQHandler + .thumb_set LPTIM2_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak LPTIM3_IRQHandler + .thumb_set LPTIM3_IRQHandler,Default_Handler + + .weak SUBGHZSPI_IRQHandler + .thumb_set SUBGHZSPI_IRQHandler,Default_Handler + + .weak IPCC_C1_RX_IRQHandler + .thumb_set IPCC_C1_RX_IRQHandler,Default_Handler + + .weak IPCC_C1_TX_IRQHandler + .thumb_set IPCC_C1_TX_IRQHandler,Default_Handler + + .weak HSEM_IRQHandler + .thumb_set HSEM_IRQHandler,Default_Handler + + .weak I2C3_EV_IRQHandler + .thumb_set I2C3_EV_IRQHandler,Default_Handler + + .weak I2C3_ER_IRQHandler + .thumb_set I2C3_ER_IRQHandler,Default_Handler + + .weak SUBGHZ_Radio_IRQHandler + .thumb_set SUBGHZ_Radio_IRQHandler,Default_Handler + + .weak AES_IRQHandler + .thumb_set AES_IRQHandler,Default_Handler + + .weak RNG_IRQHandler + .thumb_set RNG_IRQHandler,Default_Handler + + .weak PKA_IRQHandler + .thumb_set PKA_IRQHandler,Default_Handler + + .weak DMA2_Channel1_IRQHandler + .thumb_set DMA2_Channel1_IRQHandler,Default_Handler + + .weak DMA2_Channel2_IRQHandler + .thumb_set DMA2_Channel2_IRQHandler,Default_Handler + + .weak DMA2_Channel3_IRQHandler + .thumb_set DMA2_Channel3_IRQHandler,Default_Handler + + .weak DMA2_Channel4_IRQHandler + .thumb_set DMA2_Channel4_IRQHandler,Default_Handler + + .weak DMA2_Channel5_IRQHandler + .thumb_set DMA2_Channel5_IRQHandler,Default_Handler + + .weak DMA2_Channel6_IRQHandler + .thumb_set DMA2_Channel6_IRQHandler,Default_Handler + + .weak DMA2_Channel7_IRQHandler + .thumb_set DMA2_Channel7_IRQHandler,Default_Handler + + .weak DMAMUX1_OVR_IRQHandler + .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler + + .weak SystemInit diff --git a/STM32CubeIDE/STM32WL55JCIX_FLASH.ld b/STM32CubeIDE/STM32WL55JCIX_FLASH.ld new file mode 100644 index 0000000..7646938 --- /dev/null +++ b/STM32CubeIDE/STM32WL55JCIX_FLASH.ld @@ -0,0 +1,211 @@ +/* +****************************************************************************** +** +** File : LinkerScript.ld +** +** Author : STM32CubeIDE +** +** Abstract : Linker script for STM32WL55xC Device +** 256Kbytes FLASH +** 64Kbytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed as is without any warranty +** of any kind. +** +** Note : For specific memory allocation, linker and startup files must be customized. +** Refer to STM32CubeIDE user guide (UM2609), chapter "Modify the linker script". +** +***************************************************************************** +** @attention +** +** Copyright (c) 2021 STMicroelectronics. +** All rights reserved. +** +** This software is licensed under terms that can be found in the LICENSE file +** in the root directory of this software component. +** If no LICENSE file comes with this software, it is provided AS-IS. +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM1) + LENGTH(RAM1); /* end of "RAM1" Ram type memory */ + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x800; /* required amount of stack */ + +/* Memories definition */ +MEMORY +{ + RAM1 (xrw) : ORIGIN = 0x20000000, LENGTH = 32K + RAM2 (xrw) : ORIGIN = 0x20008000, LENGTH = 32K + FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 256K +} + +/* Sections */ +SECTIONS +{ + /* The startup code into "FLASH" Rom type memory */ + .isr_vector : + { + . = ALIGN(8); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(8); + } >FLASH + + /* The program code and other data into "FLASH" Rom type memory */ + .text : + { + . = ALIGN(8); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(8); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data into "FLASH" Rom type memory */ + .rodata : + { + . = ALIGN(8); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(8); + } >FLASH + + .ARM.extab : { + . = ALIGN(8); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(8); + } >FLASH + + .ARM : { + . = ALIGN(8); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(8); + } >FLASH + + .preinit_array : + { + . = ALIGN(8); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(8); + } >FLASH + + .init_array : + { + . = ALIGN(8); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(8); + } >FLASH + + .fini_array : + { + . = ALIGN(8); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(8); + } >FLASH + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM1" Ram type memory */ + .data : + { + . = ALIGN(8); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + . = ALIGN(8); + _edata = .; /* define a global symbol at data end */ + + } >RAM1 AT> FLASH + + /* Uninitialized data section into "RAM1" Ram type memory */ + . = ALIGN(8); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(8); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM1 + + /* Data section into "RAM1" Ram type memory: Non-backup RAM1 dedicated to CM4 */ + . = ALIGN(8); + RAM1_region : + { + _sRAM1_region = .; /* define a global symbol at section start */ + *(.RAM1_region) + + . = ALIGN(8); + _eRAM1_region = .; /* define a global symbol at section end */ + } >RAM1 + + /* Data section into "RAM2" Ram type memory: Backup RAM2 dedicated to CM4 */ + . = ALIGN(8); + RAM2_region : + { + _sRAM2_region = .; /* define a global symbol at section start */ + *(.RAM2_region) + + . = ALIGN(8); + _eRAM2_region = .; /* define a global symbol at section end */ + } >RAM2 + + /* User_heap_stack section, used to check that there is enough "RAM1" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM1 + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/STM32WL55JCIX_FLASH.ld b/STM32WL55JCIX_FLASH.ld new file mode 100644 index 0000000..f57efa3 --- /dev/null +++ b/STM32WL55JCIX_FLASH.ld @@ -0,0 +1,187 @@ +/* +****************************************************************************** +** +** File : LinkerScript.ld +** +** Author : STM32CubeIDE +** +** Abstract : Linker script for STM32WL55xC Device +** 256Kbytes FLASH +** 64Kbytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed as is without any warranty +** of any kind. +** +***************************************************************************** +** @attention +** +** Copyright (c) 2025 STMicroelectronics. +** All rights reserved. +** +** This software is licensed under terms that can be found in the LICENSE file +** in the root directory of this software component. +** If no LICENSE file comes with this software, it is provided AS-IS. +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x800; /* required amount of stack */ + +/* Memories definition */ +MEMORY +{ + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K + RAM2 (xrw) : ORIGIN = 0x10000000, LENGTH = 32K + FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 256K +} + +/* Sections */ +SECTIONS +{ + /* The startup code into "FLASH" Rom type memory */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data into "FLASH" Rom type memory */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data into "FLASH" Rom type memory */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >FLASH + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >FLASH + + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + + } >RAM AT> FLASH + + /* Uninitialized data section into "RAM" Ram type memory */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/SubGHz_Phy/App/app_subghz_phy.c b/SubGHz_Phy/App/app_subghz_phy.c new file mode 100644 index 0000000..d50826c --- /dev/null +++ b/SubGHz_Phy/App/app_subghz_phy.c @@ -0,0 +1,16 @@ +#include "app_subghz_phy.h" +#include "subghz_phy_app.h" +#include "sys_app.h" +#include "stm32_seq.h" + +void MX_SubGHz_Phy_Init(void) +{ + SystemApp_Init(); + SubghzApp_Init(); +} + +void MX_SubGHz_Phy_Process(void) +{ + SubghzApp_Process(); + UTIL_SEQ_Run(UTIL_SEQ_DEFAULT); +} diff --git a/SubGHz_Phy/App/app_subghz_phy.h b/SubGHz_Phy/App/app_subghz_phy.h new file mode 100644 index 0000000..3f62081 --- /dev/null +++ b/SubGHz_Phy/App/app_subghz_phy.h @@ -0,0 +1,73 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file app_subghz_phy.h + * @author MCD Application Team + * @brief Header of application of the SubGHz_Phy Middleware + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __APP_SUBGHZ_PHY_H__ +#define __APP_SUBGHZ_PHY_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported Functions Prototypes ---------------------------------------------*/ +/** + * @brief Init SubGHz Radio Application + */ +void MX_SubGHz_Phy_Init(void); + +/** + * @brief SubGHz Radio Application Process + */ +void MX_SubGHz_Phy_Process(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +#ifdef __cplusplus +} +#endif + +#endif /*__APP_SUBGHZ_PHY_H__*/ diff --git a/SubGHz_Phy/App/app_version.h b/SubGHz_Phy/App/app_version.h new file mode 100644 index 0000000..66a3a6f --- /dev/null +++ b/SubGHz_Phy/App/app_version.h @@ -0,0 +1,82 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file app_version.h + * @author MCD Application Team + * @brief Definition the version of the application + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __APP_VERSION_H__ +#define __APP_VERSION_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +#define APP_VERSION_MAIN (0x01U) /*!< [31:24] main version */ +#define APP_VERSION_SUB1 (0x04U) /*!< [23:16] sub1 version */ +#define APP_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */ +#define APP_VERSION_RC (0x00U) /*!< [7:0] release candidate */ + +#define APP_VERSION_MAIN_SHIFT 24 /*!< main byte shift */ +#define APP_VERSION_SUB1_SHIFT 16 /*!< sub1 byte shift */ +#define APP_VERSION_SUB2_SHIFT 8 /*!< sub2 byte shift */ +#define APP_VERSION_RC_SHIFT 0 /*!< release candidate byte shift */ + +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + +/* Exported macros -----------------------------------------------------------*/ +/** + * @brief Application version + */ +#define APP_VERSION ((APP_VERSION_MAIN << APP_VERSION_MAIN_SHIFT)\ + |(APP_VERSION_SUB1 << APP_VERSION_SUB1_SHIFT)\ + |(APP_VERSION_SUB2 << APP_VERSION_SUB2_SHIFT)\ + |(APP_VERSION_RC << APP_VERSION_RC_SHIFT)) + +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +#ifdef __cplusplus +} +#endif + +#endif /*__APP_VERSION_H__*/ diff --git a/SubGHz_Phy/App/subghz_phy_app.c b/SubGHz_Phy/App/subghz_phy_app.c new file mode 100644 index 0000000..94d04b1 --- /dev/null +++ b/SubGHz_Phy/App/subghz_phy_app.c @@ -0,0 +1,901 @@ +#include "platform.h" +#include "subghz_phy_app.h" +#include "radio.h" +#include "usart_if.h" +#include "usart.h" +#include "main.h" + +#include +#include +#include +#include +#include +#include + +#define RX_TIMEOUT_VALUE_MS 0U +#define TX_TIMEOUT_VALUE_MS 3000U +#define RX_CONTINUOUS_ON 1U +#define RADIO_SYNCWORD_LEN 3U +#define RADIO_WHITENING_SEED 0x01FFU +#define RADIO_CRC_POLY 0x8005U +#define RADIO_CRC_SEED 0xFFFFU + +#define UART_DATA_BUFFER_SIZE 220U +#define RADIO_MAX_PAYLOAD_SIZE 220U +#define TX_QUEUE_DEPTH 4U +#define CONFIG_LINE_SIZE 96U +#define CONFIG_ESCAPE_GUARD_MS 800U +#define DEFAULT_UART_PACKET_TIMEOUT_MS 20U + +typedef enum +{ + APP_MODE_DATA = 0, + APP_MODE_CONFIG +} AppMode_t; + +typedef struct +{ + uint32_t rf_frequency; + int8_t tx_power; + uint32_t fsk_bitrate; + uint32_t fsk_bandwidth; + uint32_t fsk_fdev; + uint16_t fsk_preamble_len; + uint8_t syncword[RADIO_SYNCWORD_LEN]; + uint16_t uart_packet_timeout_ms; + uint32_t uart_baudrate; +} BridgeConfig_t; + +typedef struct +{ + uint8_t data[RADIO_MAX_PAYLOAD_SIZE]; + uint8_t len; +} TxPacket_t; + +typedef struct +{ + uint8_t active; + uint8_t count; + uint8_t bytes[3]; + uint32_t start_tick; + uint32_t last_tick; +} EscapeDetector_t; + +static RadioEvents_t RadioEvents; +static BridgeConfig_t g_cfg = +{ + .rf_frequency = RF_FREQUENCY_DEFAULT, + .tx_power = TX_OUTPUT_POWER_DEFAULT, + .fsk_bitrate = FSK_DATARATE_DEFAULT, + .fsk_bandwidth = FSK_BANDWIDTH_DEFAULT, + .fsk_fdev = FSK_FDEV_DEFAULT, + .fsk_preamble_len = FSK_PREAMBLE_LENGTH_DEFAULT, + .syncword = {0xC1, 0x94, 0xC1}, + .uart_packet_timeout_ms = DEFAULT_UART_PACKET_TIMEOUT_MS, + .uart_baudrate = 115200UL, +}; + +static volatile uint8_t g_radio_tx_done = 0; +static volatile uint8_t g_radio_tx_timeout = 0; +static volatile uint8_t g_radio_rx_done = 0; +static volatile uint8_t g_radio_rx_timeout = 0; +static volatile uint8_t g_radio_rx_error = 0; +static volatile int16_t g_last_rx_rssi = 0; +static volatile int8_t g_last_rx_cfo = 0; + +static volatile uint8_t g_radio_busy = 0; +static volatile uint8_t g_radio_needs_rx_restart = 0; + +static uint8_t g_rx_payload[RADIO_MAX_PAYLOAD_SIZE]; +static uint16_t g_rx_payload_len = 0; + +static TxPacket_t g_tx_queue[TX_QUEUE_DEPTH]; +static uint8_t g_tx_q_head = 0; +static uint8_t g_tx_q_tail = 0; +static uint8_t g_tx_q_count = 0; + +static uint8_t g_uart_build_buf[UART_DATA_BUFFER_SIZE]; +static uint16_t g_uart_build_len = 0; +static uint32_t g_uart_last_data_tick = 0; + +static EscapeDetector_t g_escape = {0}; +static AppMode_t g_mode = APP_MODE_DATA; + +static char g_cfg_line[CONFIG_LINE_SIZE]; +static uint16_t g_cfg_line_len = 0; + +static uint32_t g_stat_uart_packets_tx = 0; +static uint32_t g_stat_uart_bytes_tx = 0; +static uint32_t g_stat_radio_packets_rx = 0; +static uint32_t g_stat_radio_bytes_rx = 0; +static uint32_t g_stat_queue_overflow = 0; + +static void OnTxDone(void); +static void OnRxDone(uint8_t *payload, uint16_t size, int16_t rssi, int8_t cfo); +static void OnTxTimeout(void); +static void OnRxTimeout(void); +static void OnRxError(void); + +static void UartRxByteCallback(uint8_t *rxChar, uint16_t size, uint8_t error); +static void App_ProcessRadioEvents(void); +static void App_ProcessUartPacketizer(void); +static void App_ProcessEscape(void); +static void App_StartNextTxIfPossible(void); +static void App_RadioEnterRx(void); +static void App_RadioApplyConfig(void); +static void App_RadioConfigureRx(void); +static void App_RadioConfigureTx(void); +static void App_EnterConfigMode(void); +static void App_ExitConfigMode(void); +static void App_ResetDataPath(void); +static void App_DataModeFeedByte(uint8_t ch, uint32_t now); +static void App_DataModeFlushBuilder(void); +static uint8_t App_QueuePush(const uint8_t *data, uint16_t len); +static void App_QueuePop(void); +static void App_ConfigFeedByte(uint8_t ch); +static void App_ConfigExecuteLine(char *line); +static void App_PrintConfigPrompt(void); +static void App_PrintHelp(void); +static void App_PrintStatus(void); +static void App_Printf(const char *fmt, ...); +static void App_Write(const uint8_t *data, uint16_t len); +static void App_ReconfigureUart(uint32_t baudrate); +static uint8_t App_ParseHexSyncWord(const char *text, uint8_t out[3]); +static char *App_SkipSpaces(char *s); + +void SubghzApp_Init(void) +{ + RadioEvents.TxDone = OnTxDone; + RadioEvents.RxDone = OnRxDone; + RadioEvents.TxTimeout = OnTxTimeout; + RadioEvents.RxTimeout = OnRxTimeout; + RadioEvents.RxError = OnRxError; + + Radio.Init(&RadioEvents); + App_RadioApplyConfig(); + App_RadioEnterRx(); + + g_uart_last_data_tick = HAL_GetTick(); + (void)vcom_ReceiveInit(UartRxByteCallback); + + App_Printf("\r\nSTM32WL UART<->SUBGHZ bridge started\r\n"); + App_Printf("DATA mode, escape sequence: silence 800 ms + +++ + silence 800 ms\r\n"); +} + +void SubghzApp_Process(void) +{ + App_ProcessEscape(); + App_ProcessUartPacketizer(); + App_ProcessRadioEvents(); + App_StartNextTxIfPossible(); +} + +static void App_ProcessRadioEvents(void) +{ + if (g_radio_tx_done != 0U) + { + g_radio_tx_done = 0U; + g_radio_busy = 0U; + g_stat_uart_packets_tx++; + App_QueuePop(); + g_radio_needs_rx_restart = 1U; + } + + if (g_radio_tx_timeout != 0U) + { + g_radio_tx_timeout = 0U; + g_radio_busy = 0U; + App_QueuePop(); + App_Printf("\r\n[WARN] radio tx timeout\r\n"); + g_radio_needs_rx_restart = 1U; + } + + if (g_radio_rx_done != 0U) + { + g_radio_rx_done = 0U; + g_stat_radio_packets_rx++; + g_stat_radio_bytes_rx += g_rx_payload_len; + + if (g_mode == APP_MODE_DATA) + { + App_Write(g_rx_payload, g_rx_payload_len); + } + + g_radio_needs_rx_restart = 1U; + } + + if ((g_radio_rx_timeout != 0U) || (g_radio_rx_error != 0U)) + { + g_radio_rx_timeout = 0U; + g_radio_rx_error = 0U; + g_radio_needs_rx_restart = 1U; + } + + if ((g_radio_needs_rx_restart != 0U) && (g_radio_busy == 0U) && (g_tx_q_count == 0U)) + { + g_radio_needs_rx_restart = 0U; + App_RadioEnterRx(); + } +} + +static void App_ProcessUartPacketizer(void) +{ + uint32_t now = HAL_GetTick(); + + if (g_mode != APP_MODE_DATA) + { + return; + } + + if ((g_uart_build_len > 0U) && + ((now - g_uart_last_data_tick) >= g_cfg.uart_packet_timeout_ms) && + (g_escape.active == 0U)) + { + App_DataModeFlushBuilder(); + } +} + +static void App_ProcessEscape(void) +{ + uint32_t now = HAL_GetTick(); + uint8_t i; + + if ((g_mode != APP_MODE_DATA) || (g_escape.active == 0U)) + { + return; + } + + if ((g_escape.count == 3U) && ((now - g_escape.last_tick) >= CONFIG_ESCAPE_GUARD_MS)) + { + g_escape.active = 0U; + g_escape.count = 0U; + App_EnterConfigMode(); + return; + } + + if ((g_escape.count < 3U) && ((now - g_escape.last_tick) >= CONFIG_ESCAPE_GUARD_MS)) + { + for (i = 0U; i < g_escape.count; i++) + { + App_DataModeFeedByte(g_escape.bytes[i], now); + } + g_escape.active = 0U; + g_escape.count = 0U; + } +} + +static void App_StartNextTxIfPossible(void) +{ + if ((g_mode != APP_MODE_DATA) || (g_radio_busy != 0U) || (g_tx_q_count == 0U)) + { + return; + } + + App_RadioConfigureTx(); + g_radio_busy = 1U; + (void)Radio.Send(g_tx_queue[g_tx_q_head].data, g_tx_queue[g_tx_q_head].len); +} + +static void App_RadioApplyConfig(void) +{ + Radio.SetChannel(g_cfg.rf_frequency); + g_radio_needs_rx_restart = 1U; +} + +static void App_RadioConfigureRx(void) +{ + RxConfigGeneric_t rx = {0}; + + Radio.SetChannel(g_cfg.rf_frequency); + + rx.fsk.ModulationShaping = RADIO_FSK_MOD_SHAPING_G_BT_05; + rx.fsk.Bandwidth = g_cfg.fsk_bandwidth; + rx.fsk.BitRate = g_cfg.fsk_bitrate; + rx.fsk.PreambleLen = g_cfg.fsk_preamble_len; + rx.fsk.SyncWordLength = RADIO_SYNCWORD_LEN; + rx.fsk.PreambleMinDetect = RADIO_FSK_PREAMBLE_DETECTOR_08_BITS; + rx.fsk.SyncWord = g_cfg.syncword; + rx.fsk.whiteSeed = RADIO_WHITENING_SEED; + rx.fsk.LengthMode = RADIO_FSK_PACKET_VARIABLE_LENGTH; + rx.fsk.CrcLength = RADIO_FSK_CRC_2_BYTES_IBM; + rx.fsk.CrcPolynomial = RADIO_CRC_POLY; + rx.fsk.CrcSeed = RADIO_CRC_SEED; + rx.fsk.Whitening = RADIO_FSK_DC_FREEWHITENING; + rx.fsk.MaxPayloadLength = RADIO_MAX_PAYLOAD_SIZE; + rx.fsk.StopTimerOnPreambleDetect = 0; + rx.fsk.AddrComp = RADIO_FSK_ADDRESSCOMP_FILT_OFF; + + Radio.Standby(); + if (0UL != Radio.RadioSetRxGenericConfig(GENERIC_FSK, &rx, RX_CONTINUOUS_ON, 0U)) + { + Error_Handler(); + } +} + +static void App_RadioConfigureTx(void) +{ + TxConfigGeneric_t tx = {0}; + + Radio.SetChannel(g_cfg.rf_frequency); + + tx.fsk.ModulationShaping = RADIO_FSK_MOD_SHAPING_G_BT_05; + tx.fsk.FrequencyDeviation = g_cfg.fsk_fdev; + tx.fsk.BitRate = g_cfg.fsk_bitrate; + tx.fsk.PreambleLen = g_cfg.fsk_preamble_len; + tx.fsk.SyncWordLength = RADIO_SYNCWORD_LEN; + tx.fsk.SyncWord = g_cfg.syncword; + tx.fsk.whiteSeed = RADIO_WHITENING_SEED; + tx.fsk.HeaderType = RADIO_FSK_PACKET_VARIABLE_LENGTH; + tx.fsk.CrcLength = RADIO_FSK_CRC_2_BYTES_IBM; + tx.fsk.CrcPolynomial = RADIO_CRC_POLY; + tx.fsk.CrcSeed = RADIO_CRC_SEED; + tx.fsk.Whitening = RADIO_FSK_DC_FREEWHITENING; + + Radio.Standby(); + if (0UL != Radio.RadioSetTxGenericConfig(GENERIC_FSK, &tx, g_cfg.tx_power, TX_TIMEOUT_VALUE_MS)) + { + Error_Handler(); + } +} + +static void App_RadioEnterRx(void) +{ + App_RadioConfigureRx(); + Radio.Rx(RX_TIMEOUT_VALUE_MS); +} + +static void App_EnterConfigMode(void) +{ + App_ResetDataPath(); + g_mode = APP_MODE_CONFIG; + App_Printf("\r\n\r\n[CONFIG MODE]\r\n"); + App_Printf("type 'help' for commands\r\n"); + App_PrintConfigPrompt(); +} + +static void App_ExitConfigMode(void) +{ + g_cfg_line_len = 0U; + App_ResetDataPath(); + g_mode = APP_MODE_DATA; + App_Printf("\r\n[DATA MODE]\r\n"); + g_radio_needs_rx_restart = 1U; +} + +static void App_ResetDataPath(void) +{ + g_uart_build_len = 0U; + g_escape.active = 0U; + g_escape.count = 0U; + g_tx_q_head = 0U; + g_tx_q_tail = 0U; + g_tx_q_count = 0U; +} + +static void App_DataModeFeedByte(uint8_t ch, uint32_t now) +{ + if (g_uart_build_len < UART_DATA_BUFFER_SIZE) + { + g_uart_build_buf[g_uart_build_len++] = ch; + g_uart_last_data_tick = now; + g_stat_uart_bytes_tx++; + } + else + { + App_DataModeFlushBuilder(); + if (g_uart_build_len < UART_DATA_BUFFER_SIZE) + { + g_uart_build_buf[g_uart_build_len++] = ch; + g_uart_last_data_tick = now; + g_stat_uart_bytes_tx++; + } + } +} + +static void App_DataModeFlushBuilder(void) +{ + if (g_uart_build_len == 0U) + { + return; + } + + if (App_QueuePush(g_uart_build_buf, g_uart_build_len) == 0U) + { + g_stat_queue_overflow++; + } + g_uart_build_len = 0U; +} + +static uint8_t App_QueuePush(const uint8_t *data, uint16_t len) +{ + if ((len == 0U) || (len > RADIO_MAX_PAYLOAD_SIZE) || (g_tx_q_count >= TX_QUEUE_DEPTH)) + { + return 0U; + } + + memcpy(g_tx_queue[g_tx_q_tail].data, data, len); + g_tx_queue[g_tx_q_tail].len = (uint8_t)len; + g_tx_q_tail = (uint8_t)((g_tx_q_tail + 1U) % TX_QUEUE_DEPTH); + g_tx_q_count++; + return 1U; +} + +static void App_QueuePop(void) +{ + if (g_tx_q_count == 0U) + { + return; + } + + g_tx_q_head = (uint8_t)((g_tx_q_head + 1U) % TX_QUEUE_DEPTH); + g_tx_q_count--; +} + +static void UartRxByteCallback(uint8_t *rxChar, uint16_t size, uint8_t error) +{ + uint8_t ch; + uint32_t now; + uint8_t i; + + if ((error != 0U) || (size == 0U) || (rxChar == NULL)) + { + return; + } + + ch = rxChar[0]; + now = HAL_GetTick(); + + if (g_mode == APP_MODE_CONFIG) + { + App_ConfigFeedByte(ch); + return; + } + + if (g_escape.active == 0U) + { + if (((now - g_uart_last_data_tick) >= CONFIG_ESCAPE_GUARD_MS) && (ch == '+')) + { + g_escape.active = 1U; + g_escape.count = 1U; + g_escape.bytes[0] = ch; + g_escape.start_tick = now; + g_escape.last_tick = now; + return; + } + + App_DataModeFeedByte(ch, now); + return; + } + + if ((ch == '+') && (g_escape.count < 3U)) + { + g_escape.bytes[g_escape.count++] = ch; + g_escape.last_tick = now; + return; + } + + for (i = 0U; i < g_escape.count; i++) + { + App_DataModeFeedByte(g_escape.bytes[i], now); + } + g_escape.active = 0U; + g_escape.count = 0U; + + if (((now - g_uart_last_data_tick) >= CONFIG_ESCAPE_GUARD_MS) && (ch == '+')) + { + g_escape.active = 1U; + g_escape.count = 1U; + g_escape.bytes[0] = ch; + g_escape.start_tick = now; + g_escape.last_tick = now; + return; + } + + App_DataModeFeedByte(ch, now); +} + +static void App_ConfigFeedByte(uint8_t ch) +{ + if ((ch == '\r') || (ch == '\n')) + { + if (g_cfg_line_len > 0U) + { + g_cfg_line[g_cfg_line_len] = '\0'; + App_Printf("\r\n"); + App_ConfigExecuteLine(g_cfg_line); + g_cfg_line_len = 0U; + } + App_PrintConfigPrompt(); + return; + } + + if ((ch == 0x08U) || (ch == 0x7FU)) + { + if (g_cfg_line_len > 0U) + { + g_cfg_line_len--; + App_Write((const uint8_t *)"\b \b", 3U); + } + return; + } + + if ((isprint(ch) != 0) && (g_cfg_line_len < (CONFIG_LINE_SIZE - 1U))) + { + g_cfg_line[g_cfg_line_len++] = (char)ch; + App_Write(&ch, 1U); + } +} + +static void App_ConfigExecuteLine(char *line) +{ + char *arg; + uint32_t u32; + uint8_t sync[3]; + + line = App_SkipSpaces(line); + if (*line == '\0') + { + return; + } + + if ((strcmp(line, "help") == 0) || (strcmp(line, "?") == 0)) + { + App_PrintHelp(); + return; + } + + if ((strcmp(line, "show") == 0) || (strcmp(line, "status") == 0)) + { + App_PrintStatus(); + return; + } + + if (strcmp(line, "exit") == 0) + { + App_ExitConfigMode(); + return; + } + + if (strcmp(line, "defaults") == 0) + { + g_cfg.rf_frequency = RF_FREQUENCY_DEFAULT; + g_cfg.tx_power = TX_OUTPUT_POWER_DEFAULT; + g_cfg.fsk_bitrate = FSK_DATARATE_DEFAULT; + g_cfg.fsk_bandwidth = FSK_BANDWIDTH_DEFAULT; + g_cfg.fsk_fdev = FSK_FDEV_DEFAULT; + g_cfg.fsk_preamble_len = FSK_PREAMBLE_LENGTH_DEFAULT; + g_cfg.syncword[0] = 0xC1U; + g_cfg.syncword[1] = 0x94U; + g_cfg.syncword[2] = 0xC1U; + g_cfg.uart_packet_timeout_ms = DEFAULT_UART_PACKET_TIMEOUT_MS; + App_RadioApplyConfig(); + App_Printf("defaults restored\r\n"); + return; + } + + if (strncmp(line, "freq ", 5) == 0) + { + u32 = strtoul(&line[5], NULL, 10); + if (u32 < 150000000UL || u32 > 960000000UL) + { + App_Printf("bad frequency\r\n"); + return; + } + g_cfg.rf_frequency = u32; + App_RadioApplyConfig(); + App_Printf("freq=%lu\r\n", (unsigned long)g_cfg.rf_frequency); + return; + } + + if (strncmp(line, "power ", 6) == 0) + { + long pwr = strtol(&line[6], NULL, 10); + if ((pwr < -9L) || (pwr > 22L)) + { + App_Printf("bad power\r\n"); + return; + } + g_cfg.tx_power = (int8_t)pwr; + App_RadioApplyConfig(); + App_Printf("power=%d\r\n", g_cfg.tx_power); + return; + } + + if (strncmp(line, "bitrate ", 8) == 0) + { + u32 = strtoul(&line[8], NULL, 10); + if ((u32 < 600UL) || (u32 > 300000UL)) + { + App_Printf("bad bitrate\r\n"); + return; + } + g_cfg.fsk_bitrate = u32; + App_RadioApplyConfig(); + App_Printf("bitrate=%lu\r\n", (unsigned long)g_cfg.fsk_bitrate); + return; + } + + if (strncmp(line, "bandwidth ", 10) == 0) + { + u32 = strtoul(&line[10], NULL, 10); + if ((u32 < 2600UL) || (u32 > 250000UL)) + { + App_Printf("bad bandwidth\r\n"); + return; + } + g_cfg.fsk_bandwidth = u32; + App_RadioApplyConfig(); + App_Printf("bandwidth=%lu\r\n", (unsigned long)g_cfg.fsk_bandwidth); + return; + } + + if (strncmp(line, "fdev ", 5) == 0) + { + u32 = strtoul(&line[5], NULL, 10); + if (u32 > 200000UL) + { + App_Printf("bad fdev\r\n"); + return; + } + g_cfg.fsk_fdev = u32; + App_RadioApplyConfig(); + App_Printf("fdev=%lu\r\n", (unsigned long)g_cfg.fsk_fdev); + return; + } + + if (strncmp(line, "preamble ", 9) == 0) + { + u32 = strtoul(&line[9], NULL, 10); + if ((u32 < 2UL) || (u32 > 65535UL)) + { + App_Printf("bad preamble\r\n"); + return; + } + g_cfg.fsk_preamble_len = (uint16_t)u32; + App_RadioApplyConfig(); + App_Printf("preamble=%u\r\n", g_cfg.fsk_preamble_len); + return; + } + + if (strncmp(line, "timeout ", 8) == 0) + { + u32 = strtoul(&line[8], NULL, 10); + if ((u32 < 1UL) || (u32 > 1000UL)) + { + App_Printf("bad timeout\r\n"); + return; + } + g_cfg.uart_packet_timeout_ms = (uint16_t)u32; + App_Printf("timeout=%u\r\n", g_cfg.uart_packet_timeout_ms); + return; + } + + if (strncmp(line, "uart ", 5) == 0) + { + u32 = strtoul(&line[5], NULL, 10); + if ((u32 < 1200UL) || (u32 > 921600UL)) + { + App_Printf("bad uart baudrate\r\n"); + return; + } + g_cfg.uart_baudrate = u32; + App_Printf("switching uart to %lu baud\r\n", (unsigned long)g_cfg.uart_baudrate); + App_ReconfigureUart(g_cfg.uart_baudrate); + return; + } + + if (strncmp(line, "sync ", 5) == 0) + { + arg = App_SkipSpaces(&line[5]); + if (App_ParseHexSyncWord(arg, sync) == 0U) + { + App_Printf("bad sync, use 6 hex chars, e.g. C194C1\r\n"); + return; + } + memcpy(g_cfg.syncword, sync, sizeof(sync)); + App_RadioApplyConfig(); + App_Printf("sync=%02X%02X%02X\r\n", g_cfg.syncword[0], g_cfg.syncword[1], g_cfg.syncword[2]); + return; + } + + App_Printf("unknown command: %s\r\n", line); +} + +static void App_PrintConfigPrompt(void) +{ + if (g_mode == APP_MODE_CONFIG) + { + App_Printf("cfg> "); + } +} + +static void App_PrintHelp(void) +{ + App_Printf("commands:\r\n"); + App_Printf(" help - this help\r\n"); + App_Printf(" show - current config and counters\r\n"); + App_Printf(" freq - rf frequency\r\n"); + App_Printf(" power - tx power (-9..22)\r\n"); + App_Printf(" bitrate - fsk bitrate\r\n"); + App_Printf(" bandwidth - fsk rx bandwidth\r\n"); + App_Printf(" fdev - fsk frequency deviation\r\n"); + App_Printf(" preamble - fsk preamble length\r\n"); + App_Printf(" sync - 3-byte syncword, example C194C1\r\n"); + App_Printf(" timeout - uart silence before rf packet send\r\n"); + App_Printf(" uart - change uart baudrate immediately\r\n"); + App_Printf(" defaults - restore default config\r\n"); + App_Printf(" exit - return to transparent bridge mode\r\n"); +} + +static void App_PrintStatus(void) +{ + App_Printf("mode=%s\r\n", (g_mode == APP_MODE_CONFIG) ? "config" : "data"); + App_Printf("freq=%lu Hz\r\n", (unsigned long)g_cfg.rf_frequency); + App_Printf("power=%d dBm\r\n", g_cfg.tx_power); + App_Printf("bitrate=%lu bps\r\n", (unsigned long)g_cfg.fsk_bitrate); + App_Printf("bandwidth=%lu Hz\r\n", (unsigned long)g_cfg.fsk_bandwidth); + App_Printf("fdev=%lu Hz\r\n", (unsigned long)g_cfg.fsk_fdev); + App_Printf("preamble=%u bytes\r\n", g_cfg.fsk_preamble_len); + App_Printf("sync=%02X%02X%02X\r\n", g_cfg.syncword[0], g_cfg.syncword[1], g_cfg.syncword[2]); + App_Printf("uart_baud=%lu\r\n", (unsigned long)g_cfg.uart_baudrate); + App_Printf("uart_pkt_timeout=%u ms\r\n", g_cfg.uart_packet_timeout_ms); + App_Printf("tx_queue=%u/%u\r\n", g_tx_q_count, TX_QUEUE_DEPTH); + App_Printf("last_rx_rssi=%d dBm\r\n", (int)g_last_rx_rssi); + App_Printf("last_rx_cfo=%d\r\n", (int)g_last_rx_cfo); + App_Printf("stat_uart_packets_tx=%lu\r\n", (unsigned long)g_stat_uart_packets_tx); + App_Printf("stat_uart_bytes_tx=%lu\r\n", (unsigned long)g_stat_uart_bytes_tx); + App_Printf("stat_radio_packets_rx=%lu\r\n", (unsigned long)g_stat_radio_packets_rx); + App_Printf("stat_radio_bytes_rx=%lu\r\n", (unsigned long)g_stat_radio_bytes_rx); + App_Printf("stat_queue_overflow=%lu\r\n", (unsigned long)g_stat_queue_overflow); +} + +static void App_Printf(const char *fmt, ...) +{ + char buffer[192]; + va_list ap; + int len; + + va_start(ap, fmt); + len = vsnprintf(buffer, sizeof(buffer), fmt, ap); + va_end(ap); + + if (len <= 0) + { + return; + } + + if ((size_t)len >= sizeof(buffer)) + { + len = (int)(sizeof(buffer) - 1U); + } + + App_Write((const uint8_t *)buffer, (uint16_t)len); +} + +static void App_Write(const uint8_t *data, uint16_t len) +{ + if ((data == NULL) || (len == 0U)) + { + return; + } + + (void)HAL_UART_Transmit(&huart2, (uint8_t *)data, len, 1000U); +} + +static void App_ReconfigureUart(uint32_t baudrate) +{ + huart2.Init.BaudRate = baudrate; + + (void)HAL_UART_AbortReceive(&huart2); + + if (HAL_UART_Init(&huart2) != HAL_OK) + { + Error_Handler(); + } + if (HAL_UARTEx_SetTxFifoThreshold(&huart2, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK) + { + Error_Handler(); + } + if (HAL_UARTEx_SetRxFifoThreshold(&huart2, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK) + { + Error_Handler(); + } + if (HAL_UARTEx_EnableFifoMode(&huart2) != HAL_OK) + { + Error_Handler(); + } + + (void)vcom_ReceiveInit(UartRxByteCallback); +} + +static uint8_t App_ParseHexSyncWord(const char *text, uint8_t out[3]) +{ + char buf[7]; + char *endptr; + unsigned long value; + size_t i; + size_t n = 0U; + + if ((text == NULL) || (out == NULL)) + { + return 0U; + } + + while ((*text != '\0') && (n < 6U)) + { + if (isxdigit((unsigned char)*text) != 0) + { + buf[n++] = *text; + } + text++; + } + + if (n != 6U) + { + return 0U; + } + + for (i = 0U; i < n; i++) + { + if (isxdigit((unsigned char)buf[i]) == 0) + { + return 0U; + } + } + + buf[6] = '\0'; + value = strtoul(buf, &endptr, 16); + if ((endptr == NULL) || (*endptr != '\0')) + { + return 0U; + } + + out[0] = (uint8_t)((value >> 16) & 0xFFU); + out[1] = (uint8_t)((value >> 8) & 0xFFU); + out[2] = (uint8_t)(value & 0xFFU); + return 1U; +} + +static char *App_SkipSpaces(char *s) +{ + while ((s != NULL) && (*s != '\0') && isspace((unsigned char)*s)) + { + s++; + } + return s; +} + +static void OnTxDone(void) +{ + g_radio_tx_done = 1U; +} + +static void OnRxDone(uint8_t *payload, uint16_t size, int16_t rssi, int8_t cfo) +{ + g_last_rx_rssi = rssi; + g_last_rx_cfo = cfo; + + if (size > RADIO_MAX_PAYLOAD_SIZE) + { + size = RADIO_MAX_PAYLOAD_SIZE; + } + + memcpy(g_rx_payload, payload, size); + g_rx_payload_len = size; + g_radio_rx_done = 1U; +} + +static void OnTxTimeout(void) +{ + g_radio_tx_timeout = 1U; +} + +static void OnRxTimeout(void) +{ + g_radio_rx_timeout = 1U; +} + +static void OnRxError(void) +{ + g_radio_rx_error = 1U; +} diff --git a/SubGHz_Phy/App/subghz_phy_app.h b/SubGHz_Phy/App/subghz_phy_app.h new file mode 100644 index 0000000..e6c5745 --- /dev/null +++ b/SubGHz_Phy/App/subghz_phy_app.h @@ -0,0 +1,24 @@ +#ifndef __SUBGHZ_PHY_APP_H__ +#define __SUBGHZ_PHY_APP_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +#define RF_FREQUENCY_DEFAULT 433100000UL +#define TX_OUTPUT_POWER_DEFAULT 14 +#define FSK_FDEV_DEFAULT 25000UL +#define FSK_DATARATE_DEFAULT 50000UL +#define FSK_BANDWIDTH_DEFAULT 50000UL +#define FSK_PREAMBLE_LENGTH_DEFAULT 4U + +void SubghzApp_Init(void); +void SubghzApp_Process(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __SUBGHZ_PHY_APP_H__ */ diff --git a/SubGHz_Phy/Target/mw_log_conf.h b/SubGHz_Phy/Target/mw_log_conf.h new file mode 100644 index 0000000..f2c2798 --- /dev/null +++ b/SubGHz_Phy/Target/mw_log_conf.h @@ -0,0 +1,72 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file mw_log_conf.h + * @author MCD Application Team + * @brief Configure (enable/disable) traces + ******************************************************************************* + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MW_LOG_CONF_H__ +#define __MW_LOG_CONF_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32_adv_trace.h" + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +#define MW_LOG_ENABLED + +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef MW_LOG_ENABLED +#define MW_LOG(TS,VL, ...) do{ {UTIL_ADV_TRACE_COND_FSend(VL, T_REG_OFF, TS, __VA_ARGS__);} }while(0) +#else /* MW_LOG_ENABLED */ +#define MW_LOG(TS,VL, ...) +#endif /* MW_LOG_ENABLED */ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +#ifdef __cplusplus +} +#endif + +#endif /*__MW_LOG_CONF_H__ */ diff --git a/SubGHz_Phy/Target/radio_board_if.c b/SubGHz_Phy/Target/radio_board_if.c new file mode 100644 index 0000000..ed48fff --- /dev/null +++ b/SubGHz_Phy/Target/radio_board_if.c @@ -0,0 +1,256 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file radio_board_if.c + * @author MCD Application Team + * @brief This file provides an interface layer between MW and Radio Board + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "radio_board_if.h" + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* External variables ---------------------------------------------------------*/ +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN PTD */ + +/* USER CODE END PTD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ + +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* Exported functions --------------------------------------------------------*/ +int32_t RBI_Init(void) +{ + /* USER CODE BEGIN RBI_Init_1 */ + + /* USER CODE END RBI_Init_1 */ +#if defined(USE_BSP_DRIVER) + /* Important note: BSP code is board dependent + * STM32WL_Nucleo code can be found + * either in STM32CubeWL package under Drivers/BSP/STM32WLxx_Nucleo/ + * or at https://github.com/STMicroelectronics/STM32CubeWL/tree/main/Drivers/BSP/STM32WLxx_Nucleo/ + * 1/ For User boards, the BSP/STM32WLxx_Nucleo/ directory can be copied and replaced in the project. The copy must then be updated depending: + * on board RF switch configuration (pin control, number of port etc) + * on TCXO configuration + * on DC/DC configuration + * on maximum output power that the board can deliver*/ + return BSP_RADIO_Init(); +#else + /* 2/ Or implement RBI_Init here */ + int32_t retcode = 0; + /* USER CODE BEGIN RBI_Init_2 */ +#warning user to provide its board code or to call his board driver functions + /* USER CODE END RBI_Init_2 */ + return retcode; +#endif /* USE_BSP_DRIVER */ +} + +int32_t RBI_DeInit(void) +{ + /* USER CODE BEGIN RBI_DeInit_1 */ + + /* USER CODE END RBI_DeInit_1 */ +#if defined(USE_BSP_DRIVER) + /* Important note: BSP code is board dependent + * STM32WL_Nucleo code can be found + * either in STM32CubeWL package under Drivers/BSP/STM32WLxx_Nucleo/ + * or at https://github.com/STMicroelectronics/STM32CubeWL/tree/main/Drivers/BSP/STM32WLxx_Nucleo/ + * 1/ For User boards, the BSP/STM32WLxx_Nucleo/ directory can be copied and replaced in the project. The copy must then be updated depending: + * on board RF switch configuration (pin control, number of port etc) + * on TCXO configuration + * on DC/DC configuration + * on maximum output power that the board can deliver*/ + return BSP_RADIO_DeInit(); +#else + /* 2/ Or implement RBI_DeInit here */ + int32_t retcode = 0; + /* USER CODE BEGIN RBI_DeInit_2 */ +#warning user to provide its board code or to call his board driver functions + /* USER CODE END RBI_DeInit_2 */ + return retcode; +#endif /* USE_BSP_DRIVER */ +} + +int32_t RBI_ConfigRFSwitch(RBI_Switch_TypeDef Config) +{ + /* USER CODE BEGIN RBI_ConfigRFSwitch_1 */ + + /* USER CODE END RBI_ConfigRFSwitch_1 */ +#if defined(USE_BSP_DRIVER) + + /* Important note: BSP code is board dependent + * STM32WL_Nucleo code can be found + * either in STM32CubeWL package under Drivers/BSP/STM32WLxx_Nucleo/ + * or at https://github.com/STMicroelectronics/STM32CubeWL/tree/main/Drivers/BSP/STM32WLxx_Nucleo/ + * 1/ For User boards, the BSP/STM32WLxx_Nucleo/ directory can be copied and replaced in the project. The copy must then be updated depending: + * on board RF switch configuration (pin control, number of port etc) + * on TCXO configuration + * on DC/DC configuration + * on maximum output power that the board can deliver*/ + return BSP_RADIO_ConfigRFSwitch((BSP_RADIO_Switch_TypeDef) Config); +#else + /* 2/ Or implement RBI_ConfigRFSwitch here */ + int32_t retcode = 0; + /* USER CODE BEGIN RBI_ConfigRFSwitch_2 */ +#warning user to provide its board code or to call his board driver functions + /* USER CODE END RBI_ConfigRFSwitch_2 */ + return retcode; +#endif /* USE_BSP_DRIVER */ +} + +int32_t RBI_GetTxConfig(void) +{ + /* USER CODE BEGIN RBI_GetTxConfig_1 */ + + /* USER CODE END RBI_GetTxConfig_1 */ +#if defined(USE_BSP_DRIVER) + /* Important note: BSP code is board dependent + * STM32WL_Nucleo code can be found + * either in STM32CubeWL package under Drivers/BSP/STM32WLxx_Nucleo/ + * or at https://github.com/STMicroelectronics/STM32CubeWL/tree/main/Drivers/BSP/STM32WLxx_Nucleo/ + * 1/ For User boards, the BSP/STM32WLxx_Nucleo/ directory can be copied and replaced in the project. The copy must then be updated depending: + * on board RF switch configuration (pin control, number of port etc) + * on TCXO configuration + * on DC/DC configuration + * on maximum output power that the board can deliver*/ + return BSP_RADIO_GetTxConfig(); +#else + /* 2/ Or implement RBI_GetTxConfig here */ + int32_t retcode = RBI_CONF_RFO; + /* USER CODE BEGIN RBI_GetTxConfig_2 */ +#warning user to provide its board code or to call his board driver functions + /* USER CODE END RBI_GetTxConfig_2 */ + return retcode; +#endif /* USE_BSP_DRIVER */ +} + +int32_t RBI_IsTCXO(void) +{ + /* USER CODE BEGIN RBI_IsTCXO_1 */ + + /* USER CODE END RBI_IsTCXO_1 */ +#if defined(USE_BSP_DRIVER) + /* Important note: BSP code is board dependent + * STM32WL_Nucleo code can be found + * either in STM32CubeWL package under Drivers/BSP/STM32WLxx_Nucleo/ + * or at https://github.com/STMicroelectronics/STM32CubeWL/tree/main/Drivers/BSP/STM32WLxx_Nucleo/ + * 1/ For User boards, the BSP/STM32WLxx_Nucleo/ directory can be copied and replaced in the project. The copy must then be updated depending: + * on board RF switch configuration (pin control, number of port etc) + * on TCXO configuration + * on DC/DC configuration + * on maximum output power that the board can deliver*/ + return BSP_RADIO_IsTCXO(); +#else + /* 2/ Or implement RBI_IsTCXO here */ + int32_t retcode = IS_TCXO_SUPPORTED; + /* USER CODE BEGIN RBI_IsTCXO_2 */ +#warning user to provide its board code or to call his board driver functions + /* USER CODE END RBI_IsTCXO_2 */ + return retcode; +#endif /* USE_BSP_DRIVER */ +} + +int32_t RBI_IsDCDC(void) +{ + /* USER CODE BEGIN RBI_IsDCDC_1 */ + + /* USER CODE END RBI_IsDCDC_1 */ +#if defined(USE_BSP_DRIVER) + /* Important note: BSP code is board dependent + * STM32WL_Nucleo code can be found + * either in STM32CubeWL package under Drivers/BSP/STM32WLxx_Nucleo/ + * or at https://github.com/STMicroelectronics/STM32CubeWL/tree/main/Drivers/BSP/STM32WLxx_Nucleo/ + * 1/ For User boards, the BSP/STM32WLxx_Nucleo/ directory can be copied and replaced in the project. The copy must then be updated depending: + * on board RF switch configuration (pin control, number of port etc) + * on TCXO configuration + * on DC/DC configuration + * on maximum output power that the board can deliver*/ + return BSP_RADIO_IsDCDC(); +#else + /* 2/ Or implement RBI_IsDCDC here */ + int32_t retcode = IS_DCDC_SUPPORTED; + /* USER CODE BEGIN RBI_IsDCDC_2 */ +#warning user to provide its board code or to call his board driver functions + /* USER CODE END RBI_IsDCDC_2 */ + return retcode; +#endif /* USE_BSP_DRIVER */ +} + +int32_t RBI_GetRFOMaxPowerConfig(RBI_RFOMaxPowerConfig_TypeDef Config) +{ + /* USER CODE BEGIN RBI_GetRFOMaxPowerConfig_1 */ + + /* USER CODE END RBI_GetRFOMaxPowerConfig_1 */ +#if defined(USE_BSP_DRIVER) + /* Important note: BSP code is board dependent + * STM32WL_Nucleo code can be found + * either in STM32CubeWL package under Drivers/BSP/STM32WLxx_Nucleo/ + * or at https://github.com/STMicroelectronics/STM32CubeWL/tree/main/Drivers/BSP/STM32WLxx_Nucleo/ + * 1/ For User boards, the BSP/STM32WLxx_Nucleo/ directory can be copied and replaced in the project. The copy must then be updated depending: + * on board RF switch configuration (pin control, number of port etc) + * on TCXO configuration + * on DC/DC configuration + * on maximum output power that the board can deliver*/ + return BSP_RADIO_GetRFOMaxPowerConfig((BSP_RADIO_RFOMaxPowerConfig_TypeDef) Config); +#else + /* 2/ Or implement RBI_RBI_GetRFOMaxPowerConfig here */ + int32_t ret = 0; + /* USER CODE BEGIN RBI_GetRFOMaxPowerConfig_2 */ +#warning user to provide its board code or to call his board driver functions + if (Config == RBI_RFO_LP_MAXPOWER) + { + ret = 15; /*dBm*/ + } + else + { + ret = 22; /*dBm*/ + } + /* USER CODE END RBI_GetRFOMaxPowerConfig_2 */ + return ret; +#endif /* USE_BSP_DRIVER */ +} +/* USER CODE BEGIN EF */ + +/* USER CODE END EF */ + +/* Private Functions Definition -----------------------------------------------*/ +/* USER CODE BEGIN PrFD */ + +/* USER CODE END PrFD */ diff --git a/SubGHz_Phy/Target/radio_board_if.h b/SubGHz_Phy/Target/radio_board_if.h new file mode 100644 index 0000000..b603631 --- /dev/null +++ b/SubGHz_Phy/Target/radio_board_if.h @@ -0,0 +1,223 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file radio_board_if.h + * @author MCD Application Team + * @brief Header for Radio interface configuration + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef RADIO_BOARD_IF_H +#define RADIO_BOARD_IF_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "platform.h" +/* USER CODE BEGIN include */ + +/* USER CODE END include */ + +/* Exported defines ----------------------------------------------------------*/ +#if defined(USE_BSP_DRIVER) +/* code generated by STM32CubeMX does not support BSP */ +/* In order to use BSP driver, add the correspondent files in the IDE workspace */ +/* and define USE_BSP_DRIVER in the preprocessor definitions or in platform.h */ +#define RBI_CONF_RFO_LP_HP RADIO_CONF_RFO_LP_HP +#define RBI_CONF_RFO_LP RADIO_CONF_RFO_LP +#define RBI_CONF_RFO_HP RADIO_CONF_RFO_HP +#else +/* USER CODE BEGIN Board Definition */ + +/* USER CODE END Board Definition */ +#define RBI_CONF_RFO_LP_HP 0 +#define RBI_CONF_RFO_LP 1 +#define RBI_CONF_RFO_HP 2 +/* USER CODE BEGIN Board Definition_2 */ + +/* USER CODE END Board Definition_2 */ +#endif /* USE_BSP_DRIVER */ + +#if defined(USE_BSP_DRIVER) +/* code generated by STM32CubeMX does not support BSP */ +/* In order to use BSP driver, add the correspondent files in the IDE workspace */ +/* and define USE_BSP_DRIVER in the preprocessor definitions or in platform.h */ + +#else +/* USER CODE BEGIN Exported Parameters */ + +/* USER CODE END Exported Parameters */ +/* Indicates the type of switch between the ones proposed by CONFIG Constants + */ +#define RBI_CONF_RFO RBI_CONF_RFO_LP_HP + +/* Indicates whether or not TCXO is supported by the board + * 0: TCXO not supported + * 1: TCXO supported + */ +#define IS_TCXO_SUPPORTED 1U + +/* Indicates whether or not DCDC is supported by the board + * 0: DCDC not supported + * 1: DCDC supported + */ +#define IS_DCDC_SUPPORTED 1U + +/* USER CODE BEGIN Exported Parameters_2 */ + +/* USER CODE END Exported Parameters_2 */ +#endif /* USE_BSP_DRIVER */ + +#if defined(USE_BSP_DRIVER) +/* code generated by STM32CubeMX does not support BSP */ +/* In order to use BSP driver, add the correspondent files in the IDE workspace */ +/* and define USE_BSP_DRIVER in the preprocessor definitions or in platform.h */ + +#else +/* USER CODE BEGIN Exported PinMapping */ +#warning user to provide its board definitions pins +/* USER CODE END Exported PinMapping */ +#endif /* USE_BSP_DRIVER */ + +/* USER CODE BEGIN ED */ + +/* USER CODE END ED */ + +/* Exported types ------------------------------------------------------------*/ + +#if defined(USE_BSP_DRIVER) +/* code generated by STM32CubeMX does not support BSP */ +/* In order to use BSP driver, add the correspondent files in the IDE workspace */ +/* and define USE_BSP_DRIVER in the preprocessor definitions or in platform.h */ +typedef enum +{ + RBI_SWITCH_OFF = RADIO_SWITCH_OFF, + RBI_SWITCH_RX = RADIO_SWITCH_RX, + RBI_SWITCH_RFO_LP = RADIO_SWITCH_RFO_LP, + RBI_SWITCH_RFO_HP = RADIO_SWITCH_RFO_HP, +} RBI_Switch_TypeDef; + +typedef enum +{ + RBI_RFO_LP_MAXPOWER = RADIO_RFO_LP_MAXPOWER, + RBI_RFO_HP_MAXPOWER = RADIO_RFO_HP_MAXPOWER, +} RBI_RFOMaxPowerConfig_TypeDef; + +#else +/* USER CODE BEGIN Exported Types */ + +/* USER CODE END Exported Types */ +typedef enum +{ + RBI_SWITCH_OFF = 0, + RBI_SWITCH_RX = 1, + RBI_SWITCH_RFO_LP = 2, + RBI_SWITCH_RFO_HP = 3, +} RBI_Switch_TypeDef; + +typedef enum +{ + RBI_RFO_LP_MAXPOWER = 0, + RBI_RFO_HP_MAXPOWER = 1, +} RBI_RFOMaxPowerConfig_TypeDef; +/* USER CODE BEGIN Exported Types_2 */ + +/* USER CODE END Exported Types_2 */ +#endif /* USE_BSP_DRIVER */ + +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions ------------------------------------------------------- */ +/** + * @brief Init Radio Switch + * @return BSP status + */ +int32_t RBI_Init(void); + +/** + * @brief DeInit Radio Switch + * @return BSP status + */ +int32_t RBI_DeInit(void); + +/** + * @brief Configure Radio Switch. + * @param Config: Specifies the Radio RF switch path to be set. + * This parameter can be one of following parameters: + * @arg RADIO_SWITCH_OFF + * @arg RADIO_SWITCH_RX + * @arg RADIO_SWITCH_RFO_LP + * @arg RADIO_SWITCH_RFO_HP + * @return BSP status + */ +int32_t RBI_ConfigRFSwitch(RBI_Switch_TypeDef Config); + +/** + * @brief Return Board Configuration + * @retval RBI_CONF_RFO_LP_HP + * @retval RBI_CONF_RFO_LP + * @retval RBI_CONF_RFO_HP + */ +int32_t RBI_GetTxConfig(void); + +/** + * @brief Get If TCXO is to be present on board + * @note never remove called by MW, + * @retval return 1 if present, 0 if not present + */ +int32_t RBI_IsTCXO(void); + +/** + * @brief Get If DCDC is to be present on board + * @note never remove called by MW, + * @retval return 1 if present, 0 if not present + */ +int32_t RBI_IsDCDC(void); + +/** + * @brief Return RF Output Max Power Configuration of matching circuit + * @note never remove called by MW, + * @retval return Max Power configuration of matching circuit for Low Power or High Power mode in dBm + */ +int32_t RBI_GetRFOMaxPowerConfig(RBI_RFOMaxPowerConfig_TypeDef Config); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +#ifdef __cplusplus +} +#endif + +#endif /* RADIO_BOARD_IF_H */ diff --git a/SubGHz_Phy/Target/radio_conf.h b/SubGHz_Phy/Target/radio_conf.h new file mode 100644 index 0000000..952cb43 --- /dev/null +++ b/SubGHz_Phy/Target/radio_conf.h @@ -0,0 +1,178 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file radio_conf.h + * @author MCD Application Team + * @brief Header of Radio configuration + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __RADIO_CONF_H__ +#define __RADIO_CONF_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "platform.h" +#include "subghz.h" +#include "stm32_mem.h" /* RADIO_MEMSET8 def in this file */ +#include "mw_log_conf.h" /* mw trace conf */ +#include "radio_board_if.h" /* low layer api (bsp) */ +#include "utilities_def.h" /* low layer api (bsp) */ +#include "sys_debug.h" +/* USER CODE BEGIN include */ + +/* USER CODE END include */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ + +/** + * @brief drive value used anytime radio is NOT in TX low power mode + * @note override the default configuration of radio_driver.c + */ +#define SMPS_DRIVE_SETTING_DEFAULT SMPS_DRV_40 + +/** + * @brief drive value used anytime radio is in TX low power mode + * TX low power mode is the worst case because the PA sinks from SMPS + * while in high power mode, current is sunk directly from the battery + * @note override the default configuration of radio_driver.c + */ +#define SMPS_DRIVE_SETTING_MAX SMPS_DRV_60 + +/** + * @brief Provides the frequency of the chip running on the radio and the frequency step + * @remark These defines are used for computing the frequency divider to set the RF frequency + * @note override the default configuration of radio_driver.c + */ +#define XTAL_FREQ ( 32000000UL ) + +/** + * @brief in XO mode, set internal capacitor (from 0x00 to 0x2F starting 11.2pF with 0.47pF steps) + * @note override the default configuration of radio_driver.c + */ +#define XTAL_DEFAULT_CAP_VALUE ( 0x20UL ) + +/** + * @brief voltage of vdd tcxo. + * @note override the default configuration of radio_driver.c + */ +#define TCXO_CTRL_VOLTAGE TCXO_CTRL_1_7V + +/** + * @brief Radio maximum wakeup time (in ms) + * @note override the default configuration of radio_driver.c + */ +#define RF_WAKEUP_TIME ( 1UL ) + +/** + * @brief DCDC is enabled + * @remark this define is only used if the DCDC is present on the board + * @note override the default configuration of radio_driver.c + */ +#define DCDC_ENABLE ( 1UL ) + +/* USER CODE BEGIN EC */ +/** + * @brief enables the RFW module + * @note disabled by default + */ +#define RFW_ENABLE 1 + +/** + * @brief enables the RFW long packet feature + * @note disabled by default + */ +#define RFW_LONGPACKET_ENABLE 1 + +/** + * @brief enables the RFW module log + * @note disabled by default + */ +#define RFW_MW_LOG_ENABLE + +/** + * @brief Set RX pin to high or low level + */ +#define DBG_GPIO_RADIO_RX(set_rst) PROBE_GPIO_##set_rst##_LINE(PROBE_LINE1_PORT, PROBE_LINE1_PIN); + +/** + * @brief Set TX pin to high or low level + */ +#define DBG_GPIO_RADIO_TX(set_rst) PROBE_GPIO_##set_rst##_LINE(PROBE_LINE2_PORT, PROBE_LINE2_PIN); + +/* USER CODE END EC */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + +/* Exported macros -----------------------------------------------------------*/ +#ifndef CRITICAL_SECTION_BEGIN +/** + * @brief macro used to enter the critical section + */ +#define CRITICAL_SECTION_BEGIN( ) UTILS_ENTER_CRITICAL_SECTION( ) +#endif /* !CRITICAL_SECTION_BEGIN */ +#ifndef CRITICAL_SECTION_END +/** + * @brief macro used to exit the critical section + */ +#define CRITICAL_SECTION_END( ) UTILS_EXIT_CRITICAL_SECTION( ) +#endif /* !CRITICAL_SECTION_END */ + +/* Function mapping */ +/** + * @brief SUBGHZ interface init to radio Middleware + */ +#define RADIO_INIT MX_SUBGHZ_Init + +/** + * @brief Delay interface to radio Middleware + */ +#define RADIO_DELAY_MS HAL_Delay + +/** + * @brief Memset utilities interface to radio Middleware + */ +#define RADIO_MEMSET8( dest, value, size ) UTIL_MEM_set_8( dest, value, size ) + +/** + * @brief Memcpy utilities interface to radio Middleware + */ +#define RADIO_MEMCPY8( dest, src, size ) UTIL_MEM_cpy_8( dest, src, size ) + +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +#ifdef __cplusplus +} +#endif + +#endif /* __RADIO_CONF_H__*/ diff --git a/SubGHz_Phy/Target/timer.h b/SubGHz_Phy/Target/timer.h new file mode 100644 index 0000000..c6ff217 --- /dev/null +++ b/SubGHz_Phy/Target/timer.h @@ -0,0 +1,117 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file timer.h + * @author MCD Application Team + * @brief Wrapper to timer server + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __TIMER_H__ +#define __TIMER_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32_timer.h" +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/** + * @brief Max timer mask + */ +#define TIMERTIME_T_MAX ( ( uint32_t )~0 ) + +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + +/* Exported macro ------------------------------------------------------------*/ +/** + * @brief Timer value on 32 bits + */ +#define TimerTime_t UTIL_TIMER_Time_t + +/** + * @brief Timer object description + */ +#define TimerEvent_t UTIL_TIMER_Object_t + +/** + * @brief Create the timer object + */ +#define TimerInit(HANDLE, CB) do {\ + UTIL_TIMER_Create( HANDLE, TIMERTIME_T_MAX, UTIL_TIMER_ONESHOT, CB, NULL);\ + } while(0) + +/** + * @brief update the period and start the timer + */ +#define TimerSetValue(HANDLE, TIMEOUT) do{ \ + UTIL_TIMER_SetPeriod(HANDLE, TIMEOUT);\ + } while(0) + +/** + * @brief Start and adds the timer object to the list of timer events + */ +#define TimerStart(HANDLE) do {\ + UTIL_TIMER_Start(HANDLE);\ + } while(0) + +/** + * @brief Stop and removes the timer object from the list of timer events + */ +#define TimerStop(HANDLE) do {\ + UTIL_TIMER_Stop(HANDLE);\ + } while(0) + +/** + * @brief return the current time + */ +#define TimerGetCurrentTime UTIL_TIMER_GetCurrentTime + +/** + * @brief return the elapsed time + */ +#define TimerGetElapsedTime UTIL_TIMER_GetElapsedTime + +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +#ifdef __cplusplus +} +#endif + +#endif /* __TIMER_H__*/ diff --git a/SubGHz_Phy_Per (1).launch b/SubGHz_Phy_Per (1).launch new file mode 100644 index 0000000..23ac090 --- /dev/null +++ b/SubGHz_Phy_Per (1).launch @@ -0,0 +1,88 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/SubGHz_Phy_Per.ioc b/SubGHz_Phy_Per.ioc new file mode 100644 index 0000000..cc8c17f --- /dev/null +++ b/SubGHz_Phy_Per.ioc @@ -0,0 +1,345 @@ +#MicroXplorer Configuration settings - do not modify +BSP_IP_NAME=NUCLEO-WL55JC2 +CAD.formats= +CAD.pinconfig= +CAD.provider= +Dma.Request0=USART2_TX +Dma.RequestsNb=1 +Dma.USART2_TX.0.Channel_PRIV_NPRIV=DMA_CHANNEL_NPRIV_DISABLE +Dma.USART2_TX.0.Direction=DMA_MEMORY_TO_PERIPH +Dma.USART2_TX.0.EventEnable=DISABLE +Dma.USART2_TX.0.Instance=DMA1_Channel5 +Dma.USART2_TX.0.MemDataAlignment=DMA_MDATAALIGN_BYTE +Dma.USART2_TX.0.MemInc=DMA_MINC_ENABLE +Dma.USART2_TX.0.Mode=DMA_NORMAL +Dma.USART2_TX.0.PeriphDataAlignment=DMA_PDATAALIGN_BYTE +Dma.USART2_TX.0.PeriphInc=DMA_PINC_DISABLE +Dma.USART2_TX.0.Polarity=HAL_DMAMUX_REQ_GEN_RISING +Dma.USART2_TX.0.Priority=DMA_PRIORITY_LOW +Dma.USART2_TX.0.RequestNumber=1 +Dma.USART2_TX.0.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber,Channel_PRIV_NPRIV +Dma.USART2_TX.0.SignalID=NONE +Dma.USART2_TX.0.SyncEnable=DISABLE +Dma.USART2_TX.0.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT +Dma.USART2_TX.0.SyncRequestNumber=1 +Dma.USART2_TX.0.SyncSignalID=NONE +File.Version=6 +GPIO.groupedBy=Group By Peripherals +KeepUserPlacement=false +Mcu.CPN=STM32WL55JCI6 +Mcu.ContextProject=MonoOnDualCore +Mcu.Family=STM32WL +Mcu.IP0=ADV_TRACE +Mcu.IP1=DMA +Mcu.IP10=TIMER +Mcu.IP11=TINY_LPM +Mcu.IP12=USART2 +Mcu.IP13=NUCLEO-WL55JC2 +Mcu.IP2=MISC +Mcu.IP3=NVIC +Mcu.IP4=RCC +Mcu.IP5=RTC +Mcu.IP6=SEQUENCER_M4 +Mcu.IP7=SUBGHZ +Mcu.IP8=SUBGHZ_PHY +Mcu.IP9=SYS +Mcu.IPNb=14 +Mcu.Name=STM32WL55JCIx +Mcu.Package=UFBGA73 +Mcu.Pin0=PB15 +Mcu.Pin1=PC14-OSC32_IN +Mcu.Pin10=PB0-VDD_TCXO +Mcu.Pin11=PC6 +Mcu.Pin12=PA1 +Mcu.Pin13=PB11 +Mcu.Pin14=OSC_IN +Mcu.Pin15=PA3 +Mcu.Pin16=PA2 +Mcu.Pin17=VP_ADV_TRACE_VS_ADV_TRACE +Mcu.Pin18=VP_MISC_VS_MISC +Mcu.Pin19=VP_RTC_VS_RTC_Activate +Mcu.Pin2=PB9 +Mcu.Pin20=VP_RTC_VS_RTC_Calendar +Mcu.Pin21=VP_RTC_VS_RTC_Alarm_A_Intern +Mcu.Pin22=VP_SEQUENCER_M4_VS_SEQUENCER +Mcu.Pin23=VP_SUBGHZ_VS_SUBGHZ +Mcu.Pin24=VP_SUBGHZ_PHY_VS_SubGhzPhy +Mcu.Pin25=VP_SYS_VS_None +Mcu.Pin26=VP_TIMER_VS_TIMER +Mcu.Pin27=VP_TINY_LPM_VS_TINY_LPM +Mcu.Pin3=PC15-OSC32_OUT +Mcu.Pin4=PC3 +Mcu.Pin5=PA0 +Mcu.Pin6=PB13 +Mcu.Pin7=PC5 +Mcu.Pin8=PB12 +Mcu.Pin9=PC4 +Mcu.PinsNb=28 +Mcu.ThirdPartyNb=0 +Mcu.UserConstants=RTC_N_PREDIV_S,10;RTC_PREDIV_S,((1< + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Utilities/lpm/tiny_lpm/Release_Notes.html b/Utilities/lpm/tiny_lpm/Release_Notes.html new file mode 100644 index 0000000..f0468d3 --- /dev/null +++ b/Utilities/lpm/tiny_lpm/Release_Notes.html @@ -0,0 +1,303 @@ + + + + + + + Release Notes for STM32 TINY low power manager + + + + + + +
+
+
+

Release Notes for STM32 TINY low power manager

+

Copyright © 2019 STMicroelectronics
+

+ +
+

Purpose

+

The code source delivered is an utility to help customer to build a low power application.

+
+
+

Update History

+
+ +
+

Main Changes

+

Contents

+

Fixed bugs list

+ + + + + + + + + + + +
Headline
Ticket 137597 - [CodeSpell] Mistake in lpm module
+

known limitations

+

Development Toolchains and Compilers

+
    +
  • IAR Embedded Workbench for ARM (EWARM) toolchain V8.20.2
    • +
  • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.25
    • +
  • System Workbench STM32 (SW4STM32) toolchain V2.7.2
    • +
+

Supported Devices and boards

+

backward compatibility

+

Dependencies

+
+
+
+ +
+

Main Changes

+

Contents

+

Fixed bugs list

+ + + + + + + + + + + +
Headline
Release note format update
+

known limitations

+

Development Toolchains and Compilers

+
    +
  • IAR Embedded Workbench for ARM (EWARM) toolchain V8.20.2
    • +
  • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.25
    • +
  • System Workbench STM32 (SW4STM32) toolchain V2.7.2
    • +
+

Supported Devices and boards

+

backward compatibility

+

Dependencies

+
+
+
+ +
+

Main Changes

+

Contents

+

Fixed bugs list

+ + + + + + + + + + + +
Headline
Ticket 115234 - [Licensing] Update the way to declare licenses in Cube and X-CUBE components
+

known limitations

+

Development Toolchains and Compilers

+
    +
  • IAR Embedded Workbench for ARM (EWARM) toolchain V8.20.2
    • +
  • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.25
    • +
  • System Workbench STM32 (SW4STM32) toolchain V2.7.2
    • +
+

Supported Devices and boards

+

backward compatibility

+

Dependencies

+
+
+
+ +
+

Main Changes

+

release V1.3.1

+

Contents

+

Fixed bugs list

+ + + + + + + + + + + +
Headline
Ticket 86948 - CodeSpell : Correct some English words typo
+

known limitations

+

Development Toolchains and Compilers

+
    +
  • IAR Embedded Workbench for ARM (EWARM) toolchain V8.20.2
    • +
  • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.25
    • +
  • System Workbench STM32 (SW4STM32) toolchain V2.7.2
    • +
+

Supported Devices and boards

+

backward compatibility

+

Dependencies

+
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+ +
+

Main Changes

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release V1.3.0

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Contents

+

Fixed bugs list

+ + + + + + + + + + + + + + + + + +
Headline
Ticket 86948 - CodeSpell : Correct some English words typo
Ticket 89624 - Utilities Releases Notes improvements - Link on openorg BSD-3-Clause
Ticket 91318 - need specific CRITICAL_SECTION for UTIL_LPM_EnterLowPower function
+

known limitations

+

Development Toolchains and Compilers

+
    +
  • IAR Embedded Workbench for ARM (EWARM) toolchain V8.20.2
    • +
  • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.25
    • +
  • System Workbench STM32 (SW4STM32) toolchain V2.7.2
    • +
+

Supported Devices and boards

+

backward compatibility

+

Dependencies

+
+
+
+ +
+

Main Changes

+

release V1.2.0

+

Contents

+

Fixed bugs list

+ + + + + + + + + + + + + + +
Headline
Add the doxygen tag in the source code.
MISRAC update.
+

known limitations

+

Development Toolchains and Compilers

+
    +
  • IAR Embedded Workbench for ARM (EWARM) toolchain V8.20.2
    • +
  • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.25
    • +
  • System Workbench STM32 (SW4STM32) toolchain V2.7.2
    • +
+

Supported Devices and boards

+

backward compatibility

+

Dependencies

+
+
+
+ +
+

Main Changes

+

release V1.1.0

+

Contents

+

Fixed bugs list

+ + + + + + + + + + + +
Headline
Add CubeMx tag inside the template file.
+

known limitations

+

Development Toolchains and Compilers

+
    +
  • IAR Embedded Workbench for ARM (EWARM) toolchain V8.20.2
    • +
  • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.25
    • +
  • System Workbench STM32 (SW4STM32) toolchain V2.7.2
    • +
+

Supported Devices and boards

+

backward compatibility

+

Dependencies

+
+
+
+ +
+

Main Changes

+

First release

+

Contents

+

Fixed bugs list

+ + + + + + + + + + + +
Headline
first official release
+

known limitations

+

Development Toolchains and Compilers

+
    +
  • IAR Embedded Workbench for ARM (EWARM) toolchain V8.20.2
    • +
  • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.25
    • +
  • System Workbench STM32 (SW4STM32) toolchain V2.7.2
    • +
+

Supported Devices and boards

+

backward compatibility

+

Dependencies

+
+
+
+
+
+
+
+ +
+

Info

+
+
+
+ + diff --git a/Utilities/lpm/tiny_lpm/_htmresc/favicon.png b/Utilities/lpm/tiny_lpm/_htmresc/favicon.png new file mode 100644 index 0000000..06713ee Binary files /dev/null and b/Utilities/lpm/tiny_lpm/_htmresc/favicon.png differ diff --git a/Utilities/lpm/tiny_lpm/_htmresc/mini-st.css b/Utilities/lpm/tiny_lpm/_htmresc/mini-st.css new file mode 100644 index 0000000..986f4d4 --- /dev/null +++ b/Utilities/lpm/tiny_lpm/_htmresc/mini-st.css @@ -0,0 +1,1711 @@ +@charset "UTF-8"; +/* + Flavor name: Custom (mini-custom) + Generated online - https://minicss.org/flavors + mini.css version: v3.0.1 +*/ +/* + Browsers resets and base typography. +*/ +/* Core module CSS variable definitions */ +:root { + --fore-color: #03234b; + --secondary-fore-color: #03234b; + --back-color: #ffffff; + --secondary-back-color: #ffffff; + --blockquote-color: #e6007e; + --pre-color: #e6007e; + --border-color: #3cb4e6; + --secondary-border-color: #3cb4e6; + --heading-ratio: 1.2; + --universal-margin: 0.5rem; + --universal-padding: 0.25rem; + --universal-border-radius: 0.075rem; + --background-margin: 1.5%; + --a-link-color: #3cb4e6; + --a-visited-color: #8c0078; } + +html { + font-size: 13.5px; } + +a, b, del, em, i, ins, q, span, strong, u { + font-size: 1em; } + +html, * { + font-family: -apple-system, BlinkMacSystemFont, Helvetica, arial, sans-serif; + line-height: 1.25; + -webkit-text-size-adjust: 100%; } + +* { + font-size: 1rem; } + +body { + margin: 0; + color: var(--fore-color); + @background: var(--back-color); + background: var(--back-color) linear-gradient(#ffd200, #ffd200) repeat-y left top; + background-size: var(--background-margin); + } + +details { + display: block; } + +summary { + display: list-item; } + +abbr[title] { + border-bottom: none; + text-decoration: underline dotted; } + +input { + overflow: visible; } + +img { + max-width: 100%; + height: auto; } + +h1, h2, h3, h4, h5, h6 { + line-height: 1.25; + margin: calc(1.5 * var(--universal-margin)) var(--universal-margin); + font-weight: 400; } + h1 small, h2 small, h3 small, h4 small, h5 small, h6 small { + color: var(--secondary-fore-color); + display: block; + margin-top: -0.25rem; } + +h1 { + font-size: calc(1rem * var(--heading-ratio) * var(--heading-ratio) * var(--heading-ratio)); } + +h2 { + font-size: calc(1rem * var(--heading-ratio) * var(--heading-ratio) ); + border-style: none none solid none ; + border-width: thin; + border-color: var(--border-color); } +h3 { + font-size: calc(1rem * var(--heading-ratio) ); } + +h4 { + font-size: calc(1rem * var(--heading-ratio)); } + +h5 { + font-size: 1rem; } + +h6 { + font-size: calc(1rem / var(--heading-ratio)); } + +p { + margin: var(--universal-margin); } + +ol, ul { + margin: var(--universal-margin); + padding-left: calc(3 * var(--universal-margin)); } + +b, strong { + font-weight: 700; } + +hr { + box-sizing: content-box; + border: 0; + line-height: 1.25em; + margin: var(--universal-margin); + height: 0.0714285714rem; + background: linear-gradient(to right, transparent, var(--border-color) 20%, var(--border-color) 80%, transparent); } + +blockquote { + display: block; + position: relative; + font-style: italic; + color: var(--secondary-fore-color); + margin: var(--universal-margin); + padding: calc(3 * var(--universal-padding)); + border: 0.0714285714rem solid var(--secondary-border-color); + border-left: 0.3rem solid var(--blockquote-color); + border-radius: 0 var(--universal-border-radius) var(--universal-border-radius) 0; } + blockquote:before { + position: absolute; + top: calc(0rem - var(--universal-padding)); + left: 0; + font-family: sans-serif; + font-size: 2rem; + font-weight: 800; + content: "\201c"; + color: var(--blockquote-color); } + blockquote[cite]:after { + font-style: normal; + font-size: 0.75em; + font-weight: 700; + content: "\a— " attr(cite); + white-space: pre; } + +code, kbd, pre, samp { + font-family: Menlo, Consolas, monospace; + font-size: 0.85em; } + +code { + background: var(--secondary-back-color); + border-radius: var(--universal-border-radius); + padding: calc(var(--universal-padding) / 4) calc(var(--universal-padding) / 2); } + +kbd { + background: var(--fore-color); + color: var(--back-color); + border-radius: var(--universal-border-radius); + padding: calc(var(--universal-padding) / 4) calc(var(--universal-padding) / 2); } + +pre { + overflow: auto; + background: var(--secondary-back-color); + padding: calc(1.5 * var(--universal-padding)); + margin: var(--universal-margin); + border: 0.0714285714rem solid var(--secondary-border-color); + border-left: 0.2857142857rem solid var(--pre-color); + border-radius: 0 var(--universal-border-radius) var(--universal-border-radius) 0; } + +sup, sub, code, kbd { + line-height: 0; + position: relative; + vertical-align: baseline; } + +small, sup, sub, figcaption { + font-size: 0.75em; } + +sup { + top: -0.5em; } + +sub { + bottom: -0.25em; } + +figure { + margin: var(--universal-margin); } + +figcaption { + color: var(--secondary-fore-color); } + +a { + text-decoration: none; } + a:link { + color: var(--a-link-color); } + a:visited { + color: var(--a-visited-color); } + a:hover, a:focus { + text-decoration: underline; } + +/* + Definitions for the grid system, cards and containers. +*/ +.container { + margin: 0 auto; + padding: 0 calc(1.5 * var(--universal-padding)); } + +.row { + box-sizing: border-box; + display: flex; + flex: 0 1 auto; + flex-flow: row wrap; + margin: 0 0 0 var(--background-margin); } + +.col-sm, +[class^='col-sm-'], +[class^='col-sm-offset-'], +.row[class*='cols-sm-'] > * { + box-sizing: border-box; + flex: 0 0 auto; + padding: 0 calc(var(--universal-padding) / 2); } + +.col-sm, +.row.cols-sm > * { + max-width: 100%; + flex-grow: 1; + flex-basis: 0; } + +.col-sm-1, +.row.cols-sm-1 > * { + max-width: 8.3333333333%; + flex-basis: 8.3333333333%; } + +.col-sm-offset-0 { + margin-left: 0; } + +.col-sm-2, +.row.cols-sm-2 > * { + max-width: 16.6666666667%; + flex-basis: 16.6666666667%; } + +.col-sm-offset-1 { + margin-left: 8.3333333333%; } + +.col-sm-3, +.row.cols-sm-3 > * { + max-width: 25%; + flex-basis: 25%; } + +.col-sm-offset-2 { + margin-left: 16.6666666667%; } + +.col-sm-4, +.row.cols-sm-4 > * { + max-width: 33.3333333333%; + flex-basis: 33.3333333333%; } + +.col-sm-offset-3 { + margin-left: 25%; } + +.col-sm-5, +.row.cols-sm-5 > * { + max-width: 41.6666666667%; + flex-basis: 41.6666666667%; } + +.col-sm-offset-4 { + margin-left: 33.3333333333%; } + +.col-sm-6, +.row.cols-sm-6 > * { + max-width: 50%; + flex-basis: 50%; } + +.col-sm-offset-5 { + margin-left: 41.6666666667%; } + +.col-sm-7, +.row.cols-sm-7 > * { + max-width: 58.3333333333%; + flex-basis: 58.3333333333%; } + +.col-sm-offset-6 { + margin-left: 50%; } + +.col-sm-8, +.row.cols-sm-8 > * { + max-width: 66.6666666667%; + flex-basis: 66.6666666667%; } + +.col-sm-offset-7 { + margin-left: 58.3333333333%; } + +.col-sm-9, +.row.cols-sm-9 > * { + max-width: 75%; + flex-basis: 75%; } + +.col-sm-offset-8 { + margin-left: 66.6666666667%; } + +.col-sm-10, +.row.cols-sm-10 > * { + max-width: 83.3333333333%; + flex-basis: 83.3333333333%; } + +.col-sm-offset-9 { + margin-left: 75%; } + +.col-sm-11, +.row.cols-sm-11 > * { + max-width: 91.6666666667%; + flex-basis: 91.6666666667%; } + +.col-sm-offset-10 { + margin-left: 83.3333333333%; } + +.col-sm-12, +.row.cols-sm-12 > * { + max-width: 100%; + flex-basis: 100%; } + +.col-sm-offset-11 { + margin-left: 91.6666666667%; } + +.col-sm-normal { + order: initial; } + +.col-sm-first { + order: -999; } + +.col-sm-last { + order: 999; } + +@media screen and (min-width: 500px) { + .col-md, + [class^='col-md-'], + [class^='col-md-offset-'], + .row[class*='cols-md-'] > * { + box-sizing: border-box; + flex: 0 0 auto; + padding: 0 calc(var(--universal-padding) / 2); } + + .col-md, + .row.cols-md > * { + max-width: 100%; + flex-grow: 1; + flex-basis: 0; } + + .col-md-1, + .row.cols-md-1 > * { + max-width: 8.3333333333%; + flex-basis: 8.3333333333%; } + + .col-md-offset-0 { + margin-left: 0; } + + .col-md-2, + .row.cols-md-2 > * { + max-width: 16.6666666667%; + flex-basis: 16.6666666667%; } + + .col-md-offset-1 { + margin-left: 8.3333333333%; } + + .col-md-3, + .row.cols-md-3 > * { + max-width: 25%; + flex-basis: 25%; } + + .col-md-offset-2 { + margin-left: 16.6666666667%; } + + .col-md-4, + .row.cols-md-4 > * { + max-width: 33.3333333333%; + flex-basis: 33.3333333333%; } + + .col-md-offset-3 { + margin-left: 25%; } + + .col-md-5, + .row.cols-md-5 > * { + max-width: 41.6666666667%; + flex-basis: 41.6666666667%; } + + .col-md-offset-4 { + margin-left: 33.3333333333%; } + + .col-md-6, + .row.cols-md-6 > * { + max-width: 50%; + flex-basis: 50%; } + + .col-md-offset-5 { + margin-left: 41.6666666667%; } + + .col-md-7, + .row.cols-md-7 > * { + max-width: 58.3333333333%; + flex-basis: 58.3333333333%; } + + .col-md-offset-6 { + margin-left: 50%; } + + .col-md-8, + .row.cols-md-8 > * { + max-width: 66.6666666667%; + flex-basis: 66.6666666667%; } + + .col-md-offset-7 { + margin-left: 58.3333333333%; } + + .col-md-9, + .row.cols-md-9 > * { + max-width: 75%; + flex-basis: 75%; } + + .col-md-offset-8 { + margin-left: 66.6666666667%; } + + .col-md-10, + .row.cols-md-10 > * { + max-width: 83.3333333333%; + flex-basis: 83.3333333333%; } + + .col-md-offset-9 { + margin-left: 75%; } + + .col-md-11, + .row.cols-md-11 > * { + max-width: 91.6666666667%; + flex-basis: 91.6666666667%; } + + .col-md-offset-10 { + margin-left: 83.3333333333%; } + + .col-md-12, + .row.cols-md-12 > * { + max-width: 100%; + flex-basis: 100%; } + + .col-md-offset-11 { + margin-left: 91.6666666667%; } + + .col-md-normal { + order: initial; } + + .col-md-first { + order: -999; } + + .col-md-last { + order: 999; } } +@media screen and (min-width: 1280px) { + .col-lg, + [class^='col-lg-'], + [class^='col-lg-offset-'], + .row[class*='cols-lg-'] > * { + box-sizing: border-box; + flex: 0 0 auto; + padding: 0 calc(var(--universal-padding) / 2); } + + .col-lg, + .row.cols-lg > * { + max-width: 100%; + flex-grow: 1; + flex-basis: 0; } + + .col-lg-1, + .row.cols-lg-1 > * { + max-width: 8.3333333333%; + flex-basis: 8.3333333333%; } + + .col-lg-offset-0 { + margin-left: 0; } + + .col-lg-2, + .row.cols-lg-2 > * { + max-width: 16.6666666667%; + flex-basis: 16.6666666667%; } + + .col-lg-offset-1 { + margin-left: 8.3333333333%; } + + .col-lg-3, + .row.cols-lg-3 > * { + max-width: 25%; + flex-basis: 25%; } + + .col-lg-offset-2 { + margin-left: 16.6666666667%; } + + .col-lg-4, + .row.cols-lg-4 > * { + max-width: 33.3333333333%; + flex-basis: 33.3333333333%; } + + .col-lg-offset-3 { + margin-left: 25%; } + + .col-lg-5, + .row.cols-lg-5 > * { + max-width: 41.6666666667%; + flex-basis: 41.6666666667%; } + + .col-lg-offset-4 { + margin-left: 33.3333333333%; } + + .col-lg-6, + .row.cols-lg-6 > * { + max-width: 50%; + flex-basis: 50%; } + + .col-lg-offset-5 { + margin-left: 41.6666666667%; } + + .col-lg-7, + .row.cols-lg-7 > * { + max-width: 58.3333333333%; + flex-basis: 58.3333333333%; } + + .col-lg-offset-6 { + margin-left: 50%; } + + .col-lg-8, + .row.cols-lg-8 > * { + max-width: 66.6666666667%; + flex-basis: 66.6666666667%; } + + .col-lg-offset-7 { + margin-left: 58.3333333333%; } + + .col-lg-9, + .row.cols-lg-9 > * { + max-width: 75%; + flex-basis: 75%; } + + .col-lg-offset-8 { + margin-left: 66.6666666667%; } + + .col-lg-10, + .row.cols-lg-10 > * { + max-width: 83.3333333333%; + flex-basis: 83.3333333333%; } + + .col-lg-offset-9 { + margin-left: 75%; } + + .col-lg-11, + .row.cols-lg-11 > * { + max-width: 91.6666666667%; + flex-basis: 91.6666666667%; } + + .col-lg-offset-10 { + margin-left: 83.3333333333%; } + + .col-lg-12, + .row.cols-lg-12 > * { + max-width: 100%; + flex-basis: 100%; } + + .col-lg-offset-11 { + margin-left: 91.6666666667%; } + + .col-lg-normal { + order: initial; } + + .col-lg-first { + order: -999; } + + .col-lg-last { + order: 999; } } +/* Card component CSS variable definitions */ +:root { + --card-back-color: #3cb4e6; + --card-fore-color: #03234b; + --card-border-color: #03234b; } + +.card { + display: flex; + flex-direction: column; + justify-content: space-between; + align-self: center; + position: relative; + width: 100%; + background: var(--card-back-color); + color: var(--card-fore-color); + border: 0.0714285714rem solid var(--card-border-color); + border-radius: var(--universal-border-radius); + margin: var(--universal-margin); + overflow: hidden; } + @media screen and (min-width: 320px) { + .card { + max-width: 320px; } } + .card > .sectione { + background: var(--card-back-color); + color: var(--card-fore-color); + box-sizing: border-box; + margin: 0; + border: 0; + border-radius: 0; + border-bottom: 0.0714285714rem solid var(--card-border-color); + padding: var(--universal-padding); + width: 100%; } + .card > .sectione.media { + height: 200px; + padding: 0; + -o-object-fit: cover; + object-fit: cover; } + .card > .sectione:last-child { + border-bottom: 0; } + +/* + Custom elements for card elements. +*/ +@media screen and (min-width: 240px) { + .card.small { + max-width: 240px; } } +@media screen and (min-width: 480px) { + .card.large { + max-width: 480px; } } +.card.fluid { + max-width: 100%; + width: auto; } + +.card.warning { + --card-back-color: #e5b8b7; + --card-fore-color: #3b234b; + --card-border-color: #8c0078; } + +.card.error { + --card-back-color: #464650; + --card-fore-color: #ffffff; + --card-border-color: #8c0078; } + +.card > .sectione.dark { + --card-back-color: #3b234b; + --card-fore-color: #ffffff; } + +.card > .sectione.double-padded { + padding: calc(1.5 * var(--universal-padding)); } + +/* + Definitions for forms and input elements. +*/ +/* Input_control module CSS variable definitions */ +:root { + --form-back-color: #ffe97f; + --form-fore-color: #03234b; + --form-border-color: #3cb4e6; + --input-back-color: #ffffff; + --input-fore-color: #03234b; + --input-border-color: #3cb4e6; + --input-focus-color: #0288d1; + --input-invalid-color: #d32f2f; + --button-back-color: #e2e2e2; + --button-hover-back-color: #dcdcdc; + --button-fore-color: #212121; + --button-border-color: transparent; + --button-hover-border-color: transparent; + --button-group-border-color: rgba(124, 124, 124, 0.54); } + +form { + background: var(--form-back-color); + color: var(--form-fore-color); + border: 0.0714285714rem solid var(--form-border-color); + border-radius: var(--universal-border-radius); + margin: var(--universal-margin); + padding: calc(2 * var(--universal-padding)) var(--universal-padding); } + +fieldset { + border: 0.0714285714rem solid var(--form-border-color); + border-radius: var(--universal-border-radius); + margin: calc(var(--universal-margin) / 4); + padding: var(--universal-padding); } + +legend { + box-sizing: border-box; + display: table; + max-width: 100%; + white-space: normal; + font-weight: 500; + padding: calc(var(--universal-padding) / 2); } + +label { + padding: calc(var(--universal-padding) / 2) var(--universal-padding); } + +.input-group { + display: inline-block; } + .input-group.fluid { + display: flex; + align-items: center; + justify-content: center; } + .input-group.fluid > input { + max-width: 100%; + flex-grow: 1; + flex-basis: 0px; } + @media screen and (max-width: 499px) { + .input-group.fluid { + align-items: stretch; + flex-direction: column; } } + .input-group.vertical { + display: flex; + align-items: stretch; + flex-direction: column; } + .input-group.vertical > input { + max-width: 100%; + flex-grow: 1; + flex-basis: 0px; } + +[type="number"]::-webkit-inner-spin-button, [type="number"]::-webkit-outer-spin-button { + height: auto; } + +[type="search"] { + -webkit-appearance: textfield; + outline-offset: -2px; } + +[type="search"]::-webkit-search-cancel-button, +[type="search"]::-webkit-search-decoration { + -webkit-appearance: none; } + +input:not([type]), [type="text"], [type="email"], [type="number"], [type="search"], +[type="password"], [type="url"], [type="tel"], [type="checkbox"], [type="radio"], textarea, select { + box-sizing: border-box; + background: var(--input-back-color); + color: var(--input-fore-color); + border: 0.0714285714rem solid var(--input-border-color); + border-radius: var(--universal-border-radius); + margin: calc(var(--universal-margin) / 2); + padding: var(--universal-padding) calc(1.5 * var(--universal-padding)); } + +input:not([type="button"]):not([type="submit"]):not([type="reset"]):hover, input:not([type="button"]):not([type="submit"]):not([type="reset"]):focus, textarea:hover, textarea:focus, select:hover, select:focus { + border-color: var(--input-focus-color); + box-shadow: none; } +input:not([type="button"]):not([type="submit"]):not([type="reset"]):invalid, input:not([type="button"]):not([type="submit"]):not([type="reset"]):focus:invalid, textarea:invalid, textarea:focus:invalid, select:invalid, select:focus:invalid { + border-color: var(--input-invalid-color); + box-shadow: none; } +input:not([type="button"]):not([type="submit"]):not([type="reset"])[readonly], textarea[readonly], select[readonly] { + background: var(--secondary-back-color); } + +select { + max-width: 100%; } + +option { + overflow: hidden; + text-overflow: ellipsis; } + +[type="checkbox"], [type="radio"] { + -webkit-appearance: none; + -moz-appearance: none; + appearance: none; + position: relative; + height: calc(1rem + var(--universal-padding) / 2); + width: calc(1rem + var(--universal-padding) / 2); + vertical-align: text-bottom; + padding: 0; + flex-basis: calc(1rem + var(--universal-padding) / 2) !important; + flex-grow: 0 !important; } + [type="checkbox"]:checked:before, [type="radio"]:checked:before { + position: absolute; } + +[type="checkbox"]:checked:before { + content: '\2713'; + font-family: sans-serif; + font-size: calc(1rem + var(--universal-padding) / 2); + top: calc(0rem - var(--universal-padding)); + left: calc(var(--universal-padding) / 4); } + +[type="radio"] { + border-radius: 100%; } + [type="radio"]:checked:before { + border-radius: 100%; + content: ''; + top: calc(0.0714285714rem + var(--universal-padding) / 2); + left: calc(0.0714285714rem + var(--universal-padding) / 2); + background: var(--input-fore-color); + width: 0.5rem; + height: 0.5rem; } + +:placeholder-shown { + color: var(--input-fore-color); } + +::-ms-placeholder { + color: var(--input-fore-color); + opacity: 0.54; } + +button::-moz-focus-inner, [type="button"]::-moz-focus-inner, [type="reset"]::-moz-focus-inner, [type="submit"]::-moz-focus-inner { + border-style: none; + padding: 0; } + +button, html [type="button"], [type="reset"], [type="submit"] { + -webkit-appearance: button; } + +button { + overflow: visible; + text-transform: none; } + +button, [type="button"], [type="submit"], [type="reset"], +a.button, label.button, .button, +a[role="button"], label[role="button"], [role="button"] { + display: inline-block; + background: var(--button-back-color); + color: var(--button-fore-color); + border: 0.0714285714rem solid var(--button-border-color); + border-radius: var(--universal-border-radius); + padding: var(--universal-padding) calc(1.5 * var(--universal-padding)); + margin: var(--universal-margin); + text-decoration: none; + cursor: pointer; + transition: background 0.3s; } + button:hover, button:focus, [type="button"]:hover, [type="button"]:focus, [type="submit"]:hover, [type="submit"]:focus, [type="reset"]:hover, [type="reset"]:focus, + a.button:hover, + a.button:focus, label.button:hover, label.button:focus, .button:hover, .button:focus, + a[role="button"]:hover, + a[role="button"]:focus, label[role="button"]:hover, label[role="button"]:focus, [role="button"]:hover, [role="button"]:focus { + background: var(--button-hover-back-color); + border-color: var(--button-hover-border-color); } + +input:disabled, input[disabled], textarea:disabled, textarea[disabled], select:disabled, select[disabled], button:disabled, button[disabled], .button:disabled, .button[disabled], [role="button"]:disabled, [role="button"][disabled] { + cursor: not-allowed; + opacity: 0.75; } + +.button-group { + display: flex; + border: 0.0714285714rem solid var(--button-group-border-color); + border-radius: var(--universal-border-radius); + margin: var(--universal-margin); } + .button-group > button, .button-group [type="button"], .button-group > [type="submit"], .button-group > [type="reset"], .button-group > .button, .button-group > [role="button"] { + margin: 0; + max-width: 100%; + flex: 1 1 auto; + text-align: center; + border: 0; + border-radius: 0; + box-shadow: none; } + .button-group > :not(:first-child) { + border-left: 0.0714285714rem solid var(--button-group-border-color); } + @media screen and (max-width: 499px) { + .button-group { + flex-direction: column; } + .button-group > :not(:first-child) { + border: 0; + border-top: 0.0714285714rem solid var(--button-group-border-color); } } + +/* + Custom elements for forms and input elements. +*/ +button.primary, [type="button"].primary, [type="submit"].primary, [type="reset"].primary, .button.primary, [role="button"].primary { + --button-back-color: #1976d2; + --button-fore-color: #f8f8f8; } + button.primary:hover, button.primary:focus, [type="button"].primary:hover, [type="button"].primary:focus, [type="submit"].primary:hover, [type="submit"].primary:focus, [type="reset"].primary:hover, [type="reset"].primary:focus, .button.primary:hover, .button.primary:focus, [role="button"].primary:hover, [role="button"].primary:focus { + --button-hover-back-color: #1565c0; } + +button.secondary, [type="button"].secondary, [type="submit"].secondary, [type="reset"].secondary, .button.secondary, [role="button"].secondary { + --button-back-color: #d32f2f; + --button-fore-color: #f8f8f8; } + button.secondary:hover, button.secondary:focus, [type="button"].secondary:hover, [type="button"].secondary:focus, [type="submit"].secondary:hover, [type="submit"].secondary:focus, [type="reset"].secondary:hover, [type="reset"].secondary:focus, .button.secondary:hover, .button.secondary:focus, [role="button"].secondary:hover, [role="button"].secondary:focus { + --button-hover-back-color: #c62828; } + +button.tertiary, [type="button"].tertiary, [type="submit"].tertiary, [type="reset"].tertiary, .button.tertiary, [role="button"].tertiary { + --button-back-color: #308732; + --button-fore-color: #f8f8f8; } + button.tertiary:hover, button.tertiary:focus, [type="button"].tertiary:hover, [type="button"].tertiary:focus, [type="submit"].tertiary:hover, [type="submit"].tertiary:focus, [type="reset"].tertiary:hover, [type="reset"].tertiary:focus, .button.tertiary:hover, .button.tertiary:focus, [role="button"].tertiary:hover, [role="button"].tertiary:focus { + --button-hover-back-color: #277529; } + +button.inverse, [type="button"].inverse, [type="submit"].inverse, [type="reset"].inverse, .button.inverse, [role="button"].inverse { + --button-back-color: #212121; + --button-fore-color: #f8f8f8; } + button.inverse:hover, button.inverse:focus, [type="button"].inverse:hover, [type="button"].inverse:focus, [type="submit"].inverse:hover, [type="submit"].inverse:focus, [type="reset"].inverse:hover, [type="reset"].inverse:focus, .button.inverse:hover, .button.inverse:focus, [role="button"].inverse:hover, [role="button"].inverse:focus { + --button-hover-back-color: #111; } + +button.small, [type="button"].small, [type="submit"].small, [type="reset"].small, .button.small, [role="button"].small { + padding: calc(0.5 * var(--universal-padding)) calc(0.75 * var(--universal-padding)); + margin: var(--universal-margin); } + +button.large, [type="button"].large, [type="submit"].large, [type="reset"].large, .button.large, [role="button"].large { + padding: calc(1.5 * var(--universal-padding)) calc(2 * var(--universal-padding)); + margin: var(--universal-margin); } + +/* + Definitions for navigation elements. +*/ +/* Navigation module CSS variable definitions */ +:root { + --header-back-color: #03234b; + --header-hover-back-color: #ffd200; + --header-fore-color: #ffffff; + --header-border-color: #3cb4e6; + --nav-back-color: #ffffff; + --nav-hover-back-color: #ffe97f; + --nav-fore-color: #e6007e; + --nav-border-color: #3cb4e6; + --nav-link-color: #3cb4e6; + --footer-fore-color: #ffffff; + --footer-back-color: #03234b; + --footer-border-color: #3cb4e6; + --footer-link-color: #3cb4e6; + --drawer-back-color: #ffffff; + --drawer-hover-back-color: #ffe97f; + --drawer-border-color: #3cb4e6; + --drawer-close-color: #e6007e; } + +header { + height: 2.75rem; + background: var(--header-back-color); + color: var(--header-fore-color); + border-bottom: 0.0714285714rem solid var(--header-border-color); + padding: calc(var(--universal-padding) / 4) 0; + white-space: nowrap; + overflow-x: auto; + overflow-y: hidden; } + header.row { + box-sizing: content-box; } + header .logo { + color: var(--header-fore-color); + font-size: 1.75rem; + padding: var(--universal-padding) calc(2 * var(--universal-padding)); + text-decoration: none; } + header button, header [type="button"], header .button, header [role="button"] { + box-sizing: border-box; + position: relative; + top: calc(0rem - var(--universal-padding) / 4); + height: calc(3.1875rem + var(--universal-padding) / 2); + background: var(--header-back-color); + line-height: calc(3.1875rem - var(--universal-padding) * 1.5); + text-align: center; + color: var(--header-fore-color); + border: 0; + border-radius: 0; + margin: 0; + text-transform: uppercase; } + header button:hover, header button:focus, header [type="button"]:hover, header [type="button"]:focus, header .button:hover, header .button:focus, header [role="button"]:hover, header [role="button"]:focus { + background: var(--header-hover-back-color); } + +nav { + background: var(--nav-back-color); + color: var(--nav-fore-color); + border: 0.0714285714rem solid var(--nav-border-color); + border-radius: var(--universal-border-radius); + margin: var(--universal-margin); } + nav * { + padding: var(--universal-padding) calc(1.5 * var(--universal-padding)); } + nav a, nav a:visited { + display: block; + color: var(--nav-link-color); + border-radius: var(--universal-border-radius); + transition: background 0.3s; } + nav a:hover, nav a:focus, nav a:visited:hover, nav a:visited:focus { + text-decoration: none; + background: var(--nav-hover-back-color); } + nav .sublink-1 { + position: relative; + margin-left: calc(2 * var(--universal-padding)); } + nav .sublink-1:before { + position: absolute; + left: calc(var(--universal-padding) - 1 * var(--universal-padding)); + top: -0.0714285714rem; + content: ''; + height: 100%; + border: 0.0714285714rem solid var(--nav-border-color); + border-left: 0; } + nav .sublink-2 { + position: relative; + margin-left: calc(4 * var(--universal-padding)); } + nav .sublink-2:before { + position: absolute; + left: calc(var(--universal-padding) - 3 * var(--universal-padding)); + top: -0.0714285714rem; + content: ''; + height: 100%; + border: 0.0714285714rem solid var(--nav-border-color); + border-left: 0; } + +footer { + background: var(--footer-back-color); + color: var(--footer-fore-color); + border-top: 0.0714285714rem solid var(--footer-border-color); + padding: calc(2 * var(--universal-padding)) var(--universal-padding); + font-size: 0.875rem; } + footer a, footer a:visited { + color: var(--footer-link-color); } + +header.sticky { + position: -webkit-sticky; + position: sticky; + z-index: 1101; + top: 0; } + +footer.sticky { + position: -webkit-sticky; + position: sticky; + z-index: 1101; + bottom: 0; } + +.drawer-toggle:before { + display: inline-block; + position: relative; + vertical-align: bottom; + content: '\00a0\2261\00a0'; + font-family: sans-serif; + font-size: 1.5em; } +@media screen and (min-width: 500px) { + .drawer-toggle:not(.persistent) { + display: none; } } + +[type="checkbox"].drawer { + height: 1px; + width: 1px; + margin: -1px; + overflow: hidden; + position: absolute; + clip: rect(0 0 0 0); + -webkit-clip-path: inset(100%); + clip-path: inset(100%); } + [type="checkbox"].drawer + * { + display: block; + box-sizing: border-box; + position: fixed; + top: 0; + width: 320px; + height: 100vh; + overflow-y: auto; + background: var(--drawer-back-color); + border: 0.0714285714rem solid var(--drawer-border-color); + border-radius: 0; + margin: 0; + z-index: 1110; + right: -320px; + transition: right 0.3s; } + [type="checkbox"].drawer + * .drawer-close { + position: absolute; + top: var(--universal-margin); + right: var(--universal-margin); + z-index: 1111; + width: 2rem; + height: 2rem; + border-radius: var(--universal-border-radius); + padding: var(--universal-padding); + margin: 0; + cursor: pointer; + transition: background 0.3s; } + [type="checkbox"].drawer + * .drawer-close:before { + display: block; + content: '\00D7'; + color: var(--drawer-close-color); + position: relative; + font-family: sans-serif; + font-size: 2rem; + line-height: 1; + text-align: center; } + [type="checkbox"].drawer + * .drawer-close:hover, [type="checkbox"].drawer + * .drawer-close:focus { + background: var(--drawer-hover-back-color); } + @media screen and (max-width: 320px) { + [type="checkbox"].drawer + * { + width: 100%; } } + [type="checkbox"].drawer:checked + * { + right: 0; } + @media screen and (min-width: 500px) { + [type="checkbox"].drawer:not(.persistent) + * { + position: static; + height: 100%; + z-index: 1100; } + [type="checkbox"].drawer:not(.persistent) + * .drawer-close { + display: none; } } + +/* + Definitions for the responsive table component. +*/ +/* Table module CSS variable definitions. */ +:root { + --table-border-color: #03234b; + --table-border-separator-color: #03234b; + --table-head-back-color: #03234b; + --table-head-fore-color: #ffffff; + --table-body-back-color: #ffffff; + --table-body-fore-color: #03234b; + --table-body-alt-back-color: #f4f4f4; } + +table { + border-collapse: separate; + border-spacing: 0; + margin: 0; + display: flex; + flex: 0 1 auto; + flex-flow: row wrap; + padding: var(--universal-padding); + padding-top: 0; } + table caption { + font-size: 1rem; + margin: calc(2 * var(--universal-margin)) 0; + max-width: 100%; + flex: 0 0 100%; } + table thead, table tbody { + display: flex; + flex-flow: row wrap; + border: 0.0714285714rem solid var(--table-border-color); } + table thead { + z-index: 999; + border-radius: var(--universal-border-radius) var(--universal-border-radius) 0 0; + border-bottom: 0.0714285714rem solid var(--table-border-separator-color); } + table tbody { + border-top: 0; + margin-top: calc(0 - var(--universal-margin)); + border-radius: 0 0 var(--universal-border-radius) var(--universal-border-radius); } + table tr { + display: flex; + padding: 0; } + table th, table td { + padding: calc(0.5 * var(--universal-padding)); + font-size: 0.9rem; } + table th { + text-align: left; + background: var(--table-head-back-color); + color: var(--table-head-fore-color); } + table td { + background: var(--table-body-back-color); + color: var(--table-body-fore-color); + border-top: 0.0714285714rem solid var(--table-border-color); } + +table:not(.horizontal) { + overflow: auto; + max-height: 100%; } + table:not(.horizontal) thead, table:not(.horizontal) tbody { + max-width: 100%; + flex: 0 0 100%; } + table:not(.horizontal) tr { + flex-flow: row wrap; + flex: 0 0 100%; } + table:not(.horizontal) th, table:not(.horizontal) td { + flex: 1 0 0%; + overflow: hidden; + text-overflow: ellipsis; } + table:not(.horizontal) thead { + position: sticky; + top: 0; } + table:not(.horizontal) tbody tr:first-child td { + border-top: 0; } + +table.horizontal { + border: 0; } + table.horizontal thead, table.horizontal tbody { + border: 0; + flex: .2 0 0; + flex-flow: row nowrap; } + table.horizontal tbody { + overflow: auto; + justify-content: space-between; + flex: .8 0 0; + margin-left: 0; + padding-bottom: calc(var(--universal-padding) / 4); } + table.horizontal tr { + flex-direction: column; + flex: 1 0 auto; } + table.horizontal th, table.horizontal td { + width: auto; + border: 0; + border-bottom: 0.0714285714rem solid var(--table-border-color); } + table.horizontal th:not(:first-child), table.horizontal td:not(:first-child) { + border-top: 0; } + table.horizontal th { + text-align: right; + border-left: 0.0714285714rem solid var(--table-border-color); + border-right: 0.0714285714rem solid var(--table-border-separator-color); } + table.horizontal thead tr:first-child { + padding-left: 0; } + table.horizontal th:first-child, table.horizontal td:first-child { + border-top: 0.0714285714rem solid var(--table-border-color); } + table.horizontal tbody tr:last-child td { + border-right: 0.0714285714rem solid var(--table-border-color); } + table.horizontal tbody tr:last-child td:first-child { + border-top-right-radius: 0.25rem; } + table.horizontal tbody tr:last-child td:last-child { + border-bottom-right-radius: 0.25rem; } + table.horizontal thead tr:first-child th:first-child { + border-top-left-radius: 0.25rem; } + table.horizontal thead tr:first-child th:last-child { + border-bottom-left-radius: 0.25rem; } + +@media screen and (max-width: 499px) { + table, table.horizontal { + border-collapse: collapse; + border: 0; + width: 100%; + display: table; } + table thead, table th, table.horizontal thead, table.horizontal th { + border: 0; + height: 1px; + width: 1px; + margin: -1px; + overflow: hidden; + padding: 0; + position: absolute; + clip: rect(0 0 0 0); + -webkit-clip-path: inset(100%); + clip-path: inset(100%); } + table tbody, table.horizontal tbody { + border: 0; + display: table-row-group; } + table tr, table.horizontal tr { + display: block; + border: 0.0714285714rem solid var(--table-border-color); + border-radius: var(--universal-border-radius); + background: #ffffff; + padding: var(--universal-padding); + margin: var(--universal-margin); + margin-bottom: calc(1 * var(--universal-margin)); } + table th, table td, table.horizontal th, table.horizontal td { + width: auto; } + table td, table.horizontal td { + display: block; + border: 0; + text-align: right; } + table td:before, table.horizontal td:before { + content: attr(data-label); + float: left; + font-weight: 600; } + table th:first-child, table td:first-child, table.horizontal th:first-child, table.horizontal td:first-child { + border-top: 0; } + table tbody tr:last-child td, table.horizontal tbody tr:last-child td { + border-right: 0; } } +table tr:nth-of-type(2n) > td { + background: var(--table-body-alt-back-color); } + +@media screen and (max-width: 500px) { + table tr:nth-of-type(2n) { + background: var(--table-body-alt-back-color); } } +:root { + --table-body-hover-back-color: #90caf9; } + +table.hoverable tr:hover, table.hoverable tr:hover > td, table.hoverable tr:focus, table.hoverable tr:focus > td { + background: var(--table-body-hover-back-color); } + +@media screen and (max-width: 500px) { + table.hoverable tr:hover, table.hoverable tr:hover > td, table.hoverable tr:focus, table.hoverable tr:focus > td { + background: var(--table-body-hover-back-color); } } +/* + Definitions for contextual background elements, toasts and tooltips. +*/ +/* Contextual module CSS variable definitions */ +:root { + --mark-back-color: #3cb4e6; + --mark-fore-color: #ffffff; } + +mark { + background: var(--mark-back-color); + color: var(--mark-fore-color); + font-size: 0.95em; + line-height: 1em; + border-radius: var(--universal-border-radius); + padding: calc(var(--universal-padding) / 4) var(--universal-padding); } + mark.inline-block { + display: inline-block; + font-size: 1em; + line-height: 1.4; + padding: calc(var(--universal-padding) / 2) var(--universal-padding); } + +:root { + --toast-back-color: #424242; + --toast-fore-color: #fafafa; } + +.toast { + position: fixed; + bottom: calc(var(--universal-margin) * 3); + left: 50%; + transform: translate(-50%, -50%); + z-index: 1111; + color: var(--toast-fore-color); + background: var(--toast-back-color); + border-radius: calc(var(--universal-border-radius) * 16); + padding: var(--universal-padding) calc(var(--universal-padding) * 3); } + +:root { + --tooltip-back-color: #212121; + --tooltip-fore-color: #fafafa; } + +.tooltip { + position: relative; + display: inline-block; } + .tooltip:before, .tooltip:after { + position: absolute; + opacity: 0; + clip: rect(0 0 0 0); + -webkit-clip-path: inset(100%); + clip-path: inset(100%); + transition: all 0.3s; + z-index: 1010; + left: 50%; } + .tooltip:not(.bottom):before, .tooltip:not(.bottom):after { + bottom: 75%; } + .tooltip.bottom:before, .tooltip.bottom:after { + top: 75%; } + .tooltip:hover:before, .tooltip:hover:after, .tooltip:focus:before, .tooltip:focus:after { + opacity: 1; + clip: auto; + -webkit-clip-path: inset(0%); + clip-path: inset(0%); } + .tooltip:before { + content: ''; + background: transparent; + border: var(--universal-margin) solid transparent; + left: calc(50% - var(--universal-margin)); } + .tooltip:not(.bottom):before { + border-top-color: #212121; } + .tooltip.bottom:before { + border-bottom-color: #212121; } + .tooltip:after { + content: attr(aria-label); + color: var(--tooltip-fore-color); + background: var(--tooltip-back-color); + border-radius: var(--universal-border-radius); + padding: var(--universal-padding); + white-space: nowrap; + transform: translateX(-50%); } + .tooltip:not(.bottom):after { + margin-bottom: calc(2 * var(--universal-margin)); } + .tooltip.bottom:after { + margin-top: calc(2 * var(--universal-margin)); } + +:root { + --modal-overlay-color: rgba(0, 0, 0, 0.45); + --modal-close-color: #e6007e; + --modal-close-hover-color: #ffe97f; } + +[type="checkbox"].modal { + height: 1px; + width: 1px; + margin: -1px; + overflow: hidden; + position: absolute; + clip: rect(0 0 0 0); + -webkit-clip-path: inset(100%); + clip-path: inset(100%); } + [type="checkbox"].modal + div { + position: fixed; + top: 0; + left: 0; + display: none; + width: 100vw; + height: 100vh; + background: var(--modal-overlay-color); } + [type="checkbox"].modal + div .card { + margin: 0 auto; + max-height: 50vh; + overflow: auto; } + [type="checkbox"].modal + div .card .modal-close { + position: absolute; + top: 0; + right: 0; + width: 1.75rem; + height: 1.75rem; + border-radius: var(--universal-border-radius); + padding: var(--universal-padding); + margin: 0; + cursor: pointer; + transition: background 0.3s; } + [type="checkbox"].modal + div .card .modal-close:before { + display: block; + content: '\00D7'; + color: var(--modal-close-color); + position: relative; + font-family: sans-serif; + font-size: 1.75rem; + line-height: 1; + text-align: center; } + [type="checkbox"].modal + div .card .modal-close:hover, [type="checkbox"].modal + div .card .modal-close:focus { + background: var(--modal-close-hover-color); } + [type="checkbox"].modal:checked + div { + display: flex; + flex: 0 1 auto; + z-index: 1200; } + [type="checkbox"].modal:checked + div .card .modal-close { + z-index: 1211; } + +:root { + --collapse-label-back-color: #03234b; + --collapse-label-fore-color: #ffffff; + --collapse-label-hover-back-color: #3cb4e6; + --collapse-selected-label-back-color: #3cb4e6; + --collapse-border-color: var(--collapse-label-back-color); + --collapse-selected-border-color: #ceecf8; + --collapse-content-back-color: #ffffff; + --collapse-selected-label-border-color: #3cb4e6; } + +.collapse { + width: calc(100% - 2 * var(--universal-margin)); + opacity: 1; + display: flex; + flex-direction: column; + margin: var(--universal-margin); + border-radius: var(--universal-border-radius); } + .collapse > [type="radio"], .collapse > [type="checkbox"] { + height: 1px; + width: 1px; + margin: -1px; + overflow: hidden; + position: absolute; + clip: rect(0 0 0 0); + -webkit-clip-path: inset(100%); + clip-path: inset(100%); } + .collapse > label { + flex-grow: 1; + display: inline-block; + height: 1.25rem; + cursor: pointer; + transition: background 0.2s; + color: var(--collapse-label-fore-color); + background: var(--collapse-label-back-color); + border: 0.0714285714rem solid var(--collapse-selected-border-color); + padding: calc(1.25 * var(--universal-padding)); } + .collapse > label:hover, .collapse > label:focus { + background: var(--collapse-label-hover-back-color); } + .collapse > label + div { + flex-basis: auto; + height: 1px; + width: 1px; + margin: -1px; + overflow: hidden; + position: absolute; + clip: rect(0 0 0 0); + -webkit-clip-path: inset(100%); + clip-path: inset(100%); + transition: max-height 0.3s; + max-height: 1px; } + .collapse > :checked + label { + background: var(--collapse-selected-label-back-color); + border-color: var(--collapse-selected-label-border-color); } + .collapse > :checked + label + div { + box-sizing: border-box; + position: relative; + width: 100%; + height: auto; + overflow: auto; + margin: 0; + background: var(--collapse-content-back-color); + border: 0.0714285714rem solid var(--collapse-selected-border-color); + border-top: 0; + padding: var(--universal-padding); + clip: auto; + -webkit-clip-path: inset(0%); + clip-path: inset(0%); + max-height: 100%; } + .collapse > label:not(:first-of-type) { + border-top: 0; } + .collapse > label:first-of-type { + border-radius: var(--universal-border-radius) var(--universal-border-radius) 0 0; } + .collapse > label:last-of-type:not(:first-of-type) { + border-radius: 0 0 var(--universal-border-radius) var(--universal-border-radius); } + .collapse > label:last-of-type:first-of-type { + border-radius: var(--universal-border-radius); } + .collapse > :checked:last-of-type:not(:first-of-type) + label { + border-radius: 0; } + .collapse > :checked:last-of-type + label + div { + border-radius: 0 0 var(--universal-border-radius) var(--universal-border-radius); } + +/* + Custom elements for contextual background elements, toasts and tooltips. +*/ +mark.tertiary { + --mark-back-color: #3cb4e6; } + +mark.tag { + padding: calc(var(--universal-padding)/2) var(--universal-padding); + border-radius: 1em; } + +/* + Definitions for progress elements and spinners. +*/ +/* Progress module CSS variable definitions */ +:root { + --progress-back-color: #3cb4e6; + --progress-fore-color: #555; } + +progress { + display: block; + vertical-align: baseline; + -webkit-appearance: none; + -moz-appearance: none; + appearance: none; + height: 0.75rem; + width: calc(100% - 2 * var(--universal-margin)); + margin: var(--universal-margin); + border: 0; + border-radius: calc(2 * var(--universal-border-radius)); + background: var(--progress-back-color); + color: var(--progress-fore-color); } + progress::-webkit-progress-value { + background: var(--progress-fore-color); + border-top-left-radius: calc(2 * var(--universal-border-radius)); + border-bottom-left-radius: calc(2 * var(--universal-border-radius)); } + progress::-webkit-progress-bar { + background: var(--progress-back-color); } + progress::-moz-progress-bar { + background: var(--progress-fore-color); + border-top-left-radius: calc(2 * var(--universal-border-radius)); + border-bottom-left-radius: calc(2 * var(--universal-border-radius)); } + progress[value="1000"]::-webkit-progress-value { + border-radius: calc(2 * var(--universal-border-radius)); } + progress[value="1000"]::-moz-progress-bar { + border-radius: calc(2 * var(--universal-border-radius)); } + progress.inline { + display: inline-block; + vertical-align: middle; + width: 60%; } + +:root { + --spinner-back-color: #ddd; + --spinner-fore-color: #555; } + +@keyframes spinner-donut-anim { + 0% { + transform: rotate(0deg); } + 100% { + transform: rotate(360deg); } } +.spinner { + display: inline-block; + margin: var(--universal-margin); + border: 0.25rem solid var(--spinner-back-color); + border-left: 0.25rem solid var(--spinner-fore-color); + border-radius: 50%; + width: 1.25rem; + height: 1.25rem; + animation: spinner-donut-anim 1.2s linear infinite; } + +/* + Custom elements for progress bars and spinners. +*/ +progress.primary { + --progress-fore-color: #1976d2; } + +progress.secondary { + --progress-fore-color: #d32f2f; } + +progress.tertiary { + --progress-fore-color: #308732; } + +.spinner.primary { + --spinner-fore-color: #1976d2; } + +.spinner.secondary { + --spinner-fore-color: #d32f2f; } + +.spinner.tertiary { + --spinner-fore-color: #308732; } + +/* + Definitions for icons - powered by Feather (https://feathericons.com/). +*/ +span[class^='icon-'] { + display: inline-block; + height: 1em; + width: 1em; + vertical-align: -0.125em; + background-size: contain; + margin: 0 calc(var(--universal-margin) / 4); } + span[class^='icon-'].secondary { + -webkit-filter: invert(25%); + filter: invert(25%); } + span[class^='icon-'].inverse { + -webkit-filter: invert(100%); + filter: invert(100%); } + +span.icon-alert { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='8' x2='12' y2='12'%3E%3C/line%3E%3Cline x1='12' y1='16' x2='12' y2='16'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-bookmark { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M19 21l-7-5-7 5V5a2 2 0 0 1 2-2h10a2 2 0 0 1 2 2z'%3E%3C/path%3E%3C/svg%3E"); } +span.icon-calendar { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='3' y='4' width='18' height='18' rx='2' ry='2'%3E%3C/rect%3E%3Cline x1='16' y1='2' x2='16' y2='6'%3E%3C/line%3E%3Cline x1='8' y1='2' x2='8' y2='6'%3E%3C/line%3E%3Cline x1='3' y1='10' x2='21' y2='10'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-credit { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='1' y='4' width='22' height='16' rx='2' ry='2'%3E%3C/rect%3E%3Cline x1='1' y1='10' x2='23' y2='10'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-edit { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M20 14.66V20a2 2 0 0 1-2 2H4a2 2 0 0 1-2-2V6a2 2 0 0 1 2-2h5.34'%3E%3C/path%3E%3Cpolygon points='18 2 22 6 12 16 8 16 8 12 18 2'%3E%3C/polygon%3E%3C/svg%3E"); } +span.icon-link { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M18 13v6a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2V8a2 2 0 0 1 2-2h6'%3E%3C/path%3E%3Cpolyline points='15 3 21 3 21 9'%3E%3C/polyline%3E%3Cline x1='10' y1='14' x2='21' y2='3'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-help { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M9.09 9a3 3 0 0 1 5.83 1c0 2-3 3-3 3'%3E%3C/path%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='17' x2='12' y2='17'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-home { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M3 9l9-7 9 7v11a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2z'%3E%3C/path%3E%3Cpolyline points='9 22 9 12 15 12 15 22'%3E%3C/polyline%3E%3C/svg%3E"); } +span.icon-info { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='16' x2='12' y2='12'%3E%3C/line%3E%3Cline x1='12' y1='8' x2='12' y2='8'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-lock { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='3' y='11' width='18' height='11' rx='2' ry='2'%3E%3C/rect%3E%3Cpath d='M7 11V7a5 5 0 0 1 10 0v4'%3E%3C/path%3E%3C/svg%3E"); } +span.icon-mail { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M4 4h16c1.1 0 2 .9 2 2v12c0 1.1-.9 2-2 2H4c-1.1 0-2-.9-2-2V6c0-1.1.9-2 2-2z'%3E%3C/path%3E%3Cpolyline points='22,6 12,13 2,6'%3E%3C/polyline%3E%3C/svg%3E"); } +span.icon-location { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M21 10c0 7-9 13-9 13s-9-6-9-13a9 9 0 0 1 18 0z'%3E%3C/path%3E%3Ccircle cx='12' cy='10' r='3'%3E%3C/circle%3E%3C/svg%3E"); } +span.icon-phone { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M22 16.92v3a2 2 0 0 1-2.18 2 19.79 19.79 0 0 1-8.63-3.07 19.5 19.5 0 0 1-6-6 19.79 19.79 0 0 1-3.07-8.67A2 2 0 0 1 4.11 2h3a2 2 0 0 1 2 1.72 12.84 12.84 0 0 0 .7 2.81 2 2 0 0 1-.45 2.11L8.09 9.91a16 16 0 0 0 6 6l1.27-1.27a2 2 0 0 1 2.11-.45 12.84 12.84 0 0 0 2.81.7A2 2 0 0 1 22 16.92z'%3E%3C/path%3E%3C/svg%3E"); } +span.icon-rss { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M4 11a9 9 0 0 1 9 9'%3E%3C/path%3E%3Cpath d='M4 4a16 16 0 0 1 16 16'%3E%3C/path%3E%3Ccircle cx='5' cy='19' r='1'%3E%3C/circle%3E%3C/svg%3E"); } +span.icon-search { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='11' cy='11' r='8'%3E%3C/circle%3E%3Cline x1='21' y1='21' x2='16.65' y2='16.65'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-settings { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='3'%3E%3C/circle%3E%3Cpath d='M19.4 15a1.65 1.65 0 0 0 .33 1.82l.06.06a2 2 0 0 1 0 2.83 2 2 0 0 1-2.83 0l-.06-.06a1.65 1.65 0 0 0-1.82-.33 1.65 1.65 0 0 0-1 1.51V21a2 2 0 0 1-2 2 2 2 0 0 1-2-2v-.09A1.65 1.65 0 0 0 9 19.4a1.65 1.65 0 0 0-1.82.33l-.06.06a2 2 0 0 1-2.83 0 2 2 0 0 1 0-2.83l.06-.06a1.65 1.65 0 0 0 .33-1.82 1.65 1.65 0 0 0-1.51-1H3a2 2 0 0 1-2-2 2 2 0 0 1 2-2h.09A1.65 1.65 0 0 0 4.6 9a1.65 1.65 0 0 0-.33-1.82l-.06-.06a2 2 0 0 1 0-2.83 2 2 0 0 1 2.83 0l.06.06a1.65 1.65 0 0 0 1.82.33H9a1.65 1.65 0 0 0 1-1.51V3a2 2 0 0 1 2-2 2 2 0 0 1 2 2v.09a1.65 1.65 0 0 0 1 1.51 1.65 1.65 0 0 0 1.82-.33l.06-.06a2 2 0 0 1 2.83 0 2 2 0 0 1 0 2.83l-.06.06a1.65 1.65 0 0 0-.33 1.82V9a1.65 1.65 0 0 0 1.51 1H21a2 2 0 0 1 2 2 2 2 0 0 1-2 2h-.09a1.65 1.65 0 0 0-1.51 1z'%3E%3C/path%3E%3C/svg%3E"); } +span.icon-share { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='18' cy='5' r='3'%3E%3C/circle%3E%3Ccircle cx='6' cy='12' r='3'%3E%3C/circle%3E%3Ccircle cx='18' cy='19' r='3'%3E%3C/circle%3E%3Cline x1='8.59' y1='13.51' x2='15.42' y2='17.49'%3E%3C/line%3E%3Cline x1='15.41' y1='6.51' x2='8.59' y2='10.49'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-cart { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='9' cy='21' r='1'%3E%3C/circle%3E%3Ccircle cx='20' cy='21' r='1'%3E%3C/circle%3E%3Cpath d='M1 1h4l2.68 13.39a2 2 0 0 0 2 1.61h9.72a2 2 0 0 0 2-1.61L23 6H6'%3E%3C/path%3E%3C/svg%3E"); } +span.icon-upload { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M21 15v4a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2v-4'%3E%3C/path%3E%3Cpolyline points='17 8 12 3 7 8'%3E%3C/polyline%3E%3Cline x1='12' y1='3' x2='12' y2='15'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-user { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M20 21v-2a4 4 0 0 0-4-4H8a4 4 0 0 0-4 4v2'%3E%3C/path%3E%3Ccircle cx='12' cy='7' r='4'%3E%3C/circle%3E%3C/svg%3E"); } + +/* + Definitions for STMicroelectronics icons (https://brandportal.st.com/document/26). +*/ +span.icon-st-update { + background-image: url("Update.svg"); } +span.icon-st-add { + background-image: url("Add button.svg"); } + +/* + Definitions for utilities and helper classes. +*/ +/* Utility module CSS variable definitions */ +:root { + --generic-border-color: rgba(0, 0, 0, 0.3); + --generic-box-shadow: 0 0.2857142857rem 0.2857142857rem 0 rgba(0, 0, 0, 0.125), 0 0.1428571429rem 0.1428571429rem -0.1428571429rem rgba(0, 0, 0, 0.125); } + +.hidden { + display: none !important; } + +.visually-hidden { + position: absolute !important; + width: 1px !important; + height: 1px !important; + margin: -1px !important; + border: 0 !important; + padding: 0 !important; + clip: rect(0 0 0 0) !important; + -webkit-clip-path: inset(100%) !important; + clip-path: inset(100%) !important; + overflow: hidden !important; } + +.bordered { + border: 0.0714285714rem solid var(--generic-border-color) !important; } + +.rounded { + border-radius: var(--universal-border-radius) !important; } + +.circular { + border-radius: 50% !important; } + +.shadowed { + box-shadow: var(--generic-box-shadow) !important; } + +.responsive-margin { + margin: calc(var(--universal-margin) / 4) !important; } + @media screen and (min-width: 500px) { + .responsive-margin { + margin: calc(var(--universal-margin) / 2) !important; } } + @media screen and (min-width: 1280px) { + .responsive-margin { + margin: var(--universal-margin) !important; } } + +.responsive-padding { + padding: calc(var(--universal-padding) / 4) !important; } + @media screen and (min-width: 500px) { + .responsive-padding { + padding: calc(var(--universal-padding) / 2) !important; } } + @media screen and (min-width: 1280px) { + .responsive-padding { + padding: var(--universal-padding) !important; } } + +@media screen and (max-width: 499px) { + .hidden-sm { + display: none !important; } } +@media screen and (min-width: 500px) and (max-width: 1279px) { + .hidden-md { + display: none !important; } } +@media screen and (min-width: 1280px) { + .hidden-lg { + display: none !important; } } +@media screen and (max-width: 499px) { + .visually-hidden-sm { + position: absolute !important; + width: 1px !important; + height: 1px !important; + margin: -1px !important; + border: 0 !important; + padding: 0 !important; + clip: rect(0 0 0 0) !important; + -webkit-clip-path: inset(100%) !important; + clip-path: inset(100%) !important; + overflow: hidden !important; } } +@media screen and (min-width: 500px) and (max-width: 1279px) { + .visually-hidden-md { + position: absolute !important; + width: 1px !important; + height: 1px !important; + margin: -1px !important; + border: 0 !important; + padding: 0 !important; + clip: rect(0 0 0 0) !important; + -webkit-clip-path: inset(100%) !important; + clip-path: inset(100%) !important; + overflow: hidden !important; } } +@media screen and (min-width: 1280px) { + .visually-hidden-lg { + position: absolute !important; + width: 1px !important; + height: 1px !important; + margin: -1px !important; + border: 0 !important; + padding: 0 !important; + clip: rect(0 0 0 0) !important; + -webkit-clip-path: inset(100%) !important; + clip-path: inset(100%) !important; + overflow: hidden !important; } } + +/*# sourceMappingURL=mini-custom.css.map */ + +img[alt="ST logo"] { display: block; margin: auto; width: 75%; max-width: 250px; min-width: 71px; } +img[alt="Cube logo"] { float: right; width: 30%; max-width: 10rem; min-width: 8rem; padding-right: 1rem;} + +.figure { + display: block; + margin-left: auto; + margin-right: auto; + text-align: center; +} \ No newline at end of file diff --git a/Utilities/lpm/tiny_lpm/_htmresc/st_logo_2020.png b/Utilities/lpm/tiny_lpm/_htmresc/st_logo_2020.png new file mode 100644 index 0000000..d6cebb5 Binary files /dev/null and b/Utilities/lpm/tiny_lpm/_htmresc/st_logo_2020.png differ diff --git a/Utilities/lpm/tiny_lpm/stm32_lpm.c b/Utilities/lpm/tiny_lpm/stm32_lpm.c new file mode 100644 index 0000000..8f4e7cd --- /dev/null +++ b/Utilities/lpm/tiny_lpm/stm32_lpm.c @@ -0,0 +1,258 @@ +/** + ****************************************************************************** + * @file stm32_lpm.c + * @author MCD Application Team + * @brief Low Power Manager + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32_lpm.h" +#include "utilities_conf.h" + +/** @addtogroup TINY_LPM + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @defgroup TINY_LPM_Private_macros TINY LPM private macros + * @{ + */ + +/** + * @brief macro used to initialized the critical section + */ +#ifndef UTIL_LPM_INIT_CRITICAL_SECTION + #define UTIL_LPM_INIT_CRITICAL_SECTION( ) +#endif + +/** + * @brief macro used to enter the critical section + */ +#ifndef UTIL_LPM_ENTER_CRITICAL_SECTION + #define UTIL_LPM_ENTER_CRITICAL_SECTION( ) UTILS_ENTER_CRITICAL_SECTION( ) +#endif + +/** + * @brief macro used to exit the critical section + */ +#ifndef UTIL_LPM_EXIT_CRITICAL_SECTION + #define UTIL_LPM_EXIT_CRITICAL_SECTION( ) UTILS_EXIT_CRITICAL_SECTION( ) +#endif + +/** + * @brief macro used to enter the critical section when Entering Low Power + * @note this macro is only called inside the function UTIL_LPM_EnterLowPower + * and in a basic configuration shall be identcal to the macro + * UTIL_LPM_EXIT_CRITICAL_SECTION. In general, the request to enter the + * low power mode is already done under a critical section and + * nesting it is useless (in specific implementations not even possible). + * So the users could define their own macro) + */ +#ifndef UTIL_LPM_ENTER_CRITICAL_SECTION_ELP + #define UTIL_LPM_ENTER_CRITICAL_SECTION_ELP( ) UTIL_LPM_ENTER_CRITICAL_SECTION( ) +#endif + +/** + * @brief macro used to exit the critical section when exiting Low Power mode + * @note the behavior of the macro shall be symmetrical with the macro + * UTIL_LPM_ENTER_CRITICAL_SECTION_ELP + */ +#ifndef UTIL_LPM_EXIT_CRITICAL_SECTION_ELP + #define UTIL_LPM_EXIT_CRITICAL_SECTION_ELP( ) UTIL_LPM_EXIT_CRITICAL_SECTION( ) +#endif + +/** + * @} + */ +/* Private function prototypes -----------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private typedef -----------------------------------------------------------*/ +/* Private defines -----------------------------------------------------------*/ +/** @defgroup TINY_LPM_Private_define TINY LPM private defines + * @{ + */ + +/** + * @brief value used to reset the LPM mode + */ +#define UTIL_LPM_NO_BIT_SET (0UL) + +/** + * @} + */ +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @defgroup TINY_LPM_Private_variables TINY LPM private variables + * @{ + */ + +/** + * @brief value used to represent the LPM state of stop mode + */ +static UTIL_LPM_bm_t StopModeDisable = UTIL_LPM_NO_BIT_SET; + +/** + * @brief value used to represent the LPM state of off mode + */ +static UTIL_LPM_bm_t OffModeDisable = UTIL_LPM_NO_BIT_SET; + +/** + * @} + */ +/* Global variables ----------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Functions Definition ------------------------------------------------------*/ + +/** @addtogroup TINY_LPM_Exported_function + * @{ + */ +void UTIL_LPM_Init( void ) +{ + StopModeDisable = UTIL_LPM_NO_BIT_SET; + OffModeDisable = UTIL_LPM_NO_BIT_SET; + UTIL_LPM_INIT_CRITICAL_SECTION( ); +} + +void UTIL_LPM_DeInit( void ) +{ +} + +void UTIL_LPM_SetStopMode( UTIL_LPM_bm_t lpm_id_bm, UTIL_LPM_State_t state ) +{ + UTIL_LPM_ENTER_CRITICAL_SECTION( ); + + switch( state ) + { + case UTIL_LPM_DISABLE: + { + StopModeDisable |= lpm_id_bm; + break; + } + case UTIL_LPM_ENABLE: + { + StopModeDisable &= ( ~lpm_id_bm ); + break; + } + default : + { + break; + } + } + + UTIL_LPM_EXIT_CRITICAL_SECTION( ); +} + +void UTIL_LPM_SetOffMode( UTIL_LPM_bm_t lpm_id_bm, UTIL_LPM_State_t state ) +{ + UTIL_LPM_ENTER_CRITICAL_SECTION( ); + + switch(state) + { + case UTIL_LPM_DISABLE: + { + OffModeDisable |= lpm_id_bm; + break; + } + case UTIL_LPM_ENABLE: + { + OffModeDisable &= ( ~lpm_id_bm ); + break; + } + default : + { + break; + } + } + + UTIL_LPM_EXIT_CRITICAL_SECTION( ); +} + +UTIL_LPM_Mode_t UTIL_LPM_GetMode( void ) +{ + UTIL_LPM_Mode_t mode_selected; + + UTIL_LPM_ENTER_CRITICAL_SECTION( ); + + if( StopModeDisable != UTIL_LPM_NO_BIT_SET ) + { + /** + * At least one user disallows Stop Mode + */ + mode_selected = UTIL_LPM_SLEEPMODE; + } + else + { + if( OffModeDisable != UTIL_LPM_NO_BIT_SET ) + { + /** + * At least one user disallows Off Mode + */ + mode_selected = UTIL_LPM_STOPMODE; + } + else + { + mode_selected = UTIL_LPM_OFFMODE; + } + } + + UTIL_LPM_EXIT_CRITICAL_SECTION( ); + + return mode_selected; +} + +void UTIL_LPM_EnterLowPower( void ) +{ + UTIL_LPM_ENTER_CRITICAL_SECTION_ELP( ); + + if( StopModeDisable != UTIL_LPM_NO_BIT_SET ) + { + /** + * At least one user disallows Stop Mode + * SLEEP mode is required + */ + UTIL_PowerDriver.EnterSleepMode( ); + UTIL_PowerDriver.ExitSleepMode( ); + } + else + { + if( OffModeDisable != UTIL_LPM_NO_BIT_SET ) + { + /** + * At least one user disallows Off Mode + * STOP mode is required + */ + UTIL_PowerDriver.EnterStopMode( ); + UTIL_PowerDriver.ExitStopMode( ); + } + else + { + /** + * OFF mode is required + */ + UTIL_PowerDriver.EnterOffMode( ); + UTIL_PowerDriver.ExitOffMode( ); + } + } + + UTIL_LPM_EXIT_CRITICAL_SECTION_ELP( ); +} + +/** + * @} + */ + +/** + * @} + */ diff --git a/Utilities/lpm/tiny_lpm/stm32_lpm.h b/Utilities/lpm/tiny_lpm/stm32_lpm.h new file mode 100644 index 0000000..a262f9c --- /dev/null +++ b/Utilities/lpm/tiny_lpm/stm32_lpm.h @@ -0,0 +1,167 @@ +/** + ****************************************************************************** + * @file stm32_lpm.h + * @author MCD Application Team + * @brief Header for stm32_lpm.c module + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** +*/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32_TINY_LPM_H +#define STM32_TINY_LPM_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stdint.h" + +/** @defgroup TINY_LPM TINY LPM + * @{ + */ + +/* Exported typedef ---------------------------------------------------------*/ +/** @defgroup TINY_LPM_Exported_typedef TINY LPM exported typedef + * @{ + */ + +/** + * @brief type definition to represent the bit mask of an LPM mode + */ +typedef uint32_t UTIL_LPM_bm_t; + +/** + * @brief type definition to represent value of an LPM mode + */ +typedef enum +{ + UTIL_LPM_ENABLE=0, + UTIL_LPM_DISABLE, +} UTIL_LPM_State_t; + +/** + * @brief type definition to represent the different type of LPM mode + */ + +typedef enum +{ + UTIL_LPM_SLEEPMODE, + UTIL_LPM_STOPMODE, + UTIL_LPM_OFFMODE, +} UTIL_LPM_Mode_t; + +/** + * @} + */ + +/** @defgroup TINY_LPM_Exported_struct TINY LPM exported struct + * @{ + */ + +/** + * @brief LPM driver definition + */ +struct UTIL_LPM_Driver_s +{ + void (*EnterSleepMode) ( void ); /*! + + + + + + Release Notes for STM32 miscellaneous utilities + + + + + + +
+
+
+

Release Notes for

+

STM32 miscellaneous utilities

+

Copyright © 2021 STMicroelectronics
+

+ +
+

Purpose

+

The source code delivered is a utility to help managing miscellaneous utilities within an embedded application: memory, system time and vsnprintf.

+
+
+

Update History

+
+ +
+

Main Changes

+

Contents

+
    +
  • Update release note name
    • +
+

Known limitations

+

Development Toolchains and Compilers

+

Supported Devices and boards

+

backward compatibility

+

Dependencies

+
+
+
+ +
+

Main Changes

+

Contents

+
    +
  • Update release note format
    • +
+

Known limitations

+

Development Toolchains and Compilers

+

Supported Devices and boards

+

backward compatibility

+

Dependencies

+
+
+
+ +
+

Main Changes

+
    +
  • Licensing information should be updated AND missing header user section code should be added
    • +
+

Contents

+
    +
  • Update release note format
    • +
+

Known limitations

+

Development Toolchains and Compilers

+

Supported Devices and boards

+

backward compatibility

+

Dependencies

+
+
+
+ +
+

Main Changes

+
    +
  • release V1.0.2
    • +
+

Contents

+
    +
  • Update release note format
    • +
+

Known limitations

+

Development Toolchains and Compilers

+

Supported Devices and boards

+

backward compatibility

+

Dependencies

+
+
+
+ +
+

Main Changes

+
    +
  • release V1.0.1
    • +
+

Contents

+
    +
  • add empty line at the end of stm32_mem.h
    • +
+

Known limitations

+

Development Toolchains and Compilers

+

Supported Devices and boards

+

backward compatibility

+

Dependencies

+
+
+
+ +
+

Main Changes

+
    +
  • release V1.0.0
    • +
+

Contents

+
    +
  • First release
    • +
+

known limitations

+

Development Toolchains and Compilers

+

Supported Devices and boards

+

backward compatibility

+

Dependencies

+
+
+
+
+ + + diff --git a/Utilities/misc/_htmresc/Add button.svg b/Utilities/misc/_htmresc/Add button.svg new file mode 100644 index 0000000..c211545 --- /dev/null +++ b/Utilities/misc/_htmresc/Add button.svg @@ -0,0 +1,2 @@ + + diff --git a/Utilities/misc/_htmresc/Update.svg b/Utilities/misc/_htmresc/Update.svg new file mode 100644 index 0000000..f88381f --- /dev/null +++ b/Utilities/misc/_htmresc/Update.svg @@ -0,0 +1,2 @@ + + diff --git a/Utilities/misc/_htmresc/favicon.png b/Utilities/misc/_htmresc/favicon.png new file mode 100644 index 0000000..06713ee Binary files /dev/null and b/Utilities/misc/_htmresc/favicon.png differ diff --git a/Utilities/misc/_htmresc/mini-st_2020.css b/Utilities/misc/_htmresc/mini-st_2020.css new file mode 100644 index 0000000..986f4d4 --- /dev/null +++ b/Utilities/misc/_htmresc/mini-st_2020.css @@ -0,0 +1,1711 @@ +@charset "UTF-8"; +/* + Flavor name: Custom (mini-custom) + Generated online - https://minicss.org/flavors + mini.css version: v3.0.1 +*/ +/* + Browsers resets and base typography. +*/ +/* Core module CSS variable definitions */ +:root { + --fore-color: #03234b; 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+ flex-basis: 8.3333333333%; } + + .col-md-offset-0 { + margin-left: 0; } + + .col-md-2, + .row.cols-md-2 > * { + max-width: 16.6666666667%; + flex-basis: 16.6666666667%; } + + .col-md-offset-1 { + margin-left: 8.3333333333%; } + + .col-md-3, + .row.cols-md-3 > * { + max-width: 25%; + flex-basis: 25%; } + + .col-md-offset-2 { + margin-left: 16.6666666667%; } + + .col-md-4, + .row.cols-md-4 > * { + max-width: 33.3333333333%; + flex-basis: 33.3333333333%; } + + .col-md-offset-3 { + margin-left: 25%; } + + .col-md-5, + .row.cols-md-5 > * { + max-width: 41.6666666667%; + flex-basis: 41.6666666667%; } + + .col-md-offset-4 { + margin-left: 33.3333333333%; } + + .col-md-6, + .row.cols-md-6 > * { + max-width: 50%; + flex-basis: 50%; } + + .col-md-offset-5 { + margin-left: 41.6666666667%; } + + .col-md-7, + .row.cols-md-7 > * { + max-width: 58.3333333333%; + flex-basis: 58.3333333333%; } + + .col-md-offset-6 { + margin-left: 50%; } + + .col-md-8, + .row.cols-md-8 > * { + max-width: 66.6666666667%; + flex-basis: 66.6666666667%; } + + .col-md-offset-7 { + margin-left: 58.3333333333%; } + + .col-md-9, + .row.cols-md-9 > * { + max-width: 75%; + flex-basis: 75%; } + + .col-md-offset-8 { + margin-left: 66.6666666667%; } + + .col-md-10, + .row.cols-md-10 > * { + max-width: 83.3333333333%; + flex-basis: 83.3333333333%; } + + .col-md-offset-9 { + margin-left: 75%; } + + .col-md-11, + .row.cols-md-11 > * { + max-width: 91.6666666667%; + flex-basis: 91.6666666667%; } + + .col-md-offset-10 { + margin-left: 83.3333333333%; } + + .col-md-12, + .row.cols-md-12 > * { + max-width: 100%; + flex-basis: 100%; } + + .col-md-offset-11 { + margin-left: 91.6666666667%; } + + .col-md-normal { + order: initial; } + + .col-md-first { + order: -999; } + + .col-md-last { + order: 999; } } +@media screen and (min-width: 1280px) { + .col-lg, + [class^='col-lg-'], + [class^='col-lg-offset-'], + .row[class*='cols-lg-'] > * { + box-sizing: border-box; + flex: 0 0 auto; + padding: 0 calc(var(--universal-padding) / 2); } + + .col-lg, + .row.cols-lg > * { + max-width: 100%; + flex-grow: 1; + flex-basis: 0; } + + .col-lg-1, + .row.cols-lg-1 > * { + max-width: 8.3333333333%; + flex-basis: 8.3333333333%; } + + .col-lg-offset-0 { + margin-left: 0; } + + .col-lg-2, + .row.cols-lg-2 > * { + max-width: 16.6666666667%; + flex-basis: 16.6666666667%; } + + .col-lg-offset-1 { + margin-left: 8.3333333333%; } + + .col-lg-3, + .row.cols-lg-3 > * { + max-width: 25%; + flex-basis: 25%; } + + .col-lg-offset-2 { + margin-left: 16.6666666667%; } + + .col-lg-4, + .row.cols-lg-4 > * { + max-width: 33.3333333333%; + flex-basis: 33.3333333333%; } + + .col-lg-offset-3 { + margin-left: 25%; } + + .col-lg-5, + .row.cols-lg-5 > * { + max-width: 41.6666666667%; + flex-basis: 41.6666666667%; } + + .col-lg-offset-4 { + margin-left: 33.3333333333%; } + + .col-lg-6, + .row.cols-lg-6 > * { + max-width: 50%; + flex-basis: 50%; } + + .col-lg-offset-5 { + margin-left: 41.6666666667%; } + + .col-lg-7, + .row.cols-lg-7 > * { + max-width: 58.3333333333%; + flex-basis: 58.3333333333%; } + + .col-lg-offset-6 { + margin-left: 50%; } + + .col-lg-8, + .row.cols-lg-8 > * { + max-width: 66.6666666667%; + flex-basis: 66.6666666667%; } + + .col-lg-offset-7 { + margin-left: 58.3333333333%; } + + .col-lg-9, + .row.cols-lg-9 > * { + max-width: 75%; + flex-basis: 75%; } + + .col-lg-offset-8 { + margin-left: 66.6666666667%; } + + .col-lg-10, + .row.cols-lg-10 > * { + max-width: 83.3333333333%; + flex-basis: 83.3333333333%; } + + .col-lg-offset-9 { + margin-left: 75%; } + + .col-lg-11, + .row.cols-lg-11 > * { + max-width: 91.6666666667%; + flex-basis: 91.6666666667%; } + + .col-lg-offset-10 { + margin-left: 83.3333333333%; } + + .col-lg-12, + .row.cols-lg-12 > * { + max-width: 100%; + flex-basis: 100%; } + + .col-lg-offset-11 { + margin-left: 91.6666666667%; } + + .col-lg-normal { + order: initial; } + + .col-lg-first { + order: -999; } + + .col-lg-last { + order: 999; } } +/* Card component CSS variable definitions */ +:root { + --card-back-color: #3cb4e6; + --card-fore-color: #03234b; + --card-border-color: #03234b; } + +.card { + display: flex; + flex-direction: column; + justify-content: space-between; + align-self: center; + position: relative; + width: 100%; + background: var(--card-back-color); + color: var(--card-fore-color); + border: 0.0714285714rem solid var(--card-border-color); + border-radius: var(--universal-border-radius); + margin: var(--universal-margin); + overflow: hidden; } + @media screen and (min-width: 320px) { + .card { + max-width: 320px; } } + .card > .sectione { + background: var(--card-back-color); + color: var(--card-fore-color); + box-sizing: border-box; + margin: 0; + border: 0; + border-radius: 0; + border-bottom: 0.0714285714rem solid var(--card-border-color); + padding: var(--universal-padding); + width: 100%; } + .card > .sectione.media { + height: 200px; + padding: 0; + -o-object-fit: cover; + object-fit: cover; } + .card > .sectione:last-child { + border-bottom: 0; } + +/* + Custom elements for card elements. +*/ +@media screen and (min-width: 240px) { + .card.small { + max-width: 240px; } } +@media screen and (min-width: 480px) { + .card.large { + max-width: 480px; } } +.card.fluid { + max-width: 100%; + width: auto; } + +.card.warning { + --card-back-color: #e5b8b7; + --card-fore-color: #3b234b; + --card-border-color: #8c0078; } + +.card.error { + --card-back-color: #464650; + --card-fore-color: #ffffff; + --card-border-color: #8c0078; } + +.card > .sectione.dark { + --card-back-color: #3b234b; + --card-fore-color: #ffffff; } + +.card > .sectione.double-padded { + padding: calc(1.5 * var(--universal-padding)); } + +/* + Definitions for forms and input elements. +*/ +/* Input_control module CSS variable definitions */ +:root { + --form-back-color: #ffe97f; + --form-fore-color: #03234b; + --form-border-color: #3cb4e6; + --input-back-color: #ffffff; + --input-fore-color: #03234b; + --input-border-color: #3cb4e6; + --input-focus-color: #0288d1; + --input-invalid-color: #d32f2f; + --button-back-color: #e2e2e2; + --button-hover-back-color: #dcdcdc; + --button-fore-color: #212121; + --button-border-color: transparent; + --button-hover-border-color: transparent; + --button-group-border-color: rgba(124, 124, 124, 0.54); } + +form { + background: var(--form-back-color); + color: var(--form-fore-color); + border: 0.0714285714rem solid var(--form-border-color); + border-radius: var(--universal-border-radius); + margin: var(--universal-margin); + padding: calc(2 * var(--universal-padding)) var(--universal-padding); } + +fieldset { + border: 0.0714285714rem solid var(--form-border-color); + border-radius: var(--universal-border-radius); + margin: calc(var(--universal-margin) / 4); + padding: var(--universal-padding); } + +legend { + box-sizing: border-box; + display: table; + max-width: 100%; + white-space: normal; + font-weight: 500; + padding: calc(var(--universal-padding) / 2); } + +label { + padding: calc(var(--universal-padding) / 2) var(--universal-padding); } + +.input-group { + display: inline-block; } + .input-group.fluid { + display: flex; + align-items: center; + justify-content: center; } + .input-group.fluid > input { + max-width: 100%; + flex-grow: 1; + flex-basis: 0px; } + @media screen and (max-width: 499px) { + .input-group.fluid { + align-items: stretch; + flex-direction: column; } } + .input-group.vertical { + display: flex; + align-items: stretch; + flex-direction: column; } + .input-group.vertical > input { + max-width: 100%; + flex-grow: 1; + flex-basis: 0px; } + +[type="number"]::-webkit-inner-spin-button, [type="number"]::-webkit-outer-spin-button { + height: auto; } + +[type="search"] { + -webkit-appearance: textfield; + outline-offset: -2px; } + +[type="search"]::-webkit-search-cancel-button, +[type="search"]::-webkit-search-decoration { + -webkit-appearance: none; } + +input:not([type]), [type="text"], [type="email"], [type="number"], [type="search"], +[type="password"], [type="url"], [type="tel"], [type="checkbox"], [type="radio"], textarea, select { + box-sizing: border-box; + background: var(--input-back-color); + color: var(--input-fore-color); + border: 0.0714285714rem solid var(--input-border-color); + border-radius: var(--universal-border-radius); + margin: calc(var(--universal-margin) / 2); + padding: var(--universal-padding) calc(1.5 * var(--universal-padding)); } + +input:not([type="button"]):not([type="submit"]):not([type="reset"]):hover, input:not([type="button"]):not([type="submit"]):not([type="reset"]):focus, textarea:hover, textarea:focus, select:hover, select:focus { + border-color: var(--input-focus-color); + box-shadow: none; } +input:not([type="button"]):not([type="submit"]):not([type="reset"]):invalid, input:not([type="button"]):not([type="submit"]):not([type="reset"]):focus:invalid, textarea:invalid, textarea:focus:invalid, select:invalid, select:focus:invalid { + border-color: var(--input-invalid-color); + box-shadow: none; } +input:not([type="button"]):not([type="submit"]):not([type="reset"])[readonly], textarea[readonly], select[readonly] { + background: var(--secondary-back-color); } + +select { + max-width: 100%; } + +option { + overflow: hidden; + text-overflow: ellipsis; } + +[type="checkbox"], [type="radio"] { + -webkit-appearance: none; + -moz-appearance: none; + appearance: none; + position: relative; + height: calc(1rem + var(--universal-padding) / 2); + width: calc(1rem + var(--universal-padding) / 2); + vertical-align: text-bottom; + padding: 0; + flex-basis: calc(1rem + var(--universal-padding) / 2) !important; + flex-grow: 0 !important; } + [type="checkbox"]:checked:before, [type="radio"]:checked:before { + position: absolute; } + +[type="checkbox"]:checked:before { + content: '\2713'; + font-family: sans-serif; + font-size: calc(1rem + var(--universal-padding) / 2); + top: calc(0rem - var(--universal-padding)); + left: calc(var(--universal-padding) / 4); } + +[type="radio"] { + border-radius: 100%; } + [type="radio"]:checked:before { + border-radius: 100%; + content: ''; + top: calc(0.0714285714rem + var(--universal-padding) / 2); + left: calc(0.0714285714rem + var(--universal-padding) / 2); + background: var(--input-fore-color); + width: 0.5rem; + height: 0.5rem; } + +:placeholder-shown { + color: var(--input-fore-color); } + +::-ms-placeholder { + color: var(--input-fore-color); + opacity: 0.54; } + +button::-moz-focus-inner, [type="button"]::-moz-focus-inner, [type="reset"]::-moz-focus-inner, [type="submit"]::-moz-focus-inner { + border-style: none; + padding: 0; } + +button, html [type="button"], [type="reset"], [type="submit"] { + -webkit-appearance: button; } + +button { + overflow: visible; + text-transform: none; } + +button, [type="button"], [type="submit"], [type="reset"], +a.button, label.button, .button, +a[role="button"], label[role="button"], [role="button"] { + display: inline-block; + background: var(--button-back-color); + color: var(--button-fore-color); + border: 0.0714285714rem solid var(--button-border-color); + border-radius: var(--universal-border-radius); + padding: var(--universal-padding) calc(1.5 * var(--universal-padding)); + margin: var(--universal-margin); + text-decoration: none; + cursor: pointer; + transition: background 0.3s; } + button:hover, button:focus, [type="button"]:hover, [type="button"]:focus, [type="submit"]:hover, [type="submit"]:focus, [type="reset"]:hover, [type="reset"]:focus, + a.button:hover, + a.button:focus, label.button:hover, label.button:focus, .button:hover, .button:focus, + a[role="button"]:hover, + a[role="button"]:focus, label[role="button"]:hover, label[role="button"]:focus, [role="button"]:hover, [role="button"]:focus { + background: var(--button-hover-back-color); + border-color: var(--button-hover-border-color); } + +input:disabled, input[disabled], textarea:disabled, textarea[disabled], select:disabled, select[disabled], button:disabled, button[disabled], .button:disabled, .button[disabled], [role="button"]:disabled, [role="button"][disabled] { + cursor: not-allowed; + opacity: 0.75; } + +.button-group { + display: flex; + border: 0.0714285714rem solid var(--button-group-border-color); + border-radius: var(--universal-border-radius); + margin: var(--universal-margin); } + .button-group > button, .button-group [type="button"], .button-group > [type="submit"], .button-group > [type="reset"], .button-group > .button, .button-group > [role="button"] { + margin: 0; + max-width: 100%; + flex: 1 1 auto; + text-align: center; + border: 0; + border-radius: 0; + box-shadow: none; } + .button-group > :not(:first-child) { + border-left: 0.0714285714rem solid var(--button-group-border-color); } + @media screen and (max-width: 499px) { + .button-group { + flex-direction: column; } + .button-group > :not(:first-child) { + border: 0; + border-top: 0.0714285714rem solid var(--button-group-border-color); } } + +/* + Custom elements for forms and input elements. +*/ +button.primary, [type="button"].primary, [type="submit"].primary, [type="reset"].primary, .button.primary, [role="button"].primary { + --button-back-color: #1976d2; + --button-fore-color: #f8f8f8; } + button.primary:hover, button.primary:focus, [type="button"].primary:hover, [type="button"].primary:focus, [type="submit"].primary:hover, [type="submit"].primary:focus, [type="reset"].primary:hover, [type="reset"].primary:focus, .button.primary:hover, .button.primary:focus, [role="button"].primary:hover, [role="button"].primary:focus { + --button-hover-back-color: #1565c0; } + +button.secondary, [type="button"].secondary, [type="submit"].secondary, [type="reset"].secondary, .button.secondary, [role="button"].secondary { + --button-back-color: #d32f2f; + --button-fore-color: #f8f8f8; } + button.secondary:hover, button.secondary:focus, [type="button"].secondary:hover, [type="button"].secondary:focus, [type="submit"].secondary:hover, [type="submit"].secondary:focus, [type="reset"].secondary:hover, [type="reset"].secondary:focus, .button.secondary:hover, .button.secondary:focus, [role="button"].secondary:hover, [role="button"].secondary:focus { + --button-hover-back-color: #c62828; } + +button.tertiary, [type="button"].tertiary, [type="submit"].tertiary, [type="reset"].tertiary, .button.tertiary, [role="button"].tertiary { + --button-back-color: #308732; + --button-fore-color: #f8f8f8; } + button.tertiary:hover, button.tertiary:focus, [type="button"].tertiary:hover, [type="button"].tertiary:focus, [type="submit"].tertiary:hover, [type="submit"].tertiary:focus, [type="reset"].tertiary:hover, [type="reset"].tertiary:focus, .button.tertiary:hover, .button.tertiary:focus, [role="button"].tertiary:hover, [role="button"].tertiary:focus { + --button-hover-back-color: #277529; } + +button.inverse, [type="button"].inverse, [type="submit"].inverse, [type="reset"].inverse, .button.inverse, [role="button"].inverse { + --button-back-color: #212121; + --button-fore-color: #f8f8f8; } + button.inverse:hover, button.inverse:focus, [type="button"].inverse:hover, [type="button"].inverse:focus, [type="submit"].inverse:hover, [type="submit"].inverse:focus, [type="reset"].inverse:hover, [type="reset"].inverse:focus, .button.inverse:hover, .button.inverse:focus, [role="button"].inverse:hover, [role="button"].inverse:focus { + --button-hover-back-color: #111; } + +button.small, [type="button"].small, [type="submit"].small, [type="reset"].small, .button.small, [role="button"].small { + padding: calc(0.5 * var(--universal-padding)) calc(0.75 * var(--universal-padding)); + margin: var(--universal-margin); } + +button.large, [type="button"].large, [type="submit"].large, [type="reset"].large, .button.large, [role="button"].large { + padding: calc(1.5 * var(--universal-padding)) calc(2 * var(--universal-padding)); + margin: var(--universal-margin); } + +/* + Definitions for navigation elements. +*/ +/* Navigation module CSS variable definitions */ +:root { + --header-back-color: #03234b; + --header-hover-back-color: #ffd200; + --header-fore-color: #ffffff; + --header-border-color: #3cb4e6; + --nav-back-color: #ffffff; + --nav-hover-back-color: #ffe97f; + --nav-fore-color: #e6007e; + --nav-border-color: #3cb4e6; + --nav-link-color: #3cb4e6; + --footer-fore-color: #ffffff; + --footer-back-color: #03234b; + --footer-border-color: #3cb4e6; + --footer-link-color: #3cb4e6; + --drawer-back-color: #ffffff; + --drawer-hover-back-color: #ffe97f; + --drawer-border-color: #3cb4e6; + --drawer-close-color: #e6007e; } + +header { + height: 2.75rem; + background: var(--header-back-color); + color: var(--header-fore-color); + border-bottom: 0.0714285714rem solid var(--header-border-color); + padding: calc(var(--universal-padding) / 4) 0; + white-space: nowrap; + overflow-x: auto; + overflow-y: hidden; } + header.row { + box-sizing: content-box; } + header .logo { + color: var(--header-fore-color); + font-size: 1.75rem; + padding: var(--universal-padding) calc(2 * var(--universal-padding)); + text-decoration: none; } + header button, header [type="button"], header .button, header [role="button"] { + box-sizing: border-box; + position: relative; + top: calc(0rem - var(--universal-padding) / 4); + height: calc(3.1875rem + var(--universal-padding) / 2); + background: var(--header-back-color); + line-height: calc(3.1875rem - var(--universal-padding) * 1.5); + text-align: center; + color: var(--header-fore-color); + border: 0; + border-radius: 0; + margin: 0; + text-transform: uppercase; } + header button:hover, header button:focus, header [type="button"]:hover, header [type="button"]:focus, header .button:hover, header .button:focus, header [role="button"]:hover, header [role="button"]:focus { + background: var(--header-hover-back-color); } + +nav { + background: var(--nav-back-color); + color: var(--nav-fore-color); + border: 0.0714285714rem solid var(--nav-border-color); + border-radius: var(--universal-border-radius); + margin: var(--universal-margin); } + nav * { + padding: var(--universal-padding) calc(1.5 * var(--universal-padding)); } + nav a, nav a:visited { + display: block; + color: var(--nav-link-color); + border-radius: var(--universal-border-radius); + transition: background 0.3s; } + nav a:hover, nav a:focus, nav a:visited:hover, nav a:visited:focus { + text-decoration: none; + background: var(--nav-hover-back-color); } + nav .sublink-1 { + position: relative; + margin-left: calc(2 * var(--universal-padding)); } + nav .sublink-1:before { + position: absolute; + left: calc(var(--universal-padding) - 1 * var(--universal-padding)); + top: -0.0714285714rem; + content: ''; + height: 100%; + border: 0.0714285714rem solid var(--nav-border-color); + border-left: 0; } + nav .sublink-2 { + position: relative; + margin-left: calc(4 * var(--universal-padding)); } + nav .sublink-2:before { + position: absolute; + left: calc(var(--universal-padding) - 3 * var(--universal-padding)); + top: -0.0714285714rem; + content: ''; + height: 100%; + border: 0.0714285714rem solid var(--nav-border-color); + border-left: 0; } + +footer { + background: var(--footer-back-color); + color: var(--footer-fore-color); + border-top: 0.0714285714rem solid var(--footer-border-color); + padding: calc(2 * var(--universal-padding)) var(--universal-padding); + font-size: 0.875rem; } + footer a, footer a:visited { + color: var(--footer-link-color); } + +header.sticky { + position: -webkit-sticky; + position: sticky; + z-index: 1101; + top: 0; } + +footer.sticky { + position: -webkit-sticky; + position: sticky; + z-index: 1101; + bottom: 0; } + +.drawer-toggle:before { + display: inline-block; + position: relative; + vertical-align: bottom; + content: '\00a0\2261\00a0'; + font-family: sans-serif; + font-size: 1.5em; } +@media screen and (min-width: 500px) { + .drawer-toggle:not(.persistent) { + display: none; } } + +[type="checkbox"].drawer { + height: 1px; + width: 1px; + margin: -1px; + overflow: hidden; + position: absolute; + clip: rect(0 0 0 0); + -webkit-clip-path: inset(100%); + clip-path: inset(100%); } + [type="checkbox"].drawer + * { + display: block; + box-sizing: border-box; + position: fixed; + top: 0; + width: 320px; + height: 100vh; + overflow-y: auto; + background: var(--drawer-back-color); + border: 0.0714285714rem solid var(--drawer-border-color); + border-radius: 0; + margin: 0; + z-index: 1110; + right: -320px; + transition: right 0.3s; } + [type="checkbox"].drawer + * .drawer-close { + position: absolute; + top: var(--universal-margin); + right: var(--universal-margin); + z-index: 1111; + width: 2rem; + height: 2rem; + border-radius: var(--universal-border-radius); + padding: var(--universal-padding); + margin: 0; + cursor: pointer; + transition: background 0.3s; } + [type="checkbox"].drawer + * .drawer-close:before { + display: block; + content: '\00D7'; + color: var(--drawer-close-color); + position: relative; + font-family: sans-serif; + font-size: 2rem; + line-height: 1; + text-align: center; } + [type="checkbox"].drawer + * .drawer-close:hover, [type="checkbox"].drawer + * .drawer-close:focus { + background: var(--drawer-hover-back-color); } + @media screen and (max-width: 320px) { + [type="checkbox"].drawer + * { + width: 100%; } } + [type="checkbox"].drawer:checked + * { + right: 0; } + @media screen and (min-width: 500px) { + [type="checkbox"].drawer:not(.persistent) + * { + position: static; + height: 100%; + z-index: 1100; } + [type="checkbox"].drawer:not(.persistent) + * .drawer-close { + display: none; } } + +/* + Definitions for the responsive table component. +*/ +/* Table module CSS variable definitions. */ +:root { + --table-border-color: #03234b; + --table-border-separator-color: #03234b; + --table-head-back-color: #03234b; + --table-head-fore-color: #ffffff; + --table-body-back-color: #ffffff; + --table-body-fore-color: #03234b; + --table-body-alt-back-color: #f4f4f4; } + +table { + border-collapse: separate; + border-spacing: 0; + margin: 0; + display: flex; + flex: 0 1 auto; + flex-flow: row wrap; + padding: var(--universal-padding); + padding-top: 0; } + table caption { + font-size: 1rem; + margin: calc(2 * var(--universal-margin)) 0; + max-width: 100%; + flex: 0 0 100%; } + table thead, table tbody { + display: flex; + flex-flow: row wrap; + border: 0.0714285714rem solid var(--table-border-color); } + table thead { + z-index: 999; + border-radius: var(--universal-border-radius) var(--universal-border-radius) 0 0; + border-bottom: 0.0714285714rem solid var(--table-border-separator-color); } + table tbody { + border-top: 0; + margin-top: calc(0 - var(--universal-margin)); + border-radius: 0 0 var(--universal-border-radius) var(--universal-border-radius); } + table tr { + display: flex; + padding: 0; } + table th, table td { + padding: calc(0.5 * var(--universal-padding)); + font-size: 0.9rem; } + table th { + text-align: left; + background: var(--table-head-back-color); + color: var(--table-head-fore-color); } + table td { + background: var(--table-body-back-color); + color: var(--table-body-fore-color); + border-top: 0.0714285714rem solid var(--table-border-color); } + +table:not(.horizontal) { + overflow: auto; + max-height: 100%; } + table:not(.horizontal) thead, table:not(.horizontal) tbody { + max-width: 100%; + flex: 0 0 100%; } + table:not(.horizontal) tr { + flex-flow: row wrap; + flex: 0 0 100%; } + table:not(.horizontal) th, table:not(.horizontal) td { + flex: 1 0 0%; + overflow: hidden; + text-overflow: ellipsis; } + table:not(.horizontal) thead { + position: sticky; + top: 0; } + table:not(.horizontal) tbody tr:first-child td { + border-top: 0; } + +table.horizontal { + border: 0; } + table.horizontal thead, table.horizontal tbody { + border: 0; + flex: .2 0 0; + flex-flow: row nowrap; } + table.horizontal tbody { + overflow: auto; + justify-content: space-between; + flex: .8 0 0; + margin-left: 0; + padding-bottom: calc(var(--universal-padding) / 4); } + table.horizontal tr { + flex-direction: column; + flex: 1 0 auto; } + table.horizontal th, table.horizontal td { + width: auto; + border: 0; + border-bottom: 0.0714285714rem solid var(--table-border-color); } + table.horizontal th:not(:first-child), table.horizontal td:not(:first-child) { + border-top: 0; } + table.horizontal th { + text-align: right; + border-left: 0.0714285714rem solid var(--table-border-color); + border-right: 0.0714285714rem solid var(--table-border-separator-color); } + table.horizontal thead tr:first-child { + padding-left: 0; } + table.horizontal th:first-child, table.horizontal td:first-child { + border-top: 0.0714285714rem solid var(--table-border-color); } + table.horizontal tbody tr:last-child td { + border-right: 0.0714285714rem solid var(--table-border-color); } + table.horizontal tbody tr:last-child td:first-child { + border-top-right-radius: 0.25rem; } + table.horizontal tbody tr:last-child td:last-child { + border-bottom-right-radius: 0.25rem; } + table.horizontal thead tr:first-child th:first-child { + border-top-left-radius: 0.25rem; } + table.horizontal thead tr:first-child th:last-child { + border-bottom-left-radius: 0.25rem; } + +@media screen and (max-width: 499px) { + table, table.horizontal { + border-collapse: collapse; + border: 0; + width: 100%; + display: table; } + table thead, table th, table.horizontal thead, table.horizontal th { + border: 0; + height: 1px; + width: 1px; + margin: -1px; + overflow: hidden; + padding: 0; + position: absolute; + clip: rect(0 0 0 0); + -webkit-clip-path: inset(100%); + clip-path: inset(100%); } + table tbody, table.horizontal tbody { + border: 0; + display: table-row-group; } + table tr, table.horizontal tr { + display: block; + border: 0.0714285714rem solid var(--table-border-color); + border-radius: var(--universal-border-radius); + background: #ffffff; + padding: var(--universal-padding); + margin: var(--universal-margin); + margin-bottom: calc(1 * var(--universal-margin)); } + table th, table td, table.horizontal th, table.horizontal td { + width: auto; } + table td, table.horizontal td { + display: block; + border: 0; + text-align: right; } + table td:before, table.horizontal td:before { + content: attr(data-label); + float: left; + font-weight: 600; } + table th:first-child, table td:first-child, table.horizontal th:first-child, table.horizontal td:first-child { + border-top: 0; } + table tbody tr:last-child td, table.horizontal tbody tr:last-child td { + border-right: 0; } } +table tr:nth-of-type(2n) > td { + background: var(--table-body-alt-back-color); } + +@media screen and (max-width: 500px) { + table tr:nth-of-type(2n) { + background: var(--table-body-alt-back-color); } } +:root { + --table-body-hover-back-color: #90caf9; } + +table.hoverable tr:hover, table.hoverable tr:hover > td, table.hoverable tr:focus, table.hoverable tr:focus > td { + background: var(--table-body-hover-back-color); } + +@media screen and (max-width: 500px) { + table.hoverable tr:hover, table.hoverable tr:hover > td, table.hoverable tr:focus, table.hoverable tr:focus > td { + background: var(--table-body-hover-back-color); } } +/* + Definitions for contextual background elements, toasts and tooltips. +*/ +/* Contextual module CSS variable definitions */ +:root { + --mark-back-color: #3cb4e6; + --mark-fore-color: #ffffff; } + +mark { + background: var(--mark-back-color); + color: var(--mark-fore-color); + font-size: 0.95em; + line-height: 1em; + border-radius: var(--universal-border-radius); + padding: calc(var(--universal-padding) / 4) var(--universal-padding); } + mark.inline-block { + display: inline-block; + font-size: 1em; + line-height: 1.4; + padding: calc(var(--universal-padding) / 2) var(--universal-padding); } + +:root { + --toast-back-color: #424242; + --toast-fore-color: #fafafa; } + +.toast { + position: fixed; + bottom: calc(var(--universal-margin) * 3); + left: 50%; + transform: translate(-50%, -50%); + z-index: 1111; + color: var(--toast-fore-color); + background: var(--toast-back-color); + border-radius: calc(var(--universal-border-radius) * 16); + padding: var(--universal-padding) calc(var(--universal-padding) * 3); } + +:root { + --tooltip-back-color: #212121; + --tooltip-fore-color: #fafafa; } + +.tooltip { + position: relative; + display: inline-block; } + .tooltip:before, .tooltip:after { + position: absolute; + opacity: 0; + clip: rect(0 0 0 0); + -webkit-clip-path: inset(100%); + clip-path: inset(100%); + transition: all 0.3s; + z-index: 1010; + left: 50%; } + .tooltip:not(.bottom):before, .tooltip:not(.bottom):after { + bottom: 75%; } + .tooltip.bottom:before, .tooltip.bottom:after { + top: 75%; } + .tooltip:hover:before, .tooltip:hover:after, .tooltip:focus:before, .tooltip:focus:after { + opacity: 1; + clip: auto; + -webkit-clip-path: inset(0%); + clip-path: inset(0%); } + .tooltip:before { + content: ''; + background: transparent; + border: var(--universal-margin) solid transparent; + left: calc(50% - var(--universal-margin)); } + .tooltip:not(.bottom):before { + border-top-color: #212121; } + .tooltip.bottom:before { + border-bottom-color: #212121; } + .tooltip:after { + content: attr(aria-label); + color: var(--tooltip-fore-color); + background: var(--tooltip-back-color); + border-radius: var(--universal-border-radius); + padding: var(--universal-padding); + white-space: nowrap; + transform: translateX(-50%); } + .tooltip:not(.bottom):after { + margin-bottom: calc(2 * var(--universal-margin)); } + .tooltip.bottom:after { + margin-top: calc(2 * var(--universal-margin)); } + +:root { + --modal-overlay-color: rgba(0, 0, 0, 0.45); + --modal-close-color: #e6007e; + --modal-close-hover-color: #ffe97f; } + +[type="checkbox"].modal { + height: 1px; + width: 1px; + margin: -1px; + overflow: hidden; + position: absolute; + clip: rect(0 0 0 0); + -webkit-clip-path: inset(100%); + clip-path: inset(100%); } + [type="checkbox"].modal + div { + position: fixed; + top: 0; + left: 0; + display: none; + width: 100vw; + height: 100vh; + background: var(--modal-overlay-color); } + [type="checkbox"].modal + div .card { + margin: 0 auto; + max-height: 50vh; + overflow: auto; } + [type="checkbox"].modal + div .card .modal-close { + position: absolute; + top: 0; + right: 0; + width: 1.75rem; + height: 1.75rem; + border-radius: var(--universal-border-radius); + padding: var(--universal-padding); + margin: 0; + cursor: pointer; + transition: background 0.3s; } + [type="checkbox"].modal + div .card .modal-close:before { + display: block; + content: '\00D7'; + color: var(--modal-close-color); + position: relative; + font-family: sans-serif; + font-size: 1.75rem; + line-height: 1; + text-align: center; } + [type="checkbox"].modal + div .card .modal-close:hover, [type="checkbox"].modal + div .card .modal-close:focus { + background: var(--modal-close-hover-color); } + [type="checkbox"].modal:checked + div { + display: flex; + flex: 0 1 auto; + z-index: 1200; } + [type="checkbox"].modal:checked + div .card .modal-close { + z-index: 1211; } + +:root { + --collapse-label-back-color: #03234b; + --collapse-label-fore-color: #ffffff; + --collapse-label-hover-back-color: #3cb4e6; + --collapse-selected-label-back-color: #3cb4e6; + --collapse-border-color: var(--collapse-label-back-color); + --collapse-selected-border-color: #ceecf8; + --collapse-content-back-color: #ffffff; + --collapse-selected-label-border-color: #3cb4e6; } + +.collapse { + width: calc(100% - 2 * var(--universal-margin)); + opacity: 1; + display: flex; + flex-direction: column; + margin: var(--universal-margin); + border-radius: var(--universal-border-radius); } + .collapse > [type="radio"], .collapse > [type="checkbox"] { + height: 1px; + width: 1px; + margin: -1px; + overflow: hidden; + position: absolute; + clip: rect(0 0 0 0); + -webkit-clip-path: inset(100%); + clip-path: inset(100%); } + .collapse > label { + flex-grow: 1; + display: inline-block; + height: 1.25rem; + cursor: pointer; + transition: background 0.2s; + color: var(--collapse-label-fore-color); + background: var(--collapse-label-back-color); + border: 0.0714285714rem solid var(--collapse-selected-border-color); + padding: calc(1.25 * var(--universal-padding)); } + .collapse > label:hover, .collapse > label:focus { + background: var(--collapse-label-hover-back-color); } + .collapse > label + div { + flex-basis: auto; + height: 1px; + width: 1px; + margin: -1px; + overflow: hidden; + position: absolute; + clip: rect(0 0 0 0); + -webkit-clip-path: inset(100%); + clip-path: inset(100%); + transition: max-height 0.3s; + max-height: 1px; } + .collapse > :checked + label { + background: var(--collapse-selected-label-back-color); + border-color: var(--collapse-selected-label-border-color); } + .collapse > :checked + label + div { + box-sizing: border-box; + position: relative; + width: 100%; + height: auto; + overflow: auto; + margin: 0; + background: var(--collapse-content-back-color); + border: 0.0714285714rem solid var(--collapse-selected-border-color); + border-top: 0; + padding: var(--universal-padding); + clip: auto; + -webkit-clip-path: inset(0%); + clip-path: inset(0%); + max-height: 100%; } + .collapse > label:not(:first-of-type) { + border-top: 0; } + .collapse > label:first-of-type { + border-radius: var(--universal-border-radius) var(--universal-border-radius) 0 0; } + .collapse > label:last-of-type:not(:first-of-type) { + border-radius: 0 0 var(--universal-border-radius) var(--universal-border-radius); } + .collapse > label:last-of-type:first-of-type { + border-radius: var(--universal-border-radius); } + .collapse > :checked:last-of-type:not(:first-of-type) + label { + border-radius: 0; } + .collapse > :checked:last-of-type + label + div { + border-radius: 0 0 var(--universal-border-radius) var(--universal-border-radius); } + +/* + Custom elements for contextual background elements, toasts and tooltips. +*/ +mark.tertiary { + --mark-back-color: #3cb4e6; } + +mark.tag { + padding: calc(var(--universal-padding)/2) var(--universal-padding); + border-radius: 1em; } + +/* + Definitions for progress elements and spinners. +*/ +/* Progress module CSS variable definitions */ +:root { + --progress-back-color: #3cb4e6; + --progress-fore-color: #555; } + +progress { + display: block; + vertical-align: baseline; + -webkit-appearance: none; + -moz-appearance: none; + appearance: none; + height: 0.75rem; + width: calc(100% - 2 * var(--universal-margin)); + margin: var(--universal-margin); + border: 0; + border-radius: calc(2 * var(--universal-border-radius)); + background: var(--progress-back-color); + color: var(--progress-fore-color); } + progress::-webkit-progress-value { + background: var(--progress-fore-color); + border-top-left-radius: calc(2 * var(--universal-border-radius)); + border-bottom-left-radius: calc(2 * var(--universal-border-radius)); } + progress::-webkit-progress-bar { + background: var(--progress-back-color); } + progress::-moz-progress-bar { + background: var(--progress-fore-color); + border-top-left-radius: calc(2 * var(--universal-border-radius)); + border-bottom-left-radius: calc(2 * var(--universal-border-radius)); } + progress[value="1000"]::-webkit-progress-value { + border-radius: calc(2 * var(--universal-border-radius)); } + progress[value="1000"]::-moz-progress-bar { + border-radius: calc(2 * var(--universal-border-radius)); } + progress.inline { + display: inline-block; + vertical-align: middle; + width: 60%; } + +:root { + --spinner-back-color: #ddd; + --spinner-fore-color: #555; } + +@keyframes spinner-donut-anim { + 0% { + transform: rotate(0deg); } + 100% { + transform: rotate(360deg); } } +.spinner { + display: inline-block; + margin: var(--universal-margin); + border: 0.25rem solid var(--spinner-back-color); + border-left: 0.25rem solid var(--spinner-fore-color); + border-radius: 50%; + width: 1.25rem; + height: 1.25rem; + animation: spinner-donut-anim 1.2s linear infinite; } + +/* + Custom elements for progress bars and spinners. +*/ +progress.primary { + --progress-fore-color: #1976d2; } + +progress.secondary { + --progress-fore-color: #d32f2f; } + +progress.tertiary { + --progress-fore-color: #308732; } + +.spinner.primary { + --spinner-fore-color: #1976d2; } + +.spinner.secondary { + --spinner-fore-color: #d32f2f; } + +.spinner.tertiary { + --spinner-fore-color: #308732; } + +/* + Definitions for icons - powered by Feather (https://feathericons.com/). +*/ +span[class^='icon-'] { + display: inline-block; + height: 1em; + width: 1em; + vertical-align: -0.125em; + background-size: contain; + margin: 0 calc(var(--universal-margin) / 4); } + span[class^='icon-'].secondary { + -webkit-filter: invert(25%); + filter: invert(25%); } + span[class^='icon-'].inverse { + -webkit-filter: invert(100%); + filter: invert(100%); } + +span.icon-alert { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='8' x2='12' y2='12'%3E%3C/line%3E%3Cline x1='12' y1='16' x2='12' y2='16'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-bookmark { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M19 21l-7-5-7 5V5a2 2 0 0 1 2-2h10a2 2 0 0 1 2 2z'%3E%3C/path%3E%3C/svg%3E"); } +span.icon-calendar { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='3' y='4' width='18' height='18' rx='2' ry='2'%3E%3C/rect%3E%3Cline x1='16' y1='2' x2='16' y2='6'%3E%3C/line%3E%3Cline x1='8' y1='2' x2='8' y2='6'%3E%3C/line%3E%3Cline x1='3' y1='10' x2='21' y2='10'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-credit { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='1' y='4' width='22' height='16' rx='2' ry='2'%3E%3C/rect%3E%3Cline x1='1' y1='10' x2='23' y2='10'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-edit { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M20 14.66V20a2 2 0 0 1-2 2H4a2 2 0 0 1-2-2V6a2 2 0 0 1 2-2h5.34'%3E%3C/path%3E%3Cpolygon points='18 2 22 6 12 16 8 16 8 12 18 2'%3E%3C/polygon%3E%3C/svg%3E"); } +span.icon-link { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M18 13v6a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2V8a2 2 0 0 1 2-2h6'%3E%3C/path%3E%3Cpolyline points='15 3 21 3 21 9'%3E%3C/polyline%3E%3Cline x1='10' y1='14' x2='21' y2='3'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-help { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M9.09 9a3 3 0 0 1 5.83 1c0 2-3 3-3 3'%3E%3C/path%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='17' x2='12' y2='17'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-home { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M3 9l9-7 9 7v11a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2z'%3E%3C/path%3E%3Cpolyline points='9 22 9 12 15 12 15 22'%3E%3C/polyline%3E%3C/svg%3E"); } +span.icon-info { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='16' x2='12' y2='12'%3E%3C/line%3E%3Cline x1='12' y1='8' x2='12' y2='8'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-lock { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='3' y='11' width='18' height='11' rx='2' ry='2'%3E%3C/rect%3E%3Cpath d='M7 11V7a5 5 0 0 1 10 0v4'%3E%3C/path%3E%3C/svg%3E"); } +span.icon-mail { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M4 4h16c1.1 0 2 .9 2 2v12c0 1.1-.9 2-2 2H4c-1.1 0-2-.9-2-2V6c0-1.1.9-2 2-2z'%3E%3C/path%3E%3Cpolyline points='22,6 12,13 2,6'%3E%3C/polyline%3E%3C/svg%3E"); } +span.icon-location { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M21 10c0 7-9 13-9 13s-9-6-9-13a9 9 0 0 1 18 0z'%3E%3C/path%3E%3Ccircle cx='12' cy='10' r='3'%3E%3C/circle%3E%3C/svg%3E"); } +span.icon-phone { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M22 16.92v3a2 2 0 0 1-2.18 2 19.79 19.79 0 0 1-8.63-3.07 19.5 19.5 0 0 1-6-6 19.79 19.79 0 0 1-3.07-8.67A2 2 0 0 1 4.11 2h3a2 2 0 0 1 2 1.72 12.84 12.84 0 0 0 .7 2.81 2 2 0 0 1-.45 2.11L8.09 9.91a16 16 0 0 0 6 6l1.27-1.27a2 2 0 0 1 2.11-.45 12.84 12.84 0 0 0 2.81.7A2 2 0 0 1 22 16.92z'%3E%3C/path%3E%3C/svg%3E"); } +span.icon-rss { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M4 11a9 9 0 0 1 9 9'%3E%3C/path%3E%3Cpath d='M4 4a16 16 0 0 1 16 16'%3E%3C/path%3E%3Ccircle cx='5' cy='19' r='1'%3E%3C/circle%3E%3C/svg%3E"); } +span.icon-search { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='11' cy='11' r='8'%3E%3C/circle%3E%3Cline x1='21' y1='21' x2='16.65' y2='16.65'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-settings { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='3'%3E%3C/circle%3E%3Cpath d='M19.4 15a1.65 1.65 0 0 0 .33 1.82l.06.06a2 2 0 0 1 0 2.83 2 2 0 0 1-2.83 0l-.06-.06a1.65 1.65 0 0 0-1.82-.33 1.65 1.65 0 0 0-1 1.51V21a2 2 0 0 1-2 2 2 2 0 0 1-2-2v-.09A1.65 1.65 0 0 0 9 19.4a1.65 1.65 0 0 0-1.82.33l-.06.06a2 2 0 0 1-2.83 0 2 2 0 0 1 0-2.83l.06-.06a1.65 1.65 0 0 0 .33-1.82 1.65 1.65 0 0 0-1.51-1H3a2 2 0 0 1-2-2 2 2 0 0 1 2-2h.09A1.65 1.65 0 0 0 4.6 9a1.65 1.65 0 0 0-.33-1.82l-.06-.06a2 2 0 0 1 0-2.83 2 2 0 0 1 2.83 0l.06.06a1.65 1.65 0 0 0 1.82.33H9a1.65 1.65 0 0 0 1-1.51V3a2 2 0 0 1 2-2 2 2 0 0 1 2 2v.09a1.65 1.65 0 0 0 1 1.51 1.65 1.65 0 0 0 1.82-.33l.06-.06a2 2 0 0 1 2.83 0 2 2 0 0 1 0 2.83l-.06.06a1.65 1.65 0 0 0-.33 1.82V9a1.65 1.65 0 0 0 1.51 1H21a2 2 0 0 1 2 2 2 2 0 0 1-2 2h-.09a1.65 1.65 0 0 0-1.51 1z'%3E%3C/path%3E%3C/svg%3E"); } +span.icon-share { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='18' cy='5' r='3'%3E%3C/circle%3E%3Ccircle cx='6' cy='12' r='3'%3E%3C/circle%3E%3Ccircle cx='18' cy='19' r='3'%3E%3C/circle%3E%3Cline x1='8.59' y1='13.51' x2='15.42' y2='17.49'%3E%3C/line%3E%3Cline x1='15.41' y1='6.51' x2='8.59' y2='10.49'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-cart { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='9' cy='21' r='1'%3E%3C/circle%3E%3Ccircle cx='20' cy='21' r='1'%3E%3C/circle%3E%3Cpath d='M1 1h4l2.68 13.39a2 2 0 0 0 2 1.61h9.72a2 2 0 0 0 2-1.61L23 6H6'%3E%3C/path%3E%3C/svg%3E"); } +span.icon-upload { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M21 15v4a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2v-4'%3E%3C/path%3E%3Cpolyline points='17 8 12 3 7 8'%3E%3C/polyline%3E%3Cline x1='12' y1='3' x2='12' y2='15'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-user { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M20 21v-2a4 4 0 0 0-4-4H8a4 4 0 0 0-4 4v2'%3E%3C/path%3E%3Ccircle cx='12' cy='7' r='4'%3E%3C/circle%3E%3C/svg%3E"); } + +/* + Definitions for STMicroelectronics icons (https://brandportal.st.com/document/26). +*/ +span.icon-st-update { + background-image: url("Update.svg"); } +span.icon-st-add { + background-image: url("Add button.svg"); } + +/* + Definitions for utilities and helper classes. +*/ +/* Utility module CSS variable definitions */ +:root { + --generic-border-color: rgba(0, 0, 0, 0.3); + --generic-box-shadow: 0 0.2857142857rem 0.2857142857rem 0 rgba(0, 0, 0, 0.125), 0 0.1428571429rem 0.1428571429rem -0.1428571429rem rgba(0, 0, 0, 0.125); } + +.hidden { + display: none !important; } + +.visually-hidden { + position: absolute !important; + width: 1px !important; + height: 1px !important; + margin: -1px !important; + border: 0 !important; + padding: 0 !important; + clip: rect(0 0 0 0) !important; + -webkit-clip-path: inset(100%) !important; + clip-path: inset(100%) !important; + overflow: hidden !important; } + +.bordered { + border: 0.0714285714rem solid var(--generic-border-color) !important; } + +.rounded { + border-radius: var(--universal-border-radius) !important; } + +.circular { + border-radius: 50% !important; } + +.shadowed { + box-shadow: var(--generic-box-shadow) !important; } + +.responsive-margin { + margin: calc(var(--universal-margin) / 4) !important; } + @media screen and (min-width: 500px) { + .responsive-margin { + margin: calc(var(--universal-margin) / 2) !important; } } + @media screen and (min-width: 1280px) { + .responsive-margin { + margin: var(--universal-margin) !important; } } + +.responsive-padding { + padding: calc(var(--universal-padding) / 4) !important; } + @media screen and (min-width: 500px) { + .responsive-padding { + padding: calc(var(--universal-padding) / 2) !important; } } + @media screen and (min-width: 1280px) { + .responsive-padding { + padding: var(--universal-padding) !important; } } + +@media screen and (max-width: 499px) { + .hidden-sm { + display: none !important; } } +@media screen and (min-width: 500px) and (max-width: 1279px) { + .hidden-md { + display: none !important; } } +@media screen and (min-width: 1280px) { + .hidden-lg { + display: none !important; } } +@media screen and (max-width: 499px) { + .visually-hidden-sm { + position: absolute !important; + width: 1px !important; + height: 1px !important; + margin: -1px !important; + border: 0 !important; + padding: 0 !important; + clip: rect(0 0 0 0) !important; + -webkit-clip-path: inset(100%) !important; + clip-path: inset(100%) !important; + overflow: hidden !important; } } +@media screen and (min-width: 500px) and (max-width: 1279px) { + .visually-hidden-md { + position: absolute !important; + width: 1px !important; + height: 1px !important; + margin: -1px !important; + border: 0 !important; + padding: 0 !important; + clip: rect(0 0 0 0) !important; + -webkit-clip-path: inset(100%) !important; + clip-path: inset(100%) !important; + overflow: hidden !important; } } +@media screen and (min-width: 1280px) { + .visually-hidden-lg { + position: absolute !important; + width: 1px !important; + height: 1px !important; + margin: -1px !important; + border: 0 !important; + padding: 0 !important; + clip: rect(0 0 0 0) !important; + -webkit-clip-path: inset(100%) !important; + clip-path: inset(100%) !important; + overflow: hidden !important; } } + +/*# sourceMappingURL=mini-custom.css.map */ + +img[alt="ST logo"] { display: block; margin: auto; width: 75%; max-width: 250px; min-width: 71px; } +img[alt="Cube logo"] { float: right; width: 30%; max-width: 10rem; min-width: 8rem; padding-right: 1rem;} + +.figure { + display: block; + margin-left: auto; + margin-right: auto; + text-align: center; +} \ No newline at end of file diff --git a/Utilities/misc/_htmresc/st_logo_2020.png b/Utilities/misc/_htmresc/st_logo_2020.png new file mode 100644 index 0000000..d6cebb5 Binary files /dev/null and b/Utilities/misc/_htmresc/st_logo_2020.png differ diff --git a/Utilities/misc/stm32_mem.c b/Utilities/misc/stm32_mem.c new file mode 100644 index 0000000..b18ce20 --- /dev/null +++ b/Utilities/misc/stm32_mem.c @@ -0,0 +1,61 @@ +/** + ****************************************************************************** + * @file stm32_mem.c + * @author MCD Application Team + * @brief standard memory operation + ****************************************************************************** + * @attention + * + * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stdint.h" +#include "stm32_mem.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private defines -----------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Global variables ----------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Functions Definition ------------------------------------------------------*/ + +void UTIL_MEM_cpy_8( void *dst, const void *src, uint16_t size ) +{ + uint8_t* dst8= (uint8_t *) dst; + uint8_t* src8= (uint8_t *) src; + + while( size-- ) + { + *dst8++ = *src8++; + } +} + +void UTIL_MEM_cpyr_8( void *dst, const void *src, uint16_t size ) +{ + uint8_t* dst8= (uint8_t *) dst; + uint8_t* src8= (uint8_t *) src; + + dst8 = dst8 + ( size - 1 ); + while( size-- ) + { + *dst8-- = *src8++; + } +} + +void UTIL_MEM_set_8( void *dst, uint8_t value, uint16_t size ) +{ + uint8_t* dst8= (uint8_t *) dst; + while( size-- ) + { + *dst8++ = value; + } +} diff --git a/Utilities/misc/stm32_mem.h b/Utilities/misc/stm32_mem.h new file mode 100644 index 0000000..dc64ed3 --- /dev/null +++ b/Utilities/misc/stm32_mem.h @@ -0,0 +1,70 @@ +/** + ****************************************************************************** + * @file stm32_mem.h + * @author MCD Application Team + * @brief standard memory operation + ****************************************************************************** + * @attention + * + * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32_MEM_H__ +#define __STM32_MEM_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif +/* Includes ------------------------------------------------------------------*/ +#include +#include "utilities_conf.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* ---- Memory mapping macros ----------------------------------------------- */ +#define UTIL_MEM_PLACE_IN_SECTION( __x__ ) UTIL_PLACE_IN_SECTION( __x__ ) +#define UTIL_MEM_ALIGN ALIGN + +/* Exported functions ------------------------------------------------------- */ +/** +* @brief This API copies one buffer to another +* @param dst: output buffer to be filled +* @param src: input buffer +* @param size: size of 8b data +* @retval None +*/ +void UTIL_MEM_cpy_8( void *dst, const void *src, uint16_t size ); + +/** +* @brief This API copies one buffer to another in reverse +* @param dst: output buffer to be filled +* @param src: input buffer +* @param size: size of 8b data +* @retval None +*/ +void UTIL_MEM_cpyr_8( void *dst, const void *src, uint16_t size ); + +/** +* @brief This API fills a buffer with value +* @param dst: output buffer to be filled +* @param value: value +* @param size: size of 8b data +* @retval None +*/ +void UTIL_MEM_set_8( void *dst, uint8_t value, uint16_t size ); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32_MEM_H__ */ diff --git a/Utilities/misc/stm32_systime.c b/Utilities/misc/stm32_systime.c new file mode 100644 index 0000000..3423889 --- /dev/null +++ b/Utilities/misc/stm32_systime.c @@ -0,0 +1,496 @@ +/*! + * \file stm32_systime.c + * + * \brief System time functions implementation + * + * \copyright Revised BSD License, see section \ref LICENSE. + * + * \code + * ______ _ + * / _____) _ | | + * ( (____ _____ ____ _| |_ _____ ____| |__ + * \____ \| ___ | (_ _) ___ |/ ___) _ \ + * _____) ) ____| | | || |_| ____( (___| | | | + * (______/|_____)_|_|_| \__)_____)\____)_| |_| + * (C)2013-2018 Semtech - STMicroelectronics + * + * \endcode + * + * \author Miguel Luis ( Semtech ) + * + * \author Gregory Cristian ( Semtech ) + * + * \author MCD Application Team ( STMicroelectronics International ) + */ +/** + ****************************************************************************** + * @file stm32_systime.c + * @author MCD Application Team + * @brief System time functions implementation + ****************************************************************************** + * @attention + * + * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include +#include "stm32_systime.h" + +/** @addtogroup SYS_TIME + * @{ + */ + +/* Private defines -----------------------------------------------------------*/ +/** + * @defgroup SYS_TIME_private_defines SYS_TIME private defines + * @{ + */ + +/** + * @brief number of day in leap year up to the end of February + * + */ +#define END_OF_FEBRUARY_LEAP 60 //31+29 + +/** + * @brief number of day in leap year up to the end of july + * + */ +#define END_OF_JULY_LEAP 213 //31+29+... + +/** + * @brief number of day in normal year up to the end of February + * + */ +#define END_OF_FEBRUARY_NORM 59 //31+28 + +/** + * @brief number of day in normal year up to the end of july + * + */ +#define END_OF_JULY_NORM 212 //31+28+... + +/** + * @brief delta is referenced to Unix time + * @note UNIX time 0 = starts at 01:00:00, 01/01/1970 + * but calculation is easier from Monday 1st January 1968 + * + */ +#define CALC_REF_YEAR 68 + +/** + * @brief delta is referenced to Unix time + * @note UNIX time 0 = starts at 01:00:00, 01/01/1970 + * but calculation is easier from Monday 1st January 1968 + * + */ +#define CALC_REF_YEAR_TO_UNIX_REF_YEAR_COMPENSATION_IN_SECONDS ( ( TM_DAYS_IN_LEAP_YEAR + TM_DAYS_IN_YEAR ) * TM_SECONDS_IN_1DAY ) + +/** + * @brief month correction table of a normal year. To calculate the day number within a year + * @note error compensation is between 0 and 2 days. 2 bits per month + * + */ +#define DAYS_IN_MONTH_CORRECTION_NORM ( (uint32_t )0x99AAA0 ) + +/** + * @brief month correction table of a leap year. To calculate the day number within a year + * @note error compensation is between 0 and 2 days. 2 bits per month + * + */ +#define DAYS_IN_MONTH_CORRECTION_LEAP ( (uint32_t )0x445550 ) + +/** + * @brief find X/365.25 + * + */ +/* 365.25 = (366 + 365 + 365 + 365)/4 */ +#define DIV_365_25( X ) ( ( ( X ) * 91867 + 22750 ) >> 25 ) + +/** + * @brief find the nearest quotient of X/86400 (8640 number of seconds in one week) + * + */ +#define DIV_APPROX_86400( X ) ( ( ( X ) >> 18 ) + ( ( X ) >> 17 ) ) + +/** + * @brief find the nearest quotient of X/1000 + * + */ +#define DIV_APPROX_1000( X ) ( ( ( X ) >> 10 ) +( ( X ) >> 16 ) + ( ( X ) >> 17 ) ) + +/** + * @brief find the nearest quotient of X/60 + * + */ +#define DIV_APPROX_60( X ) ( ( ( X ) * 17476 ) >> 20 ) + +/** + * @brief find the nearest quotient of X/61 + * + */ +#define DIV_APPROX_61( X ) ( ( ( X ) * 68759 ) >> 22 ) + +/** + * @brief Calculates mod(x,7) + * + */ +#define MODULO_7( X ) ( ( X ) -( ( ( ( ( X ) + 1 ) * 299593 ) >> 21 ) * 7 ) ) + +/** + * @brief Calculates ceiling( X / N ) + * + */ +#define DIVC( X, N ) ( ( ( X ) + ( N ) -1 ) / ( N ) ) + +/** + * @brief Calculates ceiling( X / 4 ) + * + */ +#define DIVC_BY_4( X ) ( ( ( X ) + 3 ) >>2 ) + +/** + * @brief Calculates ceiling( X / 2 ) + * + */ +#define DIVC_BY_2( X ) ( ( ( X ) + 1 ) >> 1 ) +/** + * @} + */ + +/* Private constants -----------------------------------------------------------*/ +/** + * @defgroup SYSTIME_private_variable SYSTIME private constants + * @{ + */ +const char *WeekDayString[]={ "Sun", "Mon", "Tue", "Wed", "Thu", "Fri", "Sat" }; +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ + +/** + * @defgroup SYSTIME_private_function_prototypes SYSTIME private function prototypes + * @{ + */ +static uint32_t CalendarGetMonth( uint32_t days, uint32_t year ); +static void CalendarDiv86400( uint32_t in, uint32_t* out, uint32_t* remainder ); +static uint32_t CalendarDiv61( uint32_t in ); +static void CalendarDiv60( uint32_t in, uint32_t* out, uint32_t* remainder ); +/** + * @} + */ + +/* Functions Definition ------------------------------------------------------*/ +/** + * @addtogroup SYSTIME_exported_function + * @{ + */ + +SysTime_t SysTimeAdd( SysTime_t a, SysTime_t b ) +{ + SysTime_t c = { .Seconds = 0, .SubSeconds = 0 }; + + c.Seconds = a.Seconds + b.Seconds; + c.SubSeconds = a.SubSeconds + b.SubSeconds; + if( c.SubSeconds >= 1000 ) + { + c.Seconds++; + c.SubSeconds -= 1000; + } + return c; +} + +SysTime_t SysTimeSub( SysTime_t a, SysTime_t b ) +{ + SysTime_t c = { .Seconds = 0, .SubSeconds = 0 }; + + c.Seconds = a.Seconds - b.Seconds; + c.SubSeconds = a.SubSeconds - b.SubSeconds; + if( c.SubSeconds < 0 ) + { + c.Seconds--; + c.SubSeconds += 1000; + } + return c; +} + +void SysTimeSet( SysTime_t sysTime ) +{ + SysTime_t DeltaTime; + + SysTime_t calendarTime = { .Seconds = 0, .SubSeconds = 0 }; + + calendarTime.Seconds = UTIL_SYSTIMDriver.GetCalendarTime( ( uint16_t* )&calendarTime.SubSeconds ); + + // sysTime is UNIX epoch + DeltaTime = SysTimeSub( sysTime, calendarTime ); + + UTIL_SYSTIMDriver.BKUPWrite_Seconds( DeltaTime.Seconds ); + UTIL_SYSTIMDriver.BKUPWrite_SubSeconds( ( uint32_t ) DeltaTime.SubSeconds ); +} + +SysTime_t SysTimeGet( void ) +{ + SysTime_t calendarTime = { .Seconds = 0, .SubSeconds = 0 }; + SysTime_t sysTime = { .Seconds = 0, .SubSeconds = 0 }; + SysTime_t DeltaTime; + + calendarTime.Seconds = UTIL_SYSTIMDriver.GetCalendarTime( ( uint16_t* )&calendarTime.SubSeconds ); + + DeltaTime.SubSeconds = (int16_t)UTIL_SYSTIMDriver.BKUPRead_SubSeconds(); + DeltaTime.Seconds = UTIL_SYSTIMDriver.BKUPRead_Seconds(); + + sysTime = SysTimeAdd( DeltaTime, calendarTime ); + + return sysTime; +} + + +SysTime_t SysTimeGetMcuTime( void ) +{ + SysTime_t calendarTime = { .Seconds = 0, .SubSeconds = 0 }; + + calendarTime.Seconds = UTIL_SYSTIMDriver.GetCalendarTime( ( uint16_t* )&calendarTime.SubSeconds ); + + return calendarTime; +} + +uint32_t SysTimeToMs( SysTime_t sysTime ) +{ + SysTime_t DeltaTime; + DeltaTime.SubSeconds = (int16_t)UTIL_SYSTIMDriver.BKUPRead_SubSeconds(); + DeltaTime.Seconds = UTIL_SYSTIMDriver.BKUPRead_Seconds(); + + SysTime_t calendarTime = SysTimeSub( sysTime, DeltaTime ); + return calendarTime.Seconds * 1000 + calendarTime.SubSeconds; +} + +SysTime_t SysTimeFromMs( uint32_t timeMs ) +{ + uint32_t seconds = timeMs / 1000; + SysTime_t sysTime = { .Seconds = seconds, .SubSeconds = timeMs - seconds * 1000 }; + SysTime_t DeltaTime = { 0 }; + + DeltaTime.SubSeconds = (int16_t)UTIL_SYSTIMDriver.BKUPRead_SubSeconds(); + DeltaTime.Seconds = UTIL_SYSTIMDriver.BKUPRead_Seconds(); + return SysTimeAdd( sysTime, DeltaTime ); +} + +uint32_t SysTimeMkTime( const struct tm* localtime ) +{ + uint32_t nbdays; + uint32_t nbsecs; + uint32_t year = localtime->tm_year - CALC_REF_YEAR; + uint32_t correctionMonth[4] = + { + DAYS_IN_MONTH_CORRECTION_LEAP, + DAYS_IN_MONTH_CORRECTION_NORM, + DAYS_IN_MONTH_CORRECTION_NORM, + DAYS_IN_MONTH_CORRECTION_NORM + }; + + nbdays = DIVC( ( TM_DAYS_IN_YEAR * 3 + TM_DAYS_IN_LEAP_YEAR ) * year, 4 ); + + nbdays += ( DIVC_BY_2( ( localtime->tm_mon ) * ( 30 + 31 ) ) - + ( ( ( correctionMonth[year % 4] >> ( ( localtime->tm_mon ) * 2 ) ) & 0x03 ) ) ); + + nbdays += ( localtime->tm_mday - 1 ); + + // Convert from days to seconds + nbsecs = nbdays * TM_SECONDS_IN_1DAY; + + nbsecs += ( ( uint32_t )localtime->tm_sec + + ( ( uint32_t )localtime->tm_min * TM_SECONDS_IN_1MINUTE ) + + ( ( uint32_t )localtime->tm_hour * TM_SECONDS_IN_1HOUR ) ); + return nbsecs - CALC_REF_YEAR_TO_UNIX_REF_YEAR_COMPENSATION_IN_SECONDS; +} + +void SysTimeLocalTime( const uint32_t timestamp, struct tm *localtime ) +{ + uint32_t correctionMonth[4] = + { + DAYS_IN_MONTH_CORRECTION_LEAP, + DAYS_IN_MONTH_CORRECTION_NORM, + DAYS_IN_MONTH_CORRECTION_NORM, + DAYS_IN_MONTH_CORRECTION_NORM + }; + uint32_t weekDays = 1; // Monday 1st January 1968 + uint32_t seconds; + uint32_t minutes; + uint32_t days; + uint32_t divOut; + uint32_t divReminder; + + CalendarDiv86400( timestamp + CALC_REF_YEAR_TO_UNIX_REF_YEAR_COMPENSATION_IN_SECONDS, &days, &seconds ); + + // Calculates seconds + CalendarDiv60( seconds, &minutes, &divReminder ); + localtime->tm_sec = ( uint8_t )divReminder; + + // Calculates minutes and hours + CalendarDiv60( minutes, &divOut, &divReminder); + localtime->tm_min = ( uint8_t )divReminder; + localtime->tm_hour = ( uint8_t )divOut; + + // Calculates year + localtime->tm_year = DIV_365_25( days ); + days-= DIVC_BY_4( ( TM_DAYS_IN_YEAR * 3 + TM_DAYS_IN_LEAP_YEAR ) * localtime->tm_year ); + + localtime->tm_yday = days; + + // Calculates month + localtime->tm_mon = CalendarGetMonth( days, localtime->tm_year ); + + // calculates weekdays + weekDays += DIVC_BY_4( ( localtime->tm_year * 5 ) ); + weekDays += days; + localtime->tm_wday = MODULO_7( weekDays ); + + days -= ( DIVC_BY_2( ( localtime->tm_mon ) * ( 30 + 31 ) ) - + ( ( ( correctionMonth[localtime->tm_year % 4] >> ( ( localtime->tm_mon ) * 2 ) ) & 0x03 ) ) ); + + // Convert 0 to 1 indexed. + localtime->tm_mday = days + 1; + + localtime->tm_year += CALC_REF_YEAR; + + localtime->tm_isdst = -1; +} + +/** + * @} + */ + +/**************************** Private functions *******************************/ + +/** + * @addtogroup SYSTIME_private_function + * + * @{ + */ +static uint32_t CalendarGetMonth( uint32_t days, uint32_t year ) +{ + uint32_t month; + if( ( year % 4 ) == 0 ) + { /*leap year*/ + if( days < END_OF_FEBRUARY_LEAP ) + { // January or February + // month = days * 2 / ( 30 + 31 ); + month = CalendarDiv61( days * 2 ); + } + else if( days < END_OF_JULY_LEAP ) + { + month = CalendarDiv61( ( days - END_OF_FEBRUARY_LEAP ) * 2 ) + 2; + } + else + { + month = CalendarDiv61( ( days - END_OF_JULY_LEAP ) * 2 ) + 7; + } + } + else + { + if( days < END_OF_FEBRUARY_NORM ) + { // January or February + month = CalendarDiv61( days * 2 ); + } + else if( days < END_OF_JULY_NORM ) + { + month = CalendarDiv61( ( days - END_OF_FEBRUARY_NORM ) * 2 ) + 2; + } + else + { + month = CalendarDiv61( ( days - END_OF_JULY_NORM ) * 2 ) + 7; + } + } + return month; +} + +static void CalendarDiv86400( uint32_t in, uint32_t* out, uint32_t* remainder ) +{ +#if 0 + *remainder = in % SECONDS_IN_1DAY; + *out = in / SECONDS_IN_1DAY; +#else + uint32_t outTemp = 0; + uint32_t divResult = DIV_APPROX_86400( in ); + + while( divResult >=1 ) + { + outTemp += divResult; + in -= divResult * 86400; + divResult= DIV_APPROX_86400( in ); + } + if( in >= 86400 ) + { + outTemp += 1; + in -= 86400; + } + + *remainder = in; + *out = outTemp; +#endif +} + +static uint32_t CalendarDiv61( uint32_t in ) +{ +#if 0 + return( in / 61 ); +#else + uint32_t outTemp = 0; + uint32_t divResult = DIV_APPROX_61( in ); + while( divResult >=1 ) + { + outTemp += divResult; + in -= divResult * 61; + divResult = DIV_APPROX_61( in ); + } + if( in >= 61 ) + { + outTemp += 1; + in -= 61; + } + return outTemp; +#endif +} + +static void CalendarDiv60( uint32_t in, uint32_t* out, uint32_t* remainder ) +{ +#if 0 + *remainder = in % 60; + *out = in / 60; +#else + uint32_t outTemp = 0; + uint32_t divResult = DIV_APPROX_60( in ); + + while( divResult >=1 ) + { + outTemp += divResult; + in -= divResult * 60; + divResult = DIV_APPROX_60( in ); + } + if( in >= 60 ) + { + outTemp += 1; + in -= 60; + } + *remainder = in; + *out = outTemp; +#endif +} +/** + * @} + */ + +/** + * @} + */ diff --git a/Utilities/misc/stm32_systime.h b/Utilities/misc/stm32_systime.h new file mode 100644 index 0000000..5e219d3 --- /dev/null +++ b/Utilities/misc/stm32_systime.h @@ -0,0 +1,252 @@ +/*! + * \file stm32_systime.h + * + * \brief System time functions implementation + * + * \copyright Revised BSD License, see section \ref LICENSE. + * + * \code + * ______ _ + * / _____) _ | | + * ( (____ _____ ____ _| |_ _____ ____| |__ + * \____ \| ___ | (_ _) ___ |/ ___) _ \ + * _____) ) ____| | | || |_| ____( (___| | | | + * (______/|_____)_|_|_| \__)_____)\____)_| |_| + * (C)2013-2018 Semtech - STMicroelectronics + * + * \endcode + * + * \author Miguel Luis ( Semtech ) + * + * \author Gregory Cristian ( Semtech ) + * + * \author MCD Application Team ( STMicroelectronics International ) + */ +/** + ****************************************************************************** + * @file stm32_systime.h + * @author MCD Application Team + * @brief System time functions implementation + ****************************************************************************** + * @attention + * + * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32_SYS_TIME_H__ +#define __STM32_SYS_TIME_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** @defgroup SYSTIME timer server + * @{ + */ + +/* Includes ------------------------------------------------------------------*/ +#include +#include "time.h" + + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup SYSTIME_exported_constants SYSTIME exported constants + * @{ + */ + +/*! +* @brief Days, Hours, Minutes and seconds of systime.h +*/ +#define TM_DAYS_IN_LEAP_YEAR ( ( uint32_t ) 366U ) +#define TM_DAYS_IN_YEAR ( ( uint32_t ) 365U ) +#define TM_SECONDS_IN_1DAY ( ( uint32_t )86400U ) +#define TM_SECONDS_IN_1HOUR ( ( uint32_t ) 3600U ) +#define TM_SECONDS_IN_1MINUTE ( ( uint32_t ) 60U ) +#define TM_MINUTES_IN_1HOUR ( ( uint32_t ) 60U ) +#define TM_HOURS_IN_1DAY ( ( uint32_t ) 24U ) + +/*! +* @brief Months of systime.h +*/ +#define TM_MONTH_JANUARY ( ( uint8_t ) 0U ) +#define TM_MONTH_FEBRUARY ( ( uint8_t ) 1U ) +#define TM_MONTH_MARCH ( ( uint8_t ) 2U ) +#define TM_MONTH_APRIL ( ( uint8_t ) 3U ) +#define TM_MONTH_MAY ( ( uint8_t ) 4U ) +#define TM_MONTH_JUNE ( ( uint8_t ) 5U ) +#define TM_MONTH_JULY ( ( uint8_t ) 6U ) +#define TM_MONTH_AUGUST ( ( uint8_t ) 7U ) +#define TM_MONTH_SEPTEMBER ( ( uint8_t ) 8U ) +#define TM_MONTH_OCTOBER ( ( uint8_t ) 9U ) +#define TM_MONTH_NOVEMBER ( ( uint8_t )10U ) +#define TM_MONTH_DECEMBER ( ( uint8_t )11U ) + +/*! +* @brief Week days of systime.h +*/ +#define TM_WEEKDAY_SUNDAY ( ( uint8_t )0U ) +#define TM_WEEKDAY_MONDAY ( ( uint8_t )1U ) +#define TM_WEEKDAY_TUESDAY ( ( uint8_t )2U ) +#define TM_WEEKDAY_WEDNESDAY ( ( uint8_t )3U ) +#define TM_WEEKDAY_THURSDAY ( ( uint8_t )4U ) +#define TM_WEEKDAY_FRIDAY ( ( uint8_t )5U ) +#define TM_WEEKDAY_SATURDAY ( ( uint8_t )6U ) + +/*! +* @brief Number of seconds elapsed between Unix epoch and GPS epoch +*/ +#define UNIX_GPS_EPOCH_OFFSET 315964800 + +/** + * @} + */ + +/* External Typedef --------------------------------------------------------*/ + +/** @defgroup SYSTIME_exported_TypeDef SYSTIME exported Typedef + * @{ + */ +/** + * @brief Structure holding the system time in seconds and milliseconds. + */ +typedef struct SysTime_s +{ +uint32_t Seconds; +int16_t SubSeconds; +}SysTime_t; + +/** + * @brief SysTime driver definition + */ +typedef struct +{ + void (*BKUPWrite_Seconds) ( uint32_t Seconds); /*!< Set the timer differencebetween real time and rtc time */ + uint32_t (*BKUPRead_Seconds) ( void ); /*!< Get the timer differencebetween real time and rtc time */ + void (*BKUPWrite_SubSeconds) ( uint32_t SubSeconds); /*!< Set the timer differencebetween real time and rtc time */ + uint32_t (*BKUPRead_SubSeconds) ( void ); /*!< Get the timer differencebetween real time and rtc time */ + uint32_t (*GetCalendarTime)( uint16_t* SubSeconds ); /*!< Set the rtc time */ +} UTIL_SYSTIM_Driver_s; + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/* Exported variables ------------------------------------------------------------*/ + +/** @defgroup SYSTIME_exported_Variable SYSTIME exported Variable + * @{ + */ +/** + * @brief low layer interface to handle systim + * + * @remark This structure is defined and initialized in the specific platform + * timer implementation e.g rtc + */ +extern const UTIL_SYSTIM_Driver_s UTIL_SYSTIMDriver; +/** + * @} + */ + +/* Exported functions ------------------------------------------------------- */ +/** @defgroup SYSTIME_exported_function SYSTIME exported function + * @{ + */ + +/*! +* @brief Adds 2 SysTime_t values +* +* @param a Value +* @param b Value to added +* +* @retval result Addition result (SysTime_t value) +*/ +SysTime_t SysTimeAdd( SysTime_t a, SysTime_t b ); + +/*! +* @brief Subtracts 2 SysTime_t values +* +* @param a Value +* @param b Value to be subtracted +* +* @retval result Subtraction result (SysTime_t value) +*/ +SysTime_t SysTimeSub( SysTime_t a, SysTime_t b ); + +/*! +* @brief Sets new system time +* +* @param sysTime New seconds/sub-seconds since UNIX epoch origin +*/ +void SysTimeSet( SysTime_t sysTime ); + +/*! +* @brief Gets current system time +* +* @retval sysTime Current seconds/sub-seconds since UNIX epoch origin +*/ +SysTime_t SysTimeGet( void ); + +/*! +* @brief Gets current MCU system time +* +* @retval sysTime Current seconds/sub-seconds since Mcu started +*/ +SysTime_t SysTimeGetMcuTime( void ); + +/*! +* Converts the given SysTime to the equivalent RTC value in milliseconds +* +* @param [IN] sysTime System time to be converted +* +* @retval timeMs The RTC converted time value in ms +*/ +uint32_t SysTimeToMs( SysTime_t sysTime ); + +/*! +* Converts the given RTC value in milliseconds to the equivalent SysTime +* +* \param [IN] timeMs The RTC time value in ms to be converted +* +* \retval sysTime Converted system time +*/ +SysTime_t SysTimeFromMs( uint32_t timeMs ); + +/*! +* @brief Convert a calendar time into time since UNIX epoch as a uint32_t. +* +* @param [IN] localtime Pointer to the object containing the calendar time +* @retval timestamp The calendar time as seconds since UNIX epoch. +*/ +uint32_t SysTimeMkTime( const struct tm* localtime ); + +/*! +* @brief Converts a given time in seconds since UNIX epoch into calendar time. +* +* @param [IN] timestamp The time since UNIX epoch to convert into calendar time. +* @param [OUT] localtime Pointer to the calendar time object which will contain +the result of the conversion. +*/ +void SysTimeLocalTime( const uint32_t timestamp, struct tm *localtime ); + +/** + * @} + */ +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32_SYS_TIME_H__ */ diff --git a/Utilities/misc/stm32_tiny_sscanf.c b/Utilities/misc/stm32_tiny_sscanf.c new file mode 100644 index 0000000..1e1f41b --- /dev/null +++ b/Utilities/misc/stm32_tiny_sscanf.c @@ -0,0 +1,992 @@ +/** + * Copyright (c) 1990 The Regents of the University of California. + * All rights reserved. + * + * Redistribution and use in source and binary forms are permitted + * provided that the above copyright notice and this paragraph are + * duplicated in all such forms and that any documentation, + * advertising materials, and other materials related to such + * distribution and use acknowledge that the software was developed + * by the University of California, Berkeley. The name of the + * University may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. + */ +/** + ****************************************************************************** + * @file stm32_tiny_sscanf.c + * @author MCD Application Team + * @brief Tiny implementation of sscanf + ****************************************************************************** + * @attention + * + * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + + +/* + * This code is derived from + * https://github.com/rapid7/metasploit-payloads/, in c/meterpreter/source/bionic/libc/stdio/sscanf.c + * It has been derived in order to optimize code size. In this context + * all the formats are not supported. Current supported formats are + * %hx, %hhx, %ul, %d,... + * when TINY_SSCANF is defined + * + * When TINY_NO_OX is defined, this is not possible to sscanf("%x") of "0xab", + * only "ab" is possible + * + * When TINY_SPACE_NOT_SPECIALCASE is defined, "space" is not a special character. + * That means that we expect a single space, and not any of ispace() character + * (space, tabs,...) + */ + +/* Includes ------------------------------------------------------------------*/ +#include +#include +#include +#include +#include +#include +#include "stm32_tiny_sscanf.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private defines -----------------------------------------------------------*/ +#define TINY_SSCANF +#define TINY_NO_OX +#define TINY_SPACE_NOT_SPECIALCASE + +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Functions Definition ------------------------------------------------------*/ + +#ifdef FLOATING_POINT +#include "floatio.h" +#endif + + +#define BUF 513 /* Maximum length of numeric string. */ + +/* + * Flags used during conversion. + */ +#define LONG 0x00001 /* l: long or double */ +#define SHORT 0x00004 /* h: short */ +#define SHORTSHORT 0x00008 /* hh: 8 bit integer */ +#define UNSIGNED 0x00800 /* %[oupxX] conversions */ +#ifdef TINY_SSCANF +#else +#define LONGDBL 0x00002 /* L: long double; unimplemented */ +#define LLONG 0x00010 /* ll: long long (+ deprecated q: quad) */ +#define POINTER 0x00020 /* p: void * (as hex) */ +#define SIZEINT 0x00040 /* z: (signed) size_t */ +#define MAXINT 0x00080 /* j: intmax_t */ +#define PTRINT 0x00100 /* t: ptrdiff_t */ +#define NOSKIP 0x00200 /* [ or c: do not skip blanks */ +#define SUPPRESS 0x00400 /* *: suppress assignment */ +#endif + +/* + * The following are used in numeric conversions only: + * SIGNOK, HAVESIGN, NDIGITS, DPTOK, and EXPOK are for floating point; + * SIGNOK, HAVESIGN, NDIGITS, PFXOK, and NZDIGITS are for integral. + */ +#define SIGNOK 0x01000 /* +/- is (still) legal */ +#define HAVESIGN 0x02000 /* sign detected */ +#define NDIGITS 0x04000 /* no digits detected */ + +#define DPTOK 0x08000 /* (float) decimal point is still legal */ +#define EXPOK 0x10000 /* (float) exponent (e+3, etc) still legal */ + +#ifdef TINY_NO_OX +#else +#define PFXOK 0x08000 /* 0x prefix is (still) legal */ +#define NZDIGITS 0x10000 /* no zero digits detected */ +#endif + +/* + * Conversion types. + */ +#define CT_INT 3 /* integer, i.e., strtoimax or strtoumax */ +#define CT_FLOAT 4 /* floating, i.e., strtod */ + +#ifdef TINY_SSCANF +#else +#define CT_CHAR 0 /* %c conversion */ +#define CT_CCL 1 /* %[...] conversion */ +#define CT_STRING 2 /* %s conversion */ +#endif + +#define u_char unsigned char +#define u_long unsigned long + +#ifdef TINY_SSCANF +#else +static u_char *__sccl(char *, u_char *); +#endif + +#define VFSCANF tiny_vfscanf + +#if !defined(VFSCANF) +#define VFSCANF vfscanf +#endif + + +#define __srefill(_x) 1 +#define ungetc(_c, _fp) do { (_c), fp_p--; fp_r++; } while (0) + + +/* + * vfscanf + */ + +static inline int +VFSCANF(const char *str, const char *fmt0, va_list ap) +{ + u_char *fmt = (u_char *)fmt0; + int c; /* character from format, or conversion */ + size_t width; /* field width, or 0 */ + char *p; /* points into all kinds of strings */ + int flags; /* flags as defined above */ + int nassigned; /* number of fields assigned */ + int nread; /* number of characters consumed from fp */ + int base; /* base argument to strtoimax/strtouimax */ + char buf[BUF]; /* buffer for numeric conversions */ + const char *fp_p; + int fp_r; + uintmax_t value; + int sign_minus; + + +#ifdef TINY_SSCANF +#else + int n; /* handy integer */ + char *p0; /* saves original value of p when necessary */ + char ccltab[256]; /* character class table for %[...] */ +#endif + + /* `basefix' is used to avoid `if' tests in the integer scanner */ +#ifdef TINY_SSCANF + /* basefix[] can be removed as we do not support %i */ +#else + static short basefix[17] = + { 10, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 }; +#endif + + fp_p = str; + fp_r = strlen(str); + + nassigned = 0; + nread = 0; + base = 0; /* XXX just to keep gcc happy */ + for (;;) { + c = *fmt++; + if (c == 0) + return (nassigned); +#ifdef TINY_SPACE_NOT_SPECIALCASE +#else + if (isspace(c)) { + while ((fp_r > 0 || __srefill(fp) == 0) && + isspace(*fp_p)) + nread++, fp_r--, fp_p++; + continue; + } +#endif + if (c != '%') + goto literal; + width = 0; + flags = 0; + /* + * switch on the format. continue if done; + * break once format type is derived. + */ +again: c = *fmt++; + switch (c) { + case '%': +literal: + if (fp_r <= 0 && __srefill(fp)) + goto input_failure; + if (*fp_p != c) + goto match_failure; + fp_r--, fp_p++; + nread++; + continue; + +#ifdef TINY_SSCANF +#else + case '*': + flags |= SUPPRESS; + goto again; + case 'j': + flags |= MAXINT; + goto again; + case 'L': + flags |= LONGDBL; + goto again; +#endif + case 'h': + if (*fmt == 'h') { + fmt++; + flags |= SHORTSHORT; + } else { + flags |= SHORT; + } + goto again; + case 'l': +#ifdef TINY_SSCANF + /* %ll not supported */ + flags |= LONG; + goto again; +#else + if (*fmt == 'l') { + fmt++; + flags |= LLONG; + } else { + flags |= LONG; + } + goto again; +#endif + +#ifdef TINY_SSCANF +#else + case 'q': + flags |= LLONG; /* deprecated */ + goto again; + case 't': + flags |= PTRINT; + goto again; + case 'z': + flags |= SIZEINT; + goto again; +#endif + case '0': case '1': case '2': case '3': case '4': + case '5': case '6': case '7': case '8': case '9': + width = width * 10 + c - '0'; + goto again; + + /* + * Conversions. + * Those marked `compat' are for 4.[123]BSD compatibility. + * + * (According to ANSI, E and X formats are supposed + * to the same as e and x. Sorry about that.) + */ + case 'D': /* compat */ + flags |= LONG; + /* FALLTHROUGH */ + case 'd': + c = CT_INT; + base = 10; + break; + +#ifdef TINY_SSCANF + /* + * We do not support %i to remove potential base=8 in the following + * Hence basefix can be removed + */ +#else + case 'i': + c = CT_INT; + base = 0; + break; +#endif + +#ifdef TINY_SSCANF +#else + case 'O': /* compat */ + flags |= LONG; + /* FALLTHROUGH */ + case 'o': + c = CT_INT; + flags |= UNSIGNED; + base = 8; + break; +#endif + + case 'u': + c = CT_INT; + flags |= UNSIGNED; + base = 10; + break; + + case 'X': + case 'x': +#ifdef TINY_NO_OX +#else + flags |= PFXOK; /* enable 0x prefixing */ +#endif + c = CT_INT; + flags |= UNSIGNED; + base = 16; + break; + +#ifdef FLOATING_POINT + case 'E': + case 'G': + case 'e': + case 'f': + case 'g': + c = CT_FLOAT; + break; +#endif + +#ifdef TINY_SSCANF +#else + case 's': + c = CT_STRING; + break; + + case '[': + fmt = __sccl(ccltab, fmt); + flags |= NOSKIP; + c = CT_CCL; + break; + + case 'c': + flags |= NOSKIP; + c = CT_CHAR; + break; + + case 'p': /* pointer format is like hex */ + flags |= POINTER | PFXOK; + c = CT_INT; + flags |= UNSIGNED; + base = 16; + break; + + case 'n': + if (flags & SUPPRESS) + continue; + if (flags & SHORTSHORT) + *va_arg(ap, char *) = nread; + else if (flags & SHORT) + *va_arg(ap, short *) = nread; + else if (flags & LONG) + *va_arg(ap, long *) = nread; + else if (flags & SIZEINT) + *va_arg(ap, size_t *) = nread; + else if (flags & PTRINT) + *va_arg(ap, ptrdiff_t *) = nread; + else if (flags & LLONG) + *va_arg(ap, long long *) = nread; + else if (flags & MAXINT) + *va_arg(ap, intmax_t *) = nread; + else + *va_arg(ap, int *) = nread; + continue; +#endif + + /* + * Disgusting backwards compatibility hacks. XXX + */ + case '\0': /* compat */ + return (EOF); + + default: /* compat */ +#ifdef TINY_SSCANF +#else + if (isupper(c)) + flags |= LONG; + c = CT_INT; + base = 10; +#endif + break; + } + + /* + * We have a conversion that requires input. + */ + if (fp_r <= 0 && __srefill(fp)) + goto input_failure; + + + /* + * Consume leading white space, except for formats + * that suppress this. + */ +#ifdef TINY_SSCANF +#else + if ((flags & NOSKIP) == 0) { + while (isspace(*fp_p)) { + nread++; + if (--fp_r > 0) + fp_p++; + else if (__srefill(fp)) + goto input_failure; + } + /* + * Note that there is at least one character in + * the buffer, so conversions that do not set NOSKIP + * ca no longer result in an input failure. + */ + } +#endif + + /* + * Do the conversion. + */ + switch (c) { +#ifdef TINY_SSCANF +#else + case CT_CHAR: + /* scan arbitrary characters (sets NOSKIP) */ + if (width == 0) + width = 1; + if (flags & SUPPRESS) { + size_t sum = 0; + for (;;) { + if ((n = fp_r) < (int)width) { + sum += n; + width -= n; + fp_p += n; + if (__srefill(fp)) { + if (sum == 0) + goto input_failure; + break; + } + } else { + sum += width; + fp_r -= width; + fp_p += width; + break; + } + } + nread += sum; + } else { + size_t r = fread((void *)va_arg(ap, char *), 1, + width, fp); + + if (r == 0) + goto input_failure; + nread += r; + nassigned++; + } + break; +#endif + +#ifdef TINY_SSCANF +#else + case CT_CCL: + /* scan a (nonempty) character class (sets NOSKIP) */ + if (width == 0) + width = (size_t)~0; /* `infinity' */ + /* take only those things in the class */ + if (flags & SUPPRESS) { + n = 0; + while (ccltab[*fp_p]) { + n++, fp_r--, fp_p++; + if (--width == 0) + break; + if (fp_r <= 0 && __srefill(fp)) { + if (n == 0) + goto input_failure; + break; + } + } + if (n == 0) + goto match_failure; + } else { + p0 = p = va_arg(ap, char *); + while (ccltab[*fp_p]) { + fp_r--; + *p++ = *fp_p++; + if (--width == 0) + break; + if (fp_r <= 0 && __srefill(fp)) { + if (p == p0) + goto input_failure; + break; + } + } + n = p - p0; + if (n == 0) + goto match_failure; + *p = '\0'; + nassigned++; + } + nread += n; + break; +#endif + +#ifdef TINY_SSCANF +#else + case CT_STRING: + /* like CCL, but zero-length string OK, & no NOSKIP */ + if (width == 0) + width = (size_t)~0; + if (flags & SUPPRESS) { + n = 0; + while (!isspace(*fp_p)) { + n++, fp_r--, fp_p++; + if (--width == 0) + break; + if (fp_r <= 0 && __srefill(fp)) + break; + } + nread += n; + } else { + p0 = p = va_arg(ap, char *); + while (!isspace(*fp_p)) { + fp_r--; + *p++ = *fp_p++; + if (--width == 0) + break; + if (fp_r <= 0 && __srefill(fp)) + break; + } + *p = '\0'; + nread += p - p0; + nassigned++; + } + continue; +#endif + + case CT_INT: + /* scan an integer as if by strtoimax/strtoumax */ +#ifdef hardway + if (width == 0 || width > sizeof(buf) - 1) + width = sizeof(buf) - 1; +#else + /* size_t is unsigned, hence this optimisation */ + if (--width > sizeof(buf) - 2) + width = sizeof(buf) - 2; + width++; +#endif + +#ifdef TINY_NO_OX + flags |= SIGNOK | NDIGITS; +#else + flags |= SIGNOK | NDIGITS | NZDIGITS; +#endif + + sign_minus = 0; + value = 0; + for (p = buf; width; width--) { + c = *fp_p; + /* + * Switch on the character; `goto ok' + * if we accept it as a part of number. + */ + switch (c) { + + /* + * The digit 0 is always legal, but is + * special. For %i conversions, if no + * digits (zero or nonzero) have been + * scanned (only signs), we will have + * base==0. In that case, we should set + * it to 8 and enable 0x prefixing. + * Also, if we have not scanned zero digits + * before this, do not turn off prefixing + * (someone else will turn it off if we + * have scanned any nonzero digits). + */ + case '0': +#ifdef TINY_NO_OX + /* FALLTHROUGH */ +#else +#ifdef TINY_SSCANF +#else + if (base == 0) { + base = 8; + flags |= PFXOK; + } +#endif + if (!(flags & NDIGITS)) { + value = value * base; + } + + if (flags & NZDIGITS) + flags &= ~(SIGNOK|NZDIGITS|NDIGITS); + else + flags &= ~(SIGNOK|PFXOK|NDIGITS); + goto ok; +#endif + +#ifdef TINY_SSCANF + /* we only support base 10 and 16 */ + case '1': case '2': case '3': + case '4': case '5': case '6': case '7': + case '8': case '9': +#ifdef TINY_NO_OX + flags &= ~(SIGNOK | NDIGITS); +#else + flags &= ~(SIGNOK | PFXOK | NDIGITS); +#endif + value = value * base + c - '0'; + goto ok; +#else + /* 1 through 7 always legal */ + case '1': case '2': case '3': + case '4': case '5': case '6': case '7': + base = basefix[base]; + flags &= ~(SIGNOK | PFXOK | NDIGITS); + value = value * base + c - '0'; + goto ok; + + /* digits 8 and 9 ok iff decimal or hex */ + case '8': case '9': + base = basefix[base]; + if (base <= 8) + break; /* not legal here */ + flags &= ~(SIGNOK | PFXOK | NDIGITS); + value = value * base + c - '0'; + goto ok; +#endif + + /* letters ok iff hex */ + case 'A': case 'B': case 'C': + case 'D': case 'E': case 'F': + /* no need to fix base here */ + if (base <= 10) + break; /* not legal here */ +#ifdef TINY_NO_OX + flags &= ~(SIGNOK | NDIGITS); +#else + flags &= ~(SIGNOK | PFXOK | NDIGITS); +#endif + value = value * base + c - 'A' + 10; + goto ok; + + case 'a': case 'b': case 'c': + case 'd': case 'e': case 'f': + /* no need to fix base here */ + if (base <= 10) + break; /* not legal here */ +#ifdef TINY_NO_OX + flags &= ~(SIGNOK | NDIGITS); +#else + flags &= ~(SIGNOK | PFXOK | NDIGITS); +#endif + value = value * base + c - 'a' + 10; + goto ok; + + /* sign ok only as first character */ + case '-': + if (!(flags & HAVESIGN)) { + sign_minus = 1; + } + /* FALLTHROUGH */ + case '+': + if (flags & SIGNOK) { + flags &= ~SIGNOK; + flags |= HAVESIGN; + goto ok; + } + break; + + /* + * x ok iff flag still set and 2nd char (or + * 3rd char if we have a sign). + */ +#ifdef TINY_NO_OX +#else + case 'x': case 'X': + if ((flags & PFXOK) && p == + buf + 1 + !!(flags & HAVESIGN)) { + base = 16; /* if %i */ + flags &= ~PFXOK; + goto ok; + } + break; +#endif + } + + /* + * If we got here, c is not a legal character + * for a number. Stop accumulating digits. + */ + break; + ok: + /* + * c is legal: store it and look at the next. + */ + *p++ = c; + if (--fp_r > 0) + fp_p++; + else if (__srefill(fp)) + break; /* EOF */ + } + /* + * If we had only a sign, it is no good; push + * back the sign. If the number ends in `x', + * it was [sign] '0' 'x', so push back the x + * and treat it as [sign] '0'. + */ + if (flags & NDIGITS) { + if (p > buf) + { + --c; + --p; + ungetc(c++, fp); + /* There is a dummy post-increment to + avoid an unused value warning */ + } + goto match_failure; + } +#ifdef TINY_NO_OX +#else + c = ((u_char *)p)[-1]; + if (c == 'x' || c == 'X') { + --p; + ungetc(c, fp); + } +#endif + +#ifdef TINY_SSCANF + { +#else + if ((flags & SUPPRESS) == 0) { +#endif + + *p = '\0'; + if (sign_minus) + value = -value; + +#ifdef TINY_SSCANF +#else + if (flags & POINTER) + *va_arg(ap, void **) = + (void *)(uintptr_t)value; + else if (flags & MAXINT) + *va_arg(ap, intmax_t *) = value; + else if (flags & LLONG) + *va_arg(ap, long long *) = value; + else if (flags & SIZEINT) + *va_arg(ap, size_t *) = value; + else if (flags & PTRINT) + *va_arg(ap, ptrdiff_t *) = value; + else +#endif + if (flags & LONG) + *va_arg(ap, long *) = value; + else if (flags & SHORT) + *va_arg(ap, short *) = value; + else if (flags & SHORTSHORT) + *va_arg(ap, char *) = value; + else + *va_arg(ap, int *) = value; + nassigned++; + } + nread += p - buf; + break; + +#ifdef FLOATING_POINT + case CT_FLOAT: + /* scan a floating point number as if by strtod */ +#ifdef hardway + if (width == 0 || width > sizeof(buf) - 1) + width = sizeof(buf) - 1; +#else + /* size_t is unsigned, hence this optimisation */ + if (--width > sizeof(buf) - 2) + width = sizeof(buf) - 2; + width++; +#endif + flags |= SIGNOK | NDIGITS | DPTOK | EXPOK; + for (p = buf; width; width--) { + c = *fp->_p; + /* + * This code mimics the integer conversion + * code, but is much simpler. + */ + switch (c) { + + case '0': case '1': case '2': case '3': + case '4': case '5': case '6': case '7': + case '8': case '9': + flags &= ~(SIGNOK | NDIGITS); + goto fok; + + case '+': case '-': + if (flags & SIGNOK) { + flags &= ~SIGNOK; + goto fok; + } + break; + case '.': + if (flags & DPTOK) { + flags &= ~(SIGNOK | DPTOK); + goto fok; + } + break; + case 'e': case 'E': + /* no exponent without some digits */ + if ((flags&(NDIGITS|EXPOK)) == EXPOK) { + flags = + (flags & ~(EXPOK|DPTOK)) | + SIGNOK | NDIGITS; + goto fok; + } + break; + } + break; + fok: + *p++ = c; + if (--fp->_r > 0) + fp->_p++; + else if (__srefill(fp)) + break; /* EOF */ + } + /* + * If no digits, might be missing exponent digits + * (just give back the exponent) or might be missing + * regular digits, but had sign and/or decimal point. + */ + if (flags & NDIGITS) { + if (flags & EXPOK) { + /* no digits at all */ + while (p > buf) + ungetc(*(u_char *)--p, fp); + goto match_failure; + } + /* just a bad exponent (e and maybe sign) */ + c = *(u_char *)--p; + if (c != 'e' && c != 'E') { + (void) ungetc(c, fp);/* sign */ + c = *(u_char *)--p; + } + (void) ungetc(c, fp); + } + if ((flags & SUPPRESS) == 0) { + double res; + + *p = '\0'; + res = strtod(buf, (char **) NULL); + if (flags & LONGDBL) + *va_arg(ap, long double *) = res; + else if (flags & LONG) + *va_arg(ap, double *) = res; + else + *va_arg(ap, float *) = res; + nassigned++; + } + nread += p - buf; + break; +#endif /* FLOATING_POINT */ + } + } +input_failure: + return (nassigned ? nassigned : -1); +match_failure: + return (nassigned); +} + +#ifdef TINY_SSCANF +#else +/* + * Fill in the given table from the scanset at the given format + * (just after `['). Return a pointer to the character past the + * closing `]'. The table has a 1 wherever characters should be + * considered part of the scanset. + */ +static u_char * +__sccl(char *tab, u_char *fmt) +{ + int c, n, v; + + /* first `clear' the whole table */ + c = *fmt++; /* first char hat => negated scanset */ + if (c == '^') { + v = 1; /* default => accept */ + c = *fmt++; /* get new first char */ + } else + v = 0; /* default => reject */ + /* should probably use memset here */ + for (n = 0; n < 256; n++) + tab[n] = v; + if (c == 0) + return (fmt - 1);/* format ended before closing ] */ + + /* + * Now set the entries corresponding to the actual scanset + * to the opposite of the above. + * + * The first character may be ']' (or '-') without being special; + * the last character may be '-'. + */ + v = 1 - v; + for (;;) { + tab[c] = v; /* take character c */ +doswitch: + n = *fmt++; /* and examine the next */ + switch (n) { + + case 0: /* format ended too soon */ + return (fmt - 1); + + case '-': + /* + * A scanset of the form + * [01+-] + * is defined as `the digit 0, the digit 1, + * the character +, the character -', but + * the effect of a scanset such as + * [a-zA-Z0-9] + * is implementation defined. The V7 Unix + * scanf treats `a-z' as `the letters a through + * z', but treats `a-a' as `the letter a, the + * character -, and the letter a'. + * + * For compatibility, the `-' is not considered + * to define a range if the character following + * it is either a close bracket (required by ANSI) + * or is not numerically greater than the character + * we just stored in the table (c). + */ + n = *fmt; + if (n == ']' || n < c) { + c = '-'; + break; /* resume the for(;;) */ + } + fmt++; + do { /* fill in the range */ + tab[++c] = v; + } while (c < n); +#if 1 /* XXX another disgusting compatibility hack */ + /* + * Alas, the V7 Unix scanf also treats formats + * such as [a-c-e] as `the letters a through e'. + * This too is permitted by the standard.... + */ + goto doswitch; +#else + c = *fmt++; + if (c == 0) + return (fmt - 1); + if (c == ']') + return (fmt); +#endif + break; + + case ']': /* end of scanset */ + return (fmt); + + default: /* just another character */ + c = n; + break; + } + } + /* NOTREACHED */ +} +#endif + +int +tiny_sscanf(const char *str, const char *fmt, ...) +{ + int ret; + va_list ap; + + va_start(ap, fmt); + ret = tiny_vfscanf(str, fmt, ap); + va_end(ap); + return (ret); +} diff --git a/Utilities/misc/stm32_tiny_sscanf.h b/Utilities/misc/stm32_tiny_sscanf.h new file mode 100644 index 0000000..03a677f --- /dev/null +++ b/Utilities/misc/stm32_tiny_sscanf.h @@ -0,0 +1,65 @@ +/** + ****************************************************************************** + * @file stm32_tiny_sscanf.h + * @author MCD Application Team + * @brief Header for driver tiny_sscanf.c module + ****************************************************************************** + * @attention + * + * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32_TINY_SSCANF_H__ +#define __STM32_TINY_SSCANF_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif +/* Includes ------------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* External variables --------------------------------------------------------*/ +/* Exported macros -----------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +/** + * @brief Read formatted data from string + * + * Reads data from s and stores them according to parameter format into the + * locations given by the additional arguments, as if scanf was used, but + * reading from s instead of the standard input (stdin). + * + * The additional arguments should point to already allocated objects of the + * type specified by their corresponding format specifier within the format string. + * + * @param C string that the function processes as its source to retrieve the data. + * @param C string that contains a format string that follows the same specifications + * as format in scanf (see scanf for details). + * @param Depending on the format string, the function may expect a sequence of + * additional arguments, each containing a pointer to allocated storage + * where the interpretation of the extracted characters is stored with + * the appropriate type. + * There should be at least as many of these arguments as the number of + * values stored by the format specifiers. Additional arguments are + * ignored by the function. + * @retval The number of items in the argument list successfully filled. This + * count can match the expected number of items or be less (even zero) + * in the case of a matching failure + * @note Current supported formats are %hx, %hhx, %ul, %d,... + */ +int tiny_sscanf(const char *str, const char *fmt, ...); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32_TINY_SSCANF_H__ */ diff --git a/Utilities/misc/stm32_tiny_vsnprintf.c b/Utilities/misc/stm32_tiny_vsnprintf.c new file mode 100644 index 0000000..3cf2ad0 --- /dev/null +++ b/Utilities/misc/stm32_tiny_vsnprintf.c @@ -0,0 +1,695 @@ +/** + Copyright (C) 2002 Michael Ringgaard. All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + + 1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + 3. Neither the name of the project nor the names of its contributors + may be used to endorse or promote products derived from this software + without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE + FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + SUCH DAMAGE. +*/ +/** + ****************************************************************************** + * @file stm32_tiny_vsnprintf.c + * @author MCD Application Team + * @brief Tiny implementation of vsnprintf like function + ****************************************************************************** + * @attention + * + * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* + * Following implementation is adapted from original one + * https://github.com/jpbonn/coremark_lm32/blob/master/ee_printf.c + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32_tiny_vsnprintf.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private defines -----------------------------------------------------------*/ +#define TINY_PRINTF + +#define ZEROPAD (1<<0) /* Pad with zero */ +#define SIGN (1<<1) /* Unsigned/signed long */ +#define UPPERCASE (1<<6) /* 'ABCDEF' */ +#ifdef TINY_PRINTF +#else +#define PLUS (1<<2) /* Show plus */ +#define HEX_PREP (1<<5) /* 0x */ +#define SPACE (1<<3) /* Spacer */ +#define LEFT (1<<4) /* Left justified */ +#endif + +#define is_digit(c) ((c) >= '0' && (c) <= '9') + +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Global variables ----------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ + +static char *lower_digits = "0123456789abcdefghijklmnopqrstuvwxyz"; +static char *upper_digits = "0123456789ABCDEFGHIJKLMNOPQRSTUVWXYZ"; + +/* Functions Definition ------------------------------------------------------*/ +#ifdef TINY_PRINTF +#else +static size_t strnlen(const char *s, size_t count); + +static size_t strnlen(const char *s, size_t count) +{ + const char *sc; + for (sc = s; *sc != '\0' && count--; ++sc); + return sc - s; +} +#endif + +static int ee_skip_atoi(const char **s) +{ + int i = 0; + while (is_digit(**s)) i = i*10 + *((*s)++) - '0'; + return i; +} + +#define ASSIGN_STR(_c) do { *str++ = (_c); max_size--; if (max_size == 0) return str; } while (0) + +static char *ee_number(char *str, int max_size, long num, int base, int size, int precision, int type) +{ + char c; + char sign, tmp[66]; + char *dig = lower_digits; + int i; + + if (type & UPPERCASE) dig = upper_digits; +#ifdef TINY_PRINTF +#else + if (type & LEFT) type &= ~ZEROPAD; +#endif + if (base < 2 || base > 36) return 0; + + c = (type & ZEROPAD) ? '0' : ' '; + sign = 0; + if (type & SIGN) + { + if (num < 0) + { + sign = '-'; + num = -num; + size--; + } +#ifdef TINY_PRINTF +#else + else if (type & PLUS) + { + sign = '+'; + size--; + } + else if (type & SPACE) + { + sign = ' '; + size--; + } +#endif + } + +#ifdef TINY_PRINTF +#else + if (type & HEX_PREP) + { + if (base == 16) + size -= 2; + else if (base == 8) + size--; + } +#endif + + i = 0; + + if (num == 0) + tmp[i++] = '0'; + else + { + while (num != 0) + { + tmp[i++] = dig[((unsigned long) num) % (unsigned) base]; + num = ((unsigned long) num) / (unsigned) base; + } + } + + if (i > precision) precision = i; + size -= precision; + if (!(type & (ZEROPAD /* TINY option | LEFT */))) while (size-- > 0) ASSIGN_STR(' '); + if (sign) ASSIGN_STR(sign); + +#ifdef TINY_PRINTF +#else + if (type & HEX_PREP) + { + if (base == 8) + ASSIGN_STR('0'); + else if (base == 16) + { + ASSIGN_STR('0'); + ASSIGN_STR(lower_digits[33]); + } + } +#endif + +#ifdef TINY_PRINTF + while (size-- > 0) ASSIGN_STR(c); +#else + if (!(type & LEFT)) while (size-- > 0) ASSIGN_STR(c); +#endif + while (i < precision--) ASSIGN_STR('0'); + while (i-- > 0) ASSIGN_STR(tmp[i]); + while (size-- > 0) ASSIGN_STR(' '); + + return str; +} + +#ifdef TINY_PRINTF +#else +static char *eaddr(char *str, unsigned char *addr, int size, int precision, int type) +{ + char tmp[24]; + char *dig = lower_digits; + int i, len; + + if (type & UPPERCASE) dig = upper_digits; + len = 0; + for (i = 0; i < 6; i++) + { + if (i != 0) tmp[len++] = ':'; + tmp[len++] = dig[addr[i] >> 4]; + tmp[len++] = dig[addr[i] & 0x0F]; + } + + if (!(type & LEFT)) while (len < size--) *str++ = ' '; + for (i = 0; i < len; ++i) *str++ = tmp[i]; + while (len < size--) *str++ = ' '; + + return str; +} + +static char *iaddr(char *str, unsigned char *addr, int size, int precision, int type) +{ + char tmp[24]; + int i, n, len; + + len = 0; + for (i = 0; i < 4; i++) + { + if (i != 0) tmp[len++] = '.'; + n = addr[i]; + + if (n == 0) + tmp[len++] = lower_digits[0]; + else + { + if (n >= 100) + { + tmp[len++] = lower_digits[n / 100]; + n = n % 100; + tmp[len++] = lower_digits[n / 10]; + n = n % 10; + } + else if (n >= 10) + { + tmp[len++] = lower_digits[n / 10]; + n = n % 10; + } + + tmp[len++] = lower_digits[n]; + } + } + + if (!(type & LEFT)) while (len < size--) *str++ = ' '; + for (i = 0; i < len; ++i) *str++ = tmp[i]; + while (len < size--) *str++ = ' '; + + return str; +} +#endif + +#ifdef HAS_FLOAT + +char *ecvtbuf(double arg, int ndigits, int *decpt, int *sign, char *buf); +char *fcvtbuf(double arg, int ndigits, int *decpt, int *sign, char *buf); +static void ee_bufcpy(char *d, char *s, int count); + +void ee_bufcpy(char *pd, char *ps, int count) { + char *pe=ps+count; + while (ps!=pe) + *pd++=*ps++; +} + +static void parse_float(double value, char *buffer, char fmt, int precision) +{ + int decpt, sign, exp, pos; + char *fdigits = NULL; + char cvtbuf[80]; + int capexp = 0; + int magnitude; + + if (fmt == 'G' || fmt == 'E') + { + capexp = 1; + fmt += 'a' - 'A'; + } + + if (fmt == 'g') + { + fdigits = ecvtbuf(value, precision, &decpt, &sign, cvtbuf); + magnitude = decpt - 1; + if (magnitude < -4 || magnitude > precision - 1) + { + fmt = 'e'; + precision -= 1; + } + else + { + fmt = 'f'; + precision -= decpt; + } + } + + if (fmt == 'e') + { + fdigits = ecvtbuf(value, precision + 1, &decpt, &sign, cvtbuf); + + if (sign) *buffer++ = '-'; + *buffer++ = *fdigits; + if (precision > 0) *buffer++ = '.'; + ee_bufcpy(buffer, fdigits + 1, precision); + buffer += precision; + *buffer++ = capexp ? 'E' : 'e'; + + if (decpt == 0) + { + if (value == 0.0) + exp = 0; + else + exp = -1; + } + else + exp = decpt - 1; + + if (exp < 0) + { + *buffer++ = '-'; + exp = -exp; + } + else + *buffer++ = '+'; + + buffer[2] = (exp % 10) + '0'; + exp = exp / 10; + buffer[1] = (exp % 10) + '0'; + exp = exp / 10; + buffer[0] = (exp % 10) + '0'; + buffer += 3; + } + else if (fmt == 'f') + { + fdigits = fcvtbuf(value, precision, &decpt, &sign, cvtbuf); + if (sign) *buffer++ = '-'; + if (*fdigits) + { + if (decpt <= 0) + { + *buffer++ = '0'; + *buffer++ = '.'; + for (pos = 0; pos < -decpt; pos++) *buffer++ = '0'; + while (*fdigits) *buffer++ = *fdigits++; + } + else + { + pos = 0; + while (*fdigits) + { + if (pos++ == decpt) *buffer++ = '.'; + *buffer++ = *fdigits++; + } + } + } + else + { + *buffer++ = '0'; + if (precision > 0) + { + *buffer++ = '.'; + for (pos = 0; pos < precision; pos++) *buffer++ = '0'; + } + } + } + + *buffer = '\0'; +} + +static void decimal_point(char *buffer) +{ + while (*buffer) + { + if (*buffer == '.') return; + if (*buffer == 'e' || *buffer == 'E') break; + buffer++; + } + + if (*buffer) + { + int n = strnlen(buffer,256); + while (n > 0) + { + buffer[n + 1] = buffer[n]; + n--; + } + + *buffer = '.'; + } + else + { + *buffer++ = '.'; + *buffer = '\0'; + } +} + +static void cropzeros(char *buffer) +{ + char *stop; + + while (*buffer && *buffer != '.') buffer++; + if (*buffer++) + { + while (*buffer && *buffer != 'e' && *buffer != 'E') buffer++; + stop = buffer--; + while (*buffer == '0') buffer--; + if (*buffer == '.') buffer--; + while (buffer!=stop) + *++buffer=0; + } +} + +static char *flt(char *str, double num, int size, int precision, char fmt, int flags) +{ + char tmp[80]; + char c, sign; + int n, i; + + // Left align means no zero padding +#ifdef TINY_PRINTF +#else + if (flags & LEFT) flags &= ~ZEROPAD; +#endif + + // Determine padding and sign char + c = (flags & ZEROPAD) ? '0' : ' '; + sign = 0; + if (flags & SIGN) + { + if (num < 0.0) + { + sign = '-'; + num = -num; + size--; + } +#ifdef TINY_PRINTF +#else + else if (flags & PLUS) + { + sign = '+'; + size--; + } + else if (flags & SPACE) + { + sign = ' '; + size--; + } +#endif + } + + // Compute the precision value + if (precision < 0) + precision = 6; // Default precision: 6 + + // Convert floating point number to text + parse_float(num, tmp, fmt, precision); + +#ifdef TINY_PRINTF +#else + if ((flags & HEX_PREP) && precision == 0) decimal_point(tmp); +#endif + if (fmt == 'g' && !(flags & HEX_PREP)) cropzeros(tmp); + + n = strnlen(tmp,256); + + // Output number with alignment and padding + size -= n; + if (!(flags & (ZEROPAD | LEFT))) while (size-- > 0) *str++ = ' '; + if (sign) *str++ = sign; + if (!(flags & LEFT)) while (size-- > 0) *str++ = c; + for (i = 0; i < n; i++) *str++ = tmp[i]; + while (size-- > 0) *str++ = ' '; + + return str; +} + +#endif + +#define CHECK_STR_SIZE(_buf, _str, _size) \ + if ((((_str) - (_buf)) >= ((_size)-1))) { break; } + +int tiny_vsnprintf_like(char *buf, const int size, const char *fmt, va_list args) +{ + unsigned long num; + int base; + char *str; + int len; + int i; + char *s; + + int flags; // Flags to number() + + int field_width; // Width of output field + int precision; // Min. # of digits for integers; max number of chars for from string + int qualifier; // 'h', 'l', or 'L' for integer fields + + if (size <= 0) + { + return 0; + } + + for (str = buf; *fmt || ((str - buf) >= size-1); fmt++) + { + CHECK_STR_SIZE(buf, str, size); + + if (*fmt != '%') + { + *str++ = *fmt; + continue; + } + + // Process flags + flags = 0; +#ifdef TINY_PRINTF + /* Support %0, but not %-, %+, %space and %# */ + fmt++; + if (*fmt == '0') + { + flags |= ZEROPAD; + } +#else +repeat: + fmt++; // This also skips first '%' + switch (*fmt) + { + case '-': flags |= LEFT; goto repeat; + case '+': flags |= PLUS; goto repeat; + case ' ': flags |= SPACE; goto repeat; + case '#': flags |= HEX_PREP; goto repeat; + case '0': flags |= ZEROPAD; goto repeat; + } +#endif + + // Get field width + field_width = -1; + if (is_digit(*fmt)) + field_width = ee_skip_atoi(&fmt); +#ifdef TINY_PRINTF + /* Does not support %* */ +#else + else if (*fmt == '*') + { + fmt++; + field_width = va_arg(args, int); + if (field_width < 0) + { + field_width = -field_width; + flags |= LEFT; + } + } +#endif + + // Get the precision + precision = -1; +#ifdef TINY_PRINTF + /* Does not support %. */ +#else + if (*fmt == '.') + { + ++fmt; + if (is_digit(*fmt)) + precision = ee_skip_atoi(&fmt); + else if (*fmt == '*') + { + ++fmt; + precision = va_arg(args, int); + } + if (precision < 0) precision = 0; + } +#endif + + // Get the conversion qualifier + qualifier = -1; +#ifdef TINY_PRINTF + /* Does not support %l and %L */ +#else + if (*fmt == 'l' || *fmt == 'L') + { + qualifier = *fmt; + fmt++; + } +#endif + + // Default base + base = 10; + + switch (*fmt) + { + case 'c': +#ifdef TINY_PRINTF +#else + if (!(flags & LEFT)) +#endif + while (--field_width > 0) *str++ = ' '; + *str++ = (unsigned char) va_arg(args, int); +#ifdef TINY_PRINTF +#else + while (--field_width > 0) *str++ = ' '; +#endif + continue; + + case 's': + s = va_arg(args, char *); + if (!s) s = ""; +#ifdef TINY_PRINTF + len = strlen(s); +#else + len = strnlen(s, precision); + if (!(flags & LEFT)) +#endif + while (len < field_width--) *str++ = ' '; + for (i = 0; i < len; ++i) *str++ = *s++; +#ifdef TINY_PRINTF +#else + while (len < field_width--) *str++ = ' '; +#endif + continue; + +#ifdef TINY_PRINTF + /* Does not support %p, %A, %a, %o */ +#else + case 'p': + if (field_width == -1) + { + field_width = 2 * sizeof(void *); + flags |= ZEROPAD; + } + str = ee_number(str, (size - (str - buf)), (unsigned long) va_arg(args, void *), 16, field_width, precision, flags); + continue; + + case 'A': + flags |= UPPERCASE; + + case 'a': + if (qualifier == 'l') + str = eaddr(str, va_arg(args, unsigned char *), field_width, precision, flags); + else + str = iaddr(str, va_arg(args, unsigned char *), field_width, precision, flags); + continue; + + // Integer number formats - set up the flags and "break" + case 'o': + base = 8; + break; +#endif + + case 'X': + flags |= UPPERCASE; + + case 'x': + base = 16; + break; + + case 'd': + case 'i': + flags |= SIGN; + + case 'u': + break; + +#ifdef HAS_FLOAT + + case 'f': + str = flt(str, va_arg(args, double), field_width, precision, *fmt, flags | SIGN); + continue; + +#endif + + default: + if (*fmt != '%') *str++ = '%'; + CHECK_STR_SIZE(buf, str, size); + if (*fmt) + *str++ = *fmt; + else + --fmt; + CHECK_STR_SIZE(buf, str, size); + continue; + } + + if (qualifier == 'l') + num = va_arg(args, unsigned long); + else if (flags & SIGN) + num = va_arg(args, int); + else + num = va_arg(args, unsigned int); + + str = ee_number(str, ((size - 1) - (str - buf)), num, base, field_width, precision, flags); + } + + *str = '\0'; + return str - buf; +} diff --git a/Utilities/misc/stm32_tiny_vsnprintf.h b/Utilities/misc/stm32_tiny_vsnprintf.h new file mode 100644 index 0000000..61a358f --- /dev/null +++ b/Utilities/misc/stm32_tiny_vsnprintf.h @@ -0,0 +1,60 @@ +/** + ****************************************************************************** + * @file stm32_tiny_vsnprintf.h + * @author MCD Application Team + * @brief Header for tiny_vsnprintf.c module + ****************************************************************************** + * @attention + * + * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32_TINY_VSNPRINTF_H__ +#define __STM32_TINY_VSNPRINTF_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif +/* Includes ------------------------------------------------------------------*/ +#include +#include +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* External variables --------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +/** + * @brief Tiny implementation of vsnprintf() like function + * + * It has been adapted so that: + * - Tiny implementation, when defining TINY_PRINTF, is available. In such as case, + * not all the format are available. Instead, only %02X, %x, %d, %u, %s and %c are available. + * %f,, %+, %#, %- and others are excluded + * - Provide a snprintf like implementation. The size of the buffer is provided, + * and the length of the filled buffer is returned (not including the final '\0' char). + * The string may be truncated + * @param Pointer to a buffer where the resulting C-string is stored. The buffer should have a size of + * at least n characters. + * @param Maximum number of bytes to be used in the buffer. The generated string has a length of at + * most n-1, leaving space for the additional terminating null character. + * @param C string that contains a format string that follows the same specifications as format + * in printf (see printf for details). + * @param A value identifying a variable arguments list initialized with va_start. + * @retval The number of written char (note that this is different from vsnprintf() + */ +int tiny_vsnprintf_like(char *buf, const int size, const char *fmt, va_list args); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32_TINY_VSNPRINTF_H__ */ diff --git a/Utilities/sequencer/Release_Notes.html b/Utilities/sequencer/Release_Notes.html new file mode 100644 index 0000000..59d3286 --- /dev/null +++ b/Utilities/sequencer/Release_Notes.html @@ -0,0 +1,390 @@ + + + + + + + Release Notes for STM32 sequencer + + + + + +
+
+
+
+
+

Release Notes for STM32 sequencer

+

Copyright © 2019 STMicroelectronics
+

+ +
+
+
+

Purpose

+

The source code delivered is an utility to help the task scheduling inside a system without OS.

+
+
+

Update History

+
+ +
+

Main Changes

+

Maintenance release

+ + + + + + + + + + + + + + + + + +
Headline
Ticket 104404 - Some events may be lost due to race conditions (rework)
Ticket 115234 - [Licensing] Update the way to declare licenses in Cube and X-CUBE components
Documentation update
+

Known Limitations

+

Outstanding bugs list : None

+

Requirements not met or planned in a forthcoming release : None

+

Development Toolchains and Compilers

+
    +
  • IAR Embedded Workbench for ARM (EWARM) toolchain V8.20.2
    • +
  • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.25
    • +
  • System Workbench STM32 (SW4STM32) toolchain V2.7.2
    • +
+

Backward compatibility

+

No compatibility break with previous version

+
+
+
+ +
+

Main Changes

+

Maintenance release

+ + + + + + + + + + + +
Headline
Ticket 104404 - Some events may be lost due to race conditions
+

Known Limitations

+

Outstanding bugs list : None

+

Requirements not met or planned in a forthcoming release : None

+

Development Toolchains and Compilers

+
    +
  • IAR Embedded Workbench for ARM (EWARM) toolchain V8.20.2
    • +
  • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.25
    • +
  • System Workbench STM32 (SW4STM32) toolchain V2.7.2
    • +
+

Backward compatibility

+

No compatibility break with previous version

+
+
+
+ +
+

Main Changes

+

Maintenance release

+ + + + + + + + + + + +
Headline
Ticket 86948 - CodeSpell : Correct some english words typo
+

Known Limitations

+

Outstanding bugs list : None

+

Requirements not met or planned in a forthcoming release : None

+

Development Toolchains and Compilers

+
    +
  • IAR Embedded Workbench for ARM (EWARM) toolchain V8.20.2
    • +
  • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.25
    • +
  • System Workbench STM32 (SW4STM32) toolchain V2.7.2
    • +
+

Backward compatibility

+

No compatibility break with previous version

+
+
+
+ +
+

Main Changes

+

Maintenance release

+ + + + + + + + + + + + + + + + + +
Headline
Ticket 91315 - Four lines of code should be under a __weak function to allow overcharge it for unprivileged mode
Ticket 89624 - Utilities Releases Notes improvements - Link on openorg BSD-3-Clause
Ticket 86948 - CodeSpell : Correct some english words typo
+

Known Limitations

+

Outstanding bugs list : None

+

Requirements not met or planned in a forthcoming release : None

+

Development Toolchains and Compilers

+
    +
  • IAR Embedded Workbench for ARM (EWARM) toolchain V8.20.2
    • +
  • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.25
    • +
  • System Workbench STM32 (SW4STM32) toolchain V2.7.2
    • +
+

Backward compatibility

+

No compatibility break with previous version

+
+
+
+ +
+

Main Changes

+

Maintenance release

+ + + + + + + + + + + + + + + + + + + + +
Headline
Doxygen update
[78010][UTILITIES][SEQ] update the function UTIL_SEQ_EvtIdle to allow the run of all tasks except the task waiting for an event
[78143][UTILITIES][SEQ] UTIL_SEQ_RFU definition has been wrongly removed from UTIL_Seq.h
[77834][UTILITIES][SEQ] Allow call of WaitEvent in the context of PreIdle/PostIdle
+

Known Limitations

+

Outstanding bugs list : None

+

Requirements not met or planned in a forthcoming release : None

+

Development Toolchains and Compilers

+
    +
  • IAR Embedded Workbench for ARM (EWARM) toolchain V8.20.2
    • +
  • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.25
    • +
  • System Workbench STM32 (SW4STM32) toolchain V2.7.2
    • +
+

Backward compatibility

+

No compatibility break with previous version

+
+
+
+ +
+

Main Changes

+

release V1.3.0

+

Contents

+ + + + + + + + + + + + + + + + + + + + + +
Fixed bugs list
+
Headline
doxygen tag insertion
doxygen documentation html\index.html
MISRA 2012 test
Ticket 72443 - Scheduler: CurrentTaskIdx it is not correctly handled.
+

known limitations

+

Development Toolchains and Compilers

+
    +
  • IAR Embedded Workbench for ARM (EWARM) toolchain V8.20.2
    • +
  • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.25
    • +
  • System Workbench STM32 (SW4STM32) toolchain V2.7.2
    • +
+

Supported Devices and boards

+

backward compatibility

+

Dependencies

+
+
+
+ +
+

Main Changes

+

release V1.2.1

+

Contents

+ + + + + + + + + + + + +
Fixed bugs list
+
Headline
Ticket 72443 - Scheduler: CurrentTaskIdx it is not correctly handled.
+

known limitations

+

Development Toolchains and Compilers

+
    +
  • IAR Embedded Workbench for ARM (EWARM) toolchain V8.20.2
    • +
  • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.25
    • +
  • System Workbench STM32 (SW4STM32) toolchain V2.7.2
    • +
+

Supported Devices and boards

+

backward compatibility

+

Dependencies

+
+
+
+ +
+

Main Changes

+

release V1.2.0

+

Contents

+ + + + + + + + + + + + +
Fixed bugs list
+
Headline
Fixed to avoid infinite loop when a task is waiting for an event.
+

known limitations

+

Development Toolchains and Compilers

+
    +
  • IAR Embedded Workbench for ARM (EWARM) toolchain V8.20.2
    • +
  • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.25
    • +
  • System Workbench STM32 (SW4STM32) toolchain V2.7.2
    • +
+

Supported Devices and boards

+

backward compatibility

+

Dependencies

+
+
+
+ +
+

Main Changes

+

release V1.1.0

+

Contents

+ + + + + + + + + + + + + + + +
Fixed bugs list
+
Headline
License correction.
change __weak symbol by __WEAK to be compliant with AC6.
+

known limitations

+

Development Toolchains and Compilers

+
    +
  • IAR Embedded Workbench for ARM (EWARM) toolchain V8.20.2
    • +
  • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.25
    • +
  • System Workbench STM32 (SW4STM32) toolchain V2.7.2
    • +
+

Supported Devices and boards

+

backward compatibility

+

Dependencies

+
+
+
+ +
+

Main Changes

+

first release

+

Contents

+ + + + + + + + + + + + +
Fixed bugs list
+
Headline
first version.
+

known limitations

+

Development Toolchains and Compilers

+
    +
  • IAR Embedded Workbench for ARM (EWARM) toolchain V8.20.2
    • +
  • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.25
    • +
  • System Workbench STM32 (SW4STM32) toolchain V2.7.2
    • +
+

Supported Devices and boards

+

backward compatibility

+

Dependencies

+
+
+
+
+
+

For complete documentation on STM32,visit: [www.st.com/stm32]

+This release note uses up to date web standards and, for this reason, should not be opened with Internet Explorer but preferably with popular browsers such as Google Chrome, Mozilla Firefox, Opera or Microsoft Edge. +
+ + diff --git a/Utilities/sequencer/_htmresc/mini-st.css b/Utilities/sequencer/_htmresc/mini-st.css new file mode 100644 index 0000000..eb41d56 --- /dev/null +++ b/Utilities/sequencer/_htmresc/mini-st.css @@ -0,0 +1,1700 @@ +@charset "UTF-8"; +/* + Flavor name: Default (mini-default) + Author: Angelos Chalaris (chalarangelo@gmail.com) + Maintainers: Angelos Chalaris + mini.css version: v3.0.0-alpha.3 +*/ +/* + Browsers resets and base typography. +*/ +/* Core module CSS variable definitions */ +:root { + --fore-color: #111; + --secondary-fore-color: #444; + --back-color: #f8f8f8; + --secondary-back-color: #f0f0f0; + --blockquote-color: #f57c00; + --pre-color: #1565c0; + --border-color: #aaa; + --secondary-border-color: #ddd; + --heading-ratio: 1.19; + --universal-margin: 0.5rem; + --universal-padding: 0.125rem; + --universal-border-radius: 0.125rem; + --a-link-color: #0277bd; + --a-visited-color: #01579b; } + +html { + font-size: 14px; } + +a, b, del, em, i, ins, q, span, strong, u { + font-size: 1em; } + +html, * { + font-family: -apple-system, BlinkMacSystemFont, "Segoe UI", Roboto, Ubuntu, "Helvetica Neue", Helvetica, sans-serif; + line-height: 1.4; + -webkit-text-size-adjust: 100%; } + +* { + font-size: 1rem; } + +body { + margin: 0; + color: var(--fore-color); + background: var(--back-color); } + +details { + display: block; } + +summary { + display: list-item; } + +abbr[title] { + border-bottom: none; + text-decoration: underline dotted; } + +input { + overflow: visible; } + +img { + max-width: 100%; + height: auto; } + +h1, h2, h3, h4, h5, h6 { + line-height: 1.2; + margin: calc(1.5 * var(--universal-margin)) var(--universal-margin); + font-weight: 500; } + h1 small, h2 small, h3 small, h4 small, h5 small, h6 small { + color: var(--secondary-fore-color); + display: block; + margin-top: -0.25rem; } + +h1 { + font-size: calc(1rem * var(--heading-ratio) * var(--heading-ratio) * var(--heading-ratio)); } + +h2 { + font-size: calc(1rem * var(--heading-ratio) * var(--heading-ratio); ); + background: var(--mark-back-color); + font-weight: 600; + padding: 0.1em 0.5em 0.2em 0.5em; + color: var(--mark-fore-color); } + +h3 { + font-size: calc(1rem * var(--heading-ratio)); + padding-left: calc(2 * var(--universal-margin)); + /* background: var(--border-color); */ + } + +h4 { + font-size: 1rem;); + padding-left: calc(4 * var(--universal-margin)); } + +h5 { + font-size: 1rem; } + +h6 { + font-size: calc(1rem / var(--heading-ratio)); } + +p { + margin: var(--universal-margin); } + +ol, ul { + margin: var(--universal-margin); + padding-left: calc(6 * var(--universal-margin)); } + +b, strong { + font-weight: 700; } + +hr { + box-sizing: content-box; + border: 0; + line-height: 1.25em; + margin: var(--universal-margin); + height: 0.0625rem; + background: linear-gradient(to right, transparent, var(--border-color) 20%, var(--border-color) 80%, transparent); } + +blockquote { + display: block; + position: relative; + font-style: italic; + color: var(--secondary-fore-color); + margin: var(--universal-margin); + padding: calc(3 * var(--universal-padding)); + border: 0.0625rem solid var(--secondary-border-color); + border-left: 0.375rem solid var(--blockquote-color); + border-radius: 0 var(--universal-border-radius) var(--universal-border-radius) 0; } + blockquote:before { + position: absolute; + top: calc(0rem - var(--universal-padding)); + left: 0; + font-family: sans-serif; + font-size: 3rem; + font-weight: 700; + content: "\201c"; + color: var(--blockquote-color); } + blockquote[cite]:after { + font-style: normal; + font-size: 0.75em; + font-weight: 700; + content: "\a— " attr(cite); + white-space: pre; } + +code, kbd, pre, samp { + font-family: Menlo, Consolas, monospace; + font-size: 0.85em; } + +code { + background: var(--secondary-back-color); + border-radius: var(--universal-border-radius); + padding: calc(var(--universal-padding) / 4) calc(var(--universal-padding) / 2); } + +kbd { + background: var(--fore-color); + color: var(--back-color); + border-radius: var(--universal-border-radius); + padding: calc(var(--universal-padding) / 4) calc(var(--universal-padding) / 2); } + +pre { + overflow: auto; + background: var(--secondary-back-color); + padding: calc(1.5 * var(--universal-padding)); + margin: var(--universal-margin); + border: 0.0625rem solid var(--secondary-border-color); + border-left: 0.25rem solid var(--pre-color); + border-radius: 0 var(--universal-border-radius) var(--universal-border-radius) 0; } + +sup, sub, code, kbd { + line-height: 0; + position: relative; + vertical-align: baseline; } + +small, sup, sub, figcaption { + font-size: 0.75em; } + +sup { + top: -0.5em; } + +sub { + bottom: -0.25em; } + +figure { + margin: var(--universal-margin); } + +figcaption { + color: var(--secondary-fore-color); } + +a { + text-decoration: none; } + a:link { + color: var(--a-link-color); } + a:visited { + color: var(--a-visited-color); } + a:hover, a:focus { + text-decoration: underline; } + +/* + Definitions for the grid system, cards and containers. +*/ +.container { + margin: 0 auto; + padding: 0 calc(1.5 * var(--universal-padding)); } + +.row { + box-sizing: border-box; + display: flex; + flex: 0 1 auto; + flex-flow: row wrap; } + +.col-sm, +[class^='col-sm-'], +[class^='col-sm-offset-'], +.row[class*='cols-sm-'] > * { + box-sizing: border-box; + flex: 0 0 auto; + padding: 0 calc(var(--universal-padding) / 2); } + +.col-sm, +.row.cols-sm > * { + max-width: 100%; + flex-grow: 1; + flex-basis: 0; } + +.col-sm-1, +.row.cols-sm-1 > * { + max-width: 8.3333333333%; + flex-basis: 8.3333333333%; } + +.col-sm-offset-0 { + margin-left: 0; } + +.col-sm-2, +.row.cols-sm-2 > * { + max-width: 16.6666666667%; + flex-basis: 16.6666666667%; } + +.col-sm-offset-1 { + margin-left: 8.3333333333%; } + +.col-sm-3, +.row.cols-sm-3 > * { + max-width: 25%; + flex-basis: 25%; } + +.col-sm-offset-2 { + margin-left: 16.6666666667%; } + +.col-sm-4, +.row.cols-sm-4 > * { + max-width: 33.3333333333%; + flex-basis: 33.3333333333%; } + +.col-sm-offset-3 { + margin-left: 25%; } + +.col-sm-5, +.row.cols-sm-5 > * { + max-width: 41.6666666667%; + flex-basis: 41.6666666667%; } + +.col-sm-offset-4 { + margin-left: 33.3333333333%; } + +.col-sm-6, +.row.cols-sm-6 > * { + max-width: 50%; + flex-basis: 50%; } + +.col-sm-offset-5 { + margin-left: 41.6666666667%; } + +.col-sm-7, +.row.cols-sm-7 > * { + max-width: 58.3333333333%; + flex-basis: 58.3333333333%; } + +.col-sm-offset-6 { + margin-left: 50%; } + +.col-sm-8, +.row.cols-sm-8 > * { + max-width: 66.6666666667%; + flex-basis: 66.6666666667%; } + +.col-sm-offset-7 { + margin-left: 58.3333333333%; } + +.col-sm-9, +.row.cols-sm-9 > * { + max-width: 75%; + flex-basis: 75%; } + +.col-sm-offset-8 { + margin-left: 66.6666666667%; } + +.col-sm-10, +.row.cols-sm-10 > * { + max-width: 83.3333333333%; + flex-basis: 83.3333333333%; } + +.col-sm-offset-9 { + margin-left: 75%; } + +.col-sm-11, +.row.cols-sm-11 > * { + max-width: 91.6666666667%; + flex-basis: 91.6666666667%; } + +.col-sm-offset-10 { + margin-left: 83.3333333333%; } + +.col-sm-12, +.row.cols-sm-12 > * { + max-width: 100%; + flex-basis: 100%; } + +.col-sm-offset-11 { + margin-left: 91.6666666667%; } + +.col-sm-normal { + order: initial; } + +.col-sm-first { + order: -999; } + +.col-sm-last { + order: 999; } + +@media screen and (min-width: 500px) { + .col-md, + [class^='col-md-'], + [class^='col-md-offset-'], + .row[class*='cols-md-'] > * { + box-sizing: border-box; + flex: 0 0 auto; + padding: 0 calc(var(--universal-padding) / 2); } + + .col-md, + .row.cols-md > * { + max-width: 100%; + flex-grow: 1; + flex-basis: 0; } + + .col-md-1, + .row.cols-md-1 > * { + max-width: 8.3333333333%; + flex-basis: 8.3333333333%; } + + .col-md-offset-0 { + margin-left: 0; } + + .col-md-2, + .row.cols-md-2 > * { + max-width: 16.6666666667%; + flex-basis: 16.6666666667%; } + + .col-md-offset-1 { + margin-left: 8.3333333333%; } + + .col-md-3, + .row.cols-md-3 > * { + max-width: 25%; + flex-basis: 25%; } + + .col-md-offset-2 { + margin-left: 16.6666666667%; } + + .col-md-4, + .row.cols-md-4 > * { + max-width: 33.3333333333%; + flex-basis: 33.3333333333%; } + + .col-md-offset-3 { + margin-left: 25%; } + + .col-md-5, + .row.cols-md-5 > * { + max-width: 41.6666666667%; + flex-basis: 41.6666666667%; } + + .col-md-offset-4 { + margin-left: 33.3333333333%; } + + .col-md-6, + .row.cols-md-6 > * { + max-width: 50%; + flex-basis: 50%; } + + .col-md-offset-5 { + margin-left: 41.6666666667%; } + + .col-md-7, + .row.cols-md-7 > * { + max-width: 58.3333333333%; + flex-basis: 58.3333333333%; } + + .col-md-offset-6 { + margin-left: 50%; } + + .col-md-8, + .row.cols-md-8 > * { + max-width: 66.6666666667%; + flex-basis: 66.6666666667%; } + + .col-md-offset-7 { + margin-left: 58.3333333333%; } + + .col-md-9, + .row.cols-md-9 > * { + max-width: 75%; + flex-basis: 75%; } + + .col-md-offset-8 { + margin-left: 66.6666666667%; } + + .col-md-10, + .row.cols-md-10 > * { + max-width: 83.3333333333%; + flex-basis: 83.3333333333%; } + + .col-md-offset-9 { + margin-left: 75%; } + + .col-md-11, + .row.cols-md-11 > * { + max-width: 91.6666666667%; + flex-basis: 91.6666666667%; } + + .col-md-offset-10 { + margin-left: 83.3333333333%; } + + .col-md-12, + .row.cols-md-12 > * { + max-width: 100%; + flex-basis: 100%; } + + .col-md-offset-11 { + margin-left: 91.6666666667%; } + + .col-md-normal { + order: initial; } + + .col-md-first { + order: -999; } + + .col-md-last { + order: 999; } } +@media screen and (min-width: 1280px) { + .col-lg, + [class^='col-lg-'], + [class^='col-lg-offset-'], + .row[class*='cols-lg-'] > * { + box-sizing: border-box; + flex: 0 0 auto; + padding: 0 calc(var(--universal-padding) / 2); } + + .col-lg, + .row.cols-lg > * { + max-width: 100%; + flex-grow: 1; + flex-basis: 0; } + + .col-lg-1, + .row.cols-lg-1 > * { + max-width: 8.3333333333%; + flex-basis: 8.3333333333%; } + + .col-lg-offset-0 { + margin-left: 0; } + + .col-lg-2, + .row.cols-lg-2 > * { + max-width: 16.6666666667%; + flex-basis: 16.6666666667%; } + + .col-lg-offset-1 { + margin-left: 8.3333333333%; } + + .col-lg-3, + .row.cols-lg-3 > * { + max-width: 25%; + flex-basis: 25%; } + + .col-lg-offset-2 { + margin-left: 16.6666666667%; } + + .col-lg-4, + .row.cols-lg-4 > * { + max-width: 33.3333333333%; + flex-basis: 33.3333333333%; } + + .col-lg-offset-3 { + margin-left: 25%; } + + .col-lg-5, + .row.cols-lg-5 > * { + max-width: 41.6666666667%; + flex-basis: 41.6666666667%; } + + .col-lg-offset-4 { + margin-left: 33.3333333333%; } + + .col-lg-6, + .row.cols-lg-6 > * { + max-width: 50%; + flex-basis: 50%; } + + .col-lg-offset-5 { + margin-left: 41.6666666667%; } + + .col-lg-7, + .row.cols-lg-7 > * { + max-width: 58.3333333333%; + flex-basis: 58.3333333333%; } + + .col-lg-offset-6 { + margin-left: 50%; } + + .col-lg-8, + .row.cols-lg-8 > * { + max-width: 66.6666666667%; + flex-basis: 66.6666666667%; } + + .col-lg-offset-7 { + margin-left: 58.3333333333%; } + + .col-lg-9, + .row.cols-lg-9 > * { + max-width: 75%; + flex-basis: 75%; } + + .col-lg-offset-8 { + margin-left: 66.6666666667%; } + + .col-lg-10, + .row.cols-lg-10 > * { + max-width: 83.3333333333%; + flex-basis: 83.3333333333%; } + + .col-lg-offset-9 { + margin-left: 75%; } + + .col-lg-11, + .row.cols-lg-11 > * { + max-width: 91.6666666667%; + flex-basis: 91.6666666667%; } + + .col-lg-offset-10 { + margin-left: 83.3333333333%; } + + .col-lg-12, + .row.cols-lg-12 > * { + max-width: 100%; + flex-basis: 100%; } + + .col-lg-offset-11 { + margin-left: 91.6666666667%; } + + .col-lg-normal { + order: initial; } + + .col-lg-first { + order: -999; } + + .col-lg-last { + order: 999; } } +/* Card component CSS variable definitions */ +:root { + --card-back-color: #f8f8f8; + --card-fore-color: #111; + --card-border-color: #ddd; } + +.card { + display: flex; + flex-direction: column; + justify-content: space-between; + align-self: center; + position: relative; + width: 100%; + background: var(--card-back-color); + color: var(--card-fore-color); + border: 0.0625rem solid var(--card-border-color); + border-radius: var(--universal-border-radius); + margin: var(--universal-margin); + overflow: hidden; } + @media screen and (min-width: 320px) { + .card { + max-width: 320px; } } + .card > .sectione { + background: var(--card-back-color); + color: var(--card-fore-color); + box-sizing: border-box; + margin: 0; + border: 0; + border-radius: 0; + border-bottom: 0.0625rem solid var(--card-border-color); + padding: var(--universal-padding); + width: 100%; } + .card > .sectione.media { + height: 200px; + padding: 0; + -o-object-fit: cover; + object-fit: cover; } + .card > .sectione:last-child { + border-bottom: 0; } + +/* + Custom elements for card elements. +*/ +@media screen and (min-width: 240px) { + .card.small { + max-width: 240px; } } +@media screen and (min-width: 480px) { + .card.large { + max-width: 480px; } } +.card.fluid { + max-width: 100%; + width: auto; } + +.card.warning { +/* --card-back-color: #ffca28; */ + --card-back-color: #e5b8b7; + --card-border-color: #e8b825; } + +.card.error { + --card-back-color: #b71c1c; + --card-fore-color: #f8f8f8; + --card-border-color: #a71a1a; } + +.card > .sectione.dark { + --card-back-color: #e0e0e0; } + +.card > .sectione.double-padded { + padding: calc(1.5 * var(--universal-padding)); } + +/* + Definitions for forms and input elements. +*/ +/* Input_control module CSS variable definitions */ +:root { + --form-back-color: #f0f0f0; + --form-fore-color: #111; + --form-border-color: #ddd; + --input-back-color: #f8f8f8; + --input-fore-color: #111; + --input-border-color: #ddd; + --input-focus-color: #0288d1; + --input-invalid-color: #d32f2f; + --button-back-color: #e2e2e2; + --button-hover-back-color: #dcdcdc; + --button-fore-color: #212121; + --button-border-color: transparent; + --button-hover-border-color: transparent; + --button-group-border-color: rgba(124, 124, 124, 0.54); } + +form { + background: var(--form-back-color); + color: var(--form-fore-color); + border: 0.0625rem solid var(--form-border-color); + border-radius: var(--universal-border-radius); + margin: var(--universal-margin); + padding: calc(2 * var(--universal-padding)) var(--universal-padding); } + +fieldset { + border: 0.0625rem solid var(--form-border-color); + border-radius: var(--universal-border-radius); + margin: calc(var(--universal-margin) / 4); + padding: var(--universal-padding); } + +legend { + box-sizing: border-box; + display: table; + max-width: 100%; + white-space: normal; + font-weight: 700; + padding: calc(var(--universal-padding) / 2); } + +label { + padding: calc(var(--universal-padding) / 2) var(--universal-padding); } + +.input-group { + display: inline-block; } + .input-group.fluid { + display: flex; + align-items: center; + justify-content: center; } + .input-group.fluid > input { + max-width: 100%; + flex-grow: 1; + flex-basis: 0px; } + @media screen and (max-width: 499px) { + .input-group.fluid { + align-items: stretch; + flex-direction: column; } } + .input-group.vertical { + display: flex; + align-items: stretch; + flex-direction: column; } + .input-group.vertical > input { + max-width: 100%; + flex-grow: 1; + flex-basis: 0px; } + +[type="number"]::-webkit-inner-spin-button, [type="number"]::-webkit-outer-spin-button { + height: auto; } + +[type="search"] { + -webkit-appearance: textfield; + outline-offset: -2px; } + +[type="search"]::-webkit-search-cancel-button, +[type="search"]::-webkit-search-decoration { + -webkit-appearance: none; } + +input:not([type]), [type="text"], [type="email"], [type="number"], [type="search"], +[type="password"], [type="url"], [type="tel"], [type="checkbox"], [type="radio"], textarea, select { + box-sizing: border-box; + background: var(--input-back-color); + color: var(--input-fore-color); + border: 0.0625rem solid var(--input-border-color); + border-radius: var(--universal-border-radius); + margin: calc(var(--universal-margin) / 2); + padding: var(--universal-padding) calc(1.5 * var(--universal-padding)); } + +input:not([type="button"]):not([type="submit"]):not([type="reset"]):hover, input:not([type="button"]):not([type="submit"]):not([type="reset"]):focus, textarea:hover, textarea:focus, select:hover, select:focus { + border-color: var(--input-focus-color); + box-shadow: none; } +input:not([type="button"]):not([type="submit"]):not([type="reset"]):invalid, input:not([type="button"]):not([type="submit"]):not([type="reset"]):focus:invalid, textarea:invalid, textarea:focus:invalid, select:invalid, select:focus:invalid { + border-color: var(--input-invalid-color); + box-shadow: none; } +input:not([type="button"]):not([type="submit"]):not([type="reset"])[readonly], textarea[readonly], select[readonly] { + background: var(--secondary-back-color); } + +select { + max-width: 100%; } + +option { + overflow: hidden; + text-overflow: ellipsis; } + +[type="checkbox"], [type="radio"] { + -webkit-appearance: none; + -moz-appearance: none; + appearance: none; + position: relative; + height: calc(1rem + var(--universal-padding) / 2); + width: calc(1rem + var(--universal-padding) / 2); + vertical-align: text-bottom; + padding: 0; + flex-basis: calc(1rem + var(--universal-padding) / 2) !important; + flex-grow: 0 !important; } + [type="checkbox"]:checked:before, [type="radio"]:checked:before { + position: absolute; } + +[type="checkbox"]:checked:before { + content: '\2713'; + font-family: sans-serif; + font-size: calc(1rem + var(--universal-padding) / 2); + top: calc(0rem - var(--universal-padding)); + left: calc(var(--universal-padding) / 4); } + +[type="radio"] { + border-radius: 100%; } + [type="radio"]:checked:before { + border-radius: 100%; + content: ''; + top: calc(0.0625rem + var(--universal-padding) / 2); + left: calc(0.0625rem + var(--universal-padding) / 2); + background: var(--input-fore-color); + width: 0.5rem; + height: 0.5rem; } + +:placeholder-shown { + color: var(--input-fore-color); } + +::-ms-placeholder { + color: var(--input-fore-color); + opacity: 0.54; } + +button::-moz-focus-inner, [type="button"]::-moz-focus-inner, [type="reset"]::-moz-focus-inner, [type="submit"]::-moz-focus-inner { + border-style: none; + padding: 0; } + +button, html [type="button"], [type="reset"], [type="submit"] { + -webkit-appearance: button; } + +button { + overflow: visible; + text-transform: none; } + +button, [type="button"], [type="submit"], [type="reset"], +a.button, label.button, .button, +a[role="button"], label[role="button"], [role="button"] { + display: inline-block; + background: var(--button-back-color); + color: var(--button-fore-color); + border: 0.0625rem solid var(--button-border-color); + border-radius: var(--universal-border-radius); + padding: var(--universal-padding) calc(1.5 * var(--universal-padding)); + margin: var(--universal-margin); + text-decoration: none; + cursor: pointer; + transition: background 0.3s; } + button:hover, button:focus, [type="button"]:hover, [type="button"]:focus, [type="submit"]:hover, [type="submit"]:focus, [type="reset"]:hover, [type="reset"]:focus, + a.button:hover, + a.button:focus, label.button:hover, label.button:focus, .button:hover, .button:focus, + a[role="button"]:hover, + a[role="button"]:focus, label[role="button"]:hover, label[role="button"]:focus, [role="button"]:hover, [role="button"]:focus { + background: var(--button-hover-back-color); + border-color: var(--button-hover-border-color); } + +input:disabled, input[disabled], textarea:disabled, textarea[disabled], select:disabled, select[disabled], button:disabled, button[disabled], .button:disabled, .button[disabled], [role="button"]:disabled, [role="button"][disabled] { + cursor: not-allowed; + opacity: 0.75; } + +.button-group { + display: flex; + border: 0.0625rem solid var(--button-group-border-color); + border-radius: var(--universal-border-radius); + margin: var(--universal-margin); } + .button-group > button, .button-group [type="button"], .button-group > [type="submit"], .button-group > [type="reset"], .button-group > .button, .button-group > [role="button"] { + margin: 0; + max-width: 100%; + flex: 1 1 auto; + text-align: center; + border: 0; + border-radius: 0; + box-shadow: none; } + .button-group > :not(:first-child) { + border-left: 0.0625rem solid var(--button-group-border-color); } + @media screen and (max-width: 499px) { + .button-group { + flex-direction: column; } + .button-group > :not(:first-child) { + border: 0; + border-top: 0.0625rem solid var(--button-group-border-color); } } + +/* + Custom elements for forms and input elements. +*/ +button.primary, [type="button"].primary, [type="submit"].primary, [type="reset"].primary, .button.primary, [role="button"].primary { + --button-back-color: #1976d2; + --button-fore-color: #f8f8f8; } + button.primary:hover, button.primary:focus, [type="button"].primary:hover, [type="button"].primary:focus, [type="submit"].primary:hover, [type="submit"].primary:focus, [type="reset"].primary:hover, [type="reset"].primary:focus, .button.primary:hover, .button.primary:focus, [role="button"].primary:hover, [role="button"].primary:focus { + --button-hover-back-color: #1565c0; } + +button.secondary, [type="button"].secondary, [type="submit"].secondary, [type="reset"].secondary, .button.secondary, [role="button"].secondary { + --button-back-color: #d32f2f; + --button-fore-color: #f8f8f8; } + button.secondary:hover, button.secondary:focus, [type="button"].secondary:hover, [type="button"].secondary:focus, [type="submit"].secondary:hover, [type="submit"].secondary:focus, [type="reset"].secondary:hover, [type="reset"].secondary:focus, .button.secondary:hover, .button.secondary:focus, [role="button"].secondary:hover, [role="button"].secondary:focus { + --button-hover-back-color: #c62828; } + +button.tertiary, [type="button"].tertiary, [type="submit"].tertiary, [type="reset"].tertiary, .button.tertiary, [role="button"].tertiary { + --button-back-color: #308732; + --button-fore-color: #f8f8f8; } + button.tertiary:hover, button.tertiary:focus, [type="button"].tertiary:hover, [type="button"].tertiary:focus, [type="submit"].tertiary:hover, [type="submit"].tertiary:focus, [type="reset"].tertiary:hover, [type="reset"].tertiary:focus, .button.tertiary:hover, .button.tertiary:focus, [role="button"].tertiary:hover, [role="button"].tertiary:focus { + --button-hover-back-color: #277529; } + +button.inverse, [type="button"].inverse, [type="submit"].inverse, [type="reset"].inverse, .button.inverse, [role="button"].inverse { + --button-back-color: #212121; + --button-fore-color: #f8f8f8; } + button.inverse:hover, button.inverse:focus, [type="button"].inverse:hover, [type="button"].inverse:focus, [type="submit"].inverse:hover, [type="submit"].inverse:focus, [type="reset"].inverse:hover, [type="reset"].inverse:focus, .button.inverse:hover, .button.inverse:focus, [role="button"].inverse:hover, [role="button"].inverse:focus { + --button-hover-back-color: #111; } + +button.small, [type="button"].small, [type="submit"].small, [type="reset"].small, .button.small, [role="button"].small { + padding: calc(0.5 * var(--universal-padding)) calc(0.75 * var(--universal-padding)); + margin: var(--universal-margin); } + +button.large, [type="button"].large, [type="submit"].large, [type="reset"].large, .button.large, [role="button"].large { + padding: calc(1.5 * var(--universal-padding)) calc(2 * var(--universal-padding)); + margin: var(--universal-margin); } + +/* + Definitions for navigation elements. +*/ +/* Navigation module CSS variable definitions */ +:root { + --header-back-color: #f8f8f8; + --header-hover-back-color: #f0f0f0; + --header-fore-color: #444; + --header-border-color: #ddd; + --nav-back-color: #f8f8f8; + --nav-hover-back-color: #f0f0f0; + --nav-fore-color: #444; + --nav-border-color: #ddd; + --nav-link-color: #0277bd; + --footer-fore-color: #444; + --footer-back-color: #f8f8f8; + --footer-border-color: #ddd; + --footer-link-color: #0277bd; + --drawer-back-color: #f8f8f8; + --drawer-hover-back-color: #f0f0f0; + --drawer-border-color: #ddd; + --drawer-close-color: #444; } + +header { + height: 3.1875rem; + background: var(--header-back-color); + color: var(--header-fore-color); + border-bottom: 0.0625rem solid var(--header-border-color); + padding: calc(var(--universal-padding) / 4) 0; + white-space: nowrap; + overflow-x: auto; + overflow-y: hidden; } + header.row { + box-sizing: content-box; } + header .logo { + color: var(--header-fore-color); + font-size: 1.75rem; + padding: var(--universal-padding) calc(2 * var(--universal-padding)); + text-decoration: none; } + header button, header [type="button"], header .button, header [role="button"] { + box-sizing: border-box; + position: relative; + top: calc(0rem - var(--universal-padding) / 4); + height: calc(3.1875rem + var(--universal-padding) / 2); + background: var(--header-back-color); + line-height: calc(3.1875rem - var(--universal-padding) * 1.5); + text-align: center; + color: var(--header-fore-color); + border: 0; + border-radius: 0; + margin: 0; + text-transform: uppercase; } + header button:hover, header button:focus, header [type="button"]:hover, header [type="button"]:focus, header .button:hover, header .button:focus, header [role="button"]:hover, header [role="button"]:focus { + background: var(--header-hover-back-color); } + +nav { + background: var(--nav-back-color); + color: var(--nav-fore-color); + border: 0.0625rem solid var(--nav-border-color); + border-radius: var(--universal-border-radius); + margin: var(--universal-margin); } + nav * { + padding: var(--universal-padding) calc(1.5 * var(--universal-padding)); } + nav a, nav a:visited { + display: block; + color: var(--nav-link-color); + border-radius: var(--universal-border-radius); + transition: background 0.3s; } + nav a:hover, nav a:focus, nav a:visited:hover, nav a:visited:focus { + text-decoration: none; + background: var(--nav-hover-back-color); } + nav .sublink-1 { + position: relative; + margin-left: calc(2 * var(--universal-padding)); } + nav .sublink-1:before { + position: absolute; + left: calc(var(--universal-padding) - 1 * var(--universal-padding)); + top: -0.0625rem; + content: ''; + height: 100%; + border: 0.0625rem solid var(--nav-border-color); + border-left: 0; } + nav .sublink-2 { + position: relative; + margin-left: calc(4 * var(--universal-padding)); } + nav .sublink-2:before { + position: absolute; + left: calc(var(--universal-padding) - 3 * var(--universal-padding)); + top: -0.0625rem; + content: ''; + height: 100%; + border: 0.0625rem solid var(--nav-border-color); + border-left: 0; } + +footer { + background: var(--footer-back-color); + color: var(--footer-fore-color); + border-top: 0.0625rem solid var(--footer-border-color); + padding: calc(2 * var(--universal-padding)) var(--universal-padding); + font-size: 0.875rem; } + footer a, footer a:visited { + color: var(--footer-link-color); } + +header.sticky { + position: -webkit-sticky; + position: sticky; + z-index: 1101; + top: 0; } + +footer.sticky { + position: -webkit-sticky; + position: sticky; + z-index: 1101; + bottom: 0; } + +.drawer-toggle:before { + display: inline-block; + position: relative; + vertical-align: bottom; + content: '\00a0\2261\00a0'; + font-family: sans-serif; + font-size: 1.5em; } +@media screen and (min-width: 500px) { + .drawer-toggle:not(.persistent) { + display: none; } } + +[type="checkbox"].drawer { + height: 1px; + width: 1px; + margin: -1px; + overflow: hidden; + position: absolute; + clip: rect(0 0 0 0); + -webkit-clip-path: inset(100%); + clip-path: inset(100%); } + [type="checkbox"].drawer + * { + display: block; + box-sizing: border-box; + position: fixed; + top: 0; + width: 320px; + height: 100vh; + overflow-y: auto; + background: var(--drawer-back-color); + border: 0.0625rem solid var(--drawer-border-color); + border-radius: 0; + margin: 0; + z-index: 1110; + right: -320px; + transition: right 0.3s; } + [type="checkbox"].drawer + * .drawer-close { + position: absolute; + top: var(--universal-margin); + right: var(--universal-margin); + z-index: 1111; + width: 2rem; + height: 2rem; + border-radius: var(--universal-border-radius); + padding: var(--universal-padding); + margin: 0; + cursor: pointer; + transition: background 0.3s; } + [type="checkbox"].drawer + * .drawer-close:before { + display: block; + content: '\00D7'; + color: var(--drawer-close-color); + position: relative; + font-family: sans-serif; + font-size: 2rem; + line-height: 1; + text-align: center; } + [type="checkbox"].drawer + * .drawer-close:hover, [type="checkbox"].drawer + * .drawer-close:focus { + background: var(--drawer-hover-back-color); } + @media screen and (max-width: 320px) { + [type="checkbox"].drawer + * { + width: 100%; } } + [type="checkbox"].drawer:checked + * { + right: 0; } + @media screen and (min-width: 500px) { + [type="checkbox"].drawer:not(.persistent) + * { + position: static; + height: 100%; + z-index: 1100; } + [type="checkbox"].drawer:not(.persistent) + * .drawer-close { + display: none; } } + +/* + Definitions for the responsive table component. +*/ +/* Table module CSS variable definitions. */ +:root { + --table-border-color: #aaa; + --table-border-separator-color: #666; + --table-head-back-color: #e6e6e6; + --table-head-fore-color: #111; + --table-body-back-color: #f8f8f8; + --table-body-fore-color: #111; + --table-body-alt-back-color: #eee; } + +table { + border-collapse: separate; + border-spacing: 0; + : margin: calc(1.5 * var(--universal-margin)) var(--universal-margin); + display: flex; + flex: 0 1 auto; + flex-flow: row wrap; + padding: var(--universal-padding); + padding-top: 0; + margin: calc(1.5 * var(--universal-margin)) var(--universal-margin); } + table caption { + font-size: 1.25 * rem; + margin: calc(2 * var(--universal-margin)) 0; + max-width: 100%; + flex: 0 0 100%; + text-align: left;} + table thead, table tbody { + display: flex; + flex-flow: row wrap; + border: 0.0625rem solid var(--table-border-color); } + table thead { + z-index: 999; + border-radius: var(--universal-border-radius) var(--universal-border-radius) 0 0; + border-bottom: 0.0625rem solid var(--table-border-separator-color); } + table tbody { + border-top: 0; + margin-top: calc(0 - var(--universal-margin)); + border-radius: 0 0 var(--universal-border-radius) var(--universal-border-radius); } + table tr { + display: flex; + padding: 0; } + table th, table td { + padding: calc(0.5 * var(--universal-padding)); + font-size: 0.9rem; } + table th { + text-align: left; + background: var(--table-head-back-color); + color: var(--table-head-fore-color); } + table td { + background: var(--table-body-back-color); + color: var(--table-body-fore-color); + border-top: 0.0625rem solid var(--table-border-color); } + +table:not(.horizontal) { + overflow: auto; + max-height: 850px; } + table:not(.horizontal) thead, table:not(.horizontal) tbody { + max-width: 100%; + flex: 0 0 100%; } + table:not(.horizontal) tr { + flex-flow: row wrap; + flex: 0 0 100%; } + table:not(.horizontal) th, table:not(.horizontal) td { + flex: 1 0 0%; + overflow: hidden; + text-overflow: ellipsis; } + table:not(.horizontal) thead { + position: sticky; + top: 0; } + table:not(.horizontal) tbody tr:first-child td { + border-top: 0; } + +table.horizontal { + border: 0; } + table.horizontal thead, table.horizontal tbody { + border: 0; + flex-flow: row nowrap; } + table.horizontal tbody { + overflow: auto; + justify-content: space-between; + flex: 1 0 0; + margin-left: calc( 4 * var(--universal-margin)); + padding-bottom: calc(var(--universal-padding) / 4); } + table.horizontal tr { + flex-direction: column; + flex: 1 0 auto; } + table.horizontal th, table.horizontal td { + width: 100%; + border: 0; + border-bottom: 0.0625rem solid var(--table-border-color); } + table.horizontal th:not(:first-child), table.horizontal td:not(:first-child) { + border-top: 0; } + table.horizontal th { + text-align: right; + border-left: 0.0625rem solid var(--table-border-color); + border-right: 0.0625rem solid var(--table-border-separator-color); } + table.horizontal thead tr:first-child { + padding-left: 0; } + table.horizontal th:first-child, table.horizontal td:first-child { + border-top: 0.0625rem solid var(--table-border-color); } + table.horizontal tbody tr:last-child td { + border-right: 0.0625rem solid var(--table-border-color); } + table.horizontal tbody tr:last-child td:first-child { + border-top-right-radius: 0.25rem; } + table.horizontal tbody tr:last-child td:last-child { + border-bottom-right-radius: 0.25rem; } + table.horizontal thead tr:first-child th:first-child { + border-top-left-radius: 0.25rem; } + table.horizontal thead tr:first-child th:last-child { + border-bottom-left-radius: 0.25rem; } + +@media screen and (max-width: 499px) { + table, table.horizontal { + border-collapse: collapse; + border: 0; + width: 100%; + display: table; } + table thead, table th, table.horizontal thead, table.horizontal th { + border: 0; + height: 1px; + width: 1px; + margin: -1px; + overflow: hidden; + padding: 0; + position: absolute; + clip: rect(0 0 0 0); + -webkit-clip-path: inset(100%); + clip-path: inset(100%); } + table tbody, table.horizontal tbody { + border: 0; + display: table-row-group; } + table tr, table.horizontal tr { + display: block; + border: 0.0625rem solid var(--table-border-color); + border-radius: var(--universal-border-radius); + background: #fafafa; + padding: var(--universal-padding); + margin: var(--universal-margin); + margin-bottom: calc(2 * var(--universal-margin)); } + table th, table td, table.horizontal th, table.horizontal td { + width: auto; } + table td, table.horizontal td { + display: block; + border: 0; + text-align: right; } + table td:before, table.horizontal td:before { + content: attr(data-label); + float: left; + font-weight: 600; } + table th:first-child, table td:first-child, table.horizontal th:first-child, table.horizontal td:first-child { + border-top: 0; } + table tbody tr:last-child td, table.horizontal tbody tr:last-child td { + border-right: 0; } } +:root { + --table-body-alt-back-color: #eee; } + +table tr:nth-of-type(2n) > td { + background: var(--table-body-alt-back-color); } + +@media screen and (max-width: 500px) { + table tr:nth-of-type(2n) { + background: var(--table-body-alt-back-color); } } +:root { + --table-body-hover-back-color: #90caf9; } + +table.hoverable tr:hover, table.hoverable tr:hover > td, table.hoverable tr:focus, table.hoverable tr:focus > td { + background: var(--table-body-hover-back-color); } + +@media screen and (max-width: 500px) { + table.hoverable tr:hover, table.hoverable tr:hover > td, table.hoverable tr:focus, table.hoverable tr:focus > td { + background: var(--table-body-hover-back-color); } } +/* + Definitions for contextual background elements, toasts and tooltips. +*/ +/* Contextual module CSS variable definitions */ +:root { + --mark-back-color: #0277bd; + --mark-fore-color: #fafafa; } + +mark { + background: var(--mark-back-color); + color: var(--mark-fore-color); + font-size: 0.95em; + line-height: 1em; + border-radius: var(--universal-border-radius); + padding: calc(var(--universal-padding) / 4) calc(var(--universal-padding) / 2); } + mark.inline-block { + display: inline-block; + font-size: 1em; + line-height: 1.5; + padding: calc(var(--universal-padding) / 2) var(--universal-padding); } + +:root { + --toast-back-color: #424242; + --toast-fore-color: #fafafa; } + +.toast { + position: fixed; + bottom: calc(var(--universal-margin) * 3); + left: 50%; + transform: translate(-50%, -50%); + z-index: 1111; + color: var(--toast-fore-color); + background: var(--toast-back-color); + border-radius: calc(var(--universal-border-radius) * 16); + padding: var(--universal-padding) calc(var(--universal-padding) * 3); } + +:root { + --tooltip-back-color: #212121; + --tooltip-fore-color: #fafafa; } + +.tooltip { + position: relative; + display: inline-block; } + .tooltip:before, .tooltip:after { + position: absolute; + opacity: 0; + clip: rect(0 0 0 0); + -webkit-clip-path: inset(100%); + clip-path: inset(100%); + transition: all 0.3s; + z-index: 1010; + left: 50%; } + .tooltip:not(.bottom):before, .tooltip:not(.bottom):after { + bottom: 75%; } + .tooltip.bottom:before, .tooltip.bottom:after { + top: 75%; } + .tooltip:hover:before, .tooltip:hover:after, .tooltip:focus:before, .tooltip:focus:after { + opacity: 1; + clip: auto; + -webkit-clip-path: inset(0%); + clip-path: inset(0%); } + .tooltip:before { + content: ''; + background: transparent; + border: var(--universal-margin) solid transparent; + left: calc(50% - var(--universal-margin)); } + .tooltip:not(.bottom):before { + border-top-color: #212121; } + .tooltip.bottom:before { + border-bottom-color: #212121; } + .tooltip:after { + content: attr(aria-label); + color: var(--tooltip-fore-color); + background: var(--tooltip-back-color); + border-radius: var(--universal-border-radius); + padding: var(--universal-padding); + white-space: nowrap; + transform: translateX(-50%); } + .tooltip:not(.bottom):after { + margin-bottom: calc(2 * var(--universal-margin)); } + .tooltip.bottom:after { + margin-top: calc(2 * var(--universal-margin)); } + +:root { + --modal-overlay-color: rgba(0, 0, 0, 0.45); + --modal-close-color: #444; + --modal-close-hover-color: #f0f0f0; } + +[type="checkbox"].modal { + height: 1px; + width: 1px; + margin: -1px; + overflow: hidden; + position: absolute; + clip: rect(0 0 0 0); + -webkit-clip-path: inset(100%); + clip-path: inset(100%); } + [type="checkbox"].modal + div { + position: fixed; + top: 0; + left: 0; + display: none; + width: 100vw; + height: 100vh; + background: var(--modal-overlay-color); } + [type="checkbox"].modal + div .card { + margin: 0 auto; + max-height: 50vh; + overflow: auto; } + [type="checkbox"].modal + div .card .modal-close { + position: absolute; + top: 0; + right: 0; + width: 1.75rem; + height: 1.75rem; + border-radius: var(--universal-border-radius); + padding: var(--universal-padding); + margin: 0; + cursor: pointer; + transition: background 0.3s; } + [type="checkbox"].modal + div .card .modal-close:before { + display: block; + content: '\00D7'; + color: var(--modal-close-color); + position: relative; + font-family: sans-serif; + font-size: 1.75rem; + line-height: 1; + text-align: center; } + [type="checkbox"].modal + div .card .modal-close:hover, [type="checkbox"].modal + div .card .modal-close:focus { + background: var(--modal-close-hover-color); } + [type="checkbox"].modal:checked + div { + display: flex; + flex: 0 1 auto; + z-index: 1200; } + [type="checkbox"].modal:checked + div .card .modal-close { + z-index: 1211; } + +:root { + --collapse-label-back-color: #e8e8e8; + --collapse-label-fore-color: #212121; + --collapse-label-hover-back-color: #f0f0f0; + --collapse-selected-label-back-color: #ececec; + --collapse-border-color: #ddd; + --collapse-content-back-color: #fafafa; + --collapse-selected-label-border-color: #0277bd; } + +.collapse { + width: calc(100% - 2 * var(--universal-margin)); + opacity: 1; + display: flex; + flex-direction: column; + margin: var(--universal-margin); + border-radius: var(--universal-border-radius); } + .collapse > [type="radio"], .collapse > [type="checkbox"] { + height: 1px; + width: 1px; + margin: -1px; + overflow: hidden; + position: absolute; + clip: rect(0 0 0 0); + -webkit-clip-path: inset(100%); + clip-path: inset(100%); } + .collapse > label { + flex-grow: 1; + display: inline-block; + height: 1.5rem; + cursor: pointer; + transition: background 0.3s; + color: var(--collapse-label-fore-color); + background: var(--collapse-label-back-color); + border: 0.0625rem solid var(--collapse-border-color); + padding: calc(1.5 * var(--universal-padding)); } + .collapse > label:hover, .collapse > label:focus { + background: var(--collapse-label-hover-back-color); } + .collapse > label + div { + flex-basis: auto; + height: 1px; + width: 1px; + margin: -1px; + overflow: hidden; + position: absolute; + clip: rect(0 0 0 0); + -webkit-clip-path: inset(100%); + clip-path: inset(100%); + transition: max-height 0.3s; + max-height: 1px; } + .collapse > :checked + label { + background: var(--collapse-selected-label-back-color); + border-bottom-color: var(--collapse-selected-label-border-color); } + .collapse > :checked + label + div { + box-sizing: border-box; + position: relative; + width: 100%; + height: auto; + overflow: auto; + margin: 0; + background: var(--collapse-content-back-color); + border: 0.0625rem solid var(--collapse-border-color); + border-top: 0; + padding: var(--universal-padding); + clip: auto; + -webkit-clip-path: inset(0%); + clip-path: inset(0%); + max-height: 850px; } + .collapse > label:not(:first-of-type) { + border-top: 0; } + .collapse > label:first-of-type { + border-radius: var(--universal-border-radius) var(--universal-border-radius) 0 0; } + .collapse > label:last-of-type:not(:first-of-type) { + border-radius: 0 0 var(--universal-border-radius) var(--universal-border-radius); } + .collapse > label:last-of-type:first-of-type { + border-radius: var(--universal-border-radius); } + .collapse > :checked:last-of-type:not(:first-of-type) + label { + border-radius: 0; } + .collapse > :checked:last-of-type + label + div { + border-radius: 0 0 var(--universal-border-radius) var(--universal-border-radius); } + +/* + Custom elements for contextual background elements, toasts and tooltips. +*/ +mark.secondary { + --mark-back-color: #d32f2f; } + +mark.tertiary { + --mark-back-color: #308732; } + +mark.tag { + padding: calc(var(--universal-padding)/2) var(--universal-padding); + border-radius: 1em; } + +/* + Definitions for progress elements and spinners. +*/ +/* Progress module CSS variable definitions */ +:root { + --progress-back-color: #ddd; + --progress-fore-color: #555; } + +progress { + display: block; + vertical-align: baseline; + -webkit-appearance: none; + -moz-appearance: none; + appearance: none; + height: 0.75rem; + width: calc(100% - 2 * var(--universal-margin)); + margin: var(--universal-margin); + border: 0; + border-radius: calc(2 * var(--universal-border-radius)); + background: var(--progress-back-color); + color: var(--progress-fore-color); } + progress::-webkit-progress-value { + background: var(--progress-fore-color); + border-top-left-radius: calc(2 * var(--universal-border-radius)); + border-bottom-left-radius: calc(2 * var(--universal-border-radius)); } + progress::-webkit-progress-bar { + background: var(--progress-back-color); } + progress::-moz-progress-bar { + background: var(--progress-fore-color); + border-top-left-radius: calc(2 * var(--universal-border-radius)); + border-bottom-left-radius: calc(2 * var(--universal-border-radius)); } + progress[value="1000"]::-webkit-progress-value { + border-radius: calc(2 * var(--universal-border-radius)); } + progress[value="1000"]::-moz-progress-bar { + border-radius: calc(2 * var(--universal-border-radius)); } + progress.inline { + display: inline-block; + vertical-align: middle; + width: 60%; } + +:root { + --spinner-back-color: #ddd; + --spinner-fore-color: #555; } + +@keyframes spinner-donut-anim { + 0% { + transform: rotate(0deg); } + 100% { + transform: rotate(360deg); } } +.spinner { + display: inline-block; + margin: var(--universal-margin); + border: 0.25rem solid var(--spinner-back-color); + border-left: 0.25rem solid var(--spinner-fore-color); + border-radius: 50%; + width: 1.25rem; + height: 1.25rem; + animation: spinner-donut-anim 1.2s linear infinite; } + +/* + Custom elements for progress bars and spinners. +*/ +progress.primary { + --progress-fore-color: #1976d2; } + +progress.secondary { + --progress-fore-color: #d32f2f; } + +progress.tertiary { + --progress-fore-color: #308732; } + +.spinner.primary { + --spinner-fore-color: #1976d2; } + +.spinner.secondary { + --spinner-fore-color: #d32f2f; } + +.spinner.tertiary { + --spinner-fore-color: #308732; } + +/* + Definitions for icons - powered by Feather (https://feathericons.com/). +*/ +span[class^='icon-'] { + display: inline-block; + height: 1em; + width: 1em; + vertical-align: -0.125em; + background-size: contain; + margin: 0 calc(var(--universal-margin) / 4); } + span[class^='icon-'].secondary { + -webkit-filter: invert(25%); + filter: invert(25%); } + span[class^='icon-'].inverse { + -webkit-filter: invert(100%); + filter: invert(100%); } + +span.icon-alert { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='8' x2='12' y2='12'%3E%3C/line%3E%3Cline x1='12' y1='16' x2='12' y2='16'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-bookmark { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M19 21l-7-5-7 5V5a2 2 0 0 1 2-2h10a2 2 0 0 1 2 2z'%3E%3C/path%3E%3C/svg%3E"); } +span.icon-calendar { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='3' y='4' width='18' height='18' rx='2' ry='2'%3E%3C/rect%3E%3Cline x1='16' y1='2' x2='16' y2='6'%3E%3C/line%3E%3Cline x1='8' y1='2' x2='8' y2='6'%3E%3C/line%3E%3Cline x1='3' y1='10' x2='21' y2='10'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-credit { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='1' y='4' width='22' height='16' rx='2' ry='2'%3E%3C/rect%3E%3Cline x1='1' y1='10' x2='23' y2='10'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-edit { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M20 14.66V20a2 2 0 0 1-2 2H4a2 2 0 0 1-2-2V6a2 2 0 0 1 2-2h5.34'%3E%3C/path%3E%3Cpolygon points='18 2 22 6 12 16 8 16 8 12 18 2'%3E%3C/polygon%3E%3C/svg%3E"); } +span.icon-link { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M18 13v6a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2V8a2 2 0 0 1 2-2h6'%3E%3C/path%3E%3Cpolyline points='15 3 21 3 21 9'%3E%3C/polyline%3E%3Cline x1='10' y1='14' x2='21' y2='3'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-help { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M9.09 9a3 3 0 0 1 5.83 1c0 2-3 3-3 3'%3E%3C/path%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='17' x2='12' y2='17'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-home { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M3 9l9-7 9 7v11a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2z'%3E%3C/path%3E%3Cpolyline points='9 22 9 12 15 12 15 22'%3E%3C/polyline%3E%3C/svg%3E"); } +span.icon-info { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='16' x2='12' y2='12'%3E%3C/line%3E%3Cline x1='12' y1='8' x2='12' y2='8'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-lock { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='3' y='11' width='18' height='11' rx='2' ry='2'%3E%3C/rect%3E%3Cpath d='M7 11V7a5 5 0 0 1 10 0v4'%3E%3C/path%3E%3C/svg%3E"); } +span.icon-mail { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M4 4h16c1.1 0 2 .9 2 2v12c0 1.1-.9 2-2 2H4c-1.1 0-2-.9-2-2V6c0-1.1.9-2 2-2z'%3E%3C/path%3E%3Cpolyline points='22,6 12,13 2,6'%3E%3C/polyline%3E%3C/svg%3E"); } +span.icon-location { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M21 10c0 7-9 13-9 13s-9-6-9-13a9 9 0 0 1 18 0z'%3E%3C/path%3E%3Ccircle cx='12' cy='10' r='3'%3E%3C/circle%3E%3C/svg%3E"); } +span.icon-phone { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M22 16.92v3a2 2 0 0 1-2.18 2 19.79 19.79 0 0 1-8.63-3.07 19.5 19.5 0 0 1-6-6 19.79 19.79 0 0 1-3.07-8.67A2 2 0 0 1 4.11 2h3a2 2 0 0 1 2 1.72 12.84 12.84 0 0 0 .7 2.81 2 2 0 0 1-.45 2.11L8.09 9.91a16 16 0 0 0 6 6l1.27-1.27a2 2 0 0 1 2.11-.45 12.84 12.84 0 0 0 2.81.7A2 2 0 0 1 22 16.92z'%3E%3C/path%3E%3C/svg%3E"); } +span.icon-rss { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M4 11a9 9 0 0 1 9 9'%3E%3C/path%3E%3Cpath d='M4 4a16 16 0 0 1 16 16'%3E%3C/path%3E%3Ccircle cx='5' cy='19' r='1'%3E%3C/circle%3E%3C/svg%3E"); } +span.icon-search { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='11' cy='11' r='8'%3E%3C/circle%3E%3Cline x1='21' y1='21' x2='16.65' y2='16.65'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-settings { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='3'%3E%3C/circle%3E%3Cpath d='M19.4 15a1.65 1.65 0 0 0 .33 1.82l.06.06a2 2 0 0 1 0 2.83 2 2 0 0 1-2.83 0l-.06-.06a1.65 1.65 0 0 0-1.82-.33 1.65 1.65 0 0 0-1 1.51V21a2 2 0 0 1-2 2 2 2 0 0 1-2-2v-.09A1.65 1.65 0 0 0 9 19.4a1.65 1.65 0 0 0-1.82.33l-.06.06a2 2 0 0 1-2.83 0 2 2 0 0 1 0-2.83l.06-.06a1.65 1.65 0 0 0 .33-1.82 1.65 1.65 0 0 0-1.51-1H3a2 2 0 0 1-2-2 2 2 0 0 1 2-2h.09A1.65 1.65 0 0 0 4.6 9a1.65 1.65 0 0 0-.33-1.82l-.06-.06a2 2 0 0 1 0-2.83 2 2 0 0 1 2.83 0l.06.06a1.65 1.65 0 0 0 1.82.33H9a1.65 1.65 0 0 0 1-1.51V3a2 2 0 0 1 2-2 2 2 0 0 1 2 2v.09a1.65 1.65 0 0 0 1 1.51 1.65 1.65 0 0 0 1.82-.33l.06-.06a2 2 0 0 1 2.83 0 2 2 0 0 1 0 2.83l-.06.06a1.65 1.65 0 0 0-.33 1.82V9a1.65 1.65 0 0 0 1.51 1H21a2 2 0 0 1 2 2 2 2 0 0 1-2 2h-.09a1.65 1.65 0 0 0-1.51 1z'%3E%3C/path%3E%3C/svg%3E"); } +span.icon-share { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='18' cy='5' r='3'%3E%3C/circle%3E%3Ccircle cx='6' cy='12' r='3'%3E%3C/circle%3E%3Ccircle cx='18' cy='19' r='3'%3E%3C/circle%3E%3Cline x1='8.59' y1='13.51' x2='15.42' y2='17.49'%3E%3C/line%3E%3Cline x1='15.41' y1='6.51' x2='8.59' y2='10.49'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-cart { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='9' cy='21' r='1'%3E%3C/circle%3E%3Ccircle cx='20' cy='21' r='1'%3E%3C/circle%3E%3Cpath d='M1 1h4l2.68 13.39a2 2 0 0 0 2 1.61h9.72a2 2 0 0 0 2-1.61L23 6H6'%3E%3C/path%3E%3C/svg%3E"); } +span.icon-upload { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M21 15v4a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2v-4'%3E%3C/path%3E%3Cpolyline points='17 8 12 3 7 8'%3E%3C/polyline%3E%3Cline x1='12' y1='3' x2='12' y2='15'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-user { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M20 21v-2a4 4 0 0 0-4-4H8a4 4 0 0 0-4 4v2'%3E%3C/path%3E%3Ccircle cx='12' cy='7' r='4'%3E%3C/circle%3E%3C/svg%3E"); } + +/* + Definitions for utilities and helper classes. +*/ +/* Utility module CSS variable definitions */ +:root { + --generic-border-color: rgba(0, 0, 0, 0.3); + --generic-box-shadow: 0 0.25rem 0.25rem 0 rgba(0, 0, 0, 0.125), 0 0.125rem 0.125rem -0.125rem rgba(0, 0, 0, 0.25); } + +.hidden { + display: none !important; } + +.visually-hidden { + position: absolute !important; + width: 1px !important; + height: 1px !important; + margin: -1px !important; + border: 0 !important; + padding: 0 !important; + clip: rect(0 0 0 0) !important; + -webkit-clip-path: inset(100%) !important; + clip-path: inset(100%) !important; + overflow: hidden !important; } + +.bordered { + border: 0.0625rem solid var(--generic-border-color) !important; } + +.rounded { + border-radius: var(--universal-border-radius) !important; } + +.circular { + border-radius: 50% !important; } + +.shadowed { + box-shadow: var(--generic-box-shadow) !important; } + +.responsive-margin { + margin: calc(var(--universal-margin) / 4) !important; } + @media screen and (min-width: 500px) { + .responsive-margin { + margin: calc(var(--universal-margin) / 2) !important; } } + @media screen and (min-width: 1280px) { + .responsive-margin { + margin: var(--universal-margin) !important; } } + +.responsive-padding { + padding: calc(var(--universal-padding) / 4) !important; } + @media screen and (min-width: 500px) { + .responsive-padding { + padding: calc(var(--universal-padding) / 2) !important; } } + @media screen and (min-width: 1280px) { + .responsive-padding { + padding: var(--universal-padding) !important; } } + +@media screen and (max-width: 499px) { + .hidden-sm { + display: none !important; } } +@media screen and (min-width: 500px) and (max-width: 1279px) { + .hidden-md { + display: none !important; } } +@media screen and (min-width: 1280px) { + .hidden-lg { + display: none !important; } } +@media screen and (max-width: 499px) { + .visually-hidden-sm { + position: absolute !important; + width: 1px !important; + height: 1px !important; + margin: -1px !important; + border: 0 !important; + padding: 0 !important; + clip: rect(0 0 0 0) !important; + -webkit-clip-path: inset(100%) !important; + clip-path: inset(100%) !important; + overflow: hidden !important; } } +@media screen and (min-width: 500px) and (max-width: 1279px) { + .visually-hidden-md { + position: absolute !important; + width: 1px !important; + height: 1px !important; + margin: -1px !important; + border: 0 !important; + padding: 0 !important; + clip: rect(0 0 0 0) !important; + -webkit-clip-path: inset(100%) !important; + clip-path: inset(100%) !important; + overflow: hidden !important; } } +@media screen and (min-width: 1280px) { + .visually-hidden-lg { + position: absolute !important; + width: 1px !important; + height: 1px !important; + margin: -1px !important; + border: 0 !important; + padding: 0 !important; + clip: rect(0 0 0 0) !important; + -webkit-clip-path: inset(100%) !important; + clip-path: inset(100%) !important; + overflow: hidden !important; } } + +/*# sourceMappingURL=mini-default.css.map */ diff --git a/Utilities/sequencer/_htmresc/st_logo.png b/Utilities/sequencer/_htmresc/st_logo.png new file mode 100644 index 0000000..8b80057 Binary files /dev/null and b/Utilities/sequencer/_htmresc/st_logo.png differ diff --git a/Utilities/sequencer/html/annotated.html b/Utilities/sequencer/html/annotated.html new file mode 100644 index 0000000..a56b8bb --- /dev/null +++ b/Utilities/sequencer/html/annotated.html @@ -0,0 +1,103 @@ + + + + + + + +STM32 Sequencer: Data Structures + + + + + + + + + + + + + +
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STM32 Sequencer +  v1.6.0 +
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Data Structures
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Here are the data structures with brief descriptions:
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 CUTIL_SEQ_Priority_tStructure used to manage task scheduling
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+ + + + diff --git a/Utilities/sequencer/html/annotated_dup.js b/Utilities/sequencer/html/annotated_dup.js new file mode 100644 index 0000000..668a38e --- /dev/null +++ b/Utilities/sequencer/html/annotated_dup.js @@ -0,0 +1,4 @@ +var annotated_dup = +[ + [ "UTIL_SEQ_Priority_t", "struct_u_t_i_l___s_e_q___priority__t.html", "struct_u_t_i_l___s_e_q___priority__t" ] +]; \ No newline at end of file diff --git a/Utilities/sequencer/html/bc_s.png b/Utilities/sequencer/html/bc_s.png new file mode 100644 index 0000000..224b29a Binary files /dev/null and b/Utilities/sequencer/html/bc_s.png differ diff --git a/Utilities/sequencer/html/bdwn.png b/Utilities/sequencer/html/bdwn.png new file mode 100644 index 0000000..940a0b9 Binary files /dev/null and b/Utilities/sequencer/html/bdwn.png differ diff --git a/Utilities/sequencer/html/classes.html b/Utilities/sequencer/html/classes.html new file mode 100644 index 0000000..6cc1558 --- /dev/null +++ b/Utilities/sequencer/html/classes.html @@ -0,0 +1,104 @@ + + + + + + + +STM32 Sequencer: Data Structure Index + + + + + + + + + + + + + +
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STM32 Sequencer +  v1.6.0 +
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Data Structure Index
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U
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U
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UTIL_SEQ_Priority_t
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+
+ + + + diff --git a/Utilities/sequencer/html/closed.png b/Utilities/sequencer/html/closed.png new file mode 100644 index 0000000..98cc2c9 Binary files /dev/null and b/Utilities/sequencer/html/closed.png differ diff --git a/Utilities/sequencer/html/doc.png b/Utilities/sequencer/html/doc.png new file mode 100644 index 0000000..17edabf Binary files /dev/null and b/Utilities/sequencer/html/doc.png differ diff --git a/Utilities/sequencer/html/doxygen.css b/Utilities/sequencer/html/doxygen.css new file mode 100644 index 0000000..ffbff02 --- /dev/null +++ b/Utilities/sequencer/html/doxygen.css @@ -0,0 +1,1793 @@ +/* The standard CSS for doxygen 1.9.1 */ + +body, table, div, p, dl { + font: 400 14px/22px Roboto,sans-serif; +} + +p.reference, p.definition { + font: 400 14px/22px Roboto,sans-serif; +} + +/* @group Heading Levels */ + +h1.groupheader { + font-size: 150%; +} + +.title { + font: 400 14px/28px Roboto,sans-serif; + font-size: 150%; + font-weight: bold; + margin: 10px 2px; +} + +h2.groupheader { + border-bottom: 1px solid #879ECB; + color: #354C7B; + font-size: 150%; + font-weight: normal; + margin-top: 1.75em; + padding-top: 8px; + padding-bottom: 4px; + width: 100%; +} + +h3.groupheader { + font-size: 100%; +} + +h1, h2, h3, h4, h5, h6 { + -webkit-transition: text-shadow 0.5s linear; + -moz-transition: text-shadow 0.5s linear; + -ms-transition: text-shadow 0.5s linear; + -o-transition: text-shadow 0.5s linear; + transition: text-shadow 0.5s linear; + margin-right: 15px; +} + +h1.glow, h2.glow, h3.glow, h4.glow, h5.glow, h6.glow { + text-shadow: 0 0 15px cyan; +} + +dt { + font-weight: bold; +} + +ul.multicol { + -moz-column-gap: 1em; + -webkit-column-gap: 1em; + column-gap: 1em; + -moz-column-count: 3; + -webkit-column-count: 3; + column-count: 3; +} + +p.startli, p.startdd { + margin-top: 2px; +} + +th p.starttd, th p.intertd, th p.endtd { + font-size: 100%; + font-weight: 700; +} + +p.starttd { + margin-top: 0px; +} + +p.endli { + margin-bottom: 0px; +} + +p.enddd { + margin-bottom: 4px; +} + +p.endtd { + margin-bottom: 2px; +} + +p.interli { +} + +p.interdd { +} + +p.intertd { +} + +/* @end */ + +caption { + font-weight: bold; +} + +span.legend { + font-size: 70%; + text-align: center; +} + +h3.version { + font-size: 90%; + text-align: center; +} + +div.navtab { + border-right: 1px solid #A3B4D7; + padding-right: 15px; + text-align: right; + line-height: 110%; +} + +div.navtab table { + border-spacing: 0; +} + +td.navtab { + padding-right: 6px; + padding-left: 6px; +} +td.navtabHL { + background-image: url('tab_a.png'); + background-repeat:repeat-x; + padding-right: 6px; + padding-left: 6px; +} + +td.navtabHL a, td.navtabHL a:visited { + color: #fff; + text-shadow: 0px 1px 1px rgba(0, 0, 0, 1.0); +} + +a.navtab { + font-weight: bold; +} + +div.qindex{ + text-align: center; + width: 100%; + line-height: 140%; + font-size: 130%; + color: #A0A0A0; +} + +dt.alphachar{ + font-size: 180%; + font-weight: bold; +} + +.alphachar a{ + color: black; +} + +.alphachar a:hover, .alphachar a:visited{ + text-decoration: none; +} + +.classindex dl { + padding: 25px; + column-count:1 +} + +.classindex dd { + display:inline-block; + margin-left: 50px; + width: 90%; + line-height: 1.15em; +} + +.classindex dl.odd { + background-color: #F8F9FC; +} + +@media(min-width: 1120px) { + .classindex dl { + column-count:2 + } +} + +@media(min-width: 1320px) { + .classindex dl { + column-count:3 + } +} + + +/* @group Link Styling */ + +a { + color: #3D578C; + font-weight: normal; + text-decoration: none; +} + +.contents a:visited { + color: #4665A2; +} + +a:hover { + text-decoration: underline; +} + +.contents a.qindexHL:visited { + color: #FFFFFF; +} + +a.el { + font-weight: bold; +} + +a.elRef { +} + +a.code, a.code:visited, a.line, a.line:visited { + color: #4665A2; +} + +a.codeRef, a.codeRef:visited, a.lineRef, a.lineRef:visited { + color: #4665A2; +} + +/* @end */ + +dl.el { + margin-left: -1cm; +} + +ul { + overflow: hidden; /*Fixed: list item bullets overlap floating elements*/ +} + +#side-nav ul { + overflow: visible; /* reset ul rule for scroll bar in GENERATE_TREEVIEW window */ +} + +#main-nav ul { + overflow: visible; /* reset ul rule for the navigation bar drop down lists */ +} + +.fragment { + text-align: left; + direction: ltr; + overflow-x: auto; /*Fixed: fragment lines overlap floating elements*/ + overflow-y: hidden; +} + +pre.fragment { + border: 1px solid #C4CFE5; + background-color: #FBFCFD; + padding: 4px 6px; + margin: 4px 8px 4px 2px; + overflow: auto; + word-wrap: break-word; + font-size: 9pt; + line-height: 125%; + font-family: monospace, fixed; + font-size: 105%; +} + +div.fragment { + padding: 0 0 1px 0; /*Fixed: last line underline overlap border*/ + margin: 4px 8px 4px 2px; + background-color: #FBFCFD; + border: 1px solid #C4CFE5; +} + +div.line { + font-family: monospace, fixed; + font-size: 13px; + min-height: 13px; + line-height: 1.0; + text-wrap: unrestricted; + white-space: -moz-pre-wrap; /* Moz */ + white-space: -pre-wrap; /* Opera 4-6 */ + white-space: -o-pre-wrap; /* Opera 7 */ + white-space: pre-wrap; /* CSS3 */ + word-wrap: break-word; /* IE 5.5+ */ + text-indent: -53px; + padding-left: 53px; + padding-bottom: 0px; + margin: 0px; + -webkit-transition-property: background-color, box-shadow; + -webkit-transition-duration: 0.5s; + -moz-transition-property: background-color, box-shadow; + -moz-transition-duration: 0.5s; + -ms-transition-property: background-color, box-shadow; + -ms-transition-duration: 0.5s; + -o-transition-property: background-color, box-shadow; + -o-transition-duration: 0.5s; + transition-property: background-color, box-shadow; + transition-duration: 0.5s; +} + +div.line:after { + content:"\000A"; + white-space: pre; +} + +div.line.glow { + background-color: cyan; + box-shadow: 0 0 10px cyan; +} + + +span.lineno { + padding-right: 4px; + text-align: right; + border-right: 2px solid #0F0; + background-color: #E8E8E8; + white-space: pre; +} +span.lineno a { + background-color: #D8D8D8; +} + +span.lineno a:hover { + background-color: #C8C8C8; +} + +.lineno { + -webkit-touch-callout: none; + -webkit-user-select: none; + -khtml-user-select: none; + -moz-user-select: none; + -ms-user-select: none; + user-select: none; +} + +div.ah, span.ah { + background-color: black; + font-weight: bold; + color: #FFFFFF; + margin-bottom: 3px; + margin-top: 3px; + padding: 0.2em; + border: solid thin #333; + border-radius: 0.5em; + -webkit-border-radius: .5em; + -moz-border-radius: .5em; + box-shadow: 2px 2px 3px #999; + -webkit-box-shadow: 2px 2px 3px #999; + -moz-box-shadow: rgba(0, 0, 0, 0.15) 2px 2px 2px; + background-image: -webkit-gradient(linear, left top, left bottom, from(#eee), to(#000),color-stop(0.3, #444)); + background-image: -moz-linear-gradient(center top, #eee 0%, #444 40%, #000 110%); +} + +div.classindex ul { + list-style: none; + padding-left: 0; +} + +div.classindex span.ai { + display: inline-block; +} + +div.groupHeader { + margin-left: 16px; + margin-top: 12px; + font-weight: bold; +} + +div.groupText { + margin-left: 16px; + font-style: italic; +} + +body { + background-color: white; + color: black; + margin: 0; +} + +div.contents { + margin-top: 10px; + margin-left: 12px; + margin-right: 8px; +} + +td.indexkey { + background-color: #EBEFF6; + font-weight: bold; + border: 1px solid #C4CFE5; + margin: 2px 0px 2px 0; + padding: 2px 10px; + white-space: nowrap; + vertical-align: top; +} + +td.indexvalue { + background-color: #EBEFF6; + border: 1px solid #C4CFE5; + padding: 2px 10px; + margin: 2px 0px; +} + +tr.memlist { + background-color: #EEF1F7; +} + +p.formulaDsp { + text-align: center; +} + +img.formulaDsp { + +} + +img.formulaInl, img.inline { + vertical-align: middle; +} + +div.center { + text-align: center; + margin-top: 0px; + margin-bottom: 0px; + padding: 0px; +} + +div.center img { + border: 0px; +} + +address.footer { + text-align: right; + padding-right: 12px; +} + +img.footer { + border: 0px; + vertical-align: middle; +} + +/* @group Code Colorization */ + +span.keyword { + color: #008000 +} + +span.keywordtype { + color: #604020 +} + +span.keywordflow { + color: #e08000 +} + +span.comment { + color: #800000 +} + +span.preprocessor { + color: #806020 +} + +span.stringliteral { + color: #002080 +} + +span.charliteral { + color: #008080 +} + +span.vhdldigit { + color: #ff00ff +} + +span.vhdlchar { + color: #000000 +} + +span.vhdlkeyword { + color: #700070 +} + +span.vhdllogic { + color: #ff0000 +} + +blockquote { + background-color: #F7F8FB; + border-left: 2px solid #9CAFD4; + margin: 0 24px 0 4px; + padding: 0 12px 0 16px; +} + +blockquote.DocNodeRTL { + border-left: 0; + border-right: 2px solid #9CAFD4; + margin: 0 4px 0 24px; + padding: 0 16px 0 12px; +} + +/* @end */ + +/* +.search { + color: #003399; + font-weight: bold; +} + +form.search { + margin-bottom: 0px; + margin-top: 0px; +} + +input.search { + font-size: 75%; + color: #000080; + font-weight: normal; + background-color: #e8eef2; +} +*/ + +td.tiny { + font-size: 75%; +} + +.dirtab { + padding: 4px; + border-collapse: collapse; + border: 1px solid #A3B4D7; +} + +th.dirtab { + background: #EBEFF6; + font-weight: bold; +} + +hr { + height: 0px; + border: none; + border-top: 1px solid #4A6AAA; +} + +hr.footer { + height: 1px; +} + +/* @group Member Descriptions */ + +table.memberdecls { + border-spacing: 0px; + padding: 0px; +} + +.memberdecls td, .fieldtable tr { + -webkit-transition-property: background-color, box-shadow; + -webkit-transition-duration: 0.5s; + -moz-transition-property: background-color, box-shadow; + -moz-transition-duration: 0.5s; + -ms-transition-property: background-color, box-shadow; + -ms-transition-duration: 0.5s; + -o-transition-property: background-color, box-shadow; + -o-transition-duration: 0.5s; + transition-property: background-color, box-shadow; + transition-duration: 0.5s; +} + +.memberdecls td.glow, .fieldtable tr.glow { + background-color: cyan; + box-shadow: 0 0 15px cyan; +} + +.mdescLeft, .mdescRight, +.memItemLeft, .memItemRight, +.memTemplItemLeft, .memTemplItemRight, .memTemplParams { + background-color: #F9FAFC; + border: none; + margin: 4px; + padding: 1px 0 0 8px; +} + +.mdescLeft, .mdescRight { + padding: 0px 8px 4px 8px; + color: #555; +} + +.memSeparator { + border-bottom: 1px solid #DEE4F0; + line-height: 1px; + margin: 0px; + padding: 0px; +} + +.memItemLeft, .memTemplItemLeft { + white-space: nowrap; +} + +.memItemRight, .memTemplItemRight { + width: 100%; +} + +.memTemplParams { + color: #4665A2; + white-space: nowrap; + font-size: 80%; +} + +/* @end */ + +/* @group Member Details */ + +/* Styles for detailed member documentation */ + +.memtitle { + padding: 8px; + border-top: 1px solid #A8B8D9; + border-left: 1px solid #A8B8D9; + border-right: 1px solid #A8B8D9; + border-top-right-radius: 4px; + border-top-left-radius: 4px; + margin-bottom: -1px; + background-image: url('nav_f.png'); + background-repeat: repeat-x; + background-color: #E2E8F2; + line-height: 1.25; + font-weight: 300; + float:left; +} + +.permalink +{ + font-size: 65%; + display: inline-block; + vertical-align: middle; +} + +.memtemplate { + font-size: 80%; + color: #4665A2; + font-weight: normal; + margin-left: 9px; +} + +.memnav { + background-color: #EBEFF6; + border: 1px solid #A3B4D7; + text-align: center; + margin: 2px; + margin-right: 15px; + padding: 2px; +} + +.mempage { + width: 100%; +} + +.memitem { + padding: 0; + margin-bottom: 10px; + margin-right: 5px; + -webkit-transition: box-shadow 0.5s linear; + -moz-transition: box-shadow 0.5s linear; + -ms-transition: box-shadow 0.5s linear; + -o-transition: box-shadow 0.5s linear; + transition: box-shadow 0.5s linear; + display: table !important; + width: 100%; +} + +.memitem.glow { + box-shadow: 0 0 15px cyan; +} + +.memname { + font-weight: 400; + margin-left: 6px; +} + +.memname td { + vertical-align: bottom; +} + +.memproto, dl.reflist dt { + border-top: 1px solid #A8B8D9; + border-left: 1px solid #A8B8D9; + border-right: 1px solid #A8B8D9; + padding: 6px 0px 6px 0px; + color: #253555; + font-weight: bold; + text-shadow: 0px 1px 1px rgba(255, 255, 255, 0.9); + background-color: #DFE5F1; + /* opera specific markup */ + box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15); + border-top-right-radius: 4px; + /* firefox specific markup */ + -moz-box-shadow: rgba(0, 0, 0, 0.15) 5px 5px 5px; + -moz-border-radius-topright: 4px; + /* webkit specific markup */ + -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15); + -webkit-border-top-right-radius: 4px; + +} + +.overload { + font-family: "courier new",courier,monospace; + font-size: 65%; +} + +.memdoc, dl.reflist dd { + border-bottom: 1px solid #A8B8D9; + border-left: 1px solid #A8B8D9; + border-right: 1px solid #A8B8D9; + padding: 6px 10px 2px 10px; + background-color: #FBFCFD; + border-top-width: 0; + background-image:url('nav_g.png'); + background-repeat:repeat-x; + background-color: #FFFFFF; + /* opera specific markup */ + border-bottom-left-radius: 4px; + border-bottom-right-radius: 4px; + box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15); + /* firefox specific markup */ + -moz-border-radius-bottomleft: 4px; + -moz-border-radius-bottomright: 4px; + -moz-box-shadow: rgba(0, 0, 0, 0.15) 5px 5px 5px; + /* webkit specific markup */ + -webkit-border-bottom-left-radius: 4px; + -webkit-border-bottom-right-radius: 4px; + -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15); +} + +dl.reflist dt { + padding: 5px; +} + +dl.reflist dd { + margin: 0px 0px 10px 0px; + padding: 5px; +} + +.paramkey { + text-align: right; +} + +.paramtype { + white-space: nowrap; +} + +.paramname { + color: #602020; + white-space: nowrap; +} +.paramname em { + font-style: normal; +} +.paramname code { + line-height: 14px; +} + +.params, .retval, .exception, .tparams { + margin-left: 0px; + padding-left: 0px; +} + +.params .paramname, .retval .paramname, .tparams .paramname, .exception .paramname { + font-weight: bold; + vertical-align: top; +} + +.params .paramtype, .tparams .paramtype { + font-style: italic; + vertical-align: top; +} + +.params .paramdir, .tparams .paramdir { + font-family: "courier new",courier,monospace; + vertical-align: top; +} + +table.mlabels { + border-spacing: 0px; +} + +td.mlabels-left { + width: 100%; + padding: 0px; +} + +td.mlabels-right { + vertical-align: bottom; + padding: 0px; + white-space: nowrap; +} + +span.mlabels { + margin-left: 8px; +} + +span.mlabel { + background-color: #728DC1; + border-top:1px solid #5373B4; + border-left:1px solid #5373B4; + border-right:1px solid #C4CFE5; + border-bottom:1px solid #C4CFE5; + text-shadow: none; + color: white; + margin-right: 4px; + padding: 2px 3px; + border-radius: 3px; + font-size: 7pt; + white-space: nowrap; + vertical-align: middle; +} + + + +/* @end */ + +/* these are for tree view inside a (index) page */ + +div.directory { + margin: 10px 0px; + border-top: 1px solid #9CAFD4; + border-bottom: 1px solid #9CAFD4; + width: 100%; +} + +.directory table { + border-collapse:collapse; +} + +.directory td { + margin: 0px; + padding: 0px; + vertical-align: top; +} + +.directory td.entry { + white-space: nowrap; + padding-right: 6px; + padding-top: 3px; +} + +.directory td.entry a { + outline:none; +} + +.directory td.entry a img { + border: none; +} + +.directory td.desc { + width: 100%; + padding-left: 6px; + padding-right: 6px; + padding-top: 3px; + border-left: 1px solid rgba(0,0,0,0.05); +} + +.directory tr.even { + padding-left: 6px; + background-color: #F7F8FB; +} + +.directory img { + vertical-align: -30%; +} + +.directory .levels { + white-space: nowrap; + width: 100%; + text-align: right; + font-size: 9pt; +} + +.directory .levels span { + cursor: pointer; + padding-left: 2px; + padding-right: 2px; + color: #3D578C; +} + +.arrow { + color: #9CAFD4; + -webkit-user-select: none; + -khtml-user-select: none; + -moz-user-select: none; + -ms-user-select: none; + user-select: none; + cursor: pointer; + font-size: 80%; + display: inline-block; + width: 16px; + height: 22px; +} + +.icon { + font-family: Arial, Helvetica; + font-weight: bold; + font-size: 12px; + height: 14px; + width: 16px; + display: inline-block; + background-color: #728DC1; + color: white; + text-align: center; + border-radius: 4px; + margin-left: 2px; + margin-right: 2px; +} + +.icona { + width: 24px; + height: 22px; + display: inline-block; +} + +.iconfopen { + width: 24px; + height: 18px; + margin-bottom: 4px; + background-image:url('folderopen.png'); + background-position: 0px -4px; + background-repeat: repeat-y; + vertical-align:top; + display: inline-block; +} + +.iconfclosed { + width: 24px; + height: 18px; + margin-bottom: 4px; + background-image:url('folderclosed.png'); + background-position: 0px -4px; + background-repeat: repeat-y; + vertical-align:top; + display: inline-block; +} + +.icondoc { + width: 24px; + height: 18px; + margin-bottom: 4px; + background-image:url('doc.png'); + background-position: 0px -4px; + background-repeat: repeat-y; + vertical-align:top; + display: inline-block; +} + +table.directory { + font: 400 14px Roboto,sans-serif; +} + +/* @end */ + +div.dynheader { + margin-top: 8px; + -webkit-touch-callout: none; + -webkit-user-select: none; + -khtml-user-select: none; + -moz-user-select: none; + -ms-user-select: none; + user-select: none; +} + +address { + font-style: normal; + color: #2A3D61; +} + +table.doxtable caption { + caption-side: top; +} + +table.doxtable { + border-collapse:collapse; + margin-top: 4px; + margin-bottom: 4px; +} + +table.doxtable td, table.doxtable th { + border: 1px solid #2D4068; + padding: 3px 7px 2px; +} + +table.doxtable th { + background-color: #374F7F; + color: #FFFFFF; + font-size: 110%; + padding-bottom: 4px; + padding-top: 5px; +} + +table.fieldtable { + /*width: 100%;*/ + margin-bottom: 10px; + border: 1px solid #A8B8D9; + border-spacing: 0px; + -moz-border-radius: 4px; + -webkit-border-radius: 4px; + border-radius: 4px; + -moz-box-shadow: rgba(0, 0, 0, 0.15) 2px 2px 2px; + -webkit-box-shadow: 2px 2px 2px rgba(0, 0, 0, 0.15); + box-shadow: 2px 2px 2px rgba(0, 0, 0, 0.15); +} + +.fieldtable td, .fieldtable th { + padding: 3px 7px 2px; +} + +.fieldtable td.fieldtype, .fieldtable td.fieldname { + white-space: nowrap; + border-right: 1px solid #A8B8D9; + border-bottom: 1px solid #A8B8D9; + vertical-align: top; +} + +.fieldtable td.fieldname { + padding-top: 3px; +} + +.fieldtable td.fielddoc { + border-bottom: 1px solid #A8B8D9; + /*width: 100%;*/ +} + +.fieldtable td.fielddoc p:first-child { + margin-top: 0px; +} + +.fieldtable td.fielddoc p:last-child { + margin-bottom: 2px; +} + +.fieldtable tr:last-child td { + border-bottom: none; +} + +.fieldtable th { + background-image:url('nav_f.png'); + background-repeat:repeat-x; + background-color: #E2E8F2; + font-size: 90%; + color: #253555; + padding-bottom: 4px; + padding-top: 5px; + text-align:left; + font-weight: 400; + -moz-border-radius-topleft: 4px; + -moz-border-radius-topright: 4px; + -webkit-border-top-left-radius: 4px; + -webkit-border-top-right-radius: 4px; + border-top-left-radius: 4px; + border-top-right-radius: 4px; + border-bottom: 1px solid #A8B8D9; +} + + +.tabsearch { + top: 0px; + left: 10px; + height: 36px; + background-image: url('tab_b.png'); + z-index: 101; + overflow: hidden; + font-size: 13px; +} + +.navpath ul +{ + font-size: 11px; + background-image:url('tab_b.png'); + background-repeat:repeat-x; + background-position: 0 -5px; + height:30px; + line-height:30px; + color:#8AA0CC; + border:solid 1px #C2CDE4; + overflow:hidden; + margin:0px; + padding:0px; +} + +.navpath li +{ + list-style-type:none; + float:left; + padding-left:10px; + padding-right:15px; + background-image:url('bc_s.png'); + background-repeat:no-repeat; + background-position:right; + color:#364D7C; +} + +.navpath li.navelem a +{ + height:32px; + display:block; + text-decoration: none; + outline: none; + color: #283A5D; + font-family: 'Lucida Grande',Geneva,Helvetica,Arial,sans-serif; + text-shadow: 0px 1px 1px rgba(255, 255, 255, 0.9); + text-decoration: none; +} + +.navpath li.navelem a:hover +{ + color:#6884BD; +} + +.navpath li.footer +{ + list-style-type:none; + float:right; + padding-left:10px; + padding-right:15px; + background-image:none; + background-repeat:no-repeat; + background-position:right; + color:#364D7C; + font-size: 8pt; +} + + +div.summary +{ + float: right; + font-size: 8pt; + padding-right: 5px; + width: 50%; + text-align: right; +} + +div.summary a +{ + white-space: nowrap; +} + +table.classindex +{ + margin: 10px; + white-space: nowrap; + margin-left: 3%; + margin-right: 3%; + width: 94%; + border: 0; + border-spacing: 0; + padding: 0; +} + +div.ingroups +{ + font-size: 8pt; + width: 50%; + text-align: left; +} + +div.ingroups a +{ + white-space: nowrap; +} + +div.header +{ + background-image:url('nav_h.png'); + background-repeat:repeat-x; + background-color: #F9FAFC; + margin: 0px; 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+ padding-right: 3px; + border-right: 4px solid; + border-color: #FF0000; +} + +dl.pre, dl.post, dl.invariant { + margin-left: -7px; + padding-left: 3px; + border-left: 4px solid; + border-color: #00D000; +} + +dl.pre.DocNodeRTL, dl.post.DocNodeRTL, dl.invariant.DocNodeRTL { + margin-left: 0; + padding-left: 0; + border-left: 0; + margin-right: -7px; + padding-right: 3px; + border-right: 4px solid; + border-color: #00D000; +} + +dl.deprecated { + margin-left: -7px; + padding-left: 3px; + border-left: 4px solid; + border-color: #505050; +} + +dl.deprecated.DocNodeRTL { + margin-left: 0; + padding-left: 0; + border-left: 0; + margin-right: -7px; + padding-right: 3px; + border-right: 4px solid; + border-color: #505050; +} + +dl.todo { + margin-left: -7px; + padding-left: 3px; + border-left: 4px solid; + border-color: #00C0E0; +} + +dl.todo.DocNodeRTL { + margin-left: 0; + padding-left: 0; + border-left: 0; + margin-right: -7px; + padding-right: 3px; + border-right: 4px solid; + border-color: #00C0E0; +} + +dl.test { + margin-left: -7px; + padding-left: 3px; + border-left: 4px solid; + border-color: #3030E0; +} + +dl.test.DocNodeRTL { + margin-left: 0; + padding-left: 0; + border-left: 0; + margin-right: -7px; + padding-right: 3px; + border-right: 4px solid; + border-color: #3030E0; +} + +dl.bug { + margin-left: -7px; + padding-left: 3px; + border-left: 4px solid; + border-color: #C08050; +} + +dl.bug.DocNodeRTL { + margin-left: 0; + padding-left: 0; + border-left: 0; + margin-right: -7px; + padding-right: 3px; + border-right: 4px solid; + border-color: #C08050; +} + +dl.section dd { + margin-bottom: 6px; +} + + +#projectlogo +{ + text-align: center; + vertical-align: bottom; + border-collapse: separate; +} + +#projectlogo img +{ + border: 0px none; +} + +#projectalign +{ + vertical-align: middle; +} + +#projectname +{ + font: 300% Tahoma, Arial,sans-serif; + margin: 0px; + padding: 2px 0px; +} + +#projectbrief +{ + font: 120% Tahoma, Arial,sans-serif; + margin: 0px; + padding: 0px; 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+ text-align: right; +} + +div.toc li { + background: url("bdwn.png") no-repeat scroll 0 5px transparent; + font: 10px/1.2 Verdana,DejaVu Sans,Geneva,sans-serif; + margin-top: 5px; + padding-left: 10px; + padding-top: 2px; +} + +.PageDocRTL-title div.toc li { + background-position-x: right !important; + padding-left: 0 !important; + padding-right: 10px; +} + +div.toc h3 { + font: bold 12px/1.2 Arial,FreeSans,sans-serif; + color: #4665A2; + border-bottom: 0 none; + margin: 0; +} + +div.toc ul { + list-style: none outside none; + border: medium none; + padding: 0px; +} + +div.toc li.level1 { + margin-left: 0px; +} + +div.toc li.level2 { + margin-left: 15px; +} + +div.toc li.level3 { + margin-left: 30px; +} + +div.toc li.level4 { + margin-left: 45px; +} + +span.emoji { + /* font family used at the site: https://unicode.org/emoji/charts/full-emoji-list.html + * font-family: "Noto Color Emoji", "Apple Color Emoji", "Segoe UI Emoji", Times, Symbola, Aegyptus, Code2000, Code2001, Code2002, Musica, serif, LastResort; + */ +} + +.PageDocRTL-title div.toc li.level1 { + margin-left: 0 !important; + margin-right: 0; +} + +.PageDocRTL-title div.toc li.level2 { + margin-left: 0 !important; + margin-right: 15px; +} + +.PageDocRTL-title div.toc li.level3 { + margin-left: 0 !important; + margin-right: 30px; +} + +.PageDocRTL-title div.toc li.level4 { + margin-left: 0 !important; + margin-right: 45px; +} + +.inherit_header { + font-weight: bold; + color: gray; + cursor: pointer; + -webkit-touch-callout: none; + -webkit-user-select: none; + -khtml-user-select: none; + -moz-user-select: none; + -ms-user-select: none; + user-select: none; +} + +.inherit_header td { + padding: 6px 0px 2px 5px; +} + +.inherit { + display: none; +} + +tr.heading h2 { + margin-top: 12px; + margin-bottom: 4px; +} + +/* tooltip related style info */ + +.ttc { + position: absolute; + display: none; +} + +#powerTip { + cursor: default; + white-space: nowrap; + background-color: white; + border: 1px solid gray; + border-radius: 4px 4px 4px 4px; + box-shadow: 1px 1px 7px gray; + display: none; + font-size: smaller; + max-width: 80%; + opacity: 0.9; + padding: 1ex 1em 1em; + position: absolute; + z-index: 2147483647; +} + +#powerTip div.ttdoc { + color: grey; + font-style: italic; +} + +#powerTip div.ttname a { + font-weight: bold; +} + +#powerTip div.ttname { + font-weight: bold; +} + +#powerTip div.ttdeci { + color: #006318; +} + +#powerTip div { + margin: 0px; + padding: 0px; + font: 12px/16px Roboto,sans-serif; +} + +#powerTip:before, #powerTip:after { + content: ""; + position: absolute; + margin: 0px; +} + +#powerTip.n:after, #powerTip.n:before, +#powerTip.s:after, #powerTip.s:before, +#powerTip.w:after, #powerTip.w:before, +#powerTip.e:after, #powerTip.e:before, +#powerTip.ne:after, #powerTip.ne:before, +#powerTip.se:after, #powerTip.se:before, +#powerTip.nw:after, #powerTip.nw:before, +#powerTip.sw:after, #powerTip.sw:before { + border: solid transparent; + content: " "; + height: 0; + width: 0; + position: absolute; +} + +#powerTip.n:after, #powerTip.s:after, +#powerTip.w:after, #powerTip.e:after, +#powerTip.nw:after, #powerTip.ne:after, +#powerTip.sw:after, #powerTip.se:after { + border-color: rgba(255, 255, 255, 0); +} + +#powerTip.n:before, #powerTip.s:before, +#powerTip.w:before, #powerTip.e:before, +#powerTip.nw:before, #powerTip.ne:before, +#powerTip.sw:before, #powerTip.se:before { + border-color: rgba(128, 128, 128, 0); +} + +#powerTip.n:after, #powerTip.n:before, +#powerTip.ne:after, #powerTip.ne:before, +#powerTip.nw:after, #powerTip.nw:before { + top: 100%; +} + +#powerTip.n:after, #powerTip.ne:after, #powerTip.nw:after { + border-top-color: #FFFFFF; + border-width: 10px; + margin: 0px -10px; +} +#powerTip.n:before { + border-top-color: #808080; + border-width: 11px; + margin: 0px -11px; +} +#powerTip.n:after, #powerTip.n:before { + left: 50%; +} + +#powerTip.nw:after, #powerTip.nw:before { + right: 14px; +} + +#powerTip.ne:after, #powerTip.ne:before { + left: 14px; +} + +#powerTip.s:after, #powerTip.s:before, +#powerTip.se:after, #powerTip.se:before, +#powerTip.sw:after, #powerTip.sw:before { + bottom: 100%; +} + +#powerTip.s:after, #powerTip.se:after, #powerTip.sw:after { + border-bottom-color: #FFFFFF; + border-width: 10px; + margin: 0px -10px; +} + +#powerTip.s:before, #powerTip.se:before, #powerTip.sw:before { + border-bottom-color: #808080; + border-width: 11px; + margin: 0px -11px; +} + +#powerTip.s:after, #powerTip.s:before { + left: 50%; +} + +#powerTip.sw:after, #powerTip.sw:before { + right: 14px; +} + +#powerTip.se:after, #powerTip.se:before { + left: 14px; +} + +#powerTip.e:after, #powerTip.e:before { + left: 100%; +} +#powerTip.e:after { + border-left-color: #FFFFFF; + border-width: 10px; + top: 50%; + margin-top: -10px; +} +#powerTip.e:before { + border-left-color: #808080; + border-width: 11px; + top: 50%; + margin-top: -11px; +} + +#powerTip.w:after, #powerTip.w:before { + right: 100%; +} +#powerTip.w:after { + border-right-color: #FFFFFF; + border-width: 10px; + top: 50%; + margin-top: -10px; +} +#powerTip.w:before { + border-right-color: #808080; + border-width: 11px; + top: 50%; + margin-top: -11px; +} + +@media print +{ + #top { display: none; } + #side-nav { display: none; } + #nav-path { display: none; } + body { overflow:visible; } + h1, h2, h3, h4, h5, h6 { page-break-after: avoid; } + .summary { display: none; } + .memitem { page-break-inside: avoid; } + #doc-content + { + margin-left:0 !important; + height:auto !important; + width:auto !important; + overflow:inherit; + display:inline; + } +} + +/* @group Markdown */ + +table.markdownTable { + border-collapse:collapse; + margin-top: 4px; + margin-bottom: 4px; +} + +table.markdownTable td, table.markdownTable th { + border: 1px solid #2D4068; + padding: 3px 7px 2px; +} + +table.markdownTable tr { +} + +th.markdownTableHeadLeft, th.markdownTableHeadRight, th.markdownTableHeadCenter, th.markdownTableHeadNone { + background-color: #374F7F; + color: #FFFFFF; + font-size: 110%; + padding-bottom: 4px; + padding-top: 5px; +} + +th.markdownTableHeadLeft, td.markdownTableBodyLeft { + text-align: left +} + +th.markdownTableHeadRight, td.markdownTableBodyRight { + text-align: right +} + +th.markdownTableHeadCenter, td.markdownTableBodyCenter { + text-align: center +} + +.DocNodeRTL { + text-align: right; + direction: rtl; +} + +.DocNodeLTR { + text-align: left; + direction: ltr; +} + +table.DocNodeRTL { + width: auto; + margin-right: 0; + margin-left: auto; +} + +table.DocNodeLTR { + width: auto; + margin-right: auto; + margin-left: 0; +} + +tt, code, kbd, samp +{ + display: inline-block; + direction:ltr; +} +/* @end */ + +u { + text-decoration: underline; +} + diff --git a/Utilities/sequencer/html/doxygen.png b/Utilities/sequencer/html/doxygen.png new file mode 100644 index 0000000..3ff17d8 Binary files /dev/null and b/Utilities/sequencer/html/doxygen.png differ diff --git a/Utilities/sequencer/html/doxygen.svg b/Utilities/sequencer/html/doxygen.svg new file mode 100644 index 0000000..d42dad5 --- /dev/null +++ b/Utilities/sequencer/html/doxygen.svg @@ -0,0 +1,26 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Utilities/sequencer/html/dynsections.js b/Utilities/sequencer/html/dynsections.js new file mode 100644 index 0000000..88f2c27 --- /dev/null +++ b/Utilities/sequencer/html/dynsections.js @@ -0,0 +1,128 @@ +/* + @licstart The following is the entire license notice for the JavaScript code in this file. + + The MIT License (MIT) + + Copyright (C) 1997-2020 by Dimitri van Heesch + + Permission is hereby granted, free of charge, to any person obtaining a copy of this software + and associated documentation files (the "Software"), to deal in the Software without restriction, + including without limitation the rights to use, copy, modify, merge, publish, distribute, + sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in all copies or + substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING + BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + + @licend The above is the entire license notice for the JavaScript code in this file + */ +function toggleVisibility(linkObj) +{ + var base = $(linkObj).attr('id'); + var summary = $('#'+base+'-summary'); + var content = $('#'+base+'-content'); + var trigger = $('#'+base+'-trigger'); + var src=$(trigger).attr('src'); + if (content.is(':visible')===true) { + content.hide(); + summary.show(); + $(linkObj).addClass('closed').removeClass('opened'); + $(trigger).attr('src',src.substring(0,src.length-8)+'closed.png'); + } else { + content.show(); + summary.hide(); + $(linkObj).removeClass('closed').addClass('opened'); + $(trigger).attr('src',src.substring(0,src.length-10)+'open.png'); + } + return false; +} + +function updateStripes() +{ + $('table.directory tr'). + removeClass('even').filter(':visible:even').addClass('even'); +} + +function toggleLevel(level) +{ + $('table.directory tr').each(function() { + var l = this.id.split('_').length-1; + var i = $('#img'+this.id.substring(3)); + var a = $('#arr'+this.id.substring(3)); + if (l + + + + + + +STM32 Sequencer: File List + + + + + + + + + + + + + +
+
+ + + + + + +
+
STM32 Sequencer +  v1.6.0 +
+
+
+ + + + + + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
File List
+
+
+
Here is a list of all files with brief descriptions:
+ + + +
 stm32_seq.cSimple sequencer implementation
 stm32_seq.hSequencer interface
+
+
+
+ + + + diff --git a/Utilities/sequencer/html/files_dup.js b/Utilities/sequencer/html/files_dup.js new file mode 100644 index 0000000..d72fd3e --- /dev/null +++ b/Utilities/sequencer/html/files_dup.js @@ -0,0 +1,5 @@ +var files_dup = +[ + [ "stm32_seq.c", "stm32__seq_8c.html", "stm32__seq_8c" ], + [ "stm32_seq.h", "stm32__seq_8h.html", "stm32__seq_8h" ] +]; \ No newline at end of file diff --git a/Utilities/sequencer/html/folderclosed.png b/Utilities/sequencer/html/folderclosed.png new file mode 100644 index 0000000..bb8ab35 Binary files /dev/null and b/Utilities/sequencer/html/folderclosed.png differ diff --git a/Utilities/sequencer/html/folderopen.png b/Utilities/sequencer/html/folderopen.png new file mode 100644 index 0000000..d6c7f67 Binary files /dev/null and b/Utilities/sequencer/html/folderopen.png differ diff --git a/Utilities/sequencer/html/functions.html b/Utilities/sequencer/html/functions.html new file mode 100644 index 0000000..285c275 --- /dev/null +++ b/Utilities/sequencer/html/functions.html @@ -0,0 +1,102 @@ + + + + + + + +STM32 Sequencer: Data Fields + + + + + + + + + + + + + +
+
+ + + + + + +
+
STM32 Sequencer +  v1.6.0 +
+
+
+ + + + + + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
Here is a list of all struct and union fields with links to the structures/unions they belong to:
+
+
+ + + + diff --git a/Utilities/sequencer/html/functions_vars.html b/Utilities/sequencer/html/functions_vars.html new file mode 100644 index 0000000..b7cb474 --- /dev/null +++ b/Utilities/sequencer/html/functions_vars.html @@ -0,0 +1,102 @@ + + + + + + + +STM32 Sequencer: Data Fields - Variables + + + + + + + + + + + + + +
+
+ + + + + + +
+
STM32 Sequencer +  v1.6.0 +
+
+
+ + + + + + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+  +
+
+ + + + diff --git a/Utilities/sequencer/html/globals.html b/Utilities/sequencer/html/globals.html new file mode 100644 index 0000000..7bd2472 --- /dev/null +++ b/Utilities/sequencer/html/globals.html @@ -0,0 +1,195 @@ + + + + + + + +STM32 Sequencer: Globals + + + + + + + + + + + + + +
+
+ + + + + + +
+
STM32 Sequencer +  v1.6.0 +
+
+
+ + + + + + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:
+ +

- s -

+ + +

- u -

+
+
+ + + + diff --git a/Utilities/sequencer/html/globals_defs.html b/Utilities/sequencer/html/globals_defs.html new file mode 100644 index 0000000..2c01d1d --- /dev/null +++ b/Utilities/sequencer/html/globals_defs.html @@ -0,0 +1,132 @@ + + + + + + + +STM32 Sequencer: Globals + + + + + + + + + + + + + +
+
+ + + + + + +
+
STM32 Sequencer +  v1.6.0 +
+
+
+ + + + + + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+  +
+
+ + + + diff --git a/Utilities/sequencer/html/globals_func.html b/Utilities/sequencer/html/globals_func.html new file mode 100644 index 0000000..27c4431 --- /dev/null +++ b/Utilities/sequencer/html/globals_func.html @@ -0,0 +1,150 @@ + + + + + + + +STM32 Sequencer: Globals + + + + + + + + + + + + + +
+
+ + + + + + +
+
STM32 Sequencer +  v1.6.0 +
+
+
+ + + + + + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+  +
+
+ + + + diff --git a/Utilities/sequencer/html/globals_type.html b/Utilities/sequencer/html/globals_type.html new file mode 100644 index 0000000..409f065 --- /dev/null +++ b/Utilities/sequencer/html/globals_type.html @@ -0,0 +1,99 @@ + + + + + + + +STM32 Sequencer: Globals + + + + + + + + + + + + + +
+
+ + + + + + +
+
STM32 Sequencer +  v1.6.0 +
+
+
+ + + + + + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+  +
+
+ + + + diff --git a/Utilities/sequencer/html/globals_vars.html b/Utilities/sequencer/html/globals_vars.html new file mode 100644 index 0000000..9ca49f9 --- /dev/null +++ b/Utilities/sequencer/html/globals_vars.html @@ -0,0 +1,128 @@ + + + + + + + +Sequencer: Globals + + + + + + + + + + + + + + +
+
+ + + + + + +
+
Sequencer +
+
+
+ + + + + + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+  +
+
+ + + + diff --git a/Utilities/sequencer/html/group___s_e_q_u_e_n_c_e_r.html b/Utilities/sequencer/html/group___s_e_q_u_e_n_c_e_r.html new file mode 100644 index 0000000..f4fa4f6 --- /dev/null +++ b/Utilities/sequencer/html/group___s_e_q_u_e_n_c_e_r.html @@ -0,0 +1,121 @@ + + + + + + + +STM32 Sequencer: sequencer utilities + + + + + + + + + + + + + +
+
+ + + + + + +
+
STM32 Sequencer +  v1.6.0 +
+
+
+ + + + + + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Modules
+
+
sequencer utilities
+
+
+ + + + + + + + + + + + + + + + + + +

+Modules

 SEQUENCER private type
 
 SEQUENCER private defines
 
 SEQUENCER private variables
 
 SEQUENCER private functions
 
 SEQUENCER exported types
 
 SEQUENCER exported constants
 
 SEQUENCER exported macros
 
 SEQUENCER exported functions
 
+

Detailed Description

+
+
+ + + + diff --git a/Utilities/sequencer/html/group___s_e_q_u_e_n_c_e_r.js b/Utilities/sequencer/html/group___s_e_q_u_e_n_c_e_r.js new file mode 100644 index 0000000..7f17721 --- /dev/null +++ b/Utilities/sequencer/html/group___s_e_q_u_e_n_c_e_r.js @@ -0,0 +1,11 @@ +var group___s_e_q_u_e_n_c_e_r = +[ + [ "SEQUENCER private type", "group___s_e_q_u_e_n_c_e_r___private__type.html", "group___s_e_q_u_e_n_c_e_r___private__type" ], + [ "SEQUENCER private defines", "group___s_e_q_u_e_n_c_e_r___private__define.html", "group___s_e_q_u_e_n_c_e_r___private__define" ], + [ "SEQUENCER private variables", "group___s_e_q_u_e_n_c_e_r___private__varaible.html", null ], + [ "SEQUENCER private functions", "group___s_e_q_u_e_n_c_e_r___private__function.html", "group___s_e_q_u_e_n_c_e_r___private__function" ], + [ "SEQUENCER exported types", "group___s_e_q_u_e_n_c_e_r___exported__type.html", "group___s_e_q_u_e_n_c_e_r___exported__type" ], + [ "SEQUENCER exported constants", "group___s_e_q_u_e_n_c_e_r___exported__const.html", "group___s_e_q_u_e_n_c_e_r___exported__const" ], + [ "SEQUENCER exported macros", "group___s_e_q_u_e_n_c_e_r___exported__macro.html", "group___s_e_q_u_e_n_c_e_r___exported__macro" ], + [ "SEQUENCER exported functions", "group___s_e_q_u_e_n_c_e_r___exported__function.html", "group___s_e_q_u_e_n_c_e_r___exported__function" ] +]; \ No newline at end of file diff --git a/Utilities/sequencer/html/group___s_e_q_u_e_n_c_e_r___exported__const.html b/Utilities/sequencer/html/group___s_e_q_u_e_n_c_e_r___exported__const.html new file mode 100644 index 0000000..033403c --- /dev/null +++ b/Utilities/sequencer/html/group___s_e_q_u_e_n_c_e_r___exported__const.html @@ -0,0 +1,155 @@ + + + + + + + +STM32 Sequencer: SEQUENCER exported constants + + + + + + + + + + + + + +
+
+ + + + + + +
+
STM32 Sequencer +  v1.6.0 +
+
+
+ + + + + + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
SEQUENCER exported constants
sequencer utilities
+
+
+ + + + + + + + +

+Macros

#define UTIL_SEQ_RFU   0
 This provides a default value for unused parameter. More...
 
#define UTIL_SEQ_DEFAULT   (~0U)
 Default value used to start the scheduling. More...
 
+

Detailed Description

+

Macro Definition Documentation

+ +

◆ UTIL_SEQ_DEFAULT

+ +
+
+ + + + +
#define UTIL_SEQ_DEFAULT   (~0U)
+
+ +

Default value used to start the scheduling.

+

This informs the sequencer that all tasks registered shall be considered

+
Note
This should be used in the application
+while(1)
+{
+ UTIL_SEQ_Run( UTIL_SEQ_DEFAULT );
+}
+
+ +

Definition at line 76 of file stm32_seq.h.

+ +
+
+ +

◆ UTIL_SEQ_RFU

+ +
+
+ + + + +
#define UTIL_SEQ_RFU   0
+
+ +

This provides a default value for unused parameter.

+ +

Definition at line 61 of file stm32_seq.h.

+ +
+
+
+
+ + + + diff --git a/Utilities/sequencer/html/group___s_e_q_u_e_n_c_e_r___exported__const.js b/Utilities/sequencer/html/group___s_e_q_u_e_n_c_e_r___exported__const.js new file mode 100644 index 0000000..0b0d42d --- /dev/null +++ b/Utilities/sequencer/html/group___s_e_q_u_e_n_c_e_r___exported__const.js @@ -0,0 +1,5 @@ +var group___s_e_q_u_e_n_c_e_r___exported__const = +[ + [ "UTIL_SEQ_DEFAULT", "group___s_e_q_u_e_n_c_e_r___exported__const.html#ga46541edfe05cb5082dec927f2bcf7b46", null ], + [ "UTIL_SEQ_RFU", "group___s_e_q_u_e_n_c_e_r___exported__const.html#ga44641e680786c27986945f4d0589c83a", null ] +]; \ No newline at end of file diff --git a/Utilities/sequencer/html/group___s_e_q_u_e_n_c_e_r___exported__function.html b/Utilities/sequencer/html/group___s_e_q_u_e_n_c_e_r___exported__function.html new file mode 100644 index 0000000..3d22bf7 --- /dev/null +++ b/Utilities/sequencer/html/group___s_e_q_u_e_n_c_e_r___exported__function.html @@ -0,0 +1,683 @@ + + + + + + + +STM32 Sequencer: SEQUENCER exported functions + + + + + + + + + + + + + +
+
+ + + + + + +
+
STM32 Sequencer +  v1.6.0 +
+
+
+ + + + + + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Functions
+
+
SEQUENCER exported functions
sequencer utilities
+
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

void UTIL_SEQ_Init (void)
 This function initializes the sequencer resources. More...
 
void UTIL_SEQ_DeInit (void)
 This function un-initializes the sequencer resources. More...
 
void UTIL_SEQ_Run (UTIL_SEQ_bm_t Mask_bm)
 This function requests the sequencer to execute all pending tasks using round robin mechanism. When no task are pending, it calls UTIL_SEQ_Idle(); This function should be called in a while loop in the application. More...
 
void UTIL_SEQ_RegTask (UTIL_SEQ_bm_t TaskId_bm, uint32_t Flags, void(*Task)(void))
 This function registers a task in the sequencer. More...
 
void UTIL_SEQ_SetTask (UTIL_SEQ_bm_t TaskId_bm, uint32_t Task_Prio)
 This function requests a task to be executed. More...
 
uint32_t UTIL_SEQ_IsSchedulableTask (UTIL_SEQ_bm_t TaskId_bm)
 This function checks if a task could be scheduled. More...
 
void UTIL_SEQ_PauseTask (UTIL_SEQ_bm_t TaskId_bm)
 This function prevents a task to be called by the sequencer even when set with UTIL_SEQ_SetTask() By default, all tasks are executed by the sequencer when set with UTIL_SEQ_SetTask() When a task is paused, it is moved out from the sequencer list. More...
 
uint32_t UTIL_SEQ_IsPauseTask (UTIL_SEQ_bm_t TaskId_bm)
 This function allows to know if the task has been put in pause. By default, all tasks are executed by the sequencer when set with UTIL_SEQ_SetTask() The exit of the pause shall be done by the function UTIL_SEQ_ResumeTask. More...
 
void UTIL_SEQ_ResumeTask (UTIL_SEQ_bm_t TaskId_bm)
 This function allows again a task to be called by the sequencer if set with UTIL_SEQ_SetTask() This is used in relation with UTIL_SEQ_PauseTask() More...
 
void UTIL_SEQ_SetEvt (UTIL_SEQ_bm_t EvtId_bm)
 This function sets an event that is waited with UTIL_SEQ_WaitEvt() More...
 
void UTIL_SEQ_ClrEvt (UTIL_SEQ_bm_t EvtId_bm)
 This function may be used to clear the event before calling UTIL_SEQ_WaitEvt() This API may be useful when the UTIL_SEQ_SetEvt() is called several time to notify the same event. Due to Software Architecture where the timings are hard to control, this may be an unwanted case. More...
 
void UTIL_SEQ_WaitEvt (UTIL_SEQ_bm_t EvtId_bm)
 This function waits for a specific event to be set. The sequencer loops UTIL_SEQ_EvtIdle() until the event is set When called recursively, it acts as a First in / Last out mechanism. The sequencer waits for the last event requested to be set even though one of the already requested event has been set. More...
 
UTIL_SEQ_bm_t UTIL_SEQ_IsEvtPend (void)
 This function returns whether the waited event is pending or not It is useful only when the UTIL_SEQ_EvtIdle() is overloaded by the application. In that case, when the low power mode needs to be executed, the application shall first check whether the waited event is pending or not. Both the event checking and the low power mode processing should be done in critical section. More...
 
__WEAK void UTIL_SEQ_EvtIdle (UTIL_SEQ_bm_t TaskId_bm, UTIL_SEQ_bm_t EvtWaited_bm)
 This function loops until the waited event is set. More...
 
__WEAK void UTIL_SEQ_Idle (void)
 This function is called by the sequencer in critical section (PRIMASK bit) when. More...
 
__WEAK void UTIL_SEQ_PreIdle (void)
 This function is called by the sequencer outside critical section just before calling UTIL_SEQ_Idle( ) UTIL_SEQ_PreIdle() is considered as the last task executed before calling UTIL_SEQ_Idle( ) In case a task or an event is set from an interrupt handler just after UTIL_SEQ_PreIdle() is called, UTIL_SEQ_Idle() will not be called. More...
 
__WEAK void UTIL_SEQ_PostIdle (void)
 This function is called by the sequencer outside critical section either. More...
 
+

Detailed Description

+

Function Documentation

+ +

◆ UTIL_SEQ_ClrEvt()

+ +
+
+ + + + + + + + +
void UTIL_SEQ_ClrEvt (UTIL_SEQ_bm_t EvtId_bm)
+
+ +

This function may be used to clear the event before calling UTIL_SEQ_WaitEvt() This API may be useful when the UTIL_SEQ_SetEvt() is called several time to notify the same event. Due to Software Architecture where the timings are hard to control, this may be an unwanted case.

+
Parameters
+ + +
EvtId_bmevent id bm It shall be a bit mapping where only 1 bit is set
+
+
+
Note
It may be called from an ISR.
+ +

Definition at line 407 of file stm32_seq.c.

+ +
+
+ +

◆ UTIL_SEQ_DeInit()

+ +
+
+ + + + + + + + +
void UTIL_SEQ_DeInit (void )
+
+ +

This function un-initializes the sequencer resources.

+
Note
It shall not be called from an ISR
+ +

Definition at line 199 of file stm32_seq.c.

+ +
+
+ +

◆ UTIL_SEQ_EvtIdle()

+ +
+
+ + + + + + + + + + + + + + + + + + +
void UTIL_SEQ_EvtIdle (UTIL_SEQ_bm_t TaskId_bm,
UTIL_SEQ_bm_t EvtWaited_bm 
)
+
+ +

This function loops until the waited event is set.

+
Parameters
+ + + +
TaskId_bmThe task id that is currently running. When task_id_bm = 0, it means UTIL_SEQ_WaitEvt( ) has been called outside a registered task (ie at startup before UTIL_SEQ_Run( ) has been called
EvtWaited_bmThe event id that is waited.
+
+
+
Note
When not implemented by the application, it calls UTIL_SEQ_Run(~TaskId_bm) which means the waited task is suspended until the waited event and the other tasks are running or the application enter low power mode. Else the user can redefine his own function for example call sequencer UTIL_SEQ_Run(0) to suspend all the task and let the sequencer enter the low power mode. It shall be called only by the sequencer.
+ +

Definition at line 477 of file stm32_seq.c.

+ +

References UTIL_SEQ_Run().

+ +
+
+ +

◆ UTIL_SEQ_Idle()

+ +
+
+ + + + + + + + +
void UTIL_SEQ_Idle (void )
+
+ +

This function is called by the sequencer in critical section (PRIMASK bit) when.

+
    +
  • there are no more tasks to be executed AND
    • +
  • there are no pending event or the pending event is still not set
    Note
    The application should enter low power mode in this function When this function is not implemented by the application, the sequencer keeps running a while loop (RUN MODE). It shall be called only by the sequencer.
    +
    • +
+ +

Definition at line 484 of file stm32_seq.c.

+ +
+
+ +

◆ UTIL_SEQ_Init()

+ +
+
+ + + + + + + + +
void UTIL_SEQ_Init (void )
+
+ +

This function initializes the sequencer resources.

+
Note
It shall not be called from an ISR.
+ +

Definition at line 182 of file stm32_seq.c.

+ +
+
+ +

◆ UTIL_SEQ_IsEvtPend()

+ +
+
+ + + + + + + + +
UTIL_SEQ_bm_t UTIL_SEQ_IsEvtPend (void )
+
+ +

This function returns whether the waited event is pending or not It is useful only when the UTIL_SEQ_EvtIdle() is overloaded by the application. In that case, when the low power mode needs to be executed, the application shall first check whether the waited event is pending or not. Both the event checking and the low power mode processing should be done in critical section.

+
Return values
+ + +
0when the waited event is not there or the evt_id when the waited event is pending
+
+
+
Note
It may be called from an ISR.
+ +

Definition at line 471 of file stm32_seq.c.

+ +
+
+ +

◆ UTIL_SEQ_IsPauseTask()

+ +
+
+ + + + + + + + +
uint32_t UTIL_SEQ_IsPauseTask (UTIL_SEQ_bm_t TaskId_bm)
+
+ +

This function allows to know if the task has been put in pause. By default, all tasks are executed by the sequencer when set with UTIL_SEQ_SetTask() The exit of the pause shall be done by the function UTIL_SEQ_ResumeTask.

+
Parameters
+ + +
TaskId_bmThe Id of the task It shall be (1<<task_id) where task_id is the number assigned when the task has been registered
+
+
+
Note
It may be called from an ISR.
+ +

Definition at line 374 of file stm32_seq.c.

+ +
+
+ +

◆ UTIL_SEQ_IsSchedulableTask()

+ +
+
+ + + + + + + + +
uint32_t UTIL_SEQ_IsSchedulableTask (UTIL_SEQ_bm_t TaskId_bm)
+
+ +

This function checks if a task could be scheduled.

+
Parameters
+ + +
TaskId_bmThe Id of the task It shall be (1<<task_id) where task_id is the number assigned when the task has been registered
+
+
+
Return values
+ + +
0if not 1 if true
+
+
+
Note
It may be called from an ISR.
+ +

Definition at line 349 of file stm32_seq.c.

+ +
+
+ +

◆ UTIL_SEQ_PauseTask()

+ +
+
+ + + + + + + + +
void UTIL_SEQ_PauseTask (UTIL_SEQ_bm_t TaskId_bm)
+
+ +

This function prevents a task to be called by the sequencer even when set with UTIL_SEQ_SetTask() By default, all tasks are executed by the sequencer when set with UTIL_SEQ_SetTask() When a task is paused, it is moved out from the sequencer list.

+
Parameters
+ + +
TaskId_bmThe Id of the task It shall be (1<<task_id) where task_id is the number assigned when the task has been registered
+
+
+
Note
It may be called from an ISR.
+ +

Definition at line 363 of file stm32_seq.c.

+ +
+
+ +

◆ UTIL_SEQ_PostIdle()

+ +
+
+ + + + + + + + +
void UTIL_SEQ_PostIdle (void )
+
+ +

This function is called by the sequencer outside critical section either.

+ +
Note
UTIL_SEQ_PostIdle() is always called if UTIL_SEQ_PreIdle() has been called and never called otherwise. It shall be called only by the sequencer.
+ +

Definition at line 497 of file stm32_seq.c.

+ +
+
+ +

◆ UTIL_SEQ_PreIdle()

+ +
+
+ + + + + + + + +
void UTIL_SEQ_PreIdle (void )
+
+ +

This function is called by the sequencer outside critical section just before calling UTIL_SEQ_Idle( ) UTIL_SEQ_PreIdle() is considered as the last task executed before calling UTIL_SEQ_Idle( ) In case a task or an event is set from an interrupt handler just after UTIL_SEQ_PreIdle() is called, UTIL_SEQ_Idle() will not be called.

+
Note
It shall be called only by the sequencer.
+ +

Definition at line 489 of file stm32_seq.c.

+ +
+
+ +

◆ UTIL_SEQ_RegTask()

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
void UTIL_SEQ_RegTask (UTIL_SEQ_bm_t TaskId_bm,
uint32_t Flags,
void(*)(void) Task 
)
+
+ +

This function registers a task in the sequencer.

+
Parameters
+ + + + +
TaskId_bmThe Id of the task
FlagsFlags are reserved param for future use
TaskReference of the function to be executed
+
+
+
Note
It may be called from an ISR.
+ +

Definition at line 325 of file stm32_seq.c.

+ +
+
+ +

◆ UTIL_SEQ_ResumeTask()

+ +
+
+ + + + + + + + +
void UTIL_SEQ_ResumeTask (UTIL_SEQ_bm_t TaskId_bm)
+
+ +

This function allows again a task to be called by the sequencer if set with UTIL_SEQ_SetTask() This is used in relation with UTIL_SEQ_PauseTask()

+
Parameters
+ + +
TaskId_bmThe Id of the task It shall be (1<<task_id) where task_id is the number assigned when the task has been registered
+
+
+
Note
It may be called from an ISR.
+ +

Definition at line 385 of file stm32_seq.c.

+ +
+
+ +

◆ UTIL_SEQ_Run()

+ +
+
+ + + + + + + + +
void UTIL_SEQ_Run (UTIL_SEQ_bm_t Mask_bm)
+
+ +

This function requests the sequencer to execute all pending tasks using round robin mechanism. When no task are pending, it calls UTIL_SEQ_Idle(); This function should be called in a while loop in the application.

+

This function can be nested. That is the reason why many variables that are used only in that function are declared static. Note: These variables could have been declared static in the function.

+
Parameters
+ + +
Mask_bmlist of task (bit mapping) that is be kept in the sequencer list.
+
+
+
Note
It shall not be called from an ISR.
+
+The construction of the task must take into account the fact that there is no counting / protection on the activation of the task. Thus, when the task is running, it must perform all the operations in progress programmed before its call or manage a reprogramming of the task.
+ +

Definition at line 209 of file stm32_seq.c.

+ +

Referenced by UTIL_SEQ_EvtIdle().

+ +
+
+ +

◆ UTIL_SEQ_SetEvt()

+ +
+
+ + + + + + + + +
void UTIL_SEQ_SetEvt (UTIL_SEQ_bm_t EvtId_bm)
+
+ +

This function sets an event that is waited with UTIL_SEQ_WaitEvt()

+
Parameters
+ + +
EvtId_bmevent id bit mask
+
+
+
Note
An event shall be a 32 bit mapping where only 1 bit is set It may be called from an ISR.
+ +

Definition at line 396 of file stm32_seq.c.

+ +
+
+ +

◆ UTIL_SEQ_SetTask()

+ +
+
+ + + + + + + + + + + + + + + + + + +
void UTIL_SEQ_SetTask (UTIL_SEQ_bm_t TaskId_bm,
uint32_t Task_Prio 
)
+
+ +

This function requests a task to be executed.

+
Parameters
+ + + +
TaskId_bmThe Id of the task It shall be (1<<task_id) where task_id is the number assigned when the task has been registered
Task_PrioThe priority of the task It shall a number from 0 (high priority) to 31 (low priority) The priority is checked each time the sequencer needs to select a new task to execute It does not permit to preempt a running task with lower priority
+
+
+
Note
It may be called from an ISR
+ +

Definition at line 337 of file stm32_seq.c.

+ +
+
+ +

◆ UTIL_SEQ_WaitEvt()

+ +
+
+ + + + + + + + +
void UTIL_SEQ_WaitEvt (UTIL_SEQ_bm_t EvtId_bm)
+
+ +

This function waits for a specific event to be set. The sequencer loops UTIL_SEQ_EvtIdle() until the event is set When called recursively, it acts as a First in / Last out mechanism. The sequencer waits for the last event requested to be set even though one of the already requested event has been set.

+
Parameters
+ + +
EvtId_bmevent id bit mask It shall be a bit mapping where only 1 bit is set
+
+
+
Note
It shall not be called from an ISR.
+
+The construction of the task must take into account the fact that there is no counting / protection on the event. Thus, when the task is running, it must perform all the operations in progress programmed before its call or manage a reprogramming of the task.
+ +

Definition at line 418 of file stm32_seq.c.

+ +
+
+
+
+ + + + diff --git a/Utilities/sequencer/html/group___s_e_q_u_e_n_c_e_r___exported__function.js b/Utilities/sequencer/html/group___s_e_q_u_e_n_c_e_r___exported__function.js new file mode 100644 index 0000000..6da5279 --- /dev/null +++ b/Utilities/sequencer/html/group___s_e_q_u_e_n_c_e_r___exported__function.js @@ -0,0 +1,20 @@ +var group___s_e_q_u_e_n_c_e_r___exported__function = +[ + [ "UTIL_SEQ_ClrEvt", "group___s_e_q_u_e_n_c_e_r___exported__function.html#ga2b48c77f677158e69ff072f7c05cded4", null ], + [ "UTIL_SEQ_DeInit", "group___s_e_q_u_e_n_c_e_r___exported__function.html#ga91cceef5931daa30c4ec3a6577c11106", null ], + [ "UTIL_SEQ_EvtIdle", "group___s_e_q_u_e_n_c_e_r___exported__function.html#ga6bd90dbfc7e3515391128d1ca1739c17", null ], + [ "UTIL_SEQ_Idle", "group___s_e_q_u_e_n_c_e_r___exported__function.html#ga5efb8394fc5244b650c8cc8f642e6271", null ], + [ "UTIL_SEQ_Init", "group___s_e_q_u_e_n_c_e_r___exported__function.html#gaef07a06c105da3570c971633460a8aa5", null ], + [ "UTIL_SEQ_IsEvtPend", "group___s_e_q_u_e_n_c_e_r___exported__function.html#ga8d6c2fd6aac8b833a25602ec4b8c5fc7", null ], + [ "UTIL_SEQ_IsPauseTask", "group___s_e_q_u_e_n_c_e_r___exported__function.html#gaa177da1e5c77c8430096356181d12b18", null ], + [ "UTIL_SEQ_IsSchedulableTask", "group___s_e_q_u_e_n_c_e_r___exported__function.html#ga58bf5ad581a43e749b60a811353af558", null ], + [ "UTIL_SEQ_PauseTask", "group___s_e_q_u_e_n_c_e_r___exported__function.html#gaad482af89f56e87da251f56d98674c02", null ], + [ "UTIL_SEQ_PostIdle", "group___s_e_q_u_e_n_c_e_r___exported__function.html#ga481b45c409e4d8180c64efdef67daa7f", null ], + [ "UTIL_SEQ_PreIdle", "group___s_e_q_u_e_n_c_e_r___exported__function.html#ga373387b03a48559d58eacb919f44a799", null ], + [ "UTIL_SEQ_RegTask", "group___s_e_q_u_e_n_c_e_r___exported__function.html#gacb5ddba0d11449d470c840d0bd961c14", null ], + [ "UTIL_SEQ_ResumeTask", "group___s_e_q_u_e_n_c_e_r___exported__function.html#ga66f6a7fbff82b6d397ca054bcf9350ec", null ], + [ "UTIL_SEQ_Run", "group___s_e_q_u_e_n_c_e_r___exported__function.html#gae047669fe53f205396460fdbd3a5d8f5", null ], + [ "UTIL_SEQ_SetEvt", "group___s_e_q_u_e_n_c_e_r___exported__function.html#ga20f607dcbe03ca04f5c56a47e3cc846c", null ], + [ "UTIL_SEQ_SetTask", "group___s_e_q_u_e_n_c_e_r___exported__function.html#ga66de990da4bde412751f15a7622a0da8", null ], + [ "UTIL_SEQ_WaitEvt", "group___s_e_q_u_e_n_c_e_r___exported__function.html#ga3546ca66266d5cc956741505318723a2", null ] +]; \ No newline at end of file diff --git a/Utilities/sequencer/html/group___s_e_q_u_e_n_c_e_r___exported__macro.html b/Utilities/sequencer/html/group___s_e_q_u_e_n_c_e_r___exported__macro.html new file mode 100644 index 0000000..772a330 --- /dev/null +++ b/Utilities/sequencer/html/group___s_e_q_u_e_n_c_e_r___exported__macro.html @@ -0,0 +1,200 @@ + + + + + + + +STM32 Sequencer: SEQUENCER exported macros + + + + + + + + + + + + + +
+
+ + + + + + +
+
STM32 Sequencer +  v1.6.0 +
+
+
+ + + + + + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
SEQUENCER exported macros
sequencer utilities
+
+
+ + + + + + + + +

+Macros

#define UTIL_SEQ_TaskParamDef(_FUNC_, _PARAM_VAL_)
 This macro can be used to define a task with one parameter. More...
 
#define UTIL_SEQ_TaskFunction(_FUNC_, _PARAM_VAL_)   SEQ_FUNC_##_FUNC_##_PARAM_VAL_
 This macro is used to retrieve the function name of the task. More...
 
+

Detailed Description

+

Macro Definition Documentation

+ +

◆ UTIL_SEQ_TaskFunction

+ +
+
+ + + + + + + + + + + + + + + + + + +
#define UTIL_SEQ_TaskFunction( _FUNC_,
 _PARAM_VAL_ 
)   SEQ_FUNC_##_FUNC_##_PARAM_VAL_
+
+ +

This macro is used to retrieve the function name of the task.

+ +

Definition at line 124 of file stm32_seq.h.

+ +
+
+ +

◆ UTIL_SEQ_TaskParamDef

+ +
+
+ + + + + + + + + + + + + + + + + + +
#define UTIL_SEQ_TaskParamDef( _FUNC_,
 _PARAM_VAL_ 
)
+
+Value:
static void SEQ_FUNC_##_FUNC_##_PARAM_VAL_(void); \
+
static void SEQ_FUNC_##_FUNC_##_PARAM_VAL_(void) \
+
{ \
+
static void *SEQ_PARAM_##_FUNC_ = (void*)&_PARAM_VAL_;\
+
_FUNC_(SEQ_PARAM_##_FUNC_); \
+
}
+
+

This macro can be used to define a task with one parameter.

+
Note
this is an example of using this macro 
    task prototype definition
+    void FUNCTION_NAME(void *Instance)
+    {
+        uint8_t _instance = *(uint8_t*) Instance;
+    }
+
+    task declaration in the application for two instances
+    const uint8_t instance1 = 1;
+    const uint8_t instance2 = 2;
+    UTIL_SEQ_TaskParamDef(FUNCTION_NAME, instance1)
+    UTIL_SEQ_TaskParamDef(FUNCTION_NAME, instance2)
+
+    task initialization
+    UTIL_SEQ_RegTask(1 << 1,  0, UTIL_SEQ_TaskFunction(FUNCTION_NAME,instance2));
+    UTIL_SEQ_RegTask(1 << 10, 0, UTIL_SEQ_TaskFunction(FUNCTION_NAME,instance3));
+
+    Then no change on the management of the task within the application, the instance being managed within the overloaded function
+
+ +

Definition at line 113 of file stm32_seq.h.

+ +
+
+
+
+ + + + diff --git a/Utilities/sequencer/html/group___s_e_q_u_e_n_c_e_r___exported__macro.js b/Utilities/sequencer/html/group___s_e_q_u_e_n_c_e_r___exported__macro.js new file mode 100644 index 0000000..7ebe1a4 --- /dev/null +++ b/Utilities/sequencer/html/group___s_e_q_u_e_n_c_e_r___exported__macro.js @@ -0,0 +1,5 @@ +var group___s_e_q_u_e_n_c_e_r___exported__macro = +[ + [ "UTIL_SEQ_TaskFunction", "group___s_e_q_u_e_n_c_e_r___exported__macro.html#gac4b0290fac7278810aa24b9be4574da1", null ], + [ "UTIL_SEQ_TaskParamDef", "group___s_e_q_u_e_n_c_e_r___exported__macro.html#ga99985a546d3297b5fd8ace7f5f045c14", null ] +]; \ No newline at end of file diff --git a/Utilities/sequencer/html/group___s_e_q_u_e_n_c_e_r___exported__type.html b/Utilities/sequencer/html/group___s_e_q_u_e_n_c_e_r___exported__type.html new file mode 100644 index 0000000..f010e87 --- /dev/null +++ b/Utilities/sequencer/html/group___s_e_q_u_e_n_c_e_r___exported__type.html @@ -0,0 +1,127 @@ + + + + + + + +STM32 Sequencer: SEQUENCER exported types + + + + + + + + + + + + + +
+
+ + + + + + +
+
STM32 Sequencer +  v1.6.0 +
+
+
+ + + + + + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Typedefs
+
+
SEQUENCER exported types
sequencer utilities
+
+
+ + + + + +

+Typedefs

typedef uint32_t UTIL_SEQ_bm_t
 bit mapping of the task. this value is used to represent a list of task (each corresponds to a task). More...
 
+

Detailed Description

+

Typedef Documentation

+ +

◆ UTIL_SEQ_bm_t

+ +
+
+ + + + +
typedef uint32_t UTIL_SEQ_bm_t
+
+ +

bit mapping of the task. this value is used to represent a list of task (each corresponds to a task).

+ +

Definition at line 45 of file stm32_seq.h.

+ +
+
+
+
+ + + + diff --git a/Utilities/sequencer/html/group___s_e_q_u_e_n_c_e_r___exported__type.js b/Utilities/sequencer/html/group___s_e_q_u_e_n_c_e_r___exported__type.js new file mode 100644 index 0000000..a440427 --- /dev/null +++ b/Utilities/sequencer/html/group___s_e_q_u_e_n_c_e_r___exported__type.js @@ -0,0 +1,4 @@ +var group___s_e_q_u_e_n_c_e_r___exported__type = +[ + [ "UTIL_SEQ_bm_t", "group___s_e_q_u_e_n_c_e_r___exported__type.html#gaf1d37385aa3a7ce76c48447ba7dd5707", null ] +]; \ No newline at end of file diff --git a/Utilities/sequencer/html/group___s_e_q_u_e_n_c_e_r___private__define.html b/Utilities/sequencer/html/group___s_e_q_u_e_n_c_e_r___private__define.html new file mode 100644 index 0000000..065a0d2 --- /dev/null +++ b/Utilities/sequencer/html/group___s_e_q_u_e_n_c_e_r___private__define.html @@ -0,0 +1,302 @@ + + + + + + + +STM32 Sequencer: SEQUENCER private defines + + + + + + + + + + + + + +
+
+ + + + + + +
+
STM32 Sequencer +  v1.6.0 +
+
+
+ + + + + + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
SEQUENCER private defines
sequencer utilities
+
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define UTIL_SEQ_ENTER_CRITICAL_SECTION_IDLE()   UTIL_SEQ_ENTER_CRITICAL_SECTION( )
 macro used to enter the critical section before calling the IDLE function More...
 
#define UTIL_SEQ_EXIT_CRITICAL_SECTION_IDLE()   UTIL_SEQ_EXIT_CRITICAL_SECTION( )
 macro used to exit the critical section when exiting the IDLE function More...
 
#define UTIL_SEQ_NOTASKRUNNING   (0xFFFFFFFFU)
 define to represent no task running More...
 
#define UTIL_SEQ_NO_BIT_SET   (0U)
 define to represent no bit set inside uint32_t mapping More...
 
#define UTIL_SEQ_ALL_BIT_SET   (~0U)
 define to represent all bits set inside uint32_t mapping More...
 
#define UTIL_SEQ_CONF_TASK_NBR   (32)
 default number of task is default 32 (maximum), can be reduced by redefining in utilities_conf.h More...
 
#define UTIL_SEQ_CONF_PRIO_NBR   (2)
 default value of priority number. More...
 
#define UTIL_SEQ_MEMSET8(dest, value, size)   UTILS_MEMSET8( dest, value, size )
 default memset function. More...
 
+

Detailed Description

+

Macro Definition Documentation

+ +

◆ UTIL_SEQ_ALL_BIT_SET

+ +
+
+ + + + +
#define UTIL_SEQ_ALL_BIT_SET   (~0U)
+
+ +

define to represent all bits set inside uint32_t mapping

+ +

Definition at line 86 of file stm32_seq.c.

+ +
+
+ +

◆ UTIL_SEQ_CONF_PRIO_NBR

+ +
+
+ + + + +
#define UTIL_SEQ_CONF_PRIO_NBR   (2)
+
+ +

default value of priority number.

+ +

Definition at line 103 of file stm32_seq.c.

+ +
+
+ +

◆ UTIL_SEQ_CONF_TASK_NBR

+ +
+
+ + + + +
#define UTIL_SEQ_CONF_TASK_NBR   (32)
+
+ +

default number of task is default 32 (maximum), can be reduced by redefining in utilities_conf.h

+ +

Definition at line 92 of file stm32_seq.c.

+ +
+
+ +

◆ UTIL_SEQ_ENTER_CRITICAL_SECTION_IDLE

+ +
+
+ + + + + + + +
#define UTIL_SEQ_ENTER_CRITICAL_SECTION_IDLE()   UTIL_SEQ_ENTER_CRITICAL_SECTION( )
+
+ +

macro used to enter the critical section before calling the IDLE function

+
Note
in a basic configuration shall be identical to the macro UTIL_SEQ_ENTER_CRITICAL_SECTION. The redefinition of this macro will allow to perform specific operation
+ +

Definition at line 61 of file stm32_seq.c.

+ +
+
+ +

◆ UTIL_SEQ_EXIT_CRITICAL_SECTION_IDLE

+ +
+
+ + + + + + + +
#define UTIL_SEQ_EXIT_CRITICAL_SECTION_IDLE()   UTIL_SEQ_EXIT_CRITICAL_SECTION( )
+
+ +

macro used to exit the critical section when exiting the IDLE function

+
Note
the behavior of the macro shall be symmetrical with the macro UTIL_SEQ_ENTER_CRITICAL_SECTION_IDLE
+ +

Definition at line 70 of file stm32_seq.c.

+ +
+
+ +

◆ UTIL_SEQ_MEMSET8

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
#define UTIL_SEQ_MEMSET8( dest,
 value,
 size 
)   UTILS_MEMSET8( dest, value, size )
+
+ +

default memset function.

+ +

Definition at line 110 of file stm32_seq.c.

+ +
+
+ +

◆ UTIL_SEQ_NO_BIT_SET

+ +
+
+ + + + +
#define UTIL_SEQ_NO_BIT_SET   (0U)
+
+ +

define to represent no bit set inside uint32_t mapping

+ +

Definition at line 81 of file stm32_seq.c.

+ +
+
+ +

◆ UTIL_SEQ_NOTASKRUNNING

+ +
+
+ + + + +
#define UTIL_SEQ_NOTASKRUNNING   (0xFFFFFFFFU)
+
+ +

define to represent no task running

+ +

Definition at line 76 of file stm32_seq.c.

+ +
+
+
+
+ + + + diff --git a/Utilities/sequencer/html/group___s_e_q_u_e_n_c_e_r___private__define.js b/Utilities/sequencer/html/group___s_e_q_u_e_n_c_e_r___private__define.js new file mode 100644 index 0000000..d2662b9 --- /dev/null +++ b/Utilities/sequencer/html/group___s_e_q_u_e_n_c_e_r___private__define.js @@ -0,0 +1,11 @@ +var group___s_e_q_u_e_n_c_e_r___private__define = +[ + [ "UTIL_SEQ_ALL_BIT_SET", "group___s_e_q_u_e_n_c_e_r___private__define.html#ga24e4c1a2fd61c0cbda16ba7f42f1703a", null ], + [ "UTIL_SEQ_CONF_PRIO_NBR", "group___s_e_q_u_e_n_c_e_r___private__define.html#ga13e13f6ac2442ffb667502a9f35df865", null ], + [ "UTIL_SEQ_CONF_TASK_NBR", "group___s_e_q_u_e_n_c_e_r___private__define.html#gaaf974b4a940fc6a921b3a76344e5c7ed", null ], + [ "UTIL_SEQ_ENTER_CRITICAL_SECTION_IDLE", "group___s_e_q_u_e_n_c_e_r___private__define.html#ga7af4785dcb8ef602f75b2d8f423010c1", null ], + [ "UTIL_SEQ_EXIT_CRITICAL_SECTION_IDLE", "group___s_e_q_u_e_n_c_e_r___private__define.html#ga2dcda5eb256d445147b385a8374cc658", null ], + [ "UTIL_SEQ_MEMSET8", "group___s_e_q_u_e_n_c_e_r___private__define.html#gad3b4f5f14f4f512725984e6da759871c", null ], + [ "UTIL_SEQ_NO_BIT_SET", "group___s_e_q_u_e_n_c_e_r___private__define.html#gad03df74638c0f274fa22474f034384bf", null ], + [ "UTIL_SEQ_NOTASKRUNNING", "group___s_e_q_u_e_n_c_e_r___private__define.html#ga9d782cdb4f3654c8238e9dd3adbabf16", null ] +]; \ No newline at end of file diff --git a/Utilities/sequencer/html/group___s_e_q_u_e_n_c_e_r___private__function.html b/Utilities/sequencer/html/group___s_e_q_u_e_n_c_e_r___private__function.html new file mode 100644 index 0000000..ea5d365 --- /dev/null +++ b/Utilities/sequencer/html/group___s_e_q_u_e_n_c_e_r___private__function.html @@ -0,0 +1,143 @@ + + + + + + + +STM32 Sequencer: SEQUENCER private functions + + + + + + + + + + + + + +
+
+ + + + + + +
+
STM32 Sequencer +  v1.6.0 +
+
+
+ + + + + + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Functions
+
+
SEQUENCER private functions
sequencer utilities
+
+
+ + + + + +

+Functions

uint8_t SEQ_BitPosition (uint32_t Value)
 return the position of the first bit set to 1 More...
 
+

Detailed Description

+

Function Documentation

+ +

◆ SEQ_BitPosition()

+ +
+
+ + + + + + + + +
uint8_t SEQ_BitPosition (uint32_t Value)
+
+ +

return the position of the first bit set to 1

+
Parameters
+ + +
Value32 bit value
+
+
+
Return values
+ + +
bitposition
+
+
+ +

Definition at line 519 of file stm32_seq.c.

+ +
+
+
+
+ + + + diff --git a/Utilities/sequencer/html/group___s_e_q_u_e_n_c_e_r___private__function.js b/Utilities/sequencer/html/group___s_e_q_u_e_n_c_e_r___private__function.js new file mode 100644 index 0000000..352d67d --- /dev/null +++ b/Utilities/sequencer/html/group___s_e_q_u_e_n_c_e_r___private__function.js @@ -0,0 +1,4 @@ +var group___s_e_q_u_e_n_c_e_r___private__function = +[ + [ "SEQ_BitPosition", "group___s_e_q_u_e_n_c_e_r___private__function.html#ga7dcde6efa35f7c100af9bf4117a4bf12", null ] +]; \ No newline at end of file diff --git a/Utilities/sequencer/html/group___s_e_q_u_e_n_c_e_r___private__type.html b/Utilities/sequencer/html/group___s_e_q_u_e_n_c_e_r___private__type.html new file mode 100644 index 0000000..6eeb38b --- /dev/null +++ b/Utilities/sequencer/html/group___s_e_q_u_e_n_c_e_r___private__type.html @@ -0,0 +1,108 @@ + + + + + + + +STM32 Sequencer: SEQUENCER private type + + + + + + + + + + + + + +
+
+ + + + + + +
+
STM32 Sequencer +  v1.6.0 +
+
+
+ + + + + + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Data Structures
+
+
SEQUENCER private type
sequencer utilities
+
+
+ + + + + +

+Data Structures

struct  UTIL_SEQ_Priority_t
 structure used to manage task scheduling More...
 
+

Detailed Description

+
+
+ + + + diff --git a/Utilities/sequencer/html/group___s_e_q_u_e_n_c_e_r___private__type.js b/Utilities/sequencer/html/group___s_e_q_u_e_n_c_e_r___private__type.js new file mode 100644 index 0000000..24462ce --- /dev/null +++ b/Utilities/sequencer/html/group___s_e_q_u_e_n_c_e_r___private__type.js @@ -0,0 +1,7 @@ +var group___s_e_q_u_e_n_c_e_r___private__type = +[ + [ "UTIL_SEQ_Priority_t", "struct_u_t_i_l___s_e_q___priority__t.html", [ + [ "priority", "struct_u_t_i_l___s_e_q___priority__t.html#a59563315cdb7b76c8a482160851cac3f", null ], + [ "round_robin", "struct_u_t_i_l___s_e_q___priority__t.html#a10895a689ca10b69554ba4a822329f54", null ] + ] ] +]; \ No newline at end of file diff --git a/Utilities/sequencer/html/group___s_e_q_u_e_n_c_e_r___private__varaible.html b/Utilities/sequencer/html/group___s_e_q_u_e_n_c_e_r___private__varaible.html new file mode 100644 index 0000000..83bcf02 --- /dev/null +++ b/Utilities/sequencer/html/group___s_e_q_u_e_n_c_e_r___private__varaible.html @@ -0,0 +1,99 @@ + + + + + + + +STM32 Sequencer: SEQUENCER private variables + + + + + + + + + + + + + +
+
+ + + + + + +
+
STM32 Sequencer +  v1.6.0 +
+
+
+ + + + + + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
SEQUENCER private variables
sequencer utilities
+
+
+

Detailed Description

+
+
+ + + + diff --git a/Utilities/sequencer/html/group___s_e_q_u_e_n_c_e_r___private__varaible.js b/Utilities/sequencer/html/group___s_e_q_u_e_n_c_e_r___private__varaible.js new file mode 100644 index 0000000..3020c3a --- /dev/null +++ b/Utilities/sequencer/html/group___s_e_q_u_e_n_c_e_r___private__varaible.js @@ -0,0 +1,11 @@ +var group___s_e_q_u_e_n_c_e_r___private__varaible = +[ + [ "CurrentTaskIdx", "group___s_e_q_u_e_n_c_e_r___private__varaible.html#ga2d00e58496abe08f37dfaa2679226c35", null ], + [ "EvtSet", "group___s_e_q_u_e_n_c_e_r___private__varaible.html#ga4c0c4cdb1e59756fac982daba7f66e8c", null ], + [ "EvtWaited", "group___s_e_q_u_e_n_c_e_r___private__varaible.html#ga2993ab71529fc7f716b41b74c1475889", null ], + [ "SuperMask", "group___s_e_q_u_e_n_c_e_r___private__varaible.html#ga0c890a69236d5f7438c51df3cf20c480", null ], + [ "TaskCb", "group___s_e_q_u_e_n_c_e_r___private__varaible.html#ga893dc0e5ab501c52067b7eda416249aa", null ], + [ "TaskMask", "group___s_e_q_u_e_n_c_e_r___private__varaible.html#ga5ac59b09d15935337ee4a154db1cde25", null ], + [ "TaskPrio", "group___s_e_q_u_e_n_c_e_r___private__varaible.html#ga1a1b2fb52456411a929b68a015a66635", null ], + [ "TaskSet", "group___s_e_q_u_e_n_c_e_r___private__varaible.html#gacf3f1ab2184d36d2cb57326539e3563b", null ] +]; \ No newline at end of file diff --git a/Utilities/sequencer/html/index.html b/Utilities/sequencer/html/index.html new file mode 100644 index 0000000..fad4bdc --- /dev/null +++ b/Utilities/sequencer/html/index.html @@ -0,0 +1,98 @@ + + + + + + + +STM32 Sequencer: Main Page + + + + + + + + + + + + + +
+
+ + + + + + +
+
STM32 Sequencer +  v1.6.0 +
+
+
+ + + + + + + +
+
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+ +
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+ +
+ +
+
+
STM32 Sequencer Documentation
+
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+
+
+ + + + diff --git a/Utilities/sequencer/html/jquery.js b/Utilities/sequencer/html/jquery.js new file mode 100644 index 0000000..103c32d --- /dev/null +++ b/Utilities/sequencer/html/jquery.js @@ -0,0 +1,35 @@ +/*! jQuery v3.4.1 | (c) JS Foundation and other contributors | jquery.org/license */ +!function(e,t){"use strict";"object"==typeof module&&"object"==typeof module.exports?module.exports=e.document?t(e,!0):function(e){if(!e.document)throw new Error("jQuery requires a window with a document");return t(e)}:t(e)}("undefined"!=typeof window?window:this,function(C,e){"use strict";var t=[],E=C.document,r=Object.getPrototypeOf,s=t.slice,g=t.concat,u=t.push,i=t.indexOf,n={},o=n.toString,v=n.hasOwnProperty,a=v.toString,l=a.call(Object),y={},m=function(e){return"function"==typeof e&&"number"!=typeof e.nodeType},x=function(e){return null!=e&&e===e.window},c={type:!0,src:!0,nonce:!0,noModule:!0};function b(e,t,n){var r,i,o=(n=n||E).createElement("script");if(o.text=e,t)for(r in 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$.SmartMenus=function(t,e){this.$root=$(t),this.opts=e,this.rootId="",this.accessIdPrefix="",this.$subArrow=null,this.activatedItems=[],this.visibleSubMenus=[],this.showTimeout=0,this.hideTimeout=0,this.scrollTimeout=0,this.clickActivated=!1,this.focusActivated=!1,this.zIndexInc=0,this.idInc=0,this.$firstLink=null,this.$firstSub=null,this.disabled=!1,this.$disableOverlay=null,this.$touchScrollingSub=null,this.cssTransforms3d="perspective"in t.style||"webkitPerspective"in t.style,this.wasCollapsible=!1,this.init()},$.extend($.SmartMenus,{hideAll:function(){$.each(menuTrees,function(){this.menuHideAll()})},destroy:function(){for(;menuTrees.length;)menuTrees[0].destroy();initMouseDetection(!0)},prototype:{init:function(t){var e=this;if(!t){menuTrees.push(this),this.rootId=((new Date).getTime()+Math.random()+"").replace(/\D/g,""),this.accessIdPrefix="sm-"+this.rootId+"-",this.$root.hasClass("sm-rtl")&&(this.opts.rightToLeftSubMenus=!0);var i=".smartmenus";this.$root.data("smartmenus",this).attr("data-smartmenus-id",this.rootId).dataSM("level",1).on(getEventsNS({"mouseover focusin":$.proxy(this.rootOver,this),"mouseout focusout":$.proxy(this.rootOut,this),keydown:$.proxy(this.rootKeyDown,this)},i)).on(getEventsNS({mouseenter:$.proxy(this.itemEnter,this),mouseleave:$.proxy(this.itemLeave,this),mousedown:$.proxy(this.itemDown,this),focus:$.proxy(this.itemFocus,this),blur:$.proxy(this.itemBlur,this),click:$.proxy(this.itemClick,this)},i),"a"),i+=this.rootId,this.opts.hideOnClick&&$(document).on(getEventsNS({touchstart:$.proxy(this.docTouchStart,this),touchmove:$.proxy(this.docTouchMove,this),touchend:$.proxy(this.docTouchEnd,this),click:$.proxy(this.docClick,this)},i)),$(window).on(getEventsNS({"resize orientationchange":$.proxy(this.winResize,this)},i)),this.opts.subIndicators&&(this.$subArrow=$("").addClass("sub-arrow"),this.opts.subIndicatorsText&&this.$subArrow.html(this.opts.subIndicatorsText)),initMouseDetection()}if(this.$firstSub=this.$root.find("ul").each(function(){e.menuInit($(this))}).eq(0),this.$firstLink=this.$root.find("a").eq(0),this.opts.markCurrentItem){var s=/(index|default)\.[^#\?\/]*/i,o=/#.*/,a=window.location.href.replace(s,""),n=a.replace(o,"");this.$root.find("a").each(function(){var t=this.href.replace(s,""),i=$(this);(t==a||t==n)&&(i.addClass("current"),e.opts.markCurrentTree&&i.parentsUntil("[data-smartmenus-id]","ul").each(function(){$(this).dataSM("parent-a").addClass("current")}))})}this.wasCollapsible=this.isCollapsible()},destroy:function(t){if(!t){var e=".smartmenus";this.$root.removeData("smartmenus").removeAttr("data-smartmenus-id").removeDataSM("level").off(e),e+=this.rootId,$(document).off(e),$(window).off(e),this.opts.subIndicators&&(this.$subArrow=null)}this.menuHideAll();var i=this;this.$root.find("ul").each(function(){var t=$(this);t.dataSM("scroll-arrows")&&t.dataSM("scroll-arrows").remove(),t.dataSM("shown-before")&&((i.opts.subMenusMinWidth||i.opts.subMenusMaxWidth)&&t.css({width:"",minWidth:"",maxWidth:""}).removeClass("sm-nowrap"),t.dataSM("scroll-arrows")&&t.dataSM("scroll-arrows").remove(),t.css({zIndex:"",top:"",left:"",marginLeft:"",marginTop:"",display:""})),0==(t.attr("id")||"").indexOf(i.accessIdPrefix)&&t.removeAttr("id")}).removeDataSM("in-mega").removeDataSM("shown-before").removeDataSM("scroll-arrows").removeDataSM("parent-a").removeDataSM("level").removeDataSM("beforefirstshowfired").removeAttr("role").removeAttr("aria-hidden").removeAttr("aria-labelledby").removeAttr("aria-expanded"),this.$root.find("a.has-submenu").each(function(){var t=$(this);0==t.attr("id").indexOf(i.accessIdPrefix)&&t.removeAttr("id")}).removeClass("has-submenu").removeDataSM("sub").removeAttr("aria-haspopup").removeAttr("aria-controls").removeAttr("aria-expanded").closest("li").removeDataSM("sub"),this.opts.subIndicators&&this.$root.find("span.sub-arrow").remove(),this.opts.markCurrentItem&&this.$root.find("a.current").removeClass("current"),t||(this.$root=null,this.$firstLink=null,this.$firstSub=null,this.$disableOverlay&&(this.$disableOverlay.remove(),this.$disableOverlay=null),menuTrees.splice($.inArray(this,menuTrees),1))},disable:function(t){if(!this.disabled){if(this.menuHideAll(),!t&&!this.opts.isPopup&&this.$root.is(":visible")){var e=this.$root.offset();this.$disableOverlay=$('
').css({position:"absolute",top:e.top,left:e.left,width:this.$root.outerWidth(),height:this.$root.outerHeight(),zIndex:this.getStartZIndex(!0),opacity:0}).appendTo(document.body)}this.disabled=!0}},docClick:function(t){return this.$touchScrollingSub?(this.$touchScrollingSub=null,void 0):((this.visibleSubMenus.length&&!$.contains(this.$root[0],t.target)||$(t.target).closest("a").length)&&this.menuHideAll(),void 0)},docTouchEnd:function(){if(this.lastTouch){if(!(!this.visibleSubMenus.length||void 0!==this.lastTouch.x2&&this.lastTouch.x1!=this.lastTouch.x2||void 0!==this.lastTouch.y2&&this.lastTouch.y1!=this.lastTouch.y2||this.lastTouch.target&&$.contains(this.$root[0],this.lastTouch.target))){this.hideTimeout&&(clearTimeout(this.hideTimeout),this.hideTimeout=0);var t=this;this.hideTimeout=setTimeout(function(){t.menuHideAll()},350)}this.lastTouch=null}},docTouchMove:function(t){if(this.lastTouch){var e=t.originalEvent.touches[0];this.lastTouch.x2=e.pageX,this.lastTouch.y2=e.pageY}},docTouchStart:function(t){var e=t.originalEvent.touches[0];this.lastTouch={x1:e.pageX,y1:e.pageY,target:e.target}},enable:function(){this.disabled&&(this.$disableOverlay&&(this.$disableOverlay.remove(),this.$disableOverlay=null),this.disabled=!1)},getClosestMenu:function(t){for(var e=$(t).closest("ul");e.dataSM("in-mega");)e=e.parent().closest("ul");return e[0]||null},getHeight:function(t){return this.getOffset(t,!0)},getOffset:function(t,e){var i;"none"==t.css("display")&&(i={position:t[0].style.position,visibility:t[0].style.visibility},t.css({position:"absolute",visibility:"hidden"}).show());var s=t[0].getBoundingClientRect&&t[0].getBoundingClientRect(),o=s&&(e?s.height||s.bottom-s.top:s.width||s.right-s.left);return o||0===o||(o=e?t[0].offsetHeight:t[0].offsetWidth),i&&t.hide().css(i),o},getStartZIndex:function(t){var e=parseInt(this[t?"$root":"$firstSub"].css("z-index"));return!t&&isNaN(e)&&(e=parseInt(this.$root.css("z-index"))),isNaN(e)?1:e},getTouchPoint:function(t){return t.touches&&t.touches[0]||t.changedTouches&&t.changedTouches[0]||t},getViewport:function(t){var e=t?"Height":"Width",i=document.documentElement["client"+e],s=window["inner"+e];return s&&(i=Math.min(i,s)),i},getViewportHeight:function(){return this.getViewport(!0)},getViewportWidth:function(){return this.getViewport()},getWidth:function(t){return this.getOffset(t)},handleEvents:function(){return!this.disabled&&this.isCSSOn()},handleItemEvents:function(t){return this.handleEvents()&&!this.isLinkInMegaMenu(t)},isCollapsible:function(){return"static"==this.$firstSub.css("position")},isCSSOn:function(){return"inline"!=this.$firstLink.css("display")},isFixed:function(){var t="fixed"==this.$root.css("position");return t||this.$root.parentsUntil("body").each(function(){return"fixed"==$(this).css("position")?(t=!0,!1):void 0}),t},isLinkInMegaMenu:function(t){return $(this.getClosestMenu(t[0])).hasClass("mega-menu")},isTouchMode:function(){return!mouse||this.opts.noMouseOver||this.isCollapsible()},itemActivate:function(t,e){var i=t.closest("ul"),s=i.dataSM("level");if(s>1&&(!this.activatedItems[s-2]||this.activatedItems[s-2][0]!=i.dataSM("parent-a")[0])){var o=this;$(i.parentsUntil("[data-smartmenus-id]","ul").get().reverse()).add(i).each(function(){o.itemActivate($(this).dataSM("parent-a"))})}if((!this.isCollapsible()||e)&&this.menuHideSubMenus(this.activatedItems[s-1]&&this.activatedItems[s-1][0]==t[0]?s:s-1),this.activatedItems[s-1]=t,this.$root.triggerHandler("activate.smapi",t[0])!==!1){var a=t.dataSM("sub");a&&(this.isTouchMode()||!this.opts.showOnClick||this.clickActivated)&&this.menuShow(a)}},itemBlur:function(t){var e=$(t.currentTarget);this.handleItemEvents(e)&&this.$root.triggerHandler("blur.smapi",e[0])},itemClick:function(t){var e=$(t.currentTarget);if(this.handleItemEvents(e)){if(this.$touchScrollingSub&&this.$touchScrollingSub[0]==e.closest("ul")[0])return this.$touchScrollingSub=null,t.stopPropagation(),!1;if(this.$root.triggerHandler("click.smapi",e[0])===!1)return!1;var i=$(t.target).is(".sub-arrow"),s=e.dataSM("sub"),o=s?2==s.dataSM("level"):!1,a=this.isCollapsible(),n=/toggle$/.test(this.opts.collapsibleBehavior),r=/link$/.test(this.opts.collapsibleBehavior),h=/^accordion/.test(this.opts.collapsibleBehavior);if(s&&!s.is(":visible")){if((!r||!a||i)&&(this.opts.showOnClick&&o&&(this.clickActivated=!0),this.itemActivate(e,h),s.is(":visible")))return this.focusActivated=!0,!1}else if(a&&(n||i))return this.itemActivate(e,h),this.menuHide(s),n&&(this.focusActivated=!1),!1;return this.opts.showOnClick&&o||e.hasClass("disabled")||this.$root.triggerHandler("select.smapi",e[0])===!1?!1:void 0}},itemDown:function(t){var e=$(t.currentTarget);this.handleItemEvents(e)&&e.dataSM("mousedown",!0)},itemEnter:function(t){var e=$(t.currentTarget);if(this.handleItemEvents(e)){if(!this.isTouchMode()){this.showTimeout&&(clearTimeout(this.showTimeout),this.showTimeout=0);var i=this;this.showTimeout=setTimeout(function(){i.itemActivate(e)},this.opts.showOnClick&&1==e.closest("ul").dataSM("level")?1:this.opts.showTimeout)}this.$root.triggerHandler("mouseenter.smapi",e[0])}},itemFocus:function(t){var e=$(t.currentTarget);this.handleItemEvents(e)&&(!this.focusActivated||this.isTouchMode()&&e.dataSM("mousedown")||this.activatedItems.length&&this.activatedItems[this.activatedItems.length-1][0]==e[0]||this.itemActivate(e,!0),this.$root.triggerHandler("focus.smapi",e[0]))},itemLeave:function(t){var e=$(t.currentTarget);this.handleItemEvents(e)&&(this.isTouchMode()||(e[0].blur(),this.showTimeout&&(clearTimeout(this.showTimeout),this.showTimeout=0)),e.removeDataSM("mousedown"),this.$root.triggerHandler("mouseleave.smapi",e[0]))},menuHide:function(t){if(this.$root.triggerHandler("beforehide.smapi",t[0])!==!1&&(canAnimate&&t.stop(!0,!0),"none"!=t.css("display"))){var e=function(){t.css("z-index","")};this.isCollapsible()?canAnimate&&this.opts.collapsibleHideFunction?this.opts.collapsibleHideFunction.call(this,t,e):t.hide(this.opts.collapsibleHideDuration,e):canAnimate&&this.opts.hideFunction?this.opts.hideFunction.call(this,t,e):t.hide(this.opts.hideDuration,e),t.dataSM("scroll")&&(this.menuScrollStop(t),t.css({"touch-action":"","-ms-touch-action":"","-webkit-transform":"",transform:""}).off(".smartmenus_scroll").removeDataSM("scroll").dataSM("scroll-arrows").hide()),t.dataSM("parent-a").removeClass("highlighted").attr("aria-expanded","false"),t.attr({"aria-expanded":"false","aria-hidden":"true"});var i=t.dataSM("level");this.activatedItems.splice(i-1,1),this.visibleSubMenus.splice($.inArray(t,this.visibleSubMenus),1),this.$root.triggerHandler("hide.smapi",t[0])}},menuHideAll:function(){this.showTimeout&&(clearTimeout(this.showTimeout),this.showTimeout=0);for(var t=this.opts.isPopup?1:0,e=this.visibleSubMenus.length-1;e>=t;e--)this.menuHide(this.visibleSubMenus[e]);this.opts.isPopup&&(canAnimate&&this.$root.stop(!0,!0),this.$root.is(":visible")&&(canAnimate&&this.opts.hideFunction?this.opts.hideFunction.call(this,this.$root):this.$root.hide(this.opts.hideDuration))),this.activatedItems=[],this.visibleSubMenus=[],this.clickActivated=!1,this.focusActivated=!1,this.zIndexInc=0,this.$root.triggerHandler("hideAll.smapi")},menuHideSubMenus:function(t){for(var e=this.activatedItems.length-1;e>=t;e--){var i=this.activatedItems[e].dataSM("sub");i&&this.menuHide(i)}},menuInit:function(t){if(!t.dataSM("in-mega")){t.hasClass("mega-menu")&&t.find("ul").dataSM("in-mega",!0);for(var e=2,i=t[0];(i=i.parentNode.parentNode)!=this.$root[0];)e++;var s=t.prevAll("a").eq(-1);s.length||(s=t.prevAll().find("a").eq(-1)),s.addClass("has-submenu").dataSM("sub",t),t.dataSM("parent-a",s).dataSM("level",e).parent().dataSM("sub",t);var o=s.attr("id")||this.accessIdPrefix+ ++this.idInc,a=t.attr("id")||this.accessIdPrefix+ ++this.idInc;s.attr({id:o,"aria-haspopup":"true","aria-controls":a,"aria-expanded":"false"}),t.attr({id:a,role:"group","aria-hidden":"true","aria-labelledby":o,"aria-expanded":"false"}),this.opts.subIndicators&&s[this.opts.subIndicatorsPos](this.$subArrow.clone())}},menuPosition:function(t){var e,i,s=t.dataSM("parent-a"),o=s.closest("li"),a=o.parent(),n=t.dataSM("level"),r=this.getWidth(t),h=this.getHeight(t),u=s.offset(),l=u.left,c=u.top,d=this.getWidth(s),m=this.getHeight(s),p=$(window),f=p.scrollLeft(),v=p.scrollTop(),b=this.getViewportWidth(),S=this.getViewportHeight(),g=a.parent().is("[data-sm-horizontal-sub]")||2==n&&!a.hasClass("sm-vertical"),M=this.opts.rightToLeftSubMenus&&!o.is("[data-sm-reverse]")||!this.opts.rightToLeftSubMenus&&o.is("[data-sm-reverse]"),w=2==n?this.opts.mainMenuSubOffsetX:this.opts.subMenusSubOffsetX,T=2==n?this.opts.mainMenuSubOffsetY:this.opts.subMenusSubOffsetY;if(g?(e=M?d-r-w:w,i=this.opts.bottomToTopSubMenus?-h-T:m+T):(e=M?w-r:d-w,i=this.opts.bottomToTopSubMenus?m-T-h:T),this.opts.keepInViewport){var y=l+e,I=c+i;if(M&&f>y?e=g?f-y+e:d-w:!M&&y+r>f+b&&(e=g?f+b-r-y+e:w-r),g||(S>h&&I+h>v+S?i+=v+S-h-I:(h>=S||v>I)&&(i+=v-I)),g&&(I+h>v+S+.49||v>I)||!g&&h>S+.49){var x=this;t.dataSM("scroll-arrows")||t.dataSM("scroll-arrows",$([$('')[0],$('')[0]]).on({mouseenter:function(){t.dataSM("scroll").up=$(this).hasClass("scroll-up"),x.menuScroll(t)},mouseleave:function(e){x.menuScrollStop(t),x.menuScrollOut(t,e)},"mousewheel DOMMouseScroll":function(t){t.preventDefault()}}).insertAfter(t));var A=".smartmenus_scroll";if(t.dataSM("scroll",{y:this.cssTransforms3d?0:i-m,step:1,itemH:m,subH:h,arrowDownH:this.getHeight(t.dataSM("scroll-arrows").eq(1))}).on(getEventsNS({mouseover:function(e){x.menuScrollOver(t,e)},mouseout:function(e){x.menuScrollOut(t,e)},"mousewheel DOMMouseScroll":function(e){x.menuScrollMousewheel(t,e)}},A)).dataSM("scroll-arrows").css({top:"auto",left:"0",marginLeft:e+(parseInt(t.css("border-left-width"))||0),width:r-(parseInt(t.css("border-left-width"))||0)-(parseInt(t.css("border-right-width"))||0),zIndex:t.css("z-index")}).eq(g&&this.opts.bottomToTopSubMenus?0:1).show(),this.isFixed()){var C={};C[touchEvents?"touchstart touchmove touchend":"pointerdown pointermove pointerup MSPointerDown MSPointerMove MSPointerUp"]=function(e){x.menuScrollTouch(t,e)},t.css({"touch-action":"none","-ms-touch-action":"none"}).on(getEventsNS(C,A))}}}t.css({top:"auto",left:"0",marginLeft:e,marginTop:i-m})},menuScroll:function(t,e,i){var s,o=t.dataSM("scroll"),a=t.dataSM("scroll-arrows"),n=o.up?o.upEnd:o.downEnd;if(!e&&o.momentum){if(o.momentum*=.92,s=o.momentum,.5>s)return this.menuScrollStop(t),void 0}else s=i||(e||!this.opts.scrollAccelerate?this.opts.scrollStep:Math.floor(o.step));var r=t.dataSM("level");if(this.activatedItems[r-1]&&this.activatedItems[r-1].dataSM("sub")&&this.activatedItems[r-1].dataSM("sub").is(":visible")&&this.menuHideSubMenus(r-1),o.y=o.up&&o.y>=n||!o.up&&n>=o.y?o.y:Math.abs(n-o.y)>s?o.y+(o.up?s:-s):n,t.css(this.cssTransforms3d?{"-webkit-transform":"translate3d(0, "+o.y+"px, 0)",transform:"translate3d(0, "+o.y+"px, 0)"}:{marginTop:o.y}),mouse&&(o.up&&o.y>o.downEnd||!o.up&&o.y0;t.dataSM("scroll-arrows").eq(i?0:1).is(":visible")&&(t.dataSM("scroll").up=i,this.menuScroll(t,!0))}e.preventDefault()},menuScrollOut:function(t,e){mouse&&(/^scroll-(up|down)/.test((e.relatedTarget||"").className)||(t[0]==e.relatedTarget||$.contains(t[0],e.relatedTarget))&&this.getClosestMenu(e.relatedTarget)==t[0]||t.dataSM("scroll-arrows").css("visibility","hidden"))},menuScrollOver:function(t,e){if(mouse&&!/^scroll-(up|down)/.test(e.target.className)&&this.getClosestMenu(e.target)==t[0]){this.menuScrollRefreshData(t);var i=t.dataSM("scroll"),s=$(window).scrollTop()-t.dataSM("parent-a").offset().top-i.itemH;t.dataSM("scroll-arrows").eq(0).css("margin-top",s).end().eq(1).css("margin-top",s+this.getViewportHeight()-i.arrowDownH).end().css("visibility","visible")}},menuScrollRefreshData:function(t){var e=t.dataSM("scroll"),i=$(window).scrollTop()-t.dataSM("parent-a").offset().top-e.itemH;this.cssTransforms3d&&(i=-(parseFloat(t.css("margin-top"))-i)),$.extend(e,{upEnd:i,downEnd:i+this.getViewportHeight()-e.subH})},menuScrollStop:function(t){return this.scrollTimeout?(cancelAnimationFrame(this.scrollTimeout),this.scrollTimeout=0,t.dataSM("scroll").step=1,!0):void 0},menuScrollTouch:function(t,e){if(e=e.originalEvent,isTouchEvent(e)){var i=this.getTouchPoint(e);if(this.getClosestMenu(i.target)==t[0]){var s=t.dataSM("scroll");if(/(start|down)$/i.test(e.type))this.menuScrollStop(t)?(e.preventDefault(),this.$touchScrollingSub=t):this.$touchScrollingSub=null,this.menuScrollRefreshData(t),$.extend(s,{touchStartY:i.pageY,touchStartTime:e.timeStamp});else if(/move$/i.test(e.type)){var o=void 0!==s.touchY?s.touchY:s.touchStartY;if(void 0!==o&&o!=i.pageY){this.$touchScrollingSub=t;var a=i.pageY>o;void 0!==s.up&&s.up!=a&&$.extend(s,{touchStartY:i.pageY,touchStartTime:e.timeStamp}),$.extend(s,{up:a,touchY:i.pageY}),this.menuScroll(t,!0,Math.abs(i.pageY-o))}e.preventDefault()}else void 0!==s.touchY&&((s.momentum=15*Math.pow(Math.abs(i.pageY-s.touchStartY)/(e.timeStamp-s.touchStartTime),2))&&(this.menuScrollStop(t),this.menuScroll(t),e.preventDefault()),delete s.touchY)}}},menuShow:function(t){if((t.dataSM("beforefirstshowfired")||(t.dataSM("beforefirstshowfired",!0),this.$root.triggerHandler("beforefirstshow.smapi",t[0])!==!1))&&this.$root.triggerHandler("beforeshow.smapi",t[0])!==!1&&(t.dataSM("shown-before",!0),canAnimate&&t.stop(!0,!0),!t.is(":visible"))){var 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/dev/null +++ b/Utilities/sequencer/html/menu.js @@ -0,0 +1,51 @@ +/* + @licstart The following is the entire license notice for the JavaScript code in this file. + + The MIT License (MIT) + + Copyright (C) 1997-2020 by Dimitri van Heesch + + Permission is hereby granted, free of charge, to any person obtaining a copy of this software + and associated documentation files (the "Software"), to deal in the Software without restriction, + including without limitation the rights to use, copy, modify, merge, publish, distribute, + sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in all copies or + substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING + BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + + @licend The above is the entire license notice for the JavaScript code in this file + */ +function initMenu(relPath,searchEnabled,serverSide,searchPage,search) { + function makeTree(data,relPath) { + var result=''; + if ('children' in data) { + result+=''; + } + return result; + } + + $('#main-nav').append(makeTree(menudata,relPath)); + $('#main-nav').children(':first').addClass('sm sm-dox').attr('id','main-menu'); + if (searchEnabled) { + if (serverSide) { + $('#main-menu').append('
    • '); + } else { + $('#main-menu').append('
    • '); + } + } + $('#main-menu').smartmenus(); +} +/* @license-end */ diff --git a/Utilities/sequencer/html/menudata.js b/Utilities/sequencer/html/menudata.js new file mode 100644 index 0000000..16743b2 --- /dev/null +++ b/Utilities/sequencer/html/menudata.js @@ -0,0 +1,42 @@ +/* + @licstart The following is the entire license notice for the JavaScript code in this file. + + The MIT License (MIT) + + Copyright (C) 1997-2020 by Dimitri van Heesch + + Permission is hereby granted, free of charge, to any person obtaining a copy of this software + and associated documentation files (the "Software"), to deal in the Software without restriction, + including without limitation the rights to use, copy, modify, merge, publish, distribute, + sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in all copies or + substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING + BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + + @licend The above is the entire license notice for the JavaScript code in this file +*/ +var menudata={children:[ +{text:"Main Page",url:"index.html"}, +{text:"Modules",url:"modules.html"}, +{text:"Data Structures",url:"annotated.html",children:[ +{text:"Data Structures",url:"annotated.html"}, +{text:"Data Structure Index",url:"classes.html"}, +{text:"Data Fields",url:"functions.html",children:[ +{text:"All",url:"functions.html"}, +{text:"Variables",url:"functions_vars.html"}]}]}, +{text:"Files",url:"files.html",children:[ +{text:"File List",url:"files.html"}, +{text:"Globals",url:"globals.html",children:[ +{text:"All",url:"globals.html",children:[ +{text:"s",url:"globals.html#index_s"}, +{text:"u",url:"globals.html#index_u"}]}, +{text:"Functions",url:"globals_func.html"}, +{text:"Typedefs",url:"globals_type.html"}, +{text:"Macros",url:"globals_defs.html"}]}]}]} diff --git a/Utilities/sequencer/html/modules.html b/Utilities/sequencer/html/modules.html new file mode 100644 index 0000000..0ccffb2 --- /dev/null +++ b/Utilities/sequencer/html/modules.html @@ -0,0 +1,111 @@ + + + + + + + +STM32 Sequencer: Modules + + + + + + + + + + + + + +
    +
    + + + + + + +
    +
    STM32 Sequencer +  v1.6.0 +
    +
    +
    + + + + + + + +
    +
    + +
    +
    +
    + +
    + +
    +
    + + +
    + +
    + +
    +
    +
    Modules
    +
    +
    +
    Here is a list of all modules:
    +
    [detail level 12]
    + + + + + + + + + +
     ▼sequencer utilities
     SEQUENCER private type
     SEQUENCER private defines
     SEQUENCER private variables
     SEQUENCER private functions
     SEQUENCER exported types
     SEQUENCER exported constants
     SEQUENCER exported macros
     SEQUENCER exported functions
    +
    +
    +
    + + + + diff --git a/Utilities/sequencer/html/modules.js b/Utilities/sequencer/html/modules.js new file mode 100644 index 0000000..406df7f --- /dev/null +++ b/Utilities/sequencer/html/modules.js @@ -0,0 +1,4 @@ +var modules = +[ + [ "sequencer utilities", "group___s_e_q_u_e_n_c_e_r.html", "group___s_e_q_u_e_n_c_e_r" ] +]; \ No newline at end of file diff --git a/Utilities/sequencer/html/nav_f.png b/Utilities/sequencer/html/nav_f.png new file mode 100644 index 0000000..72a58a5 Binary files /dev/null and b/Utilities/sequencer/html/nav_f.png differ diff --git a/Utilities/sequencer/html/nav_g.png b/Utilities/sequencer/html/nav_g.png new file mode 100644 index 0000000..2093a23 Binary files /dev/null and b/Utilities/sequencer/html/nav_g.png differ diff --git a/Utilities/sequencer/html/nav_h.png b/Utilities/sequencer/html/nav_h.png new file mode 100644 index 0000000..33389b1 Binary files /dev/null and b/Utilities/sequencer/html/nav_h.png differ diff --git a/Utilities/sequencer/html/navtree.css b/Utilities/sequencer/html/navtree.css new file mode 100644 index 0000000..33341a6 --- /dev/null +++ b/Utilities/sequencer/html/navtree.css @@ -0,0 +1,146 @@ +#nav-tree .children_ul { + margin:0; + padding:4px; +} + +#nav-tree ul { + list-style:none outside none; + margin:0px; + padding:0px; +} + +#nav-tree li { + white-space:nowrap; + margin:0px; + padding:0px; +} + +#nav-tree .plus { + margin:0px; +} + +#nav-tree .selected { + background-image: url('tab_a.png'); + background-repeat:repeat-x; + color: #fff; + text-shadow: 0px 1px 1px rgba(0, 0, 0, 1.0); +} + +#nav-tree img { + margin:0px; + padding:0px; + border:0px; + vertical-align: middle; +} + +#nav-tree a { + text-decoration:none; + padding:0px; + margin:0px; + outline:none; +} + +#nav-tree .label { + margin:0px; + padding:0px; + font: 12px 'Lucida Grande',Geneva,Helvetica,Arial,sans-serif; +} + +#nav-tree .label a { + padding:2px; +} + +#nav-tree .selected a { + text-decoration:none; + color:#fff; +} + +#nav-tree .children_ul { + margin:0px; + padding:0px; +} + +#nav-tree .item { + margin:0px; + padding:0px; +} + +#nav-tree { + padding: 0px 0px; + background-color: #FAFAFF; + font-size:14px; + overflow:auto; +} + +#doc-content { + overflow:auto; + display:block; + padding:0px; + margin:0px; + -webkit-overflow-scrolling : touch; /* iOS 5+ */ +} + +#side-nav { + padding:0 6px 0 0; + margin: 0px; + display:block; + position: absolute; + left: 0px; + width: 250px; +} + +.ui-resizable .ui-resizable-handle { + display:block; +} + +.ui-resizable-e { + background-image:url("splitbar.png"); + background-size:100%; + background-repeat:repeat-y; + background-attachment: scroll; + cursor:ew-resize; + height:100%; + right:0; + top:0; + width:6px; +} + +.ui-resizable-handle { + display:none; + font-size:0.1px; + position:absolute; + z-index:1; +} + +#nav-tree-contents { + margin: 6px 0px 0px 0px; +} + +#nav-tree { + background-image:url('nav_h.png'); + background-repeat:repeat-x; + background-color: #F9FAFC; + -webkit-overflow-scrolling : touch; /* iOS 5+ */ +} + +#nav-sync { + position:absolute; + top:5px; + right:24px; + z-index:0; +} + +#nav-sync img { + opacity:0.3; +} + +#nav-sync img:hover { + opacity:0.9; +} + +@media print +{ + #nav-tree { display: none; } + div.ui-resizable-handle { display: none; position: relative; } +} + diff --git a/Utilities/sequencer/html/navtree.js b/Utilities/sequencer/html/navtree.js new file mode 100644 index 0000000..1e272d3 --- /dev/null +++ b/Utilities/sequencer/html/navtree.js @@ -0,0 +1,546 @@ +/* + @licstart The following is the entire license notice for the JavaScript code in this file. + + The MIT License (MIT) + + Copyright (C) 1997-2020 by Dimitri van Heesch + + Permission is hereby granted, free of charge, to any person obtaining a copy of this software + and associated documentation files (the "Software"), to deal in the Software without restriction, + including without limitation the rights to use, copy, modify, merge, publish, distribute, + sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in all copies or + substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING + BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + + @licend The above is the entire license notice for the JavaScript code in this file + */ +var navTreeSubIndices = new Array(); +var arrowDown = '▼'; +var arrowRight = '►'; + +function getData(varName) +{ + var i = varName.lastIndexOf('/'); + var n = i>=0 ? varName.substring(i+1) : varName; + return eval(n.replace(/\-/g,'_')); +} + +function stripPath(uri) +{ + return uri.substring(uri.lastIndexOf('/')+1); +} + +function stripPath2(uri) +{ + var i = uri.lastIndexOf('/'); + var s = uri.substring(i+1); + var m = uri.substring(0,i+1).match(/\/d\w\/d\w\w\/$/); + return m ? uri.substring(i-6) : s; +} + +function hashValue() +{ + return $(location).attr('hash').substring(1).replace(/[^\w\-]/g,''); +} + +function hashUrl() +{ + return '#'+hashValue(); +} + +function pathName() +{ + return $(location).attr('pathname').replace(/[^-A-Za-z0-9+&@#/%?=~_|!:,.;\(\)]/g, ''); +} + +function localStorageSupported() +{ + try { + return 'localStorage' in window && window['localStorage'] !== null && window.localStorage.getItem; + } + catch(e) { + return false; + } +} + +function storeLink(link) +{ + if (!$("#nav-sync").hasClass('sync') && localStorageSupported()) { + window.localStorage.setItem('navpath',link); + } +} + +function deleteLink() +{ + if (localStorageSupported()) { + window.localStorage.setItem('navpath',''); + } +} + +function cachedLink() +{ + if (localStorageSupported()) { + return window.localStorage.getItem('navpath'); + } else { + return ''; + } +} + +function getScript(scriptName,func,show) +{ + var head = document.getElementsByTagName("head")[0]; + var script = document.createElement('script'); + script.id = scriptName; + script.type = 'text/javascript'; + script.onload = func; + script.src = scriptName+'.js'; + head.appendChild(script); +} + +function createIndent(o,domNode,node,level) +{ + var level=-1; + var n = node; + while (n.parentNode) { level++; n=n.parentNode; } + if (node.childrenData) { + var imgNode = document.createElement("span"); + imgNode.className = 'arrow'; + imgNode.style.paddingLeft=(16*level).toString()+'px'; + imgNode.innerHTML=arrowRight; + node.plus_img = imgNode; + node.expandToggle = document.createElement("a"); + node.expandToggle.href = "javascript:void(0)"; + node.expandToggle.onclick = function() { + if (node.expanded) { + $(node.getChildrenUL()).slideUp("fast"); + node.plus_img.innerHTML=arrowRight; + node.expanded = false; + } else { + expandNode(o, node, false, false); + } + } + node.expandToggle.appendChild(imgNode); + domNode.appendChild(node.expandToggle); + } else { + var span = document.createElement("span"); + span.className = 'arrow'; + span.style.width = 16*(level+1)+'px'; + span.innerHTML = ' '; + domNode.appendChild(span); + } +} + +var animationInProgress = false; + +function gotoAnchor(anchor,aname,updateLocation) +{ + var pos, docContent = $('#doc-content'); + var ancParent = $(anchor.parent()); + if (ancParent.hasClass('memItemLeft') || + ancParent.hasClass('memtitle') || + ancParent.hasClass('fieldname') || + ancParent.hasClass('fieldtype') || + ancParent.is(':header')) + { + pos = ancParent.position().top; + } else if (anchor.position()) { + pos = anchor.position().top; + } + if (pos) { + var dist = Math.abs(Math.min( + pos-docContent.offset().top, + docContent[0].scrollHeight- + docContent.height()-docContent.scrollTop())); + animationInProgress=true; + docContent.animate({ + scrollTop: pos + docContent.scrollTop() - docContent.offset().top + },Math.max(50,Math.min(500,dist)),function(){ + if (updateLocation) window.location.href=aname; + animationInProgress=false; + }); + } +} + +function newNode(o, po, text, link, childrenData, lastNode) +{ + var node = new Object(); + node.children = Array(); + node.childrenData = childrenData; + node.depth = po.depth + 1; + node.relpath = po.relpath; + node.isLast = lastNode; + + node.li = document.createElement("li"); + po.getChildrenUL().appendChild(node.li); + node.parentNode = po; + + node.itemDiv = document.createElement("div"); + node.itemDiv.className = "item"; + + node.labelSpan = document.createElement("span"); + node.labelSpan.className = "label"; + + createIndent(o,node.itemDiv,node,0); + node.itemDiv.appendChild(node.labelSpan); + node.li.appendChild(node.itemDiv); + + var a = document.createElement("a"); + node.labelSpan.appendChild(a); + node.label = document.createTextNode(text); + node.expanded = false; + a.appendChild(node.label); + if (link) { + var url; + if (link.substring(0,1)=='^') { + url = link.substring(1); + link = url; + } else { + url = node.relpath+link; + } + a.className = stripPath(link.replace('#',':')); + if (link.indexOf('#')!=-1) { + var aname = '#'+link.split('#')[1]; + var srcPage = stripPath(pathName()); + var targetPage = stripPath(link.split('#')[0]); + a.href = srcPage!=targetPage ? url : "javascript:void(0)"; + a.onclick = function(){ + storeLink(link); + if (!$(a).parent().parent().hasClass('selected')) + { + $('.item').removeClass('selected'); + $('.item').removeAttr('id'); + $(a).parent().parent().addClass('selected'); + $(a).parent().parent().attr('id','selected'); + } + var anchor = $(aname); + gotoAnchor(anchor,aname,true); + }; + } else { + a.href = url; + a.onclick = function() { storeLink(link); } + } + } else { + if (childrenData != null) + { + a.className = "nolink"; + a.href = "javascript:void(0)"; + a.onclick = node.expandToggle.onclick; + } + } + + node.childrenUL = null; + node.getChildrenUL = function() { + if (!node.childrenUL) { + node.childrenUL = document.createElement("ul"); + node.childrenUL.className = "children_ul"; + node.childrenUL.style.display = "none"; + node.li.appendChild(node.childrenUL); + } + return node.childrenUL; + }; + + return node; +} + +function showRoot() +{ + var headerHeight = $("#top").height(); + var footerHeight = $("#nav-path").height(); + var windowHeight = $(window).height() - headerHeight - footerHeight; + (function (){ // retry until we can scroll to the selected item + try { + var navtree=$('#nav-tree'); + navtree.scrollTo('#selected',100,{offset:-windowHeight/2}); + } catch (err) { + setTimeout(arguments.callee, 0); + } + })(); +} + +function expandNode(o, node, imm, showRoot) +{ + if (node.childrenData && !node.expanded) { + if (typeof(node.childrenData)==='string') { + var varName = node.childrenData; + getScript(node.relpath+varName,function(){ + node.childrenData = getData(varName); + expandNode(o, node, imm, showRoot); + }, showRoot); + } else { + if (!node.childrenVisited) { + getNode(o, node); + } + $(node.getChildrenUL()).slideDown("fast"); + node.plus_img.innerHTML = arrowDown; + node.expanded = true; + } + } +} + +function glowEffect(n,duration) +{ + n.addClass('glow').delay(duration).queue(function(next){ + $(this).removeClass('glow');next(); + }); +} + +function highlightAnchor() +{ + var aname = hashUrl(); + var anchor = $(aname); + if (anchor.parent().attr('class')=='memItemLeft'){ + var rows = $('.memberdecls tr[class$="'+hashValue()+'"]'); + glowEffect(rows.children(),300); // member without details + } else if (anchor.parent().attr('class')=='fieldname'){ + glowEffect(anchor.parent().parent(),1000); // enum value + } else if (anchor.parent().attr('class')=='fieldtype'){ + glowEffect(anchor.parent().parent(),1000); // struct field + } else if (anchor.parent().is(":header")) { + glowEffect(anchor.parent(),1000); // section header + } else { + glowEffect(anchor.next(),1000); // normal member + } +} + +function selectAndHighlight(hash,n) +{ + var a; + if (hash) { + var link=stripPath(pathName())+':'+hash.substring(1); + a=$('.item a[class$="'+link+'"]'); + } + if (a && a.length) { + a.parent().parent().addClass('selected'); + a.parent().parent().attr('id','selected'); + highlightAnchor(); + } else if (n) { + $(n.itemDiv).addClass('selected'); + $(n.itemDiv).attr('id','selected'); + } + if ($('#nav-tree-contents .item:first').hasClass('selected')) { + $('#nav-sync').css('top','30px'); + } else { + $('#nav-sync').css('top','5px'); + } + showRoot(); +} + +function showNode(o, node, index, hash) +{ + if (node && node.childrenData) { + if (typeof(node.childrenData)==='string') { + var varName = node.childrenData; + getScript(node.relpath+varName,function(){ + node.childrenData = getData(varName); + showNode(o,node,index,hash); + },true); + } else { + if (!node.childrenVisited) { + getNode(o, node); + } + $(node.getChildrenUL()).css({'display':'block'}); + node.plus_img.innerHTML = arrowDown; + node.expanded = true; + var n = node.children[o.breadcrumbs[index]]; + if (index+11) hash = '#'+parts[1].replace(/[^\w\-]/g,''); + else hash=''; + } + if (hash.match(/^#l\d+$/)) { + var anchor=$('a[name='+hash.substring(1)+']'); + glowEffect(anchor.parent(),1000); // line number + hash=''; // strip line number anchors + } + var url=root+hash; + var i=-1; + while (NAVTREEINDEX[i+1]<=url) i++; + if (i==-1) { i=0; root=NAVTREE[0][1]; } // fallback: show index + if (navTreeSubIndices[i]) { + gotoNode(o,i,root,hash,relpath) + } else { + getScript(relpath+'navtreeindex'+i,function(){ + navTreeSubIndices[i] = eval('NAVTREEINDEX'+i); + if (navTreeSubIndices[i]) { + gotoNode(o,i,root,hash,relpath); + } + },true); + } +} + +function showSyncOff(n,relpath) +{ + n.html(''); +} + +function showSyncOn(n,relpath) +{ + n.html(''); +} + +function toggleSyncButton(relpath) +{ + var navSync = $('#nav-sync'); + if (navSync.hasClass('sync')) { + navSync.removeClass('sync'); + showSyncOff(navSync,relpath); + storeLink(stripPath2(pathName())+hashUrl()); + } else { + navSync.addClass('sync'); + showSyncOn(navSync,relpath); + deleteLink(); + } +} + +var loadTriggered = false; +var readyTriggered = false; +var loadObject,loadToRoot,loadUrl,loadRelPath; + +$(window).on('load',function(){ + if (readyTriggered) { // ready first + navTo(loadObject,loadToRoot,loadUrl,loadRelPath); + showRoot(); + } + loadTriggered=true; +}); + +function initNavTree(toroot,relpath) +{ + var o = new Object(); + o.toroot = toroot; + o.node = new Object(); + o.node.li = document.getElementById("nav-tree-contents"); + o.node.childrenData = NAVTREE; + o.node.children = new Array(); + o.node.childrenUL = document.createElement("ul"); + o.node.getChildrenUL = function() { return o.node.childrenUL; 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    + + diff --git a/Utilities/sequencer/html/search/groups_0.js b/Utilities/sequencer/html/search/groups_0.js new file mode 100644 index 0000000..78f0562 --- /dev/null +++ b/Utilities/sequencer/html/search/groups_0.js @@ -0,0 +1,12 @@ +var searchData= +[ + ['sequencer_20exported_20constants_69',['SEQUENCER exported constants',['../group___s_e_q_u_e_n_c_e_r___exported__const.html',1,'']]], + ['sequencer_20exported_20functions_70',['SEQUENCER exported functions',['../group___s_e_q_u_e_n_c_e_r___exported__function.html',1,'']]], + ['sequencer_20exported_20macros_71',['SEQUENCER exported macros',['../group___s_e_q_u_e_n_c_e_r___exported__macro.html',1,'']]], + ['sequencer_20exported_20types_72',['SEQUENCER exported types',['../group___s_e_q_u_e_n_c_e_r___exported__type.html',1,'']]], + ['sequencer_20private_20defines_73',['SEQUENCER private defines',['../group___s_e_q_u_e_n_c_e_r___private__define.html',1,'']]], + ['sequencer_20private_20functions_74',['SEQUENCER private functions',['../group___s_e_q_u_e_n_c_e_r___private__function.html',1,'']]], + ['sequencer_20private_20type_75',['SEQUENCER private type',['../group___s_e_q_u_e_n_c_e_r___private__type.html',1,'']]], + ['sequencer_20private_20variables_76',['SEQUENCER private variables',['../group___s_e_q_u_e_n_c_e_r___private__varaible.html',1,'']]], + ['sequencer_20utilities_77',['sequencer utilities',['../group___s_e_q_u_e_n_c_e_r.html',1,'']]] +]; diff --git a/Utilities/sequencer/html/search/mag_sel.png b/Utilities/sequencer/html/search/mag_sel.png new file mode 100644 index 0000000..39c0ed5 Binary files /dev/null and b/Utilities/sequencer/html/search/mag_sel.png differ diff --git a/Utilities/sequencer/html/search/mag_sel.svg b/Utilities/sequencer/html/search/mag_sel.svg new file mode 100644 index 0000000..03626f6 --- /dev/null +++ b/Utilities/sequencer/html/search/mag_sel.svg @@ -0,0 +1,74 @@ + + + + + + + + image/svg+xml + + + + + + + + + + + diff --git a/Utilities/sequencer/html/search/nomatches.html b/Utilities/sequencer/html/search/nomatches.html new file mode 100644 index 0000000..2b9360b --- /dev/null +++ b/Utilities/sequencer/html/search/nomatches.html @@ -0,0 +1,13 @@ + + + + + + + + +
    +
    No Matches
    +
    + + diff --git a/Utilities/sequencer/html/search/search.css b/Utilities/sequencer/html/search/search.css new file mode 100644 index 0000000..9074198 --- /dev/null +++ b/Utilities/sequencer/html/search/search.css @@ -0,0 +1,257 @@ +/*---------------- Search Box */ + +#MSearchBox { + white-space : nowrap; + background: white; + border-radius: 0.65em; + box-shadow: inset 0.5px 0.5px 3px 0px #555; + z-index: 102; +} + +#MSearchBox .left { + display: inline-block; + vertical-align: middle; + height: 1.4em; +} + +#MSearchSelect { + display: inline-block; + vertical-align: middle; + height: 1.4em; + padding: 0 0 0 0.3em; + margin: 0; +} + +#MSearchField { + display: inline-block; + vertical-align: middle; + width: 7.5em; + height: 1.1em; + margin: 0 0.15em; + padding: 0; + line-height: 1em; + border:none; + color: #909090; + outline: none; + font-family: Arial, Verdana, sans-serif; + -webkit-border-radius: 0px; + border-radius: 0px; + background: none; +} + + +#MSearchBox .right { + display: inline-block; + vertical-align: middle; + width: 1.4em; + height: 1.4em; +} + +#MSearchClose { + display: none; + font-size: inherit; + background : none; + border: none; + margin: 0; + padding: 0; + outline: none; + +} + +#MSearchCloseImg { + height: 1.4em; + padding: 0.3em; + margin: 0; +} + +.MSearchBoxActive #MSearchField { + color: #000000; +} + +#main-menu > li:last-child { + /* This
  • object is the parent of the search bar */ + display: flex; + justify-content: center; + align-items: center; + height: 36px; + margin-right: 1em; +} + +/*---------------- Search filter selection */ + +#MSearchSelectWindow { + display: none; + position: absolute; + left: 0; top: 0; + border: 1px solid #90A5CE; + background-color: #F9FAFC; + z-index: 10001; + padding-top: 4px; + padding-bottom: 4px; + -moz-border-radius: 4px; + -webkit-border-top-left-radius: 4px; + -webkit-border-top-right-radius: 4px; + -webkit-border-bottom-left-radius: 4px; + -webkit-border-bottom-right-radius: 4px; + -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15); +} + +.SelectItem { + font: 8pt Arial, Verdana, sans-serif; + padding-left: 2px; + padding-right: 12px; + border: 0px; +} + +span.SelectionMark { + margin-right: 4px; + font-family: monospace; + outline-style: none; + text-decoration: none; +} + +a.SelectItem { + display: block; + outline-style: none; + color: #000000; + text-decoration: none; + padding-left: 6px; + padding-right: 12px; +} + +a.SelectItem:focus, +a.SelectItem:active { + color: #000000; + outline-style: none; + text-decoration: none; +} + +a.SelectItem:hover { + color: #FFFFFF; + background-color: #3D578C; + outline-style: none; + text-decoration: none; + cursor: pointer; + display: block; +} + +/*---------------- Search results window */ + +iframe#MSearchResults { + width: 60ex; + height: 15em; +} + +#MSearchResultsWindow { + display: none; + position: absolute; + left: 0; top: 0; + border: 1px solid #000; + background-color: #EEF1F7; + z-index:10000; +} + +/* ----------------------------------- */ + + +#SRIndex { + clear:both; + padding-bottom: 15px; +} + +.SREntry { + font-size: 10pt; + padding-left: 1ex; +} + +.SRPage .SREntry { + font-size: 8pt; + padding: 1px 5px; +} + +body.SRPage { + margin: 5px 2px; +} + +.SRChildren { + padding-left: 3ex; padding-bottom: .5em +} + +.SRPage .SRChildren { + display: none; +} + +.SRSymbol { + font-weight: bold; + color: #425E97; + font-family: Arial, Verdana, sans-serif; + text-decoration: none; + outline: none; +} + +a.SRScope { + display: block; + color: #425E97; + font-family: Arial, Verdana, sans-serif; + text-decoration: none; + outline: none; +} + +a.SRSymbol:focus, a.SRSymbol:active, +a.SRScope:focus, a.SRScope:active { + text-decoration: underline; +} + +span.SRScope { + padding-left: 4px; + font-family: Arial, Verdana, sans-serif; +} + +.SRPage .SRStatus { + padding: 2px 5px; + font-size: 8pt; + font-style: italic; + font-family: Arial, Verdana, sans-serif; +} + +.SRResult { + display: none; +} + +div.searchresults { + margin-left: 10px; + margin-right: 10px; +} + +/*---------------- External search page results */ + +.searchresult { + background-color: #F0F3F8; +} + +.pages b { + color: white; + padding: 5px 5px 3px 5px; + background-image: url("../tab_a.png"); + background-repeat: repeat-x; + text-shadow: 0 1px 1px #000000; +} + +.pages { + line-height: 17px; + margin-left: 4px; + text-decoration: none; +} + +.hl { + font-weight: bold; +} + +#searchresults { + margin-bottom: 20px; +} + +.searchpages { + margin-top: 10px; +} + diff --git a/Utilities/sequencer/html/search/search.js b/Utilities/sequencer/html/search/search.js new file mode 100644 index 0000000..fb226f7 --- /dev/null +++ b/Utilities/sequencer/html/search/search.js @@ -0,0 +1,816 @@ +/* + @licstart The following is the entire license notice for the JavaScript code in this file. + + The MIT License (MIT) + + Copyright (C) 1997-2020 by Dimitri van Heesch + + Permission is hereby granted, free of charge, to any person obtaining a copy of this software + and associated documentation files (the "Software"), to deal in the Software without restriction, + including without limitation the rights to use, copy, modify, merge, publish, distribute, + sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in all copies or + substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING + BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + + @licend The above is the entire license notice for the JavaScript code in this file + */ +function convertToId(search) +{ + var result = ''; + for (i=0;i do a search + { + this.Search(); + } + } + + this.OnSearchSelectKey = function(evt) + { + var e = (evt) ? evt : window.event; // for IE + if (e.keyCode==40 && this.searchIndex0) // Up + { + this.searchIndex--; + this.OnSelectItem(this.searchIndex); + } + else if (e.keyCode==13 || e.keyCode==27) + { + this.OnSelectItem(this.searchIndex); + this.CloseSelectionWindow(); + this.DOMSearchField().focus(); + } + return false; + } + + // --------- Actions + + // Closes the results window. + this.CloseResultsWindow = function() + { + this.DOMPopupSearchResultsWindow().style.display = 'none'; + this.DOMSearchClose().style.display = 'none'; + this.Activate(false); + } + + this.CloseSelectionWindow = function() + { + this.DOMSearchSelectWindow().style.display = 'none'; + } + + // Performs a search. + this.Search = function() + { + this.keyTimeout = 0; + + // strip leading whitespace + var searchValue = this.DOMSearchField().value.replace(/^ +/, ""); + + var code = searchValue.toLowerCase().charCodeAt(0); + var idxChar = searchValue.substr(0, 1).toLowerCase(); + if ( 0xD800 <= code && code <= 0xDBFF && searchValue > 1) // surrogate pair + { + idxChar = searchValue.substr(0, 2); + } + + var resultsPage; + var resultsPageWithSearch; + var hasResultsPage; + + var idx = indexSectionsWithContent[this.searchIndex].indexOf(idxChar); + if (idx!=-1) + { + var hexCode=idx.toString(16); + resultsPage = this.resultsPath + '/' + indexSectionNames[this.searchIndex] + '_' + hexCode + this.extension; + resultsPageWithSearch = resultsPage+'?'+escape(searchValue); + hasResultsPage = true; + } + else // nothing available for this search term + { + resultsPage = this.resultsPath + '/nomatches' + this.extension; + resultsPageWithSearch = resultsPage; + hasResultsPage = false; + } + + window.frames.MSearchResults.location = resultsPageWithSearch; + var domPopupSearchResultsWindow = this.DOMPopupSearchResultsWindow(); + + if (domPopupSearchResultsWindow.style.display!='block') + { + var domSearchBox = this.DOMSearchBox(); + this.DOMSearchClose().style.display = 'inline-block'; + if (this.insideFrame) + { + var domPopupSearchResults = this.DOMPopupSearchResults(); + domPopupSearchResultsWindow.style.position = 'relative'; + domPopupSearchResultsWindow.style.display = 'block'; + var width = document.body.clientWidth - 8; // the -8 is for IE :-( + domPopupSearchResultsWindow.style.width = width + 'px'; + domPopupSearchResults.style.width = width + 'px'; + } + else + { + var domPopupSearchResults = this.DOMPopupSearchResults(); + var left = getXPos(domSearchBox) + 150; // domSearchBox.offsetWidth; + var top = getYPos(domSearchBox) + 20; // domSearchBox.offsetHeight + 1; + domPopupSearchResultsWindow.style.display = 'block'; + left -= domPopupSearchResults.offsetWidth; + domPopupSearchResultsWindow.style.top = top + 'px'; + domPopupSearchResultsWindow.style.left = left + 'px'; + } + } + + this.lastSearchValue = searchValue; + this.lastResultsPage = resultsPage; + } + + // -------- Activation Functions + + // Activates or deactivates the search panel, resetting things to + // their default values if necessary. + this.Activate = function(isActive) + { + if (isActive || // open it + this.DOMPopupSearchResultsWindow().style.display == 'block' + ) + { + this.DOMSearchBox().className = 'MSearchBoxActive'; + + var searchField = this.DOMSearchField(); + + if (searchField.value == this.searchLabel) // clear "Search" term upon entry + { + searchField.value = ''; + this.searchActive = true; + } + } + else if (!isActive) // directly remove the panel + { + this.DOMSearchBox().className = 'MSearchBoxInactive'; + this.DOMSearchField().value = this.searchLabel; + this.searchActive = false; + this.lastSearchValue = '' + this.lastResultsPage = ''; + } + } +} + +// ----------------------------------------------------------------------- + +// The class that handles everything on the search results page. +function SearchResults(name) +{ + // The number of matches from the last run of . + this.lastMatchCount = 0; + this.lastKey = 0; + this.repeatOn = false; + + // Toggles the visibility of the passed element ID. + this.FindChildElement = function(id) + { + var parentElement = document.getElementById(id); + var element = parentElement.firstChild; + + while (element && element!=parentElement) + { + if (element.nodeName.toLowerCase() == 'div' && element.className == 'SRChildren') + { + return element; + } + + if (element.nodeName.toLowerCase() == 'div' && element.hasChildNodes()) + { + element = element.firstChild; + } + else if (element.nextSibling) + { + element = element.nextSibling; + } + else + { + do + { + element = element.parentNode; + } + while (element && element!=parentElement && !element.nextSibling); + + if (element && element!=parentElement) + { + element = element.nextSibling; + } + } + } + } + + this.Toggle = function(id) + { + var element = this.FindChildElement(id); + if (element) + { + if (element.style.display == 'block') + { + element.style.display = 'none'; + } + else + { + element.style.display = 'block'; + } + } + } + + // Searches for the passed string. If there is no parameter, + // it takes it from the URL query. + // + // Always returns true, since other documents may try to call it + // and that may or may not be possible. + this.Search = function(search) + { + if (!search) // get search word from URL + { + search = window.location.search; + search = search.substring(1); // Remove the leading '?' + search = unescape(search); + } + + search = search.replace(/^ +/, ""); // strip leading spaces + search = search.replace(/ +$/, ""); // strip trailing spaces + search = search.toLowerCase(); + search = convertToId(search); + + var resultRows = document.getElementsByTagName("div"); + var matches = 0; + + var i = 0; + while (i < resultRows.length) + { + var row = resultRows.item(i); + if (row.className == "SRResult") + { + var rowMatchName = row.id.toLowerCase(); + rowMatchName = rowMatchName.replace(/^sr\d*_/, ''); // strip 'sr123_' + + if (search.length<=rowMatchName.length && + rowMatchName.substr(0, search.length)==search) + { + row.style.display = 'block'; + matches++; + } + else + { + row.style.display = 'none'; + } + } + i++; + } + document.getElementById("Searching").style.display='none'; + if (matches == 0) // no results + { + document.getElementById("NoMatches").style.display='block'; + } + else // at least one result + { + document.getElementById("NoMatches").style.display='none'; + } + this.lastMatchCount = matches; + return true; + } + + // return the first item with index index or higher that is visible + this.NavNext = function(index) + { + var focusItem; + while (1) + { + var focusName = 'Item'+index; + focusItem = document.getElementById(focusName); + if (focusItem && focusItem.parentNode.parentNode.style.display=='block') + { + break; + } + else if (!focusItem) // last element + { + break; + } + focusItem=null; + index++; + } + return focusItem; + } + + this.NavPrev = function(index) + { + var focusItem; + while (1) + { + var focusName = 'Item'+index; + focusItem = document.getElementById(focusName); + if (focusItem && focusItem.parentNode.parentNode.style.display=='block') + { + break; + } + else if (!focusItem) // last element + { + break; + } + focusItem=null; + index--; + } + return focusItem; + } + + this.ProcessKeys = function(e) + { + if (e.type == "keydown") + { + this.repeatOn = false; + this.lastKey = e.keyCode; + } + else if (e.type == "keypress") + { + if (!this.repeatOn) + { + if (this.lastKey) this.repeatOn = true; + return false; // ignore first keypress after keydown + } + } + else if (e.type == "keyup") + { + this.lastKey = 0; + this.repeatOn = false; + } + return this.lastKey!=0; + } + + this.Nav = function(evt,itemIndex) + { + var e = (evt) ? evt : window.event; // for IE + if (e.keyCode==13) return true; + if (!this.ProcessKeys(e)) return false; + + if (this.lastKey==38) // Up + { + var newIndex = itemIndex-1; + var focusItem = this.NavPrev(newIndex); + if (focusItem) + { + var child = this.FindChildElement(focusItem.parentNode.parentNode.id); + if (child && child.style.display == 'block') // children visible + { + var n=0; + var tmpElem; + while (1) // search for last child + { + tmpElem = document.getElementById('Item'+newIndex+'_c'+n); + if (tmpElem) + { + focusItem = tmpElem; + } + else // found it! + { + break; + } + n++; + } + } + } + if (focusItem) + { + focusItem.focus(); + } + else // return focus to search field + { + parent.document.getElementById("MSearchField").focus(); + } + } + else if (this.lastKey==40) // Down + { + var newIndex = itemIndex+1; + var focusItem; + var item = document.getElementById('Item'+itemIndex); + var elem = this.FindChildElement(item.parentNode.parentNode.id); + if (elem && elem.style.display == 'block') // children visible + { + focusItem = document.getElementById('Item'+itemIndex+'_c0'); + } + if (!focusItem) focusItem = this.NavNext(newIndex); + if (focusItem) focusItem.focus(); + } + else if (this.lastKey==39) // Right + { + var item = document.getElementById('Item'+itemIndex); + var elem = this.FindChildElement(item.parentNode.parentNode.id); + if (elem) elem.style.display = 'block'; + } + else if (this.lastKey==37) // Left + { + var item = document.getElementById('Item'+itemIndex); + var elem = this.FindChildElement(item.parentNode.parentNode.id); + if (elem) elem.style.display = 'none'; + } + else if (this.lastKey==27) // Escape + { + parent.searchBox.CloseResultsWindow(); + parent.document.getElementById("MSearchField").focus(); + } + else if (this.lastKey==13) // Enter + { + return true; + } + return false; + } + + this.NavChild = function(evt,itemIndex,childIndex) + { + var e = (evt) ? evt : window.event; // for IE + if (e.keyCode==13) return true; + if (!this.ProcessKeys(e)) return false; + + if (this.lastKey==38) // Up + { + if (childIndex>0) + { + var newIndex = childIndex-1; + document.getElementById('Item'+itemIndex+'_c'+newIndex).focus(); + } + else // already at first child, jump to parent + { + document.getElementById('Item'+itemIndex).focus(); + } + } + else if (this.lastKey==40) // Down + { + var newIndex = childIndex+1; + var elem = document.getElementById('Item'+itemIndex+'_c'+newIndex); + if (!elem) // last child, jump to parent next parent + { + elem = this.NavNext(itemIndex+1); + } + if (elem) + { + elem.focus(); + } + } + else if (this.lastKey==27) // Escape + { + parent.searchBox.CloseResultsWindow(); + parent.document.getElementById("MSearchField").focus(); + } + else if (this.lastKey==13) // Enter + { + return true; + } + return false; + } +} + +function setKeyActions(elem,action) +{ + elem.setAttribute('onkeydown',action); + elem.setAttribute('onkeypress',action); + elem.setAttribute('onkeyup',action); +} + +function setClassAttr(elem,attr) +{ + elem.setAttribute('class',attr); + elem.setAttribute('className',attr); +} + +function createResults() +{ + var results = document.getElementById("SRResults"); + for (var e=0; e + + + + + + + + + +
    +
    Loading...
    +
    + +
    Searching...
    +
    No Matches
    + +
    + + diff --git a/Utilities/sequencer/html/search/typedefs_0.js b/Utilities/sequencer/html/search/typedefs_0.js new file mode 100644 index 0000000..e154a64 --- /dev/null +++ b/Utilities/sequencer/html/search/typedefs_0.js @@ -0,0 +1,4 @@ +var searchData= +[ + ['util_5fseq_5fbm_5ft_68',['UTIL_SEQ_bm_t',['../group___s_e_q_u_e_n_c_e_r___exported__type.html#gaf1d37385aa3a7ce76c48447ba7dd5707',1,'stm32_seq.h']]] +]; diff --git a/Utilities/sequencer/html/search/variables_0.html b/Utilities/sequencer/html/search/variables_0.html new file mode 100644 index 0000000..1e477c0 --- /dev/null +++ b/Utilities/sequencer/html/search/variables_0.html @@ -0,0 +1,37 @@ + + + + + + + + + + +
    +
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    +
    + +
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    + +
    + + diff --git a/Utilities/sequencer/html/search/variables_0.js b/Utilities/sequencer/html/search/variables_0.js new file mode 100644 index 0000000..8abaf33 --- /dev/null +++ b/Utilities/sequencer/html/search/variables_0.js @@ -0,0 +1,4 @@ +var searchData= +[ + ['priority_66',['priority',['../struct_u_t_i_l___s_e_q___priority__t.html#a59563315cdb7b76c8a482160851cac3f',1,'UTIL_SEQ_Priority_t']]] +]; diff --git a/Utilities/sequencer/html/search/variables_1.html b/Utilities/sequencer/html/search/variables_1.html new file mode 100644 index 0000000..ea73d9a --- /dev/null +++ b/Utilities/sequencer/html/search/variables_1.html @@ -0,0 +1,37 @@ + + + + + + + + + + +
    +
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    +
    + +
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    +
    No Matches
    + +
    + + diff --git a/Utilities/sequencer/html/search/variables_1.js b/Utilities/sequencer/html/search/variables_1.js new file mode 100644 index 0000000..4e81053 --- /dev/null +++ b/Utilities/sequencer/html/search/variables_1.js @@ -0,0 +1,4 @@ +var searchData= +[ + ['round_5frobin_67',['round_robin',['../struct_u_t_i_l___s_e_q___priority__t.html#a10895a689ca10b69554ba4a822329f54',1,'UTIL_SEQ_Priority_t']]] +]; diff --git a/Utilities/sequencer/html/search/variables_2.html b/Utilities/sequencer/html/search/variables_2.html new file mode 100644 index 0000000..647df20 --- /dev/null +++ b/Utilities/sequencer/html/search/variables_2.html @@ -0,0 +1,30 @@ + + + + + + + + + +
    +
    Loading...
    +
    + +
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    +
    No Matches
    + +
    + + diff --git a/Utilities/sequencer/html/search/variables_2.js b/Utilities/sequencer/html/search/variables_2.js new file mode 100644 index 0000000..febc21e --- /dev/null +++ b/Utilities/sequencer/html/search/variables_2.js @@ -0,0 +1,4 @@ +var searchData= +[ + ['priority_71',['priority',['../struct_u_t_i_l___s_e_q___priority__t.html#a59563315cdb7b76c8a482160851cac3f',1,'UTIL_SEQ_Priority_t']]] +]; diff --git a/Utilities/sequencer/html/search/variables_3.html b/Utilities/sequencer/html/search/variables_3.html new file mode 100644 index 0000000..9dc9b89 --- /dev/null +++ b/Utilities/sequencer/html/search/variables_3.html @@ -0,0 +1,30 @@ + + + + + + + + + +
    +
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    +
    + +
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    +
    No Matches
    + +
    + + diff --git a/Utilities/sequencer/html/search/variables_3.js b/Utilities/sequencer/html/search/variables_3.js new file mode 100644 index 0000000..82c9cdd --- /dev/null +++ b/Utilities/sequencer/html/search/variables_3.js @@ -0,0 +1,4 @@ +var searchData= +[ + ['round_5frobin_72',['round_robin',['../struct_u_t_i_l___s_e_q___priority__t.html#a10895a689ca10b69554ba4a822329f54',1,'UTIL_SEQ_Priority_t']]] +]; diff --git a/Utilities/sequencer/html/search/variables_4.html b/Utilities/sequencer/html/search/variables_4.html new file mode 100644 index 0000000..78cc2c7 --- /dev/null +++ b/Utilities/sequencer/html/search/variables_4.html @@ -0,0 +1,30 @@ + + + + + + + + + +
    +
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    + + diff --git a/Utilities/sequencer/html/search/variables_4.js b/Utilities/sequencer/html/search/variables_4.js new file mode 100644 index 0000000..30357fb --- /dev/null +++ b/Utilities/sequencer/html/search/variables_4.js @@ -0,0 +1,5 @@ +var searchData= +[ + ['seq_5fclz_5ftable_5f4bit_73',['SEQ_clz_table_4bit',['../group___s_e_q_u_e_n_c_e_r___private__function.html#gabdb22f5d7f0704e4d2bcf415e8a02e10',1,'stm32_seq.c']]], + ['supermask_74',['SuperMask',['../group___s_e_q_u_e_n_c_e_r___private__varaible.html#ga0c890a69236d5f7438c51df3cf20c480',1,'stm32_seq.c']]] +]; diff --git a/Utilities/sequencer/html/search/variables_5.html b/Utilities/sequencer/html/search/variables_5.html new file mode 100644 index 0000000..dfa3558 --- /dev/null +++ b/Utilities/sequencer/html/search/variables_5.html @@ -0,0 +1,30 @@ + + + + + + + + + +
    +
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    +
    + +
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    +
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    + +
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    +
    + + + + + + +
    +
    STM32 Sequencer +  v1.6.0 +
    +
    +
    + + + + + + + +
    +
    + +
    +
    +
    + +
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    +
    + + +
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    +
    +Data Structures | +Macros | +Functions
    +
    +
    stm32_seq.c File Reference
    +
    +
    + +

    Simple sequencer implementation. +More...

    +
    #include "stm32_seq.h"
    +#include "utilities_conf.h"
    +
    +

    Go to the source code of this file.

    + + + + + +

    +Data Structures

    struct  UTIL_SEQ_Priority_t
     structure used to manage task scheduling More...
     
    + + + + + + + + + + + + + + + + + + + + + + + + + +

    +Macros

    #define UTIL_SEQ_ENTER_CRITICAL_SECTION_IDLE()   UTIL_SEQ_ENTER_CRITICAL_SECTION( )
     macro used to enter the critical section before calling the IDLE function More...
     
    #define UTIL_SEQ_EXIT_CRITICAL_SECTION_IDLE()   UTIL_SEQ_EXIT_CRITICAL_SECTION( )
     macro used to exit the critical section when exiting the IDLE function More...
     
    #define UTIL_SEQ_NOTASKRUNNING   (0xFFFFFFFFU)
     define to represent no task running More...
     
    #define UTIL_SEQ_NO_BIT_SET   (0U)
     define to represent no bit set inside uint32_t mapping More...
     
    #define UTIL_SEQ_ALL_BIT_SET   (~0U)
     define to represent all bits set inside uint32_t mapping More...
     
    #define UTIL_SEQ_CONF_TASK_NBR   (32)
     default number of task is default 32 (maximum), can be reduced by redefining in utilities_conf.h More...
     
    #define UTIL_SEQ_CONF_PRIO_NBR   (2)
     default value of priority number. More...
     
    #define UTIL_SEQ_MEMSET8(dest, value, size)   UTILS_MEMSET8( dest, value, size )
     default memset function. More...
     
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

    +Functions

    uint8_t SEQ_BitPosition (uint32_t Value)
     return the position of the first bit set to 1 More...
     
    void UTIL_SEQ_Init (void)
     This function initializes the sequencer resources. More...
     
    void UTIL_SEQ_DeInit (void)
     This function un-initializes the sequencer resources. More...
     
    void UTIL_SEQ_Run (UTIL_SEQ_bm_t Mask_bm)
     This function requests the sequencer to execute all pending tasks using round robin mechanism. When no task are pending, it calls UTIL_SEQ_Idle(); This function should be called in a while loop in the application. More...
     
    void UTIL_SEQ_RegTask (UTIL_SEQ_bm_t TaskId_bm, uint32_t Flags, void(*Task)(void))
     This function registers a task in the sequencer. More...
     
    void UTIL_SEQ_SetTask (UTIL_SEQ_bm_t TaskId_bm, uint32_t Task_Prio)
     This function requests a task to be executed. More...
     
    uint32_t UTIL_SEQ_IsSchedulableTask (UTIL_SEQ_bm_t TaskId_bm)
     This function checks if a task could be scheduled. More...
     
    void UTIL_SEQ_PauseTask (UTIL_SEQ_bm_t TaskId_bm)
     This function prevents a task to be called by the sequencer even when set with UTIL_SEQ_SetTask() By default, all tasks are executed by the sequencer when set with UTIL_SEQ_SetTask() When a task is paused, it is moved out from the sequencer list. More...
     
    uint32_t UTIL_SEQ_IsPauseTask (UTIL_SEQ_bm_t TaskId_bm)
     This function allows to know if the task has been put in pause. By default, all tasks are executed by the sequencer when set with UTIL_SEQ_SetTask() The exit of the pause shall be done by the function UTIL_SEQ_ResumeTask. More...
     
    void UTIL_SEQ_ResumeTask (UTIL_SEQ_bm_t TaskId_bm)
     This function allows again a task to be called by the sequencer if set with UTIL_SEQ_SetTask() This is used in relation with UTIL_SEQ_PauseTask() More...
     
    void UTIL_SEQ_SetEvt (UTIL_SEQ_bm_t EvtId_bm)
     This function sets an event that is waited with UTIL_SEQ_WaitEvt() More...
     
    void UTIL_SEQ_ClrEvt (UTIL_SEQ_bm_t EvtId_bm)
     This function may be used to clear the event before calling UTIL_SEQ_WaitEvt() This API may be useful when the UTIL_SEQ_SetEvt() is called several time to notify the same event. Due to Software Architecture where the timings are hard to control, this may be an unwanted case. More...
     
    void UTIL_SEQ_WaitEvt (UTIL_SEQ_bm_t EvtId_bm)
     This function waits for a specific event to be set. The sequencer loops UTIL_SEQ_EvtIdle() until the event is set When called recursively, it acts as a First in / Last out mechanism. The sequencer waits for the last event requested to be set even though one of the already requested event has been set. More...
     
    UTIL_SEQ_bm_t UTIL_SEQ_IsEvtPend (void)
     This function returns whether the waited event is pending or not It is useful only when the UTIL_SEQ_EvtIdle() is overloaded by the application. In that case, when the low power mode needs to be executed, the application shall first check whether the waited event is pending or not. Both the event checking and the low power mode processing should be done in critical section. More...
     
    __WEAK void UTIL_SEQ_EvtIdle (UTIL_SEQ_bm_t TaskId_bm, UTIL_SEQ_bm_t EvtWaited_bm)
     This function loops until the waited event is set. More...
     
    __WEAK void UTIL_SEQ_Idle (void)
     This function is called by the sequencer in critical section (PRIMASK bit) when. More...
     
    __WEAK void UTIL_SEQ_PreIdle (void)
     This function is called by the sequencer outside critical section just before calling UTIL_SEQ_Idle( ) UTIL_SEQ_PreIdle() is considered as the last task executed before calling UTIL_SEQ_Idle( ) In case a task or an event is set from an interrupt handler just after UTIL_SEQ_PreIdle() is called, UTIL_SEQ_Idle() will not be called. More...
     
    __WEAK void UTIL_SEQ_PostIdle (void)
     This function is called by the sequencer outside critical section either. More...
     
    +

    Detailed Description

    +

    Simple sequencer implementation.

    +
    Author
    MCD Application Team
    +
    Attention
    +

    © Copyright (c) 2019 STMicroelectronics. All rights reserved.

    +

    This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

    + +

    Definition in file stm32_seq.c.

    +
    +
    + + + + diff --git a/Utilities/sequencer/html/stm32__seq_8c.js b/Utilities/sequencer/html/stm32__seq_8c.js new file mode 100644 index 0000000..c150ced --- /dev/null +++ b/Utilities/sequencer/html/stm32__seq_8c.js @@ -0,0 +1,29 @@ +var stm32__seq_8c = +[ + [ "UTIL_SEQ_ALL_BIT_SET", "group___s_e_q_u_e_n_c_e_r___private__define.html#ga24e4c1a2fd61c0cbda16ba7f42f1703a", null ], + [ "UTIL_SEQ_CONF_PRIO_NBR", "group___s_e_q_u_e_n_c_e_r___private__define.html#ga13e13f6ac2442ffb667502a9f35df865", null ], + [ "UTIL_SEQ_CONF_TASK_NBR", "group___s_e_q_u_e_n_c_e_r___private__define.html#gaaf974b4a940fc6a921b3a76344e5c7ed", null ], + [ "UTIL_SEQ_ENTER_CRITICAL_SECTION_IDLE", "group___s_e_q_u_e_n_c_e_r___private__define.html#ga7af4785dcb8ef602f75b2d8f423010c1", null ], + [ "UTIL_SEQ_EXIT_CRITICAL_SECTION_IDLE", "group___s_e_q_u_e_n_c_e_r___private__define.html#ga2dcda5eb256d445147b385a8374cc658", null ], + [ "UTIL_SEQ_MEMSET8", "group___s_e_q_u_e_n_c_e_r___private__define.html#gad3b4f5f14f4f512725984e6da759871c", null ], + [ "UTIL_SEQ_NO_BIT_SET", "group___s_e_q_u_e_n_c_e_r___private__define.html#gad03df74638c0f274fa22474f034384bf", null ], + [ "UTIL_SEQ_NOTASKRUNNING", "group___s_e_q_u_e_n_c_e_r___private__define.html#ga9d782cdb4f3654c8238e9dd3adbabf16", null ], + [ "SEQ_BitPosition", "group___s_e_q_u_e_n_c_e_r___private__function.html#ga7dcde6efa35f7c100af9bf4117a4bf12", null ], + [ "UTIL_SEQ_ClrEvt", "group___s_e_q_u_e_n_c_e_r___exported__function.html#ga2b48c77f677158e69ff072f7c05cded4", null ], + [ "UTIL_SEQ_DeInit", "group___s_e_q_u_e_n_c_e_r___exported__function.html#ga91cceef5931daa30c4ec3a6577c11106", null ], + [ "UTIL_SEQ_EvtIdle", "group___s_e_q_u_e_n_c_e_r___exported__function.html#ga6bd90dbfc7e3515391128d1ca1739c17", null ], + [ "UTIL_SEQ_Idle", "group___s_e_q_u_e_n_c_e_r___exported__function.html#ga5efb8394fc5244b650c8cc8f642e6271", null ], + [ "UTIL_SEQ_Init", "group___s_e_q_u_e_n_c_e_r___exported__function.html#gaef07a06c105da3570c971633460a8aa5", null ], + [ "UTIL_SEQ_IsEvtPend", "group___s_e_q_u_e_n_c_e_r___exported__function.html#ga8d6c2fd6aac8b833a25602ec4b8c5fc7", null ], + [ "UTIL_SEQ_IsPauseTask", "group___s_e_q_u_e_n_c_e_r___exported__function.html#gaa177da1e5c77c8430096356181d12b18", null ], + [ "UTIL_SEQ_IsSchedulableTask", "group___s_e_q_u_e_n_c_e_r___exported__function.html#ga58bf5ad581a43e749b60a811353af558", null ], + [ "UTIL_SEQ_PauseTask", "group___s_e_q_u_e_n_c_e_r___exported__function.html#gaad482af89f56e87da251f56d98674c02", null ], + [ "UTIL_SEQ_PostIdle", "group___s_e_q_u_e_n_c_e_r___exported__function.html#ga481b45c409e4d8180c64efdef67daa7f", null ], + [ "UTIL_SEQ_PreIdle", "group___s_e_q_u_e_n_c_e_r___exported__function.html#ga373387b03a48559d58eacb919f44a799", null ], + [ "UTIL_SEQ_RegTask", "group___s_e_q_u_e_n_c_e_r___exported__function.html#gacb5ddba0d11449d470c840d0bd961c14", null ], + [ "UTIL_SEQ_ResumeTask", "group___s_e_q_u_e_n_c_e_r___exported__function.html#ga66f6a7fbff82b6d397ca054bcf9350ec", null ], + [ "UTIL_SEQ_Run", "group___s_e_q_u_e_n_c_e_r___exported__function.html#gae047669fe53f205396460fdbd3a5d8f5", null ], + [ "UTIL_SEQ_SetEvt", "group___s_e_q_u_e_n_c_e_r___exported__function.html#ga20f607dcbe03ca04f5c56a47e3cc846c", null ], + [ "UTIL_SEQ_SetTask", "group___s_e_q_u_e_n_c_e_r___exported__function.html#ga66de990da4bde412751f15a7622a0da8", null ], + [ "UTIL_SEQ_WaitEvt", "group___s_e_q_u_e_n_c_e_r___exported__function.html#ga3546ca66266d5cc956741505318723a2", null ] +]; \ No newline at end of file diff --git a/Utilities/sequencer/html/stm32__seq_8c_source.html b/Utilities/sequencer/html/stm32__seq_8c_source.html new file mode 100644 index 0000000..6132b47 --- /dev/null +++ b/Utilities/sequencer/html/stm32__seq_8c_source.html @@ -0,0 +1,537 @@ + + + + + + + +STM32 Sequencer: stm32_seq.c Source File + + + + + + + + + + + + + +
    +
    + + + + + + +
    +
    STM32 Sequencer +  v1.6.0 +
    +
    +
    + + + + + + + +
    +
    + +
    +
    +
    + +
    + +
    +
    + + +
    + +
    + +
    +
    +
    stm32_seq.c
    +
    +
    +Go to the documentation of this file.
    1 
    +
    21 /* Includes ------------------------------------------------------------------*/
    +
    22 #include "stm32_seq.h"
    +
    23 #include "utilities_conf.h"
    +
    24 
    +
    29 /* Private typedef -----------------------------------------------------------*/
    +
    37 typedef struct
    +
    38 {
    +
    39  uint32_t priority;
    +
    40  uint32_t round_robin;
    +
    41 } UTIL_SEQ_Priority_t;
    +
    42 
    +
    47 /* Private defines -----------------------------------------------------------*/
    +
    48 
    +
    60 #ifndef UTIL_SEQ_ENTER_CRITICAL_SECTION_IDLE
    +
    61  #define UTIL_SEQ_ENTER_CRITICAL_SECTION_IDLE( ) UTIL_SEQ_ENTER_CRITICAL_SECTION( )
    +
    62 #endif
    +
    63 
    +
    69 #ifndef UTIL_SEQ_EXIT_CRITICAL_SECTION_IDLE
    +
    70  #define UTIL_SEQ_EXIT_CRITICAL_SECTION_IDLE( ) UTIL_SEQ_EXIT_CRITICAL_SECTION( )
    +
    71 #endif
    +
    72 
    +
    76 #define UTIL_SEQ_NOTASKRUNNING (0xFFFFFFFFU)
    +
    77 
    +
    81 #define UTIL_SEQ_NO_BIT_SET (0U)
    +
    82 
    +
    86 #define UTIL_SEQ_ALL_BIT_SET (~0U)
    +
    87 
    +
    91 #ifndef UTIL_SEQ_CONF_TASK_NBR
    +
    92  #define UTIL_SEQ_CONF_TASK_NBR (32)
    +
    93 #endif
    +
    94 
    +
    95 #if UTIL_SEQ_CONF_TASK_NBR > 32
    +
    96 #error "UTIL_SEQ_CONF_PRIO_NBR must be less of equal then 32"
    +
    97 #endif
    +
    98 
    +
    102 #ifndef UTIL_SEQ_CONF_PRIO_NBR
    +
    103  #define UTIL_SEQ_CONF_PRIO_NBR (2)
    +
    104 #endif
    +
    105 
    +
    109 #ifndef UTIL_SEQ_MEMSET8
    +
    110 #define UTIL_SEQ_MEMSET8( dest, value, size ) UTILS_MEMSET8( dest, value, size )
    +
    111 #endif
    +
    112 
    +
    117 /* Private variables ---------------------------------------------------------*/
    +
    118 
    +
    126 static volatile UTIL_SEQ_bm_t TaskSet;
    +
    127 
    +
    131 static volatile UTIL_SEQ_bm_t TaskMask = UTIL_SEQ_ALL_BIT_SET;
    +
    132 
    +
    136 static UTIL_SEQ_bm_t SuperMask = UTIL_SEQ_ALL_BIT_SET;
    +
    137 
    +
    141 static volatile UTIL_SEQ_bm_t EvtSet = UTIL_SEQ_NO_BIT_SET;
    +
    142 
    +
    146 static volatile UTIL_SEQ_bm_t EvtWaited = UTIL_SEQ_NO_BIT_SET;
    +
    147 
    +
    151 static uint32_t CurrentTaskIdx = 0U;
    +
    152 
    +
    156 static void (*TaskCb[UTIL_SEQ_CONF_TASK_NBR])( void );
    +
    157 
    +
    161 static volatile UTIL_SEQ_Priority_t TaskPrio[UTIL_SEQ_CONF_PRIO_NBR];
    +
    162 
    +
    167 /* Private function prototypes -----------------------------------------------*/
    +
    171 uint8_t SEQ_BitPosition(uint32_t Value);
    +
    172 
    +
    177 /* Functions Definition ------------------------------------------------------*/
    +
    178 
    +
    182 void UTIL_SEQ_Init( void )
    +
    183 {
    +
    184  TaskSet = UTIL_SEQ_NO_BIT_SET;
    +
    185  TaskMask = UTIL_SEQ_ALL_BIT_SET;
    +
    186  SuperMask = UTIL_SEQ_ALL_BIT_SET;
    +
    187  EvtSet = UTIL_SEQ_NO_BIT_SET;
    +
    188  EvtWaited = UTIL_SEQ_NO_BIT_SET;
    +
    189  CurrentTaskIdx = 0U;
    +
    190  (void)UTIL_SEQ_MEMSET8((uint8_t *)TaskCb, 0, sizeof(TaskCb));
    +
    191  for(uint32_t index = 0; index < UTIL_SEQ_CONF_PRIO_NBR; index++)
    +
    192  {
    +
    193  TaskPrio[index].priority = 0;
    +
    194  TaskPrio[index].round_robin = 0;
    +
    195  }
    +
    196  UTIL_SEQ_INIT_CRITICAL_SECTION( );
    +
    197 }
    +
    198 
    +
    199 void UTIL_SEQ_DeInit( void )
    +
    200 {
    +
    201 }
    +
    202 
    +
    209 void UTIL_SEQ_Run( UTIL_SEQ_bm_t Mask_bm )
    +
    210 {
    +
    211  uint32_t counter;
    +
    212  UTIL_SEQ_bm_t current_task_set;
    +
    213  UTIL_SEQ_bm_t super_mask_backup;
    +
    214  UTIL_SEQ_bm_t local_taskset;
    +
    215  UTIL_SEQ_bm_t local_evtset;
    +
    216  UTIL_SEQ_bm_t local_taskmask;
    +
    217  UTIL_SEQ_bm_t local_evtwaited;
    +
    218 
    +
    219  /*
    +
    220  * When this function is nested, the mask to be applied cannot be larger than the first call
    +
    221  * The mask is always getting smaller and smaller
    +
    222  * A copy is made of the mask set by UTIL_SEQ_Run() in case it is called again in the task
    +
    223  */
    +
    224  super_mask_backup = SuperMask;
    +
    225  SuperMask &= Mask_bm;
    +
    226 
    +
    227  /*
    +
    228  * There are two independent mask to check:
    +
    229  * TaskMask that comes from UTIL_SEQ_PauseTask() / UTIL_SEQ_ResumeTask
    +
    230  * SuperMask that comes from UTIL_SEQ_Run
    +
    231  * If the waited event is there, exit from UTIL_SEQ_Run() to return to the
    +
    232  * waiting task
    +
    233  */
    +
    234  local_taskset = TaskSet;
    +
    235  local_evtset = EvtSet;
    +
    236  local_taskmask = TaskMask;
    +
    237  local_evtwaited = EvtWaited;
    +
    238  while(((local_taskset & local_taskmask & SuperMask) != 0U) && ((local_evtset & local_evtwaited)==0U))
    +
    239  {
    +
    240  counter = 0U;
    +
    241  /*
    +
    242  * When a flag is set, the associated bit is set in TaskPrio[counter].priority mask depending
    +
    243  * on the priority parameter given from UTIL_SEQ_SetTask()
    +
    244  * The while loop is looking for a flag set from the highest priority maskr to the lower
    +
    245  */
    +
    246  while((TaskPrio[counter].priority & local_taskmask & SuperMask)== 0U)
    +
    247  {
    +
    248  counter++;
    +
    249  }
    +
    250 
    +
    251  current_task_set = TaskPrio[counter].priority & local_taskmask & SuperMask;
    +
    252 
    +
    253  /*
    +
    254  * The round_robin register is a mask of allowed flags to be evaluated.
    +
    255  * The concept is to make sure that on each round on UTIL_SEQ_Run(), if two same flags are always set,
    +
    256  * the sequencer does not run always only the first one.
    +
    257  * When a task has been executed, The flag is removed from the round_robin mask.
    +
    258  * If on the next UTIL_SEQ_RUN(), the two same flags are set again, the round_robin mask will mask out the first flag
    +
    259  * so that the second one can be executed.
    +
    260  * Note that the first flag is not removed from the list of pending task but just masked by the round_robin mask
    +
    261  *
    +
    262  * In the check below, the round_robin mask is reinitialize in case all pending tasks haven been executed at least once
    +
    263  */
    +
    264  if ((TaskPrio[counter].round_robin & current_task_set) == 0U)
    +
    265  {
    +
    266  TaskPrio[counter].round_robin = UTIL_SEQ_ALL_BIT_SET;
    +
    267  }
    +
    268 
    +
    269  /*
    +
    270  * Read the flag index of the task to be executed
    +
    271  * Once the index is read, the associated task will be executed even though a higher priority stack is requested
    +
    272  * before task execution.
    +
    273  */
    +
    274  CurrentTaskIdx = (SEQ_BitPosition(current_task_set & TaskPrio[counter].round_robin));
    +
    275 
    +
    276  /*
    +
    277  * remove from the roun_robin mask the task that has been selected to be executed
    +
    278  */
    +
    279  TaskPrio[counter].round_robin &= ~(1U << CurrentTaskIdx);
    +
    280 
    +
    281  UTIL_SEQ_ENTER_CRITICAL_SECTION( );
    +
    282  /* remove from the list or pending task the one that has been selected to be executed */
    +
    283  TaskSet &= ~(1U << CurrentTaskIdx);
    +
    284  /* remove from all priority mask the task that has been selected to be executed */
    +
    285  for (counter = UTIL_SEQ_CONF_PRIO_NBR; counter != 0U; counter--)
    +
    286  {
    +
    287  TaskPrio[counter - 1U].priority &= ~(1U << CurrentTaskIdx);
    +
    288  }
    +
    289  UTIL_SEQ_EXIT_CRITICAL_SECTION( );
    +
    290 
    +
    291  /* Execute the task */
    +
    292  TaskCb[CurrentTaskIdx]( );
    +
    293 
    +
    294  local_taskset = TaskSet;
    +
    295  local_evtset = EvtSet;
    +
    296  local_taskmask = TaskMask;
    +
    297  local_evtwaited = EvtWaited;
    +
    298  }
    +
    299 
    +
    300  /* the set of CurrentTaskIdx to no task running allows to call WaitEvt in the Pre/Post ilde context */
    +
    301  CurrentTaskIdx = UTIL_SEQ_NOTASKRUNNING;
    +
    302  UTIL_SEQ_PreIdle( );
    +
    303 
    +
    304  UTIL_SEQ_ENTER_CRITICAL_SECTION_IDLE( );
    +
    305  local_taskset = TaskSet;
    +
    306  local_evtset = EvtSet;
    +
    307  local_taskmask = TaskMask;
    +
    308  if ((local_taskset & local_taskmask & SuperMask) == 0U)
    +
    309  {
    +
    310  if ((local_evtset & EvtWaited)== 0U)
    +
    311  {
    +
    312  UTIL_SEQ_Idle( );
    +
    313  }
    +
    314  }
    +
    315  UTIL_SEQ_EXIT_CRITICAL_SECTION_IDLE( );
    +
    316 
    +
    317  UTIL_SEQ_PostIdle( );
    +
    318 
    +
    319  /* restore the mask from UTIL_SEQ_Run() */
    +
    320  SuperMask = super_mask_backup;
    +
    321 
    +
    322  return;
    +
    323 }
    +
    324 
    +
    325 void UTIL_SEQ_RegTask(UTIL_SEQ_bm_t TaskId_bm, uint32_t Flags, void (*Task)( void ))
    +
    326 {
    +
    327  (void)Flags;
    +
    328  UTIL_SEQ_ENTER_CRITICAL_SECTION();
    +
    329 
    +
    330  TaskCb[SEQ_BitPosition(TaskId_bm)] = Task;
    +
    331 
    +
    332  UTIL_SEQ_EXIT_CRITICAL_SECTION();
    +
    333 
    +
    334  return;
    +
    335 }
    +
    336 
    +
    337 void UTIL_SEQ_SetTask( UTIL_SEQ_bm_t TaskId_bm , uint32_t Task_Prio )
    +
    338 {
    +
    339  UTIL_SEQ_ENTER_CRITICAL_SECTION( );
    +
    340 
    +
    341  TaskSet |= TaskId_bm;
    +
    342  TaskPrio[Task_Prio].priority |= TaskId_bm;
    +
    343 
    +
    344  UTIL_SEQ_EXIT_CRITICAL_SECTION( );
    +
    345 
    +
    346  return;
    +
    347 }
    +
    348 
    +
    349 uint32_t UTIL_SEQ_IsSchedulableTask( UTIL_SEQ_bm_t TaskId_bm)
    +
    350 {
    +
    351  uint32_t _status;
    +
    352  UTIL_SEQ_bm_t local_taskset;
    +
    353 
    +
    354  UTIL_SEQ_ENTER_CRITICAL_SECTION();
    +
    355 
    +
    356  local_taskset = TaskSet;
    +
    357  _status = ((local_taskset & TaskMask & SuperMask & TaskId_bm) == TaskId_bm)? 1U: 0U;
    +
    358 
    +
    359  UTIL_SEQ_EXIT_CRITICAL_SECTION();
    +
    360  return _status;
    +
    361 }
    +
    362 
    +
    363 void UTIL_SEQ_PauseTask( UTIL_SEQ_bm_t TaskId_bm )
    +
    364 {
    +
    365  UTIL_SEQ_ENTER_CRITICAL_SECTION( );
    +
    366 
    +
    367  TaskMask &= (~TaskId_bm);
    +
    368 
    +
    369  UTIL_SEQ_EXIT_CRITICAL_SECTION( );
    +
    370 
    +
    371  return;
    +
    372 }
    +
    373 
    +
    374 uint32_t UTIL_SEQ_IsPauseTask( UTIL_SEQ_bm_t TaskId_bm )
    +
    375 {
    +
    376  uint32_t _status;
    +
    377  UTIL_SEQ_ENTER_CRITICAL_SECTION( );
    +
    378 
    +
    379  _status = ((TaskMask & TaskId_bm) == TaskId_bm) ? 0u:1u;
    +
    380 
    +
    381  UTIL_SEQ_EXIT_CRITICAL_SECTION( );
    +
    382  return _status;
    +
    383 }
    +
    384 
    +
    385 void UTIL_SEQ_ResumeTask( UTIL_SEQ_bm_t TaskId_bm )
    +
    386 {
    +
    387  UTIL_SEQ_ENTER_CRITICAL_SECTION( );
    +
    388 
    +
    389  TaskMask |= TaskId_bm;
    +
    390 
    +
    391  UTIL_SEQ_EXIT_CRITICAL_SECTION( );
    +
    392 
    +
    393  return;
    +
    394 }
    +
    395 
    +
    396 void UTIL_SEQ_SetEvt( UTIL_SEQ_bm_t EvtId_bm )
    +
    397 {
    +
    398  UTIL_SEQ_ENTER_CRITICAL_SECTION( );
    +
    399 
    +
    400  EvtSet |= EvtId_bm;
    +
    401 
    +
    402  UTIL_SEQ_EXIT_CRITICAL_SECTION( );
    +
    403 
    +
    404  return;
    +
    405 }
    +
    406 
    +
    407 void UTIL_SEQ_ClrEvt( UTIL_SEQ_bm_t EvtId_bm )
    +
    408 {
    +
    409  UTIL_SEQ_ENTER_CRITICAL_SECTION( );
    +
    410 
    +
    411  EvtSet &= (~EvtId_bm);
    +
    412 
    +
    413  UTIL_SEQ_EXIT_CRITICAL_SECTION( );
    +
    414 
    +
    415  return;
    +
    416 }
    +
    417 
    +
    418 void UTIL_SEQ_WaitEvt(UTIL_SEQ_bm_t EvtId_bm)
    +
    419 {
    +
    420  UTIL_SEQ_bm_t event_waited_id_backup;
    +
    421  UTIL_SEQ_bm_t current_task_idx;
    +
    422  UTIL_SEQ_bm_t wait_task_idx;
    +
    423  /*
    +
    424  * store in local the current_task_id_bm as the global variable CurrentTaskIdx
    +
    425  * may be overwritten in case there are nested call of UTIL_SEQ_Run()
    +
    426  */
    +
    427  current_task_idx = CurrentTaskIdx;
    +
    428  if(UTIL_SEQ_NOTASKRUNNING == CurrentTaskIdx)
    +
    429  {
    +
    430  wait_task_idx = 0u;
    +
    431  }
    +
    432  else
    +
    433  {
    +
    434  wait_task_idx = (uint32_t)1u << CurrentTaskIdx;
    +
    435  }
    +
    436 
    +
    437  /* backup the event id that was currently waited */
    +
    438  event_waited_id_backup = EvtWaited;
    +
    439  EvtWaited = EvtId_bm;
    +
    440  /*
    +
    441  * wait for the new event
    +
    442  * note: that means that if the previous waited event occurs, it will not exit
    +
    443  * the while loop below.
    +
    444  * The system is waiting only for the last waited event.
    +
    445  * When it will go out, it will wait again from the previous one.
    +
    446  * It case it occurs while waiting for the second one, the while loop will exit immediately
    +
    447  */
    +
    448 
    +
    449  while ((EvtSet & EvtId_bm) == 0U)
    +
    450  {
    +
    451  UTIL_SEQ_EvtIdle(wait_task_idx, EvtId_bm);
    +
    452  }
    +
    453 
    +
    454  /*
    +
    455  * Restore the CurrentTaskIdx that may have been modified by call of UTIL_SEQ_Run() from UTIL_SEQ_EvtIdle()
    +
    456  * This is required so that a second call of UTIL_SEQ_WaitEvt() in the same process pass the correct current_task_id_bm
    +
    457  * in the call of UTIL_SEQ_EvtIdle()
    +
    458  */
    +
    459  CurrentTaskIdx = current_task_idx;
    +
    460 
    +
    461  UTIL_SEQ_ENTER_CRITICAL_SECTION( );
    +
    462 
    +
    463  EvtSet &= (~EvtId_bm);
    +
    464 
    +
    465  UTIL_SEQ_EXIT_CRITICAL_SECTION( );
    +
    466 
    +
    467  EvtWaited = event_waited_id_backup;
    +
    468  return;
    +
    469 }
    +
    470 
    +
    471 UTIL_SEQ_bm_t UTIL_SEQ_IsEvtPend( void )
    +
    472 {
    +
    473  UTIL_SEQ_bm_t local_evtwaited = EvtWaited;
    +
    474  return (EvtSet & local_evtwaited);
    +
    475 }
    +
    476 
    +
    477 __WEAK void UTIL_SEQ_EvtIdle( UTIL_SEQ_bm_t TaskId_bm, UTIL_SEQ_bm_t EvtWaited_bm )
    +
    478 {
    +
    479  (void)EvtWaited_bm;
    +
    480  UTIL_SEQ_Run(~TaskId_bm);
    +
    481  return;
    +
    482 }
    +
    483 
    +
    484 __WEAK void UTIL_SEQ_Idle( void )
    +
    485 {
    +
    486  return;
    +
    487 }
    +
    488 
    +
    489 __WEAK void UTIL_SEQ_PreIdle( void )
    +
    490 {
    +
    491  /*
    +
    492  * Unless specified by the application, there is nothing to be done
    +
    493  */
    +
    494  return;
    +
    495 }
    +
    496 
    +
    497 __WEAK void UTIL_SEQ_PostIdle( void )
    +
    498 {
    +
    499  /*
    +
    500  * Unless specified by the application, there is nothing to be done
    +
    501  */
    +
    502  return;
    +
    503 }
    +
    504 
    +
    513 #if( __CORTEX_M == 0)
    +
    519 uint8_t SEQ_BitPosition(uint32_t Value)
    +
    520 {
    +
    521 static const uint8_t SEQ_clz_table_4bit[16] = { 4U, 3U, 2U, 2U, 1U, 1U, 1U, 1U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U };
    +
    522 uint8_t n = 0U;
    +
    523 uint32_t lvalue = Value;
    +
    524 
    +
    525  if ((lvalue & 0xFFFF0000U) == 0U) { n = 16U; lvalue <<= 16U; }
    +
    526  if ((lvalue & 0xFF000000U) == 0U) { n += 8U; lvalue <<= 8U; }
    +
    527  if ((lvalue & 0xF0000000U) == 0U) { n += 4U; lvalue <<= 4U; }
    +
    528 
    +
    529  n += SEQ_clz_table_4bit[lvalue >> (32-4)];
    +
    530 
    +
    531  return (uint8_t)(31U-n);
    +
    532 }
    +
    533 #else
    +
    539 uint8_t SEQ_BitPosition(uint32_t Value)
    +
    540 {
    +
    541  return (uint8_t)(31 -__CLZ( Value ));
    +
    542 }
    +
    543 #endif
    +
    544 
    +
    553 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
    +
    UTIL_SEQ_SetEvt
    void UTIL_SEQ_SetEvt(UTIL_SEQ_bm_t EvtId_bm)
    This function sets an event that is waited with UTIL_SEQ_WaitEvt()
    Definition: stm32_seq.c:396
    +
    UTIL_SEQ_ClrEvt
    void UTIL_SEQ_ClrEvt(UTIL_SEQ_bm_t EvtId_bm)
    This function may be used to clear the event before calling UTIL_SEQ_WaitEvt() This API may be useful...
    Definition: stm32_seq.c:407
    +
    UTIL_SEQ_WaitEvt
    void UTIL_SEQ_WaitEvt(UTIL_SEQ_bm_t EvtId_bm)
    This function waits for a specific event to be set. The sequencer loops UTIL_SEQ_EvtIdle() until the ...
    Definition: stm32_seq.c:418
    +
    UTIL_SEQ_PreIdle
    __WEAK void UTIL_SEQ_PreIdle(void)
    This function is called by the sequencer outside critical section just before calling UTIL_SEQ_Idle( ...
    Definition: stm32_seq.c:489
    +
    UTIL_SEQ_PostIdle
    __WEAK void UTIL_SEQ_PostIdle(void)
    This function is called by the sequencer outside critical section either.
    Definition: stm32_seq.c:497
    +
    UTIL_SEQ_IsSchedulableTask
    uint32_t UTIL_SEQ_IsSchedulableTask(UTIL_SEQ_bm_t TaskId_bm)
    This function checks if a task could be scheduled.
    Definition: stm32_seq.c:349
    +
    UTIL_SEQ_Idle
    __WEAK void UTIL_SEQ_Idle(void)
    This function is called by the sequencer in critical section (PRIMASK bit) when.
    Definition: stm32_seq.c:484
    +
    UTIL_SEQ_SetTask
    void UTIL_SEQ_SetTask(UTIL_SEQ_bm_t TaskId_bm, uint32_t Task_Prio)
    This function requests a task to be executed.
    Definition: stm32_seq.c:337
    +
    UTIL_SEQ_ResumeTask
    void UTIL_SEQ_ResumeTask(UTIL_SEQ_bm_t TaskId_bm)
    This function allows again a task to be called by the sequencer if set with UTIL_SEQ_SetTask() This i...
    Definition: stm32_seq.c:385
    +
    UTIL_SEQ_EvtIdle
    __WEAK void UTIL_SEQ_EvtIdle(UTIL_SEQ_bm_t TaskId_bm, UTIL_SEQ_bm_t EvtWaited_bm)
    This function loops until the waited event is set.
    Definition: stm32_seq.c:477
    +
    UTIL_SEQ_IsEvtPend
    UTIL_SEQ_bm_t UTIL_SEQ_IsEvtPend(void)
    This function returns whether the waited event is pending or not It is useful only when the UTIL_SEQ_...
    Definition: stm32_seq.c:471
    +
    UTIL_SEQ_DeInit
    void UTIL_SEQ_DeInit(void)
    This function un-initializes the sequencer resources.
    Definition: stm32_seq.c:199
    +
    UTIL_SEQ_IsPauseTask
    uint32_t UTIL_SEQ_IsPauseTask(UTIL_SEQ_bm_t TaskId_bm)
    This function allows to know if the task has been put in pause. By default, all tasks are executed by...
    Definition: stm32_seq.c:374
    +
    UTIL_SEQ_PauseTask
    void UTIL_SEQ_PauseTask(UTIL_SEQ_bm_t TaskId_bm)
    This function prevents a task to be called by the sequencer even when set with UTIL_SEQ_SetTask() By ...
    Definition: stm32_seq.c:363
    +
    UTIL_SEQ_RegTask
    void UTIL_SEQ_RegTask(UTIL_SEQ_bm_t TaskId_bm, uint32_t Flags, void(*Task)(void))
    This function registers a task in the sequencer.
    Definition: stm32_seq.c:325
    +
    UTIL_SEQ_Run
    void UTIL_SEQ_Run(UTIL_SEQ_bm_t Mask_bm)
    This function requests the sequencer to execute all pending tasks using round robin mechanism....
    Definition: stm32_seq.c:209
    +
    UTIL_SEQ_Init
    void UTIL_SEQ_Init(void)
    This function initializes the sequencer resources.
    Definition: stm32_seq.c:182
    +
    UTIL_SEQ_bm_t
    uint32_t UTIL_SEQ_bm_t
    bit mapping of the task. this value is used to represent a list of task (each corresponds to a task).
    Definition: stm32_seq.h:45
    +
    UTIL_SEQ_CONF_PRIO_NBR
    #define UTIL_SEQ_CONF_PRIO_NBR
    default value of priority number.
    Definition: stm32_seq.c:103
    +
    UTIL_SEQ_ALL_BIT_SET
    #define UTIL_SEQ_ALL_BIT_SET
    define to represent all bits set inside uint32_t mapping
    Definition: stm32_seq.c:86
    +
    UTIL_SEQ_EXIT_CRITICAL_SECTION_IDLE
    #define UTIL_SEQ_EXIT_CRITICAL_SECTION_IDLE()
    macro used to exit the critical section when exiting the IDLE function
    Definition: stm32_seq.c:70
    +
    UTIL_SEQ_ENTER_CRITICAL_SECTION_IDLE
    #define UTIL_SEQ_ENTER_CRITICAL_SECTION_IDLE()
    macro used to enter the critical section before calling the IDLE function
    Definition: stm32_seq.c:61
    +
    UTIL_SEQ_NOTASKRUNNING
    #define UTIL_SEQ_NOTASKRUNNING
    define to represent no task running
    Definition: stm32_seq.c:76
    +
    UTIL_SEQ_CONF_TASK_NBR
    #define UTIL_SEQ_CONF_TASK_NBR
    default number of task is default 32 (maximum), can be reduced by redefining in utilities_conf....
    Definition: stm32_seq.c:92
    +
    UTIL_SEQ_NO_BIT_SET
    #define UTIL_SEQ_NO_BIT_SET
    define to represent no bit set inside uint32_t mapping
    Definition: stm32_seq.c:81
    +
    UTIL_SEQ_MEMSET8
    #define UTIL_SEQ_MEMSET8(dest, value, size)
    default memset function.
    Definition: stm32_seq.c:110
    +
    SEQ_BitPosition
    uint8_t SEQ_BitPosition(uint32_t Value)
    return the position of the first bit set to 1
    Definition: stm32_seq.c:519
    +
    stm32_seq.h
    sequencer interface
    +
    UTIL_SEQ_Priority_t
    structure used to manage task scheduling
    Definition: stm32_seq.c:38
    +
    UTIL_SEQ_Priority_t::round_robin
    uint32_t round_robin
    Definition: stm32_seq.c:40
    +
    UTIL_SEQ_Priority_t::priority
    uint32_t priority
    Definition: stm32_seq.c:39
    +
    +
    + + + + diff --git a/Utilities/sequencer/html/stm32__seq_8h.html b/Utilities/sequencer/html/stm32__seq_8h.html new file mode 100644 index 0000000..9dbadf1 --- /dev/null +++ b/Utilities/sequencer/html/stm32__seq_8h.html @@ -0,0 +1,193 @@ + + + + + + + +STM32 Sequencer: stm32_seq.h File Reference + + + + + + + + + + + + + +
    +
    + + + + + + +
    +
    STM32 Sequencer +  v1.6.0 +
    +
    +
    + + + + + + + +
    +
    + +
    +
    +
    + +
    + +
    +
    + + +
    + +
    + +
    +
    +Macros | +Typedefs | +Functions
    +
    +
    stm32_seq.h File Reference
    +
    +
    + +

    sequencer interface +More...

    +
    #include "stdint.h"
    +
    +

    Go to the source code of this file.

    + + + + + + + + + + + + + + +

    +Macros

    #define UTIL_SEQ_RFU   0
     This provides a default value for unused parameter. More...
     
    #define UTIL_SEQ_DEFAULT   (~0U)
     Default value used to start the scheduling. More...
     
    #define UTIL_SEQ_TaskParamDef(_FUNC_, _PARAM_VAL_)
     This macro can be used to define a task with one parameter. More...
     
    #define UTIL_SEQ_TaskFunction(_FUNC_, _PARAM_VAL_)   SEQ_FUNC_##_FUNC_##_PARAM_VAL_
     This macro is used to retrieve the function name of the task. More...
     
    + + + + +

    +Typedefs

    typedef uint32_t UTIL_SEQ_bm_t
     bit mapping of the task. this value is used to represent a list of task (each corresponds to a task). More...
     
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

    +Functions

    void UTIL_SEQ_Init (void)
     This function initializes the sequencer resources. More...
     
    void UTIL_SEQ_DeInit (void)
     This function un-initializes the sequencer resources. More...
     
    __WEAK void UTIL_SEQ_Idle (void)
     This function is called by the sequencer in critical section (PRIMASK bit) when. More...
     
    __WEAK void UTIL_SEQ_PreIdle (void)
     This function is called by the sequencer outside critical section just before calling UTIL_SEQ_Idle( ) UTIL_SEQ_PreIdle() is considered as the last task executed before calling UTIL_SEQ_Idle( ) In case a task or an event is set from an interrupt handler just after UTIL_SEQ_PreIdle() is called, UTIL_SEQ_Idle() will not be called. More...
     
    __WEAK void UTIL_SEQ_PostIdle (void)
     This function is called by the sequencer outside critical section either. More...
     
    void UTIL_SEQ_Run (UTIL_SEQ_bm_t Mask_bm)
     This function requests the sequencer to execute all pending tasks using round robin mechanism. When no task are pending, it calls UTIL_SEQ_Idle(); This function should be called in a while loop in the application. More...
     
    void UTIL_SEQ_RegTask (UTIL_SEQ_bm_t TaskId_bm, uint32_t Flags, void(*Task)(void))
     This function registers a task in the sequencer. More...
     
    void UTIL_SEQ_SetTask (UTIL_SEQ_bm_t TaskId_bm, uint32_t Task_Prio)
     This function requests a task to be executed. More...
     
    uint32_t UTIL_SEQ_IsSchedulableTask (UTIL_SEQ_bm_t TaskId_bm)
     This function checks if a task could be scheduled. More...
     
    void UTIL_SEQ_PauseTask (UTIL_SEQ_bm_t TaskId_bm)
     This function prevents a task to be called by the sequencer even when set with UTIL_SEQ_SetTask() By default, all tasks are executed by the sequencer when set with UTIL_SEQ_SetTask() When a task is paused, it is moved out from the sequencer list. More...
     
    uint32_t UTIL_SEQ_IsPauseTask (UTIL_SEQ_bm_t TaskId_bm)
     This function allows to know if the task has been put in pause. By default, all tasks are executed by the sequencer when set with UTIL_SEQ_SetTask() The exit of the pause shall be done by the function UTIL_SEQ_ResumeTask. More...
     
    void UTIL_SEQ_ResumeTask (UTIL_SEQ_bm_t TaskId_bm)
     This function allows again a task to be called by the sequencer if set with UTIL_SEQ_SetTask() This is used in relation with UTIL_SEQ_PauseTask() More...
     
    void UTIL_SEQ_SetEvt (UTIL_SEQ_bm_t EvtId_bm)
     This function sets an event that is waited with UTIL_SEQ_WaitEvt() More...
     
    void UTIL_SEQ_ClrEvt (UTIL_SEQ_bm_t EvtId_bm)
     This function may be used to clear the event before calling UTIL_SEQ_WaitEvt() This API may be useful when the UTIL_SEQ_SetEvt() is called several time to notify the same event. Due to Software Architecture where the timings are hard to control, this may be an unwanted case. More...
     
    void UTIL_SEQ_WaitEvt (UTIL_SEQ_bm_t EvtId_bm)
     This function waits for a specific event to be set. The sequencer loops UTIL_SEQ_EvtIdle() until the event is set When called recursively, it acts as a First in / Last out mechanism. The sequencer waits for the last event requested to be set even though one of the already requested event has been set. More...
     
    UTIL_SEQ_bm_t UTIL_SEQ_IsEvtPend (void)
     This function returns whether the waited event is pending or not It is useful only when the UTIL_SEQ_EvtIdle() is overloaded by the application. In that case, when the low power mode needs to be executed, the application shall first check whether the waited event is pending or not. Both the event checking and the low power mode processing should be done in critical section. More...
     
    __WEAK void UTIL_SEQ_EvtIdle (UTIL_SEQ_bm_t TaskId_bm, UTIL_SEQ_bm_t EvtWaited_bm)
     This function loops until the waited event is set. More...
     
    +

    Detailed Description

    +

    sequencer interface

    +
    Author
    MCD Application Team
    +
    Attention
    +

    © Copyright (c) 2019 STMicroelectronics. All rights reserved.

    +

    This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

    + +

    Definition in file stm32_seq.h.

    +
    +
    + + + + diff --git a/Utilities/sequencer/html/stm32__seq_8h.js b/Utilities/sequencer/html/stm32__seq_8h.js new file mode 100644 index 0000000..e44baef --- /dev/null +++ b/Utilities/sequencer/html/stm32__seq_8h.js @@ -0,0 +1,25 @@ +var stm32__seq_8h = +[ + [ "UTIL_SEQ_DEFAULT", "group___s_e_q_u_e_n_c_e_r___exported__const.html#ga46541edfe05cb5082dec927f2bcf7b46", null ], + [ "UTIL_SEQ_RFU", "group___s_e_q_u_e_n_c_e_r___exported__const.html#ga44641e680786c27986945f4d0589c83a", null ], + [ "UTIL_SEQ_TaskFunction", "group___s_e_q_u_e_n_c_e_r___exported__macro.html#gac4b0290fac7278810aa24b9be4574da1", null ], + [ "UTIL_SEQ_TaskParamDef", "group___s_e_q_u_e_n_c_e_r___exported__macro.html#ga99985a546d3297b5fd8ace7f5f045c14", null ], + [ "UTIL_SEQ_bm_t", "group___s_e_q_u_e_n_c_e_r___exported__type.html#gaf1d37385aa3a7ce76c48447ba7dd5707", null ], + [ "UTIL_SEQ_ClrEvt", "group___s_e_q_u_e_n_c_e_r___exported__function.html#ga2b48c77f677158e69ff072f7c05cded4", null ], + [ "UTIL_SEQ_DeInit", "group___s_e_q_u_e_n_c_e_r___exported__function.html#ga91cceef5931daa30c4ec3a6577c11106", null ], + [ "UTIL_SEQ_EvtIdle", "group___s_e_q_u_e_n_c_e_r___exported__function.html#ga6bd90dbfc7e3515391128d1ca1739c17", null ], + [ "UTIL_SEQ_Idle", "group___s_e_q_u_e_n_c_e_r___exported__function.html#ga5efb8394fc5244b650c8cc8f642e6271", null ], + [ "UTIL_SEQ_Init", "group___s_e_q_u_e_n_c_e_r___exported__function.html#gaef07a06c105da3570c971633460a8aa5", null ], + [ "UTIL_SEQ_IsEvtPend", "group___s_e_q_u_e_n_c_e_r___exported__function.html#ga8d6c2fd6aac8b833a25602ec4b8c5fc7", null ], + [ "UTIL_SEQ_IsPauseTask", "group___s_e_q_u_e_n_c_e_r___exported__function.html#gaa177da1e5c77c8430096356181d12b18", null ], + [ "UTIL_SEQ_IsSchedulableTask", "group___s_e_q_u_e_n_c_e_r___exported__function.html#ga58bf5ad581a43e749b60a811353af558", null ], + [ "UTIL_SEQ_PauseTask", "group___s_e_q_u_e_n_c_e_r___exported__function.html#gaad482af89f56e87da251f56d98674c02", null ], + [ "UTIL_SEQ_PostIdle", "group___s_e_q_u_e_n_c_e_r___exported__function.html#ga481b45c409e4d8180c64efdef67daa7f", null ], + [ "UTIL_SEQ_PreIdle", "group___s_e_q_u_e_n_c_e_r___exported__function.html#ga373387b03a48559d58eacb919f44a799", null ], + [ "UTIL_SEQ_RegTask", "group___s_e_q_u_e_n_c_e_r___exported__function.html#gacb5ddba0d11449d470c840d0bd961c14", null ], + [ "UTIL_SEQ_ResumeTask", "group___s_e_q_u_e_n_c_e_r___exported__function.html#ga66f6a7fbff82b6d397ca054bcf9350ec", null ], + [ "UTIL_SEQ_Run", "group___s_e_q_u_e_n_c_e_r___exported__function.html#gae047669fe53f205396460fdbd3a5d8f5", null ], + [ "UTIL_SEQ_SetEvt", "group___s_e_q_u_e_n_c_e_r___exported__function.html#ga20f607dcbe03ca04f5c56a47e3cc846c", null ], + [ "UTIL_SEQ_SetTask", "group___s_e_q_u_e_n_c_e_r___exported__function.html#ga66de990da4bde412751f15a7622a0da8", null ], + [ "UTIL_SEQ_WaitEvt", "group___s_e_q_u_e_n_c_e_r___exported__function.html#ga3546ca66266d5cc956741505318723a2", null ] +]; \ No newline at end of file diff --git a/Utilities/sequencer/html/stm32__seq_8h_source.html b/Utilities/sequencer/html/stm32__seq_8h_source.html new file mode 100644 index 0000000..400609f --- /dev/null +++ b/Utilities/sequencer/html/stm32__seq_8h_source.html @@ -0,0 +1,194 @@ + + + + + + + +STM32 Sequencer: stm32_seq.h Source File + + + + + + + + + + + + + +
    +
    + + + + + + +
    +
    STM32 Sequencer +  v1.6.0 +
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    +
    stm32_seq.h
    +
    +
    +Go to the documentation of this file.
    1 
    +
    21 /* Define to prevent recursive inclusion -------------------------------------*/
    +
    22 #ifndef STM32_SEQ_H
    +
    23 #define STM32_SEQ_H
    +
    24 
    +
    25 #ifdef __cplusplus
    +
    26 extern "C" {
    +
    27 #endif
    +
    28 
    +
    29 /* Includes ------------------------------------------------------------------*/
    +
    30 #include "stdint.h"
    +
    31 
    +
    36 /* Exported types ------------------------------------------------------------*/
    +
    45 typedef uint32_t UTIL_SEQ_bm_t;
    +
    46 
    +
    51 /* Exported constants --------------------------------------------------------*/
    +
    52 
    +
    61 #define UTIL_SEQ_RFU 0
    +
    62 
    +
    76 #define UTIL_SEQ_DEFAULT (~0U)
    +
    77 
    +
    82 /* External variables --------------------------------------------------------*/
    +
    83 /* Exported macros -----------------------------------------------------------*/
    +
    84 
    +
    113 #define UTIL_SEQ_TaskParamDef(_FUNC_,_PARAM_VAL_) \
    +
    114  static void SEQ_FUNC_##_FUNC_##_PARAM_VAL_(void); \
    +
    115  static void SEQ_FUNC_##_FUNC_##_PARAM_VAL_(void) \
    +
    116  { \
    +
    117  static void *SEQ_PARAM_##_FUNC_ = (void*)&_PARAM_VAL_;\
    +
    118  _FUNC_(SEQ_PARAM_##_FUNC_); \
    +
    119  }
    +
    120 
    +
    124 #define UTIL_SEQ_TaskFunction(_FUNC_,_PARAM_VAL_) SEQ_FUNC_##_FUNC_##_PARAM_VAL_
    +
    125 
    +
    130 /* Exported functions ------------------------------------------------------- */
    +
    131 
    +
    142 void UTIL_SEQ_Init( void );
    +
    143 
    +
    150 void UTIL_SEQ_DeInit( void );
    +
    151 
    +
    162 void UTIL_SEQ_Idle( void );
    +
    163 
    +
    173 void UTIL_SEQ_PreIdle( void );
    +
    174 
    +
    186 void UTIL_SEQ_PostIdle( void );
    +
    187 
    +
    201 void UTIL_SEQ_Run( UTIL_SEQ_bm_t Mask_bm );
    +
    202 
    +
    213 void UTIL_SEQ_RegTask( UTIL_SEQ_bm_t TaskId_bm, uint32_t Flags, void (*Task)( void ) );
    +
    214 
    +
    228 void UTIL_SEQ_SetTask( UTIL_SEQ_bm_t TaskId_bm , uint32_t Task_Prio );
    +
    229 
    +
    240 uint32_t UTIL_SEQ_IsSchedulableTask( UTIL_SEQ_bm_t TaskId_bm);
    +
    241 
    +
    253 void UTIL_SEQ_PauseTask( UTIL_SEQ_bm_t TaskId_bm );
    +
    254 
    +
    266 uint32_t UTIL_SEQ_IsPauseTask( UTIL_SEQ_bm_t TaskId_bm );
    +
    267 
    +
    278 void UTIL_SEQ_ResumeTask( UTIL_SEQ_bm_t TaskId_bm );
    +
    279 
    +
    289 void UTIL_SEQ_SetEvt( UTIL_SEQ_bm_t EvtId_bm );
    +
    290 
    +
    302 void UTIL_SEQ_ClrEvt( UTIL_SEQ_bm_t EvtId_bm );
    +
    303 
    +
    317 void UTIL_SEQ_WaitEvt( UTIL_SEQ_bm_t EvtId_bm );
    +
    318 
    +
    330 UTIL_SEQ_bm_t UTIL_SEQ_IsEvtPend( void );
    +
    331 
    +
    346 void UTIL_SEQ_EvtIdle( UTIL_SEQ_bm_t TaskId_bm, UTIL_SEQ_bm_t EvtWaited_bm );
    +
    347 
    +
    356 #ifdef __cplusplus
    +
    357 }
    +
    358 #endif
    +
    359 
    +
    360 #endif /*__STM32_SEQ_H */
    +
    361 
    +
    362 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
    +
    UTIL_SEQ_SetEvt
    void UTIL_SEQ_SetEvt(UTIL_SEQ_bm_t EvtId_bm)
    This function sets an event that is waited with UTIL_SEQ_WaitEvt()
    Definition: stm32_seq.c:396
    +
    UTIL_SEQ_ClrEvt
    void UTIL_SEQ_ClrEvt(UTIL_SEQ_bm_t EvtId_bm)
    This function may be used to clear the event before calling UTIL_SEQ_WaitEvt() This API may be useful...
    Definition: stm32_seq.c:407
    +
    UTIL_SEQ_WaitEvt
    void UTIL_SEQ_WaitEvt(UTIL_SEQ_bm_t EvtId_bm)
    This function waits for a specific event to be set. The sequencer loops UTIL_SEQ_EvtIdle() until the ...
    Definition: stm32_seq.c:418
    +
    UTIL_SEQ_PreIdle
    __WEAK void UTIL_SEQ_PreIdle(void)
    This function is called by the sequencer outside critical section just before calling UTIL_SEQ_Idle( ...
    Definition: stm32_seq.c:489
    +
    UTIL_SEQ_PostIdle
    __WEAK void UTIL_SEQ_PostIdle(void)
    This function is called by the sequencer outside critical section either.
    Definition: stm32_seq.c:497
    +
    UTIL_SEQ_IsSchedulableTask
    uint32_t UTIL_SEQ_IsSchedulableTask(UTIL_SEQ_bm_t TaskId_bm)
    This function checks if a task could be scheduled.
    Definition: stm32_seq.c:349
    +
    UTIL_SEQ_Idle
    __WEAK void UTIL_SEQ_Idle(void)
    This function is called by the sequencer in critical section (PRIMASK bit) when.
    Definition: stm32_seq.c:484
    +
    UTIL_SEQ_SetTask
    void UTIL_SEQ_SetTask(UTIL_SEQ_bm_t TaskId_bm, uint32_t Task_Prio)
    This function requests a task to be executed.
    Definition: stm32_seq.c:337
    +
    UTIL_SEQ_ResumeTask
    void UTIL_SEQ_ResumeTask(UTIL_SEQ_bm_t TaskId_bm)
    This function allows again a task to be called by the sequencer if set with UTIL_SEQ_SetTask() This i...
    Definition: stm32_seq.c:385
    +
    UTIL_SEQ_EvtIdle
    __WEAK void UTIL_SEQ_EvtIdle(UTIL_SEQ_bm_t TaskId_bm, UTIL_SEQ_bm_t EvtWaited_bm)
    This function loops until the waited event is set.
    Definition: stm32_seq.c:477
    +
    UTIL_SEQ_IsEvtPend
    UTIL_SEQ_bm_t UTIL_SEQ_IsEvtPend(void)
    This function returns whether the waited event is pending or not It is useful only when the UTIL_SEQ_...
    Definition: stm32_seq.c:471
    +
    UTIL_SEQ_DeInit
    void UTIL_SEQ_DeInit(void)
    This function un-initializes the sequencer resources.
    Definition: stm32_seq.c:199
    +
    UTIL_SEQ_IsPauseTask
    uint32_t UTIL_SEQ_IsPauseTask(UTIL_SEQ_bm_t TaskId_bm)
    This function allows to know if the task has been put in pause. By default, all tasks are executed by...
    Definition: stm32_seq.c:374
    +
    UTIL_SEQ_PauseTask
    void UTIL_SEQ_PauseTask(UTIL_SEQ_bm_t TaskId_bm)
    This function prevents a task to be called by the sequencer even when set with UTIL_SEQ_SetTask() By ...
    Definition: stm32_seq.c:363
    +
    UTIL_SEQ_RegTask
    void UTIL_SEQ_RegTask(UTIL_SEQ_bm_t TaskId_bm, uint32_t Flags, void(*Task)(void))
    This function registers a task in the sequencer.
    Definition: stm32_seq.c:325
    +
    UTIL_SEQ_Run
    void UTIL_SEQ_Run(UTIL_SEQ_bm_t Mask_bm)
    This function requests the sequencer to execute all pending tasks using round robin mechanism....
    Definition: stm32_seq.c:209
    +
    UTIL_SEQ_Init
    void UTIL_SEQ_Init(void)
    This function initializes the sequencer resources.
    Definition: stm32_seq.c:182
    +
    UTIL_SEQ_bm_t
    uint32_t UTIL_SEQ_bm_t
    bit mapping of the task. this value is used to represent a list of task (each corresponds to a task).
    Definition: stm32_seq.h:45
    +
    +
    + + + + diff --git a/Utilities/sequencer/html/struct_u_t_i_l___s_e_q___priority__t.html b/Utilities/sequencer/html/struct_u_t_i_l___s_e_q___priority__t.html new file mode 100644 index 0000000..02225b0 --- /dev/null +++ b/Utilities/sequencer/html/struct_u_t_i_l___s_e_q___priority__t.html @@ -0,0 +1,155 @@ + + + + + + + +STM32 Sequencer: UTIL_SEQ_Priority_t Struct Reference + + + + + + + + + + + + + +
    +
    + + + + + + +
    +
    STM32 Sequencer +  v1.6.0 +
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    +
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    + +
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    + + +
    + +
    + +
    +
    +Data Fields
    +
    +
    UTIL_SEQ_Priority_t Struct Reference
    sequencer utilities » SEQUENCER private type
    +
    +
    + +

    structure used to manage task scheduling + More...

    + + + + + + +

    +Data Fields

    uint32_t priority
     
    uint32_t round_robin
     
    +

    Detailed Description

    +

    structure used to manage task scheduling

    + +

    Definition at line 37 of file stm32_seq.c.

    +

    Field Documentation

    + +

    ◆ priority

    + +
    +
    + + + + +
    uint32_t UTIL_SEQ_Priority_t::priority
    +
    +

    bit field of the enabled task.
    +

    + +

    Definition at line 39 of file stm32_seq.c.

    + +
    +
    + +

    ◆ round_robin

    + +
    +
    + + + + +
    uint32_t UTIL_SEQ_Priority_t::round_robin
    +
    +

    mask on the allowed task to be running.

    + +

    Definition at line 40 of file stm32_seq.c.

    + +
    +
    +
    The documentation for this struct was generated from the following file: +
    +
    + + + + diff --git a/Utilities/sequencer/html/struct_u_t_i_l___s_e_q___priority__t.js b/Utilities/sequencer/html/struct_u_t_i_l___s_e_q___priority__t.js new file mode 100644 index 0000000..2efe5a2 --- /dev/null +++ b/Utilities/sequencer/html/struct_u_t_i_l___s_e_q___priority__t.js @@ -0,0 +1,5 @@ +var struct_u_t_i_l___s_e_q___priority__t = +[ + [ "priority", "struct_u_t_i_l___s_e_q___priority__t.html#a59563315cdb7b76c8a482160851cac3f", null ], + [ "round_robin", "struct_u_t_i_l___s_e_q___priority__t.html#a10895a689ca10b69554ba4a822329f54", null ] +]; \ No newline at end of file diff --git a/Utilities/sequencer/html/sync_off.png b/Utilities/sequencer/html/sync_off.png new file mode 100644 index 0000000..3b443fc Binary files /dev/null and b/Utilities/sequencer/html/sync_off.png differ diff --git a/Utilities/sequencer/html/sync_on.png b/Utilities/sequencer/html/sync_on.png new file mode 100644 index 0000000..e08320f Binary files /dev/null and b/Utilities/sequencer/html/sync_on.png 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a.highlighted{background:#fff}.sm-dox.sm-vertical a.disabled{background-image:url("tab_b.png")}.sm-dox.sm-vertical a span.sub-arrow{right:8px;top:50%;margin-top:-5px;border-width:5px;border-style:dashed dashed dashed solid;border-color:transparent transparent transparent #555}.sm-dox.sm-vertical>li>ul:before,.sm-dox.sm-vertical>li>ul:after{display:none}.sm-dox.sm-vertical ul a{padding:10px 20px}.sm-dox.sm-vertical ul a:hover,.sm-dox.sm-vertical ul a:focus,.sm-dox.sm-vertical ul a:active,.sm-dox.sm-vertical ul a.highlighted{background:#eee}.sm-dox.sm-vertical ul a.disabled{background:#fff}} \ No newline at end of file diff --git a/Utilities/sequencer/stm32_seq.c b/Utilities/sequencer/stm32_seq.c new file mode 100644 index 0000000..f36f3bc --- /dev/null +++ b/Utilities/sequencer/stm32_seq.c @@ -0,0 +1,550 @@ +/** + ****************************************************************************** + * @file stm32_seq.c + * @author MCD Application Team + * @brief Simple sequencer implementation + ****************************************************************************** + * @attention + * + *

    © Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

    + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32_seq.h" +#include "utilities_conf.h" + +/** @addtogroup SEQUENCER + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/** @defgroup SEQUENCER_Private_type SEQUENCER private type + * @{ + */ + +/** + * @brief structure used to manage task scheduling + */ +typedef struct +{ + uint32_t priority; /*! 32 +#error "UTIL_SEQ_CONF_PRIO_NBR must be less of equal then 32" +#endif + +/** + * @brief default value of priority number. + */ +#ifndef UTIL_SEQ_CONF_PRIO_NBR + #define UTIL_SEQ_CONF_PRIO_NBR (2) +#endif + +/** + * @brief default memset function. + */ +#ifndef UTIL_SEQ_MEMSET8 +#define UTIL_SEQ_MEMSET8( dest, value, size ) UTILS_MEMSET8( dest, value, size ) +#endif + +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ + +/** @defgroup SEQUENCER_Private_varaible SEQUENCER private variables + * @{ + */ + +/** + * @brief task set. + */ +static volatile UTIL_SEQ_bm_t TaskSet; + +/** + * @brief task mask. + */ +static volatile UTIL_SEQ_bm_t TaskMask = UTIL_SEQ_ALL_BIT_SET; + +/** + * @brief super mask. + */ +static UTIL_SEQ_bm_t SuperMask = UTIL_SEQ_ALL_BIT_SET; + +/** + * @brief evt set mask. + */ +static volatile UTIL_SEQ_bm_t EvtSet = UTIL_SEQ_NO_BIT_SET; + +/** + * @brief evt expected mask. + */ +static volatile UTIL_SEQ_bm_t EvtWaited = UTIL_SEQ_NO_BIT_SET; + +/** + * @brief current task id. + */ +static uint32_t CurrentTaskIdx = 0U; + +/** + * @brief task function registered. + */ +static void (*TaskCb[UTIL_SEQ_CONF_TASK_NBR])( void ); + +/** + * @brief task prio management. + */ +static volatile UTIL_SEQ_Priority_t TaskPrio[UTIL_SEQ_CONF_PRIO_NBR]; + +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup SEQUENCER_Private_function SEQUENCER private functions + * @{ + */ +uint8_t SEQ_BitPosition(uint32_t Value); + +/** + * @} + */ + +/* Functions Definition ------------------------------------------------------*/ + +/** @addtogroup SEQUENCER_Exported_function SEQUENCER exported functions + * @{ + */ +void UTIL_SEQ_Init( void ) +{ + TaskSet = UTIL_SEQ_NO_BIT_SET; + TaskMask = UTIL_SEQ_ALL_BIT_SET; + SuperMask = UTIL_SEQ_ALL_BIT_SET; + EvtSet = UTIL_SEQ_NO_BIT_SET; + EvtWaited = UTIL_SEQ_NO_BIT_SET; + CurrentTaskIdx = 0U; + (void)UTIL_SEQ_MEMSET8((uint8_t *)TaskCb, 0, sizeof(TaskCb)); + for(uint32_t index = 0; index < UTIL_SEQ_CONF_PRIO_NBR; index++) + { + TaskPrio[index].priority = 0; + TaskPrio[index].round_robin = 0; + } + UTIL_SEQ_INIT_CRITICAL_SECTION( ); +} + +void UTIL_SEQ_DeInit( void ) +{ +} + +/** + * This function can be nested. + * That is the reason why many variables that are used only in that function are declared static. + * Note: These variables could have been declared static in the function. + * + */ +void UTIL_SEQ_Run( UTIL_SEQ_bm_t Mask_bm ) +{ + uint32_t counter; + UTIL_SEQ_bm_t current_task_set; + UTIL_SEQ_bm_t super_mask_backup; + UTIL_SEQ_bm_t local_taskset; + UTIL_SEQ_bm_t local_evtset; + UTIL_SEQ_bm_t local_taskmask; + UTIL_SEQ_bm_t local_evtwaited; + + /* + * When this function is nested, the mask to be applied cannot be larger than the first call + * The mask is always getting smaller and smaller + * A copy is made of the mask set by UTIL_SEQ_Run() in case it is called again in the task + */ + super_mask_backup = SuperMask; + SuperMask &= Mask_bm; + + /* + * There are two independent mask to check: + * TaskMask that comes from UTIL_SEQ_PauseTask() / UTIL_SEQ_ResumeTask + * SuperMask that comes from UTIL_SEQ_Run + * If the waited event is there, exit from UTIL_SEQ_Run() to return to the + * waiting task + */ + local_taskset = TaskSet; + local_evtset = EvtSet; + local_taskmask = TaskMask; + local_evtwaited = EvtWaited; + while(((local_taskset & local_taskmask & SuperMask) != 0U) && ((local_evtset & local_evtwaited)==0U)) + { + counter = 0U; + /* + * When a flag is set, the associated bit is set in TaskPrio[counter].priority mask depending + * on the priority parameter given from UTIL_SEQ_SetTask() + * The while loop is looking for a flag set from the highest priority maskr to the lower + */ + while((TaskPrio[counter].priority & local_taskmask & SuperMask)== 0U) + { + counter++; + } + + current_task_set = TaskPrio[counter].priority & local_taskmask & SuperMask; + + /* + * The round_robin register is a mask of allowed flags to be evaluated. + * The concept is to make sure that on each round on UTIL_SEQ_Run(), if two same flags are always set, + * the sequencer does not run always only the first one. + * When a task has been executed, The flag is removed from the round_robin mask. + * If on the next UTIL_SEQ_RUN(), the two same flags are set again, the round_robin mask will mask out the first flag + * so that the second one can be executed. + * Note that the first flag is not removed from the list of pending task but just masked by the round_robin mask + * + * In the check below, the round_robin mask is reinitialize in case all pending tasks haven been executed at least once + */ + if ((TaskPrio[counter].round_robin & current_task_set) == 0U) + { + TaskPrio[counter].round_robin = UTIL_SEQ_ALL_BIT_SET; + } + + /* + * Read the flag index of the task to be executed + * Once the index is read, the associated task will be executed even though a higher priority stack is requested + * before task execution. + */ + CurrentTaskIdx = (SEQ_BitPosition(current_task_set & TaskPrio[counter].round_robin)); + + /* + * remove from the roun_robin mask the task that has been selected to be executed + */ + TaskPrio[counter].round_robin &= ~(1U << CurrentTaskIdx); + + UTIL_SEQ_ENTER_CRITICAL_SECTION( ); + /* remove from the list or pending task the one that has been selected to be executed */ + TaskSet &= ~(1U << CurrentTaskIdx); + /* remove from all priority mask the task that has been selected to be executed */ + for (counter = UTIL_SEQ_CONF_PRIO_NBR; counter != 0U; counter--) + { + TaskPrio[counter - 1U].priority &= ~(1U << CurrentTaskIdx); + } + UTIL_SEQ_EXIT_CRITICAL_SECTION( ); + + /* Execute the task */ + TaskCb[CurrentTaskIdx]( ); + + local_taskset = TaskSet; + local_evtset = EvtSet; + local_taskmask = TaskMask; + local_evtwaited = EvtWaited; + } + + /* the set of CurrentTaskIdx to no task running allows to call WaitEvt in the Pre/Post ilde context */ + CurrentTaskIdx = UTIL_SEQ_NOTASKRUNNING; + UTIL_SEQ_PreIdle( ); + + UTIL_SEQ_ENTER_CRITICAL_SECTION_IDLE( ); + local_taskset = TaskSet; + local_evtset = EvtSet; + local_taskmask = TaskMask; + if ((local_taskset & local_taskmask & SuperMask) == 0U) + { + if ((local_evtset & EvtWaited)== 0U) + { + UTIL_SEQ_Idle( ); + } + } + UTIL_SEQ_EXIT_CRITICAL_SECTION_IDLE( ); + + UTIL_SEQ_PostIdle( ); + + /* restore the mask from UTIL_SEQ_Run() */ + SuperMask = super_mask_backup; + + return; +} + +void UTIL_SEQ_RegTask(UTIL_SEQ_bm_t TaskId_bm, uint32_t Flags, void (*Task)( void )) +{ + (void)Flags; + UTIL_SEQ_ENTER_CRITICAL_SECTION(); + + TaskCb[SEQ_BitPosition(TaskId_bm)] = Task; + + UTIL_SEQ_EXIT_CRITICAL_SECTION(); + + return; +} + +void UTIL_SEQ_SetTask( UTIL_SEQ_bm_t TaskId_bm , uint32_t Task_Prio ) +{ + UTIL_SEQ_ENTER_CRITICAL_SECTION( ); + + TaskSet |= TaskId_bm; + TaskPrio[Task_Prio].priority |= TaskId_bm; + + UTIL_SEQ_EXIT_CRITICAL_SECTION( ); + + return; +} + +uint32_t UTIL_SEQ_IsSchedulableTask( UTIL_SEQ_bm_t TaskId_bm) +{ + uint32_t _status; + UTIL_SEQ_bm_t local_taskset; + + UTIL_SEQ_ENTER_CRITICAL_SECTION(); + + local_taskset = TaskSet; + _status = ((local_taskset & TaskMask & SuperMask & TaskId_bm) == TaskId_bm)? 1U: 0U; + + UTIL_SEQ_EXIT_CRITICAL_SECTION(); + return _status; +} + +void UTIL_SEQ_PauseTask( UTIL_SEQ_bm_t TaskId_bm ) +{ + UTIL_SEQ_ENTER_CRITICAL_SECTION( ); + + TaskMask &= (~TaskId_bm); + + UTIL_SEQ_EXIT_CRITICAL_SECTION( ); + + return; +} + +uint32_t UTIL_SEQ_IsPauseTask( UTIL_SEQ_bm_t TaskId_bm ) +{ + uint32_t _status; + UTIL_SEQ_ENTER_CRITICAL_SECTION( ); + + _status = ((TaskMask & TaskId_bm) == TaskId_bm) ? 0u:1u; + + UTIL_SEQ_EXIT_CRITICAL_SECTION( ); + return _status; +} + +void UTIL_SEQ_ResumeTask( UTIL_SEQ_bm_t TaskId_bm ) +{ + UTIL_SEQ_ENTER_CRITICAL_SECTION( ); + + TaskMask |= TaskId_bm; + + UTIL_SEQ_EXIT_CRITICAL_SECTION( ); + + return; +} + +void UTIL_SEQ_SetEvt( UTIL_SEQ_bm_t EvtId_bm ) +{ + UTIL_SEQ_ENTER_CRITICAL_SECTION( ); + + EvtSet |= EvtId_bm; + + UTIL_SEQ_EXIT_CRITICAL_SECTION( ); + + return; +} + +void UTIL_SEQ_ClrEvt( UTIL_SEQ_bm_t EvtId_bm ) +{ + UTIL_SEQ_ENTER_CRITICAL_SECTION( ); + + EvtSet &= (~EvtId_bm); + + UTIL_SEQ_EXIT_CRITICAL_SECTION( ); + + return; +} + +void UTIL_SEQ_WaitEvt(UTIL_SEQ_bm_t EvtId_bm) +{ + UTIL_SEQ_bm_t event_waited_id_backup; + UTIL_SEQ_bm_t current_task_idx; + UTIL_SEQ_bm_t wait_task_idx; + /* + * store in local the current_task_id_bm as the global variable CurrentTaskIdx + * may be overwritten in case there are nested call of UTIL_SEQ_Run() + */ + current_task_idx = CurrentTaskIdx; + if(UTIL_SEQ_NOTASKRUNNING == CurrentTaskIdx) + { + wait_task_idx = 0u; + } + else + { + wait_task_idx = (uint32_t)1u << CurrentTaskIdx; + } + + /* backup the event id that was currently waited */ + event_waited_id_backup = EvtWaited; + EvtWaited = EvtId_bm; + /* + * wait for the new event + * note: that means that if the previous waited event occurs, it will not exit + * the while loop below. + * The system is waiting only for the last waited event. + * When it will go out, it will wait again from the previous one. + * It case it occurs while waiting for the second one, the while loop will exit immediately + */ + + while ((EvtSet & EvtId_bm) == 0U) + { + UTIL_SEQ_EvtIdle(wait_task_idx, EvtId_bm); + } + + /* + * Restore the CurrentTaskIdx that may have been modified by call of UTIL_SEQ_Run() from UTIL_SEQ_EvtIdle() + * This is required so that a second call of UTIL_SEQ_WaitEvt() in the same process pass the correct current_task_id_bm + * in the call of UTIL_SEQ_EvtIdle() + */ + CurrentTaskIdx = current_task_idx; + + UTIL_SEQ_ENTER_CRITICAL_SECTION( ); + + EvtSet &= (~EvtId_bm); + + UTIL_SEQ_EXIT_CRITICAL_SECTION( ); + + EvtWaited = event_waited_id_backup; + return; +} + +UTIL_SEQ_bm_t UTIL_SEQ_IsEvtPend( void ) +{ + UTIL_SEQ_bm_t local_evtwaited = EvtWaited; + return (EvtSet & local_evtwaited); +} + +__WEAK void UTIL_SEQ_EvtIdle( UTIL_SEQ_bm_t TaskId_bm, UTIL_SEQ_bm_t EvtWaited_bm ) +{ + (void)EvtWaited_bm; + UTIL_SEQ_Run(~TaskId_bm); + return; +} + +__WEAK void UTIL_SEQ_Idle( void ) +{ + return; +} + +__WEAK void UTIL_SEQ_PreIdle( void ) +{ + /* + * Unless specified by the application, there is nothing to be done + */ + return; +} + +__WEAK void UTIL_SEQ_PostIdle( void ) +{ + /* + * Unless specified by the application, there is nothing to be done + */ + return; +} + +/** + * @} + */ + +/** @addtogroup SEQUENCER_Private_function + * @{ + */ + +#if( __CORTEX_M == 0) +const uint8_t SEQ_clz_table_4bit[16U] = { 4U, 3U, 2U, 2U, 1U, 1U, 1U, 1U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U }; +/** + * @brief return the position of the first bit set to 1 + * @param Value 32 bit value + * @retval bit position + */ +uint8_t SEQ_BitPosition(uint32_t Value) +{ +uint8_t n = 0U; +uint32_t lvalue = Value; + + if ((lvalue & 0xFFFF0000U) == 0U) { n = 16U; lvalue <<= 16U; } + if ((lvalue & 0xFF000000U) == 0U) { n += 8U; lvalue <<= 8U; } + if ((lvalue & 0xF0000000U) == 0U) { n += 4U; lvalue <<= 4U; } + + n += SEQ_clz_table_4bit[lvalue >> (32-4)]; + + return (uint8_t)(31U-n); +} +#else +/** + * @brief return the position of the first bit set to 1 + * @param Value 32 bit value + * @retval bit position + */ +uint8_t SEQ_BitPosition(uint32_t Value) +{ + return (uint8_t)(31 -__CLZ( Value )); +} +#endif + +/** + * @} + */ + +/** + * @} + */ + diff --git a/Utilities/sequencer/stm32_seq.h b/Utilities/sequencer/stm32_seq.h new file mode 100644 index 0000000..ea96197 --- /dev/null +++ b/Utilities/sequencer/stm32_seq.h @@ -0,0 +1,360 @@ +/** + ****************************************************************************** + * @file stm32_seq.h + * @author MCD Application Team + * @brief sequencer interface + ****************************************************************************** + * @attention + * + *

    © Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

    + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32_SEQ_H +#define STM32_SEQ_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stdint.h" + +/** @defgroup SEQUENCER sequencer utilities + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup SEQUENCER_Exported_type SEQUENCER exported types + * @{ + */ +/** + * @brief bit mapping of the task. + * this value is used to represent a list of task (each corresponds to a task). + */ + +typedef uint32_t UTIL_SEQ_bm_t; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup SEQUENCER_Exported_const SEQUENCER exported constants + * @{ + */ + +/** + * @brief This provides a default value for unused parameter + * + */ +#define UTIL_SEQ_RFU 0 + +/** + * @brief Default value used to start the scheduling. + * + * This informs the sequencer that all tasks registered shall be considered + * + * @note + * This should be used in the application\n + * while(1)\n + * {\n + * UTIL_SEQ_Run( UTIL_SEQ_DEFAULT );\n + * }\n + * + */ +#define UTIL_SEQ_DEFAULT (~0U) + +/** + * @} + */ + +/* External variables --------------------------------------------------------*/ +/* Exported macros -----------------------------------------------------------*/ + +/** @defgroup SEQUENCER_Exported_macro SEQUENCER exported macros + * @{ + */ + +/** + * @brief This macro can be used to define a task with one parameter + * + * @note this is an example of using this macro + * + * task prototype definition + * void FUNCTION_NAME(void *Instance) + * { + * uint8_t _instance = *(uint8_t*) Instance; + * } + * + * task declaration in the application for two instances + * const uint8_t instance1 = 1; + * const uint8_t instance2 = 2; + * UTIL_SEQ_TaskParamDef(FUNCTION_NAME, instance1) + * UTIL_SEQ_TaskParamDef(FUNCTION_NAME, instance2) + * + * task initialization + * UTIL_SEQ_RegTask(1 << 1, 0, UTIL_SEQ_TaskFunction(FUNCTION_NAME,instance2)); + * UTIL_SEQ_RegTask(1 << 10, 0, UTIL_SEQ_TaskFunction(FUNCTION_NAME,instance3)); + * + * Then no change on the management of the task within the application, the instance being managed within the overloaded function + * + */ +#define UTIL_SEQ_TaskParamDef(_FUNC_,_PARAM_VAL_) \ + static void SEQ_FUNC_##_FUNC_##_PARAM_VAL_(void); \ + static void SEQ_FUNC_##_FUNC_##_PARAM_VAL_(void) \ + { \ + static void *SEQ_PARAM_##_FUNC_ = (void*)&_PARAM_VAL_;\ + _FUNC_(SEQ_PARAM_##_FUNC_); \ + } + +/** + * @brief This macro is used to retrieve the function name of the task + */ +#define UTIL_SEQ_TaskFunction(_FUNC_,_PARAM_VAL_) SEQ_FUNC_##_FUNC_##_PARAM_VAL_ + +/** + * @} + */ + +/* Exported functions ------------------------------------------------------- */ + +/** @defgroup SEQUENCER_Exported_function SEQUENCER exported functions + * @{ + */ + +/** + * @brief This function initializes the sequencer resources. + * + * @note It shall not be called from an ISR. + * + */ +void UTIL_SEQ_Init( void ); + +/** + * @brief This function un-initializes the sequencer resources. + * + * @note It shall not be called from an ISR + * + */ +void UTIL_SEQ_DeInit( void ); + +/** + * @brief This function is called by the sequencer in critical section (PRIMASK bit) when + * - there are no more tasks to be executed + * AND + * - there are no pending event or the pending event is still not set + * @note The application should enter low power mode in this function + * When this function is not implemented by the application, the sequencer keeps running a while loop (RUN MODE). + * It shall be called only by the sequencer. + * + */ +void UTIL_SEQ_Idle( void ); + +/** + * @brief This function is called by the sequencer outside critical section just before calling UTIL_SEQ_Idle( ) + * UTIL_SEQ_PreIdle() is considered as the last task executed before calling UTIL_SEQ_Idle( ) + * In case a task or an event is set from an interrupt handler just after UTIL_SEQ_PreIdle() is called, + * UTIL_SEQ_Idle() will not be called. + * + * @note It shall be called only by the sequencer. + * + */ +void UTIL_SEQ_PreIdle( void ); + +/** + * @brief This function is called by the sequencer outside critical section either + * - after calling UTIL_SEQ_Idle( ) + * OR + * - after calling UTIL_SEQ_PreIdle( ) without call to UTIL_SEQ_Idle() due to an incoming task set or event + * requested after UTIL_SEQ_PreIdle() has been called. + * + * @note UTIL_SEQ_PostIdle() is always called if UTIL_SEQ_PreIdle() has been called and never called otherwise. + * It shall be called only by the sequencer. + * + */ +void UTIL_SEQ_PostIdle( void ); + +/** + * @brief This function requests the sequencer to execute all pending tasks using round robin mechanism. + * When no task are pending, it calls UTIL_SEQ_Idle(); + * This function should be called in a while loop in the application + * + * @param Mask_bm list of task (bit mapping) that is be kept in the sequencer list. + * + * @note It shall not be called from an ISR. + * @note The construction of the task must take into account the fact that there is no counting / protection + * on the activation of the task. Thus, when the task is running, it must perform all the operations + * in progress programmed before its call or manage a reprogramming of the task. + * + */ +void UTIL_SEQ_Run( UTIL_SEQ_bm_t Mask_bm ); + +/** + * @brief This function registers a task in the sequencer. + * + * @param TaskId_bm The Id of the task + * @param Flags Flags are reserved param for future use + * @param Task Reference of the function to be executed + * + * @note It may be called from an ISR. + * + */ +void UTIL_SEQ_RegTask( UTIL_SEQ_bm_t TaskId_bm, uint32_t Flags, void (*Task)( void ) ); + +/** + * @brief This function requests a task to be executed + * + * @param TaskId_bm The Id of the task + * It shall be (1< + + + + + + Release Notes for STM32 timer server + + + + + + +
    +
    +
    +

    Release Notes for STM32 timer server

    +

    Copyright © 2019 STMicroelectronics
    +

    + +
    +

    Purpose

    +

    The source code delivered is an utility to help managing timer services within an embedded application.

    +
    +
    +

    Update History

    +
    + +
    +

    Main Changes

    +

    Contents

    +

    Fixed bugs list

    + + + + + + + + + + + + + + +
    Headline
    Ticket 137606 - [CodeSpell] Mistake in timer module
    Ticket 127700 - add UTIL_TIMER_GetTimerList function
    +

    known limitations

    +

    Development Toolchains and Compilers

    +
      +
    • IAR Embedded Workbench for ARM (EWARM) toolchain V8.20.2
      • +
    • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.25
      • +
    • System Workbench STM32 (SW4STM32) toolchain V2.7.2
      • +
    +

    Supported Devices and boards

    +

    backward compatibility

    +

    Dependencies

    +
    +
    +
    + +
    +

    Main Changes

    +

    Contents

    +

    Fixed bugs list

    + + + + + + + + + + + +
    Headline
    Release note format update
    +

    known limitations

    +

    Development Toolchains and Compilers

    +
      +
    • IAR Embedded Workbench for ARM (EWARM) toolchain V8.20.2
      • +
    • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.25
      • +
    • System Workbench STM32 (SW4STM32) toolchain V2.7.2
      • +
    +

    Supported Devices and boards

    +

    backward compatibility

    +

    Dependencies

    +
    +
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    + +
    +

    Main Changes

    +

    Contents

    +

    Fixed bugs list

    + + + + + + + + + + + +
    Headline
    Ticket 115234 - [Licensing] Update the way to declare licenses in Cube and X-CUBE components
    +

    known limitations

    +

    Development Toolchains and Compilers

    +
      +
    • IAR Embedded Workbench for ARM (EWARM) toolchain V8.20.2
      • +
    • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.25
      • +
    • System Workbench STM32 (SW4STM32) toolchain V2.7.2
      • +
    +

    Supported Devices and boards

    +

    backward compatibility

    +

    Dependencies

    +
    +
    +
    + +
    +

    Main Changes

    +

    release V1.1.2

    +

    Contents

    +

    Fixed bugs list

    + + + + + + + + + + + +
    Headline
    Ticket 86948 - CodeSpell : Correct some english words typo
    +

    known limitations

    +

    Development Toolchains and Compilers

    +
      +
    • IAR Embedded Workbench for ARM (EWARM) toolchain V8.20.2
      • +
    • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.25
      • +
    • System Workbench STM32 (SW4STM32) toolchain V2.7.2
      • +
    +

    Supported Devices and boards

    +

    backward compatibility

    +

    Dependencies

    +
    +
    +
    + +
    +

    Main Changes

    +

    release V1.1.1

    +

    Contents

    +

    Fixed bugs list

    + + + + + + + + + + + +
    Headline
    Ticket 89624 - Utilities Releases Notes Improvements - Link on openorg BSD-3-Clause
    +

    known limitations

    +

    Development Toolchains and Compilers

    +
      +
    • IAR Embedded Workbench for ARM (EWARM) toolchain V8.20.2
      • +
    • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.25
      • +
    • System Workbench STM32 (SW4STM32) toolchain V2.7.2
      • +
    +

    Supported Devices and boards

    +

    backward compatibility

    +

    Dependencies

    +
    +
    +
    + +
    +

    Main Changes

    +

    release V1.1.0

    +

    Contents

    +

    Fixed bugs list

    + + + + + + + + + + + + + + + + + + + + +
    Headline
    Ticket 86948 - CodeSpell : Correct some english words typo
    Ticket 75887 - [UTILITIES] add TIMER_START_XXXXXX function with parameter Period + Type
    MISRA update
    Doxygen tag update
    +

    known limitations

    +

    Development Toolchains and Compilers

    +
      +
    • IAR Embedded Workbench for ARM (EWARM) toolchain V8.20.2
      • +
    • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.25
      • +
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      • +
    +

    Supported Devices and boards

    +

    backward compatibility

    +

    Dependencies

    +
    +
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    + +
    +

    Main Changes

    +

    release V1.0.1

    +

    Contents

    +

    Fixed bugs list

    + + + + + + + + + + + +
    Headline
    Release note correction
    +

    known limitations

    +

    Development Toolchains and Compilers

    +
      +
    • IAR Embedded Workbench for ARM (EWARM) toolchain V8.20.2
      • +
    • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.25
      • +
    • System Workbench STM32 (SW4STM32) toolchain V2.7.2
      • +
    +

    Supported Devices and boards

    +

    backward compatibility

    +

    Dependencies

    +
    +
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    + +
    +

    Main Changes

    +

    release V1.0.0

    +

    Contents

    +

    Fixed bugs list

    + + + + + + + + + + + +
    Headline
    [Ticket 73263] insert default definition for the critical section
    +

    known limitations

    +

    Development Toolchains and Compilers

    +
      +
    • IAR Embedded Workbench for ARM (EWARM) toolchain V8.20.2
      • +
    • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.25
      • +
    • System Workbench STM32 (SW4STM32) toolchain V2.7.2
      • +
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    Supported Devices and boards

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    backward compatibility

    +

    Dependencies

    +
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    +

    Info

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    +
    +
    + + diff --git a/Utilities/timer/_htmresc/favicon.png b/Utilities/timer/_htmresc/favicon.png new file mode 100644 index 0000000..06713ee Binary files /dev/null and b/Utilities/timer/_htmresc/favicon.png differ diff --git a/Utilities/timer/_htmresc/mini-st.css b/Utilities/timer/_htmresc/mini-st.css new file mode 100644 index 0000000..986f4d4 --- /dev/null +++ b/Utilities/timer/_htmresc/mini-st.css @@ -0,0 +1,1711 @@ +@charset "UTF-8"; +/* + Flavor name: Custom (mini-custom) + Generated online - https://minicss.org/flavors + mini.css version: v3.0.1 +*/ +/* + Browsers resets and base typography. +*/ +/* Core module CSS variable definitions */ +:root { + --fore-color: #03234b; + --secondary-fore-color: #03234b; + --back-color: #ffffff; + --secondary-back-color: #ffffff; + --blockquote-color: #e6007e; + --pre-color: #e6007e; + --border-color: #3cb4e6; + --secondary-border-color: #3cb4e6; + --heading-ratio: 1.2; + --universal-margin: 0.5rem; + --universal-padding: 0.25rem; + --universal-border-radius: 0.075rem; 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+ font-style: italic; + color: var(--secondary-fore-color); + margin: var(--universal-margin); + padding: calc(3 * var(--universal-padding)); + border: 0.0714285714rem solid var(--secondary-border-color); + border-left: 0.3rem solid var(--blockquote-color); + border-radius: 0 var(--universal-border-radius) var(--universal-border-radius) 0; } + blockquote:before { + position: absolute; + top: calc(0rem - var(--universal-padding)); + left: 0; + font-family: sans-serif; + font-size: 2rem; + font-weight: 800; + content: "\201c"; + color: var(--blockquote-color); } + blockquote[cite]:after { + font-style: normal; + font-size: 0.75em; + font-weight: 700; + content: "\a— " attr(cite); + white-space: pre; } + +code, kbd, pre, samp { + font-family: Menlo, Consolas, monospace; + font-size: 0.85em; } + +code { + background: var(--secondary-back-color); + border-radius: var(--universal-border-radius); + padding: calc(var(--universal-padding) / 4) calc(var(--universal-padding) / 2); } + +kbd { + background: var(--fore-color); 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} + +/* + Definitions for the grid system, cards and containers. +*/ +.container { + margin: 0 auto; + padding: 0 calc(1.5 * var(--universal-padding)); } + +.row { + box-sizing: border-box; + display: flex; + flex: 0 1 auto; + flex-flow: row wrap; + margin: 0 0 0 var(--background-margin); } + +.col-sm, +[class^='col-sm-'], +[class^='col-sm-offset-'], +.row[class*='cols-sm-'] > * { + box-sizing: border-box; + flex: 0 0 auto; + padding: 0 calc(var(--universal-padding) / 2); } + +.col-sm, +.row.cols-sm > * { + max-width: 100%; + flex-grow: 1; + flex-basis: 0; } + +.col-sm-1, +.row.cols-sm-1 > * { + max-width: 8.3333333333%; + flex-basis: 8.3333333333%; } + +.col-sm-offset-0 { + margin-left: 0; } + +.col-sm-2, +.row.cols-sm-2 > * { + max-width: 16.6666666667%; + flex-basis: 16.6666666667%; } + +.col-sm-offset-1 { + margin-left: 8.3333333333%; } + +.col-sm-3, +.row.cols-sm-3 > * { + max-width: 25%; + flex-basis: 25%; } + +.col-sm-offset-2 { + margin-left: 16.6666666667%; } + +.col-sm-4, +.row.cols-sm-4 > * { + max-width: 33.3333333333%; + flex-basis: 33.3333333333%; } + +.col-sm-offset-3 { + margin-left: 25%; } + +.col-sm-5, +.row.cols-sm-5 > * { + max-width: 41.6666666667%; + flex-basis: 41.6666666667%; } + +.col-sm-offset-4 { + margin-left: 33.3333333333%; } + +.col-sm-6, +.row.cols-sm-6 > * { + max-width: 50%; + flex-basis: 50%; } + +.col-sm-offset-5 { + margin-left: 41.6666666667%; } + +.col-sm-7, +.row.cols-sm-7 > * { + max-width: 58.3333333333%; + flex-basis: 58.3333333333%; } + +.col-sm-offset-6 { + margin-left: 50%; } + +.col-sm-8, +.row.cols-sm-8 > * { + max-width: 66.6666666667%; + flex-basis: 66.6666666667%; } + +.col-sm-offset-7 { + margin-left: 58.3333333333%; } + +.col-sm-9, +.row.cols-sm-9 > * { + max-width: 75%; + flex-basis: 75%; } + +.col-sm-offset-8 { + margin-left: 66.6666666667%; } + +.col-sm-10, +.row.cols-sm-10 > * { + max-width: 83.3333333333%; + flex-basis: 83.3333333333%; } + +.col-sm-offset-9 { + margin-left: 75%; } + +.col-sm-11, +.row.cols-sm-11 > * { + max-width: 91.6666666667%; + flex-basis: 91.6666666667%; } + +.col-sm-offset-10 { + margin-left: 83.3333333333%; } + +.col-sm-12, +.row.cols-sm-12 > * { + max-width: 100%; + flex-basis: 100%; } + +.col-sm-offset-11 { + margin-left: 91.6666666667%; } + +.col-sm-normal { + order: initial; } + +.col-sm-first { + order: -999; } + +.col-sm-last { + order: 999; } + +@media screen and (min-width: 500px) { + .col-md, + [class^='col-md-'], + [class^='col-md-offset-'], + .row[class*='cols-md-'] > * { + box-sizing: border-box; + flex: 0 0 auto; + padding: 0 calc(var(--universal-padding) / 2); } + + .col-md, + .row.cols-md > * { + max-width: 100%; + flex-grow: 1; + flex-basis: 0; } + + .col-md-1, + .row.cols-md-1 > * { + max-width: 8.3333333333%; + flex-basis: 8.3333333333%; } + + .col-md-offset-0 { + margin-left: 0; } + + .col-md-2, + .row.cols-md-2 > * { + max-width: 16.6666666667%; + flex-basis: 16.6666666667%; } + + .col-md-offset-1 { + margin-left: 8.3333333333%; } + + .col-md-3, + .row.cols-md-3 > * { + max-width: 25%; + flex-basis: 25%; } + + .col-md-offset-2 { + margin-left: 16.6666666667%; } + + .col-md-4, + .row.cols-md-4 > * { + max-width: 33.3333333333%; + flex-basis: 33.3333333333%; } + + .col-md-offset-3 { + margin-left: 25%; } + + .col-md-5, + .row.cols-md-5 > * { + max-width: 41.6666666667%; + flex-basis: 41.6666666667%; } + + .col-md-offset-4 { + margin-left: 33.3333333333%; } + + .col-md-6, + .row.cols-md-6 > * { + max-width: 50%; + flex-basis: 50%; } + + .col-md-offset-5 { + margin-left: 41.6666666667%; } + + .col-md-7, + .row.cols-md-7 > * { + max-width: 58.3333333333%; + flex-basis: 58.3333333333%; } + + .col-md-offset-6 { + margin-left: 50%; } + + .col-md-8, + .row.cols-md-8 > * { + max-width: 66.6666666667%; + flex-basis: 66.6666666667%; } + + .col-md-offset-7 { + margin-left: 58.3333333333%; } + + .col-md-9, + .row.cols-md-9 > * { + max-width: 75%; + flex-basis: 75%; } + + .col-md-offset-8 { + margin-left: 66.6666666667%; } + + .col-md-10, + .row.cols-md-10 > * { + max-width: 83.3333333333%; + flex-basis: 83.3333333333%; } + + .col-md-offset-9 { + margin-left: 75%; } + + .col-md-11, + .row.cols-md-11 > * { + max-width: 91.6666666667%; + flex-basis: 91.6666666667%; } + + .col-md-offset-10 { + margin-left: 83.3333333333%; } + + .col-md-12, + .row.cols-md-12 > * { + max-width: 100%; + flex-basis: 100%; } + + .col-md-offset-11 { + margin-left: 91.6666666667%; } + + .col-md-normal { + order: initial; } + + .col-md-first { + order: -999; } + + .col-md-last { + order: 999; } } +@media screen and (min-width: 1280px) { + .col-lg, + [class^='col-lg-'], + [class^='col-lg-offset-'], + .row[class*='cols-lg-'] > * { + box-sizing: border-box; + flex: 0 0 auto; + padding: 0 calc(var(--universal-padding) / 2); } + + .col-lg, + .row.cols-lg > * { + max-width: 100%; + flex-grow: 1; + flex-basis: 0; } + + .col-lg-1, + .row.cols-lg-1 > * { + max-width: 8.3333333333%; + flex-basis: 8.3333333333%; } + + .col-lg-offset-0 { + margin-left: 0; } + + .col-lg-2, + .row.cols-lg-2 > * { + max-width: 16.6666666667%; + flex-basis: 16.6666666667%; } + + .col-lg-offset-1 { + margin-left: 8.3333333333%; } + + .col-lg-3, + .row.cols-lg-3 > * { + max-width: 25%; + flex-basis: 25%; } + + .col-lg-offset-2 { + margin-left: 16.6666666667%; } + + .col-lg-4, + .row.cols-lg-4 > * { + max-width: 33.3333333333%; + flex-basis: 33.3333333333%; } + + .col-lg-offset-3 { + margin-left: 25%; } + + .col-lg-5, + .row.cols-lg-5 > * { + max-width: 41.6666666667%; + flex-basis: 41.6666666667%; } + + .col-lg-offset-4 { + margin-left: 33.3333333333%; } + + .col-lg-6, + .row.cols-lg-6 > * { + max-width: 50%; + flex-basis: 50%; } + + .col-lg-offset-5 { + margin-left: 41.6666666667%; } + + .col-lg-7, + .row.cols-lg-7 > * { + max-width: 58.3333333333%; + flex-basis: 58.3333333333%; } + + .col-lg-offset-6 { + margin-left: 50%; } + + .col-lg-8, + .row.cols-lg-8 > * { + max-width: 66.6666666667%; + flex-basis: 66.6666666667%; } + + .col-lg-offset-7 { + margin-left: 58.3333333333%; } + + .col-lg-9, + .row.cols-lg-9 > * { + max-width: 75%; + flex-basis: 75%; } + + .col-lg-offset-8 { + margin-left: 66.6666666667%; } + + .col-lg-10, + .row.cols-lg-10 > * { + max-width: 83.3333333333%; + flex-basis: 83.3333333333%; } + + .col-lg-offset-9 { + margin-left: 75%; } + + .col-lg-11, + .row.cols-lg-11 > * { + max-width: 91.6666666667%; + flex-basis: 91.6666666667%; } + + .col-lg-offset-10 { + margin-left: 83.3333333333%; } + + .col-lg-12, + .row.cols-lg-12 > * { + max-width: 100%; + flex-basis: 100%; } + + .col-lg-offset-11 { + margin-left: 91.6666666667%; } + + .col-lg-normal { + order: initial; } + + .col-lg-first { + order: -999; } + + .col-lg-last { + order: 999; } } +/* Card component CSS variable definitions */ +:root { + --card-back-color: #3cb4e6; + --card-fore-color: #03234b; + --card-border-color: #03234b; } + +.card { + display: flex; + flex-direction: column; + justify-content: space-between; + align-self: center; + position: relative; + width: 100%; + background: var(--card-back-color); + color: var(--card-fore-color); + border: 0.0714285714rem solid var(--card-border-color); + border-radius: var(--universal-border-radius); + margin: var(--universal-margin); + overflow: hidden; } + @media screen and (min-width: 320px) { + .card { + max-width: 320px; } } + .card > .sectione { + background: var(--card-back-color); + color: var(--card-fore-color); + box-sizing: border-box; + margin: 0; + border: 0; + border-radius: 0; + border-bottom: 0.0714285714rem solid var(--card-border-color); + padding: var(--universal-padding); + width: 100%; } + .card > .sectione.media { + height: 200px; + padding: 0; + -o-object-fit: cover; + object-fit: cover; } + .card > .sectione:last-child { + border-bottom: 0; } + +/* + Custom elements for card elements. +*/ +@media screen and (min-width: 240px) { + .card.small { + max-width: 240px; } } +@media screen and (min-width: 480px) { + .card.large { + max-width: 480px; } } +.card.fluid { + max-width: 100%; + width: auto; } + +.card.warning { + --card-back-color: #e5b8b7; + --card-fore-color: #3b234b; + --card-border-color: #8c0078; } + +.card.error { + --card-back-color: #464650; + --card-fore-color: #ffffff; + --card-border-color: #8c0078; } + +.card > .sectione.dark { + --card-back-color: #3b234b; + --card-fore-color: #ffffff; } + +.card > .sectione.double-padded { + padding: calc(1.5 * var(--universal-padding)); } + +/* + Definitions for forms and input elements. +*/ +/* Input_control module CSS variable definitions */ +:root { + --form-back-color: #ffe97f; + --form-fore-color: #03234b; + --form-border-color: #3cb4e6; + --input-back-color: #ffffff; + --input-fore-color: #03234b; + --input-border-color: #3cb4e6; + --input-focus-color: #0288d1; + --input-invalid-color: #d32f2f; + --button-back-color: #e2e2e2; + --button-hover-back-color: #dcdcdc; + --button-fore-color: #212121; + --button-border-color: transparent; + --button-hover-border-color: transparent; + --button-group-border-color: rgba(124, 124, 124, 0.54); } + +form { + background: var(--form-back-color); + color: var(--form-fore-color); + border: 0.0714285714rem solid var(--form-border-color); + border-radius: var(--universal-border-radius); + margin: var(--universal-margin); + padding: calc(2 * var(--universal-padding)) var(--universal-padding); } + +fieldset { + border: 0.0714285714rem solid var(--form-border-color); + border-radius: var(--universal-border-radius); + margin: calc(var(--universal-margin) / 4); + padding: var(--universal-padding); } + +legend { + box-sizing: border-box; + display: table; + max-width: 100%; + white-space: normal; + font-weight: 500; + padding: calc(var(--universal-padding) / 2); } + +label { + padding: calc(var(--universal-padding) / 2) var(--universal-padding); } + +.input-group { + display: inline-block; } + .input-group.fluid { + display: flex; + align-items: center; + justify-content: center; } + .input-group.fluid > input { + max-width: 100%; + flex-grow: 1; + flex-basis: 0px; } + @media screen and (max-width: 499px) { + .input-group.fluid { + align-items: stretch; + flex-direction: column; } } + .input-group.vertical { + display: flex; + align-items: stretch; + flex-direction: column; } + .input-group.vertical > input { + max-width: 100%; + flex-grow: 1; + flex-basis: 0px; } + +[type="number"]::-webkit-inner-spin-button, [type="number"]::-webkit-outer-spin-button { + height: auto; } + +[type="search"] { + -webkit-appearance: textfield; + outline-offset: -2px; } + +[type="search"]::-webkit-search-cancel-button, +[type="search"]::-webkit-search-decoration { + -webkit-appearance: none; } + +input:not([type]), [type="text"], [type="email"], [type="number"], [type="search"], +[type="password"], [type="url"], [type="tel"], [type="checkbox"], [type="radio"], textarea, select { + box-sizing: border-box; + background: var(--input-back-color); + color: var(--input-fore-color); + border: 0.0714285714rem solid var(--input-border-color); + border-radius: var(--universal-border-radius); + margin: calc(var(--universal-margin) / 2); + padding: var(--universal-padding) calc(1.5 * var(--universal-padding)); } + +input:not([type="button"]):not([type="submit"]):not([type="reset"]):hover, input:not([type="button"]):not([type="submit"]):not([type="reset"]):focus, textarea:hover, textarea:focus, select:hover, select:focus { + border-color: var(--input-focus-color); + box-shadow: none; } +input:not([type="button"]):not([type="submit"]):not([type="reset"]):invalid, input:not([type="button"]):not([type="submit"]):not([type="reset"]):focus:invalid, textarea:invalid, textarea:focus:invalid, select:invalid, select:focus:invalid { + border-color: var(--input-invalid-color); + box-shadow: none; } +input:not([type="button"]):not([type="submit"]):not([type="reset"])[readonly], textarea[readonly], select[readonly] { + background: var(--secondary-back-color); } + +select { + max-width: 100%; } + +option { + overflow: hidden; + text-overflow: ellipsis; } + +[type="checkbox"], [type="radio"] { + -webkit-appearance: none; + -moz-appearance: none; + appearance: none; + position: relative; + height: calc(1rem + var(--universal-padding) / 2); + width: calc(1rem + var(--universal-padding) / 2); + vertical-align: text-bottom; + padding: 0; + flex-basis: calc(1rem + var(--universal-padding) / 2) !important; + flex-grow: 0 !important; } + [type="checkbox"]:checked:before, [type="radio"]:checked:before { + position: absolute; } + +[type="checkbox"]:checked:before { + content: '\2713'; + font-family: sans-serif; + font-size: calc(1rem + var(--universal-padding) / 2); + top: calc(0rem - var(--universal-padding)); + left: calc(var(--universal-padding) / 4); } + +[type="radio"] { + border-radius: 100%; } + [type="radio"]:checked:before { + border-radius: 100%; + content: ''; + top: calc(0.0714285714rem + var(--universal-padding) / 2); + left: calc(0.0714285714rem + var(--universal-padding) / 2); + background: var(--input-fore-color); + width: 0.5rem; + height: 0.5rem; } + +:placeholder-shown { + color: var(--input-fore-color); } + +::-ms-placeholder { + color: var(--input-fore-color); + opacity: 0.54; } + +button::-moz-focus-inner, [type="button"]::-moz-focus-inner, [type="reset"]::-moz-focus-inner, [type="submit"]::-moz-focus-inner { + border-style: none; + padding: 0; } + +button, html [type="button"], [type="reset"], [type="submit"] { + -webkit-appearance: button; } + +button { + overflow: visible; + text-transform: none; } + +button, [type="button"], [type="submit"], [type="reset"], +a.button, label.button, .button, +a[role="button"], label[role="button"], [role="button"] { + display: inline-block; + background: var(--button-back-color); + color: var(--button-fore-color); + border: 0.0714285714rem solid var(--button-border-color); + border-radius: var(--universal-border-radius); + padding: var(--universal-padding) calc(1.5 * var(--universal-padding)); + margin: var(--universal-margin); + text-decoration: none; + cursor: pointer; + transition: background 0.3s; } + button:hover, button:focus, [type="button"]:hover, [type="button"]:focus, [type="submit"]:hover, [type="submit"]:focus, [type="reset"]:hover, [type="reset"]:focus, + a.button:hover, + a.button:focus, label.button:hover, label.button:focus, .button:hover, .button:focus, + a[role="button"]:hover, + a[role="button"]:focus, label[role="button"]:hover, label[role="button"]:focus, [role="button"]:hover, [role="button"]:focus { + background: var(--button-hover-back-color); + border-color: var(--button-hover-border-color); } + +input:disabled, input[disabled], textarea:disabled, textarea[disabled], select:disabled, select[disabled], button:disabled, button[disabled], .button:disabled, .button[disabled], [role="button"]:disabled, [role="button"][disabled] { + cursor: not-allowed; + opacity: 0.75; } + +.button-group { + display: flex; + border: 0.0714285714rem solid var(--button-group-border-color); + border-radius: var(--universal-border-radius); + margin: var(--universal-margin); } + .button-group > button, .button-group [type="button"], .button-group > [type="submit"], .button-group > [type="reset"], .button-group > .button, .button-group > [role="button"] { + margin: 0; + max-width: 100%; + flex: 1 1 auto; + text-align: center; + border: 0; + border-radius: 0; + box-shadow: none; } + .button-group > :not(:first-child) { + border-left: 0.0714285714rem solid var(--button-group-border-color); } + @media screen and (max-width: 499px) { + .button-group { + flex-direction: column; } + .button-group > :not(:first-child) { + border: 0; + border-top: 0.0714285714rem solid var(--button-group-border-color); } } + +/* + Custom elements for forms and input elements. +*/ +button.primary, [type="button"].primary, [type="submit"].primary, [type="reset"].primary, .button.primary, [role="button"].primary { + --button-back-color: #1976d2; + --button-fore-color: #f8f8f8; } + button.primary:hover, button.primary:focus, [type="button"].primary:hover, [type="button"].primary:focus, [type="submit"].primary:hover, [type="submit"].primary:focus, [type="reset"].primary:hover, [type="reset"].primary:focus, .button.primary:hover, .button.primary:focus, [role="button"].primary:hover, [role="button"].primary:focus { + --button-hover-back-color: #1565c0; } + +button.secondary, [type="button"].secondary, [type="submit"].secondary, [type="reset"].secondary, .button.secondary, [role="button"].secondary { + --button-back-color: #d32f2f; + --button-fore-color: #f8f8f8; } + button.secondary:hover, button.secondary:focus, [type="button"].secondary:hover, [type="button"].secondary:focus, [type="submit"].secondary:hover, [type="submit"].secondary:focus, [type="reset"].secondary:hover, [type="reset"].secondary:focus, .button.secondary:hover, .button.secondary:focus, [role="button"].secondary:hover, [role="button"].secondary:focus { + --button-hover-back-color: #c62828; } + +button.tertiary, [type="button"].tertiary, [type="submit"].tertiary, [type="reset"].tertiary, .button.tertiary, [role="button"].tertiary { + --button-back-color: #308732; + --button-fore-color: #f8f8f8; } + button.tertiary:hover, button.tertiary:focus, [type="button"].tertiary:hover, [type="button"].tertiary:focus, [type="submit"].tertiary:hover, [type="submit"].tertiary:focus, [type="reset"].tertiary:hover, [type="reset"].tertiary:focus, .button.tertiary:hover, .button.tertiary:focus, [role="button"].tertiary:hover, [role="button"].tertiary:focus { + --button-hover-back-color: #277529; } + +button.inverse, [type="button"].inverse, [type="submit"].inverse, [type="reset"].inverse, .button.inverse, [role="button"].inverse { + --button-back-color: #212121; + --button-fore-color: #f8f8f8; } + button.inverse:hover, button.inverse:focus, [type="button"].inverse:hover, [type="button"].inverse:focus, [type="submit"].inverse:hover, [type="submit"].inverse:focus, [type="reset"].inverse:hover, [type="reset"].inverse:focus, .button.inverse:hover, .button.inverse:focus, [role="button"].inverse:hover, [role="button"].inverse:focus { + --button-hover-back-color: #111; } + +button.small, [type="button"].small, [type="submit"].small, [type="reset"].small, .button.small, [role="button"].small { + padding: calc(0.5 * var(--universal-padding)) calc(0.75 * var(--universal-padding)); + margin: var(--universal-margin); } + +button.large, [type="button"].large, [type="submit"].large, [type="reset"].large, .button.large, [role="button"].large { + padding: calc(1.5 * var(--universal-padding)) calc(2 * var(--universal-padding)); + margin: var(--universal-margin); } + +/* + Definitions for navigation elements. +*/ +/* Navigation module CSS variable definitions */ +:root { + --header-back-color: #03234b; + --header-hover-back-color: #ffd200; + --header-fore-color: #ffffff; + --header-border-color: #3cb4e6; + --nav-back-color: #ffffff; + --nav-hover-back-color: #ffe97f; + --nav-fore-color: #e6007e; + --nav-border-color: #3cb4e6; + --nav-link-color: #3cb4e6; + --footer-fore-color: #ffffff; + --footer-back-color: #03234b; + --footer-border-color: #3cb4e6; + --footer-link-color: #3cb4e6; + --drawer-back-color: #ffffff; + --drawer-hover-back-color: #ffe97f; + --drawer-border-color: #3cb4e6; + --drawer-close-color: #e6007e; } + +header { + height: 2.75rem; + background: var(--header-back-color); + color: var(--header-fore-color); + border-bottom: 0.0714285714rem solid var(--header-border-color); + padding: calc(var(--universal-padding) / 4) 0; + white-space: nowrap; + overflow-x: auto; + overflow-y: hidden; } + header.row { + box-sizing: content-box; } + header .logo { + color: var(--header-fore-color); + font-size: 1.75rem; + padding: var(--universal-padding) calc(2 * var(--universal-padding)); + text-decoration: none; } + header button, header [type="button"], header .button, header [role="button"] { + box-sizing: border-box; + position: relative; + top: calc(0rem - var(--universal-padding) / 4); + height: calc(3.1875rem + var(--universal-padding) / 2); + background: var(--header-back-color); + line-height: calc(3.1875rem - var(--universal-padding) * 1.5); + text-align: center; + color: var(--header-fore-color); + border: 0; + border-radius: 0; + margin: 0; + text-transform: uppercase; } + header button:hover, header button:focus, header [type="button"]:hover, header [type="button"]:focus, header .button:hover, header .button:focus, header [role="button"]:hover, header [role="button"]:focus { + background: var(--header-hover-back-color); } + +nav { + background: var(--nav-back-color); + color: var(--nav-fore-color); + border: 0.0714285714rem solid var(--nav-border-color); + border-radius: var(--universal-border-radius); + margin: var(--universal-margin); } + nav * { + padding: var(--universal-padding) calc(1.5 * var(--universal-padding)); } + nav a, nav a:visited { + display: block; + color: var(--nav-link-color); + border-radius: var(--universal-border-radius); + transition: background 0.3s; } + nav a:hover, nav a:focus, nav a:visited:hover, nav a:visited:focus { + text-decoration: none; + background: var(--nav-hover-back-color); } + nav .sublink-1 { + position: relative; + margin-left: calc(2 * var(--universal-padding)); } + nav .sublink-1:before { + position: absolute; + left: calc(var(--universal-padding) - 1 * var(--universal-padding)); + top: -0.0714285714rem; + content: ''; + height: 100%; + border: 0.0714285714rem solid var(--nav-border-color); + border-left: 0; } + nav .sublink-2 { + position: relative; + margin-left: calc(4 * var(--universal-padding)); } + nav .sublink-2:before { + position: absolute; + left: calc(var(--universal-padding) - 3 * var(--universal-padding)); + top: -0.0714285714rem; + content: ''; + height: 100%; + border: 0.0714285714rem solid var(--nav-border-color); + border-left: 0; } + +footer { + background: var(--footer-back-color); + color: var(--footer-fore-color); + border-top: 0.0714285714rem solid var(--footer-border-color); + padding: calc(2 * var(--universal-padding)) var(--universal-padding); + font-size: 0.875rem; } + footer a, footer a:visited { + color: var(--footer-link-color); } + +header.sticky { + position: -webkit-sticky; + position: sticky; + z-index: 1101; + top: 0; } + +footer.sticky { + position: -webkit-sticky; + position: sticky; + z-index: 1101; + bottom: 0; } + +.drawer-toggle:before { + display: inline-block; + position: relative; + vertical-align: bottom; + content: '\00a0\2261\00a0'; + font-family: sans-serif; + font-size: 1.5em; } +@media screen and (min-width: 500px) { + .drawer-toggle:not(.persistent) { + display: none; } } + +[type="checkbox"].drawer { + height: 1px; + width: 1px; + margin: -1px; + overflow: hidden; + position: absolute; + clip: rect(0 0 0 0); + -webkit-clip-path: inset(100%); + clip-path: inset(100%); } + [type="checkbox"].drawer + * { + display: block; + box-sizing: border-box; + position: fixed; + top: 0; + width: 320px; + height: 100vh; + overflow-y: auto; + background: var(--drawer-back-color); + border: 0.0714285714rem solid var(--drawer-border-color); + border-radius: 0; + margin: 0; + z-index: 1110; + right: -320px; + transition: right 0.3s; } + [type="checkbox"].drawer + * .drawer-close { + position: absolute; + top: var(--universal-margin); + right: var(--universal-margin); + z-index: 1111; + width: 2rem; + height: 2rem; + border-radius: var(--universal-border-radius); + padding: var(--universal-padding); + margin: 0; + cursor: pointer; + transition: background 0.3s; } + [type="checkbox"].drawer + * .drawer-close:before { + display: block; + content: '\00D7'; + color: var(--drawer-close-color); + position: relative; + font-family: sans-serif; + font-size: 2rem; + line-height: 1; + text-align: center; } + [type="checkbox"].drawer + * .drawer-close:hover, [type="checkbox"].drawer + * .drawer-close:focus { + background: var(--drawer-hover-back-color); } + @media screen and (max-width: 320px) { + [type="checkbox"].drawer + * { + width: 100%; } } + [type="checkbox"].drawer:checked + * { + right: 0; } + @media screen and (min-width: 500px) { + [type="checkbox"].drawer:not(.persistent) + * { + position: static; + height: 100%; + z-index: 1100; } + [type="checkbox"].drawer:not(.persistent) + * .drawer-close { + display: none; } } + +/* + Definitions for the responsive table component. +*/ +/* Table module CSS variable definitions. */ +:root { + --table-border-color: #03234b; + --table-border-separator-color: #03234b; + --table-head-back-color: #03234b; + --table-head-fore-color: #ffffff; + --table-body-back-color: #ffffff; + --table-body-fore-color: #03234b; + --table-body-alt-back-color: #f4f4f4; } + +table { + border-collapse: separate; + border-spacing: 0; + margin: 0; + display: flex; + flex: 0 1 auto; + flex-flow: row wrap; + padding: var(--universal-padding); + padding-top: 0; } + table caption { + font-size: 1rem; + margin: calc(2 * var(--universal-margin)) 0; + max-width: 100%; + flex: 0 0 100%; } + table thead, table tbody { + display: flex; + flex-flow: row wrap; + border: 0.0714285714rem solid var(--table-border-color); } + table thead { + z-index: 999; + border-radius: var(--universal-border-radius) var(--universal-border-radius) 0 0; + border-bottom: 0.0714285714rem solid var(--table-border-separator-color); } + table tbody { + border-top: 0; + margin-top: calc(0 - var(--universal-margin)); + border-radius: 0 0 var(--universal-border-radius) var(--universal-border-radius); } + table tr { + display: flex; + padding: 0; } + table th, table td { + padding: calc(0.5 * var(--universal-padding)); + font-size: 0.9rem; } + table th { + text-align: left; + background: var(--table-head-back-color); + color: var(--table-head-fore-color); } + table td { + background: var(--table-body-back-color); + color: var(--table-body-fore-color); + border-top: 0.0714285714rem solid var(--table-border-color); } + +table:not(.horizontal) { + overflow: auto; + max-height: 100%; } + table:not(.horizontal) thead, table:not(.horizontal) tbody { + max-width: 100%; + flex: 0 0 100%; } + table:not(.horizontal) tr { + flex-flow: row wrap; + flex: 0 0 100%; } + table:not(.horizontal) th, table:not(.horizontal) td { + flex: 1 0 0%; + overflow: hidden; + text-overflow: ellipsis; } + table:not(.horizontal) thead { + position: sticky; + top: 0; } + table:not(.horizontal) tbody tr:first-child td { + border-top: 0; } + +table.horizontal { + border: 0; } + table.horizontal thead, table.horizontal tbody { + border: 0; + flex: .2 0 0; + flex-flow: row nowrap; } + table.horizontal tbody { + overflow: auto; + justify-content: space-between; + flex: .8 0 0; + margin-left: 0; + padding-bottom: calc(var(--universal-padding) / 4); } + table.horizontal tr { + flex-direction: column; + flex: 1 0 auto; } + table.horizontal th, table.horizontal td { + width: auto; + border: 0; + border-bottom: 0.0714285714rem solid var(--table-border-color); } + table.horizontal th:not(:first-child), table.horizontal td:not(:first-child) { + border-top: 0; } + table.horizontal th { + text-align: right; + border-left: 0.0714285714rem solid var(--table-border-color); + border-right: 0.0714285714rem solid var(--table-border-separator-color); } + table.horizontal thead tr:first-child { + padding-left: 0; } + table.horizontal th:first-child, table.horizontal td:first-child { + border-top: 0.0714285714rem solid var(--table-border-color); } + table.horizontal tbody tr:last-child td { + border-right: 0.0714285714rem solid var(--table-border-color); } + table.horizontal tbody tr:last-child td:first-child { + border-top-right-radius: 0.25rem; } + table.horizontal tbody tr:last-child td:last-child { + border-bottom-right-radius: 0.25rem; } + table.horizontal thead tr:first-child th:first-child { + border-top-left-radius: 0.25rem; } + table.horizontal thead tr:first-child th:last-child { + border-bottom-left-radius: 0.25rem; } + +@media screen and (max-width: 499px) { + table, table.horizontal { + border-collapse: collapse; + border: 0; + width: 100%; + display: table; } + table thead, table th, table.horizontal thead, table.horizontal th { + border: 0; + height: 1px; + width: 1px; + margin: -1px; + overflow: hidden; + padding: 0; + position: absolute; + clip: rect(0 0 0 0); + -webkit-clip-path: inset(100%); + clip-path: inset(100%); } + table tbody, table.horizontal tbody { + border: 0; + display: table-row-group; } + table tr, table.horizontal tr { + display: block; + border: 0.0714285714rem solid var(--table-border-color); + border-radius: var(--universal-border-radius); + background: #ffffff; + padding: var(--universal-padding); + margin: var(--universal-margin); + margin-bottom: calc(1 * var(--universal-margin)); } + table th, table td, table.horizontal th, table.horizontal td { + width: auto; } + table td, table.horizontal td { + display: block; + border: 0; + text-align: right; } + table td:before, table.horizontal td:before { + content: attr(data-label); + float: left; + font-weight: 600; } + table th:first-child, table td:first-child, table.horizontal th:first-child, table.horizontal td:first-child { + border-top: 0; } + table tbody tr:last-child td, table.horizontal tbody tr:last-child td { + border-right: 0; } } +table tr:nth-of-type(2n) > td { + background: var(--table-body-alt-back-color); } + +@media screen and (max-width: 500px) { + table tr:nth-of-type(2n) { + background: var(--table-body-alt-back-color); } } +:root { + --table-body-hover-back-color: #90caf9; } + +table.hoverable tr:hover, table.hoverable tr:hover > td, table.hoverable tr:focus, table.hoverable tr:focus > td { + background: var(--table-body-hover-back-color); } + +@media screen and (max-width: 500px) { + table.hoverable tr:hover, table.hoverable tr:hover > td, table.hoverable tr:focus, table.hoverable tr:focus > td { + background: var(--table-body-hover-back-color); } } +/* + Definitions for contextual background elements, toasts and tooltips. +*/ +/* Contextual module CSS variable definitions */ +:root { + --mark-back-color: #3cb4e6; + --mark-fore-color: #ffffff; } + +mark { + background: var(--mark-back-color); + color: var(--mark-fore-color); + font-size: 0.95em; + line-height: 1em; + border-radius: var(--universal-border-radius); + padding: calc(var(--universal-padding) / 4) var(--universal-padding); } + mark.inline-block { + display: inline-block; + font-size: 1em; + line-height: 1.4; + padding: calc(var(--universal-padding) / 2) var(--universal-padding); } + +:root { + --toast-back-color: #424242; + --toast-fore-color: #fafafa; } + +.toast { + position: fixed; + bottom: calc(var(--universal-margin) * 3); + left: 50%; + transform: translate(-50%, -50%); + z-index: 1111; + color: var(--toast-fore-color); + background: var(--toast-back-color); + border-radius: calc(var(--universal-border-radius) * 16); + padding: var(--universal-padding) calc(var(--universal-padding) * 3); } + +:root { + --tooltip-back-color: #212121; + --tooltip-fore-color: #fafafa; } + +.tooltip { + position: relative; + display: inline-block; } + .tooltip:before, .tooltip:after { + position: absolute; + opacity: 0; + clip: rect(0 0 0 0); + -webkit-clip-path: inset(100%); + clip-path: inset(100%); + transition: all 0.3s; + z-index: 1010; + left: 50%; } + .tooltip:not(.bottom):before, .tooltip:not(.bottom):after { + bottom: 75%; } + .tooltip.bottom:before, .tooltip.bottom:after { + top: 75%; } + .tooltip:hover:before, .tooltip:hover:after, .tooltip:focus:before, .tooltip:focus:after { + opacity: 1; + clip: auto; + -webkit-clip-path: inset(0%); + clip-path: inset(0%); } + .tooltip:before { + content: ''; + background: transparent; + border: var(--universal-margin) solid transparent; + left: calc(50% - var(--universal-margin)); } + .tooltip:not(.bottom):before { + border-top-color: #212121; } + .tooltip.bottom:before { + border-bottom-color: #212121; } + .tooltip:after { + content: attr(aria-label); + color: var(--tooltip-fore-color); + background: var(--tooltip-back-color); + border-radius: var(--universal-border-radius); + padding: var(--universal-padding); + white-space: nowrap; + transform: translateX(-50%); } + .tooltip:not(.bottom):after { + margin-bottom: calc(2 * var(--universal-margin)); } + .tooltip.bottom:after { + margin-top: calc(2 * var(--universal-margin)); } + +:root { + --modal-overlay-color: rgba(0, 0, 0, 0.45); + --modal-close-color: #e6007e; + --modal-close-hover-color: #ffe97f; } + +[type="checkbox"].modal { + height: 1px; + width: 1px; + margin: -1px; + overflow: hidden; + position: absolute; + clip: rect(0 0 0 0); + -webkit-clip-path: inset(100%); + clip-path: inset(100%); } + [type="checkbox"].modal + div { + position: fixed; + top: 0; + left: 0; + display: none; + width: 100vw; + height: 100vh; + background: var(--modal-overlay-color); } + [type="checkbox"].modal + div .card { + margin: 0 auto; + max-height: 50vh; + overflow: auto; } + [type="checkbox"].modal + div .card .modal-close { + position: absolute; + top: 0; + right: 0; + width: 1.75rem; + height: 1.75rem; + border-radius: var(--universal-border-radius); + padding: var(--universal-padding); + margin: 0; + cursor: pointer; + transition: background 0.3s; } + [type="checkbox"].modal + div .card .modal-close:before { + display: block; + content: '\00D7'; + color: var(--modal-close-color); + position: relative; + font-family: sans-serif; + font-size: 1.75rem; + line-height: 1; + text-align: center; } + [type="checkbox"].modal + div .card .modal-close:hover, [type="checkbox"].modal + div .card .modal-close:focus { + background: var(--modal-close-hover-color); } + [type="checkbox"].modal:checked + div { + display: flex; + flex: 0 1 auto; + z-index: 1200; } + [type="checkbox"].modal:checked + div .card .modal-close { + z-index: 1211; } + +:root { + --collapse-label-back-color: #03234b; + --collapse-label-fore-color: #ffffff; + --collapse-label-hover-back-color: #3cb4e6; + --collapse-selected-label-back-color: #3cb4e6; + --collapse-border-color: var(--collapse-label-back-color); + --collapse-selected-border-color: #ceecf8; + --collapse-content-back-color: #ffffff; + --collapse-selected-label-border-color: #3cb4e6; } + +.collapse { + width: calc(100% - 2 * var(--universal-margin)); + opacity: 1; + display: flex; + flex-direction: column; + margin: var(--universal-margin); + border-radius: var(--universal-border-radius); } + .collapse > [type="radio"], .collapse > [type="checkbox"] { + height: 1px; + width: 1px; + margin: -1px; + overflow: hidden; + position: absolute; + clip: rect(0 0 0 0); + -webkit-clip-path: inset(100%); + clip-path: inset(100%); } + .collapse > label { + flex-grow: 1; + display: inline-block; + height: 1.25rem; + cursor: pointer; + transition: background 0.2s; + color: var(--collapse-label-fore-color); + background: var(--collapse-label-back-color); + border: 0.0714285714rem solid var(--collapse-selected-border-color); + padding: calc(1.25 * var(--universal-padding)); } + .collapse > label:hover, .collapse > label:focus { + background: var(--collapse-label-hover-back-color); } + .collapse > label + div { + flex-basis: auto; + height: 1px; + width: 1px; + margin: -1px; + overflow: hidden; + position: absolute; + clip: rect(0 0 0 0); + -webkit-clip-path: inset(100%); + clip-path: inset(100%); + transition: max-height 0.3s; + max-height: 1px; } + .collapse > :checked + label { + background: var(--collapse-selected-label-back-color); + border-color: var(--collapse-selected-label-border-color); } + .collapse > :checked + label + div { + box-sizing: border-box; + position: relative; + width: 100%; + height: auto; + overflow: auto; + margin: 0; + background: var(--collapse-content-back-color); + border: 0.0714285714rem solid var(--collapse-selected-border-color); + border-top: 0; + padding: var(--universal-padding); + clip: auto; + -webkit-clip-path: inset(0%); + clip-path: inset(0%); + max-height: 100%; } + .collapse > label:not(:first-of-type) { + border-top: 0; } + .collapse > label:first-of-type { + border-radius: var(--universal-border-radius) var(--universal-border-radius) 0 0; } + .collapse > label:last-of-type:not(:first-of-type) { + border-radius: 0 0 var(--universal-border-radius) var(--universal-border-radius); } + .collapse > label:last-of-type:first-of-type { + border-radius: var(--universal-border-radius); } + .collapse > :checked:last-of-type:not(:first-of-type) + label { + border-radius: 0; } + .collapse > :checked:last-of-type + label + div { + border-radius: 0 0 var(--universal-border-radius) var(--universal-border-radius); } + +/* + Custom elements for contextual background elements, toasts and tooltips. +*/ +mark.tertiary { + --mark-back-color: #3cb4e6; } + +mark.tag { + padding: calc(var(--universal-padding)/2) var(--universal-padding); + border-radius: 1em; } + +/* + Definitions for progress elements and spinners. +*/ +/* Progress module CSS variable definitions */ +:root { + --progress-back-color: #3cb4e6; + --progress-fore-color: #555; } + +progress { + display: block; + vertical-align: baseline; + -webkit-appearance: none; + -moz-appearance: none; + appearance: none; + height: 0.75rem; + width: calc(100% - 2 * var(--universal-margin)); + margin: var(--universal-margin); + border: 0; + border-radius: calc(2 * var(--universal-border-radius)); + background: var(--progress-back-color); + color: var(--progress-fore-color); } + progress::-webkit-progress-value { + background: var(--progress-fore-color); + border-top-left-radius: calc(2 * var(--universal-border-radius)); + border-bottom-left-radius: calc(2 * var(--universal-border-radius)); } + progress::-webkit-progress-bar { + background: var(--progress-back-color); } + progress::-moz-progress-bar { + background: var(--progress-fore-color); + border-top-left-radius: calc(2 * var(--universal-border-radius)); + border-bottom-left-radius: calc(2 * var(--universal-border-radius)); } + progress[value="1000"]::-webkit-progress-value { + border-radius: calc(2 * var(--universal-border-radius)); } + progress[value="1000"]::-moz-progress-bar { + border-radius: calc(2 * var(--universal-border-radius)); } + progress.inline { + display: inline-block; + vertical-align: middle; + width: 60%; } + +:root { + --spinner-back-color: #ddd; + --spinner-fore-color: #555; } + +@keyframes spinner-donut-anim { + 0% { + transform: rotate(0deg); } + 100% { + transform: rotate(360deg); } } +.spinner { + display: inline-block; + margin: var(--universal-margin); + border: 0.25rem solid var(--spinner-back-color); + border-left: 0.25rem solid var(--spinner-fore-color); + border-radius: 50%; + width: 1.25rem; + height: 1.25rem; + animation: spinner-donut-anim 1.2s linear infinite; } + +/* + Custom elements for progress bars and spinners. +*/ +progress.primary { + --progress-fore-color: #1976d2; } + +progress.secondary { + --progress-fore-color: #d32f2f; } + +progress.tertiary { + --progress-fore-color: #308732; } + +.spinner.primary { + --spinner-fore-color: #1976d2; } + +.spinner.secondary { + --spinner-fore-color: #d32f2f; } + +.spinner.tertiary { + --spinner-fore-color: #308732; } + +/* + Definitions for icons - powered by Feather (https://feathericons.com/). +*/ +span[class^='icon-'] { + display: inline-block; + height: 1em; + width: 1em; + vertical-align: -0.125em; + background-size: contain; + margin: 0 calc(var(--universal-margin) / 4); } + span[class^='icon-'].secondary { + -webkit-filter: invert(25%); + filter: invert(25%); } + span[class^='icon-'].inverse { + -webkit-filter: invert(100%); + filter: invert(100%); } + +span.icon-alert { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='8' x2='12' y2='12'%3E%3C/line%3E%3Cline x1='12' y1='16' x2='12' y2='16'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-bookmark { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M19 21l-7-5-7 5V5a2 2 0 0 1 2-2h10a2 2 0 0 1 2 2z'%3E%3C/path%3E%3C/svg%3E"); } +span.icon-calendar { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='3' y='4' width='18' height='18' rx='2' ry='2'%3E%3C/rect%3E%3Cline x1='16' y1='2' x2='16' y2='6'%3E%3C/line%3E%3Cline x1='8' y1='2' x2='8' y2='6'%3E%3C/line%3E%3Cline x1='3' y1='10' x2='21' y2='10'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-credit { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='1' y='4' width='22' height='16' rx='2' ry='2'%3E%3C/rect%3E%3Cline x1='1' y1='10' x2='23' y2='10'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-edit { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M20 14.66V20a2 2 0 0 1-2 2H4a2 2 0 0 1-2-2V6a2 2 0 0 1 2-2h5.34'%3E%3C/path%3E%3Cpolygon points='18 2 22 6 12 16 8 16 8 12 18 2'%3E%3C/polygon%3E%3C/svg%3E"); } +span.icon-link { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M18 13v6a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2V8a2 2 0 0 1 2-2h6'%3E%3C/path%3E%3Cpolyline points='15 3 21 3 21 9'%3E%3C/polyline%3E%3Cline x1='10' y1='14' x2='21' y2='3'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-help { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M9.09 9a3 3 0 0 1 5.83 1c0 2-3 3-3 3'%3E%3C/path%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='17' x2='12' y2='17'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-home { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M3 9l9-7 9 7v11a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2z'%3E%3C/path%3E%3Cpolyline points='9 22 9 12 15 12 15 22'%3E%3C/polyline%3E%3C/svg%3E"); } +span.icon-info { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='16' x2='12' y2='12'%3E%3C/line%3E%3Cline x1='12' y1='8' x2='12' y2='8'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-lock { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='3' y='11' width='18' height='11' rx='2' ry='2'%3E%3C/rect%3E%3Cpath d='M7 11V7a5 5 0 0 1 10 0v4'%3E%3C/path%3E%3C/svg%3E"); } +span.icon-mail { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M4 4h16c1.1 0 2 .9 2 2v12c0 1.1-.9 2-2 2H4c-1.1 0-2-.9-2-2V6c0-1.1.9-2 2-2z'%3E%3C/path%3E%3Cpolyline points='22,6 12,13 2,6'%3E%3C/polyline%3E%3C/svg%3E"); } +span.icon-location { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M21 10c0 7-9 13-9 13s-9-6-9-13a9 9 0 0 1 18 0z'%3E%3C/path%3E%3Ccircle cx='12' cy='10' r='3'%3E%3C/circle%3E%3C/svg%3E"); } +span.icon-phone { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M22 16.92v3a2 2 0 0 1-2.18 2 19.79 19.79 0 0 1-8.63-3.07 19.5 19.5 0 0 1-6-6 19.79 19.79 0 0 1-3.07-8.67A2 2 0 0 1 4.11 2h3a2 2 0 0 1 2 1.72 12.84 12.84 0 0 0 .7 2.81 2 2 0 0 1-.45 2.11L8.09 9.91a16 16 0 0 0 6 6l1.27-1.27a2 2 0 0 1 2.11-.45 12.84 12.84 0 0 0 2.81.7A2 2 0 0 1 22 16.92z'%3E%3C/path%3E%3C/svg%3E"); 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} +span.icon-share { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='18' cy='5' r='3'%3E%3C/circle%3E%3Ccircle cx='6' cy='12' r='3'%3E%3C/circle%3E%3Ccircle cx='18' cy='19' r='3'%3E%3C/circle%3E%3Cline x1='8.59' y1='13.51' x2='15.42' y2='17.49'%3E%3C/line%3E%3Cline x1='15.41' y1='6.51' x2='8.59' y2='10.49'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-cart { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='9' cy='21' r='1'%3E%3C/circle%3E%3Ccircle cx='20' cy='21' r='1'%3E%3C/circle%3E%3Cpath d='M1 1h4l2.68 13.39a2 2 0 0 0 2 1.61h9.72a2 2 0 0 0 2-1.61L23 6H6'%3E%3C/path%3E%3C/svg%3E"); } +span.icon-upload { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M21 15v4a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2v-4'%3E%3C/path%3E%3Cpolyline points='17 8 12 3 7 8'%3E%3C/polyline%3E%3Cline x1='12' y1='3' x2='12' y2='15'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-user { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M20 21v-2a4 4 0 0 0-4-4H8a4 4 0 0 0-4 4v2'%3E%3C/path%3E%3Ccircle cx='12' cy='7' r='4'%3E%3C/circle%3E%3C/svg%3E"); } + +/* + Definitions for STMicroelectronics icons (https://brandportal.st.com/document/26). +*/ +span.icon-st-update { + background-image: url("Update.svg"); } +span.icon-st-add { + background-image: url("Add button.svg"); } + +/* + Definitions for utilities and helper classes. +*/ +/* Utility module CSS variable definitions */ +:root { + --generic-border-color: rgba(0, 0, 0, 0.3); + --generic-box-shadow: 0 0.2857142857rem 0.2857142857rem 0 rgba(0, 0, 0, 0.125), 0 0.1428571429rem 0.1428571429rem -0.1428571429rem rgba(0, 0, 0, 0.125); } + +.hidden { + display: none !important; } + +.visually-hidden { + position: absolute !important; + width: 1px !important; + height: 1px !important; + margin: -1px !important; + border: 0 !important; + padding: 0 !important; + clip: rect(0 0 0 0) !important; + -webkit-clip-path: inset(100%) !important; + clip-path: inset(100%) !important; + overflow: hidden !important; } + +.bordered { + border: 0.0714285714rem solid var(--generic-border-color) !important; } + +.rounded { + border-radius: var(--universal-border-radius) !important; } + +.circular { + border-radius: 50% !important; } + +.shadowed { + box-shadow: var(--generic-box-shadow) !important; } + +.responsive-margin { + margin: calc(var(--universal-margin) / 4) !important; } + @media screen and (min-width: 500px) { + .responsive-margin { + margin: calc(var(--universal-margin) / 2) !important; } } + @media screen and (min-width: 1280px) { + .responsive-margin { + margin: var(--universal-margin) !important; } } + +.responsive-padding { + padding: calc(var(--universal-padding) / 4) !important; } + @media screen and (min-width: 500px) { + .responsive-padding { + padding: calc(var(--universal-padding) / 2) !important; } } + @media screen and (min-width: 1280px) { + .responsive-padding { + padding: var(--universal-padding) !important; } } + +@media screen and (max-width: 499px) { + .hidden-sm { + display: none !important; } } +@media screen and (min-width: 500px) and (max-width: 1279px) { + .hidden-md { + display: none !important; } } +@media screen and (min-width: 1280px) { + .hidden-lg { + display: none !important; } } +@media screen and (max-width: 499px) { + .visually-hidden-sm { + position: absolute !important; + width: 1px !important; + height: 1px !important; + margin: -1px !important; + border: 0 !important; + padding: 0 !important; + clip: rect(0 0 0 0) !important; + -webkit-clip-path: inset(100%) !important; + clip-path: inset(100%) !important; + overflow: hidden !important; } } +@media screen and (min-width: 500px) and (max-width: 1279px) { + .visually-hidden-md { + position: absolute !important; + width: 1px !important; + height: 1px !important; + margin: -1px !important; + border: 0 !important; + padding: 0 !important; + clip: rect(0 0 0 0) !important; + -webkit-clip-path: inset(100%) !important; + clip-path: inset(100%) !important; + overflow: hidden !important; } } +@media screen and (min-width: 1280px) { + .visually-hidden-lg { + position: absolute !important; + width: 1px !important; + height: 1px !important; + margin: -1px !important; + border: 0 !important; + padding: 0 !important; + clip: rect(0 0 0 0) !important; + -webkit-clip-path: inset(100%) !important; + clip-path: inset(100%) !important; + overflow: hidden !important; } } + +/*# sourceMappingURL=mini-custom.css.map */ + +img[alt="ST logo"] { display: block; margin: auto; width: 75%; max-width: 250px; min-width: 71px; } +img[alt="Cube logo"] { float: right; width: 30%; max-width: 10rem; min-width: 8rem; padding-right: 1rem;} + +.figure { + display: block; + margin-left: auto; + margin-right: auto; + text-align: center; +} \ No newline at end of file diff --git a/Utilities/timer/_htmresc/st_logo.png b/Utilities/timer/_htmresc/st_logo.png new file mode 100644 index 0000000..8b80057 Binary files /dev/null and b/Utilities/timer/_htmresc/st_logo.png differ diff --git a/Utilities/timer/_htmresc/st_logo_2020.png b/Utilities/timer/_htmresc/st_logo_2020.png new file mode 100644 index 0000000..d6cebb5 Binary files /dev/null and b/Utilities/timer/_htmresc/st_logo_2020.png differ diff --git a/Utilities/timer/stm32_timer.c b/Utilities/timer/stm32_timer.c new file mode 100644 index 0000000..3c9ce51 --- /dev/null +++ b/Utilities/timer/stm32_timer.c @@ -0,0 +1,547 @@ +/*! + * \file timer.c + * + * \brief Timer objects and scheduling management implementation + * + * \copyright Revised BSD License, see section \ref LICENSE. + * + * \code + * ______ _ + * / _____) _ | | + * ( (____ _____ ____ _| |_ _____ ____| |__ + * \____ \| ___ | (_ _) ___ |/ ___) _ \ + * _____) ) ____| | | || |_| ____( (___| | | | + * (______/|_____)_|_|_| \__)_____)\____)_| |_| + * (C)2013-2017 Semtech + * + * \endcode + * + * \author Miguel Luis ( Semtech ) + * + * \author Gregory Cristian ( Semtech ) + */ + +/****************************************************************************** + * @file stm32_timer.c + * @author MCD Application Team + * @brief Time server utility + ****************************************************************************** + * @attention + * + *

    © Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

    + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32_timer.h" + +/** @addtogroup TIMER_SERVER + * @{ + */ + +/* Private macro -----------------------------------------------------------*/ +/** + * @defgroup TIMER_SERVER_private_macro TIMER_SERVER private macros + * @{ + */ +/** + * @brief macro definition to initialize a critical section. + * + */ +#ifndef UTIL_TIMER_INIT_CRITICAL_SECTION + #define UTIL_TIMER_INIT_CRITICAL_SECTION( ) +#endif + +/** + * @brief macro definition to enter a critical section. + * + */ +#ifndef UTIL_TIMER_ENTER_CRITICAL_SECTION + #define UTIL_TIMER_ENTER_CRITICAL_SECTION( ) UTILS_ENTER_CRITICAL_SECTION( ) +#endif + +/** + * @brief macro definition to exit a critical section. + * + */ +#ifndef UTIL_TIMER_EXIT_CRITICAL_SECTION + #define UTIL_TIMER_EXIT_CRITICAL_SECTION( ) UTILS_EXIT_CRITICAL_SECTION( ) +#endif +/** + * @} + */ + +/* Private variables -----------------------------------------------------------*/ +/** + * @defgroup TIMER_SERVER_private_varaible TIMER_SERVER private variable + * @{ + */ + +/** + * @brief Timers list head pointer + * + */ +static UTIL_TIMER_Object_t *TimerListHead = NULL; + +/** + * @} + */ + +/** + * @defgroup TIMER_SERVER_private_function TIMER_SERVER private function + * @{ + */ + +void TimerInsertNewHeadTimer( UTIL_TIMER_Object_t *TimerObject ); +void TimerInsertTimer( UTIL_TIMER_Object_t *TimerObject ); +void TimerSetTimeout( UTIL_TIMER_Object_t *TimerObject ); +bool TimerExists( UTIL_TIMER_Object_t *TimerObject ); + +/** + * @} + */ + +/* Functions Definition ------------------------------------------------------*/ +/** + * @addtogroup TIMER_SERVER_exported_function + * @{ + */ + +UTIL_TIMER_Status_t UTIL_TIMER_Init(void) +{ + UTIL_TIMER_INIT_CRITICAL_SECTION(); + TimerListHead = NULL; + return UTIL_TimerDriver.InitTimer(); +} + +UTIL_TIMER_Status_t UTIL_TIMER_DeInit(void) +{ + return UTIL_TimerDriver.DeInitTimer(); +} + +UTIL_TIMER_Status_t UTIL_TIMER_Create( UTIL_TIMER_Object_t *TimerObject, uint32_t PeriodValue, UTIL_TIMER_Mode_t Mode, void ( *Callback )( void *), void *Argument) +{ + if((TimerObject != NULL) && (Callback != NULL)) + { + TimerObject->Timestamp = 0U; + TimerObject->ReloadValue = UTIL_TimerDriver.ms2Tick(PeriodValue); + TimerObject->IsPending = 0U; + TimerObject->IsRunning = 0U; + TimerObject->IsReloadStopped = 0U; + TimerObject->Callback = Callback; + TimerObject->argument = Argument; + TimerObject->Mode = Mode; + TimerObject->Next = NULL; + return UTIL_TIMER_OK; + } + else + { + return UTIL_TIMER_INVALID_PARAM; + } +} + +UTIL_TIMER_Status_t UTIL_TIMER_Start( UTIL_TIMER_Object_t *TimerObject) +{ + UTIL_TIMER_Status_t ret = UTIL_TIMER_OK; + uint32_t elapsedTime; + uint32_t minValue; + uint32_t ticks; + + if(( TimerObject != NULL ) && ( TimerExists( TimerObject ) == false ) && (TimerObject->IsRunning == 0U)) + { + UTIL_TIMER_ENTER_CRITICAL_SECTION(); + ticks = TimerObject->ReloadValue; + minValue = UTIL_TimerDriver.GetMinimumTimeout( ); + + if( ticks < minValue ) + { + ticks = minValue; + } + + TimerObject->Timestamp = ticks; + TimerObject->IsPending = 0U; + TimerObject->IsRunning = 1U; + TimerObject->IsReloadStopped = 0U; + if( TimerListHead == NULL ) + { + UTIL_TimerDriver.SetTimerContext(); + TimerInsertNewHeadTimer( TimerObject ); /* insert a timeout at now+obj->Timestamp */ + } + else + { + elapsedTime = UTIL_TimerDriver.GetTimerElapsedTime( ); + TimerObject->Timestamp += elapsedTime; + + if( TimerObject->Timestamp < TimerListHead->Timestamp ) + { + TimerInsertNewHeadTimer( TimerObject); + } + else + { + TimerInsertTimer( TimerObject); + } + } + UTIL_TIMER_EXIT_CRITICAL_SECTION(); + } + else + { + ret = UTIL_TIMER_INVALID_PARAM; + } + return ret; +} + +UTIL_TIMER_Status_t UTIL_TIMER_StartWithPeriod( UTIL_TIMER_Object_t *TimerObject, uint32_t PeriodValue) +{ + UTIL_TIMER_Status_t ret = UTIL_TIMER_OK; + + if(NULL == TimerObject) + { + ret = UTIL_TIMER_INVALID_PARAM; + } + else + { + TimerObject->ReloadValue = UTIL_TimerDriver.ms2Tick(PeriodValue); + if(TimerExists(TimerObject)) + { + (void)UTIL_TIMER_Stop(TimerObject); + } + ret = UTIL_TIMER_Start(TimerObject); + } + return ret; +} + +UTIL_TIMER_Status_t UTIL_TIMER_Stop( UTIL_TIMER_Object_t *TimerObject ) +{ + UTIL_TIMER_Status_t ret = UTIL_TIMER_OK; + + if (NULL != TimerObject) + { + UTIL_TIMER_ENTER_CRITICAL_SECTION(); + UTIL_TIMER_Object_t* prev = TimerListHead; + UTIL_TIMER_Object_t* cur = TimerListHead; + TimerObject->IsReloadStopped = 1U; + + /* List is empty or the Obj to stop does not exist */ + if(NULL != TimerListHead) + { + TimerObject->IsRunning = 0U; + + if( TimerListHead == TimerObject ) /* Stop the Head */ + { + TimerListHead->IsPending = 0; + if( TimerListHead->Next != NULL ) + { + TimerListHead = TimerListHead->Next; + TimerSetTimeout( TimerListHead ); + } + else + { + UTIL_TimerDriver.StopTimerEvt( ); + TimerListHead = NULL; + } + } + else /* Stop an object within the list */ + { + while( cur != NULL ) + { + if( cur == TimerObject ) + { + if( cur->Next != NULL ) + { + cur = cur->Next; + prev->Next = cur; + } + else + { + cur = NULL; + prev->Next = cur; + } + break; + } + else + { + prev = cur; + cur = cur->Next; + } + } + } + ret = UTIL_TIMER_OK; + } + UTIL_TIMER_EXIT_CRITICAL_SECTION(); + } + else + { + ret = UTIL_TIMER_INVALID_PARAM; + } + return ret; +} + +UTIL_TIMER_Status_t UTIL_TIMER_SetPeriod(UTIL_TIMER_Object_t *TimerObject, uint32_t NewPeriodValue) +{ + UTIL_TIMER_Status_t ret = UTIL_TIMER_OK; + + if(NULL == TimerObject) + { + ret = UTIL_TIMER_INVALID_PARAM; + } + else + { + TimerObject->ReloadValue = UTIL_TimerDriver.ms2Tick(NewPeriodValue); + if(TimerExists(TimerObject)) + { + (void)UTIL_TIMER_Stop(TimerObject); + ret = UTIL_TIMER_Start(TimerObject); + } + } + return ret; +} + +UTIL_TIMER_Status_t UTIL_TIMER_SetReloadMode(UTIL_TIMER_Object_t *TimerObject, UTIL_TIMER_Mode_t ReloadMode) +{ + UTIL_TIMER_Status_t ret = UTIL_TIMER_OK; + + if(NULL == TimerObject) + { + ret = UTIL_TIMER_INVALID_PARAM; + } + else + { + TimerObject->Mode = ReloadMode; + } + return ret; +} + +UTIL_TIMER_Status_t UTIL_TIMER_GetRemainingTime(UTIL_TIMER_Object_t *TimerObject, uint32_t *ElapsedTime) +{ + UTIL_TIMER_Status_t ret = UTIL_TIMER_OK; + if(TimerExists(TimerObject)) + { + uint32_t time = UTIL_TimerDriver.GetTimerElapsedTime(); + if (TimerObject->Timestamp < time ) + { + *ElapsedTime = 0; + } + else + { + *ElapsedTime = TimerObject->Timestamp - time; + } + } + else + { + ret = UTIL_TIMER_INVALID_PARAM; + } + return ret; +} + +uint32_t UTIL_TIMER_IsRunning( UTIL_TIMER_Object_t *TimerObject ) +{ + if( TimerObject != NULL ) + { + return TimerObject->IsRunning; + } + else + { + return 0; + } +} + +uint32_t UTIL_TIMER_GetFirstRemainingTime(void) +{ + uint32_t NextTimer = 0xFFFFFFFFU; + + if(TimerListHead != NULL) + { + (void)UTIL_TIMER_GetRemainingTime(TimerListHead, &NextTimer); + } + return NextTimer; +} + +void UTIL_TIMER_IRQ_Handler( void ) +{ + UTIL_TIMER_Object_t* cur; + uint32_t old, now, DeltaContext; + + UTIL_TIMER_ENTER_CRITICAL_SECTION(); + + old = UTIL_TimerDriver.GetTimerContext( ); + now = UTIL_TimerDriver.SetTimerContext( ); + + DeltaContext = now - old; /*intentional wrap around */ + + /* update timeStamp based upon new Time Reference*/ + /* because delta context should never exceed 2^32*/ + if ( TimerListHead != NULL ) + { + cur = TimerListHead; + do { + if (cur->Timestamp > DeltaContext) + { + cur->Timestamp -= DeltaContext; + } + else + { + cur->Timestamp = 0; + } + cur = cur->Next; + } while(cur != NULL); + } + + /* Execute expired timer and update the list */ + while ((TimerListHead != NULL) && ((TimerListHead->Timestamp == 0U) || (TimerListHead->Timestamp < UTIL_TimerDriver.GetTimerElapsedTime( )))) + { + cur = TimerListHead; + TimerListHead = TimerListHead->Next; + cur->IsPending = 0; + cur->IsRunning = 0; + cur->Callback(cur->argument); + if(( cur->Mode == UTIL_TIMER_PERIODIC) && (cur->IsReloadStopped == 0U)) + { + (void)UTIL_TIMER_Start(cur); + } + } + + /* start the next TimerListHead if it exists and it is not pending*/ + if(( TimerListHead != NULL ) && (TimerListHead->IsPending == 0U)) + { + TimerSetTimeout( TimerListHead ); + } + UTIL_TIMER_EXIT_CRITICAL_SECTION(); +} + +UTIL_TIMER_Time_t UTIL_TIMER_GetCurrentTime(void) +{ + uint32_t now = UTIL_TimerDriver.GetTimerValue( ); + return UTIL_TimerDriver.Tick2ms(now); +} + +UTIL_TIMER_Time_t UTIL_TIMER_GetElapsedTime(UTIL_TIMER_Time_t past ) +{ + uint32_t nowInTicks = UTIL_TimerDriver.GetTimerValue( ); + uint32_t pastInTicks = UTIL_TimerDriver.ms2Tick( past ); + /* intentional wrap around. Works Ok if tick duation below 1ms */ + return UTIL_TimerDriver.Tick2ms( nowInTicks- pastInTicks ); +} + +UTIL_TIMER_Object_t *UTIL_TIMER_GetTimerList(void) +{ + return TimerListHead; +} + +/** + * @} + */ + +/**************************** Private functions *******************************/ + +/** + * @addtogroup TIMER_SERVER_private_function + * + * @{ + */ +/** + * @brief Check if the Object to be added is not already in the list + * + * @param TimerObject Structure containing the timer object parameters + * @retval 1 (the object is already in the list) or 0 + */ +bool TimerExists( UTIL_TIMER_Object_t *TimerObject ) +{ + UTIL_TIMER_Object_t* cur = TimerListHead; + + while( cur != NULL ) + { + if( cur == TimerObject ) + { + return true; + } + cur = cur->Next; + } + return false; +} + +/** + * @brief Sets a timeout with the duration "timestamp" + * + * @param TimerObject Structure containing the timer object parameters + */ +void TimerSetTimeout( UTIL_TIMER_Object_t *TimerObject ) +{ + uint32_t minTicks= UTIL_TimerDriver.GetMinimumTimeout( ); + TimerObject->IsPending = 1; + + /* In case deadline too soon */ + if(TimerObject->Timestamp < (UTIL_TimerDriver.GetTimerElapsedTime( ) + minTicks) ) + { + TimerObject->Timestamp = UTIL_TimerDriver.GetTimerElapsedTime( ) + minTicks; + } + UTIL_TimerDriver.StartTimerEvt( TimerObject->Timestamp ); +} + +/** + * @brief Adds a timer to the list. + * + * @remark The list is automatically sorted. The list head always contains the + * next timer to expire. + * + * @param TimerObject Structure containing the timer object parameters + */ +void TimerInsertTimer( UTIL_TIMER_Object_t *TimerObject) +{ + UTIL_TIMER_Object_t* cur = TimerListHead; + UTIL_TIMER_Object_t* next = TimerListHead->Next; + + while (cur->Next != NULL ) + { + if( TimerObject->Timestamp > next->Timestamp ) + { + cur = next; + next = next->Next; + } + else + { + cur->Next = TimerObject; + TimerObject->Next = next; + return; + + } + } + cur->Next = TimerObject; + TimerObject->Next = NULL; +} + +/** + * @brief Adds or replace the head timer of the list. + * + * @param TimerObject Structure containing the timer object parameters + * + * @remark The list is automatically sorted. The list head always contains the + * next timer to expire. + */ +void TimerInsertNewHeadTimer( UTIL_TIMER_Object_t *TimerObject ) +{ + UTIL_TIMER_Object_t* cur = TimerListHead; + + if( cur != NULL ) + { + cur->IsPending = 0; + } + + TimerObject->Next = cur; + TimerListHead = TimerObject; + TimerSetTimeout( TimerListHead ); +} + +/** + * @} + */ + +/** + * @} + */ + diff --git a/Utilities/timer/stm32_timer.h b/Utilities/timer/stm32_timer.h new file mode 100644 index 0000000..9256b77 --- /dev/null +++ b/Utilities/timer/stm32_timer.h @@ -0,0 +1,303 @@ +/*! + * \file timer.h + * + * \brief Timer objects and scheduling management implementation + * + * \copyright Revised BSD License, see section \ref LICENSE. + * + * \code + * ______ _ + * / _____) _ | | + * ( (____ _____ ____ _| |_ _____ ____| |__ + * \____ \| ___ | (_ _) ___ |/ ___) _ \ + * _____) ) ____| | | || |_| ____( (___| | | | + * (______/|_____)_|_|_| \__)_____)\____)_| |_| + * (C)2013-2017 Semtech + * + * \endcode + * + * \author Miguel Luis ( Semtech ) + * + * \author Gregory Cristian ( Semtech ) + */ + +/****************************************************************************** + * @file stm32_timer.h + * @author MCD Application Team + * @brief This is the header of the timer server driver + ****************************************************************************** + * @attention + * + *

    © Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

    + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef UTIL_TIME_SERVER_H__ +#define UTIL_TIME_SERVER_H__ + +#ifdef __cplusplus + + extern "C" { +#endif + + /** @defgroup TIMER_SERVER timer server + * @{ + */ + +/* Includes ------------------------------------------------------------------*/ +#include +#include +#include +#include +#include "utilities_conf.h" + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup TIMER_SERVER_exported_TypeDef TIMER_SERVER exported Typedef + * @{ + */ + +/** + * @brief Timer mode + */ +typedef enum { + UTIL_TIMER_ONESHOT = 0, /*! + + + + + + Release Notes for STM32 advanced tracer + + + + + +
    +
    +
    +
    +
    +

    Release Notes for STM32 adv_trace

    +

    Copyright © 2019 STMicroelectronics
    +

    + +
    +
    +
    +

    License

    +

    This software component is licensed by ST under BSD 3-Clause license, the “License”; You may not use this file except in compliance with the License. You may obtain a copy of the License at:

    +

    https://opensource.org/licenses/BSD-3-Clause

    +

    Purpose

    +

    The source code delivered is an utility to help the application debug by providing a trace service.

    +
    +
    +

    Update History

    +
    + +
    +

    Main Changes

    +

    Contents

    + + + + + + + + + + + + +
    Fixed bugs list
    +
    Headline
    Ticket 115234 - [Licensing] Update the way to declare licenses in Cube and X-CUBE components
    +

    known limitations

    +

    Development Toolchains and Compilers

    +
      +
    • IAR Embedded Workbench for ARM (EWARM) toolchain V8.20.2
      • +
    • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.25
      • +
    • System Workbench STM32 (SW4STM32) toolchain V2.7.2
      • +
    +

    Supported Devices and boards

    +

    backward compatibility

    +

    Dependencies

    +
    +
    +
    + +
    +

    Main Changes

    +

    release v1.2.0

    +

    Contents

    + + + + + + + + + + + + +
    Fixed bugs list
    +
    Headline
    Ticket 106337 - CodeSpell issues detected on adv_traceproject
    +

    known limitations

    +

    Development Toolchains and Compilers

    +
      +
    • IAR Embedded Workbench for ARM (EWARM) toolchain V8.20.2
      • +
    • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.25
      • +
    • System Workbench STM32 (SW4STM32) toolchain V2.7.2
      • +
    +

    Supported Devices and boards

    +

    backward compatibility

    +

    Dependencies

    +
    +
    +
    + +
    +

    Main Changes

    +

    release v1.1.0

    +

    Contents

    + + + + + + + + + + + + + + + +
    Fixed bugs list
    +
    Headline
    Ticket 99822 - add API to poll when if buffer is empty ( uint8_t UTIL_ADV_TRACE_IsBufferEmpty(void))
    Code review - Improve overrun feature
    +

    known limitations

    +

    Development Toolchains and Compilers

    +
      +
    • IAR Embedded Workbench for ARM (EWARM) toolchain V8.20.2
      • +
    • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.25
      • +
    • System Workbench STM32 (SW4STM32) toolchain V2.7.2
      • +
    +

    Supported Devices and boards

    +

    backward compatibility

    +

    Dependencies

    +
    +
    +
    + +
    +

    Main Changes

    +

    release v1.0.5

    +

    Contents

    + + + + + + + + + + + + +
    Fixed bugs list
    +
    Headline
    Ticket 94664 - stm32_adv_trace_if_template.c be updated
    +

    known limitations

    +

    Development Toolchains and Compilers

    +
      +
    • IAR Embedded Workbench for ARM (EWARM) toolchain V8.20.2
      • +
    • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.25
      • +
    • System Workbench STM32 (SW4STM32) toolchain V2.7.2
      • +
    +

    Supported Devices and boards

    +

    backward compatibility

    +

    Dependencies

    +
    +
    +
    + +
    +

    Main Changes

    +

    release v1.0.4

    +

    Contents

    + + + + + + + + + + + + +
    Fixed bugs list
    +
    Headline
    Ticket 86948 - CodeSpell : Correct some english words typo
    +

    known limitations

    +

    Development Toolchains and Compilers

    +
      +
    • IAR Embedded Workbench for ARM (EWARM) toolchain V8.20.2
      • +
    • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.25
      • +
    • System Workbench STM32 (SW4STM32) toolchain V2.7.2
      • +
    +

    Supported Devices and boards

    +

    backward compatibility

    +

    Dependencies

    +
    +
    +
    + +
    +

    Main Changes

    +

    release v1.0.3

    +

    Contents

    + + + + + + + + + + + + +
    Fixed bugs list
    +
    Headline
    Ticket 89624 - Utilities Releases Notes Improvements - Link on openorg BSD-3-Clause.
    +

    known limitations

    +

    Development Toolchains and Compilers

    +
      +
    • IAR Embedded Workbench for ARM (EWARM) toolchain V8.20.2
      • +
    • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.25
      • +
    • System Workbench STM32 (SW4STM32) toolchain V2.7.2
      • +
    +

    Supported Devices and boards

    +

    backward compatibility

    +

    Dependencies

    +
    +
    +
    + +
    +

    Main Changes

    +

    release v1.0.2

    +

    Contents

    + + + + + + + + + + + + + + + + + + +
    Fixed bugs list
    +
    Headline
    Ticket 83642 - add possibility to sprintf directly to queue in unchunk mode.
    Ticket 86948 - CodeSpell : Correct some english words typo.
    Ticket 88566 - for security reasons, need to place the TraceBuffer.
    +

    known limitations

    +

    Development Toolchains and Compilers

    +
      +
    • IAR Embedded Workbench for ARM (EWARM) toolchain V8.20.2
      • +
    • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.25
      • +
    • System Workbench STM32 (SW4STM32) toolchain V2.7.2
      • +
    +

    Supported Devices and boards

    +

    backward compatibility

    +

    Dependencies

    +
    +
    +
    + +
    +

    Main Changes

    +

    release v1.0.1

    +

    Contents

    + + + + + + + + + + + + +
    Fixed bugs list
    +
    Headline
    Release note update.
    +

    known limitations

    +

    Development Toolchains and Compilers

    +
      +
    • IAR Embedded Workbench for ARM (EWARM) toolchain V8.20.2
      • +
    • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.25
      • +
    • System Workbench STM32 (SW4STM32) toolchain V2.7.2
      • +
    +

    Supported Devices and boards

    +

    backward compatibility

    +

    Dependencies

    +
    +
    +
    + +
    +

    Main Changes

    +

    first release

    +

    Contents

    + + + + + + + + + + + + +
    Fixed bugs list
    +
    Headline
    first version.
    +

    known limitations

    +

    Development Toolchains and Compilers

    +
      +
    • IAR Embedded Workbench for ARM (EWARM) toolchain V8.20.2
      • +
    • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.25
      • +
    • System Workbench STM32 (SW4STM32) toolchain V2.7.2
      • +
    +

    Supported Devices and boards

    +

    backward compatibility

    +

    Dependencies

    +
    +
    +
    +
    +
    +

    For complete documentation on STM32,visit: [www.st.com/stm32]

    +This release note uses up to date web standards and, for this reason, should not be opened with Internet Explorer but preferably with popular browsers such as Google Chrome, Mozilla Firefox, Opera or Microsoft Edge. +
    + + diff --git a/Utilities/trace/adv_trace/_htmresc/mini-st.css b/Utilities/trace/adv_trace/_htmresc/mini-st.css new file mode 100644 index 0000000..eb41d56 --- /dev/null +++ b/Utilities/trace/adv_trace/_htmresc/mini-st.css @@ -0,0 +1,1700 @@ +@charset "UTF-8"; +/* + Flavor name: Default (mini-default) + Author: Angelos Chalaris (chalarangelo@gmail.com) + Maintainers: Angelos Chalaris + mini.css version: v3.0.0-alpha.3 +*/ +/* + Browsers resets and base typography. +*/ +/* Core module CSS variable definitions */ +:root { + --fore-color: #111; + --secondary-fore-color: #444; + --back-color: #f8f8f8; + --secondary-back-color: #f0f0f0; + --blockquote-color: #f57c00; + --pre-color: #1565c0; + --border-color: #aaa; + --secondary-border-color: #ddd; + --heading-ratio: 1.19; + --universal-margin: 0.5rem; + --universal-padding: 0.125rem; + --universal-border-radius: 0.125rem; + --a-link-color: #0277bd; + --a-visited-color: #01579b; } + +html { + font-size: 14px; } + +a, b, del, em, i, ins, q, span, strong, u { + font-size: 1em; } + +html, * { + font-family: -apple-system, BlinkMacSystemFont, "Segoe UI", Roboto, Ubuntu, "Helvetica Neue", Helvetica, sans-serif; + line-height: 1.4; + -webkit-text-size-adjust: 100%; } + +* { + font-size: 1rem; } + +body { + margin: 0; + color: var(--fore-color); + background: var(--back-color); } + +details { + display: block; } + +summary { + display: list-item; } + +abbr[title] { + border-bottom: none; + text-decoration: underline dotted; } + +input { + overflow: visible; } + +img { + max-width: 100%; + height: auto; } + +h1, h2, h3, h4, h5, h6 { + line-height: 1.2; + margin: calc(1.5 * var(--universal-margin)) var(--universal-margin); + font-weight: 500; } + h1 small, h2 small, h3 small, h4 small, h5 small, h6 small { + color: var(--secondary-fore-color); + display: block; + margin-top: -0.25rem; } + +h1 { + font-size: calc(1rem * var(--heading-ratio) * var(--heading-ratio) * var(--heading-ratio)); } + +h2 { + font-size: calc(1rem * var(--heading-ratio) * var(--heading-ratio); ); + background: var(--mark-back-color); + font-weight: 600; + padding: 0.1em 0.5em 0.2em 0.5em; + color: var(--mark-fore-color); } + +h3 { + font-size: calc(1rem * var(--heading-ratio)); + padding-left: calc(2 * var(--universal-margin)); + /* background: var(--border-color); */ + } + +h4 { + font-size: 1rem;); + padding-left: calc(4 * var(--universal-margin)); } + +h5 { + font-size: 1rem; } + +h6 { + font-size: calc(1rem / var(--heading-ratio)); } + +p { + margin: var(--universal-margin); } + +ol, ul { + margin: var(--universal-margin); + padding-left: calc(6 * var(--universal-margin)); } + +b, strong { + font-weight: 700; } + +hr { + box-sizing: content-box; + border: 0; + line-height: 1.25em; + margin: var(--universal-margin); + height: 0.0625rem; + background: linear-gradient(to right, transparent, var(--border-color) 20%, var(--border-color) 80%, transparent); } + +blockquote { + display: block; + position: relative; + font-style: italic; + color: var(--secondary-fore-color); + margin: var(--universal-margin); + padding: calc(3 * var(--universal-padding)); + border: 0.0625rem solid var(--secondary-border-color); + border-left: 0.375rem solid var(--blockquote-color); + border-radius: 0 var(--universal-border-radius) var(--universal-border-radius) 0; } + blockquote:before { + position: absolute; + top: calc(0rem - var(--universal-padding)); + left: 0; + font-family: sans-serif; + font-size: 3rem; + font-weight: 700; + content: "\201c"; + color: var(--blockquote-color); } + blockquote[cite]:after { + font-style: normal; + font-size: 0.75em; + font-weight: 700; + content: "\a— " attr(cite); + white-space: pre; } + +code, kbd, pre, samp { + font-family: Menlo, Consolas, monospace; + font-size: 0.85em; } + +code { + background: var(--secondary-back-color); + border-radius: var(--universal-border-radius); + padding: calc(var(--universal-padding) / 4) calc(var(--universal-padding) / 2); } + +kbd { + background: var(--fore-color); + color: var(--back-color); + border-radius: var(--universal-border-radius); + padding: calc(var(--universal-padding) / 4) calc(var(--universal-padding) / 2); } + +pre { + overflow: auto; + background: var(--secondary-back-color); + padding: calc(1.5 * var(--universal-padding)); + margin: var(--universal-margin); + border: 0.0625rem solid var(--secondary-border-color); + border-left: 0.25rem solid var(--pre-color); + border-radius: 0 var(--universal-border-radius) var(--universal-border-radius) 0; } + +sup, sub, code, kbd { + line-height: 0; + position: relative; + vertical-align: baseline; } + +small, sup, sub, figcaption { + font-size: 0.75em; } + +sup { + top: -0.5em; } + +sub { + bottom: -0.25em; } + +figure { + margin: var(--universal-margin); } + +figcaption { + color: var(--secondary-fore-color); } + +a { + text-decoration: none; } + a:link { + color: var(--a-link-color); } + a:visited { + color: var(--a-visited-color); } + a:hover, a:focus { + text-decoration: underline; } + +/* + Definitions for the grid system, cards and containers. +*/ +.container { + margin: 0 auto; + padding: 0 calc(1.5 * var(--universal-padding)); } + +.row { + box-sizing: border-box; + display: flex; + flex: 0 1 auto; + flex-flow: row wrap; } + +.col-sm, +[class^='col-sm-'], +[class^='col-sm-offset-'], +.row[class*='cols-sm-'] > * { + box-sizing: border-box; + flex: 0 0 auto; + padding: 0 calc(var(--universal-padding) / 2); } + +.col-sm, +.row.cols-sm > * { + max-width: 100%; + flex-grow: 1; + flex-basis: 0; } + +.col-sm-1, +.row.cols-sm-1 > * { + max-width: 8.3333333333%; + flex-basis: 8.3333333333%; } + +.col-sm-offset-0 { + margin-left: 0; } + +.col-sm-2, +.row.cols-sm-2 > * { + max-width: 16.6666666667%; + flex-basis: 16.6666666667%; } + +.col-sm-offset-1 { + margin-left: 8.3333333333%; } + +.col-sm-3, +.row.cols-sm-3 > * { + max-width: 25%; + flex-basis: 25%; } + +.col-sm-offset-2 { + margin-left: 16.6666666667%; } + +.col-sm-4, +.row.cols-sm-4 > * { + max-width: 33.3333333333%; + flex-basis: 33.3333333333%; } + +.col-sm-offset-3 { + margin-left: 25%; } + +.col-sm-5, +.row.cols-sm-5 > * { + max-width: 41.6666666667%; + flex-basis: 41.6666666667%; } + +.col-sm-offset-4 { + margin-left: 33.3333333333%; } + +.col-sm-6, +.row.cols-sm-6 > * { + max-width: 50%; + flex-basis: 50%; } + +.col-sm-offset-5 { + margin-left: 41.6666666667%; } + +.col-sm-7, +.row.cols-sm-7 > * { + max-width: 58.3333333333%; + flex-basis: 58.3333333333%; } + +.col-sm-offset-6 { + margin-left: 50%; } + +.col-sm-8, +.row.cols-sm-8 > * { + max-width: 66.6666666667%; + flex-basis: 66.6666666667%; } + +.col-sm-offset-7 { + margin-left: 58.3333333333%; } + +.col-sm-9, +.row.cols-sm-9 > * { + max-width: 75%; + flex-basis: 75%; } + +.col-sm-offset-8 { + margin-left: 66.6666666667%; } + +.col-sm-10, +.row.cols-sm-10 > * { + max-width: 83.3333333333%; + flex-basis: 83.3333333333%; } + +.col-sm-offset-9 { + margin-left: 75%; } + +.col-sm-11, +.row.cols-sm-11 > * { + max-width: 91.6666666667%; + flex-basis: 91.6666666667%; } + +.col-sm-offset-10 { + margin-left: 83.3333333333%; } + +.col-sm-12, +.row.cols-sm-12 > * { + max-width: 100%; + flex-basis: 100%; } + +.col-sm-offset-11 { + margin-left: 91.6666666667%; } + +.col-sm-normal { + order: initial; } + +.col-sm-first { + order: -999; } + +.col-sm-last { + order: 999; } + +@media screen and (min-width: 500px) { + .col-md, + [class^='col-md-'], + [class^='col-md-offset-'], + .row[class*='cols-md-'] > * { + box-sizing: border-box; + flex: 0 0 auto; + padding: 0 calc(var(--universal-padding) / 2); } + + .col-md, + .row.cols-md > * { + max-width: 100%; + flex-grow: 1; + flex-basis: 0; } + + .col-md-1, + .row.cols-md-1 > * { + max-width: 8.3333333333%; + flex-basis: 8.3333333333%; } + + .col-md-offset-0 { + margin-left: 0; } + + .col-md-2, + .row.cols-md-2 > * { + max-width: 16.6666666667%; + flex-basis: 16.6666666667%; } + + .col-md-offset-1 { + margin-left: 8.3333333333%; } + + .col-md-3, + .row.cols-md-3 > * { + max-width: 25%; + flex-basis: 25%; } + + .col-md-offset-2 { + margin-left: 16.6666666667%; } + + .col-md-4, + .row.cols-md-4 > * { + max-width: 33.3333333333%; + flex-basis: 33.3333333333%; } + + .col-md-offset-3 { + margin-left: 25%; } + + .col-md-5, + .row.cols-md-5 > * { + max-width: 41.6666666667%; + flex-basis: 41.6666666667%; } + + .col-md-offset-4 { + margin-left: 33.3333333333%; } + + .col-md-6, + .row.cols-md-6 > * { + max-width: 50%; + flex-basis: 50%; } + + .col-md-offset-5 { + margin-left: 41.6666666667%; } + + .col-md-7, + .row.cols-md-7 > * { + max-width: 58.3333333333%; + flex-basis: 58.3333333333%; } + + .col-md-offset-6 { + margin-left: 50%; } + + .col-md-8, + .row.cols-md-8 > * { + max-width: 66.6666666667%; + flex-basis: 66.6666666667%; } + + .col-md-offset-7 { + margin-left: 58.3333333333%; } + + .col-md-9, + .row.cols-md-9 > * { + max-width: 75%; + flex-basis: 75%; } + + .col-md-offset-8 { + margin-left: 66.6666666667%; } + + .col-md-10, + .row.cols-md-10 > * { + max-width: 83.3333333333%; + flex-basis: 83.3333333333%; } + + .col-md-offset-9 { + margin-left: 75%; } + + .col-md-11, + .row.cols-md-11 > * { + max-width: 91.6666666667%; + flex-basis: 91.6666666667%; } + + .col-md-offset-10 { + margin-left: 83.3333333333%; } + + .col-md-12, + .row.cols-md-12 > * { + max-width: 100%; + flex-basis: 100%; } + + .col-md-offset-11 { + margin-left: 91.6666666667%; } + + .col-md-normal { + order: initial; } + + .col-md-first { + order: -999; } + + .col-md-last { + order: 999; } } +@media screen and (min-width: 1280px) { + .col-lg, + [class^='col-lg-'], + [class^='col-lg-offset-'], + .row[class*='cols-lg-'] > * { + box-sizing: border-box; + flex: 0 0 auto; + padding: 0 calc(var(--universal-padding) / 2); } + + .col-lg, + .row.cols-lg > * { + max-width: 100%; + flex-grow: 1; + flex-basis: 0; } + + .col-lg-1, + .row.cols-lg-1 > * { + max-width: 8.3333333333%; + flex-basis: 8.3333333333%; } + + .col-lg-offset-0 { + margin-left: 0; } + + .col-lg-2, + .row.cols-lg-2 > * { + max-width: 16.6666666667%; + flex-basis: 16.6666666667%; } + + .col-lg-offset-1 { + margin-left: 8.3333333333%; } + + .col-lg-3, + .row.cols-lg-3 > * { + max-width: 25%; + flex-basis: 25%; } + + .col-lg-offset-2 { + margin-left: 16.6666666667%; } + + .col-lg-4, + .row.cols-lg-4 > * { + max-width: 33.3333333333%; + flex-basis: 33.3333333333%; } + + .col-lg-offset-3 { + margin-left: 25%; } + + .col-lg-5, + .row.cols-lg-5 > * { + max-width: 41.6666666667%; + flex-basis: 41.6666666667%; } + + .col-lg-offset-4 { + margin-left: 33.3333333333%; } + + .col-lg-6, + .row.cols-lg-6 > * { + max-width: 50%; + flex-basis: 50%; } + + .col-lg-offset-5 { + margin-left: 41.6666666667%; } + + .col-lg-7, + .row.cols-lg-7 > * { + max-width: 58.3333333333%; + flex-basis: 58.3333333333%; } + + .col-lg-offset-6 { + margin-left: 50%; } + + .col-lg-8, + .row.cols-lg-8 > * { + max-width: 66.6666666667%; + flex-basis: 66.6666666667%; } + + .col-lg-offset-7 { + margin-left: 58.3333333333%; } + + .col-lg-9, + .row.cols-lg-9 > * { + max-width: 75%; + flex-basis: 75%; } + + .col-lg-offset-8 { + margin-left: 66.6666666667%; } + + .col-lg-10, + .row.cols-lg-10 > * { + max-width: 83.3333333333%; + flex-basis: 83.3333333333%; } + + .col-lg-offset-9 { + margin-left: 75%; } + + .col-lg-11, + .row.cols-lg-11 > * { + max-width: 91.6666666667%; + flex-basis: 91.6666666667%; } + + .col-lg-offset-10 { + margin-left: 83.3333333333%; } + + .col-lg-12, + .row.cols-lg-12 > * { + max-width: 100%; + flex-basis: 100%; } + + .col-lg-offset-11 { + margin-left: 91.6666666667%; } + + .col-lg-normal { + order: initial; } + + .col-lg-first { + order: -999; } + + .col-lg-last { + order: 999; } } +/* Card component CSS variable definitions */ +:root { + --card-back-color: #f8f8f8; + --card-fore-color: #111; + --card-border-color: #ddd; } + +.card { + display: flex; + flex-direction: column; + justify-content: space-between; + align-self: center; + position: relative; + width: 100%; + background: var(--card-back-color); + color: var(--card-fore-color); + border: 0.0625rem solid var(--card-border-color); + border-radius: var(--universal-border-radius); + margin: var(--universal-margin); + overflow: hidden; } + @media screen and (min-width: 320px) { + .card { + max-width: 320px; } } + .card > .sectione { + background: var(--card-back-color); + color: var(--card-fore-color); + box-sizing: border-box; + margin: 0; + border: 0; + border-radius: 0; + border-bottom: 0.0625rem solid var(--card-border-color); + padding: var(--universal-padding); + width: 100%; } + .card > .sectione.media { + height: 200px; + padding: 0; + -o-object-fit: cover; + object-fit: cover; } + .card > .sectione:last-child { + border-bottom: 0; } + +/* + Custom elements for card elements. +*/ +@media screen and (min-width: 240px) { + .card.small { + max-width: 240px; } } +@media screen and (min-width: 480px) { + .card.large { + max-width: 480px; } } +.card.fluid { + max-width: 100%; + width: auto; } + +.card.warning { +/* --card-back-color: #ffca28; */ + --card-back-color: #e5b8b7; + --card-border-color: #e8b825; } + +.card.error { + --card-back-color: #b71c1c; + --card-fore-color: #f8f8f8; + --card-border-color: #a71a1a; } + +.card > .sectione.dark { + --card-back-color: #e0e0e0; } + +.card > .sectione.double-padded { + padding: calc(1.5 * var(--universal-padding)); } + +/* + Definitions for forms and input elements. +*/ +/* Input_control module CSS variable definitions */ +:root { + --form-back-color: #f0f0f0; + --form-fore-color: #111; + --form-border-color: #ddd; + --input-back-color: #f8f8f8; + --input-fore-color: #111; + --input-border-color: #ddd; + --input-focus-color: #0288d1; + --input-invalid-color: #d32f2f; + --button-back-color: #e2e2e2; + --button-hover-back-color: #dcdcdc; + --button-fore-color: #212121; + --button-border-color: transparent; + --button-hover-border-color: transparent; + --button-group-border-color: rgba(124, 124, 124, 0.54); } + +form { + background: var(--form-back-color); + color: var(--form-fore-color); + border: 0.0625rem solid var(--form-border-color); + border-radius: var(--universal-border-radius); + margin: var(--universal-margin); + padding: calc(2 * var(--universal-padding)) var(--universal-padding); } + +fieldset { + border: 0.0625rem solid var(--form-border-color); + border-radius: var(--universal-border-radius); + margin: calc(var(--universal-margin) / 4); + padding: var(--universal-padding); } + +legend { + box-sizing: border-box; + display: table; + max-width: 100%; + white-space: normal; + font-weight: 700; + padding: calc(var(--universal-padding) / 2); } + +label { + padding: calc(var(--universal-padding) / 2) var(--universal-padding); } + +.input-group { + display: inline-block; } + .input-group.fluid { + display: flex; + align-items: center; + justify-content: center; } + .input-group.fluid > input { + max-width: 100%; + flex-grow: 1; + flex-basis: 0px; } + @media screen and (max-width: 499px) { + .input-group.fluid { + align-items: stretch; + flex-direction: column; } } + .input-group.vertical { + display: flex; + align-items: stretch; + flex-direction: column; } + .input-group.vertical > input { + max-width: 100%; + flex-grow: 1; + flex-basis: 0px; } + +[type="number"]::-webkit-inner-spin-button, [type="number"]::-webkit-outer-spin-button { + height: auto; } + +[type="search"] { + -webkit-appearance: textfield; + outline-offset: -2px; } + +[type="search"]::-webkit-search-cancel-button, +[type="search"]::-webkit-search-decoration { + -webkit-appearance: none; } + +input:not([type]), [type="text"], [type="email"], [type="number"], [type="search"], +[type="password"], [type="url"], [type="tel"], [type="checkbox"], [type="radio"], textarea, select { + box-sizing: border-box; + background: var(--input-back-color); + color: var(--input-fore-color); + border: 0.0625rem solid var(--input-border-color); + border-radius: var(--universal-border-radius); + margin: calc(var(--universal-margin) / 2); + padding: var(--universal-padding) calc(1.5 * var(--universal-padding)); } + +input:not([type="button"]):not([type="submit"]):not([type="reset"]):hover, input:not([type="button"]):not([type="submit"]):not([type="reset"]):focus, textarea:hover, textarea:focus, select:hover, select:focus { + border-color: var(--input-focus-color); + box-shadow: none; } +input:not([type="button"]):not([type="submit"]):not([type="reset"]):invalid, input:not([type="button"]):not([type="submit"]):not([type="reset"]):focus:invalid, textarea:invalid, textarea:focus:invalid, select:invalid, select:focus:invalid { + border-color: var(--input-invalid-color); + box-shadow: none; } +input:not([type="button"]):not([type="submit"]):not([type="reset"])[readonly], textarea[readonly], select[readonly] { + background: var(--secondary-back-color); } + +select { + max-width: 100%; } + +option { + overflow: hidden; + text-overflow: ellipsis; } + +[type="checkbox"], [type="radio"] { + -webkit-appearance: none; + -moz-appearance: none; + appearance: none; + position: relative; + height: calc(1rem + var(--universal-padding) / 2); + width: calc(1rem + var(--universal-padding) / 2); + vertical-align: text-bottom; + padding: 0; + flex-basis: calc(1rem + var(--universal-padding) / 2) !important; + flex-grow: 0 !important; } + [type="checkbox"]:checked:before, [type="radio"]:checked:before { + position: absolute; } + +[type="checkbox"]:checked:before { + content: '\2713'; + font-family: sans-serif; + font-size: calc(1rem + var(--universal-padding) / 2); + top: calc(0rem - var(--universal-padding)); + left: calc(var(--universal-padding) / 4); } + +[type="radio"] { + border-radius: 100%; } + [type="radio"]:checked:before { + border-radius: 100%; + content: ''; + top: calc(0.0625rem + var(--universal-padding) / 2); + left: calc(0.0625rem + var(--universal-padding) / 2); + background: var(--input-fore-color); + width: 0.5rem; + height: 0.5rem; } + +:placeholder-shown { + color: var(--input-fore-color); } + +::-ms-placeholder { + color: var(--input-fore-color); + opacity: 0.54; } + +button::-moz-focus-inner, [type="button"]::-moz-focus-inner, [type="reset"]::-moz-focus-inner, [type="submit"]::-moz-focus-inner { + border-style: none; + padding: 0; } + +button, html [type="button"], [type="reset"], [type="submit"] { + -webkit-appearance: button; } + +button { + overflow: visible; + text-transform: none; } + +button, [type="button"], [type="submit"], [type="reset"], +a.button, label.button, .button, +a[role="button"], label[role="button"], [role="button"] { + display: inline-block; + background: var(--button-back-color); + color: var(--button-fore-color); + border: 0.0625rem solid var(--button-border-color); + border-radius: var(--universal-border-radius); + padding: var(--universal-padding) calc(1.5 * var(--universal-padding)); + margin: var(--universal-margin); + text-decoration: none; + cursor: pointer; + transition: background 0.3s; } + button:hover, button:focus, [type="button"]:hover, [type="button"]:focus, [type="submit"]:hover, [type="submit"]:focus, [type="reset"]:hover, [type="reset"]:focus, + a.button:hover, + a.button:focus, label.button:hover, label.button:focus, .button:hover, .button:focus, + a[role="button"]:hover, + a[role="button"]:focus, label[role="button"]:hover, label[role="button"]:focus, [role="button"]:hover, [role="button"]:focus { + background: var(--button-hover-back-color); + border-color: var(--button-hover-border-color); } + +input:disabled, input[disabled], textarea:disabled, textarea[disabled], select:disabled, select[disabled], button:disabled, button[disabled], .button:disabled, .button[disabled], [role="button"]:disabled, [role="button"][disabled] { + cursor: not-allowed; + opacity: 0.75; } + +.button-group { + display: flex; + border: 0.0625rem solid var(--button-group-border-color); + border-radius: var(--universal-border-radius); + margin: var(--universal-margin); } + .button-group > button, .button-group [type="button"], .button-group > [type="submit"], .button-group > [type="reset"], .button-group > .button, .button-group > [role="button"] { + margin: 0; + max-width: 100%; + flex: 1 1 auto; + text-align: center; + border: 0; + border-radius: 0; + box-shadow: none; } + .button-group > :not(:first-child) { + border-left: 0.0625rem solid var(--button-group-border-color); } + @media screen and (max-width: 499px) { + .button-group { + flex-direction: column; } + .button-group > :not(:first-child) { + border: 0; + border-top: 0.0625rem solid var(--button-group-border-color); } } + +/* + Custom elements for forms and input elements. +*/ +button.primary, [type="button"].primary, [type="submit"].primary, [type="reset"].primary, .button.primary, [role="button"].primary { + --button-back-color: #1976d2; + --button-fore-color: #f8f8f8; } + button.primary:hover, button.primary:focus, [type="button"].primary:hover, [type="button"].primary:focus, [type="submit"].primary:hover, [type="submit"].primary:focus, [type="reset"].primary:hover, [type="reset"].primary:focus, .button.primary:hover, .button.primary:focus, [role="button"].primary:hover, [role="button"].primary:focus { + --button-hover-back-color: #1565c0; } + +button.secondary, [type="button"].secondary, [type="submit"].secondary, [type="reset"].secondary, .button.secondary, [role="button"].secondary { + --button-back-color: #d32f2f; + --button-fore-color: #f8f8f8; } + button.secondary:hover, button.secondary:focus, [type="button"].secondary:hover, [type="button"].secondary:focus, [type="submit"].secondary:hover, [type="submit"].secondary:focus, [type="reset"].secondary:hover, [type="reset"].secondary:focus, .button.secondary:hover, .button.secondary:focus, [role="button"].secondary:hover, [role="button"].secondary:focus { + --button-hover-back-color: #c62828; } + +button.tertiary, [type="button"].tertiary, [type="submit"].tertiary, [type="reset"].tertiary, .button.tertiary, [role="button"].tertiary { + --button-back-color: #308732; + --button-fore-color: #f8f8f8; } + button.tertiary:hover, button.tertiary:focus, [type="button"].tertiary:hover, [type="button"].tertiary:focus, [type="submit"].tertiary:hover, [type="submit"].tertiary:focus, [type="reset"].tertiary:hover, [type="reset"].tertiary:focus, .button.tertiary:hover, .button.tertiary:focus, [role="button"].tertiary:hover, [role="button"].tertiary:focus { + --button-hover-back-color: #277529; } + +button.inverse, [type="button"].inverse, [type="submit"].inverse, [type="reset"].inverse, .button.inverse, [role="button"].inverse { + --button-back-color: #212121; + --button-fore-color: #f8f8f8; } + button.inverse:hover, button.inverse:focus, [type="button"].inverse:hover, [type="button"].inverse:focus, [type="submit"].inverse:hover, [type="submit"].inverse:focus, [type="reset"].inverse:hover, [type="reset"].inverse:focus, .button.inverse:hover, .button.inverse:focus, [role="button"].inverse:hover, [role="button"].inverse:focus { + --button-hover-back-color: #111; } + +button.small, [type="button"].small, [type="submit"].small, [type="reset"].small, .button.small, [role="button"].small { + padding: calc(0.5 * var(--universal-padding)) calc(0.75 * var(--universal-padding)); + margin: var(--universal-margin); } + +button.large, [type="button"].large, [type="submit"].large, [type="reset"].large, .button.large, [role="button"].large { + padding: calc(1.5 * var(--universal-padding)) calc(2 * var(--universal-padding)); + margin: var(--universal-margin); } + +/* + Definitions for navigation elements. +*/ +/* Navigation module CSS variable definitions */ +:root { + --header-back-color: #f8f8f8; + --header-hover-back-color: #f0f0f0; + --header-fore-color: #444; + --header-border-color: #ddd; + --nav-back-color: #f8f8f8; + --nav-hover-back-color: #f0f0f0; + --nav-fore-color: #444; + --nav-border-color: #ddd; + --nav-link-color: #0277bd; + --footer-fore-color: #444; + --footer-back-color: #f8f8f8; + --footer-border-color: #ddd; + --footer-link-color: #0277bd; + --drawer-back-color: #f8f8f8; + --drawer-hover-back-color: #f0f0f0; + --drawer-border-color: #ddd; + --drawer-close-color: #444; } + +header { + height: 3.1875rem; + background: var(--header-back-color); + color: var(--header-fore-color); + border-bottom: 0.0625rem solid var(--header-border-color); + padding: calc(var(--universal-padding) / 4) 0; + white-space: nowrap; + overflow-x: auto; + overflow-y: hidden; } + header.row { + box-sizing: content-box; } + header .logo { + color: var(--header-fore-color); + font-size: 1.75rem; + padding: var(--universal-padding) calc(2 * var(--universal-padding)); + text-decoration: none; } + header button, header [type="button"], header .button, header [role="button"] { + box-sizing: border-box; + position: relative; + top: calc(0rem - var(--universal-padding) / 4); + height: calc(3.1875rem + var(--universal-padding) / 2); + background: var(--header-back-color); + line-height: calc(3.1875rem - var(--universal-padding) * 1.5); + text-align: center; + color: var(--header-fore-color); + border: 0; + border-radius: 0; + margin: 0; + text-transform: uppercase; } + header button:hover, header button:focus, header [type="button"]:hover, header [type="button"]:focus, header .button:hover, header .button:focus, header [role="button"]:hover, header [role="button"]:focus { + background: var(--header-hover-back-color); } + +nav { + background: var(--nav-back-color); + color: var(--nav-fore-color); + border: 0.0625rem solid var(--nav-border-color); + border-radius: var(--universal-border-radius); + margin: var(--universal-margin); } + nav * { + padding: var(--universal-padding) calc(1.5 * var(--universal-padding)); } + nav a, nav a:visited { + display: block; + color: var(--nav-link-color); + border-radius: var(--universal-border-radius); + transition: background 0.3s; } + nav a:hover, nav a:focus, nav a:visited:hover, nav a:visited:focus { + text-decoration: none; + background: var(--nav-hover-back-color); } + nav .sublink-1 { + position: relative; + margin-left: calc(2 * var(--universal-padding)); } + nav .sublink-1:before { + position: absolute; + left: calc(var(--universal-padding) - 1 * var(--universal-padding)); + top: -0.0625rem; + content: ''; + height: 100%; + border: 0.0625rem solid var(--nav-border-color); + border-left: 0; } + nav .sublink-2 { + position: relative; + margin-left: calc(4 * var(--universal-padding)); } + nav .sublink-2:before { + position: absolute; + left: calc(var(--universal-padding) - 3 * var(--universal-padding)); + top: -0.0625rem; + content: ''; + height: 100%; + border: 0.0625rem solid var(--nav-border-color); + border-left: 0; } + +footer { + background: var(--footer-back-color); + color: var(--footer-fore-color); + border-top: 0.0625rem solid var(--footer-border-color); + padding: calc(2 * var(--universal-padding)) var(--universal-padding); + font-size: 0.875rem; } + footer a, footer a:visited { + color: var(--footer-link-color); } + +header.sticky { + position: -webkit-sticky; + position: sticky; + z-index: 1101; + top: 0; } + +footer.sticky { + position: -webkit-sticky; + position: sticky; + z-index: 1101; + bottom: 0; } + +.drawer-toggle:before { + display: inline-block; + position: relative; + vertical-align: bottom; + content: '\00a0\2261\00a0'; + font-family: sans-serif; + font-size: 1.5em; } +@media screen and (min-width: 500px) { + .drawer-toggle:not(.persistent) { + display: none; } } + +[type="checkbox"].drawer { + height: 1px; + width: 1px; + margin: -1px; + overflow: hidden; + position: absolute; + clip: rect(0 0 0 0); + -webkit-clip-path: inset(100%); + clip-path: inset(100%); } + [type="checkbox"].drawer + * { + display: block; + box-sizing: border-box; + position: fixed; + top: 0; + width: 320px; + height: 100vh; + overflow-y: auto; + background: var(--drawer-back-color); + border: 0.0625rem solid var(--drawer-border-color); + border-radius: 0; + margin: 0; + z-index: 1110; + right: -320px; + transition: right 0.3s; } + [type="checkbox"].drawer + * .drawer-close { + position: absolute; + top: var(--universal-margin); + right: var(--universal-margin); + z-index: 1111; + width: 2rem; + height: 2rem; + border-radius: var(--universal-border-radius); + padding: var(--universal-padding); + margin: 0; + cursor: pointer; + transition: background 0.3s; } + [type="checkbox"].drawer + * .drawer-close:before { + display: block; + content: '\00D7'; + color: var(--drawer-close-color); + position: relative; + font-family: sans-serif; + font-size: 2rem; + line-height: 1; + text-align: center; } + [type="checkbox"].drawer + * .drawer-close:hover, [type="checkbox"].drawer + * .drawer-close:focus { + background: var(--drawer-hover-back-color); } + @media screen and (max-width: 320px) { + [type="checkbox"].drawer + * { + width: 100%; } } + [type="checkbox"].drawer:checked + * { + right: 0; } + @media screen and (min-width: 500px) { + [type="checkbox"].drawer:not(.persistent) + * { + position: static; + height: 100%; + z-index: 1100; } + [type="checkbox"].drawer:not(.persistent) + * .drawer-close { + display: none; } } + +/* + Definitions for the responsive table component. +*/ +/* Table module CSS variable definitions. */ +:root { + --table-border-color: #aaa; + --table-border-separator-color: #666; + --table-head-back-color: #e6e6e6; + --table-head-fore-color: #111; + --table-body-back-color: #f8f8f8; + --table-body-fore-color: #111; + --table-body-alt-back-color: #eee; } + +table { + border-collapse: separate; + border-spacing: 0; + : margin: calc(1.5 * var(--universal-margin)) var(--universal-margin); + display: flex; + flex: 0 1 auto; + flex-flow: row wrap; + padding: var(--universal-padding); + padding-top: 0; + margin: calc(1.5 * var(--universal-margin)) var(--universal-margin); } + table caption { + font-size: 1.25 * rem; + margin: calc(2 * var(--universal-margin)) 0; + max-width: 100%; + flex: 0 0 100%; + text-align: left;} + table thead, table tbody { + display: flex; + flex-flow: row wrap; + border: 0.0625rem solid var(--table-border-color); } + table thead { + z-index: 999; + border-radius: var(--universal-border-radius) var(--universal-border-radius) 0 0; + border-bottom: 0.0625rem solid var(--table-border-separator-color); } + table tbody { + border-top: 0; + margin-top: calc(0 - var(--universal-margin)); + border-radius: 0 0 var(--universal-border-radius) var(--universal-border-radius); } + table tr { + display: flex; + padding: 0; } + table th, table td { + padding: calc(0.5 * var(--universal-padding)); + font-size: 0.9rem; } + table th { + text-align: left; + background: var(--table-head-back-color); + color: var(--table-head-fore-color); } + table td { + background: var(--table-body-back-color); + color: var(--table-body-fore-color); + border-top: 0.0625rem solid var(--table-border-color); } + +table:not(.horizontal) { + overflow: auto; + max-height: 850px; } + table:not(.horizontal) thead, table:not(.horizontal) tbody { + max-width: 100%; + flex: 0 0 100%; } + table:not(.horizontal) tr { + flex-flow: row wrap; + flex: 0 0 100%; } + table:not(.horizontal) th, table:not(.horizontal) td { + flex: 1 0 0%; + overflow: hidden; + text-overflow: ellipsis; } + table:not(.horizontal) thead { + position: sticky; + top: 0; } + table:not(.horizontal) tbody tr:first-child td { + border-top: 0; } + +table.horizontal { + border: 0; } + table.horizontal thead, table.horizontal tbody { + border: 0; + flex-flow: row nowrap; } + table.horizontal tbody { + overflow: auto; + justify-content: space-between; + flex: 1 0 0; + margin-left: calc( 4 * var(--universal-margin)); + padding-bottom: calc(var(--universal-padding) / 4); } + table.horizontal tr { + flex-direction: column; + flex: 1 0 auto; } + table.horizontal th, table.horizontal td { + width: 100%; + border: 0; + border-bottom: 0.0625rem solid var(--table-border-color); } + table.horizontal th:not(:first-child), table.horizontal td:not(:first-child) { + border-top: 0; } + table.horizontal th { + text-align: right; + border-left: 0.0625rem solid var(--table-border-color); + border-right: 0.0625rem solid var(--table-border-separator-color); } + table.horizontal thead tr:first-child { + padding-left: 0; } + table.horizontal th:first-child, table.horizontal td:first-child { + border-top: 0.0625rem solid var(--table-border-color); } + table.horizontal tbody tr:last-child td { + border-right: 0.0625rem solid var(--table-border-color); } + table.horizontal tbody tr:last-child td:first-child { + border-top-right-radius: 0.25rem; } + table.horizontal tbody tr:last-child td:last-child { + border-bottom-right-radius: 0.25rem; } + table.horizontal thead tr:first-child th:first-child { + border-top-left-radius: 0.25rem; } + table.horizontal thead tr:first-child th:last-child { + border-bottom-left-radius: 0.25rem; } + +@media screen and (max-width: 499px) { + table, table.horizontal { + border-collapse: collapse; + border: 0; + width: 100%; + display: table; } + table thead, table th, table.horizontal thead, table.horizontal th { + border: 0; + height: 1px; + width: 1px; + margin: -1px; + overflow: hidden; + padding: 0; + position: absolute; + clip: rect(0 0 0 0); + -webkit-clip-path: inset(100%); + clip-path: inset(100%); } + table tbody, table.horizontal tbody { + border: 0; + display: table-row-group; } + table tr, table.horizontal tr { + display: block; + border: 0.0625rem solid var(--table-border-color); + border-radius: var(--universal-border-radius); + background: #fafafa; + padding: var(--universal-padding); + margin: var(--universal-margin); + margin-bottom: calc(2 * var(--universal-margin)); } + table th, table td, table.horizontal th, table.horizontal td { + width: auto; } + table td, table.horizontal td { + display: block; + border: 0; + text-align: right; } + table td:before, table.horizontal td:before { + content: attr(data-label); + float: left; + font-weight: 600; } + table th:first-child, table td:first-child, table.horizontal th:first-child, table.horizontal td:first-child { + border-top: 0; } + table tbody tr:last-child td, table.horizontal tbody tr:last-child td { + border-right: 0; } } +:root { + --table-body-alt-back-color: #eee; } + +table tr:nth-of-type(2n) > td { + background: var(--table-body-alt-back-color); } + +@media screen and (max-width: 500px) { + table tr:nth-of-type(2n) { + background: var(--table-body-alt-back-color); } } +:root { + --table-body-hover-back-color: #90caf9; } + +table.hoverable tr:hover, table.hoverable tr:hover > td, table.hoverable tr:focus, table.hoverable tr:focus > td { + background: var(--table-body-hover-back-color); } + +@media screen and (max-width: 500px) { + table.hoverable tr:hover, table.hoverable tr:hover > td, table.hoverable tr:focus, table.hoverable tr:focus > td { + background: var(--table-body-hover-back-color); } } +/* + Definitions for contextual background elements, toasts and tooltips. +*/ +/* Contextual module CSS variable definitions */ +:root { + --mark-back-color: #0277bd; + --mark-fore-color: #fafafa; } + +mark { + background: var(--mark-back-color); + color: var(--mark-fore-color); + font-size: 0.95em; + line-height: 1em; + border-radius: var(--universal-border-radius); + padding: calc(var(--universal-padding) / 4) calc(var(--universal-padding) / 2); } + mark.inline-block { + display: inline-block; + font-size: 1em; + line-height: 1.5; + padding: calc(var(--universal-padding) / 2) var(--universal-padding); } + +:root { + --toast-back-color: #424242; + --toast-fore-color: #fafafa; } + +.toast { + position: fixed; + bottom: calc(var(--universal-margin) * 3); + left: 50%; + transform: translate(-50%, -50%); + z-index: 1111; + color: var(--toast-fore-color); + background: var(--toast-back-color); + border-radius: calc(var(--universal-border-radius) * 16); + padding: var(--universal-padding) calc(var(--universal-padding) * 3); } + +:root { + --tooltip-back-color: #212121; + --tooltip-fore-color: #fafafa; } + +.tooltip { + position: relative; + display: inline-block; } + .tooltip:before, .tooltip:after { + position: absolute; + opacity: 0; + clip: rect(0 0 0 0); + -webkit-clip-path: inset(100%); + clip-path: inset(100%); + transition: all 0.3s; + z-index: 1010; + left: 50%; } + .tooltip:not(.bottom):before, .tooltip:not(.bottom):after { + bottom: 75%; } + .tooltip.bottom:before, .tooltip.bottom:after { + top: 75%; } + .tooltip:hover:before, .tooltip:hover:after, .tooltip:focus:before, .tooltip:focus:after { + opacity: 1; + clip: auto; + -webkit-clip-path: inset(0%); + clip-path: inset(0%); } + .tooltip:before { + content: ''; + background: transparent; + border: var(--universal-margin) solid transparent; + left: calc(50% - var(--universal-margin)); } + .tooltip:not(.bottom):before { + border-top-color: #212121; } + .tooltip.bottom:before { + border-bottom-color: #212121; } + .tooltip:after { + content: attr(aria-label); + color: var(--tooltip-fore-color); + background: var(--tooltip-back-color); + border-radius: var(--universal-border-radius); + padding: var(--universal-padding); + white-space: nowrap; + transform: translateX(-50%); } + .tooltip:not(.bottom):after { + margin-bottom: calc(2 * var(--universal-margin)); } + .tooltip.bottom:after { + margin-top: calc(2 * var(--universal-margin)); } + +:root { + --modal-overlay-color: rgba(0, 0, 0, 0.45); + --modal-close-color: #444; + --modal-close-hover-color: #f0f0f0; } + +[type="checkbox"].modal { + height: 1px; + width: 1px; + margin: -1px; + overflow: hidden; + position: absolute; + clip: rect(0 0 0 0); + -webkit-clip-path: inset(100%); + clip-path: inset(100%); } + [type="checkbox"].modal + div { + position: fixed; + top: 0; + left: 0; + display: none; + width: 100vw; + height: 100vh; + background: var(--modal-overlay-color); } + [type="checkbox"].modal + div .card { + margin: 0 auto; + max-height: 50vh; + overflow: auto; } + [type="checkbox"].modal + div .card .modal-close { + position: absolute; + top: 0; + right: 0; + width: 1.75rem; + height: 1.75rem; + border-radius: var(--universal-border-radius); + padding: var(--universal-padding); + margin: 0; + cursor: pointer; + transition: background 0.3s; } + [type="checkbox"].modal + div .card .modal-close:before { + display: block; + content: '\00D7'; + color: var(--modal-close-color); + position: relative; + font-family: sans-serif; + font-size: 1.75rem; + line-height: 1; + text-align: center; } + [type="checkbox"].modal + div .card .modal-close:hover, [type="checkbox"].modal + div .card .modal-close:focus { + background: var(--modal-close-hover-color); } + [type="checkbox"].modal:checked + div { + display: flex; + flex: 0 1 auto; + z-index: 1200; } + [type="checkbox"].modal:checked + div .card .modal-close { + z-index: 1211; } + +:root { + --collapse-label-back-color: #e8e8e8; + --collapse-label-fore-color: #212121; + --collapse-label-hover-back-color: #f0f0f0; + --collapse-selected-label-back-color: #ececec; + --collapse-border-color: #ddd; + --collapse-content-back-color: #fafafa; + --collapse-selected-label-border-color: #0277bd; } + +.collapse { + width: calc(100% - 2 * var(--universal-margin)); + opacity: 1; + display: flex; + flex-direction: column; + margin: var(--universal-margin); + border-radius: var(--universal-border-radius); } + .collapse > [type="radio"], .collapse > [type="checkbox"] { + height: 1px; + width: 1px; + margin: -1px; + overflow: hidden; + position: absolute; + clip: rect(0 0 0 0); + -webkit-clip-path: inset(100%); + clip-path: inset(100%); } + .collapse > label { + flex-grow: 1; + display: inline-block; + height: 1.5rem; + cursor: pointer; + transition: background 0.3s; + color: var(--collapse-label-fore-color); + background: var(--collapse-label-back-color); + border: 0.0625rem solid var(--collapse-border-color); + padding: calc(1.5 * var(--universal-padding)); } + .collapse > label:hover, .collapse > label:focus { + background: var(--collapse-label-hover-back-color); } + .collapse > label + div { + flex-basis: auto; + height: 1px; + width: 1px; + margin: -1px; + overflow: hidden; + position: absolute; + clip: rect(0 0 0 0); + -webkit-clip-path: inset(100%); + clip-path: inset(100%); + transition: max-height 0.3s; + max-height: 1px; } + .collapse > :checked + label { + background: var(--collapse-selected-label-back-color); + border-bottom-color: var(--collapse-selected-label-border-color); } + .collapse > :checked + label + div { + box-sizing: border-box; + position: relative; + width: 100%; + height: auto; + overflow: auto; + margin: 0; + background: var(--collapse-content-back-color); + border: 0.0625rem solid var(--collapse-border-color); + border-top: 0; + padding: var(--universal-padding); + clip: auto; + -webkit-clip-path: inset(0%); + clip-path: inset(0%); + max-height: 850px; } + .collapse > label:not(:first-of-type) { + border-top: 0; } + .collapse > label:first-of-type { + border-radius: var(--universal-border-radius) var(--universal-border-radius) 0 0; } + .collapse > label:last-of-type:not(:first-of-type) { + border-radius: 0 0 var(--universal-border-radius) var(--universal-border-radius); } + .collapse > label:last-of-type:first-of-type { + border-radius: var(--universal-border-radius); } + .collapse > :checked:last-of-type:not(:first-of-type) + label { + border-radius: 0; } + .collapse > :checked:last-of-type + label + div { + border-radius: 0 0 var(--universal-border-radius) var(--universal-border-radius); } + +/* + Custom elements for contextual background elements, toasts and tooltips. +*/ +mark.secondary { + --mark-back-color: #d32f2f; } + +mark.tertiary { + --mark-back-color: #308732; } + +mark.tag { + padding: calc(var(--universal-padding)/2) var(--universal-padding); + border-radius: 1em; } + +/* + Definitions for progress elements and spinners. +*/ +/* Progress module CSS variable definitions */ +:root { + --progress-back-color: #ddd; + --progress-fore-color: #555; } + +progress { + display: block; + vertical-align: baseline; + -webkit-appearance: none; + -moz-appearance: none; + appearance: none; + height: 0.75rem; + width: calc(100% - 2 * var(--universal-margin)); + margin: var(--universal-margin); + border: 0; + border-radius: calc(2 * var(--universal-border-radius)); + background: var(--progress-back-color); + color: var(--progress-fore-color); } + progress::-webkit-progress-value { + background: var(--progress-fore-color); + border-top-left-radius: calc(2 * var(--universal-border-radius)); + border-bottom-left-radius: calc(2 * var(--universal-border-radius)); } + progress::-webkit-progress-bar { + background: var(--progress-back-color); } + progress::-moz-progress-bar { + background: var(--progress-fore-color); + border-top-left-radius: calc(2 * var(--universal-border-radius)); + border-bottom-left-radius: calc(2 * var(--universal-border-radius)); } + progress[value="1000"]::-webkit-progress-value { + border-radius: calc(2 * var(--universal-border-radius)); } + progress[value="1000"]::-moz-progress-bar { + border-radius: calc(2 * var(--universal-border-radius)); } + progress.inline { + display: inline-block; + vertical-align: middle; + width: 60%; } + +:root { + --spinner-back-color: #ddd; + --spinner-fore-color: #555; } + +@keyframes spinner-donut-anim { + 0% { + transform: rotate(0deg); } + 100% { + transform: rotate(360deg); } } +.spinner { + display: inline-block; + margin: var(--universal-margin); + border: 0.25rem solid var(--spinner-back-color); + border-left: 0.25rem solid var(--spinner-fore-color); + border-radius: 50%; + width: 1.25rem; + height: 1.25rem; + animation: spinner-donut-anim 1.2s linear infinite; } + +/* + Custom elements for progress bars and spinners. +*/ +progress.primary { + --progress-fore-color: #1976d2; } + +progress.secondary { + --progress-fore-color: #d32f2f; } + +progress.tertiary { + --progress-fore-color: #308732; } + +.spinner.primary { + --spinner-fore-color: #1976d2; } + +.spinner.secondary { + --spinner-fore-color: #d32f2f; } + +.spinner.tertiary { + --spinner-fore-color: #308732; } + +/* + Definitions for icons - powered by Feather (https://feathericons.com/). +*/ +span[class^='icon-'] { + display: inline-block; + height: 1em; + width: 1em; + vertical-align: -0.125em; + background-size: contain; + margin: 0 calc(var(--universal-margin) / 4); } + span[class^='icon-'].secondary { + -webkit-filter: invert(25%); + filter: invert(25%); } + span[class^='icon-'].inverse { + -webkit-filter: invert(100%); + filter: invert(100%); } + +span.icon-alert { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='8' x2='12' y2='12'%3E%3C/line%3E%3Cline x1='12' y1='16' x2='12' y2='16'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-bookmark { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M19 21l-7-5-7 5V5a2 2 0 0 1 2-2h10a2 2 0 0 1 2 2z'%3E%3C/path%3E%3C/svg%3E"); } +span.icon-calendar { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='3' y='4' width='18' height='18' rx='2' ry='2'%3E%3C/rect%3E%3Cline x1='16' y1='2' x2='16' y2='6'%3E%3C/line%3E%3Cline x1='8' y1='2' x2='8' y2='6'%3E%3C/line%3E%3Cline x1='3' y1='10' x2='21' y2='10'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-credit { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='1' y='4' width='22' height='16' rx='2' ry='2'%3E%3C/rect%3E%3Cline x1='1' y1='10' x2='23' y2='10'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-edit { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M20 14.66V20a2 2 0 0 1-2 2H4a2 2 0 0 1-2-2V6a2 2 0 0 1 2-2h5.34'%3E%3C/path%3E%3Cpolygon points='18 2 22 6 12 16 8 16 8 12 18 2'%3E%3C/polygon%3E%3C/svg%3E"); } +span.icon-link { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M18 13v6a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2V8a2 2 0 0 1 2-2h6'%3E%3C/path%3E%3Cpolyline points='15 3 21 3 21 9'%3E%3C/polyline%3E%3Cline x1='10' y1='14' x2='21' y2='3'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-help { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M9.09 9a3 3 0 0 1 5.83 1c0 2-3 3-3 3'%3E%3C/path%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='17' x2='12' y2='17'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-home { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M3 9l9-7 9 7v11a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2z'%3E%3C/path%3E%3Cpolyline points='9 22 9 12 15 12 15 22'%3E%3C/polyline%3E%3C/svg%3E"); } +span.icon-info { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='16' x2='12' y2='12'%3E%3C/line%3E%3Cline x1='12' y1='8' x2='12' y2='8'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-lock { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='3' y='11' width='18' height='11' rx='2' ry='2'%3E%3C/rect%3E%3Cpath d='M7 11V7a5 5 0 0 1 10 0v4'%3E%3C/path%3E%3C/svg%3E"); } +span.icon-mail { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M4 4h16c1.1 0 2 .9 2 2v12c0 1.1-.9 2-2 2H4c-1.1 0-2-.9-2-2V6c0-1.1.9-2 2-2z'%3E%3C/path%3E%3Cpolyline points='22,6 12,13 2,6'%3E%3C/polyline%3E%3C/svg%3E"); } +span.icon-location { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M21 10c0 7-9 13-9 13s-9-6-9-13a9 9 0 0 1 18 0z'%3E%3C/path%3E%3Ccircle cx='12' cy='10' r='3'%3E%3C/circle%3E%3C/svg%3E"); } +span.icon-phone { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M22 16.92v3a2 2 0 0 1-2.18 2 19.79 19.79 0 0 1-8.63-3.07 19.5 19.5 0 0 1-6-6 19.79 19.79 0 0 1-3.07-8.67A2 2 0 0 1 4.11 2h3a2 2 0 0 1 2 1.72 12.84 12.84 0 0 0 .7 2.81 2 2 0 0 1-.45 2.11L8.09 9.91a16 16 0 0 0 6 6l1.27-1.27a2 2 0 0 1 2.11-.45 12.84 12.84 0 0 0 2.81.7A2 2 0 0 1 22 16.92z'%3E%3C/path%3E%3C/svg%3E"); } +span.icon-rss { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M4 11a9 9 0 0 1 9 9'%3E%3C/path%3E%3Cpath d='M4 4a16 16 0 0 1 16 16'%3E%3C/path%3E%3Ccircle cx='5' cy='19' r='1'%3E%3C/circle%3E%3C/svg%3E"); } +span.icon-search { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='11' cy='11' r='8'%3E%3C/circle%3E%3Cline x1='21' y1='21' x2='16.65' y2='16.65'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-settings { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='3'%3E%3C/circle%3E%3Cpath d='M19.4 15a1.65 1.65 0 0 0 .33 1.82l.06.06a2 2 0 0 1 0 2.83 2 2 0 0 1-2.83 0l-.06-.06a1.65 1.65 0 0 0-1.82-.33 1.65 1.65 0 0 0-1 1.51V21a2 2 0 0 1-2 2 2 2 0 0 1-2-2v-.09A1.65 1.65 0 0 0 9 19.4a1.65 1.65 0 0 0-1.82.33l-.06.06a2 2 0 0 1-2.83 0 2 2 0 0 1 0-2.83l.06-.06a1.65 1.65 0 0 0 .33-1.82 1.65 1.65 0 0 0-1.51-1H3a2 2 0 0 1-2-2 2 2 0 0 1 2-2h.09A1.65 1.65 0 0 0 4.6 9a1.65 1.65 0 0 0-.33-1.82l-.06-.06a2 2 0 0 1 0-2.83 2 2 0 0 1 2.83 0l.06.06a1.65 1.65 0 0 0 1.82.33H9a1.65 1.65 0 0 0 1-1.51V3a2 2 0 0 1 2-2 2 2 0 0 1 2 2v.09a1.65 1.65 0 0 0 1 1.51 1.65 1.65 0 0 0 1.82-.33l.06-.06a2 2 0 0 1 2.83 0 2 2 0 0 1 0 2.83l-.06.06a1.65 1.65 0 0 0-.33 1.82V9a1.65 1.65 0 0 0 1.51 1H21a2 2 0 0 1 2 2 2 2 0 0 1-2 2h-.09a1.65 1.65 0 0 0-1.51 1z'%3E%3C/path%3E%3C/svg%3E"); } +span.icon-share { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='18' cy='5' r='3'%3E%3C/circle%3E%3Ccircle cx='6' cy='12' r='3'%3E%3C/circle%3E%3Ccircle cx='18' cy='19' r='3'%3E%3C/circle%3E%3Cline x1='8.59' y1='13.51' x2='15.42' y2='17.49'%3E%3C/line%3E%3Cline x1='15.41' y1='6.51' x2='8.59' y2='10.49'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-cart { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='9' cy='21' r='1'%3E%3C/circle%3E%3Ccircle cx='20' cy='21' r='1'%3E%3C/circle%3E%3Cpath d='M1 1h4l2.68 13.39a2 2 0 0 0 2 1.61h9.72a2 2 0 0 0 2-1.61L23 6H6'%3E%3C/path%3E%3C/svg%3E"); } +span.icon-upload { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M21 15v4a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2v-4'%3E%3C/path%3E%3Cpolyline points='17 8 12 3 7 8'%3E%3C/polyline%3E%3Cline x1='12' y1='3' x2='12' y2='15'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-user { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M20 21v-2a4 4 0 0 0-4-4H8a4 4 0 0 0-4 4v2'%3E%3C/path%3E%3Ccircle cx='12' cy='7' r='4'%3E%3C/circle%3E%3C/svg%3E"); } + +/* + Definitions for utilities and helper classes. +*/ +/* Utility module CSS variable definitions */ +:root { + --generic-border-color: rgba(0, 0, 0, 0.3); + --generic-box-shadow: 0 0.25rem 0.25rem 0 rgba(0, 0, 0, 0.125), 0 0.125rem 0.125rem -0.125rem rgba(0, 0, 0, 0.25); } + +.hidden { + display: none !important; } + +.visually-hidden { + position: absolute !important; + width: 1px !important; + height: 1px !important; + margin: -1px !important; + border: 0 !important; + padding: 0 !important; + clip: rect(0 0 0 0) !important; + -webkit-clip-path: inset(100%) !important; + clip-path: inset(100%) !important; + overflow: hidden !important; } + +.bordered { + border: 0.0625rem solid var(--generic-border-color) !important; } + +.rounded { + border-radius: var(--universal-border-radius) !important; } + +.circular { + border-radius: 50% !important; } + +.shadowed { + box-shadow: var(--generic-box-shadow) !important; } + +.responsive-margin { + margin: calc(var(--universal-margin) / 4) !important; } + @media screen and (min-width: 500px) { + .responsive-margin { + margin: calc(var(--universal-margin) / 2) !important; } } + @media screen and (min-width: 1280px) { + .responsive-margin { + margin: var(--universal-margin) !important; } } + +.responsive-padding { + padding: calc(var(--universal-padding) / 4) !important; } + @media screen and (min-width: 500px) { + .responsive-padding { + padding: calc(var(--universal-padding) / 2) !important; } } + @media screen and (min-width: 1280px) { + .responsive-padding { + padding: var(--universal-padding) !important; } } + +@media screen and (max-width: 499px) { + .hidden-sm { + display: none !important; } } +@media screen and (min-width: 500px) and (max-width: 1279px) { + .hidden-md { + display: none !important; } } +@media screen and (min-width: 1280px) { + .hidden-lg { + display: none !important; } } +@media screen and (max-width: 499px) { + .visually-hidden-sm { + position: absolute !important; + width: 1px !important; + height: 1px !important; + margin: -1px !important; + border: 0 !important; + padding: 0 !important; + clip: rect(0 0 0 0) !important; + -webkit-clip-path: inset(100%) !important; + clip-path: inset(100%) !important; + overflow: hidden !important; } } +@media screen and (min-width: 500px) and (max-width: 1279px) { + .visually-hidden-md { + position: absolute !important; + width: 1px !important; + height: 1px !important; + margin: -1px !important; + border: 0 !important; + padding: 0 !important; + clip: rect(0 0 0 0) !important; + -webkit-clip-path: inset(100%) !important; + clip-path: inset(100%) !important; + overflow: hidden !important; } } +@media screen and (min-width: 1280px) { + .visually-hidden-lg { + position: absolute !important; + width: 1px !important; + height: 1px !important; + margin: -1px !important; + border: 0 !important; + padding: 0 !important; + clip: rect(0 0 0 0) !important; + -webkit-clip-path: inset(100%) !important; + clip-path: inset(100%) !important; + overflow: hidden !important; } } + +/*# sourceMappingURL=mini-default.css.map */ diff --git a/Utilities/trace/adv_trace/_htmresc/st_logo.png b/Utilities/trace/adv_trace/_htmresc/st_logo.png new file mode 100644 index 0000000..8b80057 Binary files /dev/null and b/Utilities/trace/adv_trace/_htmresc/st_logo.png differ diff --git a/Utilities/trace/adv_trace/stm32_adv_trace.c b/Utilities/trace/adv_trace/stm32_adv_trace.c new file mode 100644 index 0000000..d7590d8 --- /dev/null +++ b/Utilities/trace/adv_trace/stm32_adv_trace.c @@ -0,0 +1,828 @@ +/** + ****************************************************************************** + * @file stm32_adv_trace.c + * @author MCD Application Team + * @brief This file contains the advanced trace utility functions. + ****************************************************************************** + * @attention + * + *

    © Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

    + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32_adv_trace.h" +#include "stdarg.h" +#include "stdio.h" + +/** @addtogroup ADV_TRACE + * @{ + */ + +/* Private defines -----------------------------------------------------------*/ + +/** @defgroup ADV_TRACE_Private_defines ADV_TRACE Privates defines + * @{ + */ + +/** + * @brief memory address of the trace buffer location. + * This define can be used, to change the buffer location. + * + */ +#if !defined(UTIL_ADV_TRACE_MEMLOCATION) +#define UTIL_ADV_TRACE_MEMLOCATION +#endif + +#if defined(UTIL_ADV_TRACE_OVERRUN) +/** + * @brief List the overrun status. + * list of the overrun status used to handle the overrun trace evacuation. + * + * @note only valid if UTIL_ADV_TRACE_OVERRUN has been enabled inside utilities conf + */ +typedef enum { + TRACE_OVERRUN_NONE = 0, /*!= VerboseLevel)) + { + return UTIL_ADV_TRACE_GIVEUP; + } + + if((Region & ADV_TRACE_Ctx.RegionMask) != Region) + { + return UTIL_ADV_TRACE_REGIONMASKED; + } + +#if defined(UTIL_ADV_TRACE_UNCHUNK_MODE) + if((ADV_TRACE_Ctx.timestamp_func != NULL) && (TimeStampState != 0u)) + { + ADV_TRACE_Ctx.timestamp_func(buf,×tamp_size); + } + + va_start( vaArgs, strFormat); + buff_size =(uint16_t)UTIL_ADV_TRACE_VSNPRINTF((char *)sztmp,UTIL_ADV_TRACE_TMP_BUF_SIZE, strFormat, vaArgs); + + TRACE_Lock(); + + /* if allocation is ok, write data into the buffer */ + if (TRACE_AllocateBufer((buff_size+timestamp_size),&writepos) != -1) + { +#if defined(UTIL_ADV_TRACE_OVERRUN) + UTIL_ADV_TRACE_ENTER_CRITICAL_SECTION(); + if(ADV_TRACE_Ctx.OverRunStatus == TRACE_OVERRUN_EXECUTED) + { + /* clear the over run */ + ADV_TRACE_Ctx.OverRunStatus = TRACE_OVERRUN_NONE; + } + UTIL_ADV_TRACE_EXIT_CRITICAL_SECTION(); +#endif + + /* copy the timestamp */ + for (idx = 0u; idx < timestamp_size; idx++) + { + ADV_TRACE_Buffer[writepos] = buf[idx]; + writepos = writepos + 1u; + } + + /* copy the data */ + (void)UTIL_ADV_TRACE_VSNPRINTF((char *)(&ADV_TRACE_Buffer[writepos]), UTIL_ADV_TRACE_TMP_BUF_SIZE, strFormat, vaArgs); + va_end(vaArgs); + + TRACE_UnLock(); + + return TRACE_Send(); + } + + va_end(vaArgs); + TRACE_UnLock(); +#if defined(UTIL_ADV_TRACE_OVERRUN) + UTIL_ADV_TRACE_ENTER_CRITICAL_SECTION(); + if((ADV_TRACE_Ctx.OverRunStatus == TRACE_OVERRUN_NONE ) && (NULL != ADV_TRACE_Ctx.overrun_func)) + { + UTIL_ADV_TRACE_DEBUG("UTIL_ADV_TRACE_Send:TRACE_OVERRUN_INDICATION"); + ADV_TRACE_Ctx.OverRunStatus = TRACE_OVERRUN_INDICATION; + } + UTIL_ADV_TRACE_EXIT_CRITICAL_SECTION(); +#endif + + return UTIL_ADV_TRACE_MEM_FULL; + +#else + if((ADV_TRACE_Ctx.timestamp_func != NULL) && (TimeStampState != 0u)) + { + ADV_TRACE_Ctx.timestamp_func(buf,&buff_size); + } + + va_start(vaArgs, strFormat); + buff_size += (uint16_t) UTIL_ADV_TRACE_VSNPRINTF((char* )(buf + buff_size), UTIL_ADV_TRACE_TMP_BUF_SIZE, strFormat, vaArgs); + va_end(vaArgs); + + return UTIL_ADV_TRACE_Send(buf, buff_size); +#endif +} +#endif + +UTIL_ADV_TRACE_Status_t UTIL_ADV_TRACE_FSend(const char *strFormat, ...) +{ + uint8_t buf[UTIL_ADV_TRACE_TMP_BUF_SIZE]; + va_list vaArgs; + + va_start(vaArgs, strFormat); + uint16_t bufSize = (uint16_t) UTIL_ADV_TRACE_VSNPRINTF((char* )buf, UTIL_ADV_TRACE_TMP_BUF_SIZE, strFormat, vaArgs); + va_end(vaArgs); + + return UTIL_ADV_TRACE_Send(buf, bufSize); +} + +#if defined(UTIL_ADV_TRACE_CONDITIONNAL) +UTIL_ADV_TRACE_Status_t UTIL_ADV_TRACE_COND_ZCSend_Allocation(uint32_t VerboseLevel, uint32_t Region, uint32_t TimeStampState, uint16_t length, uint8_t **pData, uint16_t *FifoSize, uint16_t *WritePos) +{ + UTIL_ADV_TRACE_Status_t ret = UTIL_ADV_TRACE_OK; + uint16_t writepos; + uint8_t timestamp_ptr[UTIL_ADV_TRACE_TMP_MAX_TIMESTMAP_SIZE]; + uint16_t timestamp_size = 0u; + + /* check verbose level */ + if(!(ADV_TRACE_Ctx.CurrentVerboseLevel >= VerboseLevel)) + { + return UTIL_ADV_TRACE_GIVEUP; + } + + if((Region & ADV_TRACE_Ctx.RegionMask) != Region) + { + return UTIL_ADV_TRACE_REGIONMASKED; + } + + if((ADV_TRACE_Ctx.timestamp_func != NULL) && (TimeStampState != 0u)) + { + ADV_TRACE_Ctx.timestamp_func(timestamp_ptr, ×tamp_size); + } + + TRACE_Lock(); + + /* if allocation is ok, write data into the buffer */ + if (TRACE_AllocateBufer(length+timestamp_size, &writepos) != -1) + { + /* fill time stamp information */ + for (uint16_t index = 0u; index < timestamp_size; index++) + { + ADV_TRACE_Buffer[writepos] = timestamp_ptr[index]; + writepos = (uint16_t) ((writepos + 1u) % UTIL_ADV_TRACE_FIFO_SIZE); + } + + /*user fill */ + *pData = ADV_TRACE_Buffer; + *FifoSize = (uint16_t) UTIL_ADV_TRACE_FIFO_SIZE; + *WritePos = writepos; + } + else + { + TRACE_UnLock(); + ret = UTIL_ADV_TRACE_MEM_FULL; + } + return ret; +} + +UTIL_ADV_TRACE_Status_t UTIL_ADV_TRACE_COND_ZCSend_Finalize(void) +{ + return UTIL_ADV_TRACE_ZCSend_Finalize(); +} +#endif + +UTIL_ADV_TRACE_Status_t UTIL_ADV_TRACE_ZCSend_Allocation(uint16_t Length, uint8_t **pData, uint16_t *FifoSize, uint16_t *WritePos) +{ + UTIL_ADV_TRACE_Status_t ret = UTIL_ADV_TRACE_OK; + uint16_t writepos; + + TRACE_Lock(); + + /* if allocation is ok, write data into the buffer */ + if (TRACE_AllocateBufer(Length,&writepos) != -1) + { + /*user fill */ + *pData = ADV_TRACE_Buffer; + *FifoSize = UTIL_ADV_TRACE_FIFO_SIZE; + *WritePos = (uint16_t)writepos; + } + else + { + TRACE_UnLock(); + ret = UTIL_ADV_TRACE_MEM_FULL; + } + + return ret; +} + +UTIL_ADV_TRACE_Status_t UTIL_ADV_TRACE_ZCSend_Finalize(void) +{ + TRACE_UnLock(); + return TRACE_Send(); +} + +#if defined(UTIL_ADV_TRACE_CONDITIONNAL) +UTIL_ADV_TRACE_Status_t UTIL_ADV_TRACE_COND_Send(uint32_t VerboseLevel, uint32_t Region, uint32_t TimeStampState, const uint8_t *pData, uint16_t Length) +{ + UTIL_ADV_TRACE_Status_t ret; + uint16_t writepos; + uint32_t idx; + uint8_t timestamp_ptr[UTIL_ADV_TRACE_TMP_MAX_TIMESTMAP_SIZE]; + uint16_t timestamp_size = 0u; + + /* check verbose level */ + if(!(ADV_TRACE_Ctx.CurrentVerboseLevel >= VerboseLevel)) + { + return UTIL_ADV_TRACE_GIVEUP; + } + + if((Region & ADV_TRACE_Ctx.RegionMask) != Region) + { + return UTIL_ADV_TRACE_REGIONMASKED; + } + + if((ADV_TRACE_Ctx.timestamp_func != NULL) && (TimeStampState != 0u)) + { + ADV_TRACE_Ctx.timestamp_func(timestamp_ptr, ×tamp_size); + } + + TRACE_Lock(); + + /* if allocation is ok, write data into the buffer */ + if (TRACE_AllocateBufer(Length + timestamp_size, &writepos) != -1) + { + /* fill time stamp information */ + for (idx = 0; idx < timestamp_size; idx++) + { + ADV_TRACE_Buffer[writepos] = timestamp_ptr[idx]; + writepos = (uint16_t) ((writepos + 1u) % UTIL_ADV_TRACE_FIFO_SIZE); + } + + for (idx = 0u; idx < Length; idx++) + { + ADV_TRACE_Buffer[writepos] = pData[idx]; + writepos = (uint16_t) ((writepos + 1u) % UTIL_ADV_TRACE_FIFO_SIZE); + } + + TRACE_UnLock(); + ret = TRACE_Send(); + } + else + { + TRACE_UnLock(); + ret = UTIL_ADV_TRACE_MEM_FULL; + } + + return ret; +} +#endif + +UTIL_ADV_TRACE_Status_t UTIL_ADV_TRACE_Send(const uint8_t *pData, uint16_t Length) +{ + UTIL_ADV_TRACE_Status_t ret; + uint16_t writepos; + uint32_t idx; + + TRACE_Lock(); + + /* if allocation is ok, write data into the buffer */ + if (TRACE_AllocateBufer(Length,&writepos) != -1) + { + /* initialize the Ptr for Read/Write */ + for (idx = 0u; idx < Length; idx++) + { + ADV_TRACE_Buffer[writepos] = pData[idx]; + writepos = (uint16_t) ((writepos + 1u) % UTIL_ADV_TRACE_FIFO_SIZE); + } + TRACE_UnLock(); + + ret = TRACE_Send(); + } + else + { + TRACE_UnLock(); + ret = UTIL_ADV_TRACE_MEM_FULL; + } + + return ret; +} + +#if defined(UTIL_ADV_TRACE_OVERRUN) +void UTIL_ADV_TRACE_RegisterOverRunFunction(cb_overrun *cb) +{ + ADV_TRACE_Ctx.overrun_func = *cb; +} +#endif + +#if defined(UTIL_ADV_TRACE_CONDITIONNAL) +void UTIL_ADV_TRACE_RegisterTimeStampFunction(cb_timestamp *cb) +{ + ADV_TRACE_Ctx.timestamp_func = *cb; +} + +void UTIL_ADV_TRACE_SetVerboseLevel(uint8_t Level) +{ + ADV_TRACE_Ctx.CurrentVerboseLevel = Level; +} + +uint8_t UTIL_ADV_TRACE_GetVerboseLevel(void) +{ + return ADV_TRACE_Ctx.CurrentVerboseLevel; +} + +void UTIL_ADV_TRACE_SetRegion(uint32_t Region) +{ + ADV_TRACE_Ctx.RegionMask |= Region; +} + +uint32_t UTIL_ADV_TRACE_GetRegion(void) +{ + return ADV_TRACE_Ctx.RegionMask; +} + +void UTIL_ADV_TRACE_ResetRegion(uint32_t Region) +{ + ADV_TRACE_Ctx.RegionMask &= ~Region; +} +#endif + +__WEAK void UTIL_ADV_TRACE_PreSendHook(void) +{ +} + +__WEAK void UTIL_ADV_TRACE_PostSendHook(void) +{ +} + +/** + * @} + */ + +/** @addtogroup ADV_TRACE_private_function + * @{ + */ + +/** + * @brief send the data of the trace to low layer + * @retval Status based on @ref UTIL_ADV_TRACE_Status_t + */ +static UTIL_ADV_TRACE_Status_t TRACE_Send(void) +{ + UTIL_ADV_TRACE_Status_t ret = UTIL_ADV_TRACE_OK; + uint8_t *ptr = NULL; + + UTIL_ADV_TRACE_ENTER_CRITICAL_SECTION(); + + if(TRACE_IsLocked() == 0u) + { + TRACE_Lock(); + + if(ADV_TRACE_Ctx.TraceRdPtr != ADV_TRACE_Ctx.TraceWrPtr) + { +#ifdef UTIL_ADV_TRACE_UNCHUNK_MODE + if(TRACE_UNCHUNK_DETECTED == ADV_TRACE_Ctx.unchunk_status) + { + ADV_TRACE_Ctx.TraceSentSize = (uint16_t) (ADV_TRACE_Ctx.unchunk_enabled - ADV_TRACE_Ctx.TraceRdPtr); + ADV_TRACE_Ctx.unchunk_status = TRACE_UNCHUNK_TRANSFER; + ADV_TRACE_Ctx.unchunk_enabled = 0; + + UTIL_ADV_TRACE_DEBUG("\nTRACE_TxCpltCallback::unchunk start(%d,%d)\n", ADV_TRACE_Ctx.unchunk_enabled, ADV_TRACE_Ctx.TraceRdPtr); + + if(0u == ADV_TRACE_Ctx.TraceSentSize) + { + ADV_TRACE_Ctx.unchunk_status = TRACE_UNCHUNK_NONE; + ADV_TRACE_Ctx.TraceRdPtr = 0; + } + } + + if(TRACE_UNCHUNK_NONE == ADV_TRACE_Ctx.unchunk_status) + { +#endif + if(ADV_TRACE_Ctx.TraceWrPtr > ADV_TRACE_Ctx.TraceRdPtr) + { + ADV_TRACE_Ctx.TraceSentSize = ADV_TRACE_Ctx.TraceWrPtr - ADV_TRACE_Ctx.TraceRdPtr; + } + else /* TraceRdPtr > TraceWrPtr */ + { + ADV_TRACE_Ctx.TraceSentSize = UTIL_ADV_TRACE_FIFO_SIZE - ADV_TRACE_Ctx.TraceRdPtr; + + } +#ifdef UTIL_ADV_TRACE_UNCHUNK_MODE + } +#endif + ptr = &ADV_TRACE_Buffer[ADV_TRACE_Ctx.TraceRdPtr]; + + UTIL_ADV_TRACE_EXIT_CRITICAL_SECTION(); + UTIL_ADV_TRACE_PreSendHook(); + + UTIL_ADV_TRACE_DEBUG("\n--TRACE_Send(%d-%d)--\n", ADV_TRACE_Ctx.TraceRdPtr, ADV_TRACE_Ctx.TraceSentSize); + ret = UTIL_TraceDriver.Send(ptr, ADV_TRACE_Ctx.TraceSentSize); + } + else + { + TRACE_UnLock(); + UTIL_ADV_TRACE_EXIT_CRITICAL_SECTION(); + } + } + else + { + UTIL_ADV_TRACE_EXIT_CRITICAL_SECTION(); + } + + return ret; +} + +/** + * @brief Tx callback called by the low layer level to inform a transfer complete + * @param Ptr pointer not used only for HAL compatibility + * @retval none + */ +static void TRACE_TxCpltCallback(void *Ptr) +{ + uint8_t *ptr = NULL; + UTIL_ADV_TRACE_ENTER_CRITICAL_SECTION(); + +#if defined(UTIL_ADV_TRACE_OVERRUN) + if(ADV_TRACE_Ctx.OverRunStatus == TRACE_OVERRUN_TRANSFERT) + { + ADV_TRACE_Ctx.OverRunStatus = TRACE_OVERRUN_EXECUTED; + UTIL_ADV_TRACE_DEBUG("\n--TRACE_Send overrun complete--\n"); + ADV_TRACE_Ctx.TraceSentSize = 0u; + } +#endif + +#if defined(UTIL_ADV_TRACE_UNCHUNK_MODE) + if(TRACE_UNCHUNK_TRANSFER == ADV_TRACE_Ctx.unchunk_status) + { + ADV_TRACE_Ctx.unchunk_status = TRACE_UNCHUNK_NONE; + ADV_TRACE_Ctx.TraceRdPtr = 0; + UTIL_ADV_TRACE_DEBUG("\nTRACE_TxCpltCallback::unchunk complete\n"); + } + else + { + ADV_TRACE_Ctx.TraceRdPtr = (ADV_TRACE_Ctx.TraceRdPtr + ADV_TRACE_Ctx.TraceSentSize) % UTIL_ADV_TRACE_FIFO_SIZE; + } +#else + ADV_TRACE_Ctx.TraceRdPtr = (ADV_TRACE_Ctx.TraceRdPtr + ADV_TRACE_Ctx.TraceSentSize) % UTIL_ADV_TRACE_FIFO_SIZE; +#endif + +#if defined(UTIL_ADV_TRACE_OVERRUN) + if(ADV_TRACE_Ctx.OverRunStatus == TRACE_OVERRUN_INDICATION) + { + uint8_t *ptr = NULL; + ADV_TRACE_Ctx.OverRunStatus = TRACE_OVERRUN_TRANSFERT; + UTIL_ADV_TRACE_EXIT_CRITICAL_SECTION(); + ADV_TRACE_Ctx.overrun_func(&ptr, &ADV_TRACE_Ctx.TraceSentSize); + UTIL_ADV_TRACE_DEBUG("\n--Driver_Send overrun(%d)--\n", ADV_TRACE_Ctx.TraceSentSize); + UTIL_TraceDriver.Send(ptr, ADV_TRACE_Ctx.TraceSentSize); + return; + } +#endif + + if((ADV_TRACE_Ctx.TraceRdPtr != ADV_TRACE_Ctx.TraceWrPtr) && (1u == ADV_TRACE_Ctx.TraceLock)) + { +#ifdef UTIL_ADV_TRACE_UNCHUNK_MODE + if(TRACE_UNCHUNK_DETECTED == ADV_TRACE_Ctx.unchunk_status) + { + ADV_TRACE_Ctx.TraceSentSize = ADV_TRACE_Ctx.unchunk_enabled - ADV_TRACE_Ctx.TraceRdPtr; + ADV_TRACE_Ctx.unchunk_status = TRACE_UNCHUNK_TRANSFER; + ADV_TRACE_Ctx.unchunk_enabled = 0; + + UTIL_ADV_TRACE_DEBUG("\nTRACE_TxCpltCallback::unchunk start(%d,%d)\n", ADV_TRACE_Ctx.unchunk_enabled, ADV_TRACE_Ctx.TraceRdPtr); + + if(0u == ADV_TRACE_Ctx.TraceSentSize) + { + /* this case occurs when an ongoing write aligned the Rd position with chunk position */ + /* in that case the unchunk is forgot */ + ADV_TRACE_Ctx.unchunk_status = TRACE_UNCHUNK_NONE; + ADV_TRACE_Ctx.TraceRdPtr = 0; + } + } + + if(TRACE_UNCHUNK_NONE == ADV_TRACE_Ctx.unchunk_status) + { +#endif + if(ADV_TRACE_Ctx.TraceWrPtr > ADV_TRACE_Ctx.TraceRdPtr) + { + ADV_TRACE_Ctx.TraceSentSize = ADV_TRACE_Ctx.TraceWrPtr - ADV_TRACE_Ctx.TraceRdPtr; + } + else /* TraceRdPtr > TraceWrPtr */ + { + ADV_TRACE_Ctx.TraceSentSize = UTIL_ADV_TRACE_FIFO_SIZE - ADV_TRACE_Ctx.TraceRdPtr; + } +#ifdef UTIL_ADV_TRACE_UNCHUNK_MODE + } +#endif + ptr = &ADV_TRACE_Buffer[ADV_TRACE_Ctx.TraceRdPtr]; + UTIL_ADV_TRACE_EXIT_CRITICAL_SECTION(); + UTIL_ADV_TRACE_DEBUG("\n--TRACE_Send(%d-%d)--\n", ADV_TRACE_Ctx.TraceRdPtr, ADV_TRACE_Ctx.TraceSentSize); + UTIL_TraceDriver.Send(ptr, ADV_TRACE_Ctx.TraceSentSize); + } + else + { + UTIL_ADV_TRACE_EXIT_CRITICAL_SECTION(); + UTIL_ADV_TRACE_PostSendHook(); + TRACE_UnLock(); + } +} + +/** + * @brief allocate space inside the buffer to push data + * @param Size to allocate within fifo + * @param Pos position within the fifo + * @retval write position inside the buffer is -1 no space available. + */ +static int16_t TRACE_AllocateBufer(uint16_t Size, uint16_t *Pos) +{ + uint16_t freesize; + int16_t ret = -1; + + UTIL_ADV_TRACE_ENTER_CRITICAL_SECTION(); + + if(ADV_TRACE_Ctx.TraceWrPtr == ADV_TRACE_Ctx.TraceRdPtr) + { +#ifdef UTIL_ADV_TRACE_UNCHUNK_MODE + freesize = (uint16_t)(UTIL_ADV_TRACE_FIFO_SIZE - ADV_TRACE_Ctx.TraceWrPtr); + if((Size >= freesize) && (ADV_TRACE_Ctx.TraceRdPtr > Size)) + { + ADV_TRACE_Ctx.unchunk_status = TRACE_UNCHUNK_DETECTED; + ADV_TRACE_Ctx.unchunk_enabled = ADV_TRACE_Ctx.TraceWrPtr; + freesize = ADV_TRACE_Ctx.TraceRdPtr; + ADV_TRACE_Ctx.TraceWrPtr = 0; + } +#else + /* need to add buffer full management*/ + freesize = (int16_t)UTIL_ADV_TRACE_FIFO_SIZE; +#endif + } + else + { +#ifdef UTIL_ADV_TRACE_UNCHUNK_MODE + if (ADV_TRACE_Ctx.TraceWrPtr > ADV_TRACE_Ctx.TraceRdPtr) + { + freesize = (uint16_t)(UTIL_ADV_TRACE_FIFO_SIZE - ADV_TRACE_Ctx.TraceWrPtr); + if((Size >= freesize) && (ADV_TRACE_Ctx.TraceRdPtr > Size)) + { + ADV_TRACE_Ctx.unchunk_status = TRACE_UNCHUNK_DETECTED; + ADV_TRACE_Ctx.unchunk_enabled = ADV_TRACE_Ctx.TraceWrPtr; + freesize = ADV_TRACE_Ctx.TraceRdPtr; + ADV_TRACE_Ctx.TraceWrPtr = 0; + } + } + else + { + freesize = (uint16_t)(ADV_TRACE_Ctx.TraceRdPtr - ADV_TRACE_Ctx.TraceWrPtr); + } +#else + if (ADV_TRACE_Ctx.TraceWrPtr > ADV_TRACE_Ctx.TraceRdPtr) + { + freesize = UTIL_ADV_TRACE_FIFO_SIZE - ADV_TRACE_Ctx.TraceWrPtr + ADV_TRACE_Ctx.TraceRdPtr; + } + else + { + freesize = ADV_TRACE_Ctx.TraceRdPtr - ADV_TRACE_Ctx.TraceWrPtr; + } +#endif + } + + if(freesize > Size) + { + *Pos = ADV_TRACE_Ctx.TraceWrPtr; + ADV_TRACE_Ctx.TraceWrPtr = (ADV_TRACE_Ctx.TraceWrPtr + Size) % UTIL_ADV_TRACE_FIFO_SIZE; + ret = 0; +#if defined(UTIL_ADV_TRACE_OVERRUN) + if(ADV_TRACE_Ctx.OverRunStatus == TRACE_OVERRUN_EXECUTED) + { + /* clear the over run */ + ADV_TRACE_Ctx.OverRunStatus = TRACE_OVERRUN_NONE; + } +#endif + +#ifdef UTIL_ADV_TRACE_UNCHUNK_MODE + UTIL_ADV_TRACE_DEBUG("\n--TRACE_AllocateBufer(%d-%d-%d::%d-%d)--\n", freesize - Size, Size, ADV_TRACE_Ctx.unchunk_enabled, ADV_TRACE_Ctx.TraceRdPtr, ADV_TRACE_Ctx.TraceWrPtr); +#else + UTIL_ADV_TRACE_DEBUG("\n--TRACE_AllocateBufer(%d-%d::%d-%d)--\n",freesize - Size, Size, ADV_TRACE_Ctx.TraceRdPtr, ADV_TRACE_Ctx.TraceWrPtr); +#endif + } +#if defined(UTIL_ADV_TRACE_OVERRUN) + else + { + if((ADV_TRACE_Ctx.OverRunStatus == TRACE_OVERRUN_NONE) && (NULL != ADV_TRACE_Ctx.overrun_func)) + { + UTIL_ADV_TRACE_DEBUG(":TRACE_OVERRUN_INDICATION"); + ADV_TRACE_Ctx.OverRunStatus = TRACE_OVERRUN_INDICATION; + } + } +#endif + + UTIL_ADV_TRACE_EXIT_CRITICAL_SECTION(); + return ret; +} + +/** + * @brief Lock the trace buffer. + * @retval None. + */ +static void TRACE_Lock(void) +{ + UTIL_ADV_TRACE_ENTER_CRITICAL_SECTION(); + ADV_TRACE_Ctx.TraceLock++; + UTIL_ADV_TRACE_EXIT_CRITICAL_SECTION(); +} + +/** + * @brief UnLock the trace buffer. + * @retval None. + */ +static void TRACE_UnLock(void) +{ + UTIL_ADV_TRACE_ENTER_CRITICAL_SECTION(); + ADV_TRACE_Ctx.TraceLock--; + UTIL_ADV_TRACE_EXIT_CRITICAL_SECTION(); +} + +/** + * @brief UnLock the trace buffer. + * @retval None. + */ +static uint32_t TRACE_IsLocked(void) +{ + return (ADV_TRACE_Ctx.TraceLock == 0u? 0u: 1u); +} + +/** + * @} + */ + +/** + * @} + */ + diff --git a/Utilities/trace/adv_trace/stm32_adv_trace.h b/Utilities/trace/adv_trace/stm32_adv_trace.h new file mode 100644 index 0000000..ee2b6fd --- /dev/null +++ b/Utilities/trace/adv_trace/stm32_adv_trace.h @@ -0,0 +1,273 @@ +/** + ****************************************************************************** + * @file stm32_adv_trace.h + * @author MCD Application Team + * @brief Header for stm32_adv_trace.c +****************************************************************************** + * @attention + * + *

    © Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

    + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** +*/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __ADV_TRACE_H +#define __ADV_TRACE_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stdint.h" +#include "utilities_conf.h" + +/** @defgroup ADV_TRACE advanced tracer + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup ADV_TRACE_exported_TypeDef ADV_TRACE exported Typedef + * @{ + */ + +/** + * @brief prototype of the time stamp function. + */ +typedef void cb_timestamp(uint8_t *pData, uint16_t *Size); + +/** + * @brief prototype of the overrun function. + */ +typedef void cb_overrun(uint8_t **pData, uint16_t *size); +/** + * @brief List the Advanced trace function status. + * list of the returned status value, any negative value is corresponding to an error. + */ +typedef enum{ + UTIL_ADV_TRACE_OK = 0, /*!< Operation terminated successfully.*/ + UTIL_ADV_TRACE_INVALID_PARAM = -1, /*!< Invalid Parameter. */ + UTIL_ADV_TRACE_HW_ERROR = -2, /*!< Hardware Error. */ + UTIL_ADV_TRACE_MEM_FULL = -3, /*!< Memory fifo full. */ + UTIL_ADV_TRACE_UNKNOWN_ERROR = -4, /*!< Unknown Error. */ +#if defined(UTIL_ADV_TRACE_CONDITIONNAL) + UTIL_ADV_TRACE_GIVEUP = -5, /*!< trace give up */ + UTIL_ADV_TRACE_REGIONMASKED = -6 /*!< trace region masked */ +#endif +} UTIL_ADV_TRACE_Status_t; + +/** + * @brief Advanced trace driver definition + */ +typedef struct { + UTIL_ADV_TRACE_Status_t (* Init)(void (*cb)(void *ptr)); /*!< Media initialization. */ + UTIL_ADV_TRACE_Status_t (* DeInit)(void); /*!< Media Un-initialization. */ + UTIL_ADV_TRACE_Status_t (* StartRx)(void (*cb)(uint8_t *pdata, uint16_t size, uint8_t error)); /*!< Media to start RX process. */ + UTIL_ADV_TRACE_Status_t (* Send)(uint8_t *pdata, uint16_t size); /*!< Media to send data. */ +}UTIL_ADV_TRACE_Driver_s; + +/** + * @} + */ + +/* External variables --------------------------------------------------------*/ +/** @defgroup ADV_TRACE_exported_variables ADV_TRACE exported variables + * + * @{ + */ +/** + * @brief This structure is the linked with the IF layer implementation. + */ +extern const UTIL_ADV_TRACE_Driver_s UTIL_TraceDriver; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/* Exported macros -----------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +/** @defgroup ADV_TRACE_exported_function ADV_TRACE exported function + * @{ + */ + +/** + * @brief TraceInit Initializes Logging feature + * @retval Status based on @ref UTIL_ADV_TRACE_Status_t + */ +UTIL_ADV_TRACE_Status_t UTIL_ADV_TRACE_Init(void); + +/** + * @brief TraceDeInit module DeInitializes. + * @retval Status based on @ref UTIL_ADV_TRACE_Status_t + */ +UTIL_ADV_TRACE_Status_t UTIL_ADV_TRACE_DeInit(void); + +/** + * @brief this function check if the buffer is empty. + * @retval 1 if the buffer is empty else 0 + */ +uint8_t UTIL_ADV_TRACE_IsBufferEmpty(void); + +/** + * @brief start the RX process. + * @param UserCallback ptr function used to get the RX data + * @retval Status based on @ref UTIL_ADV_TRACE_Status_t + */ +UTIL_ADV_TRACE_Status_t UTIL_ADV_TRACE_StartRxProcess(void (*UserCallback)(uint8_t *PData, uint16_t Size, uint8_t Error)); + +/** + * @brief TraceSend decode the strFormat and post it to the circular queue for printing + * @param strFormat Trace message and format + * @retval Status based on @ref UTIL_ADV_TRACE_Status_t + */ +UTIL_ADV_TRACE_Status_t UTIL_ADV_TRACE_FSend(const char *strFormat, ...); + +/** + * @brief post data to the circular queue + * @param *pdata pointer to Data + * @param length length of data buffer to be sent + * @retval Status based on @ref UTIL_ADV_TRACE_Status_t + */ +UTIL_ADV_TRACE_Status_t UTIL_ADV_TRACE_Send(const uint8_t *pdata, uint16_t length); + +/** + * @brief ZCSend_Allocation allocate the memory and return information to write the data + * @param Length trase size + * @param pData pointer on the fifo + * @param FifoSize size of the fifo + * @param WritePos write position of the fifo + * @retval Status based on @ref UTIL_ADV_TRACE_Status_t + */ +UTIL_ADV_TRACE_Status_t UTIL_ADV_TRACE_ZCSend_Allocation(uint16_t Length, uint8_t **pData, uint16_t *FifoSize, uint16_t *WritePos); + +/** + * @brief ZCSend finalize the data transfer + * @retval Status based on @ref UTIL_ADV_TRACE_Status_t + */ +UTIL_ADV_TRACE_Status_t UTIL_ADV_TRACE_ZCSend_Finalize(void); +/** + * @brief Trace send started hook + * @retval None + */ + +/** + * @brief Trace send pre hook function + */ +void UTIL_ADV_TRACE_PreSendHook(void); + +/** + * @brief Trace send post hook function + */ +void UTIL_ADV_TRACE_PostSendHook(void); + +#if defined(UTIL_ADV_TRACE_OVERRUN) +/** + * @brief Register a function used to add overrun info inside the trace + * @param cb pointer of function to return overrun information + */ +void UTIL_ADV_TRACE_RegisterOverRunFunction(cb_overrun *cb); +#endif + +#if defined(UTIL_ADV_TRACE_CONDITIONNAL) + +/** + * @brief conditional FSend decode the strFormat and post it to the circular queue for printing + * @param VerboseLevel verbose level of the trace + * @param Region region of the trace + * @param TimeStampState 0 no time stamp insertion, 1 time stamp inserted inside the trace data + * @param strFormat formatted string + * @retval Status based on @ref UTIL_ADV_TRACE_Status_t + */ +UTIL_ADV_TRACE_Status_t UTIL_ADV_TRACE_COND_FSend(uint32_t VerboseLevel, uint32_t Region,uint32_t TimeStampState, const char *strFormat, ...); + +/** + * @brief conditional ZCSend Write user formatted data directly in the FIFO (Z-Cpy) + * @param VerboseLevel verbose level of the trace + * @param Region region of the trace + * @param TimeStampState 0 no time stamp insertion, 1 time stamp inserted inside the trace data + * @param length data length + * @param pData pointer on the fifo + * @param FifoSize size of the fifo + * @param WritePos write position of the fifo + * @retval Status based on @ref UTIL_ADV_TRACE_Status_t + */ +UTIL_ADV_TRACE_Status_t UTIL_ADV_TRACE_COND_ZCSend_Allocation(uint32_t VerboseLevel, uint32_t Region, uint32_t TimeStampState, uint16_t length,uint8_t **pData, uint16_t *FifoSize, uint16_t *WritePos); + +/** + * @brief conditional ZCSend finalize the data transfer + * @retval Status based on @ref UTIL_ADV_TRACE_Status_t + */ +UTIL_ADV_TRACE_Status_t UTIL_ADV_TRACE_COND_ZCSend_Finalize(void); + +/** + * @brief confitionnal Send post data to the circular queue + * @param VerboseLevel verbose level of the trace + * @param Region region of the trace + * @param TimeStampState 0 no time stamp insertion, 1 time stamp inserted inside the trace data + * @param *pdata pointer to Data + * @param length length of data buffer ro be sent + * @retval Status based on @ref UTIL_ADV_TRACE_Status_t + */ +UTIL_ADV_TRACE_Status_t UTIL_ADV_TRACE_COND_Send(uint32_t VerboseLevel, uint32_t Region, uint32_t TimeStampState, const uint8_t *pdata, uint16_t length); + +/** + * @brief Register a function used to add timestamp inside the trace + * @param cb pointer of function to return timestamp information + */ +void UTIL_ADV_TRACE_RegisterTimeStampFunction(cb_timestamp *cb); + +/** + * @brief Set the verbose level + * @param Level (0 to 255) + * @retval None + */ +void UTIL_ADV_TRACE_SetVerboseLevel(uint8_t Level); + +/** + * @brief Get the verbose level + * @retval verbose level + */ +uint8_t UTIL_ADV_TRACE_GetVerboseLevel(void); + +/** + * @brief add to the mask a bit field region. + * @param Region bit field of region to enable + * @retval None + */ +void UTIL_ADV_TRACE_SetRegion(uint32_t Region); + +/** + * @brief add to the mask a bit field region. + * @retval None + */ +uint32_t UTIL_ADV_TRACE_GetRegion(void); + +/** + * @brief remove from the mask a bit field region. + * @param Region Region bit field of region to disable + * @retval None + */ +void UTIL_ADV_TRACE_ResetRegion(uint32_t Region); + +#endif + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /*__ADV_TRACE_H */ diff --git a/readme.txt b/readme.txt new file mode 100644 index 0000000..9c4d4f7 --- /dev/null +++ b/readme.txt @@ -0,0 +1,177 @@ +/** + @page SubGHz_Phy_Per Readme file + + @verbatim + ****************************************************************************** + * @file Applications/SubGHz_Phy/SubGHz_Phy_Per/readme.txt + * @author MCD Application Team + * @brief This application is a simple demo application software between 2 + * LoRa Objects: a STM32WL Nucleo board and whatever other LoRa Radio + * board embedding SubGHz_Phy_Per application too + ****************************************************************************** + * + * Copyright (c) 2020-2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @endverbatim + +@par Description + +This directory contains a set of source files that implements a PER (Packet Error Rate) tests application +with IBM whitening between one Tx device and one Rx device. + +Tx device: + - in /SubGHz_Phy/App/subghz_phy_app.c update #define TEST_MODE to RADIO_TX, compile and load + - packet content is : preamble | sync | payload length | payload | crc + + crc calculated using payload length and payload + + whitening is calculated over payload length | payload | crc + - the transmission starts forever in GFSK 50kbit/s with a payload of 64 bytes + - user button 1 increments "packet length" by 16 bytes + - user button 2 increments "packet length" by 1 bytes + - user button 3 toggles packet "payload mode" from ramp (0x00, 0x01..) to prbs9 + - LED blue on while radio in Tx +Rx device: + - in /SubGHz_Phy/App/subghz_phy_app.c update #define TEST_MODE to RADIO_RX, compile and load + - LED green on when Rx OK, LED red when Rx KO + + ****************************************************************************** + +@par Keywords + +Applications, SubGHz_Phy, PER, SingleCore + +@par Directory contents + + + - SubGHz_Phy_Per/Core/Inc/dma.h This file contains all the function prototypes for + the dma.c file + - SubGHz_Phy_Per/Core/Inc/gpio.h This file contains all the function prototypes for + the gpio.c file + - SubGHz_Phy_Per/Core/Inc/main.h : Header for main.c file. + This file contains the common defines of the application. + - SubGHz_Phy_Per/Core/Inc/platform.h Header for General HW instances configuration + - SubGHz_Phy_Per/Core/Inc/rtc.h This file contains all the function prototypes for + the rtc.c file + - SubGHz_Phy_Per/Core/Inc/stm32wlxx_hal_conf.h HAL configuration file. + - SubGHz_Phy_Per/Core/Inc/stm32wlxx_it.h This file contains the headers of the interrupt handlers. + - SubGHz_Phy_Per/Core/Inc/stm32wlxx_nucleo_conf.h STM32WLxx_Nucleo board configuration file. + - SubGHz_Phy_Per/Core/Inc/stm32_lpm_if.h Header for Low Power Manager interface configuration + - SubGHz_Phy_Per/Core/Inc/subghz.h This file contains all the function prototypes for + the subghz.c file + - SubGHz_Phy_Per/Core/Inc/sys_app.h Function prototypes for sys_app.c file + - SubGHz_Phy_Per/Core/Inc/sys_conf.h Applicative configuration, e.g. : debug, trace, low power, sensors + - SubGHz_Phy_Per/Core/Inc/sys_debug.h Configuration of the debug.c instances + - SubGHz_Phy_Per/Core/Inc/timer_if.h configuration of the timer_if.c instances + - SubGHz_Phy_Per/Core/Inc/usart.h This file contains all the function prototypes for + the usart.c file + - SubGHz_Phy_Per/Core/Inc/usart_if.h Header for USART interface configuration + - SubGHz_Phy_Per/Core/Inc/utilities_conf.h Header for configuration file to utilities + - SubGHz_Phy_Per/Core/Inc/utilities_def.h Definitions for modules requiring utilities + - SubGHz_Phy_Per/SubGHz_Phy/App/app_subghz_phy.h Header of application of the SubGHz_Phy Middleware + - SubGHz_Phy_Per/SubGHz_Phy/App/app_version.h Definition the version of the application + - SubGHz_Phy_Per/SubGHz_Phy/App/subghz_phy_app.h Header of application of the SubGHz_Phy Middleware + - SubGHz_Phy_Per/SubGHz_Phy/Target/mw_log_conf.h Configure (enable/disable) traces + - SubGHz_Phy_Per/SubGHz_Phy/Target/radio_board_if.h Header for Radio interface configuration + - SubGHz_Phy_Per/SubGHz_Phy/Target/radio_conf.h Header of Radio configuration + - SubGHz_Phy_Per/SubGHz_Phy/Target/timer.h Wrapper to timer server + + - SubGHz_Phy_Per/Core/Src/dma.c This file provides code for the configuration + of all the requested memory to memory DMA transfers. + - SubGHz_Phy_Per/Core/Src/gpio.c This file provides code for the configuration + of all used GPIO pins. + - SubGHz_Phy_Per/Core/Src/main.c : Main program body + - SubGHz_Phy_Per/Core/Src/rtc.c This file provides code for the configuration + of the RTC instances. + - SubGHz_Phy_Per/Core/Src/stm32wlxx_hal_msp.c This file provides code for the MSP Initialization + and de-Initialization codes. + - SubGHz_Phy_Per/Core/Src/stm32wlxx_it.c Interrupt Service Routines. + - SubGHz_Phy_Per/Core/Src/stm32_lpm_if.c Low layer function to enter/exit low power modes (stop, sleep) + - SubGHz_Phy_Per/Core/Src/subghz.c This file provides code for the configuration + of the SUBGHZ instances. + - SubGHz_Phy_Per/Core/Src/system_stm32wlxx.c CMSIS Cortex Device Peripheral Access Layer System Source File + - SubGHz_Phy_Per/Core/Src/sys_app.c Initializes HW and SW system entities (not related to the radio) + - SubGHz_Phy_Per/Core/Src/sys_debug.c Configure probes pins RealTime debugging and JTAG/SerialWires for LowPower + - SubGHz_Phy_Per/Core/Src/timer_if.c Configure RTC Alarm, Tick and Calendar manager + - SubGHz_Phy_Per/Core/Src/usart.c This file provides code for the configuration + of the USART instances. + - SubGHz_Phy_Per/Core/Src/usart_if.c Configuration of UART driver interface for hyperterminal communication + - SubGHz_Phy_Per/STM32CubeIDE/Application/User/Core/syscalls.c STM32CubeIDE Minimal System calls file + - SubGHz_Phy_Per/STM32CubeIDE/Application/User/Core/sysmem.c STM32CubeIDE System Memory calls file + - SubGHz_Phy_Per/SubGHz_Phy/App/app_subghz_phy.c Application of the SubGHz_Phy Middleware + - SubGHz_Phy_Per/SubGHz_Phy/App/subghz_phy_app.c Application of the SubGHz_Phy Middleware + - SubGHz_Phy_Per/SubGHz_Phy/Target/radio_board_if.c This file provides an interface layer between MW and Radio Board + + +@par Hardware and Software environment + + - This example runs on the STM32WLxx Nucleo boards. Both NUCLEO-WL55JC1 (HIGH-BAND) and NUCLEO-WL55JC2 (LOW-BAND) are suitable. + + - STM32WLxx Nucleo board Set-up + - Connect the Nucleo board to your PC with a USB cable type A to micro-B + to ST-LINK connector. + - Please ensure that the ST-LINK connector jumpers are fitted. + + - Configure the software via the configuration files: + - sys_conf.h, radio_conf.h, mw_log_conf.h, main.h, etc + + -Set Up: + + -------------------------- V V -------------------------- + | Tx Device | | | | Rx Device | + | | | | | | + ComPort<--| |--| |--| |-->ComPort + | | | | + -------------------------- -------------------------- + +@par How to use it ? +In order to make the program work, you must do the following : + - Open your preferred toolchain + - Rebuild all files and load your image into target memory + - Do the same for second board + - Reset the two boards + - Run the example on two boards + - Open two Terminals, each connected to their respective Tx or Rx Device + - UART Config = 115200, 8b, 1 stopbit, no parity, no flow control + +@par How to debug ? + - make sure the flag DEBUGGER_ENABLED to 1 in sys_conf.h + - simpler to define the flag LOW_POWER_DISABLE to 1 as well + - compile, download and attach + +@par How to use MX to modify some RF middleware and application settings + This example is compatible (with some problems/limitations) with STM32CubeMX + and the RF application and middleware configuration can be modified via GUI. Few warnings and guidelines: + - ioc file is provided in the project directory and can be opened with STM32CubeMX v6.7.0 or higher. + - warning: when regenerating with the provided ioc file, + the IDE projects are regenerated and paths to HAL and MWs files from STM32Cube/Repository location are erroneously added; to avoid that, + user shall uncheck the "Use Default Firmware Location" in the GUI "Project-Manager" panel + and shall replace "Firmware Relative Path" with the root directory of the STM32CubeWL firmware package (e.g. C:\myDir\STM32Cube_FW_WL_V1.3.0\); + problem will be fixed in next STM32CubeMX version. + - .extSettings file allows to add to the generated IDE projects additional files not generated natively by MX (e.g. BSP files). + - when regenerating on existing code and existing linker files: + - STM32CubeMX updates the existing project content and preserves linker files. + - STM32CubeMX does not update the USER CODE sections (lines between /* USER CODE BEGIN Xxx */ and /* USER CODE END Xxx */). + - when regenerating after copying only the ioc file in an empty directory: + - STM32CubeMX generates default project files and default linker files. (Please check original linker file from project directory) + - it is up to the user to to fill the USER CODE sections with his application code. + This SubGHz_Phy project is based on "Advanced template" (MX GUI Application). + USER CODE SECTION are filled to end up with "Switch_Fhss_Fsk_Lora" project. + +@par How to use it with Azure ThreadX RTOS? + This example can be combined with Azure ThreadX RTOS via STM32CubeMX. The video tutorial: + "STM32WL - How to port an existing RF application on Azure ThreadX RTOS" + is available on https://www.youtube.com/playlist?list=PLnMKNibPkDnE2eaR-ZGM3ZJXadyQLtTpX + but not sufficient for the complete porting of this example. + After following the video instructions the user shall open "subghz_phy_app.c" and manually: + - delete "stm32_seq.h" inclusion + - delete the line "UTIL_SEQ_RegTask((1 << CFG_SEQ_Task_SubGHz_Phy_App_Process), UTIL_SEQ_RFU, Per_Process); + - call Per_Process(); function within /* USER CODE App_Main_Thread_Entry_Loop */ + - replace "UTIL_SEQ_SetTask(..) calls" with tx_thread_resume(&App_MainThread); + + *

    © COPYRIGHT STMicroelectronics

    + */ diff --git a/test1/RF_test/.project b/test1/RF_test/.project new file mode 100644 index 0000000..f54c8fa --- /dev/null +++ b/test1/RF_test/.project @@ -0,0 +1,33 @@ + + + My_UART_Test + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + com.st.stm32cube.ide.mcu.MCUProjectNature + org.eclipse.cdt.core.cnature + com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAev2ProjectNature + com.st.stm32cube.ide.mcu.MCUCubeProjectNature + com.st.stm32cube.ide.mcu.MCUAdvancedStructureProjectNature + com.st.stm32cube.ide.mcu.MCUEndUserDisabledMultiCpuProjectNature + com.st.stm32cube.ide.mcu.MCUMultiCpuProjectNature + com.st.stm32cube.ide.mcu.MCURootProjectNature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + diff --git a/test2/SubGHz_Phy_Per/.project b/test2/SubGHz_Phy_Per/.project new file mode 100644 index 0000000..765e097 --- /dev/null +++ b/test2/SubGHz_Phy_Per/.project @@ -0,0 +1,33 @@ + + + SubGHz_Phy_Per + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + com.st.stm32cube.ide.mcu.MCUProjectNature + org.eclipse.cdt.core.cnature + com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAev2ProjectNature + com.st.stm32cube.ide.mcu.MCUCubeProjectNature + com.st.stm32cube.ide.mcu.MCUAdvancedStructureProjectNature + com.st.stm32cube.ide.mcu.MCUEndUserDisabledMultiCpuProjectNature + com.st.stm32cube.ide.mcu.MCUMultiCpuProjectNature + com.st.stm32cube.ide.mcu.MCURootProjectNature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + +